panel: s6e3fc3: send 10 bit global para during sleep outandroid-u-qpr3-beta-2.1_r0.4android-15-beta-1_r0.6android-15-beta-1_r0.4android-15-beta-1_r0.2android-15-beta-1_r0.1android-gs-tangorpro-5.10-android15-dpandroid-gs-tangorpro-5.10-android15-betaandroid-gs-pantah-5.10-android15-dpandroid-gs-pantah-5.10-android15-betaandroid-gs-pantah-5.10-android14-qpr3-betaandroid-gs-felix-5.10-android15-dpandroid-gs-felix-5.10-android15-betaandroid-gs-bluejay-5.10-android15-dpandroid-gs-bluejay-5.10-android15-beta

- send 10 bit global para during sleep out
- after switched to 10 bit,
  replace all existing 8 bit global para with 10 bit
- remove all other 8/10 bit control change command

Bug: 290849324
Test: display works properly
Change-Id: Ic0795b33cd1a836c71ca25555315ad571f7f64a2
Signed-off-by: Safayat Ullah <safayat@google.com>

1 files changed, 2 insertions, 24 deletions

diff --git a/samsung/panel/panel-samsung-s6e3fc3.c b/samsung/panel/panel-samsung-s6e3fc3.c
index d3d52b7..23f64aa 100644
--- a/samsung/panel/panel-samsung-s6e3fc3.c
+++ b/samsung/panel/panel-samsung-s6e3fc3.c
@@ -75,8 +75,6 @@ static const struct exynos_dsi_cmd s6e3fc3_lp_high_cmds[] = {
 
 static const struct exynos_dsi_cmd s6e3fc3_1_pwm_cmds[] = {
 	EXYNOS_DSI_CMD0(test_key_on_f0),
-	EXYNOS_DSI_CMD_SEQ(0xB0, 0x28, 0xF2),
-	EXYNOS_DSI_CMD_SEQ(0xF2, 0xCC),
 	EXYNOS_DSI_CMD_SEQ(0xB0, 0x01, 0xF2, 0x65),
 	EXYNOS_DSI_CMD_SEQ(0x65, 0x00, 0x72),
 	EXYNOS_DSI_CMD_SEQ(0xB0, 0x01, 0xD2, 0x65),
@@ -85,8 +83,6 @@ static const struct exynos_dsi_cmd s6e3fc3_1_pwm_cmds[] = {
 	EXYNOS_DSI_CMD_SEQ(0x65, 0x01, 0x02, 0x22),
 	EXYNOS_DSI_CMD_SEQ(0xB0, 0x02, 0x38, 0x65),
 	EXYNOS_DSI_CMD_SEQ(0x65, 0x01, 0x00, 0x01, 0x00),
-	EXYNOS_DSI_CMD_SEQ(0xB0, 0x00, 0x28, 0xF2),
-	EXYNOS_DSI_CMD_SEQ(0xF2, 0xC4),
 	EXYNOS_DSI_CMD0(freq_update),
 	EXYNOS_DSI_CMD0(test_key_off_f0)
 };
@@ -94,8 +90,6 @@ static DEFINE_EXYNOS_CMD_SET(s6e3fc3_1_pwm);
 
 static const struct exynos_dsi_cmd s6e3fc3_4_pwm_cmds[] = {
 	EXYNOS_DSI_CMD0(test_key_on_f0),
-	EXYNOS_DSI_CMD_SEQ(0xB0, 0x28, 0xF2),
-	EXYNOS_DSI_CMD_SEQ(0xF2, 0xCC),
 	EXYNOS_DSI_CMD_SEQ(0xB0, 0x01, 0xF2, 0x65),
 	EXYNOS_DSI_CMD_SEQ(0x65, 0x01, 0xC4),
 	EXYNOS_DSI_CMD_SEQ(0xB0, 0x01, 0xD2, 0x65),
@@ -104,8 +98,6 @@ static const struct exynos_dsi_cmd s6e3fc3_4_pwm_cmds[] = {
 	EXYNOS_DSI_CMD_SEQ(0x65, 0x01, 0x02, 0x22),
 	EXYNOS_DSI_CMD_SEQ(0xB0, 0x02, 0x38, 0x65),
 	EXYNOS_DSI_CMD_SEQ(0x65, 0x01, 0x00, 0x01, 0x00),
-	EXYNOS_DSI_CMD_SEQ(0xB0, 0x00, 0x28, 0xF2),
-	EXYNOS_DSI_CMD_SEQ(0xF2, 0xC4),
 	EXYNOS_DSI_CMD0(freq_update),
 	EXYNOS_DSI_CMD0(test_key_off_f0)
 };
@@ -131,7 +123,7 @@ static const struct exynos_dsi_cmd s6e3fc3_init_cmds[] = {
 			       0xB9, 0x01, 0x09, 0x5C, 0x00, 0x0B),
 
 	/* FQ CON setting */
-	EXYNOS_DSI_CMD_SEQ(0xB0, 0x27, 0xF2 ),
+	EXYNOS_DSI_CMD_SEQ(0xB0, 0x27, 0xF2),
 	EXYNOS_DSI_CMD_SEQ(0xF2, 0x00),
 	EXYNOS_DSI_CMD0(freq_update),
 
@@ -149,8 +141,6 @@ static const struct exynos_dsi_cmd s6e3fc3_init_cmds[] = {
 	EXYNOS_DSI_CMD_SEQ(0xF2, 0xCC),
 	EXYNOS_DSI_CMD_SEQ(0xB0, 0x01, 0x34, 0x68),
 	EXYNOS_DSI_CMD_SEQ(0x68, 0x21, 0xC6, 0xE9),
-	EXYNOS_DSI_CMD_SEQ(0xB0, 0x00, 0x28, 0xF2),
-	EXYNOS_DSI_CMD_SEQ(0xF2, 0xC4),
 	EXYNOS_DSI_CMD0(test_key_off_f1),
 
 	EXYNOS_DSI_CMD0(test_key_off_f0)
@@ -226,8 +216,6 @@ static void s6e3fc3_update_te2(struct exynos_panel *ctx)
 	}
 
 	EXYNOS_DCS_WRITE_TABLE(ctx, test_key_on_f0);
-	EXYNOS_DCS_WRITE_SEQ(ctx, 0xB0, 0x28, 0xF2); /* global para  */
-	EXYNOS_DCS_WRITE_SEQ(ctx, 0xF2, 0xCC); /* global para 10bit */
 	EXYNOS_DCS_WRITE_SEQ(ctx, 0xB0, 0x00, 0x26, 0xF2); /* global para */
 	EXYNOS_DCS_WRITE_SEQ(ctx, 0xF2, 0x03, 0x14); /* TE2 on */
 	EXYNOS_DCS_WRITE_SEQ(ctx, 0xB0, 0x00, 0xAF, 0xCB); /* global para */
@@ -238,8 +226,6 @@ static void s6e3fc3_update_te2(struct exynos_panel *ctx)
 		EXYNOS_DCS_WRITE_SEQ(ctx, 0xB0, 0x01, 0xAF, 0xCB); /* global para */
 		EXYNOS_DCS_WRITE_TABLE(ctx, lp_setting); /* HLPM mode */
 	}
-	EXYNOS_DCS_WRITE_SEQ(ctx, 0xB0, 0x00, 0x28, 0xF2); /* global para */
-	EXYNOS_DCS_WRITE_SEQ(ctx, 0xF2, 0xC4); /* global para 8bit */
 	EXYNOS_DCS_WRITE_TABLE(ctx, freq_update); /* LTPS update */
 	EXYNOS_DCS_WRITE_TABLE(ctx, test_key_off_f0);
 }
@@ -309,8 +295,6 @@ static int s6e3fc3_lhbm_gamma_read(struct exynos_panel *ctx)
 	int ret;
 
 	EXYNOS_DCS_WRITE_TABLE(ctx, test_key_on_f0);
-	EXYNOS_DCS_WRITE_SEQ(ctx, 0xB0, 0x28, 0xF2); /* global para*/
-	EXYNOS_DCS_WRITE_SEQ(ctx, 0xF2, 0xCC); /* 10 bit */
 	EXYNOS_DCS_WRITE_SEQ(ctx, 0xB0, 0x00, 0x22, 0xD8); /* global para */
 	ret = mipi_dsi_dcs_read(dsi, 0xD8, gamma_cmd + 1, S6E3FC3_LOCAL_HBM_GAMMA_CMD_SIZE - 1);
 	if (ret == (S6E3FC3_LOCAL_HBM_GAMMA_CMD_SIZE - 1)) {
@@ -321,8 +305,6 @@ static int s6e3fc3_lhbm_gamma_read(struct exynos_panel *ctx)
 		dev_err(ctx->dev, "fail to read LHBM gamma\n");
 		ret = -EIO;
 	}
-	EXYNOS_DCS_WRITE_SEQ(ctx, 0xB0, 0x00, 0x28, 0xF2); /* global para*/
-	EXYNOS_DCS_WRITE_SEQ(ctx, 0xF2, 0xC4); /* 8 bit */
 	EXYNOS_DCS_WRITE_TABLE(ctx, test_key_off_f0);
 	return ret;
 }
@@ -330,13 +312,9 @@ static int s6e3fc3_lhbm_gamma_read(struct exynos_panel *ctx)
 static void s6e3fc3_lhbm_gamma_write(struct exynos_panel *ctx)
 {
 	EXYNOS_DCS_WRITE_TABLE(ctx, test_key_on_f0);
-	EXYNOS_DCS_WRITE_SEQ(ctx, 0xB0, 0x28, 0xF2); /* global para*/
-	EXYNOS_DCS_WRITE_SEQ(ctx, 0xF2, 0xCC); /* 10 bit */
 	EXYNOS_DCS_WRITE_SEQ(ctx, 0xB0, 0x03, 0xCD, 0x65); /* global para */
 	exynos_dcs_write(ctx, ctx->hbm.local_hbm.gamma_cmd,
 			 S6E3FC3_LOCAL_HBM_GAMMA_CMD_SIZE); /* write gamma */
-	EXYNOS_DCS_WRITE_SEQ(ctx, 0xB0, 0x00, 0x28, 0xF2); /* global para*/
-	EXYNOS_DCS_WRITE_SEQ(ctx, 0xF2, 0xC4); /* 8 bit */
 	EXYNOS_DCS_WRITE_TABLE(ctx, test_key_off_f0);
 }
 
@@ -405,7 +383,7 @@ static void s6e3fc3_set_hbm_mode(struct exynos_panel *exynos_panel,
 	}
 	if (irc_update) {
 		EXYNOS_DCS_WRITE_SEQ(exynos_panel, 0xF0, 0x5A, 0x5A);
-		EXYNOS_DCS_WRITE_SEQ(exynos_panel, 0xB0, 0x03, 0x8F);
+		EXYNOS_DCS_WRITE_SEQ(exynos_panel, 0xB0, 0x00, 0x03, 0x8F);
 		EXYNOS_DCS_WRITE_SEQ(exynos_panel, 0x8F, IS_HBM_ON_IRC_OFF(mode) ? 0x05 : 0x25);
 		EXYNOS_DCS_WRITE_SEQ(exynos_panel, 0xF0, 0xA5, 0xA5);
 	}