Took this DT fvp-base-gicv2-psci.dtb from linaroHEADjuice-2013.10master

openembedded 13.09 release page and modified panel
resolution to 640x480 from 1024x768 to speed up booting.

Change-Id: Ibc3e874918367babcf5b275d9ffb58566f29bd82
Signed-off-by: Amit Pundir <amit.pundir@linaro.org>

1 files changed, 397 insertions, 0 deletions

diff --git a/arch/arm64/boot/dts/fvp-base-gicv2-psci-android.dts b/arch/arm64/boot/dts/fvp-base-gicv2-psci-android.dts
new file mode 100644
index 00000000000..bc2354bfc9c
--- /dev/null
+++ b/arch/arm64/boot/dts/fvp-base-gicv2-psci-android.dts
@@ -0,0 +1,397 @@
+/dts-v1/;
+
+/memreserve/   0x0000000080000000 0x0000000000010000;
+/ {
+       model = "FVP Base";
+       compatible = "arm,vfp-base", "arm,vexpress";
+       interrupt-parent = <0x1>;
+       #address-cells = <0x2>;
+       #size-cells = <0x2>;
+
+       chosen {
+       };
+
+       aliases {
+               serial0 = "/smb/motherboard/iofpga@3,00000000/uart@090000";
+               serial1 = "/smb/motherboard/iofpga@3,00000000/uart@0a0000";
+               serial2 = "/smb/motherboard/iofpga@3,00000000/uart@0b0000";
+               serial3 = "/smb/motherboard/iofpga@3,00000000/uart@0c0000";
+       };
+
+       psci {
+               compatible = "arm,psci";
+               method = "smc";
+               cpu_suspend = <0xc4000001>;
+               cpu_off = <0x84000002>;
+               cpu_on = <0xc4000003>;
+       };
+
+       cpus {
+               #address-cells = <0x2>;
+               #size-cells = <0x0>;
+
+               cpu@0 {
+                       device_type = "cpu";
+                       compatible = "arm,armv8";
+                       reg = <0x0 0x0>;
+                       enable-method = "psci";
+               };
+
+               cpu@1 {
+                       device_type = "cpu";
+                       compatible = "arm,armv8";
+                       reg = <0x0 0x1>;
+                       enable-method = "psci";
+               };
+
+               cpu@2 {
+                       device_type = "cpu";
+                       compatible = "arm,armv8";
+                       reg = <0x0 0x2>;
+                       enable-method = "psci";
+               };
+
+               cpu@3 {
+                       device_type = "cpu";
+                       compatible = "arm,armv8";
+                       reg = <0x0 0x3>;
+                       enable-method = "psci";
+               };
+
+               cpu@100 {
+                       device_type = "cpu";
+                       compatible = "arm,armv8";
+                       reg = <0x0 0x100>;
+                       enable-method = "psci";
+               };
+
+               cpu@101 {
+                       device_type = "cpu";
+                       compatible = "arm,armv8";
+                       reg = <0x0 0x101>;
+                       enable-method = "psci";
+               };
+
+               cpu@102 {
+                       device_type = "cpu";
+                       compatible = "arm,armv8";
+                       reg = <0x0 0x102>;
+                       enable-method = "psci";
+               };
+
+               cpu@103 {
+                       device_type = "cpu";
+                       compatible = "arm,armv8";
+                       reg = <0x0 0x103>;
+                       enable-method = "psci";
+               };
+       };
+
+       memory@80000000 {
+               device_type = "memory";
+               reg = <0x0 0x80000000 0x0 0x80000000>;
+       };
+
+       interrupt-controller@2f000000 {
+               compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
+               #interrupt-cells = <0x3>;
+               #address-cells = <0x0>;
+               interrupt-controller;
+               reg = <0x0 0x2f000000 0x0 0x10000 0x0 0x2c000000 0x0 0x2000 0x0 0x2c010000 0x0 0x2000 0x0 0x2c02f000 0x0 0x2000>;
+               interrupts = <0x1 0x9 0xf04>;
+               linux,phandle = <0x1>;
+               phandle = <0x1>;
+       };
+
+       timer {
+               compatible = "arm,armv8-timer";
+               interrupts = <0x1 0xd 0xff01 0x1 0xe 0xff01 0x1 0xb 0xff01 0x1 0xa 0xff01>;
+               clock-frequency = <0x5f5e100>;
+       };
+
+       pmu {
+               compatible = "arm,armv8-pmuv3";
+               interrupts = <0x0 0x3c 0x4 0x0 0x3d 0x4 0x0 0x3e 0x4 0x0 0x3f 0x4>;
+       };
+
+       smb {
+               compatible = "simple-bus";
+               #address-cells = <0x2>;
+               #size-cells = <0x1>;
+               ranges = <0x0 0x0 0x0 0x8000000 0x4000000 0x1 0x0 0x0 0x14000000 0x4000000 0x2 0x0 0x0 0x18000000 0x4000000 0x3 0x0 0x0 0x1c000000 0x4000000 0x4 0x0 0x0 0xc000000 0x4000000 0x5 0x0 0x0 0x10000000 0x4000000>;
+               #interrupt-cells = <0x1>;
+               interrupt-map-mask = <0x0 0x0 0x3f>;
+               interrupt-map = <0x0 0x0 0x0 0x1 0x0 0x0 0x4 0x0 0x0 0x1 0x1 0x0 0x1 0x4 0x0 0x0 0x2 0x1 0x0 0x2 0x4 0x0 0x0 0x3 0x1 0x0 0x3 0x4 0x0 0x0 0x4 0x1 0x0 0x4 0x4 0x0 0x0 0x5 0x1 0x0 0x5 0x4 0x0 0x0 0x6 0x1 0x0 0x6 0x4 0x0 0x0 0x7 0x1 0x0 0x7 0x4 0x0 0x0 0x8 0x1 0x0 0x8 0x4 0x0 0x0 0x9 0x1 0x0 0x9 0x4 0x0 0x0 0xa 0x1 0x0 0xa 0x4 0x0 0x0 0xb 0x1 0x0 0xb 0x4 0x0 0x0 0xc 0x1 0x0 0xc 0x4 0x0 0x0 0xd 0x1 0x0 0xd 0x4 0x0 0x0 0xe 0x1 0x0 0xe 0x4 0x0 0x0 0xf 0x1 0x0 0xf 0x4 0x0 0x0 0x10 0x1 0x0 0x10 0x4 0x0 0x0 0x11 0x1 0x0 0x11 0x4 0x0 0x0 0x12 0x1 0x0 0x12 0x4 0x0 0x0 0x13 0x1 0x0 0x13 0x4 0x0 0x0 0x14 0x1 0x0 0x14 0x4 0x0 0x0 0x15 0x1 0x0 0x15 0x4 0x0 0x0 0x16 0x1 0x0 0x16 0x4 0x0 0x0 0x17 0x1 0x0 0x17 0x4 0x0 0x0 0x18 0x1 0x0 0x18 0x4 0x0 0x0 0x19 0x1 0x0 0x19 0x4 0x0 0x0 0x1a 0x1 0x0 0x1a 0x4 0x0 0x0 0x1b 0x1 0x0 0x1b 0x4 0x0 0x0 0x1c 0x1 0x0 0x1c 0x4 0x0 0x0 0x1d 0x1 0x0 0x1d 0x4 0x0 0x0 0x1e 0x1 0x0 0x1e 0x4 0x0 0x0 0x1f 0x1 0x0 0x1f 0x4 0x0 0x0 0x20 0x1 0x0 0x20 0x4 0x0 0x0 0x21 0x1 0x0 0x21 0x4 0x0 0x0 0x22 0x1 0x0 0x22 0x4 0x0 0x0 0x23 0x1 0x0 0x23 0x4 0x0 0x0 0x24 0x1 0x0 0x24 0x4 0x0 0x0 0x25 0x1 0x0 0x25 0x4 0x0 0x0 0x26 0x1 0x0 0x26 0x4 0x0 0x0 0x27 0x1 0x0 0x27 0x4 0x0 0x0 0x28 0x1 0x0 0x28 0x4 0x0 0x0 0x29 0x1 0x0 0x29 0x4 0x0 0x0 0x2a 0x1 0x0 0x2a 0x4>;
+
+               motherboard {
+                       arm,v2m-memory-map = "rs1";
+                       compatible = "arm,vexpress,v2m-p1", "simple-bus";
+                       #address-cells = <0x2>;
+                       #size-cells = <0x1>;
+                       #interrupt-cells = <0x1>;
+                       ranges;
+
+                       flash@0,00000000 {
+                               compatible = "arm,vexpress-flash", "cfi-flash";
+                               reg = <0x0 0x0 0x4000000 0x4 0x0 0x4000000>;
+                               bank-width = <0x4>;
+                       };
+
+                       vram@2,00000000 {
+                               compatible = "arm,vexpress-vram";
+                               reg = <0x2 0x0 0x800000>;
+                       };
+
+                       ethernet@2,02000000 {
+                               compatible = "smsc,lan91c111";
+                               reg = <0x2 0x2000000 0x10000>;
+                               interrupts = <0xf>;
+                       };
+
+                       clk24mhz {
+                               compatible = "fixed-clock";
+                               #clock-cells = <0x0>;
+                               clock-frequency = <0x16e3600>;
+                               clock-output-names = "v2m:clk24mhz";
+                               linux,phandle = <0x4>;
+                               phandle = <0x4>;
+                       };
+
+                       refclk1mhz {
+                               compatible = "fixed-clock";
+                               #clock-cells = <0x0>;
+                               clock-frequency = <0xf4240>;
+                               clock-output-names = "v2m:refclk1mhz";
+                               linux,phandle = <0x3>;
+                               phandle = <0x3>;
+                       };
+
+                       refclk32khz {
+                               compatible = "fixed-clock";
+                               #clock-cells = <0x0>;
+                               clock-frequency = <0x8000>;
+                               clock-output-names = "v2m:refclk32khz";
+                               linux,phandle = <0x2>;
+                               phandle = <0x2>;
+                       };
+
+                       iofpga@3,00000000 {
+                               compatible = "arm,amba-bus", "simple-bus";
+                               #address-cells = <0x1>;
+                               #size-cells = <0x1>;
+                               ranges = <0x0 0x3 0x0 0x200000>;
+
+                               sysreg@010000 {
+                                       compatible = "arm,vexpress-sysreg";
+                                       reg = <0x10000 0x1000>;
+                                       gpio-controller;
+                                       #gpio-cells = <0x2>;
+                                       linux,phandle = <0x5>;
+                                       phandle = <0x5>;
+                               };
+
+                               sysctl@020000 {
+                                       compatible = "arm,sp810", "arm,primecell";
+                                       reg = <0x20000 0x1000>;
+                                       clocks = <0x2 0x3 0x4>;
+                                       clock-names = "refclk", "timclk", "apb_pclk";
+                                       #clock-cells = <0x1>;
+                                       clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3";
+                                       linux,phandle = <0x7>;
+                                       phandle = <0x7>;
+                               };
+
+                               aaci@040000 {
+                                       compatible = "arm,pl041", "arm,primecell";
+                                       reg = <0x40000 0x1000>;
+                                       interrupts = <0xb>;
+                                       clocks = <0x4>;
+                                       clock-names = "apb_pclk";
+                               };
+
+                               mmci@050000 {
+                                       compatible = "arm,pl180", "arm,primecell";
+                                       reg = <0x50000 0x1000>;
+                                       interrupts = <0x9 0xa>;
+                                       cd-gpios = <0x5 0x0 0x0>;
+                                       wp-gpios = <0x5 0x1 0x0>;
+                                       max-frequency = <0xb71b00>;
+                                       vmmc-supply = <0x6>;
+                                       clocks = <0x4 0x4>;
+                                       clock-names = "mclk", "apb_pclk";
+                               };
+
+                               kmi@060000 {
+                                       compatible = "arm,pl050", "arm,primecell";
+                                       reg = <0x60000 0x1000>;
+                                       interrupts = <0xc>;
+                                       clocks = <0x4 0x4>;
+                                       clock-names = "KMIREFCLK", "apb_pclk";
+                               };
+
+                               kmi@070000 {
+                                       compatible = "arm,pl050", "arm,primecell";
+                                       reg = <0x70000 0x1000>;
+                                       interrupts = <0xd>;
+                                       clocks = <0x4 0x4>;
+                                       clock-names = "KMIREFCLK", "apb_pclk";
+                               };
+
+                               uart@090000 {
+                                       compatible = "arm,pl011", "arm,primecell";
+                                       reg = <0x90000 0x1000>;
+                                       interrupts = <0x5>;
+                                       clocks = <0x4 0x4>;
+                                       clock-names = "uartclk", "apb_pclk";
+                               };
+
+                               uart@0a0000 {
+                                       compatible = "arm,pl011", "arm,primecell";
+                                       reg = <0xa0000 0x1000>;
+                                       interrupts = <0x6>;
+                                       clocks = <0x4 0x4>;
+                                       clock-names = "uartclk", "apb_pclk";
+                               };
+
+                               uart@0b0000 {
+                                       compatible = "arm,pl011", "arm,primecell";
+                                       reg = <0xb0000 0x1000>;
+                                       interrupts = <0x7>;
+                                       clocks = <0x4 0x4>;
+                                       clock-names = "uartclk", "apb_pclk";
+                               };
+
+                               uart@0c0000 {
+                                       compatible = "arm,pl011", "arm,primecell";
+                                       reg = <0xc0000 0x1000>;
+                                       interrupts = <0x8>;
+                                       clocks = <0x4 0x4>;
+                                       clock-names = "uartclk", "apb_pclk";
+                               };
+
+                               wdt@0f0000 {
+                                       compatible = "arm,sp805", "arm,primecell";
+                                       reg = <0xf0000 0x1000>;
+                                       interrupts = <0x0>;
+                                       clocks = <0x2 0x4>;
+                                       clock-names = "wdogclk", "apb_pclk";
+                               };
+
+                               timer@110000 {
+                                       compatible = "arm,sp804", "arm,primecell";
+                                       reg = <0x110000 0x1000>;
+                                       interrupts = <0x2>;
+                                       clocks = <0x7 0x0 0x7 0x1 0x4>;
+                                       clock-names = "timclken1", "timclken2", "apb_pclk";
+                               };
+
+                               timer@120000 {
+                                       compatible = "arm,sp804", "arm,primecell";
+                                       reg = <0x120000 0x1000>;
+                                       interrupts = <0x3>;
+                                       clocks = <0x7 0x2 0x7 0x3 0x4>;
+                                       clock-names = "timclken1", "timclken2", "apb_pclk";
+                               };
+
+                               rtc@170000 {
+                                       compatible = "arm,pl031", "arm,primecell";
+                                       reg = <0x170000 0x1000>;
+                                       interrupts = <0x4>;
+                                       clocks = <0x4>;
+                                       clock-names = "apb_pclk";
+                               };
+
+                               clcd@1f0000 {
+                                       compatible = "arm,pl111", "arm,primecell";
+                                       reg = <0x1f0000 0x1000>;
+                                       interrupts = <0xe>;
+                                       clocks = <0x8 0x4>;
+                                       clock-names = "clcdclk", "apb_pclk";
+                                       mode = "XVGA";
+                                       use_dma = <0x0>;
+                                       framebuffer = <0x18000000 0x180000>;
+                               };
+
+                               virtio_block@0130000 {
+                                       compatible = "virtio,mmio";
+                                       reg = <0x130000 0x1000>;
+                                       interrupts = <0x2a>;
+                               };
+                       };
+
+                       fixedregulator@0 {
+                               compatible = "regulator-fixed";
+                               regulator-name = "3V3";
+                               regulator-min-microvolt = <0x325aa0>;
+                               regulator-max-microvolt = <0x325aa0>;
+                               regulator-always-on;
+                               linux,phandle = <0x6>;
+                               phandle = <0x6>;
+                       };
+
+                       mcc {
+                               compatible = "arm,vexpress,config-bus", "simple-bus";
+                               arm,vexpress,config-bridge = <0x5>;
+
+                               osc@1 {
+                                       compatible = "arm,vexpress-osc";
+                                       arm,vexpress-sysreg,func = <0x1 0x1>;
+                                       freq-range = <0x16a6570 0x3c8eee0>;
+                                       #clock-cells = <0x0>;
+                                       clock-output-names = "v2m:oscclk1";
+                                       linux,phandle = <0x8>;
+                                       phandle = <0x8>;
+                               };
+
+                               reset@0 {
+                                       compatible = "arm,vexpress-reset";
+                                       arm,vexpress-sysreg,func = <0x5 0x0>;
+                               };
+
+                               muxfpga@0 {
+                                       compatible = "arm,vexpress-muxfpga";
+                                       arm,vexpress-sysreg,func = <0x7 0x0>;
+                               };
+
+                               shutdown@0 {
+                                       compatible = "arm,vexpress-shutdown";
+                                       arm,vexpress-sysreg,func = <0x8 0x0>;
+                               };
+
+                               reboot@0 {
+                                       compatible = "arm,vexpress-reboot";
+                                       arm,vexpress-sysreg,func = <0x9 0x0>;
+                               };
+
+                               dvimode@0 {
+                                       compatible = "arm,vexpress-dvimode";
+                                       arm,vexpress-sysreg,func = <0xb 0x0>;
+                               };
+                       };
+               };
+       };
+
+       panels {
+
+               panel@0 {
+                       compatible = "panel";
+                       mode = "XVGA";
+                       refresh = <0x3c>;
+                       xres = <0x280>;
+                       yres = <0x1E0>;
+                       pixclock = <0x3d84>;
+                       left_margin = <0x98>;
+                       right_margin = <0x30>;
+                       upper_margin = <0x17>;
+                       lower_margin = <0x3>;
+                       hsync_len = <0x68>;
+                       vsync_len = <0x4>;
+                       sync = <0x0>;
+                       vmode = "FB_VMODE_NONINTERLACED";
+                       tim2 = "TIM2_BCD", "TIM2_IPC";
+                       cntl = "CNTL_LCDTFT", "CNTL_BGR", "CNTL_LCDVCOMP(1)";
+                       caps = "CLCD_CAP_5551", "CLCD_CAP_565", "CLCD_CAP_888";
+                       bpp = <0x10>;
+               };
+       };
+};