earlyboot: reduce dts footprint6AM.1.3-rvc-video-earlyboot

temp: for benchmarking purpose, reduce dts footprint

Change-Id: I8df671274c850aeac45a2ee3c4240d56140ff5c0
Signed-off-by: Praneeth Bajjuri <praneeth@ti.com>

3 files changed, 0 insertions, 599 deletions

diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts
index 388142161259..9d3b184c1cb9 100644
--- a/arch/arm/boot/dts/dra7-evm.dts
+++ b/arch/arm/boot/dts/dra7-evm.dts
@@ -33,20 +33,6 @@
 			status = "okay";
 		};
 
-		dsp1_cma_pool: dsp1_cma@99000000 {
-			compatible = "shared-dma-pool";
-			reg = <0x0 0x99000000 0x0 0x4000000>;
-			reusable;
-			status = "okay";
-		};
-
-		ipu1_cma_pool: ipu1_cma@9d000000 {
-			compatible = "shared-dma-pool";
-			reg = <0x0 0x9d000000 0x0 0x2000000>;
-			reusable;
-			status = "okay";
-		};
-
 		dsp2_cma_pool: dsp2_cma@9f000000 {
 			compatible = "shared-dma-pool";
 			reg = <0x0 0x9f000000 0x0 0x800000>;
@@ -56,11 +42,7 @@
 	};
 
 	aliases {
-		display0 = &hdmi0;
-		display1 = &fpd_disp;
 		sound0 = &snd0;
-		sound1 = &hdmi;
-		i2c7 = &disp_ser;
 	};
 
 	evm_3v3_sd: fixedregulator-sd {
@@ -155,137 +137,9 @@
 		};
 	};
 
-	leds {
-		compatible = "gpio-leds";
-		led@0 {
-			label = "dra7:usr1";
-			gpios = <&pcf_lcd 4 GPIO_ACTIVE_LOW>;
-			default-state = "off";
-		};
-
-		led@1 {
-			label = "dra7:usr2";
-			gpios = <&pcf_lcd 5 GPIO_ACTIVE_LOW>;
-			default-state = "off";
-		};
-
-		led@2 {
-			label = "dra7:usr3";
-			gpios = <&pcf_lcd 6 GPIO_ACTIVE_LOW>;
-			default-state = "off";
-		};
-
-		led@3 {
-			label = "dra7:usr4";
-			gpios = <&pcf_lcd 7 GPIO_ACTIVE_LOW>;
-			default-state = "off";
-		};
-	};
-
-	gpio_keys {
-		compatible = "gpio-keys";
-		#address-cells = <1>;
-		#size-cells = <0>;
-		autorepeat;
-
-		USER1 {
-			label = "btnUser1";
-			linux,code = <BTN_0>;
-			gpios = <&pcf_lcd 2 GPIO_ACTIVE_LOW>;
-		};
-
-		USER2 {
-			label = "btnUser2";
-			linux,code = <BTN_1>;
-			gpios = <&pcf_lcd 3 GPIO_ACTIVE_LOW>;
-		};
-	};
-
-	hdmi0: connector@1 {
-		compatible = "hdmi-connector";
-		label = "hdmi";
-
-		type = "a";
-
-		port {
-			hdmi_connector_in: endpoint {
-				remote-endpoint = <&tpd12s015_out>;
-			};
-		};
-	};
-
-	tpd12s015: encoder@1 {
-		compatible = "ti,dra7evm-tpd12s015";
-
-		pinctrl-names = "i2c", "ddc";
-		pinctrl-0 = <&hdmi_i2c_sel_pin &hdmi_i2c_pins_i2c>;
-		pinctrl-1 = <&hdmi_i2c_sel_pin &hdmi_i2c_pins_ddc>;
-
-		ddc-i2c-bus = <&i2c2>;
-		mcasp-gpio = <&mcasp8>;
-
-		gpios = <&pcf_hdmi 4 0>,	/* P4, CT CP HPD */
-			<&pcf_hdmi 5 0>,	/* P5, LS OE */
-			<&gpio7 12 0>;	/* gpio7_12/sp1_cs2, HPD */
-
-		ports {
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			port@0 {
-				reg = <0>;
-
-				tpd12s015_in: endpoint@0 {
-					remote-endpoint = <&hdmi_out>;
-				};
-			};
-
-			port@1 {
-				reg = <1>;
-
-				tpd12s015_out: endpoint@0 {
-					remote-endpoint = <&hdmi_connector_in>;
-				};
-			};
-		};
-	};
 };
 
 &dra7_pmx_core {
-	dcan1_pins_default: dcan1_pins_default {
-		pinctrl-single,pins = <
-			0x3d0   (PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */
-			0x418   (PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */
-		>;
-	};
-
-	dcan1_pins_sleep: dcan1_pins_sleep {
-		pinctrl-single,pins = <
-			0x3d0   (MUX_MODE15 | PULL_UP)	/* dcan1_tx.off */
-			0x418   (MUX_MODE15 | PULL_UP)	/* wakeup0.off */
-		>;
-	};
-
-	hdmi_i2c_sel_pin: pinmux_hdmi_i2c_sel_pin {
-		pinctrl-single,pins = <
-			/* this pin is used as a GPIO via mcasp */
-			0x2fc   (PIN_OUTPUT | MUX_MODE1) /* mcasp8_axr2 */
-		>;
-	};
-
-	hdmi_i2c_pins_i2c: pinmux_hdmi_i2c_pins_default {
-		pinctrl-single,pins = <
-			0x408   (PIN_INPUT | MUX_MODE0) /* i2c2_sda.i2c2_sda */
-			0x40c   (PIN_INPUT | MUX_MODE0) /* i2c2_scl.i2c2_scl */
-		>;
-	};
-
-	hdmi_i2c_pins_ddc: pinmux_hdmi_i2c_pins_ddc {
-		pinctrl-single,pins = <
-			0x408   (PIN_INPUT | MUX_MODE1) /* i2c2_sda.hdmi1_ddc_scl */
-			0x40c   (PIN_INPUT | MUX_MODE1) /* i2c2_scl.hdmi1_ddc_sda */
-		>;
-	};
 
 	mmc1_pins_default: pinmux_mmc1_default_pins {
 		pinctrl-single,pins = <
@@ -424,49 +278,6 @@
 		>;
 	};
 
-	mmc4_pins_default: mmc4_pins_default {
-		pinctrl-single,pins = <
-			0x3e8 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE3) /* uart1_ctsn.mmc4_clk */
-			0x3ec (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */
-			0x3f0 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE3) /* uart2_rxd.mmc4_dat0 */
-			0x3f4 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE3) /* uart2_txd.mmc4_dat1 */
-			0x3f8 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE3) /* uart2_ctsn.mmc4_dat2 */
-			0x3fC (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE3) /* uart2_rtsn.mmc4_dat3 */
-		>;
-	};
-
-	mmc4_pins_hs: mmc4_pins_hs {
-		pinctrl-single,pins = <
-			0x3e8 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE3) /* uart1_ctsn.mmc4_clk */
-			0x3ec (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */
-			0x3f0 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE3) /* uart2_rxd.mmc4_dat0 */
-			0x3f4 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE3) /* uart2_txd.mmc4_dat1 */
-			0x3f8 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE3) /* uart2_ctsn.mmc4_dat2 */
-			0x3fC (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE3) /* uart2_rtsn.mmc4_dat3 */
-		>;
-	};
-
-	mmc4_pins_sdr12: mmc4_pins_sdr12 {
-		pinctrl-single,pins = <
-			0x3e8 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE3) /* uart1_ctsn.mmc4_clk */
-			0x3eC (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */
-			0x3f0 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE3) /* uart2_rxd.mmc4_dat0 */
-			0x3f4 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE3) /* uart2_txd.mmc4_dat1 */
-			0x3f8 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE3) /* uart2_ctsn.mmc4_dat2 */
-			0x3fc (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE3) /* uart2_rtsn.mmc4_dat3 */
-		>;
-	};
-
-	mmc4_pins_sdr25: mmc4_pins_sdr25 {
-		pinctrl-single,pins = <
-			0x3e8 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE3) /* uart1_ctsn.mmc4_clk */
-			0x3eC (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */
-			0x3f0 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE3) /* uart2_rxd.mmc4_dat0 */
-			0x3f4 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE3) /* uart2_txd.mmc4_dat1 */
-			0x3f8 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE3) /* uart2_ctsn.mmc4_dat2 */
-			0x3fc (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE3) /* uart2_rtsn.mmc4_dat3 */
-		>;
-	};
 };
 
 &dra7_iodelay_core {
@@ -662,93 +473,6 @@
 		>;
 	};
 
-	mmc4_iodelay_ds_rev11_conf: mmc4_iodelay_ds_rev11_conf {
-		pinctrl-single,pins = <
-			0x840 (A_DELAY(0) | G_DELAY(0))		/* CFG_UART1_CTSN_IN */
-			0x848 (A_DELAY(0) | G_DELAY(0))		/* CFG_UART1_CTSN_OUT */
-			0x84c (A_DELAY(96) | G_DELAY(0))	/* CFG_UART1_RTSN_IN */
-			0x850 (A_DELAY(0) | G_DELAY(0))		/* CFG_UART1_RTSN_OEN */
-			0x854 (A_DELAY(0) | G_DELAY(0))		/* CFG_UART1_RTSN_OUT */
-			0x870 (A_DELAY(582) | G_DELAY(0))	/* CFG_UART2_CTSN_IN */
-			0x874 (A_DELAY(0) | G_DELAY(0))		/* CFG_UART2_CTSN_OEN */
-			0x878 (A_DELAY(0) | G_DELAY(0))		/* CFG_UART2_CTSN_OUT */
-			0x87c (A_DELAY(391) | G_DELAY(0))	/* CFG_UART2_RTSN_IN */
-			0x880 (A_DELAY(0) | G_DELAY(0))		/* CFG_UART2_RTSN_OEN */
-			0x884 (A_DELAY(0) | G_DELAY(0))		/* CFG_UART2_RTSN_OUT */
-			0x888 (A_DELAY(561) | G_DELAY(0))	/* CFG_UART2_RXD_IN */
-			0x88c (A_DELAY(0) | G_DELAY(0))		/* CFG_UART2_RXD_OEN */
-			0x890 (A_DELAY(0) | G_DELAY(0))		/* CFG_UART2_RXD_OUT */
-			0x894 (A_DELAY(588) | G_DELAY(0))	/* CFG_UART2_TXD_IN */
-			0x898 (A_DELAY(0) | G_DELAY(0))		/* CFG_UART2_TXD_OEN */
-			0x89c (A_DELAY(0) | G_DELAY(0))		/* CFG_UART2_TXD_OUT */
-		>;
-	};
-
-	mmc4_iodelay_ds_rev20_conf: mmc4_iodelay_ds_rev20_conf {
-		pinctrl-single,pins = <
-			0x840 (A_DELAY(0) | G_DELAY(0))		/* CFG_UART1_CTSN_IN */
-			0x848 (A_DELAY(0) | G_DELAY(0))		/* CFG_UART1_CTSN_OUT */
-			0x84c (A_DELAY(307) | G_DELAY(0))	/* CFG_UART1_RTSN_IN */
-			0x850 (A_DELAY(0) | G_DELAY(0))		/* CFG_UART1_RTSN_OEN */
-			0x854 (A_DELAY(0) | G_DELAY(0))		/* CFG_UART1_RTSN_OUT */
-			0x870 (A_DELAY(785) | G_DELAY(0))	/* CFG_UART2_CTSN_IN */
-			0x874 (A_DELAY(0) | G_DELAY(0))		/* CFG_UART2_CTSN_OEN */
-			0x878 (A_DELAY(0) | G_DELAY(0))		/* CFG_UART2_CTSN_OUT */
-			0x87c (A_DELAY(613) | G_DELAY(0))	/* CFG_UART2_RTSN_IN */
-			0x880 (A_DELAY(0) | G_DELAY(0))		/* CFG_UART2_RTSN_OEN */
-			0x884 (A_DELAY(0) | G_DELAY(0))		/* CFG_UART2_RTSN_OUT */
-			0x888 (A_DELAY(683) | G_DELAY(0))	/* CFG_UART2_RXD_IN */
-			0x88c (A_DELAY(0) | G_DELAY(0))		/* CFG_UART2_RXD_OEN */
-			0x890 (A_DELAY(0) | G_DELAY(0))		/* CFG_UART2_RXD_OUT */
-			0x894 (A_DELAY(835) | G_DELAY(0))	/* CFG_UART2_TXD_IN */
-			0x898 (A_DELAY(0) | G_DELAY(0))		/* CFG_UART2_TXD_OEN */
-			0x89c (A_DELAY(0) | G_DELAY(0))		/* CFG_UART2_TXD_OUT */
-		>;
-	};
-
-	mmc4_iodelay_sdr12_hs_sdr25_rev11_conf: mmc4_iodelay_sdr12_hs_sdr25_rev11_conf {
-		pinctrl-single,pins = <
-			0x840 (A_DELAY(0) | G_DELAY(0))		/* CFG_UART1_CTSN_IN */
-			0x848 (A_DELAY(2651) | G_DELAY(0))	/* CFG_UART1_CTSN_OUT */
-			0x84c (A_DELAY(1572) | G_DELAY(0))	/* CFG_UART1_RTSN_IN */
-			0x850 (A_DELAY(0) | G_DELAY(0))		/* CFG_UART1_RTSN_OEN */
-			0x854 (A_DELAY(0) | G_DELAY(0))		/* CFG_UART1_RTSN_OUT */
-			0x870 (A_DELAY(1913) | G_DELAY(0))	/* CFG_UART2_CTSN_IN */
-			0x874 (A_DELAY(0) | G_DELAY(0))		/* CFG_UART2_CTSN_OEN */
-			0x878 (A_DELAY(0) | G_DELAY(0))		/* CFG_UART2_CTSN_OUT */
-			0x87c (A_DELAY(1721) | G_DELAY(0))	/* CFG_UART2_RTSN_IN */
-			0x880 (A_DELAY(0) | G_DELAY(0))		/* CFG_UART2_RTSN_OEN */
-			0x884 (A_DELAY(0) | G_DELAY(0))		/* CFG_UART2_RTSN_OUT */
-			0x888 (A_DELAY(1891) | G_DELAY(0))	/* CFG_UART2_RXD_IN */
-			0x88c (A_DELAY(0) | G_DELAY(0))		/* CFG_UART2_RXD_OEN */
-			0x890 (A_DELAY(0) | G_DELAY(0))		/* CFG_UART2_RXD_OUT */
-			0x894 (A_DELAY(1919) | G_DELAY(0))	/* CFG_UART2_TXD_IN */
-			0x898 (A_DELAY(0) | G_DELAY(0))		/* CFG_UART2_TXD_OEN */
-			0x89c (A_DELAY(0) | G_DELAY(0))		/* CFG_UART2_TXD_OUT */
-		>;
-	};
-
-	mmc4_iodelay_sdr12_hs_sdr25_rev20_conf: mmc4_iodelay_sdr12_hs_sdr25_rev20_conf {
-		pinctrl-single,pins = <
-			0x840 (A_DELAY(0) | G_DELAY(0))		/* CFG_UART1_CTSN_IN */
-			0x848 (A_DELAY(1147) | G_DELAY(0))	/* CFG_UART1_CTSN_OUT */
-			0x84c (A_DELAY(1834) | G_DELAY(0))	/* CFG_UART1_RTSN_IN */
-			0x850 (A_DELAY(0) | G_DELAY(0))		/* CFG_UART1_RTSN_OEN */
-			0x854 (A_DELAY(0) | G_DELAY(0))		/* CFG_UART1_RTSN_OUT */
-			0x870 (A_DELAY(2165) | G_DELAY(0))	/* CFG_UART2_CTSN_IN */
-			0x874 (A_DELAY(0) | G_DELAY(0))		/* CFG_UART2_CTSN_OEN */
-			0x878 (A_DELAY(0) | G_DELAY(0))		/* CFG_UART2_CTSN_OUT */
-			0x87c (A_DELAY(1929) | G_DELAY(64))	/* CFG_UART2_RTSN_IN */
-			0x880 (A_DELAY(0) | G_DELAY(0))		/* CFG_UART2_RTSN_OEN */
-			0x884 (A_DELAY(0) | G_DELAY(0))		/* CFG_UART2_RTSN_OUT */
-			0x888 (A_DELAY(1935) | G_DELAY(128))	/* CFG_UART2_RXD_IN */
-			0x88c (A_DELAY(0) | G_DELAY(0))		/* CFG_UART2_RXD_OEN */
-			0x890 (A_DELAY(0) | G_DELAY(0))		/* CFG_UART2_RXD_OUT */
-			0x894 (A_DELAY(2172) | G_DELAY(44))	/* CFG_UART2_TXD_IN */
-			0x898 (A_DELAY(0) | G_DELAY(0))		/* CFG_UART2_TXD_OEN */
-			0x89c (A_DELAY(0) | G_DELAY(0))		/* CFG_UART2_TXD_OUT */
-		>;
-	};
 };
 
 &i2c1 {
@@ -972,36 +696,6 @@ i2c_p3_exp: &i2c2 {
 		};
 	};
 
-	disp_ser: serializer@1b {
-		compatible = "ti,ds90uh925q";
-		reg = <0x1b>;
-
-		#address-cells = <1>;
-		#size-cells = <0>;
-		ranges = <0x2c 0x2c>,
-			<0x1c 0x1c>;
-
-		disp_des: deserializer@2c {
-			compatible = "ti,ds90uh928q";
-			reg = <0x2c>;
-			slave-mode;
-		};
-
-		/* TLC chip for LCD panel power and backlight */
-		fpd_disp: tlc59108@1c {
-			status = "disabled";
-			reg = <0x1c>;
-			compatible = "ti,tlc59108-fpddisp";
-			enable-gpios = <&pcf_gpio_21 0 GPIO_ACTIVE_LOW>;
-			/* P0, SEL_GPMC_AD_VID_S0 */
-
-			port@lcd3 {
-					fpd_in: endpoint {
-					remote-endpoint = <&dpi_out3>;
-				};
-			};
-		};
-	};
 };
 
 &i2c3 {
@@ -1009,13 +703,6 @@ i2c_p3_exp: &i2c2 {
 	clock-frequency = <400000>;
 };
 
-&mcspi1 {
-	status = "okay";
-};
-
-&mcspi2 {
-	status = "okay";
-};
 
 &uart1 {
 	status = "okay";
@@ -1023,14 +710,6 @@ i2c_p3_exp: &i2c2 {
 			      <&dra7_pmx_core 0x3e0>;
 };
 
-&uart2 {
-	status = "okay";
-};
-
-&uart3 {
-	status = "okay";
-};
-
 &mmc1 {
 	status = "okay";
 	vmmc-supply = <&evm_3v3_sd>;
@@ -1068,34 +747,6 @@ i2c_p3_exp: &i2c2 {
 	pinctrl-5 = <&mmc2_pins_hs200_1_8v &mmc2_iodelay_hs200_1_8v_rev20_conf>;
 };
 
-&mmc4 {
-	status = "disabled";
-	vmmc-supply = <&vmmcwl_fixed>;
-	bus-width = <4>;
-	cap-power-off-card;
-	keep-power-in-suspend;
-	ti,non-removable;
-
-	pinctrl-names = "default-rev11", "default", "hs-rev11", "hs", "sdr12-rev11", "sdr12", "sdr25-rev11", "sdr25";
-	pinctrl-0 = <&mmc4_pins_default &mmc4_iodelay_ds_rev11_conf>;
-	pinctrl-1 = <&mmc4_pins_default &mmc4_iodelay_ds_rev20_conf>;
-	pinctrl-2 = <&mmc4_pins_hs &mmc4_iodelay_sdr12_hs_sdr25_rev11_conf>;
-	pinctrl-3 = <&mmc4_pins_hs &mmc4_iodelay_sdr12_hs_sdr25_rev20_conf>;
-	pinctrl-4 = <&mmc4_pins_sdr12 &mmc4_iodelay_sdr12_hs_sdr25_rev11_conf>;
-	pinctrl-5 = <&mmc4_pins_sdr12 &mmc4_iodelay_sdr12_hs_sdr25_rev20_conf>;
-	pinctrl-6 = <&mmc4_pins_sdr25 &mmc4_iodelay_sdr12_hs_sdr25_rev11_conf>;
-	pinctrl-7 = <&mmc4_pins_sdr25 &mmc4_iodelay_sdr12_hs_sdr25_rev20_conf>;
-
-	#address-cells = <1>;
-	#size-cells = <0>;
-	wlcore: wlcore@0 {
-		compatible = "ti,wl1835";
-		reg = <2>;
-		interrupt-parent = <&gpio5>;
-		interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
-	};
-};
-
 &oppdm_mpu {
 	vdd-supply = <&smps123_reg>;
 };
@@ -1116,199 +767,11 @@ i2c_p3_exp: &i2c2 {
 	vdd-supply = <&smps7_reg>;
 };
 
-&pcie1_rc {
-	status = "okay";
-};
-
-&qspi {
-	status = "okay";
-
-	spi-max-frequency = <76800000>;
-	m25p80@0 {
-		compatible = "s25fl256s1";
-		spi-max-frequency = <76800000>;
-		reg = <0>;
-		spi-tx-bus-width = <1>;
-		spi-rx-bus-width = <4>;
-		#address-cells = <1>;
-		#size-cells = <1>;
-
-		/* MTD partition table.
-		 * The ROM checks the first four physical blocks
-		 * for a valid file to boot and the flash here is
-		 * 64KiB block size.
-		 */
-		partition@0 {
-			label = "QSPI.SPL";
-			reg = <0x00000000 0x000040000>;
-		};
-		partition@1 {
-			label = "QSPI.u-boot";
-			reg = <0x00040000 0x00100000>;
-		};
-		partition@2 {
-			label = "QSPI.u-boot-spl-os";
-			reg = <0x00140000 0x00080000>;
-		};
-		partition@3 {
-			label = "QSPI.u-boot-env";
-			reg = <0x001c0000 0x00010000>;
-		};
-		partition@4 {
-			label = "QSPI.u-boot-env.backup1";
-			reg = <0x001d0000 0x0010000>;
-		};
-		partition@5 {
-			label = "QSPI.kernel";
-			reg = <0x001e0000 0x0800000>;
-		};
-		partition@6 {
-			label = "QSPI.file-system";
-			reg = <0x009e0000 0x01620000>;
-		};
-	};
-};
-
-&omap_dwc3_1 {
-	extcon = <&extcon_usb1>;
-};
-
-&omap_dwc3_2 {
-	extcon = <&extcon_usb2>;
-};
-
-&usb1 {
-	dr_mode = "otg";
-};
-
-&usb2 {
-	dr_mode = "host";
-};
-
-&elm {
-	status = "okay";
-};
-
-&gpmc {
-	status = "okay";
-	ranges = <0 0 0x08000000 0x01000000>;	/* minimum GPMC partition = 16MB */
-	nand@0,0 {
-		compatible = "ti,omap2-nand";
-		reg = <0 0 4>;		/* device IO registers */
-		interrupt-parent = <&gpmc>;
-		interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
-			     <1 IRQ_TYPE_NONE>; /* termcount */
-		rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 pin */
-		ti,nand-ecc-opt = "bch8";
-		ti,elm-id = <&elm>;
-		nand-bus-width = <16>;
-		gpmc,device-width = <2>;
-		gpmc,sync-clk-ps = <0>;
-		gpmc,cs-on-ns = <0>;
-		gpmc,cs-rd-off-ns = <80>;
-		gpmc,cs-wr-off-ns = <80>;
-		gpmc,adv-on-ns = <0>;
-		gpmc,adv-rd-off-ns = <60>;
-		gpmc,adv-wr-off-ns = <60>;
-		gpmc,we-on-ns = <10>;
-		gpmc,we-off-ns = <50>;
-		gpmc,oe-on-ns = <4>;
-		gpmc,oe-off-ns = <40>;
-		gpmc,access-ns = <40>;
-		gpmc,wr-access-ns = <80>;
-		gpmc,rd-cycle-ns = <80>;
-		gpmc,wr-cycle-ns = <80>;
-		gpmc,bus-turnaround-ns = <0>;
-		gpmc,cycle2cycle-delay-ns = <0>;
-		gpmc,clk-activation-ns = <0>;
-		gpmc,wr-data-mux-bus-ns = <0>;
-		/* MTD partition table */
-		/* All SPL-* partitions are sized to minimal length
-		 * which can be independently programmable. For
-		 * NAND flash this is equal to size of erase-block */
-		#address-cells = <1>;
-		#size-cells = <1>;
-		partition@0 {
-			label = "NAND.SPL";
-			reg = <0x00000000 0x000020000>;
-		};
-		partition@1 {
-			label = "NAND.SPL.backup1";
-			reg = <0x00020000 0x00020000>;
-		};
-		partition@2 {
-			label = "NAND.SPL.backup2";
-			reg = <0x00040000 0x00020000>;
-		};
-		partition@3 {
-			label = "NAND.SPL.backup3";
-			reg = <0x00060000 0x00020000>;
-		};
-		partition@4 {
-			label = "NAND.u-boot-spl-os";
-			reg = <0x00080000 0x00040000>;
-		};
-		partition@5 {
-			label = "NAND.u-boot";
-			reg = <0x000c0000 0x00100000>;
-		};
-		partition@6 {
-			label = "NAND.u-boot-env";
-			reg = <0x001c0000 0x00020000>;
-		};
-		partition@7 {
-			label = "NAND.u-boot-env.backup1";
-			reg = <0x001e0000 0x00020000>;
-		};
-		partition@8 {
-			label = "NAND.kernel";
-			reg = <0x00200000 0x00800000>;
-		};
-		partition@9 {
-			label = "NAND.file-system";
-			reg = <0x00a00000 0x0f600000>;
-		};
-	};
-};
-
-&usb2_phy1 {
-	phy-supply = <&ldousb_reg>;
-};
-
-&usb2_phy2 {
-	phy-supply = <&ldousb_reg>;
-};
-
 &gpio7 {
 	ti,no-reset-on-init;
 	ti,no-idle-on-init;
 };
 
-&mac {
-	status = "okay";
-	dual_emac;
-};
-
-&cpsw_emac0 {
-	phy_id = <&davinci_mdio>, <2>;
-	phy-mode = "rgmii";
-	dual_emac_res_vlan = <1>;
-};
-
-&cpsw_emac1 {
-	phy_id = <&davinci_mdio>, <3>;
-	phy-mode = "rgmii";
-	dual_emac_res_vlan = <2>;
-};
-
-&dcan1 {
-	status = "ok";
-	pinctrl-names = "default", "sleep", "active";
-	pinctrl-0 = <&dcan1_pins_sleep>;
-	pinctrl-1 = <&dcan1_pins_sleep>;
-	pinctrl-2 = <&dcan1_pins_default>;
-};
-
 &atl {
 	assigned-clocks = <&abe_dpll_sys_clk_mux>,
 			  <&atl_gfclk_mux>,
@@ -1346,11 +809,6 @@ i2c_p3_exp: &i2c2 {
 	rx-num-evt = <32>;
 };
 
-&mcasp8 {
-	/* not used for audio. only the AXR2 pin is used as GPIO */
-	status = "okay";
-};
-
 &mailbox5 {
 	status = "okay";
 	mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
@@ -1375,10 +833,6 @@ i2c_p3_exp: &i2c2 {
 	status = "okay";
 };
 
-&mmu1_dsp1 {
-	status = "okay";
-};
-
 &mmu0_dsp2 {
 	status = "okay";
 };
@@ -1387,10 +841,6 @@ i2c_p3_exp: &i2c2 {
 	status = "okay";
 };
 
-&mmu_ipu1 {
-	status = "okay";
-};
-
 &mmu_ipu2 {
 	status = "okay";
 };
@@ -1403,22 +853,6 @@ i2c_p3_exp: &i2c2 {
 	watchdog-timers = <&timer4>, <&timer9>;
 };
 
-&ipu1 {
-	status = "okay";
-	memory-region = <&ipu1_cma_pool>;
-	mboxes = <&mailbox5 &mbox_ipu1_ipc3x>;
-	timers = <&timer11>;
-	watchdog-timers = <&timer7>, <&timer8>;
-};
-
-&dsp1 {
-	status = "okay";
-	memory-region = <&dsp1_cma_pool>;
-	mboxes = <&mailbox5 &mbox_dsp1_ipc3x>;
-	timers = <&timer5>;
-	watchdog-timers = <&timer10>;
-};
-
 &dsp2 {
 	status = "okay";
 	memory-region = <&dsp2_cma_pool>;
@@ -1431,35 +865,6 @@ i2c_p3_exp: &i2c2 {
 
 	vdda_video-supply = <&ldoln_reg>;
 
-	ports {
-		#address-cells = <1>;
-		#size-cells = <0>;
-		status = "disabled";
-
-		port@lcd3 {
-			reg = <2>;
-
-			dpi_out3: endpoint {
-				remote-endpoint = <&fpd_in>;
-				data-lines = <24>;
-			};
-		};
-	};
-};
-
-&bb2d {
-	status = "okay";
-};
-
-&hdmi {
-	status = "ok";
-	vdda-supply = <&ldo3_reg>;
-
-	port {
-		hdmi_out: endpoint {
-			remote-endpoint = <&tpd12s015_in>;
-		};
-	};
 };
 
 &vip1 {
diff --git a/arch/arm/boot/dts/dra7x-evm-lcd-lg.dtsi b/arch/arm/boot/dts/dra7x-evm-lcd-lg.dtsi
index 97939eef7b94..e254dccd13a3 100644
--- a/arch/arm/boot/dts/dra7x-evm-lcd-lg.dtsi
+++ b/arch/arm/boot/dts/dra7x-evm-lcd-lg.dtsi
@@ -11,8 +11,6 @@
 / {
 	aliases {
 		display0 = &tlc59108;
-		display1 = &hdmi0;
-		display2 = &fpd_disp;
 	};
 
 	backlight {
diff --git a/arch/arm/boot/dts/dra7x-evm-lcd-osd.dtsi b/arch/arm/boot/dts/dra7x-evm-lcd-osd.dtsi
index 219e4f953797..66c3e3ec03aa 100644
--- a/arch/arm/boot/dts/dra7x-evm-lcd-osd.dtsi
+++ b/arch/arm/boot/dts/dra7x-evm-lcd-osd.dtsi
@@ -9,8 +9,6 @@
 / {
 	aliases {
 		display0 = &lcd;
-		display1 = &hdmi0;
-		display2 = &fpd_disp;
 	};
 
 	lcd_bl: backlight {