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authorCatalin Marinas <catalin.marinas@arm.com>2012-02-14 12:09:08 +0000
committerJon Medhurst <tixy@linaro.org>2012-05-21 12:51:22 +0100
commitffb66d370de41ad36b249cd9621f58d3a27ecf21 (patch)
tree9d66051db27e21ba566bda6de6b081efffeaca64 /crypto
parent35d5dcd371217884374a2be9af99b659f9366479 (diff)
downloadlinux-topics-tracking-previous-armlt-arm-arch-fixes-llt-20121206.0.tar.gz
Clearing bit 22 in the PL310 Auxiliary Control register (shared attribute override enable) has the side effect of transforming Normal Shared Non-cacheable reads into Cacheable no-allocate reads. Coherent DMA buffers in Linux always have a Cacheable alias via the kernel linear mapping and the processor can speculatively load cache lines into the PL310 controller. With bit 22 cleared, Non-cacheable reads would unexpectedly hit such cache lines leading to buffer corruption. This patch ensures that bit 22 is set in the l2x0_init() function if PL310 and not rely on the platform code to specify it. It also modifies the 'aux' variable only if the actual register is written so that the final printk displays the real hardware value. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Tested-by: Kyungmin Park <kyungmin.park@samsung.com>
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