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| author | Ritesh Kumar <riteshk@qti.qualcomm.com> | 2019-09-30 15:03:45 +0530 |
|---|---|---|
| committer | Ritesh Kumar <riteshk@qti.qualcomm.com> | 2019-09-30 15:03:45 +0530 |
| commit | 1c47775c38ef9d1845b5d07daac49cb4f539f009 (patch) | |
| tree | 33dbc3c11fe5a81973bf6b6093e7e42773120a0c | |
| parent | fa0c026d461ec0ec320d1c591ff25c55898ec92a (diff) | |
| download | devicetree-1c47775c38ef9d1845b5d07daac49cb4f539f009.tar.gz | |
ARM: dts: msm: remove MDSS GDSC vote from dsi pll driver for lito
Remove MDSS GDSC vote from DSI PLL as it is hardware controlled and
vote is not needed anymore. GDSC vote was adding unnecessary
delays in locking new clockrates during resolution switch
scenarios causing frame drops.
Change-Id: Ice99928d83efd1662b412a040334fa29c58c9e1c
| -rw-r--r-- | qcom/lito-sde-pll.dtsi | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/qcom/lito-sde-pll.dtsi b/qcom/lito-sde-pll.dtsi index bd2e25d7..11e5635c 100644 --- a/qcom/lito-sde-pll.dtsi +++ b/qcom/lito-sde-pll.dtsi @@ -14,7 +14,6 @@ clock-names = "iface_clk"; clock-rate = <0>; memory-region = <&dfps_data_memory>; - gdsc-supply = <&mdss_core_gdsc>; qcom,dsi-pll-ssc-en; qcom,dsi-pll-ssc-mode = "down-spread"; qcom,platform-supply-entries { @@ -45,7 +44,6 @@ clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>; clock-names = "iface_clk"; clock-rate = <0>; - gdsc-supply = <&mdss_core_gdsc>; qcom,dsi-pll-ssc-en; qcom,dsi-pll-ssc-mode = "down-spread"; qcom,platform-supply-entries { |