diff options
| author | Ritesh Kumar <riteshk@qti.qualcomm.com> | 2020-04-02 16:48:52 +0800 |
|---|---|---|
| committer | Chris Lu <luchris@google.com> | 2020-04-15 11:30:51 +0800 |
| commit | d3d3c69ce053f6d140a0f1559e878ad1d8eceb51 (patch) | |
| tree | 09a47c6d1e7113e7ccb8529d349145c8e9dfa381 | |
| parent | 783de67d0277f9c2a1b22390d62881a6657a9065 (diff) | |
| download | devicetree-d3d3c69ce053f6d140a0f1559e878ad1d8eceb51.tar.gz | |
ARM: dts: msm: remove supply entry node for DSI PLL on lito
No separate supplies are required for enabling DSI PLL as
it is enabled with GDSC which is hardware controlled. This
change removes the unnecessary supply entry node on lito target.
Bug: 151276793
Test: RSS test
Change-Id: I3c5712bdb7048550af0d27424c45870c06fa67cc
Signed-off-by: Chris Lu <luchris@google.com>
| -rw-r--r-- | qcom/lito-sde-pll.dtsi | 24 |
1 files changed, 0 insertions, 24 deletions
diff --git a/qcom/lito-sde-pll.dtsi b/qcom/lito-sde-pll.dtsi index 9aa770cf..7bdedf7b 100644 --- a/qcom/lito-sde-pll.dtsi +++ b/qcom/lito-sde-pll.dtsi @@ -17,18 +17,6 @@ qcom,dsi-pll-ssc-en; qcom,dsi-pll-ssc-mode = "down-spread"; qcom,msm-bus,name = "dsi_pll_7nm_v4_1_0"; - qcom,platform-supply-entries { - #address-cells = <1>; - #size-cells = <0>; - qcom,platform-supply-entry@0 { - reg = <0>; - qcom,supply-name = "gdsc"; - qcom,supply-min-voltage = <0>; - qcom,supply-max-voltage = <0>; - qcom,supply-enable-load = <0>; - qcom,supply-disable-load = <0>; - }; - }; }; mdss_dsi1_pll: qcom,mdss_dsi1_pll { @@ -48,18 +36,6 @@ qcom,dsi-pll-ssc-en; qcom,dsi-pll-ssc-mode = "down-spread"; qcom,msm-bus,name = "dsi_pll_7nm_v4_1_1"; - qcom,platform-supply-entries { - #address-cells = <1>; - #size-cells = <0>; - qcom,platform-supply-entry@0 { - reg = <0>; - qcom,supply-name = "gdsc"; - qcom,supply-min-voltage = <0>; - qcom,supply-max-voltage = <0>; - qcom,supply-enable-load = <0>; - qcom,supply-disable-load = <0>; - }; - }; }; mdss_dp_pll: qcom,mdss_dp_pll@c011000 { compatible = "qcom,mdss_dp_pll_7nm_v2"; |