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-rw-r--r--bindings/bt-fm/fm.txt29
-rw-r--r--bindings/clock/qcom,clock-cpu-8939.txt79
-rw-r--r--bindings/clock/qcom,gcc.txt4
-rw-r--r--bindings/clock/qcom,rpmcc.txt3
-rw-r--r--bindings/clock/qcom,sdm-cpucc.txt96
-rw-r--r--bindings/cnss/wcnss-wlan.txt110
-rw-r--r--bindings/iio/adc/qcom-rradc.txt4
-rw-r--r--bindings/media/video/msm-vidc.txt1
-rw-r--r--bindings/mfd/qcom-pm8xxx.txt1
-rw-r--r--bindings/misc/qcom,qrc.txt13
-rw-r--r--bindings/regulator/gdsc-regulator.txt2
-rw-r--r--bindings/thermal/qcom-thermal-efprom.txt73
-rw-r--r--bindings/wcnss/wcnss-wlan.txt110
13 files changed, 441 insertions, 84 deletions
diff --git a/bindings/bt-fm/fm.txt b/bindings/bt-fm/fm.txt
new file mode 100644
index 00000000..ed73e5d2
--- /dev/null
+++ b/bindings/bt-fm/fm.txt
@@ -0,0 +1,29 @@
+Qti radio iris device
+
+-FM RX playback with no RDS
+
+ FM samples is filtered by external RF chips at baseband, then send to Riva-FM core through serial link.
+ FM signal is demodulated then audio L/R samples are stored inside memory.
+ FM Rx received samples data is connected to external audio codec.
+
+-Audio playback to FM TX
+
+ Used to play audio source to FM TX.
+ FM TX module will read the audio samples from memory then modulated samples will be send through serial interface to external RF chip.
+
+-RX playback with RDS
+
+ FM Rx receive audio data along with RDS.
+
+-FM TX with RDS
+
+ Used to send RDS messages to external FM receiver.
+
+Required Properties:
+- compatible: "qcom,iris_fm"
+
+Example:
+ qcom,iris-fm {
+ compatible = "qcom,iris_fm";
+ };
+
diff --git a/bindings/clock/qcom,clock-cpu-8939.txt b/bindings/clock/qcom,clock-cpu-8939.txt
deleted file mode 100644
index e2190df5..00000000
--- a/bindings/clock/qcom,clock-cpu-8939.txt
+++ /dev/null
@@ -1,79 +0,0 @@
-Qualcomm Technologies, Inc. MSM8939 CPU clock tree
-
-clock-cpu-8939 is a device that represents the MSM8939 or MSM8952 CPU
-subsystem clock tree. It lists the various power supplies that need to be
-scaled when the clocks are scaled and also other HW specific parameters like
-fmax tables, avs settings table, etc.
-
-Required properties:
-- compatible: Must be one of "qcom,clock-cpu-8939" or
- "qcom,cpu-clock-8952", "qcom,cpu-clock-8917",
- "qcom,cpu-clock-sdm439", "qcom,cpu-clock-sdm429".
-- reg: Pairs of physical base addresses and region sizes of
- memory mapped registers.
-- reg-names: Names of the bases for the above registers. Expected
- bases are:
- "apcs-c0-rcg-base", "apcs-c1-rcg-base",
- "apcs-cci-rcg-base", "efuse", "efuse1", "efuse2"
-- vdd-c0-supply: The regulator powering the little cluster
-- vdd-c1-supply: The regulator powering the big cluster
-- vdd-cci-supply: The regulator powering the CCI cluster
-- qcom,speedX-bin-vY-ZZZ:
- A table of CPU frequency (Hz) to voltage (corner)
- mapping that represents the max frequency possible
- for each supported voltage level for a CPU. 'X' is
- the speed bin into which the device falls into - a
- bin will have unique frequency-voltage relationships.
- 'Y' is the characterization version, implying that
- characterization (deciding what speed bin a device
- falls into) methods and/or encoding may change. The
- values 'X' and 'Y' are read from efuse registers, and
- the right table is picked from multiple possible tables.
- 'ZZZ' can be c1, c0 or cci depending on whether the table
- is for the big cluster, little cluster or cci.
-Optional properties:
-- qcom,cpu-pcnoc-vote: Boolean to indicate cpu clocks would need to keep
- active pcnoc vote.
-- qcom,num-cluster: Boolean to indicate cpu clock code is used for single
- cluster.
-Example:
- clock_cpu: qcom,cpu-clock-8939@f9015000 {
- compatible = "qcom,cpu-clock-8939";
- reg = <0xf9015000 0x1000>,
- <0xf9016000 0x1000>,
- <0xf9011000 0x1000>,
- <0xf900d000 0x1000>,
- <0xf900f000 0x1000>,
- <0xf9112000 0x1000>;
- reg-names = "apcs-c0-rcg-base", "apcs-c1-rcg-base",
- "apcs-cci-rcg-base", "efuse", "efuse1",
- "efuse2";
- vdd-c0-supply = <&apc_vreg_corner>;
- vdd-c1-supply = <&apc_vreg_corner>;
- vdd-cci-supply = <&apc_vreg_corner>;
- qcom,speed0-bin-v0-c0 =
- < 0 0>,
- < 384000000 1>,
- < 787200000 2>,
- <1286400000 3>;
- qcom,speed0-bin-v0-c1 =
- < 0 0>,
- < 384000000 1>,
- < 787200000 2>,
- <1785600000 3>;
- qcom,speed0-bin-v0-cci =
- < 0 0>,
- < 150000000 1>,
- < 300000000 2>,
- < 600000000 3>;
- clocks = <&clock_gcc clk_gpll0_ao>,
- <&clock_gcc clk_a53ss_c0_pll>,
- <&clock_gcc clk_gpll0_ao>,
- <&clock_gcc clk_a53ss_c1_pll>,
- <&clock_gcc clk_gpll0_ao>,
- <&clock_gcc clk_a53ss_cci_pll>;
- clock-names = "clk-c0-4", "clk-c0-5",
- "clk-c1-4", "clk-c1-5",
- "clk-cci-4", "clk-cci-5";
- #clock-cells = <1>;
-};
diff --git a/bindings/clock/qcom,gcc.txt b/bindings/clock/qcom,gcc.txt
index 179f56cb..2f066cd5 100644
--- a/bindings/clock/qcom,gcc.txt
+++ b/bindings/clock/qcom,gcc.txt
@@ -32,11 +32,9 @@ Required properties :
"qcom,gcc-msm8937"
"qcom,gcc-sdm429w"
"qcom,gcc-mdss-msm8937"
- "qcom,gcc-mdss-8917"
+ "qcom,gcc-mdss-qm215"
"qcom,gcc-mdss-sdm429w"
- "qcom,gcc-mdss-sdm429"
"qcom,gcc-mdss-sdm439"
- "qcom,gcc-mdss-sdm429w"
- reg : shall contain base register location and length
- #clock-cells : shall contain 1
diff --git a/bindings/clock/qcom,rpmcc.txt b/bindings/clock/qcom,rpmcc.txt
index 4a3152d9..2c167462 100644
--- a/bindings/clock/qcom,rpmcc.txt
+++ b/bindings/clock/qcom,rpmcc.txt
@@ -18,8 +18,7 @@ Required properties :
"qcom,rpmcc-msm8996", "qcom,rpmcc"
"qcom,rpmcc-bengal", "qcom,rpmcc"
"qcom,rpmcc-sdm660", "qcom,rpmcc"
- "qcom,rpmcc-msm8937", "qcom,rpmcc"
- "qcom,rpmcc-msm8917", "qcom,rpmcc"
+ "qcom,rpmcc-sdm439", "qcom,rpmcc"
"qcom,rpmcc-qm215", "qcom,rpmcc"
- #clock-cells : shall contain 1
diff --git a/bindings/clock/qcom,sdm-cpucc.txt b/bindings/clock/qcom,sdm-cpucc.txt
new file mode 100644
index 00000000..4b6d9101
--- /dev/null
+++ b/bindings/clock/qcom,sdm-cpucc.txt
@@ -0,0 +1,96 @@
+Qualcomm Technologies, Inc. SDM CPU clock driver
+---------------------------------------------------
+
+It is the clock controller driver which provides higher frequency
+clocks and allows CPU frequency scaling on sdm based platforms.
+
+Required properties:
+- compatible: Shall contain following:
+ "qcom,cpu-clock-sdm", "qcom,cpu-clock-qm215",
+ "qcom,cpu-clock-sdm439", "qcom,cpu-clock-sdm429"
+- clocks: Phandle to the clock device.
+- clock-names: Names of the used clocks. Shall contain following:
+ "xo_ao", "gpll0_ao"
+- reg: Shall contain base register offset and size.
+- reg-names: Names of the bases for the above registers. Shall contain following:
+ "apcs-c1-rcg-base", "apcs-cci-rcg-base", "apcs_pll", "efuse"
+- vdd_dig_ao-supply: The regulator(active only) powering the digital logic of APSS PLL.
+- vdd_hf_pll-supply: The regulator(active only) powering the Analog logic of APSS PLL.
+- cpu-vdd-supply: The regulator powering the APSS C1 RCG and APSS CCI RCG.
+- qcom,speedX-bin-vY-Z: A table of CPU frequency (Hz) to regulator voltage (uV) mapping.
+ Format: <freq uV>
+ This represents the max frequency possible for each possible
+ power configuration for a CPU that's binned as speed bin X,
+ speed bin revision Y. Version can be between [0-3]. Z
+ is the mux id c1 or cci.
+- #clock-cells: Shall contain 1.
+
+Example:
+ clock_cpu: qcom,clock-cpu@0b011050 {
+ compatible = "qcom,cpu-clock-sdm";
+ clocks = <&rpmcc RPM_SMD_XO_A_CLK_SRC>,
+ <&gcc GPLL0_AO_OUT_MAIN>;
+ clock-names = "xo_ao", "gpll0_ao" ;
+ reg = <0xb011050 0x8>,
+ <0xb1d1050 0x8>,
+ <0xb016000 0x34>,
+ <0x00a412c 0x8>;
+ reg-names = "apcs-c1-rcg-base",
+ "apcs-cci-rcg-base", "apcs_pll", "efuse";
+ cpu-vdd-supply = <&apc_vreg_corner>;
+ vdd_dig_ao-supply = <&L12A_AO;
+ vdd_hf_pll-supply = <&VDD_CX_LEVEL_AO>;
+ qcom,speed0-bin-v0-c1 =
+ < 0 0>,
+ < 960000000 1>,
+ < 1305600000 1>,
+ < 1497600000 2>,
+ < 1708800000 3>,
+ < 1958400000 5>;
+
+ qcom,speed0-bin-v0-cci =
+ < 0 0>,
+ < 400000000 1>,
+ < 533333333 3>;
+
+ qcom,speed1-bin-v0-c1 =
+ < 0 0>,
+ < 960000000 1>,
+ < 1305600000 1>,
+ < 1497600000 2>,
+ < 1708800000 3>,
+ < 1804800000 5>;
+
+ qcom,speed1-bin-v0-cci =
+ < 0 0>,
+ < 400000000 1>,
+ < 533333333 3>;
+
+ qcom,speed4-bin-v0-c1 =
+ < 0 0>,
+ < 960000000 1>,
+ < 1305600000 1>,
+ < 1497600000 2>,
+ < 1708800000 3>,
+ < 1958400000 5>,
+ < 2016000000 6>;
+
+ qcom,speed4-bin-v0-cci =
+ < 0 0>,
+ < 400000000 1>,
+ < 533333333 3>;
+
+ qcom,speed5-bin-v0-c1 =
+ < 0 0>,
+ < 960000000 1>,
+ < 1305600000 1>,
+ < 1497600000 2>,
+ < 1708800000 3>;
+
+ qcom,speed5-bin-v0-cci =
+ < 0 0>,
+ < 400000000 1>,
+ < 533333333 3>;
+
+ #clock-cells = <1>;
+ };
diff --git a/bindings/cnss/wcnss-wlan.txt b/bindings/cnss/wcnss-wlan.txt
new file mode 100644
index 00000000..fbe1bcad
--- /dev/null
+++ b/bindings/cnss/wcnss-wlan.txt
@@ -0,0 +1,110 @@
+* Qualcomm Technologies Inc. WCNSS Platform Driver
+
+WCNSS driver is the platform driver. It is used for performing the cold
+boot-up of the wireless device. It is responsible for adjusting
+the necessary I/O rails and enabling appropriate gpios for wireless
+connectivity subsystem.
+
+Required properties:
+- compatible: "wcnss_wlan"
+- reg: physical address and length of the register set for the device.
+- reg-names: "wcnss_mmio", "wcnss_fiq", "pronto_phy_base", "riva_phy_base",
+ "riva_ccu_base", "pronto_a2xb_base", "pronto_ccpu_base",
+ "pronto_saw2_base", "wlan_tx_phy_aborts","wlan_brdg_err_source",
+ "wlan_tx_status", "alarms_txctl", "alarms_tactl",
+ "pronto_mcu_base", "pronto_qfuse".
+- interupts: Pronto to Apps interrupts for tx done and rx pending.
+- qcom,pronto-vddmx-supply: regulator to supply pronto pll.
+- qcom,pronto-vddcx-supply: voltage corner regulator to supply WLAN/BT/FM
+digital module.
+- qcom,pronto-vddpx-supply: regulator to supply WLAN DAC.
+- qcom,iris-vddxo-supply : regulator to supply RF XO.
+- qcom,iris-vddrfa-supply : regulator to supply RFA digital.
+- qcom,iris-vddpa-supply : regulator to supply RF PA.
+- qcom,iris-vdddig-supply : regulator to supply RF digital(BT/FM).
+- gpios: gpio numbers to configure 5-wire interface of WLAN connectivity
+- qcom,has-48mhz-xo: boolean flag to determine the usage of 24MHz XO from RF
+- qcom,has-pronto-hw: boolean flag to determine the revId of the WLAN subsystem
+- qcom,wcnss-adc_tm: ADC handle for vbatt notification APIs.
+- qcom,wcnss-vadc: VADC handle for battery voltage notification APIs.
+- pinctrl-<n> : Pinctrl states as described in bindings/pinctrl/pinctrl-bindings.txt
+- pinctrl-names : Names corresponding to the numbered pinctrl states
+- clocks: from common clock binding: handle to xo, rf_clk and wcnss snoc clocks.
+- clock-names: Names of all the clocks that are accessed by the subsystem
+- qcom,vdd-voltage-level: This property represents (nominal, min, max) voltage
+for iris and pronto regulators in milli-volts.
+- qcom,vdd-current: This property represents current value for
+iris and pronto regulators in micro-amps.
+
+Optional properties:
+- qcom,has-autodetect-xo: boolean flag to determine whether Iris XO auto detect
+should be performed during boot up.
+- qcom,snoc-wcnss-clock-freq: indicates the wcnss snoc clock frequency in Hz.
+If wcnss_snoc clock is specified in the list of clocks, this property needs
+to be set to make it functional.
+- qcom,wlan-rx-buff-count: WLAN RX buffer count is a configurable value,
+using a smaller count for this buffer will reduce the memory usage.
+- qcom,is-pronto-v3: boolean flag to determine the pronto hardware version
+in use. subsequently correct workqueue will be used by DXE engine to push frames
+in TX data path.
+- qcom,is-dual-band-disable: boolean flag to determine the WLAN dual band
+capability.
+- qcom,is-pronto-vadc: boolean flag to determine Battery voltage feature
+support for pronto hardware.
+- qcom,wcnss-pm : <Core rail LDO#, PA rail LDO#, XO settling time,
+RPM power collapse enabled, standalone power collapse enabled>
+Power manager related parameter for LDO configuration.
+ 11 - WCN CORE rail LDO number
+ 21 - WCN PA rail LDO number
+ 1200 - WCN XO settling time (usec)
+ 1 - WCN RPM power collapse enabled
+ 1 - WCN standalone power collapse enabled
+ 6 - GPIO strength value
+- qcom,has-vsys-adc-channel: boolean flag to determine which ADC HW channel need
+to use for VBATT feature.
+- qcom,has-a2xb-split-reg: boolean flag to determine A2xb split timeout limit
+register is available or not.
+
+Example:
+
+qcom,wcnss-wlan@fb000000 {
+ compatible = "qcom,wcnss_wlan";
+ reg = <0xfb000000 0x280000>,
+ <0xf9011008 0x04>;
+reg-names = "wcnss_mmio", "wcnss_fiq";
+ interrupts = <0 145 0 0 146 0>;
+ interrupt-names = "wcnss_wlantx_irq", "wcnss_wlanrx_irq";
+
+ qcom,pronto-vddmx-supply = <&pm8841_s1>;
+ qcom,pronto-vddcx-supply = <&pm8841_s2_corner>;
+ qcom,pronto-vddpx-supply = <&pm8941_s3>;
+ qcom,iris-vddxo-supply = <&pm8941_l6>;
+ qcom,iris-vddrfa-supply = <&pm8941_l11>;
+ qcom,iris-vddpa-supply = <&pm8941_l19>;
+ qcom,iris-vdddig-supply = <&pm8941_l3>;
+
+ gpios = <&msmgpio 36 0>, <&msmgpio 37 0>, <&msmgpio 38 0>,
+ <&msmgpio 39 0>, <&msmgpio 40 0>;
+ qcom,has-48mhz-xo;
+ qcom,is-pronto-vt;
+ qcom,wlan-rx-buff-count = <512>;
+ qcom,has-pronto-hw;
+ qcom,wcnss-adc_tm = <&pm8226_adc_tm>;
+
+ pinctrl-names = "wcnss_default", "wcnss_sleep";
+ pinctrl-0 = <&wcnss_default>;
+ pinctrl-1 = <&wcnss_sleep>;
+ pinctrl-2 = <&wcnss_gpio_default>;
+
+ clocks = <&clock_rpm clk_xo_wlan_clk>,
+ <&clock_rpm clk_rf_clk2>,
+ <&clock_debug clk_gcc_debug_mux>,
+ <&clock_gcc clk_wcnss_m_clk>,
+ <&clock_gcc clk_snoc_wcnss_a_clk>;
+
+ clock-names = "xo", "rf_clk", "measure", "wcnss_debug",
+ "snoc_wcnss";
+
+ qcom,snoc-wcnss-clock-freq = <200000000>;
+ qcom,wcnss-pm = <11 21 1200 1 1 6>;
+};
diff --git a/bindings/iio/adc/qcom-rradc.txt b/bindings/iio/adc/qcom-rradc.txt
index 1ab49edf..f21aa901 100644
--- a/bindings/iio/adc/qcom-rradc.txt
+++ b/bindings/iio/adc/qcom-rradc.txt
@@ -45,6 +45,10 @@ Optional property:
- qcom,pmic-revid : Phandle pointing to the revision peripheral node. Use it to query the
PMIC fabrication ID for applying the appropriate temperature
compensation parameters.
+
+- qcom,rradc-fg-reset-wa : With this property enabled, RRADC can register for a power supply
+ notifier and reset FG through a power supply property if it gets stuck.
+
Example:
/* RRADC node */
diff --git a/bindings/media/video/msm-vidc.txt b/bindings/media/video/msm-vidc.txt
index 264725fb..793a1a61 100644
--- a/bindings/media/video/msm-vidc.txt
+++ b/bindings/media/video/msm-vidc.txt
@@ -11,6 +11,7 @@ Required properties:
- "qcom,bengal-vidc" : Invokes driver specific data for BENGAL.
- "qcom,lagoon-vidc" : Invokes driver specific data for LAGOON.
- "qcom,scuba-vidc" : Invokes driver specific data for SCUBA.
+ - "qcom,qcs8250-vidc" : Invokes driver specific data for KONA.
Optional properties:
- reg : offset and length of the register set for the device.
- sku-index : sku version of the hardware.
diff --git a/bindings/mfd/qcom-pm8xxx.txt b/bindings/mfd/qcom-pm8xxx.txt
index 07f49254..3d3d628d 100644
--- a/bindings/mfd/qcom-pm8xxx.txt
+++ b/bindings/mfd/qcom-pm8xxx.txt
@@ -65,6 +65,7 @@ The below bindings specify the set of valid subnodes.
"qcom,pm8941-rtc"
"qcom,pm8018-rtc"
"qcom,pmk8350-rtc"
+ "qcom,pm8916-rtc"
- reg:
Usage: required
diff --git a/bindings/misc/qcom,qrc.txt b/bindings/misc/qcom,qrc.txt
new file mode 100644
index 00000000..61980793
--- /dev/null
+++ b/bindings/misc/qcom,qrc.txt
@@ -0,0 +1,13 @@
+Qualcomm Technologies, Inc. qrc driver
+
+Driver for QTI robotic controller.
+
+Required properties:
+
+compatible = "qcom,qrc-uart";
+
+Example:
+
+qrc: qcom,qrc_uart {
+ compatible = "qcom,qrc-uart";
+};
diff --git a/bindings/regulator/gdsc-regulator.txt b/bindings/regulator/gdsc-regulator.txt
index 4f31737f..bb45a065 100644
--- a/bindings/regulator/gdsc-regulator.txt
+++ b/bindings/regulator/gdsc-regulator.txt
@@ -76,6 +76,8 @@ Optional properties:
- qcom,skip-disable-before-sw-enable : Presence denotes a hardware requirement
to leave the GDSC on that has been
enabled by an entity external to HLOS.
+ - qcom,no-config-gdscr: Presence denotes HW only supports a single register
+ per GDSC.
[1]: Documentation/devicetree/bindings/arm/msm/msm_bus.txt
diff --git a/bindings/thermal/qcom-thermal-efprom.txt b/bindings/thermal/qcom-thermal-efprom.txt
new file mode 100644
index 00000000..d9e50103
--- /dev/null
+++ b/bindings/thermal/qcom-thermal-efprom.txt
@@ -0,0 +1,73 @@
+Modify Thermal Zone based on efuse data
+
+This driver is to enable/disable pre-configured thermal
+zones selectively at runtime based on efuse data. It uses QFPROM
+nvmem cell interface to read efuse data. It supports multiple
+efuse condition. If any of the efuse condition fails, driver just
+exits with default enabled thermal zones.
+
+Properties:
+
+- compatible:
+ Usage: Required
+ Value type: <string>
+ Definition: shall be "qcom,thermal-qfprom-device".
+
+- nvmem-cells:
+ Usage: Required
+ Value type: <array of phandle>
+ Definition: Array of phandles pointing to a nvmem-cells node
+ representing the efuse registers that has information that
+ is used to select the right thermal zone to enable.
+ Please refer nvmem-cells bindings
+ Documentation/devicetree/bindings/nvmem/nvmem.txt and also
+ example below.
+
+ nvmem-cell-names:
+ Usage: Required
+ Value type: <array of string>
+ Definition: Should be array of name for each nvmem-cells phandle data.
+ Please refer nvmem-cells bindings
+ Documentation/devicetree/bindings/nvmem/nvmem.txt and also
+ example below.
+
+- qcom,thermal-qfprom-bit-values: It should be array of bit mask values to
+ match with each nvmem-cells bit value respectively. If all
+ nvmem-cells values are matching with respective bit mask value
+ from this property, then driver will update thermal zones as
+ per thermal zones mentioned in 'qcom,thermal-zone-enable-list'
+ and 'qcom,thermal-zone-disable-list'.
+
+- qcom,thermal-zone-enable-list:
+ Usage: Required
+ Value type: <array of strings>
+ Definition: Should define this property with list of thermal zone
+ names those need to be enabled if nvmem-cells condition is met.
+
+- qcom,thermal-zone-disable-list:
+ Usage: Required
+ Value type: <array of strings>
+ Definition: Should define this property with list of thermal zone
+ names those need to be disabled if nvmem-cells condition is met.
+
+Example:
+ qcom-thermal-qfprom {
+ compatible = "qcom,thermal-qfprom-device";
+ nvmem-cells = <&thermal_cpe>, <&thermal_revision>;
+ nvmem-cell-names = "cpe", "revision";
+ qcom,thermal-qfprom-bit-values = <0x1 0x3>
+ qcom,thermal-zone-enable-list = "mdm-core-0-cpe-step",
+ "mdm-core-1-cpe-step";
+ qcom,thermal-zone-disable-list = "mdm-core-0-step",
+ "mdm-core-1-step";
+ };
+
+ In this example, driver gets efuse bit values of nvmem-cell register
+ for both 'cpe' and 'revision' nvmem cells. It then compares these efuse
+ values with property 'qcom,thermal-qfprom-bit-values' values (0x1 and
+ 0x3 here) respectively. If both efuse values are matching with this
+ property values, driver enables thermal zones listed in property
+ 'qcom,thermal-zone-enable-list' and disables thermal zones listed in
+ property 'qcom,thermal-zone-disable-list'. If any of the efuse
+ value is not matching with respective 'qcom,thermal-qfprom-bit-values'
+ values, driver just exits without modifying any thermal zone.
diff --git a/bindings/wcnss/wcnss-wlan.txt b/bindings/wcnss/wcnss-wlan.txt
new file mode 100644
index 00000000..fbe1bcad
--- /dev/null
+++ b/bindings/wcnss/wcnss-wlan.txt
@@ -0,0 +1,110 @@
+* Qualcomm Technologies Inc. WCNSS Platform Driver
+
+WCNSS driver is the platform driver. It is used for performing the cold
+boot-up of the wireless device. It is responsible for adjusting
+the necessary I/O rails and enabling appropriate gpios for wireless
+connectivity subsystem.
+
+Required properties:
+- compatible: "wcnss_wlan"
+- reg: physical address and length of the register set for the device.
+- reg-names: "wcnss_mmio", "wcnss_fiq", "pronto_phy_base", "riva_phy_base",
+ "riva_ccu_base", "pronto_a2xb_base", "pronto_ccpu_base",
+ "pronto_saw2_base", "wlan_tx_phy_aborts","wlan_brdg_err_source",
+ "wlan_tx_status", "alarms_txctl", "alarms_tactl",
+ "pronto_mcu_base", "pronto_qfuse".
+- interupts: Pronto to Apps interrupts for tx done and rx pending.
+- qcom,pronto-vddmx-supply: regulator to supply pronto pll.
+- qcom,pronto-vddcx-supply: voltage corner regulator to supply WLAN/BT/FM
+digital module.
+- qcom,pronto-vddpx-supply: regulator to supply WLAN DAC.
+- qcom,iris-vddxo-supply : regulator to supply RF XO.
+- qcom,iris-vddrfa-supply : regulator to supply RFA digital.
+- qcom,iris-vddpa-supply : regulator to supply RF PA.
+- qcom,iris-vdddig-supply : regulator to supply RF digital(BT/FM).
+- gpios: gpio numbers to configure 5-wire interface of WLAN connectivity
+- qcom,has-48mhz-xo: boolean flag to determine the usage of 24MHz XO from RF
+- qcom,has-pronto-hw: boolean flag to determine the revId of the WLAN subsystem
+- qcom,wcnss-adc_tm: ADC handle for vbatt notification APIs.
+- qcom,wcnss-vadc: VADC handle for battery voltage notification APIs.
+- pinctrl-<n> : Pinctrl states as described in bindings/pinctrl/pinctrl-bindings.txt
+- pinctrl-names : Names corresponding to the numbered pinctrl states
+- clocks: from common clock binding: handle to xo, rf_clk and wcnss snoc clocks.
+- clock-names: Names of all the clocks that are accessed by the subsystem
+- qcom,vdd-voltage-level: This property represents (nominal, min, max) voltage
+for iris and pronto regulators in milli-volts.
+- qcom,vdd-current: This property represents current value for
+iris and pronto regulators in micro-amps.
+
+Optional properties:
+- qcom,has-autodetect-xo: boolean flag to determine whether Iris XO auto detect
+should be performed during boot up.
+- qcom,snoc-wcnss-clock-freq: indicates the wcnss snoc clock frequency in Hz.
+If wcnss_snoc clock is specified in the list of clocks, this property needs
+to be set to make it functional.
+- qcom,wlan-rx-buff-count: WLAN RX buffer count is a configurable value,
+using a smaller count for this buffer will reduce the memory usage.
+- qcom,is-pronto-v3: boolean flag to determine the pronto hardware version
+in use. subsequently correct workqueue will be used by DXE engine to push frames
+in TX data path.
+- qcom,is-dual-band-disable: boolean flag to determine the WLAN dual band
+capability.
+- qcom,is-pronto-vadc: boolean flag to determine Battery voltage feature
+support for pronto hardware.
+- qcom,wcnss-pm : <Core rail LDO#, PA rail LDO#, XO settling time,
+RPM power collapse enabled, standalone power collapse enabled>
+Power manager related parameter for LDO configuration.
+ 11 - WCN CORE rail LDO number
+ 21 - WCN PA rail LDO number
+ 1200 - WCN XO settling time (usec)
+ 1 - WCN RPM power collapse enabled
+ 1 - WCN standalone power collapse enabled
+ 6 - GPIO strength value
+- qcom,has-vsys-adc-channel: boolean flag to determine which ADC HW channel need
+to use for VBATT feature.
+- qcom,has-a2xb-split-reg: boolean flag to determine A2xb split timeout limit
+register is available or not.
+
+Example:
+
+qcom,wcnss-wlan@fb000000 {
+ compatible = "qcom,wcnss_wlan";
+ reg = <0xfb000000 0x280000>,
+ <0xf9011008 0x04>;
+reg-names = "wcnss_mmio", "wcnss_fiq";
+ interrupts = <0 145 0 0 146 0>;
+ interrupt-names = "wcnss_wlantx_irq", "wcnss_wlanrx_irq";
+
+ qcom,pronto-vddmx-supply = <&pm8841_s1>;
+ qcom,pronto-vddcx-supply = <&pm8841_s2_corner>;
+ qcom,pronto-vddpx-supply = <&pm8941_s3>;
+ qcom,iris-vddxo-supply = <&pm8941_l6>;
+ qcom,iris-vddrfa-supply = <&pm8941_l11>;
+ qcom,iris-vddpa-supply = <&pm8941_l19>;
+ qcom,iris-vdddig-supply = <&pm8941_l3>;
+
+ gpios = <&msmgpio 36 0>, <&msmgpio 37 0>, <&msmgpio 38 0>,
+ <&msmgpio 39 0>, <&msmgpio 40 0>;
+ qcom,has-48mhz-xo;
+ qcom,is-pronto-vt;
+ qcom,wlan-rx-buff-count = <512>;
+ qcom,has-pronto-hw;
+ qcom,wcnss-adc_tm = <&pm8226_adc_tm>;
+
+ pinctrl-names = "wcnss_default", "wcnss_sleep";
+ pinctrl-0 = <&wcnss_default>;
+ pinctrl-1 = <&wcnss_sleep>;
+ pinctrl-2 = <&wcnss_gpio_default>;
+
+ clocks = <&clock_rpm clk_xo_wlan_clk>,
+ <&clock_rpm clk_rf_clk2>,
+ <&clock_debug clk_gcc_debug_mux>,
+ <&clock_gcc clk_wcnss_m_clk>,
+ <&clock_gcc clk_snoc_wcnss_a_clk>;
+
+ clock-names = "xo", "rf_clk", "measure", "wcnss_debug",
+ "snoc_wcnss";
+
+ qcom,snoc-wcnss-clock-freq = <200000000>;
+ qcom,wcnss-pm = <11 21 1200 1 1 6>;
+};
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-02 22:37:56 +0000