1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
|
&soc {
mdss_dsi0_pll: qcom,mdss_dsi0_pll {
compatible = "qcom,mdss_dsi_pll_7nm_v4_1";
label = "MDSS DSI 0 PLL";
cell-index = <0>;
#clock-cells = <1>;
reg = <0xae94900 0x280>,
<0xae94400 0x800>,
<0xaf03000 0x8>,
<0xae94200 0x100>;
reg-names = "pll_base", "phy_base", "gdsc_base",
"dynamic_pll_base";
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>;
clock-names = "iface_clk";
clock-rate = <0>;
memory-region = <&dfps_data_memory>;
qcom,dsi-pll-ssc-en;
qcom,dsi-pll-ssc-mode = "down-spread";
qcom,msm-bus,name = "dsi_pll_7nm_v4_1_0";
};
mdss_dsi1_pll: qcom,mdss_dsi1_pll {
compatible = "qcom,mdss_dsi_pll_7nm_v4_1";
label = "MDSS DSI 1 PLL";
cell-index = <1>;
#clock-cells = <1>;
reg = <0xae96900 0x280>,
<0xae96400 0x800>,
<0xaf03000 0x8>,
<0xae96200 0x100>;
reg-names = "pll_base", "phy_base", "gdsc_base",
"dynamic_pll_base";
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>;
clock-names = "iface_clk";
clock-rate = <0>;
qcom,dsi-pll-ssc-en;
qcom,dsi-pll-ssc-mode = "down-spread";
qcom,msm-bus,name = "dsi_pll_7nm_v4_1_1";
};
mdss_dp_pll: qcom,mdss_dp_pll@c011000 {
compatible = "qcom,mdss_dp_pll_7nm_v2";
label = "MDSS DP PLL";
cell-index = <0>;
#clock-cells = <1>;
reg = <0x088ea000 0x200>,
<0x088eaa00 0x200>,
<0x088ea200 0x200>,
<0x088ea2c0 0x8>,
<0x088ea2c8 0x4>,
<0x088ea600 0x200>,
<0x088ea6c0 0x8>,
<0x088ea6c8 0x4>,
<0xaf03000 0x8>;
reg-names = "pll_base", "phy_base",
"ln_tx0_base", "ln_tx0_tran_base", "ln_tx0_vmode_base",
"ln_tx1_base", "ln_tx1_tran_base", "ln_tx1_vmode_base",
"gdsc_base";
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
<&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_DISP_AHB_CLK>,
<&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
clock-names = "iface_clk", "ref_clk_src",
"gcc_iface", "pipe_clk";
clock-rate = <0>;
qcom,msm-bus,name = "dp_pll_7nm";
};
};
|
