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path: root/drivers/emac-dwc-eqos/DWC_ETH_QOS_mdio.c
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Diffstat (limited to 'drivers/emac-dwc-eqos/DWC_ETH_QOS_mdio.c')
-rw-r--r--drivers/emac-dwc-eqos/DWC_ETH_QOS_mdio.c69
1 files changed, 56 insertions, 13 deletions
diff --git a/drivers/emac-dwc-eqos/DWC_ETH_QOS_mdio.c b/drivers/emac-dwc-eqos/DWC_ETH_QOS_mdio.c
index 75a27ed..57c9383 100644
--- a/drivers/emac-dwc-eqos/DWC_ETH_QOS_mdio.c
+++ b/drivers/emac-dwc-eqos/DWC_ETH_QOS_mdio.c
@@ -295,6 +295,9 @@ static INT DWC_ETH_QOS_mdio_reset(struct mii_bus *bus)
DBGPR_MDIO("-->DWC_ETH_QOS_mdio_reset: phyaddr : %d\n", pdata->phyaddr);
+ if (pdata->res_data->early_eth_en)
+ return 0;
+
#if 0 /* def DWC_ETH_QOS_CONFIG_PGTEST */
pr_alert("PHY Programming for Autoneg disable\n");
hw_if->read_phy_regs(pdata->phyaddr, MII_BMCR, &phydata);
@@ -458,7 +461,7 @@ static void DWC_ETH_QOS_set_phy_hibernation_mode(struct DWC_ETH_QOS_prv_data *pd
uint mode)
{
u32 phydata = 0;
- EMACINFO("Enter\n");
+ EMACDBG("Enter\n");
DWC_ETH_QOS_mdio_write_direct(pdata, pdata->phyaddr,
DWC_ETH_QOS_PHY_DEBUG_PORT_ADDR_OFFSET,
@@ -467,7 +470,7 @@ static void DWC_ETH_QOS_set_phy_hibernation_mode(struct DWC_ETH_QOS_prv_data *pd
DWC_ETH_QOS_PHY_DEBUG_PORT_DATAPORT,
&phydata);
- EMACINFO("value read 0x%x\n", phydata);
+ EMACDBG("value read 0x%x\n", phydata);
phydata = ((phydata & DWC_ETH_QOS_PHY_HIB_CTRL_PS_HIB_EN_WR_MASK)
| ((DWC_ETH_QOS_PHY_HIB_CTRL_PS_HIB_EN_MASK & mode) << 15));
@@ -482,7 +485,7 @@ static void DWC_ETH_QOS_set_phy_hibernation_mode(struct DWC_ETH_QOS_prv_data *pd
DWC_ETH_QOS_PHY_DEBUG_PORT_DATAPORT,
&phydata);
- EMACINFO("Exit value written 0x%x\n", phydata);
+ EMACDBG("Exit value written 0x%x\n", phydata);
}
/*!
@@ -677,6 +680,7 @@ static void configure_phy_rx_tx_delay(struct DWC_ETH_QOS_prv_data *pdata)
pdata->emac_hw_version_type != EMAC_HW_v2_1_2)
set_phy_rx_tx_delay(pdata, DISABLE_RX_DELAY, DISABLE_TX_DELAY);
}
+ }
break;
}
EMACDBG("Exit\n");
@@ -795,7 +799,6 @@ static inline int DWC_ETH_QOS_configure_io_macro_dll_settings(
EMACDBG("Enter\n");
#ifndef DWC_ETH_QOS_EMULATION_PLATFORM
- if (pdata->emac_hw_version_type == EMAC_HW_v2_0_0 || pdata->emac_hw_version_type == EMAC_HW_v2_3_1)
DWC_ETH_QOS_rgmii_io_macro_dll_reset(pdata);
/* For RGMII ID mode with internal delay*/
@@ -896,6 +899,11 @@ void DWC_ETH_QOS_adjust_link(struct net_device *dev)
if (!phydev)
return;
+ if (pdata->oldlink == -1 && !phydev->link) {
+ pdata->oldlink = phydev->link;
+ return;
+ }
+
DBGPR_MDIO(
"-->DWC_ETH_QOS_adjust_link. address %d link %d\n",
phydev->mdio.addr, phydev->link);
@@ -987,6 +995,13 @@ void DWC_ETH_QOS_adjust_link(struct net_device *dev)
if (new_state) {
phy_print_status(phydev);
+#ifdef CONFIG_MSM_BOOT_TIME_MARKER
+ if ((phydev->link == 1) && !pdata->print_kpi) {
+ place_marker("M - Ethernet is Ready.Link is UP");
+ pdata->print_kpi = 1;
+ }
+#endif
+
if (pdata->ipa_enabled && netif_running(dev)) {
if (phydev->link == 1)
DWC_ETH_QOS_ipa_offload_event_handler(pdata, EV_PHY_LINK_UP);
@@ -994,7 +1009,9 @@ void DWC_ETH_QOS_adjust_link(struct net_device *dev)
DWC_ETH_QOS_ipa_offload_event_handler(pdata, EV_PHY_LINK_DOWN);
}
- if (phydev->link == 0 && pdata->io_macro_phy_intf != RMII_MODE)
+ if (phydev->link == 1)
+ pdata->hw_if.start_mac_tx_rx();
+ else if (phydev->link == 0 && pdata->io_macro_phy_intf != RMII_MODE)
DWC_ETH_QOS_set_clk_and_bus_config(pdata, SPEED_10);
}
@@ -1033,8 +1050,11 @@ static void DWC_ETH_QOS_request_phy_wol(struct DWC_ETH_QOS_prv_data *pdata)
if (!phy_ethtool_set_wol(pdata->phydev, &wol)){
pdata->phy_wol_wolopts = wol.wolopts;
+
+ enable_irq_wake(pdata->phy_irq);
+
device_set_wakeup_enable(&pdata->pdev->dev, 1);
- EMACINFO("Enabled WoL[0x%x] in %s\n", wol.wolopts,
+ EMACDBG("Enabled WoL[0x%x] in %s\n", wol.wolopts,
pdata->phydev->drv->name);
}
}
@@ -1109,20 +1129,27 @@ static int DWC_ETH_QOS_init_phy(struct net_device *dev)
EMACDBG("Phy polling enabled\n");
#endif
- if (pdata->interface == PHY_INTERFACE_MODE_GMII ||
- pdata->interface == PHY_INTERFACE_MODE_RGMII) {
+
+ if (pdata->interface == PHY_INTERFACE_MODE_GMII || pdata->interface == PHY_INTERFACE_MODE_RGMII) {
phy_set_max_speed(phydev, SPEED_1000);
/* Half duplex not supported */
phydev->supported &= ~(SUPPORTED_10baseT_Half | SUPPORTED_100baseT_Half | SUPPORTED_1000baseT_Half);
- } else if ((pdata->interface == PHY_INTERFACE_MODE_MII) ||
- (pdata->interface == PHY_INTERFACE_MODE_RMII)) {
+ } else if ((pdata->interface == PHY_INTERFACE_MODE_MII) || (pdata->interface == PHY_INTERFACE_MODE_RMII)) {
phy_set_max_speed(phydev, SPEED_100);
/* Half duplex is not supported */
phydev->supported &= ~(SUPPORTED_10baseT_Half | SUPPORTED_100baseT_Half);
}
-
phydev->advertising = phydev->supported;
+ if (pdata->res_data->early_eth_en ) {
+ phydev->autoneg = AUTONEG_DISABLE;
+ phydev->speed = SPEED_100;
+ phydev->duplex = DUPLEX_FULL;
+ phydev->advertising = phydev->supported;
+ phydev->advertising &= ~(SUPPORTED_1000baseT_Full);
+ EMACDBG("Set max speed to SPEED_100 as early ethernet enabled\n");
+ }
+
pdata->phydev = phydev;
/* Disable smart speed function for AR8035*/
@@ -1147,7 +1174,7 @@ static int DWC_ETH_QOS_init_phy(struct net_device *dev)
DWC_ETH_QOS_set_phy_hibernation_mode(pdata, 0);
}
- if (pdata->phy_intr_en && pdata->phy_irq) {
+ if (pdata->phy_intr_en) {
INIT_WORK(&pdata->emac_phy_work, DWC_ETH_QOS_defer_phy_isr_work);
init_completion(&pdata->clk_enable_done);
@@ -1163,8 +1190,12 @@ static int DWC_ETH_QOS_init_phy(struct net_device *dev)
phydev->interrupts = PHY_INTERRUPT_ENABLED;
if (phydev->drv->config_intr &&
- !phydev->drv->config_intr(phydev))
+ !phydev->drv->config_intr(phydev)){
DWC_ETH_QOS_request_phy_wol(pdata);
+ } else {
+ EMACERR("Failed to configure PHY interrupts");
+ BUG();
+ }
}
phy_start(pdata->phydev);
@@ -1210,6 +1241,7 @@ int DWC_ETH_QOS_mdio_register(struct net_device *dev)
int ret = Y_SUCCESS;
int phy_reg_read_status, mii_status;
u32 phy_id, phy_id1, phy_id2;
+ u32 phydata = 0;
DBGPR_MDIO("-->DWC_ETH_QOS_mdio_register\n");
@@ -1244,6 +1276,17 @@ int DWC_ETH_QOS_mdio_register(struct net_device *dev)
pdata->phy_intr_en = false;
pdata->always_on_phy = false;
+ if(pdata->res_data->early_eth_en) {
+ EMACDBG("Updated speed to 100 in emac\n");
+ pdata->hw_if.set_mii_speed_100();
+
+ phydata = BMCR_SPEED100;
+ phydata |= BMCR_FULLDPLX;
+ EMACDBG("Updated speed to 100 and autoneg disable\n");
+ pdata->hw_if.write_phy_regs(pdata->phyaddr,
+ MII_BMCR, phydata);
+ }
+
DBGPHY_REGS(pdata);
new_bus = mdiobus_alloc();
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-18 09:38:25 +0000