diff options
author | Catalin Marinas <catalin.marinas@arm.com> | 2012-01-16 17:02:24 +0000 |
---|---|---|
committer | Jon Medhurst <tixy@linaro.org> | 2012-02-16 03:20:06 +0000 |
commit | f0253701194ce4027adb441e155518f1e96356ea (patch) | |
tree | e1596f0f27caefd8a8f826c5561f9bccfc7c1546 | |
parent | 82d5586754c8562bd603788ed8d51800932ce90e (diff) | |
download | vexpress-a9-armlt-linaro-android-3.2.tar.gz |
ARM: Add TLB flushing for both entries in a PMDandroid-release-2012.02-0armlt-linaro-android-3.2
Linux uses two PMD entries for a PTE with the classic page table format,
covering 2MB range. However, the __pte_free_tlb() function only adds a
single TLB flush corresponding to 1MB range covering 'addr'. On
Cortex-A15, level 1 entries can be cached by the TLB independently of
the level 2 entries and without additional flushing a PMD entry would be
left pointing at the wrong PTE. The patch limits the TLB flushing range
to two 4KB pages around the 1MB boundary within PMD.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
-rw-r--r-- | arch/arm/include/asm/tlb.h | 10 |
1 files changed, 9 insertions, 1 deletions
diff --git a/arch/arm/include/asm/tlb.h b/arch/arm/include/asm/tlb.h index 265f908c4a6..05043645004 100644 --- a/arch/arm/include/asm/tlb.h +++ b/arch/arm/include/asm/tlb.h @@ -198,7 +198,15 @@ static inline void __pte_free_tlb(struct mmu_gather *tlb, pgtable_t pte, unsigned long addr) { pgtable_page_dtor(pte); - tlb_add_flush(tlb, addr); + + /* + * With the classic ARM MMU, a pte page has two corresponding pmd + * entries, each covering 1MB. + */ + addr &= PMD_MASK; + tlb_add_flush(tlb, addr + SZ_1M - PAGE_SIZE); + tlb_add_flush(tlb, addr + SZ_1M); + tlb_remove_page(tlb, pte); } |