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| author | Catalin Marinas <catalin.marinas@arm.com> | 2012-09-07 15:37:15 +0100 |
|---|---|---|
| committer | Catalin Marinas <catalin.marinas@arm.com> | 2012-09-07 15:54:40 +0100 |
| commit | ab770d839e1f6ed377b31b7e5eff4d6a2aa96300 (patch) | |
| tree | d9b0d3cf3aa7c419f542d3c8af38cd981b1860c3 | |
| parent | 6c875649e098d66589e658058109a9bcf688e0e3 (diff) | |
| download | linux-aarch64-ab770d839e1f6ed377b31b7e5eff4d6a2aa96300.tar.gz | |
arm64: Update the booting.txt document initial register values and caches
This patch adds the requirement that x1-x3 registers are set to 0 during
boot for the primary CPU (reserved for future use). For the secondary
CPUs, registers x0-x3 must also be set to 0 (reserved for future use).
External caches (if present) must be configured and disabled.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
| -rw-r--r-- | Documentation/arm64/booting.txt | 21 |
1 files changed, 16 insertions, 5 deletions
diff --git a/Documentation/arm64/booting.txt b/Documentation/arm64/booting.txt index 3197820460c..9c4d388dadd 100644 --- a/Documentation/arm64/booting.txt +++ b/Documentation/arm64/booting.txt @@ -2,7 +2,7 @@ ===================== Author: Will Deacon <will.deacon@arm.com> -Date : 25 April 2012 +Date : 07 September 2012 This document is based on the ARM booting document by Russell King and is relevant to all public releases of the AArch64 Linux kernel. @@ -56,10 +56,11 @@ blob using a single section mapping in the initial page tables. Requirement: OPTIONAL -The AArch64 kernel does not provide a decompressor and therefore -requires gzip decompression to be performed by the boot loader if the -default Image.gz target is used. For bootloaders that do not implement -this requirement, the larger Image target is available instead. +The AArch64 kernel does not currently provide a decompressor and +therefore requires decompression (gzip etc.) to be performed by the boot +loader if a compressed Image target (e.g. Image.gz) is used. For +bootloaders that do not implement this requirement, the uncompressed +Image target is available instead. 4. Call the kernel image @@ -87,6 +88,9 @@ Before jumping into the kernel, the following conditions must be met: - Primary CPU general-purpose register settings x0 = physical address of device tree blob (dtb) in system RAM. + x1 = 0 (reserved for future use) + x2 = 0 (reserved for future use) + x3 = 0 (reserved for future use) - CPU mode All forms of interrupts must be masked in PSTATE.DAIF (Debug, SError, @@ -98,6 +102,7 @@ Before jumping into the kernel, the following conditions must be met: The MMU must be off. Instruction cache may be on or off. Data cache must be off and invalidated. + External caches (if present) must be configured and disabled. - Architected timers CNTFRQ must be programmed with the timer frequency. @@ -139,3 +144,9 @@ following manner: the primary CPU. When a read of the location pointed to by the cpu-release-addr returns a non-zero value, the CPU must jump directly to this value. + +- Secondary CPU general-purpose register settings + x0 = 0 (reserved for future use) + x1 = 0 (reserved for future use) + x2 = 0 (reserved for future use) + x3 = 0 (reserved for future use) |