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AgeCommit message (Expand)Author
2022-08-19Rename xnn_qs8_minmax_params to xnn_qc8_conv_minmax_paramsMarat Dukhan
2022-08-19Enable Relaxed SIMD microkernels for QS8/QU8 VCVT & VLRELUMarat Dukhan
2022-08-18Refactor declarations of microkernel function pointersMarat Dukhan
2022-08-17Depth to space nchw2nhwc uses transposeAlan Kelly
2022-08-16Enable ARM SIMD32 microkernels for pre-NEON AArch32 processorsMarat Dukhan
2022-08-16Rename ARMV6SIMD to ARMSIMD32Marat Dukhan
2022-08-01Convert AArch32 and AArch64 F32 GEMM and IGEMM microkernels used for default ...Zhi An Ng
2022-07-27Rename xnn_q[su]8_addsub_minmax_params to xnn_q[su]8_add_minmax_paramsMarat Dukhan
2022-07-27Refactor declarations of microkernel parametersMarat Dukhan
2022-07-19Add option to disable ARM DotProd instructionsMarat Dukhan
2022-07-19FP16 dwconv2d CHW x8Frank Barchard
2022-07-19Support disabling ARM FP16 instructionsMarat Dukhan
2022-06-29F16 ELU NC operatorMarat Dukhan
2022-06-27Fix RISC-V buildMarat Dukhan
2022-06-27QS8 / QU8 Convert NC operatorsMarat Dukhan
2022-06-23Enable FP16 ibilinear-chw microkernel for AArch64Frank Barchard
2022-06-23QS8 / QU8 Leaky ReLU operator using VLRELU microkernelsMarat Dukhan
2022-06-14Enable Q8 4x8 Cortex A35 Q8 IGEMM microkernelsFrank Barchard
2022-06-02Enable Q8 1x8 AArch32 IGEMM for Cortex A7/A35Frank Barchard
2022-05-31Rollback initialization for Cortex A35 Q8 IGEMM microkernelsFrank Barchard
2022-05-27xnn_qc8_dwconv_up16x3__aarch32_neonv8_mla8_cortex_a35Frank Barchard
2022-05-25Enable LD128 variant of 16x3 DWCONV for QC8 NEONFrank Barchard
2022-05-24Initialize pointers to NEONFP16ARITH CHW microkernelsFrank Barchard
2022-05-17Enable 4X8 IGEMM for Cortex A7/32/A35Frank Barchard
2022-05-15Enable Q8 1x8 AArch32 GEMM for Cortex A55r0Frank Barchard
2022-05-13Add a compile time flag (xnn_enable_gemm_m_specialization) to enable selectin...Zhi An Ng
2022-05-12Enable Q8 1x8 AArch32 GEMM for Cortex A53 / A57Frank Barchard
2022-05-12Enable Q8 1x8 AArch32 GEMM for Cortex A7 / A35Frank Barchard
2022-05-11Fix gemm2 microkernel indices in init.cZhi An Ng
2022-05-09Enable QC8 4x8 GEMM for Cortex A32Frank Barchard
2022-05-04Add initial heuristic MR selection and add 4x8 GEMM and IGEMM microkernel for...Zhi An Ng
2022-05-02Add additional fields to gemm_fused_ukernels to allow specifying GEMM and IGE...Zhi An Ng
2022-04-28Remove JIT 6x8 AArch64 A75 microkernel, upto6x8 is the equivalentZhi An Ng
2022-04-28Enable FP32 6x8__aarch64_neonfma_prfm_cortex_a75 GEMM/IGEMM for Cortex A57Frank Barchard
2022-04-27F16 Average Pooling NHWC operatorMarat Dukhan
2022-04-25F16 Square Root NC operatorMarat Dukhan
2022-04-21QC8 DWCONV3 microkernelsMarat Dukhan
2022-04-21Always allocate code and weights memory at page-aligned sizesZhi An Ng
2022-04-21Move definition of xnn_params out of init.c into its own fileZhi An Ng
2022-04-20Enable DWCONV microkernels using Relaxed FMAMarat Dukhan
2022-04-20F16 Rounding operatorsMarat Dukhan
2022-04-17F16 Divide/Minimum/Maximum/Subtract/Squared Difference ND operatorsMarat Dukhan
2022-04-15Abs/Negate/Square NC operatorsMarat Dukhan
2022-04-13Initialize AArch32 microkernels for Cortex A32Frank Barchard
2022-04-11Remove WAsm SIMD VRND microkernels using ADDSUB & CVT algorithmsMarat Dukhan
2022-04-11Target Chrome M91 WebAssembly SIMD instructionsMarat Dukhan
2022-04-07Enable WAsm Relaxed SIMD FP32 GEMM/IGEMM microkernelsMarat Dukhan
2022-04-07Remove WAsm DWCONV/GEMM/IGEMM microkernels with LINEAR activationsMarat Dukhan
2022-03-21Enable FP32 prfm version of 1x8 GEMM/IGEMM microkernels for Cortex A53Frank Barchard
2022-03-16Enable FP32 4x2 IGEMM assembly microkernel for Cortex A75Frank Barchard
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