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| author | Grzegorz Jaszczyk <jaz@semihalf.com> | 2019-01-13 15:29:10 +0200 |
|---|---|---|
| committer | Marcin Wojtas <mw@semihalf.com> | 2020-06-07 00:06:03 +0200 |
| commit | 2da75ae1174205b43f80b64bb7deae42ea6b70a1 (patch) | |
| tree | 6c0df63a1d6fe78b40f79e1ea3e7a175383e2837 | |
| parent | dc402531eff62ca54c3f9f360be50c1c113d16f9 (diff) | |
| download | arm-trusted-firmware-2da75ae1174205b43f80b64bb7deae42ea6b70a1.tar.gz | |
plat: marvell: ap807: use correct address for MCIx4 register
The AP807 uses different register offset for MCIx4 register, reflect it
in the code.
Change-Id: Ic7e44fede3c69083e8629741e7c440b1ae08c35f
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
| -rw-r--r-- | drivers/marvell/mochi/ap807_setup.c | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/drivers/marvell/mochi/ap807_setup.c b/drivers/marvell/mochi/ap807_setup.c index 864c9230a..132fffc9e 100644 --- a/drivers/marvell/mochi/ap807_setup.c +++ b/drivers/marvell/mochi/ap807_setup.c @@ -31,6 +31,11 @@ #define DSS_CR0 (MVEBU_RFU_BASE + 0x100) #define DVM_48BIT_VA_ENABLE (1 << 21) + +/* SoC RFU / IHBx4 Control */ +#define MCIX4_807_REG_START_ADDR_REG(unit_id) (MVEBU_RFU_BASE + \ + 0x4258 + (unit_id * 0x4)) + /* Secure MoChi incoming access */ #define SEC_MOCHI_IN_ACC_REG (MVEBU_RFU_BASE + 0x4738) #define SEC_MOCHI_IN_ACC_IHB0_EN (1) @@ -124,7 +129,7 @@ static void mci_remap_indirect_access_base(void) uint32_t mci; for (mci = 0; mci < MCI_MAX_UNIT_ID; mci++) - mmio_write_32(MCIX4_REG_START_ADDRESS_REG(mci), + mmio_write_32(MCIX4_807_REG_START_ADDR_REG(mci), MVEBU_MCI_REG_BASE_REMAP(mci) >> MCI_REMAP_OFF_SHIFT); } |