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| author | Yatharth Kochar <yatharth.kochar@arm.com> | 2016-06-30 15:02:31 +0100 |
|---|---|---|
| committer | Yatharth Kochar <yatharth.kochar@arm.com> | 2016-09-21 16:28:39 +0100 |
| commit | 3bdf0e5df25cf730fbbde7df3dd857d7f2803d1a (patch) | |
| tree | d14afa2696b06bd6c557dac387afca8cf0de97f9 /bl32/sp_min/sp_min.ld.S | |
| parent | 6fe8aa2fa638a7f8c54e6fc084bf2ed6103c2854 (diff) | |
| download | arm-trusted-firmware-3bdf0e5df25cf730fbbde7df3dd857d7f2803d1a.tar.gz | |
AArch32: Refactor SP_MIN to support RESET_TO_SP_MIN
This patch uses the `el3_entrypoint_common` macro to initialize
CPU registers, in SP_MIN entrypoint.s file, in both cold and warm
boot path. It also adds conditional compilation, in cold and warm
boot entry path, based on RESET_TO_SP_MIN.
Change-Id: Id493ca840dc7b9e26948dc78ee928e9fdb76b9e4
Diffstat (limited to 'bl32/sp_min/sp_min.ld.S')
| -rw-r--r-- | bl32/sp_min/sp_min.ld.S | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/bl32/sp_min/sp_min.ld.S b/bl32/sp_min/sp_min.ld.S index b158db16d..e0e23e8f9 100644 --- a/bl32/sp_min/sp_min.ld.S +++ b/bl32/sp_min/sp_min.ld.S @@ -50,6 +50,7 @@ SECTIONS __TEXT_START__ = .; *entrypoint.o(.text*) *(.text*) + *(.vectors) . = NEXT(4096); __TEXT_END__ = .; } >RAM @@ -98,6 +99,7 @@ SECTIONS KEEP(*(cpu_ops)) __CPU_OPS_END__ = .; + *(.vectors) __RO_END_UNALIGNED__ = .; /* |