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Diffstat (limited to 'docs/plat/nvidia-tegra.rst')
| -rw-r--r-- | docs/plat/nvidia-tegra.rst | 30 |
1 files changed, 13 insertions, 17 deletions
diff --git a/docs/plat/nvidia-tegra.rst b/docs/plat/nvidia-tegra.rst index 02ff38bef..391c7c815 100644 --- a/docs/plat/nvidia-tegra.rst +++ b/docs/plat/nvidia-tegra.rst @@ -19,7 +19,7 @@ The NVIDIA® Parker (T186) series system-on-chip (SoC) delivers a heterogeneous multi-processing (HMP) solution designed to optimize performance and efficiency. -T186 has Dual NVIDIA Denver 2 ARM® CPU cores, plus Quad ARM Cortex®-A57 cores, +T186 has Dual NVIDIA Denver2 ARM® CPU cores, plus Quad ARM Cortex®-A57 cores, in a coherent multiprocessor configuration. The Denver 2 and Cortex-A57 cores support ARMv8, executing both 64-bit Aarch64 code, and 32-bit Aarch32 code including legacy ARMv7 applications. The Denver 2 processors each have 128 KB @@ -29,20 +29,6 @@ Data Level 1 caches; and also have a 2 MB shared Level 2 unified cache. A high speed coherency fabric connects these two processor complexes and allows heterogeneous multi-processing with all six cores if required. -- .. rubric:: T210 - :name: t210 - -T210 has Quad Arm® Cortex®-A57 cores in a switched configuration with a -companion set of quad Arm Cortex-A53 cores. The Cortex-A57 and A53 cores -support Armv8-A, executing both 64-bit Aarch64 code, and 32-bit Aarch32 code -including legacy Armv7-A applications. The Cortex-A57 processors each have -48 KB Instruction and 32 KB Data Level 1 caches; and have a 2 MB shared -Level 2 unified cache. The Cortex-A53 processors each have 32 KB Instruction -and 32 KB Data Level 1 caches; and have a 512 KB shared Level 2 unified cache. - -- .. rubric:: T132 - :name: t132 - Denver is NVIDIA's own custom-designed, 64-bit, dual-core CPU which is fully Armv8-A architecture compatible. Each of the two Denver cores implements a 7-way superscalar microarchitecture (up to 7 concurrent @@ -68,6 +54,17 @@ Denver also features new low latency power-state transitions, in addition to extensive power-gating and dynamic voltage and clock scaling based on workloads. +- .. rubric:: T210 + :name: t210 + +T210 has Quad Arm® Cortex®-A57 cores in a switched configuration with a +companion set of quad Arm Cortex-A53 cores. The Cortex-A57 and A53 cores +support Armv8-A, executing both 64-bit Aarch64 code, and 32-bit Aarch32 code +including legacy Armv7-A applications. The Cortex-A57 processors each have +48 KB Instruction and 32 KB Data Level 1 caches; and have a 2 MB shared +Level 2 unified cache. The Cortex-A53 processors each have 32 KB Instruction +and 32 KB Data Level 1 caches; and have a 512 KB shared Level 2 unified cache. + Directory structure ------------------- @@ -89,7 +86,6 @@ their dispatchers in the image without changing any makefiles. These are the supported Trusted OS' by Tegra platforms. -- Tegra132: TLK - Tegra210: TLK and Trusty - Tegra186: Trusty - Tegra194: Trusty @@ -110,7 +106,7 @@ Preparing the BL31 image to run on Tegra SoCs .. code:: shell CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-none-elf- make PLAT=tegra \ - TARGET_SOC=<target-soc e.g. t194|t186|t210|t132> SPD=<dispatcher e.g. trusty|tlkd> + TARGET_SOC=<target-soc e.g. t194|t186|t210> SPD=<dispatcher e.g. trusty|tlkd> bl31 Platforms wanting to use different TZDRAM\_BASE, can add ``TZDRAM_BASE=<value>`` |