diff options
Diffstat (limited to 'drivers/marvell/mochi/cp110_setup.c')
-rw-r--r-- | drivers/marvell/mochi/cp110_setup.c | 53 |
1 files changed, 48 insertions, 5 deletions
diff --git a/drivers/marvell/mochi/cp110_setup.c b/drivers/marvell/mochi/cp110_setup.c index 0fa049764..f12da0ef8 100644 --- a/drivers/marvell/mochi/cp110_setup.c +++ b/drivers/marvell/mochi/cp110_setup.c @@ -12,7 +12,9 @@ #include <drivers/marvell/amb_adec.h> #include <drivers/marvell/iob.h> #include <drivers/marvell/mochi/cp110_setup.h> +#include <drivers/rambus/trng_ip_76.h> +#include <efuse_def.h> #include <plat_marvell.h> /* @@ -105,6 +107,13 @@ #define MVEBU_RTC_READ_OUTPUT_DELAY_MASK 0xFFFF #define MVEBU_RTC_READ_OUTPUT_DELAY_DEFAULT 0x1F +/******************************************************************************* + * TRNG Configuration + ******************************************************************************/ +#define MVEBU_TRNG_BASE (0x760000) +#define MVEBU_EFUSE_TRNG_ENABLE_EFUSE_WORD MVEBU_AP_LDX_220_189_EFUSE_OFFS +#define MVEBU_EFUSE_TRNG_ENABLE_BIT_OFFSET 13 /* LD0[202] */ + enum axi_attr { AXI_ADUNIT_ATTR = 0, AXI_COMUNIT_ATTR, @@ -130,7 +139,7 @@ enum axi_attr { #define USB3H_1_STREAM_ID_REG (RFU_STREAM_ID_BASE + 0x10) #define SATA_0_STREAM_ID_REG (RFU_STREAM_ID_BASE + 0x14) #define SATA_1_STREAM_ID_REG (RFU_STREAM_ID_BASE + 0x18) -#define SDIO_0_STREAM_ID_REG (RFU_STREAM_ID_BASE + 0x28) +#define SDIO_STREAM_ID_REG (RFU_STREAM_ID_BASE + 0x28) #define CP_DMA_0_STREAM_ID_REG (0x6B0010) #define CP_DMA_1_STREAM_ID_REG (0x6D0010) @@ -138,14 +147,14 @@ enum axi_attr { /* We allocate IDs 128-255 for PCIe */ #define MAX_STREAM_ID (0x80) -uintptr_t stream_id_reg[] = { +static uintptr_t stream_id_reg[] = { USB3H_0_STREAM_ID_REG, USB3H_1_STREAM_ID_REG, CP_DMA_0_STREAM_ID_REG, CP_DMA_1_STREAM_ID_REG, SATA_0_STREAM_ID_REG, SATA_1_STREAM_ID_REG, - SDIO_0_STREAM_ID_REG, + SDIO_STREAM_ID_REG, 0 }; @@ -180,8 +189,9 @@ static void cp110_pcie_clk_cfg(uintptr_t base) pcie0_clk = (reg & SAR_PCIE0_CLK_CFG_MASK) >> SAR_PCIE0_CLK_CFG_OFFSET; pcie1_clk = (reg & SAR_PCIE1_CLK_CFG_MASK) >> SAR_PCIE1_CLK_CFG_OFFSET; - /* CP110 revision A2 */ - if (cp110_rev_id_get(base) == MVEBU_CP110_REF_ID_A2) { + /* CP110 revision A2 or CN913x */ + if (cp110_rev_id_get(base) == MVEBU_CP110_REF_ID_A2 || + cp110_device_id_get(base) == MVEBU_CN9130_DEV_ID) { /* * PCIe Reference Clock Buffer Control register must be * set according to the clock direction (input/output) @@ -378,6 +388,36 @@ static void cp110_amb_adec_init(uintptr_t base) init_amb_adec(base); } +static void cp110_trng_init(uintptr_t base) +{ + static bool done; + int ret; + uint32_t reg_val, efuse; + + /* Set access to LD0 */ + reg_val = mmio_read_32(MVEBU_AP_EFUSE_SRV_CTRL_REG); + reg_val &= ~EFUSE_SRV_CTRL_LD_SELECT_MASK; + mmio_write_32(MVEBU_AP_EFUSE_SRV_CTRL_REG, reg_val); + + /* Obtain the AP LD0 bit defining TRNG presence */ + efuse = mmio_read_32(MVEBU_EFUSE_TRNG_ENABLE_EFUSE_WORD); + efuse >>= MVEBU_EFUSE_TRNG_ENABLE_BIT_OFFSET; + efuse &= 1; + + if (efuse == 0) { + VERBOSE("TRNG is not present, skipping"); + return; + } + + if (!done) { + ret = eip76_rng_probe(base + MVEBU_TRNG_BASE); + if (ret != 0) { + ERROR("Failed to init TRNG @ 0x%lx\n", base); + return; + } + done = true; + } +} void cp110_init(uintptr_t cp110_base, uint32_t stream_id) { INFO("%s: Initialize CPx - base = %lx\n", __func__, cp110_base); @@ -405,6 +445,9 @@ void cp110_init(uintptr_t cp110_base, uint32_t stream_id) /* Reset RTC if needed */ cp110_rtc_init(cp110_base); + + /* TRNG init - for CP0 only */ + cp110_trng_init(cp110_base); } /* Do the minimal setup required to configure the CP in BLE */ |