diff options
Diffstat (limited to 'fdts')
35 files changed, 655 insertions, 220 deletions
diff --git a/fdts/arm_fpga.dts b/fdts/arm_fpga.dts index b7b4f0e6a..c0efd0949 100644 --- a/fdts/arm_fpga.dts +++ b/fdts/arm_fpga.dts @@ -40,7 +40,6 @@ timer { compatible = "arm,armv8-timer"; - clock-frequency = <10000000>; interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, @@ -82,7 +81,7 @@ dbg_uart: serial@7ff80000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x0 0x7ff80000 0x0 0x00001000>; - interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>; clocks = <&uartclk>, <&bus_refclk>; clock-names = "uartclk", "apb_pclk"; }; @@ -98,5 +97,12 @@ /* The GICR size will be adjusted at runtime to match the cores. */ <0x0 0x30040000 0x0 0x00020000>; /* GICR for one core */ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; + + its: msi-controller@30040000 { + compatible = "arm,gic-v3-its"; + reg = <0x0 0x30040000 0x0 0x40000>; + #msi-cells = <1>; + msi-controller; + }; }; }; diff --git a/fdts/fvp-base-gicv3-psci-common.dtsi b/fdts/fvp-base-gicv3-psci-common.dtsi index b6753de8e..3cb613f63 100644 --- a/fdts/fvp-base-gicv3-psci-common.dtsi +++ b/fdts/fvp-base-gicv3-psci-common.dtsi @@ -24,7 +24,11 @@ #address-cells = <2>; #size-cells = <2>; - chosen { }; +#if (ENABLE_RME == 1) + chosen { bootargs = "mem=1G console=ttyAMA0 earlycon=pl011,0x1c090000 root=/dev/vda ip=on";}; +#else + chosen {}; +#endif aliases { serial0 = &v2m_serial0; @@ -135,8 +139,13 @@ memory@80000000 { device_type = "memory"; +#if (ENABLE_RME == 1) + reg = <0x00000000 0x80000000 0 0x7C000000>, + <0x00000008 0x80000000 0 0x80000000>; +#else reg = <0x00000000 0x80000000 0 0x7F000000>, <0x00000008 0x80000000 0 0x80000000>; +#endif }; gic: interrupt-controller@2f000000 { diff --git a/fdts/juno-ethosn.dtsi b/fdts/juno-ethosn.dtsi index 87ab378a2..e2f33550e 100644 --- a/fdts/juno-ethosn.dtsi +++ b/fdts/juno-ethosn.dtsi @@ -4,19 +4,21 @@ * SPDX-License-Identifier: BSD-3-Clause */ +/* + * For examples of multi-core and multi-device NPU, refer to the examples given in the + * Arm Ethos-N NPU driver stack. + * https://github.com/ARM-software/ethos-n-driver-stack + */ + / { #address-cells = <2>; #size-cells = <2>; - ethosn: ethosn@6f300000 { + ethosn0: ethosn@6f300000 { compatible = "ethosn"; reg = <0 0x6f300000 0 0x00100000>; status = "okay"; - /* - * Single-core NPU. For multi-core NPU, additional core nodes - * and reg values must be added. - */ core0 { compatible = "ethosn-core"; status = "okay"; diff --git a/fdts/stm32mp15-bl2.dtsi b/fdts/stm32mp15-bl2.dtsi new file mode 100644 index 000000000..074414bb2 --- /dev/null +++ b/fdts/stm32mp15-bl2.dtsi @@ -0,0 +1,91 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2020-2021 - All Rights Reserved + */ + +/ { +#if !STM32MP_EMMC && !STM32MP_SDMMC + aliases { + /delete-property/ mmc0; + }; +#endif + + cpus { + /delete-node/ cpu@1; + }; + + /delete-node/ psci; + + soc { + /delete-node/ timer@40006000; + /delete-node/ timer@44006000; +#if !STM32MP_USB_PROGRAMMER + /delete-node/ usb-otg@49000000; +#endif + /delete-node/ pwr_mcu@50001014; + /delete-node/ cryp@54001000; + /delete-node/ rng@54003000; +#if !STM32MP_RAW_NAND + /delete-node/ memory-controller@58002000; +#endif +#if !STM32MP_SPI_NAND && !STM32MP_SPI_NOR + /delete-node/ spi@58003000; +#endif +#if !STM32MP_EMMC && !STM32MP_SDMMC + /delete-node/ mmc@58005000; + /delete-node/ mmc@58007000; +#endif +#if !STM32MP_USB_PROGRAMMER + /delete-node/ usbphyc@5a006000; +#endif + /delete-node/ spi@5c001000; + /delete-node/ rtc@5c004000; + /delete-node/ etzpc@5c007000; + /delete-node/ stgen@5c008000; + /delete-node/ i2c@5c009000; + /delete-node/ tamp@5c00a000; + + pin-controller@50002000 { +#if !STM32MP_RAW_NAND + /delete-node/ fmc-0; +#endif +#if !STM32MP_SPI_NAND && !STM32MP_SPI_NOR + /delete-node/ qspi-clk-0; + /delete-node/ qspi-bk1-0; + /delete-node/ qspi-bk2-0; +#endif +#if !STM32MP_EMMC && !STM32MP_SDMMC + /delete-node/ sdmmc1-b4-0; + /delete-node/ sdmmc1-dir-0; + /delete-node/ sdmmc2-b4-0; + /delete-node/ sdmmc2-b4-1; + /delete-node/ sdmmc2-d47-0; +#endif +#if !STM32MP_USB_PROGRAMMER + /delete-node/ usbotg_hs-0; + /delete-node/ usbotg-fs-dp-dm-0; +#endif + }; + }; + +#if !STM32MP_USE_STM32IMAGE + /* + * UUID's here are UUID RFC 4122 compliant meaning fieds are stored in + * network order (big endian) + */ + + st-io_policies { + fip-handles { + compatible = "st,io-fip-handle"; + fw_cfg_uuid = "5807e16a-8459-47be-8ed5-648e8dddab0e"; + bl32_uuid = "05d0e189-53dc-1347-8d2b-500a4b7a3e38"; + bl32_extra1_uuid = "0b70c29b-2a5a-7840-9f65-0a5682738288"; + bl32_extra2_uuid = "8ea87bb1-cfa2-3f4d-85fd-e7bba50220d9"; + bl33_uuid = "d6d0eea7-fcea-d54b-9782-9934f234b6e4"; + hw_cfg_uuid = "08b8f1d9-c9cf-9349-a962-6fbc6b7265cc"; + tos_fw_cfg_uuid = "26257c1a-dbc6-7f47-8d96-c4c4b0248021"; + nt_fw_cfg_uuid = "28da9815-93e8-7e44-ac66-1aaf801550f9"; + }; + }; +#endif /* !STM32MP_USE_STM32IMAGE */ +}; diff --git a/fdts/stm32mp15-bl32.dtsi b/fdts/stm32mp15-bl32.dtsi new file mode 100644 index 000000000..ca4bb3ea5 --- /dev/null +++ b/fdts/stm32mp15-bl32.dtsi @@ -0,0 +1,46 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2020-2021 - All Rights Reserved + */ + +/ { + aliases { + /delete-property/ mmc0; + /delete-property/ mmc1; + }; + + cpus { + /delete-node/ cpu@1; + }; + + /delete-node/ psci; + + soc { + /delete-node/ usb-otg@49000000; + /delete-node/ hash@54002000; + /delete-node/ memory-controller@58002000; + /delete-node/ spi@58003000; + /delete-node/ mmc@58005000; + /delete-node/ mmc@58007000; + /delete-node/ usbphyc@5a006000; + /delete-node/ spi@5c001000; + /delete-node/ stgen@5c008000; + /delete-node/ i2c@5c009000; + + pin-controller@50002000 { + /delete-node/ fmc-0; + /delete-node/ qspi-clk-0; + /delete-node/ qspi-bk1-0; + /delete-node/ qspi-bk2-0; + /delete-node/ sdmmc1-b4-0; + /delete-node/ sdmmc1-dir-0; + /delete-node/ sdmmc2-b4-0; + /delete-node/ sdmmc2-b4-1; + /delete-node/ sdmmc2-d47-0; + /delete-node/ sdmmc2-d47-1; + /delete-node/ sdmmc2-d47-3; + /delete-node/ usbotg_hs-0; + /delete-node/ usbotg-fs-dp-dm-0; + }; + }; +}; diff --git a/fdts/stm32mp15-ddr.dtsi b/fdts/stm32mp15-ddr.dtsi index 4825691f9..e5efd9256 100644 --- a/fdts/stm32mp15-ddr.dtsi +++ b/fdts/stm32mp15-ddr.dtsi @@ -1,153 +1,127 @@ // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause /* - * Copyright (C) 2018, STMicroelectronics - All Rights Reserved + * Copyright (C) 2018-2021, STMicroelectronics - All Rights Reserved */ -/ { - soc { - ddr: ddr@5a003000{ +&ddr { + st,mem-name = DDR_MEM_NAME; + st,mem-speed = <DDR_MEM_SPEED>; + st,mem-size = <DDR_MEM_SIZE>; - compatible = "st,stm32mp1-ddr"; + st,ctl-reg = < + DDR_MSTR + DDR_MRCTRL0 + DDR_MRCTRL1 + DDR_DERATEEN + DDR_DERATEINT + DDR_PWRCTL + DDR_PWRTMG + DDR_HWLPCTL + DDR_RFSHCTL0 + DDR_RFSHCTL3 + DDR_CRCPARCTL0 + DDR_ZQCTL0 + DDR_DFITMG0 + DDR_DFITMG1 + DDR_DFILPCFG0 + DDR_DFIUPD0 + DDR_DFIUPD1 + DDR_DFIUPD2 + DDR_DFIPHYMSTR + DDR_ODTMAP + DDR_DBG0 + DDR_DBG1 + DDR_DBGCMD + DDR_POISONCFG + DDR_PCCFG + >; - reg = <0x5A003000 0x550 - 0x5A004000 0x234>; + st,ctl-timing = < + DDR_RFSHTMG + DDR_DRAMTMG0 + DDR_DRAMTMG1 + DDR_DRAMTMG2 + DDR_DRAMTMG3 + DDR_DRAMTMG4 + DDR_DRAMTMG5 + DDR_DRAMTMG6 + DDR_DRAMTMG7 + DDR_DRAMTMG8 + DDR_DRAMTMG14 + DDR_ODTCFG + >; - clocks = <&rcc AXIDCG>, - <&rcc DDRC1>, - <&rcc DDRC2>, - <&rcc DDRPHYC>, - <&rcc DDRCAPB>, - <&rcc DDRPHYCAPB>; + st,ctl-map = < + DDR_ADDRMAP1 + DDR_ADDRMAP2 + DDR_ADDRMAP3 + DDR_ADDRMAP4 + DDR_ADDRMAP5 + DDR_ADDRMAP6 + DDR_ADDRMAP9 + DDR_ADDRMAP10 + DDR_ADDRMAP11 + >; - clock-names = "axidcg", - "ddrc1", - "ddrc2", - "ddrphyc", - "ddrcapb", - "ddrphycapb"; + st,ctl-perf = < + DDR_SCHED + DDR_SCHED1 + DDR_PERFHPR1 + DDR_PERFLPR1 + DDR_PERFWR1 + DDR_PCFGR_0 + DDR_PCFGW_0 + DDR_PCFGQOS0_0 + DDR_PCFGQOS1_0 + DDR_PCFGWQOS0_0 + DDR_PCFGWQOS1_0 + DDR_PCFGR_1 + DDR_PCFGW_1 + DDR_PCFGQOS0_1 + DDR_PCFGQOS1_1 + DDR_PCFGWQOS0_1 + DDR_PCFGWQOS1_1 + >; - st,mem-name = DDR_MEM_NAME; - st,mem-speed = <DDR_MEM_SPEED>; - st,mem-size = <DDR_MEM_SIZE>; + st,phy-reg = < + DDR_PGCR + DDR_ACIOCR + DDR_DXCCR + DDR_DSGCR + DDR_DCR + DDR_ODTCR + DDR_ZQ0CR1 + DDR_DX0GCR + DDR_DX1GCR + DDR_DX2GCR + DDR_DX3GCR + >; - st,ctl-reg = < - DDR_MSTR - DDR_MRCTRL0 - DDR_MRCTRL1 - DDR_DERATEEN - DDR_DERATEINT - DDR_PWRCTL - DDR_PWRTMG - DDR_HWLPCTL - DDR_RFSHCTL0 - DDR_RFSHCTL3 - DDR_CRCPARCTL0 - DDR_ZQCTL0 - DDR_DFITMG0 - DDR_DFITMG1 - DDR_DFILPCFG0 - DDR_DFIUPD0 - DDR_DFIUPD1 - DDR_DFIUPD2 - DDR_DFIPHYMSTR - DDR_ODTMAP - DDR_DBG0 - DDR_DBG1 - DDR_DBGCMD - DDR_POISONCFG - DDR_PCCFG - >; + st,phy-timing = < + DDR_PTR0 + DDR_PTR1 + DDR_PTR2 + DDR_DTPR0 + DDR_DTPR1 + DDR_DTPR2 + DDR_MR0 + DDR_MR1 + DDR_MR2 + DDR_MR3 + >; - st,ctl-timing = < - DDR_RFSHTMG - DDR_DRAMTMG0 - DDR_DRAMTMG1 - DDR_DRAMTMG2 - DDR_DRAMTMG3 - DDR_DRAMTMG4 - DDR_DRAMTMG5 - DDR_DRAMTMG6 - DDR_DRAMTMG7 - DDR_DRAMTMG8 - DDR_DRAMTMG14 - DDR_ODTCFG - >; - - st,ctl-map = < - DDR_ADDRMAP1 - DDR_ADDRMAP2 - DDR_ADDRMAP3 - DDR_ADDRMAP4 - DDR_ADDRMAP5 - DDR_ADDRMAP6 - DDR_ADDRMAP9 - DDR_ADDRMAP10 - DDR_ADDRMAP11 - >; - - st,ctl-perf = < - DDR_SCHED - DDR_SCHED1 - DDR_PERFHPR1 - DDR_PERFLPR1 - DDR_PERFWR1 - DDR_PCFGR_0 - DDR_PCFGW_0 - DDR_PCFGQOS0_0 - DDR_PCFGQOS1_0 - DDR_PCFGWQOS0_0 - DDR_PCFGWQOS1_0 - DDR_PCFGR_1 - DDR_PCFGW_1 - DDR_PCFGQOS0_1 - DDR_PCFGQOS1_1 - DDR_PCFGWQOS0_1 - DDR_PCFGWQOS1_1 - >; - - st,phy-reg = < - DDR_PGCR - DDR_ACIOCR - DDR_DXCCR - DDR_DSGCR - DDR_DCR - DDR_ODTCR - DDR_ZQ0CR1 - DDR_DX0GCR - DDR_DX1GCR - DDR_DX2GCR - DDR_DX3GCR - >; - - st,phy-timing = < - DDR_PTR0 - DDR_PTR1 - DDR_PTR2 - DDR_DTPR0 - DDR_DTPR1 - DDR_DTPR2 - DDR_MR0 - DDR_MR1 - DDR_MR2 - DDR_MR3 - >; - - st,phy-cal = < - DDR_DX0DLLCR - DDR_DX0DQTR - DDR_DX0DQSTR - DDR_DX1DLLCR - DDR_DX1DQTR - DDR_DX1DQSTR - DDR_DX2DLLCR - DDR_DX2DQTR - DDR_DX2DQSTR - DDR_DX3DLLCR - DDR_DX3DQTR - DDR_DX3DQSTR - >; - - status = "okay"; - }; - }; + st,phy-cal = < + DDR_DX0DLLCR + DDR_DX0DQTR + DDR_DX0DQSTR + DDR_DX1DLLCR + DDR_DX1DQTR + DDR_DX1DQSTR + DDR_DX2DLLCR + DDR_DX2DQTR + DDR_DX2DQSTR + DDR_DX3DLLCR + DDR_DX3DQTR + DDR_DX3DQSTR + >; }; diff --git a/fdts/stm32mp15-ddr3-1x4Gb-1066-binG.dtsi b/fdts/stm32mp15-ddr3-1x4Gb-1066-binG.dtsi index c0fc1f772..c6d6434a9 100644 --- a/fdts/stm32mp15-ddr3-1x4Gb-1066-binG.dtsi +++ b/fdts/stm32mp15-ddr3-1x4Gb-1066-binG.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause /* - * Copyright (C) 2018, STMicroelectronics - All Rights Reserved + * Copyright (c) 2018-2021, STMicroelectronics - All Rights Reserved */ /* @@ -15,7 +15,7 @@ * Save Date: 2020.02.20, save Time: 18:45:20 */ -#define DDR_MEM_NAME "DDR3-DDR3L 16bits 533000Khz" +#define DDR_MEM_NAME "DDR3-DDR3L 16bits 533000kHz" #define DDR_MEM_SPEED 533000 #define DDR_MEM_SIZE 0x20000000 diff --git a/fdts/stm32mp15-ddr3-2x4Gb-1066-binG.dtsi b/fdts/stm32mp15-ddr3-2x4Gb-1066-binG.dtsi index fc226d254..9614ab4c8 100644 --- a/fdts/stm32mp15-ddr3-2x4Gb-1066-binG.dtsi +++ b/fdts/stm32mp15-ddr3-2x4Gb-1066-binG.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause /* - * Copyright (C) 2018, STMicroelectronics - All Rights Reserved + * Copyright (c) 2018-2021, STMicroelectronics - All Rights Reserved */ /* @@ -15,7 +15,7 @@ * Save Date: 2020.02.20, save Time: 18:49:33 */ -#define DDR_MEM_NAME "DDR3-DDR3L 32bits 533000Khz" +#define DDR_MEM_NAME "DDR3-DDR3L 32bits 533000kHz" #define DDR_MEM_SPEED 533000 #define DDR_MEM_SIZE 0x40000000 diff --git a/fdts/stm32mp15-fw-config.dtsi b/fdts/stm32mp15-fw-config.dtsi new file mode 100644 index 000000000..8aece289a --- /dev/null +++ b/fdts/stm32mp15-fw-config.dtsi @@ -0,0 +1,80 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (c) 2021, STMicroelectronics - All Rights Reserved + */ + +#include <common/tbbr/tbbr_img_def.h> +#include <dt-bindings/soc/stm32mp15-tzc400.h> + +#include <platform_def.h> + +#ifndef DDR_SIZE +#error "DDR_SIZE is not defined" +#endif + +#define DDR_NS_BASE STM32MP_DDR_BASE +#ifdef AARCH32_SP_OPTEE +/* OP-TEE reserved shared memory: located at DDR top */ +#define DDR_SHARE_SIZE STM32MP_DDR_SHMEM_SIZE +#define DDR_SHARE_BASE (STM32MP_DDR_BASE + (DDR_SIZE - DDR_SHARE_SIZE)) +/* OP-TEE secure memory: located right below OP-TEE reserved shared memory */ +#define DDR_SEC_SIZE STM32MP_DDR_S_SIZE +#define DDR_SEC_BASE (DDR_SHARE_BASE - DDR_SEC_SIZE) +#define DDR_NS_SIZE (DDR_SEC_BASE - DDR_NS_BASE) +#else /* !AARCH32_SP_OPTEE */ +#define DDR_NS_SIZE DDR_SIZE +#endif /* AARCH32_SP_OPTEE */ + +/dts-v1/; + +/ { + dtb-registry { + compatible = "fconf,dyn_cfg-dtb_registry"; + + hw-config { + load-address = <0x0 STM32MP_HW_CONFIG_BASE>; + max-size = <STM32MP_HW_CONFIG_MAX_SIZE>; + id = <HW_CONFIG_ID>; + }; + + nt_fw { + load-address = <0x0 STM32MP_BL33_BASE>; + max-size = <STM32MP_BL33_MAX_SIZE>; + id = <BL33_IMAGE_ID>; + }; + +#ifdef AARCH32_SP_OPTEE + tos_fw { + load-address = <0x0 STM32MP_OPTEE_BASE>; + max-size = <STM32MP_OPTEE_SIZE>; + id = <BL32_IMAGE_ID>; + }; +#else + tos_fw { + load-address = <0x0 STM32MP_BL32_BASE>; + max-size = <STM32MP_BL32_SIZE>; + id = <BL32_IMAGE_ID>; + }; + + tos_fw-config { + load-address = <0x0 STM32MP_BL32_DTB_BASE>; + max-size = <STM32MP_BL32_DTB_SIZE>; + id = <TOS_FW_CONFIG_ID>; + }; +#endif + }; + + st-mem-firewall { + compatible = "st,mem-firewall"; +#ifdef AARCH32_SP_OPTEE + memory-ranges = < + DDR_NS_BASE DDR_NS_SIZE TZC_REGION_S_NONE TZC_REGION_NSEC_ALL_ACCESS_RDWR + DDR_SEC_BASE DDR_SEC_SIZE TZC_REGION_S_RDWR 0 + DDR_SHARE_BASE DDR_SHARE_SIZE TZC_REGION_S_NONE + TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_A7_ID)>; +#else + memory-ranges = < + DDR_NS_BASE DDR_NS_SIZE TZC_REGION_S_NONE TZC_REGION_NSEC_ALL_ACCESS_RDWR>; +#endif + }; +}; diff --git a/fdts/stm32mp15-pinctrl.dtsi b/fdts/stm32mp15-pinctrl.dtsi index 058cde264..d74dc2b09 100644 --- a/fdts/stm32mp15-pinctrl.dtsi +++ b/fdts/stm32mp15-pinctrl.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) /* - * Copyright (C) STMicroelectronics 2017 - All Rights Reserved + * Copyright (c) 2017-2021, STMicroelectronics - All Rights Reserved * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics. */ #include <dt-bindings/pinctrl/stm32-pinfunc.h> @@ -86,12 +86,6 @@ }; }; - rtc_out2_rmp_pins_a: rtc-out2-rmp-pins-0 { - pins { - pinmux = <STM32_PINMUX('I', 8, ANALOG)>; /* RTC_OUT2_RMP */ - }; - }; - sdmmc1_b4_pins_a: sdmmc1-b4-0 { pins1 { pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */ @@ -176,6 +170,18 @@ }; }; + sdmmc2_d47_pins_b: sdmmc2-d47-1 { + pins { + pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */ + <STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */ + <STM32_PINMUX('C', 6, AF10)>, /* SDMMC2_D6 */ + <STM32_PINMUX('C', 7, AF10)>; /* SDMMC2_D7 */ + slew-rate = <1>; + drive-push-pull; + bias-disable; + }; + }; + sdmmc2_d47_pins_d: sdmmc2-d47-3 { pins { pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */ @@ -213,34 +219,90 @@ uart7_pins_a: uart7-0 { pins1 { - pinmux = <STM32_PINMUX('E', 8, AF7)>; /* UART4_TX */ + pinmux = <STM32_PINMUX('E', 8, AF7)>; /* UART7_TX */ bias-disable; drive-push-pull; slew-rate = <0>; }; pins2 { - pinmux = <STM32_PINMUX('E', 7, AF7)>, /* UART4_RX */ - <STM32_PINMUX('E', 10, AF7)>, /* UART4_CTS */ - <STM32_PINMUX('E', 9, AF7)>; /* UART4_RTS */ + pinmux = <STM32_PINMUX('E', 7, AF7)>, /* UART7_RX */ + <STM32_PINMUX('E', 10, AF7)>, /* UART7_CTS */ + <STM32_PINMUX('E', 9, AF7)>; /* UART7_RTS */ bias-disable; }; }; uart7_pins_b: uart7-1 { pins1 { - pinmux = <STM32_PINMUX('E', 8, AF7)>; /* USART7_TX */ + pinmux = <STM32_PINMUX('F', 7, AF7)>; /* UART7_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = <STM32_PINMUX('F', 6, AF7)>; /* UART7_RX */ + bias-disable; + }; + }; + + uart7_pins_c: uart7-2 { + pins1 { + pinmux = <STM32_PINMUX('E', 8, AF7)>; /* UART7_TX */ bias-disable; drive-push-pull; slew-rate = <0>; }; pins2 { - pinmux = <STM32_PINMUX('E', 7, AF7)>; /* USART7_RX */ + pinmux = <STM32_PINMUX('E', 7, AF7)>; /* UART7_RX */ + bias-disable; + }; + }; + + uart8_pins_a: uart8-0 { + pins1 { + pinmux = <STM32_PINMUX('E', 1, AF8)>; /* UART8_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = <STM32_PINMUX('E', 0, AF8)>; /* UART8_RX */ bias-disable; }; }; usart2_pins_a: usart2-0 { pins1 { + pinmux = <STM32_PINMUX('F', 5, AF7)>, /* USART2_TX */ + <STM32_PINMUX('D', 4, AF7)>; /* USART2_RTS */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = <STM32_PINMUX('D', 6, AF7)>, /* USART2_RX */ + <STM32_PINMUX('D', 3, AF7)>; /* USART2_CTS_NSS */ + bias-disable; + }; + }; + + usart2_pins_b: usart2-1 { + pins1 { + pinmux = <STM32_PINMUX('F', 5, AF7)>, /* USART2_TX */ + <STM32_PINMUX('A', 1, AF7)>; /* USART2_RTS */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = <STM32_PINMUX('F', 4, AF7)>, /* USART2_RX */ + <STM32_PINMUX('E', 15, AF7)>; /* USART2_CTS_NSS */ + bias-disable; + }; + }; + + usart2_pins_c: usart2-2 { + pins1 { pinmux = <STM32_PINMUX('D', 5, AF7)>, /* USART2_TX */ <STM32_PINMUX('D', 4, AF7)>; /* USART2_RTS */ bias-disable; @@ -256,6 +318,19 @@ usart3_pins_a: usart3-0 { pins1 { + pinmux = <STM32_PINMUX('B', 10, AF7)>; /* USART3_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = <STM32_PINMUX('B', 12, AF8)>; /* USART3_RX */ + bias-disable; + }; + }; + + usart3_pins_b: usart3-1 { + pins1 { pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */ <STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */ bias-disable; @@ -269,7 +344,7 @@ }; }; - usart3_pins_b: usart3-1 { + usart3_pins_c: usart3-2 { pins1 { pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */ <STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */ @@ -284,7 +359,7 @@ }; }; - usbotg_hs_pins_a: usbotg_hs-0 { + usbotg_hs_pins_a: usbotg-hs-0 { pins { pinmux = <STM32_PINMUX('A', 10, ANALOG)>; /* OTG_ID */ }; diff --git a/fdts/stm32mp151.dtsi b/fdts/stm32mp151.dtsi index c350c66de..ca93f0c35 100644 --- a/fdts/stm32mp151.dtsi +++ b/fdts/stm32mp151.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) /* - * Copyright (C) STMicroelectronics 2017 - All Rights Reserved + * Copyright (c) 2017-2021, STMicroelectronics - All Rights Reserved * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics. */ #include <dt-bindings/interrupt-controller/arm-gic.h> @@ -174,7 +174,7 @@ }; usbotg_hs: usb-otg@49000000 { - compatible = "st,stm32mp1-hsotg", "snps,dwc2"; + compatible = "st,stm32mp15-hsotg", "snps,dwc2"; reg = <0x49000000 0x10000>; clocks = <&rcc USBO_K>; clock-names = "otg"; @@ -319,7 +319,7 @@ status = "disabled"; }; - sdmmc1: sdmmc@58005000 { + sdmmc1: mmc@58005000 { compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; arm,primecell-periphid = <0x00253180>; reg = <0x58005000 0x1000>, <0x58006000 0x1000>; @@ -334,7 +334,7 @@ status = "disabled"; }; - sdmmc2: sdmmc@58007000 { + sdmmc2: mmc@58007000 { compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; arm,primecell-periphid = <0x00253180>; reg = <0x58007000 0x1000>, <0x58008000 0x1000>; @@ -358,6 +358,24 @@ status = "disabled"; }; + ddr: ddr@5a003000{ + compatible = "st,stm32mp1-ddr"; + reg = <0x5A003000 0x550 0x5A004000 0x234>; + clocks = <&rcc AXIDCG>, + <&rcc DDRC1>, + <&rcc DDRC2>, + <&rcc DDRPHYC>, + <&rcc DDRCAPB>, + <&rcc DDRPHYCAPB>; + clock-names = "axidcg", + "ddrc1", + "ddrc2", + "ddrphyc", + "ddrcapb", + "ddrphycapb"; + status = "okay"; + }; + usbphyc: usbphyc@5a006000 { #address-cells = <1>; #size-cells = <0>; @@ -434,7 +452,7 @@ status = "disabled"; }; - bsec: nvmem@5c005000 { + bsec: efuse@5c005000 { compatible = "st,stm32mp15-bsec"; reg = <0x5c005000 0x400>; #address-cells = <1>; diff --git a/fdts/stm32mp157a-avenger96-fw-config.dts b/fdts/stm32mp157a-avenger96-fw-config.dts new file mode 100644 index 000000000..2abbe50e6 --- /dev/null +++ b/fdts/stm32mp157a-avenger96-fw-config.dts @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (c) 2020-2021, STMicroelectronics - All Rights Reserved + */ + +#define DDR_SIZE 0x40000000 /* 1GB */ +#include "stm32mp15-fw-config.dtsi" diff --git a/fdts/stm32mp157a-dk1-fw-config.dts b/fdts/stm32mp157a-dk1-fw-config.dts new file mode 100644 index 000000000..83116d103 --- /dev/null +++ b/fdts/stm32mp157a-dk1-fw-config.dts @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (c) 2020-2021, STMicroelectronics - All Rights Reserved + */ + +#define DDR_SIZE 0x20000000 /* 512MB */ +#include "stm32mp15-fw-config.dtsi" diff --git a/fdts/stm32mp157a-ed1-fw-config.dts b/fdts/stm32mp157a-ed1-fw-config.dts new file mode 100644 index 000000000..2abbe50e6 --- /dev/null +++ b/fdts/stm32mp157a-ed1-fw-config.dts @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (c) 2020-2021, STMicroelectronics - All Rights Reserved + */ + +#define DDR_SIZE 0x40000000 /* 1GB */ +#include "stm32mp15-fw-config.dtsi" diff --git a/fdts/stm32mp157a-ev1-fw-config.dts b/fdts/stm32mp157a-ev1-fw-config.dts new file mode 100644 index 000000000..2abbe50e6 --- /dev/null +++ b/fdts/stm32mp157a-ev1-fw-config.dts @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (c) 2020-2021, STMicroelectronics - All Rights Reserved + */ + +#define DDR_SIZE 0x40000000 /* 1GB */ +#include "stm32mp15-fw-config.dtsi" diff --git a/fdts/stm32mp157c-dk2-fw-config.dts b/fdts/stm32mp157c-dk2-fw-config.dts new file mode 100644 index 000000000..83116d103 --- /dev/null +++ b/fdts/stm32mp157c-dk2-fw-config.dts @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (c) 2020-2021, STMicroelectronics - All Rights Reserved + */ + +#define DDR_SIZE 0x20000000 /* 512MB */ +#include "stm32mp15-fw-config.dtsi" diff --git a/fdts/stm32mp157c-ed1-fw-config.dts b/fdts/stm32mp157c-ed1-fw-config.dts new file mode 100644 index 000000000..2abbe50e6 --- /dev/null +++ b/fdts/stm32mp157c-ed1-fw-config.dts @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (c) 2020-2021, STMicroelectronics - All Rights Reserved + */ + +#define DDR_SIZE 0x40000000 /* 1GB */ +#include "stm32mp15-fw-config.dtsi" diff --git a/fdts/stm32mp157c-ed1.dts b/fdts/stm32mp157c-ed1.dts index a6b98b7d9..11e0a6111 100644 --- a/fdts/stm32mp157c-ed1.dts +++ b/fdts/stm32mp157c-ed1.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) /* - * Copyright (C) STMicroelectronics 2017-2019 - All Rights Reserved + * Copyright (c) 2017-2021, STMicroelectronics - All Rights Reserved * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics. */ /dts-v1/; @@ -20,7 +20,6 @@ stdout-path = "serial0:115200n8"; }; - memory@c0000000 { device_type = "memory"; reg = <0xC0000000 0x40000000>; @@ -52,7 +51,7 @@ }; &cryp1 { - status="okay"; + status = "okay"; }; &hash1 { @@ -233,7 +232,7 @@ CLK_CKPER_HSE CLK_FMC_ACLK CLK_QSPI_ACLK - CLK_ETH_DISABLED + CLK_ETH_PLL4P CLK_SDMMC12_PLL4P CLK_DSI_DSIPLL CLK_STGEN_HSE @@ -269,25 +268,33 @@ /* VCO = 1300.0 MHz => P = 650 (CPU) */ pll1: st,pll@0 { - cfg = < 2 80 0 0 0 PQR(1,0,0) >; - frac = < 0x800 >; + compatible = "st,stm32mp1-pll"; + reg = <0>; + cfg = <2 80 0 0 0 PQR(1,0,0)>; + frac = <0x800>; }; /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */ pll2: st,pll@1 { - cfg = < 2 65 1 0 0 PQR(1,1,1) >; - frac = < 0x1400 >; + compatible = "st,stm32mp1-pll"; + reg = <1>; + cfg = <2 65 1 0 0 PQR(1,1,1)>; + frac = <0x1400>; }; /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */ pll3: st,pll@2 { - cfg = < 1 33 1 16 36 PQR(1,1,1) >; - frac = < 0x1a04 >; + compatible = "st,stm32mp1-pll"; + reg = <2>; + cfg = <1 33 1 16 36 PQR(1,1,1)>; + frac = <0x1a04>; }; /* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */ pll4: st,pll@3 { - cfg = < 3 98 5 7 7 PQR(1,1,1) >; + compatible = "st,stm32mp1-pll"; + reg = <3>; + cfg = <3 98 5 7 7 PQR(1,1,1)>; }; }; diff --git a/fdts/stm32mp157c-ev1-fw-config.dts b/fdts/stm32mp157c-ev1-fw-config.dts new file mode 100644 index 000000000..2abbe50e6 --- /dev/null +++ b/fdts/stm32mp157c-ev1-fw-config.dts @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (c) 2020-2021, STMicroelectronics - All Rights Reserved + */ + +#define DDR_SIZE 0x40000000 /* 1GB */ +#include "stm32mp15-fw-config.dtsi" diff --git a/fdts/stm32mp157c-ev1.dts b/fdts/stm32mp157c-ev1.dts index c5d12e3b2..02840a2e5 100644 --- a/fdts/stm32mp157c-ev1.dts +++ b/fdts/stm32mp157c-ev1.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) /* - * Copyright (C) STMicroelectronics 2017-2019 - All Rights Reserved + * Copyright (c) 2017-2021, STMicroelectronics - All Rights Reserved * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics. */ /dts-v1/; @@ -57,6 +57,7 @@ &usart3 { pinctrl-names = "default"; - pinctrl-0 = <&usart3_pins_a>; + pinctrl-0 = <&usart3_pins_b>; + uart-has-rtscts; status = "disabled"; }; diff --git a/fdts/stm32mp157c-lxa-mc1-fw-config.dts b/fdts/stm32mp157c-lxa-mc1-fw-config.dts new file mode 100644 index 000000000..9ee09e93e --- /dev/null +++ b/fdts/stm32mp157c-lxa-mc1-fw-config.dts @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (c) 2021, STMicroelectronics - All Rights Reserved + */ + +#define DDR_SIZE 0x20000000 /* 512MB */ +#include "stm32mp15-fw-config.dtsi" diff --git a/fdts/stm32mp157c-lxa-mc1.dts b/fdts/stm32mp157c-lxa-mc1.dts index 7b8e48127..6f677123a 100644 --- a/fdts/stm32mp157c-lxa-mc1.dts +++ b/fdts/stm32mp157c-lxa-mc1.dts @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) */ /* - * Copyright (C) 2020 STMicroelectronics - All Rights Reserved + * Copyright (c) 2020-2021, STMicroelectronics - All Rights Reserved * Copyright (C) 2020 Ahmad Fatoum, Pengutronix */ @@ -75,7 +75,7 @@ &sdmmc2 { pinctrl-names = "default"; - pinctrl-0 = <&sdmmc2_b4_pins_a &mc1_sdmmc2_d47_pins_b>; + pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_b>; bus-width = <8>; no-1-8-v; no-sd; @@ -91,17 +91,3 @@ pinctrl-0 = <&uart4_pins_a>; status = "okay"; }; - -&pinctrl { - mc1_sdmmc2_d47_pins_b: mc1-sdmmc2-d47-1 { - pins { - pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */ - <STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */ - <STM32_PINMUX('C', 6, AF10)>, /* SDMMC2_D6 */ - <STM32_PINMUX('C', 7, AF10)>; /* SDMMC2_D7 */ - slew-rate = <1>; - drive-push-pull; - bias-disable; - }; - }; -}; diff --git a/fdts/stm32mp157c-odyssey-fw-config.dts b/fdts/stm32mp157c-odyssey-fw-config.dts new file mode 100644 index 000000000..9ee09e93e --- /dev/null +++ b/fdts/stm32mp157c-odyssey-fw-config.dts @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (c) 2021, STMicroelectronics - All Rights Reserved + */ + +#define DDR_SIZE 0x20000000 /* 512MB */ +#include "stm32mp15-fw-config.dtsi" diff --git a/fdts/stm32mp157d-dk1-fw-config.dts b/fdts/stm32mp157d-dk1-fw-config.dts new file mode 100644 index 000000000..83116d103 --- /dev/null +++ b/fdts/stm32mp157d-dk1-fw-config.dts @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (c) 2020-2021, STMicroelectronics - All Rights Reserved + */ + +#define DDR_SIZE 0x20000000 /* 512MB */ +#include "stm32mp15-fw-config.dtsi" diff --git a/fdts/stm32mp157d-ed1-fw-config.dts b/fdts/stm32mp157d-ed1-fw-config.dts new file mode 100644 index 000000000..2abbe50e6 --- /dev/null +++ b/fdts/stm32mp157d-ed1-fw-config.dts @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (c) 2020-2021, STMicroelectronics - All Rights Reserved + */ + +#define DDR_SIZE 0x40000000 /* 1GB */ +#include "stm32mp15-fw-config.dtsi" diff --git a/fdts/stm32mp157d-ev1-fw-config.dts b/fdts/stm32mp157d-ev1-fw-config.dts new file mode 100644 index 000000000..2abbe50e6 --- /dev/null +++ b/fdts/stm32mp157d-ev1-fw-config.dts @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (c) 2020-2021, STMicroelectronics - All Rights Reserved + */ + +#define DDR_SIZE 0x40000000 /* 1GB */ +#include "stm32mp15-fw-config.dtsi" diff --git a/fdts/stm32mp157f-dk2-fw-config.dts b/fdts/stm32mp157f-dk2-fw-config.dts new file mode 100644 index 000000000..83116d103 --- /dev/null +++ b/fdts/stm32mp157f-dk2-fw-config.dts @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (c) 2020-2021, STMicroelectronics - All Rights Reserved + */ + +#define DDR_SIZE 0x20000000 /* 512MB */ +#include "stm32mp15-fw-config.dtsi" diff --git a/fdts/stm32mp157f-ed1-fw-config.dts b/fdts/stm32mp157f-ed1-fw-config.dts new file mode 100644 index 000000000..2abbe50e6 --- /dev/null +++ b/fdts/stm32mp157f-ed1-fw-config.dts @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (c) 2020-2021, STMicroelectronics - All Rights Reserved + */ + +#define DDR_SIZE 0x40000000 /* 1GB */ +#include "stm32mp15-fw-config.dtsi" diff --git a/fdts/stm32mp157f-ev1-fw-config.dts b/fdts/stm32mp157f-ev1-fw-config.dts new file mode 100644 index 000000000..2abbe50e6 --- /dev/null +++ b/fdts/stm32mp157f-ev1-fw-config.dts @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (c) 2020-2021, STMicroelectronics - All Rights Reserved + */ + +#define DDR_SIZE 0x40000000 /* 1GB */ +#include "stm32mp15-fw-config.dtsi" diff --git a/fdts/stm32mp15xx-dkx.dtsi b/fdts/stm32mp15xx-dkx.dtsi index 52b914b84..9cc5368d8 100644 --- a/fdts/stm32mp15xx-dkx.dtsi +++ b/fdts/stm32mp15xx-dkx.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) /* - * Copyright (C) STMicroelectronics 2019 - All Rights Reserved + * Copyright (c) 2019-2021, STMicroelectronics - All Rights Reserved * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics. */ @@ -141,7 +141,6 @@ regulator-name = "vdd_usb"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - regulator-always-on; }; vdda: ldo5 { @@ -223,7 +222,7 @@ CLK_CKPER_HSE CLK_FMC_ACLK CLK_QSPI_ACLK - CLK_ETH_DISABLED + CLK_ETH_PLL4P CLK_SDMMC12_PLL4P CLK_DSI_DSIPLL CLK_STGEN_HSE @@ -319,13 +318,13 @@ &uart7 { pinctrl-names = "default"; - pinctrl-0 = <&uart7_pins_b>; + pinctrl-0 = <&uart7_pins_c>; status = "disabled"; }; &usart3 { pinctrl-names = "default"; - pinctrl-0 = <&usart3_pins_b>; + pinctrl-0 = <&usart3_pins_c>; uart-has-rtscts; status = "disabled"; }; diff --git a/fdts/stm32mp15xxaa-pinctrl.dtsi b/fdts/stm32mp15xxaa-pinctrl.dtsi index 64e566bf8..f1d540abe 100644 --- a/fdts/stm32mp15xxaa-pinctrl.dtsi +++ b/fdts/stm32mp15xxaa-pinctrl.dtsi @@ -1,7 +1,7 @@ // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) /* - * Copyright (C) STMicroelectronics 2019 - All Rights Reserved - * Author: Alexandre Torgue <alexandre.torgue@st.com> + * Copyright (c) 2019-2021, STMicroelectronics - All Rights Reserved + * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics. */ &pinctrl { diff --git a/fdts/stm32mp15xxab-pinctrl.dtsi b/fdts/stm32mp15xxab-pinctrl.dtsi index d29af8986..b58c7e2bf 100644 --- a/fdts/stm32mp15xxab-pinctrl.dtsi +++ b/fdts/stm32mp15xxab-pinctrl.dtsi @@ -1,7 +1,7 @@ // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) /* - * Copyright (C) STMicroelectronics 2019 - All Rights Reserved - * Author: Alexandre Torgue <alexandre.torgue@st.com> + * Copyright (c) 2019-2021, STMicroelectronics - All Rights Reserved + * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics. */ &pinctrl { diff --git a/fdts/stm32mp15xxac-pinctrl.dtsi b/fdts/stm32mp15xxac-pinctrl.dtsi index 5d8199fd1..11e7e0344 100644 --- a/fdts/stm32mp15xxac-pinctrl.dtsi +++ b/fdts/stm32mp15xxac-pinctrl.dtsi @@ -1,7 +1,7 @@ // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) /* - * Copyright (C) STMicroelectronics 2019 - All Rights Reserved - * Author: Alexandre Torgue <alexandre.torgue@st.com> + * Copyright (c) 2019-2021, STMicroelectronics - All Rights Reserved + * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics. */ &pinctrl { diff --git a/fdts/stm32mp15xxad-pinctrl.dtsi b/fdts/stm32mp15xxad-pinctrl.dtsi index 023f5404c..52806d61c 100644 --- a/fdts/stm32mp15xxad-pinctrl.dtsi +++ b/fdts/stm32mp15xxad-pinctrl.dtsi @@ -1,7 +1,7 @@ // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) /* - * Copyright (C) STMicroelectronics 2019 - All Rights Reserved - * Author: Alexandre Torgue <alexandre.torgue@st.com> + * Copyright (c) 2019-2021, STMicroelectronics - All Rights Reserved + * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics. */ &pinctrl { diff --git a/fdts/tc.dts b/fdts/tc.dts index f66d55670..13c9e16e4 100644 --- a/fdts/tc.dts +++ b/fdts/tc.dts @@ -79,6 +79,31 @@ }; }; + amus { + amu: amu-0 { + #address-cells = <1>; + #size-cells = <0>; + + mpmm_gear0: counter@0 { + reg = <0>; + + enable-at-el3; + }; + + mpmm_gear1: counter@1 { + reg = <1>; + + enable-at-el3; + }; + + mpmm_gear2: counter@2 { + reg = <2>; + + enable-at-el3; + }; + }; + }; + CPU0:cpu@0 { device_type = "cpu"; compatible = "arm,armv8"; @@ -87,6 +112,8 @@ clocks = <&scmi_dvfs 0>; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; capacity-dmips-mhz = <406>; + amu = <&amu>; + supports-mpmm; }; CPU1:cpu@100 { @@ -97,6 +124,8 @@ clocks = <&scmi_dvfs 0>; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; capacity-dmips-mhz = <406>; + amu = <&amu>; + supports-mpmm; }; CPU2:cpu@200 { @@ -107,6 +136,8 @@ clocks = <&scmi_dvfs 0>; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; capacity-dmips-mhz = <406>; + amu = <&amu>; + supports-mpmm; }; CPU3:cpu@300 { @@ -117,6 +148,8 @@ clocks = <&scmi_dvfs 0>; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; capacity-dmips-mhz = <406>; + amu = <&amu>; + supports-mpmm; }; CPU4:cpu@400 { @@ -127,6 +160,8 @@ clocks = <&scmi_dvfs 1>; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; capacity-dmips-mhz = <912>; + amu = <&amu>; + supports-mpmm; }; CPU5:cpu@500 { @@ -137,6 +172,8 @@ clocks = <&scmi_dvfs 1>; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; capacity-dmips-mhz = <912>; + amu = <&amu>; + supports-mpmm; }; CPU6:cpu@600 { @@ -147,6 +184,8 @@ clocks = <&scmi_dvfs 1>; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; capacity-dmips-mhz = <912>; + amu = <&amu>; + supports-mpmm; }; CPU7:cpu@700 { @@ -157,15 +196,12 @@ clocks = <&scmi_dvfs 2>; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; capacity-dmips-mhz = <1024>; + amu = <&amu>; + supports-mpmm; }; }; - memory@80000000 { - device_type = "memory"; - reg = <0x0 0x80000000 0x0 0x7d000000>; - }; - reserved-memory { #address-cells = <2>; #size-cells = <2>; |