diff options
Diffstat (limited to 'include/arch/aarch64/el3_common_macros.S')
| -rw-r--r-- | include/arch/aarch64/el3_common_macros.S | 24 |
1 files changed, 18 insertions, 6 deletions
diff --git a/include/arch/aarch64/el3_common_macros.S b/include/arch/aarch64/el3_common_macros.S index f75998351..973433575 100644 --- a/include/arch/aarch64/el3_common_macros.S +++ b/include/arch/aarch64/el3_common_macros.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -113,8 +113,13 @@ * * MDCR_EL3.SCCD: Set to one so that cycle counting by PMCCNTR_EL0 is * prohibited in Secure state. This bit is RES0 in versions of the - * architecture earlier than ARMv8.5, setting it to 1 doesn't have any - * effect on them. + * architecture with FEAT_PMUv3p5 not implemented, setting it to 1 + * doesn't have any effect on them. + * + * MDCR_EL3.MCCD: Set to one so that cycle counting by PMCCNTR_EL0 is + * prohibited in EL3. This bit is RES0 in versions of the + * architecture with FEAT_PMUv3p7 not implemented, setting it to 1 + * doesn't have any effect on them. * * MDCR_EL3.SPME: Set to zero so that event counting by the programmable * counters PMEVCNTR<n>_EL0 is prohibited in Secure state. If ARMv8.2 @@ -124,9 +129,9 @@ * --------------------------------------------------------------------- */ mov_imm x0, ((MDCR_EL3_RESET_VAL | MDCR_SDD_BIT | \ - MDCR_SPD32(MDCR_SPD32_DISABLE) | MDCR_SCCD_BIT) & \ - ~(MDCR_SPME_BIT | MDCR_TDOSA_BIT | MDCR_TDA_BIT | \ - MDCR_TPM_BIT)) + MDCR_SPD32(MDCR_SPD32_DISABLE) | MDCR_SCCD_BIT | \ + MDCR_MCCD_BIT) & ~(MDCR_SPME_BIT | MDCR_TDOSA_BIT | \ + MDCR_TDA_BIT | MDCR_TPM_BIT)) msr mdcr_el3, x0 @@ -180,7 +185,14 @@ * CPTR_EL3.TFP: Set to zero so that accesses to the V- or Z- registers * by Advanced SIMD, floating-point or SVE instructions (if implemented) * do not trap to EL3. + * + * CPTR_EL3.TAM: Set to one so that Activity Monitor access is + * trapped to EL3 by default. + * + * CPTR_EL3.EZ: Set to zero so that all SVE functionality is trapped + * to EL3 by default. */ + mov_imm x0, (CPTR_EL3_RESET_VAL & ~(TCPAC_BIT | TTA_BIT | TFP_BIT)) msr cptr_el3, x0 |