diff options
Diffstat (limited to 'include/lib/cpus')
| -rw-r--r-- | include/lib/cpus/aarch64/cortex_a710.h | 18 | ||||
| -rw-r--r-- | include/lib/cpus/aarch64/cortex_a78.h | 3 | ||||
| -rw-r--r-- | include/lib/cpus/aarch64/cortex_hayes.h (renamed from include/lib/cpus/aarch64/cortex_demeter.h) | 14 | ||||
| -rw-r--r-- | include/lib/cpus/aarch64/cortex_hunter.h | 23 | ||||
| -rw-r--r-- | include/lib/cpus/aarch64/neoverse_demeter.h | 23 | ||||
| -rw-r--r-- | include/lib/cpus/aarch64/neoverse_n2.h | 35 | ||||
| -rw-r--r-- | include/lib/cpus/aarch64/neoverse_v1.h | 3 |
7 files changed, 98 insertions, 21 deletions
diff --git a/include/lib/cpus/aarch64/cortex_a710.h b/include/lib/cpus/aarch64/cortex_a710.h index 8b011aaea..d2bc146d9 100644 --- a/include/lib/cpus/aarch64/cortex_a710.h +++ b/include/lib/cpus/aarch64/cortex_a710.h @@ -13,7 +13,7 @@ * CPU Extended Control register specific definitions ******************************************************************************/ #define CORTEX_A710_CPUECTLR_EL1 S3_0_C15_C1_4 -#define CORTEX_A710_CPUECTLR_EL1_PFSTIDIS_BIT (ULL(1) << 8) +#define CORTEX_A710_CPUECTLR_EL1_PFSTIDIS_BIT (ULL(1) << 8) /******************************************************************************* * CPU Power Control register specific definitions @@ -25,6 +25,20 @@ * CPU Auxiliary Control register specific definitions. ******************************************************************************/ #define CORTEX_A710_CPUACTLR_EL1 S3_0_C15_C1_0 -#define CORTEX_A710_CPUACTLR_EL1_BIT_46 (ULL(1) << 46) +#define CORTEX_A710_CPUACTLR_EL1_BIT_46 (ULL(1) << 46) + +/******************************************************************************* + * CPU Auxiliary Control register specific definitions. + ******************************************************************************/ +#define CORTEX_A710_CPUACTLR5_EL1 S3_0_C15_C8_0 +#define CORTEX_A710_CPUACTLR5_EL1_BIT_13 (ULL(1) << 13) + +/******************************************************************************* + * CPU Auxiliary Control register specific definitions. + ******************************************************************************/ +#define CORTEX_A710_CPUECTLR2_EL1 S3_0_C15_C1_5 +#define CORTEX_A710_CPUECTLR2_EL1_PF_MODE_CNSRV ULL(9) +#define CPUECTLR2_EL1_PF_MODE_LSB U(11) +#define CPUECTLR2_EL1_PF_MODE_WIDTH U(4) #endif /* CORTEX_A710_H */ diff --git a/include/lib/cpus/aarch64/cortex_a78.h b/include/lib/cpus/aarch64/cortex_a78.h index 4bc49f303..42b08336d 100644 --- a/include/lib/cpus/aarch64/cortex_a78.h +++ b/include/lib/cpus/aarch64/cortex_a78.h @@ -16,6 +16,9 @@ ******************************************************************************/ #define CORTEX_A78_CPUECTLR_EL1 S3_0_C15_C1_4 #define CORTEX_A78_CPUECTLR_EL1_BIT_8 (ULL(1) << 8) +#define CORTEX_A78_CPUECTLR_EL1_PF_MODE_CNSRV ULL(3) +#define CPUECTLR_EL1_PF_MODE_LSB U(6) +#define CPUECTLR_EL1_PF_MODE_WIDTH U(2) /******************************************************************************* * CPU Power Control register specific definitions diff --git a/include/lib/cpus/aarch64/cortex_demeter.h b/include/lib/cpus/aarch64/cortex_hayes.h index 9dd0987ab..82022e9ff 100644 --- a/include/lib/cpus/aarch64/cortex_demeter.h +++ b/include/lib/cpus/aarch64/cortex_hayes.h @@ -4,20 +4,20 @@ * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef CORTEX_DEMETER_H -#define CORTEX_DEMETER_H +#ifndef CORTEX_HAYES_H +#define CORTEX_HAYES_H -#define CORTEX_DEMETER_MIDR U(0x410FD4F0) +#define CORTEX_HAYES_MIDR U(0x410FD800) /******************************************************************************* * CPU Extended Control register specific definitions ******************************************************************************/ -#define CORTEX_DEMETER_CPUECTLR_EL1 S3_0_C15_C1_4 +#define CORTEX_HAYES_CPUECTLR_EL1 S3_0_C15_C1_4 /******************************************************************************* * CPU Power Control register specific definitions ******************************************************************************/ -#define CORTEX_DEMETER_CPUPWRCTLR_EL1 S3_0_C15_C2_7 -#define CORTEX_DEMETER_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) +#define CORTEX_HAYES_CPUPWRCTLR_EL1 S3_0_C15_C2_7 +#define CORTEX_HAYES_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) -#endif /* CORTEX_DEMETER_H */ +#endif /* CORTEX_HAYES_H */ diff --git a/include/lib/cpus/aarch64/cortex_hunter.h b/include/lib/cpus/aarch64/cortex_hunter.h new file mode 100644 index 000000000..8b59fd9ea --- /dev/null +++ b/include/lib/cpus/aarch64/cortex_hunter.h @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2021, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef CORTEX_HUNTER_H +#define CORTEX_HUNTER_H + +#define CORTEX_HUNTER_MIDR U(0x410FD810) + +/******************************************************************************* + * CPU Extended Control register specific definitions + ******************************************************************************/ +#define CORTEX_HUNTER_CPUECTLR_EL1 S3_0_C15_C1_4 + +/******************************************************************************* + * CPU Power Control register specific definitions + ******************************************************************************/ +#define CORTEX_HUNTER_CPUPWRCTLR_EL1 S3_0_C15_C2_7 +#define CORTEX_HUNTER_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) + +#endif /* CORTEX_HUNTER_H */ diff --git a/include/lib/cpus/aarch64/neoverse_demeter.h b/include/lib/cpus/aarch64/neoverse_demeter.h new file mode 100644 index 000000000..230ed6651 --- /dev/null +++ b/include/lib/cpus/aarch64/neoverse_demeter.h @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2021, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef NEOVERSE_DEMETER_H +#define NEOVERSE_DEMETER_H + +#define NEOVERSE_DEMETER_MIDR U(0x410FD4F0) + +/******************************************************************************* + * CPU Extended Control register specific definitions + ******************************************************************************/ +#define NEOVERSE_DEMETER_CPUECTLR_EL1 S3_0_C15_C1_4 + +/******************************************************************************* + * CPU Power Control register specific definitions + ******************************************************************************/ +#define NEOVERSE_DEMETER_CPUPWRCTLR_EL1 S3_0_C15_C2_7 +#define NEOVERSE_DEMETER_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) + +#endif /* NEOVERSE_DEMETER_H */ diff --git a/include/lib/cpus/aarch64/neoverse_n2.h b/include/lib/cpus/aarch64/neoverse_n2.h index 948f96511..a1e676ec2 100644 --- a/include/lib/cpus/aarch64/neoverse_n2.h +++ b/include/lib/cpus/aarch64/neoverse_n2.h @@ -8,37 +8,48 @@ #define NEOVERSE_N2_H /* Neoverse N2 ID register for revision r0p0 */ -#define NEOVERSE_N2_MIDR U(0x410FD490) +#define NEOVERSE_N2_MIDR U(0x410FD490) /******************************************************************************* * CPU Power control register ******************************************************************************/ -#define NEOVERSE_N2_CPUPWRCTLR_EL1 S3_0_C15_C2_7 -#define NEOVERSE_N2_CORE_PWRDN_EN_BIT (ULL(1) << 0) +#define NEOVERSE_N2_CPUPWRCTLR_EL1 S3_0_C15_C2_7 +#define NEOVERSE_N2_CORE_PWRDN_EN_BIT (ULL(1) << 0) /******************************************************************************* * CPU Extended Control register specific definitions. ******************************************************************************/ -#define NEOVERSE_N2_CPUECTLR_EL1 S3_0_C15_C1_4 -#define NEOVERSE_N2_CPUECTLR_EL1_EXTLLC_BIT (ULL(1) << 0) -#define NEOVERSE_N2_CPUECTLR_EL1_PFSTIDIS_BIT (ULL(1) << 8) +#define NEOVERSE_N2_CPUECTLR_EL1 S3_0_C15_C1_4 +#define NEOVERSE_N2_CPUECTLR_EL1_EXTLLC_BIT (ULL(1) << 0) +#define NEOVERSE_N2_CPUECTLR_EL1_PFSTIDIS_BIT (ULL(1) << 8) /******************************************************************************* * CPU Auxiliary Control register specific definitions. ******************************************************************************/ -#define NEOVERSE_N2_CPUACTLR_EL1 S3_0_C15_C1_0 -#define NEOVERSE_N2_CPUACTLR_EL1_BIT_46 (ULL(1) << 46) +#define NEOVERSE_N2_CPUACTLR_EL1 S3_0_C15_C1_0 +#define NEOVERSE_N2_CPUACTLR_EL1_BIT_46 (ULL(1) << 46) +#define NEOVERSE_N2_CPUACTLR_EL1_BIT_22 (ULL(1) << 22) /******************************************************************************* * CPU Auxiliary Control register 2 specific definitions. ******************************************************************************/ -#define NEOVERSE_N2_CPUACTLR2_EL1 S3_0_C15_C1_1 -#define NEOVERSE_N2_CPUACTLR2_EL1_BIT_2 (ULL(1) << 2) +#define NEOVERSE_N2_CPUACTLR2_EL1 S3_0_C15_C1_1 +#define NEOVERSE_N2_CPUACTLR2_EL1_BIT_2 (ULL(1) << 2) /******************************************************************************* * CPU Auxiliary Control register 5 specific definitions. ******************************************************************************/ -#define NEOVERSE_N2_CPUACTLR5_EL1 S3_0_C15_C8_0 -#define NEOVERSE_N2_CPUACTLR5_EL1_BIT_44 (ULL(1) << 44) +#define NEOVERSE_N2_CPUACTLR5_EL1 S3_0_C15_C8_0 +#define NEOVERSE_N2_CPUACTLR5_EL1_BIT_44 (ULL(1) << 44) +#define NEOVERSE_N2_CPUACTLR5_EL1_BIT_13 (ULL(1) << 13) +#define NEOVERSE_N2_CPUACTLR5_EL1_BIT_17 (ULL(1) << 17) + +/******************************************************************************* + * CPU Auxiliary Control register specific definitions. + ******************************************************************************/ +#define NEOVERSE_N2_CPUECTLR2_EL1 S3_0_C15_C1_5 +#define NEOVERSE_N2_CPUECTLR2_EL1_PF_MODE_CNSRV ULL(9) +#define CPUECTLR2_EL1_PF_MODE_LSB U(11) +#define CPUECTLR2_EL1_PF_MODE_WIDTH U(4) #endif /* NEOVERSE_N2_H */ diff --git a/include/lib/cpus/aarch64/neoverse_v1.h b/include/lib/cpus/aarch64/neoverse_v1.h index cfb26ab61..e43c90798 100644 --- a/include/lib/cpus/aarch64/neoverse_v1.h +++ b/include/lib/cpus/aarch64/neoverse_v1.h @@ -15,6 +15,9 @@ #define NEOVERSE_V1_CPUECTLR_EL1 S3_0_C15_C1_4 #define NEOVERSE_V1_CPUECTLR_EL1_BIT_8 (ULL(1) << 8) #define NEOVERSE_V1_CPUECTLR_EL1_BIT_53 (ULL(1) << 53) +#define NEOVERSE_V1_CPUECTLR_EL1_PF_MODE_CNSRV ULL(3) +#define CPUECTLR_EL1_PF_MODE_LSB U(6) +#define CPUECTLR_EL1_PF_MODE_WIDTH U(2) /******************************************************************************* * CPU Power Control register specific definitions |