diff options
Diffstat (limited to 'include/plat/arm')
| -rw-r--r-- | include/plat/arm/board/common/v2m_def.h | 29 | ||||
| -rw-r--r-- | include/plat/arm/board/fvp_r/fvp_r_bl1.h | 13 | ||||
| -rw-r--r-- | include/plat/arm/common/arm_def.h | 244 | ||||
| -rw-r--r-- | include/plat/arm/common/arm_dyn_cfg_helpers.h | 6 | ||||
| -rw-r--r-- | include/plat/arm/common/arm_pas_def.h | 94 | ||||
| -rw-r--r-- | include/plat/arm/common/fconf_ethosn_getter.h | 9 | ||||
| -rw-r--r-- | include/plat/arm/common/plat_arm.h | 25 |
7 files changed, 335 insertions, 85 deletions
diff --git a/include/plat/arm/board/common/v2m_def.h b/include/plat/arm/board/common/v2m_def.h index 6a6979c9c..cb11dac47 100644 --- a/include/plat/arm/board/common/v2m_def.h +++ b/include/plat/arm/board/common/v2m_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -8,6 +8,13 @@ #include <lib/utils_def.h> +/* Base address of all V2M */ +#ifdef PLAT_V2M_OFFSET +#define V2M_OFFSET PLAT_V2M_OFFSET +#else +#define V2M_OFFSET UL(0) +#endif + /* V2M motherboard system registers & offsets */ #define V2M_SYSREGS_BASE UL(0x1c010000) #define V2M_SYS_ID UL(0x0) @@ -69,18 +76,18 @@ /* NOR Flash */ -#define V2M_FLASH0_BASE UL(0x08000000) +#define V2M_FLASH0_BASE (V2M_OFFSET + UL(0x08000000)) #define V2M_FLASH0_SIZE UL(0x04000000) -#define V2M_FLASH_BLOCK_SIZE UL(0x00040000) /* 256 KB */ +#define V2M_FLASH_BLOCK_SIZE UL(0x00040000) /* 256 KB */ -#define V2M_IOFPGA_BASE UL(0x1c000000) +#define V2M_IOFPGA_BASE (V2M_OFFSET + UL(0x1c000000)) #define V2M_IOFPGA_SIZE UL(0x03000000) /* PL011 UART related constants */ -#define V2M_IOFPGA_UART0_BASE UL(0x1c090000) -#define V2M_IOFPGA_UART1_BASE UL(0x1c0a0000) -#define V2M_IOFPGA_UART2_BASE UL(0x1c0b0000) -#define V2M_IOFPGA_UART3_BASE UL(0x1c0c0000) +#define V2M_IOFPGA_UART0_BASE (V2M_OFFSET + UL(0x1c090000)) +#define V2M_IOFPGA_UART1_BASE (V2M_OFFSET + UL(0x1c0a0000)) +#define V2M_IOFPGA_UART2_BASE (V2M_OFFSET + UL(0x1c0b0000)) +#define V2M_IOFPGA_UART3_BASE (V2M_OFFSET + UL(0x1c0c0000)) #define V2M_IOFPGA_UART0_CLK_IN_HZ 24000000 #define V2M_IOFPGA_UART1_CLK_IN_HZ 24000000 @@ -88,11 +95,11 @@ #define V2M_IOFPGA_UART3_CLK_IN_HZ 24000000 /* SP804 timer related constants */ -#define V2M_SP804_TIMER0_BASE UL(0x1C110000) -#define V2M_SP804_TIMER1_BASE UL(0x1C120000) +#define V2M_SP804_TIMER0_BASE (V2M_OFFSET + UL(0x1C110000)) +#define V2M_SP804_TIMER1_BASE (V2M_OFFSET + UL(0x1C120000)) /* SP810 controller */ -#define V2M_SP810_BASE UL(0x1c020000) +#define V2M_SP810_BASE (V2M_OFFSET + UL(0x1c020000)) #define V2M_SP810_CTRL_TIM0_SEL BIT_32(15) #define V2M_SP810_CTRL_TIM1_SEL BIT_32(17) #define V2M_SP810_CTRL_TIM2_SEL BIT_32(19) diff --git a/include/plat/arm/board/fvp_r/fvp_r_bl1.h b/include/plat/arm/board/fvp_r/fvp_r_bl1.h new file mode 100644 index 000000000..0b41e672f --- /dev/null +++ b/include/plat/arm/board/fvp_r/fvp_r_bl1.h @@ -0,0 +1,13 @@ +/* + * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FVP_R_BL1_H +#define FVP_R_BL1_H + +void bl1_load_bl33(void); +void bl1_transfer_bl33(void); + +#endif /* FVP_R_BL1_H */ diff --git a/include/plat/arm/common/arm_def.h b/include/plat/arm/common/arm_def.h index ae80628f1..1993cb401 100644 --- a/include/plat/arm/common/arm_def.h +++ b/include/plat/arm/common/arm_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -58,8 +58,12 @@ #define ARM_TRUSTED_DRAM_ID 1 #define ARM_DRAM_ID 2 -/* The first 4KB of Trusted SRAM are used as shared memory */ +#ifdef PLAT_ARM_TRUSTED_SRAM_BASE +#define ARM_TRUSTED_SRAM_BASE PLAT_ARM_TRUSTED_SRAM_BASE +#else #define ARM_TRUSTED_SRAM_BASE UL(0x04000000) +#endif /* PLAT_ARM_TRUSTED_SRAM_BASE */ + #define ARM_SHARED_RAM_BASE ARM_TRUSTED_SRAM_BASE #define ARM_SHARED_RAM_SIZE UL(0x00001000) /* 4 KB */ @@ -70,38 +74,84 @@ ARM_SHARED_RAM_SIZE) /* - * The top 16MB of DRAM1 is configured as secure access only using the TZC + * The top 16MB (or 64MB if RME is enabled) of DRAM1 is configured as + * follows: * - SCP TZC DRAM: If present, DRAM reserved for SCP use + * - L1 GPT DRAM: Reserved for L1 GPT if RME is enabled + * - REALM DRAM: Reserved for Realm world if RME is enabled * - AP TZC DRAM: The remaining TZC secured DRAM reserved for AP use + * + * RME enabled(64MB) RME not enabled(16MB) + * -------------------- ------------------- + * | | | | + * | AP TZC (~28MB) | | AP TZC (~14MB) | + * -------------------- ------------------- + * | | | | + * | REALM (32MB) | | EL3 TZC (2MB) | + * -------------------- ------------------- + * | | | | + * | EL3 TZC (3MB) | | SCP TZC | + * -------------------- 0xFFFF_FFFF------------------- + * | L1 GPT + SCP TZC | + * | (~1MB) | + * 0xFFFF_FFFF -------------------- + */ +#if ENABLE_RME +#define ARM_TZC_DRAM1_SIZE UL(0x04000000) /* 64MB */ +/* + * Define a region within the TZC secured DRAM for use by EL3 runtime + * firmware. This region is meant to be NOLOAD and will not be zero + * initialized. Data sections with the attribute `arm_el3_tzc_dram` will be + * placed here. 3MB region is reserved if RME is enabled, 2MB otherwise. */ -#define ARM_TZC_DRAM1_SIZE UL(0x01000000) +#define ARM_EL3_TZC_DRAM1_SIZE UL(0x00300000) /* 3MB */ +#define ARM_L1_GPT_SIZE UL(0x00100000) /* 1MB */ +#define ARM_REALM_SIZE UL(0x02000000) /* 32MB */ +#else +#define ARM_TZC_DRAM1_SIZE UL(0x01000000) /* 16MB */ +#define ARM_EL3_TZC_DRAM1_SIZE UL(0x00200000) /* 2MB */ +#define ARM_L1_GPT_SIZE UL(0) +#define ARM_REALM_SIZE UL(0) +#endif /* ENABLE_RME */ #define ARM_SCP_TZC_DRAM1_BASE (ARM_DRAM1_BASE + \ - ARM_DRAM1_SIZE - \ - ARM_SCP_TZC_DRAM1_SIZE) + ARM_DRAM1_SIZE - \ + (ARM_SCP_TZC_DRAM1_SIZE + \ + ARM_L1_GPT_SIZE)) #define ARM_SCP_TZC_DRAM1_SIZE PLAT_ARM_SCP_TZC_DRAM1_SIZE #define ARM_SCP_TZC_DRAM1_END (ARM_SCP_TZC_DRAM1_BASE + \ - ARM_SCP_TZC_DRAM1_SIZE - 1U) - -/* - * Define a 2MB region within the TZC secured DRAM for use by EL3 runtime - * firmware. This region is meant to be NOLOAD and will not be zero - * initialized. Data sections with the attribute `arm_el3_tzc_dram` will be - * placed here. - */ -#define ARM_EL3_TZC_DRAM1_BASE (ARM_SCP_TZC_DRAM1_BASE - ARM_EL3_TZC_DRAM1_SIZE) -#define ARM_EL3_TZC_DRAM1_SIZE UL(0x00200000) /* 2 MB */ + ARM_SCP_TZC_DRAM1_SIZE - 1U) +#if ENABLE_RME +#define ARM_L1_GPT_ADDR_BASE (ARM_DRAM1_BASE + \ + ARM_DRAM1_SIZE - \ + ARM_L1_GPT_SIZE) +#define ARM_L1_GPT_END (ARM_L1_GPT_ADDR_BASE + \ + ARM_L1_GPT_SIZE - 1U) + +#define ARM_REALM_BASE (ARM_DRAM1_BASE + \ + ARM_DRAM1_SIZE - \ + (ARM_SCP_TZC_DRAM1_SIZE + \ + ARM_EL3_TZC_DRAM1_SIZE + \ + ARM_REALM_SIZE + \ + ARM_L1_GPT_SIZE)) +#define ARM_REALM_END (ARM_REALM_BASE + ARM_REALM_SIZE - 1U) +#endif /* ENABLE_RME */ + +#define ARM_EL3_TZC_DRAM1_BASE (ARM_SCP_TZC_DRAM1_BASE - \ + ARM_EL3_TZC_DRAM1_SIZE) #define ARM_EL3_TZC_DRAM1_END (ARM_EL3_TZC_DRAM1_BASE + \ ARM_EL3_TZC_DRAM1_SIZE - 1U) #define ARM_AP_TZC_DRAM1_BASE (ARM_DRAM1_BASE + \ - ARM_DRAM1_SIZE - \ - ARM_TZC_DRAM1_SIZE) + ARM_DRAM1_SIZE - \ + ARM_TZC_DRAM1_SIZE) #define ARM_AP_TZC_DRAM1_SIZE (ARM_TZC_DRAM1_SIZE - \ - (ARM_SCP_TZC_DRAM1_SIZE + \ - ARM_EL3_TZC_DRAM1_SIZE)) + (ARM_SCP_TZC_DRAM1_SIZE + \ + ARM_EL3_TZC_DRAM1_SIZE + \ + ARM_REALM_SIZE + \ + ARM_L1_GPT_SIZE)) #define ARM_AP_TZC_DRAM1_END (ARM_AP_TZC_DRAM1_BASE + \ - ARM_AP_TZC_DRAM1_SIZE - 1U) + ARM_AP_TZC_DRAM1_SIZE - 1U) /* Define the Access permissions for Secure peripherals to NS_DRAM */ #if ARM_CRYPTOCELL_INTEG @@ -149,8 +199,12 @@ ARM_TZC_DRAM1_SIZE) #define ARM_NS_DRAM1_END (ARM_NS_DRAM1_BASE + \ ARM_NS_DRAM1_SIZE - 1U) - +#ifdef PLAT_ARM_DRAM1_BASE +#define ARM_DRAM1_BASE PLAT_ARM_DRAM1_BASE +#else #define ARM_DRAM1_BASE ULL(0x80000000) +#endif /* PLAT_ARM_DRAM1_BASE */ + #define ARM_DRAM1_SIZE ULL(0x80000000) #define ARM_DRAM1_END (ARM_DRAM1_BASE + \ ARM_DRAM1_SIZE - 1U) @@ -198,45 +252,58 @@ INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, (grp), \ GIC_INTR_CFG_EDGE) -#define ARM_MAP_SHARED_RAM MAP_REGION_FLAT( \ - ARM_SHARED_RAM_BASE, \ - ARM_SHARED_RAM_SIZE, \ - MT_DEVICE | MT_RW | MT_SECURE) +#define ARM_MAP_SHARED_RAM MAP_REGION_FLAT( \ + ARM_SHARED_RAM_BASE, \ + ARM_SHARED_RAM_SIZE, \ + MT_DEVICE | MT_RW | EL3_PAS) -#define ARM_MAP_NS_DRAM1 MAP_REGION_FLAT( \ - ARM_NS_DRAM1_BASE, \ - ARM_NS_DRAM1_SIZE, \ - MT_MEMORY | MT_RW | MT_NS) +#define ARM_MAP_NS_DRAM1 MAP_REGION_FLAT( \ + ARM_NS_DRAM1_BASE, \ + ARM_NS_DRAM1_SIZE, \ + MT_MEMORY | MT_RW | MT_NS) -#define ARM_MAP_DRAM2 MAP_REGION_FLAT( \ - ARM_DRAM2_BASE, \ - ARM_DRAM2_SIZE, \ - MT_MEMORY | MT_RW | MT_NS) +#define ARM_MAP_DRAM2 MAP_REGION_FLAT( \ + ARM_DRAM2_BASE, \ + ARM_DRAM2_SIZE, \ + MT_MEMORY | MT_RW | MT_NS) -#define ARM_MAP_TSP_SEC_MEM MAP_REGION_FLAT( \ - TSP_SEC_MEM_BASE, \ - TSP_SEC_MEM_SIZE, \ - MT_MEMORY | MT_RW | MT_SECURE) +#define ARM_MAP_TSP_SEC_MEM MAP_REGION_FLAT( \ + TSP_SEC_MEM_BASE, \ + TSP_SEC_MEM_SIZE, \ + MT_MEMORY | MT_RW | MT_SECURE) #if ARM_BL31_IN_DRAM -#define ARM_MAP_BL31_SEC_DRAM MAP_REGION_FLAT( \ - BL31_BASE, \ - PLAT_ARM_MAX_BL31_SIZE, \ - MT_MEMORY | MT_RW | MT_SECURE) +#define ARM_MAP_BL31_SEC_DRAM MAP_REGION_FLAT( \ + BL31_BASE, \ + PLAT_ARM_MAX_BL31_SIZE, \ + MT_MEMORY | MT_RW | MT_SECURE) #endif -#define ARM_MAP_EL3_TZC_DRAM MAP_REGION_FLAT( \ - ARM_EL3_TZC_DRAM1_BASE, \ - ARM_EL3_TZC_DRAM1_SIZE, \ - MT_MEMORY | MT_RW | MT_SECURE) +#define ARM_MAP_EL3_TZC_DRAM MAP_REGION_FLAT( \ + ARM_EL3_TZC_DRAM1_BASE, \ + ARM_EL3_TZC_DRAM1_SIZE, \ + MT_MEMORY | MT_RW | EL3_PAS) #if defined(SPD_spmd) -#define ARM_MAP_TRUSTED_DRAM MAP_REGION_FLAT( \ - PLAT_ARM_TRUSTED_DRAM_BASE, \ - PLAT_ARM_TRUSTED_DRAM_SIZE, \ - MT_MEMORY | MT_RW | MT_SECURE) +#define ARM_MAP_TRUSTED_DRAM MAP_REGION_FLAT( \ + PLAT_ARM_TRUSTED_DRAM_BASE, \ + PLAT_ARM_TRUSTED_DRAM_SIZE, \ + MT_MEMORY | MT_RW | MT_SECURE) #endif +#if ENABLE_RME +#define ARM_MAP_RMM_DRAM MAP_REGION_FLAT( \ + PLAT_ARM_RMM_BASE, \ + PLAT_ARM_RMM_SIZE, \ + MT_MEMORY | MT_RW | MT_REALM) + + +#define ARM_MAP_GPT_L1_DRAM MAP_REGION_FLAT( \ + ARM_L1_GPT_ADDR_BASE, \ + ARM_L1_GPT_SIZE, \ + MT_MEMORY | MT_RW | EL3_PAS) + +#endif /* ENABLE_RME */ /* * Mapping for the BL1 RW region. This mapping is needed by BL2 in order to @@ -247,7 +314,7 @@ #define ARM_MAP_BL1_RW MAP_REGION_FLAT( \ BL1_RW_BASE, \ BL1_RW_LIMIT - BL1_RW_BASE, \ - MT_MEMORY | MT_RW | MT_SECURE) + MT_MEMORY | MT_RW | EL3_PAS) /* * If SEPARATE_CODE_AND_RODATA=1 we define a region for each section @@ -257,35 +324,35 @@ #define ARM_MAP_BL_RO MAP_REGION_FLAT( \ BL_CODE_BASE, \ BL_CODE_END - BL_CODE_BASE, \ - MT_CODE | MT_SECURE), \ + MT_CODE | EL3_PAS), \ MAP_REGION_FLAT( \ BL_RO_DATA_BASE, \ BL_RO_DATA_END \ - BL_RO_DATA_BASE, \ - MT_RO_DATA | MT_SECURE) + MT_RO_DATA | EL3_PAS) #else #define ARM_MAP_BL_RO MAP_REGION_FLAT( \ BL_CODE_BASE, \ BL_CODE_END - BL_CODE_BASE, \ - MT_CODE | MT_SECURE) + MT_CODE | EL3_PAS) #endif #if USE_COHERENT_MEM #define ARM_MAP_BL_COHERENT_RAM MAP_REGION_FLAT( \ BL_COHERENT_RAM_BASE, \ BL_COHERENT_RAM_END \ - BL_COHERENT_RAM_BASE, \ - MT_DEVICE | MT_RW | MT_SECURE) + MT_DEVICE | MT_RW | EL3_PAS) #endif #if USE_ROMLIB #define ARM_MAP_ROMLIB_CODE MAP_REGION_FLAT( \ ROMLIB_RO_BASE, \ ROMLIB_RO_LIMIT - ROMLIB_RO_BASE,\ - MT_CODE | MT_SECURE) + MT_CODE | EL3_PAS) #define ARM_MAP_ROMLIB_DATA MAP_REGION_FLAT( \ ROMLIB_RW_BASE, \ ROMLIB_RW_END - ROMLIB_RW_BASE,\ - MT_MEMORY | MT_RW | MT_SECURE) + MT_MEMORY | MT_RW | EL3_PAS) #endif /* @@ -300,7 +367,15 @@ #define ARM_MAP_BL_CONFIG_REGION MAP_REGION_FLAT(ARM_BL_RAM_BASE, \ (ARM_FW_CONFIGS_LIMIT \ - ARM_BL_RAM_BASE), \ - MT_MEMORY | MT_RW | MT_SECURE) + MT_MEMORY | MT_RW | EL3_PAS) +/* + * Map L0_GPT with read and write permissions + */ +#if ENABLE_RME +#define ARM_MAP_L0_GPT_REGION MAP_REGION_FLAT(ARM_L0_GPT_ADDR_BASE, \ + ARM_L0_GPT_SIZE, \ + MT_MEMORY | MT_RW | MT_ROOT) +#endif /* * The max number of regions like RO(code), coherent and data required by @@ -312,16 +387,44 @@ ARM_BL_REGIONS) /* Memory mapped Generic timer interfaces */ +#ifdef PLAT_ARM_SYS_CNTCTL_BASE +#define ARM_SYS_CNTCTL_BASE PLAT_ARM_SYS_CNTCTL_BASE +#else #define ARM_SYS_CNTCTL_BASE UL(0x2a430000) +#endif + +#ifdef PLAT_ARM_SYS_CNTREAD_BASE +#define ARM_SYS_CNTREAD_BASE PLAT_ARM_SYS_CNTREAD_BASE +#else #define ARM_SYS_CNTREAD_BASE UL(0x2a800000) +#endif + +#ifdef PLAT_ARM_SYS_TIMCTL_BASE +#define ARM_SYS_TIMCTL_BASE PLAT_ARM_SYS_TIMCTL_BASE +#else #define ARM_SYS_TIMCTL_BASE UL(0x2a810000) +#endif + +#ifdef PLAT_ARM_SYS_CNT_BASE_S +#define ARM_SYS_CNT_BASE_S PLAT_ARM_SYS_CNT_BASE_S +#else #define ARM_SYS_CNT_BASE_S UL(0x2a820000) +#endif + +#ifdef PLAT_ARM_SYS_CNT_BASE_NS +#define ARM_SYS_CNT_BASE_NS PLAT_ARM_SYS_CNT_BASE_NS +#else #define ARM_SYS_CNT_BASE_NS UL(0x2a830000) +#endif #define ARM_CONSOLE_BAUDRATE 115200 /* Trusted Watchdog constants */ +#ifdef PLAT_ARM_SP805_TWDG_BASE +#define ARM_SP805_TWDG_BASE PLAT_ARM_SP805_TWDG_BASE +#else #define ARM_SP805_TWDG_BASE UL(0x2a490000) +#endif #define ARM_SP805_TWDG_CLK_HZ 32768 /* The TBBR document specifies a watchdog timeout of 256 seconds. SP805 * asserts reset after two consecutive countdowns (2 x 128 = 256 sec) */ @@ -373,15 +476,32 @@ */ #define ARM_FW_CONFIGS_LIMIT (ARM_BL_RAM_BASE + (PAGE_SIZE * 2)) +#if ENABLE_RME +/* + * Store the L0 GPT on Trusted SRAM next to firmware + * configuration memory, 4KB aligned. + */ +#define ARM_L0_GPT_SIZE (PAGE_SIZE) +#define ARM_L0_GPT_ADDR_BASE (ARM_FW_CONFIGS_LIMIT) +#define ARM_L0_GPT_LIMIT (ARM_L0_GPT_ADDR_BASE + ARM_L0_GPT_SIZE) +#else +#define ARM_L0_GPT_SIZE U(0) +#endif + /******************************************************************************* * BL1 specific defines. * BL1 RW data is relocated from ROM to RAM at runtime so we need 2 sets of * addresses. ******************************************************************************/ #define BL1_RO_BASE PLAT_ARM_TRUSTED_ROM_BASE +#ifdef PLAT_BL1_RO_LIMIT +#define BL1_RO_LIMIT PLAT_BL1_RO_LIMIT +#else #define BL1_RO_LIMIT (PLAT_ARM_TRUSTED_ROM_BASE \ + (PLAT_ARM_TRUSTED_ROM_SIZE - \ PLAT_ARM_MAX_ROMLIB_RO_SIZE)) +#endif + /* * Put BL1 RW at the top of the Trusted SRAM. */ @@ -460,6 +580,14 @@ #endif #endif +/****************************************************************************** + * RMM specific defines + *****************************************************************************/ +#if ENABLE_RME +#define RMM_BASE (ARM_REALM_BASE) +#define RMM_LIMIT (RMM_BASE + ARM_REALM_SIZE) +#endif + #if !defined(__aarch64__) || JUNO_AARCH32_EL3_RUNTIME /******************************************************************************* * BL32 specific defines for EL3 runtime in AArch32 mode diff --git a/include/plat/arm/common/arm_dyn_cfg_helpers.h b/include/plat/arm/common/arm_dyn_cfg_helpers.h index 34bf07c0d..ff00fe7be 100644 --- a/include/plat/arm/common/arm_dyn_cfg_helpers.h +++ b/include/plat/arm/common/arm_dyn_cfg_helpers.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2021, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -14,8 +14,4 @@ int arm_dyn_tb_fw_cfg_init(void *dtb, int *node); int arm_set_dtb_mbedtls_heap_info(void *dtb, void *heap_addr, size_t heap_size); -#if MEASURED_BOOT -int arm_set_bl2_hash_info(void *dtb, void *data); -#endif - #endif /* ARM_DYN_CFG_HELPERS_H */ diff --git a/include/plat/arm/common/arm_pas_def.h b/include/plat/arm/common/arm_pas_def.h new file mode 100644 index 000000000..4fee41b3f --- /dev/null +++ b/include/plat/arm/common/arm_pas_def.h @@ -0,0 +1,94 @@ +/* + * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef ARM_PAS_DEF_H +#define ARM_PAS_DEF_H + +#include <lib/gpt_rme/gpt_rme.h> +#include <plat/arm/common/arm_def.h> + +/***************************************************************************** + * PAS regions used to initialize the Granule Protection Table (GPT) + ****************************************************************************/ + +/* + * The PA space is initially mapped in the GPT as follows: + * + * ============================================================================ + * Base Addr| Size |L? GPT|PAS |Content |Comment + * ============================================================================ + * 0GB | 1GB |L0 GPT|ANY |TBROM (EL3 code) |Fixed mapping + * | | | |TSRAM (EL3 data) | + * | | | |IO (incl.UARTs & GIC) | + * ---------------------------------------------------------------------------- + * 1GB | 1GB |L0 GPT|ANY |IO |Fixed mapping + * ---------------------------------------------------------------------------- + * 2GB | 1GB |L1 GPT|NS |DRAM (NS Kernel) |Use T.Descrip + * ---------------------------------------------------------------------------- + * 3GB |1GB-64MB |L1 GPT|NS |DRAM (NS Kernel) |Use T.Descrip + * ---------------------------------------------------------------------------- + * 4GB-64MB |64MB-32MB | | | | + * | -4MB |L1 GPT|SECURE|DRAM TZC |Use T.Descrip + * ---------------------------------------------------------------------------- + * 4GB-32MB | | | | | + * -3MB-1MB |32MB |L1 GPT|REALM |RMM |Use T.Descrip + * ---------------------------------------------------------------------------- + * 4GB-3MB | | | | | + * -1MB |3MB |L1 GPT|ROOT |EL3 DRAM data |Use T.Descrip + * ---------------------------------------------------------------------------- + * 4GB-1MB |1MB |L1 GPT|ROOT |DRAM (L1 GPTs, SCP TZC) |Fixed mapping + * ============================================================================ + * + * - 4KB of L0 GPT reside in TSRAM, on top of the CONFIG section. + * - ~1MB of L1 GPTs reside at the top of DRAM1 (TZC area). + * - The first 1GB region has GPT_GPI_ANY and, therefore, is not protected by + * the GPT. + * - The DRAM TZC area is split into three regions: the L1 GPT region and + * 3MB of region below that are defined as GPT_GPI_ROOT, 32MB Realm region + * below that is defined as GPT_GPI_REALM and the rest of it is defined as + * GPT_GPI_SECURE. + */ + +/* TODO: This might not be the best way to map the PAS */ + +/* Device memory 0 to 2GB */ +#define ARM_PAS_1_BASE (U(0)) +#define ARM_PAS_1_SIZE ((ULL(1)<<31)) /* 2GB */ + +/* NS memory 2GB to (end - 64MB) */ +#define ARM_PAS_2_BASE (ARM_PAS_1_BASE + ARM_PAS_1_SIZE) +#define ARM_PAS_2_SIZE (ARM_NS_DRAM1_SIZE) + +/* Secure TZC region */ +#define ARM_PAS_3_BASE (ARM_AP_TZC_DRAM1_BASE) +#define ARM_PAS_3_SIZE (ARM_AP_TZC_DRAM1_SIZE) + +#define ARM_PAS_GPI_ANY MAP_GPT_REGION(ARM_PAS_1_BASE, \ + ARM_PAS_1_SIZE, \ + GPT_GPI_ANY) +#define ARM_PAS_KERNEL GPT_MAP_REGION_GRANULE(ARM_PAS_2_BASE, \ + ARM_PAS_2_SIZE, \ + GPT_GPI_NS) + +#define ARM_PAS_SECURE GPT_MAP_REGION_GRANULE(ARM_PAS_3_BASE, \ + ARM_PAS_3_SIZE, \ + GPT_GPI_SECURE) + +#define ARM_PAS_REALM GPT_MAP_REGION_GRANULE(ARM_REALM_BASE, \ + ARM_REALM_SIZE, \ + GPT_GPI_REALM) + +#define ARM_PAS_EL3_DRAM GPT_MAP_REGION_GRANULE(ARM_EL3_TZC_DRAM1_BASE, \ + ARM_EL3_TZC_DRAM1_SIZE, \ + GPT_GPI_ROOT) + +#define ARM_PAS_GPTS GPT_MAP_REGION_GRANULE(ARM_L1_GPT_ADDR_BASE, \ + ARM_L1_GPT_SIZE, \ + GPT_GPI_ROOT) + +/* GPT Configuration options */ +#define PLATFORM_L0GPTSZ GPCCR_L0GPTSZ_30BITS + +#endif /* ARM_PAS_DEF_H */ diff --git a/include/plat/arm/common/fconf_ethosn_getter.h b/include/plat/arm/common/fconf_ethosn_getter.h index 0fd1f025a..fcdc31f8b 100644 --- a/include/plat/arm/common/fconf_ethosn_getter.h +++ b/include/plat/arm/common/fconf_ethosn_getter.h @@ -14,7 +14,7 @@ #define hw_config__ethosn_config_getter(prop) ethosn_config.prop #define hw_config__ethosn_core_addr_getter(idx) __extension__ ({ \ assert(idx < ethosn_config.num_cores); \ - ethosn_config.core_addr[idx]; \ + ethosn_config.core[idx].addr; \ }) #define ETHOSN_STATUS_DISABLED U(0) @@ -22,10 +22,13 @@ #define ETHOSN_CORE_NUM_MAX U(64) +struct ethosn_core_t { + uint64_t addr; +}; + struct ethosn_config_t { - uint8_t status; uint32_t num_cores; - uint64_t core_addr[ETHOSN_CORE_NUM_MAX]; + struct ethosn_core_t core[ETHOSN_CORE_NUM_MAX]; }; int fconf_populate_arm_ethosn(uintptr_t config); diff --git a/include/plat/arm/common/plat_arm.h b/include/plat/arm/common/plat_arm.h index 0a19d8b36..9618700a2 100644 --- a/include/plat/arm/common/plat_arm.h +++ b/include/plat/arm/common/plat_arm.h @@ -41,7 +41,7 @@ typedef struct arm_tzc_regions_info { ******************************************************************************/ #if SPM_MM #define ARM_TZC_REGIONS_DEF \ - {ARM_AP_TZC_DRAM1_BASE, ARM_EL3_TZC_DRAM1_END, \ + {ARM_AP_TZC_DRAM1_BASE, ARM_EL3_TZC_DRAM1_END + ARM_L1_GPT_SIZE,\ TZC_REGION_S_RDWR, 0}, \ {ARM_NS_DRAM1_BASE, ARM_NS_DRAM1_END, ARM_TZC_NS_DRAM_S_ACCESS, \ PLAT_ARM_TZC_NS_DEV_ACCESS}, \ @@ -51,9 +51,20 @@ typedef struct arm_tzc_regions_info { PLAT_SP_IMAGE_NS_BUF_SIZE) - 1, TZC_REGION_S_NONE, \ PLAT_ARM_TZC_NS_DEV_ACCESS} +#elif ENABLE_RME +#define ARM_TZC_REGIONS_DEF \ + {ARM_AP_TZC_DRAM1_BASE, ARM_AP_TZC_DRAM1_END, TZC_REGION_S_RDWR, 0},\ + {ARM_EL3_TZC_DRAM1_BASE, ARM_L1_GPT_END, TZC_REGION_S_RDWR, 0}, \ + {ARM_NS_DRAM1_BASE, ARM_NS_DRAM1_END, ARM_TZC_NS_DRAM_S_ACCESS, \ + PLAT_ARM_TZC_NS_DEV_ACCESS}, \ + {ARM_REALM_BASE, ARM_REALM_END, ARM_TZC_NS_DRAM_S_ACCESS, \ + PLAT_ARM_TZC_NS_DEV_ACCESS}, \ + {ARM_DRAM2_BASE, ARM_DRAM2_END, ARM_TZC_NS_DRAM_S_ACCESS, \ + PLAT_ARM_TZC_NS_DEV_ACCESS} + #else #define ARM_TZC_REGIONS_DEF \ - {ARM_AP_TZC_DRAM1_BASE, ARM_EL3_TZC_DRAM1_END, \ + {ARM_AP_TZC_DRAM1_BASE, ARM_EL3_TZC_DRAM1_END + ARM_L1_GPT_SIZE,\ TZC_REGION_S_RDWR, 0}, \ {ARM_NS_DRAM1_BASE, ARM_NS_DRAM1_END, ARM_TZC_NS_DRAM_S_ACCESS, \ PLAT_ARM_TZC_NS_DEV_ACCESS}, \ @@ -239,12 +250,8 @@ void arm_bl1_set_mbedtls_heap(void); int arm_get_mbedtls_heap(void **heap_addr, size_t *heap_size); #if MEASURED_BOOT -/* Measured boot related functions */ -void arm_bl1_set_bl2_hash(const image_desc_t *image_desc); -void arm_bl2_get_hash(void *data); -int arm_set_tos_fw_info(uintptr_t config_base, uintptr_t log_addr, - size_t log_size); -int arm_set_nt_fw_info(uintptr_t config_base, +int arm_set_tos_fw_info(uintptr_t log_addr, size_t log_size); +int arm_set_nt_fw_info( /* * Currently OP-TEE does not support reading DTBs from Secure memory * and this option should be removed when feature is supported. @@ -253,6 +260,8 @@ int arm_set_nt_fw_info(uintptr_t config_base, uintptr_t log_addr, #endif size_t log_size, uintptr_t *ns_log_addr); +int arm_set_tb_fw_info(uintptr_t log_addr, size_t log_size); +int arm_get_tb_fw_info(uint64_t *log_addr, size_t *log_size); #endif /* MEASURED_BOOT */ /* |