diff options
Diffstat (limited to 'plat/allwinner/common/include/platform_def.h')
-rw-r--r-- | plat/allwinner/common/include/platform_def.h | 39 |
1 files changed, 27 insertions, 12 deletions
diff --git a/plat/allwinner/common/include/platform_def.h b/plat/allwinner/common/include/platform_def.h index 93720fff2..49951e080 100644 --- a/plat/allwinner/common/include/platform_def.h +++ b/plat/allwinner/common/include/platform_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -13,20 +13,37 @@ #include <sunxi_mmap.h> -#define BL31_BASE (SUNXI_SRAM_A2_BASE + 0x4000) +#ifdef SUNXI_BL31_IN_DRAM + +#define BL31_BASE SUNXI_DRAM_BASE +#define BL31_LIMIT (SUNXI_DRAM_BASE + 0x40000) + +#define MAX_XLAT_TABLES 4 +#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) + +#define SUNXI_BL33_VIRT_BASE PRELOADED_BL33_BASE + +#else /* !SUNXI_BL31_IN_DRAM */ + +#define BL31_BASE (SUNXI_SRAM_A2_BASE + \ + SUNXI_SRAM_A2_BL31_OFFSET) #define BL31_LIMIT (SUNXI_SRAM_A2_BASE + \ SUNXI_SRAM_A2_SIZE - SUNXI_SCP_SIZE) -/* The SCP firmware is allocated the last 16KiB of SRAM A2. */ -#define SUNXI_SCP_BASE BL31_LIMIT -#define SUNXI_SCP_SIZE 0x4000 - /* Overwrite U-Boot SPL, but reserve the first page for the SPL header. */ #define BL31_NOBITS_BASE (SUNXI_SRAM_A1_BASE + 0x1000) #define BL31_NOBITS_LIMIT (SUNXI_SRAM_A1_BASE + SUNXI_SRAM_A1_SIZE) -/* How much memory to reserve as secure for BL32, if configured */ -#define SUNXI_DRAM_SEC_SIZE (32U << 20) +#define MAX_XLAT_TABLES 1 +#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 28) + +#define SUNXI_BL33_VIRT_BASE SUNXI_DRAM_VIRT_BASE + +/* The SCP firmware is allocated the last 16KiB of SRAM A2. */ +#define SUNXI_SCP_BASE BL31_LIMIT +#define SUNXI_SCP_SIZE 0x4000 + +#endif /* SUNXI_BL31_IN_DRAM */ /* How much DRAM to map (to map BL33, for fetching the DTB from U-Boot) */ #define SUNXI_DRAM_MAP_SIZE (64U << 20) @@ -34,8 +51,8 @@ #define CACHE_WRITEBACK_SHIFT 6 #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) -#define MAX_MMAP_REGIONS (3 + PLATFORM_MMAP_REGIONS) -#define MAX_XLAT_TABLES 1 +#define MAX_STATIC_MMAP_REGIONS 3 +#define MAX_MMAP_REGIONS (5 + MAX_STATIC_MMAP_REGIONS) #define PLAT_CSS_SCP_COM_SHARED_MEM_BASE \ (SUNXI_SRAM_A2_BASE + SUNXI_SRAM_A2_SIZE - 0x200) @@ -50,13 +67,11 @@ PLATFORM_CORE_COUNT) #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) -#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 28) #define PLATFORM_CLUSTER_COUNT U(1) #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * \ PLATFORM_MAX_CPUS_PER_CLUSTER) #define PLATFORM_MAX_CPUS_PER_CLUSTER U(4) -#define PLATFORM_MMAP_REGIONS 5 #define PLATFORM_STACK_SIZE (0x1000 / PLATFORM_CORE_COUNT) #ifndef SPD_none |