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-rw-r--r--plat/renesas/common/aarch64/plat_helpers.S6
-rw-r--r--plat/renesas/common/bl2_cpg_init.c34
-rw-r--r--plat/renesas/common/bl2_secure_setting.c12
-rw-r--r--plat/renesas/common/common.mk9
-rw-r--r--plat/renesas/common/include/platform_def.h4
-rw-r--r--plat/renesas/common/include/rcar_def.h4
-rw-r--r--plat/renesas/common/plat_pm.c20
-rw-r--r--plat/renesas/rcar/bl2_plat_setup.c44
-rw-r--r--plat/renesas/rzg/bl2_plat_setup.c4
9 files changed, 74 insertions, 63 deletions
diff --git a/plat/renesas/common/aarch64/plat_helpers.S b/plat/renesas/common/aarch64/plat_helpers.S
index ec21f2510..21c3bedaf 100644
--- a/plat/renesas/common/aarch64/plat_helpers.S
+++ b/plat/renesas/common/aarch64/plat_helpers.S
@@ -1,6 +1,6 @@
/*
* Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
- * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2021, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -284,7 +284,11 @@ func plat_crash_console_putc
str x3, [sp, #-16]!
str x4, [sp, #-16]!
str x5, [sp, #-16]!
+ str x6, [sp, #-16]!
+ str x7, [sp, #-16]!
bl console_rcar_putc
+ ldr x7, [sp], #16
+ ldr x6, [sp], #16
ldr x5, [sp], #16
ldr x4, [sp], #16
ldr x3, [sp], #16
diff --git a/plat/renesas/common/bl2_cpg_init.c b/plat/renesas/common/bl2_cpg_init.c
index ba8e53b58..a545f7106 100644
--- a/plat/renesas/common/bl2_cpg_init.c
+++ b/plat/renesas/common/bl2_cpg_init.c
@@ -40,7 +40,6 @@ static void bl2_system_cpg_init_e3(void);
#endif
#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_D3)
-static void bl2_realtime_cpg_init_d3(void);
static void bl2_system_cpg_init_d3(void);
#endif
@@ -140,7 +139,7 @@ static void bl2_system_cpg_init_h3(void)
cpg_write(SMSTPCR1, 0xFFFFFFFFU);
cpg_write(SMSTPCR2, 0x040E2FDCU);
cpg_write(SMSTPCR3, 0xFFFFFBDFU);
- cpg_write(SMSTPCR4, 0x80000004U);
+ cpg_write(SMSTPCR4, 0x80000000U | (mmio_read_32(SMSTPCR4) & 0x4));
cpg_write(SMSTPCR5, 0xC3FFFFFFU);
cpg_write(SMSTPCR6, 0xFFFFFFFFU);
cpg_write(SMSTPCR7, 0xFFFFFFFFU);
@@ -176,7 +175,7 @@ static void bl2_system_cpg_init_m3(void)
cpg_write(SMSTPCR1, 0xFFFFFFFFU);
cpg_write(SMSTPCR2, 0x040E2FDCU);
cpg_write(SMSTPCR3, 0xFFFFFBDFU);
- cpg_write(SMSTPCR4, 0x80000004U);
+ cpg_write(SMSTPCR4, 0x80000000U | (mmio_read_32(SMSTPCR4) & 0x4));
cpg_write(SMSTPCR5, 0xC3FFFFFFU);
cpg_write(SMSTPCR6, 0xFFFFFFFFU);
cpg_write(SMSTPCR7, 0xFFFFFFFFU);
@@ -212,7 +211,7 @@ static void bl2_system_cpg_init_m3n(void)
cpg_write(SMSTPCR1, 0xFFFFFFFFU);
cpg_write(SMSTPCR2, 0x040E2FDCU);
cpg_write(SMSTPCR3, 0xFFFFFBDFU);
- cpg_write(SMSTPCR4, 0x80000004U);
+ cpg_write(SMSTPCR4, 0x80000000U | (mmio_read_32(SMSTPCR4) & 0x4));
cpg_write(SMSTPCR5, 0xC3FFFFFFU);
cpg_write(SMSTPCR6, 0xFFFFFFFFU);
cpg_write(SMSTPCR7, 0xFFFFFFFFU);
@@ -246,7 +245,7 @@ static void bl2_system_cpg_init_v3m(void)
cpg_write(SMSTPCR1, 0xFFFFFFFFU);
cpg_write(SMSTPCR2, 0x340E2FDCU);
cpg_write(SMSTPCR3, 0xFFFFFBDFU);
- cpg_write(SMSTPCR4, 0x80000004U);
+ cpg_write(SMSTPCR4, 0x80000000U | (mmio_read_32(SMSTPCR4) & 0x4));
cpg_write(SMSTPCR5, 0xC3FFFFFFU);
cpg_write(SMSTPCR6, 0xFFFFFFFFU);
cpg_write(SMSTPCR7, 0xFFFFFFFFU);
@@ -280,7 +279,7 @@ static void bl2_system_cpg_init_e3(void)
cpg_write(SMSTPCR1, 0xFFFFFFFFU);
cpg_write(SMSTPCR2, 0x000E2FDCU);
cpg_write(SMSTPCR3, 0xFFFFFBDFU);
- cpg_write(SMSTPCR4, 0x80000004U);
+ cpg_write(SMSTPCR4, 0x80000000U | (mmio_read_32(SMSTPCR4) & 0x4));
cpg_write(SMSTPCR5, 0xC3FFFFFFU);
cpg_write(SMSTPCR6, 0xFFFFFFFFU);
cpg_write(SMSTPCR7, 0xFFFFFFFFU);
@@ -292,23 +291,6 @@ static void bl2_system_cpg_init_e3(void)
#endif
#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_D3)
-static void bl2_realtime_cpg_init_d3(void)
-{
- /* Realtime Module Stop Control Registers */
- cpg_write(RMSTPCR0, 0x00010000U);
- cpg_write(RMSTPCR1, 0xFFFFFFFFU);
- cpg_write(RMSTPCR2, 0x00060FDCU);
- cpg_write(RMSTPCR3, 0xFFFFFFDFU);
- cpg_write(RMSTPCR4, 0x80000184U);
- cpg_write(RMSTPCR5, 0x83FFFFFFU);
- cpg_write(RMSTPCR6, 0xFFFFFFFFU);
- cpg_write(RMSTPCR7, 0xFFFFFFFFU);
- cpg_write(RMSTPCR8, 0x00F1FFF7U);
- cpg_write(RMSTPCR9, 0xF3F5E016U);
- cpg_write(RMSTPCR10, 0xFFFEFFE0U);
- cpg_write(RMSTPCR11, 0x000000B7U);
-}
-
static void bl2_system_cpg_init_d3(void)
{
/* System Module Stop Control Registers */
@@ -316,7 +298,7 @@ static void bl2_system_cpg_init_d3(void)
cpg_write(SMSTPCR1, 0xFFFFFFFFU);
cpg_write(SMSTPCR2, 0x00060FDCU);
cpg_write(SMSTPCR3, 0xFFFFFBDFU);
- cpg_write(SMSTPCR4, 0x00000084U);
+ cpg_write(SMSTPCR4, 0x00000080U | (mmio_read_32(SMSTPCR4) & 0x4));
cpg_write(SMSTPCR5, 0x83FFFFFFU);
cpg_write(SMSTPCR6, 0xFFFFFFFFU);
cpg_write(SMSTPCR7, 0xFFFFFFFFU);
@@ -356,7 +338,7 @@ void bl2_cpg_init(void)
bl2_realtime_cpg_init_e3();
break;
case PRR_PRODUCT_D3:
- bl2_realtime_cpg_init_d3();
+ /* no need */
break;
default:
panic();
@@ -373,7 +355,7 @@ void bl2_cpg_init(void)
#elif RCAR_LSI == RCAR_E3 || RCAR_LSI == RZ_G2E
bl2_realtime_cpg_init_e3();
#elif RCAR_LSI == RCAR_D3
- bl2_realtime_cpg_init_d3();
+ /* no need */
#else
#error "Don't have CPG initialize routine(unknown)."
#endif
diff --git a/plat/renesas/common/bl2_secure_setting.c b/plat/renesas/common/bl2_secure_setting.c
index 095d1f62a..2f8b0011d 100644
--- a/plat/renesas/common/bl2_secure_setting.c
+++ b/plat/renesas/common/bl2_secure_setting.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2021, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -49,10 +49,10 @@ static const struct {
/*
* Bit13: SCEG PKA (secure APB) slave ports
* 0: registers accessed from secure resource only
- * 1: Reserved[R-Car E3]
+ * 1: Reserved[R-Car E3/D3]
* Bit12: SCEG PKA (public APB) slave ports
* 0: registers accessed from secure resource only
- * 1: Reserved[R-Car E3]
+ * 1: Reserved[R-Car E3/D3]
* Bit10: SCEG Secure Core slave ports
* 0: registers accessed from secure resource only
*/
@@ -152,14 +152,14 @@ static const struct {
* Security group 1 attribute setting for slave ports 6
* Bit13: SCEG PKA (secure APB) slave ports
* SecurityGroup3
- * Reserved[R-Car E3]
+ * Reserved[R-Car E3/D3]
* Bit12: SCEG PKA (public APB) slave ports
* SecurityGroup3
- * Reserved[R-Car E3]
+ * Reserved[R-Car E3/D3]
* Bit10: SCEG Secure Core slave ports
* SecurityGroup3
*/
-#if RCAR_LSI == RCAR_E3
+#if RCAR_LSI == RCAR_E3 || RCAR_LSI == RCAR_D3
{ SEC_GRP0COND6, 0x00000400U },
{ SEC_GRP1COND6, 0x00000400U },
#else /* RCAR_LSI == RCAR_E3 */
diff --git a/plat/renesas/common/common.mk b/plat/renesas/common/common.mk
index fafce9834..0d88d658e 100644
--- a/plat/renesas/common/common.mk
+++ b/plat/renesas/common/common.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2018-2020, Renesas Electronics Corporation. All rights reserved.
+# Copyright (c) 2018-2021, Renesas Electronics Corporation. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -65,10 +65,12 @@ $(eval $(call add_define,RCAR_CUT_30))
ERRATA_A53_835769 := 1
ERRATA_A53_843419 := 1
ERRATA_A53_855873 := 1
+ERRATA_A53_1530924 := 1
# Enable workarounds for selected Cortex-A57 erratas.
ERRATA_A57_859972 := 1
ERRATA_A57_813419 := 1
+ERRATA_A57_1319537 := 1
PLAT_INCLUDES := -Iplat/renesas/common/include/registers \
-Iplat/renesas/common/include \
@@ -77,9 +79,8 @@ PLAT_INCLUDES := -Iplat/renesas/common/include/registers \
PLAT_BL_COMMON_SOURCES := drivers/renesas/common/iic_dvfs/iic_dvfs.c \
plat/renesas/common/rcar_common.c
-RCAR_GIC_SOURCES := drivers/arm/gic/common/gic_common.c \
- drivers/arm/gic/v2/gicv2_main.c \
- drivers/arm/gic/v2/gicv2_helpers.c \
+include drivers/arm/gic/v2/gicv2.mk
+RCAR_GIC_SOURCES := ${GICV2_SOURCES} \
plat/common/plat_gicv2.c
BL2_SOURCES += ${RCAR_GIC_SOURCES} \
diff --git a/plat/renesas/common/include/platform_def.h b/plat/renesas/common/include/platform_def.h
index 72c768891..1213a3c96 100644
--- a/plat/renesas/common/include/platform_def.h
+++ b/plat/renesas/common/include/platform_def.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2021, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -144,7 +144,7 @@
******************************************************************************/
#ifndef SPD_NONE
#define BL32_BASE U(0x44100000)
-#define BL32_LIMIT (BL32_BASE + U(0x100000))
+#define BL32_LIMIT (BL32_BASE + U(0x200000))
#endif
/*******************************************************************************
diff --git a/plat/renesas/common/include/rcar_def.h b/plat/renesas/common/include/rcar_def.h
index 93a65f1a4..2cd26edbf 100644
--- a/plat/renesas/common/include/rcar_def.h
+++ b/plat/renesas/common/include/rcar_def.h
@@ -148,9 +148,13 @@
#define RCAR_PWRER5 U(0xE61801D4) /* shutoff/resume error */
#define RCAR_SYSCISR U(0xE6180004) /* Interrupt status */
#define RCAR_SYSCISCR U(0xE6180008) /* Interrupt stat clear */
+#define RCAR_SYSCEXTMASK U(0xE61802F8) /* External Request Mask */
+ /* H3/H3-N, M3 v3.0, M3-N, E3 */
/* Product register */
#define RCAR_PRR U(0xFFF00044)
#define RCAR_M3_CUT_VER11 U(0x00000010) /* M3 Ver.1.1/Ver.1.2 */
+#define RCAR_D3_CUT_VER10 U(0x00000000) /* D3 Ver.1.0 */
+#define RCAR_D3_CUT_VER11 U(0x00000010) /* D3 Ver.1.1 */
#define RCAR_MAJOR_MASK U(0x000000F0)
#define RCAR_MINOR_MASK U(0x0000000F)
#define PRR_PRODUCT_SHIFT U(8)
diff --git a/plat/renesas/common/plat_pm.c b/plat/renesas/common/plat_pm.c
index 6a9ad450d..1d4a7f634 100644
--- a/plat/renesas/common/plat_pm.c
+++ b/plat/renesas/common/plat_pm.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2021, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -128,11 +128,6 @@ static void rcar_pwr_domain_suspend(const psci_power_state_t *target_state)
rcar_pwrc_clusteroff(mpidr);
}
-
-#if RCAR_SYSTEM_SUSPEND
- if (SYSTEM_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE)
- rcar_pwrc_suspend_to_ram();
-#endif
}
static void rcar_pwr_domain_suspend_finish(const psci_power_state_t
@@ -160,6 +155,18 @@ finish:
rcar_pwr_domain_on_finish(target_state);
}
+static void __dead2 rcar_pwr_domain_pwr_down_wfi(const psci_power_state_t *target_state)
+{
+#if RCAR_SYSTEM_SUSPEND
+ if (SYSTEM_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE)
+ rcar_pwrc_suspend_to_ram();
+#endif
+ wfi();
+
+ ERROR("RCAR Power Down: operation not handled.\n");
+ panic();
+}
+
static void __dead2 rcar_system_off(void)
{
#if PMIC_ROHM_BD9571
@@ -292,6 +299,7 @@ static const plat_psci_ops_t rcar_plat_psci_ops = {
.system_off = rcar_system_off,
.system_reset = rcar_system_reset,
.validate_power_state = rcar_validate_power_state,
+ .pwr_domain_pwr_down_wfi = rcar_pwr_domain_pwr_down_wfi,
#if RCAR_SYSTEM_SUSPEND
.get_sys_suspend_power_state = rcar_get_sys_suspend_power_state,
#endif
diff --git a/plat/renesas/rcar/bl2_plat_setup.c b/plat/renesas/rcar/bl2_plat_setup.c
index 41b2d11e7..bbfa16927 100644
--- a/plat/renesas/rcar/bl2_plat_setup.c
+++ b/plat/renesas/rcar/bl2_plat_setup.c
@@ -1,9 +1,11 @@
/*
- * Copyright (c) 2018-2020, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2018-2021, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
+#include <inttypes.h>
+#include <stdint.h>
#include <string.h>
#include <libfdt.h>
@@ -263,9 +265,6 @@ void bl2_plat_flush_bl31_params(void)
if (product == PRR_PRODUCT_H3 && PRR_PRODUCT_20 > cut)
goto tlb;
- if (product == PRR_PRODUCT_D3)
- goto tlb;
-
/* Disable MFIS write protection */
mmio_write_32(MFISWPCNTR, MFISWPCNTR_PASSWORD | 1);
@@ -625,7 +624,7 @@ static void bl2_add_dram_entry(uint64_t start, uint64_t size)
return;
err:
- NOTICE("BL2: Cannot add memory node [%llx - %llx] to FDT (ret=%i)\n",
+ NOTICE("BL2: Cannot add memory node [%" PRIx64 " - %" PRIx64 "] to FDT (ret=%i)\n",
start, start + size - 1, ret);
panic();
}
@@ -641,7 +640,7 @@ static void bl2_advertise_dram_entries(uint64_t dram_config[8])
if (!size)
continue;
- NOTICE("BL2: CH%d: %llx - %llx, %lld %siB\n",
+ NOTICE("BL2: CH%d: %" PRIx64 " - %" PRIx64 ", %" PRId64 " %siB\n",
chan, start, start + size - 1,
(size >> 30) ? : size >> 20,
(size >> 30) ? "G" : "M");
@@ -708,6 +707,7 @@ static void bl2_advertise_dram_size(uint32_t product)
[4] = 0x600000000ULL,
[6] = 0x700000000ULL,
};
+ uint32_t cut = mmio_read_32(RCAR_PRR) & PRR_CUT_MASK;
switch (product) {
case PRR_PRODUCT_H3:
@@ -733,15 +733,21 @@ static void bl2_advertise_dram_size(uint32_t product)
break;
case PRR_PRODUCT_M3:
+ if (cut < PRR_PRODUCT_30) {
#if (RCAR_GEN3_ULCB == 1)
- /* 2GB(1GBx2 2ch split) */
- dram_config[1] = 0x40000000ULL;
- dram_config[5] = 0x40000000ULL;
+ /* 2GB(1GBx2 2ch split) */
+ dram_config[1] = 0x40000000ULL;
+ dram_config[5] = 0x40000000ULL;
#else
- /* 4GB(2GBx2 2ch split) */
- dram_config[1] = 0x80000000ULL;
- dram_config[5] = 0x80000000ULL;
+ /* 4GB(2GBx2 2ch split) */
+ dram_config[1] = 0x80000000ULL;
+ dram_config[5] = 0x80000000ULL;
#endif
+ } else {
+ /* 8GB(2GBx4 2ch split) */
+ dram_config[1] = 0x100000000ULL;
+ dram_config[5] = 0x100000000ULL;
+ }
break;
case PRR_PRODUCT_M3N:
@@ -897,6 +903,14 @@ void bl2_el3_early_platform_setup(u_register_t arg1, u_register_t arg2,
str,
(reg & RCAR_MINOR_MASK) + RCAR_M3_MINOR_OFFSET);
}
+ } else if (product == PRR_PRODUCT_D3) {
+ if (RCAR_D3_CUT_VER10 == (reg & PRR_CUT_MASK)) {
+ NOTICE("BL2: PRR is R-Car %s Ver.1.0\n", str);
+ } else if (RCAR_D3_CUT_VER11 == (reg & PRR_CUT_MASK)) {
+ NOTICE("BL2: PRR is R-Car %s Ver.1.1\n", str);
+ } else {
+ NOTICE("BL2: PRR is R-Car %s Ver.X.X\n", str);
+ }
} else {
major = (reg & RCAR_MAJOR_MASK) >> RCAR_MAJOR_SHIFT;
major = major + RCAR_MAJOR_OFFSET;
@@ -904,7 +918,7 @@ void bl2_el3_early_platform_setup(u_register_t arg1, u_register_t arg2,
NOTICE("BL2: PRR is R-Car %s Ver.%d.%d\n", str, major, minor);
}
- if (product == PRR_PRODUCT_E3) {
+ if (PRR_PRODUCT_E3 == product || PRR_PRODUCT_D3 == product) {
reg = mmio_read_32(RCAR_MODEMR);
sscg = reg & RCAR_SSCG_MASK;
str = sscg == RCAR_SSCG_ENABLE ? sscg_on : sscg_off;
@@ -968,10 +982,6 @@ void bl2_el3_early_platform_setup(u_register_t arg1, u_register_t arg2,
str = boot_emmc25x1;
break;
case MODEMR_BOOT_DEV_EMMC_50X8:
-#if RCAR_LSI == RCAR_D3
- ERROR("BL2: Failed to Initialize. eMMC is not supported.\n");
- panic();
-#endif
str = boot_emmc50x8;
break;
default:
diff --git a/plat/renesas/rzg/bl2_plat_setup.c b/plat/renesas/rzg/bl2_plat_setup.c
index ccc2562ee..e9dbd2058 100644
--- a/plat/renesas/rzg/bl2_plat_setup.c
+++ b/plat/renesas/rzg/bl2_plat_setup.c
@@ -4,6 +4,8 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
+#include <inttypes.h>
+#include <stdint.h>
#include <string.h>
#include <arch_helpers.h>
@@ -531,7 +533,7 @@ static void bl2_advertise_dram_entries(uint64_t dram_config[8])
continue;
}
- NOTICE("BL2: CH%d: %llx - %llx, %lld %siB\n",
+ NOTICE("BL2: CH%d: %" PRIx64 " - %" PRIx64 ", %" PRId64 " %siB\n",
chan, start, start + size - 1U,
(size >> 30) ? : size >> 20,
(size >> 30) ? "G" : "M");
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-23 12:25:09 +0000