diff options
Diffstat (limited to 'plat/xilinx/zynqmp/bl31_zynqmp_setup.c')
| -rw-r--r-- | plat/xilinx/zynqmp/bl31_zynqmp_setup.c | 102 |
1 files changed, 73 insertions, 29 deletions
diff --git a/plat/xilinx/zynqmp/bl31_zynqmp_setup.c b/plat/xilinx/zynqmp/bl31_zynqmp_setup.c index d4cd7f65b..47be4e17c 100644 --- a/plat/xilinx/zynqmp/bl31_zynqmp_setup.c +++ b/plat/xilinx/zynqmp/bl31_zynqmp_setup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2021, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -10,6 +10,7 @@ #include <bl31/bl31.h> #include <common/bl_common.h> #include <common/debug.h> +#include <drivers/arm/dcc.h> #include <drivers/console.h> #include <plat/arm/common/plat_arm.h> #include <plat/common/platform.h> @@ -19,6 +20,10 @@ #include <plat_private.h> #include <zynqmp_def.h> +#include <common/fdt_fixup.h> +#include <common/fdt_wrappers.h> +#include <libfdt.h> + static entry_point_info_t bl32_image_ep_info; static entry_point_info_t bl33_image_ep_info; @@ -62,15 +67,23 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, u_register_t arg2, u_register_t arg3) { uint64_t atf_handoff_addr; - /* Register the console to provide early debug support */ - static console_t bl31_boot_console; - (void)console_cdns_register(ZYNQMP_UART_BASE, - zynqmp_get_uart_clk(), - ZYNQMP_UART_BAUDRATE, - &bl31_boot_console); - console_set_scope(&bl31_boot_console, - CONSOLE_FLAG_RUNTIME | CONSOLE_FLAG_BOOT); + if (ZYNQMP_CONSOLE_IS(cadence)) { + /* Register the console to provide early debug support */ + static console_t bl31_boot_console; + (void)console_cdns_register(ZYNQMP_UART_BASE, + zynqmp_get_uart_clk(), + ZYNQMP_UART_BAUDRATE, + &bl31_boot_console); + console_set_scope(&bl31_boot_console, + CONSOLE_FLAG_RUNTIME | CONSOLE_FLAG_BOOT); + } else if (ZYNQMP_CONSOLE_IS(dcc)) { + /* Initialize the dcc console for debug */ + int rc = console_dcc_register(); + if (rc == 0) { + panic(); + } + } /* Initialize the platform config for future decision making */ zynqmp_config_setup(); @@ -114,25 +127,6 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, } } -/* Enable the test setup */ -#ifndef ZYNQMP_TESTING -static void zynqmp_testing_setup(void) { } -#else -static void zynqmp_testing_setup(void) -{ - uint32_t actlr_el3, actlr_el2; - - /* Enable CPU ACTLR AND L2ACTLR RW access from non-secure world */ - actlr_el3 = read_actlr_el3(); - actlr_el2 = read_actlr_el2(); - - actlr_el3 |= ACTLR_EL3_L2ACTLR_BIT | ACTLR_EL3_CPUACTLR_BIT; - actlr_el2 |= ACTLR_EL3_L2ACTLR_BIT | ACTLR_EL3_CPUACTLR_BIT; - write_actlr_el3(actlr_el3); - write_actlr_el2(actlr_el2); -} -#endif - #if ZYNQMP_WDT_RESTART static interrupt_type_handler_t type_el3_interrupt_table[MAX_INTR_EL3]; @@ -169,12 +163,58 @@ static uint64_t rdo_el3_interrupt_handler(uint32_t id, uint32_t flags, } #endif +#if (BL31_LIMIT < PLAT_DDR_LOWMEM_MAX) +static void prepare_dtb(void) +{ + void *dtb = (void *)XILINX_OF_BOARD_DTB_ADDR; + int ret; + + /* Return if no device tree is detected */ + if (fdt_check_header(dtb) != 0) { + NOTICE("Can't read DT at 0x%p\n", dtb); + return; + } + + ret = fdt_open_into(dtb, dtb, XILINX_OF_BOARD_DTB_MAX_SIZE); + if (ret < 0) { + ERROR("Invalid Device Tree at %p: error %d\n", dtb, ret); + return; + } + + if (dt_add_psci_node(dtb)) { + ERROR("Failed to add PSCI Device Tree node\n"); + return; + } + + if (dt_add_psci_cpu_enable_methods(dtb)) { + ERROR("Failed to add PSCI cpu enable methods in Device Tree\n"); + return; + } + + /* Reserve memory used by Trusted Firmware. */ + if (fdt_add_reserved_memory(dtb, "tf-a", BL31_BASE, BL31_LIMIT - BL31_BASE)) { + WARN("Failed to add reserved memory nodes to DT.\n"); + } + + ret = fdt_pack(dtb); + if (ret < 0) { + ERROR("Failed to pack Device Tree at %p: error %d\n", dtb, ret); + } + + clean_dcache_range((uintptr_t)dtb, fdt_blob_size(dtb)); + INFO("Changed device tree to advertise PSCI and reserved memories.\n"); +} +#endif + void bl31_platform_setup(void) { +#if (BL31_LIMIT < PLAT_DDR_LOWMEM_MAX) + prepare_dtb(); +#endif + /* Initialize the gic cpu and distributor interfaces */ plat_arm_gic_driver_init(); plat_arm_gic_init(); - zynqmp_testing_setup(); } void bl31_plat_runtime_setup(void) @@ -202,6 +242,10 @@ void bl31_plat_arch_setup(void) const mmap_region_t bl_regions[] = { +#if (BL31_LIMIT < PLAT_DDR_LOWMEM_MAX) + MAP_REGION_FLAT(XILINX_OF_BOARD_DTB_ADDR, XILINX_OF_BOARD_DTB_MAX_SIZE, + MT_MEMORY | MT_RW | MT_NS), +#endif MAP_REGION_FLAT(BL31_BASE, BL31_END - BL31_BASE, MT_MEMORY | MT_RW | MT_SECURE), MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, |