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author | Teresa Charlin <teresa.charlinreyes@arm.com> | 2023-03-23 15:28:02 +0000 |
---|---|---|
committer | TeresaARM <teresa.charlinreyes@arm.com> | 2023-04-19 08:54:57 +0000 |
commit | 93f0ad0016a6450670fbf650568f5724c7bbb63e (patch) | |
tree | efb5f687ff93bf34bae1fe9d218124b57c2681ac /src | |
parent | acb3ec51e51542d3011ed87842f87c2261abaaff (diff) | |
download | armnn-93f0ad0016a6450670fbf650568f5724c7bbb63e.tar.gz |
GitHub #640 Add support for CEIL operator
* Reference workload
* TfLite Delegate
* TfLite Parser
* Serializer and Deserializer
* Changed fallback tests in delegate to use COS instead of CEIL
Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com>
Signed-off-by: Mike Kelly <mike.kelly@arm.com>
Change-Id: I36e0dbff33694182d1dba0c95d463506428e2f04
Diffstat (limited to 'src')
-rw-r--r-- | src/armnnDeserializer/Deserializer.cpp | 2 | ||||
-rw-r--r-- | src/armnnDeserializer/test/DeserializeElementwiseUnary.cpp | 19 | ||||
-rw-r--r-- | src/armnnSerializer/ArmnnSchema.fbs | 3 | ||||
-rw-r--r-- | src/armnnSerializer/SerializerUtils.cpp | 2 | ||||
-rw-r--r-- | src/armnnSerializer/test/SerializerTests.cpp | 2 | ||||
-rw-r--r-- | src/armnnTfLiteParser/TfLiteParser.cpp | 6 | ||||
-rw-r--r-- | src/armnnTfLiteParser/TfLiteParser.hpp | 1 | ||||
-rw-r--r-- | src/armnnTfLiteParser/test/ElementWiseUnary.cpp | 13 | ||||
-rw-r--r-- | src/backends/reference/workloads/Ceil.hpp | 25 | ||||
-rw-r--r-- | src/backends/reference/workloads/ElementwiseFunction.cpp | 5 | ||||
-rw-r--r-- | src/backends/reference/workloads/RefElementwiseUnaryWorkload.cpp | 9 |
11 files changed, 80 insertions, 7 deletions
diff --git a/src/armnnDeserializer/Deserializer.cpp b/src/armnnDeserializer/Deserializer.cpp index ed921880e..3bd24bd9d 100644 --- a/src/armnnDeserializer/Deserializer.cpp +++ b/src/armnnDeserializer/Deserializer.cpp @@ -592,6 +592,8 @@ armnn::UnaryOperation ToElementwiseUnaryOperation(armnnSerializer::UnaryOperatio { case armnnSerializer::UnaryOperation::UnaryOperation_Abs: return armnn::UnaryOperation::Abs; + case armnnSerializer::UnaryOperation::UnaryOperation_Ceil: + return armnn::UnaryOperation::Ceil; case armnnSerializer::UnaryOperation::UnaryOperation_Rsqrt: return armnn::UnaryOperation::Rsqrt; case armnnSerializer::UnaryOperation::UnaryOperation_Sqrt: diff --git a/src/armnnDeserializer/test/DeserializeElementwiseUnary.cpp b/src/armnnDeserializer/test/DeserializeElementwiseUnary.cpp index 0a89f48f1..b62fb07ca 100644 --- a/src/armnnDeserializer/test/DeserializeElementwiseUnary.cpp +++ b/src/armnnDeserializer/test/DeserializeElementwiseUnary.cpp @@ -1,5 +1,5 @@ // -// Copyright © 2021 Arm Ltd and Contributors. All rights reserved. +// Copyright © 2021,2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // @@ -170,4 +170,21 @@ FIXTURE_TEST_CASE(SimpleSinTest, SimpleSinFixture) {{"OutputLayer", {0.50636564111f, -0.23237376165f, -0.76249375473f, -0.4794255386f, 0.0f, 0.99988301347f, 0.35905835402f, -0.50636564111f}}}); } + +struct SimpleCeilFixture : ElementwiseUnaryFixture +{ + SimpleCeilFixture() : ElementwiseUnaryFixture("[ 1, 2, 2, 2 ]", // inputShape + "[ 1, 2, 2, 2 ]", // outputShape + "Float32", // dataType + "Ceil") // unaryOperation + {} +}; + +FIXTURE_TEST_CASE(SimpleCeilTest, SimpleCeilFixture) +{ + RunTest<4, armnn::DataType::Float32>( + 0, + {{"InputLayer", {-100.0f, -50.5f, -25.9999f, -0.5f, 0.0f, 1.5555f, 25.5f, 100.0f}}}, + {{"OutputLayer", {-100.0f, -50.0f, -25.0f, 0.0f, 0.0f, 2.0f, 26.0f, 100.0f}}}); +} }
\ No newline at end of file diff --git a/src/armnnSerializer/ArmnnSchema.fbs b/src/armnnSerializer/ArmnnSchema.fbs index fb3bc018b..a8b5d72da 100644 --- a/src/armnnSerializer/ArmnnSchema.fbs +++ b/src/armnnSerializer/ArmnnSchema.fbs @@ -351,7 +351,8 @@ enum UnaryOperation : byte { Neg = 4, LogicalNot = 5, Log = 6, - Sin = 7 + Sin = 7, + Ceil = 8 } table ElementwiseUnaryDescriptor { diff --git a/src/armnnSerializer/SerializerUtils.cpp b/src/armnnSerializer/SerializerUtils.cpp index 703f56ff5..2188fdccd 100644 --- a/src/armnnSerializer/SerializerUtils.cpp +++ b/src/armnnSerializer/SerializerUtils.cpp @@ -134,6 +134,8 @@ armnnSerializer::UnaryOperation GetFlatBufferUnaryOperation(armnn::UnaryOperatio { case armnn::UnaryOperation::Abs: return armnnSerializer::UnaryOperation::UnaryOperation_Abs; + case armnn::UnaryOperation::Ceil: + return armnnSerializer::UnaryOperation::UnaryOperation_Ceil; case armnn::UnaryOperation::Rsqrt: return armnnSerializer::UnaryOperation::UnaryOperation_Rsqrt; case armnn::UnaryOperation::Sqrt: diff --git a/src/armnnSerializer/test/SerializerTests.cpp b/src/armnnSerializer/test/SerializerTests.cpp index 90d778991..6b9b5df1e 100644 --- a/src/armnnSerializer/test/SerializerTests.cpp +++ b/src/armnnSerializer/test/SerializerTests.cpp @@ -1056,7 +1056,7 @@ void SerializeElementwiseUnaryTest(armnn::UnaryOperation unaryOperation) TEST_CASE("SerializeElementwiseUnary") { using op = armnn::UnaryOperation; - std::initializer_list<op> allUnaryOperations = {op::Abs, op::Exp, op::Sqrt, op::Rsqrt, op::Neg, + std::initializer_list<op> allUnaryOperations = {op::Abs, op::Ceil, op::Exp, op::Sqrt, op::Rsqrt, op::Neg, op::LogicalNot, op::Log, op::Sin}; for (auto unaryOperation : allUnaryOperations) diff --git a/src/armnnTfLiteParser/TfLiteParser.cpp b/src/armnnTfLiteParser/TfLiteParser.cpp index ee4cadd21..2a7f04947 100644 --- a/src/armnnTfLiteParser/TfLiteParser.cpp +++ b/src/armnnTfLiteParser/TfLiteParser.cpp @@ -729,6 +729,7 @@ TfLiteParserImpl::TfLiteParserImpl(const Optional<ITfLiteParser::TfLiteParserOpt m_ParserFunctions[tflite::BuiltinOperator_AVERAGE_POOL_2D] = &TfLiteParserImpl::ParseAveragePool2D; m_ParserFunctions[tflite::BuiltinOperator_BATCH_TO_SPACE_ND] = &TfLiteParserImpl::ParseBatchToSpaceND; m_ParserFunctions[tflite::BuiltinOperator_BATCH_MATMUL] = &TfLiteParserImpl::ParseBatchMatMul; + m_ParserFunctions[tflite::BuiltinOperator_CEIL] = &TfLiteParserImpl::ParseCeil; m_ParserFunctions[tflite::BuiltinOperator_CAST] = &TfLiteParserImpl::ParseCast; m_ParserFunctions[tflite::BuiltinOperator_CONCATENATION] = &TfLiteParserImpl::ParseConcatenation; m_ParserFunctions[tflite::BuiltinOperator_CONV_2D] = &TfLiteParserImpl::ParseConv2D; @@ -4509,6 +4510,11 @@ void TfLiteParserImpl::ParseAbs(size_t subgraphIndex, size_t operatorIndex) ParseElementwiseUnary(subgraphIndex, operatorIndex, armnn::UnaryOperation::Abs); } +void TfLiteParserImpl::ParseCeil(size_t subgraphIndex, size_t operatorIndex) +{ + ParseElementwiseUnary(subgraphIndex, operatorIndex, armnn::UnaryOperation::Ceil); +} + void TfLiteParserImpl::ParseExp(size_t subgraphIndex, size_t operatorIndex) { ParseElementwiseUnary(subgraphIndex, operatorIndex, armnn::UnaryOperation::Exp); diff --git a/src/armnnTfLiteParser/TfLiteParser.hpp b/src/armnnTfLiteParser/TfLiteParser.hpp index ec03c23a5..91fad43b8 100644 --- a/src/armnnTfLiteParser/TfLiteParser.hpp +++ b/src/armnnTfLiteParser/TfLiteParser.hpp @@ -118,6 +118,7 @@ private: void ParseBatchMatMul(size_t subgraphIndex, size_t operatorIndex); void ParseBatchToSpaceND(size_t subgraphIndex, size_t operatorIndex); void ParseCast(size_t subgraphIndex, size_t operatorIndex); + void ParseCeil(size_t subgraphIndex, size_t operatorIndex); void ParseComparison(size_t subgraphIndex, size_t operatorIndex, armnn::ComparisonOperation comparisonOperation); void ParseConcatenation(size_t subgraphIndex, size_t operatorIndex); void ParseConv2D(size_t subgraphIndex, size_t operatorIndex); diff --git a/src/armnnTfLiteParser/test/ElementWiseUnary.cpp b/src/armnnTfLiteParser/test/ElementWiseUnary.cpp index 67c2080d6..ffdf1cca6 100644 --- a/src/armnnTfLiteParser/test/ElementWiseUnary.cpp +++ b/src/armnnTfLiteParser/test/ElementWiseUnary.cpp @@ -1,5 +1,5 @@ // -// Copyright © 2022 Arm Ltd and Contributors. All rights reserved. +// Copyright © 2021-2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // @@ -180,4 +180,15 @@ TEST_CASE_FIXTURE(SimpleSinFixture, "ParseSin") 0.4794255386f, -0.99177885344f, -0.8414709848f} }}); } +struct SimpleCeilFixture : public ElementWiseUnaryFixture +{ + SimpleCeilFixture() : ElementWiseUnaryFixture("CEIL", "FLOAT32", "[ 1, 2, 3, 1 ]", "[ 1, 2, 3, 1 ]") {} +}; + +TEST_CASE_FIXTURE(SimpleCeilFixture, "ParseCeil") +{ + RunTest<4, armnn::DataType::Float32>(0, {{ "inputTensor", { -50.5f, -25.9999f, -0.5f, 0.0f, 1.5555f, 25.5f } }}, + {{ "outputTensor",{ -50.0f, -25.0f, 0.0f, 0.0f, 2.0f, 26.0f} }}); +} + } diff --git a/src/backends/reference/workloads/Ceil.hpp b/src/backends/reference/workloads/Ceil.hpp new file mode 100644 index 000000000..2e415b9c0 --- /dev/null +++ b/src/backends/reference/workloads/Ceil.hpp @@ -0,0 +1,25 @@ +// +// Copyright © 2023 Arm Ltd and Contributors. All rights reserved. +// SPDX-License-Identifier: MIT +// + +#pragma once + +#include <iostream> + +namespace armnn +{ +template<typename T> +struct ceil + { + typedef T result_type; + typedef T argument_type; + + T + operator () (const T& inputData) const + { + return std::ceil(inputData); + } + }; + +} //namespace armnn diff --git a/src/backends/reference/workloads/ElementwiseFunction.cpp b/src/backends/reference/workloads/ElementwiseFunction.cpp index 82bcf9928..c5b0ad1f2 100644 --- a/src/backends/reference/workloads/ElementwiseFunction.cpp +++ b/src/backends/reference/workloads/ElementwiseFunction.cpp @@ -1,14 +1,14 @@ // -// Copyright © 2017 Arm Ltd and Contributors. All rights reserved. +// Copyright © 2017-2021,2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #include "ElementwiseFunction.hpp" #include "Broadcast.hpp" -#include <functional> #include "Minimum.hpp" #include "Maximum.hpp" #include "Abs.hpp" +#include "Ceil.hpp" #include "Exp.hpp" #include "Log.hpp" #include "Rsqrt.hpp" @@ -85,6 +85,7 @@ template struct armnn::ElementwiseBinaryFunction<std::not_equal_to<float>>; // Unary template struct armnn::ElementwiseUnaryFunction<armnn::abs<float>>; +template struct armnn::ElementwiseUnaryFunction<armnn::ceil<float>>; template struct armnn::ElementwiseUnaryFunction<armnn::exp<float>>; template struct armnn::ElementwiseUnaryFunction<armnn::log<float>>; template struct armnn::ElementwiseUnaryFunction<std::negate<float>>; diff --git a/src/backends/reference/workloads/RefElementwiseUnaryWorkload.cpp b/src/backends/reference/workloads/RefElementwiseUnaryWorkload.cpp index 4bd5a51a5..f4775e0c1 100644 --- a/src/backends/reference/workloads/RefElementwiseUnaryWorkload.cpp +++ b/src/backends/reference/workloads/RefElementwiseUnaryWorkload.cpp @@ -1,5 +1,5 @@ // -// Copyright © 2022 Arm Ltd and Contributors. All rights reserved. +// Copyright © 2020-2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // @@ -10,6 +10,7 @@ #include "Encoders.hpp" #include "RefWorkloadUtils.hpp" #include "Abs.hpp" +#include "Ceil.hpp" #include "Exp.hpp" #include "Log.hpp" #include "Rsqrt.hpp" @@ -56,6 +57,7 @@ void RefElementwiseUnaryWorkload::Execute(std::vector<ITensorHandle*> inputs, st std::unique_ptr<Encoder<OutType>> output= MakeEncoder<OutType>(outputInfo, outputs[0]->Map()); using AbsFunction = ElementwiseUnaryFunction<abs<InType>>; + using CeilFunction = ElementwiseUnaryFunction<ceil<InType>>; using ExpFunction = ElementwiseUnaryFunction<exp<InType>>; using LogFunction = ElementwiseUnaryFunction<log<InType>>; using NegFunction = ElementwiseUnaryFunction<std::negate<InType>>; @@ -70,6 +72,11 @@ void RefElementwiseUnaryWorkload::Execute(std::vector<ITensorHandle*> inputs, st AbsFunction(inShape, outShape, *input, *output); break; } + case UnaryOperation::Ceil: + { + CeilFunction(inShape, outShape, *input, *output); + break; + } case UnaryOperation::Exp: { ExpFunction(inShape, outShape, *input, *output); |