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authorArvind Sudarsanam <arvind.sudarsanam@intel.com>2023-03-07 18:09:58 -0800
committerArvind Sudarsanam <arvind.sudarsanam@intel.com>2023-03-07 18:09:58 -0800
commit391c490359e75875bb641a577a36cd37b9114631 (patch)
tree580f7307f438d58ea6a7f7f59a7b0a44195e90c7 /include/spirv/unified1/spirv.hpp
parent78a1e8aaa4d3922a641e04492a8c65cbd373a93e (diff)
parent295cf5fb3bfe2454360e82b26bae7fc0de699abe (diff)
downloadSPIRV-Headers-391c490359e75875bb641a577a36cd37b9114631.tar.gz
Merge remote-tracking branch 'real-origin/main' into asudarsa/add_fpga_latency_control_ext
Diffstat (limited to 'include/spirv/unified1/spirv.hpp')
-rw-r--r--include/spirv/unified1/spirv.hpp2
1 files changed, 2 insertions, 0 deletions
diff --git a/include/spirv/unified1/spirv.hpp b/include/spirv/unified1/spirv.hpp
index 55fded6..5b458f7 100644
--- a/include/spirv/unified1/spirv.hpp
+++ b/include/spirv/unified1/spirv.hpp
@@ -196,6 +196,7 @@ enum ExecutionMode {
ExecutionModeNumSIMDWorkitemsINTEL = 5896,
ExecutionModeSchedulerTargetFmaxMhzINTEL = 5903,
ExecutionModeStreamingInterfaceINTEL = 6154,
+ ExecutionModeRegisterMapInterfaceINTEL = 6160,
ExecutionModeNamedBarrierCountINTEL = 6417,
ExecutionModeMax = 0x7fffffff,
};
@@ -1144,6 +1145,7 @@ enum Capability {
CapabilityAtomicFloat16AddEXT = 6095,
CapabilityDebugInfoModuleINTEL = 6114,
CapabilitySplitBarrierINTEL = 6141,
+ CapabilityFPGAKernelAttributesv2INTEL = 6161,
CapabilityFPGALatencyControlINTEL = 6171,
CapabilityFPGAArgumentInterfacesINTEL = 6174,
CapabilityGroupUniformArithmeticKHR = 6400,