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| author | David Neto <dneto@google.com> | 2024-01-24 16:06:13 -0500 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-01-24 16:06:13 -0500 |
| commit | ae6a8b39717523d96683bc0d20b541944e28072f (patch) | |
| tree | b8802dd0aeea819b730c6ef01e60d8c1deedaed0 /include/spirv/unified1/spirv.hpp | |
| parent | 2b9ba211f3bde10dc638badc59157f7cd7e28d63 (diff) | |
| download | SPIRV-Headers-ae6a8b39717523d96683bc0d20b541944e28072f.tar.gz | |
SPV_KHR_float_controls2 (#409)
Diffstat (limited to 'include/spirv/unified1/spirv.hpp')
| -rw-r--r-- | include/spirv/unified1/spirv.hpp | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/include/spirv/unified1/spirv.hpp b/include/spirv/unified1/spirv.hpp index dafaf46..ee1de78 100644 --- a/include/spirv/unified1/spirv.hpp +++ b/include/spirv/unified1/spirv.hpp @@ -209,6 +209,7 @@ enum ExecutionMode { ExecutionModeNumSIMDWorkitemsINTEL = 5896, ExecutionModeSchedulerTargetFmaxMhzINTEL = 5903, ExecutionModeMaximallyReconvergesKHR = 6023, + ExecutionModeFPFastMathDefault = 6028, ExecutionModeStreamingInterfaceINTEL = 6154, ExecutionModeRegisterMapInterfaceINTEL = 6160, ExecutionModeNamedBarrierCountINTEL = 6417, @@ -428,8 +429,11 @@ enum FPFastMathModeShift { FPFastMathModeNSZShift = 2, FPFastMathModeAllowRecipShift = 3, FPFastMathModeFastShift = 4, + FPFastMathModeAllowContractShift = 16, FPFastMathModeAllowContractFastINTELShift = 16, + FPFastMathModeAllowReassocShift = 17, FPFastMathModeAllowReassocINTELShift = 17, + FPFastMathModeAllowTransformShift = 18, FPFastMathModeMax = 0x7fffffff, }; @@ -440,8 +444,11 @@ enum FPFastMathModeMask { FPFastMathModeNSZMask = 0x00000004, FPFastMathModeAllowRecipMask = 0x00000008, FPFastMathModeFastMask = 0x00000010, + FPFastMathModeAllowContractMask = 0x00010000, FPFastMathModeAllowContractFastINTELMask = 0x00010000, + FPFastMathModeAllowReassocMask = 0x00020000, FPFastMathModeAllowReassocINTELMask = 0x00020000, + FPFastMathModeAllowTransformMask = 0x00040000, }; enum FPRoundingMode { @@ -1193,6 +1200,7 @@ enum Capability { CapabilityCooperativeMatrixKHR = 6022, CapabilityBitInstructions = 6025, CapabilityGroupNonUniformRotateKHR = 6026, + CapabilityFloatControls2 = 6029, CapabilityAtomicFloat32AddEXT = 6033, CapabilityAtomicFloat64AddEXT = 6034, CapabilityLongCompositesINTEL = 6089, |