Add RISC-V register names

RISC-V register names are needed in order to load DWARF call frame
information.

Bug: fuchsia:124084
Change-Id: I2791b3a38ea35ddc2bb293f60f75dcc86338e354
Reviewed-on: https://chromium-review.googlesource.com/c/breakpad/breakpad/+/4376827
Reviewed-by: Mike Frysinger <vapier@chromium.org>

4 files changed, 41 insertions, 0 deletions

diff --git a/src/common/dwarf_cfi_to_module.cc b/src/common/dwarf_cfi_to_module.cc
index 287c851e..7e04d3c5 100644
--- a/src/common/dwarf_cfi_to_module.cc
+++ b/src/common/dwarf_cfi_to_module.cc
@@ -147,6 +147,29 @@ vector<string> DwarfCFIToModule::RegisterNames::MIPS() {
                     sizeof(kRegisterNames) / sizeof(kRegisterNames[0]));
 }
 
+vector<string> DwarfCFIToModule::RegisterNames::RISCV() {
+  static const char *const names[] = {
+    "x0",  "x1",  "x2",  "x3",  "x4",  "x5",  "x6",  "x7",
+    "x8",  "x9",  "x10", "x11", "x12", "x13", "x14", "x15",
+    "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",
+    "x24", "x25", "x26", "x27", "x28", "x29", "x30", "x31",
+    "f0",  "f1",  "f2",  "f3",  "f4",  "f5",  "f6",  "f7",
+    "f8",  "f9",  "f10", "f11", "f12", "f13", "f14", "f15",
+    "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
+    "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
+    "",    "",    "",    "",    "",    "",    "",    "",
+    "",    "",    "",    "",    "",    "",    "",    "",
+    "",    "",    "",    "",    "",    "",    "",    "",
+    "",    "",    "",    "",    "",    "",    "",    "",
+    "v0",  "v1",  "v2",  "v3",  "v4",  "v5",  "v6",  "v7",
+    "v8",  "v9",  "v10", "v11", "v12", "v13", "v14", "v15",
+    "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
+    "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31"
+  };
+
+  return MakeVector(names, sizeof(names) / sizeof(names[0]));
+}
+
 bool DwarfCFIToModule::Entry(size_t offset, uint64_t address, uint64_t length,
                              uint8_t version, const string& augmentation,
                              unsigned return_address) {
diff --git a/src/common/dwarf_cfi_to_module.h b/src/common/dwarf_cfi_to_module.h
index 42b618d5..19297db9 100644
--- a/src/common/dwarf_cfi_to_module.h
+++ b/src/common/dwarf_cfi_to_module.h
@@ -114,6 +114,9 @@ class DwarfCFIToModule: public CallFrameInfo::Handler {
     // MIPS.
     static vector<string> MIPS();
 
+    // RISC-V.
+    static vector<string> RISCV();
+
    private:
     // Given STRINGS, an array of C strings with SIZE elements, return an
     // equivalent vector<string>.
diff --git a/src/common/dwarf_cfi_to_module_unittest.cc b/src/common/dwarf_cfi_to_module_unittest.cc
index 43b5e7c4..b407edd0 100644
--- a/src/common/dwarf_cfi_to_module_unittest.cc
+++ b/src/common/dwarf_cfi_to_module_unittest.cc
@@ -307,3 +307,15 @@ TEST(RegisterNames, X86_64) {
   EXPECT_EQ("$rsp", names[7]);
   EXPECT_EQ("$rip", names[16]);
 }
+
+TEST(RegisterNames, RISCV) {
+  vector<string> names = DwarfCFIToModule::RegisterNames::RISCV();
+
+  EXPECT_EQ("x0", names[0]);
+  EXPECT_EQ("x31", names[31]);
+  EXPECT_EQ("f0", names[32]);
+  EXPECT_EQ("f31", names[63]);
+  EXPECT_EQ("v0", names[96]);
+  EXPECT_EQ("v31", names[127]);
+}
+
diff --git a/src/common/linux/dump_symbols.cc b/src/common/linux/dump_symbols.cc
index 36687bf4..8179663b 100644
--- a/src/common/linux/dump_symbols.cc
+++ b/src/common/linux/dump_symbols.cc
@@ -449,6 +449,9 @@ bool DwarfCFIRegisterNames(const typename ElfClass::Ehdr* elf_header,
     case EM_X86_64:
       *register_names = DwarfCFIToModule::RegisterNames::X86_64();
       return true;
+    case EM_RISCV:
+      *register_names = DwarfCFIToModule::RegisterNames::RISCV();
+      return true;
     default:
       return false;
   }