Merge remote-tracking branch 'upstream/master' into rebase

571 files changed, 11189 insertions, 22957 deletions

diff --git a/cmake/modules/AddSphinxTarget.cmake b/cmake/modules/AddSphinxTarget.cmake
index 1ba77a4d24..fc28a49407 100644
--- a/cmake/modules/AddSphinxTarget.cmake
+++ b/cmake/modules/AddSphinxTarget.cmake
@@ -39,16 +39,18 @@ function (add_sphinx_target builder project)
     add_dependencies(sphinx ${SPHINX_TARGET_NAME})
 
     # Handle installation
-    if (builder STREQUAL man)
-      # FIXME: We might not ship all the tools that these man pages describe
-      install(DIRECTORY "${SPHINX_BUILD_DIR}/" # Slash indicates contents of
-              DESTINATION share/man/man1)
+    if (NOT LLVM_INSTALL_TOOLCHAIN_ONLY)
+      if (builder STREQUAL man)
+        # FIXME: We might not ship all the tools that these man pages describe
+        install(DIRECTORY "${SPHINX_BUILD_DIR}/" # Slash indicates contents of
+                DESTINATION share/man/man1)
 
-    elseif (builder STREQUAL html)
-      install(DIRECTORY "${SPHINX_BUILD_DIR}"
-              DESTINATION "share/doc/${project}")
-    else()
-      message(WARNING Installation of ${builder} not supported)
+      elseif (builder STREQUAL html)
+        install(DIRECTORY "${SPHINX_BUILD_DIR}"
+                DESTINATION "share/doc/${project}")
+      else()
+        message(WARNING Installation of ${builder} not supported)
+      endif()
     endif()
   endif()
 endfunction()
diff --git a/docs/CMake.rst b/docs/CMake.rst
index f0f1726879..ce71dab6fc 100644
--- a/docs/CMake.rst
+++ b/docs/CMake.rst
@@ -283,6 +283,12 @@ LLVM-specific variables
   are ``Address``, ``Memory`` and ``MemoryWithOrigins``. Defaults to empty
   string.
 
+**LLVM_BUILD_DOCS**:BOOL
+  Enables all enabled documentation targets (i.e. Doxgyen and Sphinx targets) to
+  be built as part of the normal build. If the ``install`` target is run then
+  this also enables all built documentation targets to be installed. Defaults to
+  OFF.
+
 **LLVM_ENABLE_DOXYGEN**:BOOL
   Enables the generation of browsable HTML documentation using doxygen.
   Defaults to OFF.
@@ -328,6 +334,27 @@ LLVM-specific variables
   ``-DLLVM_ENABLE_DOXYGEN_QT_HELP=ON``; otherwise this has no
   effect.
 
+**LLVM_ENABLE_SPHINX**:BOOL
+  If enabled CMake will search for the ``sphinx-build`` executable and will make
+  the ``SPHINX_OUTPUT_HTML`` and ``SPHINX_OUTPUT_MAN`` CMake options available.
+  Defaults to OFF.
+
+**SPHINX_EXECUTABLE**:STRING
+  The path to the ``sphinx-build`` executable detected by CMake.
+
+**SPHINX_OUTPUT_HTML**:BOOL
+  If enabled (and ``LLVM_ENABLE_SPHINX`` is enabled) then the targets for
+  building the documentation as html are added (but not built by default unless
+  ``LLVM_BUILD_DOCS`` is enabled). There is a target for each project in the
+  source tree that uses sphinx (e.g.  ``docs-llvm-html``, ``docs-clang-html``
+  and ``docs-lld-html``). Defaults to ON.
+
+**SPHINX_OUTPUT_MAN**:BOOL
+  If enabled (and ``LLVM_ENABLE_SPHINX`` is enabled) the targets for building
+  the man pages are added (but not built by default unless ``LLVM_BUILD_DOCS``
+  is enabled). Currently the only target added is ``docs-llvm-man``. Defaults
+  to ON.
+
 Executing the test suite
 ========================
 
diff --git a/docs/Extensions.rst b/docs/Extensions.rst
index 7d8c521ec4..9dddab5b5e 100644
--- a/docs/Extensions.rst
+++ b/docs/Extensions.rst
@@ -159,3 +159,34 @@ different COMDATs:
   .globl Symbol2
   Symbol2:
   .long 1
+
+Target Specific Behaviour
+=========================
+
+Windows on ARM
+--------------
+
+Stack Probe Emission
+^^^^^^^^^^^^^^^^^^^^
+
+The reference implementation (Microsoft Visual Studio 2012) emits stack probes
+in the following fashion:
+
+.. code-block:: gas
+
+  movw r4, #constant
+  bl __chkstk
+  sub.w sp, sp, r4
+
+However, this has the limitation of 32 MiB (±16MiB).  In order to accomodate
+larger binaries, LLVM supports the use of ``-mcode-model=large`` to allow a 4GiB
+range via a slight deviation.  It will generate an indirect jump as follows:
+
+.. code-block:: gas
+
+  movw r4, #constant
+  movw r12, :lower16:__chkstk
+  movt r12, :upper16:__chkstk
+  blx r12
+  sub.w sp, sp, r4
+
diff --git a/examples/BrainF/BrainFDriver.cpp b/examples/BrainF/BrainFDriver.cpp
index d726464a52..e2de6bc58d 100644
--- a/examples/BrainF/BrainFDriver.cpp
+++ b/examples/BrainF/BrainFDriver.cpp
@@ -31,6 +31,7 @@
 #include "llvm/IR/Constants.h"
 #include "llvm/IR/Verifier.h"
 #include "llvm/Support/CommandLine.h"
+#include "llvm/Support/FileSystem.h"
 #include "llvm/Support/ManagedStatic.h"
 #include "llvm/Support/TargetSelect.h"
 #include "llvm/Support/raw_ostream.h"
diff --git a/include/llvm/ADT/PointerUnion.h b/include/llvm/ADT/PointerUnion.h
index dafd0e0510..a6dddd2776 100644
--- a/include/llvm/ADT/PointerUnion.h
+++ b/include/llvm/ADT/PointerUnion.h
@@ -154,6 +154,12 @@ namespace llvm {
          "Can't get the address because PointerLikeTypeTraits changes the ptr");
       return (PT1 *)Val.getAddrOfPointer();
     }
+
+    /// \brief Assignment from nullptr which just clears the union.
+    const PointerUnion &operator=(std::nullptr_t) {
+      Val.initWithPointer(nullptr);
+      return *this;
+    }
     
     /// Assignment operators - Allow assigning into this union from either
     /// pointer type, setting the discriminator to remember what it came from.
@@ -298,6 +304,12 @@ namespace llvm {
       if (is<T>()) return get<T>();
       return T();
     }
+
+    /// \brief Assignment from nullptr which just clears the union.
+    const PointerUnion3 &operator=(std::nullptr_t) {
+      Val = nullptr;
+      return *this;
+    }
     
     /// Assignment operators - Allow assigning into this union from either
     /// pointer type, setting the discriminator to remember what it came from.
@@ -407,6 +419,12 @@ namespace llvm {
       if (is<T>()) return get<T>();
       return T();
     }
+
+    /// \brief Assignment from nullptr which just clears the union.
+    const PointerUnion4 &operator=(std::nullptr_t) {
+      Val = nullptr;
+      return *this;
+    }
     
     /// Assignment operators - Allow assigning into this union from either
     /// pointer type, setting the discriminator to remember what it came from.
diff --git a/include/llvm/ADT/SmallVector.h b/include/llvm/ADT/SmallVector.h
index df46f91911..dcf0354860 100644
--- a/include/llvm/ADT/SmallVector.h
+++ b/include/llvm/ADT/SmallVector.h
@@ -805,7 +805,7 @@ SmallVectorImpl<T> &SmallVectorImpl<T>::operator=(SmallVectorImpl<T> &&RHS) {
     this->grow(RHSSize);
   } else if (CurSize) {
     // Otherwise, use assignment for the already-constructed elements.
-    this->move(RHS.begin(), RHS.end(), this->begin());
+    this->move(RHS.begin(), RHS.begin()+CurSize, this->begin());
   }
 
   // Move-construct the new elements in place.
diff --git a/include/llvm/ADT/iterator.h b/include/llvm/ADT/iterator.h
index af9b85c56c..56041dbb10 100644
--- a/include/llvm/ADT/iterator.h
+++ b/include/llvm/ADT/iterator.h
@@ -35,18 +35,36 @@ namespace llvm {
 template <typename DerivedT, typename IteratorCategoryT, typename T,
           typename DifferenceTypeT = std::ptrdiff_t, typename PointerT = T *,
           typename ReferenceT = T &>
-struct iterator_facade_base
-    : std::iterator<IteratorCategoryT, T, DifferenceTypeT, PointerT,
-                    ReferenceT> {
+class iterator_facade_base
+    : public std::iterator<IteratorCategoryT, T, DifferenceTypeT, PointerT,
+                           ReferenceT> {
+protected:
+  enum {
+    IsRandomAccess =
+        std::is_base_of<std::random_access_iterator_tag, IteratorCategoryT>::value,
+    IsBidirectional =
+        std::is_base_of<std::bidirectional_iterator_tag, IteratorCategoryT>::value,
+  };
+
+public:
   DerivedT operator+(DifferenceTypeT n) const {
+    static_assert(
+        IsRandomAccess,
+        "The '+' operator is only defined for random access iterators.");
     DerivedT tmp = *static_cast<const DerivedT *>(this);
     tmp += n;
     return tmp;
   }
   friend DerivedT operator+(DifferenceTypeT n, const DerivedT &i) {
+    static_assert(
+        IsRandomAccess,
+        "The '+' operator is only defined for random access iterators.");
     return i + n;
   }
   DerivedT operator-(DifferenceTypeT n) const {
+    static_assert(
+        IsRandomAccess,
+        "The '-' operator is only defined for random access iterators.");
     DerivedT tmp = *static_cast<const DerivedT *>(this);
     tmp -= n;
     return tmp;
@@ -61,9 +79,15 @@ struct iterator_facade_base
     return tmp;
   }
   DerivedT &operator--() {
+    static_assert(
+        IsBidirectional,
+        "The decrement operator is only defined for bidirectional iterators.");
     return static_cast<DerivedT *>(this)->operator-=(1);
   }
   DerivedT operator--(int) {
+    static_assert(
+        IsBidirectional,
+        "The decrement operator is only defined for bidirectional iterators.");
     DerivedT tmp = *static_cast<DerivedT *>(this);
     --*static_cast<DerivedT *>(this);
     return tmp;
@@ -74,13 +98,22 @@ struct iterator_facade_base
   }
 
   bool operator>(const DerivedT &RHS) const {
+    static_assert(
+        IsRandomAccess,
+        "Relational operators are only defined for random access iterators.");
     return !static_cast<const DerivedT *>(this)->operator<(RHS) &&
            !static_cast<const DerivedT *>(this)->operator==(RHS);
   }
   bool operator<=(const DerivedT &RHS) const {
+    static_assert(
+        IsRandomAccess,
+        "Relational operators are only defined for random access iterators.");
     return !static_cast<const DerivedT *>(this)->operator>(RHS);
   }
   bool operator>=(const DerivedT &RHS) const {
+    static_assert(
+        IsRandomAccess,
+        "Relational operators are only defined for random access iterators.");
     return !static_cast<const DerivedT *>(this)->operator<(RHS);
   }
 
@@ -88,6 +121,8 @@ struct iterator_facade_base
     return &static_cast<const DerivedT *>(this)->operator*();
   }
   ReferenceT operator[](DifferenceTypeT n) const {
+    static_assert(IsRandomAccess,
+                  "Subscripting is only defined for random access iterators.");
     return *static_cast<const DerivedT *>(this)->operator+(n);
   }
 };
@@ -97,14 +132,19 @@ struct iterator_facade_base
 /// This class can be used through CRTP to adapt one iterator into another.
 /// Typically this is done through providing in the derived class a custom \c
 /// operator* implementation. Other methods can be overridden as well.
-template <typename DerivedT, typename WrappedIteratorT, typename T,
-          typename PointerT = T *, typename ReferenceT = T &,
-          // Don't provide these, they are mostly to act as aliases below.
-          typename WrappedTraitsT = std::iterator_traits<WrappedIteratorT>>
+template <
+    typename DerivedT, typename WrappedIteratorT,
+    typename IteratorCategoryT =
+        typename std::iterator_traits<WrappedIteratorT>::iterator_category,
+    typename T = typename std::iterator_traits<WrappedIteratorT>::value_type,
+    typename DifferenceTypeT =
+        typename std::iterator_traits<WrappedIteratorT>::difference_type,
+    typename PointerT = T *, typename ReferenceT = T &,
+    // Don't provide these, they are mostly to act as aliases below.
+    typename WrappedTraitsT = std::iterator_traits<WrappedIteratorT>>
 class iterator_adaptor_base
-    : public iterator_facade_base<
-          DerivedT, typename WrappedTraitsT::iterator_category, T,
-          typename WrappedTraitsT::difference_type, PointerT, ReferenceT> {
+    : public iterator_facade_base<DerivedT, IteratorCategoryT, T,
+                                  DifferenceTypeT, PointerT, ReferenceT> {
   typedef typename iterator_adaptor_base::iterator_facade_base BaseT;
 
 protected:
@@ -123,18 +163,29 @@ protected:
       : I(std::forward<U &&>(u)) {}
 
 public:
-  typedef typename WrappedTraitsT::difference_type difference_type;
+  typedef DifferenceTypeT difference_type;
 
   DerivedT &operator+=(difference_type n) {
+    static_assert(
+        BaseT::IsRandomAccess,
+        "The '+=' operator is only defined for random access iterators.");
     I += n;
     return *static_cast<DerivedT *>(this);
   }
   DerivedT &operator-=(difference_type n) {
+    static_assert(
+        BaseT::IsRandomAccess,
+        "The '-=' operator is only defined for random access iterators.");
     I -= n;
     return *static_cast<DerivedT *>(this);
   }
   using BaseT::operator-;
-  difference_type operator-(const DerivedT &RHS) const { return I - RHS.I; }
+  difference_type operator-(const DerivedT &RHS) const {
+    static_assert(
+        BaseT::IsRandomAccess,
+        "The '-' operator is only defined for random access iterators.");
+    return I - RHS.I;
+  }
 
   // We have to explicitly provide ++ and -- rather than letting the facade
   // forward to += because WrappedIteratorT might not support +=.
@@ -145,12 +196,20 @@ public:
   }
   using BaseT::operator--;
   DerivedT &operator--() {
+    static_assert(
+        BaseT::IsBidirectional,
+        "The decrement operator is only defined for bidirectional iterators.");
     --I;
     return *static_cast<DerivedT *>(this);
   }
 
   bool operator==(const DerivedT &RHS) const { return I == RHS.I; }
-  bool operator<(const DerivedT &RHS) const { return I < RHS.I; }
+  bool operator<(const DerivedT &RHS) const {
+    static_assert(
+        BaseT::IsRandomAccess,
+        "Relational operators are only defined for random access iterators.");
+    return I < RHS.I;
+  }
 
   ReferenceT operator*() const { return *I; }
 };
@@ -168,8 +227,10 @@ template <typename WrappedIteratorT,
           typename T = typename std::remove_reference<
               decltype(**std::declval<WrappedIteratorT>())>::type>
 struct pointee_iterator
-    : iterator_adaptor_base<pointee_iterator<WrappedIteratorT>,
-                            WrappedIteratorT, T> {
+    : iterator_adaptor_base<
+          pointee_iterator<WrappedIteratorT>, WrappedIteratorT,
+          typename std::iterator_traits<WrappedIteratorT>::iterator_category,
+          T> {
   pointee_iterator() {}
   template <typename U>
   pointee_iterator(U &&u)
diff --git a/include/llvm/Analysis/BlockFrequencyInfoImpl.h b/include/llvm/Analysis/BlockFrequencyInfoImpl.h
index 1b8ba91593..8018f784b8 100644
--- a/include/llvm/Analysis/BlockFrequencyInfoImpl.h
+++ b/include/llvm/Analysis/BlockFrequencyInfoImpl.h
@@ -8,6 +8,7 @@
 //===----------------------------------------------------------------------===//
 //
 // Shared implementation of BlockFrequency for IR and Machine Instructions.
+// See the documentation below for BlockFrequencyInfoImpl for details.
 //
 //===----------------------------------------------------------------------===//
 
@@ -16,15 +17,17 @@
 
 #include "llvm/ADT/DenseMap.h"
 #include "llvm/ADT/PostOrderIterator.h"
+#include "llvm/ADT/SCCIterator.h"
 #include "llvm/ADT/iterator_range.h"
 #include "llvm/IR/BasicBlock.h"
 #include "llvm/Support/BlockFrequency.h"
 #include "llvm/Support/BranchProbability.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/raw_ostream.h"
+#include <deque>
+#include <list>
 #include <string>
 #include <vector>
-#include <list>
 
 #define DEBUG_TYPE "block-freq"
 
@@ -756,86 +759,11 @@ public:
     return *this;
   }
 
-  /// \brief Scale by another mass.
-  ///
-  /// The current implementation is a little imprecise, but it's relatively
-  /// fast, never overflows, and maintains the property that 1.0*1.0==1.0
-  /// (where isFull represents the number 1.0).  It's an approximation of
-  /// 128-bit multiply that gets right-shifted by 64-bits.
-  ///
-  /// For a given digit size, multiplying two-digit numbers looks like:
-  ///
-  ///                  U1 .    L1
-  ///                * U2 .    L2
-  ///                ============
-  ///           0 .       . L1*L2
-  ///     +     0 . U1*L2 .     0 // (shift left once by a digit-size)
-  ///     +     0 . U2*L1 .     0 // (shift left once by a digit-size)
-  ///     + U1*L2 .     0 .     0 // (shift left twice by a digit-size)
-  ///
-  /// BlockMass has 64-bit numbers.  Split each into two 32-bit digits, stored
-  /// 64-bit.  Add 1 to the lower digits, to model isFull as 1.0; this won't
-  /// overflow, since we have 64-bit storage for each digit.
-  ///
-  /// To do this accurately, (a) multiply into two 64-bit digits, incrementing
-  /// the upper digit on overflows of the lower digit (carry), (b) subtract 1
-  /// from the lower digit, decrementing the upper digit on underflow (carry),
-  /// and (c) truncate the lower digit.  For the 1.0*1.0 case, the upper digit
-  /// will be 0 at the end of step (a), and then will underflow back to isFull
-  /// (1.0) in step (b).
-  ///
-  /// Instead, the implementation does something a little faster with a small
-  /// loss of accuracy: ignore the lower 64-bit digit entirely.  The loss of
-  /// accuracy is small, since the sum of the unmodelled carries is 0 or 1
-  /// (i.e., step (a) will overflow at most once, and step (b) will underflow
-  /// only if step (a) overflows).
-  ///
-  /// This is the formula we're calculating:
-  ///
-  ///     U1.L1 * U2.L2 == U1 * U2 + (U1 * (L2+1))>>32 + (U2 * (L1+1))>>32
-  ///
-  /// As a demonstration of 1.0*1.0, consider two 4-bit numbers that are both
-  /// full (1111).
-  ///
-  ///     U1.L1 * U2.L2 == U1 * U2 + (U1 * (L2+1))>>2 + (U2 * (L1+1))>>2
-  ///     11.11 * 11.11 == 11 * 11 + (11 * (11+1))/4 + (11 * (11+1))/4
-  ///                   == 1001 + (11 * 100)/4 + (11 * 100)/4
-  ///                   == 1001 + 1100/4 + 1100/4
-  ///                   == 1001 + 0011 + 0011
-  ///                   == 1111
-  BlockMass &operator*=(const BlockMass &X) {
-    uint64_t U1 = Mass >> 32, L1 = Mass & UINT32_MAX, U2 = X.Mass >> 32,
-             L2 = X.Mass & UINT32_MAX;
-    Mass = U1 * U2 + (U1 * (L2 + 1) >> 32) + ((L1 + 1) * U2 >> 32);
+  BlockMass &operator*=(const BranchProbability &P) {
+    Mass = P.scale(Mass);
     return *this;
   }
 
-  /// \brief Multiply by a branch probability.
-  ///
-  /// Multiply by P.  Guarantees full precision.
-  ///
-  /// This could be naively implemented by multiplying by the numerator and
-  /// dividing by the denominator, but in what order?  Multiplying first can
-  /// overflow, while dividing first will lose precision (potentially, changing
-  /// a non-zero mass to zero).
-  ///
-  /// The implementation mixes the two methods.  Since \a BranchProbability
-  /// uses 32-bits and \a BlockMass 64-bits, shift the mass as far to the left
-  /// as there is room, then divide by the denominator to get a quotient.
-  /// Multiplying by the numerator and right shifting gives a first
-  /// approximation.
-  ///
-  /// Calculate the error in this first approximation by calculating the
-  /// opposite mass (multiply by the opposite numerator and shift) and
-  /// subtracting both from teh original mass.
-  ///
-  /// Add to the first approximation the correct fraction of this error value.
-  /// This time, multiply first and then divide, since there is no danger of
-  /// overflow.
-  ///
-  /// \pre P represents a fraction between 0.0 and 1.0.
-  BlockMass &operator*=(const BranchProbability &P);
-
   bool operator==(const BlockMass &X) const { return Mass == X.Mass; }
   bool operator!=(const BlockMass &X) const { return Mass != X.Mass; }
   bool operator<=(const BlockMass &X) const { return Mass <= X.Mass; }
@@ -859,9 +787,6 @@ inline BlockMass operator+(const BlockMass &L, const BlockMass &R) {
 inline BlockMass operator-(const BlockMass &L, const BlockMass &R) {
   return BlockMass(L) -= R;
 }
-inline BlockMass operator*(const BlockMass &L, const BlockMass &R) {
-  return BlockMass(L) *= R;
-}
 inline BlockMass operator*(const BlockMass &L, const BranchProbability &R) {
   return BlockMass(L) *= R;
 }
@@ -896,6 +821,13 @@ class MachineFunction;
 class MachineLoop;
 class MachineLoopInfo;
 
+namespace bfi_detail {
+struct IrreducibleGraph;
+
+// This is part of a workaround for a GCC 4.7 crash on lambdas.
+template <class BT> struct BlockEdgesAdder;
+}
+
 /// \brief Base class for BlockFrequencyInfoImpl
 ///
 /// BlockFrequencyInfoImplBase has supporting data structures and some
@@ -948,6 +880,7 @@ public:
     typedef SmallVector<BlockNode, 4> NodeList;
     LoopData *Parent;       ///< The parent loop.
     bool IsPackaged;        ///< Whether this has been packaged.
+    uint32_t NumHeaders;    ///< Number of headers.
     ExitMap Exits;          ///< Successor edges (and weights).
     NodeList Nodes;         ///< Header and the members of the loop.
     BlockMass BackedgeMass; ///< Mass returned to loop header.
@@ -955,11 +888,26 @@ public:
     Float Scale;
 
     LoopData(LoopData *Parent, const BlockNode &Header)
-        : Parent(Parent), IsPackaged(false), Nodes(1, Header) {}
-    bool isHeader(const BlockNode &Node) const { return Node == Nodes[0]; }
+        : Parent(Parent), IsPackaged(false), NumHeaders(1), Nodes(1, Header) {}
+    template <class It1, class It2>
+    LoopData(LoopData *Parent, It1 FirstHeader, It1 LastHeader, It2 FirstOther,
+             It2 LastOther)
+        : Parent(Parent), IsPackaged(false), Nodes(FirstHeader, LastHeader) {
+      NumHeaders = Nodes.size();
+      Nodes.insert(Nodes.end(), FirstOther, LastOther);
+    }
+    bool isHeader(const BlockNode &Node) const {
+      if (isIrreducible())
+        return std::binary_search(Nodes.begin(), Nodes.begin() + NumHeaders,
+                                  Node);
+      return Node == Nodes[0];
+    }
     BlockNode getHeader() const { return Nodes[0]; }
+    bool isIrreducible() const { return NumHeaders > 1; }
 
-    NodeList::const_iterator members_begin() const { return Nodes.begin() + 1; }
+    NodeList::const_iterator members_begin() const {
+      return Nodes.begin() + NumHeaders;
+    }
     NodeList::const_iterator members_end() const { return Nodes.end(); }
     iterator_range<NodeList::const_iterator> members() const {
       return make_range(members_begin(), members_end());
@@ -975,9 +923,17 @@ public:
     WorkingData(const BlockNode &Node) : Node(Node), Loop(nullptr) {}
 
     bool isLoopHeader() const { return Loop && Loop->isHeader(Node); }
+    bool isDoubleLoopHeader() const {
+      return isLoopHeader() && Loop->Parent && Loop->Parent->isIrreducible() &&
+             Loop->Parent->isHeader(Node);
+    }
 
     LoopData *getContainingLoop() const {
-      return isLoopHeader() ? Loop->Parent : Loop;
+      if (!isLoopHeader())
+        return Loop;
+      if (!isDoubleLoopHeader())
+        return Loop->Parent;
+      return Loop->Parent->Parent;
     }
 
     /// \brief Resolve a node to its representative.
@@ -1011,12 +967,22 @@ public:
     /// Get appropriate mass for Node.  If Node is a loop-header (whose loop
     /// has been packaged), returns the mass of its pseudo-node.  If it's a
     /// node inside a packaged loop, it returns the loop's mass.
-    BlockMass &getMass() { return isAPackage() ? Loop->Mass : Mass; }
+    BlockMass &getMass() {
+      if (!isAPackage())
+        return Mass;
+      if (!isADoublePackage())
+        return Loop->Mass;
+      return Loop->Parent->Mass;
+    }
 
     /// \brief Has ContainingLoop been packaged up?
     bool isPackaged() const { return getResolvedNode() != Node; }
     /// \brief Has Loop been packaged up?
     bool isAPackage() const { return isLoopHeader() && Loop->IsPackaged; }
+    /// \brief Has Loop been packaged up twice?
+    bool isADoublePackage() const {
+      return isDoubleLoopHeader() && Loop->Parent->IsPackaged;
+    }
   };
 
   /// \brief Unscaled probability weight.
@@ -1093,7 +1059,9 @@ public:
   ///
   /// Adds all edges from LocalLoopHead to Dist.  Calls addToDist() to add each
   /// successor edge.
-  void addLoopSuccessorsToDist(const LoopData *OuterLoop, LoopData &Loop,
+  ///
+  /// \return \c true unless there's an irreducible backedge.
+  bool addLoopSuccessorsToDist(const LoopData *OuterLoop, LoopData &Loop,
                                Distribution &Dist);
 
   /// \brief Add an edge to the distribution.
@@ -1101,7 +1069,9 @@ public:
   /// Adds an edge to Succ to Dist.  If \c LoopHead.isValid(), then whether the
   /// edge is local/exit/backedge is in the context of LoopHead.  Otherwise,
   /// every edge should be a local edge (since all the loops are packaged up).
-  void addToDist(Distribution &Dist, const LoopData *OuterLoop,
+  ///
+  /// \return \c true unless aborted due to an irreducible backedge.
+  bool addToDist(Distribution &Dist, const LoopData *OuterLoop,
                  const BlockNode &Pred, const BlockNode &Succ, uint64_t Weight);
 
   LoopData &getLoopPackage(const BlockNode &Head) {
@@ -1110,6 +1080,25 @@ public:
     return *Working[Head.Index].Loop;
   }
 
+  /// \brief Analyze irreducible SCCs.
+  ///
+  /// Separate irreducible SCCs from \c G, which is an explict graph of \c
+  /// OuterLoop (or the top-level function, if \c OuterLoop is \c nullptr).
+  /// Insert them into \a Loops before \c Insert.
+  ///
+  /// \return the \c LoopData nodes representing the irreducible SCCs.
+  iterator_range<std::list<LoopData>::iterator>
+  analyzeIrreducible(const bfi_detail::IrreducibleGraph &G, LoopData *OuterLoop,
+                     std::list<LoopData>::iterator Insert);
+
+  /// \brief Update a loop after packaging irreducible SCCs inside of it.
+  ///
+  /// Update \c OuterLoop.  Before finding irreducible control flow, it was
+  /// partway through \a computeMassInLoop(), so \a LoopData::Exits and \a
+  /// LoopData::BackedgeMass need to be reset.  Also, nodes that were packaged
+  /// up need to be removed from \a OuterLoop::Nodes.
+  void updateLoopWithIrreducible(LoopData &OuterLoop);
+
   /// \brief Distribute mass according to a distribution.
   ///
   /// Distributes the mass in Source according to Dist.  If LoopHead.isValid(),
@@ -1138,6 +1127,7 @@ public:
   void clear();
 
   virtual std::string getBlockName(const BlockNode &Node) const;
+  std::string getLoopName(const LoopData &Loop) const;
 
   virtual raw_ostream &print(raw_ostream &OS) const { return OS; }
   void dump() const { print(dbgs()); }
@@ -1197,6 +1187,106 @@ template <> inline std::string getBlockName(const BasicBlock *BB) {
   assert(BB && "Unexpected nullptr");
   return BB->getName().str();
 }
+
+/// \brief Graph of irreducible control flow.
+///
+/// This graph is used for determining the SCCs in a loop (or top-level
+/// function) that has irreducible control flow.
+///
+/// During the block frequency algorithm, the local graphs are defined in a
+/// light-weight way, deferring to the \a BasicBlock or \a MachineBasicBlock
+/// graphs for most edges, but getting others from \a LoopData::ExitMap.  The
+/// latter only has successor information.
+///
+/// \a IrreducibleGraph makes this graph explicit.  It's in a form that can use
+/// \a GraphTraits (so that \a analyzeIrreducible() can use \a scc_iterator),
+/// and it explicitly lists predecessors and successors.  The initialization
+/// that relies on \c MachineBasicBlock is defined in the header.
+struct IrreducibleGraph {
+  typedef BlockFrequencyInfoImplBase BFIBase;
+
+  BFIBase &BFI;
+
+  typedef BFIBase::BlockNode BlockNode;
+  struct IrrNode {
+    BlockNode Node;
+    unsigned NumIn;
+    std::deque<const IrrNode *> Edges;
+    IrrNode(const BlockNode &Node) : Node(Node), NumIn(0) {}
+
+    typedef std::deque<const IrrNode *>::const_iterator iterator;
+    iterator pred_begin() const { return Edges.begin(); }
+    iterator succ_begin() const { return Edges.begin() + NumIn; }
+    iterator pred_end() const { return succ_begin(); }
+    iterator succ_end() const { return Edges.end(); }
+  };
+  BlockNode Start;
+  const IrrNode *StartIrr;
+  std::vector<IrrNode> Nodes;
+  SmallDenseMap<uint32_t, IrrNode *, 4> Lookup;
+
+  /// \brief Construct an explicit graph containing irreducible control flow.
+  ///
+  /// Construct an explicit graph of the control flow in \c OuterLoop (or the
+  /// top-level function, if \c OuterLoop is \c nullptr).  Uses \c
+  /// addBlockEdges to add block successors that have not been packaged into
+  /// loops.
+  ///
+  /// \a BlockFrequencyInfoImpl::computeIrreducibleMass() is the only expected
+  /// user of this.
+  template <class BlockEdgesAdder>
+  IrreducibleGraph(BFIBase &BFI, const BFIBase::LoopData *OuterLoop,
+                   BlockEdgesAdder addBlockEdges)
+      : BFI(BFI), StartIrr(nullptr) {
+    initialize(OuterLoop, addBlockEdges);
+  }
+
+  template <class BlockEdgesAdder>
+  void initialize(const BFIBase::LoopData *OuterLoop,
+                  BlockEdgesAdder addBlockEdges);
+  void addNodesInLoop(const BFIBase::LoopData &OuterLoop);
+  void addNodesInFunction();
+  void addNode(const BlockNode &Node) {
+    Nodes.emplace_back(Node);
+    BFI.Working[Node.Index].getMass() = BlockMass::getEmpty();
+  }
+  void indexNodes();
+  template <class BlockEdgesAdder>
+  void addEdges(const BlockNode &Node, const BFIBase::LoopData *OuterLoop,
+                BlockEdgesAdder addBlockEdges);
+  void addEdge(IrrNode &Irr, const BlockNode &Succ,
+               const BFIBase::LoopData *OuterLoop);
+};
+template <class BlockEdgesAdder>
+void IrreducibleGraph::initialize(const BFIBase::LoopData *OuterLoop,
+                                  BlockEdgesAdder addBlockEdges) {
+  if (OuterLoop) {
+    addNodesInLoop(*OuterLoop);
+    for (auto N : OuterLoop->Nodes)
+      addEdges(N, OuterLoop, addBlockEdges);
+  } else {
+    addNodesInFunction();
+    for (uint32_t Index = 0; Index < BFI.Working.size(); ++Index)
+      addEdges(Index, OuterLoop, addBlockEdges);
+  }
+  StartIrr = Lookup[Start.Index];
+}
+template <class BlockEdgesAdder>
+void IrreducibleGraph::addEdges(const BlockNode &Node,
+                                const BFIBase::LoopData *OuterLoop,
+                                BlockEdgesAdder addBlockEdges) {
+  auto L = Lookup.find(Node.Index);
+  if (L == Lookup.end())
+    return;
+  IrrNode &Irr = *L->second;
+  const auto &Working = BFI.Working[Node.Index];
+
+  if (Working.isAPackage())
+    for (const auto &I : Working.Loop->Exits)
+      addEdge(Irr, I.first, OuterLoop);
+  else
+    addBlockEdges(*this, Irr, OuterLoop);
+}
 }
 
 /// \brief Shared implementation for block frequency analysis.
@@ -1205,6 +1295,22 @@ template <> inline std::string getBlockName(const BasicBlock *BB) {
 /// MachineBlockFrequencyInfo, and calculates the relative frequencies of
 /// blocks.
 ///
+/// LoopInfo defines a loop as a "non-trivial" SCC dominated by a single block,
+/// which is called the header.  A given loop, L, can have sub-loops, which are
+/// loops within the subgraph of L that exclude its header.  (A "trivial" SCC
+/// consists of a single block that does not have a self-edge.)
+///
+/// In addition to loops, this algorithm has limited support for irreducible
+/// SCCs, which are SCCs with multiple entry blocks.  Irreducible SCCs are
+/// discovered on they fly, and modelled as loops with multiple headers.
+///
+/// The headers of irreducible sub-SCCs consist of its entry blocks and all
+/// nodes that are targets of a backedge within it (excluding backedges within
+/// true sub-loops).  Block frequency calculations act as if a block is
+/// inserted that intercepts all the edges to the headers.  All backedges and
+/// entries point to this block.  Its successors are the headers, which split
+/// the frequency evenly.
+///
 /// This algorithm leverages BlockMass and UnsignedFloat to maintain precision,
 /// separates mass distribution from loop scaling, and dithers to eliminate
 /// probability mass loss.
@@ -1228,7 +1334,7 @@ template <> inline std::string getBlockName(const BasicBlock *BB) {
 ///     All other stages make use of this ordering.  Save a lookup from BlockT
 ///     to BlockNode (the index into RPOT) in Nodes.
 ///
-///  1. Loop indexing (\a initializeLoops()).
+///  1. Loop initialization (\a initializeLoops()).
 ///
 ///     Translate LoopInfo/MachineLoopInfo into a form suitable for the rest of
 ///     the algorithm.  In particular, store the immediate members of each loop
@@ -1239,11 +1345,9 @@ template <> inline std::string getBlockName(const BasicBlock *BB) {
 ///     For each loop (bottom-up), distribute mass through the DAG resulting
 ///     from ignoring backedges and treating sub-loops as a single pseudo-node.
 ///     Track the backedge mass distributed to the loop header, and use it to
-///     calculate the loop scale (number of loop iterations).
-///
-///     Visiting loops bottom-up is a post-order traversal of loop headers.
-///     For each loop, immediate members that represent sub-loops will already
-///     have been visited and packaged into a pseudo-node.
+///     calculate the loop scale (number of loop iterations).  Immediate
+///     members that represent sub-loops will already have been visited and
+///     packaged into a pseudo-node.
 ///
 ///     Distributing mass in a loop is a reverse-post-order traversal through
 ///     the loop.  Start by assigning full mass to the Loop header.  For each
@@ -1260,6 +1364,11 @@ template <> inline std::string getBlockName(const BasicBlock *BB) {
 ///           The weight, the successor, and its category are stored in \a
 ///           Distribution.  There can be multiple edges to each successor.
 ///
+///         - If there's a backedge to a non-header, there's an irreducible SCC.
+///           The usual flow is temporarily aborted.  \a
+///           computeIrreducibleMass() finds the irreducible SCCs within the
+///           loop, packages them up, and restarts the flow.
+///
 ///         - Normalize the distribution:  scale weights down so that their sum
 ///           is 32-bits, and coalesce multiple edges to the same node.
 ///
@@ -1274,39 +1383,62 @@ template <> inline std::string getBlockName(const BasicBlock *BB) {
 ///     loops in the function.  This uses the same algorithm as distributing
 ///     mass in a loop, except that there are no exit or backedge edges.
 ///
-///  4. Loop unpackaging and cleanup (\a finalizeMetrics()).
+///  4. Unpackage loops (\a unwrapLoops()).
+///
+///     Initialize each block's frequency to a floating point representation of
+///     its mass.
 ///
-///     Initialize the frequency to a floating point representation of its
-///     mass.
+///     Visit loops top-down, scaling the frequencies of its immediate members
+///     by the loop's pseudo-node's frequency.
 ///
-///     Visit loops top-down (reverse post-order), scaling the loop header's
-///     frequency by its psuedo-node's mass and loop scale.  Keep track of the
-///     minimum and maximum final frequencies.
+///  5. Convert frequencies to a 64-bit range (\a finalizeMetrics()).
 ///
 ///     Using the min and max frequencies as a guide, translate floating point
 ///     frequencies to an appropriate range in uint64_t.
 ///
 /// It has some known flaws.
 ///
-///   - Irreducible control flow isn't modelled correctly.  In particular,
-///     LoopInfo and MachineLoopInfo ignore irreducible backedges.  The main
-///     result is that irreducible SCCs will under-scaled.  No mass is lost,
-///     but the computed branch weights for the loop pseudo-node will be
-///     incorrect.
+///   - Loop scale is limited to 4096 per loop (2^12) to avoid exhausting
+///     BlockFrequency's 64-bit integer precision.
+///
+///   - The model of irreducible control flow is a rough approximation.
 ///
 ///     Modelling irreducible control flow exactly involves setting up and
 ///     solving a group of infinite geometric series.  Such precision is
 ///     unlikely to be worthwhile, since most of our algorithms give up on
 ///     irreducible control flow anyway.
 ///
-///     Nevertheless, we might find that we need to get closer.  If
-///     LoopInfo/MachineLoopInfo flags loops with irreducible control flow
-///     (and/or the function as a whole), we can find the SCCs, compute an
-///     approximate exit frequency for the SCC as a whole, and scale up
-///     accordingly.
+///     Nevertheless, we might find that we need to get closer.  Here's a sort
+///     of TODO list for the model with diminishing returns, to be completed as
+///     necessary.
 ///
-///   - Loop scale is limited to 4096 per loop (2^12) to avoid exhausting
-///     BlockFrequency's 64-bit integer precision.
+///       - The headers for the \a LoopData representing an irreducible SCC
+///         include non-entry blocks.  When these extra blocks exist, they
+///         indicate a self-contained irreducible sub-SCC.  We could treat them
+///         as sub-loops, rather than arbitrarily shoving the problematic
+///         blocks into the headers of the main irreducible SCC.
+///
+///       - Backedge frequencies are assumed to be evenly split between the
+///         headers of a given irreducible SCC.  Instead, we could track the
+///         backedge mass separately for each header, and adjust their relative
+///         frequencies.
+///
+///       - Entry frequencies are assumed to be evenly split between the
+///         headers of a given irreducible SCC, which is the only option if we
+///         need to compute mass in the SCC before its parent loop.  Instead,
+///         we could partially compute mass in the parent loop, and stop when
+///         we get to the SCC.  Here, we have the correct ratio of entry
+///         masses, which we can use to adjust their relative frequencies.
+///         Compute mass in the SCC, and then continue propagation in the
+///         parent.
+///
+///       - We can propagate mass iteratively through the SCC, for some fixed
+///         number of iterations.  Each iteration starts by assigning the entry
+///         blocks their backedge mass from the prior iteration.  The final
+///         mass for each block (and each exit, and the total backedge mass
+///         used for computing loop scale) is the sum of all iterations.
+///         (Running this until fixed point would "solve" the geometric
+///         series by simulation.)
 template <class BT> class BlockFrequencyInfoImpl : BlockFrequencyInfoImplBase {
   typedef typename bfi_detail::TypeMap<BT>::BlockT BlockT;
   typedef typename bfi_detail::TypeMap<BT>::FunctionT FunctionT;
@@ -1315,6 +1447,9 @@ template <class BT> class BlockFrequencyInfoImpl : BlockFrequencyInfoImplBase {
   typedef typename bfi_detail::TypeMap<BT>::LoopT LoopT;
   typedef typename bfi_detail::TypeMap<BT>::LoopInfoT LoopInfoT;
 
+  // This is part of a workaround for a GCC 4.7 crash on lambdas.
+  friend struct bfi_detail::BlockEdgesAdder<BT>;
+
   typedef GraphTraits<const BlockT *> Successor;
   typedef GraphTraits<Inverse<const BlockT *>> Predecessor;
 
@@ -1361,7 +1496,9 @@ template <class BT> class BlockFrequencyInfoImpl : BlockFrequencyInfoImplBase {
   ///
   /// In the context of distributing mass through \c OuterLoop, divide the mass
   /// currently assigned to \c Node between its successors.
-  void propagateMassToSuccessors(LoopData *OuterLoop, const BlockNode &Node);
+  ///
+  /// \return \c true unless there's an irreducible backedge.
+  bool propagateMassToSuccessors(LoopData *OuterLoop, const BlockNode &Node);
 
   /// \brief Compute mass in a particular loop.
   ///
@@ -1370,20 +1507,51 @@ template <class BT> class BlockFrequencyInfoImpl : BlockFrequencyInfoImplBase {
   /// that have not been packaged into sub-loops.
   ///
   /// \pre \a computeMassInLoop() has been called for each subloop of \c Loop.
-  void computeMassInLoop(LoopData &Loop);
+  /// \return \c true unless there's an irreducible backedge.
+  bool computeMassInLoop(LoopData &Loop);
+
+  /// \brief Try to compute mass in the top-level function.
+  ///
+  /// Assign mass to the entry block, and then for each block in reverse
+  /// post-order, distribute mass to its successors.  Skips nodes that have
+  /// been packaged into loops.
+  ///
+  /// \pre \a computeMassInLoops() has been called.
+  /// \return \c true unless there's an irreducible backedge.
+  bool tryToComputeMassInFunction();
+
+  /// \brief Compute mass in (and package up) irreducible SCCs.
+  ///
+  /// Find the irreducible SCCs in \c OuterLoop, add them to \a Loops (in front
+  /// of \c Insert), and call \a computeMassInLoop() on each of them.
+  ///
+  /// If \c OuterLoop is \c nullptr, it refers to the top-level function.
+  ///
+  /// \pre \a computeMassInLoop() has been called for each subloop of \c
+  /// OuterLoop.
+  /// \pre \c Insert points at the the last loop successfully processed by \a
+  /// computeMassInLoop().
+  /// \pre \c OuterLoop has irreducible SCCs.
+  void computeIrreducibleMass(LoopData *OuterLoop,
+                              std::list<LoopData>::iterator Insert);
 
   /// \brief Compute mass in all loops.
   ///
   /// For each loop bottom-up, call \a computeMassInLoop().
+  ///
+  /// \a computeMassInLoop() aborts (and returns \c false) on loops that
+  /// contain a irreducible sub-SCCs.  Use \a computeIrreducibleMass() and then
+  /// re-enter \a computeMassInLoop().
+  ///
+  /// \post \a computeMassInLoop() has returned \c true for every loop.
   void computeMassInLoops();
 
   /// \brief Compute mass in the top-level function.
   ///
-  /// Assign mass to the entry block, and then for each block in reverse
-  /// post-order, distribute mass to its successors.  Skips nodes that have
-  /// been packaged into loops.
+  /// Uses \a tryToComputeMassInFunction() and \a computeIrreducibleMass() to
+  /// compute mass in the top-level function.
   ///
-  /// \pre \a computeMassInLoops() has been called.
+  /// \post \a tryToComputeMassInFunction() has returned \c true.
   void computeMassInFunction();
 
   std::string getBlockName(const BlockNode &Node) const override {
@@ -1530,27 +1698,50 @@ template <class BT> void BlockFrequencyInfoImpl<BT>::initializeLoops() {
 
 template <class BT> void BlockFrequencyInfoImpl<BT>::computeMassInLoops() {
   // Visit loops with the deepest first, and the top-level loops last.
-  for (auto L = Loops.rbegin(), E = Loops.rend(); L != E; ++L)
-    computeMassInLoop(*L);
+  for (auto L = Loops.rbegin(), E = Loops.rend(); L != E; ++L) {
+    if (computeMassInLoop(*L))
+      continue;
+    auto Next = std::next(L);
+    computeIrreducibleMass(&*L, L.base());
+    L = std::prev(Next);
+    if (computeMassInLoop(*L))
+      continue;
+    llvm_unreachable("unhandled irreducible control flow");
+  }
 }
 
 template <class BT>
-void BlockFrequencyInfoImpl<BT>::computeMassInLoop(LoopData &Loop) {
+bool BlockFrequencyInfoImpl<BT>::computeMassInLoop(LoopData &Loop) {
   // Compute mass in loop.
-  DEBUG(dbgs() << "compute-mass-in-loop: " << getBlockName(Loop.getHeader())
-               << "\n");
-
-  Working[Loop.getHeader().Index].getMass() = BlockMass::getFull();
-  propagateMassToSuccessors(&Loop, Loop.getHeader());
-
-  for (const BlockNode &M : Loop.members())
-    propagateMassToSuccessors(&Loop, M);
+  DEBUG(dbgs() << "compute-mass-in-loop: " << getLoopName(Loop) << "\n");
+
+  if (Loop.isIrreducible()) {
+    BlockMass Remaining = BlockMass::getFull();
+    for (uint32_t H = 0; H < Loop.NumHeaders; ++H) {
+      auto &Mass = Working[Loop.Nodes[H].Index].getMass();
+      Mass = Remaining * BranchProbability(1, Loop.NumHeaders - H);
+      Remaining -= Mass;
+    }
+    for (const BlockNode &M : Loop.Nodes)
+      if (!propagateMassToSuccessors(&Loop, M))
+        llvm_unreachable("unhandled irreducible control flow");
+  } else {
+    Working[Loop.getHeader().Index].getMass() = BlockMass::getFull();
+    if (!propagateMassToSuccessors(&Loop, Loop.getHeader()))
+      llvm_unreachable("irreducible control flow to loop header!?");
+    for (const BlockNode &M : Loop.members())
+      if (!propagateMassToSuccessors(&Loop, M))
+        // Irreducible backedge.
+        return false;
+  }
 
   computeLoopScale(Loop);
   packageLoop(Loop);
+  return true;
 }
 
-template <class BT> void BlockFrequencyInfoImpl<BT>::computeMassInFunction() {
+template <class BT>
+bool BlockFrequencyInfoImpl<BT>::tryToComputeMassInFunction() {
   // Compute mass in function.
   DEBUG(dbgs() << "compute-mass-in-function\n");
   assert(!Working.empty() && "no blocks in function");
@@ -1563,12 +1754,63 @@ template <class BT> void BlockFrequencyInfoImpl<BT>::computeMassInFunction() {
     if (Working[Node.Index].isPackaged())
       continue;
 
-    propagateMassToSuccessors(nullptr, Node);
+    if (!propagateMassToSuccessors(nullptr, Node))
+      return false;
   }
+  return true;
 }
 
+template <class BT> void BlockFrequencyInfoImpl<BT>::computeMassInFunction() {
+  if (tryToComputeMassInFunction())
+    return;
+  computeIrreducibleMass(nullptr, Loops.begin());
+  if (tryToComputeMassInFunction())
+    return;
+  llvm_unreachable("unhandled irreducible control flow");
+}
+
+/// \note This should be a lambda, but that crashes GCC 4.7.
+namespace bfi_detail {
+template <class BT> struct BlockEdgesAdder {
+  typedef BT BlockT;
+  typedef BlockFrequencyInfoImplBase::LoopData LoopData;
+  typedef GraphTraits<const BlockT *> Successor;
+
+  const BlockFrequencyInfoImpl<BT> &BFI;
+  explicit BlockEdgesAdder(const BlockFrequencyInfoImpl<BT> &BFI)
+      : BFI(BFI) {}
+  void operator()(IrreducibleGraph &G, IrreducibleGraph::IrrNode &Irr,
+                  const LoopData *OuterLoop) {
+    const BlockT *BB = BFI.RPOT[Irr.Node.Index];
+    for (auto I = Successor::child_begin(BB), E = Successor::child_end(BB);
+         I != E; ++I)
+      G.addEdge(Irr, BFI.getNode(*I), OuterLoop);
+  }
+};
+}
 template <class BT>
-void
+void BlockFrequencyInfoImpl<BT>::computeIrreducibleMass(
+    LoopData *OuterLoop, std::list<LoopData>::iterator Insert) {
+  DEBUG(dbgs() << "analyze-irreducible-in-";
+        if (OuterLoop) dbgs() << "loop: " << getLoopName(*OuterLoop) << "\n";
+        else dbgs() << "function\n");
+
+  using namespace bfi_detail;
+  // Ideally, addBlockEdges() would be declared here as a lambda, but that
+  // crashes GCC 4.7.
+  BlockEdgesAdder<BT> addBlockEdges(*this);
+  IrreducibleGraph G(*this, OuterLoop, addBlockEdges);
+
+  for (auto &L : analyzeIrreducible(G, OuterLoop, Insert))
+    computeMassInLoop(L);
+
+  if (!OuterLoop)
+    return;
+  updateLoopWithIrreducible(*OuterLoop);
+}
+
+template <class BT>
+bool
 BlockFrequencyInfoImpl<BT>::propagateMassToSuccessors(LoopData *OuterLoop,
                                                       const BlockNode &Node) {
   DEBUG(dbgs() << " - node: " << getBlockName(Node) << "\n");
@@ -1576,20 +1818,25 @@ BlockFrequencyInfoImpl<BT>::propagateMassToSuccessors(LoopData *OuterLoop,
   Distribution Dist;
   if (auto *Loop = Working[Node.Index].getPackagedLoop()) {
     assert(Loop != OuterLoop && "Cannot propagate mass in a packaged loop");
-    addLoopSuccessorsToDist(OuterLoop, *Loop, Dist);
+    if (!addLoopSuccessorsToDist(OuterLoop, *Loop, Dist))
+      // Irreducible backedge.
+      return false;
   } else {
     const BlockT *BB = getBlock(Node);
     for (auto SI = Successor::child_begin(BB), SE = Successor::child_end(BB);
          SI != SE; ++SI)
       // Do not dereference SI, or getEdgeWeight() is linear in the number of
       // successors.
-      addToDist(Dist, OuterLoop, Node, getNode(*SI),
-                BPI->getEdgeWeight(BB, SI));
+      if (!addToDist(Dist, OuterLoop, Node, getNode(*SI),
+                     BPI->getEdgeWeight(BB, SI)))
+        // Irreducible backedge.
+        return false;
   }
 
   // Distribute mass to successors, saving exit and backedge data in the
   // loop header.
   distributeMass(Node, OuterLoop, Dist);
+  return true;
 }
 
 template <class BT>
diff --git a/include/llvm/Analysis/DOTGraphTraitsPass.h b/include/llvm/Analysis/DOTGraphTraitsPass.h
index ff3392a1f9..53c832cbeb 100644
--- a/include/llvm/Analysis/DOTGraphTraitsPass.h
+++ b/include/llvm/Analysis/DOTGraphTraitsPass.h
@@ -16,6 +16,7 @@
 
 #include "llvm/Analysis/CFGPrinter.h"
 #include "llvm/Pass.h"
+#include "llvm/Support/FileSystem.h"
 
 namespace llvm {
 
diff --git a/include/llvm/Analysis/LazyCallGraph.h b/include/llvm/Analysis/LazyCallGraph.h
index e406981952..2b391e0476 100644
--- a/include/llvm/Analysis/LazyCallGraph.h
+++ b/include/llvm/Analysis/LazyCallGraph.h
@@ -113,8 +113,9 @@ public:
   /// be scanned for "calls" or uses of functions and its child information
   /// will be constructed. All of these results are accumulated and cached in
   /// the graph.
-  class iterator : public iterator_adaptor_base<
-                       iterator, NodeVectorImplT::iterator, Node> {
+  class iterator
+      : public iterator_adaptor_base<iterator, NodeVectorImplT::iterator,
+                                     std::bidirectional_iterator_tag, Node> {
     friend class LazyCallGraph;
     friend class LazyCallGraph::Node;
 
@@ -123,11 +124,30 @@ public:
 
     // Build the iterator for a specific position in a node list.
     iterator(LazyCallGraph &G, NodeVectorImplT::iterator NI)
-        : iterator_adaptor_base(NI), G(&G) {}
+        : iterator_adaptor_base(NI), G(&G) {
+      while (I->isNull())
+        ++I;
+    }
 
   public:
     iterator() {}
 
+    using iterator_adaptor_base::operator++;
+    iterator &operator++() {
+      do {
+        ++I;
+      } while (I->isNull());
+      return *this;
+    }
+
+    using iterator_adaptor_base::operator--;
+    iterator &operator--() {
+      do {
+        --I;
+      } while (I->isNull());
+      return *this;
+    }
+
     reference operator*() const {
       if (I->is<Node *>())
         return *I->get<Node *>();
@@ -166,6 +186,9 @@ public:
     /// \brief Internal helper to insert a callee.
     void insertEdgeInternal(Function &Callee);
 
+    /// \brief Internal helper to insert a callee.
+    void insertEdgeInternal(Node &CalleeN);
+
     /// \brief Internal helper to remove a callee from this node.
     void removeEdgeInternal(Function &Callee);
 
@@ -229,6 +252,12 @@ public:
     /// Note that these methods sometimes have complex runtimes, so be careful
     /// how you call them.
 
+    /// \brief Insert an edge from one node in this SCC to another in this SCC.
+    ///
+    /// By the definition of an SCC, this does not change the nature or make-up
+    /// of any SCCs.
+    void insertIntraSCCEdge(Node &CallerN, Node &CalleeN);
+
     /// \brief Remove an edge whose source is in this SCC and target is *not*.
     ///
     /// This removes an inter-SCC edge. All inter-SCC edges originating from
diff --git a/include/llvm/Analysis/LoopInfo.h b/include/llvm/Analysis/LoopInfo.h
index 045d4dc565..bef03e91bb 100644
--- a/include/llvm/Analysis/LoopInfo.h
+++ b/include/llvm/Analysis/LoopInfo.h
@@ -453,6 +453,31 @@ public:
 
   void dump() const;
 
+  /// \brief Return the debug location of the start of this loop.
+  /// This looks for a BB terminating instruction with a known debug
+  /// location by looking at the preheader and header blocks. If it
+  /// cannot find a terminating instruction with location information,
+  /// it returns an unknown location.
+  DebugLoc getStartLoc() const {
+    DebugLoc StartLoc;
+    BasicBlock *HeadBB;
+
+    // Try the pre-header first.
+    if ((HeadBB = getLoopPreheader()) != nullptr) {
+      StartLoc = HeadBB->getTerminator()->getDebugLoc();
+      if (!StartLoc.isUnknown())
+        return StartLoc;
+    }
+
+    // If we have no pre-header or there are no instructions with debug
+    // info in it, try the header.
+    HeadBB = getHeader();
+    if (HeadBB)
+      StartLoc = HeadBB->getTerminator()->getDebugLoc();
+
+    return StartLoc;
+  }
+
 private:
   friend class LoopInfoBase<BasicBlock, Loop>;
   explicit Loop(BasicBlock *BB) : LoopBase<BasicBlock, Loop>(BB) {}
diff --git a/include/llvm/ExecutionEngine/ExecutionEngine.h b/include/llvm/ExecutionEngine/ExecutionEngine.h
index 70440d725d..7518c1e1d8 100644
--- a/include/llvm/ExecutionEngine/ExecutionEngine.h
+++ b/include/llvm/ExecutionEngine/ExecutionEngine.h
@@ -222,10 +222,7 @@ public:
   /// needed by another object.
   ///
   /// MCJIT will take ownership of the ObjectFile.
-  virtual void addObjectFile(object::ObjectFile *O) {
-    llvm_unreachable(
-      "ExecutionEngine subclass doesn't implement addObjectFile.");
-  }
+  virtual void addObjectFile(std::unique_ptr<object::ObjectFile> O);
 
   /// addArchive - Add an Archive to the execution engine.
   ///
diff --git a/include/llvm/ExecutionEngine/RuntimeDyld.h b/include/llvm/ExecutionEngine/RuntimeDyld.h
index 8d7b81bb6e..30c0d49ade 100644
--- a/include/llvm/ExecutionEngine/RuntimeDyld.h
+++ b/include/llvm/ExecutionEngine/RuntimeDyld.h
@@ -55,7 +55,7 @@ public:
   /// Ownership of the input object is transferred to the ObjectImage
   /// instance returned from this function if successful. In the case of load
   /// failure, the input object will be deleted.
-  ObjectImage *loadObject(object::ObjectFile *InputObject);
+  ObjectImage *loadObject(std::unique_ptr<object::ObjectFile> InputObject);
 
   /// Get the address of our local copy of the symbol. This may or may not
   /// be the address used for relocation (clients can copy the data around
diff --git a/include/llvm/IR/IntrinsicsX86.td b/include/llvm/IR/IntrinsicsX86.td
index e262687e91..145da599a1 100644
--- a/include/llvm/IR/IntrinsicsX86.td
+++ b/include/llvm/IR/IntrinsicsX86.td
@@ -1129,6 +1129,27 @@ let TargetPrefix = "x86" in {  // All intrinsics start with "llvm.x86.".
         GCCBuiltin<"__builtin_ia32_vperm2f128_si256">,
         Intrinsic<[llvm_v8i32_ty], [llvm_v8i32_ty,
                   llvm_v8i32_ty, llvm_i8_ty], [IntrNoMem]>;
+
+  def int_x86_avx512_mask_vpermt_d_512:
+        GCCBuiltin<"__builtin_ia32_vpermt2vard512_mask">,
+        Intrinsic<[llvm_v16i32_ty], [llvm_v16i32_ty,
+                  llvm_v16i32_ty, llvm_v16i32_ty, llvm_i16_ty], [IntrNoMem]>;
+
+  def int_x86_avx512_mask_vpermt_q_512:
+        GCCBuiltin<"__builtin_ia32_vpermt2varq512_mask">,
+        Intrinsic<[llvm_v8i64_ty], [llvm_v8i64_ty,
+                  llvm_v8i64_ty, llvm_v8i64_ty, llvm_i8_ty], [IntrNoMem]>;
+
+  def int_x86_avx512_mask_vpermt_ps_512:
+        GCCBuiltin<"__builtin_ia32_vpermt2varps512_mask">,
+        Intrinsic<[llvm_v16f32_ty], [llvm_v16i32_ty,
+                  llvm_v16f32_ty, llvm_v16f32_ty, llvm_i16_ty], [IntrNoMem]>;
+
+  def int_x86_avx512_mask_vpermt_pd_512:
+        GCCBuiltin<"__builtin_ia32_vpermt2varpd512_mask">,
+        Intrinsic<[llvm_v8f64_ty], [llvm_v8i64_ty,
+                  llvm_v8f64_ty, llvm_v8f64_ty, llvm_i8_ty], [IntrNoMem]>;
+
 }
 
 // Vector blend
diff --git a/include/llvm/IR/Use.h b/include/llvm/IR/Use.h
index 41755daed3..033cd3e2f5 100644
--- a/include/llvm/IR/Use.h
+++ b/include/llvm/IR/Use.h
@@ -60,7 +60,7 @@ public:
 /// implicit. The implicit pointer is found via a waymarking algorithm
 /// described in the programmer's manual:
 ///
-///   http://www.llvm.org/docs/ProgrammersManual.html#UserLayout
+///   http://www.llvm.org/docs/ProgrammersManual.html#the-waymarking-algorithm
 ///
 /// This is essentially the single most memory intensive object in LLVM because
 /// of the number of uses in the system. At the same time, the constant time
diff --git a/include/llvm/IR/User.h b/include/llvm/IR/User.h
index 453b6ad169..bc7696bdaf 100644
--- a/include/llvm/IR/User.h
+++ b/include/llvm/IR/User.h
@@ -131,8 +131,9 @@ public:
   /// Convenience iterator for directly iterating over the Values in the
   /// OperandList
   struct value_op_iterator
-      : iterator_adaptor_base<value_op_iterator, op_iterator, Value *, Value *,
-                              Value *> {
+      : iterator_adaptor_base<value_op_iterator, op_iterator,
+                              std::random_access_iterator_tag, Value *,
+                              ptrdiff_t, Value *, Value *> {
     explicit value_op_iterator(Use *U = nullptr) : iterator_adaptor_base(U) {}
 
     Value *operator*() const { return *I; }
diff --git a/include/llvm/MC/MCAssembler.h b/include/llvm/MC/MCAssembler.h
index e71775a8c1..be13b3681e 100644
--- a/include/llvm/MC/MCAssembler.h
+++ b/include/llvm/MC/MCAssembler.h
@@ -902,7 +902,7 @@ private:
   // here. Maybe when the relocation stuff moves to target specific,
   // this can go with it? The streamer would need some target specific
   // refactoring too.
-  SmallPtrSet<const MCSymbol*, 64> ThumbFuncs;
+  mutable SmallPtrSet<const MCSymbol*, 64> ThumbFuncs;
 
   /// \brief The bundle alignment size currently set in the assembler.
   ///
@@ -995,9 +995,7 @@ public:
                         const MCAsmLayout &Layout) const;
 
   /// Check whether a given symbol has been flagged with .thumb_func.
-  bool isThumbFunc(const MCSymbol *Func) const {
-    return ThumbFuncs.count(Func);
-  }
+  bool isThumbFunc(const MCSymbol *Func) const;
 
   /// Flag a function symbol as the target of a .thumb_func directive.
   void setIsThumbFunc(const MCSymbol *Func) { ThumbFuncs.insert(Func); }
diff --git a/include/llvm/MC/MCELFSymbolFlags.h b/include/llvm/MC/MCELFSymbolFlags.h
index 5b82a58f40..2f1f561221 100644
--- a/include/llvm/MC/MCELFSymbolFlags.h
+++ b/include/llvm/MC/MCELFSymbolFlags.h
@@ -24,9 +24,7 @@ namespace llvm {
     ELF_STT_Shift   = 0,  // Shift value for STT_* flags.
     ELF_STB_Shift   = 4,  // Shift value for STB_* flags.
     ELF_STV_Shift   = 8,  // Shift value for STV_* flags.
-    ELF_STO_Shift   = 10, // Shift value for STO_* flags.
-    ELF_Other_Shift = 16  // Shift value for llvm local flags,
-                          // not part of the final object file
+    ELF_STO_Shift   = 10  // Shift value for STO_* flags.
   };
 
   enum ELFSymbolFlags {
@@ -49,9 +47,7 @@ namespace llvm {
       ELF_STV_Default   = (ELF::STV_DEFAULT   << ELF_STV_Shift),
       ELF_STV_Internal  = (ELF::STV_INTERNAL  << ELF_STV_Shift),
       ELF_STV_Hidden    = (ELF::STV_HIDDEN    << ELF_STV_Shift),
-      ELF_STV_Protected = (ELF::STV_PROTECTED << ELF_STV_Shift),
-
-      ELF_Other_ThumbFunc = (1                << ELF_Other_Shift)
+      ELF_STV_Protected = (ELF::STV_PROTECTED << ELF_STV_Shift)
   };
 
 } // end namespace llvm
diff --git a/include/llvm/MC/MCExpr.h b/include/llvm/MC/MCExpr.h
index 0033a54e42..f28adfa865 100644
--- a/include/llvm/MC/MCExpr.h
+++ b/include/llvm/MC/MCExpr.h
@@ -53,8 +53,9 @@ protected:
 
   bool EvaluateAsRelocatableImpl(MCValue &Res, const MCAssembler *Asm,
                                  const MCAsmLayout *Layout,
-                                 const SectionAddrMap *Addrs,
-                                 bool InSet) const;
+                                 const SectionAddrMap *Addrs, bool InSet,
+                                 bool ForceVarExpansion) const;
+
 public:
   /// @name Accessors
   /// @{
@@ -93,6 +94,14 @@ public:
   /// @result - True on success.
   bool EvaluateAsRelocatable(MCValue &Res, const MCAsmLayout *Layout) const;
 
+  /// \brief Try to evaluate the expression to the form (a - b + constant) where
+  /// neither a nor b are variables.
+  ///
+  /// This is a more aggressive variant of EvaluateAsRelocatable. The intended
+  /// use is for when relocations are not available, like the symbol value in
+  /// the symbol table.
+  bool EvaluateAsValue(MCValue &Res, const MCAsmLayout *Layout) const;
+
   /// FindAssociatedSection - Find the "associated section" for this expression,
   /// which is currently defined as the absolute section for constants, or
   /// otherwise the section associated with the first defined symbol in the
diff --git a/include/llvm/MC/MCSectionELF.h b/include/llvm/MC/MCSectionELF.h
index b91cea5c99..5ec23f1afa 100644
--- a/include/llvm/MC/MCSectionELF.h
+++ b/include/llvm/MC/MCSectionELF.h
@@ -14,7 +14,7 @@
 #ifndef LLVM_MC_MCSECTIONELF_H
 #define LLVM_MC_MCSECTIONELF_H
 
-#include "llvm/ADT/StringRef.h"
+#include "llvm/ADT/Twine.h"
 #include "llvm/MC/MCSection.h"
 #include "llvm/MC/MCSymbol.h"
 #include "llvm/Support/Debug.h"
diff --git a/include/llvm/Object/ELF.h b/include/llvm/Object/ELF.h
index bc9cc673cb..a9989c2a80 100644
--- a/include/llvm/Object/ELF.h
+++ b/include/llvm/Object/ELF.h
@@ -317,6 +317,11 @@ public:
 
   ELFFile(MemoryBuffer *Object, error_code &ec);
 
+  bool isMipsELF64() const {
+    return Header->e_machine == ELF::EM_MIPS &&
+      Header->getFileClass() == ELF::ELFCLASS64;
+  }
+
   bool isMips64EL() const {
     return Header->e_machine == ELF::EM_MIPS &&
       Header->getFileClass() == ELF::ELFCLASS64 &&
@@ -537,10 +542,16 @@ StringRef ELFFile<ELFT>::getRelocationTypeName(uint32_t Type) const {
 template <class ELFT>
 void ELFFile<ELFT>::getRelocationTypeName(uint32_t Type,
                                           SmallVectorImpl<char> &Result) const {
-  if (!isMips64EL()) {
+  if (!isMipsELF64()) {
     StringRef Name = getRelocationTypeName(Type);
     Result.append(Name.begin(), Name.end());
   } else {
+    // The Mips N64 ABI allows up to three operations to be specified per
+    // relocation record. Unfortunately there's no easy way to test for the
+    // presence of N64 ELFs as they have no special flag that identifies them
+    // as being N64. We can safely assume at the moment that all Mips
+    // ELFCLASS64 ELFs are N64. New Mips64 ABIs should provide enough
+    // information to disambiguate between old vs new ABIs.
     uint8_t Type1 = (Type >> 0) & 0xFF;
     uint8_t Type2 = (Type >> 8) & 0xFF;
     uint8_t Type3 = (Type >> 16) & 0xFF;
diff --git a/include/llvm/Object/StringTableBuilder.h b/include/llvm/Object/StringTableBuilder.h
new file mode 100644
index 0000000000..c61e216bdf
--- /dev/null
+++ b/include/llvm/Object/StringTableBuilder.h
@@ -0,0 +1,59 @@
+//===-- StringTableBuilder.h - String table building utility ------*- C++ -*-=//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_OBJECT_STRINGTABLE_BUILDER_H
+#define LLVM_OBJECT_STRINGTABLE_BUILDER_H
+
+#include "llvm/ADT/SmallString.h"
+#include "llvm/ADT/StringMap.h"
+#include <cassert>
+
+namespace llvm {
+
+/// \brief Utility for building string tables with deduplicated suffixes.
+class StringTableBuilder {
+  SmallString<256> StringTable;
+  StringMap<size_t> StringIndexMap;
+
+public:
+  /// \brief Add a string to the builder. Returns a StringRef to the internal
+  /// copy of s. Can only be used before the table is finalized.
+  StringRef add(StringRef s) {
+    assert(!isFinalized());
+    return StringIndexMap.GetOrCreateValue(s, 0).getKey();
+  }
+
+  /// \brief Analyze the strings and build the final table. No more strings can
+  /// be added after this point.
+  void finalize();
+
+  /// \brief Retrieve the string table data. Can only be used after the table
+  /// is finalized.
+  StringRef data() {
+    assert(isFinalized());
+    return StringTable;
+  }
+
+  /// \brief Get the offest of a string in the string table. Can only be used
+  /// after the table is finalized.
+  size_t getOffset(StringRef s) {
+    assert(isFinalized());
+    assert(StringIndexMap.count(s) && "String is not in table!");
+    return StringIndexMap[s];
+  }
+
+private:
+  bool isFinalized() {
+    return !StringTable.empty();
+  }
+};
+
+} // end llvm namespace
+
+#endif
diff --git a/include/llvm/Support/BlockFrequency.h b/include/llvm/Support/BlockFrequency.h
index dae520b54e..4304a253b2 100644
--- a/include/llvm/Support/BlockFrequency.h
+++ b/include/llvm/Support/BlockFrequency.h
@@ -23,14 +23,8 @@ class BranchProbability;
 
 // This class represents Block Frequency as a 64-bit value.
 class BlockFrequency {
-
   uint64_t Frequency;
 
-  /// \brief Scale the given BlockFrequency by N/D. Return the remainder from
-  /// the division by D. Upon overflow, the routine will saturate and
-  /// additionally will return the remainder set to D.
-  uint32_t scale(uint32_t N, uint32_t D);
-
 public:
   BlockFrequency(uint64_t Freq = 0) : Frequency(Freq) { }
 
@@ -58,10 +52,6 @@ public:
   /// \brief Shift block frequency to the right by count digits saturating to 1.
   BlockFrequency &operator>>=(const unsigned count);
 
-  /// \brief Scale the given BlockFrequency by N/D. Return the remainder from
-  /// the division by D. Upon overflow, the routine will saturate.
-  uint32_t scale(const BranchProbability &Prob);
-
   bool operator<(const BlockFrequency &RHS) const {
     return Frequency < RHS.Frequency;
   }
diff --git a/include/llvm/Support/BranchProbability.h b/include/llvm/Support/BranchProbability.h
index eedf69247e..9aab6ace6e 100644
--- a/include/llvm/Support/BranchProbability.h
+++ b/include/llvm/Support/BranchProbability.h
@@ -46,10 +46,26 @@ public:
     return BranchProbability(D - N, D);
   }
 
-  void print(raw_ostream &OS) const;
+  raw_ostream &print(raw_ostream &OS) const;
 
   void dump() const;
 
+  /// \brief Scale a large integer.
+  ///
+  /// Scales \c Num.  Guarantees full precision.  Returns the floor of the
+  /// result.
+  ///
+  /// \return \c Num times \c this.
+  uint64_t scale(uint64_t Num) const;
+
+  /// \brief Scale a large integer by the inverse.
+  ///
+  /// Scales \c Num by the inverse of \c this.  Guarantees full precision.
+  /// Returns the floor of the result.
+  ///
+  /// \return \c Num divided by \c this.
+  uint64_t scaleByInverse(uint64_t Num) const;
+
   bool operator==(BranchProbability RHS) const {
     return (uint64_t)N * RHS.D == (uint64_t)D * RHS.N;
   }
@@ -59,18 +75,14 @@ public:
   bool operator<(BranchProbability RHS) const {
     return (uint64_t)N * RHS.D < (uint64_t)D * RHS.N;
   }
-  bool operator>(BranchProbability RHS) const {
-    return RHS < *this;
-  }
-  bool operator<=(BranchProbability RHS) const {
-    return (uint64_t)N * RHS.D <= (uint64_t)D * RHS.N;
-  }
-  bool operator>=(BranchProbability RHS) const {
-    return RHS <= *this;
-  }
+  bool operator>(BranchProbability RHS) const { return RHS < *this; }
+  bool operator<=(BranchProbability RHS) const { return !(RHS < *this); }
+  bool operator>=(BranchProbability RHS) const { return !(*this < RHS); }
 };
 
-raw_ostream &operator<<(raw_ostream &OS, const BranchProbability &Prob);
+inline raw_ostream &operator<<(raw_ostream &OS, const BranchProbability &Prob) {
+  return Prob.print(OS);
+}
 
 }
 
diff --git a/include/llvm/Support/FileSystem.h b/include/llvm/Support/FileSystem.h
index b2a0677082..806a3e376c 100644
--- a/include/llvm/Support/FileSystem.h
+++ b/include/llvm/Support/FileSystem.h
@@ -165,15 +165,30 @@ class file_status
   file_type Type;
   perms Perms;
 public:
-  file_status() : Type(file_type::status_error) {}
-  file_status(file_type Type) : Type(Type) {}
-
   #if defined(LLVM_ON_UNIX)
+    file_status() : fs_st_dev(0), fs_st_ino(0), fs_st_mtime(0),
+        fs_st_uid(0), fs_st_gid(0), fs_st_size(0),
+        Type(file_type::status_error), Perms(perms_not_known) {}
+
+    file_status(file_type Type) : fs_st_dev(0), fs_st_ino(0), fs_st_mtime(0),
+        fs_st_uid(0), fs_st_gid(0), fs_st_size(0), Type(Type),
+        Perms(perms_not_known) {}
+
     file_status(file_type Type, perms Perms, dev_t Dev, ino_t Ino, time_t MTime,
                 uid_t UID, gid_t GID, off_t Size)
         : fs_st_dev(Dev), fs_st_ino(Ino), fs_st_mtime(MTime), fs_st_uid(UID),
           fs_st_gid(GID), fs_st_size(Size), Type(Type), Perms(Perms) {}
   #elif defined(LLVM_ON_WIN32)
+    file_status() : LastWriteTimeHigh(0), LastWriteTimeLow(0),
+        VolumeSerialNumber(0), FileSizeHigh(0), FileSizeLow(0),
+        FileIndexHigh(0), FileIndexLow(0), Type(file_type::status_error),
+        Perms(perms_not_known) {}
+
+    file_status(file_type Type) : LastWriteTimeHigh(0), LastWriteTimeLow(0),
+        VolumeSerialNumber(0), FileSizeHigh(0), FileSizeLow(0),
+        FileIndexHigh(0), FileIndexLow(0), Type(Type),
+        Perms(perms_not_known) {}
+
     file_status(file_type Type, uint32_t LastWriteTimeHigh,
                 uint32_t LastWriteTimeLow, uint32_t VolumeSerialNumber,
                 uint32_t FileSizeHigh, uint32_t FileSizeLow,
@@ -562,7 +577,7 @@ error_code createTemporaryFile(const Twine &Prefix, StringRef Suffix,
 error_code createUniqueDirectory(const Twine &Prefix,
                                  SmallVectorImpl<char> &ResultPath);
 
-enum OpenFlags {
+enum OpenFlags : unsigned {
   F_None = 0,
 
   /// F_Excl - When opening a file, this flag makes raw_fd_ostream
diff --git a/include/llvm/Support/raw_ostream.h b/include/llvm/Support/raw_ostream.h
index a0f2c7798f..34fbe082cd 100644
--- a/include/llvm/Support/raw_ostream.h
+++ b/include/llvm/Support/raw_ostream.h
@@ -17,13 +17,18 @@
 #include "llvm/ADT/StringRef.h"
 #include "llvm/Support/Compiler.h"
 #include "llvm/Support/DataTypes.h"
-#include "llvm/Support/FileSystem.h"
 
 namespace llvm {
   class format_object_base;
   template <typename T>
   class SmallVectorImpl;
 
+  namespace sys {
+    namespace fs {
+      enum OpenFlags : unsigned;
+    }
+  }
+
 /// raw_ostream - This class implements an extremely fast bulk output stream
 /// that can *only* output to a stream.  It does not support seeking, reopening,
 /// rewinding, line buffered disciplines etc. It is a simple buffer that outputs
@@ -157,7 +162,7 @@ public:
     size_t Size = Str.size();
 
     // Make sure we can use the fast path.
-    if (OutBufCur+Size > OutBufEnd)
+    if (Size > (size_t)(OutBufEnd - OutBufCur))
       return write(Str.data(), Size);
 
     memcpy(OutBufCur, Str.data(), Size);
diff --git a/lib/Analysis/BlockFrequencyInfoImpl.cpp b/lib/Analysis/BlockFrequencyInfoImpl.cpp
index 2fcd9b8377..4a61e3446d 100644
--- a/lib/Analysis/BlockFrequencyInfoImpl.cpp
+++ b/lib/Analysis/BlockFrequencyInfoImpl.cpp
@@ -17,6 +17,7 @@
 #include <deque>
 
 using namespace llvm;
+using namespace llvm::bfi_detail;
 
 #define DEBUG_TYPE "block-freq"
 
@@ -310,32 +311,6 @@ std::pair<uint64_t, int16_t> UnsignedFloatBase::multiply64(uint64_t L,
 // BlockMass implementation.
 //
 //===----------------------------------------------------------------------===//
-BlockMass &BlockMass::operator*=(const BranchProbability &P) {
-  uint32_t N = P.getNumerator(), D = P.getDenominator();
-  assert(D && "divide by 0");
-  assert(N <= D && "fraction greater than 1");
-
-  // Fast path for multiplying by 1.0.
-  if (!Mass || N == D)
-    return *this;
-
-  // Get as much precision as we can.
-  int Shift = countLeadingZeros(Mass);
-  uint64_t ShiftedQuotient = (Mass << Shift) / D;
-  uint64_t Product = ShiftedQuotient * N >> Shift;
-
-  // Now check for what's lost.
-  uint64_t Left = ShiftedQuotient * (D - N) >> Shift;
-  uint64_t Lost = Mass - Product - Left;
-
-  // TODO: prove this assertion.
-  assert(Lost <= UINT32_MAX);
-
-  // Take the product plus a portion of the spoils.
-  Mass = Product + Lost * N / D;
-  return *this;
-}
-
 UnsignedFloat<uint64_t> BlockMass::toFloat() const {
   if (isFull())
     return UnsignedFloat<uint64_t>(1, 0);
@@ -568,7 +543,7 @@ static void cleanup(BlockFrequencyInfoImplBase &BFI) {
   BFI.Freqs = std::move(SavedFreqs);
 }
 
-void BlockFrequencyInfoImplBase::addToDist(Distribution &Dist,
+bool BlockFrequencyInfoImplBase::addToDist(Distribution &Dist,
                                            const LoopData *OuterLoop,
                                            const BlockNode &Pred,
                                            const BlockNode &Succ,
@@ -598,34 +573,48 @@ void BlockFrequencyInfoImplBase::addToDist(Distribution &Dist,
   if (isLoopHeader(Resolved)) {
     DEBUG(debugSuccessor("backedge"));
     Dist.addBackedge(OuterLoop->getHeader(), Weight);
-    return;
+    return true;
   }
 
   if (Working[Resolved.Index].getContainingLoop() != OuterLoop) {
     DEBUG(debugSuccessor("  exit  "));
     Dist.addExit(Resolved, Weight);
-    return;
+    return true;
   }
 
   if (Resolved < Pred) {
-    // Irreducible backedge.  Skip.
-    DEBUG(debugSuccessor("  skip  "));
-    return;
+    if (!isLoopHeader(Pred)) {
+      // If OuterLoop is an irreducible loop, we can't actually handle this.
+      assert((!OuterLoop || !OuterLoop->isIrreducible()) &&
+             "unhandled irreducible control flow");
+
+      // Irreducible backedge.  Abort.
+      DEBUG(debugSuccessor("abort!!!"));
+      return false;
+    }
+
+    // If "Pred" is a loop header, then this isn't really a backedge; rather,
+    // OuterLoop must be irreducible.  These false backedges can come only from
+    // secondary loop headers.
+    assert(OuterLoop && OuterLoop->isIrreducible() && !isLoopHeader(Resolved) &&
+           "unhandled irreducible control flow");
   }
 
   DEBUG(debugSuccessor(" local  "));
   Dist.addLocal(Resolved, Weight);
+  return true;
 }
 
-void BlockFrequencyInfoImplBase::addLoopSuccessorsToDist(
+bool BlockFrequencyInfoImplBase::addLoopSuccessorsToDist(
     const LoopData *OuterLoop, LoopData &Loop, Distribution &Dist) {
   // Copy the exit map into Dist.
   for (const auto &I : Loop.Exits)
-    addToDist(Dist, OuterLoop, Loop.getHeader(), I.first, I.second.getMass());
+    if (!addToDist(Dist, OuterLoop, Loop.getHeader(), I.first,
+                   I.second.getMass()))
+      // Irreducible backedge.
+      return false;
 
-  // We don't need this map any more.  Clear it to prevent quadratic memory
-  // usage in deeply nested loops with irreducible control flow.
-  Loop.Exits.clear();
+  return true;
 }
 
 /// \brief Get the maximum allowed loop scale.
@@ -637,8 +626,7 @@ static Float getMaxLoopScale() { return Float(1, 12); }
 /// \brief Compute the loop scale for a loop.
 void BlockFrequencyInfoImplBase::computeLoopScale(LoopData &Loop) {
   // Compute loop scale.
-  DEBUG(dbgs() << "compute-loop-scale: " << getBlockName(Loop.getHeader())
-               << "\n");
+  DEBUG(dbgs() << "compute-loop-scale: " << getLoopName(Loop) << "\n");
 
   // LoopScale == 1 / ExitMass
   // ExitMass == HeadMass - BackedgeMass
@@ -659,12 +647,15 @@ void BlockFrequencyInfoImplBase::computeLoopScale(LoopData &Loop) {
 
 /// \brief Package up a loop.
 void BlockFrequencyInfoImplBase::packageLoop(LoopData &Loop) {
-  DEBUG(dbgs() << "packaging-loop: " << getBlockName(Loop.getHeader()) << "\n");
+  DEBUG(dbgs() << "packaging-loop: " << getLoopName(Loop) << "\n");
+
+  // Clear the subloop exits to prevent quadratic memory usage.
+  for (const BlockNode &M : Loop.Nodes) {
+    if (auto *Loop = Working[M.Index].getPackagedLoop())
+      Loop->Exits.clear();
+    DEBUG(dbgs() << " - node: " << getBlockName(M.Index) << "\n");
+  }
   Loop.IsPackaged = true;
-  DEBUG(for (const BlockNode &M
-             : Loop.members()) {
-               dbgs() << " - node: " << getBlockName(M.Index) << "\n";
-             });
 }
 
 void BlockFrequencyInfoImplBase::distributeMass(const BlockNode &Source,
@@ -745,7 +736,7 @@ static void convertFloatingToInteger(BlockFrequencyInfoImplBase &BFI,
 /// Visits all the members of a loop, adjusting their BlockData according to
 /// the loop's pseudo-node.
 static void unwrapLoop(BlockFrequencyInfoImplBase &BFI, LoopData &Loop) {
-  DEBUG(dbgs() << "unwrap-loop-package: " << BFI.getBlockName(Loop.getHeader())
+  DEBUG(dbgs() << "unwrap-loop-package: " << BFI.getLoopName(Loop)
                << ": mass = " << Loop.Mass << ", scale = " << Loop.Scale
                << "\n");
   Loop.Scale *= Loop.Mass.toFloat();
@@ -757,7 +748,7 @@ static void unwrapLoop(BlockFrequencyInfoImplBase &BFI, LoopData &Loop) {
   // final head scale will be used for updated the rest of the members.
   for (const BlockNode &N : Loop.Nodes) {
     const auto &Working = BFI.Working[N.Index];
-    Float &F = Working.isAPackage() ? BFI.getLoopPackage(N).Scale
+    Float &F = Working.isAPackage() ? Working.getPackagedLoop()->Scale
                                     : BFI.Freqs[N.Index].Floating;
     Float New = Loop.Scale * F;
     DEBUG(dbgs() << " - " << BFI.getBlockName(N) << ": " << F << " => " << New
@@ -813,6 +804,10 @@ std::string
 BlockFrequencyInfoImplBase::getBlockName(const BlockNode &Node) const {
   return std::string();
 }
+std::string
+BlockFrequencyInfoImplBase::getLoopName(const LoopData &Loop) const {
+  return getBlockName(Loop.getHeader()) + (Loop.isIrreducible() ? "**" : "*");
+}
 
 raw_ostream &
 BlockFrequencyInfoImplBase::printBlockFreq(raw_ostream &OS,
@@ -828,3 +823,172 @@ BlockFrequencyInfoImplBase::printBlockFreq(raw_ostream &OS,
 
   return OS << Block / Entry;
 }
+
+void IrreducibleGraph::addNodesInLoop(const BFIBase::LoopData &OuterLoop) {
+  Start = OuterLoop.getHeader();
+  Nodes.reserve(OuterLoop.Nodes.size());
+  for (auto N : OuterLoop.Nodes)
+    addNode(N);
+  indexNodes();
+}
+void IrreducibleGraph::addNodesInFunction() {
+  Start = 0;
+  for (uint32_t Index = 0; Index < BFI.Working.size(); ++Index)
+    if (!BFI.Working[Index].isPackaged())
+      addNode(Index);
+  indexNodes();
+}
+void IrreducibleGraph::indexNodes() {
+  for (auto &I : Nodes)
+    Lookup[I.Node.Index] = &I;
+}
+void IrreducibleGraph::addEdge(IrrNode &Irr, const BlockNode &Succ,
+                               const BFIBase::LoopData *OuterLoop) {
+  if (OuterLoop && OuterLoop->isHeader(Succ))
+    return;
+  auto L = Lookup.find(Succ.Index);
+  if (L == Lookup.end())
+    return;
+  IrrNode &SuccIrr = *L->second;
+  Irr.Edges.push_back(&SuccIrr);
+  SuccIrr.Edges.push_front(&Irr);
+  ++SuccIrr.NumIn;
+}
+
+namespace llvm {
+template <> struct GraphTraits<IrreducibleGraph> {
+  typedef bfi_detail::IrreducibleGraph GraphT;
+
+  typedef const GraphT::IrrNode NodeType;
+  typedef GraphT::IrrNode::iterator ChildIteratorType;
+
+  static const NodeType *getEntryNode(const GraphT &G) {
+    return G.StartIrr;
+  }
+  static ChildIteratorType child_begin(NodeType *N) { return N->succ_begin(); }
+  static ChildIteratorType child_end(NodeType *N) { return N->succ_end(); }
+};
+}
+
+/// \brief Find extra irreducible headers.
+///
+/// Find entry blocks and other blocks with backedges, which exist when \c G
+/// contains irreducible sub-SCCs.
+static void findIrreducibleHeaders(
+    const BlockFrequencyInfoImplBase &BFI,
+    const IrreducibleGraph &G,
+    const std::vector<const IrreducibleGraph::IrrNode *> &SCC,
+    LoopData::NodeList &Headers, LoopData::NodeList &Others) {
+  // Map from nodes in the SCC to whether it's an entry block.
+  SmallDenseMap<const IrreducibleGraph::IrrNode *, bool, 8> InSCC;
+
+  // InSCC also acts the set of nodes in the graph.  Seed it.
+  for (const auto *I : SCC)
+    InSCC[I] = false;
+
+  for (auto I = InSCC.begin(), E = InSCC.end(); I != E; ++I) {
+    auto &Irr = *I->first;
+    for (const auto *P : make_range(Irr.pred_begin(), Irr.pred_end())) {
+      if (InSCC.count(P))
+        continue;
+
+      // This is an entry block.
+      I->second = true;
+      Headers.push_back(Irr.Node);
+      DEBUG(dbgs() << "  => entry = " << BFI.getBlockName(Irr.Node) << "\n");
+      break;
+    }
+  }
+  assert(Headers.size() >= 2 && "Should be irreducible");
+  if (Headers.size() == InSCC.size()) {
+    // Every block is a header.
+    std::sort(Headers.begin(), Headers.end());
+    return;
+  }
+
+  // Look for extra headers from irreducible sub-SCCs.
+  for (const auto &I : InSCC) {
+    // Entry blocks are already headers.
+    if (I.second)
+      continue;
+
+    auto &Irr = *I.first;
+    for (const auto *P : make_range(Irr.pred_begin(), Irr.pred_end())) {
+      // Skip forward edges.
+      if (P->Node < Irr.Node)
+        continue;
+
+      // Skip predecessors from entry blocks.  These can have inverted
+      // ordering.
+      if (InSCC.lookup(P))
+        continue;
+
+      // Store the extra header.
+      Headers.push_back(Irr.Node);
+      DEBUG(dbgs() << "  => extra = " << BFI.getBlockName(Irr.Node) << "\n");
+      break;
+    }
+    if (Headers.back() == Irr.Node)
+      // Added this as a header.
+      continue;
+
+    // This is not a header.
+    Others.push_back(Irr.Node);
+    DEBUG(dbgs() << "  => other = " << BFI.getBlockName(Irr.Node) << "\n");
+  }
+  std::sort(Headers.begin(), Headers.end());
+  std::sort(Others.begin(), Others.end());
+}
+
+static void createIrreducibleLoop(
+    BlockFrequencyInfoImplBase &BFI, const IrreducibleGraph &G,
+    LoopData *OuterLoop, std::list<LoopData>::iterator Insert,
+    const std::vector<const IrreducibleGraph::IrrNode *> &SCC) {
+  // Translate the SCC into RPO.
+  DEBUG(dbgs() << " - found-scc\n");
+
+  LoopData::NodeList Headers;
+  LoopData::NodeList Others;
+  findIrreducibleHeaders(BFI, G, SCC, Headers, Others);
+
+  auto Loop = BFI.Loops.emplace(Insert, OuterLoop, Headers.begin(),
+                                Headers.end(), Others.begin(), Others.end());
+
+  // Update loop hierarchy.
+  for (const auto &N : Loop->Nodes)
+    if (BFI.Working[N.Index].isLoopHeader())
+      BFI.Working[N.Index].Loop->Parent = &*Loop;
+    else
+      BFI.Working[N.Index].Loop = &*Loop;
+}
+
+iterator_range<std::list<LoopData>::iterator>
+BlockFrequencyInfoImplBase::analyzeIrreducible(
+    const IrreducibleGraph &G, LoopData *OuterLoop,
+    std::list<LoopData>::iterator Insert) {
+  assert((OuterLoop == nullptr) == (Insert == Loops.begin()));
+  auto Prev = OuterLoop ? std::prev(Insert) : Loops.end();
+
+  for (auto I = scc_begin(G); !I.isAtEnd(); ++I) {
+    if (I->size() < 2)
+      continue;
+
+    // Translate the SCC into RPO.
+    createIrreducibleLoop(*this, G, OuterLoop, Insert, *I);
+  }
+
+  if (OuterLoop)
+    return make_range(std::next(Prev), Insert);
+  return make_range(Loops.begin(), Insert);
+}
+
+void
+BlockFrequencyInfoImplBase::updateLoopWithIrreducible(LoopData &OuterLoop) {
+  OuterLoop.Exits.clear();
+  OuterLoop.BackedgeMass = BlockMass::getEmpty();
+  auto O = OuterLoop.Nodes.begin() + 1;
+  for (auto I = O, E = OuterLoop.Nodes.end(); I != E; ++I)
+    if (!Working[I->Index].isPackaged())
+      *O++ = *I;
+  OuterLoop.Nodes.erase(O, OuterLoop.Nodes.end());
+}
diff --git a/lib/Analysis/CFGPrinter.cpp b/lib/Analysis/CFGPrinter.cpp
index 0fcc24e409..6d421ab236 100644
--- a/lib/Analysis/CFGPrinter.cpp
+++ b/lib/Analysis/CFGPrinter.cpp
@@ -19,6 +19,7 @@
 
 #include "llvm/Analysis/CFGPrinter.h"
 #include "llvm/Pass.h"
+#include "llvm/Support/FileSystem.h"
 using namespace llvm;
 
 namespace {
diff --git a/lib/Analysis/LazyCallGraph.cpp b/lib/Analysis/LazyCallGraph.cpp
index 05757e1e2f..6c4574f867 100644
--- a/lib/Analysis/LazyCallGraph.cpp
+++ b/lib/Analysis/LazyCallGraph.cpp
@@ -76,11 +76,16 @@ LazyCallGraph::Node::Node(LazyCallGraph &G, Function &F)
 }
 
 void LazyCallGraph::Node::insertEdgeInternal(Function &Callee) {
-  CalleeIndexMap.insert(std::make_pair(&Callee, Callees.size()));
   if (Node *N = G->lookup(Callee))
-    Callees.push_back(N);
-  else
-    Callees.push_back(&Callee);
+    return insertEdgeInternal(*N);
+
+  CalleeIndexMap.insert(std::make_pair(&Callee, Callees.size()));
+  Callees.push_back(&Callee);
+}
+
+void LazyCallGraph::Node::insertEdgeInternal(Node &CalleeN) {
+  CalleeIndexMap.insert(std::make_pair(&CalleeN.getFunction(), Callees.size()));
+  Callees.push_back(&CalleeN);
 }
 
 void LazyCallGraph::Node::removeEdgeInternal(Function &Callee) {
@@ -88,7 +93,7 @@ void LazyCallGraph::Node::removeEdgeInternal(Function &Callee) {
   assert(IndexMapI != CalleeIndexMap.end() &&
          "Callee not in the callee set for this caller?");
 
-  Callees.erase(Callees.begin() + IndexMapI->second);
+  Callees[IndexMapI->second] = nullptr;
   CalleeIndexMap.erase(IndexMapI);
 }
 
@@ -115,11 +120,14 @@ LazyCallGraph::LazyCallGraph(Module &M) : NextDFSNumber(0) {
                   "entry set.\n");
   findCallees(Worklist, Visited, EntryNodes, EntryIndexMap);
 
-  for (auto &Entry : EntryNodes)
+  for (auto &Entry : EntryNodes) {
+    assert(!Entry.isNull() &&
+           "We can't have removed edges before we finish the constructor!");
     if (Function *F = Entry.dyn_cast<Function *>())
       SCCEntryNodes.push_back(F);
     else
       SCCEntryNodes.push_back(&Entry.get<Node *>()->getFunction());
+  }
 }
 
 LazyCallGraph::LazyCallGraph(LazyCallGraph &&G)
@@ -154,6 +162,16 @@ void LazyCallGraph::SCC::insert(Node &N) {
   G->SCCMap[&N] = this;
 }
 
+void LazyCallGraph::SCC::insertIntraSCCEdge(Node &CallerN, Node &CalleeN) {
+  // First insert it into the caller.
+  CallerN.insertEdgeInternal(CalleeN);
+
+  assert(G->SCCMap.lookup(&CallerN) == this && "Caller must be in this SCC.");
+  assert(G->SCCMap.lookup(&CalleeN) == this && "Callee must be in this SCC.");
+
+  // Nothing changes about this SCC or any other.
+}
+
 void LazyCallGraph::SCC::removeInterSCCEdge(Node &CallerN, Node &CalleeN) {
   // First remove it from the node.
   CallerN.removeEdgeInternal(CalleeN.getFunction());
@@ -391,8 +409,9 @@ void LazyCallGraph::updateGraphPtrs() {
       Node *N = Worklist.pop_back_val();
       N->G = this;
       for (auto &Callee : N->Callees)
-        if (Node *CalleeN = Callee.dyn_cast<Node *>())
-          Worklist.push_back(CalleeN);
+        if (!Callee.isNull())
+          if (Node *CalleeN = Callee.dyn_cast<Node *>())
+            Worklist.push_back(CalleeN);
     }
   }
 
diff --git a/lib/Bitcode/Writer/BitWriter.cpp b/lib/Bitcode/Writer/BitWriter.cpp
index 0275f96fc9..3747122fc9 100644
--- a/lib/Bitcode/Writer/BitWriter.cpp
+++ b/lib/Bitcode/Writer/BitWriter.cpp
@@ -10,6 +10,7 @@
 #include "llvm-c/BitWriter.h"
 #include "llvm/Bitcode/ReaderWriter.h"
 #include "llvm/IR/Module.h"
+#include "llvm/Support/FileSystem.h"
 #include "llvm/Support/raw_ostream.h"
 using namespace llvm;
 
diff --git a/lib/CodeGen/AsmPrinter/AddressPool.h b/lib/CodeGen/AsmPrinter/AddressPool.h
index 3058fed33f..42757d732f 100644
--- a/lib/CodeGen/AsmPrinter/AddressPool.h
+++ b/lib/CodeGen/AsmPrinter/AddressPool.h
@@ -26,6 +26,11 @@ class AddressPool {
     AddressPoolEntry(unsigned Number, bool TLS) : Number(Number), TLS(TLS) {}
   };
   DenseMap<const MCSymbol *, AddressPoolEntry> Pool;
+
+  /// Record whether the AddressPool has been queried for an address index since
+  /// the last "resetUsedFlag" call. Used to implement type unit fallback - a
+  /// type that references addresses cannot be placed in a type unit when using
+  /// fission.
   bool HasBeenUsed;
 
 public:
diff --git a/lib/CodeGen/AsmPrinter/DIE.h b/lib/CodeGen/AsmPrinter/DIE.h
index 1a1c080c32..ef05f17078 100644
--- a/lib/CodeGen/AsmPrinter/DIE.h
+++ b/lib/CodeGen/AsmPrinter/DIE.h
@@ -124,6 +124,12 @@ protected:
 
   /// Children DIEs.
   ///
+  // This can't be a vector<DIE> because pointer validity is requirent for the
+  // Parent pointer and DIEEntry.
+  // It can't be a list<DIE> because some clients need pointer validity before
+  // the object has been added to any child list
+  // (eg: DwarfUnit::constructVariableDIE). These aren't insurmountable, but may
+  // be more convoluted than beneficial.
   std::vector<std::unique_ptr<DIE>> Children;
 
   DIE *Parent;
diff --git a/lib/CodeGen/AsmPrinter/DwarfDebug.cpp b/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
index 948d7fd380..4033e65ace 100644
--- a/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
+++ b/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
@@ -118,7 +118,6 @@ bool DbgVariable::isBlockByrefVariable() const {
   return Var.isBlockByrefVariable(DD->getTypeIdentifierMap());
 }
 
-
 DIType DbgVariable::getType() const {
   DIType Ty = Var.getType().resolve(DD->getTypeIdentifierMap());
   // FIXME: isBlockByrefVariable should be reformulated in terms of complex
@@ -210,9 +209,8 @@ DwarfDebug::DwarfDebug(AsmPrinter *A, Module *M)
   else
     HasDwarfPubSections = DwarfPubSections == Enable;
 
-  DwarfVersion = DwarfVersionNumber
-                     ? DwarfVersionNumber
-                     : MMI->getModule()->getDwarfVersion();
+  DwarfVersion = DwarfVersionNumber ? DwarfVersionNumber
+                                    : MMI->getModule()->getDwarfVersion();
 
   {
     NamedRegionTimer T(DbgTimerName, DWARFGroupName, TimePassesIsEnabled);
@@ -311,7 +309,7 @@ bool DwarfDebug::isSubprogramContext(const MDNode *Context) {
 // Find DIE for the given subprogram and attach appropriate DW_AT_low_pc
 // and DW_AT_high_pc attributes. If there are global variables in this
 // scope then create and insert DIEs for these variables.
-DIE *DwarfDebug::updateSubprogramScopeDIE(DwarfCompileUnit &SPCU,
+DIE &DwarfDebug::updateSubprogramScopeDIE(DwarfCompileUnit &SPCU,
                                           DISubprogram SP) {
   DIE *SPDie = SPCU.getDIE(SP);
 
@@ -361,7 +359,7 @@ DIE *DwarfDebug::updateSubprogramScopeDIE(DwarfCompileUnit &SPCU,
   // to have concrete versions of our DW_TAG_subprogram nodes.
   addSubprogramNames(SP, *SPDie);
 
-  return SPDie;
+  return *SPDie;
 }
 
 /// Check whether we should create a DIE for the given Scope, return true
@@ -421,12 +419,13 @@ void DwarfDebug::addScopeRangeList(DwarfCompileUnit &TheCU, DIE &ScopeDIE,
 
 // Construct new DW_TAG_lexical_block for this scope and attach
 // DW_AT_low_pc/DW_AT_high_pc labels.
-DIE *DwarfDebug::constructLexicalScopeDIE(DwarfCompileUnit &TheCU,
-                                          LexicalScope *Scope) {
+std::unique_ptr<DIE>
+DwarfDebug::constructLexicalScopeDIE(DwarfCompileUnit &TheCU,
+                                     LexicalScope *Scope) {
   if (isLexicalScopeDIENull(Scope))
     return nullptr;
 
-  DIE *ScopeDIE = new DIE(dwarf::DW_TAG_lexical_block);
+  auto ScopeDIE = make_unique<DIE>(dwarf::DW_TAG_lexical_block);
   if (Scope->isAbstractScope())
     return ScopeDIE;
 
@@ -454,8 +453,9 @@ DIE *DwarfDebug::constructLexicalScopeDIE(DwarfCompileUnit &TheCU,
 
 // This scope represents inlined body of a function. Construct DIE to
 // represent this concrete inlined copy of the function.
-DIE *DwarfDebug::constructInlinedScopeDIE(DwarfCompileUnit &TheCU,
-                                          LexicalScope *Scope) {
+std::unique_ptr<DIE>
+DwarfDebug::constructInlinedScopeDIE(DwarfCompileUnit &TheCU,
+                                     LexicalScope *Scope) {
   const SmallVectorImpl<InsnRange> &ScopeRanges = Scope->getRanges();
   assert(!ScopeRanges.empty() &&
          "LexicalScope does not have instruction markers!");
@@ -470,7 +470,7 @@ DIE *DwarfDebug::constructInlinedScopeDIE(DwarfCompileUnit &TheCU,
     return nullptr;
   }
 
-  DIE *ScopeDIE = new DIE(dwarf::DW_TAG_inlined_subroutine);
+  auto ScopeDIE = make_unique<DIE>(dwarf::DW_TAG_inlined_subroutine);
   TheCU.addDIEEntry(*ScopeDIE, dwarf::DW_AT_abstract_origin, *OriginDIE);
 
   // If we have multiple ranges, emit them into the range section.
@@ -539,38 +539,82 @@ DIE *DwarfDebug::createScopeChildrenDIE(
       ObjectPointer = Children.back().get();
   }
   for (LexicalScope *LS : Scope->getChildren())
-    if (DIE *Nested = constructScopeDIE(TheCU, LS))
-      Children.push_back(std::unique_ptr<DIE>(Nested));
+    if (std::unique_ptr<DIE> Nested = constructScopeDIE(TheCU, LS))
+      Children.push_back(std::move(Nested));
   return ObjectPointer;
 }
 
+void DwarfDebug::createAndAddScopeChildren(DwarfCompileUnit &TheCU,
+                                           LexicalScope *Scope, DIE &ScopeDIE) {
+  // We create children when the scope DIE is not null.
+  SmallVector<std::unique_ptr<DIE>, 8> Children;
+  if (DIE *ObjectPointer = createScopeChildrenDIE(TheCU, Scope, Children))
+    TheCU.addDIEEntry(ScopeDIE, dwarf::DW_AT_object_pointer, *ObjectPointer);
+
+  // Add children
+  for (auto &I : Children)
+    ScopeDIE.addChild(std::move(I));
+}
+
+void DwarfDebug::constructAbstractSubprogramScopeDIE(DwarfCompileUnit &TheCU,
+                                                     LexicalScope *Scope) {
+  assert(Scope && Scope->getScopeNode());
+  assert(Scope->isAbstractScope());
+  assert(!Scope->getInlinedAt());
+
+  DISubprogram Sub(Scope->getScopeNode());
+
+  ProcessedSPNodes.insert(Sub);
+
+  if (DIE *ScopeDIE = TheCU.getDIE(Sub)) {
+    AbstractSPDies.insert(std::make_pair(Sub, ScopeDIE));
+    createAndAddScopeChildren(TheCU, Scope, *ScopeDIE);
+  }
+}
+
+DIE &DwarfDebug::constructSubprogramScopeDIE(DwarfCompileUnit &TheCU,
+                                             LexicalScope *Scope) {
+  assert(Scope && Scope->getScopeNode());
+  assert(!Scope->getInlinedAt());
+  assert(!Scope->isAbstractScope());
+  assert(DIScope(Scope->getScopeNode()).isSubprogram());
+
+  DISubprogram Sub(Scope->getScopeNode());
+
+  ProcessedSPNodes.insert(Sub);
+
+  DIE &ScopeDIE = updateSubprogramScopeDIE(TheCU, Sub);
+
+  createAndAddScopeChildren(TheCU, Scope, ScopeDIE);
+
+  return ScopeDIE;
+}
+
 // Construct a DIE for this scope.
-DIE *DwarfDebug::constructScopeDIE(DwarfCompileUnit &TheCU,
-                                   LexicalScope *Scope) {
+std::unique_ptr<DIE> DwarfDebug::constructScopeDIE(DwarfCompileUnit &TheCU,
+                                                   LexicalScope *Scope) {
   if (!Scope || !Scope->getScopeNode())
     return nullptr;
 
   DIScope DS(Scope->getScopeNode());
 
+  assert((Scope->getInlinedAt() || !DS.isSubprogram()) &&
+         "Only handle inlined subprograms here, use "
+         "constructSubprogramScopeDIE for non-inlined "
+         "subprograms");
+
   SmallVector<std::unique_ptr<DIE>, 8> Children;
-  DIE *ObjectPointer = nullptr;
-  bool ChildrenCreated = false;
 
   // We try to create the scope DIE first, then the children DIEs. This will
   // avoid creating un-used children then removing them later when we find out
   // the scope DIE is null.
-  DIE *ScopeDIE = nullptr;
-  if (Scope->getInlinedAt())
+  std::unique_ptr<DIE> ScopeDIE;
+  if (Scope->getInlinedAt()) {
     ScopeDIE = constructInlinedScopeDIE(TheCU, Scope);
-  else if (DS.isSubprogram()) {
-    ProcessedSPNodes.insert(DS);
-    if (Scope->isAbstractScope()) {
-      ScopeDIE = TheCU.getDIE(DS);
-      // Note down abstract DIE.
-      if (ScopeDIE)
-        AbstractSPDies.insert(std::make_pair(DS, ScopeDIE));
-    } else
-      ScopeDIE = updateSubprogramScopeDIE(TheCU, DISubprogram(DS));
+    if (!ScopeDIE)
+      return nullptr;
+    // We create children when the scope DIE is not null.
+    createScopeChildrenDIE(TheCU, Scope, Children);
   } else {
     // Early exit when we know the scope DIE is going to be null.
     if (isLexicalScopeDIENull(Scope))
@@ -578,42 +622,28 @@ DIE *DwarfDebug::constructScopeDIE(DwarfCompileUnit &TheCU,
 
     // We create children here when we know the scope DIE is not going to be
     // null and the children will be added to the scope DIE.
-    ObjectPointer = createScopeChildrenDIE(TheCU, Scope, Children);
-    ChildrenCreated = true;
+    createScopeChildrenDIE(TheCU, Scope, Children);
 
     // There is no need to emit empty lexical block DIE.
     std::pair<ImportedEntityMap::const_iterator,
               ImportedEntityMap::const_iterator> Range =
-        std::equal_range(
-            ScopesWithImportedEntities.begin(),
-            ScopesWithImportedEntities.end(),
-            std::pair<const MDNode *, const MDNode *>(DS, nullptr),
-            less_first());
+        std::equal_range(ScopesWithImportedEntities.begin(),
+                         ScopesWithImportedEntities.end(),
+                         std::pair<const MDNode *, const MDNode *>(DS, nullptr),
+                         less_first());
     if (Children.empty() && Range.first == Range.second)
       return nullptr;
     ScopeDIE = constructLexicalScopeDIE(TheCU, Scope);
     assert(ScopeDIE && "Scope DIE should not be null.");
     for (ImportedEntityMap::const_iterator i = Range.first; i != Range.second;
          ++i)
-      constructImportedEntityDIE(TheCU, i->second, ScopeDIE);
-  }
-
-  if (!ScopeDIE) {
-    assert(Children.empty() &&
-           "We create children only when the scope DIE is not null.");
-    return nullptr;
+      constructImportedEntityDIE(TheCU, i->second, *ScopeDIE);
   }
-  if (!ChildrenCreated)
-    // We create children when the scope DIE is not null.
-    ObjectPointer = createScopeChildrenDIE(TheCU, Scope, Children);
 
   // Add children
   for (auto &I : Children)
     ScopeDIE->addChild(std::move(I));
 
-  if (DS.isSubprogram() && ObjectPointer != nullptr)
-    TheCU.addDIEEntry(*ScopeDIE, dwarf::DW_AT_object_pointer, *ObjectPointer);
-
   return ScopeDIE;
 }
 
@@ -630,10 +660,10 @@ DwarfCompileUnit &DwarfDebug::constructDwarfCompileUnit(DICompileUnit DIUnit) {
   StringRef FN = DIUnit.getFilename();
   CompilationDir = DIUnit.getDirectory();
 
-  DIE *Die = new DIE(dwarf::DW_TAG_compile_unit);
   auto OwnedUnit = make_unique<DwarfCompileUnit>(
-      InfoHolder.getUnits().size(), Die, DIUnit, Asm, this, &InfoHolder);
+      InfoHolder.getUnits().size(), DIUnit, Asm, this, &InfoHolder);
   DwarfCompileUnit &NewCU = *OwnedUnit;
+  DIE &Die = NewCU.getUnitDie();
   InfoHolder.addUnit(std::move(OwnedUnit));
 
   // LTO with assembly output shares a single line table amongst multiple CUs.
@@ -644,10 +674,10 @@ DwarfCompileUnit &DwarfDebug::constructDwarfCompileUnit(DICompileUnit DIUnit) {
     Asm->OutStreamer.getContext().setMCLineTableCompilationDir(
         NewCU.getUniqueID(), CompilationDir);
 
-  NewCU.addString(*Die, dwarf::DW_AT_producer, DIUnit.getProducer());
-  NewCU.addUInt(*Die, dwarf::DW_AT_language, dwarf::DW_FORM_data2,
+  NewCU.addString(Die, dwarf::DW_AT_producer, DIUnit.getProducer());
+  NewCU.addUInt(Die, dwarf::DW_AT_language, dwarf::DW_FORM_data2,
                 DIUnit.getLanguage());
-  NewCU.addString(*Die, dwarf::DW_AT_name, FN);
+  NewCU.addString(Die, dwarf::DW_AT_name, FN);
 
   if (!useSplitDwarf()) {
     NewCU.initStmtList(DwarfLineSectionSym);
@@ -655,20 +685,20 @@ DwarfCompileUnit &DwarfDebug::constructDwarfCompileUnit(DICompileUnit DIUnit) {
     // If we're using split dwarf the compilation dir is going to be in the
     // skeleton CU and so we don't need to duplicate it here.
     if (!CompilationDir.empty())
-      NewCU.addString(*Die, dwarf::DW_AT_comp_dir, CompilationDir);
+      NewCU.addString(Die, dwarf::DW_AT_comp_dir, CompilationDir);
 
-    addGnuPubAttributes(NewCU, *Die);
+    addGnuPubAttributes(NewCU, Die);
   }
 
   if (DIUnit.isOptimized())
-    NewCU.addFlag(*Die, dwarf::DW_AT_APPLE_optimized);
+    NewCU.addFlag(Die, dwarf::DW_AT_APPLE_optimized);
 
   StringRef Flags = DIUnit.getFlags();
   if (!Flags.empty())
-    NewCU.addString(*Die, dwarf::DW_AT_APPLE_flags, Flags);
+    NewCU.addString(Die, dwarf::DW_AT_APPLE_flags, Flags);
 
   if (unsigned RVer = DIUnit.getRunTimeVersion())
-    NewCU.addUInt(*Die, dwarf::DW_AT_APPLE_major_runtime_vers,
+    NewCU.addUInt(Die, dwarf::DW_AT_APPLE_major_runtime_vers,
                   dwarf::DW_FORM_data1, RVer);
 
   if (!FirstCU)
@@ -683,7 +713,7 @@ DwarfCompileUnit &DwarfDebug::constructDwarfCompileUnit(DICompileUnit DIUnit) {
                       DwarfInfoSectionSym);
 
   CUMap.insert(std::make_pair(DIUnit, &NewCU));
-  CUDieMap.insert(std::make_pair(Die, &NewCU));
+  CUDieMap.insert(std::make_pair(&Die, &NewCU));
   return NewCU;
 }
 
@@ -716,11 +746,11 @@ void DwarfDebug::constructImportedEntityDIE(DwarfCompileUnit &TheCU,
   DIImportedEntity Module(N);
   assert(Module.Verify());
   if (DIE *D = TheCU.getOrCreateContextDIE(Module.getContext()))
-    constructImportedEntityDIE(TheCU, Module, D);
+    constructImportedEntityDIE(TheCU, Module, *D);
 }
 
 void DwarfDebug::constructImportedEntityDIE(DwarfCompileUnit &TheCU,
-                                            const MDNode *N, DIE *Context) {
+                                            const MDNode *N, DIE &Context) {
   DIImportedEntity Module(N);
   assert(Module.Verify());
   return constructImportedEntityDIE(TheCU, Module, Context);
@@ -728,11 +758,10 @@ void DwarfDebug::constructImportedEntityDIE(DwarfCompileUnit &TheCU,
 
 void DwarfDebug::constructImportedEntityDIE(DwarfCompileUnit &TheCU,
                                             const DIImportedEntity &Module,
-                                            DIE *Context) {
+                                            DIE &Context) {
   assert(Module.Verify() &&
          "Use one of the MDNode * overloads to handle invalid metadata");
-  assert(Context && "Should always have a context for an imported_module");
-  DIE &IMDie = TheCU.createAndAddDIE(Module.getTag(), *Context, Module);
+  DIE &IMDie = TheCU.createAndAddDIE(Module.getTag(), Context, Module);
   DIE *EntityDie;
   DIDescriptor Entity = resolve(Module.getEntity());
   if (Entity.isNameSpace())
@@ -1655,10 +1684,10 @@ void DwarfDebug::endFunction(const MachineFunction *MF) {
       }
     }
     if (ProcessedSPNodes.count(AScope->getScopeNode()) == 0)
-      constructScopeDIE(TheCU, AScope);
+      constructAbstractSubprogramScopeDIE(TheCU, AScope);
   }
 
-  DIE &CurFnDIE = *constructScopeDIE(TheCU, FnScope);
+  DIE &CurFnDIE = constructSubprogramScopeDIE(TheCU, FnScope);
   if (!CurFn->getTarget().Options.DisableFramePointerElim(*CurFn))
     TheCU.addFlag(CurFnDIE, dwarf::DW_AT_APPLE_omit_frame_ptr);
 
@@ -2051,7 +2080,7 @@ void DwarfDebug::emitDebugStr() {
 void DwarfDebug::emitDebugLocEntry(ByteStreamer &Streamer,
                                    const DebugLocEntry &Entry) {
   assert(Entry.getValues().size() == 1 &&
-	 "multi-value entries are not supported yet.");
+         "multi-value entries are not supported yet.");
   const DebugLocEntry::Value Value = Entry.getValues()[0];
   DIVariable DV(Value.getVariable());
   if (Value.isInt()) {
@@ -2185,7 +2214,7 @@ void DwarfDebug::emitDebugARanges() {
   Asm->OutStreamer.SwitchSection(
       Asm->getObjFileLowering().getDwarfARangesSection());
 
-  typedef DenseMap<DwarfCompileUnit *, std::vector<ArangeSpan> > SpansType;
+  typedef DenseMap<DwarfCompileUnit *, std::vector<ArangeSpan>> SpansType;
 
   SpansType Spans;
 
@@ -2334,9 +2363,6 @@ void DwarfDebug::emitDebugRanges() {
   for (const auto &I : CUMap) {
     DwarfCompileUnit *TheCU = I.second;
 
-    // Emit a symbol so we can find the beginning of our ranges.
-    Asm->OutStreamer.EmitLabel(TheCU->getLabelRange());
-
     // Iterate over the misc ranges for the compile units in the module.
     for (const RangeSpanList &List : TheCU->getRangeLists()) {
       // Emit our symbol so we can find the beginning of the range.
@@ -2402,16 +2428,15 @@ void DwarfDebug::initSkeletonUnit(const DwarfUnit &U, DIE &Die,
 // DW_AT_addr_base, DW_AT_ranges_base.
 DwarfCompileUnit &DwarfDebug::constructSkeletonCU(const DwarfCompileUnit &CU) {
 
-  DIE *Die = new DIE(dwarf::DW_TAG_compile_unit);
   auto OwnedUnit = make_unique<DwarfCompileUnit>(
-      CU.getUniqueID(), Die, CU.getCUNode(), Asm, this, &SkeletonHolder);
+      CU.getUniqueID(), CU.getCUNode(), Asm, this, &SkeletonHolder);
   DwarfCompileUnit &NewCU = *OwnedUnit;
   NewCU.initSection(Asm->getObjFileLowering().getDwarfInfoSection(),
                     DwarfInfoSectionSym);
 
   NewCU.initStmtList(DwarfLineSectionSym);
 
-  initSkeletonUnit(CU, *Die, std::move(OwnedUnit));
+  initSkeletonUnit(CU, NewCU.getUnitDie(), std::move(OwnedUnit));
 
   return NewCU;
 }
@@ -2422,16 +2447,15 @@ DwarfTypeUnit &DwarfDebug::constructSkeletonTU(DwarfTypeUnit &TU) {
   DwarfCompileUnit &CU = static_cast<DwarfCompileUnit &>(
       *SkeletonHolder.getUnits()[TU.getCU().getUniqueID()]);
 
-  DIE *Die = new DIE(dwarf::DW_TAG_type_unit);
-  auto OwnedUnit = make_unique<DwarfTypeUnit>(TU.getUniqueID(), Die, CU, Asm,
-                                              this, &SkeletonHolder);
+  auto OwnedUnit = make_unique<DwarfTypeUnit>(TU.getUniqueID(), CU, Asm, this,
+                                              &SkeletonHolder);
   DwarfTypeUnit &NewTU = *OwnedUnit;
   NewTU.setTypeSignature(TU.getTypeSignature());
   NewTU.setType(nullptr);
   NewTU.initSection(
       Asm->getObjFileLowering().getDwarfTypesSection(TU.getTypeSignature()));
 
-  initSkeletonUnit(TU, *Die, std::move(OwnedUnit));
+  initSkeletonUnit(TU, NewTU.getUnitDie(), std::move(OwnedUnit));
   return NewTU;
 }
 
@@ -2441,7 +2465,7 @@ void DwarfDebug::emitDebugInfoDWO() {
   assert(useSplitDwarf() && "No split dwarf debug info?");
   // Don't pass an abbrev symbol, using a constant zero instead so as not to
   // emit relocations into the dwo file.
-  InfoHolder.emitUnits(this, /* AbbrevSymbol */nullptr);
+  InfoHolder.emitUnits(this, /* AbbrevSymbol */ nullptr);
 }
 
 // Emit the .debug_abbrev.dwo section for separated dwarf. This contains the
@@ -2507,22 +2531,23 @@ void DwarfDebug::addDwarfTypeUnitType(DwarfCompileUnit &CU,
   bool TopLevelType = TypeUnitsUnderConstruction.empty();
   AddrPool.resetUsedFlag();
 
-  DIE *UnitDie = new DIE(dwarf::DW_TAG_type_unit);
   auto OwnedUnit =
-      make_unique<DwarfTypeUnit>(InfoHolder.getUnits().size(), UnitDie, CU, Asm,
-                                 this, &InfoHolder, getDwoLineTable(CU));
+      make_unique<DwarfTypeUnit>(InfoHolder.getUnits().size(), CU, Asm, this,
+                                 &InfoHolder, getDwoLineTable(CU));
   DwarfTypeUnit &NewTU = *OwnedUnit;
+  DIE &UnitDie = NewTU.getUnitDie();
   TU = &NewTU;
-  TypeUnitsUnderConstruction.push_back(std::make_pair(std::move(OwnedUnit), CTy));
+  TypeUnitsUnderConstruction.push_back(
+      std::make_pair(std::move(OwnedUnit), CTy));
 
-  NewTU.addUInt(*UnitDie, dwarf::DW_AT_language, dwarf::DW_FORM_data2,
+  NewTU.addUInt(UnitDie, dwarf::DW_AT_language, dwarf::DW_FORM_data2,
                 CU.getLanguage());
 
   uint64_t Signature = makeTypeSignature(Identifier);
   NewTU.setTypeSignature(Signature);
 
   if (!useSplitDwarf())
-    CU.applyStmtList(*UnitDie);
+    CU.applyStmtList(UnitDie);
 
   NewTU.initSection(
       useSplitDwarf()
diff --git a/lib/CodeGen/AsmPrinter/DwarfDebug.h b/lib/CodeGen/AsmPrinter/DwarfDebug.h
index 1c4903c948..b5b07aee11 100644
--- a/lib/CodeGen/AsmPrinter/DwarfDebug.h
+++ b/lib/CodeGen/AsmPrinter/DwarfDebug.h
@@ -346,7 +346,7 @@ class DwarfDebug : public AsmPrinterHandler {
   /// DW_AT_low_pc and DW_AT_high_pc attributes. If there are global
   /// variables in this scope then create and insert DIEs for these
   /// variables.
-  DIE *updateSubprogramScopeDIE(DwarfCompileUnit &SPCU, DISubprogram SP);
+  DIE &updateSubprogramScopeDIE(DwarfCompileUnit &SPCU, DISubprogram SP);
 
   /// \brief A helper function to check whether the DIE for a given Scope is
   /// going to be null.
@@ -359,14 +359,25 @@ class DwarfDebug : public AsmPrinterHandler {
 
   /// \brief Construct new DW_TAG_lexical_block for this scope and
   /// attach DW_AT_low_pc/DW_AT_high_pc labels.
-  DIE *constructLexicalScopeDIE(DwarfCompileUnit &TheCU, LexicalScope *Scope);
+  std::unique_ptr<DIE> constructLexicalScopeDIE(DwarfCompileUnit &TheCU,
+                                                LexicalScope *Scope);
 
   /// \brief This scope represents inlined body of a function. Construct
   /// DIE to represent this concrete inlined copy of the function.
-  DIE *constructInlinedScopeDIE(DwarfCompileUnit &TheCU, LexicalScope *Scope);
+  std::unique_ptr<DIE> constructInlinedScopeDIE(DwarfCompileUnit &TheCU,
+                                                LexicalScope *Scope);
 
   /// \brief Construct a DIE for this scope.
-  DIE *constructScopeDIE(DwarfCompileUnit &TheCU, LexicalScope *Scope);
+  std::unique_ptr<DIE> constructScopeDIE(DwarfCompileUnit &TheCU,
+                                         LexicalScope *Scope);
+  void createAndAddScopeChildren(DwarfCompileUnit &TheCU, LexicalScope *Scope,
+                                 DIE &ScopeDIE);
+  /// \brief Construct a DIE for this abstract scope.
+  void constructAbstractSubprogramScopeDIE(DwarfCompileUnit &TheCU,
+                                           LexicalScope *Scope);
+  /// \brief Construct a DIE for this subprogram scope.
+  DIE &constructSubprogramScopeDIE(DwarfCompileUnit &TheCU,
+                                   LexicalScope *Scope);
   /// A helper function to create children of a Scope DIE.
   DIE *createScopeChildrenDIE(DwarfCompileUnit &TheCU, LexicalScope *Scope,
                               SmallVectorImpl<std::unique_ptr<DIE>> &Children);
@@ -494,11 +505,11 @@ class DwarfDebug : public AsmPrinterHandler {
 
   /// \brief Construct import_module DIE.
   void constructImportedEntityDIE(DwarfCompileUnit &TheCU, const MDNode *N,
-                                  DIE *Context);
+                                  DIE &Context);
 
   /// \brief Construct import_module DIE.
   void constructImportedEntityDIE(DwarfCompileUnit &TheCU,
-                                  const DIImportedEntity &Module, DIE *Context);
+                                  const DIImportedEntity &Module, DIE &Context);
 
   /// \brief Register a source line with debug info. Returns the unique
   /// label that was emitted and which provides correspondence to the
diff --git a/lib/CodeGen/AsmPrinter/DwarfUnit.cpp b/lib/CodeGen/AsmPrinter/DwarfUnit.cpp
index f3cd80027d..4210a55459 100644
--- a/lib/CodeGen/AsmPrinter/DwarfUnit.cpp
+++ b/lib/CodeGen/AsmPrinter/DwarfUnit.cpp
@@ -41,28 +41,30 @@ GenerateDwarfTypeUnits("generate-type-units", cl::Hidden,
                        cl::init(false));
 
 /// Unit - Unit constructor.
-DwarfUnit::DwarfUnit(unsigned UID, DIE *D, DICompileUnit Node, AsmPrinter *A,
-                     DwarfDebug *DW, DwarfFile *DWU)
-    : UniqueID(UID), CUNode(Node), UnitDie(D), DebugInfoOffset(0), Asm(A),
+DwarfUnit::DwarfUnit(unsigned UID, dwarf::Tag UnitTag, DICompileUnit Node,
+                     AsmPrinter *A, DwarfDebug *DW, DwarfFile *DWU)
+    : UniqueID(UID), CUNode(Node), UnitDie(UnitTag), DebugInfoOffset(0), Asm(A),
       DD(DW), DU(DWU), IndexTyDie(nullptr), Section(nullptr),
       Skeleton(nullptr) {
+  assert(UnitTag == dwarf::DW_TAG_compile_unit ||
+         UnitTag == dwarf::DW_TAG_type_unit);
   DIEIntegerOne = new (DIEValueAllocator) DIEInteger(1);
 }
 
-DwarfCompileUnit::DwarfCompileUnit(unsigned UID, DIE *D, DICompileUnit Node,
+DwarfCompileUnit::DwarfCompileUnit(unsigned UID, DICompileUnit Node,
                                    AsmPrinter *A, DwarfDebug *DW,
                                    DwarfFile *DWU)
-    : DwarfUnit(UID, D, Node, A, DW, DWU) {
-  insertDIE(Node, D);
+    : DwarfUnit(UID, dwarf::DW_TAG_compile_unit, Node, A, DW, DWU) {
+  insertDIE(Node, &getUnitDie());
 }
 
-DwarfTypeUnit::DwarfTypeUnit(unsigned UID, DIE *D, DwarfCompileUnit &CU,
-                             AsmPrinter *A, DwarfDebug *DW, DwarfFile *DWU,
+DwarfTypeUnit::DwarfTypeUnit(unsigned UID, DwarfCompileUnit &CU, AsmPrinter *A,
+                             DwarfDebug *DW, DwarfFile *DWU,
                              MCDwarfDwoLineTable *SplitLineTable)
-    : DwarfUnit(UID, D, CU.getCUNode(), A, DW, DWU), CU(CU),
-      SplitLineTable(SplitLineTable) {
+    : DwarfUnit(UID, dwarf::DW_TAG_type_unit, CU.getCUNode(), A, DW, DWU),
+      CU(CU), SplitLineTable(SplitLineTable) {
   if (SplitLineTable)
-    addSectionOffset(*UnitDie, dwarf::DW_AT_stmt_list, 0);
+    addSectionOffset(UnitDie, dwarf::DW_AT_stmt_list, 0);
 }
 
 /// ~Unit - Destructor for compile unit.
@@ -1423,7 +1425,7 @@ DIE *DwarfUnit::getOrCreateSubprogramDIE(DISubprogram SP) {
   DISubprogram SPDecl = SP.getFunctionDeclaration();
   if (SPDecl.isSubprogram())
     // Add subprogram definitions to the CU die directly.
-    ContextDIE = UnitDie.get();
+    ContextDIE = &getUnitDie();
 
   // DW_TAG_inlined_subroutine may refer to this DIE.
   DIE &SPDie = createAndAddDIE(dwarf::DW_TAG_subprogram, *ContextDIE, SP);
@@ -1643,7 +1645,7 @@ void DwarfCompileUnit::createGlobalVariableDIE(DIGlobalVariable GV) {
     if (GVContext && GV.isDefinition() && !GVContext.isCompileUnit() &&
         !GVContext.isFile() && !DD->isSubprogramContext(GVContext)) {
       // Create specification DIE.
-      VariableSpecDIE = &createAndAddDIE(dwarf::DW_TAG_variable, *UnitDie);
+      VariableSpecDIE = &createAndAddDIE(dwarf::DW_TAG_variable, UnitDie);
       addDIEEntry(*VariableSpecDIE, dwarf::DW_AT_specification, *VariableDIE);
       addBlock(*VariableSpecDIE, dwarf::DW_AT_location, Loc);
       // A static member's declaration is already flagged as such.
@@ -1741,7 +1743,7 @@ void DwarfUnit::constructArrayTypeDIE(DIE &Buffer, DICompositeType CTy) {
   DIE *IdxTy = getIndexTyDie();
   if (!IdxTy) {
     // Construct an integer type to use for indexes.
-    IdxTy = &createAndAddDIE(dwarf::DW_TAG_base_type, *UnitDie);
+    IdxTy = &createAndAddDIE(dwarf::DW_TAG_base_type, UnitDie);
     addString(*IdxTy, dwarf::DW_AT_name, "sizetype");
     addUInt(*IdxTy, dwarf::DW_AT_byte_size, None, sizeof(int64_t));
     addUInt(*IdxTy, dwarf::DW_AT_encoding, dwarf::DW_FORM_data1,
@@ -2048,7 +2050,7 @@ void DwarfCompileUnit::initStmtList(MCSymbol *DwarfLineSectionSym) {
   MCSymbol *LineTableStartSym =
       Asm->OutStreamer.getDwarfLineTableSymbol(getUniqueID());
 
-  stmtListIndex = UnitDie->getValues().size();
+  stmtListIndex = UnitDie.getValues().size();
 
   // DW_AT_stmt_list is a offset of line number information for this
   // compile unit in debug_line section. For split dwarf this is
@@ -2056,16 +2058,16 @@ void DwarfCompileUnit::initStmtList(MCSymbol *DwarfLineSectionSym) {
   // The line table entries are not always emitted in assembly, so it
   // is not okay to use line_table_start here.
   if (Asm->MAI->doesDwarfUseRelocationsAcrossSections())
-    addSectionLabel(*UnitDie, dwarf::DW_AT_stmt_list, LineTableStartSym);
+    addSectionLabel(UnitDie, dwarf::DW_AT_stmt_list, LineTableStartSym);
   else
-    addSectionDelta(*UnitDie, dwarf::DW_AT_stmt_list, LineTableStartSym,
+    addSectionDelta(UnitDie, dwarf::DW_AT_stmt_list, LineTableStartSym,
                     DwarfLineSectionSym);
 }
 
 void DwarfCompileUnit::applyStmtList(DIE &D) {
   D.addValue(dwarf::DW_AT_stmt_list,
-             UnitDie->getAbbrev().getData()[stmtListIndex].getForm(),
-             UnitDie->getValues()[stmtListIndex]);
+             UnitDie.getAbbrev().getData()[stmtListIndex].getForm(),
+             UnitDie.getValues()[stmtListIndex]);
 }
 
 void DwarfTypeUnit::emitHeader(const MCSymbol *ASectionSym) const {
@@ -2090,5 +2092,4 @@ void DwarfTypeUnit::initSection(const MCSection *Section) {
       Asm->GetTempSymbol(Section->getLabelBeginName(), getUniqueID());
   this->LabelEnd =
       Asm->GetTempSymbol(Section->getLabelEndName(), getUniqueID());
-  this->LabelRange = Asm->GetTempSymbol("gnu_ranges", getUniqueID());
 }
diff --git a/lib/CodeGen/AsmPrinter/DwarfUnit.h b/lib/CodeGen/AsmPrinter/DwarfUnit.h
index 69774f551b..5ce6595c88 100644
--- a/lib/CodeGen/AsmPrinter/DwarfUnit.h
+++ b/lib/CodeGen/AsmPrinter/DwarfUnit.h
@@ -73,7 +73,7 @@ protected:
   DICompileUnit CUNode;
 
   /// Unit debug information entry.
-  const std::unique_ptr<DIE> UnitDie;
+  DIE UnitDie;
 
   /// Offset of the UnitDie from beginning of debug info section.
   unsigned DebugInfoOffset;
@@ -138,13 +138,10 @@ protected:
   /// The end of the unit within its section.
   MCSymbol *LabelEnd;
 
-  /// The label for the start of the range sets for the elements of this unit.
-  MCSymbol *LabelRange;
-
   /// Skeleton unit associated with this unit.
   DwarfUnit *Skeleton;
 
-  DwarfUnit(unsigned UID, DIE *D, DICompileUnit CU, AsmPrinter *A,
+  DwarfUnit(unsigned UID, dwarf::Tag, DICompileUnit CU, AsmPrinter *A,
             DwarfDebug *DW, DwarfFile *DWU);
 
 public:
@@ -167,7 +164,6 @@ public:
         Asm->GetTempSymbol(Section->getLabelBeginName(), getUniqueID());
     this->LabelEnd =
         Asm->GetTempSymbol(Section->getLabelEndName(), getUniqueID());
-    this->LabelRange = Asm->GetTempSymbol("gnu_ranges", getUniqueID());
   }
 
   const MCSection *getSection() const {
@@ -206,16 +202,11 @@ public:
     return LabelEnd;
   }
 
-  MCSymbol *getLabelRange() const {
-    assert(Section);
-    return LabelRange;
-  }
-
   // Accessors.
   unsigned getUniqueID() const { return UniqueID; }
   uint16_t getLanguage() const { return CUNode.getLanguage(); }
   DICompileUnit getCUNode() const { return CUNode; }
-  DIE &getUnitDie() const { return *UnitDie; }
+  DIE &getUnitDie() { return UnitDie; }
   const StringMap<const DIE *> &getGlobalNames() const { return GlobalNames; }
   const StringMap<const DIE *> &getGlobalTypes() const { return GlobalTypes; }
 
@@ -223,7 +214,7 @@ public:
   void setDebugInfoOffset(unsigned DbgInfoOff) { DebugInfoOffset = DbgInfoOff; }
 
   /// hasContent - Return true if this compile unit has something to write out.
-  bool hasContent() const { return !UnitDie->getChildren().empty(); }
+  bool hasContent() const { return !UnitDie.getChildren().empty(); }
 
   /// addRange - Add an address range to the list of ranges for this unit.
   void addRange(RangeSpan Range);
@@ -533,7 +524,7 @@ class DwarfCompileUnit : public DwarfUnit {
   unsigned stmtListIndex;
 
 public:
-  DwarfCompileUnit(unsigned UID, DIE *D, DICompileUnit Node, AsmPrinter *A,
+  DwarfCompileUnit(unsigned UID, DICompileUnit Node, AsmPrinter *A,
                    DwarfDebug *DW, DwarfFile *DWU);
 
   void initStmtList(MCSymbol *DwarfLineSectionSym);
@@ -567,7 +558,7 @@ private:
   MCDwarfDwoLineTable *SplitLineTable;
 
 public:
-  DwarfTypeUnit(unsigned UID, DIE *D, DwarfCompileUnit &CU, AsmPrinter *A,
+  DwarfTypeUnit(unsigned UID, DwarfCompileUnit &CU, AsmPrinter *A,
                 DwarfDebug *DW, DwarfFile *DWU,
                 MCDwarfDwoLineTable *SplitLineTable = nullptr);
 
diff --git a/lib/CodeGen/MachineScheduler.cpp b/lib/CodeGen/MachineScheduler.cpp
index 26d16cddc9..23847d6a75 100644
--- a/lib/CodeGen/MachineScheduler.cpp
+++ b/lib/CodeGen/MachineScheduler.cpp
@@ -3347,7 +3347,7 @@ public:
   InstructionShuffler(bool alternate, bool topdown)
     : IsAlternating(alternate), IsTopDown(topdown) {}
 
-  virtual void initialize(ScheduleDAGMI*) {
+  void initialize(ScheduleDAGMI*) override {
     TopQ.clear();
     BottomQ.clear();
   }
@@ -3355,7 +3355,7 @@ public:
   /// Implement MachineSchedStrategy interface.
   /// -----------------------------------------
 
-  virtual SUnit *pickNode(bool &IsTopNode) {
+  SUnit *pickNode(bool &IsTopNode) override {
     SUnit *SU;
     if (IsTopDown) {
       do {
@@ -3378,12 +3378,12 @@ public:
     return SU;
   }
 
-  virtual void schedNode(SUnit *SU, bool IsTopNode) {}
+  void schedNode(SUnit *SU, bool IsTopNode) override {}
 
-  virtual void releaseTopNode(SUnit *SU) {
+  void releaseTopNode(SUnit *SU) override {
     TopQ.push(SU);
   }
-  virtual void releaseBottomNode(SUnit *SU) {
+  void releaseBottomNode(SUnit *SU) override {
     BottomQ.push(SU);
   }
 };
diff --git a/lib/CodeGen/MachineVerifier.cpp b/lib/CodeGen/MachineVerifier.cpp
index e218a274d0..37d476b2c0 100644
--- a/lib/CodeGen/MachineVerifier.cpp
+++ b/lib/CodeGen/MachineVerifier.cpp
@@ -42,6 +42,7 @@
 #include "llvm/MC/MCAsmInfo.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/ErrorHandling.h"
+#include "llvm/Support/FileSystem.h"
 #include "llvm/Support/raw_ostream.h"
 #include "llvm/Target/TargetInstrInfo.h"
 #include "llvm/Target/TargetMachine.h"
diff --git a/lib/CodeGen/RegAllocPBQP.cpp b/lib/CodeGen/RegAllocPBQP.cpp
index 9f8b401a81..323368bd3e 100644
--- a/lib/CodeGen/RegAllocPBQP.cpp
+++ b/lib/CodeGen/RegAllocPBQP.cpp
@@ -46,6 +46,7 @@
 #include "llvm/CodeGen/VirtRegMap.h"
 #include "llvm/IR/Module.h"
 #include "llvm/Support/Debug.h"
+#include "llvm/Support/FileSystem.h"
 #include "llvm/Support/raw_ostream.h"
 #include "llvm/Target/TargetInstrInfo.h"
 #include "llvm/Target/TargetMachine.h"
diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 7f156537cb..014e97d7b2 100644
--- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -2511,7 +2511,7 @@ SDValue DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) {
 
     assert(N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType() &&
            "Inputs to shuffles are not the same type");
- 
+
     // Check that both shuffles use the same mask. The masks are known to be of
     // the same length because the result vector type is the same.
     // Check also that shuffles have only one use to avoid introducing extra
@@ -3249,11 +3249,11 @@ SDValue DAGCombiner::visitOR(SDNode *N) {
       // two ways to fold this node into a shuffle.
       SmallVector<int,4> Mask1;
       SmallVector<int,4> Mask2;
-      
+
       for (unsigned i = 0; i != NumElts && CanFold; ++i) {
         int M0 = SV0->getMaskElt(i);
         int M1 = SV1->getMaskElt(i);
-   
+
         // Both shuffle indexes are undef. Propagate Undef.
         if (M0 < 0 && M1 < 0) {
           Mask1.push_back(M0);
@@ -3267,7 +3267,7 @@ SDValue DAGCombiner::visitOR(SDNode *N) {
           CanFold = false;
           break;
         }
-        
+
         Mask1.push_back(M0 < (int)NumElts ? M0 : M1 + NumElts);
         Mask2.push_back(M1 < (int)NumElts ? M1 : M0 + NumElts);
       }
@@ -4703,7 +4703,7 @@ SDValue DAGCombiner::visitSETCC(SDNode *N) {
 // tryToFoldExtendOfConstant - Try to fold a sext/zext/aext
 // dag node into a ConstantSDNode or a build_vector of constants.
 // This function is called by the DAGCombiner when visiting sext/zext/aext
-// dag nodes (see for example method DAGCombiner::visitSIGN_EXTEND). 
+// dag nodes (see for example method DAGCombiner::visitSIGN_EXTEND).
 // Vector extends are not folded if operations are legal; this is to
 // avoid introducing illegal build_vector dag nodes.
 static SDNode *tryToFoldExtendOfConstant(SDNode *N, const TargetLowering &TLI,
@@ -4730,7 +4730,7 @@ static SDNode *tryToFoldExtendOfConstant(SDNode *N, const TargetLowering &TLI,
       (!LegalTypes || (!LegalOperations && TLI.isTypeLegal(SVT))) &&
       ISD::isBuildVectorOfConstantSDNodes(N0.getNode())))
     return nullptr;
-  
+
   // We can fold this node into a build_vector.
   unsigned VTBits = SVT.getSizeInBits();
   unsigned EVTBits = N0->getValueType(0).getScalarType().getSizeInBits();
@@ -10125,7 +10125,7 @@ SDValue DAGCombiner::visitBUILD_VECTOR(SDNode *N) {
     }
   }
 
-    // If everything is good, we can make a shuffle operation.
+  // If everything is good, we can make a shuffle operation.
   if (VecIn1.getNode()) {
     SmallVector<int, 8> Mask;
     for (unsigned i = 0; i != NumInScalars; ++i) {
diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
index 7e4958ef80..dac372fcea 100644
--- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -3711,8 +3711,7 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node) {
       BottomHalf = DAG.getNode(Ops[isSigned][1], dl, DAG.getVTList(VT, VT), LHS,
                                RHS);
       TopHalf = BottomHalf.getValue(1);
-    } else if (TLI.isTypeLegal(EVT::getIntegerVT(*DAG.getContext(),
-                                                 VT.getSizeInBits() * 2))) {
+    } else if (TLI.isTypeLegal(WideVT)) {
       LHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, LHS);
       RHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, RHS);
       Tmp1 = DAG.getNode(ISD::MUL, dl, WideVT, LHS, RHS);
diff --git a/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp b/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
index 78aaaec34d..0d943efc04 100644
--- a/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
@@ -1563,7 +1563,7 @@ void DAGTypeLegalizer::ExpandIntRes_ADDSUB(SDNode *N,
 
   if (N->getOpcode() == ISD::ADD) {
     Lo = DAG.getNode(ISD::ADD, dl, NVT, LoOps);
-    Hi = DAG.getNode(ISD::ADD, dl, NVT, ArrayRef<SDValue>(HiOps, 2));
+    Hi = DAG.getNode(ISD::ADD, dl, NVT, makeArrayRef(HiOps, 2));
     SDValue Cmp1 = DAG.getSetCC(dl, getSetCCResultType(NVT), Lo, LoOps[0],
                                 ISD::SETULT);
     SDValue Carry1 = DAG.getSelect(dl, NVT, Cmp1,
@@ -1576,7 +1576,7 @@ void DAGTypeLegalizer::ExpandIntRes_ADDSUB(SDNode *N,
     Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, Carry2);
   } else {
     Lo = DAG.getNode(ISD::SUB, dl, NVT, LoOps);
-    Hi = DAG.getNode(ISD::SUB, dl, NVT, ArrayRef<SDValue>(HiOps, 2));
+    Hi = DAG.getNode(ISD::SUB, dl, NVT, makeArrayRef(HiOps, 2));
     SDValue Cmp =
       DAG.getSetCC(dl, getSetCCResultType(LoOps[0].getValueType()),
                    LoOps[0], LoOps[1], ISD::SETULT);
diff --git a/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp b/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp
index d0539e460d..f40ed76b01 100644
--- a/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp
@@ -355,7 +355,7 @@ SDValue DAGTypeLegalizer::ExpandOp_BITCAST(SDNode *N) {
     IntegerToVector(N->getOperand(0), NumElts, Ops, NVT.getVectorElementType());
 
     SDValue Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT,
-                              ArrayRef<SDValue>(&Ops[0], NumElts));
+                              makeArrayRef(Ops.data(), NumElts));
     return DAG.getNode(ISD::BITCAST, dl, N->getValueType(0), Vec);
   }
 
diff --git a/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp b/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
index b249dbacd9..368eba3966 100644
--- a/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
@@ -1745,7 +1745,7 @@ SDValue DAGTypeLegalizer::WidenVecRes_BinaryCanTrap(SDNode *N) {
       ConcatOps[j] = UndefVal;
   }
   return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT,
-                     ArrayRef<SDValue>(&ConcatOps[0], NumOps));
+                     makeArrayRef(ConcatOps.data(), NumOps));
 }
 
 SDValue DAGTypeLegalizer::WidenVecRes_Convert(SDNode *N) {
@@ -2724,8 +2724,7 @@ SDValue DAGTypeLegalizer::GenWidenVectorLoads(SmallVectorImpl<SDValue> &LdChain,
     if (NewLdTy != LdTy) {
       // Create a larger vector
       ConcatOps[End-1] = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewLdTy,
-                                     ArrayRef<SDValue>(&ConcatOps[Idx],
-                                                       End - Idx));
+                                     makeArrayRef(&ConcatOps[Idx], End - Idx));
       Idx = End - 1;
       LdTy = NewLdTy;
     }
@@ -2734,7 +2733,7 @@ SDValue DAGTypeLegalizer::GenWidenVectorLoads(SmallVectorImpl<SDValue> &LdChain,
 
   if (WidenWidth == LdTy.getSizeInBits()*(End - Idx))
     return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT,
-                       ArrayRef<SDValue>(&ConcatOps[Idx], End - Idx));
+                       makeArrayRef(&ConcatOps[Idx], End - Idx));
 
   // We need to fill the rest with undefs to build the vector
   unsigned NumOps = WidenWidth / LdTy.getSizeInBits();
diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
index cfa0858ce7..78ec4df95f 100644
--- a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
@@ -1784,7 +1784,7 @@ public:
   }
 
 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
-  void dump(ScheduleDAG *DAG) const {
+  void dump(ScheduleDAG *DAG) const override {
     // Emulate pop() without clobbering NodeQueueIds.
     std::vector<SUnit*> DumpQueue = Queue;
     SF DumpPicker = Picker;
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index c545bcca07..bf311226cd 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -527,7 +527,7 @@ static void AddNodeIDNode(FoldingSetNodeID &ID, const SDNode *N) {
   // Add the return value info.
   AddNodeIDValueTypes(ID, N->getVTList());
   // Add the operand info.
-  AddNodeIDOperands(ID, ArrayRef<SDUse>(N->op_begin(), N->op_end()));
+  AddNodeIDOperands(ID, makeArrayRef(N->op_begin(), N->op_end()));
 
   // Handle SDNode leafs with special info.
   AddNodeIDCustom(ID, N);
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
index acd5c16dbb..1cc6105e98 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -3480,7 +3480,7 @@ void SelectionDAGBuilder::visitLoad(const LoadInst &I) {
     if (ChainI == MaxParallelChains) {
       assert(PendingLoads.empty() && "PendingLoads must be serialized first");
       SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
-                                  ArrayRef<SDValue>(Chains.data(), ChainI));
+                                  makeArrayRef(Chains.data(), ChainI));
       Root = Chain;
       ChainI = 0;
     }
@@ -3498,7 +3498,7 @@ void SelectionDAGBuilder::visitLoad(const LoadInst &I) {
 
   if (!ConstantMemory) {
     SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
-                                ArrayRef<SDValue>(Chains.data(), ChainI));
+                                makeArrayRef(Chains.data(), ChainI));
     if (isVolatile)
       DAG.setRoot(Chain);
     else
@@ -3543,7 +3543,7 @@ void SelectionDAGBuilder::visitStore(const StoreInst &I) {
     // See visitLoad comments.
     if (ChainI == MaxParallelChains) {
       SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
-                                  ArrayRef<SDValue>(Chains.data(), ChainI));
+                                  makeArrayRef(Chains.data(), ChainI));
       Root = Chain;
       ChainI = 0;
     }
@@ -3557,7 +3557,7 @@ void SelectionDAGBuilder::visitStore(const StoreInst &I) {
   }
 
   SDValue StoreNode = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
-                                  ArrayRef<SDValue>(Chains.data(), ChainI));
+                                  makeArrayRef(Chains.data(), ChainI));
   DAG.setRoot(StoreNode);
 }
 
@@ -7496,8 +7496,7 @@ void SelectionDAGISel::LowerArguments(const Function &F) {
         dyn_cast<FrameIndexSDNode>(ArgValues[0].getNode()))
       FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
 
-    SDValue Res = DAG.getMergeValues(ArrayRef<SDValue>(ArgValues.data(),
-                                                       NumValues),
+    SDValue Res = DAG.getMergeValues(makeArrayRef(ArgValues.data(), NumValues),
                                      SDB->getCurSDLoc());
 
     SDB->setValue(I, Res);
diff --git a/lib/DebugInfo/DWARFContext.cpp b/lib/DebugInfo/DWARFContext.cpp
index 08b7b91637..3d04e73903 100644
--- a/lib/DebugInfo/DWARFContext.cpp
+++ b/lib/DebugInfo/DWARFContext.cpp
@@ -130,8 +130,9 @@ void DWARFContext::dump(raw_ostream &OS, DIDumpType DumpType) {
       if (stmtOffset != -1U) {
         DataExtractor lineData(getLineSection().Data, isLittleEndian(),
                                savedAddressByteSize);
-        DWARFDebugLine::DumpingState state(OS);
-        DWARFDebugLine::parseStatementTable(lineData, &getLineSection().Relocs, &stmtOffset, state);
+        DWARFDebugLine::LineTable LineTable;
+        LineTable.parse(lineData, &getLineSection().Relocs, &stmtOffset);
+        LineTable.dump(OS);
       }
     }
   }
@@ -141,9 +142,11 @@ void DWARFContext::dump(raw_ostream &OS, DIDumpType DumpType) {
     unsigned stmtOffset = 0;
     DataExtractor lineData(getLineDWOSection().Data, isLittleEndian(),
                            savedAddressByteSize);
-    DWARFDebugLine::DumpingState state(OS);
-    while (DWARFDebugLine::parsePrologue(lineData, &stmtOffset, &state.Prologue))
-      state.finalize();
+    DWARFDebugLine::LineTable LineTable;
+    while (LineTable.Prologue.parse(lineData, &stmtOffset)) {
+      LineTable.dump(OS);
+      LineTable.clear();
+    }
   }
 
   if (DumpType == DIDT_All || DumpType == DIDT_Str) {
diff --git a/lib/DebugInfo/DWARFDebugArangeSet.h b/lib/DebugInfo/DWARFDebugArangeSet.h
index c18b3c5e50..d6c2d8b27c 100644
--- a/lib/DebugInfo/DWARFDebugArangeSet.h
+++ b/lib/DebugInfo/DWARFDebugArangeSet.h
@@ -63,7 +63,6 @@ public:
     return desc_iterator_range(ArangeDescriptors.begin(),
                                ArangeDescriptors.end());
   }
-  uint32_t getNumDescriptors() const { return ArangeDescriptors.size(); }
 };
 
 }
diff --git a/lib/DebugInfo/DWARFDebugAranges.cpp b/lib/DebugInfo/DWARFDebugAranges.cpp
index 4d7bf306f6..2524adc25c 100644
--- a/lib/DebugInfo/DWARFDebugAranges.cpp
+++ b/lib/DebugInfo/DWARFDebugAranges.cpp
@@ -21,23 +21,11 @@ void DWARFDebugAranges::extract(DataExtractor DebugArangesData) {
   if (!DebugArangesData.isValidOffset(0))
     return;
   uint32_t Offset = 0;
-  typedef std::vector<DWARFDebugArangeSet> RangeSetColl;
-  RangeSetColl Sets;
   DWARFDebugArangeSet Set;
-  uint32_t TotalRanges = 0;
 
   while (Set.extract(DebugArangesData, &Offset)) {
-    Sets.push_back(Set);
-    TotalRanges += Set.getNumDescriptors();
-  }
-  if (TotalRanges == 0)
-    return;
-
-  Aranges.reserve(TotalRanges);
-  for (const auto &I : Sets) {
-    uint32_t CUOffset = I.getCompileUnitDIEOffset();
-
-    for (const auto &Desc : I.descriptors()) {
+    uint32_t CUOffset = Set.getCompileUnitDIEOffset();
+    for (const auto &Desc : Set.descriptors()) {
       uint64_t LowPC = Desc.Address;
       uint64_t HighPC = Desc.getEndAddress();
       appendRange(CUOffset, LowPC, HighPC);
@@ -112,11 +100,6 @@ void DWARFDebugAranges::sortAndMinimize() {
       ++minimal_size;
   }
 
-  // If the sizes are the same, then no consecutive aranges can be
-  // combined, we are done.
-  if (minimal_size == orig_arange_size)
-    return;
-
   // Else, make a new RangeColl that _only_ contains what we need.
   RangeColl minimal_aranges;
   minimal_aranges.resize(minimal_size);
diff --git a/lib/DebugInfo/DWARFDebugFrame.cpp b/lib/DebugInfo/DWARFDebugFrame.cpp
index 425c47cbf0..a33548e95b 100644
--- a/lib/DebugInfo/DWARFDebugFrame.cpp
+++ b/lib/DebugInfo/DWARFDebugFrame.cpp
@@ -26,8 +26,8 @@ using namespace dwarf;
 class llvm::FrameEntry {
 public:
   enum FrameKind {FK_CIE, FK_FDE};
-  FrameEntry(FrameKind K, DataExtractor D, uint64_t Offset, uint64_t Length)
-    : Kind(K), Data(D), Offset(Offset), Length(Length) {}
+  FrameEntry(FrameKind K, uint64_t Offset, uint64_t Length)
+      : Kind(K), Offset(Offset), Length(Length) {}
 
   virtual ~FrameEntry() {
   }
@@ -35,11 +35,12 @@ public:
   FrameKind getKind() const { return Kind; }
   virtual uint64_t getOffset() const { return Offset; }
 
-  /// \brief Parse and store a sequence of CFI instructions from our data
-  /// stream, starting at *Offset and ending at EndOffset. If everything
+  /// \brief Parse and store a sequence of CFI instructions from Data,
+  /// starting at *Offset and ending at EndOffset. If everything
   /// goes well, *Offset should be equal to EndOffset when this method
   /// returns. Otherwise, an error occurred.
-  virtual void parseInstructions(uint32_t *Offset, uint32_t EndOffset);
+  virtual void parseInstructions(DataExtractor Data, uint32_t *Offset,
+                                 uint32_t EndOffset);
 
   /// \brief Dump the entry header to the given output stream.
   virtual void dumpHeader(raw_ostream &OS) const = 0;
@@ -50,10 +51,6 @@ public:
 protected:
   const FrameKind Kind;
 
-  /// \brief The data stream holding the section from which the entry was
-  /// parsed.
-  DataExtractor Data;
-
   /// \brief Offset of this entry in the section.
   uint64_t Offset;
 
@@ -97,8 +94,8 @@ protected:
 const uint8_t DWARF_CFI_PRIMARY_OPCODE_MASK = 0xc0;
 const uint8_t DWARF_CFI_PRIMARY_OPERAND_MASK = 0x3f;
 
-
-void FrameEntry::parseInstructions(uint32_t *Offset, uint32_t EndOffset) {
+void FrameEntry::parseInstructions(DataExtractor Data, uint32_t *Offset,
+                                   uint32_t EndOffset) {
   while (*Offset < EndOffset) {
     uint8_t Opcode = Data.getU8(Offset);
     // Some instructions have a primary opcode encoded in the top bits.
@@ -201,13 +198,13 @@ class CIE : public FrameEntry {
 public:
   // CIEs (and FDEs) are simply container classes, so the only sensible way to
   // create them is by providing the full parsed contents in the constructor.
-  CIE(DataExtractor D, uint64_t Offset, uint64_t Length, uint8_t Version,
+  CIE(uint64_t Offset, uint64_t Length, uint8_t Version,
       SmallString<8> Augmentation, uint64_t CodeAlignmentFactor,
       int64_t DataAlignmentFactor, uint64_t ReturnAddressRegister)
-   : FrameEntry(FK_CIE, D, Offset, Length), Version(Version),
-     Augmentation(Augmentation), CodeAlignmentFactor(CodeAlignmentFactor),
-     DataAlignmentFactor(DataAlignmentFactor),
-     ReturnAddressRegister(ReturnAddressRegister) {}
+      : FrameEntry(FK_CIE, Offset, Length), Version(Version),
+        Augmentation(Augmentation), CodeAlignmentFactor(CodeAlignmentFactor),
+        DataAlignmentFactor(DataAlignmentFactor),
+        ReturnAddressRegister(ReturnAddressRegister) {}
 
   ~CIE() {
   }
@@ -229,7 +226,7 @@ public:
 
   static bool classof(const FrameEntry *FE) {
     return FE->getKind() == FK_CIE;
-  } 
+  }
 
 private:
   /// The following fields are defined in section 6.4.1 of the DWARF standard v3
@@ -247,11 +244,11 @@ public:
   // Each FDE has a CIE it's "linked to". Our FDE contains is constructed with
   // an offset to the CIE (provided by parsing the FDE header). The CIE itself
   // is obtained lazily once it's actually required.
-  FDE(DataExtractor D, uint64_t Offset, uint64_t Length,
-      int64_t LinkedCIEOffset, uint64_t InitialLocation, uint64_t AddressRange)
-   : FrameEntry(FK_FDE, D, Offset, Length), LinkedCIEOffset(LinkedCIEOffset),
-     InitialLocation(InitialLocation), AddressRange(AddressRange),
-     LinkedCIE(nullptr) {}
+  FDE(uint64_t Offset, uint64_t Length, int64_t LinkedCIEOffset,
+      uint64_t InitialLocation, uint64_t AddressRange)
+      : FrameEntry(FK_FDE, Offset, Length), LinkedCIEOffset(LinkedCIEOffset),
+        InitialLocation(InitialLocation), AddressRange(AddressRange),
+        LinkedCIE(nullptr) {}
 
   ~FDE() {
   }
@@ -270,9 +267,9 @@ public:
 
   static bool classof(const FrameEntry *FE) {
     return FE->getKind() == FK_FDE;
-  } 
-private:
+  }
 
+private:
   /// The following fields are defined in section 6.4.1 of the DWARF standard v3
   uint64_t LinkedCIEOffset;
   uint64_t InitialLocation;
@@ -285,14 +282,9 @@ private:
 DWARFDebugFrame::DWARFDebugFrame() {
 }
 
-
 DWARFDebugFrame::~DWARFDebugFrame() {
-  for (const auto &Entry : Entries) {
-    delete Entry;
-  }
 }
 
-
 static void LLVM_ATTRIBUTE_UNUSED dumpDataAux(DataExtractor Data,
                                               uint32_t Offset, int Length) {
   errs() << "DUMP: ";
@@ -334,7 +326,6 @@ void DWARFDebugFrame::parse(DataExtractor Data) {
     Id = Data.getUnsigned(&Offset, IsDWARF64 ? 8 : 4);
     bool IsCIE = ((IsDWARF64 && Id == DW64_CIE_ID) || Id == DW_CIE_ID);
 
-    FrameEntry *Entry = nullptr;
     if (IsCIE) {
       // Note: this is specifically DWARFv3 CIE header structure. It was
       // changed in DWARFv4. We currently don't support reading DWARFv4
@@ -346,30 +337,25 @@ void DWARFDebugFrame::parse(DataExtractor Data) {
       int64_t DataAlignmentFactor = Data.getSLEB128(&Offset);
       uint64_t ReturnAddressRegister = Data.getULEB128(&Offset);
 
-      Entry = new CIE(Data, StartOffset, Length, Version,
-                      StringRef(Augmentation), CodeAlignmentFactor,
-                      DataAlignmentFactor, ReturnAddressRegister);
+      Entries.emplace_back(new CIE(StartOffset, Length, Version,
+                                   StringRef(Augmentation), CodeAlignmentFactor,
+                                   DataAlignmentFactor, ReturnAddressRegister));
     } else {
       // FDE
       uint64_t CIEPointer = Id;
       uint64_t InitialLocation = Data.getAddress(&Offset);
       uint64_t AddressRange = Data.getAddress(&Offset);
 
-      Entry = new FDE(Data, StartOffset, Length, CIEPointer,
-                      InitialLocation, AddressRange);
+      Entries.emplace_back(new FDE(StartOffset, Length, CIEPointer,
+                                   InitialLocation, AddressRange));
     }
 
-    assert(Entry && "Expected Entry to be populated with CIE or FDE");
-    Entry->parseInstructions(&Offset, EndStructureOffset);
+    Entries.back()->parseInstructions(Data, &Offset, EndStructureOffset);
 
-    if (Offset == EndStructureOffset) {
-      // Entry instrucitons parsed successfully.
-      Entries.push_back(Entry);
-    } else {
+    if (Offset != EndStructureOffset) {
       std::string Str;
       raw_string_ostream OS(Str);
-      OS << format("Parsing entry instructions at %lx failed",
-                   Entry->getOffset());
+      OS << format("Parsing entry instructions at %lx failed", StartOffset);
       report_fatal_error(Str);
     }
   }
diff --git a/lib/DebugInfo/DWARFDebugFrame.h b/lib/DebugInfo/DWARFDebugFrame.h
index 7683849b4a..bd4ef45e4c 100644
--- a/lib/DebugInfo/DWARFDebugFrame.h
+++ b/lib/DebugInfo/DWARFDebugFrame.h
@@ -12,14 +12,13 @@
 
 #include "llvm/Support/DataExtractor.h"
 #include "llvm/Support/raw_ostream.h"
+#include <memory>
 #include <vector>
 
-
 namespace llvm {
 
 class FrameEntry;
 
-
 /// \brief A parsed .debug_frame section
 ///
 class DWARFDebugFrame {
@@ -35,8 +34,7 @@ public:
   void parse(DataExtractor Data);
 
 private:
-  typedef std::vector<FrameEntry *> EntryVector;
-  EntryVector Entries;
+  std::vector<std::unique_ptr<FrameEntry>> Entries;
 };
 
 
diff --git a/lib/DebugInfo/DWARFDebugInfoEntry.h b/lib/DebugInfo/DWARFDebugInfoEntry.h
index 2d0e953de3..35140d7359 100644
--- a/lib/DebugInfo/DWARFDebugInfoEntry.h
+++ b/lib/DebugInfo/DWARFDebugInfoEntry.h
@@ -29,17 +29,13 @@ class DWARFDebugInfoEntryMinimal {
   /// Offset within the .debug_info of the start of this entry.
   uint32_t Offset;
 
-  /// How many to subtract from "this" to get the parent.
-  /// If zero this die has no parent.
-  uint32_t ParentIdx;
-
   /// How many to add to "this" to get the sibling.
   uint32_t SiblingIdx;
 
   const DWARFAbbreviationDeclaration *AbbrevDecl;
 public:
   DWARFDebugInfoEntryMinimal()
-    : Offset(0), ParentIdx(0), SiblingIdx(0), AbbrevDecl(nullptr) {}
+    : Offset(0), SiblingIdx(0), AbbrevDecl(nullptr) {}
 
   void dump(raw_ostream &OS, const DWARFUnit *u, unsigned recurseDepth,
             unsigned indent = 0) const;
@@ -64,45 +60,23 @@ public:
   bool hasChildren() const { return !isNULL() && AbbrevDecl->hasChildren(); }
 
   // We know we are kept in a vector of contiguous entries, so we know
-  // our parent will be some index behind "this".
-  DWARFDebugInfoEntryMinimal *getParent() {
-    return ParentIdx > 0 ? this - ParentIdx : nullptr;
-  }
-  const DWARFDebugInfoEntryMinimal *getParent() const {
-    return ParentIdx > 0 ? this - ParentIdx : nullptr;
-  }
-  // We know we are kept in a vector of contiguous entries, so we know
   // our sibling will be some index after "this".
-  DWARFDebugInfoEntryMinimal *getSibling() {
-    return SiblingIdx > 0 ? this + SiblingIdx : nullptr;
-  }
   const DWARFDebugInfoEntryMinimal *getSibling() const {
     return SiblingIdx > 0 ? this + SiblingIdx : nullptr;
   }
+
   // We know we are kept in a vector of contiguous entries, so we know
   // we don't need to store our child pointer, if we have a child it will
   // be the next entry in the list...
-  DWARFDebugInfoEntryMinimal *getFirstChild() {
-    return hasChildren() ? this + 1 : nullptr;
-  }
   const DWARFDebugInfoEntryMinimal *getFirstChild() const {
     return hasChildren() ? this + 1 : nullptr;
   }
 
-  void setParent(DWARFDebugInfoEntryMinimal *parent) {
-    if (parent) {
-      // We know we are kept in a vector of contiguous entries, so we know
-      // our parent will be some index behind "this".
-      ParentIdx = this - parent;
-    } else
-      ParentIdx = 0;
-  }
-  void setSibling(DWARFDebugInfoEntryMinimal *sibling) {
-    if (sibling) {
+  void setSibling(const DWARFDebugInfoEntryMinimal *Sibling) {
+    if (Sibling) {
       // We know we are kept in a vector of contiguous entries, so we know
       // our sibling will be some index after "this".
-      SiblingIdx = sibling - this;
-      sibling->setParent(getParent());
+      SiblingIdx = Sibling - this;
     } else
       SiblingIdx = 0;
   }
diff --git a/lib/DebugInfo/DWARFDebugLine.cpp b/lib/DebugInfo/DWARFDebugLine.cpp
index de543eec2d..a5261d7644 100644
--- a/lib/DebugInfo/DWARFDebugLine.cpp
+++ b/lib/DebugInfo/DWARFDebugLine.cpp
@@ -16,6 +16,19 @@
 using namespace llvm;
 using namespace dwarf;
 
+DWARFDebugLine::Prologue::Prologue() {
+  clear();
+}
+
+void DWARFDebugLine::Prologue::clear() {
+  TotalLength = Version = PrologueLength = 0;
+  MinInstLength = MaxOpsPerInst = DefaultIsStmt = LineBase = LineRange = 0;
+  OpcodeBase = 0;
+  StandardOpcodeLengths.clear();
+  IncludeDirectories.clear();
+  FileNames.clear();
+}
+
 void DWARFDebugLine::Prologue::dump(raw_ostream &OS) const {
   OS << "Line table prologue:\n"
      << format("    total_length: 0x%8.8x\n", TotalLength)
@@ -51,6 +64,67 @@ void DWARFDebugLine::Prologue::dump(raw_ostream &OS) const {
   }
 }
 
+bool DWARFDebugLine::Prologue::parse(DataExtractor debug_line_data,
+                                     uint32_t *offset_ptr) {
+  const uint32_t prologue_offset = *offset_ptr;
+
+  clear();
+  TotalLength = debug_line_data.getU32(offset_ptr);
+  Version = debug_line_data.getU16(offset_ptr);
+  if (Version < 2)
+    return false;
+
+  PrologueLength = debug_line_data.getU32(offset_ptr);
+  const uint32_t end_prologue_offset = PrologueLength + *offset_ptr;
+  MinInstLength = debug_line_data.getU8(offset_ptr);
+  if (Version >= 4)
+    MaxOpsPerInst = debug_line_data.getU8(offset_ptr);
+  DefaultIsStmt = debug_line_data.getU8(offset_ptr);
+  LineBase = debug_line_data.getU8(offset_ptr);
+  LineRange = debug_line_data.getU8(offset_ptr);
+  OpcodeBase = debug_line_data.getU8(offset_ptr);
+
+  StandardOpcodeLengths.reserve(OpcodeBase - 1);
+  for (uint32_t i = 1; i < OpcodeBase; ++i) {
+    uint8_t op_len = debug_line_data.getU8(offset_ptr);
+    StandardOpcodeLengths.push_back(op_len);
+  }
+
+  while (*offset_ptr < end_prologue_offset) {
+    const char *s = debug_line_data.getCStr(offset_ptr);
+    if (s && s[0])
+      IncludeDirectories.push_back(s);
+    else
+      break;
+  }
+
+  while (*offset_ptr < end_prologue_offset) {
+    const char *name = debug_line_data.getCStr(offset_ptr);
+    if (name && name[0]) {
+      FileNameEntry fileEntry;
+      fileEntry.Name = name;
+      fileEntry.DirIdx = debug_line_data.getULEB128(offset_ptr);
+      fileEntry.ModTime = debug_line_data.getULEB128(offset_ptr);
+      fileEntry.Length = debug_line_data.getULEB128(offset_ptr);
+      FileNames.push_back(fileEntry);
+    } else {
+      break;
+    }
+  }
+
+  if (*offset_ptr != end_prologue_offset) {
+    fprintf(stderr, "warning: parsing line table prologue at 0x%8.8x should"
+                    " have ended at 0x%8.8x but it ended at 0x%8.8x\n",
+            prologue_offset, end_prologue_offset, *offset_ptr);
+    return false;
+  }
+  return true;
+}
+
+DWARFDebugLine::Row::Row(bool default_is_stmt) {
+  reset(default_is_stmt);
+}
+
 void DWARFDebugLine::Row::postAppend() {
   BasicBlock = false;
   PrologueEnd = false;
@@ -82,6 +156,22 @@ void DWARFDebugLine::Row::dump(raw_ostream &OS) const {
      << '\n';
 }
 
+DWARFDebugLine::Sequence::Sequence() {
+  reset();
+}
+
+void DWARFDebugLine::Sequence::reset() {
+  LowPC = 0;
+  HighPC = 0;
+  FirstRowIndex = 0;
+  LastRowIndex = 0;
+  Empty = true;
+}
+
+DWARFDebugLine::LineTable::LineTable() {
+  clear();
+}
+
 void DWARFDebugLine::LineTable::dump(raw_ostream &OS) const {
   Prologue.dump(OS);
   OS << '\n';
@@ -96,50 +186,40 @@ void DWARFDebugLine::LineTable::dump(raw_ostream &OS) const {
   }
 }
 
-DWARFDebugLine::State::~State() {}
-
-void DWARFDebugLine::State::appendRowToMatrix(uint32_t offset) {
-  if (Sequence::Empty) {
-    // Record the beginning of instruction sequence.
-    Sequence::Empty = false;
-    Sequence::LowPC = Address;
-    Sequence::FirstRowIndex = row;
-  }
-  ++row;  // Increase the row number.
-  LineTable::appendRow(*this);
-  if (EndSequence) {
-    // Record the end of instruction sequence.
-    Sequence::HighPC = Address;
-    Sequence::LastRowIndex = row;
-    if (Sequence::isValid())
-      LineTable::appendSequence(*this);
-    Sequence::reset();
-  }
-  Row::postAppend();
+void DWARFDebugLine::LineTable::clear() {
+  Prologue.clear();
+  Rows.clear();
+  Sequences.clear();
 }
 
-void DWARFDebugLine::State::finalize() {
-  row = DoneParsingLineTable;
-  if (!Sequence::Empty) {
-    fprintf(stderr, "warning: last sequence in debug line table is not"
-                    "terminated!\n");
-  }
-  // Sort all sequences so that address lookup will work faster.
-  if (!Sequences.empty()) {
-    std::sort(Sequences.begin(), Sequences.end(), Sequence::orderByLowPC);
-    // Note: actually, instruction address ranges of sequences should not
-    // overlap (in shared objects and executables). If they do, the address
-    // lookup would still work, though, but result would be ambiguous.
-    // We don't report warning in this case. For example,
-    // sometimes .so compiled from multiple object files contains a few
-    // rudimentary sequences for address ranges [0x0, 0xsomething).
-  }
+DWARFDebugLine::ParsingState::ParsingState(struct LineTable *LT)
+    : LineTable(LT), RowNumber(0) {
+  resetRowAndSequence();
 }
 
-DWARFDebugLine::DumpingState::~DumpingState() {}
+void DWARFDebugLine::ParsingState::resetRowAndSequence() {
+  Row.reset(LineTable->Prologue.DefaultIsStmt);
+  Sequence.reset();
+}
 
-void DWARFDebugLine::DumpingState::finalize() {
-  LineTable::dump(OS);
+void DWARFDebugLine::ParsingState::appendRowToMatrix(uint32_t offset) {
+  if (Sequence.Empty) {
+    // Record the beginning of instruction sequence.
+    Sequence.Empty = false;
+    Sequence.LowPC = Row.Address;
+    Sequence.FirstRowIndex = RowNumber;
+  }
+  ++RowNumber;
+  LineTable->appendRow(Row);
+  if (Row.EndSequence) {
+    // Record the end of instruction sequence.
+    Sequence.HighPC = Row.Address;
+    Sequence.LastRowIndex = RowNumber;
+    if (Sequence.isValid())
+      LineTable->appendSequence(Sequence);
+    Sequence.reset();
+  }
+  Row.postAppend();
 }
 
 const DWARFDebugLine::LineTable *
@@ -155,91 +235,31 @@ DWARFDebugLine::getOrParseLineTable(DataExtractor debug_line_data,
                                     uint32_t offset) {
   std::pair<LineTableIter, bool> pos =
     LineTableMap.insert(LineTableMapTy::value_type(offset, LineTable()));
+  LineTable *LT = &pos.first->second;
   if (pos.second) {
-    // Parse and cache the line table for at this offset.
-    State state;
-    if (!parseStatementTable(debug_line_data, RelocMap, &offset, state))
+    if (!LT->parse(debug_line_data, RelocMap, &offset))
       return nullptr;
-    pos.first->second = state;
   }
-  return &pos.first->second;
+  return LT;
 }
 
-bool
-DWARFDebugLine::parsePrologue(DataExtractor debug_line_data,
-                              uint32_t *offset_ptr, Prologue *prologue) {
-  const uint32_t prologue_offset = *offset_ptr;
-
-  prologue->clear();
-  prologue->TotalLength = debug_line_data.getU32(offset_ptr);
-  prologue->Version = debug_line_data.getU16(offset_ptr);
-  if (prologue->Version < 2)
-    return false;
-
-  prologue->PrologueLength = debug_line_data.getU32(offset_ptr);
-  const uint32_t end_prologue_offset = prologue->PrologueLength + *offset_ptr;
-  prologue->MinInstLength = debug_line_data.getU8(offset_ptr);
-  if (prologue->Version >= 4)
-    prologue->MaxOpsPerInst = debug_line_data.getU8(offset_ptr);
-  prologue->DefaultIsStmt = debug_line_data.getU8(offset_ptr);
-  prologue->LineBase = debug_line_data.getU8(offset_ptr);
-  prologue->LineRange = debug_line_data.getU8(offset_ptr);
-  prologue->OpcodeBase = debug_line_data.getU8(offset_ptr);
-
-  prologue->StandardOpcodeLengths.reserve(prologue->OpcodeBase-1);
-  for (uint32_t i = 1; i < prologue->OpcodeBase; ++i) {
-    uint8_t op_len = debug_line_data.getU8(offset_ptr);
-    prologue->StandardOpcodeLengths.push_back(op_len);
-  }
-
-  while (*offset_ptr < end_prologue_offset) {
-    const char *s = debug_line_data.getCStr(offset_ptr);
-    if (s && s[0])
-      prologue->IncludeDirectories.push_back(s);
-    else
-      break;
-  }
-
-  while (*offset_ptr < end_prologue_offset) {
-    const char *name = debug_line_data.getCStr(offset_ptr);
-    if (name && name[0]) {
-      FileNameEntry fileEntry;
-      fileEntry.Name = name;
-      fileEntry.DirIdx = debug_line_data.getULEB128(offset_ptr);
-      fileEntry.ModTime = debug_line_data.getULEB128(offset_ptr);
-      fileEntry.Length = debug_line_data.getULEB128(offset_ptr);
-      prologue->FileNames.push_back(fileEntry);
-    } else {
-      break;
-    }
-  }
-
-  if (*offset_ptr != end_prologue_offset) {
-    fprintf(stderr, "warning: parsing line table prologue at 0x%8.8x should"
-                    " have ended at 0x%8.8x but it ended at 0x%8.8x\n",
-            prologue_offset, end_prologue_offset, *offset_ptr);
-    return false;
-  }
-  return true;
-}
-
-bool DWARFDebugLine::parseStatementTable(DataExtractor debug_line_data,
-                                         const RelocAddrMap *RMap,
-                                         uint32_t *offset_ptr, State &state) {
+bool DWARFDebugLine::LineTable::parse(DataExtractor debug_line_data,
+                                      const RelocAddrMap *RMap,
+                                      uint32_t *offset_ptr) {
   const uint32_t debug_line_offset = *offset_ptr;
 
-  Prologue *prologue = &state.Prologue;
+  clear();
 
-  if (!parsePrologue(debug_line_data, offset_ptr, prologue)) {
+  if (!Prologue.parse(debug_line_data, offset_ptr)) {
     // Restore our offset and return false to indicate failure!
     *offset_ptr = debug_line_offset;
     return false;
   }
 
-  const uint32_t end_offset = debug_line_offset + prologue->TotalLength +
-                              sizeof(prologue->TotalLength);
+  const uint32_t end_offset = debug_line_offset + Prologue.TotalLength +
+                              sizeof(Prologue.TotalLength);
 
-  state.reset();
+  ParsingState State(this);
 
   while (*offset_ptr < end_offset) {
     uint8_t opcode = debug_line_data.getU8(offset_ptr);
@@ -261,9 +281,9 @@ bool DWARFDebugLine::parseStatementTable(DataExtractor debug_line_data,
         // with a DW_LNE_end_sequence instruction which creates a row whose
         // address is that of the byte after the last target machine instruction
         // of the sequence.
-        state.EndSequence = true;
-        state.appendRowToMatrix(*offset_ptr);
-        state.reset();
+        State.Row.EndSequence = true;
+        State.appendRowToMatrix(*offset_ptr);
+        State.resetRowAndSequence();
         break;
 
       case DW_LNE_set_address:
@@ -278,9 +298,10 @@ bool DWARFDebugLine::parseStatementTable(DataExtractor debug_line_data,
           RelocAddrMap::const_iterator AI = RMap->find(*offset_ptr);
           if (AI != RMap->end()) {
              const std::pair<uint8_t, int64_t> &R = AI->second;
-             state.Address = debug_line_data.getAddress(offset_ptr) + R.second;
+             State.Row.Address =
+                 debug_line_data.getAddress(offset_ptr) + R.second;
           } else
-            state.Address = debug_line_data.getAddress(offset_ptr);
+            State.Row.Address = debug_line_data.getAddress(offset_ptr);
         }
         break;
 
@@ -311,12 +332,12 @@ bool DWARFDebugLine::parseStatementTable(DataExtractor debug_line_data,
           fileEntry.DirIdx = debug_line_data.getULEB128(offset_ptr);
           fileEntry.ModTime = debug_line_data.getULEB128(offset_ptr);
           fileEntry.Length = debug_line_data.getULEB128(offset_ptr);
-          prologue->FileNames.push_back(fileEntry);
+          Prologue.FileNames.push_back(fileEntry);
         }
         break;
 
       case DW_LNE_set_discriminator:
-        state.Discriminator = debug_line_data.getULEB128(offset_ptr);
+        State.Row.Discriminator = debug_line_data.getULEB128(offset_ptr);
         break;
 
       default:
@@ -325,52 +346,52 @@ bool DWARFDebugLine::parseStatementTable(DataExtractor debug_line_data,
         (*offset_ptr) += arg_size;
         break;
       }
-    } else if (opcode < prologue->OpcodeBase) {
+    } else if (opcode < Prologue.OpcodeBase) {
       switch (opcode) {
       // Standard Opcodes
       case DW_LNS_copy:
         // Takes no arguments. Append a row to the matrix using the
         // current values of the state-machine registers. Then set
         // the basic_block register to false.
-        state.appendRowToMatrix(*offset_ptr);
+        State.appendRowToMatrix(*offset_ptr);
         break;
 
       case DW_LNS_advance_pc:
         // Takes a single unsigned LEB128 operand, multiplies it by the
         // min_inst_length field of the prologue, and adds the
         // result to the address register of the state machine.
-        state.Address += debug_line_data.getULEB128(offset_ptr) *
-                         prologue->MinInstLength;
+        State.Row.Address +=
+            debug_line_data.getULEB128(offset_ptr) * Prologue.MinInstLength;
         break;
 
       case DW_LNS_advance_line:
         // Takes a single signed LEB128 operand and adds that value to
         // the line register of the state machine.
-        state.Line += debug_line_data.getSLEB128(offset_ptr);
+        State.Row.Line += debug_line_data.getSLEB128(offset_ptr);
         break;
 
       case DW_LNS_set_file:
         // Takes a single unsigned LEB128 operand and stores it in the file
         // register of the state machine.
-        state.File = debug_line_data.getULEB128(offset_ptr);
+        State.Row.File = debug_line_data.getULEB128(offset_ptr);
         break;
 
       case DW_LNS_set_column:
         // Takes a single unsigned LEB128 operand and stores it in the
         // column register of the state machine.
-        state.Column = debug_line_data.getULEB128(offset_ptr);
+        State.Row.Column = debug_line_data.getULEB128(offset_ptr);
         break;
 
       case DW_LNS_negate_stmt:
         // Takes no arguments. Set the is_stmt register of the state
         // machine to the logical negation of its current value.
-        state.IsStmt = !state.IsStmt;
+        State.Row.IsStmt = !State.Row.IsStmt;
         break;
 
       case DW_LNS_set_basic_block:
         // Takes no arguments. Set the basic_block register of the
         // state machine to true
-        state.BasicBlock = true;
+        State.Row.BasicBlock = true;
         break;
 
       case DW_LNS_const_add_pc:
@@ -386,10 +407,10 @@ bool DWARFDebugLine::parseStatementTable(DataExtractor debug_line_data,
         // than twice that range will it need to use both DW_LNS_advance_pc
         // and a special opcode, requiring three or more bytes.
         {
-          uint8_t adjust_opcode = 255 - prologue->OpcodeBase;
-          uint64_t addr_offset = (adjust_opcode / prologue->LineRange) *
-                                 prologue->MinInstLength;
-          state.Address += addr_offset;
+          uint8_t adjust_opcode = 255 - Prologue.OpcodeBase;
+          uint64_t addr_offset =
+              (adjust_opcode / Prologue.LineRange) * Prologue.MinInstLength;
+          State.Row.Address += addr_offset;
         }
         break;
 
@@ -403,25 +424,25 @@ bool DWARFDebugLine::parseStatementTable(DataExtractor debug_line_data,
         // judge when the computation of a special opcode overflows and
         // requires the use of DW_LNS_advance_pc. Such assemblers, however,
         // can use DW_LNS_fixed_advance_pc instead, sacrificing compression.
-        state.Address += debug_line_data.getU16(offset_ptr);
+        State.Row.Address += debug_line_data.getU16(offset_ptr);
         break;
 
       case DW_LNS_set_prologue_end:
         // Takes no arguments. Set the prologue_end register of the
         // state machine to true
-        state.PrologueEnd = true;
+        State.Row.PrologueEnd = true;
         break;
 
       case DW_LNS_set_epilogue_begin:
         // Takes no arguments. Set the basic_block register of the
         // state machine to true
-        state.EpilogueBegin = true;
+        State.Row.EpilogueBegin = true;
         break;
 
       case DW_LNS_set_isa:
         // Takes a single unsigned LEB128 operand and stores it in the
         // column register of the state machine.
-        state.Isa = debug_line_data.getULEB128(offset_ptr);
+        State.Row.Isa = debug_line_data.getULEB128(offset_ptr);
         break;
 
       default:
@@ -429,9 +450,9 @@ bool DWARFDebugLine::parseStatementTable(DataExtractor debug_line_data,
         // of such opcodes because they are specified in the prologue
         // as a multiple of LEB128 operands for each opcode.
         {
-          assert(opcode - 1U < prologue->StandardOpcodeLengths.size());
-          uint8_t opcode_length = prologue->StandardOpcodeLengths[opcode - 1];
-          for (uint8_t i=0; i<opcode_length; ++i)
+          assert(opcode - 1U < Prologue.StandardOpcodeLengths.size());
+          uint8_t opcode_length = Prologue.StandardOpcodeLengths[opcode - 1];
+          for (uint8_t i = 0; i < opcode_length; ++i)
             debug_line_data.getULEB128(offset_ptr);
         }
         break;
@@ -470,24 +491,37 @@ bool DWARFDebugLine::parseStatementTable(DataExtractor debug_line_data,
       //
       // line increment = line_base + (adjusted opcode % line_range)
 
-      uint8_t adjust_opcode = opcode - prologue->OpcodeBase;
-      uint64_t addr_offset = (adjust_opcode / prologue->LineRange) *
-                             prologue->MinInstLength;
-      int32_t line_offset = prologue->LineBase +
-                            (adjust_opcode % prologue->LineRange);
-      state.Line += line_offset;
-      state.Address += addr_offset;
-      state.appendRowToMatrix(*offset_ptr);
+      uint8_t adjust_opcode = opcode - Prologue.OpcodeBase;
+      uint64_t addr_offset =
+          (adjust_opcode / Prologue.LineRange) * Prologue.MinInstLength;
+      int32_t line_offset =
+          Prologue.LineBase + (adjust_opcode % Prologue.LineRange);
+      State.Row.Line += line_offset;
+      State.Row.Address += addr_offset;
+      State.appendRowToMatrix(*offset_ptr);
     }
   }
 
-  state.finalize();
+  if (!State.Sequence.Empty) {
+    fprintf(stderr, "warning: last sequence in debug line table is not"
+                    "terminated!\n");
+  }
+
+  // Sort all sequences so that address lookup will work faster.
+  if (!Sequences.empty()) {
+    std::sort(Sequences.begin(), Sequences.end(), Sequence::orderByLowPC);
+    // Note: actually, instruction address ranges of sequences should not
+    // overlap (in shared objects and executables). If they do, the address
+    // lookup would still work, though, but result would be ambiguous.
+    // We don't report warning in this case. For example,
+    // sometimes .so compiled from multiple object files contains a few
+    // rudimentary sequences for address ranges [0x0, 0xsomething).
+  }
 
   return end_offset;
 }
 
-uint32_t
-DWARFDebugLine::LineTable::lookupAddress(uint64_t address) const {
+uint32_t DWARFDebugLine::LineTable::lookupAddress(uint64_t address) const {
   uint32_t unknown_index = UINT32_MAX;
   if (Sequences.empty())
     return unknown_index;
@@ -532,10 +566,8 @@ DWARFDebugLine::LineTable::lookupAddress(uint64_t address) const {
   return index;
 }
 
-bool
-DWARFDebugLine::LineTable::lookupAddressRange(uint64_t address,
-                                       uint64_t size, 
-                                       std::vector<uint32_t>& result) const {
+bool DWARFDebugLine::LineTable::lookupAddressRange(
+    uint64_t address, uint64_t size, std::vector<uint32_t> &result) const {
   if (Sequences.empty())
     return false;
   uint64_t end_addr = address + size;
diff --git a/lib/DebugInfo/DWARFDebugLine.h b/lib/DebugInfo/DWARFDebugLine.h
index 890eb28c1e..0b3e267c2f 100644
--- a/lib/DebugInfo/DWARFDebugLine.h
+++ b/lib/DebugInfo/DWARFDebugLine.h
@@ -33,10 +33,7 @@ public:
   };
 
   struct Prologue {
-    Prologue()
-        : TotalLength(0), Version(0), PrologueLength(0), MinInstLength(0),
-          MaxOpsPerInst(0), DefaultIsStmt(0), LineBase(0), LineRange(0),
-          OpcodeBase(0) {}
+    Prologue();
 
     // The size in bytes of the statement information for this compilation unit
     // (not including the total_length field itself).
@@ -77,19 +74,16 @@ public:
     int32_t getMaxLineIncrementForSpecialOpcode() const {
       return LineBase + (int8_t)LineRange - 1;
     }
+
+    void clear();
     void dump(raw_ostream &OS) const;
-    void clear() {
-      TotalLength = Version = PrologueLength = 0;
-      MinInstLength = LineBase = LineRange = OpcodeBase = 0;
-      StandardOpcodeLengths.clear();
-      IncludeDirectories.clear();
-      FileNames.clear();
-    }
+    bool parse(DataExtractor debug_line_data, uint32_t *offset_ptr);
   };
 
   // Standard .debug_line state machine structure.
   struct Row {
-    Row(bool default_is_stmt = false) { reset(default_is_stmt); }
+    explicit Row(bool default_is_stmt = false);
+
     /// Called after a row is appended to the matrix.
     void postAppend();
     void reset(bool default_is_stmt);
@@ -151,14 +145,9 @@ public:
     unsigned LastRowIndex;
     bool Empty;
 
-    Sequence() { reset(); }
-    void reset() {
-      LowPC = 0;
-      HighPC = 0;
-      FirstRowIndex = 0;
-      LastRowIndex = 0;
-      Empty = true;
-    }
+    Sequence();
+    void reset();
+
     static bool orderByLowPC(const Sequence& LHS, const Sequence& RHS) {
       return LHS.LowPC < RHS.LowPC;
     }
@@ -171,23 +160,21 @@ public:
   };
 
   struct LineTable {
-    void appendRow(const DWARFDebugLine::Row &state) { Rows.push_back(state); }
-    void appendSequence(const DWARFDebugLine::Sequence &sequence) {
-      Sequences.push_back(sequence);
+    LineTable();
+
+    void appendRow(const DWARFDebugLine::Row &R) {
+      Rows.push_back(R);
     }
-    void clear() {
-      Prologue.clear();
-      Rows.clear();
-      Sequences.clear();
+    void appendSequence(const DWARFDebugLine::Sequence &S) {
+      Sequences.push_back(S);
     }
 
     // Returns the index of the row with file/line info for a given address,
     // or -1 if there is no such row.
     uint32_t lookupAddress(uint64_t address) const;
 
-    bool lookupAddressRange(uint64_t address,
-                            uint64_t size, 
-                            std::vector<uint32_t>& result) const;
+    bool lookupAddressRange(uint64_t address, uint64_t size,
+                            std::vector<uint32_t> &result) const;
 
     // Extracts filename by its index in filename table in prologue.
     // Returns true on success.
@@ -196,6 +183,11 @@ public:
                             std::string &Result) const;
 
     void dump(raw_ostream &OS) const;
+    void clear();
+
+    /// Parse prologue and all rows.
+    bool parse(DataExtractor debug_line_data, const RelocAddrMap *RMap,
+               uint32_t *offset_ptr);
 
     struct Prologue Prologue;
     typedef std::vector<Row> RowVector;
@@ -206,48 +198,26 @@ public:
     SequenceVector Sequences;
   };
 
-  struct State : public Row, public Sequence, public LineTable {
-    // Special row codes.
-    enum {
-      StartParsingLineTable = 0,
-      DoneParsingLineTable = -1
-    };
-
-    State() : row(StartParsingLineTable) {}
-    virtual ~State();
-
-    virtual void appendRowToMatrix(uint32_t offset);
-    virtual void finalize();
-    virtual void reset() {
-      Row::reset(Prologue.DefaultIsStmt);
-      Sequence::reset();
-    }
-
-    // The row number that starts at zero for the prologue, and increases for
-    // each row added to the matrix.
-    unsigned row;
-  };
-
-  struct DumpingState : public State {
-    DumpingState(raw_ostream &OS) : OS(OS) {}
-    virtual ~DumpingState();
-    void finalize() override;
-  private:
-    raw_ostream &OS;
-  };
-
-  static bool parsePrologue(DataExtractor debug_line_data, uint32_t *offset_ptr,
-                            Prologue *prologue);
-  /// Parse a single line table (prologue and all rows).
-  static bool parseStatementTable(DataExtractor debug_line_data,
-                                  const RelocAddrMap *RMap,
-                                  uint32_t *offset_ptr, State &state);
-
   const LineTable *getLineTable(uint32_t offset) const;
   const LineTable *getOrParseLineTable(DataExtractor debug_line_data,
                                        uint32_t offset);
 
 private:
+  struct ParsingState {
+    ParsingState(struct LineTable *LT);
+
+    void resetRowAndSequence();
+    void appendRowToMatrix(uint32_t offset);
+
+    // Line table we're currently parsing.
+    struct LineTable *LineTable;
+    // The row number that starts at zero for the prologue, and increases for
+    // each row added to the matrix.
+    unsigned RowNumber;
+    struct Row Row;
+    struct Sequence Sequence;
+  };
+
   typedef std::map<uint32_t, LineTable> LineTableMapTy;
   typedef LineTableMapTy::iterator LineTableIter;
   typedef LineTableMapTy::const_iterator LineTableConstIter;
diff --git a/lib/DebugInfo/DWARFUnit.cpp b/lib/DebugInfo/DWARFUnit.cpp
index c49020ad62..f5f5072b9d 100644
--- a/lib/DebugInfo/DWARFUnit.cpp
+++ b/lib/DebugInfo/DWARFUnit.cpp
@@ -126,38 +126,32 @@ uint64_t DWARFUnit::getDWOId() {
 }
 
 void DWARFUnit::setDIERelations() {
-  if (DieArray.empty())
+  if (DieArray.size() <= 1)
     return;
-  DWARFDebugInfoEntryMinimal *die_array_begin = &DieArray.front();
-  DWARFDebugInfoEntryMinimal *die_array_end = &DieArray.back();
-  DWARFDebugInfoEntryMinimal *curr_die;
-  // We purposely are skipping the last element in the array in the loop below
-  // so that we can always have a valid next item
-  for (curr_die = die_array_begin; curr_die < die_array_end; ++curr_die) {
-    // Since our loop doesn't include the last element, we can always
-    // safely access the next die in the array.
-    DWARFDebugInfoEntryMinimal *next_die = curr_die + 1;
-
-    const DWARFAbbreviationDeclaration *curr_die_abbrev =
-      curr_die->getAbbreviationDeclarationPtr();
-
-    if (curr_die_abbrev) {
-      // Normal DIE
-      if (curr_die_abbrev->hasChildren())
-        next_die->setParent(curr_die);
-      else
-        curr_die->setSibling(next_die);
+
+  std::vector<DWARFDebugInfoEntryMinimal *> ParentChain;
+  DWARFDebugInfoEntryMinimal *SiblingChain = nullptr;
+  for (auto &DIE : DieArray) {
+    if (SiblingChain) {
+      SiblingChain->setSibling(&DIE);
+    }
+    if (const DWARFAbbreviationDeclaration *AbbrDecl =
+            DIE.getAbbreviationDeclarationPtr()) {
+      // Normal DIE.
+      if (AbbrDecl->hasChildren()) {
+        ParentChain.push_back(&DIE);
+        SiblingChain = nullptr;
+      } else {
+        SiblingChain = &DIE;
+      }
     } else {
-      // NULL DIE that terminates a sibling chain
-      DWARFDebugInfoEntryMinimal *parent = curr_die->getParent();
-      if (parent)
-        parent->setSibling(next_die);
+      // NULL entry terminates the sibling chain.
+      SiblingChain = ParentChain.back();
+      ParentChain.pop_back();
     }
   }
-
-  // Since we skipped the last element, we need to fix it up!
-  if (die_array_begin < die_array_end)
-    curr_die->setParent(die_array_begin);
+  assert(SiblingChain == nullptr || SiblingChain == &DieArray[0]);
+  assert(ParentChain.empty());
 }
 
 void DWARFUnit::extractDIEsToVector(
@@ -189,9 +183,8 @@ void DWARFUnit::extractDIEsToVector(
       Dies.push_back(DIE);
     }
 
-    const DWARFAbbreviationDeclaration *AbbrDecl =
-      DIE.getAbbreviationDeclarationPtr();
-    if (AbbrDecl) {
+    if (const DWARFAbbreviationDeclaration *AbbrDecl =
+            DIE.getAbbreviationDeclarationPtr()) {
       // Normal DIE
       if (AbbrDecl->hasChildren())
         ++Depth;
diff --git a/lib/ExecutionEngine/ExecutionEngine.cpp b/lib/ExecutionEngine/ExecutionEngine.cpp
index ab89814951..be759c6b35 100644
--- a/lib/ExecutionEngine/ExecutionEngine.cpp
+++ b/lib/ExecutionEngine/ExecutionEngine.cpp
@@ -24,6 +24,7 @@
 #include "llvm/IR/Module.h"
 #include "llvm/IR/Operator.h"
 #include "llvm/IR/ValueHandle.h"
+#include "llvm/Object/ObjectFile.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/DynamicLibrary.h"
 #include "llvm/Support/ErrorHandling.h"
@@ -121,6 +122,10 @@ char *ExecutionEngine::getMemoryForGV(const GlobalVariable *GV) {
   return GVMemoryBlock::Create(GV, *getDataLayout());
 }
 
+void ExecutionEngine::addObjectFile(std::unique_ptr<object::ObjectFile> O) {
+  llvm_unreachable("ExecutionEngine subclass doesn't implement addObjectFile.");
+}
+
 bool ExecutionEngine::removeModule(Module *M) {
   for(SmallVectorImpl<Module *>::iterator I = Modules.begin(),
         E = Modules.end(); I != E; ++I) {
diff --git a/lib/ExecutionEngine/MCJIT/MCJIT.cpp b/lib/ExecutionEngine/MCJIT/MCJIT.cpp
index 6b9dff238a..42cb4ea6d8 100644
--- a/lib/ExecutionEngine/MCJIT/MCJIT.cpp
+++ b/lib/ExecutionEngine/MCJIT/MCJIT.cpp
@@ -113,8 +113,8 @@ bool MCJIT::removeModule(Module *M) {
 
 
 
-void MCJIT::addObjectFile(object::ObjectFile *Obj) {
-  ObjectImage *LoadedObject = Dyld.loadObject(Obj);
+void MCJIT::addObjectFile(std::unique_ptr<object::ObjectFile> Obj) {
+  ObjectImage *LoadedObject = Dyld.loadObject(std::move(Obj));
   if (!LoadedObject || Dyld.hasError())
     report_fatal_error(Dyld.getErrorString());
 
@@ -308,10 +308,10 @@ uint64_t MCJIT::getSymbolAddress(const std::string &Name,
       std::unique_ptr<object::Binary> ChildBin;
       // FIXME: Support nested archives?
       if (!ChildIt->getAsBinary(ChildBin) && ChildBin->isObject()) {
-        object::ObjectFile *OF = reinterpret_cast<object::ObjectFile *>(
-                                                            ChildBin.release());
+        std::unique_ptr<object::ObjectFile> OF(
+            static_cast<object::ObjectFile *>(ChildBin.release()));
         // This causes the object file to be loaded.
-        addObjectFile(OF);
+        addObjectFile(std::move(OF));
         // The address should be here now.
         Addr = getExistingSymbolAddress(Name);
         if (Addr)
diff --git a/lib/ExecutionEngine/MCJIT/MCJIT.h b/lib/ExecutionEngine/MCJIT/MCJIT.h
index da1e975d4c..100e9a23fc 100644
--- a/lib/ExecutionEngine/MCJIT/MCJIT.h
+++ b/lib/ExecutionEngine/MCJIT/MCJIT.h
@@ -239,7 +239,7 @@ public:
   /// @name ExecutionEngine interface implementation
   /// @{
   void addModule(Module *M) override;
-  void addObjectFile(object::ObjectFile *O) override;
+  void addObjectFile(std::unique_ptr<object::ObjectFile> O) override;
   void addArchive(object::Archive *O) override;
   bool removeModule(Module *M) override;
 
diff --git a/lib/ExecutionEngine/RuntimeDyld/ObjectImageCommon.h b/lib/ExecutionEngine/RuntimeDyld/ObjectImageCommon.h
index f5a4ea9328..4917b93a96 100644
--- a/lib/ExecutionEngine/RuntimeDyld/ObjectImageCommon.h
+++ b/lib/ExecutionEngine/RuntimeDyld/ObjectImageCommon.h
@@ -18,6 +18,8 @@
 #include "llvm/ExecutionEngine/ObjectImage.h"
 #include "llvm/Object/ObjectFile.h"
 
+#include <memory>
+
 namespace llvm {
 
 namespace object {
@@ -30,13 +32,13 @@ class ObjectImageCommon : public ObjectImage {
   void anchor() override;
 
 protected:
-  object::ObjectFile *ObjFile;
+  std::unique_ptr<object::ObjectFile> ObjFile;
 
   // This form of the constructor allows subclasses to use
   // format-specific subclasses of ObjectFile directly
-  ObjectImageCommon(ObjectBuffer *Input, object::ObjectFile *Obj)
+  ObjectImageCommon(ObjectBuffer *Input, std::unique_ptr<object::ObjectFile> Obj)
   : ObjectImage(Input), // saves Input as Buffer and takes ownership
-    ObjFile(Obj)
+    ObjFile(std::move(Obj))
   {
   }
 
@@ -44,12 +46,13 @@ public:
   ObjectImageCommon(ObjectBuffer* Input)
   : ObjectImage(Input) // saves Input as Buffer and takes ownership
   {
-    ObjFile =
-        object::ObjectFile::createObjectFile(Buffer->getMemBuffer()).get();
+    // FIXME: error checking? createObjectFile returns an ErrorOr<ObjectFile*>
+    // and should probably be checked for failure.
+    ObjFile.reset(object::ObjectFile::createObjectFile(Buffer->getMemBuffer()).get());
   }
-  ObjectImageCommon(object::ObjectFile* Input)
-  : ObjectImage(nullptr), ObjFile(Input)  {}
-  virtual ~ObjectImageCommon() { delete ObjFile; }
+  ObjectImageCommon(std::unique_ptr<object::ObjectFile> Input)
+  : ObjectImage(nullptr), ObjFile(std::move(Input))  {}
+  virtual ~ObjectImageCommon() { }
 
   object::symbol_iterator begin_symbols() const override
       { return ObjFile->symbol_begin(); }
@@ -66,7 +69,7 @@ public:
 
   StringRef getData() const override { return ObjFile->getData(); }
 
-  object::ObjectFile* getObjectFile() const override { return ObjFile; }
+  object::ObjectFile* getObjectFile() const override { return ObjFile.get(); }
 
   // Subclasses can override these methods to update the image with loaded
   // addresses for sections and common symbols
diff --git a/lib/ExecutionEngine/RuntimeDyld/RuntimeDyld.cpp b/lib/ExecutionEngine/RuntimeDyld/RuntimeDyld.cpp
index cc2f29d9df..0956761187 100644
--- a/lib/ExecutionEngine/RuntimeDyld/RuntimeDyld.cpp
+++ b/lib/ExecutionEngine/RuntimeDyld/RuntimeDyld.cpp
@@ -516,7 +516,8 @@ void RuntimeDyldImpl::addRelocationForSymbol(const RelocationEntry &RE,
 }
 
 uint8_t *RuntimeDyldImpl::createStubFunction(uint8_t *Addr) {
-  if (Arch == Triple::aarch64 || Arch == Triple::aarch64_be) {
+  if (Arch == Triple::aarch64 || Arch == Triple::aarch64_be ||
+      Arch == Triple::arm64 || Arch == Triple::arm64_be) {
     // This stub has to be able to access the full address space,
     // since symbol lookup won't necessarily find a handy, in-range,
     // PLT stub for functions which could be anywhere.
@@ -698,21 +699,23 @@ createRuntimeDyldMachO(RTDyldMemoryManager *MM, bool ProcessAllSections) {
   return Dyld;
 }
 
-ObjectImage *RuntimeDyld::loadObject(ObjectFile *InputObject) {
+ObjectImage *RuntimeDyld::loadObject(std::unique_ptr<ObjectFile> InputObject) {
   std::unique_ptr<ObjectImage> InputImage;
 
+  ObjectFile &Obj = *InputObject;
+
   if (InputObject->isELF()) {
-    InputImage.reset(RuntimeDyldELF::createObjectImageFromFile(InputObject));
+    InputImage.reset(RuntimeDyldELF::createObjectImageFromFile(std::move(InputObject)));
     if (!Dyld)
       Dyld = createRuntimeDyldELF(MM, ProcessAllSections).release();
   } else if (InputObject->isMachO()) {
-    InputImage.reset(RuntimeDyldMachO::createObjectImageFromFile(InputObject));
+    InputImage.reset(RuntimeDyldMachO::createObjectImageFromFile(std::move(InputObject)));
     if (!Dyld)
       Dyld = createRuntimeDyldMachO(MM, ProcessAllSections).release();
   } else
     report_fatal_error("Incompatible object format!");
 
-  if (!Dyld->isCompatibleFile(InputObject))
+  if (!Dyld->isCompatibleFile(&Obj))
     report_fatal_error("Incompatible object format!");
 
   Dyld->loadObject(InputImage.get());
diff --git a/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldELF.cpp b/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldELF.cpp
index abe8b6c388..c9db976dcc 100644
--- a/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldELF.cpp
+++ b/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldELF.cpp
@@ -51,7 +51,12 @@ template <class ELFT> class DyldELFObject : public ELFObjectFile<ELFT> {
 
   typedef typename ELFDataTypeTypedefHelper<ELFT>::value_type addr_type;
 
+  std::unique_ptr<ObjectFile> UnderlyingFile;
+
 public:
+  DyldELFObject(std::unique_ptr<ObjectFile> UnderlyingFile,
+                MemoryBuffer *Wrapper, error_code &ec);
+
   DyldELFObject(MemoryBuffer *Wrapper, error_code &ec);
 
   void updateSectionAddress(const SectionRef &Sec, uint64_t Addr);
@@ -68,13 +73,11 @@ public:
 };
 
 template <class ELFT> class ELFObjectImage : public ObjectImageCommon {
-protected:
-  DyldELFObject<ELFT> *DyldObj;
   bool Registered;
 
 public:
-  ELFObjectImage(ObjectBuffer *Input, DyldELFObject<ELFT> *Obj)
-      : ObjectImageCommon(Input, Obj), DyldObj(Obj), Registered(false) {}
+  ELFObjectImage(ObjectBuffer *Input, std::unique_ptr<DyldELFObject<ELFT>> Obj)
+      : ObjectImageCommon(Input, std::move(Obj)), Registered(false) {}
 
   virtual ~ELFObjectImage() {
     if (Registered)
@@ -84,11 +87,13 @@ public:
   // Subclasses can override these methods to update the image with loaded
   // addresses for sections and common symbols
   void updateSectionAddress(const SectionRef &Sec, uint64_t Addr) override {
-    DyldObj->updateSectionAddress(Sec, Addr);
+    static_cast<DyldELFObject<ELFT>*>(getObjectFile())
+        ->updateSectionAddress(Sec, Addr);
   }
 
   void updateSymbolAddress(const SymbolRef &Sym, uint64_t Addr) override {
-    DyldObj->updateSymbolAddress(Sym, Addr);
+    static_cast<DyldELFObject<ELFT>*>(getObjectFile())
+        ->updateSymbolAddress(Sym, Addr);
   }
 
   void registerWithDebugger() override {
@@ -110,6 +115,14 @@ DyldELFObject<ELFT>::DyldELFObject(MemoryBuffer *Wrapper, error_code &ec)
 }
 
 template <class ELFT>
+DyldELFObject<ELFT>::DyldELFObject(std::unique_ptr<ObjectFile> UnderlyingFile,
+                                   MemoryBuffer *Wrapper, error_code &ec)
+    : ELFObjectFile<ELFT>(Wrapper, ec),
+      UnderlyingFile(std::move(UnderlyingFile)) {
+  this->isDyldELFObject = true;
+}
+
+template <class ELFT>
 void DyldELFObject<ELFT>::updateSectionAddress(const SectionRef &Sec,
                                                uint64_t Addr) {
   DataRefImpl ShdrRef = Sec.getRawDataRefImpl();
@@ -165,7 +178,7 @@ void RuntimeDyldELF::deregisterEHFrames() {
 }
 
 ObjectImage *
-RuntimeDyldELF::createObjectImageFromFile(object::ObjectFile *ObjFile) {
+RuntimeDyldELF::createObjectImageFromFile(std::unique_ptr<object::ObjectFile> ObjFile) {
   if (!ObjFile)
     return nullptr;
 
@@ -174,21 +187,27 @@ RuntimeDyldELF::createObjectImageFromFile(object::ObjectFile *ObjFile) {
       MemoryBuffer::getMemBuffer(ObjFile->getData(), "", false);
 
   if (ObjFile->getBytesInAddress() == 4 && ObjFile->isLittleEndian()) {
-    DyldELFObject<ELFType<support::little, 2, false>> *Obj =
-        new DyldELFObject<ELFType<support::little, 2, false>>(Buffer, ec);
-    return new ELFObjectImage<ELFType<support::little, 2, false>>(nullptr, Obj);
+    auto Obj =
+        llvm::make_unique<DyldELFObject<ELFType<support::little, 2, false>>>(
+            std::move(ObjFile), Buffer, ec);
+    return new ELFObjectImage<ELFType<support::little, 2, false>>(
+        nullptr, std::move(Obj));
   } else if (ObjFile->getBytesInAddress() == 4 && !ObjFile->isLittleEndian()) {
-    DyldELFObject<ELFType<support::big, 2, false>> *Obj =
-        new DyldELFObject<ELFType<support::big, 2, false>>(Buffer, ec);
-    return new ELFObjectImage<ELFType<support::big, 2, false>>(nullptr, Obj);
+    auto Obj =
+        llvm::make_unique<DyldELFObject<ELFType<support::big, 2, false>>>(
+            std::move(ObjFile), Buffer, ec);
+    return new ELFObjectImage<ELFType<support::big, 2, false>>(nullptr, std::move(Obj));
   } else if (ObjFile->getBytesInAddress() == 8 && !ObjFile->isLittleEndian()) {
-    DyldELFObject<ELFType<support::big, 2, true>> *Obj =
-        new DyldELFObject<ELFType<support::big, 2, true>>(Buffer, ec);
-    return new ELFObjectImage<ELFType<support::big, 2, true>>(nullptr, Obj);
+    auto Obj = llvm::make_unique<DyldELFObject<ELFType<support::big, 2, true>>>(
+        std::move(ObjFile), Buffer, ec);
+    return new ELFObjectImage<ELFType<support::big, 2, true>>(nullptr,
+                                                              std::move(Obj));
   } else if (ObjFile->getBytesInAddress() == 8 && ObjFile->isLittleEndian()) {
-    DyldELFObject<ELFType<support::little, 2, true>> *Obj =
-        new DyldELFObject<ELFType<support::little, 2, true>>(Buffer, ec);
-    return new ELFObjectImage<ELFType<support::little, 2, true>>(nullptr, Obj);
+    auto Obj =
+        llvm::make_unique<DyldELFObject<ELFType<support::little, 2, true>>>(
+            std::move(ObjFile), Buffer, ec);
+    return new ELFObjectImage<ELFType<support::little, 2, true>>(
+        nullptr, std::move(Obj));
   } else
     llvm_unreachable("Unexpected ELF format");
 }
@@ -202,28 +221,29 @@ ObjectImage *RuntimeDyldELF::createObjectImage(ObjectBuffer *Buffer) {
   error_code ec;
 
   if (Ident.first == ELF::ELFCLASS32 && Ident.second == ELF::ELFDATA2LSB) {
-    DyldELFObject<ELFType<support::little, 4, false>> *Obj =
-        new DyldELFObject<ELFType<support::little, 4, false>>(
+    auto Obj =
+        llvm::make_unique<DyldELFObject<ELFType<support::little, 4, false>>>(
             Buffer->getMemBuffer(), ec);
-    return new ELFObjectImage<ELFType<support::little, 4, false>>(Buffer, Obj);
+    return new ELFObjectImage<ELFType<support::little, 4, false>>(
+        Buffer, std::move(Obj));
   } else if (Ident.first == ELF::ELFCLASS32 &&
              Ident.second == ELF::ELFDATA2MSB) {
-    DyldELFObject<ELFType<support::big, 4, false>> *Obj =
-        new DyldELFObject<ELFType<support::big, 4, false>>(
+    auto Obj =
+        llvm::make_unique<DyldELFObject<ELFType<support::big, 4, false>>>(
             Buffer->getMemBuffer(), ec);
-    return new ELFObjectImage<ELFType<support::big, 4, false>>(Buffer, Obj);
+    return new ELFObjectImage<ELFType<support::big, 4, false>>(Buffer,
+                                                               std::move(Obj));
   } else if (Ident.first == ELF::ELFCLASS64 &&
              Ident.second == ELF::ELFDATA2MSB) {
-    DyldELFObject<ELFType<support::big, 8, true>> *Obj =
-        new DyldELFObject<ELFType<support::big, 8, true>>(
-            Buffer->getMemBuffer(), ec);
-    return new ELFObjectImage<ELFType<support::big, 8, true>>(Buffer, Obj);
+    auto Obj = llvm::make_unique<DyldELFObject<ELFType<support::big, 8, true>>>(
+        Buffer->getMemBuffer(), ec);
+    return new ELFObjectImage<ELFType<support::big, 8, true>>(Buffer, std::move(Obj));
   } else if (Ident.first == ELF::ELFCLASS64 &&
              Ident.second == ELF::ELFDATA2LSB) {
-    DyldELFObject<ELFType<support::little, 8, true>> *Obj =
-        new DyldELFObject<ELFType<support::little, 8, true>>(
+    auto Obj =
+        llvm::make_unique<DyldELFObject<ELFType<support::little, 8, true>>>(
             Buffer->getMemBuffer(), ec);
-    return new ELFObjectImage<ELFType<support::little, 8, true>>(Buffer, Obj);
+    return new ELFObjectImage<ELFType<support::little, 8, true>>(Buffer, std::move(Obj));
   } else
     llvm_unreachable("Unexpected ELF format");
 }
@@ -846,6 +866,8 @@ void RuntimeDyldELF::resolveRelocation(const SectionEntry &Section,
     break;
   case Triple::aarch64:
   case Triple::aarch64_be:
+  case Triple::arm64:
+  case Triple::arm64_be:
     resolveAArch64Relocation(Section, Offset, Value, Type, Addend);
     break;
   case Triple::arm: // Fall through.
@@ -951,7 +973,8 @@ relocation_iterator RuntimeDyldELF::processRelocationRef(
 
   DEBUG(dbgs() << "\t\tSectionID: " << SectionID << " Offset: " << Offset
                << "\n");
-  if (Arch == Triple::aarch64 &&
+  if ((Arch == Triple::aarch64 || Arch == Triple::aarch64_be ||
+       Arch == Triple::arm64 || Arch == Triple::arm64_be) &&
       (RelType == ELF::R_AARCH64_CALL26 || RelType == ELF::R_AARCH64_JUMP26)) {
     // This is an AArch64 branch relocation, need to use a stub function.
     DEBUG(dbgs() << "\t\tThis is an AArch64 branch relocation.");
@@ -1299,6 +1322,9 @@ size_t RuntimeDyldELF::getGOTEntrySize() {
   switch (Arch) {
   case Triple::x86_64:
   case Triple::aarch64:
+  case Triple::aarch64_be:
+  case Triple::arm64:
+  case Triple::arm64_be:
   case Triple::ppc64:
   case Triple::ppc64le:
   case Triple::systemz:
diff --git a/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldELF.h b/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldELF.h
index 27db5cdf42..a56bd0cb3e 100644
--- a/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldELF.h
+++ b/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldELF.h
@@ -59,7 +59,8 @@ class RuntimeDyldELF : public RuntimeDyldImpl {
                                 uint64_t Value, uint32_t Type, int64_t Addend);
 
   unsigned getMaxStubSize() override {
-    if (Arch == Triple::aarch64)
+    if (Arch == Triple::aarch64 || Arch == Triple::arm64 ||
+        Arch == Triple::aarch64_be || Arch == Triple::arm64_be)
       return 20; // movz; movk; movk; movk; br
     if (Arch == Triple::arm || Arch == Triple::thumb)
       return 8; // 32-bit instruction and 32-bit address
@@ -119,7 +120,7 @@ public:
   virtual ~RuntimeDyldELF();
 
   static ObjectImage *createObjectImage(ObjectBuffer *InputBuffer);
-  static ObjectImage *createObjectImageFromFile(object::ObjectFile *Obj);
+  static ObjectImage *createObjectImageFromFile(std::unique_ptr<object::ObjectFile> Obj);
 };
 
 } // end namespace llvm
diff --git a/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldMachO.h b/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldMachO.h
index 1006176753..85d6501a26 100644
--- a/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldMachO.h
+++ b/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldMachO.h
@@ -88,8 +88,8 @@ public:
   }
 
   static ObjectImage *
-  createObjectImageFromFile(object::ObjectFile *InputObject) {
-    return new ObjectImageCommon(InputObject);
+  createObjectImageFromFile(std::unique_ptr<object::ObjectFile> InputObject) {
+    return new ObjectImageCommon(std::move(InputObject));
   }
 };
 
diff --git a/lib/IR/ConstantsContext.h b/lib/IR/ConstantsContext.h
index 8aae14aabf..f06509fb73 100644
--- a/lib/IR/ConstantsContext.h
+++ b/lib/IR/ConstantsContext.h
@@ -24,6 +24,7 @@
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/raw_ostream.h"
 #include <map>
+#include <tuple>
 
 #define DEBUG_TYPE "ir"
 
diff --git a/lib/IR/Core.cpp b/lib/IR/Core.cpp
index a843b9f602..e5b98b89db 100644
--- a/lib/IR/Core.cpp
+++ b/lib/IR/Core.cpp
@@ -31,6 +31,7 @@
 #include "llvm/PassManager.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/ErrorHandling.h"
+#include "llvm/Support/FileSystem.h"
 #include "llvm/Support/ManagedStatic.h"
 #include "llvm/Support/MemoryBuffer.h"
 #include "llvm/Support/Threading.h"
diff --git a/lib/IR/Instructions.cpp b/lib/IR/Instructions.cpp
index 5b93c5323a..e8bcddbd99 100644
--- a/lib/IR/Instructions.cpp
+++ b/lib/IR/Instructions.cpp
@@ -3587,9 +3587,10 @@ InsertValueInst *InsertValueInst::clone_impl() const {
 }
 
 AllocaInst *AllocaInst::clone_impl() const {
-  return new AllocaInst(getAllocatedType(),
-                        (Value*)getOperand(0),
-                        getAlignment());
+  AllocaInst *Result = new AllocaInst(getAllocatedType(),
+                                      (Value *)getOperand(0), getAlignment());
+  Result->setUsedWithInAlloca(isUsedWithInAlloca());
+  return Result;
 }
 
 LoadInst *LoadInst::clone_impl() const {
diff --git a/lib/MC/ELFObjectWriter.cpp b/lib/MC/ELFObjectWriter.cpp
index 68e28cf4d4..ebcc691f0a 100644
--- a/lib/MC/ELFObjectWriter.cpp
+++ b/lib/MC/ELFObjectWriter.cpp
@@ -28,6 +28,7 @@
 #include "llvm/MC/MCObjectWriter.h"
 #include "llvm/MC/MCSectionELF.h"
 #include "llvm/MC/MCValue.h"
+#include "llvm/Object/StringTableBuilder.h"
 #include "llvm/Support/Compression.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/Endian.h"
@@ -132,11 +133,11 @@ class ELFObjectWriter : public MCObjectWriter {
       MCSymbolData *SymbolData;
       uint64_t StringIndex;
       uint32_t SectionIndex;
+      StringRef Name;
 
       // Support lexicographic sorting.
       bool operator<(const ELFSymbolData &RHS) const {
-        return SymbolData->getSymbol().getName() <
-               RHS.SymbolData->getSymbol().getName();
+        return Name < RHS.Name;
       }
     };
 
@@ -149,13 +150,13 @@ class ELFObjectWriter : public MCObjectWriter {
 
     llvm::DenseMap<const MCSectionData *, std::vector<ELFRelocationEntry>>
     Relocations;
-    DenseMap<const MCSection*, uint64_t> SectionStringTableIndex;
+    StringTableBuilder ShStrTabBuilder;
 
     /// @}
     /// @name Symbol Table Data
     /// @{
 
-    SmallString<256> StringTable;
+    StringTableBuilder StrTabBuilder;
     std::vector<uint64_t> FileSymbolData;
     std::vector<ELFSymbolData> LocalSymbolData;
     std::vector<ELFSymbolData> ExternalSymbolData;
@@ -215,7 +216,8 @@ class ELFObjectWriter : public MCObjectWriter {
                           const MCAsmLayout &Layout,
                           SectionIndexMapTy &SectionIndexMap);
 
-    bool shouldRelocateWithSymbol(const MCSymbolRefExpr *RefA,
+    bool shouldRelocateWithSymbol(const MCAssembler &Asm,
+                                  const MCSymbolRefExpr *RefA,
                                   const MCSymbolData *SD, uint64_t C,
                                   unsigned Type) const;
 
@@ -486,6 +488,7 @@ void ELFObjectWriter::WriteHeader(const MCAssembler &Asm,
 
 uint64_t ELFObjectWriter::SymbolValue(MCSymbolData &OrigData,
                                       const MCAsmLayout &Layout) {
+  const MCSymbol &OrigSymbol = OrigData.getSymbol();
   MCSymbolData *Data = &OrigData;
   if (Data->isCommon() && Data->isExternal())
     return Data->getCommonAlignment();
@@ -496,7 +499,7 @@ uint64_t ELFObjectWriter::SymbolValue(MCSymbolData &OrigData,
   if (Symbol->isVariable()) {
     const MCExpr *Expr = Symbol->getVariableValue();
     MCValue Value;
-    if (!Expr->EvaluateAsRelocatable(Value, &Layout))
+    if (!Expr->EvaluateAsValue(Value, &Layout))
       llvm_unreachable("Invalid expression");
 
     assert(!Value.getSymB());
@@ -512,8 +515,8 @@ uint64_t ELFObjectWriter::SymbolValue(MCSymbolData &OrigData,
     }
   }
 
-  if ((Data && Data->getFlags() & ELF_Other_ThumbFunc) ||
-      OrigData.getFlags() & ELF_Other_ThumbFunc)
+  const MCAssembler &Asm = Layout.getAssembler();
+  if (Asm.isThumbFunc(&OrigSymbol))
     Res |= 1;
 
   if (!Symbol || !Symbol->isInSection())
@@ -606,7 +609,7 @@ static const MCSymbol *getBaseSymbol(const MCAsmLayout &Layout,
 
   const MCExpr *Expr = Symbol.getVariableValue();
   MCValue Value;
-  if (!Expr->EvaluateAsRelocatable(Value, &Layout))
+  if (!Expr->EvaluateAsValue(Value, &Layout))
     llvm_unreachable("Invalid Expression");
   const MCSymbolRefExpr *RefB = Value.getSymB();
   if (RefB) {
@@ -641,8 +644,6 @@ void ELFObjectWriter::WriteSymbol(SymbolTableWriter &Writer, ELFSymbolData &MSD,
     BaseSD = &Layout.getAssembler().getSymbolData(*Base);
     Type = mergeTypeForSet(Type, MCELF::GetType(*BaseSD));
   }
-  if (OrigData.getFlags() & ELF_Other_ThumbFunc)
-    Type = ELF::STT_FUNC;
   uint8_t Info = (Binding << ELF_STB_Shift) | (Type << ELF_STT_Shift);
 
   // Other and Visibility share the same byte with Visibility using the lower
@@ -676,7 +677,6 @@ void ELFObjectWriter::WriteSymbolTable(MCDataFragment *SymtabF,
                                        SectionIndexMapTy &SectionIndexMap) {
   // The string table must be emitted first because we need the index
   // into the string table for all the symbol names.
-  assert(StringTable.size() && "Missing string table");
 
   // FIXME: Make sure the start of the symbol table is aligned.
 
@@ -737,7 +737,8 @@ void ELFObjectWriter::WriteSymbolTable(MCDataFragment *SymtabF,
 // It is always valid to create a relocation with a symbol. It is preferable
 // to use a relocation with a section if that is possible. Using the section
 // allows us to omit some local symbols from the symbol table.
-bool ELFObjectWriter::shouldRelocateWithSymbol(const MCSymbolRefExpr *RefA,
+bool ELFObjectWriter::shouldRelocateWithSymbol(const MCAssembler &Asm,
+                                               const MCSymbolRefExpr *RefA,
                                                const MCSymbolData *SD,
                                                uint64_t C,
                                                unsigned Type) const {
@@ -825,7 +826,7 @@ bool ELFObjectWriter::shouldRelocateWithSymbol(const MCSymbolRefExpr *RefA,
   // bit. With a symbol that is done by just having the symbol have that bit
   // set, so we would lose the bit if we relocated with the section.
   // FIXME: We could use the section but add the bit to the relocation value.
-  if (SD->getFlags() & ELF_Other_ThumbFunc)
+  if (Asm.isThumbFunc(&Sym))
     return true;
 
   if (TargetObjectWriter->needsRelocateWithSymbol(Type))
@@ -887,7 +888,7 @@ void ELFObjectWriter::RecordRelocation(const MCAssembler &Asm,
   const MCSymbolData *SymAD = SymA ? &Asm.getSymbolData(*SymA) : nullptr;
 
   unsigned Type = GetRelocType(Target, Fixup, IsPCRel);
-  bool RelocateWithSymbol = shouldRelocateWithSymbol(RefA, SymAD, C, Type);
+  bool RelocateWithSymbol = shouldRelocateWithSymbol(Asm, RefA, SymAD, C, Type);
   if (!RelocateWithSymbol && SymA && !SymA->isUndefined())
     C += Layout.getSymbolOffset(SymAD);
 
@@ -1030,27 +1031,6 @@ ELFObjectWriter::computeSymbolTable(MCAssembler &Asm, const MCAsmLayout &Layout,
     MCELF::SetBinding(Data, ELF::STB_GLOBAL);
   }
 
-  // Index 0 is always the empty string.
-  StringMap<uint64_t> StringIndexMap;
-  StringTable += '\x00';
-
-  // FIXME: We could optimize suffixes in strtab in the same way we
-  // optimize them in shstrtab.
-
-  for (MCAssembler::const_file_name_iterator it = Asm.file_names_begin(),
-                                            ie = Asm.file_names_end();
-                                            it != ie;
-                                            ++it) {
-    StringRef Name = *it;
-    uint64_t &Entry = StringIndexMap[Name];
-    if (!Entry) {
-      Entry = StringTable.size();
-      StringTable += Name;
-      StringTable += '\x00';
-    }
-    FileSymbolData.push_back(Entry);
-  }
-
   // Add the data for the symbols.
   for (MCSymbolData &SD : Asm.symbols()) {
     const MCSymbol &Symbol = SD.getSymbol();
@@ -1101,7 +1081,6 @@ ELFObjectWriter::computeSymbolTable(MCAssembler &Asm, const MCAsmLayout &Layout,
     // @@ in defined ones.
     StringRef Name = Symbol.getName();
     SmallString<32> Buf;
-
     size_t Pos = Name.find("@@@");
     if (Pos != StringRef::npos) {
       Buf += Name.substr(0, Pos);
@@ -1109,14 +1088,8 @@ ELFObjectWriter::computeSymbolTable(MCAssembler &Asm, const MCAsmLayout &Layout,
       Buf += Name.substr(Pos + Skip);
       Name = Buf;
     }
+    MSD.Name = StrTabBuilder.add(Name);
 
-    uint64_t &Entry = StringIndexMap[Name];
-    if (!Entry) {
-      Entry = StringTable.size();
-      StringTable += Name;
-      StringTable += '\x00';
-    }
-    MSD.StringIndex = Entry;
     if (MSD.SectionIndex == ELF::SHN_UNDEF)
       UndefinedSymbolData.push_back(MSD);
     else if (Local)
@@ -1125,6 +1098,21 @@ ELFObjectWriter::computeSymbolTable(MCAssembler &Asm, const MCAsmLayout &Layout,
       ExternalSymbolData.push_back(MSD);
   }
 
+  for (auto i = Asm.file_names_begin(), e = Asm.file_names_end(); i != e; ++i)
+    StrTabBuilder.add(*i);
+
+  StrTabBuilder.finalize();
+
+  for (auto i = Asm.file_names_begin(), e = Asm.file_names_end(); i != e; ++i)
+    FileSymbolData.push_back(StrTabBuilder.getOffset(*i));
+
+  for (ELFSymbolData& MSD : LocalSymbolData)
+    MSD.StringIndex = StrTabBuilder.getOffset(MSD.Name);
+  for (ELFSymbolData& MSD : ExternalSymbolData)
+    MSD.StringIndex = StrTabBuilder.getOffset(MSD.Name);
+  for (ELFSymbolData& MSD : UndefinedSymbolData)
+    MSD.StringIndex = StrTabBuilder.getOffset(MSD.Name);
+
   // Symbols are required to be in lexicographic order.
   array_pod_sort(LocalSymbolData.begin(), LocalSymbolData.end());
   array_pod_sort(ExternalSymbolData.begin(), ExternalSymbolData.end());
@@ -1435,23 +1423,6 @@ void ELFObjectWriter::WriteRelocationsFragment(const MCAssembler &Asm,
   }
 }
 
-static int compareBySuffix(const MCSectionELF *const *a,
-                           const MCSectionELF *const *b) {
-  const StringRef &NameA = (*a)->getSectionName();
-  const StringRef &NameB = (*b)->getSectionName();
-  const unsigned sizeA = NameA.size();
-  const unsigned sizeB = NameB.size();
-  const unsigned len = std::min(sizeA, sizeB);
-  for (unsigned int i = 0; i < len; ++i) {
-    char ca = NameA[sizeA - i - 1];
-    char cb = NameB[sizeB - i - 1];
-    if (ca != cb)
-      return cb - ca;
-  }
-
-  return sizeB - sizeA;
-}
-
 void ELFObjectWriter::CreateMetadataSections(MCAssembler &Asm,
                                              MCAsmLayout &Layout,
                                              SectionIndexMapTy &SectionIndexMap,
@@ -1492,45 +1463,20 @@ void ELFObjectWriter::CreateMetadataSections(MCAssembler &Asm,
   WriteSymbolTable(F, Asm, Layout, SectionIndexMap);
 
   F = new MCDataFragment(&StrtabSD);
-  F->getContents().append(StringTable.begin(), StringTable.end());
+  F->getContents().append(StrTabBuilder.data().begin(),
+                          StrTabBuilder.data().end());
 
   F = new MCDataFragment(&ShstrtabSD);
 
-  std::vector<const MCSectionELF*> Sections;
-  for (MCAssembler::const_iterator it = Asm.begin(),
-         ie = Asm.end(); it != ie; ++it) {
+  // Section header string table.
+  for (auto it = Asm.begin(), ie = Asm.end(); it != ie; ++it) {
     const MCSectionELF &Section =
       static_cast<const MCSectionELF&>(it->getSection());
-    Sections.push_back(&Section);
-  }
-  array_pod_sort(Sections.begin(), Sections.end(), compareBySuffix);
-
-  // Section header string table.
-  //
-  // The first entry of a string table holds a null character so skip
-  // section 0.
-  uint64_t Index = 1;
-  F->getContents().push_back('\x00');
-
-  for (unsigned int I = 0, E = Sections.size(); I != E; ++I) {
-    const MCSectionELF &Section = *Sections[I];
-
-    StringRef Name = Section.getSectionName();
-    if (I != 0) {
-      StringRef PreviousName = Sections[I - 1]->getSectionName();
-      if (PreviousName.endswith(Name)) {
-        SectionStringTableIndex[&Section] = Index - Name.size() - 1;
-        continue;
-      }
-    }
-    // Remember the index into the string table so we can write it
-    // into the sh_name field of the section header table.
-    SectionStringTableIndex[&Section] = Index;
-
-    Index += Name.size() + 1;
-    F->getContents().append(Name.begin(), Name.end());
-    F->getContents().push_back('\x00');
+    ShStrTabBuilder.add(Section.getSectionName());
   }
+  ShStrTabBuilder.finalize();
+  F->getContents().append(ShStrTabBuilder.data().begin(),
+                          ShStrTabBuilder.data().end());
 }
 
 void ELFObjectWriter::CreateIndexedSections(MCAssembler &Asm,
@@ -1598,7 +1544,7 @@ void ELFObjectWriter::WriteSection(MCAssembler &Asm,
 
   switch(Section.getType()) {
   case ELF::SHT_DYNAMIC:
-    sh_link = SectionStringTableIndex[&Section];
+    sh_link = ShStrTabBuilder.getOffset(Section.getSectionName());
     sh_info = 0;
     break;
 
@@ -1679,7 +1625,8 @@ void ELFObjectWriter::WriteSection(MCAssembler &Asm,
     }
   }
 
-  WriteSecHdrEntry(SectionStringTableIndex[&Section], Section.getType(),
+  WriteSecHdrEntry(ShStrTabBuilder.getOffset(Section.getSectionName()),
+                   Section.getType(),
                    Section.getFlags(), 0, Offset, Size, sh_link, sh_info,
                    Alignment, Section.getEntrySize());
 }
diff --git a/lib/MC/MCAssembler.cpp b/lib/MC/MCAssembler.cpp
index b3b2bb3d31..a96e4ba151 100644
--- a/lib/MC/MCAssembler.cpp
+++ b/lib/MC/MCAssembler.cpp
@@ -27,7 +27,7 @@
 #include "llvm/Support/LEB128.h"
 #include "llvm/Support/TargetRegistry.h"
 #include "llvm/Support/raw_ostream.h"
-
+#include <tuple>
 using namespace llvm;
 
 #define DEBUG_TYPE "assembler"
@@ -117,36 +117,38 @@ uint64_t MCAsmLayout::getFragmentOffset(const MCFragment *F) const {
   return F->Offset;
 }
 
+// Simple getSymbolOffset helper for the non-varibale case.
+static uint64_t getLabelOffset(const MCAsmLayout &Layout,
+                               const MCSymbolData &SD) {
+  if (!SD.getFragment())
+    report_fatal_error("unable to evaluate offset to undefined symbol '" +
+                       SD.getSymbol().getName() + "'");
+  return Layout.getFragmentOffset(SD.getFragment()) + SD.getOffset();
+}
+
 uint64_t MCAsmLayout::getSymbolOffset(const MCSymbolData *SD) const {
   const MCSymbol &S = SD->getSymbol();
 
-  // If this is a variable, then recursively evaluate now.
-  if (S.isVariable()) {
-    MCValue Target;
-    if (!S.getVariableValue()->EvaluateAsRelocatable(Target, this))
-      report_fatal_error("unable to evaluate offset for variable '" +
-                         S.getName() + "'");
-
-    // Verify that any used symbols are defined.
-    if (Target.getSymA() && Target.getSymA()->getSymbol().isUndefined())
-      report_fatal_error("unable to evaluate offset to undefined symbol '" +
-                         Target.getSymA()->getSymbol().getName() + "'");
-    if (Target.getSymB() && Target.getSymB()->getSymbol().isUndefined())
-      report_fatal_error("unable to evaluate offset to undefined symbol '" +
-                         Target.getSymB()->getSymbol().getName() + "'");
-
-    uint64_t Offset = Target.getConstant();
-    if (Target.getSymA())
-      Offset += getSymbolOffset(&Assembler.getSymbolData(
-                                  Target.getSymA()->getSymbol()));
-    if (Target.getSymB())
-      Offset -= getSymbolOffset(&Assembler.getSymbolData(
-                                  Target.getSymB()->getSymbol()));
-    return Offset;
-  }
+  if (!S.isVariable())
+    return getLabelOffset(*this, *SD);
+
+  // If SD is a variable, evaluate it.
+  MCValue Target;
+  if (!S.getVariableValue()->EvaluateAsValue(Target, this))
+    report_fatal_error("unable to evaluate offset for variable '" +
+                       S.getName() + "'");
 
-  assert(SD->getFragment() && "Invalid getOffset() on undefined symbol!");
-  return getFragmentOffset(SD->getFragment()) + SD->getOffset();
+  uint64_t Offset = Target.getConstant();
+
+  const MCSymbolRefExpr *A = Target.getSymA();
+  if (A)
+    Offset += getLabelOffset(*this, Assembler.getSymbolData(A->getSymbol()));
+
+  const MCSymbolRefExpr *B = Target.getSymB();
+  if (B)
+    Offset -= getLabelOffset(*this, Assembler.getSymbolData(B->getSymbol()));
+
+  return Offset;
 }
 
 uint64_t MCAsmLayout::getSectionAddressSize(const MCSectionData *SD) const {
@@ -323,6 +325,31 @@ void MCAssembler::reset() {
   getLOHContainer().reset();
 }
 
+bool MCAssembler::isThumbFunc(const MCSymbol *Symbol) const {
+  if (ThumbFuncs.count(Symbol))
+    return true;
+
+  if (!Symbol->isVariable())
+    return false;
+
+  // FIXME: It looks like gas supports some cases of the form "foo + 2". It
+  // is not clear if that is a bug or a feature.
+  const MCExpr *Expr = Symbol->getVariableValue();
+  const MCSymbolRefExpr *Ref = dyn_cast<MCSymbolRefExpr>(Expr);
+  if (!Ref)
+    return false;
+
+  if (Ref->getKind() != MCSymbolRefExpr::VK_None)
+    return false;
+
+  const MCSymbol &Sym = Ref->getSymbol();
+  if (!isThumbFunc(&Sym))
+    return false;
+
+  ThumbFuncs.insert(Symbol); // Cache it.
+  return true;
+}
+
 bool MCAssembler::isSymbolLinkerVisible(const MCSymbol &Symbol) const {
   // Non-temporary labels should always be visible to the linker.
   if (!Symbol.isTemporary())
diff --git a/lib/MC/MCExpr.cpp b/lib/MC/MCExpr.cpp
index 300613530a..60b14ad53e 100644
--- a/lib/MC/MCExpr.cpp
+++ b/lib/MC/MCExpr.cpp
@@ -285,6 +285,8 @@ MCSymbolRefExpr::getVariantKindForName(StringRef Name) {
     .Case("gotoff", VK_GOTOFF)
     .Case("GOTPCREL", VK_GOTPCREL)
     .Case("gotpcrel", VK_GOTPCREL)
+    .Case("GOT_PREL", VK_GOTPCREL)
+    .Case("got_prel", VK_GOTPCREL)
     .Case("GOTTPOFF", VK_GOTTPOFF)
     .Case("gottpoff", VK_GOTTPOFF)
     .Case("INDNTPOFF", VK_INDNTPOFF)
@@ -478,7 +480,8 @@ bool MCExpr::EvaluateAsAbsolute(int64_t &Res, const MCAssembler *Asm,
   // absolutize differences across sections and that is what the MachO writer
   // uses Addrs for.
   bool IsRelocatable =
-    EvaluateAsRelocatableImpl(Value, Asm, Layout, Addrs, /*InSet*/ Addrs);
+      EvaluateAsRelocatableImpl(Value, Asm, Layout, Addrs, /*InSet*/ Addrs,
+                                /*ForceVarExpansion*/ false);
 
   // Record the current value.
   Res = Value.getConstant();
@@ -629,14 +632,20 @@ static bool EvaluateSymbolicAdd(const MCAssembler *Asm,
 bool MCExpr::EvaluateAsRelocatable(MCValue &Res,
                                    const MCAsmLayout *Layout) const {
   MCAssembler *Assembler = Layout ? &Layout->getAssembler() : nullptr;
-  return EvaluateAsRelocatableImpl(Res, Assembler, Layout, nullptr, false);
+  return EvaluateAsRelocatableImpl(Res, Assembler, Layout, nullptr, false,
+                                   /*ForceVarExpansion*/ false);
 }
 
-bool MCExpr::EvaluateAsRelocatableImpl(MCValue &Res,
-                                       const MCAssembler *Asm,
+bool MCExpr::EvaluateAsValue(MCValue &Res, const MCAsmLayout *Layout) const {
+  MCAssembler *Assembler = Layout ? &Layout->getAssembler() : nullptr;
+  return EvaluateAsRelocatableImpl(Res, Assembler, Layout, nullptr, false,
+                                   /*ForceVarExpansion*/ true);
+}
+
+bool MCExpr::EvaluateAsRelocatableImpl(MCValue &Res, const MCAssembler *Asm,
                                        const MCAsmLayout *Layout,
-                                       const SectionAddrMap *Addrs,
-                                       bool InSet) const {
+                                       const SectionAddrMap *Addrs, bool InSet,
+                                       bool ForceVarExpansion) const {
   ++stats::MCExprEvaluate;
 
   switch (getKind()) {
@@ -649,13 +658,14 @@ bool MCExpr::EvaluateAsRelocatableImpl(MCValue &Res,
 
   case SymbolRef: {
     const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(this);
+    bool IsWeakRef = SRE->getKind() == MCSymbolRefExpr::VK_WEAKREF;
     const MCSymbol &Sym = SRE->getSymbol();
     const MCAsmInfo &MCAsmInfo = SRE->getMCAsmInfo();
 
     // Evaluate recursively if this is a variable.
-    if (Sym.isVariable()) {
-      if (Sym.getVariableValue()->EvaluateAsRelocatableImpl(Res, Asm, Layout,
-                                                            Addrs, true)) {
+    if (Sym.isVariable() && !IsWeakRef) {
+      if (Sym.getVariableValue()->EvaluateAsRelocatableImpl(
+              Res, Asm, Layout, Addrs, true, ForceVarExpansion)) {
         const MCSymbolRefExpr *A = Res.getSymA();
         const MCSymbolRefExpr *B = Res.getSymB();
 
@@ -669,9 +679,10 @@ bool MCExpr::EvaluateAsRelocatableImpl(MCValue &Res,
           if (!A && !B)
             return true;
         } else {
+          if (ForceVarExpansion)
+            return true;
           bool IsSymbol = A && A->getSymbol().isDefined();
-          bool IsWeakRef = SRE->getKind() == MCSymbolRefExpr::VK_WEAKREF;
-          if (!IsSymbol && !IsWeakRef)
+          if (!IsSymbol)
             return true;
         }
       }
@@ -685,8 +696,8 @@ bool MCExpr::EvaluateAsRelocatableImpl(MCValue &Res,
     const MCUnaryExpr *AUE = cast<MCUnaryExpr>(this);
     MCValue Value;
 
-    if (!AUE->getSubExpr()->EvaluateAsRelocatableImpl(Value, Asm, Layout,
-                                                      Addrs, InSet))
+    if (!AUE->getSubExpr()->EvaluateAsRelocatableImpl(Value, Asm, Layout, Addrs,
+                                                      InSet, ForceVarExpansion))
       return false;
 
     switch (AUE->getOpcode()) {
@@ -719,10 +730,10 @@ bool MCExpr::EvaluateAsRelocatableImpl(MCValue &Res,
     const MCBinaryExpr *ABE = cast<MCBinaryExpr>(this);
     MCValue LHSValue, RHSValue;
 
-    if (!ABE->getLHS()->EvaluateAsRelocatableImpl(LHSValue, Asm, Layout,
-                                                  Addrs, InSet) ||
-        !ABE->getRHS()->EvaluateAsRelocatableImpl(RHSValue, Asm, Layout,
-                                                  Addrs, InSet))
+    if (!ABE->getLHS()->EvaluateAsRelocatableImpl(LHSValue, Asm, Layout, Addrs,
+                                                  InSet, ForceVarExpansion) ||
+        !ABE->getRHS()->EvaluateAsRelocatableImpl(RHSValue, Asm, Layout, Addrs,
+                                                  InSet, ForceVarExpansion))
       return false;
 
     // We only support a few operations on non-constant expressions, handle
diff --git a/lib/MC/MCMachOStreamer.cpp b/lib/MC/MCMachOStreamer.cpp
index 23d28b62ca..c103e41e3a 100644
--- a/lib/MC/MCMachOStreamer.cpp
+++ b/lib/MC/MCMachOStreamer.cpp
@@ -237,10 +237,6 @@ void MCMachOStreamer::EmitThumbFunc(MCSymbol *Symbol) {
   // Remember that the function is a thumb function. Fixup and relocation
   // values will need adjusted.
   getAssembler().setIsThumbFunc(Symbol);
-
-  // Mark the thumb bit on the symbol.
-  MCSymbolData &SD = getAssembler().getOrCreateSymbolData(*Symbol);
-  SD.setFlags(SD.getFlags() | SF_ThumbFunc);
 }
 
 bool MCMachOStreamer::EmitSymbolAttribute(MCSymbol *Symbol,
diff --git a/lib/MC/MCModuleYAML.cpp b/lib/MC/MCModuleYAML.cpp
index 93180b918d..f81cb149d8 100644
--- a/lib/MC/MCModuleYAML.cpp
+++ b/lib/MC/MCModuleYAML.cpp
@@ -19,6 +19,7 @@
 #include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/Object/YAML.h"
 #include "llvm/Support/Allocator.h"
+#include "llvm/Support/Casting.h"
 #include "llvm/Support/MathExtras.h"
 #include "llvm/Support/YAMLTraits.h"
 #include <vector>
diff --git a/lib/MC/MCObjectFileInfo.cpp b/lib/MC/MCObjectFileInfo.cpp
index ba132f450f..4abdde1aa1 100644
--- a/lib/MC/MCObjectFileInfo.cpp
+++ b/lib/MC/MCObjectFileInfo.cpp
@@ -291,7 +291,8 @@ void MCObjectFileInfo::InitELFMCObjectFileInfo(Triple T) {
     }
   } else if (T.getArch() == Triple::aarch64 ||
              T.getArch() == Triple::aarch64_be ||
-             T.getArch() == Triple::arm64) {
+             T.getArch() == Triple::arm64 ||
+             T.getArch() == Triple::arm64_be) {
     // The small model guarantees static code/data size < 4GB, but not where it
     // will be in memory. Most of these could end up >2GB away so even a signed
     // pc-relative 32-bit address is insufficient, theoretically.
diff --git a/lib/MC/MCParser/AsmParser.cpp b/lib/MC/MCParser/AsmParser.cpp
index bad28ef87d..633d101248 100644
--- a/lib/MC/MCParser/AsmParser.cpp
+++ b/lib/MC/MCParser/AsmParser.cpp
@@ -39,6 +39,7 @@
 #include "llvm/Support/SourceMgr.h"
 #include "llvm/Support/raw_ostream.h"
 #include <cctype>
+#include <deque>
 #include <set>
 #include <string>
 #include <vector>
diff --git a/lib/MC/MCParser/DarwinAsmParser.cpp b/lib/MC/MCParser/DarwinAsmParser.cpp
index 873a87d413..f74b30a4f1 100644
--- a/lib/MC/MCParser/DarwinAsmParser.cpp
+++ b/lib/MC/MCParser/DarwinAsmParser.cpp
@@ -17,6 +17,7 @@
 #include "llvm/MC/MCSectionMachO.h"
 #include "llvm/MC/MCStreamer.h"
 #include "llvm/MC/MCSymbol.h"
+#include "llvm/Support/FileSystem.h"
 #include "llvm/Support/MemoryBuffer.h"
 #include "llvm/Support/SourceMgr.h"
 using namespace llvm;
diff --git a/lib/MC/MachObjectWriter.cpp b/lib/MC/MachObjectWriter.cpp
index b4e53be7d5..cbaf0b87d6 100644
--- a/lib/MC/MachObjectWriter.cpp
+++ b/lib/MC/MachObjectWriter.cpp
@@ -351,6 +351,9 @@ void MachObjectWriter::WriteNlist(MachSymbolData &MSD,
     }
   }
 
+  if (Layout.getAssembler().isThumbFunc(&Symbol))
+    Flags |= SF_ThumbFunc;
+
   // struct nlist (12 bytes)
 
   Write32(MSD.StringIndex);
diff --git a/lib/Object/CMakeLists.txt b/lib/Object/CMakeLists.txt
index dc182966ae..cd8c9efe7b 100644
--- a/lib/Object/CMakeLists.txt
+++ b/lib/Object/CMakeLists.txt
@@ -12,6 +12,7 @@ add_llvm_library(LLVMObject
   MachOUniversal.cpp
   Object.cpp
   ObjectFile.cpp
+  StringTableBuilder.cpp
   SymbolicFile.cpp
   YAML.cpp
   )
diff --git a/lib/Object/ELFYAML.cpp b/lib/Object/ELFYAML.cpp
index 4b6522448c..4f0da24e40 100644
--- a/lib/Object/ELFYAML.cpp
+++ b/lib/Object/ELFYAML.cpp
@@ -12,6 +12,7 @@
 //===----------------------------------------------------------------------===//
 
 #include "llvm/Object/ELFYAML.h"
+#include "llvm/Support/Casting.h"
 
 namespace llvm {
 
diff --git a/lib/Object/StringTableBuilder.cpp b/lib/Object/StringTableBuilder.cpp
new file mode 100644
index 0000000000..9152834a29
--- /dev/null
+++ b/lib/Object/StringTableBuilder.cpp
@@ -0,0 +1,51 @@
+//===-- StringTableBuilder.cpp - String table building utility ------------===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+
+#include "llvm/ADT/SmallVector.h"
+#include "llvm/Object/StringTableBuilder.h"
+
+using namespace llvm;
+
+static bool compareBySuffix(StringRef a, StringRef b) {
+  size_t sizeA = a.size();
+  size_t sizeB = b.size();
+  size_t len = std::min(sizeA, sizeB);
+  for (size_t i = 0; i < len; ++i) {
+    char ca = a[sizeA - i - 1];
+    char cb = b[sizeB - i - 1];
+    if (ca != cb)
+      return ca > cb;
+  }
+  return sizeA > sizeB;
+}
+
+void StringTableBuilder::finalize() {
+  SmallVector<StringRef, 8> Strings;
+  for (auto i = StringIndexMap.begin(), e = StringIndexMap.end(); i != e; ++i)
+    Strings.push_back(i->getKey());
+
+  std::sort(Strings.begin(), Strings.end(), compareBySuffix);
+
+  // FIXME: Starting with a null byte is ELF specific. Generalize this so we
+  // can use the class with other object formats.
+  StringTable += '\x00';
+
+  StringRef Previous;
+  for (StringRef s : Strings) {
+    if (Previous.endswith(s)) {
+      StringIndexMap[s] = StringTable.size() - 1 - s.size();
+      continue;
+    }
+
+    StringIndexMap[s] = StringTable.size();
+    StringTable += s;
+    StringTable += '\x00';
+    Previous = s;
+  }
+}
diff --git a/lib/ProfileData/InstrProf.cpp b/lib/ProfileData/InstrProf.cpp
index 2eca8b2045..de2b13dafd 100644
--- a/lib/ProfileData/InstrProf.cpp
+++ b/lib/ProfileData/InstrProf.cpp
@@ -52,7 +52,7 @@ class InstrProfErrorCategoryType : public error_category {
     }
     llvm_unreachable("A value of instrprof_error has no message.");
   }
-  error_condition default_error_condition(int EV) const {
+  error_condition default_error_condition(int EV) const override {
     if (EV == instrprof_error::success)
       return errc::success;
     return errc::invalid_argument;
diff --git a/lib/ProfileData/InstrProfIndexed.h b/lib/ProfileData/InstrProfIndexed.h
index ede5368ca2..776170407b 100644
--- a/lib/ProfileData/InstrProfIndexed.h
+++ b/lib/ProfileData/InstrProfIndexed.h
@@ -14,6 +14,7 @@
 #ifndef LLVM_PROFILEDATA_INSTRPROF_INDEXED_H_
 #define LLVM_PROFILEDATA_INSTRPROF_INDEXED_H_
 
+#include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/MD5.h"
 
 namespace llvm {
diff --git a/lib/Support/BlockFrequency.cpp b/lib/Support/BlockFrequency.cpp
index 00cf75bd5c..6f7e341904 100644
--- a/lib/Support/BlockFrequency.cpp
+++ b/lib/Support/BlockFrequency.cpp
@@ -18,94 +18,8 @@
 
 using namespace llvm;
 
-/// Multiply FREQ by N and store result in W array.
-static void mult96bit(uint64_t freq, uint32_t N, uint32_t W[3]) {
-  uint64_t u0 = freq & UINT32_MAX;
-  uint64_t u1 = freq >> 32;
-
-  // Represent 96-bit value as W[2]:W[1]:W[0];
-  uint64_t t = u0 * N;
-  uint64_t k = t >> 32;
-  W[0] = t;
-  t = u1 * N + k;
-  W[1] = t;
-  W[2] = t >> 32;
-}
-
-/// Divide 96-bit value stored in W[2]:W[1]:W[0] by D. Since our word size is a
-/// 32 bit unsigned integer, we can use a short division algorithm.
-static uint64_t divrem96bit(uint32_t W[3], uint32_t D, uint32_t *Rout) {
-  // We assume that W[2] is non-zero since if W[2] is not then the user should
-  // just use hardware division.
-  assert(W[2] && "This routine assumes that W[2] is non-zero since if W[2] is "
-         "zero, the caller should just use 64/32 hardware.");
-  uint32_t Q[3] = { 0, 0, 0 };
-
-  // The generalized short division algorithm sets i to m + n - 1, where n is
-  // the number of words in the divisior and m is the number of words by which
-  // the divident exceeds the divisor (i.e. m + n == the length of the dividend
-  // in words). Due to our assumption that W[2] is non-zero, we know that the
-  // dividend is of length 3 implying since n is 1 that m = 2. Thus we set i to
-  // m + n - 1 = 2 + 1 - 1 = 2.
-  uint32_t R = 0;
-  for (int i = 2; i >= 0; --i) {
-    uint64_t PartialD = uint64_t(R) << 32 | W[i];
-    if (PartialD == 0) {
-      Q[i] = 0;
-      R = 0;
-    } else if (PartialD < D) {
-      Q[i] = 0;
-      R = uint32_t(PartialD);
-    } else if (PartialD == D) {
-      Q[i] = 1;
-      R = 0;
-    } else {
-      Q[i] = uint32_t(PartialD / D);
-      R = uint32_t(PartialD - (Q[i] * D));
-    }
-  }
-
-  // If Q[2] is non-zero, then we overflowed.
-  uint64_t Result;
-  if (Q[2]) {
-    Result = UINT64_MAX;
-    R = D;
-  } else {
-    // Form the final uint64_t result, avoiding endianness issues.
-    Result = uint64_t(Q[0]) | (uint64_t(Q[1]) << 32);
-  }
-
-  if (Rout)
-    *Rout = R;
-
-  return Result;
-}
-
-uint32_t BlockFrequency::scale(uint32_t N, uint32_t D) {
-  assert(D != 0 && "Division by zero");
-
-  // Calculate Frequency * N.
-  uint64_t MulLo = (Frequency & UINT32_MAX) * N;
-  uint64_t MulHi = (Frequency >> 32) * N;
-  uint64_t MulRes = (MulHi << 32) + MulLo;
-
-  // If the product fits in 64 bits, just use built-in division.
-  if (MulHi <= UINT32_MAX && MulRes >= MulLo) {
-    Frequency = MulRes / D;
-    return MulRes % D;
-  }
-
-  // Product overflowed, use 96-bit operations.
-  // 96-bit value represented as W[2]:W[1]:W[0].
-  uint32_t W[3];
-  uint32_t R;
-  mult96bit(Frequency, N, W);
-  Frequency = divrem96bit(W, D, &R);
-  return R;
-}
-
 BlockFrequency &BlockFrequency::operator*=(const BranchProbability &Prob) {
-  scale(Prob.getNumerator(), Prob.getDenominator());
+  Frequency = Prob.scale(Frequency);
   return *this;
 }
 
@@ -117,7 +31,7 @@ BlockFrequency::operator*(const BranchProbability &Prob) const {
 }
 
 BlockFrequency &BlockFrequency::operator/=(const BranchProbability &Prob) {
-  scale(Prob.getDenominator(), Prob.getNumerator());
+  Frequency = Prob.scaleByInverse(Frequency);
   return *this;
 }
 
@@ -156,8 +70,3 @@ BlockFrequency &BlockFrequency::operator>>=(const unsigned count) {
   Frequency |= Frequency == 0;
   return *this;
 }
-
-uint32_t BlockFrequency::scale(const BranchProbability &Prob) {
-  return scale(Prob.getNumerator(), Prob.getDenominator());
-}
-
diff --git a/lib/Support/BranchProbability.cpp b/lib/Support/BranchProbability.cpp
index e8b83e5980..65878d6e30 100644
--- a/lib/Support/BranchProbability.cpp
+++ b/lib/Support/BranchProbability.cpp
@@ -18,19 +18,56 @@
 
 using namespace llvm;
 
-void BranchProbability::print(raw_ostream &OS) const {
-  OS << N << " / " << D << " = " << format("%g%%", ((double)N / D) * 100.0);
+raw_ostream &BranchProbability::print(raw_ostream &OS) const {
+  return OS << N << " / " << D << " = "
+            << format("%g%%", ((double)N / D) * 100.0);
 }
 
-void BranchProbability::dump() const {
-  dbgs() << *this << '\n';
-}
+void BranchProbability::dump() const { print(dbgs()) << '\n'; }
+
+static uint64_t scale(uint64_t Num, uint32_t N, uint32_t D) {
+  assert(D && "divide by 0");
+
+  // Fast path for multiplying by 1.0.
+  if (!Num || D == N)
+    return Num;
+
+  // Split Num into upper and lower parts to multiply, then recombine.
+  uint64_t ProductHigh = (Num >> 32) * N;
+  uint64_t ProductLow = (Num & UINT32_MAX) * N;
+
+  // Split into 32-bit digits.
+  uint32_t Upper32 = ProductHigh >> 32;
+  uint32_t Lower32 = ProductLow & UINT32_MAX;
+  uint32_t Mid32Partial = ProductHigh & UINT32_MAX;
+  uint32_t Mid32 = Mid32Partial + (ProductLow >> 32);
+
+  // Carry.
+  Upper32 += Mid32 < Mid32Partial;
 
-namespace llvm {
+  // Check for overflow.
+  if (Upper32 >= D)
+    return UINT64_MAX;
+
+  uint64_t Rem = (uint64_t(Upper32) << 32) | Mid32;
+  uint64_t UpperQ = Rem / D;
+
+  // Check for overflow.
+  if (UpperQ > UINT32_MAX)
+    return UINT64_MAX;
+
+  Rem = ((Rem % D) << 32) | Lower32;
+  uint64_t LowerQ = Rem / D;
+  uint64_t Q = (UpperQ << 32) + LowerQ;
+
+  // Check for overflow.
+  return Q < LowerQ ? UINT64_MAX : Q;
+}
 
-raw_ostream &operator<<(raw_ostream &OS, const BranchProbability &Prob) {
-  Prob.print(OS);
-  return OS;
+uint64_t BranchProbability::scale(uint64_t Num) const {
+  return ::scale(Num, N, D);
 }
 
+uint64_t BranchProbability::scaleByInverse(uint64_t Num) const {
+  return ::scale(Num, D, N);
 }
diff --git a/lib/Support/Timer.cpp b/lib/Support/Timer.cpp
index eb3ffc44c8..61465ae5e8 100644
--- a/lib/Support/Timer.cpp
+++ b/lib/Support/Timer.cpp
@@ -15,6 +15,7 @@
 #include "llvm/ADT/StringMap.h"
 #include "llvm/Support/CommandLine.h"
 #include "llvm/Support/Debug.h"
+#include "llvm/Support/FileSystem.h"
 #include "llvm/Support/Format.h"
 #include "llvm/Support/ManagedStatic.h"
 #include "llvm/Support/Mutex.h"
diff --git a/lib/TableGen/Main.cpp b/lib/TableGen/Main.cpp
index fd81ab4f2b..476026dfd7 100644
--- a/lib/TableGen/Main.cpp
+++ b/lib/TableGen/Main.cpp
@@ -17,6 +17,7 @@
 
 #include "TGParser.h"
 #include "llvm/Support/CommandLine.h"
+#include "llvm/Support/FileSystem.h"
 #include "llvm/Support/MemoryBuffer.h"
 #include "llvm/Support/ToolOutputFile.h"
 #include "llvm/Support/system_error.h"
diff --git a/lib/Target/AArch64/AArch64AsmPrinter.h b/lib/Target/AArch64/AArch64AsmPrinter.h
index 824f0036bc..f77553c7b8 100644
--- a/lib/Target/AArch64/AArch64AsmPrinter.h
+++ b/lib/Target/AArch64/AArch64AsmPrinter.h
@@ -45,15 +45,15 @@ class LLVM_LIBRARY_VISIBILITY AArch64AsmPrinter : public AsmPrinter {
   MCOperand lowerSymbolOperand(const MachineOperand &MO,
                                const MCSymbol *Sym) const;
 
-  void EmitInstruction(const MachineInstr *MI);
-  void EmitEndOfAsmFile(Module &M);
+  void EmitInstruction(const MachineInstr *MI) override;
+  void EmitEndOfAsmFile(Module &M) override;
 
   bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
                        unsigned AsmVariant, const char *ExtraCode,
-                       raw_ostream &O);
+                       raw_ostream &O) override;
   bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum,
                              unsigned AsmVariant, const char *ExtraCode,
-                             raw_ostream &O);
+                             raw_ostream &O) override;
 
   /// printSymbolicAddress - Given some kind of reasonably bare symbolic
   /// reference, print out the appropriate asm string to represent it. If
@@ -65,11 +65,11 @@ class LLVM_LIBRARY_VISIBILITY AArch64AsmPrinter : public AsmPrinter {
                             bool PrintImmediatePrefix,
                             StringRef Suffix, raw_ostream &O);
 
-  virtual const char *getPassName() const {
+  const char *getPassName() const override {
     return "AArch64 Assembly Printer";
   }
 
-  virtual bool runOnMachineFunction(MachineFunction &MF);
+  bool runOnMachineFunction(MachineFunction &MF) override;
 };
 } // end namespace llvm
 
diff --git a/lib/Target/AArch64/AArch64BranchFixupPass.cpp b/lib/Target/AArch64/AArch64BranchFixupPass.cpp
index bff8ef5035..585cbee996 100644
--- a/lib/Target/AArch64/AArch64BranchFixupPass.cpp
+++ b/lib/Target/AArch64/AArch64BranchFixupPass.cpp
@@ -136,9 +136,9 @@ namespace {
     static char ID;
     AArch64BranchFixup() : MachineFunctionPass(ID) {}
 
-    virtual bool runOnMachineFunction(MachineFunction &MF);
+    bool runOnMachineFunction(MachineFunction &MF) override;
 
-    virtual const char *getPassName() const {
+    const char *getPassName() const override {
       return "AArch64 branch fixup pass";
     }
 
diff --git a/lib/Target/AArch64/AArch64FrameLowering.h b/lib/Target/AArch64/AArch64FrameLowering.h
index 032dd90fa0..6ec27e3104 100644
--- a/lib/Target/AArch64/AArch64FrameLowering.h
+++ b/lib/Target/AArch64/AArch64FrameLowering.h
@@ -47,8 +47,8 @@ public:
 
   /// emitProlog/emitEpilog - These methods insert prolog and epilog code into
   /// the function.
-  virtual void emitPrologue(MachineFunction &MF) const;
-  virtual void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
+  void emitPrologue(MachineFunction &MF) const override;
+  void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override;
 
   /// Decides how much stack adjustment to perform in each phase of the prologue
   /// and epilogue.
@@ -59,21 +59,21 @@ public:
                                      unsigned &FrameReg, int SPAdj,
                                      bool IsCalleeSaveOp) const;
 
-  virtual void processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
-                                                    RegScavenger *RS) const;
+  void processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
+                                            RegScavenger *RS) const override;
 
-  virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
-                                        MachineBasicBlock::iterator MI,
-                                        const std::vector<CalleeSavedInfo> &CSI,
-                                        const TargetRegisterInfo *TRI) const;
-  virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
-                                        MachineBasicBlock::iterator MI,
-                                        const std::vector<CalleeSavedInfo> &CSI,
-                                        const TargetRegisterInfo *TRI) const;
+  bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
+                                MachineBasicBlock::iterator MI,
+                                const std::vector<CalleeSavedInfo> &CSI,
+                                const TargetRegisterInfo *TRI) const override;
+  bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
+                                MachineBasicBlock::iterator MI,
+                                const std::vector<CalleeSavedInfo> &CSI,
+                                const TargetRegisterInfo *TRI) const override;
 
-  void eliminateCallFramePseudoInstr(MachineFunction &MF,
-                                     MachineBasicBlock &MBB,
-                                     MachineBasicBlock::iterator MI) const;
+  void
+  eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
+                                MachineBasicBlock::iterator MI) const override;
 
   /// If the register is X30 (i.e. LR) and the return address is used in the
   /// function then the callee-save store doesn't actually kill the register,
@@ -94,12 +94,12 @@ public:
                        unsigned NumClasses) const;
 
 
-  virtual bool hasFP(const MachineFunction &MF) const;
+  bool hasFP(const MachineFunction &MF) const override;
 
-  virtual bool useFPForAddressing(const MachineFunction &MF) const;
+  bool useFPForAddressing(const MachineFunction &MF) const;
 
   /// On AA
-  virtual bool hasReservedCallFrame(const MachineFunction &MF) const;
+  bool hasReservedCallFrame(const MachineFunction &MF) const override;
 
 };
 
diff --git a/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp b/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
index f22da96afc..d1d89af6e0 100644
--- a/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
+++ b/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
@@ -46,7 +46,7 @@ public:
       Subtarget(&TM.getSubtarget<AArch64Subtarget>()) {
   }
 
-  virtual const char *getPassName() const {
+  const char *getPassName() const override {
     return "AArch64 Instruction Selection";
   }
 
@@ -86,7 +86,7 @@ public:
 
   bool SelectInlineAsmMemoryOperand(const SDValue &Op,
                                     char ConstraintCode,
-                                    std::vector<SDValue> &OutOps);
+                                    std::vector<SDValue> &OutOps) override;
 
   bool SelectLogicalImm(SDValue N, SDValue &Imm);
 
@@ -108,7 +108,7 @@ public:
   SDNode *LowerToFPLitPool(SDNode *Node);
   SDNode *SelectToLitPool(SDNode *N);
 
-  SDNode* Select(SDNode*);
+  SDNode* Select(SDNode*) override;
 private:
   /// Get the opcode for table lookup instruction
   unsigned getTBLOpc(bool IsExt, bool Is64Bit, unsigned NumOfVec);
diff --git a/lib/Target/AArch64/AArch64ISelLowering.cpp b/lib/Target/AArch64/AArch64ISelLowering.cpp
index 6a073dbd44..5ad2036d51 100644
--- a/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -514,6 +514,11 @@ AArch64TargetLowering::AArch64TargetLowering(AArch64TargetMachine &TM)
                 > VT1.getVectorElementType().getSizeInBits())
           setTruncStoreAction(VT, VT1, Expand);
       }
+
+      setOperationAction(ISD::MULHS, VT, Expand);
+      setOperationAction(ISD::SMUL_LOHI, VT, Expand);
+      setOperationAction(ISD::MULHU, VT, Expand);
+      setOperationAction(ISD::UMUL_LOHI, VT, Expand);
     }
 
     // There is no v1i64/v2i64 multiply, expand v1i64/v2i64 to GPR i64 multiply.
diff --git a/lib/Target/AArch64/AArch64ISelLowering.h b/lib/Target/AArch64/AArch64ISelLowering.h
index 5e7716664a..f6239a04f8 100644
--- a/lib/Target/AArch64/AArch64ISelLowering.h
+++ b/lib/Target/AArch64/AArch64ISelLowering.h
@@ -205,7 +205,7 @@ class AArch64TargetLowering : public TargetLowering {
 public:
   explicit AArch64TargetLowering(AArch64TargetMachine &TM);
 
-  const char *getTargetNodeName(unsigned Opcode) const;
+  const char *getTargetNodeName(unsigned Opcode) const override;
 
   CCAssignFn *CCAssignFnForNode(CallingConv::ID CC) const;
 
@@ -213,18 +213,18 @@ public:
                                CallingConv::ID CallConv, bool isVarArg,
                                const SmallVectorImpl<ISD::InputArg> &Ins,
                                SDLoc dl, SelectionDAG &DAG,
-                               SmallVectorImpl<SDValue> &InVals) const;
+                               SmallVectorImpl<SDValue> &InVals) const override;
 
   SDValue LowerReturn(SDValue Chain,
                       CallingConv::ID CallConv, bool isVarArg,
                       const SmallVectorImpl<ISD::OutputArg> &Outs,
                       const SmallVectorImpl<SDValue> &OutVals,
-                      SDLoc dl, SelectionDAG &DAG) const;
+                      SDLoc dl, SelectionDAG &DAG) const override;
 
-  virtual unsigned getByValTypeAlignment(Type *Ty) const override;
+  unsigned getByValTypeAlignment(Type *Ty) const override;
 
   SDValue LowerCall(CallLoweringInfo &CLI,
-                    SmallVectorImpl<SDValue> &InVals) const;
+                    SmallVectorImpl<SDValue> &InVals) const override;
 
   SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
                           CallingConv::ID CallConv, bool IsVarArg,
@@ -268,15 +268,15 @@ public:
   SDValue addTokenForArgument(SDValue Chain, SelectionDAG &DAG,
                               MachineFrameInfo *MFI, int ClobberedFI) const;
 
-  EVT getSetCCResultType(LLVMContext &Context, EVT VT) const;
+  EVT getSetCCResultType(LLVMContext &Context, EVT VT) const override;
 
   bool DoesCalleeRestoreStack(CallingConv::ID CallCC, bool TailCallOpt) const;
 
   bool IsTailCallConvention(CallingConv::ID CallCC) const;
 
-  SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
+  SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
 
-  bool isLegalICmpImmediate(int64_t Val) const;
+  bool isLegalICmpImmediate(int64_t Val) const override;
 
   /// \brief Return true if the addressing mode represented by AM is legal for
   /// this target, for a load/store of the specified type.
@@ -299,8 +299,9 @@ public:
   SDValue getSelectableIntSetCC(SDValue LHS, SDValue RHS, ISD::CondCode CC,
                          SDValue &A64cc, SelectionDAG &DAG, SDLoc &dl) const;
 
-  virtual MachineBasicBlock *
-  EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const;
+  MachineBasicBlock *
+  EmitInstrWithCustomInserter(MachineInstr *MI,
+                              MachineBasicBlock *MBB) const override;
 
   MachineBasicBlock *
   emitAtomicBinary(MachineInstr *MI, MachineBasicBlock *MBB,
@@ -347,34 +348,37 @@ public:
   SDValue LowerVACOPY(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
 
-  virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
+  SDValue PerformDAGCombine(SDNode *N,DAGCombinerInfo &DCI) const override;
 
   /// isFMAFasterThanFMulAndFAdd - Return true if an FMA operation is faster
   /// than a pair of fmul and fadd instructions. fmuladd intrinsics will be
   /// expanded to FMAs when this method returns true, otherwise fmuladd is
   /// expanded to fmul + fadd.
-  virtual bool isFMAFasterThanFMulAndFAdd(EVT VT) const;
+  bool isFMAFasterThanFMulAndFAdd(EVT VT) const override;
 
   /// allowsUnalignedMemoryAccesses - Returns true if the target allows
   /// unaligned memory accesses of the specified type. Returns whether it
   /// is "fast" by reference in the second argument.
-  virtual bool allowsUnalignedMemoryAccesses(EVT VT, unsigned AddrSpace,
-                                             bool *Fast) const;
+  bool allowsUnalignedMemoryAccesses(EVT VT, unsigned AddrSpace,
+                                     bool *Fast) const override;
 
-  ConstraintType getConstraintType(const std::string &Constraint) const;
+  ConstraintType
+  getConstraintType(const std::string &Constraint) const override;
 
-  ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &Info,
-                                                  const char *Constraint) const;
+  ConstraintWeight
+  getSingleConstraintMatchWeight(AsmOperandInfo &Info,
+                                 const char *Constraint) const override;
   void LowerAsmOperandForConstraint(SDValue Op,
                                     std::string &Constraint,
                                     std::vector<SDValue> &Ops,
-                                    SelectionDAG &DAG) const;
+                                    SelectionDAG &DAG) const override;
 
   std::pair<unsigned, const TargetRegisterClass*>
-  getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const;
+  getRegForInlineAsmConstraint(const std::string &Constraint,
+                               MVT VT) const override;
 
-  virtual bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I,
-                                  unsigned Intrinsic) const override;
+  bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I,
+                          unsigned Intrinsic) const override;
 
   /// getMaximalGlobalOffset - Returns the maximal possible offset which can
   /// be used for loads / stores from the global.
@@ -382,7 +386,7 @@ public:
 
 protected:
   std::pair<const TargetRegisterClass*, uint8_t>
-  findRepresentativeClass(MVT VT) const;
+  findRepresentativeClass(MVT VT) const override;
 
 private:
   const InstrItineraryData *Itins;
diff --git a/lib/Target/AArch64/AArch64InstrInfo.cpp b/lib/Target/AArch64/AArch64InstrInfo.cpp
index a39c1c5f25..e2612abffa 100644
--- a/lib/Target/AArch64/AArch64InstrInfo.cpp
+++ b/lib/Target/AArch64/AArch64InstrInfo.cpp
@@ -867,7 +867,7 @@ namespace {
     static char ID;
     LDTLSCleanup() : MachineFunctionPass(ID) {}
 
-    virtual bool runOnMachineFunction(MachineFunction &MF) {
+    bool runOnMachineFunction(MachineFunction &MF) override {
       AArch64MachineFunctionInfo* MFI
         = MF.getInfo<AArch64MachineFunctionInfo>();
       if (MFI->getNumLocalDynamicTLSAccesses() < 2) {
@@ -962,11 +962,11 @@ namespace {
       return Copy;
     }
 
-    virtual const char *getPassName() const {
+    const char *getPassName() const override {
       return "Local Dynamic TLS Access Clean-up";
     }
 
-    virtual void getAnalysisUsage(AnalysisUsage &AU) const {
+    void getAnalysisUsage(AnalysisUsage &AU) const override {
       AU.setPreservesCFG();
       AU.addRequired<MachineDominatorTree>();
       MachineFunctionPass::getAnalysisUsage(AU);
diff --git a/lib/Target/AArch64/AArch64InstrInfo.h b/lib/Target/AArch64/AArch64InstrInfo.h
index ad20f9c984..10d5185ab6 100644
--- a/lib/Target/AArch64/AArch64InstrInfo.h
+++ b/lib/Target/AArch64/AArch64InstrInfo.h
@@ -41,7 +41,7 @@ public:
   void copyPhysReg(MachineBasicBlock &MBB,
                    MachineBasicBlock::iterator I, DebugLoc DL,
                    unsigned DestReg, unsigned SrcReg,
-                   bool KillSrc) const;
+                   bool KillSrc) const override;
   void CopyPhysRegTuple(MachineBasicBlock &MBB,
                         MachineBasicBlock::iterator I, DebugLoc DL,
                         unsigned DestReg, unsigned SrcReg) const;
@@ -50,25 +50,26 @@ public:
                            MachineBasicBlock::iterator MI,
                            unsigned SrcReg, bool isKill, int FrameIndex,
                            const TargetRegisterClass *RC,
-                           const TargetRegisterInfo *TRI) const;
+                           const TargetRegisterInfo *TRI) const override;
   void loadRegFromStackSlot(MachineBasicBlock &MBB,
                             MachineBasicBlock::iterator MBBI,
                             unsigned DestReg, int FrameIdx,
                             const TargetRegisterClass *RC,
-                            const TargetRegisterInfo *TRI) const;
+                            const TargetRegisterInfo *TRI) const override;
 
   bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
                      MachineBasicBlock *&FBB,
                      SmallVectorImpl<MachineOperand> &Cond,
-                     bool AllowModify = false) const;
+                     bool AllowModify = false) const override;
   unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
                         MachineBasicBlock *FBB,
                         const SmallVectorImpl<MachineOperand> &Cond,
-                        DebugLoc DL) const;
-  unsigned RemoveBranch(MachineBasicBlock &MBB) const;
-  bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
+                        DebugLoc DL) const override;
+  unsigned RemoveBranch(MachineBasicBlock &MBB) const override;
+  bool
+  ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
 
-  bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const;
+  bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const override;
 
   /// Look through the instructions in this function and work out the largest
   /// the stack frame can be while maintaining the ability to address local
diff --git a/lib/Target/AArch64/AArch64RegisterInfo.h b/lib/Target/AArch64/AArch64RegisterInfo.h
index 0fbef94851..5b501f9cc1 100644
--- a/lib/Target/AArch64/AArch64RegisterInfo.h
+++ b/lib/Target/AArch64/AArch64RegisterInfo.h
@@ -27,10 +27,11 @@ class AArch64Subtarget;
 struct AArch64RegisterInfo : public AArch64GenRegisterInfo {
   AArch64RegisterInfo();
 
-  const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF =nullptr) const;
-  const uint32_t *getCallPreservedMask(CallingConv::ID) const;
+  const MCPhysReg *
+  getCalleeSavedRegs(const MachineFunction *MF =nullptr) const override;
+  const uint32_t *getCallPreservedMask(CallingConv::ID) const override;
 
-  unsigned getCSRFirstUseCost() const {
+  unsigned getCSRFirstUseCost() const override {
     // The cost will be compared against BlockFrequency where entry has the
     // value of 1 << 14. A value of 5 will choose to spill or split really
     // cold path instead of using a callee-saved register.
@@ -39,38 +40,38 @@ struct AArch64RegisterInfo : public AArch64GenRegisterInfo {
 
   const uint32_t *getTLSDescCallPreservedMask() const;
 
-  BitVector getReservedRegs(const MachineFunction &MF) const;
-  unsigned getFrameRegister(const MachineFunction &MF) const;
+  BitVector getReservedRegs(const MachineFunction &MF) const override;
+  unsigned getFrameRegister(const MachineFunction &MF) const override;
 
   void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
                            unsigned FIOperandNum,
-                           RegScavenger *Rs = nullptr) const;
+                           RegScavenger *Rs = nullptr) const override;
 
   /// getCrossCopyRegClass - Returns a legal register class to copy a register
   /// in the specified class to or from. Returns original class if it is
   /// possible to copy between a two registers of the specified class.
   const TargetRegisterClass *
-  getCrossCopyRegClass(const TargetRegisterClass *RC) const;
+  getCrossCopyRegClass(const TargetRegisterClass *RC) const override;
 
   /// getLargestLegalSuperClass - Returns the largest super class of RC that is
   /// legal to use in the current sub-target and has the same spill size.
   const TargetRegisterClass*
-  getLargestLegalSuperClass(const TargetRegisterClass *RC) const {
+  getLargestLegalSuperClass(const TargetRegisterClass *RC) const override {
     if (RC == &AArch64::tcGPR64RegClass)
       return &AArch64::GPR64RegClass;
 
     return RC;
   }
 
-  bool requiresRegisterScavenging(const MachineFunction &MF) const {
+  bool requiresRegisterScavenging(const MachineFunction &MF) const override {
     return true;
   }
 
-  bool requiresFrameIndexScavenging(const MachineFunction &MF) const {
+  bool requiresFrameIndexScavenging(const MachineFunction &MF) const override {
     return true;
   }
 
-  bool useFPForScavengingIndex(const MachineFunction &MF) const;
+  bool useFPForScavengingIndex(const MachineFunction &MF) const override;
 };
 
 } // end namespace llvm
diff --git a/lib/Target/AArch64/AArch64Subtarget.h b/lib/Target/AArch64/AArch64Subtarget.h
index 8cd346e839..dd2b4d211f 100644
--- a/lib/Target/AArch64/AArch64Subtarget.h
+++ b/lib/Target/AArch64/AArch64Subtarget.h
@@ -61,7 +61,7 @@ public:
   AArch64Subtarget(StringRef TT, StringRef CPU, StringRef FS,
                    bool LittleEndian);
 
-  virtual bool enableMachineScheduler() const {
+  bool enableMachineScheduler() const override {
     return true;
   }
 
diff --git a/lib/Target/AArch64/AArch64TargetMachine.cpp b/lib/Target/AArch64/AArch64TargetMachine.cpp
index 844e8ab219..6bd6f5912d 100644
--- a/lib/Target/AArch64/AArch64TargetMachine.cpp
+++ b/lib/Target/AArch64/AArch64TargetMachine.cpp
@@ -88,8 +88,8 @@ public:
   }
 
   bool addPreISel() override;
-  virtual bool addInstSelector();
-  virtual bool addPreEmitPass();
+  bool addInstSelector() override;
+  bool addPreEmitPass() override;
 };
 } // namespace
 
diff --git a/lib/Target/AArch64/AArch64TargetMachine.h b/lib/Target/AArch64/AArch64TargetMachine.h
index 4297c92182..3800635e0f 100644
--- a/lib/Target/AArch64/AArch64TargetMachine.h
+++ b/lib/Target/AArch64/AArch64TargetMachine.h
@@ -39,32 +39,32 @@ public:
                        CodeGenOpt::Level OL,
                        bool LittleEndian);
 
-  const AArch64InstrInfo *getInstrInfo() const {
+  const AArch64InstrInfo *getInstrInfo() const override {
     return &InstrInfo;
   }
 
-  const AArch64FrameLowering *getFrameLowering() const {
+  const AArch64FrameLowering *getFrameLowering() const override {
     return &FrameLowering;
   }
 
-  const AArch64TargetLowering *getTargetLowering() const {
+  const AArch64TargetLowering *getTargetLowering() const override {
     return &TLInfo;
   }
 
-  const AArch64SelectionDAGInfo *getSelectionDAGInfo() const {
+  const AArch64SelectionDAGInfo *getSelectionDAGInfo() const override {
     return &TSInfo;
   }
 
-  const AArch64Subtarget *getSubtargetImpl() const { return &Subtarget; }
+  const AArch64Subtarget *getSubtargetImpl() const override { return &Subtarget; }
 
-  const DataLayout *getDataLayout() const { return &DL; }
+  const DataLayout *getDataLayout() const override { return &DL; }
 
-  const TargetRegisterInfo *getRegisterInfo() const {
+  const TargetRegisterInfo *getRegisterInfo() const override {
     return &InstrInfo.getRegisterInfo();
   }
-  TargetPassConfig *createPassConfig(PassManagerBase &PM);
+  TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
 
-  virtual void addAnalysisPasses(PassManagerBase &PM);
+  void addAnalysisPasses(PassManagerBase &PM) override;
 };
 
 // AArch64leTargetMachine - AArch64 little endian target machine.
diff --git a/lib/Target/AArch64/AArch64TargetObjectFile.h b/lib/Target/AArch64/AArch64TargetObjectFile.h
index 0f00a789d6..6e57103a42 100644
--- a/lib/Target/AArch64/AArch64TargetObjectFile.h
+++ b/lib/Target/AArch64/AArch64TargetObjectFile.h
@@ -23,7 +23,7 @@ namespace llvm {
   /// AArch64ElfTargetObjectFile - This implementation is used for ELF
   /// AArch64 targets.
   class AArch64ElfTargetObjectFile : public TargetLoweringObjectFileELF {
-    virtual void Initialize(MCContext &Ctx, const TargetMachine &TM);
+    void Initialize(MCContext &Ctx, const TargetMachine &TM) override;
   };
 
 } // end namespace llvm
diff --git a/lib/Target/AArch64/AArch64TargetTransformInfo.cpp b/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
index c37ffb5915..0228d123bc 100644
--- a/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
+++ b/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
@@ -75,7 +75,7 @@ public:
   /// \name Vector TTI Implementations
   /// @{
 
-  unsigned getNumberOfRegisters(bool Vector) const {
+  unsigned getNumberOfRegisters(bool Vector) const override {
     if (Vector) {
       if (ST->hasNEON())
         return 32;
@@ -84,7 +84,7 @@ public:
     return 32;
   }
 
-  unsigned getRegisterBitWidth(bool Vector) const {
+  unsigned getRegisterBitWidth(bool Vector) const override {
     if (Vector) {
       if (ST->hasNEON())
         return 128;
diff --git a/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp b/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
index 361f9848ce..9fe3497c6a 100644
--- a/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+++ b/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
@@ -65,19 +65,19 @@ public:
   }
 
   // These are the public interface of the MCTargetAsmParser
-  bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
+  bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
   bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
-                        SMLoc NameLoc,
-                        SmallVectorImpl<MCParsedAsmOperand*> &Operands);
+                       SMLoc NameLoc,
+                       SmallVectorImpl<MCParsedAsmOperand*> &Operands) override;
 
-  bool ParseDirective(AsmToken DirectiveID);
+  bool ParseDirective(AsmToken DirectiveID) override;
   bool ParseDirectiveTLSDescCall(SMLoc L);
   bool ParseDirectiveWord(unsigned Size, SMLoc L);
 
   bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
                                SmallVectorImpl<MCParsedAsmOperand*> &Operands,
                                MCStreamer&Out, unsigned &ErrorInfo,
-                               bool MatchingInlineAsm);
+                               bool MatchingInlineAsm) override;
 
   // The rest of the sub-parsers have more freedom over interface: they return
   // an OperandMatchResultTy because it's less ambiguous than true/false or
@@ -235,17 +235,17 @@ public:
   AArch64Operand(const AArch64Operand &o) : MCParsedAsmOperand() {
   }
 
-  SMLoc getStartLoc() const { return StartLoc; }
-  SMLoc getEndLoc() const { return EndLoc; }
-  void print(raw_ostream&) const;
-  void dump() const;
+  SMLoc getStartLoc() const override { return StartLoc; }
+  SMLoc getEndLoc() const override { return EndLoc; }
+  void print(raw_ostream&) const override;
+  void dump() const override;
 
   StringRef getToken() const {
     assert(Kind == k_Token && "Invalid access!");
     return StringRef(Tok.Data, Tok.Length);
   }
 
-  unsigned getReg() const {
+  unsigned getReg() const override {
     assert((Kind == k_Register || Kind == k_WrappedRegister)
            && "Invalid access!");
     return Reg.RegNum;
@@ -275,10 +275,10 @@ public:
   }
 
   bool isCondCode() const { return Kind == k_CondCode; }
-  bool isToken() const { return Kind == k_Token; }
-  bool isReg() const { return Kind == k_Register; }
-  bool isImm() const { return Kind == k_Immediate; }
-  bool isMem() const { return false; }
+  bool isToken() const override { return Kind == k_Token; }
+  bool isReg() const override { return Kind == k_Register; }
+  bool isImm() const override { return Kind == k_Immediate; }
+  bool isMem() const override { return false; }
   bool isFPImm() const { return Kind == k_FPImmediate; }
   bool isShiftOrExtend() const { return Kind == k_ShiftExtend; }
   bool isSysReg() const { return Kind == k_SysReg; }
diff --git a/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp b/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
index 270a6a9809..01f1497dc3 100644
--- a/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
+++ b/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
@@ -53,7 +53,7 @@ public:
                               const MemoryObject &region,
                               uint64_t address,
                               raw_ostream &vStream,
-                              raw_ostream &cStream) const;
+                              raw_ostream &cStream) const override;
 };
 
 }
diff --git a/lib/Target/AArch64/InstPrinter/AArch64InstPrinter.h b/lib/Target/AArch64/InstPrinter/AArch64InstPrinter.h
index 37b7273438..a0319a95ef 100644
--- a/lib/Target/AArch64/InstPrinter/AArch64InstPrinter.h
+++ b/lib/Target/AArch64/InstPrinter/AArch64InstPrinter.h
@@ -34,7 +34,7 @@ public:
   static const char *getRegisterName(unsigned RegNo);
   static const char *getInstructionName(unsigned Opcode);
 
-  void printRegName(raw_ostream &O, unsigned RegNum) const;
+  void printRegName(raw_ostream &O, unsigned RegNum) const override;
 
   template<unsigned MemSize, unsigned RmSize>
   void printAddrRegExtendOperand(const MCInst *MI, unsigned OpNum,
@@ -159,7 +159,7 @@ public:
 
   void printVPRRegister(const MCInst *MI, unsigned OpNo, raw_ostream &O);
   void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
-  virtual void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot);
+  void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot) override;
 
   bool isStackReg(unsigned RegNo) {
     return RegNo == AArch64::XSP || RegNo == AArch64::WSP;
diff --git a/lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp b/lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp
index f1452ab428..e0931e4207 100644
--- a/lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp
+++ b/lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp
@@ -38,13 +38,13 @@ public:
     delete STI;
   }
 
-  bool writeNopData(uint64_t Count, MCObjectWriter *OW) const;
+  bool writeNopData(uint64_t Count, MCObjectWriter *OW) const override;
 
   virtual void processFixupValue(const MCAssembler &Asm,
                                  const MCAsmLayout &Layout,
                                  const MCFixup &Fixup, const MCFragment *DF,
                                  const MCValue &Target, uint64_t &Value,
-                                 bool &IsResolved);
+                                 bool &IsResolved) override;
 };
 } // end anonymous namespace
 
@@ -89,13 +89,13 @@ public:
   bool fixupNeedsRelaxation(const MCFixup &Fixup,
                             uint64_t Value,
                             const MCRelaxableFragment *DF,
-                            const MCAsmLayout &Layout) const;
+                            const MCAsmLayout &Layout) const override;
 
-  unsigned int getNumFixupKinds() const {
+  unsigned int getNumFixupKinds() const override {
     return AArch64::NumTargetFixupKinds;
   }
 
-  const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const {
+  const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override {
     const static MCFixupKindInfo Infos[AArch64::NumTargetFixupKinds] = {
 // This table *must* be in the order that the fixup_* kinds are defined in
 // AArch64FixupKinds.h.
@@ -177,7 +177,7 @@ public:
   }
 
   void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
-                  uint64_t Value, bool IsPCRel) const {
+                  uint64_t Value, bool IsPCRel) const override {
     unsigned NumBytes = getFixupKindInfo(Fixup.getKind()).TargetSize / 8;
     Value = adjustFixupValue(Fixup.getKind(), Value);
     if (!Value) return;           // Doesn't change encoding.
@@ -192,15 +192,15 @@ public:
     }
   }
 
-  bool mayNeedRelaxation(const MCInst&) const {
+  bool mayNeedRelaxation(const MCInst&) const override {
     return false;
   }
 
-  void relaxInstruction(const MCInst&, llvm::MCInst&) const {
+  void relaxInstruction(const MCInst&, llvm::MCInst&) const override {
     llvm_unreachable("Cannot relax instructions");
   }
 
-  MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
+  MCObjectWriter *createObjectWriter(raw_ostream &OS) const override {
     return createAArch64ELFObjectWriter(OS, OSABI, IsLittle);
   }
 };
diff --git a/lib/Target/AArch64/MCTargetDesc/AArch64ELFStreamer.cpp b/lib/Target/AArch64/MCTargetDesc/AArch64ELFStreamer.cpp
index 16485217a2..df2cb38375 100644
--- a/lib/Target/AArch64/MCTargetDesc/AArch64ELFStreamer.cpp
+++ b/lib/Target/AArch64/MCTargetDesc/AArch64ELFStreamer.cpp
@@ -62,8 +62,8 @@ public:
 
   ~AArch64ELFStreamer() {}
 
-  virtual void ChangeSection(const MCSection *Section,
-                             const MCExpr *Subsection) {
+  void ChangeSection(const MCSection *Section,
+                     const MCExpr *Subsection) override {
     // We have to keep track of the mapping symbol state of any sections we
     // use. Each one should start off as EMS_None, which is provided as the
     // default constructor by DenseMap::lookup.
@@ -76,7 +76,8 @@ public:
   /// This function is the one used to emit instruction data into the ELF
   /// streamer. We override it to add the appropriate mapping symbol if
   /// necessary.
-  virtual void EmitInstruction(const MCInst& Inst, const MCSubtargetInfo &STI) {
+  void EmitInstruction(const MCInst& Inst,
+                       const MCSubtargetInfo &STI) override {
     EmitA64MappingSymbol();
     MCELFStreamer::EmitInstruction(Inst, STI);
   }
@@ -84,7 +85,7 @@ public:
   /// This is one of the functions used to emit data into an ELF section, so the
   /// AArch64 streamer overrides it to add the appropriate mapping symbol ($d)
   /// if necessary.
-  virtual void EmitBytes(StringRef Data) {
+  void EmitBytes(StringRef Data) override {
     EmitDataMappingSymbol();
     MCELFStreamer::EmitBytes(Data);
   }
@@ -92,8 +93,8 @@ public:
   /// This is one of the functions used to emit data into an ELF section, so the
   /// AArch64 streamer overrides it to add the appropriate mapping symbol ($d)
   /// if necessary.
-  virtual void EmitValueImpl(const MCExpr *Value, unsigned Size,
-                             const SMLoc &Loc) {
+  void EmitValueImpl(const MCExpr *Value, unsigned Size,
+                     const SMLoc &Loc) override {
     EmitDataMappingSymbol();
     MCELFStreamer::EmitValueImpl(Value, Size, Loc);
   }
diff --git a/lib/Target/AArch64/MCTargetDesc/AArch64MCAsmInfo.h b/lib/Target/AArch64/MCTargetDesc/AArch64MCAsmInfo.h
index 43c0e47029..78fd5d5b4f 100644
--- a/lib/Target/AArch64/MCTargetDesc/AArch64MCAsmInfo.h
+++ b/lib/Target/AArch64/MCTargetDesc/AArch64MCAsmInfo.h
@@ -21,7 +21,7 @@ namespace llvm {
 struct AArch64ELFMCAsmInfo : public MCAsmInfoELF {
   explicit AArch64ELFMCAsmInfo(StringRef TT);
 private:
-  virtual void anchor();
+  void anchor() override;
 };
 
 } // namespace llvm
diff --git a/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp b/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp
index 9e2348905b..7ff46d71df 100644
--- a/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp
+++ b/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp
@@ -143,7 +143,7 @@ public:
 
   void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
                          SmallVectorImpl<MCFixup> &Fixups,
-                         const MCSubtargetInfo &STI) const;
+                         const MCSubtargetInfo &STI) const override;
 
   template<int hasRs, int hasRt2> unsigned
   fixLoadStoreExclusive(const MCInst &MI, unsigned EncodedValue,
diff --git a/lib/Target/AArch64/MCTargetDesc/AArch64MCExpr.h b/lib/Target/AArch64/MCTargetDesc/AArch64MCExpr.h
index d9798ae990..23128fefb0 100644
--- a/lib/Target/AArch64/MCTargetDesc/AArch64MCExpr.h
+++ b/lib/Target/AArch64/MCTargetDesc/AArch64MCExpr.h
@@ -165,15 +165,15 @@ public:
 
   /// @}
 
-  void PrintImpl(raw_ostream &OS) const;
+  void PrintImpl(raw_ostream &OS) const override;
   bool EvaluateAsRelocatableImpl(MCValue &Res,
-                                 const MCAsmLayout *Layout) const;
-  void AddValueSymbols(MCAssembler *) const;
-  const MCSection *FindAssociatedSection() const {
+                                 const MCAsmLayout *Layout) const override;
+  void AddValueSymbols(MCAssembler *) const override;
+  const MCSection *FindAssociatedSection() const override {
     return getSubExpr()->FindAssociatedSection();
   }
 
-  void fixELFSymbolsInTLSFixups(MCAssembler &Asm) const;
+  void fixELFSymbolsInTLSFixups(MCAssembler &Asm) const override;
 
   static bool classof(const MCExpr *E) {
     return E->getKind() == MCExpr::Target;
diff --git a/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp b/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp
index 9a104b70e0..599949c043 100644
--- a/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp
+++ b/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp
@@ -123,14 +123,14 @@ class AArch64MCInstrAnalysis : public MCInstrAnalysis {
 public:
   AArch64MCInstrAnalysis(const MCInstrInfo *Info) : MCInstrAnalysis(Info) {}
 
-  virtual bool isUnconditionalBranch(const MCInst &Inst) const {
+  bool isUnconditionalBranch(const MCInst &Inst) const override {
     if (Inst.getOpcode() == AArch64::Bcc
         && Inst.getOperand(0).getImm() == A64CC::AL)
       return true;
     return MCInstrAnalysis::isUnconditionalBranch(Inst);
   }
 
-  virtual bool isConditionalBranch(const MCInst &Inst) const {
+  bool isConditionalBranch(const MCInst &Inst) const override {
     if (Inst.getOpcode() == AArch64::Bcc
         && Inst.getOperand(0).getImm() == A64CC::AL)
       return false;
@@ -138,7 +138,7 @@ public:
   }
 
   bool evaluateBranch(const MCInst &Inst, uint64_t Addr,
-                      uint64_t Size, uint64_t &Target) const {
+                      uint64_t Size, uint64_t &Target) const override {
     unsigned LblOperand = Inst.getOpcode() == AArch64::Bcc ? 1 : 0;
     // FIXME: We only handle PCRel branches for now.
     if (Info->get(Inst.getOpcode()).OpInfo[LblOperand].OperandType
diff --git a/lib/Target/ARM/ARMAsmPrinter.cpp b/lib/Target/ARM/ARMAsmPrinter.cpp
index 05e004ca07..f101053708 100644
--- a/lib/Target/ARM/ARMAsmPrinter.cpp
+++ b/lib/Target/ARM/ARMAsmPrinter.cpp
@@ -44,6 +44,7 @@
 #include "llvm/MC/MCStreamer.h"
 #include "llvm/MC/MCSymbol.h"
 #include "llvm/Support/ARMBuildAttributes.h"
+#include "llvm/Support/COFF.h"
 #include "llvm/Support/CommandLine.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/ELF.h"
@@ -97,7 +98,28 @@ bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
   AFI = MF.getInfo<ARMFunctionInfo>();
   MCP = MF.getConstantPool();
 
-  return AsmPrinter::runOnMachineFunction(MF);
+  SetupMachineFunction(MF);
+
+  if (Subtarget->isTargetCOFF()) {
+    bool Internal = MF.getFunction()->hasInternalLinkage();
+    COFF::SymbolStorageClass Scl = Internal ? COFF::IMAGE_SYM_CLASS_STATIC
+                                            : COFF::IMAGE_SYM_CLASS_EXTERNAL;
+    int Type = COFF::IMAGE_SYM_DTYPE_FUNCTION << COFF::SCT_COMPLEX_TYPE_SHIFT;
+
+    OutStreamer.BeginCOFFSymbolDef(CurrentFnSym);
+    OutStreamer.EmitCOFFSymbolStorageClass(Scl);
+    OutStreamer.EmitCOFFSymbolType(Type);
+    OutStreamer.EndCOFFSymbolDef();
+  }
+
+  // Have common code print out the function header with linkage info etc.
+  EmitFunctionHeader();
+
+  // Emit the rest of the function body.
+  EmitFunctionBody();
+
+  // We didn't modify anything.
+  return false;
 }
 
 void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
@@ -457,6 +479,29 @@ void ARMAsmPrinter::EmitStartOfAsmFile(Module &M) {
     emitAttributes();
 }
 
+static void
+emitNonLazySymbolPointer(MCStreamer &OutStreamer, MCSymbol *StubLabel,
+                         MachineModuleInfoImpl::StubValueTy &MCSym) {
+  // L_foo$stub:
+  OutStreamer.EmitLabel(StubLabel);
+  //   .indirect_symbol _foo
+  OutStreamer.EmitSymbolAttribute(MCSym.getPointer(), MCSA_IndirectSymbol);
+
+  if (MCSym.getInt())
+    // External to current translation unit.
+    OutStreamer.EmitIntValue(0, 4/*size*/);
+  else
+    // Internal to current translation unit.
+    //
+    // When we place the LSDA into the TEXT section, the type info
+    // pointers need to be indirect and pc-rel. We accomplish this by
+    // using NLPs; however, sometimes the types are local to the file.
+    // We need to fill in the value for the NLP in those cases.
+    OutStreamer.EmitValue(
+        MCSymbolRefExpr::Create(MCSym.getPointer(), OutStreamer.getContext()),
+        4 /*size*/);
+}
+
 
 void ARMAsmPrinter::EmitEndOfAsmFile(Module &M) {
   if (Subtarget->isTargetMachO()) {
@@ -473,27 +518,9 @@ void ARMAsmPrinter::EmitEndOfAsmFile(Module &M) {
       // Switch with ".non_lazy_symbol_pointer" directive.
       OutStreamer.SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
       EmitAlignment(2);
-      for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
-        // L_foo$stub:
-        OutStreamer.EmitLabel(Stubs[i].first);
-        //   .indirect_symbol _foo
-        MachineModuleInfoImpl::StubValueTy &MCSym = Stubs[i].second;
-        OutStreamer.EmitSymbolAttribute(MCSym.getPointer(),MCSA_IndirectSymbol);
-
-        if (MCSym.getInt())
-          // External to current translation unit.
-          OutStreamer.EmitIntValue(0, 4/*size*/);
-        else
-          // Internal to current translation unit.
-          //
-          // When we place the LSDA into the TEXT section, the type info
-          // pointers need to be indirect and pc-rel. We accomplish this by
-          // using NLPs; however, sometimes the types are local to the file.
-          // We need to fill in the value for the NLP in those cases.
-          OutStreamer.EmitValue(MCSymbolRefExpr::Create(MCSym.getPointer(),
-                                                        OutContext),
-                                4/*size*/);
-      }
+
+      for (auto &Stub : Stubs)
+        emitNonLazySymbolPointer(OutStreamer, Stub.first, Stub.second);
 
       Stubs.clear();
       OutStreamer.AddBlankLine();
@@ -501,17 +528,11 @@ void ARMAsmPrinter::EmitEndOfAsmFile(Module &M) {
 
     Stubs = MMIMacho.GetHiddenGVStubList();
     if (!Stubs.empty()) {
-      OutStreamer.SwitchSection(getObjFileLowering().getDataSection());
+      OutStreamer.SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
       EmitAlignment(2);
-      for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
-        // L_foo$stub:
-        OutStreamer.EmitLabel(Stubs[i].first);
-        //   .long _foo
-        OutStreamer.EmitValue(MCSymbolRefExpr::
-                              Create(Stubs[i].second.getPointer(),
-                                     OutContext),
-                              4/*size*/);
-      }
+
+      for (auto &Stub : Stubs)
+        emitNonLazySymbolPointer(OutStreamer, Stub.first, Stub.second);
 
       Stubs.clear();
       OutStreamer.AddBlankLine();
diff --git a/lib/Target/ARM/ARMExpandPseudoInsts.cpp b/lib/Target/ARM/ARMExpandPseudoInsts.cpp
index d3219aa6ef..72a9b648dc 100644
--- a/lib/Target/ARM/ARMExpandPseudoInsts.cpp
+++ b/lib/Target/ARM/ARMExpandPseudoInsts.cpp
@@ -615,6 +615,39 @@ void ARMExpandPseudo::ExpandVTBL(MachineBasicBlock::iterator &MBBI,
   MI.eraseFromParent();
 }
 
+static bool IsAnAddressOperand(const MachineOperand &MO) {
+  // This check is overly conservative.  Unless we are certain that the machine
+  // operand is not a symbol reference, we return that it is a symbol reference.
+  // This is important as the load pair may not be split up Windows.
+  switch (MO.getType()) {
+  case MachineOperand::MO_Register:
+  case MachineOperand::MO_Immediate:
+  case MachineOperand::MO_CImmediate:
+  case MachineOperand::MO_FPImmediate:
+    return false;
+  case MachineOperand::MO_MachineBasicBlock:
+    return true;
+  case MachineOperand::MO_FrameIndex:
+    return false;
+  case MachineOperand::MO_ConstantPoolIndex:
+  case MachineOperand::MO_TargetIndex:
+  case MachineOperand::MO_JumpTableIndex:
+  case MachineOperand::MO_ExternalSymbol:
+  case MachineOperand::MO_GlobalAddress:
+  case MachineOperand::MO_BlockAddress:
+    return true;
+  case MachineOperand::MO_RegisterMask:
+  case MachineOperand::MO_RegisterLiveOut:
+    return false;
+  case MachineOperand::MO_Metadata:
+  case MachineOperand::MO_MCSymbol:
+    return true;
+  case MachineOperand::MO_CFIIndex:
+    return false;
+  }
+  llvm_unreachable("unhandled machine operand type");
+}
+
 void ARMExpandPseudo::ExpandMOV32BitImm(MachineBasicBlock &MBB,
                                         MachineBasicBlock::iterator &MBBI) {
   MachineInstr &MI = *MBBI;
@@ -625,10 +658,14 @@ void ARMExpandPseudo::ExpandMOV32BitImm(MachineBasicBlock &MBB,
   bool DstIsDead = MI.getOperand(0).isDead();
   bool isCC = Opcode == ARM::MOVCCi32imm || Opcode == ARM::t2MOVCCi32imm;
   const MachineOperand &MO = MI.getOperand(isCC ? 2 : 1);
+  bool RequiresBundling = STI->isTargetWindows() && IsAnAddressOperand(MO);
   MachineInstrBuilder LO16, HI16;
 
   if (!STI->hasV6T2Ops() &&
       (Opcode == ARM::MOVi32imm || Opcode == ARM::MOVCCi32imm)) {
+    // FIXME Windows CE supports older ARM CPUs
+    assert(!STI->isTargetWindows() && "Windows on ARM requires ARMv7+");
+
     // Expand into a movi + orr.
     LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVi), DstReg);
     HI16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::ORRri))
@@ -660,6 +697,9 @@ void ARMExpandPseudo::ExpandMOV32BitImm(MachineBasicBlock &MBB,
     HI16Opc = ARM::MOVTi16;
   }
 
+  if (RequiresBundling)
+    BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(TargetOpcode::BUNDLE));
+
   LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(LO16Opc), DstReg);
   HI16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(HI16Opc))
     .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
@@ -683,6 +723,11 @@ void ARMExpandPseudo::ExpandMOV32BitImm(MachineBasicBlock &MBB,
   LO16.addImm(Pred).addReg(PredReg);
   HI16.addImm(Pred).addReg(PredReg);
 
+  if (RequiresBundling) {
+    LO16->bundleWithPred();
+    HI16->bundleWithPred();
+  }
+
   TransferImpOps(MI, LO16, HI16);
   MI.eraseFromParent();
 }
diff --git a/lib/Target/ARM/ARMFrameLowering.cpp b/lib/Target/ARM/ARMFrameLowering.cpp
index aae7aa45e4..af4c97db68 100644
--- a/lib/Target/ARM/ARMFrameLowering.cpp
+++ b/lib/Target/ARM/ARMFrameLowering.cpp
@@ -25,6 +25,7 @@
 #include "llvm/CodeGen/RegisterScavenging.h"
 #include "llvm/IR/CallingConv.h"
 #include "llvm/IR/Function.h"
+#include "llvm/IR/Module.h"
 #include "llvm/MC/MCContext.h"
 #include "llvm/Support/CommandLine.h"
 #include "llvm/Target/TargetOptions.h"
@@ -142,6 +143,14 @@ static int sizeOfSPAdjustment(const MachineInstr *MI) {
   return count;
 }
 
+static bool WindowsRequiresStackProbe(const MachineFunction &MF,
+                                      size_t StackSizeInBytes) {
+  const MachineFrameInfo *MFI = MF.getFrameInfo();
+  if (MFI->getStackProtectorIndex() > 0)
+    return StackSizeInBytes >= 4080;
+  return StackSizeInBytes >= 4096;
+}
+
 void ARMFrameLowering::emitPrologue(MachineFunction &MF) const {
   MachineBasicBlock &MBB = MF.front();
   MachineBasicBlock::iterator MBBI = MBB.begin();
@@ -149,15 +158,16 @@ void ARMFrameLowering::emitPrologue(MachineFunction &MF) const {
   ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
   MachineModuleInfo &MMI = MF.getMMI();
   MCContext &Context = MMI.getContext();
+  const TargetMachine &TM = MF.getTarget();
   const MCRegisterInfo *MRI = Context.getRegisterInfo();
   const ARMBaseRegisterInfo *RegInfo =
-    static_cast<const ARMBaseRegisterInfo*>(MF.getTarget().getRegisterInfo());
+    static_cast<const ARMBaseRegisterInfo*>(TM.getRegisterInfo());
   const ARMBaseInstrInfo &TII =
-    *static_cast<const ARMBaseInstrInfo*>(MF.getTarget().getInstrInfo());
+    *static_cast<const ARMBaseInstrInfo*>(TM.getInstrInfo());
   assert(!AFI->isThumb1OnlyFunction() &&
          "This emitPrologue does not support Thumb1!");
   bool isARM = !AFI->isThumbFunction();
-  unsigned Align = MF.getTarget().getFrameLowering()->getStackAlignment();
+  unsigned Align = TM.getFrameLowering()->getStackAlignment();
   unsigned ArgRegsSaveSize = AFI->getArgRegsSaveSize(Align);
   unsigned NumBytes = MFI->getStackSize();
   const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
@@ -187,7 +197,8 @@ void ARMFrameLowering::emitPrologue(MachineFunction &MF) const {
         .addCFIIndex(CFIIndex);
   }
 
-  if (!AFI->hasStackFrame()) {
+  if (!AFI->hasStackFrame() &&
+      (!STI.isTargetWindows() || !WindowsRequiresStackProbe(MF, NumBytes))) {
     if (NumBytes - ArgRegsSaveSize != 0) {
       emitSPUpdate(isARM, MBB, MBBI, dl, TII, -(NumBytes - ArgRegsSaveSize),
                    MachineInstr::FrameSetup);
@@ -284,6 +295,50 @@ void ARMFrameLowering::emitPrologue(MachineFunction &MF) const {
   } else
     NumBytes = DPRCSOffset;
 
+  if (STI.isTargetWindows() && WindowsRequiresStackProbe(MF, NumBytes)) {
+    uint32_t NumWords = NumBytes >> 2;
+
+    if (NumWords < 65536)
+      AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi16), ARM::R4)
+                     .addImm(NumWords));
+    else
+      BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi32imm), ARM::R4)
+        .addImm(NumWords);
+
+    switch (TM.getCodeModel()) {
+    case CodeModel::Small:
+    case CodeModel::Medium:
+    case CodeModel::Default:
+    case CodeModel::Kernel:
+      BuildMI(MBB, MBBI, dl, TII.get(ARM::tBL))
+        .addImm((unsigned)ARMCC::AL).addReg(0)
+        .addExternalSymbol("__chkstk")
+        .addReg(ARM::R4, RegState::Implicit);
+      break;
+    case CodeModel::Large:
+    case CodeModel::JITDefault: {
+      LLVMContext &Ctx = MF.getMMI().getModule()->getContext();
+      const GlobalValue *F =
+        Function::Create(FunctionType::get(Type::getVoidTy(Ctx), false),
+                         GlobalValue::AvailableExternallyLinkage, "__chkstk");
+
+      BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi32imm), ARM::R12)
+        .addGlobalAddress(F);
+      BuildMI(MBB, MBBI, dl, TII.get(ARM::BLX))
+        .addReg(ARM::R12, RegState::Kill)
+        .addReg(ARM::R4, RegState::Implicit);
+      break;
+    }
+    }
+
+    AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::t2SUBrr),
+                                        ARM::SP)
+                                .addReg(ARM::SP, RegState::Define)
+                                .addReg(ARM::R4, RegState::Kill)
+                                .setMIFlags(MachineInstr::FrameSetup)));
+    NumBytes = 0;
+  }
+
   unsigned adjustedGPRCS1Size = GPRCS1Size;
   if (NumBytes) {
     // Adjust SP after all the callee-save spills.
diff --git a/lib/Target/ARM/ARMFrameLowering.h b/lib/Target/ARM/ARMFrameLowering.h
index 524ee36dd3..981d320971 100644
--- a/lib/Target/ARM/ARMFrameLowering.h
+++ b/lib/Target/ARM/ARMFrameLowering.h
@@ -57,7 +57,7 @@ public:
   void processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
                                             RegScavenger *RS) const override;
 
-  void adjustForSegmentedStacks(MachineFunction &MF) const;
+  void adjustForSegmentedStacks(MachineFunction &MF) const override;
 
  private:
   void emitPushInst(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
diff --git a/lib/Target/ARM/ARMOptimizeBarriersPass.cpp b/lib/Target/ARM/ARMOptimizeBarriersPass.cpp
index 5c665b1e1e..2a4925572a 100644
--- a/lib/Target/ARM/ARMOptimizeBarriersPass.cpp
+++ b/lib/Target/ARM/ARMOptimizeBarriersPass.cpp
@@ -25,9 +25,9 @@ public:
   static char ID;
   ARMOptimizeBarriersPass() : MachineFunctionPass(ID) {}
 
-  virtual bool runOnMachineFunction(MachineFunction &Fn);
+  bool runOnMachineFunction(MachineFunction &Fn) override;
 
-  virtual const char *getPassName() const {
+  const char *getPassName() const override {
     return "optimise barriers pass";
   }
 
diff --git a/lib/Target/ARM/ARMSelectionDAGInfo.cpp b/lib/Target/ARM/ARMSelectionDAGInfo.cpp
index c18941449a..f3922035b6 100644
--- a/lib/Target/ARM/ARMSelectionDAGInfo.cpp
+++ b/lib/Target/ARM/ARMSelectionDAGInfo.cpp
@@ -73,7 +73,7 @@ ARMSelectionDAGInfo::EmitTargetCodeForMemcpy(SelectionDAG &DAG, SDLoc dl,
       SrcOff += VTSize;
     }
     Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
-                        ArrayRef<SDValue>(TFOps, i));
+                        makeArrayRef(TFOps, i));
 
     for (i = 0;
          i < MAX_LOADS_IN_LDM && EmittedNumMemOps + i < NumMemOps; ++i) {
@@ -85,7 +85,7 @@ ARMSelectionDAGInfo::EmitTargetCodeForMemcpy(SelectionDAG &DAG, SDLoc dl,
       DstOff += VTSize;
     }
     Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
-                        ArrayRef<SDValue>(TFOps, i));
+                        makeArrayRef(TFOps, i));
 
     EmittedNumMemOps += i;
   }
@@ -116,7 +116,7 @@ ARMSelectionDAGInfo::EmitTargetCodeForMemcpy(SelectionDAG &DAG, SDLoc dl,
     BytesLeft -= VTSize;
   }
   Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
-                      ArrayRef<SDValue>(TFOps, i));
+                      makeArrayRef(TFOps, i));
 
   i = 0;
   BytesLeft = BytesLeftSave;
@@ -138,7 +138,7 @@ ARMSelectionDAGInfo::EmitTargetCodeForMemcpy(SelectionDAG &DAG, SDLoc dl,
     BytesLeft -= VTSize;
   }
   return DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
-                     ArrayRef<SDValue>(TFOps, i));
+                     makeArrayRef(TFOps, i));
 }
 
 // Adjust parameters for memset, EABI uses format (ptr, size, value),
diff --git a/lib/Target/ARM/ARMTargetMachine.h b/lib/Target/ARM/ARMTargetMachine.h
index 389839eae9..664c992ea1 100644
--- a/lib/Target/ARM/ARMTargetMachine.h
+++ b/lib/Target/ARM/ARMTargetMachine.h
@@ -101,7 +101,7 @@ class ARMTargetMachine : public ARMBaseTargetMachine {
 /// ARMLETargetMachine - ARM little endian target machine.
 ///
 class ARMLETargetMachine : public ARMTargetMachine {
-  virtual void anchor();
+  void anchor() override;
 public:
   ARMLETargetMachine(const Target &T, StringRef TT,
                      StringRef CPU, StringRef FS, const TargetOptions &Options,
@@ -112,7 +112,7 @@ public:
 /// ARMBETargetMachine - ARM big endian target machine.
 ///
 class ARMBETargetMachine : public ARMTargetMachine {
-  virtual void anchor();
+  void anchor() override;
 public:
   ARMBETargetMachine(const Target &T, StringRef TT,
                      StringRef CPU, StringRef FS, const TargetOptions &Options,
@@ -168,7 +168,7 @@ public:
 /// ThumbLETargetMachine - Thumb little endian target machine.
 ///
 class ThumbLETargetMachine : public ThumbTargetMachine {
-  virtual void anchor();
+  void anchor() override;
 public:
   ThumbLETargetMachine(const Target &T, StringRef TT,
                      StringRef CPU, StringRef FS, const TargetOptions &Options,
@@ -179,7 +179,7 @@ public:
 /// ThumbBETargetMachine - Thumb big endian target machine.
 ///
 class ThumbBETargetMachine : public ThumbTargetMachine {
-  virtual void anchor();
+  void anchor() override;
 public:
   ThumbBETargetMachine(const Target &T, StringRef TT, StringRef CPU,
                        StringRef FS, const TargetOptions &Options,
diff --git a/lib/Target/ARM/MCTargetDesc/ARMELFObjectWriter.cpp b/lib/Target/ARM/MCTargetDesc/ARMELFObjectWriter.cpp
index a4661b1a4f..a6f7258e65 100644
--- a/lib/Target/ARM/MCTargetDesc/ARMELFObjectWriter.cpp
+++ b/lib/Target/ARM/MCTargetDesc/ARMELFObjectWriter.cpp
@@ -91,6 +91,9 @@ unsigned ARMELFObjectWriter::GetRelocTypeInner(const MCValue &Target,
       case MCSymbolRefExpr::VK_GOTTPOFF:
         Type = ELF::R_ARM_TLS_IE32;
         break;
+      case MCSymbolRefExpr::VK_GOTPCREL:
+        Type = ELF::R_ARM_GOT_PREL;
+        break;
       }
       break;
     case ARM::fixup_arm_blx:
@@ -167,6 +170,9 @@ unsigned ARMELFObjectWriter::GetRelocTypeInner(const MCValue &Target,
       case MCSymbolRefExpr::VK_GOTOFF:
         Type = ELF::R_ARM_GOTOFF32;
         break;
+      case MCSymbolRefExpr::VK_GOTPCREL:
+        Type = ELF::R_ARM_GOT_PREL;
+        break;
       case MCSymbolRefExpr::VK_ARM_TARGET1:
         Type = ELF::R_ARM_TARGET1;
         break;
diff --git a/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp b/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp
index 6d5fd6a293..e55aa66713 100644
--- a/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp
+++ b/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp
@@ -609,12 +609,8 @@ private:
   }
 
   void EmitThumbFunc(MCSymbol *Func) override {
-    // FIXME: Anything needed here to flag the function as thumb?
-
     getAssembler().setIsThumbFunc(Func);
-
-    MCSymbolData &SD = getAssembler().getOrCreateSymbolData(*Func);
-    SD.setFlags(SD.getFlags() | ELF_Other_ThumbFunc);
+    EmitSymbolAttribute(Func, MCSA_ELF_TypeFunction);
   }
 
   // Helper functions for ARM exception handling directives
diff --git a/lib/Target/ARM/MCTargetDesc/ARMMCAsmInfo.h b/lib/Target/ARM/MCTargetDesc/ARMMCAsmInfo.h
index beaf6a4000..51cfa0adc1 100644
--- a/lib/Target/ARM/MCTargetDesc/ARMMCAsmInfo.h
+++ b/lib/Target/ARM/MCTargetDesc/ARMMCAsmInfo.h
@@ -35,13 +35,13 @@ namespace llvm {
   };
 
   class ARMCOFFMCAsmInfoMicrosoft : public MCAsmInfoMicrosoft {
-    void anchor();
+    void anchor() override;
   public:
     explicit ARMCOFFMCAsmInfoMicrosoft();
   };
 
   class ARMCOFFMCAsmInfoGNU : public MCAsmInfoGNUCOFF {
-    void anchor();
+    void anchor() override;
   public:
     explicit ARMCOFFMCAsmInfoGNU();
   };
diff --git a/lib/Target/ARM/MCTargetDesc/ARMMachObjectWriter.cpp b/lib/Target/ARM/MCTargetDesc/ARMMachObjectWriter.cpp
index 38ed5632e4..ecfa4e54b2 100644
--- a/lib/Target/ARM/MCTargetDesc/ARMMachObjectWriter.cpp
+++ b/lib/Target/ARM/MCTargetDesc/ARMMachObjectWriter.cpp
@@ -206,11 +206,11 @@ RecordARMScatteredHalfRelocation(MachObjectWriter *Writer,
     // The thumb bit shouldn't be set in the 'other-half' bit of the
     // relocation, but it will be set in FixedValue if the base symbol
     // is a thumb function. Clear it out here.
-    if (A_SD->getFlags() & SF_ThumbFunc)
+    if (Asm.isThumbFunc(A))
       FixedValue &= 0xfffffffe;
     break;
   case ARM::fixup_t2_movt_hi16:
-    if (A_SD->getFlags() & SF_ThumbFunc)
+    if (Asm.isThumbFunc(A))
       FixedValue &= 0xfffffffe;
     MovtBit = 1;
     // Fallthrough
diff --git a/lib/Target/ARM64/ARM64AddressTypePromotion.cpp b/lib/Target/ARM64/ARM64AddressTypePromotion.cpp
index c6e45def9a..be2b5eed2a 100644
--- a/lib/Target/ARM64/ARM64AddressTypePromotion.cpp
+++ b/lib/Target/ARM64/ARM64AddressTypePromotion.cpp
@@ -75,13 +75,13 @@ public:
     initializeARM64AddressTypePromotionPass(*PassRegistry::getPassRegistry());
   }
 
-  virtual const char *getPassName() const {
+  const char *getPassName() const override {
     return "ARM64 Address Type Promotion";
   }
 
   /// Iterate over the functions and promote the computation of interesting
   // sext instructions.
-  bool runOnFunction(Function &F);
+  bool runOnFunction(Function &F) override;
 
 private:
   /// The current function.
@@ -91,7 +91,7 @@ private:
   Type *ConsideredSExtType;
 
   // This transformation requires dominator info.
-  virtual void getAnalysisUsage(AnalysisUsage &AU) const {
+  void getAnalysisUsage(AnalysisUsage &AU) const override {
     AU.setPreservesCFG();
     AU.addRequired<DominatorTreeWrapperPass>();
     AU.addPreserved<DominatorTreeWrapperPass>();
diff --git a/lib/Target/ARM64/ARM64AdvSIMDScalarPass.cpp b/lib/Target/ARM64/ARM64AdvSIMDScalarPass.cpp
index 87eec8f616..da280f8be0 100644
--- a/lib/Target/ARM64/ARM64AdvSIMDScalarPass.cpp
+++ b/lib/Target/ARM64/ARM64AdvSIMDScalarPass.cpp
@@ -87,13 +87,13 @@ public:
   static char ID; // Pass identification, replacement for typeid.
   explicit ARM64AdvSIMDScalar() : MachineFunctionPass(ID) {}
 
-  virtual bool runOnMachineFunction(MachineFunction &F);
+  bool runOnMachineFunction(MachineFunction &F) override;
 
-  const char *getPassName() const {
+  const char *getPassName() const override {
     return "AdvSIMD Scalar Operation Optimization";
   }
 
-  virtual void getAnalysisUsage(AnalysisUsage &AU) const {
+  void getAnalysisUsage(AnalysisUsage &AU) const override {
     AU.setPreservesCFG();
     MachineFunctionPass::getAnalysisUsage(AU);
   }
diff --git a/lib/Target/ARM64/ARM64AsmPrinter.cpp b/lib/Target/ARM64/ARM64AsmPrinter.cpp
index 615cb2884d..bc6fef1aa4 100644
--- a/lib/Target/ARM64/ARM64AsmPrinter.cpp
+++ b/lib/Target/ARM64/ARM64AsmPrinter.cpp
@@ -56,7 +56,7 @@ public:
         MCInstLowering(OutContext, *Mang, *this), SM(*this), ARM64FI(nullptr),
         LOHLabelCounter(0) {}
 
-  virtual const char *getPassName() const { return "ARM64 Assembly Printer"; }
+  const char *getPassName() const override { return "ARM64 Assembly Printer"; }
 
   /// \brief Wrapper for MCInstLowering.lowerOperand() for the
   /// tblgen'erated pseudo lowering.
@@ -73,14 +73,14 @@ public:
   bool emitPseudoExpansionLowering(MCStreamer &OutStreamer,
                                    const MachineInstr *MI);
 
-  void EmitInstruction(const MachineInstr *MI);
+  void EmitInstruction(const MachineInstr *MI) override;
 
-  void getAnalysisUsage(AnalysisUsage &AU) const {
+  void getAnalysisUsage(AnalysisUsage &AU) const override {
     AsmPrinter::getAnalysisUsage(AU);
     AU.setPreservesAll();
   }
 
-  bool runOnMachineFunction(MachineFunction &F) {
+  bool runOnMachineFunction(MachineFunction &F) override {
     ARM64FI = F.getInfo<ARM64FunctionInfo>();
     return AsmPrinter::runOnMachineFunction(F);
   }
@@ -95,17 +95,17 @@ private:
 
   bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
                        unsigned AsmVariant, const char *ExtraCode,
-                       raw_ostream &O);
+                       raw_ostream &O) override;
   bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum,
                              unsigned AsmVariant, const char *ExtraCode,
-                             raw_ostream &O);
+                             raw_ostream &O) override;
 
   void PrintDebugValueComment(const MachineInstr *MI, raw_ostream &OS);
 
-  void EmitFunctionBodyEnd();
+  void EmitFunctionBodyEnd() override;
 
-  MCSymbol *GetCPISymbol(unsigned CPID) const;
-  void EmitEndOfAsmFile(Module &M);
+  MCSymbol *GetCPISymbol(unsigned CPID) const override;
+  void EmitEndOfAsmFile(Module &M) override;
   ARM64FunctionInfo *ARM64FI;
 
   /// \brief Emit the LOHs contained in ARM64FI.
diff --git a/lib/Target/ARM64/ARM64BranchRelaxation.cpp b/lib/Target/ARM64/ARM64BranchRelaxation.cpp
index 06c6733ee6..cbe97edde2 100644
--- a/lib/Target/ARM64/ARM64BranchRelaxation.cpp
+++ b/lib/Target/ARM64/ARM64BranchRelaxation.cpp
@@ -94,9 +94,9 @@ public:
   static char ID;
   ARM64BranchRelaxation() : MachineFunctionPass(ID) {}
 
-  virtual bool runOnMachineFunction(MachineFunction &MF);
+  bool runOnMachineFunction(MachineFunction &MF) override;
 
-  virtual const char *getPassName() const {
+  const char *getPassName() const override {
     return "ARM64 branch relaxation pass";
   }
 };
diff --git a/lib/Target/ARM64/ARM64CleanupLocalDynamicTLSPass.cpp b/lib/Target/ARM64/ARM64CleanupLocalDynamicTLSPass.cpp
index e3f8248751..dce1301b92 100644
--- a/lib/Target/ARM64/ARM64CleanupLocalDynamicTLSPass.cpp
+++ b/lib/Target/ARM64/ARM64CleanupLocalDynamicTLSPass.cpp
@@ -38,7 +38,7 @@ struct LDTLSCleanup : public MachineFunctionPass {
   static char ID;
   LDTLSCleanup() : MachineFunctionPass(ID) {}
 
-  virtual bool runOnMachineFunction(MachineFunction &MF) {
+  bool runOnMachineFunction(MachineFunction &MF) override {
     ARM64FunctionInfo *AFI = MF.getInfo<ARM64FunctionInfo>();
     if (AFI->getNumLocalDynamicTLSAccesses() < 2) {
       // No point folding accesses if there isn't at least two.
@@ -129,11 +129,11 @@ struct LDTLSCleanup : public MachineFunctionPass {
     return Copy;
   }
 
-  virtual const char *getPassName() const {
+  const char *getPassName() const override {
     return "Local Dynamic TLS Access Clean-up";
   }
 
-  virtual void getAnalysisUsage(AnalysisUsage &AU) const {
+  void getAnalysisUsage(AnalysisUsage &AU) const override {
     AU.setPreservesCFG();
     AU.addRequired<MachineDominatorTree>();
     MachineFunctionPass::getAnalysisUsage(AU);
diff --git a/lib/Target/ARM64/ARM64CollectLOH.cpp b/lib/Target/ARM64/ARM64CollectLOH.cpp
index 7b8a270b89..8b48f3ae9b 100644
--- a/lib/Target/ARM64/ARM64CollectLOH.cpp
+++ b/lib/Target/ARM64/ARM64CollectLOH.cpp
@@ -174,13 +174,13 @@ struct ARM64CollectLOH : public MachineFunctionPass {
     initializeARM64CollectLOHPass(*PassRegistry::getPassRegistry());
   }
 
-  virtual bool runOnMachineFunction(MachineFunction &MF);
+  bool runOnMachineFunction(MachineFunction &MF) override;
 
-  virtual const char *getPassName() const {
+  const char *getPassName() const override {
     return "ARM64 Collect Linker Optimization Hint (LOH)";
   }
 
-  void getAnalysisUsage(AnalysisUsage &AU) const {
+  void getAnalysisUsage(AnalysisUsage &AU) const override {
     AU.setPreservesAll();
     MachineFunctionPass::getAnalysisUsage(AU);
     AU.addRequired<MachineDominatorTree>();
diff --git a/lib/Target/ARM64/ARM64ConditionalCompares.cpp b/lib/Target/ARM64/ARM64ConditionalCompares.cpp
index 16324ffa77..2243cce51a 100644
--- a/lib/Target/ARM64/ARM64ConditionalCompares.cpp
+++ b/lib/Target/ARM64/ARM64ConditionalCompares.cpp
@@ -63,8 +63,8 @@ STATISTIC(NumCmpBranchRejs, "Number of ccmps rejected (CmpBB branch)");
 STATISTIC(NumCmpTermRejs, "Number of ccmps rejected (CmpBB is cbz...)");
 STATISTIC(NumImmRangeRejs, "Number of ccmps rejected (Imm out of range)");
 STATISTIC(NumLiveDstRejs, "Number of ccmps rejected (Cmp dest live)");
-STATISTIC(NumMultCPSRUses, "Number of ccmps rejected (CPSR used)");
-STATISTIC(NumUnknCPSRDefs, "Number of ccmps rejected (CPSR def unknown)");
+STATISTIC(NumMultNZCVUses, "Number of ccmps rejected (NZCV used)");
+STATISTIC(NumUnknNZCVDefs, "Number of ccmps rejected (NZCV def unknown)");
 
 STATISTIC(NumSpeculateRejs, "Number of ccmps rejected (Can't speculate)");
 
@@ -300,7 +300,7 @@ MachineInstr *SSACCmpConv::findConvertibleCompare(MachineBasicBlock *MBB) {
   if (I == MBB->end())
     return nullptr;
   // The terminator must be controlled by the flags.
-  if (!I->readsRegister(ARM64::CPSR)) {
+  if (!I->readsRegister(ARM64::NZCV)) {
     switch (I->getOpcode()) {
     case ARM64::CBZW:
     case ARM64::CBZX:
@@ -351,20 +351,20 @@ MachineInstr *SSACCmpConv::findConvertibleCompare(MachineBasicBlock *MBB) {
 
     // Check for flag reads and clobbers.
     MIOperands::PhysRegInfo PRI =
-        MIOperands(I).analyzePhysReg(ARM64::CPSR, TRI);
+        MIOperands(I).analyzePhysReg(ARM64::NZCV, TRI);
 
     if (PRI.Reads) {
       // The ccmp doesn't produce exactly the same flags as the original
       // compare, so reject the transform if there are uses of the flags
       // besides the terminators.
       DEBUG(dbgs() << "Can't create ccmp with multiple uses: " << *I);
-      ++NumMultCPSRUses;
+      ++NumMultNZCVUses;
       return nullptr;
     }
 
     if (PRI.Clobbers) {
       DEBUG(dbgs() << "Not convertible compare: " << *I);
-      ++NumUnknCPSRDefs;
+      ++NumUnknNZCVDefs;
       return nullptr;
     }
   }
@@ -379,7 +379,7 @@ MachineInstr *SSACCmpConv::findConvertibleCompare(MachineBasicBlock *MBB) {
 ///
 bool SSACCmpConv::canSpeculateInstrs(MachineBasicBlock *MBB,
                                      const MachineInstr *CmpMI) {
-  // Reject any live-in physregs. It's probably CPSR/EFLAGS, and very hard to
+  // Reject any live-in physregs. It's probably NZCV/EFLAGS, and very hard to
   // get right.
   if (!MBB->livein_empty()) {
     DEBUG(dbgs() << "BB#" << MBB->getNumber() << " has live-ins.\n");
@@ -422,7 +422,7 @@ bool SSACCmpConv::canSpeculateInstrs(MachineBasicBlock *MBB,
     }
 
     // Only CmpMI is allowed to clobber the flags.
-    if (&I != CmpMI && I.modifiesRegister(ARM64::CPSR, TRI)) {
+    if (&I != CmpMI && I.modifiesRegister(ARM64::NZCV, TRI)) {
       DEBUG(dbgs() << "Clobbers flags: " << I);
       return false;
     }
@@ -736,9 +736,11 @@ class ARM64ConditionalCompares : public MachineFunctionPass {
 public:
   static char ID;
   ARM64ConditionalCompares() : MachineFunctionPass(ID) {}
-  void getAnalysisUsage(AnalysisUsage &AU) const;
-  bool runOnMachineFunction(MachineFunction &MF);
-  const char *getPassName() const { return "ARM64 Conditional Compares"; }
+  void getAnalysisUsage(AnalysisUsage &AU) const override;
+  bool runOnMachineFunction(MachineFunction &MF) override;
+  const char *getPassName() const override {
+    return "ARM64 Conditional Compares";
+  }
 
 private:
   bool tryConvert(MachineBasicBlock *);
diff --git a/lib/Target/ARM64/ARM64DeadRegisterDefinitionsPass.cpp b/lib/Target/ARM64/ARM64DeadRegisterDefinitionsPass.cpp
index eded8bd9e6..e8f03ec833 100644
--- a/lib/Target/ARM64/ARM64DeadRegisterDefinitionsPass.cpp
+++ b/lib/Target/ARM64/ARM64DeadRegisterDefinitionsPass.cpp
@@ -36,11 +36,11 @@ public:
   static char ID; // Pass identification, replacement for typeid.
   explicit ARM64DeadRegisterDefinitions() : MachineFunctionPass(ID) {}
 
-  virtual bool runOnMachineFunction(MachineFunction &F);
+  virtual bool runOnMachineFunction(MachineFunction &F) override;
 
-  const char *getPassName() const { return "Dead register definitions"; }
+  const char *getPassName() const override { return "Dead register definitions"; }
 
-  virtual void getAnalysisUsage(AnalysisUsage &AU) const {
+  virtual void getAnalysisUsage(AnalysisUsage &AU) const override {
     AU.setPreservesCFG();
     MachineFunctionPass::getAnalysisUsage(AU);
   }
diff --git a/lib/Target/ARM64/ARM64ExpandPseudoInsts.cpp b/lib/Target/ARM64/ARM64ExpandPseudoInsts.cpp
index 7928c7e586..a4b5d31314 100644
--- a/lib/Target/ARM64/ARM64ExpandPseudoInsts.cpp
+++ b/lib/Target/ARM64/ARM64ExpandPseudoInsts.cpp
@@ -29,9 +29,9 @@ public:
 
   const ARM64InstrInfo *TII;
 
-  virtual bool runOnMachineFunction(MachineFunction &Fn);
+  bool runOnMachineFunction(MachineFunction &Fn) override;
 
-  virtual const char *getPassName() const {
+  const char *getPassName() const override {
     return "ARM64 pseudo instruction expansion pass";
   }
 
diff --git a/lib/Target/ARM64/ARM64FastISel.cpp b/lib/Target/ARM64/ARM64FastISel.cpp
index 459c48030f..c43f2af15b 100644
--- a/lib/Target/ARM64/ARM64FastISel.cpp
+++ b/lib/Target/ARM64/ARM64FastISel.cpp
@@ -147,8 +147,8 @@ private:
 
 public:
   // Backend specific FastISel code.
-  virtual unsigned TargetMaterializeAlloca(const AllocaInst *AI);
-  virtual unsigned TargetMaterializeConstant(const Constant *C);
+  unsigned TargetMaterializeAlloca(const AllocaInst *AI) override;
+  unsigned TargetMaterializeConstant(const Constant *C) override;
 
   explicit ARM64FastISel(FunctionLoweringInfo &funcInfo,
                          const TargetLibraryInfo *libInfo)
@@ -157,7 +157,7 @@ public:
     Context = &funcInfo.Fn->getContext();
   }
 
-  virtual bool TargetSelectInstruction(const Instruction *I);
+  bool TargetSelectInstruction(const Instruction *I) override;
 
 #include "ARM64GenFastISel.inc"
 };
@@ -197,6 +197,9 @@ unsigned ARM64FastISel::TargetMaterializeAlloca(const AllocaInst *AI) {
 }
 
 unsigned ARM64FastISel::ARM64MaterializeFP(const ConstantFP *CFP, MVT VT) {
+  if (VT != MVT::f32 && VT != MVT::f64)
+    return 0;
+
   const APFloat Val = CFP->getValueAPF();
   bool is64bit = (VT == MVT::f64);
 
@@ -418,7 +421,11 @@ bool ARM64FastISel::isTypeLegal(Type *Ty, MVT &VT) {
     return false;
   VT = evt.getSimpleVT();
 
-  // Handle all legal types, i.e. a register that will directly hold this
+  // This is a legal type, but it's not something we handle in fast-isel.
+  if (VT == MVT::f128)
+    return false;
+
+  // Handle all other legal types, i.e. a register that will directly hold this
   // value.
   return TLI.isTypeLegal(VT);
 }
@@ -737,9 +744,9 @@ static ARM64CC::CondCode getCompareCC(CmpInst::Predicate Pred) {
   case CmpInst::ICMP_NE:
     return ARM64CC::NE;
   case CmpInst::ICMP_UGE:
-    return ARM64CC::CS;
+    return ARM64CC::HS;
   case CmpInst::ICMP_ULT:
-    return ARM64CC::CC;
+    return ARM64CC::LO;
   }
 }
 
@@ -1107,6 +1114,8 @@ bool ARM64FastISel::SelectFPToInt(const Instruction *I, bool Signed) {
     return false;
 
   EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType(), true);
+  if (SrcVT == MVT::f128)
+    return false;
 
   unsigned Opc;
   if (SrcVT == MVT::f64) {
@@ -1132,6 +1141,8 @@ bool ARM64FastISel::SelectIntToFP(const Instruction *I, bool Signed) {
   MVT DestVT;
   if (!isTypeLegal(I->getType(), DestVT) || DestVT.isVector())
     return false;
+  assert ((DestVT == MVT::f32 || DestVT == MVT::f64) &&
+          "Unexpected value type.");
 
   unsigned SrcReg = getRegForValue(I->getOperand(0));
   if (SrcReg == 0)
@@ -1578,6 +1589,8 @@ bool ARM64FastISel::SelectRet(const Instruction *I) {
     if (!RVEVT.isSimple())
       return false;
     MVT RVVT = RVEVT.getSimpleVT();
+    if (RVVT == MVT::f128)
+      return false;
     MVT DestVT = VA.getValVT();
     // Special handling for extended integers.
     if (RVVT != DestVT) {
@@ -1746,6 +1759,15 @@ unsigned ARM64FastISel::EmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
   // Handle i8 and i16 as i32.
   if (DestVT == MVT::i8 || DestVT == MVT::i16)
     DestVT = MVT::i32;
+  else if (DestVT == MVT::i64) {
+    unsigned Src64 = MRI.createVirtualRegister(&ARM64::GPR64RegClass);
+    BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
+            TII.get(ARM64::SUBREG_TO_REG), Src64)
+        .addImm(0)
+        .addReg(SrcReg)
+        .addImm(ARM64::sub_32);
+    SrcReg = Src64;
+  }
 
   unsigned ResultReg = createResultReg(TLI.getRegClassFor(DestVT));
   BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
diff --git a/lib/Target/ARM64/ARM64FrameLowering.h b/lib/Target/ARM64/ARM64FrameLowering.h
index 02edcdb590..1991a0a18d 100644
--- a/lib/Target/ARM64/ARM64FrameLowering.h
+++ b/lib/Target/ARM64/ARM64FrameLowering.h
@@ -36,38 +36,38 @@ public:
                                  unsigned FramePtr) const;
 
   void eliminateCallFramePseudoInstr(MachineFunction &MF,
-                                     MachineBasicBlock &MBB,
-                                     MachineBasicBlock::iterator I) const;
+                                  MachineBasicBlock &MBB,
+                                  MachineBasicBlock::iterator I) const override;
 
   /// emitProlog/emitEpilog - These methods insert prolog and epilog code into
   /// the function.
-  void emitPrologue(MachineFunction &MF) const;
-  void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
+  void emitPrologue(MachineFunction &MF) const override;
+  void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override;
 
-  int getFrameIndexOffset(const MachineFunction &MF, int FI) const;
+  int getFrameIndexOffset(const MachineFunction &MF, int FI) const override;
   int getFrameIndexReference(const MachineFunction &MF, int FI,
-                             unsigned &FrameReg) const;
+                             unsigned &FrameReg) const override;
   int resolveFrameIndexReference(const MachineFunction &MF, int FI,
                                  unsigned &FrameReg,
                                  bool PreferFP = false) const;
   bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
                                  MachineBasicBlock::iterator MI,
                                  const std::vector<CalleeSavedInfo> &CSI,
-                                 const TargetRegisterInfo *TRI) const;
+                                 const TargetRegisterInfo *TRI) const override;
 
   bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
-                                   MachineBasicBlock::iterator MI,
-                                   const std::vector<CalleeSavedInfo> &CSI,
-                                   const TargetRegisterInfo *TRI) const;
+                                  MachineBasicBlock::iterator MI,
+                                  const std::vector<CalleeSavedInfo> &CSI,
+                                  const TargetRegisterInfo *TRI) const override;
 
   /// \brief Can this function use the red zone for local allocations.
   bool canUseRedZone(const MachineFunction &MF) const;
 
-  bool hasFP(const MachineFunction &MF) const;
-  bool hasReservedCallFrame(const MachineFunction &MF) const;
+  bool hasFP(const MachineFunction &MF) const override;
+  bool hasReservedCallFrame(const MachineFunction &MF) const override;
 
   void processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
-                                            RegScavenger *RS) const;
+                                            RegScavenger *RS) const override;
 };
 
 } // End llvm namespace
diff --git a/lib/Target/ARM64/ARM64ISelDAGToDAG.cpp b/lib/Target/ARM64/ARM64ISelDAGToDAG.cpp
index 2971cba362..07e47e0f54 100644
--- a/lib/Target/ARM64/ARM64ISelDAGToDAG.cpp
+++ b/lib/Target/ARM64/ARM64ISelDAGToDAG.cpp
@@ -47,11 +47,11 @@ public:
       : SelectionDAGISel(tm, OptLevel), TM(tm),
         Subtarget(&TM.getSubtarget<ARM64Subtarget>()), ForCodeSize(false) {}
 
-  virtual const char *getPassName() const {
+  const char *getPassName() const override {
     return "ARM64 Instruction Selection";
   }
 
-  virtual bool runOnMachineFunction(MachineFunction &MF) {
+  bool runOnMachineFunction(MachineFunction &MF) override {
     AttributeSet FnAttrs = MF.getFunction()->getAttributes();
     ForCodeSize =
         FnAttrs.hasAttribute(AttributeSet::FunctionIndex,
@@ -60,13 +60,13 @@ public:
     return SelectionDAGISel::runOnMachineFunction(MF);
   }
 
-  SDNode *Select(SDNode *Node);
+  SDNode *Select(SDNode *Node) override;
 
   /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
   /// inline asm expressions.
-  virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
-                                            char ConstraintCode,
-                                            std::vector<SDValue> &OutOps);
+  bool SelectInlineAsmMemoryOperand(const SDValue &Op,
+                                    char ConstraintCode,
+                                    std::vector<SDValue> &OutOps) override;
 
   SDNode *SelectMLAV64LaneV128(SDNode *N);
   SDNode *SelectMULLV64LaneV128(unsigned IntNo, SDNode *N);
diff --git a/lib/Target/ARM64/ARM64ISelLowering.cpp b/lib/Target/ARM64/ARM64ISelLowering.cpp
index 024bc74168..ccd80175fa 100644
--- a/lib/Target/ARM64/ARM64ISelLowering.cpp
+++ b/lib/Target/ARM64/ARM64ISelLowering.cpp
@@ -213,7 +213,7 @@ ARM64TargetLowering::ARM64TargetLowering(ARM64TargetMachine &TM)
   // BlockAddress
   setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
 
-  // Add/Sub overflow ops with MVT::Glues are lowered to CPSR dependences.
+  // Add/Sub overflow ops with MVT::Glues are lowered to NZCV dependences.
   setOperationAction(ISD::ADDC, MVT::i32, Custom);
   setOperationAction(ISD::ADDE, MVT::i32, Custom);
   setOperationAction(ISD::SUBC, MVT::i32, Custom);
@@ -738,7 +738,7 @@ ARM64TargetLowering::EmitF128CSEL(MachineInstr *MI,
   unsigned IfTrueReg = MI->getOperand(1).getReg();
   unsigned IfFalseReg = MI->getOperand(2).getReg();
   unsigned CondCode = MI->getOperand(3).getImm();
-  bool CPSRKilled = MI->getOperand(4).isKill();
+  bool NZCVKilled = MI->getOperand(4).isKill();
 
   MachineBasicBlock *TrueBB = MF->CreateMachineBasicBlock(LLVM_BB);
   MachineBasicBlock *EndBB = MF->CreateMachineBasicBlock(LLVM_BB);
@@ -758,9 +758,9 @@ ARM64TargetLowering::EmitF128CSEL(MachineInstr *MI,
   // TrueBB falls through to the end.
   TrueBB->addSuccessor(EndBB);
 
-  if (!CPSRKilled) {
-    TrueBB->addLiveIn(ARM64::CPSR);
-    EndBB->addLiveIn(ARM64::CPSR);
+  if (!NZCVKilled) {
+    TrueBB->addLiveIn(ARM64::NZCV);
+    EndBB->addLiveIn(ARM64::NZCV);
   }
 
   BuildMI(*EndBB, EndBB->begin(), DL, TII->get(ARM64::PHI), DestReg)
@@ -822,9 +822,9 @@ static ARM64CC::CondCode changeIntCCToARM64CC(ISD::CondCode CC) {
   case ISD::SETUGT:
     return ARM64CC::HI;
   case ISD::SETUGE:
-    return ARM64CC::CS;
+    return ARM64CC::HS;
   case ISD::SETULT:
-    return ARM64CC::CC;
+    return ARM64CC::LO;
   case ISD::SETULE:
     return ARM64CC::LS;
   }
@@ -1052,7 +1052,7 @@ getARM64XALUOOp(ARM64CC::CondCode &CC, SDValue Op, SelectionDAG &DAG) {
     break;
   case ISD::UADDO:
     Opc = ARM64ISD::ADDS;
-    CC = ARM64CC::CS;
+    CC = ARM64CC::HS;
     break;
   case ISD::SSUBO:
     Opc = ARM64ISD::SUBS;
@@ -1060,7 +1060,7 @@ getARM64XALUOOp(ARM64CC::CondCode &CC, SDValue Op, SelectionDAG &DAG) {
     break;
   case ISD::USUBO:
     Opc = ARM64ISD::SUBS;
-    CC = ARM64CC::CC;
+    CC = ARM64CC::LO;
     break;
   // Multiply needs a little bit extra work.
   case ISD::SMULO:
@@ -1678,13 +1678,9 @@ SDValue ARM64TargetLowering::LowerFormalArguments(
         RC = &ARM64::GPR64RegClass;
       else if (RegVT == MVT::f32)
         RC = &ARM64::FPR32RegClass;
-      else if (RegVT == MVT::f64 || RegVT == MVT::v1i64 ||
-               RegVT == MVT::v1f64 || RegVT == MVT::v2i32 ||
-               RegVT == MVT::v4i16 || RegVT == MVT::v8i8)
+      else if (RegVT == MVT::f64 || RegVT.is64BitVector())
         RC = &ARM64::FPR64RegClass;
-      else if (RegVT == MVT::f128 ||RegVT == MVT::v2i64 ||
-               RegVT == MVT::v4i32||RegVT == MVT::v8i16 ||
-               RegVT == MVT::v16i8)
+      else if (RegVT == MVT::f128 || RegVT.is128BitVector())
         RC = &ARM64::FPR128RegClass;
       else
         llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering");
@@ -2354,7 +2350,7 @@ ARM64TargetLowering::LowerDarwinGlobalTLSAddress(SDValue Op,
   MFI->setAdjustsStack(true);
 
   // TLS calls preserve all registers except those that absolutely must be
-  // trashed: X0 (it takes an argument), LR (it's a call) and CPSR (let's not be
+  // trashed: X0 (it takes an argument), LR (it's a call) and NZCV (let's not be
   // silly).
   const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
   const ARM64RegisterInfo *ARI = static_cast<const ARM64RegisterInfo *>(TRI);
@@ -2375,7 +2371,7 @@ ARM64TargetLowering::LowerDarwinGlobalTLSAddress(SDValue Op,
 /// have a descriptor, accessible via a PC-relative ADRP, and whose first entry
 /// is a function pointer to carry out the resolution. This function takes the
 /// address of the descriptor in X0 and returns the TPIDR_EL0 offset in X0. All
-/// other registers (except LR, CPSR) are preserved.
+/// other registers (except LR, NZCV) are preserved.
 ///
 /// Thus, the ideal call sequence on AArch64 is:
 ///
@@ -2402,7 +2398,7 @@ SDValue ARM64TargetLowering::LowerELFTLSDescCall(SDValue SymAddr,
   SDValue Func = DAG.getNode(ARM64ISD::LOADgot, DL, PtrVT, SymAddr);
 
   // TLS calls preserve all registers except those that absolutely must be
-  // trashed: X0 (it takes an argument), LR (it's a call) and CPSR (let's not be
+  // trashed: X0 (it takes an argument), LR (it's a call) and NZCV (let's not be
   // silly).
   const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
   const ARM64RegisterInfo *ARI = static_cast<const ARM64RegisterInfo *>(TRI);
@@ -3606,7 +3602,7 @@ ARM64TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
     }
   }
   if (StringRef("{cc}").equals_lower(Constraint))
-    return std::make_pair(unsigned(ARM64::CPSR), &ARM64::CCRRegClass);
+    return std::make_pair(unsigned(ARM64::NZCV), &ARM64::CCRRegClass);
 
   // Use the default implementation in TargetLowering to convert the register
   // constraint into a member of a register class.
@@ -3981,40 +3977,41 @@ static bool isSingletonEXTMask(ArrayRef<int> M, EVT VT, unsigned &Imm) {
 // vector sources of the shuffle are different.
 static bool isEXTMask(ArrayRef<int> M, EVT VT, bool &ReverseEXT,
                       unsigned &Imm) {
-  unsigned NumElts = VT.getVectorNumElements();
-  ReverseEXT = false;
+  // Look for the first non-undef element.
+  const int *FirstRealElt = std::find_if(M.begin(), M.end(),
+      [](int Elt) {return Elt >= 0;});
 
-  // Look for the first non-undef choice and count backwards from
-  // that. E.g. <-1, -1, 3, ...> means that an EXT must start at 3 - 2 = 1. This
-  // guarantees that at least one index is correct.
-  const int *FirstRealElt =
-      std::find_if(M.begin(), M.end(), [](int Elt) { return Elt >= 0; });
-  assert(FirstRealElt != M.end() && "Completely UNDEF shuffle? Why bother?");
-  Imm = *FirstRealElt - (FirstRealElt - M.begin());
+  // Benefit form APInt to handle overflow when calculating expected element.
+  unsigned NumElts = VT.getVectorNumElements();
+  unsigned MaskBits = APInt(32, NumElts * 2).logBase2();
+  APInt ExpectedElt = APInt(MaskBits, *FirstRealElt + 1);
+  // The following shuffle indices must be the successive elements after the
+  // first real element.
+  const int *FirstWrongElt = std::find_if(FirstRealElt + 1, M.end(),
+      [&](int Elt) {return Elt != ExpectedElt++ && Elt != -1;});
+  if (FirstWrongElt != M.end())
+    return false;
 
-  // If this is a VEXT shuffle, the immediate value is the index of the first
-  // element.  The other shuffle indices must be the successive elements after
-  // the first one.
-  unsigned ExpectedElt = Imm;
-  for (unsigned i = 1; i < NumElts; ++i) {
-    // Increment the expected index.  If it wraps around, it may still be
-    // a VEXT but the source vectors must be swapped.
-    ExpectedElt += 1;
-    if (ExpectedElt == NumElts * 2) {
-      ExpectedElt = 0;
+  // The index of an EXT is the first element if it is not UNDEF.
+  // Watch out for the beginning UNDEFs. The EXT index should be the expected
+  // value of the first element.
+  // E.g. <-1, -1, 3, ...> is treated as <1, 2, 3, ...>.
+  //      <-1, -1, 0, 1, ...> is treated as <IDX, IDX+1, 0, 1, ...>. IDX is
+  // equal to the ExpectedElt.
+  Imm = (M[0] >= 0) ? static_cast<unsigned>(M[0]) : ExpectedElt.getZExtValue();
+
+  // If no beginning UNDEFs, do swap when M[0] >= NumElts.
+  if (M[0] >= 0 && Imm >= NumElts) {
+    ReverseEXT = true;
+    Imm -= NumElts;
+  } else if (M[0] < 0) {
+    // Only do swap when beginning UNDEFs more than the first real element,
+    if (*FirstRealElt < FirstRealElt - M.begin())
       ReverseEXT = true;
-    }
-
-    if (M[i] < 0)
-      continue; // ignore UNDEF indices
-    if (ExpectedElt != static_cast<unsigned>(M[i]))
-      return false;
+    if (Imm >= NumElts)
+      Imm -= NumElts;
   }
 
-  // Adjust the index value if the source operands will be swapped.
-  if (ReverseEXT)
-    Imm -= NumElts;
-
   return true;
 }
 
@@ -4357,7 +4354,7 @@ static SDValue GenerateTBL(SDValue Op, ArrayRef<int> ShuffleMask,
         ISD::INTRINSIC_WO_CHAIN, DL, IndexVT,
         DAG.getConstant(Intrinsic::arm64_neon_tbl1, MVT::i32), V1Cst,
         DAG.getNode(ISD::BUILD_VECTOR, DL, IndexVT,
-                    ArrayRef<SDValue>(TBLMask.data(), IndexLen)));
+                    makeArrayRef(TBLMask.data(), IndexLen)));
   } else {
     if (IndexLen == 8) {
       V1Cst = DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v16i8, V1Cst, V2Cst);
@@ -4365,7 +4362,7 @@ static SDValue GenerateTBL(SDValue Op, ArrayRef<int> ShuffleMask,
           ISD::INTRINSIC_WO_CHAIN, DL, IndexVT,
           DAG.getConstant(Intrinsic::arm64_neon_tbl1, MVT::i32), V1Cst,
           DAG.getNode(ISD::BUILD_VECTOR, DL, IndexVT,
-                      ArrayRef<SDValue>(TBLMask.data(), IndexLen)));
+                      makeArrayRef(TBLMask.data(), IndexLen)));
     } else {
       // FIXME: We cannot, for the moment, emit a TBL2 instruction because we
       // cannot currently represent the register constraints on the input
@@ -4377,7 +4374,7 @@ static SDValue GenerateTBL(SDValue Op, ArrayRef<int> ShuffleMask,
           ISD::INTRINSIC_WO_CHAIN, DL, IndexVT,
           DAG.getConstant(Intrinsic::arm64_neon_tbl2, MVT::i32), V1Cst, V2Cst,
           DAG.getNode(ISD::BUILD_VECTOR, DL, IndexVT,
-                      ArrayRef<SDValue>(TBLMask.data(), IndexLen)));
+                      makeArrayRef(TBLMask.data(), IndexLen)));
     }
   }
   return DAG.getNode(ISD::BITCAST, DL, Op.getValueType(), Shuffle);
@@ -5556,7 +5553,7 @@ static SDValue EmitVectorComparison(SDValue LHS, SDValue RHS,
     return DAG.getNode(ARM64ISD::CMGE, dl, VT, RHS, LHS);
   case ARM64CC::LS:
     return DAG.getNode(ARM64ISD::CMHS, dl, VT, RHS, LHS);
-  case ARM64CC::CC:
+  case ARM64CC::LO:
     return DAG.getNode(ARM64ISD::CMHI, dl, VT, RHS, LHS);
   case ARM64CC::LT:
     if (IsZero)
@@ -5564,7 +5561,7 @@ static SDValue EmitVectorComparison(SDValue LHS, SDValue RHS,
     return DAG.getNode(ARM64ISD::CMGT, dl, VT, RHS, LHS);
   case ARM64CC::HI:
     return DAG.getNode(ARM64ISD::CMHI, dl, VT, LHS, RHS);
-  case ARM64CC::CS:
+  case ARM64CC::HS:
     return DAG.getNode(ARM64ISD::CMHS, dl, VT, LHS, RHS);
   }
 }
diff --git a/lib/Target/ARM64/ARM64ISelLowering.h b/lib/Target/ARM64/ARM64ISelLowering.h
index ebecedccd5..ddaf347bf1 100644
--- a/lib/Target/ARM64/ARM64ISelLowering.h
+++ b/lib/Target/ARM64/ARM64ISelLowering.h
@@ -183,7 +183,7 @@ public:
   /// KnownZero/KnownOne bitsets.
   void computeMaskedBitsForTargetNode(const SDValue Op, APInt &KnownZero,
                                       APInt &KnownOne, const SelectionDAG &DAG,
-                                      unsigned Depth = 0) const;
+                                      unsigned Depth = 0) const override;
 
   MVT getScalarShiftAmountTy(EVT LHSTy) const override;
 
@@ -383,33 +383,36 @@ private:
   SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerFSINCOS(SDValue Op, SelectionDAG &DAG) const;
 
-  ConstraintType getConstraintType(const std::string &Constraint) const;
+  ConstraintType
+  getConstraintType(const std::string &Constraint) const override;
 
   /// Examine constraint string and operand type and determine a weight value.
   /// The operand object must already have been set up with the operand type.
-  ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &info,
-                                                  const char *constraint) const;
+  ConstraintWeight
+  getSingleConstraintMatchWeight(AsmOperandInfo &info,
+                                 const char *constraint) const override;
 
   std::pair<unsigned, const TargetRegisterClass *>
-  getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const;
+  getRegForInlineAsmConstraint(const std::string &Constraint,
+                               MVT VT) const override;
   void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
                                     std::vector<SDValue> &Ops,
-                                    SelectionDAG &DAG) const;
+                                    SelectionDAG &DAG) const override;
 
-  bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const;
-  bool mayBeEmittedAsTailCall(CallInst *CI) const;
+  bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override;
+  bool mayBeEmittedAsTailCall(CallInst *CI) const override;
   bool getIndexedAddressParts(SDNode *Op, SDValue &Base, SDValue &Offset,
                               ISD::MemIndexedMode &AM, bool &IsInc,
                               SelectionDAG &DAG) const;
   bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset,
                                  ISD::MemIndexedMode &AM,
-                                 SelectionDAG &DAG) const;
+                                 SelectionDAG &DAG) const override;
   bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base,
                                   SDValue &Offset, ISD::MemIndexedMode &AM,
-                                  SelectionDAG &DAG) const;
+                                  SelectionDAG &DAG) const override;
 
   void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
-                          SelectionDAG &DAG) const;
+                          SelectionDAG &DAG) const override;
 };
 
 namespace ARM64 {
diff --git a/lib/Target/ARM64/ARM64InstrFormats.td b/lib/Target/ARM64/ARM64InstrFormats.td
index 86ddb0722a..ea6484985e 100644
--- a/lib/Target/ARM64/ARM64InstrFormats.td
+++ b/lib/Target/ARM64/ARM64InstrFormats.td
@@ -191,7 +191,7 @@ def SImm7s4Operand : AsmOperandClass {
 }
 def simm7s4 : Operand<i32> {
   let ParserMatchClass = SImm7s4Operand;
-  let PrintMethod = "printImmScale4";
+  let PrintMethod = "printImmScale<4>";
 }
 
 // simm7s8 predicate - True if the immediate is a multiple of 8 in the range
@@ -202,7 +202,7 @@ def SImm7s8Operand : AsmOperandClass {
 }
 def simm7s8 : Operand<i32> {
   let ParserMatchClass = SImm7s8Operand;
-  let PrintMethod = "printImmScale8";
+  let PrintMethod = "printImmScale<8>";
 }
 
 // simm7s16 predicate - True if the immediate is a multiple of 16 in the range
@@ -213,7 +213,7 @@ def SImm7s16Operand : AsmOperandClass {
 }
 def simm7s16 : Operand<i32> {
   let ParserMatchClass = SImm7s16Operand;
-  let PrintMethod = "printImmScale16";
+  let PrintMethod = "printImmScale<16>";
 }
 
 // imm0_65535 predicate - True if the immediate is in the range [0,65535].
@@ -222,6 +222,7 @@ def imm0_65535 : Operand<i32>, ImmLeaf<i32, [{
   return ((uint32_t)Imm) < 65536;
 }]> {
   let ParserMatchClass = Imm0_65535Operand;
+  let PrintMethod = "printHexImm";
 }
 
 def Imm1_8Operand : AsmOperandClass {
@@ -452,6 +453,7 @@ def imm0_255 : Operand<i32>, ImmLeaf<i32, [{
   return ((uint32_t)Imm) < 256;
 }]> {
   let ParserMatchClass = Imm0_255Operand;
+  let PrintMethod = "printHexImm";
 }
 
 // imm0_127 predicate - True if the immediate is in the range [0,127]
@@ -460,6 +462,7 @@ def imm0_127 : Operand<i32>, ImmLeaf<i32, [{
   return ((uint32_t)Imm) < 128;
 }]> {
   let ParserMatchClass = Imm0_127Operand;
+  let PrintMethod = "printHexImm";
 }
 
 // NOTE: These imm0_N operands have to be of type i64 because i64 is the size
@@ -724,6 +727,7 @@ class CRmSystemI<Operand crmtype, bits<3> opc, string asm>
 def MRSSystemRegisterOperand : AsmOperandClass {
   let Name = "MRSSystemRegister";
   let ParserMethod = "tryParseSysReg";
+  let DiagnosticType = "MRS";
 }
 // concatenation of 1, op0, op1, CRn, CRm, op2. 16-bit immediate.
 def mrs_sysreg_op : Operand<i32> {
@@ -735,6 +739,7 @@ def mrs_sysreg_op : Operand<i32> {
 def MSRSystemRegisterOperand : AsmOperandClass {
   let Name = "MSRSystemRegister";
   let ParserMethod = "tryParseSysReg";
+  let DiagnosticType = "MSR";
 }
 def msr_sysreg_op : Operand<i32> {
   let ParserMatchClass = MSRSystemRegisterOperand;
@@ -749,7 +754,7 @@ class MRSI : RtSystemI<1, (outs GPR64:$Rt), (ins mrs_sysreg_op:$systemreg),
   let Inst{19-5} = systemreg;
 }
 
-// FIXME: Some of these def CPSR, others don't. Best way to model that?
+// FIXME: Some of these def NZCV, others don't. Best way to model that?
 // Explicitly modeling each of the system register as a register class
 // would do it, but feels like overkill at this point.
 class MSRI : RtSystemI<0, (outs), (ins msr_sysreg_op:$systemreg, GPR64:$Rt),
@@ -759,28 +764,29 @@ class MSRI : RtSystemI<0, (outs), (ins msr_sysreg_op:$systemreg, GPR64:$Rt),
   let Inst{19-5} = systemreg;
 }
 
-def SystemCPSRFieldOperand : AsmOperandClass {
-  let Name = "SystemCPSRField";
+def SystemPStateFieldOperand : AsmOperandClass {
+  let Name = "SystemPStateField";
   let ParserMethod = "tryParseSysReg";
 }
-def cpsrfield_op : Operand<i32> {
-  let ParserMatchClass = SystemCPSRFieldOperand;
-  let PrintMethod = "printSystemCPSRField";
+def pstatefield_op : Operand<i32> {
+  let ParserMatchClass = SystemPStateFieldOperand;
+  let PrintMethod = "printSystemPStateField";
 }
 
-let Defs = [CPSR] in
-class MSRcpsrI : SimpleSystemI<0, (ins cpsrfield_op:$cpsr_field, imm0_15:$imm),
-                               "msr", "\t$cpsr_field, $imm">,
-                 Sched<[WriteSys]> {
-  bits<6> cpsrfield;
+let Defs = [NZCV] in
+class MSRpstateI
+  : SimpleSystemI<0, (ins pstatefield_op:$pstate_field, imm0_15:$imm),
+                  "msr", "\t$pstate_field, $imm">,
+    Sched<[WriteSys]> {
+  bits<6> pstatefield;
   bits<4> imm;
   let Inst{20-19} = 0b00;
-  let Inst{18-16} = cpsrfield{5-3};
+  let Inst{18-16} = pstatefield{5-3};
   let Inst{15-12} = 0b0100;
   let Inst{11-8} = imm;
-  let Inst{7-5} = cpsrfield{2-0};
+  let Inst{7-5} = pstatefield{2-0};
 
-  let DecoderMethod = "DecodeSystemCPSRInstruction";
+  let DecoderMethod = "DecodeSystemPStateInstruction";
 }
 
 // SYS and SYSL generic system instructions.
@@ -879,11 +885,11 @@ def am_brcond : Operand<OtherVT> {
 
 class BranchCond : I<(outs), (ins dotCcode:$cond, am_brcond:$target),
                      "b", "$cond\t$target", "",
-                     [(ARM64brcond bb:$target, imm:$cond, CPSR)]>,
+                     [(ARM64brcond bb:$target, imm:$cond, NZCV)]>,
                    Sched<[WriteBr]> {
   let isBranch = 1;
   let isTerminator = 1;
-  let Uses = [CPSR];
+  let Uses = [NZCV];
 
   bits<4> cond;
   bits<19> target;
@@ -1038,7 +1044,7 @@ class BaseBaseAddSubCarry<bit isSub, RegisterClass regtype, string asm,
     : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm),
         asm, "\t$Rd, $Rn, $Rm", "", pattern>,
       Sched<[WriteI]> {
-  let Uses = [CPSR];
+  let Uses = [NZCV];
   bits<5> Rd;
   bits<5> Rn;
   bits<5> Rm;
@@ -1053,14 +1059,14 @@ class BaseBaseAddSubCarry<bit isSub, RegisterClass regtype, string asm,
 class BaseAddSubCarry<bit isSub, RegisterClass regtype, string asm,
                       SDNode OpNode>
     : BaseBaseAddSubCarry<isSub, regtype, asm,
-        [(set regtype:$Rd, (OpNode regtype:$Rn, regtype:$Rm, CPSR))]>;
+        [(set regtype:$Rd, (OpNode regtype:$Rn, regtype:$Rm, NZCV))]>;
 
 class BaseAddSubCarrySetFlags<bit isSub, RegisterClass regtype, string asm,
                               SDNode OpNode>
     : BaseBaseAddSubCarry<isSub, regtype, asm,
-        [(set regtype:$Rd, (OpNode regtype:$Rn, regtype:$Rm, CPSR)),
-         (implicit CPSR)]> {
-  let Defs = [CPSR];
+        [(set regtype:$Rd, (OpNode regtype:$Rn, regtype:$Rm, NZCV)),
+         (implicit NZCV)]> {
+  let Defs = [NZCV];
 }
 
 multiclass AddSubCarry<bit isSub, string asm, string asm_setflags,
@@ -1272,6 +1278,7 @@ class ADRI<bit page, string asm, Operand adr, list<dag> pattern>
 def movimm32_imm : Operand<i32> {
   let ParserMatchClass = Imm0_65535Operand;
   let EncoderMethod = "getMoveWideImmOpValue";
+  let PrintMethod = "printHexImm";
 }
 def movimm32_shift : Operand<i32> {
   let PrintMethod = "printShifter";
@@ -1518,7 +1525,7 @@ multiclass AddSub<bit isSub, string mnemonic,
 }
 
 multiclass AddSubS<bit isSub, string mnemonic, SDNode OpNode> {
-  let isCompare = 1, Defs = [CPSR] in {
+  let isCompare = 1, Defs = [NZCV] in {
   // Add/Subtract immediate
   def Wri  : BaseAddSubImm<isSub, 1, GPR32, GPR32sp, addsub_shifted_imm32,
                            mnemonic, OpNode> {
@@ -1561,7 +1568,7 @@ multiclass AddSubS<bit isSub, string mnemonic, SDNode OpNode> {
     let Inst{14-13} = 0b11;
     let Inst{31} = 1;
   }
-  } // Defs = [CPSR]
+  } // Defs = [NZCV]
 
   // Register/register aliases with no shift when SP is not used.
   def : AddSubRegAlias<mnemonic, !cast<Instruction>(NAME#"Wrs"),
@@ -1766,7 +1773,7 @@ multiclass LogicalImm<bits<2> opc, string mnemonic, SDNode OpNode> {
 }
 
 multiclass LogicalImmS<bits<2> opc, string mnemonic, SDNode OpNode> {
-  let isCompare = 1, Defs = [CPSR] in {
+  let isCompare = 1, Defs = [NZCV] in {
   def Wri  : BaseLogicalImm<opc, GPR32, GPR32, logical_imm32, mnemonic,
       [(set GPR32:$Rd, (OpNode GPR32:$Rn, logical_imm32:$imm))]> {
     let Inst{31} = 0;
@@ -1776,7 +1783,7 @@ multiclass LogicalImmS<bits<2> opc, string mnemonic, SDNode OpNode> {
       [(set GPR64:$Rd, (OpNode GPR64:$Rn, logical_imm64:$imm))]> {
     let Inst{31} = 1;
   }
-  } // end Defs = [CPSR]
+  } // end Defs = [NZCV]
 }
 
 class BaseLogicalRegPseudo<RegisterClass regtype, SDPatternOperator OpNode>
@@ -1807,10 +1814,10 @@ multiclass LogicalReg<bits<2> opc, bit N, string mnemonic,
                         !cast<Instruction>(NAME#"Xrs"), GPR64>;
 }
 
-// Split from LogicalReg to allow setting CPSR Defs
+// Split from LogicalReg to allow setting NZCV Defs
 multiclass LogicalRegS<bits<2> opc, bit N, string mnemonic,
                        SDPatternOperator OpNode = null_frag> {
-  let Defs = [CPSR], mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
+  let Defs = [NZCV], mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
   def Wrr : BaseLogicalRegPseudo<GPR32, OpNode>;
   def Xrr : BaseLogicalRegPseudo<GPR64, OpNode>;
 
@@ -1822,7 +1829,7 @@ multiclass LogicalRegS<bits<2> opc, bit N, string mnemonic,
             [(set GPR64:$Rd, (OpNode GPR64:$Rn, logical_shifted_reg64:$Rm))]> {
     let Inst{31} = 1;
   }
-  } // Defs = [CPSR]
+  } // Defs = [NZCV]
 
   def : LogicalRegAlias<mnemonic,
                         !cast<Instruction>(NAME#"Wrs"), GPR32>;
@@ -1845,8 +1852,8 @@ class BaseCondSetFlagsImm<bit op, RegisterClass regtype, string asm>
     : I<(outs), (ins regtype:$Rn, imm0_31:$imm, imm0_15:$nzcv, ccode:$cond),
          asm, "\t$Rn, $imm, $nzcv, $cond", "", []>,
       Sched<[WriteI]> {
-  let Uses = [CPSR];
-  let Defs = [CPSR];
+  let Uses = [NZCV];
+  let Defs = [NZCV];
 
   bits<5> Rn;
   bits<5> imm;
@@ -1877,8 +1884,8 @@ class BaseCondSetFlagsReg<bit op, RegisterClass regtype, string asm>
     : I<(outs), (ins regtype:$Rn, regtype:$Rm, imm0_15:$nzcv, ccode:$cond),
          asm, "\t$Rn, $Rm, $nzcv, $cond", "", []>,
       Sched<[WriteI]> {
-  let Uses = [CPSR];
-  let Defs = [CPSR];
+  let Uses = [NZCV];
+  let Defs = [NZCV];
 
   bits<5> Rn;
   bits<5> Rm;
@@ -1912,9 +1919,9 @@ class BaseCondSelect<bit op, bits<2> op2, RegisterClass regtype, string asm>
     : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm, ccode:$cond),
          asm, "\t$Rd, $Rn, $Rm, $cond", "",
          [(set regtype:$Rd,
-               (ARM64csel regtype:$Rn, regtype:$Rm, (i32 imm:$cond), CPSR))]>,
+               (ARM64csel regtype:$Rn, regtype:$Rm, (i32 imm:$cond), NZCV))]>,
       Sched<[WriteI]> {
-  let Uses = [CPSR];
+  let Uses = [NZCV];
 
   bits<5> Rd;
   bits<5> Rn;
@@ -1945,9 +1952,9 @@ class BaseCondSelectOp<bit op, bits<2> op2, RegisterClass regtype, string asm,
          asm, "\t$Rd, $Rn, $Rm, $cond", "",
          [(set regtype:$Rd,
                (ARM64csel regtype:$Rn, (frag regtype:$Rm),
-               (i32 imm:$cond), CPSR))]>,
+               (i32 imm:$cond), NZCV))]>,
       Sched<[WriteI]> {
-  let Uses = [CPSR];
+  let Uses = [NZCV];
 
   bits<5> Rd;
   bits<5> Rn;
@@ -1976,11 +1983,11 @@ multiclass CondSelectOp<bit op, bits<2> op2, string asm, PatFrag frag> {
     let Inst{31} = 1;
   }
 
-  def : Pat<(ARM64csel (frag GPR32:$Rm), GPR32:$Rn, (i32 imm:$cond), CPSR),
+  def : Pat<(ARM64csel (frag GPR32:$Rm), GPR32:$Rn, (i32 imm:$cond), NZCV),
             (!cast<Instruction>(NAME # Wr) GPR32:$Rn, GPR32:$Rm,
                                            (inv_cond_XFORM imm:$cond))>;
 
-  def : Pat<(ARM64csel (frag GPR64:$Rm), GPR64:$Rn, (i32 imm:$cond), CPSR),
+  def : Pat<(ARM64csel (frag GPR64:$Rm), GPR64:$Rn, (i32 imm:$cond), NZCV),
             (!cast<Instruction>(NAME # Xr) GPR64:$Rn, GPR64:$Rm,
                                            (inv_cond_XFORM imm:$cond))>;
 }
@@ -2008,7 +2015,7 @@ def MemoryIndexed8Operand : AsmOperandClass {
 }
 def am_indexed8 : Operand<i64>,
                   ComplexPattern<i64, 2, "SelectAddrModeIndexed8", []> {
-  let PrintMethod = "printAMIndexed8";
+  let PrintMethod = "printAMIndexed<8>";
   let EncoderMethod
       = "getAMIndexed8OpValue<ARM64::fixup_arm64_ldst_imm12_scale1>";
   let ParserMatchClass = MemoryIndexed8Operand;
@@ -2023,7 +2030,7 @@ def MemoryIndexed16Operand : AsmOperandClass {
 }
 def am_indexed16 : Operand<i64>,
                    ComplexPattern<i64, 2, "SelectAddrModeIndexed16", []> {
-  let PrintMethod = "printAMIndexed16";
+  let PrintMethod = "printAMIndexed<16>";
   let EncoderMethod
       = "getAMIndexed8OpValue<ARM64::fixup_arm64_ldst_imm12_scale2>";
   let ParserMatchClass = MemoryIndexed16Operand;
@@ -2038,7 +2045,7 @@ def MemoryIndexed32Operand : AsmOperandClass {
 }
 def am_indexed32 : Operand<i64>,
                    ComplexPattern<i64, 2, "SelectAddrModeIndexed32", []> {
-  let PrintMethod = "printAMIndexed32";
+  let PrintMethod = "printAMIndexed<32>";
   let EncoderMethod
       = "getAMIndexed8OpValue<ARM64::fixup_arm64_ldst_imm12_scale4>";
   let ParserMatchClass = MemoryIndexed32Operand;
@@ -2053,7 +2060,7 @@ def MemoryIndexed64Operand : AsmOperandClass {
 }
 def am_indexed64 : Operand<i64>,
                    ComplexPattern<i64, 2, "SelectAddrModeIndexed64", []> {
-  let PrintMethod = "printAMIndexed64";
+  let PrintMethod = "printAMIndexed<64>";
   let EncoderMethod
       = "getAMIndexed8OpValue<ARM64::fixup_arm64_ldst_imm12_scale8>";
   let ParserMatchClass = MemoryIndexed64Operand;
@@ -2068,7 +2075,7 @@ def MemoryIndexed128Operand : AsmOperandClass {
 }
 def am_indexed128 : Operand<i64>,
                    ComplexPattern<i64, 2, "SelectAddrModeIndexed128", []> {
-  let PrintMethod = "printAMIndexed128";
+  let PrintMethod = "printAMIndexed<128>";
   let EncoderMethod
       = "getAMIndexed8OpValue<ARM64::fixup_arm64_ldst_imm12_scale16>";
   let ParserMatchClass = MemoryIndexed128Operand;
@@ -2192,7 +2199,7 @@ def MemROAsmOperand64 : MemROAsmOperand<64>;
 def MemROAsmOperand128 : MemROAsmOperand<128>;
 
 class ro_indexed<int sz> : Operand<i64> { // ComplexPattern<...>
-  let PrintMethod = "printMemoryRegOffset"#sz;
+  let PrintMethod = "printMemoryRegOffset<" # sz # ">";
   let MIOperandInfo = (ops GPR64sp:$base, GPR64:$offset, i32imm:$extend);
 }
 
@@ -2460,12 +2467,12 @@ def MemoryUnscaledOperand : AsmOperandClass {
   let DiagnosticType = "InvalidMemoryIndexedSImm9";
 }
 class am_unscaled_operand : Operand<i64> {
-  let PrintMethod = "printAMUnscaled";
+  let PrintMethod = "printAMIndexed<8>";
   let ParserMatchClass = MemoryUnscaledOperand;
   let MIOperandInfo = (ops GPR64sp:$base, i64imm:$offset);
 }
 class am_unscaled_wb_operand : Operand<i64> {
-  let PrintMethod = "printAMUnscaledWB";
+  let PrintMethod = "printAMIndexedWB<8>";
   let ParserMatchClass = MemoryUnscaledOperand;
   let MIOperandInfo = (ops GPR64sp:$base, i64imm:$offset);
 }
@@ -2787,12 +2794,12 @@ def MemoryIndexed32SImm7 : AsmOperandClass {
   let DiagnosticType = "InvalidMemoryIndexed32SImm7";
 }
 def am_indexed32simm7 : Operand<i32> { // ComplexPattern<...>
-  let PrintMethod = "printAMIndexed32";
+  let PrintMethod = "printAMIndexed<32>";
   let ParserMatchClass = MemoryIndexed32SImm7;
   let MIOperandInfo = (ops GPR64sp:$base, i32imm:$offset);
 }
 def am_indexed32simm7_wb : Operand<i32> { // ComplexPattern<...>
-  let PrintMethod = "printAMIndexed32WB";
+  let PrintMethod = "printAMIndexedWB<32>";
   let ParserMatchClass = MemoryIndexed32SImm7;
   let MIOperandInfo = (ops GPR64sp:$base, i32imm:$offset);
 }
@@ -2802,12 +2809,12 @@ def MemoryIndexed64SImm7 : AsmOperandClass {
   let DiagnosticType = "InvalidMemoryIndexed64SImm7";
 }
 def am_indexed64simm7 : Operand<i32> { // ComplexPattern<...>
-  let PrintMethod = "printAMIndexed64";
+  let PrintMethod = "printAMIndexed<64>";
   let ParserMatchClass = MemoryIndexed64SImm7;
   let MIOperandInfo = (ops GPR64sp:$base, i32imm:$offset);
 }
 def am_indexed64simm7_wb : Operand<i32> { // ComplexPattern<...>
-  let PrintMethod = "printAMIndexed64WB";
+  let PrintMethod = "printAMIndexedWB<64>";
   let ParserMatchClass = MemoryIndexed64SImm7;
   let MIOperandInfo = (ops GPR64sp:$base, i32imm:$offset);
 }
@@ -2817,12 +2824,12 @@ def MemoryIndexed128SImm7 : AsmOperandClass {
   let DiagnosticType = "InvalidMemoryIndexed128SImm7";
 }
 def am_indexed128simm7 : Operand<i32> { // ComplexPattern<...>
-  let PrintMethod = "printAMIndexed128";
+  let PrintMethod = "printAMIndexed<128>";
   let ParserMatchClass = MemoryIndexed128SImm7;
   let MIOperandInfo = (ops GPR64sp:$base, i32imm:$offset);
 }
 def am_indexed128simm7_wb : Operand<i32> { // ComplexPattern<...>
-  let PrintMethod = "printAMIndexed128WB";
+  let PrintMethod = "printAMIndexedWB<128>";
   let ParserMatchClass = MemoryIndexed128SImm7;
   let MIOperandInfo = (ops GPR64sp:$base, i32imm:$offset);
 }
@@ -3606,27 +3613,27 @@ class BaseTwoOperandFPComparison<bit signalAllNans, RegisterClass regtype,
 
 multiclass FPComparison<bit signalAllNans, string asm,
                         SDPatternOperator OpNode = null_frag> {
-  let Defs = [CPSR] in {
+  let Defs = [NZCV] in {
   def Srr : BaseTwoOperandFPComparison<signalAllNans, FPR32, asm,
-      [(OpNode FPR32:$Rn, (f32 FPR32:$Rm)), (implicit CPSR)]> {
+      [(OpNode FPR32:$Rn, (f32 FPR32:$Rm)), (implicit NZCV)]> {
     let Inst{22} = 0;
   }
 
   def Sri : BaseOneOperandFPComparison<signalAllNans, FPR32, asm,
-      [(OpNode (f32 FPR32:$Rn), fpimm0), (implicit CPSR)]> {
+      [(OpNode (f32 FPR32:$Rn), fpimm0), (implicit NZCV)]> {
     let Inst{22} = 0;
   }
 
   def Drr : BaseTwoOperandFPComparison<signalAllNans, FPR64, asm,
-      [(OpNode FPR64:$Rn, (f64 FPR64:$Rm)), (implicit CPSR)]> {
+      [(OpNode FPR64:$Rn, (f64 FPR64:$Rm)), (implicit NZCV)]> {
     let Inst{22} = 1;
   }
 
   def Dri : BaseOneOperandFPComparison<signalAllNans, FPR64, asm,
-      [(OpNode (f64 FPR64:$Rn), fpimm0), (implicit CPSR)]> {
+      [(OpNode (f64 FPR64:$Rn), fpimm0), (implicit NZCV)]> {
     let Inst{22} = 1;
   }
-  } // Defs = [CPSR]
+  } // Defs = [NZCV]
 }
 
 //---
@@ -3655,7 +3662,7 @@ class BaseFPCondComparison<bit signalAllNans,
 }
 
 multiclass FPCondComparison<bit signalAllNans, string asm> {
-  let Defs = [CPSR], Uses = [CPSR] in {
+  let Defs = [NZCV], Uses = [NZCV] in {
   def Srr : BaseFPCondComparison<signalAllNans, FPR32, asm> {
     let Inst{22} = 0;
   }
@@ -3663,7 +3670,7 @@ multiclass FPCondComparison<bit signalAllNans, string asm> {
   def Drr : BaseFPCondComparison<signalAllNans, FPR64, asm> {
     let Inst{22} = 1;
   }
-  } // Defs = [CPSR], Uses = [CPSR]
+  } // Defs = [NZCV], Uses = [NZCV]
 }
 
 //---
@@ -3675,7 +3682,7 @@ class BaseFPCondSelect<RegisterClass regtype, ValueType vt, string asm>
          asm, "\t$Rd, $Rn, $Rm, $cond", "",
          [(set regtype:$Rd,
                (ARM64csel (vt regtype:$Rn), regtype:$Rm,
-                          (i32 imm:$cond), CPSR))]>,
+                          (i32 imm:$cond), NZCV))]>,
       Sched<[WriteF]> {
   bits<5> Rd;
   bits<5> Rn;
@@ -3692,7 +3699,7 @@ class BaseFPCondSelect<RegisterClass regtype, ValueType vt, string asm>
 }
 
 multiclass FPCondSelect<string asm> {
-  let Uses = [CPSR] in {
+  let Uses = [NZCV] in {
   def Srrr : BaseFPCondSelect<FPR32, f32, asm> {
     let Inst{22} = 0;
   }
@@ -3700,7 +3707,7 @@ multiclass FPCondSelect<string asm> {
   def Drrr : BaseFPCondSelect<FPR64, f64, asm> {
     let Inst{22} = 1;
   }
-  } // Uses = [CPSR]
+  } // Uses = [NZCV]
 }
 
 //---
@@ -4415,11 +4422,12 @@ multiclass SIMDMixedTwoVector<bit U, bits<5> opc, string asm,
 }
 
 class BaseSIMDCmpTwoVector<bit Q, bit U, bits<2> size, bits<5> opcode,
-                           RegisterOperand regtype, string asm, string kind,
+                           RegisterOperand regtype,
+                           string asm, string kind, string zero,
                            ValueType dty, ValueType sty, SDNode OpNode>
   : I<(outs regtype:$Rd), (ins regtype:$Rn), asm,
-      "{\t$Rd" # kind # ", $Rn" # kind # ", #0" #
-      "|" # kind # "\t$Rd, $Rn, #0}", "",
+      "{\t$Rd" # kind # ", $Rn" # kind # ", #" # zero #
+      "|" # kind # "\t$Rd, $Rn, #" # zero # "}", "",
       [(set (dty regtype:$Rd), (OpNode (sty regtype:$Rn)))]>,
     Sched<[WriteV]> {
   bits<5> Rd;
@@ -4440,25 +4448,25 @@ class BaseSIMDCmpTwoVector<bit Q, bit U, bits<2> size, bits<5> opcode,
 multiclass SIMDCmpTwoVector<bit U, bits<5> opc, string asm,
                             SDNode OpNode> {
   def v8i8rz  : BaseSIMDCmpTwoVector<0, U, 0b00, opc, V64,
-                                     asm, ".8b",
+                                     asm, ".8b", "0",
                                      v8i8, v8i8, OpNode>;
   def v16i8rz : BaseSIMDCmpTwoVector<1, U, 0b00, opc, V128,
-                                     asm, ".16b",
+                                     asm, ".16b", "0",
                                      v16i8, v16i8, OpNode>;
   def v4i16rz : BaseSIMDCmpTwoVector<0, U, 0b01, opc, V64,
-                                     asm, ".4h",
+                                     asm, ".4h", "0",
                                      v4i16, v4i16, OpNode>;
   def v8i16rz : BaseSIMDCmpTwoVector<1, U, 0b01, opc, V128,
-                                     asm, ".8h",
+                                     asm, ".8h", "0",
                                      v8i16, v8i16, OpNode>;
   def v2i32rz : BaseSIMDCmpTwoVector<0, U, 0b10, opc, V64,
-                                     asm, ".2s",
+                                     asm, ".2s", "0",
                                      v2i32, v2i32, OpNode>;
   def v4i32rz : BaseSIMDCmpTwoVector<1, U, 0b10, opc, V128,
-                                     asm, ".4s",
+                                     asm, ".4s", "0",
                                      v4i32, v4i32, OpNode>;
   def v2i64rz : BaseSIMDCmpTwoVector<1, U, 0b11, opc, V128,
-                                     asm, ".2d",
+                                     asm, ".2d", "0",
                                      v2i64, v2i64, OpNode>;
 }
 
@@ -4466,14 +4474,27 @@ multiclass SIMDCmpTwoVector<bit U, bits<5> opc, string asm,
 multiclass SIMDFPCmpTwoVector<bit U, bit S, bits<5> opc,
                               string asm, SDNode OpNode> {
   def v2i32rz : BaseSIMDCmpTwoVector<0, U, {S,0}, opc, V64,
-                                     asm, ".2s",
+                                     asm, ".2s", "0.0",
                                      v2i32, v2f32, OpNode>;
   def v4i32rz : BaseSIMDCmpTwoVector<1, U, {S,0}, opc, V128,
-                                     asm, ".4s",
+                                     asm, ".4s", "0.0",
                                      v4i32, v4f32, OpNode>;
   def v2i64rz : BaseSIMDCmpTwoVector<1, U, {S,1}, opc, V128,
-                                     asm, ".2d",
+                                     asm, ".2d", "0.0",
                                      v2i64, v2f64, OpNode>;
+
+  def : InstAlias<asm # " $Vd.2s, $Vn.2s, #0",
+                  (!cast<Instruction>(NAME # v2i32rz) V64:$Vd, V64:$Vn), 0>;
+  def : InstAlias<asm # " $Vd.4s, $Vn.4s, #0",
+                  (!cast<Instruction>(NAME # v4i32rz) V128:$Vd, V128:$Vn), 0>;
+  def : InstAlias<asm # " $Vd.2d, $Vn.2d, #0",
+                  (!cast<Instruction>(NAME # v2i64rz) V128:$Vd, V128:$Vn), 0>;
+  def : InstAlias<asm # ".2s $Vd, $Vn, #0",
+                  (!cast<Instruction>(NAME # v2i32rz) V64:$Vd, V64:$Vn), 0>;
+  def : InstAlias<asm # ".4s $Vd, $Vn, #0",
+                  (!cast<Instruction>(NAME # v4i32rz) V128:$Vd, V128:$Vn), 0>;
+  def : InstAlias<asm # ".2d $Vd, $Vn, #0",
+                  (!cast<Instruction>(NAME # v2i64rz) V128:$Vd, V128:$Vn), 0>;
 }
 
 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
@@ -5182,9 +5203,9 @@ class BaseSIMDTwoScalarTied<bit U, bits<2> size, bits<5> opcode,
 
 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
 class BaseSIMDCmpTwoScalar<bit U, bits<2> size, bits<5> opcode,
-                        RegisterClass regtype, string asm>
+                        RegisterClass regtype, string asm, string zero>
   : I<(outs regtype:$Rd), (ins regtype:$Rn), asm,
-      "\t$Rd, $Rn, #0", "", []>,
+      "\t$Rd, $Rn, #" # zero, "", []>,
     Sched<[WriteV]> {
   bits<5> Rd;
   bits<5> Rn;
@@ -5214,7 +5235,7 @@ class SIMDInexactCvtTwoScalar<bits<5> opcode, string asm>
 
 multiclass SIMDCmpTwoScalarD<bit U, bits<5> opc, string asm,
                              SDPatternOperator OpNode> {
-  def v1i64rz  : BaseSIMDCmpTwoScalar<U, 0b11, opc, FPR64, asm>;
+  def v1i64rz  : BaseSIMDCmpTwoScalar<U, 0b11, opc, FPR64, asm, "0">;
 
   def : Pat<(v1i64 (OpNode FPR64:$Rn)),
             (!cast<Instruction>(NAME # v1i64rz) FPR64:$Rn)>;
@@ -5222,8 +5243,13 @@ multiclass SIMDCmpTwoScalarD<bit U, bits<5> opc, string asm,
 
 multiclass SIMDCmpTwoScalarSD<bit U, bit S, bits<5> opc, string asm,
                               SDPatternOperator OpNode> {
-  def v1i64rz  : BaseSIMDCmpTwoScalar<U, {S,1}, opc, FPR64, asm>;
-  def v1i32rz  : BaseSIMDCmpTwoScalar<U, {S,0}, opc, FPR32, asm>;
+  def v1i64rz  : BaseSIMDCmpTwoScalar<U, {S,1}, opc, FPR64, asm, "0.0">;
+  def v1i32rz  : BaseSIMDCmpTwoScalar<U, {S,0}, opc, FPR32, asm, "0.0">;
+
+  def : InstAlias<asm # " $Rd, $Rn, #0",
+                  (!cast<Instruction>(NAME # v1i64rz) FPR64:$Rd, FPR64:$Rn)>;
+  def : InstAlias<asm # " $Rd, $Rn, #0",
+                  (!cast<Instruction>(NAME # v1i32rz) FPR32:$Rd, FPR32:$Rn)>;
 
   def : Pat<(v1i64 (OpNode (v1f64 FPR64:$Rn))),
             (!cast<Instruction>(NAME # v1i64rz) FPR64:$Rn)>;
diff --git a/lib/Target/ARM64/ARM64InstrInfo.cpp b/lib/Target/ARM64/ARM64InstrInfo.cpp
index 95b247a0a2..06cc40111c 100644
--- a/lib/Target/ARM64/ARM64InstrInfo.cpp
+++ b/lib/Target/ARM64/ARM64InstrInfo.cpp
@@ -301,8 +301,8 @@ static unsigned canFoldIntoCSel(const MachineRegisterInfo &MRI, unsigned VReg,
   switch (DefMI->getOpcode()) {
   case ARM64::ADDSXri:
   case ARM64::ADDSWri:
-    // if CPSR is used, do not fold.
-    if (DefMI->findRegisterDefOperandIdx(ARM64::CPSR, true) == -1)
+    // if NZCV is used, do not fold.
+    if (DefMI->findRegisterDefOperandIdx(ARM64::NZCV, true) == -1)
       return 0;
   // fall-through to ADDXri and ADDWri.
   case ARM64::ADDXri:
@@ -328,8 +328,8 @@ static unsigned canFoldIntoCSel(const MachineRegisterInfo &MRI, unsigned VReg,
 
   case ARM64::SUBSXrr:
   case ARM64::SUBSWrr:
-    // if CPSR is used, do not fold.
-    if (DefMI->findRegisterDefOperandIdx(ARM64::CPSR, true) == -1)
+    // if NZCV is used, do not fold.
+    if (DefMI->findRegisterDefOperandIdx(ARM64::NZCV, true) == -1)
       return 0;
   // fall-through to SUBXrr and SUBWrr.
   case ARM64::SUBXrr:
@@ -559,7 +559,7 @@ bool ARM64InstrInfo::analyzeCompare(const MachineInstr *MI, unsigned &SrcReg,
   case ARM64::ADDSXrr:
   case ARM64::ADDSXrs:
   case ARM64::ADDSXrx:
-    // Replace SUBSWrr with SUBWrr if CPSR is not used.
+    // Replace SUBSWrr with SUBWrr if NZCV is not used.
     SrcReg = MI->getOperand(1).getReg();
     SrcReg2 = MI->getOperand(2).getReg();
     CmpMask = ~0;
@@ -635,9 +635,9 @@ bool ARM64InstrInfo::optimizeCompareInstr(
     MachineInstr *CmpInstr, unsigned SrcReg, unsigned SrcReg2, int CmpMask,
     int CmpValue, const MachineRegisterInfo *MRI) const {
 
-  // Replace SUBSWrr with SUBWrr if CPSR is not used.
-  int Cmp_CPSR = CmpInstr->findRegisterDefOperandIdx(ARM64::CPSR, true);
-  if (Cmp_CPSR != -1) {
+  // Replace SUBSWrr with SUBWrr if NZCV is not used.
+  int Cmp_NZCV = CmpInstr->findRegisterDefOperandIdx(ARM64::NZCV, true);
+  if (Cmp_NZCV != -1) {
     unsigned NewOpc;
     switch (CmpInstr->getOpcode()) {
     default:
@@ -662,7 +662,7 @@ bool ARM64InstrInfo::optimizeCompareInstr(
 
     const MCInstrDesc &MCID = get(NewOpc);
     CmpInstr->setDesc(MCID);
-    CmpInstr->RemoveOperand(Cmp_CPSR);
+    CmpInstr->RemoveOperand(Cmp_NZCV);
     bool succeeded = UpdateOperandRegClass(CmpInstr);
     (void)succeeded;
     assert(succeeded && "Some operands reg class are incompatible!");
@@ -684,7 +684,7 @@ bool ARM64InstrInfo::optimizeCompareInstr(
 
   // We iterate backward, starting from the instruction before CmpInstr and
   // stop when reaching the definition of the source register or done with the
-  // basic block, to check whether CPSR is used or modified in between.
+  // basic block, to check whether NZCV is used or modified in between.
   MachineBasicBlock::iterator I = CmpInstr, E = MI,
                               B = CmpInstr->getParent()->begin();
 
@@ -697,15 +697,15 @@ bool ARM64InstrInfo::optimizeCompareInstr(
   if (MI->getParent() != CmpInstr->getParent())
     return false;
 
-  // Check that CPSR isn't set between the comparison instruction and the one we
+  // Check that NZCV isn't set between the comparison instruction and the one we
   // want to change.
   const TargetRegisterInfo *TRI = &getRegisterInfo();
   for (--I; I != E; --I) {
     const MachineInstr &Instr = *I;
 
-    if (Instr.modifiesRegister(ARM64::CPSR, TRI) ||
-        Instr.readsRegister(ARM64::CPSR, TRI))
-      // This instruction modifies or uses CPSR after the one we want to
+    if (Instr.modifiesRegister(ARM64::NZCV, TRI) ||
+        Instr.readsRegister(ARM64::NZCV, TRI))
+      // This instruction modifies or uses NZCV after the one we want to
       // change. We can't do this transformation.
       return false;
     if (I == B)
@@ -742,11 +742,11 @@ bool ARM64InstrInfo::optimizeCompareInstr(
   case ARM64::ANDXri:    NewOpc = ARM64::ANDSXri; break;
   }
 
-  // Scan forward for the use of CPSR.
+  // Scan forward for the use of NZCV.
   // When checking against MI: if it's a conditional code requires
   // checking of V bit, then this is not safe to do.
-  // It is safe to remove CmpInstr if CPSR is redefined or killed.
-  // If we are done with the basic block, we need to check whether CPSR is
+  // It is safe to remove CmpInstr if NZCV is redefined or killed.
+  // If we are done with the basic block, we need to check whether NZCV is
   // live-out.
   bool IsSafe = false;
   for (MachineBasicBlock::iterator I = CmpInstr,
@@ -756,11 +756,11 @@ bool ARM64InstrInfo::optimizeCompareInstr(
     for (unsigned IO = 0, EO = Instr.getNumOperands(); !IsSafe && IO != EO;
          ++IO) {
       const MachineOperand &MO = Instr.getOperand(IO);
-      if (MO.isRegMask() && MO.clobbersPhysReg(ARM64::CPSR)) {
+      if (MO.isRegMask() && MO.clobbersPhysReg(ARM64::NZCV)) {
         IsSafe = true;
         break;
       }
-      if (!MO.isReg() || MO.getReg() != ARM64::CPSR)
+      if (!MO.isReg() || MO.getReg() != ARM64::NZCV)
         continue;
       if (MO.isDef()) {
         IsSafe = true;
@@ -793,7 +793,7 @@ bool ARM64InstrInfo::optimizeCompareInstr(
       // It is not safe to remove Compare instruction if Overflow(V) is used.
       switch (CC) {
       default:
-        // CPSR can be used multiple times, we should continue.
+        // NZCV can be used multiple times, we should continue.
         break;
       case ARM64CC::VS:
       case ARM64CC::VC:
@@ -806,22 +806,22 @@ bool ARM64InstrInfo::optimizeCompareInstr(
     }
   }
 
-  // If CPSR is not killed nor re-defined, we should check whether it is
+  // If NZCV is not killed nor re-defined, we should check whether it is
   // live-out. If it is live-out, do not optimize.
   if (!IsSafe) {
     MachineBasicBlock *ParentBlock = CmpInstr->getParent();
     for (auto *MBB : ParentBlock->successors())
-      if (MBB->isLiveIn(ARM64::CPSR))
+      if (MBB->isLiveIn(ARM64::NZCV))
         return false;
   }
 
-  // Update the instruction to set CPSR.
+  // Update the instruction to set NZCV.
   MI->setDesc(get(NewOpc));
   CmpInstr->eraseFromParent();
   bool succeeded = UpdateOperandRegClass(MI);
   (void)succeeded;
   assert(succeeded && "Some operands reg class are incompatible!");
-  MI->addRegisterDefined(ARM64::CPSR, TRI);
+  MI->addRegisterDefined(ARM64::NZCV, TRI);
   return true;
 }
 
@@ -1591,7 +1591,7 @@ void llvm::emitFrameOffset(MachineBasicBlock &MBB,
                            MachineBasicBlock::iterator MBBI, DebugLoc DL,
                            unsigned DestReg, unsigned SrcReg, int Offset,
                            const ARM64InstrInfo *TII, MachineInstr::MIFlag Flag,
-                           bool SetCPSR) {
+                           bool SetNZCV) {
   if (DestReg == SrcReg && Offset == 0)
     return;
 
@@ -1611,7 +1611,7 @@ void llvm::emitFrameOffset(MachineBasicBlock &MBB,
   //  assert(Offset < (1 << 24) && "unimplemented reg plus immediate");
 
   unsigned Opc;
-  if (SetCPSR)
+  if (SetNZCV)
     Opc = isSub ? ARM64::SUBSXri : ARM64::ADDSXri;
   else
     Opc = isSub ? ARM64::SUBXri : ARM64::ADDXri;
diff --git a/lib/Target/ARM64/ARM64InstrInfo.h b/lib/Target/ARM64/ARM64InstrInfo.h
index 03822e1c3b..8f8165b02e 100644
--- a/lib/Target/ARM64/ARM64InstrInfo.h
+++ b/lib/Target/ARM64/ARM64InstrInfo.h
@@ -162,7 +162,7 @@ void emitFrameOffset(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
                      DebugLoc DL, unsigned DestReg, unsigned SrcReg, int Offset,
                      const ARM64InstrInfo *TII,
                      MachineInstr::MIFlag = MachineInstr::NoFlags,
-                     bool SetCPSR = false);
+                     bool SetNZCV = false);
 
 /// rewriteARM64FrameIndex - Rewrite MI to access 'Offset' bytes from the
 /// FP. Return false if the offset could not be handled directly in MI, and
diff --git a/lib/Target/ARM64/ARM64InstrInfo.td b/lib/Target/ARM64/ARM64InstrInfo.td
index ddcedee04c..455cdf320c 100644
--- a/lib/Target/ARM64/ARM64InstrInfo.td
+++ b/lib/Target/ARM64/ARM64InstrInfo.td
@@ -339,7 +339,7 @@ def : InstAlias<"isb", (ISB 0xf)>;
 
 def MRS    : MRSI;
 def MSR    : MSRI;
-def MSRcpsr: MSRcpsrI;
+def MSRpstate: MSRpstateI;
 
 // The thread pointer (on Linux, at least, where this has been implemented) is
 // TPIDR_EL0.
@@ -380,17 +380,17 @@ def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movz_symbol_g2:$sym, 32)>;
 def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movz_symbol_g1:$sym, 16)>;
 def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movz_symbol_g0:$sym, 0)>;
 
-def : InstAlias<"movz $Rd, $sym", (MOVZWi GPR32:$Rd, movz_symbol_g3:$sym, 48)>;
-def : InstAlias<"movz $Rd, $sym", (MOVZWi GPR32:$Rd, movz_symbol_g2:$sym, 32)>;
-def : InstAlias<"movz $Rd, $sym", (MOVZWi GPR32:$Rd, movz_symbol_g1:$sym, 16)>;
-def : InstAlias<"movz $Rd, $sym", (MOVZWi GPR32:$Rd, movz_symbol_g0:$sym, 0)>;
-
 def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movk_symbol_g3:$sym, 48)>;
 def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movk_symbol_g2:$sym, 32)>;
 def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movk_symbol_g1:$sym, 16)>;
 def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movk_symbol_g0:$sym, 0)>;
 
-def : InstAlias<"movk $Rd, $sym", (MOVKWi GPR32:$Rd, movk_symbol_g2:$sym, 32)>;
+def : InstAlias<"movz $Rd, $sym", (MOVZWi GPR32:$Rd, movz_symbol_g1:$sym, 16)>;
+def : InstAlias<"movz $Rd, $sym", (MOVZWi GPR32:$Rd, movz_symbol_g0:$sym, 0)>;
+
+def : InstAlias<"movn $Rd, $sym", (MOVNWi GPR32:$Rd, movz_symbol_g1:$sym, 16)>;
+def : InstAlias<"movn $Rd, $sym", (MOVNWi GPR32:$Rd, movz_symbol_g0:$sym, 0)>;
+
 def : InstAlias<"movk $Rd, $sym", (MOVKWi GPR32:$Rd, movk_symbol_g1:$sym, 16)>;
 def : InstAlias<"movk $Rd, $sym", (MOVKWi GPR32:$Rd, movk_symbol_g0:$sym, 0)>;
 
@@ -544,19 +544,19 @@ defm SDIV_Int : Div<1, "sdiv", int_arm64_sdiv>;
 }
 
 // Variable shift
-defm ASRV : Shift<0b10, "asrv", sra>;
-defm LSLV : Shift<0b00, "lslv", shl>;
-defm LSRV : Shift<0b01, "lsrv", srl>;
-defm RORV : Shift<0b11, "rorv", rotr>;
-
-def : ShiftAlias<"asr", ASRVWr, GPR32>;
-def : ShiftAlias<"asr", ASRVXr, GPR64>;
-def : ShiftAlias<"lsl", LSLVWr, GPR32>;
-def : ShiftAlias<"lsl", LSLVXr, GPR64>;
-def : ShiftAlias<"lsr", LSRVWr, GPR32>;
-def : ShiftAlias<"lsr", LSRVXr, GPR64>;
-def : ShiftAlias<"ror", RORVWr, GPR32>;
-def : ShiftAlias<"ror", RORVXr, GPR64>;
+defm ASRV : Shift<0b10, "asr", sra>;
+defm LSLV : Shift<0b00, "lsl", shl>;
+defm LSRV : Shift<0b01, "lsr", srl>;
+defm RORV : Shift<0b11, "ror", rotr>;
+
+def : ShiftAlias<"asrv", ASRVWr, GPR32>;
+def : ShiftAlias<"asrv", ASRVXr, GPR64>;
+def : ShiftAlias<"lslv", LSLVWr, GPR32>;
+def : ShiftAlias<"lslv", LSLVXr, GPR64>;
+def : ShiftAlias<"lsrv", LSRVWr, GPR32>;
+def : ShiftAlias<"lsrv", LSRVXr, GPR64>;
+def : ShiftAlias<"rorv", RORVWr, GPR32>;
+def : ShiftAlias<"rorv", RORVXr, GPR64>;
 
 // Multiply-add
 let AddedComplexity = 7 in {
@@ -847,26 +847,26 @@ defm CSINC : CondSelectOp<0, 0b01, "csinc", inc>;
 defm CSINV : CondSelectOp<1, 0b00, "csinv", not>;
 defm CSNEG : CondSelectOp<1, 0b01, "csneg", ineg>;
 
-def : Pat<(ARM64csinv GPR32:$tval, GPR32:$fval, (i32 imm:$cc), CPSR),
+def : Pat<(ARM64csinv GPR32:$tval, GPR32:$fval, (i32 imm:$cc), NZCV),
           (CSINVWr GPR32:$tval, GPR32:$fval, (i32 imm:$cc))>;
-def : Pat<(ARM64csinv GPR64:$tval, GPR64:$fval, (i32 imm:$cc), CPSR),
+def : Pat<(ARM64csinv GPR64:$tval, GPR64:$fval, (i32 imm:$cc), NZCV),
           (CSINVXr GPR64:$tval, GPR64:$fval, (i32 imm:$cc))>;
-def : Pat<(ARM64csneg GPR32:$tval, GPR32:$fval, (i32 imm:$cc), CPSR),
+def : Pat<(ARM64csneg GPR32:$tval, GPR32:$fval, (i32 imm:$cc), NZCV),
           (CSNEGWr GPR32:$tval, GPR32:$fval, (i32 imm:$cc))>;
-def : Pat<(ARM64csneg GPR64:$tval, GPR64:$fval, (i32 imm:$cc), CPSR),
+def : Pat<(ARM64csneg GPR64:$tval, GPR64:$fval, (i32 imm:$cc), NZCV),
           (CSNEGXr GPR64:$tval, GPR64:$fval, (i32 imm:$cc))>;
-def : Pat<(ARM64csinc GPR32:$tval, GPR32:$fval, (i32 imm:$cc), CPSR),
+def : Pat<(ARM64csinc GPR32:$tval, GPR32:$fval, (i32 imm:$cc), NZCV),
           (CSINCWr GPR32:$tval, GPR32:$fval, (i32 imm:$cc))>;
-def : Pat<(ARM64csinc GPR64:$tval, GPR64:$fval, (i32 imm:$cc), CPSR),
+def : Pat<(ARM64csinc GPR64:$tval, GPR64:$fval, (i32 imm:$cc), NZCV),
           (CSINCXr GPR64:$tval, GPR64:$fval, (i32 imm:$cc))>;
 
-def : Pat<(ARM64csel (i32 0), (i32 1), (i32 imm:$cc), CPSR),
+def : Pat<(ARM64csel (i32 0), (i32 1), (i32 imm:$cc), NZCV),
           (CSINCWr WZR, WZR, (i32 imm:$cc))>;
-def : Pat<(ARM64csel (i64 0), (i64 1), (i32 imm:$cc), CPSR),
+def : Pat<(ARM64csel (i64 0), (i64 1), (i32 imm:$cc), NZCV),
           (CSINCXr XZR, XZR, (i32 imm:$cc))>;
-def : Pat<(ARM64csel (i32 0), (i32 -1), (i32 imm:$cc), CPSR),
+def : Pat<(ARM64csel (i32 0), (i32 -1), (i32 imm:$cc), NZCV),
           (CSINVWr WZR, WZR, (i32 imm:$cc))>;
-def : Pat<(ARM64csel (i64 0), (i64 -1), (i32 imm:$cc), CPSR),
+def : Pat<(ARM64csel (i64 0), (i64 -1), (i32 imm:$cc), NZCV),
           (CSINVXr XZR, XZR, (i32 imm:$cc))>;
 
 // The inverse of the condition code from the alias instruction is what is used
@@ -2115,8 +2115,8 @@ def F128CSEL : Pseudo<(outs FPR128:$Rd),
                       (ins FPR128:$Rn, FPR128:$Rm, ccode:$cond),
                       [(set (f128 FPR128:$Rd),
                             (ARM64csel FPR128:$Rn, FPR128:$Rm,
-                                       (i32 imm:$cond), CPSR))]> {
-  let Uses = [CPSR];
+                                       (i32 imm:$cond), NZCV))]> {
+  let Uses = [NZCV];
   let usesCustomInserter = 1;
 }
 
diff --git a/lib/Target/ARM64/ARM64LoadStoreOptimizer.cpp b/lib/Target/ARM64/ARM64LoadStoreOptimizer.cpp
index 54a642917a..da7a8cd3d9 100644
--- a/lib/Target/ARM64/ARM64LoadStoreOptimizer.cpp
+++ b/lib/Target/ARM64/ARM64LoadStoreOptimizer.cpp
@@ -101,9 +101,9 @@ struct ARM64LoadStoreOpt : public MachineFunctionPass {
 
   bool optimizeBlock(MachineBasicBlock &MBB);
 
-  virtual bool runOnMachineFunction(MachineFunction &Fn);
+  bool runOnMachineFunction(MachineFunction &Fn) override;
 
-  virtual const char *getPassName() const {
+  const char *getPassName() const override {
     return "ARM64 load / store optimization pass";
   }
 
diff --git a/lib/Target/ARM64/ARM64PromoteConstant.cpp b/lib/Target/ARM64/ARM64PromoteConstant.cpp
index 2eef90d6cf..e61a62262d 100644
--- a/lib/Target/ARM64/ARM64PromoteConstant.cpp
+++ b/lib/Target/ARM64/ARM64PromoteConstant.cpp
@@ -87,11 +87,11 @@ public:
   static char ID;
   ARM64PromoteConstant() : ModulePass(ID) {}
 
-  virtual const char *getPassName() const { return "ARM64 Promote Constant"; }
+  const char *getPassName() const override { return "ARM64 Promote Constant"; }
 
   /// Iterate over the functions and promote the interesting constants into
   /// global variables with module scope.
-  bool runOnModule(Module &M) {
+  bool runOnModule(Module &M) override {
     DEBUG(dbgs() << getPassName() << '\n');
     bool Changed = false;
     for (auto &MF : M) {
@@ -107,7 +107,7 @@ private:
   bool runOnFunction(Function &F);
 
   // This transformation requires dominator info
-  virtual void getAnalysisUsage(AnalysisUsage &AU) const {
+  void getAnalysisUsage(AnalysisUsage &AU) const override {
     AU.setPreservesCFG();
     AU.addRequired<DominatorTreeWrapperPass>();
     AU.addPreserved<DominatorTreeWrapperPass>();
diff --git a/lib/Target/ARM64/ARM64RegisterInfo.cpp b/lib/Target/ARM64/ARM64RegisterInfo.cpp
index aa7d9b70b5..d3c647bd90 100644
--- a/lib/Target/ARM64/ARM64RegisterInfo.cpp
+++ b/lib/Target/ARM64/ARM64RegisterInfo.cpp
@@ -136,7 +136,7 @@ ARM64RegisterInfo::getPointerRegClass(const MachineFunction &MF,
 const TargetRegisterClass *
 ARM64RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
   if (RC == &ARM64::CCRRegClass)
-    return nullptr; // Can't copy CPSR.
+    return nullptr; // Can't copy NZCV.
   return RC;
 }
 
diff --git a/lib/Target/ARM64/ARM64RegisterInfo.h b/lib/Target/ARM64/ARM64RegisterInfo.h
index 5743e35cfe..7691fadbcc 100644
--- a/lib/Target/ARM64/ARM64RegisterInfo.h
+++ b/lib/Target/ARM64/ARM64RegisterInfo.h
@@ -40,7 +40,7 @@ public:
   getCalleeSavedRegs(const MachineFunction *MF = nullptr) const override;
   const uint32_t *getCallPreservedMask(CallingConv::ID) const override;
 
-  unsigned getCSRFirstUseCost() const {
+  unsigned getCSRFirstUseCost() const override {
     // The cost will be compared against BlockFrequency where entry has the
     // value of 1 << 14. A value of 5 will choose to spill or split really
     // cold path instead of using a callee-saved register.
diff --git a/lib/Target/ARM64/ARM64RegisterInfo.td b/lib/Target/ARM64/ARM64RegisterInfo.td
index 3a8e969a01..d6c5acb0b9 100644
--- a/lib/Target/ARM64/ARM64RegisterInfo.td
+++ b/lib/Target/ARM64/ARM64RegisterInfo.td
@@ -119,7 +119,7 @@ def XZR   : ARM64Reg<31, "xzr", [WZR]>, DwarfRegAlias<WSP>;
 }
 
 // Condition code register.
-def CPSR  : ARM64Reg<0, "cpsr">;
+def NZCV  : ARM64Reg<0, "nzcv">;
 
 // GPR register classes with the intersections of GPR32/GPR32sp and
 // GPR64/GPR64sp for use by the coalescer.
@@ -167,21 +167,21 @@ def tcGPR64 : RegisterClass<"ARM64", [i64], 64, (sub GPR64common, X19, X20, X21,
 // GPR register classes for post increment amount of vector load/store that
 // has alternate printing when Rm=31 and prints a constant immediate value
 // equal to the total number of bytes transferred.
-def GPR64pi1  : RegisterOperand<GPR64, "printPostIncOperand1">;
-def GPR64pi2  : RegisterOperand<GPR64, "printPostIncOperand2">;
-def GPR64pi3  : RegisterOperand<GPR64, "printPostIncOperand3">;
-def GPR64pi4  : RegisterOperand<GPR64, "printPostIncOperand4">;
-def GPR64pi6  : RegisterOperand<GPR64, "printPostIncOperand6">;
-def GPR64pi8  : RegisterOperand<GPR64, "printPostIncOperand8">;
-def GPR64pi12 : RegisterOperand<GPR64, "printPostIncOperand12">;
-def GPR64pi16 : RegisterOperand<GPR64, "printPostIncOperand16">;
-def GPR64pi24 : RegisterOperand<GPR64, "printPostIncOperand24">;
-def GPR64pi32 : RegisterOperand<GPR64, "printPostIncOperand32">;
-def GPR64pi48 : RegisterOperand<GPR64, "printPostIncOperand48">;
-def GPR64pi64 : RegisterOperand<GPR64, "printPostIncOperand64">;
+def GPR64pi1  : RegisterOperand<GPR64, "printPostIncOperand<1>">;
+def GPR64pi2  : RegisterOperand<GPR64, "printPostIncOperand<2>">;
+def GPR64pi3  : RegisterOperand<GPR64, "printPostIncOperand<3>">;
+def GPR64pi4  : RegisterOperand<GPR64, "printPostIncOperand<4>">;
+def GPR64pi6  : RegisterOperand<GPR64, "printPostIncOperand<6>">;
+def GPR64pi8  : RegisterOperand<GPR64, "printPostIncOperand<8>">;
+def GPR64pi12 : RegisterOperand<GPR64, "printPostIncOperand<12>">;
+def GPR64pi16 : RegisterOperand<GPR64, "printPostIncOperand<16>">;
+def GPR64pi24 : RegisterOperand<GPR64, "printPostIncOperand<24>">;
+def GPR64pi32 : RegisterOperand<GPR64, "printPostIncOperand<32>">;
+def GPR64pi48 : RegisterOperand<GPR64, "printPostIncOperand<48>">;
+def GPR64pi64 : RegisterOperand<GPR64, "printPostIncOperand<64>">;
 
 // Condition code regclass.
-def CCR : RegisterClass<"ARM64", [i32], 32, (add CPSR)> {
+def CCR : RegisterClass<"ARM64", [i32], 32, (add NZCV)> {
   let CopyCost = -1;  // Don't allow copying of status registers.
 
   // CCR is not allocatable.
diff --git a/lib/Target/ARM64/ARM64Subtarget.h b/lib/Target/ARM64/ARM64Subtarget.h
index 031068c4b8..88b9c2e7aa 100644
--- a/lib/Target/ARM64/ARM64Subtarget.h
+++ b/lib/Target/ARM64/ARM64Subtarget.h
@@ -100,7 +100,8 @@ public:
   const char *getBZeroEntry() const;
 
   void overrideSchedPolicy(MachineSchedPolicy &Policy, MachineInstr *begin,
-                           MachineInstr *end, unsigned NumRegionInstrs) const;
+                           MachineInstr *end,
+                           unsigned NumRegionInstrs) const override;
 };
 } // End llvm namespace
 
diff --git a/lib/Target/ARM64/ARM64TargetMachine.cpp b/lib/Target/ARM64/ARM64TargetMachine.cpp
index 7e3228f023..b7e1beb858 100644
--- a/lib/Target/ARM64/ARM64TargetMachine.cpp
+++ b/lib/Target/ARM64/ARM64TargetMachine.cpp
@@ -104,13 +104,13 @@ public:
     return getTM<ARM64TargetMachine>();
   }
 
-  virtual bool addPreISel();
-  virtual bool addInstSelector();
-  virtual bool addILPOpts();
-  virtual bool addPreRegAlloc();
-  virtual bool addPostRegAlloc();
-  virtual bool addPreSched2();
-  virtual bool addPreEmitPass();
+  bool addPreISel() override;
+  bool addInstSelector() override;
+  bool addILPOpts() override;
+  bool addPreRegAlloc() override;
+  bool addPostRegAlloc() override;
+  bool addPreSched2() override;
+  bool addPreEmitPass() override;
 };
 } // namespace
 
diff --git a/lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp b/lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp
index 71cf100daf..764999b4e7 100644
--- a/lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp
+++ b/lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp
@@ -77,7 +77,8 @@ private:
   bool validateInstruction(MCInst &Inst, SmallVectorImpl<SMLoc> &Loc);
   bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
                                OperandVector &Operands, MCStreamer &Out,
-                               unsigned &ErrorInfo, bool MatchingInlineAsm);
+                               unsigned &ErrorInfo,
+                               bool MatchingInlineAsm) override;
 /// @name Auto-generated Match Functions
 /// {
 
@@ -113,11 +114,12 @@ public:
     setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
   }
 
-  virtual bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
-                                SMLoc NameLoc, OperandVector &Operands);
-  virtual bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
-  virtual bool ParseDirective(AsmToken DirectiveID);
-  unsigned validateTargetOperandClass(MCParsedAsmOperand *Op, unsigned Kind);
+  bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
+                        SMLoc NameLoc, OperandVector &Operands) override;
+  bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
+  bool ParseDirective(AsmToken DirectiveID) override;
+  unsigned validateTargetOperandClass(MCParsedAsmOperand *Op,
+                                      unsigned Kind) override;
 
   static bool classifySymbolRef(const MCExpr *Expr,
                                 ARM64MCExpr::VariantKind &ELFRefKind,
@@ -293,9 +295,9 @@ public:
   }
 
   /// getStartLoc - Get the location of the first token of this operand.
-  SMLoc getStartLoc() const { return StartLoc; }
+  SMLoc getStartLoc() const override { return StartLoc; }
   /// getEndLoc - Get the location of the last token of this operand.
-  SMLoc getEndLoc() const { return EndLoc; }
+  SMLoc getEndLoc() const override { return EndLoc; }
   /// getOffsetLoc - Get the location of the offset of this memory operand.
   SMLoc getOffsetLoc() const { return OffsetLoc; }
 
@@ -324,7 +326,7 @@ public:
     return Barrier.Val;
   }
 
-  unsigned getReg() const {
+  unsigned getReg() const override {
     assert(Kind == k_Register && "Invalid access!");
     return Reg.RegNum;
   }
@@ -369,7 +371,7 @@ public:
     return Extend.Val;
   }
 
-  bool isImm() const { return Kind == k_Immediate; }
+  bool isImm() const override { return Kind == k_Immediate; }
   bool isSImm9() const {
     if (!isImm())
       return false;
@@ -678,7 +680,7 @@ public:
 
     return IsKnownRegister;
   }
-  bool isSystemCPSRField() const {
+  bool isSystemPStateField() const {
     if (!isSysReg()) return false;
 
     bool IsKnownRegister;
@@ -686,7 +688,7 @@ public:
 
     return IsKnownRegister;
   }
-  bool isReg() const { return Kind == k_Register && !Reg.isVector; }
+  bool isReg() const override { return Kind == k_Register && !Reg.isVector; }
   bool isVectorReg() const { return Kind == k_Register && Reg.isVector; }
   bool isVectorRegLo() const {
     return Kind == k_Register && Reg.isVector &&
@@ -723,11 +725,11 @@ public:
   bool isVectorIndexD() const {
     return Kind == k_VectorIndex && VectorIndex.Val < 2;
   }
-  bool isToken() const { return Kind == k_Token; }
+  bool isToken() const override { return Kind == k_Token; }
   bool isTokenEqual(StringRef Str) const {
     return Kind == k_Token && getToken() == Str;
   }
-  bool isMem() const { return Kind == k_Memory; }
+  bool isMem() const override { return Kind == k_Memory; }
   bool isSysCR() const { return Kind == k_SysCR; }
   bool isPrefetch() const { return Kind == k_Prefetch; }
   bool isShifter() const { return Kind == k_Shifter; }
@@ -1344,7 +1346,7 @@ public:
     Inst.addOperand(MCOperand::CreateImm(Bits));
   }
 
-  void addSystemCPSRFieldOperands(MCInst &Inst, unsigned N) const {
+  void addSystemPStateFieldOperands(MCInst &Inst, unsigned N) const {
     assert(N == 1 && "Invalid number of operands!");
 
     bool Valid;
@@ -1594,7 +1596,7 @@ public:
     addMemoryWritebackIndexedOperands(Inst, N, 16);
   }
 
-  virtual void print(raw_ostream &OS) const;
+  void print(raw_ostream &OS) const override;
 
   static ARM64Operand *CreateToken(StringRef Str, bool IsSuffix, SMLoc S,
                                    MCContext &Ctx) {
@@ -2219,10 +2221,10 @@ unsigned ARM64AsmParser::parseCondCodeString(StringRef Cond) {
   unsigned CC = StringSwitch<unsigned>(Cond.lower())
                     .Case("eq", ARM64CC::EQ)
                     .Case("ne", ARM64CC::NE)
-                    .Case("cs", ARM64CC::CS)
-                    .Case("hs", ARM64CC::CS)
-                    .Case("cc", ARM64CC::CC)
-                    .Case("lo", ARM64CC::CC)
+                    .Case("cs", ARM64CC::HS)
+                    .Case("hs", ARM64CC::HS)
+                    .Case("cc", ARM64CC::LO)
+                    .Case("lo", ARM64CC::LO)
                     .Case("mi", ARM64CC::MI)
                     .Case("pl", ARM64CC::PL)
                     .Case("vs", ARM64CC::VS)
@@ -2913,6 +2915,7 @@ bool ARM64AsmParser::parseMemory(OperandVector &Operands) {
 
       // Immediate expressions.
     } else if (Parser.getTok().is(AsmToken::Hash) ||
+               Parser.getTok().is(AsmToken::Colon) ||
                Parser.getTok().is(AsmToken::Integer)) {
       if (Parser.getTok().is(AsmToken::Hash))
         Parser.Lex(); // Eat hash token.
@@ -3014,6 +3017,7 @@ bool ARM64AsmParser::parseSymbolicImmVal(const MCExpr *&ImmVal) {
                   .Case("dtprel_g1_nc", ARM64MCExpr::VK_DTPREL_G1_NC)
                   .Case("dtprel_g0", ARM64MCExpr::VK_DTPREL_G0)
                   .Case("dtprel_g0_nc", ARM64MCExpr::VK_DTPREL_G0_NC)
+                  .Case("dtprel_hi12", ARM64MCExpr::VK_DTPREL_HI12)
                   .Case("dtprel_lo12", ARM64MCExpr::VK_DTPREL_LO12)
                   .Case("dtprel_lo12_nc", ARM64MCExpr::VK_DTPREL_LO12_NC)
                   .Case("tprel_g2", ARM64MCExpr::VK_TPREL_G2)
@@ -3021,6 +3025,7 @@ bool ARM64AsmParser::parseSymbolicImmVal(const MCExpr *&ImmVal) {
                   .Case("tprel_g1_nc", ARM64MCExpr::VK_TPREL_G1_NC)
                   .Case("tprel_g0", ARM64MCExpr::VK_TPREL_G0)
                   .Case("tprel_g0_nc", ARM64MCExpr::VK_TPREL_G0_NC)
+                  .Case("tprel_hi12", ARM64MCExpr::VK_TPREL_HI12)
                   .Case("tprel_lo12", ARM64MCExpr::VK_TPREL_LO12)
                   .Case("tprel_lo12_nc", ARM64MCExpr::VK_TPREL_LO12_NC)
                   .Case("tlsdesc_lo12", ARM64MCExpr::VK_TLSDESC_LO12)
@@ -3227,7 +3232,10 @@ bool ARM64AsmParser::parseOperand(OperandVector &Operands, bool isCondCode,
     if (Tok.is(AsmToken::Real)) {
       APFloat RealVal(APFloat::IEEEdouble, Tok.getString());
       uint64_t IntVal = RealVal.bitcastToAPInt().getZExtValue();
-      if (IntVal != 0 || (Mnemonic != "fcmp" && Mnemonic != "fcmpe"))
+      if (IntVal != 0 ||
+          (Mnemonic != "fcmp" && Mnemonic != "fcmpe" && Mnemonic != "fcmeq" &&
+           Mnemonic != "fcmge" && Mnemonic != "fcmgt" && Mnemonic != "fcmle" &&
+           Mnemonic != "fcmlt"))
         return TokError("unexpected floating point literal");
       Parser.Lex(); // Eat the token.
 
@@ -3254,6 +3262,27 @@ bool ARM64AsmParser::parseOperand(OperandVector &Operands, bool isCondCode,
 bool ARM64AsmParser::ParseInstruction(ParseInstructionInfo &Info,
                                       StringRef Name, SMLoc NameLoc,
                                       OperandVector &Operands) {
+  Name = StringSwitch<StringRef>(Name.lower())
+             .Case("beq", "b.eq")
+             .Case("bne", "b.ne")
+             .Case("bhs", "b.hs")
+             .Case("bcs", "b.cs")
+             .Case("blo", "b.lo")
+             .Case("bcc", "b.cc")
+             .Case("bmi", "b.mi")
+             .Case("bpl", "b.pl")
+             .Case("bvs", "b.vs")
+             .Case("bvc", "b.vc")
+             .Case("bhi", "b.hi")
+             .Case("bls", "b.ls")
+             .Case("bge", "b.ge")
+             .Case("blt", "b.lt")
+             .Case("bgt", "b.gt")
+             .Case("ble", "b.le")
+             .Case("bal", "b.al")
+             .Case("bnv", "b.nv")
+             .Default(Name);
+
   // Create the leading tokens for the mnemonic, split by '.' characters.
   size_t Start = 0, Next = Name.find('.');
   StringRef Head = Name.slice(Start, Next);
@@ -3495,7 +3524,9 @@ bool ARM64AsmParser::validateInstruction(MCInst &Inst,
     // and resolve the value and validate the result at fixup time, but
     // that's hard as we have long since lost any source information we
     // need to generate good diagnostics by that point.
-    if (Inst.getOpcode() == ARM64::ADDXri && Inst.getOperand(2).isExpr()) {
+    if ((Inst.getOpcode() == ARM64::ADDXri ||
+         Inst.getOpcode() == ARM64::ADDWri) &&
+        Inst.getOperand(2).isExpr()) {
       const MCExpr *Expr = Inst.getOperand(2).getExpr();
       ARM64MCExpr::VariantKind ELFRefKind;
       MCSymbolRefExpr::VariantKind DarwinRefKind;
@@ -3504,18 +3535,22 @@ bool ARM64AsmParser::validateInstruction(MCInst &Inst,
         return Error(Loc[2], "invalid immediate expression");
       }
 
-      if (DarwinRefKind == MCSymbolRefExpr::VK_PAGEOFF ||
-          DarwinRefKind == MCSymbolRefExpr::VK_TLVPPAGEOFF ||
-          ELFRefKind == ARM64MCExpr::VK_LO12 ||
+      // Note that we don't range-check the addend. It's adjusted modulo page
+      // size when converted, so there is no "out of range" condition when using
+      // @pageoff. Any validity checking for the value was done in the is*()
+      // predicate function.
+      if ((DarwinRefKind == MCSymbolRefExpr::VK_PAGEOFF ||
+           DarwinRefKind == MCSymbolRefExpr::VK_TLVPPAGEOFF) &&
+          Inst.getOpcode() == ARM64::ADDXri)
+        return false;
+      if (ELFRefKind == ARM64MCExpr::VK_LO12 ||
+          ELFRefKind == ARM64MCExpr::VK_DTPREL_HI12 ||
           ELFRefKind == ARM64MCExpr::VK_DTPREL_LO12 ||
           ELFRefKind == ARM64MCExpr::VK_DTPREL_LO12_NC ||
+          ELFRefKind == ARM64MCExpr::VK_TPREL_HI12 ||
           ELFRefKind == ARM64MCExpr::VK_TPREL_LO12 ||
           ELFRefKind == ARM64MCExpr::VK_TPREL_LO12_NC ||
           ELFRefKind == ARM64MCExpr::VK_TLSDESC_LO12) {
-        // Note that we don't range-check the addend. It's adjusted
-        // modulo page size when converted, so there is no "out of range"
-        // condition when using @pageoff. Any validity checking for the value
-        // was done in the is*() predicate function.
         return false;
       } else if (DarwinRefKind == MCSymbolRefExpr::VK_GOTPAGEOFF) {
         // @gotpageoff can only be used directly, not with an addend.
@@ -3830,6 +3865,10 @@ bool ARM64AsmParser::showMatchError(SMLoc Loc, unsigned ErrCode) {
     return Error(Loc, "immediate must be an integer in range [1,64].");
   case Match_InvalidLabel:
     return Error(Loc, "expected label or encodable integer pc offset");
+  case Match_MRS:
+    return Error(Loc, "expected readable system register");
+  case Match_MSR:
+    return Error(Loc, "expected writable system register or pstate");
   case Match_MnemonicFail:
     return Error(Loc, "unrecognized instruction mnemonic");
   default:
@@ -4172,9 +4211,8 @@ bool ARM64AsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
       delete Op;
     }
   }
-  // FIXME: Likewise for [su]xt[bh] with a Xd dst operand
-  else if (NumOperands == 3 &&
-           (Tok == "sxtb" || Tok == "uxtb" || Tok == "sxth" || Tok == "uxth")) {
+  // FIXME: Likewise for sxt[bh] with a Xd dst operand
+  else if (NumOperands == 3 && (Tok == "sxtb" || Tok == "sxth")) {
     ARM64Operand *Op = static_cast<ARM64Operand *>(Operands[1]);
     if (Op->isReg() &&
         ARM64MCRegisterClasses[ARM64::GPR64allRegClassID].contains(
@@ -4190,6 +4228,23 @@ bool ARM64AsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
       }
     }
   }
+  // FIXME: Likewise for uxt[bh] with a Xd dst operand
+  else if (NumOperands == 3 && (Tok == "uxtb" || Tok == "uxth")) {
+    ARM64Operand *Op = static_cast<ARM64Operand *>(Operands[1]);
+    if (Op->isReg() &&
+        ARM64MCRegisterClasses[ARM64::GPR64allRegClassID].contains(
+            Op->getReg())) {
+      // The source register can be Wn here, but the matcher expects a
+      // GPR32. Twiddle it here if necessary.
+      ARM64Operand *Op = static_cast<ARM64Operand *>(Operands[1]);
+      if (Op->isReg()) {
+        unsigned Reg = getWRegFromXReg(Op->getReg());
+        Operands[1] = ARM64Operand::CreateReg(Reg, false, Op->getStartLoc(),
+                                              Op->getEndLoc(), getContext());
+        delete Op;
+      }
+    }
+  }
 
   // Yet another horrible hack to handle FMOV Rd, #0.0 using [WX]ZR.
   if (NumOperands == 3 && Tok == "fmov") {
@@ -4351,7 +4406,9 @@ bool ARM64AsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
   case Match_InvalidImm1_16:
   case Match_InvalidImm1_32:
   case Match_InvalidImm1_64:
-  case Match_InvalidLabel: {
+  case Match_InvalidLabel:
+  case Match_MSR:
+  case Match_MRS: {
     // Any time we get here, there's nothing fancy to do. Just get the
     // operand SMLoc and display the diagnostic.
     SMLoc ErrorLoc = ((ARM64Operand *)Operands[ErrorInfo])->getStartLoc();
diff --git a/lib/Target/ARM64/Disassembler/ARM64Disassembler.cpp b/lib/Target/ARM64/Disassembler/ARM64Disassembler.cpp
index 2ada4a4cf9..0fc559c5cf 100644
--- a/lib/Target/ARM64/Disassembler/ARM64Disassembler.cpp
+++ b/lib/Target/ARM64/Disassembler/ARM64Disassembler.cpp
@@ -137,9 +137,10 @@ static DecodeStatus DecodeBaseAddSubImm(llvm::MCInst &Inst, uint32_t insn,
 static DecodeStatus DecodeUnconditionalBranch(llvm::MCInst &Inst, uint32_t insn,
                                               uint64_t Address,
                                               const void *Decoder);
-static DecodeStatus DecodeSystemCPSRInstruction(llvm::MCInst &Inst,
-                                                uint32_t insn, uint64_t Address,
-                                                const void *Decoder);
+static DecodeStatus DecodeSystemPStateInstruction(llvm::MCInst &Inst,
+                                                  uint32_t insn,
+                                                  uint64_t Address,
+                                                  const void *Decoder);
 static DecodeStatus DecodeTestAndBranch(llvm::MCInst &Inst, uint32_t insn,
                                         uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeSIMDLdStPost(llvm::MCInst &Inst, uint32_t insn,
@@ -1408,20 +1409,20 @@ static DecodeStatus DecodeUnconditionalBranch(llvm::MCInst &Inst, uint32_t insn,
   return Success;
 }
 
-static DecodeStatus DecodeSystemCPSRInstruction(llvm::MCInst &Inst,
-                                                uint32_t insn, uint64_t Addr,
-                                                const void *Decoder) {
+static DecodeStatus DecodeSystemPStateInstruction(llvm::MCInst &Inst,
+                                                  uint32_t insn, uint64_t Addr,
+                                                  const void *Decoder) {
   uint64_t op1 = fieldFromInstruction(insn, 16, 3);
   uint64_t op2 = fieldFromInstruction(insn, 5, 3);
   uint64_t crm = fieldFromInstruction(insn, 8, 4);
 
-  uint64_t cpsr_field = (op1 << 3) | op2;
+  uint64_t pstate_field = (op1 << 3) | op2;
 
-  Inst.addOperand(MCOperand::CreateImm(cpsr_field));
+  Inst.addOperand(MCOperand::CreateImm(pstate_field));
   Inst.addOperand(MCOperand::CreateImm(crm));
 
   bool ValidNamed;
-  (void)ARM64PState::PStateMapper().toString(cpsr_field, ValidNamed);
+  (void)ARM64PState::PStateMapper().toString(pstate_field, ValidNamed);
   
   return ValidNamed ? Success : Fail;
 }
diff --git a/lib/Target/ARM64/Disassembler/ARM64Disassembler.h b/lib/Target/ARM64/Disassembler/ARM64Disassembler.h
index f60a9f07f2..8989925f36 100644
--- a/lib/Target/ARM64/Disassembler/ARM64Disassembler.h
+++ b/lib/Target/ARM64/Disassembler/ARM64Disassembler.h
@@ -29,11 +29,10 @@ public:
   ~ARM64Disassembler() {}
 
   /// getInstruction - See MCDisassembler.
-  MCDisassembler::DecodeStatus getInstruction(MCInst &instr, uint64_t &size,
-                                              const MemoryObject &region,
-                                              uint64_t address,
-                                              raw_ostream &vStream,
-                                              raw_ostream &cStream) const;
+  MCDisassembler::DecodeStatus
+  getInstruction(MCInst &instr, uint64_t &size, const MemoryObject &region,
+                 uint64_t address, raw_ostream &vStream,
+                 raw_ostream &cStream) const override;
 };
 
 } // namespace llvm
diff --git a/lib/Target/ARM64/InstPrinter/ARM64InstPrinter.cpp b/lib/Target/ARM64/InstPrinter/ARM64InstPrinter.cpp
index a07b7be00d..65d5eae2d2 100644
--- a/lib/Target/ARM64/InstPrinter/ARM64InstPrinter.cpp
+++ b/lib/Target/ARM64/InstPrinter/ARM64InstPrinter.cpp
@@ -1008,6 +1008,12 @@ void ARM64InstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
   }
 }
 
+void ARM64InstPrinter::printHexImm(const MCInst *MI, unsigned OpNo,
+                                   raw_ostream &O) {
+  const MCOperand &Op = MI->getOperand(OpNo);
+  O << format("#%#llx", Op.getImm());
+}
+
 void ARM64InstPrinter::printPostIncOperand(const MCInst *MI, unsigned OpNo,
                                            unsigned Imm, raw_ostream &O) {
   const MCOperand &Op = MI->getOperand(OpNo);
@@ -1021,66 +1027,6 @@ void ARM64InstPrinter::printPostIncOperand(const MCInst *MI, unsigned OpNo,
     assert(0 && "unknown operand kind in printPostIncOperand64");
 }
 
-void ARM64InstPrinter::printPostIncOperand1(const MCInst *MI, unsigned OpNo,
-                                            raw_ostream &O) {
-  printPostIncOperand(MI, OpNo, 1, O);
-}
-
-void ARM64InstPrinter::printPostIncOperand2(const MCInst *MI, unsigned OpNo,
-                                            raw_ostream &O) {
-  printPostIncOperand(MI, OpNo, 2, O);
-}
-
-void ARM64InstPrinter::printPostIncOperand3(const MCInst *MI, unsigned OpNo,
-                                            raw_ostream &O) {
-  printPostIncOperand(MI, OpNo, 3, O);
-}
-
-void ARM64InstPrinter::printPostIncOperand4(const MCInst *MI, unsigned OpNo,
-                                            raw_ostream &O) {
-  printPostIncOperand(MI, OpNo, 4, O);
-}
-
-void ARM64InstPrinter::printPostIncOperand6(const MCInst *MI, unsigned OpNo,
-                                            raw_ostream &O) {
-  printPostIncOperand(MI, OpNo, 6, O);
-}
-
-void ARM64InstPrinter::printPostIncOperand8(const MCInst *MI, unsigned OpNo,
-                                            raw_ostream &O) {
-  printPostIncOperand(MI, OpNo, 8, O);
-}
-
-void ARM64InstPrinter::printPostIncOperand12(const MCInst *MI, unsigned OpNo,
-                                             raw_ostream &O) {
-  printPostIncOperand(MI, OpNo, 12, O);
-}
-
-void ARM64InstPrinter::printPostIncOperand16(const MCInst *MI, unsigned OpNo,
-                                             raw_ostream &O) {
-  printPostIncOperand(MI, OpNo, 16, O);
-}
-
-void ARM64InstPrinter::printPostIncOperand24(const MCInst *MI, unsigned OpNo,
-                                             raw_ostream &O) {
-  printPostIncOperand(MI, OpNo, 24, O);
-}
-
-void ARM64InstPrinter::printPostIncOperand32(const MCInst *MI, unsigned OpNo,
-                                             raw_ostream &O) {
-  printPostIncOperand(MI, OpNo, 32, O);
-}
-
-void ARM64InstPrinter::printPostIncOperand48(const MCInst *MI, unsigned OpNo,
-                                             raw_ostream &O) {
-  printPostIncOperand(MI, OpNo, 48, O);
-}
-
-void ARM64InstPrinter::printPostIncOperand64(const MCInst *MI, unsigned OpNo,
-                                             raw_ostream &O) {
-  printPostIncOperand(MI, OpNo, 64, O);
-}
-
 void ARM64InstPrinter::printVRegOperand(const MCInst *MI, unsigned OpNo,
                                         raw_ostream &O) {
   const MCOperand &Op = MI->getOperand(OpNo);
@@ -1104,10 +1050,12 @@ void ARM64InstPrinter::printAddSubImm(const MCInst *MI, unsigned OpNum,
     assert(Val == MO.getImm() && "Add/sub immediate out of range!");
     unsigned Shift =
         ARM64_AM::getShiftValue(MI->getOperand(OpNum + 1).getImm());
-    O << '#' << (Val << Shift);
-    // Distinguish "0, lsl #12" from "0, lsl #0".
-    if (Val == 0 && Shift != 0)
+    O << '#' << Val;
+    if (Shift != 0)
       printShifter(MI, OpNum + 1, O);
+
+    if (CommentStream)
+      *CommentStream << "=#" << (Val << Shift) << '\n';
   } else {
     assert(MO.isExpr() && "Unexpected operand type!");
     O << *MO.getExpr();
@@ -1195,19 +1143,10 @@ void ARM64InstPrinter::printAMNoIndex(const MCInst *MI, unsigned OpNum,
   O << '[' << getRegisterName(MI->getOperand(OpNum).getReg()) << ']';
 }
 
-void ARM64InstPrinter::printImmScale4(const MCInst *MI, unsigned OpNum,
-                                      raw_ostream &O) {
-  O << '#' << 4 * MI->getOperand(OpNum).getImm();
-}
-
-void ARM64InstPrinter::printImmScale8(const MCInst *MI, unsigned OpNum,
-                                      raw_ostream &O) {
-  O << '#' << 8 * MI->getOperand(OpNum).getImm();
-}
-
-void ARM64InstPrinter::printImmScale16(const MCInst *MI, unsigned OpNum,
-                                       raw_ostream &O) {
-  O << '#' << 16 * MI->getOperand(OpNum).getImm();
+template<int Scale>
+void ARM64InstPrinter::printImmScale(const MCInst *MI, unsigned OpNum,
+                                     raw_ostream &O) {
+  O << '#' << Scale * MI->getOperand(OpNum).getImm();
 }
 
 void ARM64InstPrinter::printAMIndexed(const MCInst *MI, unsigned OpNum,
@@ -1248,35 +1187,14 @@ void ARM64InstPrinter::printPrefetchOp(const MCInst *MI, unsigned OpNum,
     O << '#' << prfop;
 }
 
-void ARM64InstPrinter::printMemoryPostIndexed32(const MCInst *MI,
-                                                unsigned OpNum,
-                                                raw_ostream &O) {
-  O << '[' << getRegisterName(MI->getOperand(OpNum).getReg()) << ']' << ", #"
-    << 4 * MI->getOperand(OpNum + 1).getImm();
-}
-
-void ARM64InstPrinter::printMemoryPostIndexed64(const MCInst *MI,
-                                                unsigned OpNum,
-                                                raw_ostream &O) {
-  O << '[' << getRegisterName(MI->getOperand(OpNum).getReg()) << ']' << ", #"
-    << 8 * MI->getOperand(OpNum + 1).getImm();
-}
-
-void ARM64InstPrinter::printMemoryPostIndexed128(const MCInst *MI,
-                                                 unsigned OpNum,
-                                                 raw_ostream &O) {
-  O << '[' << getRegisterName(MI->getOperand(OpNum).getReg()) << ']' << ", #"
-    << 16 * MI->getOperand(OpNum + 1).getImm();
-}
-
 void ARM64InstPrinter::printMemoryPostIndexed(const MCInst *MI, unsigned OpNum,
-                                              raw_ostream &O) {
+                                              raw_ostream &O, unsigned Scale) {
   O << '[' << getRegisterName(MI->getOperand(OpNum).getReg()) << ']' << ", #"
-    << MI->getOperand(OpNum + 1).getImm();
+    << Scale * MI->getOperand(OpNum + 1).getImm();
 }
 
 void ARM64InstPrinter::printMemoryRegOffset(const MCInst *MI, unsigned OpNum,
-                                            raw_ostream &O, int LegalShiftAmt) {
+                                            raw_ostream &O, int Scale) {
   unsigned Val = MI->getOperand(OpNum + 2).getImm();
   ARM64_AM::ExtendType ExtType = ARM64_AM::getMemExtendType(Val);
 
@@ -1295,45 +1213,18 @@ void ARM64InstPrinter::printMemoryRegOffset(const MCInst *MI, unsigned OpNum,
     O << ", " << ARM64_AM::getExtendName(ExtType);
 
   if (DoShift)
-    O << " #" << LegalShiftAmt;
+    O << " #" << Log2_32(Scale);
 
   O << "]";
 }
 
-void ARM64InstPrinter::printMemoryRegOffset8(const MCInst *MI, unsigned OpNum,
-                                             raw_ostream &O) {
-  printMemoryRegOffset(MI, OpNum, O, 0);
-}
-
-void ARM64InstPrinter::printMemoryRegOffset16(const MCInst *MI, unsigned OpNum,
-                                              raw_ostream &O) {
-  printMemoryRegOffset(MI, OpNum, O, 1);
-}
-
-void ARM64InstPrinter::printMemoryRegOffset32(const MCInst *MI, unsigned OpNum,
-                                              raw_ostream &O) {
-  printMemoryRegOffset(MI, OpNum, O, 2);
-}
-
-void ARM64InstPrinter::printMemoryRegOffset64(const MCInst *MI, unsigned OpNum,
-                                              raw_ostream &O) {
-  printMemoryRegOffset(MI, OpNum, O, 3);
-}
-
-void ARM64InstPrinter::printMemoryRegOffset128(const MCInst *MI, unsigned OpNum,
-                                               raw_ostream &O) {
-  printMemoryRegOffset(MI, OpNum, O, 4);
-}
-
 void ARM64InstPrinter::printFPImmOperand(const MCInst *MI, unsigned OpNum,
                                          raw_ostream &O) {
   const MCOperand &MO = MI->getOperand(OpNum);
-  O << '#';
-  if (MO.isFPImm())
-    // FIXME: Should this ever happen?
-    O << MO.getFPImm();
-  else
-    O << ARM64_AM::getFPImmFloat(MO.getImm());
+  float FPImm = MO.isFPImm() ? MO.getFPImm() : ARM64_AM::getFPImmFloat(MO.getImm());
+
+  // 8 decimal places are enough to perfectly represent permitted floats.
+  O << format("#%.8f", FPImm);
 }
 
 static unsigned getNextVectorRegister(unsigned Reg, unsigned Stride = 1) {
@@ -1525,8 +1416,8 @@ void ARM64InstPrinter::printMSRSystemRegister(const MCInst *MI, unsigned OpNo,
     O << StringRef(Name).upper();
 }
 
-void ARM64InstPrinter::printSystemCPSRField(const MCInst *MI, unsigned OpNo,
-                                            raw_ostream &O) {
+void ARM64InstPrinter::printSystemPStateField(const MCInst *MI, unsigned OpNo,
+                                              raw_ostream &O) {
   unsigned Val = MI->getOperand(OpNo).getImm();
 
   bool Valid;
diff --git a/lib/Target/ARM64/InstPrinter/ARM64InstPrinter.h b/lib/Target/ARM64/InstPrinter/ARM64InstPrinter.h
index 7f2a9fe12a..b3e693f68f 100644
--- a/lib/Target/ARM64/InstPrinter/ARM64InstPrinter.h
+++ b/lib/Target/ARM64/InstPrinter/ARM64InstPrinter.h
@@ -28,8 +28,8 @@ public:
   ARM64InstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII,
                    const MCRegisterInfo &MRI, const MCSubtargetInfo &STI);
 
-  virtual void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot);
-  virtual void printRegName(raw_ostream &OS, unsigned RegNo) const;
+  void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot) override;
+  void printRegName(raw_ostream &OS, unsigned RegNo) const override;
 
   // Autogenerated by tblgen.
   virtual void printInstruction(const MCInst *MI, raw_ostream &O);
@@ -44,20 +44,14 @@ protected:
   bool printSysAlias(const MCInst *MI, raw_ostream &O);
   // Operand printers
   void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
+  void printHexImm(const MCInst *MI, unsigned OpNo, raw_ostream &O);
   void printPostIncOperand(const MCInst *MI, unsigned OpNo, unsigned Imm,
                            raw_ostream &O);
-  void printPostIncOperand1(const MCInst *MI, unsigned OpNo, raw_ostream &O);
-  void printPostIncOperand2(const MCInst *MI, unsigned OpNo, raw_ostream &O);
-  void printPostIncOperand3(const MCInst *MI, unsigned OpNo, raw_ostream &O);
-  void printPostIncOperand4(const MCInst *MI, unsigned OpNo, raw_ostream &O);
-  void printPostIncOperand6(const MCInst *MI, unsigned OpNo, raw_ostream &O);
-  void printPostIncOperand8(const MCInst *MI, unsigned OpNo, raw_ostream &O);
-  void printPostIncOperand12(const MCInst *MI, unsigned OpNo, raw_ostream &O);
-  void printPostIncOperand16(const MCInst *MI, unsigned OpNo, raw_ostream &O);
-  void printPostIncOperand24(const MCInst *MI, unsigned OpNo, raw_ostream &O);
-  void printPostIncOperand32(const MCInst *MI, unsigned OpNo, raw_ostream &O);
-  void printPostIncOperand48(const MCInst *MI, unsigned OpNo, raw_ostream &O);
-  void printPostIncOperand64(const MCInst *MI, unsigned OpNo, raw_ostream &O);
+  template<int Amount>
+  void printPostIncOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
+    printPostIncOperand(MI, OpNo, Amount, O);
+  }
+
   void printVRegOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
   void printSysCROperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
   void printAddSubImm(const MCInst *MI, unsigned OpNum, raw_ostream &O);
@@ -74,66 +68,38 @@ protected:
                       raw_ostream &O);
   void printAMIndexedWB(const MCInst *MI, unsigned OpNum, unsigned Scale,
                         raw_ostream &O);
-  void printAMIndexed128(const MCInst *MI, unsigned OpNum, raw_ostream &O) {
-    printAMIndexed(MI, OpNum, 16, O);
-  }
-  void printAMIndexed128WB(const MCInst *MI, unsigned OpNum, raw_ostream &O) {
-    printAMIndexedWB(MI, OpNum, 16, O);
-  }
 
-  void printAMIndexed64(const MCInst *MI, unsigned OpNum, raw_ostream &O) {
-    printAMIndexed(MI, OpNum, 8, O);
-  }
-  void printAMIndexed64WB(const MCInst *MI, unsigned OpNum, raw_ostream &O) {
-    printAMIndexedWB(MI, OpNum, 8, O);
+  template<int BitWidth>
+  void printAMIndexed(const MCInst *MI, unsigned OpNum, raw_ostream &O) {
+    printAMIndexed(MI, OpNum, BitWidth / 8, O);
   }
 
-  void printAMIndexed32(const MCInst *MI, unsigned OpNum, raw_ostream &O) {
-    printAMIndexed(MI, OpNum, 4, O);
-  }
-  void printAMIndexed32WB(const MCInst *MI, unsigned OpNum, raw_ostream &O) {
-    printAMIndexedWB(MI, OpNum, 4, O);
+  template<int BitWidth>
+  void printAMIndexedWB(const MCInst *MI, unsigned OpNum, raw_ostream &O) {
+    printAMIndexedWB(MI, OpNum, BitWidth / 8, O);
   }
 
-  void printAMIndexed16(const MCInst *MI, unsigned OpNum, raw_ostream &O) {
-    printAMIndexed(MI, OpNum, 2, O);
-  }
-  void printAMIndexed16WB(const MCInst *MI, unsigned OpNum, raw_ostream &O) {
-    printAMIndexedWB(MI, OpNum, 2, O);
-  }
-
-  void printAMIndexed8(const MCInst *MI, unsigned OpNum, raw_ostream &O) {
-    printAMIndexed(MI, OpNum, 1, O);
-  }
-  void printAMIndexed8WB(const MCInst *MI, unsigned OpNum, raw_ostream &O) {
-    printAMIndexedWB(MI, OpNum, 1, O);
-  }
-  void printAMUnscaled(const MCInst *MI, unsigned OpNum, raw_ostream &O) {
-    printAMIndexed(MI, OpNum, 1, O);
-  }
-  void printAMUnscaledWB(const MCInst *MI, unsigned OpNum, raw_ostream &O) {
-    printAMIndexedWB(MI, OpNum, 1, O);
-  }
   void printAMNoIndex(const MCInst *MI, unsigned OpNum, raw_ostream &O);
-  void printImmScale4(const MCInst *MI, unsigned OpNum, raw_ostream &O);
-  void printImmScale8(const MCInst *MI, unsigned OpNum, raw_ostream &O);
-  void printImmScale16(const MCInst *MI, unsigned OpNum, raw_ostream &O);
+
+  template<int Scale>
+  void printImmScale(const MCInst *MI, unsigned OpNum, raw_ostream &O);
+
   void printPrefetchOp(const MCInst *MI, unsigned OpNum, raw_ostream &O);
-  void printMemoryPostIndexed(const MCInst *MI, unsigned OpNum, raw_ostream &O);
-  void printMemoryPostIndexed32(const MCInst *MI, unsigned OpNum,
-                                raw_ostream &O);
-  void printMemoryPostIndexed64(const MCInst *MI, unsigned OpNum,
-                                raw_ostream &O);
-  void printMemoryPostIndexed128(const MCInst *MI, unsigned OpNum,
-                                 raw_ostream &O);
+
+  void printMemoryPostIndexed(const MCInst *MI, unsigned OpNum, raw_ostream &O,
+                              unsigned Scale);
+  template<int BitWidth>
+  void printMemoryPostIndexed(const MCInst *MI, unsigned OpNum,
+                              raw_ostream &O) {
+    printMemoryPostIndexed(MI, OpNum, O, BitWidth / 8);
+  }
+
   void printMemoryRegOffset(const MCInst *MI, unsigned OpNum, raw_ostream &O,
                             int LegalShiftAmt);
-  void printMemoryRegOffset8(const MCInst *MI, unsigned OpNum, raw_ostream &O);
-  void printMemoryRegOffset16(const MCInst *MI, unsigned OpNum, raw_ostream &O);
-  void printMemoryRegOffset32(const MCInst *MI, unsigned OpNum, raw_ostream &O);
-  void printMemoryRegOffset64(const MCInst *MI, unsigned OpNum, raw_ostream &O);
-  void printMemoryRegOffset128(const MCInst *MI, unsigned OpNum,
-                               raw_ostream &O);
+  template<int BitWidth>
+  void printMemoryRegOffset(const MCInst *MI, unsigned OpNum, raw_ostream &O) {
+    printMemoryRegOffset(MI, OpNum, O, BitWidth / 8);
+  }
 
   void printFPImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
 
@@ -153,7 +119,7 @@ protected:
   void printBarrierOption(const MCInst *MI, unsigned OpNum, raw_ostream &O);
   void printMSRSystemRegister(const MCInst *MI, unsigned OpNum, raw_ostream &O);
   void printMRSSystemRegister(const MCInst *MI, unsigned OpNum, raw_ostream &O);
-  void printSystemCPSRField(const MCInst *MI, unsigned OpNum, raw_ostream &O);
+  void printSystemPStateField(const MCInst *MI, unsigned OpNum, raw_ostream &O);
   void printSIMDType10Operand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
 };
 
@@ -162,11 +128,11 @@ public:
   ARM64AppleInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII,
                         const MCRegisterInfo &MRI, const MCSubtargetInfo &STI);
 
-  virtual void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot);
+  void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot) override;
 
-  virtual void printInstruction(const MCInst *MI, raw_ostream &O);
-  virtual bool printAliasInstr(const MCInst *MI, raw_ostream &O);
-  virtual StringRef getRegName(unsigned RegNo) const {
+  void printInstruction(const MCInst *MI, raw_ostream &O) override;
+  bool printAliasInstr(const MCInst *MI, raw_ostream &O) override;
+  StringRef getRegName(unsigned RegNo) const override {
     return getRegisterName(RegNo);
   }
   static const char *getRegisterName(unsigned RegNo,
diff --git a/lib/Target/ARM64/MCTargetDesc/ARM64AsmBackend.cpp b/lib/Target/ARM64/MCTargetDesc/ARM64AsmBackend.cpp
index c9b95a2c16..73a2afdb47 100644
--- a/lib/Target/ARM64/MCTargetDesc/ARM64AsmBackend.cpp
+++ b/lib/Target/ARM64/MCTargetDesc/ARM64AsmBackend.cpp
@@ -29,9 +29,11 @@ class ARM64AsmBackend : public MCAsmBackend {
 public:
   ARM64AsmBackend(const Target &T) : MCAsmBackend() {}
 
-  unsigned getNumFixupKinds() const { return ARM64::NumTargetFixupKinds; }
+  unsigned getNumFixupKinds() const override {
+    return ARM64::NumTargetFixupKinds;
+  }
 
-  const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const {
+  const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override {
     const static MCFixupKindInfo Infos[ARM64::NumTargetFixupKinds] = {
       // This table *must* be in the order that the fixup_* kinds are defined in
       // ARM64FixupKinds.h.
@@ -63,14 +65,14 @@ public:
   }
 
   void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
-                  uint64_t Value, bool IsPCRel) const;
+                  uint64_t Value, bool IsPCRel) const override;
 
-  bool mayNeedRelaxation(const MCInst &Inst) const;
+  bool mayNeedRelaxation(const MCInst &Inst) const override;
   bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value,
                             const MCRelaxableFragment *DF,
-                            const MCAsmLayout &Layout) const;
-  void relaxInstruction(const MCInst &Inst, MCInst &Res) const;
-  bool writeNopData(uint64_t Count, MCObjectWriter *OW) const;
+                            const MCAsmLayout &Layout) const override;
+  void relaxInstruction(const MCInst &Inst, MCInst &Res) const override;
+  bool writeNopData(uint64_t Count, MCObjectWriter *OW) const override;
 
   void HandleAssemblerFlag(MCAssemblerFlag Flag) {}
 
@@ -306,12 +308,12 @@ public:
   DarwinARM64AsmBackend(const Target &T, const MCRegisterInfo &MRI)
       : ARM64AsmBackend(T), MRI(MRI) {}
 
-  MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
+  MCObjectWriter *createObjectWriter(raw_ostream &OS) const override {
     return createARM64MachObjectWriter(OS, MachO::CPU_TYPE_ARM64,
                                        MachO::CPU_SUBTYPE_ARM64_ALL);
   }
 
-  virtual bool doesSectionRequireSymbols(const MCSection &Section) const {
+  bool doesSectionRequireSymbols(const MCSection &Section) const override {
     // Any section for which the linker breaks things into atoms needs to
     // preserve symbols, including assembler local symbols, to identify
     // those atoms. These sections are:
@@ -348,9 +350,8 @@ public:
   }
 
   /// \brief Generate the compact unwind encoding from the CFI directives.
-  virtual uint32_t
-  generateCompactUnwindEncoding(ArrayRef<MCCFIInstruction> Instrs) const
-      override {
+  uint32_t generateCompactUnwindEncoding(
+                             ArrayRef<MCCFIInstruction> Instrs) const override {
     if (Instrs.empty())
       return CU::UNWIND_ARM64_MODE_FRAMELESS;
 
@@ -491,7 +492,7 @@ public:
   ELFARM64AsmBackend(const Target &T, uint8_t OSABI, bool IsLittleEndian)
     : ARM64AsmBackend(T), OSABI(OSABI), IsLittleEndian(IsLittleEndian) {}
 
-  MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
+  MCObjectWriter *createObjectWriter(raw_ostream &OS) const override {
     return createARM64ELFObjectWriter(OS, OSABI, IsLittleEndian);
   }
 
diff --git a/lib/Target/ARM64/MCTargetDesc/ARM64ELFObjectWriter.cpp b/lib/Target/ARM64/MCTargetDesc/ARM64ELFObjectWriter.cpp
index b775dd332f..0990a701bc 100644
--- a/lib/Target/ARM64/MCTargetDesc/ARM64ELFObjectWriter.cpp
+++ b/lib/Target/ARM64/MCTargetDesc/ARM64ELFObjectWriter.cpp
@@ -103,15 +103,19 @@ unsigned ARM64ELFObjectWriter::GetRelocType(const MCValue &Target,
     case FK_Data_8:
       return ELF::R_AARCH64_ABS64;
     case ARM64::fixup_arm64_add_imm12:
-      if (SymLoc == ARM64MCExpr::VK_DTPREL && IsNC)
+      if (RefKind == ARM64MCExpr::VK_DTPREL_HI12)
+        return ELF::R_AARCH64_TLSLD_ADD_DTPREL_HI12;
+      if (RefKind == ARM64MCExpr::VK_TPREL_HI12)
+        return ELF::R_AARCH64_TLSLE_ADD_TPREL_HI12;
+      if (RefKind == ARM64MCExpr::VK_DTPREL_LO12_NC)
         return ELF::R_AARCH64_TLSLD_ADD_DTPREL_LO12_NC;
-      if (SymLoc == ARM64MCExpr::VK_DTPREL && !IsNC)
+      if (RefKind == ARM64MCExpr::VK_DTPREL_LO12)
         return ELF::R_AARCH64_TLSLD_ADD_DTPREL_LO12;
-      if (SymLoc == ARM64MCExpr::VK_TPREL && IsNC)
+      if (RefKind == ARM64MCExpr::VK_TPREL_LO12_NC)
         return ELF::R_AARCH64_TLSLE_ADD_TPREL_LO12_NC;
-      if (SymLoc == ARM64MCExpr::VK_TPREL && !IsNC)
+      if (RefKind == ARM64MCExpr::VK_TPREL_LO12)
         return ELF::R_AARCH64_TLSLE_ADD_TPREL_LO12;
-      if (SymLoc == ARM64MCExpr::VK_TLSDESC && IsNC)
+      if (RefKind == ARM64MCExpr::VK_TLSDESC_LO12)
         return ELF::R_AARCH64_TLSDESC_ADD_LO12_NC;
       if (SymLoc == ARM64MCExpr::VK_ABS && IsNC)
         return ELF::R_AARCH64_ADD_ABS_LO12_NC;
diff --git a/lib/Target/ARM64/MCTargetDesc/ARM64ELFStreamer.cpp b/lib/Target/ARM64/MCTargetDesc/ARM64ELFStreamer.cpp
index 9af21d8cee..adbf830797 100644
--- a/lib/Target/ARM64/MCTargetDesc/ARM64ELFStreamer.cpp
+++ b/lib/Target/ARM64/MCTargetDesc/ARM64ELFStreamer.cpp
@@ -62,8 +62,8 @@ public:
 
   ~ARM64ELFStreamer() {}
 
-  virtual void ChangeSection(const MCSection *Section,
-                             const MCExpr *Subsection) {
+  void ChangeSection(const MCSection *Section,
+                     const MCExpr *Subsection) override {
     // We have to keep track of the mapping symbol state of any sections we
     // use. Each one should start off as EMS_None, which is provided as the
     // default constructor by DenseMap::lookup.
@@ -76,7 +76,8 @@ public:
   /// This function is the one used to emit instruction data into the ELF
   /// streamer. We override it to add the appropriate mapping symbol if
   /// necessary.
-  virtual void EmitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI) {
+  void EmitInstruction(const MCInst &Inst,
+                       const MCSubtargetInfo &STI) override {
     EmitA64MappingSymbol();
     MCELFStreamer::EmitInstruction(Inst, STI);
   }
@@ -84,7 +85,7 @@ public:
   /// This is one of the functions used to emit data into an ELF section, so the
   /// ARM64 streamer overrides it to add the appropriate mapping symbol ($d)
   /// if necessary.
-  virtual void EmitBytes(StringRef Data) {
+  void EmitBytes(StringRef Data) override {
     EmitDataMappingSymbol();
     MCELFStreamer::EmitBytes(Data);
   }
@@ -92,8 +93,8 @@ public:
   /// This is one of the functions used to emit data into an ELF section, so the
   /// ARM64 streamer overrides it to add the appropriate mapping symbol ($d)
   /// if necessary.
-  virtual void EmitValueImpl(const MCExpr *Value, unsigned Size,
-                             const SMLoc &Loc) {
+  void EmitValueImpl(const MCExpr *Value, unsigned Size,
+                     const SMLoc &Loc) override {
     EmitDataMappingSymbol();
     MCELFStreamer::EmitValueImpl(Value, Size);
   }
diff --git a/lib/Target/ARM64/MCTargetDesc/ARM64MCAsmInfo.cpp b/lib/Target/ARM64/MCTargetDesc/ARM64MCAsmInfo.cpp
index 137fa880ef..e211d3428b 100644
--- a/lib/Target/ARM64/MCTargetDesc/ARM64MCAsmInfo.cpp
+++ b/lib/Target/ARM64/MCTargetDesc/ARM64MCAsmInfo.cpp
@@ -66,7 +66,7 @@ const MCExpr *ARM64MCAsmInfoDarwin::getExprForPersonalitySymbol(
 
 ARM64MCAsmInfoELF::ARM64MCAsmInfoELF(StringRef TT) {
   Triple T(TT);
-  if (T.getArch() == Triple::aarch64_be)
+  if (T.getArch() == Triple::arm64_be)
     IsLittleEndian = false;
 
   // We prefer NEON instructions to be printed in the short form.
diff --git a/lib/Target/ARM64/MCTargetDesc/ARM64MCAsmInfo.h b/lib/Target/ARM64/MCTargetDesc/ARM64MCAsmInfo.h
index 2885a66de2..324bc39560 100644
--- a/lib/Target/ARM64/MCTargetDesc/ARM64MCAsmInfo.h
+++ b/lib/Target/ARM64/MCTargetDesc/ARM64MCAsmInfo.h
@@ -22,9 +22,9 @@ class StringRef;
 class MCStreamer;
 struct ARM64MCAsmInfoDarwin : public MCAsmInfoDarwin {
   explicit ARM64MCAsmInfoDarwin();
-  virtual const MCExpr *getExprForPersonalitySymbol(const MCSymbol *Sym,
-                                                    unsigned Encoding,
-                                                    MCStreamer &Streamer) const;
+  const MCExpr *
+  getExprForPersonalitySymbol(const MCSymbol *Sym, unsigned Encoding,
+                              MCStreamer &Streamer) const override;
 };
 
 struct ARM64MCAsmInfoELF : public MCAsmInfo {
diff --git a/lib/Target/ARM64/MCTargetDesc/ARM64MCCodeEmitter.cpp b/lib/Target/ARM64/MCTargetDesc/ARM64MCCodeEmitter.cpp
index 8910337d0d..3c6dbc85b1 100644
--- a/lib/Target/ARM64/MCTargetDesc/ARM64MCCodeEmitter.cpp
+++ b/lib/Target/ARM64/MCTargetDesc/ARM64MCCodeEmitter.cpp
@@ -182,7 +182,7 @@ public:
 
   void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
                          SmallVectorImpl<MCFixup> &Fixups,
-                         const MCSubtargetInfo &STI) const;
+                         const MCSubtargetInfo &STI) const override;
 
   unsigned fixMulHigh(const MCInst &MI, unsigned EncodedValue,
                       const MCSubtargetInfo &STI) const;
@@ -288,7 +288,6 @@ ARM64MCCodeEmitter::getAddSubImmOpValue(const MCInst &MI, unsigned OpIdx,
     return MO.getImm() | (ShiftVal == 0 ? 0 : (1 << 12));
   assert(MO.isExpr() && "Unable to encode MCOperand!");
   const MCExpr *Expr = MO.getExpr();
-  assert(ShiftVal == 0 && "shift not allowed on add/sub immediate with fixup");
 
   // Encode the 12 bits of the fixup.
   MCFixupKind Kind = MCFixupKind(ARM64::fixup_arm64_add_imm12);
diff --git a/lib/Target/ARM64/MCTargetDesc/ARM64MCExpr.cpp b/lib/Target/ARM64/MCTargetDesc/ARM64MCExpr.cpp
index c772002846..efa820b097 100644
--- a/lib/Target/ARM64/MCTargetDesc/ARM64MCExpr.cpp
+++ b/lib/Target/ARM64/MCTargetDesc/ARM64MCExpr.cpp
@@ -49,6 +49,7 @@ StringRef ARM64MCExpr::getVariantKindName() const {
   case VK_DTPREL_G1_NC:        return ":dtprel_g1_nc:";
   case VK_DTPREL_G0:           return ":dtprel_g0:";
   case VK_DTPREL_G0_NC:        return ":dtprel_g0_nc:";
+  case VK_DTPREL_HI12:         return ":dtprel_hi12:";
   case VK_DTPREL_LO12:         return ":dtprel_lo12:";
   case VK_DTPREL_LO12_NC:      return ":dtprel_lo12_nc:";
   case VK_TPREL_G2:            return ":tprel_g2:";
@@ -56,6 +57,7 @@ StringRef ARM64MCExpr::getVariantKindName() const {
   case VK_TPREL_G1_NC:         return ":tprel_g1_nc:";
   case VK_TPREL_G0:            return ":tprel_g0:";
   case VK_TPREL_G0_NC:         return ":tprel_g0_nc:";
+  case VK_TPREL_HI12:          return ":tprel_hi12:";
   case VK_TPREL_LO12:          return ":tprel_lo12:";
   case VK_TPREL_LO12_NC:       return ":tprel_lo12_nc:";
   case VK_TLSDESC_LO12:        return ":tlsdesc_lo12:";
diff --git a/lib/Target/ARM64/MCTargetDesc/ARM64MCExpr.h b/lib/Target/ARM64/MCTargetDesc/ARM64MCExpr.h
index cbff6e814d..d832546517 100644
--- a/lib/Target/ARM64/MCTargetDesc/ARM64MCExpr.h
+++ b/lib/Target/ARM64/MCTargetDesc/ARM64MCExpr.h
@@ -42,10 +42,11 @@ public:
     // MOVZ/MOVK.
     VK_PAGE     = 0x010,
     VK_PAGEOFF  = 0x020,
-    VK_G0       = 0x030,
-    VK_G1       = 0x040,
-    VK_G2       = 0x050,
-    VK_G3       = 0x060,
+    VK_HI12     = 0x030,
+    VK_G0       = 0x040,
+    VK_G1       = 0x050,
+    VK_G2       = 0x060,
+    VK_G3       = 0x070,
     VK_AddressFragBits = 0x0f0,
 
     // Whether the final relocation is a checked one (where a linker should
@@ -79,6 +80,7 @@ public:
     VK_DTPREL_G1_NC      = VK_DTPREL   | VK_G1      | VK_NC,
     VK_DTPREL_G0         = VK_DTPREL   | VK_G0,
     VK_DTPREL_G0_NC      = VK_DTPREL   | VK_G0      | VK_NC,
+    VK_DTPREL_HI12       = VK_DTPREL   | VK_HI12,
     VK_DTPREL_LO12       = VK_DTPREL   | VK_PAGEOFF,
     VK_DTPREL_LO12_NC    = VK_DTPREL   | VK_PAGEOFF | VK_NC,
     VK_GOTTPREL_PAGE     = VK_GOTTPREL | VK_PAGE,
@@ -90,6 +92,7 @@ public:
     VK_TPREL_G1_NC       = VK_TPREL    | VK_G1      | VK_NC,
     VK_TPREL_G0          = VK_TPREL    | VK_G0,
     VK_TPREL_G0_NC       = VK_TPREL    | VK_G0      | VK_NC,
+    VK_TPREL_HI12        = VK_TPREL    | VK_HI12,
     VK_TPREL_LO12        = VK_TPREL    | VK_PAGEOFF,
     VK_TPREL_LO12_NC     = VK_TPREL    | VK_PAGEOFF | VK_NC,
     VK_TLSDESC_LO12      = VK_TLSDESC  | VK_PAGEOFF | VK_NC,
@@ -142,16 +145,16 @@ public:
   /// (e.g. ":got:", ":lo12:").
   StringRef getVariantKindName() const;
 
-  void PrintImpl(raw_ostream &OS) const;
+  void PrintImpl(raw_ostream &OS) const override;
 
-  void AddValueSymbols(MCAssembler *) const;
+  void AddValueSymbols(MCAssembler *) const override;
 
-  const MCSection *FindAssociatedSection() const;
+  const MCSection *FindAssociatedSection() const override;
 
   bool EvaluateAsRelocatableImpl(MCValue &Res,
-                                 const MCAsmLayout *Layout) const;
+                                 const MCAsmLayout *Layout) const override;
 
-  void fixELFSymbolsInTLSFixups(MCAssembler &Asm) const;
+  void fixELFSymbolsInTLSFixups(MCAssembler &Asm) const override;
 
   static bool classof(const MCExpr *E) {
     return E->getKind() == MCExpr::Target;
diff --git a/lib/Target/ARM64/MCTargetDesc/ARM64MachObjectWriter.cpp b/lib/Target/ARM64/MCTargetDesc/ARM64MachObjectWriter.cpp
index ba725069a3..1c48159bbe 100644
--- a/lib/Target/ARM64/MCTargetDesc/ARM64MachObjectWriter.cpp
+++ b/lib/Target/ARM64/MCTargetDesc/ARM64MachObjectWriter.cpp
@@ -36,7 +36,7 @@ public:
   void RecordRelocation(MachObjectWriter *Writer, const MCAssembler &Asm,
                         const MCAsmLayout &Layout, const MCFragment *Fragment,
                         const MCFixup &Fixup, MCValue Target,
-                        uint64_t &FixedValue);
+                        uint64_t &FixedValue) override;
 };
 }
 
diff --git a/lib/Target/ARM64/Utils/ARM64BaseInfo.h b/lib/Target/ARM64/Utils/ARM64BaseInfo.h
index 66c2052e62..ef4caefab9 100644
--- a/lib/Target/ARM64/Utils/ARM64BaseInfo.h
+++ b/lib/Target/ARM64/Utils/ARM64BaseInfo.h
@@ -192,8 +192,8 @@ namespace ARM64CC {
 enum CondCode {  // Meaning (integer)          Meaning (floating-point)
   EQ = 0x0,      // Equal                      Equal
   NE = 0x1,      // Not equal                  Not equal, or unordered
-  CS = 0x2,      // Carry set                  >, ==, or unordered
-  CC = 0x3,      // Carry clear                Less than
+  HS = 0x2,      // Unsigned higher or same    >, ==, or unordered
+  LO = 0x3,      // Unsigned lower             Less than
   MI = 0x4,      // Minus, negative            Less than
   PL = 0x5,      // Plus, positive or zero     >, ==, or unordered
   VS = 0x6,      // Overflow                   Unordered
@@ -215,8 +215,8 @@ inline static const char *getCondCodeName(CondCode Code) {
   default: llvm_unreachable("Unknown condition code");
   case EQ:  return "eq";
   case NE:  return "ne";
-  case CS:  return "cs";
-  case CC:  return "cc";
+  case HS:  return "hs";
+  case LO:  return "lo";
   case MI:  return "mi";
   case PL:  return "pl";
   case VS:  return "vs";
@@ -237,8 +237,8 @@ inline static CondCode getInvertedCondCode(CondCode Code) {
   default: llvm_unreachable("Unknown condition code");
   case EQ:  return NE;
   case NE:  return EQ;
-  case CS:  return CC;
-  case CC:  return CS;
+  case HS:  return LO;
+  case LO:  return HS;
   case MI:  return PL;
   case PL:  return MI;
   case VS:  return VC;
@@ -263,8 +263,8 @@ inline static unsigned getNZCVToSatisfyCondCode(CondCode Code) {
   default: llvm_unreachable("Unknown condition code");
   case EQ: return Z; // Z == 1
   case NE: return 0; // Z == 0
-  case CS: return C; // C == 1
-  case CC: return 0; // C == 0
+  case HS: return C; // C == 1
+  case LO: return 0; // C == 0
   case MI: return N; // N == 1
   case PL: return 0; // N == 0
   case VS: return V; // V == 1
diff --git a/lib/Target/CppBackend/CPPBackend.cpp b/lib/Target/CppBackend/CPPBackend.cpp
index f16547a44e..fbb34ed50d 100644
--- a/lib/Target/CppBackend/CPPBackend.cpp
+++ b/lib/Target/CppBackend/CPPBackend.cpp
@@ -108,9 +108,9 @@ namespace {
     explicit CppWriter(formatted_raw_ostream &o) :
       ModulePass(ID), Out(o), uniqueNum(0), is_inline(false), indent_level(0){}
 
-    virtual const char *getPassName() const { return "C++ backend"; }
+    const char *getPassName() const override { return "C++ backend"; }
 
-    bool runOnModule(Module &M);
+    bool runOnModule(Module &M) override;
 
     void printProgram(const std::string& fname, const std::string& modName );
     void printModule(const std::string& fname, const std::string& modName );
diff --git a/lib/Target/CppBackend/CPPTargetMachine.h b/lib/Target/CppBackend/CPPTargetMachine.h
index ee39f2a7cd..673ade78a9 100644
--- a/lib/Target/CppBackend/CPPTargetMachine.h
+++ b/lib/Target/CppBackend/CPPTargetMachine.h
@@ -28,14 +28,12 @@ struct CPPTargetMachine : public TargetMachine {
                    CodeGenOpt::Level OL)
     : TargetMachine(T, TT, CPU, FS, Options) {}
 
-  virtual bool addPassesToEmitFile(PassManagerBase &PM,
-                                   formatted_raw_ostream &Out,
-                                   CodeGenFileType FileType,
-                                   bool DisableVerify,
-                                   AnalysisID StartAfter,
-                                   AnalysisID StopAfter);
-
-  virtual const DataLayout *getDataLayout() const { return nullptr; }
+  bool addPassesToEmitFile(PassManagerBase &PM, formatted_raw_ostream &Out,
+                           CodeGenFileType FileType, bool DisableVerify,
+                           AnalysisID StartAfter,
+                           AnalysisID StopAfter) override;
+
+  const DataLayout *getDataLayout() const override { return nullptr; }
 };
 
 extern Target TheCppBackendTarget;
diff --git a/lib/Target/Hexagon/HexagonAsmPrinter.h b/lib/Target/Hexagon/HexagonAsmPrinter.h
index a186dc9c73..7fe8c5790c 100644
--- a/lib/Target/Hexagon/HexagonAsmPrinter.h
+++ b/lib/Target/Hexagon/HexagonAsmPrinter.h
@@ -30,21 +30,22 @@ namespace llvm {
       Subtarget = &TM.getSubtarget<HexagonSubtarget>();
     }
 
-    virtual const char *getPassName() const {
+    const char *getPassName() const override {
       return "Hexagon Assembly Printer";
     }
 
-    bool isBlockOnlyReachableByFallthrough(const MachineBasicBlock *MBB) const;
+    bool isBlockOnlyReachableByFallthrough(
+                                   const MachineBasicBlock *MBB) const override;
 
-    virtual void EmitInstruction(const MachineInstr *MI);
+    void EmitInstruction(const MachineInstr *MI) override;
 
     void printOperand(const MachineInstr *MI, unsigned OpNo, raw_ostream &O);
     bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
                          unsigned AsmVariant, const char *ExtraCode,
-                         raw_ostream &OS);
+                         raw_ostream &OS) override;
     bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo,
                                unsigned AsmVariant, const char *ExtraCode,
-                               raw_ostream &OS);
+                               raw_ostream &OS) override;
 
     static const char *getRegisterName(unsigned RegNo);
   };
diff --git a/lib/Target/Hexagon/HexagonCFGOptimizer.cpp b/lib/Target/Hexagon/HexagonCFGOptimizer.cpp
index a6f807fda8..de340e0074 100644
--- a/lib/Target/Hexagon/HexagonCFGOptimizer.cpp
+++ b/lib/Target/Hexagon/HexagonCFGOptimizer.cpp
@@ -49,10 +49,10 @@ private:
     initializeHexagonCFGOptimizerPass(*PassRegistry::getPassRegistry());
   }
 
-  const char *getPassName() const {
+  const char *getPassName() const override {
     return "Hexagon CFG Optimizer";
   }
-  bool runOnMachineFunction(MachineFunction &Fn);
+  bool runOnMachineFunction(MachineFunction &Fn) override;
 };
 
 
diff --git a/lib/Target/Hexagon/HexagonCopyToCombine.cpp b/lib/Target/Hexagon/HexagonCopyToCombine.cpp
index 23de1bf77d..aeff680e6a 100644
--- a/lib/Target/Hexagon/HexagonCopyToCombine.cpp
+++ b/lib/Target/Hexagon/HexagonCopyToCombine.cpp
@@ -68,15 +68,15 @@ public:
     initializeHexagonCopyToCombinePass(*PassRegistry::getPassRegistry());
   }
 
-  virtual void getAnalysisUsage(AnalysisUsage &AU) const {
+  void getAnalysisUsage(AnalysisUsage &AU) const override {
     MachineFunctionPass::getAnalysisUsage(AU);
   }
 
-  const char *getPassName() const {
+  const char *getPassName() const override {
     return "Hexagon Copy-To-Combine Pass";
   }
 
-  virtual bool runOnMachineFunction(MachineFunction &Fn);
+  bool runOnMachineFunction(MachineFunction &Fn) override;
 
 private:
   MachineInstr *findPairable(MachineInstr *I1, bool &DoInsertAtI1);
diff --git a/lib/Target/Hexagon/HexagonExpandPredSpillCode.cpp b/lib/Target/Hexagon/HexagonExpandPredSpillCode.cpp
index e4590bbd4e..3dafe80ffc 100644
--- a/lib/Target/Hexagon/HexagonExpandPredSpillCode.cpp
+++ b/lib/Target/Hexagon/HexagonExpandPredSpillCode.cpp
@@ -60,10 +60,10 @@ class HexagonExpandPredSpillCode : public MachineFunctionPass {
       initializeHexagonExpandPredSpillCodePass(Registry);
     }
 
-    const char *getPassName() const {
+    const char *getPassName() const override {
       return "Hexagon Expand Predicate Spill Code";
     }
-    bool runOnMachineFunction(MachineFunction &Fn);
+    bool runOnMachineFunction(MachineFunction &Fn) override;
 };
 
 
diff --git a/lib/Target/Hexagon/HexagonFixupHwLoops.cpp b/lib/Target/Hexagon/HexagonFixupHwLoops.cpp
index a79264bb58..d41939a57a 100644
--- a/lib/Target/Hexagon/HexagonFixupHwLoops.cpp
+++ b/lib/Target/Hexagon/HexagonFixupHwLoops.cpp
@@ -40,11 +40,13 @@ namespace {
       initializeHexagonFixupHwLoopsPass(*PassRegistry::getPassRegistry());
     }
 
-    virtual bool runOnMachineFunction(MachineFunction &MF);
+    bool runOnMachineFunction(MachineFunction &MF) override;
 
-    const char *getPassName() const { return "Hexagon Hardware Loop Fixup"; }
+    const char *getPassName() const override {
+      return "Hexagon Hardware Loop Fixup";
+    }
 
-    virtual void getAnalysisUsage(AnalysisUsage &AU) const {
+    void getAnalysisUsage(AnalysisUsage &AU) const override {
       AU.setPreservesCFG();
       MachineFunctionPass::getAnalysisUsage(AU);
     }
diff --git a/lib/Target/Hexagon/HexagonFrameLowering.h b/lib/Target/Hexagon/HexagonFrameLowering.h
index a62c76aaf6..446af161aa 100644
--- a/lib/Target/Hexagon/HexagonFrameLowering.h
+++ b/lib/Target/Hexagon/HexagonFrameLowering.h
@@ -28,25 +28,25 @@ public:
 
   /// emitProlog/emitEpilog - These methods insert prolog and epilog code into
   /// the function.
-  void emitPrologue(MachineFunction &MF) const;
-  void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
-  virtual bool
-  spillCalleeSavedRegisters(MachineBasicBlock &MBB,
-                            MachineBasicBlock::iterator MI,
-                            const std::vector<CalleeSavedInfo> &CSI,
-                            const TargetRegisterInfo *TRI) const;
-
-  void eliminateCallFramePseudoInstr(MachineFunction &MF,
-                                     MachineBasicBlock &MBB,
-                                     MachineBasicBlock::iterator I) const;
-
-  virtual bool
+  void emitPrologue(MachineFunction &MF) const override;
+  void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override;
+  bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
+                                 MachineBasicBlock::iterator MI,
+                                 const std::vector<CalleeSavedInfo> &CSI,
+                                 const TargetRegisterInfo *TRI) const override;
+
+  void
+  eliminateCallFramePseudoInstr(MachineFunction &MF,
+                                MachineBasicBlock &MBB,
+                                MachineBasicBlock::iterator I) const override;
+
+  bool
   restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
                               MachineBasicBlock::iterator MI,
                               const std::vector<CalleeSavedInfo> &CSI,
-                              const TargetRegisterInfo *TRI) const;
-  int getFrameIndexOffset(const MachineFunction &MF, int FI) const;
-  bool hasFP(const MachineFunction &MF) const;
+                              const TargetRegisterInfo *TRI) const override;
+  int getFrameIndexOffset(const MachineFunction &MF, int FI) const override;
+  bool hasFP(const MachineFunction &MF) const override;
   bool hasTailCall(MachineBasicBlock &MBB) const;
 };
 
diff --git a/lib/Target/Hexagon/HexagonHardwareLoops.cpp b/lib/Target/Hexagon/HexagonHardwareLoops.cpp
index db83b1ab39..7f76421ac3 100644
--- a/lib/Target/Hexagon/HexagonHardwareLoops.cpp
+++ b/lib/Target/Hexagon/HexagonHardwareLoops.cpp
@@ -78,11 +78,11 @@ namespace {
       initializeHexagonHardwareLoopsPass(*PassRegistry::getPassRegistry());
     }
 
-    virtual bool runOnMachineFunction(MachineFunction &MF);
+    bool runOnMachineFunction(MachineFunction &MF) override;
 
-    const char *getPassName() const { return "Hexagon Hardware Loops"; }
+    const char *getPassName() const override { return "Hexagon Hardware Loops"; }
 
-    virtual void getAnalysisUsage(AnalysisUsage &AU) const {
+    void getAnalysisUsage(AnalysisUsage &AU) const override {
       AU.addRequired<MachineDominatorTree>();
       AU.addRequired<MachineLoopInfo>();
       MachineFunctionPass::getAnalysisUsage(AU);
diff --git a/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp b/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
index 687f097351..dabe650a5b 100644
--- a/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
+++ b/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
@@ -62,7 +62,7 @@ public:
   }
   bool hasNumUsesBelowThresGA(SDNode *N) const;
 
-  SDNode *Select(SDNode *N);
+  SDNode *Select(SDNode *N) override;
 
   // Complex Pattern Selectors.
   inline bool foldGlobalAddress(SDValue &N, SDValue &R);
@@ -79,15 +79,15 @@ public:
   bool SelectADDRriU6_1(SDValue& N, SDValue &R1, SDValue &R2);
   bool SelectADDRriU6_2(SDValue& N, SDValue &R1, SDValue &R2);
 
-  virtual const char *getPassName() const {
+  const char *getPassName() const override {
     return "Hexagon DAG->DAG Pattern Instruction Selection";
   }
 
   /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
   /// inline asm expressions.
-  virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
-                                            char ConstraintCode,
-                                            std::vector<SDValue> &OutOps);
+  bool SelectInlineAsmMemoryOperand(const SDValue &Op,
+                                    char ConstraintCode,
+                                    std::vector<SDValue> &OutOps) override;
   bool SelectAddr(SDNode *Op, SDValue Addr, SDValue &Base, SDValue &Offset);
 
   SDNode *SelectLoad(SDNode *N);
diff --git a/lib/Target/Hexagon/HexagonISelLowering.h b/lib/Target/Hexagon/HexagonISelLowering.h
index 73da226a17..4f27c27656 100644
--- a/lib/Target/Hexagon/HexagonISelLowering.h
+++ b/lib/Target/Hexagon/HexagonISelLowering.h
@@ -92,14 +92,14 @@ namespace llvm {
                                       const SmallVectorImpl<ISD::InputArg> &Ins,
                                       SelectionDAG& DAG) const;
 
-    virtual bool isTruncateFree(Type *Ty1, Type *Ty2) const;
-    virtual bool isTruncateFree(EVT VT1, EVT VT2) const;
+    bool isTruncateFree(Type *Ty1, Type *Ty2) const override;
+    bool isTruncateFree(EVT VT1, EVT VT2) const override;
 
-    virtual bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const;
+    bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override;
 
-    virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
+    SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
 
-    virtual const char *getTargetNodeName(unsigned Opcode) const;
+    const char *getTargetNodeName(unsigned Opcode) const override;
     SDValue  LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerINLINEASM(SDValue Op, SelectionDAG &DAG) const;
@@ -109,12 +109,12 @@ namespace llvm {
                                  CallingConv::ID CallConv, bool isVarArg,
                                  const SmallVectorImpl<ISD::InputArg> &Ins,
                                  SDLoc dl, SelectionDAG &DAG,
-                                 SmallVectorImpl<SDValue> &InVals) const;
+                                 SmallVectorImpl<SDValue> &InVals) const override;
     SDValue LowerGLOBALADDRESS(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
 
     SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI,
-                      SmallVectorImpl<SDValue> &InVals) const;
+                      SmallVectorImpl<SDValue> &InVals) const override;
 
     SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
                             CallingConv::ID CallConv, bool isVarArg,
@@ -133,46 +133,45 @@ namespace llvm {
                         CallingConv::ID CallConv, bool isVarArg,
                         const SmallVectorImpl<ISD::OutputArg> &Outs,
                         const SmallVectorImpl<SDValue> &OutVals,
-                        SDLoc dl, SelectionDAG &DAG) const;
+                        SDLoc dl, SelectionDAG &DAG) const override;
 
-    virtual MachineBasicBlock
-    *EmitInstrWithCustomInserter(MachineInstr *MI,
-                                 MachineBasicBlock *BB) const;
+    MachineBasicBlock *
+    EmitInstrWithCustomInserter(MachineInstr *MI,
+                                MachineBasicBlock *BB) const override;
 
     SDValue  LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
     SDValue  LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
-    virtual EVT getSetCCResultType(LLVMContext &C, EVT VT) const {
+    EVT getSetCCResultType(LLVMContext &C, EVT VT) const override {
       if (!VT.isVector())
         return MVT::i1;
       else
         return EVT::getVectorVT(C, MVT::i1, VT.getVectorNumElements());
     }
 
-    virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
-                                            SDValue &Base, SDValue &Offset,
-                                            ISD::MemIndexedMode &AM,
-                                            SelectionDAG &DAG) const;
+    bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
+                                    SDValue &Base, SDValue &Offset,
+                                    ISD::MemIndexedMode &AM,
+                                    SelectionDAG &DAG) const override;
 
     std::pair<unsigned, const TargetRegisterClass*>
     getRegForInlineAsmConstraint(const std::string &Constraint,
-                                 MVT VT) const;
+                                 MVT VT) const override;
 
     // Intrinsics
-    virtual SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op,
-                                            SelectionDAG &DAG) const;
+    SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
     /// isLegalAddressingMode - Return true if the addressing mode represented
     /// by AM is legal for this target, for a load/store of the specified type.
     /// The type may be VoidTy, in which case only return true if the addressing
     /// mode is legal for a load/store of any legal type.
     /// TODO: Handle pre/postinc as well.
-    virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const;
-    virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
+    bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const override;
+    bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
 
     /// isLegalICmpImmediate - Return true if the specified immediate is legal
     /// icmp immediate, that is the target has icmp instructions which can
     /// compare a register against the immediate without having to materialize
     /// the immediate into a register.
-    virtual bool isLegalICmpImmediate(int64_t Imm) const;
+    bool isLegalICmpImmediate(int64_t Imm) const override;
   };
 } // end namespace llvm
 
diff --git a/lib/Target/Hexagon/HexagonInstrInfo.h b/lib/Target/Hexagon/HexagonInstrInfo.h
index 2a715b2d37..6b032c95e7 100644
--- a/lib/Target/Hexagon/HexagonInstrInfo.h
+++ b/lib/Target/Hexagon/HexagonInstrInfo.h
@@ -40,124 +40,121 @@ public:
   /// such, whenever a client has an instance of instruction info, it should
   /// always be able to get register info as well (through this method).
   ///
-  virtual const HexagonRegisterInfo &getRegisterInfo() const { return RI; }
+  const HexagonRegisterInfo &getRegisterInfo() const { return RI; }
 
   /// isLoadFromStackSlot - If the specified machine instruction is a direct
   /// load from a stack slot, return the virtual or physical register number of
   /// the destination along with the FrameIndex of the loaded stack slot.  If
   /// not, return 0.  This predicate must return 0 if the instruction has
   /// any side effects other than loading from the stack slot.
-  virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
-                                       int &FrameIndex) const;
+  unsigned isLoadFromStackSlot(const MachineInstr *MI,
+                               int &FrameIndex) const override;
 
   /// isStoreToStackSlot - If the specified machine instruction is a direct
   /// store to a stack slot, return the virtual or physical register number of
   /// the source reg along with the FrameIndex of the loaded stack slot.  If
   /// not, return 0.  This predicate must return 0 if the instruction has
   /// any side effects other than storing to the stack slot.
-  virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
-                                      int &FrameIndex) const;
-
-
-  virtual bool AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
-                                 MachineBasicBlock *&FBB,
-                                 SmallVectorImpl<MachineOperand> &Cond,
-                                 bool AllowModify) const;
-
-  virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
-
-  virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
-                                MachineBasicBlock *FBB,
-                                const SmallVectorImpl<MachineOperand> &Cond,
-                                DebugLoc DL) const;
-
-  virtual bool analyzeCompare(const MachineInstr *MI,
-                              unsigned &SrcReg, unsigned &SrcReg2,
-                              int &Mask, int &Value) const;
-
-  virtual void copyPhysReg(MachineBasicBlock &MBB,
-                           MachineBasicBlock::iterator I, DebugLoc DL,
-                           unsigned DestReg, unsigned SrcReg,
-                           bool KillSrc) const;
-
-  virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
-                                   MachineBasicBlock::iterator MBBI,
-                                   unsigned SrcReg, bool isKill, int FrameIndex,
-                                   const TargetRegisterClass *RC,
-                                   const TargetRegisterInfo *TRI) const;
-
-  virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
-                              SmallVectorImpl<MachineOperand> &Addr,
-                              const TargetRegisterClass *RC,
-                              SmallVectorImpl<MachineInstr*> &NewMIs) const;
-
-  virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
-                                    MachineBasicBlock::iterator MBBI,
-                                    unsigned DestReg, int FrameIndex,
-                                    const TargetRegisterClass *RC,
-                                    const TargetRegisterInfo *TRI) const;
-
-  virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
-                               SmallVectorImpl<MachineOperand> &Addr,
-                               const TargetRegisterClass *RC,
-                               SmallVectorImpl<MachineInstr*> &NewMIs) const;
-
-  virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
-                                              MachineInstr* MI,
-                                           const SmallVectorImpl<unsigned> &Ops,
-                                              int FrameIndex) const;
-
-  virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
-                                              MachineInstr* MI,
-                                           const SmallVectorImpl<unsigned> &Ops,
-                                              MachineInstr* LoadMI) const {
+  unsigned isStoreToStackSlot(const MachineInstr *MI,
+                              int &FrameIndex) const override;
+
+
+  bool AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
+                         MachineBasicBlock *&FBB,
+                         SmallVectorImpl<MachineOperand> &Cond,
+                         bool AllowModify) const override;
+
+  unsigned RemoveBranch(MachineBasicBlock &MBB) const override;
+
+  unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
+                        MachineBasicBlock *FBB,
+                        const SmallVectorImpl<MachineOperand> &Cond,
+                        DebugLoc DL) const override;
+
+  bool analyzeCompare(const MachineInstr *MI,
+                      unsigned &SrcReg, unsigned &SrcReg2,
+                      int &Mask, int &Value) const override;
+
+  void copyPhysReg(MachineBasicBlock &MBB,
+                   MachineBasicBlock::iterator I, DebugLoc DL,
+                   unsigned DestReg, unsigned SrcReg,
+                   bool KillSrc) const override;
+
+  void storeRegToStackSlot(MachineBasicBlock &MBB,
+                           MachineBasicBlock::iterator MBBI,
+                           unsigned SrcReg, bool isKill, int FrameIndex,
+                           const TargetRegisterClass *RC,
+                           const TargetRegisterInfo *TRI) const override;
+
+  void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
+                      SmallVectorImpl<MachineOperand> &Addr,
+                      const TargetRegisterClass *RC,
+                      SmallVectorImpl<MachineInstr*> &NewMIs) const;
+
+  void loadRegFromStackSlot(MachineBasicBlock &MBB,
+                            MachineBasicBlock::iterator MBBI,
+                            unsigned DestReg, int FrameIndex,
+                            const TargetRegisterClass *RC,
+                            const TargetRegisterInfo *TRI) const override;
+
+  void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
+                       SmallVectorImpl<MachineOperand> &Addr,
+                       const TargetRegisterClass *RC,
+                       SmallVectorImpl<MachineInstr*> &NewMIs) const;
+
+  MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
+                                      MachineInstr* MI,
+                                      const SmallVectorImpl<unsigned> &Ops,
+                                      int FrameIndex) const override;
+
+  MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
+                                      MachineInstr* MI,
+                                      const SmallVectorImpl<unsigned> &Ops,
+                                      MachineInstr* LoadMI) const override {
     return nullptr;
   }
 
   unsigned createVR(MachineFunction* MF, MVT VT) const;
 
-  virtual bool isBranch(const MachineInstr *MI) const;
-  virtual bool isPredicable(MachineInstr *MI) const;
-  virtual bool
-  PredicateInstruction(MachineInstr *MI,
-                       const SmallVectorImpl<MachineOperand> &Cond) const;
-
-  virtual bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
-                                   unsigned ExtraPredCycles,
-                                   const BranchProbability &Probability) const;
-
-  virtual bool isProfitableToIfCvt(MachineBasicBlock &TMBB,
-                                   unsigned NumTCycles, unsigned ExtraTCycles,
-                                   MachineBasicBlock &FMBB,
-                                   unsigned NumFCycles, unsigned ExtraFCycles,
-                                   const BranchProbability &Probability) const;
-
-  virtual bool isPredicated(const MachineInstr *MI) const;
-  virtual bool isPredicated(unsigned Opcode) const;
-  virtual bool isPredicatedTrue(const MachineInstr *MI) const;
-  virtual bool isPredicatedTrue(unsigned Opcode) const;
-  virtual bool isPredicatedNew(const MachineInstr *MI) const;
-  virtual bool isPredicatedNew(unsigned Opcode) const;
-  virtual bool DefinesPredicate(MachineInstr *MI,
-                                std::vector<MachineOperand> &Pred) const;
-  virtual bool
-  SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
-                    const SmallVectorImpl<MachineOperand> &Pred2) const;
-
-  virtual bool
-  ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
-
-  virtual bool
-  isProfitableToDupForIfCvt(MachineBasicBlock &MBB,unsigned NumCycles,
-                            const BranchProbability &Probability) const;
-
-  virtual DFAPacketizer*
+  bool isBranch(const MachineInstr *MI) const;
+  bool isPredicable(MachineInstr *MI) const override;
+  bool PredicateInstruction(MachineInstr *MI,
+                    const SmallVectorImpl<MachineOperand> &Cond) const override;
+
+  bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
+                           unsigned ExtraPredCycles,
+                           const BranchProbability &Probability) const override;
+
+  bool isProfitableToIfCvt(MachineBasicBlock &TMBB,
+                           unsigned NumTCycles, unsigned ExtraTCycles,
+                           MachineBasicBlock &FMBB,
+                           unsigned NumFCycles, unsigned ExtraFCycles,
+                           const BranchProbability &Probability) const override;
+
+  bool isPredicated(const MachineInstr *MI) const override;
+  bool isPredicated(unsigned Opcode) const;
+  bool isPredicatedTrue(const MachineInstr *MI) const;
+  bool isPredicatedTrue(unsigned Opcode) const;
+  bool isPredicatedNew(const MachineInstr *MI) const;
+  bool isPredicatedNew(unsigned Opcode) const;
+  bool DefinesPredicate(MachineInstr *MI,
+                        std::vector<MachineOperand> &Pred) const override;
+  bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
+                   const SmallVectorImpl<MachineOperand> &Pred2) const override;
+
+  bool
+  ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
+
+  bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
+                           const BranchProbability &Probability) const override;
+
+  DFAPacketizer*
   CreateTargetScheduleState(const TargetMachine *TM,
-                            const ScheduleDAG *DAG) const;
+                            const ScheduleDAG *DAG) const override;
 
-  virtual bool isSchedulingBoundary(const MachineInstr *MI,
-                                    const MachineBasicBlock *MBB,
-                                    const MachineFunction &MF) const;
+  bool isSchedulingBoundary(const MachineInstr *MI,
+                            const MachineBasicBlock *MBB,
+                            const MachineFunction &MF) const override;
   bool isValidOffset(const int Opcode, const int Offset) const;
   bool isValidAutoIncImm(const EVT VT, const int Offset) const;
   bool isMemOp(const MachineInstr *MI) const;
diff --git a/lib/Target/Hexagon/HexagonNewValueJump.cpp b/lib/Target/Hexagon/HexagonNewValueJump.cpp
index 65bbad5225..b7c03a7277 100644
--- a/lib/Target/Hexagon/HexagonNewValueJump.cpp
+++ b/lib/Target/Hexagon/HexagonNewValueJump.cpp
@@ -75,16 +75,16 @@ namespace {
       initializeHexagonNewValueJumpPass(*PassRegistry::getPassRegistry());
     }
 
-    virtual void getAnalysisUsage(AnalysisUsage &AU) const {
+    void getAnalysisUsage(AnalysisUsage &AU) const override {
       AU.addRequired<MachineBranchProbabilityInfo>();
       MachineFunctionPass::getAnalysisUsage(AU);
     }
 
-    const char *getPassName() const {
+    const char *getPassName() const override {
       return "Hexagon NewValueJump";
     }
 
-    virtual bool runOnMachineFunction(MachineFunction &Fn);
+    bool runOnMachineFunction(MachineFunction &Fn) override;
 
   private:
     /// \brief A handle to the branch probability pass.
diff --git a/lib/Target/Hexagon/HexagonPeephole.cpp b/lib/Target/Hexagon/HexagonPeephole.cpp
index f55b78720b..48b6159085 100644
--- a/lib/Target/Hexagon/HexagonPeephole.cpp
+++ b/lib/Target/Hexagon/HexagonPeephole.cpp
@@ -90,13 +90,13 @@ namespace {
       initializeHexagonPeepholePass(*PassRegistry::getPassRegistry());
     }
 
-    bool runOnMachineFunction(MachineFunction &MF);
+    bool runOnMachineFunction(MachineFunction &MF) override;
 
-    const char *getPassName() const {
+    const char *getPassName() const override {
       return "Hexagon optimize redundant zero and size extends";
     }
 
-    void getAnalysisUsage(AnalysisUsage &AU) const {
+    void getAnalysisUsage(AnalysisUsage &AU) const override {
       MachineFunctionPass::getAnalysisUsage(AU);
     }
 
diff --git a/lib/Target/Hexagon/HexagonRegisterInfo.h b/lib/Target/Hexagon/HexagonRegisterInfo.h
index c0160d898e..648b4af9e9 100644
--- a/lib/Target/Hexagon/HexagonRegisterInfo.h
+++ b/lib/Target/Hexagon/HexagonRegisterInfo.h
@@ -49,16 +49,16 @@ struct HexagonRegisterInfo : public HexagonGenRegisterInfo {
 
   /// Code Generation virtual methods...
   const MCPhysReg *
-  getCalleeSavedRegs(const MachineFunction *MF = nullptr) const;
+  getCalleeSavedRegs(const MachineFunction *MF = nullptr) const override;
 
   const TargetRegisterClass* const*
   getCalleeSavedRegClasses(const MachineFunction *MF = nullptr) const;
 
-  BitVector getReservedRegs(const MachineFunction &MF) const;
+  BitVector getReservedRegs(const MachineFunction &MF) const override;
 
   void eliminateFrameIndex(MachineBasicBlock::iterator II,
                            int SPAdj, unsigned FIOperandNum,
-                           RegScavenger *RS = nullptr) const;
+                           RegScavenger *RS = nullptr) const override;
 
   /// determineFrameLayout - Determine the size of the frame and maximum call
   /// frame size.
@@ -66,17 +66,17 @@ struct HexagonRegisterInfo : public HexagonGenRegisterInfo {
 
   /// requiresRegisterScavenging - returns true since we may need scavenging for
   /// a temporary register when generating hardware loop instructions.
-  bool requiresRegisterScavenging(const MachineFunction &MF) const {
+  bool requiresRegisterScavenging(const MachineFunction &MF) const override {
     return true;
   }
 
-  bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const {
+  bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override {
     return true;
   }
 
   // Debug information queries.
   unsigned getRARegister() const;
-  unsigned getFrameRegister(const MachineFunction &MF) const;
+  unsigned getFrameRegister(const MachineFunction &MF) const override;
   unsigned getFrameRegister() const;
   unsigned getStackRegister() const;
 };
diff --git a/lib/Target/Hexagon/HexagonRemoveSZExtArgs.cpp b/lib/Target/Hexagon/HexagonRemoveSZExtArgs.cpp
index cadcb32c6e..2b459a4336 100644
--- a/lib/Target/Hexagon/HexagonRemoveSZExtArgs.cpp
+++ b/lib/Target/Hexagon/HexagonRemoveSZExtArgs.cpp
@@ -33,13 +33,13 @@ namespace {
     HexagonRemoveExtendArgs() : FunctionPass(ID) {
       initializeHexagonRemoveExtendArgsPass(*PassRegistry::getPassRegistry());
     }
-    virtual bool runOnFunction(Function &F);
+    bool runOnFunction(Function &F) override;
 
-    const char *getPassName() const {
+    const char *getPassName() const override {
       return "Remove sign extends";
     }
 
-    virtual void getAnalysisUsage(AnalysisUsage &AU) const {
+    void getAnalysisUsage(AnalysisUsage &AU) const override {
       AU.addRequired<MachineFunctionAnalysis>();
       AU.addPreserved<MachineFunctionAnalysis>();
       AU.addPreserved("stack-protector");
diff --git a/lib/Target/Hexagon/HexagonSelectionDAGInfo.h b/lib/Target/Hexagon/HexagonSelectionDAGInfo.h
index 31f278a185..8ba6108bdf 100644
--- a/lib/Target/Hexagon/HexagonSelectionDAGInfo.h
+++ b/lib/Target/Hexagon/HexagonSelectionDAGInfo.h
@@ -25,14 +25,13 @@ public:
   explicit HexagonSelectionDAGInfo(const HexagonTargetMachine &TM);
   ~HexagonSelectionDAGInfo();
 
-  virtual
   SDValue EmitTargetCodeForMemcpy(SelectionDAG &DAG, SDLoc dl,
                                   SDValue Chain,
                                   SDValue Dst, SDValue Src,
                                   SDValue Size, unsigned Align,
                                   bool isVolatile, bool AlwaysInline,
                                   MachinePointerInfo DstPtrInfo,
-                                  MachinePointerInfo SrcPtrInfo) const;
+                                  MachinePointerInfo SrcPtrInfo) const override;
 };
 
 }
diff --git a/lib/Target/Hexagon/HexagonSplitConst32AndConst64.cpp b/lib/Target/Hexagon/HexagonSplitConst32AndConst64.cpp
index e337952225..aa4121f4ed 100644
--- a/lib/Target/Hexagon/HexagonSplitConst32AndConst64.cpp
+++ b/lib/Target/Hexagon/HexagonSplitConst32AndConst64.cpp
@@ -55,10 +55,10 @@ class HexagonSplitConst32AndConst64 : public MachineFunctionPass {
     HexagonSplitConst32AndConst64(const HexagonTargetMachine& TM)
       : MachineFunctionPass(ID), QTM(TM), QST(*TM.getSubtargetImpl()) {}
 
-    const char *getPassName() const {
+    const char *getPassName() const override {
       return "Hexagon Split Const32s and Const64s";
     }
-    bool runOnMachineFunction(MachineFunction &Fn);
+    bool runOnMachineFunction(MachineFunction &Fn) override;
 };
 
 
diff --git a/lib/Target/Hexagon/HexagonSplitTFRCondSets.cpp b/lib/Target/Hexagon/HexagonSplitTFRCondSets.cpp
index 2f1ee41bb8..9601090af4 100644
--- a/lib/Target/Hexagon/HexagonSplitTFRCondSets.cpp
+++ b/lib/Target/Hexagon/HexagonSplitTFRCondSets.cpp
@@ -68,10 +68,10 @@ class HexagonSplitTFRCondSets : public MachineFunctionPass {
       initializeHexagonSplitTFRCondSetsPass(*PassRegistry::getPassRegistry());
     }
 
-    const char *getPassName() const {
+    const char *getPassName() const override {
       return "Hexagon Split TFRCondSets";
     }
-    bool runOnMachineFunction(MachineFunction &Fn);
+    bool runOnMachineFunction(MachineFunction &Fn) override;
 };
 
 
diff --git a/lib/Target/Hexagon/HexagonTargetMachine.cpp b/lib/Target/Hexagon/HexagonTargetMachine.cpp
index d8011a266c..0c5a643c7e 100644
--- a/lib/Target/Hexagon/HexagonTargetMachine.cpp
+++ b/lib/Target/Hexagon/HexagonTargetMachine.cpp
@@ -113,16 +113,16 @@ public:
     return getTM<HexagonTargetMachine>();
   }
 
-  virtual ScheduleDAGInstrs *
-  createMachineScheduler(MachineSchedContext *C) const {
+  ScheduleDAGInstrs *
+  createMachineScheduler(MachineSchedContext *C) const override {
     return createVLIWMachineSched(C);
   }
 
-  virtual bool addInstSelector();
-  virtual bool addPreRegAlloc();
-  virtual bool addPostRegAlloc();
-  virtual bool addPreSched2();
-  virtual bool addPreEmitPass();
+  bool addInstSelector() override;
+  bool addPreRegAlloc() override;
+  bool addPostRegAlloc() override;
+  bool addPreSched2() override;
+  bool addPreEmitPass() override;
 };
 } // namespace
 
diff --git a/lib/Target/Hexagon/HexagonTargetMachine.h b/lib/Target/Hexagon/HexagonTargetMachine.h
index cf8f9aa361..fcf5f7f15c 100644
--- a/lib/Target/Hexagon/HexagonTargetMachine.h
+++ b/lib/Target/Hexagon/HexagonTargetMachine.h
@@ -41,39 +41,39 @@ public:
                        Reloc::Model RM, CodeModel::Model CM,
                        CodeGenOpt::Level OL);
 
-  virtual const HexagonInstrInfo *getInstrInfo() const {
+  const HexagonInstrInfo *getInstrInfo() const override {
     return &InstrInfo;
   }
-  virtual const HexagonSubtarget *getSubtargetImpl() const {
+  const HexagonSubtarget *getSubtargetImpl() const override {
     return &Subtarget;
   }
-  virtual const HexagonRegisterInfo *getRegisterInfo() const {
+  const HexagonRegisterInfo *getRegisterInfo() const override {
     return &InstrInfo.getRegisterInfo();
   }
 
-  virtual const InstrItineraryData* getInstrItineraryData() const {
+  const InstrItineraryData* getInstrItineraryData() const override {
     return InstrItins;
   }
 
 
-  virtual const HexagonTargetLowering* getTargetLowering() const {
+  const HexagonTargetLowering* getTargetLowering() const override {
     return &TLInfo;
   }
 
-  virtual const HexagonFrameLowering* getFrameLowering() const {
+  const HexagonFrameLowering* getFrameLowering() const override {
     return &FrameLowering;
   }
 
-  virtual const HexagonSelectionDAGInfo* getSelectionDAGInfo() const {
+  const HexagonSelectionDAGInfo* getSelectionDAGInfo() const override {
     return &TSInfo;
   }
 
-  virtual const DataLayout       *getDataLayout() const { return &DL; }
+  const DataLayout       *getDataLayout() const override { return &DL; }
   static unsigned getModuleMatchQuality(const Module &M);
 
   // Pass Pipeline Configuration.
-  virtual bool addPassesForOptimizations(PassManagerBase &PM);
-  virtual TargetPassConfig *createPassConfig(PassManagerBase &PM);
+  virtual bool addPassesForOptimizations(PassManagerBase &PM) final;
+  TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
 };
 
 extern bool flag_aligned_memcpy;
diff --git a/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp b/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
index 867b705a05..87ce960a60 100644
--- a/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
+++ b/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
@@ -70,7 +70,7 @@ namespace {
       initializeHexagonPacketizerPass(*PassRegistry::getPassRegistry());
     }
 
-    void getAnalysisUsage(AnalysisUsage &AU) const {
+    void getAnalysisUsage(AnalysisUsage &AU) const override {
       AU.setPreservesCFG();
       AU.addRequired<MachineDominatorTree>();
       AU.addRequired<MachineBranchProbabilityInfo>();
@@ -80,11 +80,11 @@ namespace {
       MachineFunctionPass::getAnalysisUsage(AU);
     }
 
-    const char *getPassName() const {
+    const char *getPassName() const override {
       return "Hexagon Packetizer";
     }
 
-    bool runOnMachineFunction(MachineFunction &Fn);
+    bool runOnMachineFunction(MachineFunction &Fn) override;
   };
   char HexagonPacketizer::ID = 0;
 
@@ -122,24 +122,25 @@ namespace {
                           const MachineBranchProbabilityInfo *MBPI);
 
     // initPacketizerState - initialize some internal flags.
-    void initPacketizerState();
+    void initPacketizerState() override;
 
     // ignorePseudoInstruction - Ignore bundling of pseudo instructions.
-    bool ignorePseudoInstruction(MachineInstr *MI, MachineBasicBlock *MBB);
+    bool ignorePseudoInstruction(MachineInstr *MI,
+                                 MachineBasicBlock *MBB) override;
 
     // isSoloInstruction - return true if instruction MI can not be packetized
     // with any other instruction, which means that MI itself is a packet.
-    bool isSoloInstruction(MachineInstr *MI);
+    bool isSoloInstruction(MachineInstr *MI) override;
 
     // isLegalToPacketizeTogether - Is it legal to packetize SUI and SUJ
     // together.
-    bool isLegalToPacketizeTogether(SUnit *SUI, SUnit *SUJ);
+    bool isLegalToPacketizeTogether(SUnit *SUI, SUnit *SUJ) override;
 
     // isLegalToPruneDependencies - Is it legal to prune dependece between SUI
     // and SUJ.
-    bool isLegalToPruneDependencies(SUnit *SUI, SUnit *SUJ);
+    bool isLegalToPruneDependencies(SUnit *SUI, SUnit *SUJ) override;
 
-    MachineBasicBlock::iterator addToPacket(MachineInstr *MI);
+    MachineBasicBlock::iterator addToPacket(MachineInstr *MI) override;
   private:
     bool IsCallDependent(MachineInstr* MI, SDep::Kind DepType, unsigned DepReg);
     bool PromoteToDotNew(MachineInstr* MI, SDep::Kind DepType,
diff --git a/lib/Target/Hexagon/InstPrinter/HexagonInstPrinter.h b/lib/Target/Hexagon/InstPrinter/HexagonInstPrinter.h
index d0cef683da..09e3f88434 100644
--- a/lib/Target/Hexagon/InstPrinter/HexagonInstPrinter.h
+++ b/lib/Target/Hexagon/InstPrinter/HexagonInstPrinter.h
@@ -27,7 +27,7 @@ namespace llvm {
                                 const MCRegisterInfo &MRI)
       : MCInstPrinter(MAI, MII, MRI), MII(MII) {}
 
-    virtual void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot);
+    void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot) override;
     void printInst(const HexagonMCInst *MI, raw_ostream &O, StringRef Annot);
     virtual StringRef getOpcodeName(unsigned Opcode) const;
     void printInstruction(const MCInst *MI, raw_ostream &O);
diff --git a/lib/Target/Hexagon/MCTargetDesc/HexagonMCAsmInfo.h b/lib/Target/Hexagon/MCTargetDesc/HexagonMCAsmInfo.h
index bd8cb7637a..953d804b49 100644
--- a/lib/Target/Hexagon/MCTargetDesc/HexagonMCAsmInfo.h
+++ b/lib/Target/Hexagon/MCTargetDesc/HexagonMCAsmInfo.h
@@ -19,7 +19,7 @@
 
 namespace llvm {
   class HexagonMCAsmInfo : public MCAsmInfoELF {
-    virtual void anchor();
+    void anchor() override;
   public:
     explicit HexagonMCAsmInfo(StringRef TT);
   };
diff --git a/lib/Target/MSP430/InstPrinter/MSP430InstPrinter.h b/lib/Target/MSP430/InstPrinter/MSP430InstPrinter.h
index 4261224f8f..5afbd20dd4 100644
--- a/lib/Target/MSP430/InstPrinter/MSP430InstPrinter.h
+++ b/lib/Target/MSP430/InstPrinter/MSP430InstPrinter.h
@@ -25,7 +25,7 @@ namespace llvm {
                       const MCRegisterInfo &MRI)
       : MCInstPrinter(MAI, MII, MRI) {}
 
-    virtual void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot);
+    void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot) override;
 
     // Autogenerated by tblgen.
     void printInstruction(const MCInst *MI, raw_ostream &O);
diff --git a/lib/Target/MSP430/MCTargetDesc/MSP430MCAsmInfo.h b/lib/Target/MSP430/MCTargetDesc/MSP430MCAsmInfo.h
index a7e0e58941..ef805bbab5 100644
--- a/lib/Target/MSP430/MCTargetDesc/MSP430MCAsmInfo.h
+++ b/lib/Target/MSP430/MCTargetDesc/MSP430MCAsmInfo.h
@@ -20,7 +20,7 @@ namespace llvm {
   class StringRef;
 
   class MSP430MCAsmInfo : public MCAsmInfoELF {
-    virtual void anchor();
+    void anchor() override;
   public:
     explicit MSP430MCAsmInfo(StringRef TT);
   };
diff --git a/lib/Target/MSP430/MSP430AsmPrinter.cpp b/lib/Target/MSP430/MSP430AsmPrinter.cpp
index 73ef2cdb23..22a973eb17 100644
--- a/lib/Target/MSP430/MSP430AsmPrinter.cpp
+++ b/lib/Target/MSP430/MSP430AsmPrinter.cpp
@@ -42,7 +42,7 @@ namespace {
     MSP430AsmPrinter(TargetMachine &TM, MCStreamer &Streamer)
       : AsmPrinter(TM, Streamer) {}
 
-    virtual const char *getPassName() const {
+    const char *getPassName() const override {
       return "MSP430 Assembly Printer";
     }
 
@@ -52,11 +52,11 @@ namespace {
                             raw_ostream &O);
     bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
                          unsigned AsmVariant, const char *ExtraCode,
-                         raw_ostream &O);
+                         raw_ostream &O) override;
     bool PrintAsmMemoryOperand(const MachineInstr *MI,
                                unsigned OpNo, unsigned AsmVariant,
-                               const char *ExtraCode, raw_ostream &O);
-    void EmitInstruction(const MachineInstr *MI);
+                               const char *ExtraCode, raw_ostream &O) override;
+    void EmitInstruction(const MachineInstr *MI) override;
   };
 } // end of anonymous namespace
 
diff --git a/lib/Target/MSP430/MSP430BranchSelector.cpp b/lib/Target/MSP430/MSP430BranchSelector.cpp
index d33d35c5cf..a96930a098 100644
--- a/lib/Target/MSP430/MSP430BranchSelector.cpp
+++ b/lib/Target/MSP430/MSP430BranchSelector.cpp
@@ -36,9 +36,9 @@ namespace {
     /// BlockSizes - The sizes of the basic blocks in the function.
     std::vector<unsigned> BlockSizes;
 
-    virtual bool runOnMachineFunction(MachineFunction &Fn);
+    bool runOnMachineFunction(MachineFunction &Fn) override;
 
-    virtual const char *getPassName() const {
+    const char *getPassName() const override {
       return "MSP430 Branch Selector";
     }
   };
diff --git a/lib/Target/MSP430/MSP430FrameLowering.h b/lib/Target/MSP430/MSP430FrameLowering.h
index 70e14d1b51..d464dd9969 100644
--- a/lib/Target/MSP430/MSP430FrameLowering.h
+++ b/lib/Target/MSP430/MSP430FrameLowering.h
@@ -32,26 +32,26 @@ public:
 
   /// emitProlog/emitEpilog - These methods insert prolog and epilog code into
   /// the function.
-  void emitPrologue(MachineFunction &MF) const;
-  void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
+  void emitPrologue(MachineFunction &MF) const override;
+  void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override;
 
   void eliminateCallFramePseudoInstr(MachineFunction &MF,
-                                     MachineBasicBlock &MBB,
-                                     MachineBasicBlock::iterator I) const;
+                                  MachineBasicBlock &MBB,
+                                  MachineBasicBlock::iterator I) const override;
 
   bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
                                  MachineBasicBlock::iterator MI,
                                  const std::vector<CalleeSavedInfo> &CSI,
-                                 const TargetRegisterInfo *TRI) const;
+                                 const TargetRegisterInfo *TRI) const override;
   bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
-                                   MachineBasicBlock::iterator MI,
-                                   const std::vector<CalleeSavedInfo> &CSI,
-                                   const TargetRegisterInfo *TRI) const;
+                                  MachineBasicBlock::iterator MI,
+                                  const std::vector<CalleeSavedInfo> &CSI,
+                                  const TargetRegisterInfo *TRI) const override;
 
-  bool hasFP(const MachineFunction &MF) const;
-  bool hasReservedCallFrame(const MachineFunction &MF) const;
+  bool hasFP(const MachineFunction &MF) const override;
+  bool hasReservedCallFrame(const MachineFunction &MF) const override;
   void processFunctionBeforeFrameFinalized(MachineFunction &MF,
-                                       RegScavenger *RS = nullptr) const;
+                                     RegScavenger *RS = nullptr) const override;
 };
 
 } // End llvm namespace
diff --git a/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp b/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp
index 6dafc9a2a6..a9b903503d 100644
--- a/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp
+++ b/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp
@@ -101,7 +101,7 @@ namespace {
         Lowering(*TM.getTargetLowering()),
         Subtarget(*TM.getSubtargetImpl()) { }
 
-    virtual const char *getPassName() const {
+    const char *getPassName() const override {
       return "MSP430 DAG->DAG Pattern Instruction Selection";
     }
 
@@ -109,15 +109,14 @@ namespace {
     bool MatchWrapper(SDValue N, MSP430ISelAddressMode &AM);
     bool MatchAddressBase(SDValue N, MSP430ISelAddressMode &AM);
 
-    virtual bool
-    SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
-                                 std::vector<SDValue> &OutOps);
+    bool SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
+                                      std::vector<SDValue> &OutOps) override;
 
     // Include the pieces autogenerated from the target description.
   #include "MSP430GenDAGISel.inc"
 
   private:
-    SDNode *Select(SDNode *N);
+    SDNode *Select(SDNode *N) override;
     SDNode *SelectIndexedLoad(SDNode *Op);
     SDNode *SelectIndexedBinOp(SDNode *Op, SDValue N1, SDValue N2,
                                unsigned Opc8, unsigned Opc16);
diff --git a/lib/Target/MSP430/MSP430ISelLowering.h b/lib/Target/MSP430/MSP430ISelLowering.h
index 85a861ebec..3ced61de3f 100644
--- a/lib/Target/MSP430/MSP430ISelLowering.h
+++ b/lib/Target/MSP430/MSP430ISelLowering.h
@@ -73,14 +73,14 @@ namespace llvm {
   public:
     explicit MSP430TargetLowering(MSP430TargetMachine &TM);
 
-    virtual MVT getScalarShiftAmountTy(EVT LHSTy) const { return MVT::i8; }
+    MVT getScalarShiftAmountTy(EVT LHSTy) const override { return MVT::i8; }
 
     /// LowerOperation - Provide custom lowering hooks for some operations.
-    virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
+    SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
 
     /// getTargetNodeName - This method returns the name of a target specific
     /// DAG node.
-    virtual const char *getTargetNodeName(unsigned Opcode) const;
+    const char *getTargetNodeName(unsigned Opcode) const override;
 
     SDValue LowerShifts(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
@@ -97,15 +97,16 @@ namespace llvm {
     SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const;
 
     TargetLowering::ConstraintType
-    getConstraintType(const std::string &Constraint) const;
+    getConstraintType(const std::string &Constraint) const override;
     std::pair<unsigned, const TargetRegisterClass*>
-    getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const;
+    getRegForInlineAsmConstraint(const std::string &Constraint,
+                                 MVT VT) const override;
 
     /// isTruncateFree - Return true if it's free to truncate a value of type
     /// Ty1 to type Ty2. e.g. On msp430 it's free to truncate a i16 value in
     /// register R15W to i8 by referencing its sub-register R15B.
-    virtual bool isTruncateFree(Type *Ty1, Type *Ty2) const;
-    virtual bool isTruncateFree(EVT VT1, EVT VT2) const;
+    bool isTruncateFree(Type *Ty1, Type *Ty2) const override;
+    bool isTruncateFree(EVT VT1, EVT VT2) const override;
 
     /// isZExtFree - Return true if any actual instruction that defines a value
     /// of type Ty1 implicit zero-extends the value to Ty2 in the result
@@ -115,12 +116,12 @@ namespace llvm {
     /// necessarily apply to truncate instructions. e.g. on msp430, all
     /// instructions that define 8-bit values implicit zero-extend the result
     /// out to 16 bits.
-    virtual bool isZExtFree(Type *Ty1, Type *Ty2) const;
-    virtual bool isZExtFree(EVT VT1, EVT VT2) const;
-    virtual bool isZExtFree(SDValue Val, EVT VT2) const;
+    bool isZExtFree(Type *Ty1, Type *Ty2) const override;
+    bool isZExtFree(EVT VT1, EVT VT2) const override;
+    bool isZExtFree(SDValue Val, EVT VT2) const override;
 
     MachineBasicBlock* EmitInstrWithCustomInserter(MachineInstr *MI,
-                                                   MachineBasicBlock *BB) const;
+                                                   MachineBasicBlock *BB) const override;
     MachineBasicBlock* EmitShiftInstr(MachineInstr *MI,
                                       MachineBasicBlock *BB) const;
 
@@ -148,28 +149,27 @@ namespace llvm {
                             SDLoc dl, SelectionDAG &DAG,
                             SmallVectorImpl<SDValue> &InVals) const;
 
-    virtual SDValue
+    SDValue
       LowerFormalArguments(SDValue Chain,
                            CallingConv::ID CallConv, bool isVarArg,
                            const SmallVectorImpl<ISD::InputArg> &Ins,
                            SDLoc dl, SelectionDAG &DAG,
-                           SmallVectorImpl<SDValue> &InVals) const;
-    virtual SDValue
+                           SmallVectorImpl<SDValue> &InVals) const override;
+    SDValue
       LowerCall(TargetLowering::CallLoweringInfo &CLI,
-                SmallVectorImpl<SDValue> &InVals) const;
-
-    virtual SDValue
-      LowerReturn(SDValue Chain,
-                  CallingConv::ID CallConv, bool isVarArg,
-                  const SmallVectorImpl<ISD::OutputArg> &Outs,
-                  const SmallVectorImpl<SDValue> &OutVals,
-                  SDLoc dl, SelectionDAG &DAG) const;
-
-    virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
-                                            SDValue &Base,
-                                            SDValue &Offset,
-                                            ISD::MemIndexedMode &AM,
-                                            SelectionDAG &DAG) const;
+                SmallVectorImpl<SDValue> &InVals) const override;
+
+    SDValue LowerReturn(SDValue Chain,
+                        CallingConv::ID CallConv, bool isVarArg,
+                        const SmallVectorImpl<ISD::OutputArg> &Outs,
+                        const SmallVectorImpl<SDValue> &OutVals,
+                        SDLoc dl, SelectionDAG &DAG) const override;
+
+    bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
+                                    SDValue &Base,
+                                    SDValue &Offset,
+                                    ISD::MemIndexedMode &AM,
+                                    SelectionDAG &DAG) const override;
 
     const MSP430Subtarget &Subtarget;
     const DataLayout *TD;
diff --git a/lib/Target/MSP430/MSP430InstrInfo.h b/lib/Target/MSP430/MSP430InstrInfo.h
index ad2b8cc7cd..1ffcebb015 100644
--- a/lib/Target/MSP430/MSP430InstrInfo.h
+++ b/lib/Target/MSP430/MSP430InstrInfo.h
@@ -50,40 +50,41 @@ public:
   /// such, whenever a client has an instance of instruction info, it should
   /// always be able to get register info as well (through this method).
   ///
-  virtual const TargetRegisterInfo &getRegisterInfo() const { return RI; }
+  const TargetRegisterInfo &getRegisterInfo() const { return RI; }
 
   void copyPhysReg(MachineBasicBlock &MBB,
                    MachineBasicBlock::iterator I, DebugLoc DL,
                    unsigned DestReg, unsigned SrcReg,
-                   bool KillSrc) const;
-
-  virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
-                                   MachineBasicBlock::iterator MI,
-                                   unsigned SrcReg, bool isKill,
-                                   int FrameIndex,
-                                   const TargetRegisterClass *RC,
-                                   const TargetRegisterInfo *TRI) const;
-  virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
-                                    MachineBasicBlock::iterator MI,
-                                    unsigned DestReg, int FrameIdx,
-                                    const TargetRegisterClass *RC,
-                                    const TargetRegisterInfo *TRI) const;
+                   bool KillSrc) const override;
+
+  void storeRegToStackSlot(MachineBasicBlock &MBB,
+                           MachineBasicBlock::iterator MI,
+                           unsigned SrcReg, bool isKill,
+                           int FrameIndex,
+                           const TargetRegisterClass *RC,
+                           const TargetRegisterInfo *TRI) const override;
+  void loadRegFromStackSlot(MachineBasicBlock &MBB,
+                            MachineBasicBlock::iterator MI,
+                            unsigned DestReg, int FrameIdx,
+                            const TargetRegisterClass *RC,
+                            const TargetRegisterInfo *TRI) const override;
 
   unsigned GetInstSizeInBytes(const MachineInstr *MI) const;
 
   // Branch folding goodness
-  bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
-  bool isUnpredicatedTerminator(const MachineInstr *MI) const;
+  bool
+  ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
+  bool isUnpredicatedTerminator(const MachineInstr *MI) const override;
   bool AnalyzeBranch(MachineBasicBlock &MBB,
                      MachineBasicBlock *&TBB, MachineBasicBlock *&FBB,
                      SmallVectorImpl<MachineOperand> &Cond,
-                     bool AllowModify) const;
+                     bool AllowModify) const override;
 
-  unsigned RemoveBranch(MachineBasicBlock &MBB) const;
+  unsigned RemoveBranch(MachineBasicBlock &MBB) const override;
   unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
                         MachineBasicBlock *FBB,
                         const SmallVectorImpl<MachineOperand> &Cond,
-                        DebugLoc DL) const;
+                        DebugLoc DL) const override;
 
 };
 
diff --git a/lib/Target/MSP430/MSP430RegisterInfo.h b/lib/Target/MSP430/MSP430RegisterInfo.h
index 279886ed3a..a607528fd1 100644
--- a/lib/Target/MSP430/MSP430RegisterInfo.h
+++ b/lib/Target/MSP430/MSP430RegisterInfo.h
@@ -36,18 +36,19 @@ public:
 
   /// Code Generation virtual methods...
   const MCPhysReg *
-  getCalleeSavedRegs(const MachineFunction *MF = nullptr) const;
+  getCalleeSavedRegs(const MachineFunction *MF = nullptr) const override;
 
-  BitVector getReservedRegs(const MachineFunction &MF) const;
+  BitVector getReservedRegs(const MachineFunction &MF) const override;
   const TargetRegisterClass*
-  getPointerRegClass(const MachineFunction &MF, unsigned Kind = 0) const;
+  getPointerRegClass(const MachineFunction &MF,
+                     unsigned Kind = 0) const override;
 
   void eliminateFrameIndex(MachineBasicBlock::iterator II,
                            int SPAdj, unsigned FIOperandNum,
-                           RegScavenger *RS = nullptr) const;
+                           RegScavenger *RS = nullptr) const override;
 
   // Debug information queries.
-  unsigned getFrameRegister(const MachineFunction &MF) const;
+  unsigned getFrameRegister(const MachineFunction &MF) const override;
 };
 
 } // end namespace llvm
diff --git a/lib/Target/MSP430/MSP430TargetMachine.cpp b/lib/Target/MSP430/MSP430TargetMachine.cpp
index 98a6003fe6..50be2be300 100644
--- a/lib/Target/MSP430/MSP430TargetMachine.cpp
+++ b/lib/Target/MSP430/MSP430TargetMachine.cpp
@@ -51,8 +51,8 @@ public:
     return getTM<MSP430TargetMachine>();
   }
 
-  virtual bool addInstSelector();
-  virtual bool addPreEmitPass();
+  bool addInstSelector() override;
+  bool addPreEmitPass() override;
 };
 } // namespace
 
diff --git a/lib/Target/MSP430/MSP430TargetMachine.h b/lib/Target/MSP430/MSP430TargetMachine.h
index be695a2111..ea5d407370 100644
--- a/lib/Target/MSP430/MSP430TargetMachine.h
+++ b/lib/Target/MSP430/MSP430TargetMachine.h
@@ -43,25 +43,25 @@ public:
                       Reloc::Model RM, CodeModel::Model CM,
                       CodeGenOpt::Level OL);
 
-  virtual const TargetFrameLowering *getFrameLowering() const {
+  const TargetFrameLowering *getFrameLowering() const override {
     return &FrameLowering;
   }
-  virtual const MSP430InstrInfo *getInstrInfo() const  { return &InstrInfo; }
-  virtual const DataLayout *getDataLayout() const     { return &DL;}
-  virtual const MSP430Subtarget *getSubtargetImpl() const { return &Subtarget; }
+  const MSP430InstrInfo *getInstrInfo() const override  { return &InstrInfo; }
+  const DataLayout *getDataLayout() const override     { return &DL;}
+  const MSP430Subtarget *getSubtargetImpl() const override { return &Subtarget; }
 
-  virtual const TargetRegisterInfo *getRegisterInfo() const {
+  const TargetRegisterInfo *getRegisterInfo() const override {
     return &InstrInfo.getRegisterInfo();
   }
 
-  virtual const MSP430TargetLowering *getTargetLowering() const {
+  const MSP430TargetLowering *getTargetLowering() const override {
     return &TLInfo;
   }
 
-  virtual const MSP430SelectionDAGInfo* getSelectionDAGInfo() const {
+  const MSP430SelectionDAGInfo* getSelectionDAGInfo() const override {
     return &TSInfo;
   }
-  virtual TargetPassConfig *createPassConfig(PassManagerBase &PM);
+  TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
 }; // MSP430TargetMachine.
 
 } // end namespace llvm
diff --git a/lib/Target/Mips/AsmParser/MipsAsmParser.cpp b/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
index ac899a5106..4449cc20c9 100644
--- a/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
+++ b/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
@@ -75,10 +75,10 @@ class MipsAsmParser : public MCTargetAsmParser {
   bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
                                SmallVectorImpl<MCParsedAsmOperand *> &Operands,
                                MCStreamer &Out, unsigned &ErrorInfo,
-                               bool MatchingInlineAsm);
+                               bool MatchingInlineAsm) override;
 
   /// Parse a register as used in CFI directives
-  bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
+  bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
 
   bool ParseParenSuffix(StringRef Name,
                         SmallVectorImpl<MCParsedAsmOperand *> &Operands);
@@ -86,11 +86,11 @@ class MipsAsmParser : public MCTargetAsmParser {
   bool ParseBracketSuffix(StringRef Name,
                           SmallVectorImpl<MCParsedAsmOperand *> &Operands);
 
-  bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
-                        SMLoc NameLoc,
-                        SmallVectorImpl<MCParsedAsmOperand *> &Operands);
+  bool
+  ParseInstruction(ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc,
+                   SmallVectorImpl<MCParsedAsmOperand *> &Operands) override;
 
-  bool ParseDirective(AsmToken DirectiveID);
+  bool ParseDirective(AsmToken DirectiveID) override;
 
   MipsAsmParser::OperandMatchResultTy
   parseMemOperand(SmallVectorImpl<MCParsedAsmOperand *> &Operands);
@@ -137,6 +137,7 @@ class MipsAsmParser : public MCTargetAsmParser {
                      SmallVectorImpl<MCInst> &Instructions, bool isLoad,
                      bool isImmOpnd);
   bool reportParseError(StringRef ErrorMsg);
+  bool reportParseError(SMLoc Loc, StringRef ErrorMsg);
 
   bool parseMemOffset(const MCExpr *&Res, bool isParenExpr);
   bool parseRelocOperand(const MCExpr *&Res);
@@ -145,6 +146,7 @@ class MipsAsmParser : public MCTargetAsmParser {
 
   bool isEvaluated(const MCExpr *Expr);
   bool parseSetFeature(uint64_t Feature);
+  bool parseDirectiveCPLoad(SMLoc Loc);
   bool parseDirectiveCPSetup();
   bool parseDirectiveNaN();
   bool parseDirectiveSet();
@@ -577,7 +579,7 @@ public:
     addExpr(Inst, Expr);
   }
 
-  bool isReg() const {
+  bool isReg() const override {
     // As a special case until we sort out the definition of div/divu, pretend
     // that $0/$zero are k_PhysRegister so that MCK_ZERO works correctly.
     if (isGPRAsmReg() && RegIdx.Index == 0)
@@ -586,16 +588,16 @@ public:
     return Kind == k_PhysRegister;
   }
   bool isRegIdx() const { return Kind == k_RegisterIndex; }
-  bool isImm() const { return Kind == k_Immediate; }
+  bool isImm() const override { return Kind == k_Immediate; }
   bool isConstantImm() const {
     return isImm() && dyn_cast<MCConstantExpr>(getImm());
   }
-  bool isToken() const {
+  bool isToken() const override {
     // Note: It's not possible to pretend that other operand kinds are tokens.
     // The matcher emitter checks tokens first.
     return Kind == k_Token;
   }
-  bool isMem() const { return Kind == k_Memory; }
+  bool isMem() const override { return Kind == k_Memory; }
   bool isInvNum() const { return Kind == k_Immediate; }
   bool isLSAImm() const {
     if (!isConstantImm())
@@ -609,7 +611,7 @@ public:
     return StringRef(Tok.Data, Tok.Length);
   }
 
-  unsigned getReg() const {
+  unsigned getReg() const override {
     // As a special case until we sort out the definition of div/divu, pretend
     // that $0/$zero are k_PhysRegister so that MCK_ZERO works correctly.
     if (Kind == k_RegisterIndex && RegIdx.Index == 0 &&
@@ -756,9 +758,9 @@ public:
   }
 
   /// getStartLoc - Get the location of the first token of this operand.
-  SMLoc getStartLoc() const { return StartLoc; }
+  SMLoc getStartLoc() const override { return StartLoc; }
   /// getEndLoc - Get the location of the last token of this operand.
-  SMLoc getEndLoc() const { return EndLoc; }
+  SMLoc getEndLoc() const override { return EndLoc; }
 
   virtual ~MipsOperand() {
     switch (Kind) {
@@ -774,7 +776,7 @@ public:
     }
   }
 
-  virtual void print(raw_ostream &OS) const {
+  void print(raw_ostream &OS) const override {
     switch (Kind) {
     case k_Immediate:
       OS << "Imm<";
@@ -2083,6 +2085,10 @@ bool MipsAsmParser::reportParseError(StringRef ErrorMsg) {
   return Error(Loc, ErrorMsg);
 }
 
+bool MipsAsmParser::reportParseError(SMLoc Loc, StringRef ErrorMsg) {
+  return Error(Loc, ErrorMsg);
+}
+
 bool MipsAsmParser::parseSetNoAtDirective() {
   // Line should look like: ".set noat".
   // set at reg to 0.
@@ -2301,6 +2307,30 @@ bool MipsAsmParser::eatComma(StringRef ErrorStr) {
   return true;
 }
 
+bool MipsAsmParser::parseDirectiveCPLoad(SMLoc Loc) {
+  if (Options.isReorder())
+    Warning(Loc, ".cpload in reorder section");
+
+  // FIXME: Warn if cpload is used in Mips16 mode.
+
+  SmallVector<MCParsedAsmOperand *, 1> Reg;
+  OperandMatchResultTy ResTy = ParseAnyRegister(Reg);
+  if (ResTy == MatchOperand_NoMatch || ResTy == MatchOperand_ParseFail) {
+    reportParseError("expected register containing function address");
+    return false;
+  }
+
+  MipsOperand *RegOpnd = static_cast<MipsOperand *>(Reg[0]);
+  if (!RegOpnd->isGPRAsmReg()) {
+    reportParseError(RegOpnd->getStartLoc(), "invalid register");
+    return false;
+  }
+
+  getTargetStreamer().emitDirectiveCpload(RegOpnd->getGPR32Reg());
+  delete RegOpnd;
+  return false;
+}
+
 bool MipsAsmParser::parseDirectiveCPSetup() {
   unsigned FuncReg;
   unsigned Save;
@@ -2550,6 +2580,8 @@ bool MipsAsmParser::parseDirectiveOption() {
 bool MipsAsmParser::ParseDirective(AsmToken DirectiveID) {
   StringRef IDVal = DirectiveID.getString();
 
+  if (IDVal == ".cpload")
+    return parseDirectiveCPLoad(DirectiveID.getLoc());
   if (IDVal == ".dword") {
     parseDataDirective(8, DirectiveID.getLoc());
     return false;
diff --git a/lib/Target/Mips/Disassembler/MipsDisassembler.cpp b/lib/Target/Mips/Disassembler/MipsDisassembler.cpp
index 8e109cdbeb..cbe96b9123 100644
--- a/lib/Target/Mips/Disassembler/MipsDisassembler.cpp
+++ b/lib/Target/Mips/Disassembler/MipsDisassembler.cpp
@@ -64,12 +64,12 @@ public:
     }
 
   /// getInstruction - See MCDisassembler.
-  virtual DecodeStatus getInstruction(MCInst &instr,
-                                      uint64_t &size,
-                                      const MemoryObject &region,
-                                      uint64_t address,
-                                      raw_ostream &vStream,
-                                      raw_ostream &cStream) const;
+  DecodeStatus getInstruction(MCInst &instr,
+                              uint64_t &size,
+                              const MemoryObject &region,
+                              uint64_t address,
+                              raw_ostream &vStream,
+                              raw_ostream &cStream) const override;
 };
 
 
@@ -83,12 +83,12 @@ public:
     MipsDisassemblerBase(STI, Ctx, bigEndian) {}
 
   /// getInstruction - See MCDisassembler.
-  virtual DecodeStatus getInstruction(MCInst &instr,
-                                      uint64_t &size,
-                                      const MemoryObject &region,
-                                      uint64_t address,
-                                      raw_ostream &vStream,
-                                      raw_ostream &cStream) const;
+  DecodeStatus getInstruction(MCInst &instr,
+                              uint64_t &size,
+                              const MemoryObject &region,
+                              uint64_t address,
+                              raw_ostream &vStream,
+                              raw_ostream &cStream) const override;
 };
 
 } // end anonymous namespace
diff --git a/lib/Target/Mips/InstPrinter/MipsInstPrinter.h b/lib/Target/Mips/InstPrinter/MipsInstPrinter.h
index 2b745f028e..25dbcb02d2 100644
--- a/lib/Target/Mips/InstPrinter/MipsInstPrinter.h
+++ b/lib/Target/Mips/InstPrinter/MipsInstPrinter.h
@@ -85,8 +85,8 @@ public:
   void printInstruction(const MCInst *MI, raw_ostream &O);
   static const char *getRegisterName(unsigned RegNo);
 
-  virtual void printRegName(raw_ostream &OS, unsigned RegNo) const;
-  virtual void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot);
+  void printRegName(raw_ostream &OS, unsigned RegNo) const override;
+  void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot) override;
 
   bool printAliasInstr(const MCInst *MI, raw_ostream &OS);
 
diff --git a/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.h b/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.h
index cc5207a3bb..bc695e6d4f 100644
--- a/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.h
+++ b/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.h
@@ -37,14 +37,14 @@ public:
       : MCAsmBackend(), OSType(_OSType), IsLittle(_isLittle),
         Is64Bit(_is64Bit) {}
 
-  MCObjectWriter *createObjectWriter(raw_ostream &OS) const;
+  MCObjectWriter *createObjectWriter(raw_ostream &OS) const override;
 
   void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
-                  uint64_t Value, bool IsPCRel) const;
+                  uint64_t Value, bool IsPCRel) const override;
 
-  const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const;
+  const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override;
 
-  unsigned getNumFixupKinds() const {
+  unsigned getNumFixupKinds() const override {
     return Mips::NumTargetFixupKinds;
   }
 
@@ -55,7 +55,7 @@ public:
   /// relaxation.
   ///
   /// \param Inst - The instruction to test.
-  bool mayNeedRelaxation(const MCInst &Inst) const {
+  bool mayNeedRelaxation(const MCInst &Inst) const override {
     return false;
   }
 
@@ -63,7 +63,7 @@ public:
   /// fixup requires the associated instruction to be relaxed.
    bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value,
                              const MCRelaxableFragment *DF,
-                             const MCAsmLayout &Layout) const {
+                             const MCAsmLayout &Layout) const override {
     // FIXME.
     assert(0 && "RelaxInstruction() unimplemented");
     return false;
@@ -75,16 +75,16 @@ public:
   /// \param Inst - The instruction to relax, which may be the same
   /// as the output.
   /// \param [out] Res On return, the relaxed instruction.
-  void relaxInstruction(const MCInst &Inst, MCInst &Res) const {}
+  void relaxInstruction(const MCInst &Inst, MCInst &Res) const override {}
 
   /// @}
 
-  bool writeNopData(uint64_t Count, MCObjectWriter *OW) const;
+  bool writeNopData(uint64_t Count, MCObjectWriter *OW) const override;
 
   void processFixupValue(const MCAssembler &Asm, const MCAsmLayout &Layout,
                          const MCFixup &Fixup, const MCFragment *DF,
                          const MCValue &Target, uint64_t &Value,
-                         bool &IsResolved);
+                         bool &IsResolved) override;
 
 }; // class MipsAsmBackend
 
diff --git a/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.h b/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.h
index 1000113351..37ba0c4aaa 100644
--- a/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.h
+++ b/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.h
@@ -20,7 +20,7 @@ namespace llvm {
   class StringRef;
 
   class MipsMCAsmInfo : public MCAsmInfoELF {
-    virtual void anchor();
+    void anchor() override;
   public:
     explicit MipsMCAsmInfo(StringRef TT);
   };
diff --git a/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.h b/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.h
index 49a24904b4..8118e4fe45 100644
--- a/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.h
+++ b/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.h
@@ -52,7 +52,7 @@ public:
 
   void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
                          SmallVectorImpl<MCFixup> &Fixups,
-                         const MCSubtargetInfo &STI) const;
+                         const MCSubtargetInfo &STI) const override;
 
   // getBinaryCodeForInstr - TableGen'erated function for getting the
   // binary encoding for an instruction.
diff --git a/lib/Target/Mips/MCTargetDesc/MipsMCExpr.h b/lib/Target/Mips/MCTargetDesc/MipsMCExpr.h
index 722bba71e9..8d7aacde31 100644
--- a/lib/Target/Mips/MCTargetDesc/MipsMCExpr.h
+++ b/lib/Target/Mips/MCTargetDesc/MipsMCExpr.h
@@ -46,16 +46,16 @@ public:
   /// getSubExpr - Get the child of this expression.
   const MCExpr *getSubExpr() const { return Expr; }
 
-  void PrintImpl(raw_ostream &OS) const;
+  void PrintImpl(raw_ostream &OS) const override;
   bool EvaluateAsRelocatableImpl(MCValue &Res,
-                                 const MCAsmLayout *Layout) const;
-  void AddValueSymbols(MCAssembler *) const;
-  const MCSection *FindAssociatedSection() const {
+                                 const MCAsmLayout *Layout) const override;
+  void AddValueSymbols(MCAssembler *) const override;
+  const MCSection *FindAssociatedSection() const override {
     return getSubExpr()->FindAssociatedSection();
   }
 
   // There are no TLS MipsMCExprs at the moment.
-  void fixELFSymbolsInTLSFixups(MCAssembler &Asm) const {}
+  void fixELFSymbolsInTLSFixups(MCAssembler &Asm) const override {}
 
   static bool classof(const MCExpr *E) {
     return E->getKind() == MCExpr::Target;
diff --git a/lib/Target/Mips/MCTargetDesc/MipsNaClELFStreamer.cpp b/lib/Target/Mips/MCTargetDesc/MipsNaClELFStreamer.cpp
index 52fae1a16e..cd6be734df 100644
--- a/lib/Target/Mips/MCTargetDesc/MipsNaClELFStreamer.cpp
+++ b/lib/Target/Mips/MCTargetDesc/MipsNaClELFStreamer.cpp
@@ -120,7 +120,8 @@ private:
 public:
   /// This function is the one used to emit instruction data into the ELF
   /// streamer.  We override it to mask dangerous instructions.
-  virtual void EmitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI) {
+  void EmitInstruction(const MCInst &Inst,
+                       const MCSubtargetInfo &STI) override {
     // Sandbox indirect jumps.
     if (isIndirectJump(Inst)) {
       if (PendingCall)
diff --git a/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp b/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp
index 053e13e556..ab1b1f6043 100644
--- a/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp
+++ b/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp
@@ -144,6 +144,11 @@ void MipsTargetAsmStreamer::emitFMask(unsigned FPUBitmask,
   OS << "," << FPUTopSavedRegOff << '\n';
 }
 
+void MipsTargetAsmStreamer::emitDirectiveCpload(unsigned RegNo) {
+  OS << "\t.cpload\t$"
+     << StringRef(MipsInstPrinter::getRegisterName(RegNo)).lower() << "\n";
+}
+
 // This part is for ELF object output.
 MipsTargetELFStreamer::MipsTargetELFStreamer(MCStreamer &S,
                                              const MCSubtargetInfo &STI)
@@ -402,3 +407,52 @@ void MipsTargetELFStreamer::emitDirectiveSetMips64R2() {
 void MipsTargetELFStreamer::emitDirectiveSetDsp() {
   // No action required for ELF output.
 }
+
+void MipsTargetELFStreamer::emitDirectiveCpload(unsigned RegNo) {
+  // .cpload $reg
+  // This directive expands to:
+  // lui   $gp, %hi(_gp_disp)
+  // addui $gp, $gp, %lo(_gp_disp)
+  // addu  $gp, $gp, $reg
+  // when support for position independent code is enabled.
+  if (!Pic || (isN32() || isN64()))
+    return;
+
+  // There's a GNU extension controlled by -mno-shared that allows
+  // locally-binding symbols to be accessed using absolute addresses.
+  // This is currently not supported. When supported -mno-shared makes
+  // .cpload expand to:
+  //   lui     $gp, %hi(__gnu_local_gp)
+  //   addiu   $gp, $gp, %lo(__gnu_local_gp)
+
+  StringRef SymName("_gp_disp");
+  MCAssembler &MCA = getStreamer().getAssembler();
+  MCSymbol *GP_Disp = MCA.getContext().GetOrCreateSymbol(SymName);
+  MCA.getOrCreateSymbolData(*GP_Disp);
+
+  MCInst TmpInst;
+  TmpInst.setOpcode(Mips::LUi);
+  TmpInst.addOperand(MCOperand::CreateReg(Mips::GP));
+  const MCSymbolRefExpr *HiSym = MCSymbolRefExpr::Create(
+      "_gp_disp", MCSymbolRefExpr::VK_Mips_ABS_HI, MCA.getContext());
+  TmpInst.addOperand(MCOperand::CreateExpr(HiSym));
+  getStreamer().EmitInstruction(TmpInst, STI);
+
+  TmpInst.clear();
+
+  TmpInst.setOpcode(Mips::ADDiu);
+  TmpInst.addOperand(MCOperand::CreateReg(Mips::GP));
+  TmpInst.addOperand(MCOperand::CreateReg(Mips::GP));
+  const MCSymbolRefExpr *LoSym = MCSymbolRefExpr::Create(
+      "_gp_disp", MCSymbolRefExpr::VK_Mips_ABS_LO, MCA.getContext());
+  TmpInst.addOperand(MCOperand::CreateExpr(LoSym));
+  getStreamer().EmitInstruction(TmpInst, STI);
+
+  TmpInst.clear();
+
+  TmpInst.setOpcode(Mips::ADDu);
+  TmpInst.addOperand(MCOperand::CreateReg(Mips::GP));
+  TmpInst.addOperand(MCOperand::CreateReg(Mips::GP));
+  TmpInst.addOperand(MCOperand::CreateReg(RegNo));
+  getStreamer().EmitInstruction(TmpInst, STI);
+}
diff --git a/lib/Target/Mips/Mips16FrameLowering.h b/lib/Target/Mips/Mips16FrameLowering.h
index 8ce2ceda7c..3f7829dd6b 100644
--- a/lib/Target/Mips/Mips16FrameLowering.h
+++ b/lib/Target/Mips/Mips16FrameLowering.h
@@ -24,27 +24,27 @@ public:
 
   /// emitProlog/emitEpilog - These methods insert prolog and epilog code into
   /// the function.
-  void emitPrologue(MachineFunction &MF) const;
-  void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
+  void emitPrologue(MachineFunction &MF) const override;
+  void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override;
 
   void eliminateCallFramePseudoInstr(MachineFunction &MF,
-                                     MachineBasicBlock &MBB,
-                                     MachineBasicBlock::iterator I) const;
+                                  MachineBasicBlock &MBB,
+                                  MachineBasicBlock::iterator I) const override;
 
   bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
                                  MachineBasicBlock::iterator MI,
                                  const std::vector<CalleeSavedInfo> &CSI,
-                                 const TargetRegisterInfo *TRI) const;
+                                 const TargetRegisterInfo *TRI) const override;
 
   bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
-                                   MachineBasicBlock::iterator MI,
-                                   const std::vector<CalleeSavedInfo> &CSI,
-                                   const TargetRegisterInfo *TRI) const;
+                                  MachineBasicBlock::iterator MI,
+                                  const std::vector<CalleeSavedInfo> &CSI,
+                                  const TargetRegisterInfo *TRI) const override;
 
-  bool hasReservedCallFrame(const MachineFunction &MF) const;
+  bool hasReservedCallFrame(const MachineFunction &MF) const override;
 
   void processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
-                                            RegScavenger *RS) const;
+                                            RegScavenger *RS) const override;
 };
 
 } // End llvm namespace
diff --git a/lib/Target/Mips/Mips16HardFloat.h b/lib/Target/Mips/Mips16HardFloat.h
index b7f712af5b..826887ea5e 100644
--- a/lib/Target/Mips/Mips16HardFloat.h
+++ b/lib/Target/Mips/Mips16HardFloat.h
@@ -34,11 +34,11 @@ public:
     TM(TM_), Subtarget(TM.getSubtarget<MipsSubtarget>()) {
   }
 
-  virtual const char *getPassName() const {
+  const char *getPassName() const override {
     return "MIPS16 Hard Float Pass";
   }
 
-  virtual bool runOnModule(Module &M);
+  bool runOnModule(Module &M) override;
 
 protected:
   /// Keep a pointer to the MipsSubtarget around so that we can make the right
diff --git a/lib/Target/Mips/Mips16ISelDAGToDAG.h b/lib/Target/Mips/Mips16ISelDAGToDAG.h
index 49dc6e587b..e653b39103 100644
--- a/lib/Target/Mips/Mips16ISelDAGToDAG.h
+++ b/lib/Target/Mips/Mips16ISelDAGToDAG.h
@@ -28,16 +28,16 @@ private:
 
   SDValue getMips16SPAliasReg();
 
-  virtual bool runOnMachineFunction(MachineFunction &MF);
+  bool runOnMachineFunction(MachineFunction &MF) override;
 
   void getMips16SPRefReg(SDNode *Parent, SDValue &AliasReg);
 
-  virtual bool selectAddr16(SDNode *Parent, SDValue N, SDValue &Base,
-                            SDValue &Offset, SDValue &Alias);
+  bool selectAddr16(SDNode *Parent, SDValue N, SDValue &Base,
+                    SDValue &Offset, SDValue &Alias) override;
 
-  virtual std::pair<bool, SDNode*> selectNode(SDNode *Node);
+  std::pair<bool, SDNode*> selectNode(SDNode *Node) override;
 
-  virtual void processFunctionAfterISel(MachineFunction &MF);
+  void processFunctionAfterISel(MachineFunction &MF) override;
 
   // Insert instructions to initialize the global base register in the
   // first MBB of the function.
diff --git a/lib/Target/Mips/Mips16ISelLowering.h b/lib/Target/Mips/Mips16ISelLowering.h
index 618ec905ef..df883339b2 100644
--- a/lib/Target/Mips/Mips16ISelLowering.h
+++ b/lib/Target/Mips/Mips16ISelLowering.h
@@ -21,17 +21,17 @@ namespace llvm {
   public:
     explicit Mips16TargetLowering(MipsTargetMachine &TM);
 
-    virtual bool allowsUnalignedMemoryAccesses(EVT VT, unsigned AddrSpace,
-                                               bool *Fast) const;
+    bool allowsUnalignedMemoryAccesses(EVT VT, unsigned AddrSpace,
+                                       bool *Fast) const override;
 
-    virtual MachineBasicBlock *
-    EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const;
+    MachineBasicBlock *
+    EmitInstrWithCustomInserter(MachineInstr *MI,
+                                MachineBasicBlock *MBB) const override;
 
   private:
-    virtual bool
-    isEligibleForTailCallOptimization(const MipsCC &MipsCCInfo,
-                                      unsigned NextStackOffset,
-                                      const MipsFunctionInfo& FI) const;
+    bool isEligibleForTailCallOptimization(const MipsCC &MipsCCInfo,
+                                     unsigned NextStackOffset,
+                                     const MipsFunctionInfo& FI) const override;
 
     void setMips16HardFloatLibCalls();
 
@@ -41,11 +41,12 @@ namespace llvm {
     const char *getMips16HelperFunction
       (Type* RetTy, ArgListTy &Args, bool &needHelper) const;
 
-    virtual void
+    void
     getOpndList(SmallVectorImpl<SDValue> &Ops,
                 std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
                 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
-                CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const;
+                CallLoweringInfo &CLI, SDValue Callee,
+                SDValue Chain) const override;
 
     MachineBasicBlock *emitSel16(unsigned Opc, MachineInstr *MI,
                                  MachineBasicBlock *BB) const;
diff --git a/lib/Target/Mips/Mips16InstrInfo.h b/lib/Target/Mips/Mips16InstrInfo.h
index e93925c886..0dc00461cc 100644
--- a/lib/Target/Mips/Mips16InstrInfo.h
+++ b/lib/Target/Mips/Mips16InstrInfo.h
@@ -25,46 +25,46 @@ class Mips16InstrInfo : public MipsInstrInfo {
 public:
   explicit Mips16InstrInfo(MipsTargetMachine &TM);
 
-  virtual const MipsRegisterInfo &getRegisterInfo() const;
+  const MipsRegisterInfo &getRegisterInfo() const override;
 
   /// isLoadFromStackSlot - If the specified machine instruction is a direct
   /// load from a stack slot, return the virtual or physical register number of
   /// the destination along with the FrameIndex of the loaded stack slot.  If
   /// not, return 0.  This predicate must return 0 if the instruction has
   /// any side effects other than loading from the stack slot.
-  virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
-                                       int &FrameIndex) const;
+  unsigned isLoadFromStackSlot(const MachineInstr *MI,
+                               int &FrameIndex) const override;
 
   /// isStoreToStackSlot - If the specified machine instruction is a direct
   /// store to a stack slot, return the virtual or physical register number of
   /// the source reg along with the FrameIndex of the loaded stack slot.  If
   /// not, return 0.  This predicate must return 0 if the instruction has
   /// any side effects other than storing to the stack slot.
-  virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
-                                      int &FrameIndex) const;
+  unsigned isStoreToStackSlot(const MachineInstr *MI,
+                              int &FrameIndex) const override;
 
-  virtual void copyPhysReg(MachineBasicBlock &MBB,
-                           MachineBasicBlock::iterator MI, DebugLoc DL,
-                           unsigned DestReg, unsigned SrcReg,
-                           bool KillSrc) const;
+  void copyPhysReg(MachineBasicBlock &MBB,
+                   MachineBasicBlock::iterator MI, DebugLoc DL,
+                   unsigned DestReg, unsigned SrcReg,
+                   bool KillSrc) const override;
 
-  virtual void storeRegToStack(MachineBasicBlock &MBB,
-                               MachineBasicBlock::iterator MBBI,
-                               unsigned SrcReg, bool isKill, int FrameIndex,
-                               const TargetRegisterClass *RC,
-                               const TargetRegisterInfo *TRI,
-                               int64_t Offset) const;
+  void storeRegToStack(MachineBasicBlock &MBB,
+                       MachineBasicBlock::iterator MBBI,
+                       unsigned SrcReg, bool isKill, int FrameIndex,
+                       const TargetRegisterClass *RC,
+                       const TargetRegisterInfo *TRI,
+                       int64_t Offset) const override;
 
-  virtual void loadRegFromStack(MachineBasicBlock &MBB,
-                                MachineBasicBlock::iterator MBBI,
-                                unsigned DestReg, int FrameIndex,
-                                const TargetRegisterClass *RC,
-                                const TargetRegisterInfo *TRI,
-                                int64_t Offset) const;
+  void loadRegFromStack(MachineBasicBlock &MBB,
+                        MachineBasicBlock::iterator MBBI,
+                        unsigned DestReg, int FrameIndex,
+                        const TargetRegisterClass *RC,
+                        const TargetRegisterInfo *TRI,
+                        int64_t Offset) const override;
 
-  virtual bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const;
+  bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const override;
 
-  virtual unsigned getOppositeBranchOpc(unsigned Opc) const;
+  unsigned getOppositeBranchOpc(unsigned Opc) const override;
 
   // Adjust SP by FrameSize bytes. Save RA, S0, S1
   void makeFrame(unsigned SP, int64_t FrameSize, MachineBasicBlock &MBB,
@@ -104,9 +104,9 @@ public:
     (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, int64_t Imm) const;
 
   unsigned getInlineAsmLength(const char *Str,
-                              const MCAsmInfo &MAI) const;
+                              const MCAsmInfo &MAI) const override;
 private:
-  virtual unsigned getAnalyzableBrOpc(unsigned Opc) const;
+  unsigned getAnalyzableBrOpc(unsigned Opc) const override;
 
   void ExpandRetRA16(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
                    unsigned Opc) const;
diff --git a/lib/Target/Mips/Mips16RegisterInfo.h b/lib/Target/Mips/Mips16RegisterInfo.h
index 13e82a3ffb..f59f1a7c10 100644
--- a/lib/Target/Mips/Mips16RegisterInfo.h
+++ b/lib/Target/Mips/Mips16RegisterInfo.h
@@ -23,24 +23,24 @@ class Mips16RegisterInfo : public MipsRegisterInfo {
 public:
   Mips16RegisterInfo(const MipsSubtarget &Subtarget);
 
-  bool requiresRegisterScavenging(const MachineFunction &MF) const;
+  bool requiresRegisterScavenging(const MachineFunction &MF) const override;
 
-  bool requiresFrameIndexScavenging(const MachineFunction &MF) const;
+  bool requiresFrameIndexScavenging(const MachineFunction &MF) const override;
 
-  bool useFPForScavengingIndex(const MachineFunction &MF) const;
+  bool useFPForScavengingIndex(const MachineFunction &MF) const override;
 
   bool saveScavengerRegister(MachineBasicBlock &MBB,
                                      MachineBasicBlock::iterator I,
                                      MachineBasicBlock::iterator &UseMI,
                                      const TargetRegisterClass *RC,
-                                     unsigned Reg) const;
+                                     unsigned Reg) const override;
 
-  virtual const TargetRegisterClass *intRegClass(unsigned Size) const;
+  const TargetRegisterClass *intRegClass(unsigned Size) const override;
 
 private:
-  virtual void eliminateFI(MachineBasicBlock::iterator II, unsigned OpNo,
-                           int FrameIndex, uint64_t StackSize,
-                           int64_t SPOffset) const;
+  void eliminateFI(MachineBasicBlock::iterator II, unsigned OpNo,
+                   int FrameIndex, uint64_t StackSize,
+                   int64_t SPOffset) const override;
 };
 
 } // end namespace llvm
diff --git a/lib/Target/Mips/Mips64InstrInfo.td b/lib/Target/Mips/Mips64InstrInfo.td
index 81f805ae63..1303028c68 100644
--- a/lib/Target/Mips/Mips64InstrInfo.td
+++ b/lib/Target/Mips/Mips64InstrInfo.td
@@ -237,6 +237,20 @@ let isCodeGenOnly = 1, rs = 0, shamt = 0 in {
                     "sll\t$rd, $rt, 0", [], II_SLL>;
 }
 
+// We need the following two pseudo instructions to avoid offset calculation for
+// long branches.  See the comment in file MipsLongBranch.cpp for detailed
+// explanation.
+
+// Expands to: lui $dst, %highest($tgt - $baltgt)
+def LONG_BRANCH_LUi64 : PseudoSE<(outs GPR64Opnd:$dst),
+  (ins brtarget:$tgt, brtarget:$baltgt), []>;
+
+// Expands to: daddiu $dst, $src, %PART($tgt - $baltgt)
+// where %PART may be %higher, %hi or %lo, depending on the relocation kind
+// that $tgt is annotated with.
+def LONG_BRANCH_DADDiu : PseudoSE<(outs GPR64Opnd:$dst),
+  (ins GPR64Opnd:$src, brtarget:$tgt, brtarget:$baltgt), []>;
+
 // Cavium Octeon cmMIPS instructions
 let Predicates = [HasCnMips] in {
 
@@ -331,12 +345,10 @@ def VMULU : ArithLogicR<"vmulu", GPR64Opnd, 0, II_DMUL>,
 //===----------------------------------------------------------------------===//
 
 // extended loads
-let Predicates = [HasStdEnc] in {
-  def : MipsPat<(i64 (extloadi1  addr:$src)), (LB64 addr:$src)>;
-  def : MipsPat<(i64 (extloadi8  addr:$src)), (LB64 addr:$src)>;
-  def : MipsPat<(i64 (extloadi16 addr:$src)), (LH64 addr:$src)>;
-  def : MipsPat<(i64 (extloadi32 addr:$src)), (LW64 addr:$src)>;
-}
+def : MipsPat<(i64 (extloadi1  addr:$src)), (LB64 addr:$src)>;
+def : MipsPat<(i64 (extloadi8  addr:$src)), (LB64 addr:$src)>;
+def : MipsPat<(i64 (extloadi16 addr:$src)), (LH64 addr:$src)>;
+def : MipsPat<(i64 (extloadi32 addr:$src)), (LW64 addr:$src)>;
 
 // hi/lo relocs
 def : MipsPat<(MipsHi tglobaladdr:$in), (LUi64 tglobaladdr:$in)>;
@@ -428,6 +440,8 @@ def : InstAlias<"add $rs, $imm",
 def : InstAlias<"addu $rs, $imm",
                 (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rs, simm16:$imm),
                 0>;
+def : InstAlias<"dsll $rd, $rt, $rs",
+                (DSLLV GPR64Opnd:$rd, GPR64Opnd:$rt, GPR32Opnd:$rs), 0>;
 def : InstAlias<"dsubu $rt, $rs, $imm",
                 (DADDiu GPR64Opnd:$rt, GPR64Opnd:$rs,
                 InvertedImOperand64: $imm),0>;
@@ -437,6 +451,8 @@ def : InstAlias<"dsub $rs, $imm",
 def : InstAlias<"dsubu $rs, $imm",
                 (DADDiu GPR64Opnd:$rs, GPR64Opnd:$rs, InvertedImOperand64:$imm),
                 0>;
+def : InstAlias<"dsrl $rd, $rt, $rs",
+                (DSRLV GPR64Opnd:$rd, GPR64Opnd:$rt, GPR32Opnd:$rs), 0>;
 
 /// Move between CPU and coprocessor registers
 let DecoderNamespace = "Mips64", Predicates = [HasMips64] in {
diff --git a/lib/Target/Mips/MipsAsmPrinter.cpp b/lib/Target/Mips/MipsAsmPrinter.cpp
index 6d3a4f4a24..626657e9df 100644
--- a/lib/Target/Mips/MipsAsmPrinter.cpp
+++ b/lib/Target/Mips/MipsAsmPrinter.cpp
@@ -148,7 +148,8 @@ void MipsAsmPrinter::EmitInstruction(const MachineInstr *MI) {
     // removing another test for this situation downstream in the
     // callchain.
     //
-    if (I->isPseudo() && !Subtarget->inMips16Mode())
+    if (I->isPseudo() && !Subtarget->inMips16Mode()
+        && !isLongBranchPseudo(I->getOpcode()))
       llvm_unreachable("Pseudo opcode found in EmitInstruction()");
 
     MCInst TmpInst0;
@@ -954,6 +955,13 @@ void MipsAsmPrinter::NaClAlignIndirectJumpTargets(MachineFunction &MF) {
   }
 }
 
+bool MipsAsmPrinter::isLongBranchPseudo(int Opcode) const {
+  return (Opcode == Mips::LONG_BRANCH_LUi
+          || Opcode == Mips::LONG_BRANCH_ADDiu
+          || Opcode == Mips::LONG_BRANCH_LUi64
+          || Opcode == Mips::LONG_BRANCH_DADDiu);
+}
+
 // Force static initialization.
 extern "C" void LLVMInitializeMipsAsmPrinter() {
   RegisterAsmPrinter<MipsAsmPrinter> X(TheMipsTarget);
diff --git a/lib/Target/Mips/MipsAsmPrinter.h b/lib/Target/Mips/MipsAsmPrinter.h
index 4eb3eef94c..e82b145925 100644
--- a/lib/Target/Mips/MipsAsmPrinter.h
+++ b/lib/Target/Mips/MipsAsmPrinter.h
@@ -75,6 +75,8 @@ private:
 
   void NaClAlignIndirectJumpTargets(MachineFunction &MF);
 
+  bool isLongBranchPseudo(int Opcode) const;
+
 public:
 
   const MipsSubtarget *Subtarget;
@@ -87,13 +89,13 @@ public:
     Subtarget = &TM.getSubtarget<MipsSubtarget>();
   }
 
-  virtual const char *getPassName() const {
+  const char *getPassName() const override {
     return "Mips Assembly Printer";
   }
 
-  virtual bool runOnMachineFunction(MachineFunction &MF);
+  bool runOnMachineFunction(MachineFunction &MF) override;
 
-  virtual void EmitConstantPool() override {
+  void EmitConstantPool() override {
     bool UsingConstantPools =
       (Subtarget->inMips16Mode() && Subtarget->useConstantIslands());
     if (!UsingConstantPools)
@@ -101,21 +103,21 @@ public:
     // we emit constant pools customly!
   }
 
-  void EmitInstruction(const MachineInstr *MI);
+  void EmitInstruction(const MachineInstr *MI) override;
   void printSavedRegsBitmask();
   void emitFrameDirective();
   const char *getCurrentABIString() const;
-  virtual void EmitFunctionEntryLabel();
-  virtual void EmitFunctionBodyStart();
-  virtual void EmitFunctionBodyEnd();
-  virtual bool isBlockOnlyReachableByFallthrough(const MachineBasicBlock*
-                                                 MBB) const;
+  void EmitFunctionEntryLabel() override;
+  void EmitFunctionBodyStart() override;
+  void EmitFunctionBodyEnd() override;
+  bool isBlockOnlyReachableByFallthrough(
+                                   const MachineBasicBlock* MBB) const override;
   bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
                        unsigned AsmVariant, const char *ExtraCode,
-                       raw_ostream &O);
+                       raw_ostream &O) override;
   bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum,
                              unsigned AsmVariant, const char *ExtraCode,
-                             raw_ostream &O);
+                             raw_ostream &O) override;
   void printOperand(const MachineInstr *MI, int opNum, raw_ostream &O);
   void printUnsignedImm(const MachineInstr *MI, int opNum, raw_ostream &O);
   void printUnsignedImm8(const MachineInstr *MI, int opNum, raw_ostream &O);
@@ -123,8 +125,8 @@ public:
   void printMemOperandEA(const MachineInstr *MI, int opNum, raw_ostream &O);
   void printFCCOperand(const MachineInstr *MI, int opNum, raw_ostream &O,
                        const char *Modifier = nullptr);
-  void EmitStartOfAsmFile(Module &M);
-  void EmitEndOfAsmFile(Module &M);
+  void EmitStartOfAsmFile(Module &M) override;
+  void EmitEndOfAsmFile(Module &M) override;
   void PrintDebugValueComment(const MachineInstr *MI, raw_ostream &OS);
 };
 }
diff --git a/lib/Target/Mips/MipsCodeEmitter.cpp b/lib/Target/Mips/MipsCodeEmitter.cpp
index de9c5353a2..58a6be5d45 100644
--- a/lib/Target/Mips/MipsCodeEmitter.cpp
+++ b/lib/Target/Mips/MipsCodeEmitter.cpp
@@ -57,7 +57,7 @@ class MipsCodeEmitter : public MachineFunctionPass {
   const std::vector<MachineJumpTableEntry> *MJTEs;
   bool IsPIC;
 
-  void getAnalysisUsage(AnalysisUsage &AU) const {
+  void getAnalysisUsage(AnalysisUsage &AU) const override {
     AU.addRequired<MachineModuleInfo> ();
     MachineFunctionPass::getAnalysisUsage(AU);
   }
@@ -70,9 +70,9 @@ public:
       TM(tm), MCE(mce), MCPEs(nullptr), MJTEs(nullptr),
       IsPIC(TM.getRelocationModel() == Reloc::PIC_) {}
 
-  bool runOnMachineFunction(MachineFunction &MF);
+  bool runOnMachineFunction(MachineFunction &MF) override;
 
-  virtual const char *getPassName() const {
+  const char *getPassName() const override {
     return "Mips Machine Code Emitter";
   }
 
diff --git a/lib/Target/Mips/MipsCondMov.td b/lib/Target/Mips/MipsCondMov.td
index eab940e5e9..73dcecef79 100644
--- a/lib/Target/Mips/MipsCondMov.td
+++ b/lib/Target/Mips/MipsCondMov.td
@@ -106,7 +106,7 @@ multiclass MovnPats<RegisterClass CRC, RegisterClass DRC, Instruction MOVNInst,
 def MOVZ_I_I : MMRel, CMov_I_I_FT<"movz", GPR32Opnd, GPR32Opnd, II_MOVZ>,
                ADD_FM<0, 0xa>;
 
-let Predicates = [HasStdEnc], isCodeGenOnly = 1 in {
+let isCodeGenOnly = 1 in {
   def MOVZ_I_I64   : CMov_I_I_FT<"movz", GPR32Opnd, GPR64Opnd, II_MOVZ>,
                      ADD_FM<0, 0xa>;
   def MOVZ_I64_I   : CMov_I_I_FT<"movz", GPR64Opnd, GPR32Opnd, II_MOVZ>,
@@ -118,7 +118,7 @@ let Predicates = [HasStdEnc], isCodeGenOnly = 1 in {
 def MOVN_I_I       : MMRel, CMov_I_I_FT<"movn", GPR32Opnd, GPR32Opnd, II_MOVN>,
                      ADD_FM<0, 0xb>;
 
-let Predicates = [HasStdEnc], isCodeGenOnly = 1 in {
+let isCodeGenOnly = 1 in {
   def MOVN_I_I64   : CMov_I_I_FT<"movn", GPR32Opnd, GPR64Opnd, II_MOVN>,
                      ADD_FM<0, 0xb>;
   def MOVN_I64_I   : CMov_I_I_FT<"movn", GPR64Opnd, GPR32Opnd, II_MOVN>,
diff --git a/lib/Target/Mips/MipsConstantIslandPass.cpp b/lib/Target/Mips/MipsConstantIslandPass.cpp
index 34f68f1859..a37062f3b2 100644
--- a/lib/Target/Mips/MipsConstantIslandPass.cpp
+++ b/lib/Target/Mips/MipsConstantIslandPass.cpp
@@ -371,11 +371,11 @@ namespace {
         STI(&TM.getSubtarget<MipsSubtarget>()), MF(nullptr), MCP(nullptr),
         PrescannedForConstants(false){}
 
-    virtual const char *getPassName() const {
+    const char *getPassName() const override {
       return "Mips Constant Islands";
     }
 
-    bool runOnMachineFunction(MachineFunction &F);
+    bool runOnMachineFunction(MachineFunction &F) override;
 
     void doInitialPlacement(std::vector<MachineInstr*> &CPEMIs);
     CPEntry *findConstPoolEntry(unsigned CPI, const MachineInstr *CPEMI);
diff --git a/lib/Target/Mips/MipsDelaySlotFiller.cpp b/lib/Target/Mips/MipsDelaySlotFiller.cpp
index 4549873b23..d6c7cac273 100644
--- a/lib/Target/Mips/MipsDelaySlotFiller.cpp
+++ b/lib/Target/Mips/MipsDelaySlotFiller.cpp
@@ -124,7 +124,7 @@ namespace {
   public:
     NoMemInstr() : InspectMemInstr(true) {}
   private:
-    virtual bool hasHazard_(const MachineInstr &MI) { return true; }
+    bool hasHazard_(const MachineInstr &MI) override { return true; }
   };
 
   /// This subclass accepts loads from stacks and constant loads.
@@ -132,7 +132,7 @@ namespace {
   public:
     LoadFromStackOrConst() : InspectMemInstr(false) {}
   private:
-    virtual bool hasHazard_(const MachineInstr &MI);
+    bool hasHazard_(const MachineInstr &MI) override;
   };
 
   /// This subclass uses memory dependence information to determine whether a
@@ -144,7 +144,7 @@ namespace {
   private:
     typedef PointerUnion<const Value *, const PseudoSourceValue *> ValueType;
 
-    virtual bool hasHazard_(const MachineInstr &MI);
+    bool hasHazard_(const MachineInstr &MI) override;
 
     /// Update Defs and Uses. Return true if there exist dependences that
     /// disqualify the delay slot candidate between V and values in Uses and
@@ -168,11 +168,11 @@ namespace {
     Filler(TargetMachine &tm)
       : MachineFunctionPass(ID), TM(tm) { }
 
-    virtual const char *getPassName() const {
+    const char *getPassName() const override {
       return "Mips Delay Slot Filler";
     }
 
-    bool runOnMachineFunction(MachineFunction &F) {
+    bool runOnMachineFunction(MachineFunction &F) override {
       bool Changed = false;
       for (MachineFunction::iterator FI = F.begin(), FE = F.end();
            FI != FE; ++FI)
@@ -180,7 +180,7 @@ namespace {
       return Changed;
     }
 
-    void getAnalysisUsage(AnalysisUsage &AU) const {
+    void getAnalysisUsage(AnalysisUsage &AU) const override {
       AU.addRequired<MachineBranchProbabilityInfo>();
       MachineFunctionPass::getAnalysisUsage(AU);
     }
diff --git a/lib/Target/Mips/MipsFastISel.cpp b/lib/Target/Mips/MipsFastISel.cpp
index 70579bd270..c85be1e553 100644
--- a/lib/Target/Mips/MipsFastISel.cpp
+++ b/lib/Target/Mips/MipsFastISel.cpp
@@ -3,8 +3,13 @@
 
 #include "llvm/CodeGen/FunctionLoweringInfo.h"
 #include "llvm/CodeGen/FastISel.h"
+
+#include "llvm/CodeGen/MachineInstrBuilder.h"
+#include "llvm/Target/TargetInstrInfo.h"
 #include "llvm/Target/TargetLibraryInfo.h"
 #include "MipsISelLowering.h"
+#include "MipsMachineFunction.h"
+#include "MipsSubtarget.h"
 
 using namespace llvm;
 
@@ -12,12 +17,63 @@ namespace {
 
 class MipsFastISel final : public FastISel {
 
+  /// Subtarget - Keep a pointer to the MipsSubtarget around so that we can
+  /// make the right decision when generating code for different targets.
+  const MipsSubtarget *Subtarget;
+  Module &M;
+  const TargetMachine &TM;
+  const TargetInstrInfo &TII;
+  const TargetLowering &TLI;
+  MipsFunctionInfo *MFI;
+
+  // Convenience variables to avoid some queries.
+  LLVMContext *Context;
+
+  bool TargetSupported;
+
 public:
   explicit MipsFastISel(FunctionLoweringInfo &funcInfo,
                         const TargetLibraryInfo *libInfo)
-      : FastISel(funcInfo, libInfo) {}
-  bool TargetSelectInstruction(const Instruction *I) override { return false; }
+      : FastISel(funcInfo, libInfo),
+        M(const_cast<Module &>(*funcInfo.Fn->getParent())),
+        TM(funcInfo.MF->getTarget()), TII(*TM.getInstrInfo()),
+        TLI(*TM.getTargetLowering()) {
+    Subtarget = &TM.getSubtarget<MipsSubtarget>();
+    MFI = funcInfo.MF->getInfo<MipsFunctionInfo>();
+    Context = &funcInfo.Fn->getContext();
+    TargetSupported = ((Subtarget->getRelocationModel() == Reloc::PIC_) &&
+                       (Subtarget->hasMips32r2() && (Subtarget->isABI_O32())));
+  }
+
+  bool TargetSelectInstruction(const Instruction *I) override;
+
+  bool SelectRet(const Instruction *I);
 };
+
+bool MipsFastISel::SelectRet(const Instruction *I) {
+  const ReturnInst *Ret = cast<ReturnInst>(I);
+
+  if (!FuncInfo.CanLowerReturn)
+    return false;
+  if (Ret->getNumOperands() > 0) {
+    return false;
+  }
+  unsigned RetOpc = Mips::RetRA;
+  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(RetOpc));
+  return true;
+}
+
+bool MipsFastISel::TargetSelectInstruction(const Instruction *I) {
+  if (!TargetSupported)
+    return false;
+  switch (I->getOpcode()) {
+  default:
+    break;
+  case Instruction::Ret:
+    return SelectRet(I);
+  }
+  return false;
+}
 }
 
 namespace llvm {
diff --git a/lib/Target/Mips/MipsFrameLowering.h b/lib/Target/Mips/MipsFrameLowering.h
index 6a5f79d0df..e10a3a551f 100644
--- a/lib/Target/Mips/MipsFrameLowering.h
+++ b/lib/Target/Mips/MipsFrameLowering.h
@@ -32,7 +32,7 @@ public:
   static const MipsFrameLowering *create(MipsTargetMachine &TM,
                                          const MipsSubtarget &ST);
 
-  bool hasFP(const MachineFunction &MF) const;
+  bool hasFP(const MachineFunction &MF) const override;
 
 protected:
   uint64_t estimateStackSize(const MachineFunction &MF) const;
diff --git a/lib/Target/Mips/MipsISelDAGToDAG.h b/lib/Target/Mips/MipsISelDAGToDAG.h
index 4546182a24..13becb6b5b 100644
--- a/lib/Target/Mips/MipsISelDAGToDAG.h
+++ b/lib/Target/Mips/MipsISelDAGToDAG.h
@@ -35,11 +35,11 @@ public:
     : SelectionDAGISel(TM), Subtarget(TM.getSubtarget<MipsSubtarget>()) {}
 
   // Pass Name
-  virtual const char *getPassName() const {
+  const char *getPassName() const override {
     return "MIPS DAG->DAG Pattern Instruction Selection";
   }
 
-  virtual bool runOnMachineFunction(MachineFunction &MF);
+  bool runOnMachineFunction(MachineFunction &MF) override;
 
 protected:
   SDNode *getGlobalBaseReg();
@@ -110,7 +110,7 @@ private:
   /// starting at bit zero.
   virtual bool selectVSplatMaskR(SDValue N, SDValue &Imm) const;
 
-  virtual SDNode *Select(SDNode *N);
+  SDNode *Select(SDNode *N) override;
 
   virtual std::pair<bool, SDNode*> selectNode(SDNode *Node) = 0;
 
@@ -121,9 +121,9 @@ private:
 
   virtual void processFunctionAfterISel(MachineFunction &MF) = 0;
 
-  virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
-                                            char ConstraintCode,
-                                            std::vector<SDValue> &OutOps);
+  bool SelectInlineAsmMemoryOperand(const SDValue &Op,
+                                    char ConstraintCode,
+                                    std::vector<SDValue> &OutOps) override;
 };
 
 /// createMipsISelDag - This pass converts a legalized DAG into a
diff --git a/lib/Target/Mips/MipsISelLowering.h b/lib/Target/Mips/MipsISelLowering.h
index a12c9a7b43..4ac33bf114 100644
--- a/lib/Target/Mips/MipsISelLowering.h
+++ b/lib/Target/Mips/MipsISelLowering.h
@@ -223,32 +223,33 @@ namespace llvm {
     FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
                              const TargetLibraryInfo *libInfo) const override;
 
-    virtual MVT getScalarShiftAmountTy(EVT LHSTy) const { return MVT::i32; }
+    MVT getScalarShiftAmountTy(EVT LHSTy) const override { return MVT::i32; }
 
-    virtual void LowerOperationWrapper(SDNode *N,
-                                       SmallVectorImpl<SDValue> &Results,
-                                       SelectionDAG &DAG) const;
+    void LowerOperationWrapper(SDNode *N,
+                               SmallVectorImpl<SDValue> &Results,
+                               SelectionDAG &DAG) const override;
 
     /// LowerOperation - Provide custom lowering hooks for some operations.
-    virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
+    SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
 
     /// ReplaceNodeResults - Replace the results of node with an illegal result
     /// type with new values built out of custom code.
     ///
-    virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
-                                    SelectionDAG &DAG) const;
+    void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
+                            SelectionDAG &DAG) const override;
 
     /// getTargetNodeName - This method returns the name of a target specific
     //  DAG node.
-    virtual const char *getTargetNodeName(unsigned Opcode) const;
+    const char *getTargetNodeName(unsigned Opcode) const override;
 
     /// getSetCCResultType - get the ISD::SETCC result ValueType
-    EVT getSetCCResultType(LLVMContext &Context, EVT VT) const;
+    EVT getSetCCResultType(LLVMContext &Context, EVT VT) const override;
 
-    virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
+    SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
 
-    virtual MachineBasicBlock *
-    EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const;
+    MachineBasicBlock *
+    EmitInstrWithCustomInserter(MachineInstr *MI,
+                                MachineBasicBlock *MBB) const override;
 
     struct LTStr {
       bool operator()(const char *S1, const char *S2) const {
@@ -528,41 +529,39 @@ namespace llvm {
     void writeVarArgRegs(std::vector<SDValue> &OutChains, const MipsCC &CC,
                          SDValue Chain, SDLoc DL, SelectionDAG &DAG) const;
 
-    virtual SDValue
+    SDValue
       LowerFormalArguments(SDValue Chain,
                            CallingConv::ID CallConv, bool isVarArg,
                            const SmallVectorImpl<ISD::InputArg> &Ins,
                            SDLoc dl, SelectionDAG &DAG,
-                           SmallVectorImpl<SDValue> &InVals) const;
+                           SmallVectorImpl<SDValue> &InVals) const override;
 
     SDValue passArgOnStack(SDValue StackPtr, unsigned Offset, SDValue Chain,
                            SDValue Arg, SDLoc DL, bool IsTailCall,
                            SelectionDAG &DAG) const;
 
-    virtual SDValue
-      LowerCall(TargetLowering::CallLoweringInfo &CLI,
-                SmallVectorImpl<SDValue> &InVals) const;
+    SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI,
+                      SmallVectorImpl<SDValue> &InVals) const override;
 
-    virtual bool
-      CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
-                     bool isVarArg,
-                     const SmallVectorImpl<ISD::OutputArg> &Outs,
-                     LLVMContext &Context) const;
-
-    virtual SDValue
-      LowerReturn(SDValue Chain,
-                  CallingConv::ID CallConv, bool isVarArg,
-                  const SmallVectorImpl<ISD::OutputArg> &Outs,
-                  const SmallVectorImpl<SDValue> &OutVals,
-                  SDLoc dl, SelectionDAG &DAG) const;
+    bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
+                        bool isVarArg,
+                        const SmallVectorImpl<ISD::OutputArg> &Outs,
+                        LLVMContext &Context) const override;
+
+    SDValue LowerReturn(SDValue Chain,
+                        CallingConv::ID CallConv, bool isVarArg,
+                        const SmallVectorImpl<ISD::OutputArg> &Outs,
+                        const SmallVectorImpl<SDValue> &OutVals,
+                        SDLoc dl, SelectionDAG &DAG) const override;
 
     // Inline asm support
-    ConstraintType getConstraintType(const std::string &Constraint) const;
+    ConstraintType
+      getConstraintType(const std::string &Constraint) const override;
 
     /// Examine constraint string and operand type and determine a weight value.
     /// The operand object must already have been set up with the operand type.
     ConstraintWeight getSingleConstraintMatchWeight(
-      AsmOperandInfo &info, const char *constraint) const;
+      AsmOperandInfo &info, const char *constraint) const override;
 
     /// This function parses registers that appear in inline-asm constraints.
     /// It returns pair (0, 0) on failure.
@@ -571,33 +570,33 @@ namespace llvm {
 
     std::pair<unsigned, const TargetRegisterClass*>
               getRegForInlineAsmConstraint(const std::string &Constraint,
-                                           MVT VT) const;
+                                           MVT VT) const override;
 
     /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
     /// vector.  If it is invalid, don't add anything to Ops. If hasMemory is
     /// true it means one of the asm constraint of the inline asm instruction
     /// being processed is 'm'.
-    virtual void LowerAsmOperandForConstraint(SDValue Op,
-                                              std::string &Constraint,
-                                              std::vector<SDValue> &Ops,
-                                              SelectionDAG &DAG) const;
+    void LowerAsmOperandForConstraint(SDValue Op,
+                                      std::string &Constraint,
+                                      std::vector<SDValue> &Ops,
+                                      SelectionDAG &DAG) const override;
 
-    virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const;
+    bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const override;
 
-    virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
+    bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
 
-    virtual EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
-                                    unsigned SrcAlign,
-                                    bool IsMemset, bool ZeroMemset,
-                                    bool MemcpyStrSrc,
-                                    MachineFunction &MF) const;
+    EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
+                            unsigned SrcAlign,
+                            bool IsMemset, bool ZeroMemset,
+                            bool MemcpyStrSrc,
+                            MachineFunction &MF) const override;
 
     /// isFPImmLegal - Returns true if the target can instruction select the
     /// specified FP immediate natively. If false, the legalizer will
     /// materialize the FP immediate as a load from a constant pool.
-    virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
+    bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
 
-    virtual unsigned getJumpTableEncoding() const;
+    unsigned getJumpTableEncoding() const override;
 
     MachineBasicBlock *emitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
                     unsigned Size, unsigned BinOpcode, bool Nand = false) const;
diff --git a/lib/Target/Mips/MipsInstrFPU.td b/lib/Target/Mips/MipsInstrFPU.td
index 85fb16ef2c..b7db4883c2 100644
--- a/lib/Target/Mips/MipsInstrFPU.td
+++ b/lib/Target/Mips/MipsInstrFPU.td
@@ -364,10 +364,8 @@ def FMOV_D64 : ABSS_FT<"mov.d", FGR64Opnd, FGR64Opnd, II_MOV_D>,
 }
 
 /// Floating Point Memory Instructions
-let Predicates = [HasStdEnc] in {
-  def LWC1 : MMRel, LW_FT<"lwc1", FGR32Opnd, II_LWC1, load>, LW_FM<0x31>;
-  def SWC1 : MMRel, SW_FT<"swc1", FGR32Opnd, II_SWC1, store>, LW_FM<0x39>;
-}
+def LWC1 : MMRel, LW_FT<"lwc1", FGR32Opnd, II_LWC1, load>, LW_FM<0x31>;
+def SWC1 : MMRel, SW_FT<"swc1", FGR32Opnd, II_SWC1, store>, LW_FM<0x39>;
 
 let Predicates = [IsFP64bit, HasStdEnc], DecoderNamespace = "Mips64" in {
   def LDC164 : LW_FT<"ldc1", FGR64Opnd, II_LDC1, load>, LW_FM<0x35>;
@@ -380,12 +378,10 @@ let Predicates = [NotFP64bit, HasStdEnc] in {
 }
 
 /// Cop2 Memory Instructions
-let Predicates = [HasStdEnc] in {
-  def LWC2 : LW_FT<"lwc2", COP2Opnd, NoItinerary, load>, LW_FM<0x32>;
-  def SWC2 : SW_FT<"swc2", COP2Opnd, NoItinerary, store>, LW_FM<0x3a>;
-  def LDC2 : LW_FT<"ldc2", COP2Opnd, NoItinerary, load>, LW_FM<0x36>;
-  def SDC2 : SW_FT<"sdc2", COP2Opnd, NoItinerary, store>, LW_FM<0x3e>;
-}
+def LWC2 : LW_FT<"lwc2", COP2Opnd, NoItinerary, load>, LW_FM<0x32>;
+def SWC2 : SW_FT<"swc2", COP2Opnd, NoItinerary, store>, LW_FM<0x3a>;
+def LDC2 : LW_FT<"ldc2", COP2Opnd, NoItinerary, load>, LW_FM<0x36>;
+def SDC2 : SW_FT<"sdc2", COP2Opnd, NoItinerary, store>, LW_FM<0x3e>;
 
 // Indexed loads and stores.
 // Base register + offset register addressing mode (indicated by "x" in the
@@ -600,10 +596,8 @@ let Predicates = [IsFP64bit, HasStdEnc] in {
 
 // Patterns for loads/stores with a reg+imm operand.
 let AddedComplexity = 40 in {
-  let Predicates = [HasStdEnc] in {
-    def : LoadRegImmPat<LWC1, f32, load>;
-    def : StoreRegImmPat<SWC1, f32>;
-  }
+  def : LoadRegImmPat<LWC1, f32, load>;
+  def : StoreRegImmPat<SWC1, f32>;
 
   let Predicates = [IsFP64bit, HasStdEnc] in {
     def : LoadRegImmPat<LDC164, f64, load>;
diff --git a/lib/Target/Mips/MipsInstrInfo.h b/lib/Target/Mips/MipsInstrInfo.h
index d9ac961cd3..742193f712 100644
--- a/lib/Target/Mips/MipsInstrInfo.h
+++ b/lib/Target/Mips/MipsInstrInfo.h
@@ -9,6 +9,10 @@
 //
 // This file contains the Mips implementation of the TargetInstrInfo class.
 //
+// FIXME: We need to override TargetInstrInfo::getInlineAsmLength method in
+// order for MipsLongBranch pass to work correctly when the code has inline
+// assembly.  The returned value doesn't have to be the asm instruction's exact
+// size in bytes; MipsLongBranch only expects it to be the correct upper bound.
 //===----------------------------------------------------------------------===//
 
 #ifndef MIPSINSTRUCTIONINFO_H
@@ -47,20 +51,20 @@ public:
   static const MipsInstrInfo *create(MipsTargetMachine &TM);
 
   /// Branch Analysis
-  virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
-                             MachineBasicBlock *&FBB,
-                             SmallVectorImpl<MachineOperand> &Cond,
-                             bool AllowModify) const;
+  bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
+                     MachineBasicBlock *&FBB,
+                     SmallVectorImpl<MachineOperand> &Cond,
+                     bool AllowModify) const override;
 
-  virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
+  unsigned RemoveBranch(MachineBasicBlock &MBB) const override;
 
-  virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
-                                MachineBasicBlock *FBB,
-                                const SmallVectorImpl<MachineOperand> &Cond,
-                                DebugLoc DL) const;
+  unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
+                        MachineBasicBlock *FBB,
+                        const SmallVectorImpl<MachineOperand> &Cond,
+                        DebugLoc DL) const override;
 
-  virtual
-  bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
+  bool
+  ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
 
   BranchType AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
                            MachineBasicBlock *&FBB,
@@ -69,8 +73,8 @@ public:
                            SmallVectorImpl<MachineInstr*> &BranchInstrs) const;
 
   /// Insert nop instruction when hazard condition is found
-  virtual void insertNoop(MachineBasicBlock &MBB,
-                          MachineBasicBlock::iterator MI) const;
+  void insertNoop(MachineBasicBlock &MBB,
+                  MachineBasicBlock::iterator MI) const override;
 
   /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info.  As
   /// such, whenever a client has an instance of instruction info, it should
@@ -83,19 +87,19 @@ public:
   /// Return the number of bytes of code the specified instruction may be.
   unsigned GetInstSizeInBytes(const MachineInstr *MI) const;
 
-  virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
-                                   MachineBasicBlock::iterator MBBI,
-                                   unsigned SrcReg, bool isKill, int FrameIndex,
-                                   const TargetRegisterClass *RC,
-                                   const TargetRegisterInfo *TRI) const {
+  void storeRegToStackSlot(MachineBasicBlock &MBB,
+                           MachineBasicBlock::iterator MBBI,
+                           unsigned SrcReg, bool isKill, int FrameIndex,
+                           const TargetRegisterClass *RC,
+                           const TargetRegisterInfo *TRI) const override {
     storeRegToStack(MBB, MBBI, SrcReg, isKill, FrameIndex, RC, TRI, 0);
   }
 
-  virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
-                                    MachineBasicBlock::iterator MBBI,
-                                    unsigned DestReg, int FrameIndex,
-                                    const TargetRegisterClass *RC,
-                                    const TargetRegisterInfo *TRI) const {
+  void loadRegFromStackSlot(MachineBasicBlock &MBB,
+                            MachineBasicBlock::iterator MBBI,
+                            unsigned DestReg, int FrameIndex,
+                            const TargetRegisterClass *RC,
+                            const TargetRegisterInfo *TRI) const override {
     loadRegFromStack(MBB, MBBI, DestReg, FrameIndex, RC, TRI, 0);
   }
 
diff --git a/lib/Target/Mips/MipsInstrInfo.td b/lib/Target/Mips/MipsInstrInfo.td
index acc1946a4c..62cb7c3359 100644
--- a/lib/Target/Mips/MipsInstrInfo.td
+++ b/lib/Target/Mips/MipsInstrInfo.td
@@ -928,6 +928,18 @@ let isPseudo = 1, isCodeGenOnly = 1 in {
   def STORE_ACC64 : Store<"", ACC64>;
 }
 
+// We need these two pseudo instructions to avoid offset calculation for long
+// branches.  See the comment in file MipsLongBranch.cpp for detailed
+// explanation.
+
+// Expands to: lui $dst, %hi($tgt - $baltgt)
+def LONG_BRANCH_LUi : PseudoSE<(outs GPR32Opnd:$dst),
+  (ins brtarget:$tgt, brtarget:$baltgt), []>;
+
+// Expands to: addiu $dst, $src, %lo($tgt - $baltgt)
+def LONG_BRANCH_ADDiu : PseudoSE<(outs GPR32Opnd:$dst),
+  (ins GPR32Opnd:$src, brtarget:$tgt, brtarget:$baltgt), []>;
+
 //===----------------------------------------------------------------------===//
 // Instruction definition
 //===----------------------------------------------------------------------===//
@@ -1207,6 +1219,8 @@ def : InstAlias<"negu $rt, $rs",
                 (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>;
 def : InstAlias<"slt $rs, $rt, $imm",
                 (SLTi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
+def : InstAlias<"sltu $rt, $rs, $imm",
+                (SLTiu GPR32Opnd:$rt, GPR32Opnd:$rs, simm16:$imm), 0>;
 def : InstAlias<"xor $rs, $rt, $imm",
                 (XORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>;
 def : InstAlias<"or $rs, $rt, $imm",
@@ -1234,6 +1248,8 @@ def  : InstAlias<"tgeu $rs, $rt", (TGEU GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
 def  : InstAlias<"tlt $rs, $rt", (TLT GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
 def  : InstAlias<"tltu $rs, $rt", (TLTU GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
 def  : InstAlias<"tne $rs, $rt", (TNE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
+def  : InstAlias<"sll $rd, $rt, $rs",
+                 (SLLV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
 def : InstAlias<"sub, $rd, $rs, $imm",
                 (ADDi GPR32Opnd:$rd, GPR32Opnd:$rs, InvertedImOperand:$imm)>;
 def : InstAlias<"sub $rs, $imm",
@@ -1244,6 +1260,8 @@ def : InstAlias<"subu, $rd, $rs, $imm",
 def : InstAlias<"subu $rs, $imm",
                 (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rs, InvertedImOperand:$imm),
                 0>;
+def  : InstAlias<"srl $rd, $rt, $rs",
+                 (SRLV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
 //===----------------------------------------------------------------------===//
 // Assembler Pseudo Instructions
 //===----------------------------------------------------------------------===//
@@ -1358,14 +1376,11 @@ def : MipsPat<(not GPR32:$in),
               (NOR GPR32Opnd:$in, ZERO)>;
 
 // extended loads
-let Predicates = [HasStdEnc] in {
-  def : MipsPat<(i32 (extloadi1  addr:$src)), (LBu addr:$src)>;
-  def : MipsPat<(i32 (extloadi8  addr:$src)), (LBu addr:$src)>;
-  def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu addr:$src)>;
-}
+def : MipsPat<(i32 (extloadi1  addr:$src)), (LBu addr:$src)>;
+def : MipsPat<(i32 (extloadi8  addr:$src)), (LBu addr:$src)>;
+def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu addr:$src)>;
 
 // peepholes
-let Predicates = [HasStdEnc] in
 def : MipsPat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>;
 
 // brcond patterns
@@ -1459,11 +1474,9 @@ def : MipsPat<(bswap GPR32:$rt), (ROTR (WSBH GPR32:$rt), 16)>;
 
 // Load halfword/word patterns.
 let AddedComplexity = 40 in {
-  let Predicates = [HasStdEnc] in {
-    def : LoadRegImmPat<LBu, i32, zextloadi8>;
-    def : LoadRegImmPat<LH, i32, sextloadi16>;
-    def : LoadRegImmPat<LW, i32, load>;
-  }
+  def : LoadRegImmPat<LBu, i32, zextloadi8>;
+  def : LoadRegImmPat<LH, i32, sextloadi16>;
+  def : LoadRegImmPat<LW, i32, load>;
 }
 
 //===----------------------------------------------------------------------===//
diff --git a/lib/Target/Mips/MipsJITInfo.h b/lib/Target/Mips/MipsJITInfo.h
index ecda3101a0..c9dfd831d2 100644
--- a/lib/Target/Mips/MipsJITInfo.h
+++ b/lib/Target/Mips/MipsJITInfo.h
@@ -37,26 +37,26 @@ class MipsJITInfo : public TargetJITInfo {
     /// overwriting OLD with a branch to NEW.  This is used for self-modifying
     /// code.
     ///
-    virtual void replaceMachineCodeForFunction(void *Old, void *New);
+    void replaceMachineCodeForFunction(void *Old, void *New) override;
 
     // getStubLayout - Returns the size and alignment of the largest call stub
     // on Mips.
-    virtual StubLayout getStubLayout();
+    StubLayout getStubLayout() override;
 
     /// emitFunctionStub - Use the specified JITCodeEmitter object to emit a
     /// small native function that simply calls the function at the specified
     /// address.
-    virtual void *emitFunctionStub(const Function *F, void *Fn,
-                                   JITCodeEmitter &JCE);
+    void *emitFunctionStub(const Function *F, void *Fn,
+                           JITCodeEmitter &JCE) override;
 
     /// getLazyResolverFunction - Expose the lazy resolver to the JIT.
-    virtual LazyResolverFn getLazyResolverFunction(JITCompilerFn);
+    LazyResolverFn getLazyResolverFunction(JITCompilerFn) override;
 
     /// relocate - Before the JIT can run a block of code that has been emitted,
     /// it must rewrite the code to contain the actual addresses of any
     /// referenced global symbols.
-    virtual void relocate(void *Function, MachineRelocation *MR,
-                          unsigned NumRelocs, unsigned char *GOTBase);
+    void relocate(void *Function, MachineRelocation *MR,
+                  unsigned NumRelocs, unsigned char *GOTBase) override;
 
     /// Initialize - Initialize internal stage for the function being JITted.
     void Initialize(const MachineFunction &MF, bool isPIC,
diff --git a/lib/Target/Mips/MipsLongBranch.cpp b/lib/Target/Mips/MipsLongBranch.cpp
index e9514c3b20..a8fd39176e 100644
--- a/lib/Target/Mips/MipsLongBranch.cpp
+++ b/lib/Target/Mips/MipsLongBranch.cpp
@@ -10,10 +10,7 @@
 // This pass expands a branch or jump instruction into a long branch if its
 // offset is too large to fit into its immediate field.
 //
-// FIXME:
-// 1. Fix pc-region jump instructions which cross 256MB segment boundaries.
-// 2. If program has inline assembly statements whose size cannot be
-//    determined accurately, load branch target addresses from the GOT.
+// FIXME: Fix pc-region jump instructions which cross 256MB segment boundaries.
 //===----------------------------------------------------------------------===//
 
 #include "Mips.h"
@@ -69,11 +66,11 @@ namespace {
         ABI(TM.getSubtarget<MipsSubtarget>().getTargetABI()),
         LongBranchSeqSize(!IsPIC ? 2 : (ABI == MipsSubtarget::N64 ? 13 : 9)) {}
 
-    virtual const char *getPassName() const {
+    const char *getPassName() const override {
       return "Mips Long Branch";
     }
 
-    bool runOnMachineFunction(MachineFunction &F);
+    bool runOnMachineFunction(MachineFunction &F) override;
 
   private:
     void splitMBB(MachineBasicBlock *MBB);
@@ -267,20 +264,14 @@ void MipsLongBranch::expandToLongBranch(MBBInfo &I) {
     LongBrMBB->addSuccessor(BalTgtMBB);
     BalTgtMBB->addSuccessor(TgtMBB);
 
-    int64_t TgtAddress = MBBInfos[TgtMBB->getNumber()].Address;
-    unsigned BalTgtMBBSize = 5;
-    int64_t Offset = TgtAddress - (I.Address + I.Size - BalTgtMBBSize * 4);
-    int64_t Lo = SignExtend64<16>(Offset & 0xffff);
-    int64_t Hi = SignExtend64<16>(((Offset + 0x8000) >> 16) & 0xffff);
-
     if (ABI != MipsSubtarget::N64) {
       // $longbr:
       //  addiu $sp, $sp, -8
       //  sw $ra, 0($sp)
-      //  bal $baltgt
       //  lui $at, %hi($tgt - $baltgt)
-      // $baltgt:
+      //  bal $baltgt
       //  addiu $at, $at, %lo($tgt - $baltgt)
+      // $baltgt:
       //  addu $at, $ra, $at
       //  lw $ra, 0($sp)
       //  jr $at
@@ -295,14 +286,31 @@ void MipsLongBranch::expandToLongBranch(MBBInfo &I) {
       BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::SW)).addReg(Mips::RA)
         .addReg(Mips::SP).addImm(0);
 
+      // LUi and ADDiu instructions create 32-bit offset of the target basic
+      // block from the target of BAL instruction.  We cannot use immediate
+      // value for this offset because it cannot be determined accurately when
+      // the program has inline assembly statements.  We therefore use the
+      // relocation expressions %hi($tgt-$baltgt) and %lo($tgt-$baltgt) which
+      // are resolved during the fixup, so the values will always be correct.
+      //
+      // Since we cannot create %hi($tgt-$baltgt) and %lo($tgt-$baltgt)
+      // expressions at this point (it is possible only at the MC layer),
+      // we replace LUi and ADDiu with pseudo instructions
+      // LONG_BRANCH_LUi and LONG_BRANCH_ADDiu, and add both basic
+      // blocks as operands to these instructions.  When lowering these pseudo
+      // instructions to LUi and ADDiu in the MC layer, we will create
+      // %hi($tgt-$baltgt) and %lo($tgt-$baltgt) expressions and add them as
+      // operands to lowered instructions.
+
+      BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::LONG_BRANCH_LUi), Mips::AT)
+        .addMBB(TgtMBB).addMBB(BalTgtMBB);
       MIBundleBuilder(*LongBrMBB, Pos)
         .append(BuildMI(*MF, DL, TII->get(Mips::BAL_BR)).addMBB(BalTgtMBB))
-        .append(BuildMI(*MF, DL, TII->get(Mips::LUi), Mips::AT).addImm(Hi));
+        .append(BuildMI(*MF, DL, TII->get(Mips::LONG_BRANCH_ADDiu), Mips::AT)
+                  .addReg(Mips::AT).addMBB(TgtMBB).addMBB(BalTgtMBB));
 
       Pos = BalTgtMBB->begin();
 
-      BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::ADDiu), Mips::AT)
-        .addReg(Mips::AT).addImm(Lo);
       BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::ADDu), Mips::AT)
         .addReg(Mips::RA).addReg(Mips::AT);
       BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::LW), Mips::RA)
@@ -320,10 +328,10 @@ void MipsLongBranch::expandToLongBranch(MBBInfo &I) {
       //  daddiu $at, $at, %higher($tgt - $baltgt)
       //  dsll $at, $at, 16
       //  daddiu $at, $at, %hi($tgt - $baltgt)
-      //  bal $baltgt
       //  dsll $at, $at, 16
-      // $baltgt:
+      //  bal $baltgt
       //  daddiu $at, $at, %lo($tgt - $baltgt)
+      // $baltgt:
       //  daddu $at, $ra, $at
       //  ld $ra, 0($sp)
       //  jr64 $at
@@ -331,9 +339,10 @@ void MipsLongBranch::expandToLongBranch(MBBInfo &I) {
       // $fallthrough:
       //
 
-      int64_t Higher = SignExtend64<16>(((Offset + 0x80008000) >> 32) & 0xffff);
-      int64_t Highest =
-        SignExtend64<16>(((Offset + 0x800080008000LL) >> 48) & 0xffff);
+      // TODO: %highest and %higher can have non-zero values only when the
+      // offset is greater than 4GB, which is highly unlikely.  Replace
+      // them (and the following instructon that shifts $at by 16) with the
+      // instruction that sets $at to zero.
 
       Pos = LongBrMBB->begin();
 
@@ -341,24 +350,28 @@ void MipsLongBranch::expandToLongBranch(MBBInfo &I) {
         .addReg(Mips::SP_64).addImm(-16);
       BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::SD)).addReg(Mips::RA_64)
         .addReg(Mips::SP_64).addImm(0);
-      BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::LUi64), Mips::AT_64)
-        .addImm(Highest);
-      BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::DADDiu), Mips::AT_64)
-        .addReg(Mips::AT_64).addImm(Higher);
+      BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::LONG_BRANCH_LUi64),
+              Mips::AT_64).addMBB(TgtMBB).addMBB(BalTgtMBB);
+      BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::LONG_BRANCH_DADDiu),
+              Mips::AT_64).addReg(Mips::AT_64).addMBB(TgtMBB, MipsII::MO_HIGHER)
+                          .addMBB(BalTgtMBB);
+      BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::DSLL), Mips::AT_64)
+        .addReg(Mips::AT_64).addImm(16);
+      BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::LONG_BRANCH_DADDiu),
+              Mips::AT_64).addReg(Mips::AT_64).addMBB(TgtMBB, MipsII::MO_ABS_HI)
+                          .addMBB(BalTgtMBB);
       BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::DSLL), Mips::AT_64)
         .addReg(Mips::AT_64).addImm(16);
-      BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::DADDiu), Mips::AT_64)
-        .addReg(Mips::AT_64).addImm(Hi);
 
       MIBundleBuilder(*LongBrMBB, Pos)
         .append(BuildMI(*MF, DL, TII->get(Mips::BAL_BR)).addMBB(BalTgtMBB))
-        .append(BuildMI(*MF, DL, TII->get(Mips::DSLL), Mips::AT_64)
-                .addReg(Mips::AT_64).addImm(16));
+        .append(BuildMI(*MF, DL, TII->get(Mips::LONG_BRANCH_DADDiu),
+                        Mips::AT_64).addReg(Mips::AT_64)
+                                    .addMBB(TgtMBB, MipsII::MO_ABS_LO)
+                                    .addMBB(BalTgtMBB));
 
       Pos = BalTgtMBB->begin();
 
-      BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::DADDiu), Mips::AT_64)
-        .addReg(Mips::AT_64).addImm(Lo);
       BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::DADDu), Mips::AT_64)
         .addReg(Mips::RA_64).addReg(Mips::AT_64);
       BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::LD), Mips::RA_64)
@@ -370,8 +383,7 @@ void MipsLongBranch::expandToLongBranch(MBBInfo &I) {
                 .addReg(Mips::SP_64).addImm(16));
     }
 
-    assert(BalTgtMBBSize == BalTgtMBB->size());
-    assert(LongBrMBB->size() + BalTgtMBBSize == LongBranchSeqSize);
+    assert(LongBrMBB->size() + BalTgtMBB->size() == LongBranchSeqSize);
   } else {
     // $longbr:
     //  j $tgt
diff --git a/lib/Target/Mips/MipsMCInstLower.cpp b/lib/Target/Mips/MipsMCInstLower.cpp
index 7c9a9ed831..85f7867466 100644
--- a/lib/Target/Mips/MipsMCInstLower.cpp
+++ b/lib/Target/Mips/MipsMCInstLower.cpp
@@ -151,7 +151,82 @@ MCOperand MipsMCInstLower::LowerOperand(const MachineOperand &MO,
   return MCOperand();
 }
 
+MCOperand MipsMCInstLower::createSub(MachineBasicBlock *BB1,
+                                     MachineBasicBlock *BB2,
+                                     MCSymbolRefExpr::VariantKind Kind) const {
+  const MCSymbolRefExpr *Sym1 = MCSymbolRefExpr::Create(BB1->getSymbol(), *Ctx);
+  const MCSymbolRefExpr *Sym2 = MCSymbolRefExpr::Create(BB2->getSymbol(), *Ctx);
+  const MCBinaryExpr *Sub = MCBinaryExpr::CreateSub(Sym1, Sym2, *Ctx);
+
+  return MCOperand::CreateExpr(MipsMCExpr::Create(Kind, Sub, *Ctx));
+}
+
+void MipsMCInstLower::
+lowerLongBranchLUi(const MachineInstr *MI, MCInst &OutMI, int Opcode,
+                   MCSymbolRefExpr::VariantKind Kind) const {
+  OutMI.setOpcode(Opcode);
+
+  // Lower register operand.
+  OutMI.addOperand(LowerOperand(MI->getOperand(0)));
+
+  // Create %hi($tgt-$baltgt) or %highest($tgt-$baltgt).
+  OutMI.addOperand(createSub(MI->getOperand(1).getMBB(),
+                             MI->getOperand(2).getMBB(), Kind));
+}
+
+void MipsMCInstLower::
+lowerLongBranchADDiu(const MachineInstr *MI, MCInst &OutMI, int Opcode,
+                     MCSymbolRefExpr::VariantKind Kind) const {
+  OutMI.setOpcode(Opcode);
+
+  // Lower two register operands.
+  for (unsigned I = 0, E = 2; I != E; ++I) {
+    const MachineOperand &MO = MI->getOperand(I);
+    OutMI.addOperand(LowerOperand(MO));
+  }
+
+  // Create %lo($tgt-$baltgt), %hi($tgt-$baltgt) or %higher($tgt-$baltgt).
+  OutMI.addOperand(createSub(MI->getOperand(2).getMBB(),
+                             MI->getOperand(3).getMBB(), Kind));
+}
+
+bool MipsMCInstLower::lowerLongBranch(const MachineInstr *MI,
+                                      MCInst &OutMI) const {
+  switch (MI->getOpcode()) {
+  default:
+    return false;
+  case Mips::LONG_BRANCH_LUi:
+    lowerLongBranchLUi(MI, OutMI, Mips::LUi, MCSymbolRefExpr::VK_Mips_ABS_HI);
+    return true;
+  case Mips::LONG_BRANCH_LUi64:
+    lowerLongBranchLUi(MI, OutMI, Mips::LUi64,
+                       MCSymbolRefExpr::VK_Mips_HIGHEST);
+    return true;
+  case Mips::LONG_BRANCH_ADDiu:
+    lowerLongBranchADDiu(MI, OutMI, Mips::ADDiu,
+                         MCSymbolRefExpr::VK_Mips_ABS_LO);
+    return true;
+  case Mips::LONG_BRANCH_DADDiu:
+    unsigned TargetFlags = MI->getOperand(2).getTargetFlags();
+    if (TargetFlags == MipsII::MO_HIGHER)
+      lowerLongBranchADDiu(MI, OutMI, Mips::DADDiu,
+                           MCSymbolRefExpr::VK_Mips_HIGHER);
+    else if (TargetFlags == MipsII::MO_ABS_HI)
+      lowerLongBranchADDiu(MI, OutMI, Mips::DADDiu,
+                           MCSymbolRefExpr::VK_Mips_ABS_HI);
+    else if (TargetFlags == MipsII::MO_ABS_LO)
+      lowerLongBranchADDiu(MI, OutMI, Mips::DADDiu,
+                           MCSymbolRefExpr::VK_Mips_ABS_LO);
+    else
+      report_fatal_error("Unexpected flags for LONG_BRANCH_DADDiu");
+    return true;
+  }
+}
+
 void MipsMCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const {
+  if (lowerLongBranch(MI, OutMI))
+    return;
+
   OutMI.setOpcode(MI->getOpcode());
 
   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
diff --git a/lib/Target/Mips/MipsMCInstLower.h b/lib/Target/Mips/MipsMCInstLower.h
index 4570bd9099..6971f49ff2 100644
--- a/lib/Target/Mips/MipsMCInstLower.h
+++ b/lib/Target/Mips/MipsMCInstLower.h
@@ -9,6 +9,7 @@
 
 #ifndef MIPSMCINSTLOWER_H
 #define MIPSMCINSTLOWER_H
+#include "MCTargetDesc/MipsMCExpr.h"
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/CodeGen/MachineOperand.h"
 #include "llvm/Support/Compiler.h"
@@ -36,6 +37,14 @@ public:
 private:
   MCOperand LowerSymbolOperand(const MachineOperand &MO,
                                MachineOperandType MOTy, unsigned Offset) const;
+  MCOperand createSub(MachineBasicBlock *BB1, MachineBasicBlock *BB2,
+                      MCSymbolRefExpr::VariantKind Kind) const;
+  void lowerLongBranchLUi(const MachineInstr *MI, MCInst &OutMI,
+                          int Opcode, MCSymbolRefExpr::VariantKind Kind) const;
+  void lowerLongBranchADDiu(const MachineInstr *MI, MCInst &OutMI,
+                            int Opcode,
+                            MCSymbolRefExpr::VariantKind Kind) const;
+  bool lowerLongBranch(const MachineInstr *MI, MCInst &OutMI) const;
 };
 }
 
diff --git a/lib/Target/Mips/MipsMSAInstrInfo.td b/lib/Target/Mips/MipsMSAInstrInfo.td
index 5722c6cf00..a35a16e1d3 100644
--- a/lib/Target/Mips/MipsMSAInstrInfo.td
+++ b/lib/Target/Mips/MipsMSAInstrInfo.td
@@ -1505,6 +1505,15 @@ class MSA_INSERT_PSEUDO_BASE<SDPatternOperator OpNode, ValueType Ty,
   string Constraints = "$wd = $wd_in";
 }
 
+class MSA_INSERT_VIDX_PSEUDO_BASE<SDPatternOperator OpNode, ValueType Ty,
+                                  RegisterOperand ROWD, RegisterOperand ROFS> :
+      MSAPseudo<(outs ROWD:$wd), (ins ROWD:$wd_in, GPR32Opnd:$n, ROFS:$fs),
+                [(set ROWD:$wd, (OpNode (Ty ROWD:$wd_in), ROFS:$fs,
+                                        GPR32Opnd:$n))]> {
+  bit usesCustomInserter = 1;
+  string Constraints = "$wd = $wd_in";
+}
+
 class MSA_INSVE_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
                           RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
                           InstrItinClass itin = NoItinerary> {
@@ -2300,11 +2309,25 @@ class INSERT_W_DESC : MSA_INSERT_DESC_BASE<"insert.w", vinsert_v4i32,
 class INSERT_D_DESC : MSA_INSERT_DESC_BASE<"insert.d", vinsert_v2i64,
                                            MSA128DOpnd, GPR64Opnd>;
 
+class INSERT_B_VIDX_PSEUDO_DESC :
+    MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v16i8, MSA128BOpnd, GPR32Opnd>;
+class INSERT_H_VIDX_PSEUDO_DESC :
+    MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v8i16, MSA128HOpnd, GPR32Opnd>;
+class INSERT_W_VIDX_PSEUDO_DESC :
+    MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v4i32, MSA128WOpnd, GPR32Opnd>;
+class INSERT_D_VIDX_PSEUDO_DESC :
+    MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v2i64, MSA128DOpnd, GPR64Opnd>;
+
 class INSERT_FW_PSEUDO_DESC : MSA_INSERT_PSEUDO_BASE<vector_insert, v4f32,
                                                      MSA128WOpnd, FGR32Opnd>;
 class INSERT_FD_PSEUDO_DESC : MSA_INSERT_PSEUDO_BASE<vector_insert, v2f64,
                                                      MSA128DOpnd, FGR64Opnd>;
 
+class INSERT_FW_VIDX_PSEUDO_DESC :
+    MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v4f32, MSA128WOpnd, FGR32Opnd>;
+class INSERT_FD_VIDX_PSEUDO_DESC :
+    MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v2f64, MSA128DOpnd, FGR64Opnd>;
+
 class INSVE_B_DESC : MSA_INSVE_DESC_BASE<"insve.b", insve_v16i8,
                                          MSA128BOpnd>;
 class INSVE_H_DESC : MSA_INSVE_DESC_BASE<"insve.h", insve_v8i16,
@@ -3214,6 +3237,13 @@ let DecoderMethod = "DecodeINSVE_DF" in {
 def INSERT_FW_PSEUDO : INSERT_FW_PSEUDO_DESC;
 def INSERT_FD_PSEUDO : INSERT_FD_PSEUDO_DESC;
 
+def INSERT_B_VIDX_PSEUDO : INSERT_B_VIDX_PSEUDO_DESC;
+def INSERT_H_VIDX_PSEUDO : INSERT_H_VIDX_PSEUDO_DESC;
+def INSERT_W_VIDX_PSEUDO : INSERT_W_VIDX_PSEUDO_DESC;
+def INSERT_D_VIDX_PSEUDO : INSERT_D_VIDX_PSEUDO_DESC;
+def INSERT_FW_VIDX_PSEUDO : INSERT_FW_VIDX_PSEUDO_DESC;
+def INSERT_FD_VIDX_PSEUDO : INSERT_FD_VIDX_PSEUDO_DESC;
+
 def LD_B: LD_B_ENC, LD_B_DESC;
 def LD_H: LD_H_ENC, LD_H_DESC;
 def LD_W: LD_W_ENC, LD_W_DESC;
@@ -3731,3 +3761,55 @@ def SZ_D_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllZero, v2i64,
                                                MSA128D, NoItinerary>;
 def SZ_V_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAnyZero, v16i8,
                                                MSA128B, NoItinerary>;
+
+// Vector extraction with variable index
+def : MSAPat<(i32 (vextract_sext_i8 v16i8:$ws, i32:$idx)),
+             (SRA (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG (SPLAT_B v16i8:$ws,
+                                                                  i32:$idx),
+                                                         sub_lo)),
+                                    GPR32), (i32 24))>;
+def : MSAPat<(i32 (vextract_sext_i16 v8i16:$ws, i32:$idx)),
+             (SRA (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG (SPLAT_H v8i16:$ws,
+                                                                  i32:$idx),
+                                                         sub_lo)),
+                                    GPR32), (i32 16))>;
+def : MSAPat<(i32 (vextract_sext_i32 v4i32:$ws, i32:$idx)),
+             (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG (SPLAT_W v4i32:$ws,
+                                                             i32:$idx),
+                                                    sub_lo)),
+                               GPR32)>;
+def : MSAPat<(i64 (vextract_sext_i64 v2i64:$ws, i32:$idx)),
+             (COPY_TO_REGCLASS (i64 (EXTRACT_SUBREG (SPLAT_D v2i64:$ws,
+                                                             i32:$idx),
+                                                    sub_64)),
+                               GPR64), [HasMSA, IsGP64bit]>;
+
+def : MSAPat<(i32 (vextract_zext_i8 v16i8:$ws, i32:$idx)),
+             (SRL (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG (SPLAT_B v16i8:$ws,
+                                                                  i32:$idx),
+                                                         sub_lo)),
+                                    GPR32), (i32 24))>;
+def : MSAPat<(i32 (vextract_zext_i16 v8i16:$ws, i32:$idx)),
+             (SRL (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG (SPLAT_H v8i16:$ws,
+                                                                  i32:$idx),
+                                                         sub_lo)),
+                                    GPR32), (i32 16))>;
+def : MSAPat<(i32 (vextract_zext_i32 v4i32:$ws, i32:$idx)),
+             (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG (SPLAT_W v4i32:$ws,
+                                                             i32:$idx),
+                                                    sub_lo)),
+                               GPR32)>;
+def : MSAPat<(i64 (vextract_zext_i64 v2i64:$ws, i32:$idx)),
+             (COPY_TO_REGCLASS (i64 (EXTRACT_SUBREG (SPLAT_D v2i64:$ws,
+                                                             i32:$idx),
+                                                    sub_64)),
+                               GPR64), [HasMSA, IsGP64bit]>;
+
+def : MSAPat<(f32 (vector_extract v4f32:$ws, i32:$idx)),
+             (f32 (EXTRACT_SUBREG (SPLAT_W v4f32:$ws,
+                                           i32:$idx),
+                                  sub_lo))>;
+def : MSAPat<(f64 (vector_extract v2f64:$ws, i32:$idx)),
+             (f64 (EXTRACT_SUBREG (SPLAT_D v2f64:$ws,
+                                           i32:$idx),
+                                  sub_64))>;
diff --git a/lib/Target/Mips/MipsMachineFunction.h b/lib/Target/Mips/MipsMachineFunction.h
index 3e14c8cbf8..e9101cc77c 100644
--- a/lib/Target/Mips/MipsMachineFunction.h
+++ b/lib/Target/Mips/MipsMachineFunction.h
@@ -37,12 +37,12 @@ class MipsCallEntry : public PseudoSourceValue {
 public:
   explicit MipsCallEntry(const StringRef &N);
   explicit MipsCallEntry(const GlobalValue *V);
-  virtual bool isConstant(const MachineFrameInfo *) const;
-  virtual bool isAliased(const MachineFrameInfo *) const;
-  virtual bool mayAlias(const MachineFrameInfo *) const;
+  bool isConstant(const MachineFrameInfo *) const override;
+  bool isAliased(const MachineFrameInfo *) const override;
+  bool mayAlias(const MachineFrameInfo *) const override;
 
 private:
-  virtual void printCustom(raw_ostream &O) const;
+  void printCustom(raw_ostream &O) const override;
 #ifndef NDEBUG
   std::string Name;
   const GlobalValue *Val;
diff --git a/lib/Target/Mips/MipsModuleISelDAGToDAG.h b/lib/Target/Mips/MipsModuleISelDAGToDAG.h
index fda35ae288..a96862a6a1 100644
--- a/lib/Target/Mips/MipsModuleISelDAGToDAG.h
+++ b/lib/Target/Mips/MipsModuleISelDAGToDAG.h
@@ -41,15 +41,11 @@ public:
       TM(TM_), Subtarget(TM.getSubtarget<MipsSubtarget>()) {}
 
   // Pass Name
-  virtual const char *getPassName() const {
+  const char *getPassName() const override {
     return "MIPS DAG->DAG Pattern Instruction Selection";
   }
 
-  virtual bool runOnMachineFunction(MachineFunction &MF);
-
-  virtual SDNode *Select(SDNode *N) {
-    llvm_unreachable("unexpected");
-  }
+  bool runOnMachineFunction(MachineFunction &MF) override;
 
 protected:
   /// Keep a pointer to the MipsSubtarget around so that we can make the right
diff --git a/lib/Target/Mips/MipsOptimizePICCall.cpp b/lib/Target/Mips/MipsOptimizePICCall.cpp
index 87895c2d23..c234049ed1 100644
--- a/lib/Target/Mips/MipsOptimizePICCall.cpp
+++ b/lib/Target/Mips/MipsOptimizePICCall.cpp
@@ -61,11 +61,11 @@ class OptimizePICCall : public MachineFunctionPass {
 public:
   OptimizePICCall(TargetMachine &tm) : MachineFunctionPass(ID) {}
 
-  virtual const char *getPassName() const { return "Mips OptimizePICCall"; }
+  const char *getPassName() const override { return "Mips OptimizePICCall"; }
 
-  bool runOnMachineFunction(MachineFunction &F);
+  bool runOnMachineFunction(MachineFunction &F) override;
 
-  void getAnalysisUsage(AnalysisUsage &AU) const {
+  void getAnalysisUsage(AnalysisUsage &AU) const override {
     AU.addRequired<MachineDominatorTree>();
     MachineFunctionPass::getAnalysisUsage(AU);
   }
diff --git a/lib/Target/Mips/MipsOs16.h b/lib/Target/Mips/MipsOs16.h
index 21beef8549..55e5a81daf 100644
--- a/lib/Target/Mips/MipsOs16.h
+++ b/lib/Target/Mips/MipsOs16.h
@@ -34,11 +34,11 @@ public:
 
   }
 
-  virtual const char *getPassName() const {
+  const char *getPassName() const override {
     return "MIPS Os16 Optimization";
   }
 
-  virtual bool runOnModule(Module &M);
+  bool runOnModule(Module &M) override;
 
 };
 
diff --git a/lib/Target/Mips/MipsRegisterInfo.h b/lib/Target/Mips/MipsRegisterInfo.h
index 46b9d10822..b34496fd8e 100644
--- a/lib/Target/Mips/MipsRegisterInfo.h
+++ b/lib/Target/Mips/MipsRegisterInfo.h
@@ -43,30 +43,31 @@ public:
 
   /// Code Generation virtual methods...
   const TargetRegisterClass *getPointerRegClass(const MachineFunction &MF,
-                                                unsigned Kind) const;
+                                                unsigned Kind) const override;
 
   unsigned getRegPressureLimit(const TargetRegisterClass *RC,
-                               MachineFunction &MF) const;
-  const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF =nullptr) const;
-  const uint32_t *getCallPreservedMask(CallingConv::ID) const;
+                               MachineFunction &MF) const override;
+  const MCPhysReg *
+  getCalleeSavedRegs(const MachineFunction *MF = nullptr) const override;
+  const uint32_t *getCallPreservedMask(CallingConv::ID) const override;
   static const uint32_t *getMips16RetHelperMask();
 
-  BitVector getReservedRegs(const MachineFunction &MF) const;
+  BitVector getReservedRegs(const MachineFunction &MF) const override;
 
-  virtual bool requiresRegisterScavenging(const MachineFunction &MF) const;
+  bool requiresRegisterScavenging(const MachineFunction &MF) const override;
 
-  virtual bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const;
+  bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override;
 
   /// Stack Frame Processing Methods
   void eliminateFrameIndex(MachineBasicBlock::iterator II,
                            int SPAdj, unsigned FIOperandNum,
-                           RegScavenger *RS = nullptr) const;
+                           RegScavenger *RS = nullptr) const override;
 
   void processFunctionBeforeFrameFinalized(MachineFunction &MF,
                                        RegScavenger *RS = nullptr) const;
 
   /// Debug information queries.
-  unsigned getFrameRegister(const MachineFunction &MF) const;
+  unsigned getFrameRegister(const MachineFunction &MF) const override;
 
   /// \brief Return GPR register class.
   virtual const TargetRegisterClass *intRegClass(unsigned Size) const = 0;
diff --git a/lib/Target/Mips/MipsSEFrameLowering.h b/lib/Target/Mips/MipsSEFrameLowering.h
index 8fa9e46988..5d2801ffb2 100644
--- a/lib/Target/Mips/MipsSEFrameLowering.h
+++ b/lib/Target/Mips/MipsSEFrameLowering.h
@@ -25,22 +25,22 @@ public:
 
   /// emitProlog/emitEpilog - These methods insert prolog and epilog code into
   /// the function.
-  void emitPrologue(MachineFunction &MF) const;
-  void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
+  void emitPrologue(MachineFunction &MF) const override;
+  void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override;
 
   void eliminateCallFramePseudoInstr(MachineFunction &MF,
-                                     MachineBasicBlock &MBB,
-                                     MachineBasicBlock::iterator I) const;
+                                  MachineBasicBlock &MBB,
+                                  MachineBasicBlock::iterator I) const override;
 
   bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
                                  MachineBasicBlock::iterator MI,
                                  const std::vector<CalleeSavedInfo> &CSI,
-                                 const TargetRegisterInfo *TRI) const;
+                                 const TargetRegisterInfo *TRI) const override;
 
-  bool hasReservedCallFrame(const MachineFunction &MF) const;
+  bool hasReservedCallFrame(const MachineFunction &MF) const override;
 
   void processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
-                                            RegScavenger *RS) const;
+                                            RegScavenger *RS) const override;
   unsigned ehDataReg(unsigned I) const;
 };
 
diff --git a/lib/Target/Mips/MipsSEISelDAGToDAG.h b/lib/Target/Mips/MipsSEISelDAGToDAG.h
index ba84a6d397..57328d2f92 100644
--- a/lib/Target/Mips/MipsSEISelDAGToDAG.h
+++ b/lib/Target/Mips/MipsSEISelDAGToDAG.h
@@ -25,7 +25,7 @@ public:
 
 private:
 
-  virtual bool runOnMachineFunction(MachineFunction &MF);
+  bool runOnMachineFunction(MachineFunction &MF) override;
 
   void addDSPCtrlRegOperands(bool IsDef, MachineInstr &MI,
                              MachineFunction &MF);
@@ -44,66 +44,66 @@ private:
   bool selectAddrFrameIndexOffset(SDValue Addr, SDValue &Base, SDValue &Offset,
                                   unsigned OffsetBits) const;
 
-  virtual bool selectAddrRegImm(SDValue Addr, SDValue &Base,
-                                SDValue &Offset) const;
+  bool selectAddrRegImm(SDValue Addr, SDValue &Base,
+                        SDValue &Offset) const override;
 
-  virtual bool selectAddrRegReg(SDValue Addr, SDValue &Base,
-                                SDValue &Offset) const;
+  bool selectAddrRegReg(SDValue Addr, SDValue &Base,
+                        SDValue &Offset) const override;
 
-  virtual bool selectAddrDefault(SDValue Addr, SDValue &Base,
-                                 SDValue &Offset) const;
+  bool selectAddrDefault(SDValue Addr, SDValue &Base,
+                         SDValue &Offset) const override;
 
-  virtual bool selectIntAddr(SDValue Addr, SDValue &Base,
-                             SDValue &Offset) const;
+  bool selectIntAddr(SDValue Addr, SDValue &Base,
+                     SDValue &Offset) const override;
 
-  virtual bool selectAddrRegImm10(SDValue Addr, SDValue &Base,
-                                  SDValue &Offset) const;
+  bool selectAddrRegImm10(SDValue Addr, SDValue &Base,
+                          SDValue &Offset) const;
 
-  virtual bool selectAddrRegImm12(SDValue Addr, SDValue &Base,
-                                  SDValue &Offset) const;
+  bool selectAddrRegImm12(SDValue Addr, SDValue &Base,
+                          SDValue &Offset) const;
 
-  virtual bool selectIntAddrMM(SDValue Addr, SDValue &Base,
-                               SDValue &Offset) const;
+  bool selectIntAddrMM(SDValue Addr, SDValue &Base,
+                       SDValue &Offset) const override;
 
-  virtual bool selectIntAddrMSA(SDValue Addr, SDValue &Base,
-                                SDValue &Offset) const;
+  bool selectIntAddrMSA(SDValue Addr, SDValue &Base,
+                        SDValue &Offset) const override;
 
   /// \brief Select constant vector splats.
-  virtual bool selectVSplat(SDNode *N, APInt &Imm) const;
+  bool selectVSplat(SDNode *N, APInt &Imm) const override;
   /// \brief Select constant vector splats whose value fits in a given integer.
-  virtual bool selectVSplatCommon(SDValue N, SDValue &Imm, bool Signed,
+  bool selectVSplatCommon(SDValue N, SDValue &Imm, bool Signed,
                                   unsigned ImmBitSize) const;
   /// \brief Select constant vector splats whose value fits in a uimm1.
-  virtual bool selectVSplatUimm1(SDValue N, SDValue &Imm) const;
+  bool selectVSplatUimm1(SDValue N, SDValue &Imm) const override;
   /// \brief Select constant vector splats whose value fits in a uimm2.
-  virtual bool selectVSplatUimm2(SDValue N, SDValue &Imm) const;
+  bool selectVSplatUimm2(SDValue N, SDValue &Imm) const override;
   /// \brief Select constant vector splats whose value fits in a uimm3.
-  virtual bool selectVSplatUimm3(SDValue N, SDValue &Imm) const;
+  bool selectVSplatUimm3(SDValue N, SDValue &Imm) const override;
   /// \brief Select constant vector splats whose value fits in a uimm4.
-  virtual bool selectVSplatUimm4(SDValue N, SDValue &Imm) const;
+  bool selectVSplatUimm4(SDValue N, SDValue &Imm) const override;
   /// \brief Select constant vector splats whose value fits in a uimm5.
-  virtual bool selectVSplatUimm5(SDValue N, SDValue &Imm) const;
+  bool selectVSplatUimm5(SDValue N, SDValue &Imm) const override;
   /// \brief Select constant vector splats whose value fits in a uimm6.
-  virtual bool selectVSplatUimm6(SDValue N, SDValue &Imm) const;
+  bool selectVSplatUimm6(SDValue N, SDValue &Imm) const override;
   /// \brief Select constant vector splats whose value fits in a uimm8.
-  virtual bool selectVSplatUimm8(SDValue N, SDValue &Imm) const;
+  bool selectVSplatUimm8(SDValue N, SDValue &Imm) const override;
   /// \brief Select constant vector splats whose value fits in a simm5.
-  virtual bool selectVSplatSimm5(SDValue N, SDValue &Imm) const;
+  bool selectVSplatSimm5(SDValue N, SDValue &Imm) const override;
   /// \brief Select constant vector splats whose value is a power of 2.
-  virtual bool selectVSplatUimmPow2(SDValue N, SDValue &Imm) const;
+  bool selectVSplatUimmPow2(SDValue N, SDValue &Imm) const override;
   /// \brief Select constant vector splats whose value is the inverse of a
   /// power of 2.
-  virtual bool selectVSplatUimmInvPow2(SDValue N, SDValue &Imm) const;
+  bool selectVSplatUimmInvPow2(SDValue N, SDValue &Imm) const override;
   /// \brief Select constant vector splats whose value is a run of set bits
   /// ending at the most significant bit
-  virtual bool selectVSplatMaskL(SDValue N, SDValue &Imm) const;
+  bool selectVSplatMaskL(SDValue N, SDValue &Imm) const override;
   /// \brief Select constant vector splats whose value is a run of set bits
   /// starting at bit zero.
-  virtual bool selectVSplatMaskR(SDValue N, SDValue &Imm) const;
+  bool selectVSplatMaskR(SDValue N, SDValue &Imm) const override;
 
-  virtual std::pair<bool, SDNode*> selectNode(SDNode *Node);
+  std::pair<bool, SDNode*> selectNode(SDNode *Node) override;
 
-  virtual void processFunctionAfterISel(MachineFunction &MF);
+  void processFunctionAfterISel(MachineFunction &MF) override;
 
   // Insert instructions to initialize the global base register in the
   // first MBB of the function.
diff --git a/lib/Target/Mips/MipsSEISelLowering.cpp b/lib/Target/Mips/MipsSEISelLowering.cpp
index a4ff3f41eb..eb9a819aa3 100644
--- a/lib/Target/Mips/MipsSEISelLowering.cpp
+++ b/lib/Target/Mips/MipsSEISelLowering.cpp
@@ -489,7 +489,7 @@ static SDValue performANDCombine(SDNode *N, SelectionDAG &DAG,
       SDValue Ops[] = { Op0->getOperand(0), Op0->getOperand(1), Op0Op2 };
       DAG.MorphNodeTo(Op0.getNode(), MipsISD::VEXTRACT_ZEXT_ELT,
                       Op0->getVTList(),
-                      ArrayRef<SDValue>(Ops, Op0->getNumOperands()));
+                      makeArrayRef(Ops, Op0->getNumOperands()));
       return Op0;
     }
   }
@@ -834,7 +834,7 @@ static SDValue performSRACombine(SDNode *N, SelectionDAG &DAG,
                           Op0Op0->getOperand(2) };
         DAG.MorphNodeTo(Op0Op0.getNode(), MipsISD::VEXTRACT_SEXT_ELT,
                         Op0Op0->getVTList(),
-                        ArrayRef<SDValue>(Ops, Op0Op0->getNumOperands()));
+                        makeArrayRef(Ops, Op0Op0->getNumOperands()));
         return Op0Op0;
       }
     }
@@ -1054,6 +1054,18 @@ MipsSETargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
     return emitINSERT_FW(MI, BB);
   case Mips::INSERT_FD_PSEUDO:
     return emitINSERT_FD(MI, BB);
+  case Mips::INSERT_B_VIDX_PSEUDO:
+    return emitINSERT_DF_VIDX(MI, BB, 1, false);
+  case Mips::INSERT_H_VIDX_PSEUDO:
+    return emitINSERT_DF_VIDX(MI, BB, 2, false);
+  case Mips::INSERT_W_VIDX_PSEUDO:
+    return emitINSERT_DF_VIDX(MI, BB, 4, false);
+  case Mips::INSERT_D_VIDX_PSEUDO:
+    return emitINSERT_DF_VIDX(MI, BB, 8, false);
+  case Mips::INSERT_FW_VIDX_PSEUDO:
+    return emitINSERT_DF_VIDX(MI, BB, 4, true);
+  case Mips::INSERT_FD_VIDX_PSEUDO:
+    return emitINSERT_DF_VIDX(MI, BB, 8, true);
   case Mips::FILL_FW_PSEUDO:
     return emitFILL_FW(MI, BB);
   case Mips::FILL_FD_PSEUDO:
@@ -1284,7 +1296,7 @@ static SDValue lowerMSASplatZExt(SDValue Op, unsigned OpNr, SelectionDAG &DAG) {
                       LaneA, LaneB, LaneA, LaneB, LaneA, LaneB, LaneA, LaneB };
 
   SDValue Result = DAG.getNode(ISD::BUILD_VECTOR, DL, ViaVecTy,
-                       ArrayRef<SDValue>(Ops, ViaVecTy.getVectorNumElements()));
+                       makeArrayRef(Ops, ViaVecTy.getVectorNumElements()));
 
   if (ViaVecTy != ResVecTy)
     Result = DAG.getNode(ISD::BITCAST, DL, ResVecTy, Result);
@@ -1324,7 +1336,7 @@ static SDValue getBuildVectorSplat(EVT VecTy, SDValue SplatValue,
                       SplatValueA, SplatValueB, SplatValueA, SplatValueB };
 
   SDValue Result = DAG.getNode(ISD::BUILD_VECTOR, DL, ViaVecTy,
-                       ArrayRef<SDValue>(Ops, ViaVecTy.getVectorNumElements()));
+                       makeArrayRef(Ops, ViaVecTy.getVectorNumElements()));
 
   if (VecTy != ViaVecTy)
     Result = DAG.getNode(ISD::BITCAST, DL, VecTy, Result);
@@ -2887,6 +2899,131 @@ MipsSETargetLowering::emitINSERT_FD(MachineInstr *MI,
   return BB;
 }
 
+// Emit the INSERT_([BHWD]|F[WD])_VIDX pseudo instruction.
+//
+// For integer:
+// (INSERT_([BHWD]|F[WD])_PSEUDO $wd, $wd_in, $n, $rs)
+// =>
+// (SLL $lanetmp1, $lane, <log2size)
+// (SLD_B $wdtmp1, $wd_in, $wd_in, $lanetmp1)
+// (INSERT_[BHWD], $wdtmp2, $wdtmp1, 0, $rs)
+// (NEG $lanetmp2, $lanetmp1)
+// (SLD_B $wd, $wdtmp2, $wdtmp2,  $lanetmp2)
+//
+// For floating point:
+// (INSERT_([BHWD]|F[WD])_PSEUDO $wd, $wd_in, $n, $fs)
+// =>
+// (SUBREG_TO_REG $wt, $fs, <subreg>)
+// (SLL $lanetmp1, $lane, <log2size)
+// (SLD_B $wdtmp1, $wd_in, $wd_in, $lanetmp1)
+// (INSVE_[WD], $wdtmp2, 0, $wdtmp1, 0)
+// (NEG $lanetmp2, $lanetmp1)
+// (SLD_B $wd, $wdtmp2, $wdtmp2,  $lanetmp2)
+MachineBasicBlock *
+MipsSETargetLowering::emitINSERT_DF_VIDX(MachineInstr *MI,
+                                         MachineBasicBlock *BB,
+                                         unsigned EltSizeInBytes,
+                                         bool IsFP) const {
+  const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
+  MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
+  DebugLoc DL = MI->getDebugLoc();
+  unsigned Wd = MI->getOperand(0).getReg();
+  unsigned SrcVecReg = MI->getOperand(1).getReg();
+  unsigned LaneReg = MI->getOperand(2).getReg();
+  unsigned SrcValReg = MI->getOperand(3).getReg();
+
+  const TargetRegisterClass *VecRC = nullptr;
+  const TargetRegisterClass *GPRRC = isGP64bit() ? &Mips::GPR64RegClass
+                                                 : &Mips::GPR32RegClass;
+  unsigned EltLog2Size;
+  unsigned InsertOp = 0;
+  unsigned InsveOp = 0;
+  switch (EltSizeInBytes) {
+  default:
+    llvm_unreachable("Unexpected size");
+  case 1:
+    EltLog2Size = 0;
+    InsertOp = Mips::INSERT_B;
+    InsveOp = Mips::INSVE_B;
+    VecRC = &Mips::MSA128BRegClass;
+    break;
+  case 2:
+    EltLog2Size = 1;
+    InsertOp = Mips::INSERT_H;
+    InsveOp = Mips::INSVE_H;
+    VecRC = &Mips::MSA128HRegClass;
+    break;
+  case 4:
+    EltLog2Size = 2;
+    InsertOp = Mips::INSERT_W;
+    InsveOp = Mips::INSVE_W;
+    VecRC = &Mips::MSA128WRegClass;
+    break;
+  case 8:
+    EltLog2Size = 3;
+    InsertOp = Mips::INSERT_D;
+    InsveOp = Mips::INSVE_D;
+    VecRC = &Mips::MSA128DRegClass;
+    break;
+  }
+
+  if (IsFP) {
+    unsigned Wt = RegInfo.createVirtualRegister(VecRC);
+    BuildMI(*BB, MI, DL, TII->get(Mips::SUBREG_TO_REG), Wt)
+        .addImm(0)
+        .addReg(SrcValReg)
+        .addImm(EltSizeInBytes == 8 ? Mips::sub_64 : Mips::sub_lo);
+    SrcValReg = Wt;
+  }
+
+  // Convert the lane index into a byte index
+  if (EltSizeInBytes != 1) {
+    unsigned LaneTmp1 = RegInfo.createVirtualRegister(GPRRC);
+    BuildMI(*BB, MI, DL, TII->get(Mips::SLL), LaneTmp1)
+        .addReg(LaneReg)
+        .addImm(EltLog2Size);
+    LaneReg = LaneTmp1;
+  }
+
+  // Rotate bytes around so that the desired lane is element zero
+  unsigned WdTmp1 = RegInfo.createVirtualRegister(VecRC);
+  BuildMI(*BB, MI, DL, TII->get(Mips::SLD_B), WdTmp1)
+      .addReg(SrcVecReg)
+      .addReg(SrcVecReg)
+      .addReg(LaneReg);
+
+  unsigned WdTmp2 = RegInfo.createVirtualRegister(VecRC);
+  if (IsFP) {
+    // Use insve.df to insert to element zero
+    BuildMI(*BB, MI, DL, TII->get(InsveOp), WdTmp2)
+        .addReg(WdTmp1)
+        .addImm(0)
+        .addReg(SrcValReg)
+        .addImm(0);
+  } else {
+    // Use insert.df to insert to element zero
+    BuildMI(*BB, MI, DL, TII->get(InsertOp), WdTmp2)
+        .addReg(WdTmp1)
+        .addReg(SrcValReg)
+        .addImm(0);
+  }
+
+  // Rotate elements the rest of the way for a full rotation.
+  // sld.df inteprets $rt modulo the number of columns so we only need to negate
+  // the lane index to do this.
+  unsigned LaneTmp2 = RegInfo.createVirtualRegister(GPRRC);
+  BuildMI(*BB, MI, DL, TII->get(Mips::SUB), LaneTmp2)
+      .addReg(Mips::ZERO)
+      .addReg(LaneReg);
+  BuildMI(*BB, MI, DL, TII->get(Mips::SLD_B), Wd)
+      .addReg(WdTmp2)
+      .addReg(WdTmp2)
+      .addReg(LaneTmp2);
+
+  MI->eraseFromParent(); // The pseudo instruction is gone now.
+  return BB;
+}
+
 // Emit the FILL_FW pseudo instruction.
 //
 // fill_fw_pseudo $wd, $fs
diff --git a/lib/Target/Mips/MipsSEISelLowering.h b/lib/Target/Mips/MipsSEISelLowering.h
index 435c15c750..03a20ef674 100644
--- a/lib/Target/Mips/MipsSEISelLowering.h
+++ b/lib/Target/Mips/MipsSEISelLowering.h
@@ -33,19 +33,20 @@ namespace llvm {
     bool allowsUnalignedMemoryAccesses(EVT VT, unsigned AS = 0,
                                        bool *Fast = nullptr) const override;
 
-    virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
+    SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
 
-    virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
+    SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
 
-    virtual MachineBasicBlock *
-    EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const;
+    MachineBasicBlock *
+    EmitInstrWithCustomInserter(MachineInstr *MI,
+                                MachineBasicBlock *MBB) const override;
 
-    virtual bool isShuffleMaskLegal(const SmallVectorImpl<int> &Mask,
-                                    EVT VT) const {
+    bool isShuffleMaskLegal(const SmallVectorImpl<int> &Mask,
+                            EVT VT) const override {
       return false;
     }
 
-    virtual const TargetRegisterClass *getRepRegClassFor(MVT VT) const {
+    const TargetRegisterClass *getRepRegClassFor(MVT VT) const override {
       if (VT == MVT::Untyped)
         return Subtarget->hasDSP() ? &Mips::ACC64DSPRegClass :
                                      &Mips::ACC64RegClass;
@@ -54,16 +55,16 @@ namespace llvm {
     }
 
   private:
-    virtual bool
-    isEligibleForTailCallOptimization(const MipsCC &MipsCCInfo,
-                                      unsigned NextStackOffset,
-                                      const MipsFunctionInfo& FI) const;
+    bool isEligibleForTailCallOptimization(const MipsCC &MipsCCInfo,
+                                     unsigned NextStackOffset,
+                                     const MipsFunctionInfo& FI) const override;
 
-    virtual void
+    void
     getOpndList(SmallVectorImpl<SDValue> &Ops,
                 std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
                 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
-                CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const;
+                CallLoweringInfo &CLI, SDValue Callee,
+                SDValue Chain) const override;
 
     SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const;
     SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const;
@@ -97,6 +98,11 @@ namespace llvm {
     /// \brief Emit the INSERT_FD pseudo instruction
     MachineBasicBlock *emitINSERT_FD(MachineInstr *MI,
                                      MachineBasicBlock *BB) const;
+    /// \brief Emit the INSERT_([BHWD]|F[WD])_VIDX pseudo instruction
+    MachineBasicBlock *emitINSERT_DF_VIDX(MachineInstr *MI,
+                                          MachineBasicBlock *BB,
+                                          unsigned EltSizeInBytes,
+                                          bool IsFP) const;
     /// \brief Emit the FILL_FW pseudo instruction
     MachineBasicBlock *emitFILL_FW(MachineInstr *MI,
                                    MachineBasicBlock *BB) const;
diff --git a/lib/Target/Mips/MipsSEInstrInfo.h b/lib/Target/Mips/MipsSEInstrInfo.h
index 6d2dd901f3..aa68552066 100644
--- a/lib/Target/Mips/MipsSEInstrInfo.h
+++ b/lib/Target/Mips/MipsSEInstrInfo.h
@@ -26,46 +26,46 @@ class MipsSEInstrInfo : public MipsInstrInfo {
 public:
   explicit MipsSEInstrInfo(MipsTargetMachine &TM);
 
-  virtual const MipsRegisterInfo &getRegisterInfo() const;
+  const MipsRegisterInfo &getRegisterInfo() const override;
 
   /// isLoadFromStackSlot - If the specified machine instruction is a direct
   /// load from a stack slot, return the virtual or physical register number of
   /// the destination along with the FrameIndex of the loaded stack slot.  If
   /// not, return 0.  This predicate must return 0 if the instruction has
   /// any side effects other than loading from the stack slot.
-  virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
-                                       int &FrameIndex) const;
+  unsigned isLoadFromStackSlot(const MachineInstr *MI,
+                               int &FrameIndex) const override;
 
   /// isStoreToStackSlot - If the specified machine instruction is a direct
   /// store to a stack slot, return the virtual or physical register number of
   /// the source reg along with the FrameIndex of the loaded stack slot.  If
   /// not, return 0.  This predicate must return 0 if the instruction has
   /// any side effects other than storing to the stack slot.
-  virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
-                                      int &FrameIndex) const;
+  unsigned isStoreToStackSlot(const MachineInstr *MI,
+                              int &FrameIndex) const override;
 
-  virtual void copyPhysReg(MachineBasicBlock &MBB,
-                           MachineBasicBlock::iterator MI, DebugLoc DL,
-                           unsigned DestReg, unsigned SrcReg,
-                           bool KillSrc) const;
+  void copyPhysReg(MachineBasicBlock &MBB,
+                   MachineBasicBlock::iterator MI, DebugLoc DL,
+                   unsigned DestReg, unsigned SrcReg,
+                   bool KillSrc) const override;
 
-  virtual void storeRegToStack(MachineBasicBlock &MBB,
-                               MachineBasicBlock::iterator MI,
-                               unsigned SrcReg, bool isKill, int FrameIndex,
-                               const TargetRegisterClass *RC,
-                               const TargetRegisterInfo *TRI,
-                               int64_t Offset) const;
+  void storeRegToStack(MachineBasicBlock &MBB,
+                       MachineBasicBlock::iterator MI,
+                       unsigned SrcReg, bool isKill, int FrameIndex,
+                       const TargetRegisterClass *RC,
+                       const TargetRegisterInfo *TRI,
+                       int64_t Offset) const override;
 
-  virtual void loadRegFromStack(MachineBasicBlock &MBB,
-                                MachineBasicBlock::iterator MI,
-                                unsigned DestReg, int FrameIndex,
-                                const TargetRegisterClass *RC,
-                                const TargetRegisterInfo *TRI,
-                                int64_t Offset) const;
+  void loadRegFromStack(MachineBasicBlock &MBB,
+                        MachineBasicBlock::iterator MI,
+                        unsigned DestReg, int FrameIndex,
+                        const TargetRegisterClass *RC,
+                        const TargetRegisterInfo *TRI,
+                        int64_t Offset) const override;
 
-  virtual bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const;
+  bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const override;
 
-  virtual unsigned getOppositeBranchOpc(unsigned Opc) const;
+  unsigned getOppositeBranchOpc(unsigned Opc) const override;
 
   /// Adjust SP by Amount bytes.
   void adjustStackPtr(unsigned SP, int64_t Amount, MachineBasicBlock &MBB,
@@ -79,7 +79,7 @@ public:
                          unsigned *NewImm) const;
 
 private:
-  virtual unsigned getAnalyzableBrOpc(unsigned Opc) const;
+  unsigned getAnalyzableBrOpc(unsigned Opc) const override;
 
   void expandRetRA(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
                    unsigned Opc) const;
diff --git a/lib/Target/Mips/MipsSERegisterInfo.h b/lib/Target/Mips/MipsSERegisterInfo.h
index 76cdd9d230..f2f3a7e75f 100644
--- a/lib/Target/Mips/MipsSERegisterInfo.h
+++ b/lib/Target/Mips/MipsSERegisterInfo.h
@@ -24,16 +24,16 @@ class MipsSERegisterInfo : public MipsRegisterInfo {
 public:
   MipsSERegisterInfo(const MipsSubtarget &Subtarget);
 
-  bool requiresRegisterScavenging(const MachineFunction &MF) const;
+  bool requiresRegisterScavenging(const MachineFunction &MF) const override;
 
-  bool requiresFrameIndexScavenging(const MachineFunction &MF) const;
+  bool requiresFrameIndexScavenging(const MachineFunction &MF) const override;
 
-  virtual const TargetRegisterClass *intRegClass(unsigned Size) const;
+  const TargetRegisterClass *intRegClass(unsigned Size) const override;
 
 private:
-  virtual void eliminateFI(MachineBasicBlock::iterator II, unsigned OpNo,
-                           int FrameIndex, uint64_t StackSize,
-                           int64_t SPOffset) const;
+  void eliminateFI(MachineBasicBlock::iterator II, unsigned OpNo,
+                   int FrameIndex, uint64_t StackSize,
+                   int64_t SPOffset) const override;
 };
 
 } // end namespace llvm
diff --git a/lib/Target/Mips/MipsSubtarget.h b/lib/Target/Mips/MipsSubtarget.h
index c739f91817..3c70f825e1 100644
--- a/lib/Target/Mips/MipsSubtarget.h
+++ b/lib/Target/Mips/MipsSubtarget.h
@@ -130,9 +130,9 @@ protected:
 
   Triple TargetTriple;
 public:
-  virtual bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
-                                     AntiDepBreakMode& Mode,
-                                     RegClassVector& CriticalPathRCs) const;
+  bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
+                             AntiDepBreakMode& Mode,
+                             RegClassVector& CriticalPathRCs) const override;
 
   /// Only O32 and EABI supported right now.
   bool isABI_EABI() const { return MipsABI == EABI; }
diff --git a/lib/Target/Mips/MipsTargetMachine.cpp b/lib/Target/Mips/MipsTargetMachine.cpp
index c349ea7dae..984c58eb6c 100644
--- a/lib/Target/Mips/MipsTargetMachine.cpp
+++ b/lib/Target/Mips/MipsTargetMachine.cpp
@@ -171,12 +171,12 @@ public:
     return *getMipsTargetMachine().getSubtargetImpl();
   }
 
-  virtual void addIRPasses();
-  virtual bool addInstSelector();
-  virtual void addMachineSSAOptimization();
-  virtual bool addPreEmitPass();
+  void addIRPasses() override;
+  bool addInstSelector() override;
+  void addMachineSSAOptimization() override;
+  bool addPreEmitPass() override;
 
-  virtual bool addPreRegAlloc();
+  bool addPreRegAlloc() override;
 
 };
 } // namespace
diff --git a/lib/Target/Mips/MipsTargetMachine.h b/lib/Target/Mips/MipsTargetMachine.h
index 6ba8b19da6..a5aa39bc9f 100644
--- a/lib/Target/Mips/MipsTargetMachine.h
+++ b/lib/Target/Mips/MipsTargetMachine.h
@@ -55,39 +55,38 @@ public:
 
   virtual ~MipsTargetMachine() {}
 
-  virtual void addAnalysisPasses(PassManagerBase &PM);
+  void addAnalysisPasses(PassManagerBase &PM) override;
 
-  virtual const MipsInstrInfo *getInstrInfo() const
+  const MipsInstrInfo *getInstrInfo() const override
   { return InstrInfo.get(); }
-  virtual const TargetFrameLowering *getFrameLowering() const
+  const TargetFrameLowering *getFrameLowering() const override
   { return FrameLowering.get(); }
-  virtual const MipsSubtarget *getSubtargetImpl() const
+  const MipsSubtarget *getSubtargetImpl() const override
   { return &Subtarget; }
-  virtual const DataLayout *getDataLayout()    const
+  const DataLayout *getDataLayout()    const override
   { return &DL;}
 
-  virtual const InstrItineraryData *getInstrItineraryData() const {
+  const InstrItineraryData *getInstrItineraryData() const override {
     return Subtarget.inMips16Mode() ? nullptr : &InstrItins;
   }
 
-  virtual MipsJITInfo *getJITInfo()
-  { return &JITInfo; }
+  MipsJITInfo *getJITInfo() override { return &JITInfo; }
 
-  virtual const MipsRegisterInfo *getRegisterInfo()  const {
+  const MipsRegisterInfo *getRegisterInfo()  const override {
     return &InstrInfo->getRegisterInfo();
   }
 
-  virtual const MipsTargetLowering *getTargetLowering() const {
+  const MipsTargetLowering *getTargetLowering() const override {
     return TLInfo.get();
   }
 
-  virtual const MipsSelectionDAGInfo* getSelectionDAGInfo() const {
+  const MipsSelectionDAGInfo* getSelectionDAGInfo() const override {
     return &TSInfo;
   }
 
   // Pass Pipeline Configuration
-  virtual TargetPassConfig *createPassConfig(PassManagerBase &PM);
-  virtual bool addCodeEmitter(PassManagerBase &PM, JITCodeEmitter &JCE);
+  TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
+  bool addCodeEmitter(PassManagerBase &PM, JITCodeEmitter &JCE) override;
 
   // Set helper classes
   void setHelperClassesMips16();
diff --git a/lib/Target/Mips/MipsTargetStreamer.h b/lib/Target/Mips/MipsTargetStreamer.h
index 198888cf52..e649a4d14f 100644
--- a/lib/Target/Mips/MipsTargetStreamer.h
+++ b/lib/Target/Mips/MipsTargetStreamer.h
@@ -47,6 +47,9 @@ public:
   virtual void emitDirectiveSetMips64() = 0;
   virtual void emitDirectiveSetMips64R2() = 0;
   virtual void emitDirectiveSetDsp() = 0;
+
+  // PIC support
+  virtual void emitDirectiveCpload(unsigned RegNo) = 0;
 };
 
 // This part is for ascii assembly output
@@ -55,34 +58,37 @@ class MipsTargetAsmStreamer : public MipsTargetStreamer {
 
 public:
   MipsTargetAsmStreamer(MCStreamer &S, formatted_raw_ostream &OS);
-  virtual void emitDirectiveSetMicroMips();
-  virtual void emitDirectiveSetNoMicroMips();
-  virtual void emitDirectiveSetMips16();
-  virtual void emitDirectiveSetNoMips16();
-
-  virtual void emitDirectiveSetReorder();
-  virtual void emitDirectiveSetNoReorder();
-  virtual void emitDirectiveSetMacro();
-  virtual void emitDirectiveSetNoMacro();
-  virtual void emitDirectiveSetAt();
-  virtual void emitDirectiveSetNoAt();
-  virtual void emitDirectiveEnd(StringRef Name);
-
-  virtual void emitDirectiveEnt(const MCSymbol &Symbol);
-  virtual void emitDirectiveAbiCalls();
-  virtual void emitDirectiveNaN2008();
-  virtual void emitDirectiveNaNLegacy();
-  virtual void emitDirectiveOptionPic0();
-  virtual void emitDirectiveOptionPic2();
-  virtual void emitFrame(unsigned StackReg, unsigned StackSize,
-                         unsigned ReturnReg);
-  virtual void emitMask(unsigned CPUBitmask, int CPUTopSavedRegOff);
-  virtual void emitFMask(unsigned FPUBitmask, int FPUTopSavedRegOff);
-
-  virtual void emitDirectiveSetMips32R2();
-  virtual void emitDirectiveSetMips64();
-  virtual void emitDirectiveSetMips64R2();
-  virtual void emitDirectiveSetDsp();
+  void emitDirectiveSetMicroMips() override;
+  void emitDirectiveSetNoMicroMips() override;
+  void emitDirectiveSetMips16() override;
+  void emitDirectiveSetNoMips16() override;
+
+  void emitDirectiveSetReorder() override;
+  void emitDirectiveSetNoReorder() override;
+  void emitDirectiveSetMacro() override;
+  void emitDirectiveSetNoMacro() override;
+  void emitDirectiveSetAt() override;
+  void emitDirectiveSetNoAt() override;
+  void emitDirectiveEnd(StringRef Name) override;
+
+  void emitDirectiveEnt(const MCSymbol &Symbol) override;
+  void emitDirectiveAbiCalls() override;
+  void emitDirectiveNaN2008() override;
+  void emitDirectiveNaNLegacy() override;
+  void emitDirectiveOptionPic0() override;
+  void emitDirectiveOptionPic2() override;
+  void emitFrame(unsigned StackReg, unsigned StackSize,
+                 unsigned ReturnReg) override;
+  void emitMask(unsigned CPUBitmask, int CPUTopSavedRegOff) override;
+  void emitFMask(unsigned FPUBitmask, int FPUTopSavedRegOff) override;
+
+  void emitDirectiveSetMips32R2() override;
+  void emitDirectiveSetMips64() override;
+  void emitDirectiveSetMips64R2() override;
+  void emitDirectiveSetDsp() override;
+
+  // PIC support
+  virtual void emitDirectiveCpload(unsigned RegNo);
 };
 
 // This part is for ELF object output
@@ -96,38 +102,46 @@ public:
   MCELFStreamer &getStreamer();
   MipsTargetELFStreamer(MCStreamer &S, const MCSubtargetInfo &STI);
 
-  virtual void emitLabel(MCSymbol *Symbol) override;
-  virtual void emitAssignment(MCSymbol *Symbol, const MCExpr *Value) override;
+  void emitLabel(MCSymbol *Symbol) override;
+  void emitAssignment(MCSymbol *Symbol, const MCExpr *Value) override;
   void finish() override;
 
-  virtual void emitDirectiveSetMicroMips();
-  virtual void emitDirectiveSetNoMicroMips();
-  virtual void emitDirectiveSetMips16();
-  virtual void emitDirectiveSetNoMips16();
-
-  virtual void emitDirectiveSetReorder();
-  virtual void emitDirectiveSetNoReorder();
-  virtual void emitDirectiveSetMacro();
-  virtual void emitDirectiveSetNoMacro();
-  virtual void emitDirectiveSetAt();
-  virtual void emitDirectiveSetNoAt();
-  virtual void emitDirectiveEnd(StringRef Name);
-
-  virtual void emitDirectiveEnt(const MCSymbol &Symbol);
-  virtual void emitDirectiveAbiCalls();
-  virtual void emitDirectiveNaN2008();
-  virtual void emitDirectiveNaNLegacy();
-  virtual void emitDirectiveOptionPic0();
-  virtual void emitDirectiveOptionPic2();
-  virtual void emitFrame(unsigned StackReg, unsigned StackSize,
-                         unsigned ReturnReg);
-  virtual void emitMask(unsigned CPUBitmask, int CPUTopSavedRegOff);
-  virtual void emitFMask(unsigned FPUBitmask, int FPUTopSavedRegOff);
-
-  virtual void emitDirectiveSetMips32R2();
-  virtual void emitDirectiveSetMips64();
-  virtual void emitDirectiveSetMips64R2();
-  virtual void emitDirectiveSetDsp();
+  void emitDirectiveSetMicroMips() override;
+  void emitDirectiveSetNoMicroMips() override;
+  void emitDirectiveSetMips16() override;
+  void emitDirectiveSetNoMips16() override;
+
+  void emitDirectiveSetReorder() override;
+  void emitDirectiveSetNoReorder() override;
+  void emitDirectiveSetMacro() override;
+  void emitDirectiveSetNoMacro() override;
+  void emitDirectiveSetAt() override;
+  void emitDirectiveSetNoAt() override;
+  void emitDirectiveEnd(StringRef Name) override;
+
+  void emitDirectiveEnt(const MCSymbol &Symbol) override;
+  void emitDirectiveAbiCalls() override;
+  void emitDirectiveNaN2008() override;
+  void emitDirectiveNaNLegacy() override;
+  void emitDirectiveOptionPic0() override;
+  void emitDirectiveOptionPic2() override;
+  void emitFrame(unsigned StackReg, unsigned StackSize,
+                 unsigned ReturnReg) override;
+  void emitMask(unsigned CPUBitmask, int CPUTopSavedRegOff) override;
+  void emitFMask(unsigned FPUBitmask, int FPUTopSavedRegOff) override;
+
+  void emitDirectiveSetMips32R2() override;
+  void emitDirectiveSetMips64() override;
+  void emitDirectiveSetMips64R2() override;
+  void emitDirectiveSetDsp() override;
+
+  // PIC support
+  virtual void emitDirectiveCpload(unsigned RegNo);
+
+protected:
+  bool isO32() const { return STI.getFeatureBits() & Mips::FeatureO32; }
+  bool isN32() const { return STI.getFeatureBits() & Mips::FeatureN32; }
+  bool isN64() const { return STI.getFeatureBits() & Mips::FeatureN64; }
 };
 }
 #endif
diff --git a/lib/Target/NVPTX/InstPrinter/NVPTXInstPrinter.h b/lib/Target/NVPTX/InstPrinter/NVPTXInstPrinter.h
index d43c3592d8..1fb3c57390 100644
--- a/lib/Target/NVPTX/InstPrinter/NVPTXInstPrinter.h
+++ b/lib/Target/NVPTX/InstPrinter/NVPTXInstPrinter.h
@@ -27,8 +27,8 @@ public:
   NVPTXInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII,
                    const MCRegisterInfo &MRI, const MCSubtargetInfo &STI);
 
-  virtual void printRegName(raw_ostream &OS, unsigned RegNo) const;
-  virtual void printInst(const MCInst *MI, raw_ostream &OS, StringRef Annot);
+  void printRegName(raw_ostream &OS, unsigned RegNo) const override;
+  void printInst(const MCInst *MI, raw_ostream &OS, StringRef Annot) override;
 
   // Autogenerated by tblgen.
   void printInstruction(const MCInst *MI, raw_ostream &O);
diff --git a/lib/Target/NVPTX/NVPTXAllocaHoisting.h b/lib/Target/NVPTX/NVPTXAllocaHoisting.h
index 22404b75c9..5b610687e3 100644
--- a/lib/Target/NVPTX/NVPTXAllocaHoisting.h
+++ b/lib/Target/NVPTX/NVPTXAllocaHoisting.h
@@ -30,17 +30,17 @@ public:
   static char ID; // Pass ID
   NVPTXAllocaHoisting() : FunctionPass(ID) {}
 
-  void getAnalysisUsage(AnalysisUsage &AU) const {
+  void getAnalysisUsage(AnalysisUsage &AU) const override {
     AU.addRequired<DataLayoutPass>();
     AU.addPreserved("stack-protector");
     AU.addPreserved<MachineFunctionAnalysis>();
   }
 
-  virtual const char *getPassName() const {
+  const char *getPassName() const override {
     return "NVPTX specific alloca hoisting";
   }
 
-  virtual bool runOnFunction(Function &function);
+  bool runOnFunction(Function &function) override;
 };
 
 extern FunctionPass *createAllocaHoisting();
diff --git a/lib/Target/NVPTX/NVPTXAsmPrinter.h b/lib/Target/NVPTX/NVPTXAsmPrinter.h
index 4f1b7a12fb..a9f9bdd6d3 100644
--- a/lib/Target/NVPTX/NVPTXAsmPrinter.h
+++ b/lib/Target/NVPTX/NVPTXAsmPrinter.h
@@ -189,20 +189,20 @@ class LLVM_LIBRARY_VISIBILITY NVPTXAsmPrinter : public AsmPrinter {
 
   friend class AggBuffer;
 
-  virtual void emitSrcInText(StringRef filename, unsigned line);
+  void emitSrcInText(StringRef filename, unsigned line);
 
 private:
-  virtual const char *getPassName() const { return "NVPTX Assembly Printer"; }
+  const char *getPassName() const override { return "NVPTX Assembly Printer"; }
 
   const Function *F;
   std::string CurrentFnName;
 
-  void EmitFunctionEntryLabel();
-  void EmitFunctionBodyStart();
-  void EmitFunctionBodyEnd();
-  void emitImplicitDef(const MachineInstr *MI) const;
+  void EmitFunctionEntryLabel() override;
+  void EmitFunctionBodyStart() override;
+  void EmitFunctionBodyEnd() override;
+  void emitImplicitDef(const MachineInstr *MI) const override;
 
-  void EmitInstruction(const MachineInstr *);
+  void EmitInstruction(const MachineInstr *) override;
   void lowerToMCInst(const MachineInstr *MI, MCInst &OutMI);
   bool lowerOperand(const MachineOperand &MO, MCOperand &MCOp);
   MCOperand GetSymbolRef(const MCSymbol *Symbol);
@@ -234,15 +234,15 @@ private:
   void printReturnValStr(const MachineFunction &MF, raw_ostream &O);
   bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
                        unsigned AsmVariant, const char *ExtraCode,
-                       raw_ostream &);
+                       raw_ostream &) override;
   void printOperand(const MachineInstr *MI, int opNum, raw_ostream &O,
                     const char *Modifier = nullptr);
   bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo,
                              unsigned AsmVariant, const char *ExtraCode,
-                             raw_ostream &);
+                             raw_ostream &) override;
 protected:
-  bool doInitialization(Module &M);
-  bool doFinalization(Module &M);
+  bool doInitialization(Module &M) override;
+  bool doFinalization(Module &M) override;
 
 private:
   std::string CurrentBankselLabelInBasicBlock;
diff --git a/lib/Target/NVPTX/NVPTXAssignValidGlobalNames.cpp b/lib/Target/NVPTX/NVPTXAssignValidGlobalNames.cpp
index 158c482468..962b123120 100644
--- a/lib/Target/NVPTX/NVPTXAssignValidGlobalNames.cpp
+++ b/lib/Target/NVPTX/NVPTXAssignValidGlobalNames.cpp
@@ -33,7 +33,7 @@ public:
   static char ID;
   NVPTXAssignValidGlobalNames() : ModulePass(ID) {}
 
-  virtual bool runOnModule(Module &M);
+  bool runOnModule(Module &M) override;
 
   /// \brief Clean up the name to remove symbols invalid in PTX.
   std::string cleanUpName(StringRef Name);
diff --git a/lib/Target/NVPTX/NVPTXFrameLowering.h b/lib/Target/NVPTX/NVPTXFrameLowering.h
index 819f1dd3f4..2ae6d72720 100644
--- a/lib/Target/NVPTX/NVPTXFrameLowering.h
+++ b/lib/Target/NVPTX/NVPTXFrameLowering.h
@@ -28,13 +28,13 @@ public:
       : TargetFrameLowering(TargetFrameLowering::StackGrowsUp, 8, 0), tm(_tm),
         is64bit(_is64bit) {}
 
-  virtual bool hasFP(const MachineFunction &MF) const;
-  virtual void emitPrologue(MachineFunction &MF) const;
-  virtual void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
+  bool hasFP(const MachineFunction &MF) const override;
+  void emitPrologue(MachineFunction &MF) const override;
+  void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override;
 
   void eliminateCallFramePseudoInstr(MachineFunction &MF,
-                                     MachineBasicBlock &MBB,
-                                     MachineBasicBlock::iterator I) const;
+                                  MachineBasicBlock &MBB,
+                                  MachineBasicBlock::iterator I) const override;
 };
 
 } // End llvm namespace
diff --git a/lib/Target/NVPTX/NVPTXGenericToNVVM.cpp b/lib/Target/NVPTX/NVPTXGenericToNVVM.cpp
index 4209ba3602..023dd5e48c 100644
--- a/lib/Target/NVPTX/NVPTXGenericToNVVM.cpp
+++ b/lib/Target/NVPTX/NVPTXGenericToNVVM.cpp
@@ -40,10 +40,9 @@ public:
 
   GenericToNVVM() : ModulePass(ID) {}
 
-  virtual bool runOnModule(Module &M);
+  bool runOnModule(Module &M) override;
 
-  virtual void getAnalysisUsage(AnalysisUsage &AU) const {
-  }
+  void getAnalysisUsage(AnalysisUsage &AU) const override {}
 
 private:
   Value *getOrInsertCVTA(Module *M, Function *F, GlobalVariable *GV,
diff --git a/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp b/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
index ada4c22387..cd308806c3 100644
--- a/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
+++ b/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
@@ -1084,8 +1084,7 @@ SDNode *NVPTXDAGToDAGISel::SelectLDGLDUVector(SDNode *N) {
     }
 
     SDValue Ops[] = { Addr, Chain };
-    LD = CurDAG->getMachineNode(Opcode, DL, N->getVTList(),
-                                ArrayRef<SDValue>(Ops, 2));
+    LD = CurDAG->getMachineNode(Opcode, DL, N->getVTList(), Ops);
   } else if (Subtarget.is64Bit()
                  ? SelectADDRri64(Op1.getNode(), Op1, Base, Offset)
                  : SelectADDRri(Op1.getNode(), Op1, Base, Offset)) {
@@ -1271,8 +1270,7 @@ SDNode *NVPTXDAGToDAGISel::SelectLDGLDUVector(SDNode *N) {
 
     SDValue Ops[] = { Base, Offset, Chain };
 
-    LD = CurDAG->getMachineNode(Opcode, DL, N->getVTList(),
-                                ArrayRef<SDValue>(Ops, 3));
+    LD = CurDAG->getMachineNode(Opcode, DL, N->getVTList(), Ops);
   } else {
     if (Subtarget.is64Bit()) {
       switch (N->getOpcode()) {
@@ -1455,8 +1453,7 @@ SDNode *NVPTXDAGToDAGISel::SelectLDGLDUVector(SDNode *N) {
     }
 
     SDValue Ops[] = { Op1, Chain };
-    LD = CurDAG->getMachineNode(Opcode, DL, N->getVTList(),
-                                ArrayRef<SDValue>(Ops, 2));
+    LD = CurDAG->getMachineNode(Opcode, DL, N->getVTList(), Ops);
   }
 
   MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
diff --git a/lib/Target/NVPTX/NVPTXISelDAGToDAG.h b/lib/Target/NVPTX/NVPTXISelDAGToDAG.h
index 676fda4036..11f92e79d9 100644
--- a/lib/Target/NVPTX/NVPTXISelDAGToDAG.h
+++ b/lib/Target/NVPTX/NVPTXISelDAGToDAG.h
@@ -44,19 +44,20 @@ public:
                              CodeGenOpt::Level   OptLevel);
 
   // Pass Name
-  virtual const char *getPassName() const {
+  const char *getPassName() const override {
     return "NVPTX DAG->DAG Pattern Instruction Selection";
   }
 
   const NVPTXSubtarget &Subtarget;
 
-  virtual bool SelectInlineAsmMemoryOperand(
-      const SDValue &Op, char ConstraintCode, std::vector<SDValue> &OutOps);
+  bool SelectInlineAsmMemoryOperand(const SDValue &Op,
+                                    char ConstraintCode,
+                                    std::vector<SDValue> &OutOps) override;
 private:
 // Include the pieces autogenerated from the target description.
 #include "NVPTXGenDAGISel.inc"
 
-  SDNode *Select(SDNode *N);
+  SDNode *Select(SDNode *N) override;
   SDNode *SelectIntrinsicNoChain(SDNode *N);
   SDNode *SelectTexSurfHandle(SDNode *N);
   SDNode *SelectLoad(SDNode *N);
diff --git a/lib/Target/NVPTX/NVPTXISelLowering.h b/lib/Target/NVPTX/NVPTXISelLowering.h
index 38f6437542..7bad8a28f3 100644
--- a/lib/Target/NVPTX/NVPTXISelLowering.h
+++ b/lib/Target/NVPTX/NVPTXISelLowering.h
@@ -173,68 +173,70 @@ enum NodeType {
 class NVPTXTargetLowering : public TargetLowering {
 public:
   explicit NVPTXTargetLowering(NVPTXTargetMachine &TM);
-  virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
+  SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
 
   SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerGlobalAddress(const GlobalValue *GV, int64_t Offset,
                              SelectionDAG &DAG) const;
 
-  virtual const char *getTargetNodeName(unsigned Opcode) const;
+  const char *getTargetNodeName(unsigned Opcode) const override;
 
   bool isTypeSupportedInIntrinsic(MVT VT) const;
 
   bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I,
-                          unsigned Intrinsic) const;
+                          unsigned Intrinsic) const override;
 
   /// isLegalAddressingMode - Return true if the addressing mode represented
   /// by AM is legal for this target, for a load/store of the specified type
   /// Used to guide target specific optimizations, like loop strength
   /// reduction (LoopStrengthReduce.cpp) and memory optimization for
   /// address mode (CodeGenPrepare.cpp)
-  virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const;
+  bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const override;
 
   /// getFunctionAlignment - Return the Log2 alignment of this function.
-  virtual unsigned getFunctionAlignment(const Function *F) const;
+  unsigned getFunctionAlignment(const Function *F) const;
 
-  virtual EVT getSetCCResultType(LLVMContext &, EVT VT) const {
+  EVT getSetCCResultType(LLVMContext &, EVT VT) const override {
     if (VT.isVector())
       return MVT::getVectorVT(MVT::i1, VT.getVectorNumElements());
     return MVT::i1;
   }
 
-  ConstraintType getConstraintType(const std::string &Constraint) const;
+  ConstraintType
+  getConstraintType(const std::string &Constraint) const override;
   std::pair<unsigned, const TargetRegisterClass *>
-  getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const;
+  getRegForInlineAsmConstraint(const std::string &Constraint,
+                               MVT VT) const override;
 
-  virtual SDValue LowerFormalArguments(
+  SDValue LowerFormalArguments(
       SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
       const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG,
-      SmallVectorImpl<SDValue> &InVals) const;
+      SmallVectorImpl<SDValue> &InVals) const override;
 
-  virtual SDValue
-  LowerCall(CallLoweringInfo &CLI, SmallVectorImpl<SDValue> &InVals) const;
+  SDValue LowerCall(CallLoweringInfo &CLI,
+                    SmallVectorImpl<SDValue> &InVals) const override;
 
   std::string getPrototype(Type *, const ArgListTy &,
                            const SmallVectorImpl<ISD::OutputArg> &,
                            unsigned retAlignment,
                            const ImmutableCallSite *CS) const;
 
-  virtual SDValue
+  SDValue
   LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
               const SmallVectorImpl<ISD::OutputArg> &Outs,
               const SmallVectorImpl<SDValue> &OutVals, SDLoc dl,
-              SelectionDAG &DAG) const;
+              SelectionDAG &DAG) const override;
 
-  virtual void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
-                                            std::vector<SDValue> &Ops,
-                                            SelectionDAG &DAG) const;
+  void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
+                                    std::vector<SDValue> &Ops,
+                                    SelectionDAG &DAG) const override;
 
   NVPTXTargetMachine *nvTM;
 
   // PTX always uses 32-bit shift amounts
-  virtual MVT getScalarShiftAmountTy(EVT LHSTy) const { return MVT::i32; }
+  MVT getScalarShiftAmountTy(EVT LHSTy) const override { return MVT::i32; }
 
-  virtual bool shouldSplitVectorType(EVT VT) const override;
+  bool shouldSplitVectorType(EVT VT) const override;
 
 private:
   const NVPTXSubtarget &nvptxSubtarget; // cache the subtarget here
@@ -253,8 +255,8 @@ private:
   SDValue LowerSTOREi1(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerSTOREVector(SDValue Op, SelectionDAG &DAG) const;
 
-  virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
-                                  SelectionDAG &DAG) const;
+  void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
+                          SelectionDAG &DAG) const override;
 
   unsigned getArgumentAlignment(SDValue Callee, const ImmutableCallSite *CS,
                                 Type *Ty, unsigned Idx) const;
diff --git a/lib/Target/NVPTX/NVPTXImageOptimizer.cpp b/lib/Target/NVPTX/NVPTXImageOptimizer.cpp
index 5b07763814..397f4bccfe 100644
--- a/lib/Target/NVPTX/NVPTXImageOptimizer.cpp
+++ b/lib/Target/NVPTX/NVPTXImageOptimizer.cpp
@@ -33,7 +33,7 @@ private:
 public:
   NVPTXImageOptimizer();
 
-  bool runOnFunction(Function &F);
+  bool runOnFunction(Function &F) override;
 
 private:
   bool replaceIsTypePSampler(Instruction &I);
diff --git a/lib/Target/NVPTX/NVPTXInstrInfo.h b/lib/Target/NVPTX/NVPTXInstrInfo.h
index 600fc5c60a..88a9e45f25 100644
--- a/lib/Target/NVPTX/NVPTXInstrInfo.h
+++ b/lib/Target/NVPTX/NVPTXInstrInfo.h
@@ -30,7 +30,7 @@ class NVPTXInstrInfo : public NVPTXGenInstrInfo {
 public:
   explicit NVPTXInstrInfo(NVPTXTargetMachine &TM);
 
-  virtual const NVPTXRegisterInfo &getRegisterInfo() const { return RegInfo; }
+  const NVPTXRegisterInfo &getRegisterInfo() const { return RegInfo; }
 
   /* The following virtual functions are used in register allocation.
    * They are not implemented because the existing interface and the logic
@@ -50,9 +50,9 @@ public:
    *                               const TargetRegisterClass *RC) const;
    */
 
-  virtual void copyPhysReg(
+  void copyPhysReg(
       MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL,
-      unsigned DestReg, unsigned SrcReg, bool KillSrc) const;
+      unsigned DestReg, unsigned SrcReg, bool KillSrc) const override;
   virtual bool isMoveInstr(const MachineInstr &MI, unsigned &SrcReg,
                            unsigned &DestReg) const;
   bool isLoadInstr(const MachineInstr &MI, unsigned &AddrSpace) const;
@@ -61,13 +61,13 @@ public:
 
   virtual bool CanTailMerge(const MachineInstr *MI) const;
   // Branch analysis.
-  virtual bool AnalyzeBranch(
+  bool AnalyzeBranch(
       MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB,
-      SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const;
-  virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
-  virtual unsigned InsertBranch(
+      SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const override;
+  unsigned RemoveBranch(MachineBasicBlock &MBB) const override;
+  unsigned InsertBranch(
       MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB,
-      const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const;
+      const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const override;
   unsigned getLdStCodeAddrSpace(const MachineInstr &MI) const {
     return MI.getOperand(2).getImm();
   }
diff --git a/lib/Target/NVPTX/NVPTXLowerAggrCopies.h b/lib/Target/NVPTX/NVPTXLowerAggrCopies.h
index c9aa87d53a..5ec1fc9696 100644
--- a/lib/Target/NVPTX/NVPTXLowerAggrCopies.h
+++ b/lib/Target/NVPTX/NVPTXLowerAggrCopies.h
@@ -27,17 +27,17 @@ struct NVPTXLowerAggrCopies : public FunctionPass {
 
   NVPTXLowerAggrCopies() : FunctionPass(ID) {}
 
-  void getAnalysisUsage(AnalysisUsage &AU) const {
+  void getAnalysisUsage(AnalysisUsage &AU) const override {
     AU.addRequired<DataLayoutPass>();
     AU.addPreserved("stack-protector");
     AU.addPreserved<MachineFunctionAnalysis>();
   }
 
-  virtual bool runOnFunction(Function &F);
+  bool runOnFunction(Function &F) override;
 
   static const unsigned MaxAggrCopySize = 128;
 
-  virtual const char *getPassName() const {
+  const char *getPassName() const override {
     return "Lower aggregate copies/intrinsics into loops";
   }
 };
diff --git a/lib/Target/NVPTX/NVPTXMCExpr.h b/lib/Target/NVPTX/NVPTXMCExpr.h
index 8e0e225f58..0ee018cc7e 100644
--- a/lib/Target/NVPTX/NVPTXMCExpr.h
+++ b/lib/Target/NVPTX/NVPTXMCExpr.h
@@ -61,18 +61,18 @@ public:
 
 /// @}
 
-  void PrintImpl(raw_ostream &OS) const;
+  void PrintImpl(raw_ostream &OS) const override;
   bool EvaluateAsRelocatableImpl(MCValue &Res,
-                                 const MCAsmLayout *Layout) const {
+                                 const MCAsmLayout *Layout) const override {
     return false;
   }
-  void AddValueSymbols(MCAssembler *) const {};
-  const MCSection *FindAssociatedSection() const {
+  void AddValueSymbols(MCAssembler *) const override {};
+  const MCSection *FindAssociatedSection() const override {
     return nullptr;
   }
 
   // There are no TLS NVPTXMCExprs at the moment.
-  void fixELFSymbolsInTLSFixups(MCAssembler &Asm) const {}
+  void fixELFSymbolsInTLSFixups(MCAssembler &Asm) const override {}
 
   static bool classof(const MCExpr *E) {
     return E->getKind() == MCExpr::Target;
diff --git a/lib/Target/NVPTX/NVPTXPrologEpilogPass.cpp b/lib/Target/NVPTX/NVPTXPrologEpilogPass.cpp
index c2ae5d3adf..348ab0c4bf 100644
--- a/lib/Target/NVPTX/NVPTXPrologEpilogPass.cpp
+++ b/lib/Target/NVPTX/NVPTXPrologEpilogPass.cpp
@@ -33,7 +33,7 @@ public:
   static char ID;
   NVPTXPrologEpilogPass() : MachineFunctionPass(ID) {}
 
-  virtual bool runOnMachineFunction(MachineFunction &MF);
+  bool runOnMachineFunction(MachineFunction &MF) override;
 
 private:
   void calculateFrameObjectOffsets(MachineFunction &Fn);
diff --git a/lib/Target/NVPTX/NVPTXRegisterInfo.cpp b/lib/Target/NVPTX/NVPTXRegisterInfo.cpp
index 387e5a9f70..62f288b67c 100644
--- a/lib/Target/NVPTX/NVPTXRegisterInfo.cpp
+++ b/lib/Target/NVPTX/NVPTXRegisterInfo.cpp
@@ -84,13 +84,6 @@ NVPTXRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
   return CalleeSavedRegs;
 }
 
-// NVPTX Callee Saved Reg Classes
-const TargetRegisterClass *const *
-NVPTXRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
-  static const TargetRegisterClass *const CalleeSavedRegClasses[] = { nullptr };
-  return CalleeSavedRegClasses;
-}
-
 BitVector NVPTXRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
   BitVector Reserved(getNumRegs());
   return Reserved;
@@ -113,12 +106,6 @@ void NVPTXRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
   MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
 }
 
-int NVPTXRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
-  return 0;
-}
-
 unsigned NVPTXRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
   return NVPTX::VRFrame;
 }
-
-unsigned NVPTXRegisterInfo::getRARegister() const { return 0; }
diff --git a/lib/Target/NVPTX/NVPTXRegisterInfo.h b/lib/Target/NVPTX/NVPTXRegisterInfo.h
index 4aff42ea83..a7594be121 100644
--- a/lib/Target/NVPTX/NVPTXRegisterInfo.h
+++ b/lib/Target/NVPTX/NVPTXRegisterInfo.h
@@ -41,22 +41,16 @@ public:
   //------------------------------------------------------
 
   // NVPTX callee saved registers
-  virtual const MCPhysReg *
-  getCalleeSavedRegs(const MachineFunction *MF = nullptr) const;
+  const MCPhysReg *
+  getCalleeSavedRegs(const MachineFunction *MF = nullptr) const override;
 
-  // NVPTX callee saved register classes
-  virtual const TargetRegisterClass *const *
-  getCalleeSavedRegClasses(const MachineFunction *MF) const;
+  BitVector getReservedRegs(const MachineFunction &MF) const override;
 
-  virtual BitVector getReservedRegs(const MachineFunction &MF) const;
+  void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj,
+                           unsigned FIOperandNum,
+                           RegScavenger *RS = nullptr) const override;
 
-  virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj,
-                                   unsigned FIOperandNum,
-                                   RegScavenger *RS = nullptr) const;
-
-  virtual int getDwarfRegNum(unsigned RegNum, bool isEH) const;
-  virtual unsigned getFrameRegister(const MachineFunction &MF) const;
-  virtual unsigned getRARegister() const;
+  unsigned getFrameRegister(const MachineFunction &MF) const override;
 
   ManagedStringPool *getStrPool() const {
     return const_cast<ManagedStringPool *>(&ManagedStrPool);
diff --git a/lib/Target/NVPTX/NVPTXReplaceImageHandles.cpp b/lib/Target/NVPTX/NVPTXReplaceImageHandles.cpp
index f05f18880e..afd53a6a84 100644
--- a/lib/Target/NVPTX/NVPTXReplaceImageHandles.cpp
+++ b/lib/Target/NVPTX/NVPTXReplaceImageHandles.cpp
@@ -32,7 +32,7 @@ private:
 public:
   NVPTXReplaceImageHandles();
 
-  bool runOnMachineFunction(MachineFunction &MF);
+  bool runOnMachineFunction(MachineFunction &MF) override;
 private:
   bool processInstr(MachineInstr &MI);
   void replaceImageHandle(MachineOperand &Op, MachineFunction &MF);
diff --git a/lib/Target/NVPTX/NVPTXSection.h b/lib/Target/NVPTX/NVPTXSection.h
index f8a692e9b1..aa0436bf0d 100644
--- a/lib/Target/NVPTX/NVPTXSection.h
+++ b/lib/Target/NVPTX/NVPTXSection.h
@@ -31,16 +31,16 @@ public:
 
   /// Override this as NVPTX has its own way of printing switching
   /// to a section.
-  virtual void PrintSwitchToSection(const MCAsmInfo &MAI,
-                                    raw_ostream &OS,
-                                    const MCExpr *Subsection) const {}
+  void PrintSwitchToSection(const MCAsmInfo &MAI,
+                            raw_ostream &OS,
+                            const MCExpr *Subsection) const override {}
 
   /// Base address of PTX sections is zero.
-  virtual bool isBaseAddressKnownZero() const { return true; }
-  virtual bool UseCodeAlign() const { return false; }
-  virtual bool isVirtualSection() const { return false; }
-  virtual std::string getLabelBeginName() const { return ""; }
-  virtual std::string getLabelEndName() const { return ""; }
+  bool isBaseAddressKnownZero() const override { return true; }
+  bool UseCodeAlign() const override { return false; }
+  bool isVirtualSection() const override { return false; }
+  std::string getLabelBeginName() const override { return ""; }
+  std::string getLabelEndName() const override { return ""; }
 };
 
 } // end namespace llvm
diff --git a/lib/Target/NVPTX/NVPTXTargetMachine.cpp b/lib/Target/NVPTX/NVPTXTargetMachine.cpp
index 97dbde928b..0cc5c51629 100644
--- a/lib/Target/NVPTX/NVPTXTargetMachine.cpp
+++ b/lib/Target/NVPTX/NVPTXTargetMachine.cpp
@@ -115,14 +115,14 @@ public:
     return getTM<NVPTXTargetMachine>();
   }
 
-  virtual void addIRPasses();
-  virtual bool addInstSelector();
-  virtual bool addPreRegAlloc();
-  virtual bool addPostRegAlloc();
-
-  virtual FunctionPass *createTargetRegisterAllocator(bool) override;
-  virtual void addFastRegAlloc(FunctionPass *RegAllocPass);
-  virtual void addOptimizedRegAlloc(FunctionPass *RegAllocPass);
+  void addIRPasses() override;
+  bool addInstSelector() override;
+  bool addPreRegAlloc() override;
+  bool addPostRegAlloc() override;
+
+  FunctionPass *createTargetRegisterAllocator(bool) override;
+  void addFastRegAlloc(FunctionPass *RegAllocPass) override;
+  void addOptimizedRegAlloc(FunctionPass *RegAllocPass) override;
 };
 } // end anonymous namespace
 
diff --git a/lib/Target/NVPTX/NVPTXTargetMachine.h b/lib/Target/NVPTX/NVPTXTargetMachine.h
index 5fbcf735b4..2db7c18617 100644
--- a/lib/Target/NVPTX/NVPTXTargetMachine.h
+++ b/lib/Target/NVPTX/NVPTXTargetMachine.h
@@ -51,22 +51,22 @@ public:
                      const TargetOptions &Options, Reloc::Model RM,
                      CodeModel::Model CM, CodeGenOpt::Level OP, bool is64bit);
 
-  virtual const TargetFrameLowering *getFrameLowering() const {
+  const TargetFrameLowering *getFrameLowering() const override {
     return &FrameLowering;
   }
-  virtual const NVPTXInstrInfo *getInstrInfo() const { return &InstrInfo; }
-  virtual const DataLayout *getDataLayout() const { return &DL; }
-  virtual const NVPTXSubtarget *getSubtargetImpl() const { return &Subtarget; }
+  const NVPTXInstrInfo *getInstrInfo() const override { return &InstrInfo; }
+  const DataLayout *getDataLayout() const override { return &DL; }
+  const NVPTXSubtarget *getSubtargetImpl() const override { return &Subtarget; }
 
-  virtual const NVPTXRegisterInfo *getRegisterInfo() const {
+  const NVPTXRegisterInfo *getRegisterInfo() const override {
     return &(InstrInfo.getRegisterInfo());
   }
 
-  virtual NVPTXTargetLowering *getTargetLowering() const {
+  NVPTXTargetLowering *getTargetLowering() const override {
     return const_cast<NVPTXTargetLowering *>(&TLInfo);
   }
 
-  virtual const TargetSelectionDAGInfo *getSelectionDAGInfo() const {
+  const TargetSelectionDAGInfo *getSelectionDAGInfo() const override {
     return &TSInfo;
   }
 
@@ -79,17 +79,17 @@ public:
     return const_cast<ManagedStringPool *>(&ManagedStrPool);
   }
 
-  virtual TargetPassConfig *createPassConfig(PassManagerBase &PM);
+  TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
 
   // Emission of machine code through JITCodeEmitter is not supported.
-  virtual bool addPassesToEmitMachineCode(PassManagerBase &, JITCodeEmitter &,
-                                          bool = true) {
+  bool addPassesToEmitMachineCode(PassManagerBase &, JITCodeEmitter &,
+                                  bool = true) override {
     return true;
   }
 
   // Emission of machine code through MCJIT is not supported.
-  virtual bool addPassesToEmitMC(PassManagerBase &, MCContext *&, raw_ostream &,
-                                 bool = true) {
+  bool addPassesToEmitMC(PassManagerBase &, MCContext *&, raw_ostream &,
+                         bool = true) override {
     return true;
   }
 
diff --git a/lib/Target/NVPTX/NVVMReflect.cpp b/lib/Target/NVPTX/NVVMReflect.cpp
index 62413fb58d..cb8bd72602 100644
--- a/lib/Target/NVPTX/NVVMReflect.cpp
+++ b/lib/Target/NVPTX/NVVMReflect.cpp
@@ -65,8 +65,10 @@ public:
     }
   }
 
-  void getAnalysisUsage(AnalysisUsage &AU) const { AU.setPreservesAll(); }
-  virtual bool runOnModule(Module &);
+  void getAnalysisUsage(AnalysisUsage &AU) const override {
+    AU.setPreservesAll();
+  }
+  bool runOnModule(Module &) override;
 
   void setVarMap();
 };
diff --git a/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp b/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
index c7a6431e8f..3ac037dc0f 100644
--- a/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
+++ b/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
@@ -230,7 +230,7 @@ class PPCAsmParser : public MCTargetAsmParser {
   bool MatchRegisterName(const AsmToken &Tok,
                          unsigned &RegNo, int64_t &IntVal);
 
-  virtual bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
+  bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
 
   const MCExpr *ExtractModifierFromExpr(const MCExpr *E,
                                         PPCMCExpr::VariantKind &Variant);
@@ -248,7 +248,7 @@ class PPCAsmParser : public MCTargetAsmParser {
   bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
                                SmallVectorImpl<MCParsedAsmOperand*> &Operands,
                                MCStreamer &Out, unsigned &ErrorInfo,
-                               bool MatchingInlineAsm);
+                               bool MatchingInlineAsm) override;
 
   void ProcessInstruction(MCInst &Inst,
                           const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
@@ -276,17 +276,18 @@ public:
     setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
   }
 
-  virtual bool ParseInstruction(ParseInstructionInfo &Info,
-                                StringRef Name, SMLoc NameLoc,
-                                SmallVectorImpl<MCParsedAsmOperand*> &Operands);
+  bool ParseInstruction(ParseInstructionInfo &Info,
+                        StringRef Name, SMLoc NameLoc,
+                        SmallVectorImpl<MCParsedAsmOperand*> &Operands) override;
 
-  virtual bool ParseDirective(AsmToken DirectiveID);
+  bool ParseDirective(AsmToken DirectiveID) override;
 
-  unsigned validateTargetOperandClass(MCParsedAsmOperand *Op, unsigned Kind);
+  unsigned validateTargetOperandClass(MCParsedAsmOperand *Op,
+                                      unsigned Kind) override;
 
-  virtual const MCExpr *applyModifierToExpr(const MCExpr *E,
-                                            MCSymbolRefExpr::VariantKind,
-                                            MCContext &Ctx);
+  const MCExpr *applyModifierToExpr(const MCExpr *E,
+                                    MCSymbolRefExpr::VariantKind,
+                                    MCContext &Ctx) override;
 };
 
 /// PPCOperand - Instances of this class represent a parsed PowerPC machine
@@ -351,10 +352,10 @@ public:
   }
 
   /// getStartLoc - Get the location of the first token of this operand.
-  SMLoc getStartLoc() const { return StartLoc; }
+  SMLoc getStartLoc() const override { return StartLoc; }
 
   /// getEndLoc - Get the location of the last token of this operand.
-  SMLoc getEndLoc() const { return EndLoc; }
+  SMLoc getEndLoc() const override { return EndLoc; }
 
   /// isPPC64 - True if this operand is for an instruction in 64-bit mode.
   bool isPPC64() const { return IsPPC64; }
@@ -379,7 +380,7 @@ public:
     return TLSReg.Sym;
   }
 
-  unsigned getReg() const {
+  unsigned getReg() const override {
     assert(isRegNumber() && "Invalid access!");
     return (unsigned) Imm.Val;
   }
@@ -404,8 +405,8 @@ public:
     return 7 - countTrailingZeros<uint64_t>(Imm.Val);
   }
 
-  bool isToken() const { return Kind == Token; }
-  bool isImm() const { return Kind == Immediate || Kind == Expression; }
+  bool isToken() const override { return Kind == Token; }
+  bool isImm() const override { return Kind == Immediate || Kind == Expression; }
   bool isU2Imm() const { return Kind == Immediate && isUInt<2>(getImm()); }
   bool isU5Imm() const { return Kind == Immediate && isUInt<5>(getImm()); }
   bool isS5Imm() const { return Kind == Immediate && isInt<5>(getImm()); }
@@ -438,8 +439,8 @@ public:
                                        && isUInt<5>(getImm())); }
   bool isCRBitMask() const { return Kind == Immediate && isUInt<8>(getImm()) &&
                                     isPowerOf2_32(getImm()); }
-  bool isMem() const { return false; }
-  bool isReg() const { return false; }
+  bool isMem() const override { return false; }
+  bool isReg() const override { return false; }
 
   void addRegOperands(MCInst &Inst, unsigned N) const {
     llvm_unreachable("addRegOperands");
@@ -545,7 +546,7 @@ public:
     return StringRef(Tok.Data, Tok.Length);
   }
 
-  virtual void print(raw_ostream &OS) const;
+  void print(raw_ostream &OS) const override;
 
   static PPCOperand *CreateToken(StringRef Str, SMLoc S, bool IsPPC64) {
     PPCOperand *Op = new PPCOperand(Token);
diff --git a/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.h b/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.h
index 914f8657c9..211a62813e 100644
--- a/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.h
+++ b/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.h
@@ -31,8 +31,8 @@ public:
     return IsDarwin;
   }
   
-  virtual void printRegName(raw_ostream &OS, unsigned RegNo) const;
-  virtual void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot);
+  void printRegName(raw_ostream &OS, unsigned RegNo) const override;
+  void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot) override;
   
   // Autogenerated by tblgen.
   void printInstruction(const MCInst *MI, raw_ostream &O);
diff --git a/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp b/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp
index f7309bbf0a..12584bea5a 100644
--- a/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp
+++ b/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp
@@ -77,9 +77,11 @@ public:
   PPCAsmBackend(const Target &T, bool isLittle) : MCAsmBackend(), TheTarget(T),
     IsLittleEndian(isLittle) {}
 
-  unsigned getNumFixupKinds() const { return PPC::NumTargetFixupKinds; }
+  unsigned getNumFixupKinds() const override {
+    return PPC::NumTargetFixupKinds;
+  }
 
-  const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const {
+  const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override {
     const static MCFixupKindInfo InfosBE[PPC::NumTargetFixupKinds] = {
       // name                    offset  bits  flags
       { "fixup_ppc_br24",        6,      24,   MCFixupKindInfo::FKF_IsPCRel },
@@ -110,7 +112,7 @@ public:
   }
 
   void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
-                  uint64_t Value, bool IsPCRel) const {
+                  uint64_t Value, bool IsPCRel) const override {
     Value = adjustFixupValue(Fixup.getKind(), Value);
     if (!Value) return;           // Doesn't change encoding.
 
@@ -126,7 +128,7 @@ public:
     }
   }
 
-  bool mayNeedRelaxation(const MCInst &Inst) const {
+  bool mayNeedRelaxation(const MCInst &Inst) const override {
     // FIXME.
     return false;
   }
@@ -134,18 +136,18 @@ public:
   bool fixupNeedsRelaxation(const MCFixup &Fixup,
                             uint64_t Value,
                             const MCRelaxableFragment *DF,
-                            const MCAsmLayout &Layout) const {
+                            const MCAsmLayout &Layout) const override {
     // FIXME.
     llvm_unreachable("relaxInstruction() unimplemented");
   }
 
 
-  void relaxInstruction(const MCInst &Inst, MCInst &Res) const {
+  void relaxInstruction(const MCInst &Inst, MCInst &Res) const override {
     // FIXME.
     llvm_unreachable("relaxInstruction() unimplemented");
   }
 
-  bool writeNopData(uint64_t Count, MCObjectWriter *OW) const {
+  bool writeNopData(uint64_t Count, MCObjectWriter *OW) const override {
     uint64_t NumNops = Count / 4;
     for (uint64_t i = 0; i != NumNops; ++i)
       OW->Write32(0x60000000);
@@ -180,7 +182,7 @@ namespace {
   public:
     DarwinPPCAsmBackend(const Target &T) : PPCAsmBackend(T, false) { }
 
-    MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
+    MCObjectWriter *createObjectWriter(raw_ostream &OS) const override {
       bool is64 = getPointerSize() == 8;
       return createPPCMachObjectWriter(
           OS,
@@ -197,7 +199,7 @@ namespace {
       PPCAsmBackend(T, IsLittleEndian), OSABI(OSABI) { }
 
 
-    MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
+    MCObjectWriter *createObjectWriter(raw_ostream &OS) const override {
       bool is64 = getPointerSize() == 8;
       return createPPCELFObjectWriter(OS, is64, isLittleEndian(), OSABI);
     }
diff --git a/lib/Target/PowerPC/MCTargetDesc/PPCMCAsmInfo.h b/lib/Target/PowerPC/MCTargetDesc/PPCMCAsmInfo.h
index cee2cb72a9..754330b2c6 100644
--- a/lib/Target/PowerPC/MCTargetDesc/PPCMCAsmInfo.h
+++ b/lib/Target/PowerPC/MCTargetDesc/PPCMCAsmInfo.h
@@ -21,13 +21,13 @@ namespace llvm {
 class Triple;
 
   class PPCMCAsmInfoDarwin : public MCAsmInfoDarwin {
-    virtual void anchor();
+    void anchor() override;
   public:
     explicit PPCMCAsmInfoDarwin(bool is64Bit, const Triple&);
   };
 
   class PPCLinuxMCAsmInfo : public MCAsmInfoELF {
-    virtual void anchor();
+    void anchor() override;
   public:
     explicit PPCLinuxMCAsmInfo(bool is64Bit, const Triple&);
   };
diff --git a/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp b/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp
index 4bfde70f0d..a4983ad672 100644
--- a/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp
+++ b/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp
@@ -89,7 +89,7 @@ public:
                                  const MCSubtargetInfo &STI) const;
   void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
                          SmallVectorImpl<MCFixup> &Fixups,
-                         const MCSubtargetInfo &STI) const {
+                         const MCSubtargetInfo &STI) const override {
     // For fast-isel, a float COPY_TO_REGCLASS can survive this long.
     // It's just a nop to keep the register classes happy, so don't
     // generate anything.
diff --git a/lib/Target/PowerPC/MCTargetDesc/PPCMCExpr.h b/lib/Target/PowerPC/MCTargetDesc/PPCMCExpr.h
index 5fc7918334..3421b91577 100644
--- a/lib/Target/PowerPC/MCTargetDesc/PPCMCExpr.h
+++ b/lib/Target/PowerPC/MCTargetDesc/PPCMCExpr.h
@@ -76,16 +76,16 @@ public:
 
   /// @}
 
-  void PrintImpl(raw_ostream &OS) const;
+  void PrintImpl(raw_ostream &OS) const override;
   bool EvaluateAsRelocatableImpl(MCValue &Res,
-                                 const MCAsmLayout *Layout) const;
-  void AddValueSymbols(MCAssembler *) const;
-  const MCSection *FindAssociatedSection() const {
+                                 const MCAsmLayout *Layout) const override;
+  void AddValueSymbols(MCAssembler *) const override;
+  const MCSection *FindAssociatedSection() const override {
     return getSubExpr()->FindAssociatedSection();
   }
 
   // There are no TLS PPCMCExprs at the moment.
-  void fixELFSymbolsInTLSFixups(MCAssembler &Asm) const {}
+  void fixELFSymbolsInTLSFixups(MCAssembler &Asm) const override {}
 
   static bool classof(const MCExpr *E) {
     return E->getKind() == MCExpr::Target;
diff --git a/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp b/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp
index bbdc7744df..8430c0b6a3 100644
--- a/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp
+++ b/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp
@@ -115,14 +115,14 @@ class PPCTargetAsmStreamer : public PPCTargetStreamer {
 public:
   PPCTargetAsmStreamer(MCStreamer &S, formatted_raw_ostream &OS)
       : PPCTargetStreamer(S), OS(OS) {}
-  virtual void emitTCEntry(const MCSymbol &S) {
+  void emitTCEntry(const MCSymbol &S) override {
     OS << "\t.tc ";
     OS << S.getName();
     OS << "[TC],";
     OS << S.getName();
     OS << '\n';
   }
-  virtual void emitMachine(StringRef CPU) {
+  void emitMachine(StringRef CPU) override {
     OS << "\t.machine " << CPU << '\n';
   }
 };
@@ -130,11 +130,11 @@ public:
 class PPCTargetELFStreamer : public PPCTargetStreamer {
 public:
   PPCTargetELFStreamer(MCStreamer &S) : PPCTargetStreamer(S) {}
-  virtual void emitTCEntry(const MCSymbol &S) {
+  void emitTCEntry(const MCSymbol &S) override {
     // Creates a R_PPC64_TOC relocation
     Streamer.EmitSymbolValue(&S, 8);
   }
-  virtual void emitMachine(StringRef CPU) {
+  void emitMachine(StringRef CPU) override {
     // FIXME: Is there anything to do in here or does this directive only
     // limit the parser?
   }
@@ -143,10 +143,10 @@ public:
 class PPCTargetMachOStreamer : public PPCTargetStreamer {
 public:
   PPCTargetMachOStreamer(MCStreamer &S) : PPCTargetStreamer(S) {}
-  virtual void emitTCEntry(const MCSymbol &S) {
+  void emitTCEntry(const MCSymbol &S) override {
     llvm_unreachable("Unknown pseudo-op: .tc");
   }
-  virtual void emitMachine(StringRef CPU) {
+  void emitMachine(StringRef CPU) override {
     // FIXME: We should update the CPUType, CPUSubType in the Object file if
     // the new values are different from the defaults.
   }
diff --git a/lib/Target/PowerPC/MCTargetDesc/PPCMachObjectWriter.cpp b/lib/Target/PowerPC/MCTargetDesc/PPCMachObjectWriter.cpp
index 503619d5a5..cff27baeb5 100644
--- a/lib/Target/PowerPC/MCTargetDesc/PPCMachObjectWriter.cpp
+++ b/lib/Target/PowerPC/MCTargetDesc/PPCMachObjectWriter.cpp
@@ -44,7 +44,7 @@ public:
   void RecordRelocation(MachObjectWriter *Writer, const MCAssembler &Asm,
                         const MCAsmLayout &Layout, const MCFragment *Fragment,
                         const MCFixup &Fixup, MCValue Target,
-                        uint64_t &FixedValue) {
+                        uint64_t &FixedValue) override {
     if (Writer->is64Bit()) {
       report_fatal_error("Relocation emission for MachO/PPC64 unimplemented.");
     } else
diff --git a/lib/Target/PowerPC/PPCAsmPrinter.cpp b/lib/Target/PowerPC/PPCAsmPrinter.cpp
index c564dfd4f2..688ca1c5ee 100644
--- a/lib/Target/PowerPC/PPCAsmPrinter.cpp
+++ b/lib/Target/PowerPC/PPCAsmPrinter.cpp
@@ -71,22 +71,22 @@ namespace {
       : AsmPrinter(TM, Streamer),
         Subtarget(TM.getSubtarget<PPCSubtarget>()), TOCLabelID(0) {}
 
-    virtual const char *getPassName() const {
+    const char *getPassName() const override {
       return "PowerPC Assembly Printer";
     }
 
     MCSymbol *lookUpOrCreateTOCEntry(MCSymbol *Sym);
 
-    virtual void EmitInstruction(const MachineInstr *MI);
+    void EmitInstruction(const MachineInstr *MI) override;
 
     void printOperand(const MachineInstr *MI, unsigned OpNo, raw_ostream &O);
 
     bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
                          unsigned AsmVariant, const char *ExtraCode,
-                         raw_ostream &O);
+                         raw_ostream &O) override;
     bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo,
                                unsigned AsmVariant, const char *ExtraCode,
-                               raw_ostream &O);
+                               raw_ostream &O) override;
   };
 
   /// PPCLinuxAsmPrinter - PowerPC assembly printer, customized for Linux
@@ -95,15 +95,15 @@ namespace {
     explicit PPCLinuxAsmPrinter(TargetMachine &TM, MCStreamer &Streamer)
       : PPCAsmPrinter(TM, Streamer) {}
 
-    virtual const char *getPassName() const {
+    const char *getPassName() const override {
       return "Linux PPC Assembly Printer";
     }
 
-    bool doFinalization(Module &M);
+    bool doFinalization(Module &M) override;
 
-    virtual void EmitFunctionEntryLabel();
+    void EmitFunctionEntryLabel() override;
 
-    void EmitFunctionBodyEnd();
+    void EmitFunctionBodyEnd() override;
   };
 
   /// PPCDarwinAsmPrinter - PowerPC assembly printer, customized for Darwin/Mac
@@ -113,12 +113,12 @@ namespace {
     explicit PPCDarwinAsmPrinter(TargetMachine &TM, MCStreamer &Streamer)
       : PPCAsmPrinter(TM, Streamer) {}
 
-    virtual const char *getPassName() const {
+    const char *getPassName() const override {
       return "Darwin PPC Assembly Printer";
     }
 
-    bool doFinalization(Module &M);
-    void EmitStartOfAsmFile(Module &M);
+    bool doFinalization(Module &M) override;
+    void EmitStartOfAsmFile(Module &M) override;
 
     void EmitFunctionStubs(const MachineModuleInfoMachO::SymbolListTy &Stubs);
   };
diff --git a/lib/Target/PowerPC/PPCBranchSelector.cpp b/lib/Target/PowerPC/PPCBranchSelector.cpp
index 8a851d8525..ee906712ee 100644
--- a/lib/Target/PowerPC/PPCBranchSelector.cpp
+++ b/lib/Target/PowerPC/PPCBranchSelector.cpp
@@ -43,9 +43,9 @@ namespace {
     /// BlockSizes - The sizes of the basic blocks in the function.
     std::vector<unsigned> BlockSizes;
 
-    virtual bool runOnMachineFunction(MachineFunction &Fn);
+    bool runOnMachineFunction(MachineFunction &Fn) override;
 
-    virtual const char *getPassName() const {
+    const char *getPassName() const override {
       return "PowerPC Branch Selector";
     }
   };
diff --git a/lib/Target/PowerPC/PPCCTRLoops.cpp b/lib/Target/PowerPC/PPCCTRLoops.cpp
index 2ef405fd20..7749c08d2d 100644
--- a/lib/Target/PowerPC/PPCCTRLoops.cpp
+++ b/lib/Target/PowerPC/PPCCTRLoops.cpp
@@ -91,9 +91,9 @@ namespace {
       initializePPCCTRLoopsPass(*PassRegistry::getPassRegistry());
     }
 
-    virtual bool runOnFunction(Function &F);
+    bool runOnFunction(Function &F) override;
 
-    virtual void getAnalysisUsage(AnalysisUsage &AU) const {
+    void getAnalysisUsage(AnalysisUsage &AU) const override {
       AU.addRequired<LoopInfo>();
       AU.addPreserved<LoopInfo>();
       AU.addRequired<DominatorTreeWrapperPass>();
@@ -128,12 +128,12 @@ namespace {
       initializePPCCTRLoopsVerifyPass(*PassRegistry::getPassRegistry());
     }
 
-    virtual void getAnalysisUsage(AnalysisUsage &AU) const {
+    void getAnalysisUsage(AnalysisUsage &AU) const override {
       AU.addRequired<MachineDominatorTree>();
       MachineFunctionPass::getAnalysisUsage(AU);
     }
 
-    virtual bool runOnMachineFunction(MachineFunction &MF);
+    bool runOnMachineFunction(MachineFunction &MF) override;
 
   private:
     MachineDominatorTree *MDT;
diff --git a/lib/Target/PowerPC/PPCCodeEmitter.cpp b/lib/Target/PowerPC/PPCCodeEmitter.cpp
index c46a09416b..08755238f9 100644
--- a/lib/Target/PowerPC/PPCCodeEmitter.cpp
+++ b/lib/Target/PowerPC/PPCCodeEmitter.cpp
@@ -32,7 +32,7 @@ namespace {
     JITCodeEmitter &MCE;
     MachineModuleInfo *MMI;
     
-    void getAnalysisUsage(AnalysisUsage &AU) const {
+    void getAnalysisUsage(AnalysisUsage &AU) const override {
       AU.addRequired<MachineModuleInfo>();
       MachineFunctionPass::getAnalysisUsage(AU);
     }
@@ -73,11 +73,13 @@ namespace {
     unsigned getTLSRegEncoding(const MachineInstr &MI, unsigned OpNo) const;
     unsigned getTLSCallEncoding(const MachineInstr &MI, unsigned OpNo) const;
 
-    const char *getPassName() const { return "PowerPC Machine Code Emitter"; }
+    const char *getPassName() const override {
+      return "PowerPC Machine Code Emitter";
+    }
 
     /// runOnMachineFunction - emits the given MachineFunction to memory
     ///
-    bool runOnMachineFunction(MachineFunction &MF);
+    bool runOnMachineFunction(MachineFunction &MF) override;
 
     /// emitBasicBlock - emits the given MachineBasicBlock to memory
     ///
diff --git a/lib/Target/PowerPC/PPCFastISel.cpp b/lib/Target/PowerPC/PPCFastISel.cpp
index 0a0eeeaeea..266ca42136 100644
--- a/lib/Target/PowerPC/PPCFastISel.cpp
+++ b/lib/Target/PowerPC/PPCFastISel.cpp
@@ -103,24 +103,24 @@ class PPCFastISel final : public FastISel {
 
   // Backend specific FastISel code.
   private:
-    virtual bool TargetSelectInstruction(const Instruction *I);
-    virtual unsigned TargetMaterializeConstant(const Constant *C);
-    virtual unsigned TargetMaterializeAlloca(const AllocaInst *AI);
-    virtual bool tryToFoldLoadIntoMI(MachineInstr *MI, unsigned OpNo,
-                                     const LoadInst *LI);
-    virtual bool FastLowerArguments();
-    virtual unsigned FastEmit_i(MVT Ty, MVT RetTy, unsigned Opc, uint64_t Imm);
-    virtual unsigned FastEmitInst_ri(unsigned MachineInstOpcode,
-                                     const TargetRegisterClass *RC,
-                                     unsigned Op0, bool Op0IsKill,
-                                     uint64_t Imm);
-    virtual unsigned FastEmitInst_r(unsigned MachineInstOpcode,
-                                    const TargetRegisterClass *RC,
-                                    unsigned Op0, bool Op0IsKill);
-    virtual unsigned FastEmitInst_rr(unsigned MachineInstOpcode,
-                                     const TargetRegisterClass *RC,
-                                     unsigned Op0, bool Op0IsKill,
-                                     unsigned Op1, bool Op1IsKill);
+    bool TargetSelectInstruction(const Instruction *I) override;
+    unsigned TargetMaterializeConstant(const Constant *C) override;
+    unsigned TargetMaterializeAlloca(const AllocaInst *AI) override;
+    bool tryToFoldLoadIntoMI(MachineInstr *MI, unsigned OpNo,
+                             const LoadInst *LI) override;
+    bool FastLowerArguments() override;
+    unsigned FastEmit_i(MVT Ty, MVT RetTy, unsigned Opc, uint64_t Imm) override;
+    unsigned FastEmitInst_ri(unsigned MachineInstOpcode,
+                             const TargetRegisterClass *RC,
+                             unsigned Op0, bool Op0IsKill,
+                             uint64_t Imm);
+    unsigned FastEmitInst_r(unsigned MachineInstOpcode,
+                            const TargetRegisterClass *RC,
+                            unsigned Op0, bool Op0IsKill);
+    unsigned FastEmitInst_rr(unsigned MachineInstOpcode,
+                             const TargetRegisterClass *RC,
+                             unsigned Op0, bool Op0IsKill,
+                             unsigned Op1, bool Op1IsKill);
 
   // Instruction selection routines.
   private:
diff --git a/lib/Target/PowerPC/PPCFrameLowering.cpp b/lib/Target/PowerPC/PPCFrameLowering.cpp
index d8f491f349..e2941568f1 100644
--- a/lib/Target/PowerPC/PPCFrameLowering.cpp
+++ b/lib/Target/PowerPC/PPCFrameLowering.cpp
@@ -222,7 +222,7 @@ unsigned PPCFrameLowering::determineFrameLayout(MachineFunction &MF,
   if (!DisableRedZone &&
       (Subtarget.isPPC64() ||                      // 32-bit SVR4, no stack-
        !Subtarget.isSVR4ABI() ||                   //   allocated locals.
-	FrameSize == 0) &&
+        FrameSize == 0) &&
       FrameSize <= 224 &&                          // Fits in red zone.
       !MFI->hasVarSizedObjects() &&                // No dynamic alloca.
       !MFI->adjustsStack() &&                      // No calls.
@@ -281,8 +281,8 @@ bool PPCFrameLowering::needsFP(const MachineFunction &MF) const {
 
   // Naked functions have no stack frame pushed, so we don't have a frame
   // pointer.
-  if (MF.getFunction()->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
-                                                     Attribute::Naked))
+  if (MF.getFunction()->getAttributes().hasAttribute(
+          AttributeSet::FunctionIndex, Attribute::Naked))
     return false;
 
   return MF.getTarget().Options.DisableFramePointerElim(MF) ||
@@ -426,7 +426,8 @@ void PPCFrameLowering::emitPrologue(MachineFunction &MF) const {
       assert(FPIndex && "No Frame Pointer Save Slot!");
       FPOffset = FFI->getObjectOffset(FPIndex);
     } else {
-      FPOffset = PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI);
+      FPOffset =
+          PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI);
     }
   }
 
@@ -562,13 +563,14 @@ void PPCFrameLowering::emitPrologue(MachineFunction &MF) const {
     assert(NegFrameSize);
     unsigned CFIIndex = MMI.addFrameInst(
         MCCFIInstruction::createDefCfaOffset(nullptr, NegFrameSize));
-    BuildMI(MBB, MBBI, dl, TII.get(PPC::CFI_INSTRUCTION)).addCFIIndex(CFIIndex);
+    BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
+        .addCFIIndex(CFIIndex);
 
     if (HasFP) {
       unsigned Reg = MRI->getDwarfRegNum(FPReg, true);
       CFIIndex = MMI.addFrameInst(
           MCCFIInstruction::createOffset(nullptr, Reg, FPOffset));
-      BuildMI(MBB, MBBI, dl, TII.get(PPC::CFI_INSTRUCTION))
+      BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
           .addCFIIndex(CFIIndex);
     }
 
@@ -576,7 +578,7 @@ void PPCFrameLowering::emitPrologue(MachineFunction &MF) const {
       unsigned Reg = MRI->getDwarfRegNum(BPReg, true);
       CFIIndex = MMI.addFrameInst(
           MCCFIInstruction::createOffset(nullptr, Reg, BPOffset));
-      BuildMI(MBB, MBBI, dl, TII.get(PPC::CFI_INSTRUCTION))
+      BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
           .addCFIIndex(CFIIndex);
     }
 
@@ -584,7 +586,7 @@ void PPCFrameLowering::emitPrologue(MachineFunction &MF) const {
       unsigned Reg = MRI->getDwarfRegNum(LRReg, true);
       CFIIndex = MMI.addFrameInst(
           MCCFIInstruction::createOffset(nullptr, Reg, LROffset));
-      BuildMI(MBB, MBBI, dl, TII.get(PPC::CFI_INSTRUCTION))
+      BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
           .addCFIIndex(CFIIndex);
     }
   }
@@ -601,7 +603,7 @@ void PPCFrameLowering::emitPrologue(MachineFunction &MF) const {
       unsigned CFIIndex = MMI.addFrameInst(
           MCCFIInstruction::createDefCfaRegister(nullptr, Reg));
 
-      BuildMI(MBB, MBBI, dl, TII.get(PPC::CFI_INSTRUCTION))
+      BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
           .addCFIIndex(CFIIndex);
     }
   }
@@ -629,7 +631,7 @@ void PPCFrameLowering::emitPrologue(MachineFunction &MF) const {
       if (isSVR4ABI && isPPC64 && (PPC::CR2 <= Reg && Reg <= PPC::CR4)) {
         unsigned CFIIndex = MMI.addFrameInst(MCCFIInstruction::createOffset(
             nullptr, MRI->getDwarfRegNum(PPC::CR2, true), 8));
-        BuildMI(MBB, MBBI, dl, TII.get(PPC::CFI_INSTRUCTION))
+        BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
             .addCFIIndex(CFIIndex);
         continue;
       }
@@ -637,7 +639,7 @@ void PPCFrameLowering::emitPrologue(MachineFunction &MF) const {
       int Offset = MFI->getObjectOffset(CSI[I].getFrameIdx());
       unsigned CFIIndex = MMI.addFrameInst(MCCFIInstruction::createOffset(
           nullptr, MRI->getDwarfRegNum(Reg, true), Offset));
-      BuildMI(MBB, MBBI, dl, TII.get(PPC::CFI_INSTRUCTION))
+      BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
           .addCFIIndex(CFIIndex);
     }
   }
@@ -712,7 +714,8 @@ void PPCFrameLowering::emitEpilogue(MachineFunction &MF,
       assert(FPIndex && "No Frame Pointer Save Slot!");
       FPOffset = FFI->getObjectOffset(FPIndex);
     } else {
-      FPOffset = PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI);
+      FPOffset =
+          PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI);
     }
   }
 
@@ -930,9 +933,9 @@ PPCFrameLowering::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
     MFI->CreateFixedObject(-1 * TCSPDelta, TCSPDelta, true);
   }
 
-  // For 32-bit SVR4, allocate the nonvolatile CR spill slot iff the 
+  // For 32-bit SVR4, allocate the nonvolatile CR spill slot iff the
   // function uses CR 2, 3, or 4.
-  if (!isPPC64 && !isDarwinABI && 
+  if (!isPPC64 && !isDarwinABI &&
       (MRI.isPhysRegUsed(PPC::CR2) ||
        MRI.isPhysRegUsed(PPC::CR3) ||
        MRI.isPhysRegUsed(PPC::CR4))) {
@@ -1106,10 +1109,10 @@ void PPCFrameLowering::processFunctionBeforeFrameFinalized(MachineFunction &MF,
       unsigned Reg = CSI[i].getReg();
 
       if ((Subtarget.isSVR4ABI() && Reg == PPC::CR2)
-	  // Leave Darwin logic as-is.
-	  || (!Subtarget.isSVR4ABI() &&
-	      (PPC::CRBITRCRegClass.contains(Reg) ||
-	       PPC::CRRCRegClass.contains(Reg)))) {
+          // Leave Darwin logic as-is.
+          || (!Subtarget.isSVR4ABI() &&
+              (PPC::CRBITRCRegClass.contains(Reg) ||
+               PPC::CRRCRegClass.contains(Reg)))) {
         int FI = CSI[i].getFrameIdx();
 
         FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
@@ -1190,11 +1193,11 @@ PPCFrameLowering::addScavengingSpillSlot(MachineFunction &MF,
   }
 }
 
-bool 
+bool
 PPCFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
-				     MachineBasicBlock::iterator MI,
-				     const std::vector<CalleeSavedInfo> &CSI,
-				     const TargetRegisterInfo *TRI) const {
+                                     MachineBasicBlock::iterator MI,
+                                     const std::vector<CalleeSavedInfo> &CSI,
+                                     const TargetRegisterInfo *TRI) const {
 
   // Currently, this function only handles SVR4 32- and 64-bit ABIs.
   // Return false otherwise to maintain pre-existing behavior.
@@ -1207,7 +1210,7 @@ PPCFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
   DebugLoc DL;
   bool CRSpilled = false;
   MachineInstrBuilder CRMIB;
-  
+
   for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
     unsigned Reg = CSI[i].getReg();
     // Only Darwin actually uses the VRSAVE register, but it can still appear
@@ -1237,21 +1240,21 @@ PPCFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
         CRSpilled = true;
         FuncInfo->setSpillsCR();
 
-	// 32-bit:  FP-relative.  Note that we made sure CR2-CR4 all have
-	// the same frame index in PPCRegisterInfo::hasReservedSpillSlot.
-	CRMIB = BuildMI(*MF, DL, TII.get(PPC::MFCR), PPC::R12)
+        // 32-bit:  FP-relative.  Note that we made sure CR2-CR4 all have
+        // the same frame index in PPCRegisterInfo::hasReservedSpillSlot.
+        CRMIB = BuildMI(*MF, DL, TII.get(PPC::MFCR), PPC::R12)
                   .addReg(Reg, RegState::ImplicitKill);
 
-	MBB.insert(MI, CRMIB);
-	MBB.insert(MI, addFrameReference(BuildMI(*MF, DL, TII.get(PPC::STW))
-					 .addReg(PPC::R12,
-						 getKillRegState(true)),
-					 CSI[i].getFrameIdx()));
+        MBB.insert(MI, CRMIB);
+        MBB.insert(MI, addFrameReference(BuildMI(*MF, DL, TII.get(PPC::STW))
+                                         .addReg(PPC::R12,
+                                                 getKillRegState(true)),
+                                         CSI[i].getFrameIdx()));
       }
     } else {
       const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
       TII.storeRegToStackSlot(MBB, MI, Reg, true,
-			      CSI[i].getFrameIdx(), RC, TRI);
+                              CSI[i].getFrameIdx(), RC, TRI);
     }
   }
   return true;
@@ -1260,8 +1263,8 @@ PPCFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
 static void
 restoreCRs(bool isPPC64, bool is31,
            bool CR2Spilled, bool CR3Spilled, bool CR4Spilled,
-	   MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
-	   const std::vector<CalleeSavedInfo> &CSI, unsigned CSIIndex) {
+           MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
+           const std::vector<CalleeSavedInfo> &CSI, unsigned CSIIndex) {
 
   MachineFunction *MF = MBB.getParent();
   const PPCInstrInfo &TII =
@@ -1275,12 +1278,12 @@ restoreCRs(bool isPPC64, bool is31,
   else {
     // 32-bit:  FP-relative
     MBB.insert(MI, addFrameReference(BuildMI(*MF, DL, TII.get(PPC::LWZ),
-					     PPC::R12),
-				     CSI[CSIIndex].getFrameIdx()));
+                                             PPC::R12),
+                                     CSI[CSIIndex].getFrameIdx()));
     RestoreOp = PPC::MTOCRF;
     MoveReg = PPC::R12;
   }
-  
+
   if (CR2Spilled)
     MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR2)
                .addReg(MoveReg, getKillRegState(!CR3Spilled && !CR4Spilled)));
@@ -1335,11 +1338,11 @@ eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
   MBB.erase(I);
 }
 
-bool 
+bool
 PPCFrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
-					MachineBasicBlock::iterator MI,
-				        const std::vector<CalleeSavedInfo> &CSI,
-					const TargetRegisterInfo *TRI) const {
+                                        MachineBasicBlock::iterator MI,
+                                        const std::vector<CalleeSavedInfo> &CSI,
+                                        const TargetRegisterInfo *TRI) const {
 
   // Currently, this function only handles SVR4 32- and 64-bit ABIs.
   // Return false otherwise to maintain pre-existing behavior.
@@ -1387,20 +1390,20 @@ PPCFrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
       // When we first encounter a non-CR register after seeing at
       // least one CR register, restore all spilled CRs together.
       if ((CR2Spilled || CR3Spilled || CR4Spilled)
-	  && !(PPC::CR2 <= Reg && Reg <= PPC::CR4)) {
+          && !(PPC::CR2 <= Reg && Reg <= PPC::CR4)) {
         bool is31 = needsFP(*MF);
         restoreCRs(Subtarget.isPPC64(), is31,
                    CR2Spilled, CR3Spilled, CR4Spilled,
-		   MBB, I, CSI, CSIIndex);
-	CR2Spilled = CR3Spilled = CR4Spilled = false;
+                   MBB, I, CSI, CSIIndex);
+        CR2Spilled = CR3Spilled = CR4Spilled = false;
       }
 
       // Default behavior for non-CR saves.
       const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
       TII.loadRegFromStackSlot(MBB, I, Reg, CSI[i].getFrameIdx(),
-			       RC, TRI);
+                               RC, TRI);
       assert(I != MBB.begin() &&
-	     "loadRegFromStackSlot didn't insert any code!");
+             "loadRegFromStackSlot didn't insert any code!");
       }
 
     // Insert in reverse order.
@@ -1409,16 +1412,15 @@ PPCFrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
     else {
       I = BeforeI;
       ++I;
-    }	    
+    }
   }
 
   // If we haven't yet spilled the CRs, do so now.
   if (CR2Spilled || CR3Spilled || CR4Spilled) {
-    bool is31 = needsFP(*MF); 
+    bool is31 = needsFP(*MF);
     restoreCRs(Subtarget.isPPC64(), is31, CR2Spilled, CR3Spilled, CR4Spilled,
-	       MBB, I, CSI, CSIIndex);
+               MBB, I, CSI, CSIIndex);
   }
 
   return true;
 }
-
diff --git a/lib/Target/PowerPC/PPCFrameLowering.h b/lib/Target/PowerPC/PPCFrameLowering.h
index 619ad833a7..94e9b67338 100644
--- a/lib/Target/PowerPC/PPCFrameLowering.h
+++ b/lib/Target/PowerPC/PPCFrameLowering.h
@@ -38,37 +38,37 @@ public:
 
   /// emitProlog/emitEpilog - These methods insert prolog and epilog code into
   /// the function.
-  void emitPrologue(MachineFunction &MF) const;
-  void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
+  void emitPrologue(MachineFunction &MF) const override;
+  void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override;
 
-  bool hasFP(const MachineFunction &MF) const;
+  bool hasFP(const MachineFunction &MF) const override;
   bool needsFP(const MachineFunction &MF) const;
   void replaceFPWithRealFP(MachineFunction &MF) const;
 
   void processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
-                                            RegScavenger *RS = nullptr) const;
+                                     RegScavenger *RS = nullptr) const override;
   void processFunctionBeforeFrameFinalized(MachineFunction &MF,
-                                       RegScavenger *RS = nullptr) const;
+                                     RegScavenger *RS = nullptr) const override;
   void addScavengingSpillSlot(MachineFunction &MF, RegScavenger *RS) const;
 
   bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
                                  MachineBasicBlock::iterator MI,
                                  const std::vector<CalleeSavedInfo> &CSI,
-                                 const TargetRegisterInfo *TRI) const;
+                                 const TargetRegisterInfo *TRI) const override;
 
   void eliminateCallFramePseudoInstr(MachineFunction &MF,
-                                     MachineBasicBlock &MBB,
-                                     MachineBasicBlock::iterator I) const;
+                                  MachineBasicBlock &MBB,
+                                  MachineBasicBlock::iterator I) const override;
 
   bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
-                                   MachineBasicBlock::iterator MI,
-                                   const std::vector<CalleeSavedInfo> &CSI,
-                                   const TargetRegisterInfo *TRI) const;
+                                  MachineBasicBlock::iterator MI,
+                                  const std::vector<CalleeSavedInfo> &CSI,
+                                  const TargetRegisterInfo *TRI) const override;
 
   /// targetHandlesStackFrameRounding - Returns true if the target is
   /// responsible for rounding up the stack frame (probably at emitPrologue
   /// time).
-  bool targetHandlesStackFrameRounding() const { return true; }
+  bool targetHandlesStackFrameRounding() const override { return true; }
 
   /// getReturnSaveOffset - Return the previous frame offset to save the
   /// return address.
@@ -141,7 +141,7 @@ public:
 
   // With the SVR4 ABI, callee-saved registers have fixed offsets on the stack.
   const SpillSlot *
-  getCalleeSavedSpillSlots(unsigned &NumEntries) const {
+  getCalleeSavedSpillSlots(unsigned &NumEntries) const override {
     if (Subtarget.isDarwinABI()) {
       NumEntries = 1;
       if (Subtarget.isPPC64()) {
diff --git a/lib/Target/PowerPC/PPCHazardRecognizers.h b/lib/Target/PowerPC/PPCHazardRecognizers.h
index 6b7fe41e57..cf4332cffa 100644
--- a/lib/Target/PowerPC/PPCHazardRecognizers.h
+++ b/lib/Target/PowerPC/PPCHazardRecognizers.h
@@ -37,14 +37,14 @@ public:
     ScoreboardHazardRecognizer(ItinData, DAG_), DAG(DAG_),
     CurSlots(0), CurBranches(0) {}
 
-  virtual HazardType getHazardType(SUnit *SU, int Stalls);
-  virtual bool ShouldPreferAnother(SUnit* SU);
-  virtual unsigned PreEmitNoops(SUnit *SU);
-  virtual void EmitInstruction(SUnit *SU);
-  virtual void AdvanceCycle();
-  virtual void RecedeCycle();
-  virtual void Reset();
-  virtual void EmitNoop();
+  HazardType getHazardType(SUnit *SU, int Stalls) override;
+  bool ShouldPreferAnother(SUnit* SU) override;
+  unsigned PreEmitNoops(SUnit *SU) override;
+  void EmitInstruction(SUnit *SU) override;
+  void AdvanceCycle() override;
+  void RecedeCycle() override;
+  void Reset() override;
+  void EmitNoop() override;
 };
 
 /// PPCHazardRecognizer970 - This class defines a finite state automata that
@@ -76,10 +76,10 @@ class PPCHazardRecognizer970 : public ScheduleHazardRecognizer {
 
 public:
   PPCHazardRecognizer970(const TargetMachine &TM);
-  virtual HazardType getHazardType(SUnit *SU, int Stalls);
-  virtual void EmitInstruction(SUnit *SU);
-  virtual void AdvanceCycle();
-  virtual void Reset();
+  virtual HazardType getHazardType(SUnit *SU, int Stalls) override;
+  virtual void EmitInstruction(SUnit *SU) override;
+  virtual void AdvanceCycle() override;
+  virtual void Reset() override;
 
 private:
   /// EndDispatchGroup - Called when we are finishing a new dispatch group.
diff --git a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
index eef18e2d34..7101315b65 100644
--- a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
+++ b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
@@ -62,7 +62,7 @@ namespace {
       initializePPCDAGToDAGISelPass(*PassRegistry::getPassRegistry());
     }
 
-    virtual bool runOnMachineFunction(MachineFunction &MF) {
+    bool runOnMachineFunction(MachineFunction &MF) override {
       // Make sure we re-emit a set of the global base reg if necessary
       GlobalBaseReg = 0;
       SelectionDAGISel::runOnMachineFunction(MF);
@@ -73,7 +73,7 @@ namespace {
       return true;
     }
 
-    virtual void PostprocessISelDAG();
+    void PostprocessISelDAG() override;
 
     /// getI32Imm - Return a target constant with the specified value, of type
     /// i32.
@@ -110,7 +110,7 @@ namespace {
 
     // Select - Convert the specified operand from a target-independent to a
     // target-specific node if it hasn't already been changed.
-    SDNode *Select(SDNode *N);
+    SDNode *Select(SDNode *N) override;
 
     SDNode *SelectBitfieldInsert(SDNode *N);
 
@@ -169,16 +169,16 @@ namespace {
     /// a register.  The case of adding a (possibly relocatable) constant to a
     /// register can be improved, but it is wrong to substitute Reg+Reg for
     /// Reg in an asm, because the load or store opcode would have to change.
-   virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
-                                              char ConstraintCode,
-                                              std::vector<SDValue> &OutOps) {
+   bool SelectInlineAsmMemoryOperand(const SDValue &Op,
+                                      char ConstraintCode,
+                                      std::vector<SDValue> &OutOps) override {
       OutOps.push_back(Op);
       return false;
     }
 
     void InsertVRSaveCode(MachineFunction &MF);
 
-    virtual const char *getPassName() const {
+    const char *getPassName() const override {
       return "PowerPC DAG->DAG Pattern Instruction Selection";
     }
 
diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp
index e787817297..e5fa0d6a24 100644
--- a/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -3474,7 +3474,7 @@ unsigned PrepareCall(SelectionDAG &DAG, SDValue &Callee, SDValue &InFlag,
       // descriptor.
       SDVTList VTs = DAG.getVTList(MVT::i64, MVT::Other, MVT::Glue);
       SDValue LoadFuncPtr = DAG.getNode(PPCISD::LOAD, dl, VTs,
-                         ArrayRef<SDValue>(MTCTROps, InFlag.getNode() ? 3 : 2));
+                              makeArrayRef(MTCTROps, InFlag.getNode() ? 3 : 2));
       Chain = LoadFuncPtr.getValue(1);
       InFlag = LoadFuncPtr.getValue(2);
 
@@ -3511,7 +3511,7 @@ unsigned PrepareCall(SelectionDAG &DAG, SDValue &Callee, SDValue &InFlag,
     }
 
     Chain = DAG.getNode(PPCISD::MTCTR, dl, NodeTys,
-                        ArrayRef<SDValue>(MTCTROps, InFlag.getNode() ? 3 : 2));
+                        makeArrayRef(MTCTROps, InFlag.getNode() ? 3 : 2));
     InFlag = Chain.getValue(1);
 
     NodeTys.clear();
@@ -3940,8 +3940,7 @@ PPCTargetLowering::LowerCall_32SVR4(SDValue Chain, SDValue Callee,
     SDValue Ops[] = { Chain, InFlag };
 
     Chain = DAG.getNode(seenFloatArg ? PPCISD::CR6SET : PPCISD::CR6UNSET,
-                        dl, VTs,
-                        ArrayRef<SDValue>(Ops, InFlag.getNode() ? 2 : 1));
+                        dl, VTs, makeArrayRef(Ops, InFlag.getNode() ? 2 : 1));
 
     InFlag = Chain.getValue(1);
   }
@@ -5282,7 +5281,7 @@ SDValue PPCTargetLowering::LowerFLT_ROUNDS_(SDValue Op,
     MVT::f64,    // return register
     MVT::Glue    // unused in this context
   };
-  SDValue Chain = DAG.getNode(PPCISD::MFFS, dl, NodeTys, ArrayRef<SDValue>());
+  SDValue Chain = DAG.getNode(PPCISD::MFFS, dl, NodeTys, None);
 
   // Save FP register to stack slot
   int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8, false);
diff --git a/lib/Target/PowerPC/PPCISelLowering.h b/lib/Target/PowerPC/PPCISelLowering.h
index 36fdf46ceb..f05f5dd6a6 100644
--- a/lib/Target/PowerPC/PPCISelLowering.h
+++ b/lib/Target/PowerPC/PPCISelLowering.h
@@ -351,20 +351,20 @@ namespace llvm {
 
     /// getTargetNodeName() - This method returns the name of a target specific
     /// DAG node.
-    virtual const char *getTargetNodeName(unsigned Opcode) const;
+    const char *getTargetNodeName(unsigned Opcode) const override;
 
-    virtual MVT getScalarShiftAmountTy(EVT LHSTy) const { return MVT::i32; }
+    MVT getScalarShiftAmountTy(EVT LHSTy) const override { return MVT::i32; }
 
     /// getSetCCResultType - Return the ISD::SETCC ValueType
-    virtual EVT getSetCCResultType(LLVMContext &Context, EVT VT) const;
+    EVT getSetCCResultType(LLVMContext &Context, EVT VT) const override;
 
     /// getPreIndexedAddressParts - returns true by value, base pointer and
     /// offset pointer and addressing mode by reference if the node's address
     /// can be legally represented as pre-indexed load / store address.
-    virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
-                                           SDValue &Offset,
-                                           ISD::MemIndexedMode &AM,
-                                           SelectionDAG &DAG) const;
+    bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
+                                   SDValue &Offset,
+                                   ISD::MemIndexedMode &AM,
+                                   SelectionDAG &DAG) const override;
 
     /// SelectAddressRegReg - Given the specified addressed, check to see if it
     /// can be represented as an indexed [r+r] operation.  Returns false if it
@@ -384,29 +384,29 @@ namespace llvm {
     bool SelectAddressRegRegOnly(SDValue N, SDValue &Base, SDValue &Index,
                                  SelectionDAG &DAG) const;
 
-    Sched::Preference getSchedulingPreference(SDNode *N) const;
+    Sched::Preference getSchedulingPreference(SDNode *N) const override;
 
     /// LowerOperation - Provide custom lowering hooks for some operations.
     ///
-    virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
+    SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
 
     /// ReplaceNodeResults - Replace the results of node with an illegal result
     /// type with new values built out of custom code.
     ///
-    virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
-                                    SelectionDAG &DAG) const;
+    void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
+                            SelectionDAG &DAG) const override;
 
-    virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
+    SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
 
-    virtual void computeMaskedBitsForTargetNode(const SDValue Op,
-                                                APInt &KnownZero,
-                                                APInt &KnownOne,
-                                                const SelectionDAG &DAG,
-                                                unsigned Depth = 0) const;
+    void computeMaskedBitsForTargetNode(const SDValue Op,
+                                        APInt &KnownZero,
+                                        APInt &KnownOne,
+                                        const SelectionDAG &DAG,
+                                        unsigned Depth = 0) const override;
 
-    virtual MachineBasicBlock *
+    MachineBasicBlock *
       EmitInstrWithCustomInserter(MachineInstr *MI,
-                                  MachineBasicBlock *MBB) const;
+                                  MachineBasicBlock *MBB) const override;
     MachineBasicBlock *EmitAtomicBinary(MachineInstr *MI,
                                         MachineBasicBlock *MBB, bool is64Bit,
                                         unsigned BinOpcode) const;
@@ -420,32 +420,33 @@ namespace llvm {
     MachineBasicBlock *emitEHSjLjLongJmp(MachineInstr *MI,
                                          MachineBasicBlock *MBB) const;
 
-    ConstraintType getConstraintType(const std::string &Constraint) const;
+    ConstraintType
+    getConstraintType(const std::string &Constraint) const override;
 
     /// Examine constraint string and operand type and determine a weight value.
     /// The operand object must already have been set up with the operand type.
     ConstraintWeight getSingleConstraintMatchWeight(
-      AsmOperandInfo &info, const char *constraint) const;
+      AsmOperandInfo &info, const char *constraint) const override;
 
     std::pair<unsigned, const TargetRegisterClass*>
       getRegForInlineAsmConstraint(const std::string &Constraint,
-                                   MVT VT) const;
+                                   MVT VT) const override;
 
     /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
     /// function arguments in the caller parameter area.  This is the actual
     /// alignment, not its logarithm.
-    unsigned getByValTypeAlignment(Type *Ty) const;
+    unsigned getByValTypeAlignment(Type *Ty) const override;
 
     /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
     /// vector.  If it is invalid, don't add anything to Ops.
-    virtual void LowerAsmOperandForConstraint(SDValue Op,
-                                              std::string &Constraint,
-                                              std::vector<SDValue> &Ops,
-                                              SelectionDAG &DAG) const;
+    void LowerAsmOperandForConstraint(SDValue Op,
+                                      std::string &Constraint,
+                                      std::vector<SDValue> &Ops,
+                                      SelectionDAG &DAG) const override;
 
     /// isLegalAddressingMode - Return true if the addressing mode represented
     /// by AM is legal for this target, for a load/store of the specified type.
-    virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty)const;
+    bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const override;
 
     /// isLegalICmpImmediate - Return true if the specified immediate is legal
     /// icmp immediate, that is the target has icmp instructions which can
@@ -470,7 +471,7 @@ namespace llvm {
     bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
                                            Type *Ty) const override;
 
-    virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
+    bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
 
     /// getOptimalMemOpType - Returns the target specific optimal type for load
     /// and store operations as a result of memset, memcpy, and memmove
@@ -483,32 +484,32 @@ namespace llvm {
     /// source is constant so it does not need to be loaded.
     /// It returns EVT::Other if the type should be determined using generic
     /// target-independent logic.
-    virtual EVT
+    EVT
     getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign,
                         bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc,
-                        MachineFunction &MF) const;
+                        MachineFunction &MF) const override;
 
     /// Is unaligned memory access allowed for the given type, and is it fast
     /// relative to software emulation.
-    virtual bool allowsUnalignedMemoryAccesses(EVT VT,
-                                               unsigned AddrSpace,
-                                               bool *Fast = nullptr) const;
+    bool allowsUnalignedMemoryAccesses(EVT VT,
+                                       unsigned AddrSpace,
+                                       bool *Fast = nullptr) const override;
 
     /// isFMAFasterThanFMulAndFAdd - Return true if an FMA operation is faster
     /// than a pair of fmul and fadd instructions. fmuladd intrinsics will be
     /// expanded to FMAs when this method returns true, otherwise fmuladd is
     /// expanded to fmul + fadd.
-    virtual bool isFMAFasterThanFMulAndFAdd(EVT VT) const;
+    bool isFMAFasterThanFMulAndFAdd(EVT VT) const override;
 
     // Should we expand the build vector with shuffles?
-    virtual bool
+    bool
     shouldExpandBuildVectorWithShuffles(EVT VT,
-                                        unsigned DefinedValues) const;
+                                        unsigned DefinedValues) const override;
 
     /// createFastISel - This method returns a target-specific FastISel object,
     /// or null if the target does not support "fast" instruction selection.
-    virtual FastISel *createFastISel(FunctionLoweringInfo &FuncInfo,
-                                     const TargetLibraryInfo *LibInfo) const;
+    FastISel *createFastISel(FunctionLoweringInfo &FuncInfo,
+                             const TargetLibraryInfo *LibInfo) const override;
 
   private:
     SDValue getFramePointerFrameIndex(SelectionDAG & DAG) const;
@@ -582,29 +583,29 @@ namespace llvm {
                        const SmallVectorImpl<ISD::InputArg> &Ins,
                        SmallVectorImpl<SDValue> &InVals) const;
 
-    virtual SDValue
+    SDValue
       LowerFormalArguments(SDValue Chain,
                            CallingConv::ID CallConv, bool isVarArg,
                            const SmallVectorImpl<ISD::InputArg> &Ins,
                            SDLoc dl, SelectionDAG &DAG,
-                           SmallVectorImpl<SDValue> &InVals) const;
+                           SmallVectorImpl<SDValue> &InVals) const override;
 
-    virtual SDValue
+    SDValue
       LowerCall(TargetLowering::CallLoweringInfo &CLI,
-                SmallVectorImpl<SDValue> &InVals) const;
+                SmallVectorImpl<SDValue> &InVals) const override;
 
-    virtual bool
+    bool
       CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
                    bool isVarArg,
                    const SmallVectorImpl<ISD::OutputArg> &Outs,
-                   LLVMContext &Context) const;
+                   LLVMContext &Context) const override;
 
-    virtual SDValue
+    SDValue
       LowerReturn(SDValue Chain,
                   CallingConv::ID CallConv, bool isVarArg,
                   const SmallVectorImpl<ISD::OutputArg> &Outs,
                   const SmallVectorImpl<SDValue> &OutVals,
-                  SDLoc dl, SelectionDAG &DAG) const;
+                  SDLoc dl, SelectionDAG &DAG) const override;
 
     SDValue
       extendArgForPPC64(ISD::ArgFlagsTy Flags, EVT ObjectVT, SelectionDAG &DAG,
diff --git a/lib/Target/PowerPC/PPCInstrInfo.cpp b/lib/Target/PowerPC/PPCInstrInfo.cpp
index ae41fa0bd6..0c15e2d023 100644
--- a/lib/Target/PowerPC/PPCInstrInfo.cpp
+++ b/lib/Target/PowerPC/PPCInstrInfo.cpp
@@ -1812,7 +1812,7 @@ protected:
     }
 
 public:
-    virtual bool runOnMachineFunction(MachineFunction &MF) {
+    bool runOnMachineFunction(MachineFunction &MF) override {
       LIS = &getAnalysis<LiveIntervals>();
 
       TM = static_cast<const PPCTargetMachine *>(&MF.getTarget());
@@ -1832,7 +1832,7 @@ public:
       return Changed;
     }
 
-    virtual void getAnalysisUsage(AnalysisUsage &AU) const {
+    void getAnalysisUsage(AnalysisUsage &AU) const override {
       AU.addRequired<LiveIntervals>();
       AU.addPreserved<LiveIntervals>();
       AU.addRequired<SlotIndexes>();
@@ -1964,7 +1964,7 @@ protected:
     }
 
 public:
-    virtual bool runOnMachineFunction(MachineFunction &MF) {
+    bool runOnMachineFunction(MachineFunction &MF) override {
       TM = static_cast<const PPCTargetMachine *>(&MF.getTarget());
       TII = TM->getInstrInfo();
 
@@ -1979,7 +1979,7 @@ public:
       return Changed;
     }
 
-    virtual void getAnalysisUsage(AnalysisUsage &AU) const {
+    void getAnalysisUsage(AnalysisUsage &AU) const override {
       MachineFunctionPass::getAnalysisUsage(AU);
     }
   };
@@ -2038,7 +2038,7 @@ protected:
     }
 
 public:
-    virtual bool runOnMachineFunction(MachineFunction &MF) {
+    bool runOnMachineFunction(MachineFunction &MF) override {
       TM = static_cast<const PPCTargetMachine *>(&MF.getTarget());
       TII = TM->getInstrInfo();
 
@@ -2053,7 +2053,7 @@ public:
       return Changed;
     }
 
-    virtual void getAnalysisUsage(AnalysisUsage &AU) const {
+    void getAnalysisUsage(AnalysisUsage &AU) const override {
       MachineFunctionPass::getAnalysisUsage(AU);
     }
   };
@@ -2195,7 +2195,7 @@ protected:
     }
 
 public:
-    virtual bool runOnMachineFunction(MachineFunction &MF) {
+    bool runOnMachineFunction(MachineFunction &MF) override {
       TM = static_cast<const PPCTargetMachine *>(&MF.getTarget());
       TII = TM->getInstrInfo();
 
@@ -2215,7 +2215,7 @@ public:
       return Changed;
     }
 
-    virtual void getAnalysisUsage(AnalysisUsage &AU) const {
+    void getAnalysisUsage(AnalysisUsage &AU) const override {
       MachineFunctionPass::getAnalysisUsage(AU);
     }
   };
diff --git a/lib/Target/PowerPC/PPCInstrInfo.h b/lib/Target/PowerPC/PPCInstrInfo.h
index 3c8117cb63..d9db3e1b1d 100644
--- a/lib/Target/PowerPC/PPCInstrInfo.h
+++ b/lib/Target/PowerPC/PPCInstrInfo.h
@@ -86,151 +86,148 @@ public:
   /// such, whenever a client has an instance of instruction info, it should
   /// always be able to get register info as well (through this method).
   ///
-  virtual const PPCRegisterInfo &getRegisterInfo() const { return RI; }
+  const PPCRegisterInfo &getRegisterInfo() const { return RI; }
 
   ScheduleHazardRecognizer *
   CreateTargetHazardRecognizer(const TargetMachine *TM,
-                               const ScheduleDAG *DAG) const;
+                               const ScheduleDAG *DAG) const override;
   ScheduleHazardRecognizer *
   CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
-                                     const ScheduleDAG *DAG) const;
+                                     const ScheduleDAG *DAG) const override;
 
-  virtual
   int getOperandLatency(const InstrItineraryData *ItinData,
                         const MachineInstr *DefMI, unsigned DefIdx,
-                        const MachineInstr *UseMI, unsigned UseIdx) const;
-  virtual
+                        const MachineInstr *UseMI,
+                        unsigned UseIdx) const override;
   int getOperandLatency(const InstrItineraryData *ItinData,
                         SDNode *DefNode, unsigned DefIdx,
-                        SDNode *UseNode, unsigned UseIdx) const {
+                        SDNode *UseNode, unsigned UseIdx) const override {
     return PPCGenInstrInfo::getOperandLatency(ItinData, DefNode, DefIdx,
                                               UseNode, UseIdx);
   }
 
   bool isCoalescableExtInstr(const MachineInstr &MI,
                              unsigned &SrcReg, unsigned &DstReg,
-                             unsigned &SubIdx) const;
+                             unsigned &SubIdx) const override;
   unsigned isLoadFromStackSlot(const MachineInstr *MI,
-                               int &FrameIndex) const;
+                               int &FrameIndex) const override;
   unsigned isStoreToStackSlot(const MachineInstr *MI,
-                              int &FrameIndex) const;
+                              int &FrameIndex) const override;
 
   // commuteInstruction - We can commute rlwimi instructions, but only if the
   // rotate amt is zero.  We also have to munge the immediates a bit.
-  virtual MachineInstr *commuteInstruction(MachineInstr *MI, bool NewMI) const;
+  MachineInstr *commuteInstruction(MachineInstr *MI, bool NewMI) const override;
 
-  virtual bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1,
-                                     unsigned &SrcOpIdx2) const;
+  bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1,
+                             unsigned &SrcOpIdx2) const override;
 
-  virtual void insertNoop(MachineBasicBlock &MBB,
-                          MachineBasicBlock::iterator MI) const;
+  void insertNoop(MachineBasicBlock &MBB,
+                  MachineBasicBlock::iterator MI) const override;
 
 
   // Branch analysis.
-  virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
-                             MachineBasicBlock *&FBB,
-                             SmallVectorImpl<MachineOperand> &Cond,
-                             bool AllowModify) const;
-  virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
-  virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
-                                MachineBasicBlock *FBB,
-                                const SmallVectorImpl<MachineOperand> &Cond,
-                                DebugLoc DL) const;
+  bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
+                     MachineBasicBlock *&FBB,
+                     SmallVectorImpl<MachineOperand> &Cond,
+                     bool AllowModify) const override;
+  unsigned RemoveBranch(MachineBasicBlock &MBB) const override;
+  unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
+                        MachineBasicBlock *FBB,
+                        const SmallVectorImpl<MachineOperand> &Cond,
+                        DebugLoc DL) const override;
 
   // Select analysis.
-  virtual bool canInsertSelect(const MachineBasicBlock&,
-                               const SmallVectorImpl<MachineOperand> &Cond,
-                               unsigned, unsigned, int&, int&, int&) const;
-  virtual void insertSelect(MachineBasicBlock &MBB,
-                            MachineBasicBlock::iterator MI, DebugLoc DL,
-                            unsigned DstReg,
-                            const SmallVectorImpl<MachineOperand> &Cond,
-                            unsigned TrueReg, unsigned FalseReg) const;
-
-  virtual void copyPhysReg(MachineBasicBlock &MBB,
-                           MachineBasicBlock::iterator I, DebugLoc DL,
-                           unsigned DestReg, unsigned SrcReg,
-                           bool KillSrc) const;
-
-  virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
-                                   MachineBasicBlock::iterator MBBI,
-                                   unsigned SrcReg, bool isKill, int FrameIndex,
-                                   const TargetRegisterClass *RC,
-                                   const TargetRegisterInfo *TRI) const;
-
-  virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
-                                    MachineBasicBlock::iterator MBBI,
-                                    unsigned DestReg, int FrameIndex,
-                                    const TargetRegisterClass *RC,
-                                    const TargetRegisterInfo *TRI) const;
-
-  virtual
-  bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
-
-  virtual bool FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI,
-                             unsigned Reg, MachineRegisterInfo *MRI) const;
+  bool canInsertSelect(const MachineBasicBlock&,
+                       const SmallVectorImpl<MachineOperand> &Cond,
+                       unsigned, unsigned, int&, int&, int&) const override;
+  void insertSelect(MachineBasicBlock &MBB,
+                    MachineBasicBlock::iterator MI, DebugLoc DL,
+                    unsigned DstReg,
+                    const SmallVectorImpl<MachineOperand> &Cond,
+                    unsigned TrueReg, unsigned FalseReg) const override;
+
+  void copyPhysReg(MachineBasicBlock &MBB,
+                   MachineBasicBlock::iterator I, DebugLoc DL,
+                   unsigned DestReg, unsigned SrcReg,
+                   bool KillSrc) const override;
+
+  void storeRegToStackSlot(MachineBasicBlock &MBB,
+                           MachineBasicBlock::iterator MBBI,
+                           unsigned SrcReg, bool isKill, int FrameIndex,
+                           const TargetRegisterClass *RC,
+                           const TargetRegisterInfo *TRI) const override;
+
+  void loadRegFromStackSlot(MachineBasicBlock &MBB,
+                            MachineBasicBlock::iterator MBBI,
+                            unsigned DestReg, int FrameIndex,
+                            const TargetRegisterClass *RC,
+                            const TargetRegisterInfo *TRI) const override;
+
+  bool
+  ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
+
+  bool FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI,
+                     unsigned Reg, MachineRegisterInfo *MRI) const override;
 
   // If conversion by predication (only supported by some branch instructions).
   // All of the profitability checks always return true; it is always
   // profitable to use the predicated branches.
-  virtual bool isProfitableToIfCvt(MachineBasicBlock &MBB,
-                                   unsigned NumCycles, unsigned ExtraPredCycles,
-                                   const BranchProbability &Probability) const {
+  bool isProfitableToIfCvt(MachineBasicBlock &MBB,
+                          unsigned NumCycles, unsigned ExtraPredCycles,
+                          const BranchProbability &Probability) const override {
     return true;
   }
 
-  virtual bool isProfitableToIfCvt(MachineBasicBlock &TMBB,
-                                   unsigned NumT, unsigned ExtraT,
-                                   MachineBasicBlock &FMBB,
-                                   unsigned NumF, unsigned ExtraF,
-                                   const BranchProbability &Probability) const;
+  bool isProfitableToIfCvt(MachineBasicBlock &TMBB,
+                           unsigned NumT, unsigned ExtraT,
+                           MachineBasicBlock &FMBB,
+                           unsigned NumF, unsigned ExtraF,
+                           const BranchProbability &Probability) const override;
 
-  virtual bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB,
-                                         unsigned NumCycles,
-                                         const BranchProbability
-                                         &Probability) const {
+  bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB,
+                                 unsigned NumCycles,
+                                 const BranchProbability
+                                 &Probability) const override {
     return true;
   }
 
-  virtual bool isProfitableToUnpredicate(MachineBasicBlock &TMBB,
-                                         MachineBasicBlock &FMBB) const {
+  bool isProfitableToUnpredicate(MachineBasicBlock &TMBB,
+                                 MachineBasicBlock &FMBB) const override {
     return false;
   }
 
   // Predication support.
-  bool isPredicated(const MachineInstr *MI) const;
+  bool isPredicated(const MachineInstr *MI) const override;
 
-  virtual bool isUnpredicatedTerminator(const MachineInstr *MI) const;
+  bool isUnpredicatedTerminator(const MachineInstr *MI) const override;
 
-  virtual
   bool PredicateInstruction(MachineInstr *MI,
-                            const SmallVectorImpl<MachineOperand> &Pred) const;
+                    const SmallVectorImpl<MachineOperand> &Pred) const override;
 
-  virtual
   bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
-                         const SmallVectorImpl<MachineOperand> &Pred2) const;
+                   const SmallVectorImpl<MachineOperand> &Pred2) const override;
 
-  virtual bool DefinesPredicate(MachineInstr *MI,
-                                std::vector<MachineOperand> &Pred) const;
+  bool DefinesPredicate(MachineInstr *MI,
+                        std::vector<MachineOperand> &Pred) const override;
 
-  virtual bool isPredicable(MachineInstr *MI) const;
+  bool isPredicable(MachineInstr *MI) const override;
 
   // Comparison optimization.
 
 
-  virtual bool analyzeCompare(const MachineInstr *MI,
-                              unsigned &SrcReg, unsigned &SrcReg2,
-                              int &Mask, int &Value) const;
+  bool analyzeCompare(const MachineInstr *MI,
+                      unsigned &SrcReg, unsigned &SrcReg2,
+                      int &Mask, int &Value) const override;
 
-  virtual bool optimizeCompareInstr(MachineInstr *CmpInstr,
-                                    unsigned SrcReg, unsigned SrcReg2,
-                                    int Mask, int Value,
-                                    const MachineRegisterInfo *MRI) const;
+  bool optimizeCompareInstr(MachineInstr *CmpInstr,
+                            unsigned SrcReg, unsigned SrcReg2,
+                            int Mask, int Value,
+                            const MachineRegisterInfo *MRI) const override;
 
   /// GetInstSize - Return the number of bytes of code the specified
   /// instruction may be.  This returns the maximum number of bytes.
   ///
-  virtual unsigned GetInstSizeInBytes(const MachineInstr *MI) const;
+  unsigned GetInstSizeInBytes(const MachineInstr *MI) const;
 };
 
 }
diff --git a/lib/Target/PowerPC/PPCJITInfo.h b/lib/Target/PowerPC/PPCJITInfo.h
index 46d4a08eb6..0693e3e86c 100644
--- a/lib/Target/PowerPC/PPCJITInfo.h
+++ b/lib/Target/PowerPC/PPCJITInfo.h
@@ -30,19 +30,19 @@ namespace llvm {
       is64Bit = tmIs64Bit;
     }
 
-    virtual StubLayout getStubLayout();
-    virtual void *emitFunctionStub(const Function* F, void *Fn,
-                                   JITCodeEmitter &JCE);
-    virtual LazyResolverFn getLazyResolverFunction(JITCompilerFn);
-    virtual void relocate(void *Function, MachineRelocation *MR,
-                          unsigned NumRelocs, unsigned char* GOTBase);
-    
+    StubLayout getStubLayout() override;
+    void *emitFunctionStub(const Function* F, void *Fn,
+                           JITCodeEmitter &JCE) override;
+    LazyResolverFn getLazyResolverFunction(JITCompilerFn) override;
+    void relocate(void *Function, MachineRelocation *MR,
+                  unsigned NumRelocs, unsigned char* GOTBase) override;
+
     /// replaceMachineCodeForFunction - Make it so that calling the function
     /// whose machine code is at OLD turns into a call to NEW, perhaps by
     /// overwriting OLD with a branch to NEW.  This is used for self-modifying
     /// code.
     ///
-    virtual void replaceMachineCodeForFunction(void *Old, void *New);
+    void replaceMachineCodeForFunction(void *Old, void *New) override;
   };
 }
 
diff --git a/lib/Target/PowerPC/PPCRegisterInfo.h b/lib/Target/PowerPC/PPCRegisterInfo.h
index 02b9179f64..13a35f6309 100644
--- a/lib/Target/PowerPC/PPCRegisterInfo.h
+++ b/lib/Target/PowerPC/PPCRegisterInfo.h
@@ -34,36 +34,37 @@ public:
   
   /// getPointerRegClass - Return the register class to use to hold pointers.
   /// This is used for addressing modes.
-  virtual const TargetRegisterClass *
-  getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const;
+  const TargetRegisterClass *
+  getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const override;
 
   unsigned getRegPressureLimit(const TargetRegisterClass *RC,
-                               MachineFunction &MF) const;
+                               MachineFunction &MF) const override;
 
   const TargetRegisterClass*
-  getLargestLegalSuperClass(const TargetRegisterClass *RC) const;
+  getLargestLegalSuperClass(const TargetRegisterClass *RC) const override;
 
   /// Code Generation virtual methods...
-  const MCPhysReg *getCalleeSavedRegs(const MachineFunction* MF =nullptr) const;
-  const uint32_t *getCallPreservedMask(CallingConv::ID CC) const;
+  const MCPhysReg *
+  getCalleeSavedRegs(const MachineFunction* MF =nullptr) const override;
+  const uint32_t *getCallPreservedMask(CallingConv::ID CC) const override;
   const uint32_t *getNoPreservedMask() const;
 
-  BitVector getReservedRegs(const MachineFunction &MF) const;
+  BitVector getReservedRegs(const MachineFunction &MF) const override;
 
   /// We require the register scavenger.
-  bool requiresRegisterScavenging(const MachineFunction &MF) const {
+  bool requiresRegisterScavenging(const MachineFunction &MF) const override {
     return true;
   }
 
-  bool requiresFrameIndexScavenging(const MachineFunction &MF) const {
+  bool requiresFrameIndexScavenging(const MachineFunction &MF) const override {
     return true;
   }
 
-  bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const {
+  bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override {
     return true;
   }
 
-  virtual bool requiresVirtualBaseRegisters(const MachineFunction &MF) const {
+  bool requiresVirtualBaseRegisters(const MachineFunction &MF) const override {
     return true;
   }
 
@@ -82,28 +83,29 @@ public:
                           unsigned FrameIndex) const;
 
   bool hasReservedSpillSlot(const MachineFunction &MF, unsigned Reg,
-			    int &FrameIdx) const;
+			    int &FrameIdx) const override;
   void eliminateFrameIndex(MachineBasicBlock::iterator II,
                            int SPAdj, unsigned FIOperandNum,
-                           RegScavenger *RS = nullptr) const;
+                           RegScavenger *RS = nullptr) const override;
 
   // Support for virtual base registers.
-  bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const;
+  bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override;
   void materializeFrameBaseRegister(MachineBasicBlock *MBB,
                                     unsigned BaseReg, int FrameIdx,
-                                    int64_t Offset) const;
+                                    int64_t Offset) const override;
   void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
-                         int64_t Offset) const;
-  bool isFrameOffsetLegal(const MachineInstr *MI, int64_t Offset) const;
+                         int64_t Offset) const override;
+  bool isFrameOffsetLegal(const MachineInstr *MI,
+                          int64_t Offset) const override;
 
   // Debug information queries.
-  unsigned getFrameRegister(const MachineFunction &MF) const;
+  unsigned getFrameRegister(const MachineFunction &MF) const override;
 
   // Base pointer (stack realignment) support.
   unsigned getBaseRegister(const MachineFunction &MF) const;
   bool hasBasePointer(const MachineFunction &MF) const;
   bool canRealignStack(const MachineFunction &MF) const;
-  bool needsStackRealignment(const MachineFunction &MF) const;
+  bool needsStackRealignment(const MachineFunction &MF) const override;
 };
 
 } // end namespace llvm
diff --git a/lib/Target/PowerPC/PPCSubtarget.h b/lib/Target/PowerPC/PPCSubtarget.h
index 87e012ece1..75dff0679f 100644
--- a/lib/Target/PowerPC/PPCSubtarget.h
+++ b/lib/Target/PowerPC/PPCSubtarget.h
@@ -129,7 +129,7 @@ public:
   const InstrItineraryData &getInstrItineraryData() const { return InstrItins; }
 
   /// \brief Reset the features for the PowerPC target.
-  virtual void resetSubtargetFeatures(const MachineFunction *MF);
+  void resetSubtargetFeatures(const MachineFunction *MF) override;
 private:
   void initializeEnvironment();
   void resetSubtargetFeatures(StringRef CPU, StringRef FS);
@@ -200,15 +200,15 @@ public:
   /// enablePostRAScheduler - True at 'More' optimization.
   bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
                              TargetSubtargetInfo::AntiDepBreakMode& Mode,
-                             RegClassVector& CriticalPathRCs) const;
+                             RegClassVector& CriticalPathRCs) const override;
 
   // Scheduling customization.
-  bool enableMachineScheduler() const;
+  bool enableMachineScheduler() const override;
   void overrideSchedPolicy(MachineSchedPolicy &Policy,
                            MachineInstr *begin,
                            MachineInstr *end,
-                           unsigned NumRegionInstrs) const;
-  bool useAA() const;
+                           unsigned NumRegionInstrs) const override;
+  bool useAA() const override;
 };
 } // End llvm namespace
 
diff --git a/lib/Target/PowerPC/PPCTargetMachine.cpp b/lib/Target/PowerPC/PPCTargetMachine.cpp
index e7438f394c..fdfb8c9bfc 100644
--- a/lib/Target/PowerPC/PPCTargetMachine.cpp
+++ b/lib/Target/PowerPC/PPCTargetMachine.cpp
@@ -127,12 +127,12 @@ public:
     return *getPPCTargetMachine().getSubtargetImpl();
   }
 
-  virtual bool addPreISel();
-  virtual bool addILPOpts();
-  virtual bool addInstSelector();
-  virtual bool addPreRegAlloc();
-  virtual bool addPreSched2();
-  virtual bool addPreEmitPass();
+  bool addPreISel() override;
+  bool addILPOpts() override;
+  bool addInstSelector() override;
+  bool addPreRegAlloc() override;
+  bool addPreSched2() override;
+  bool addPreEmitPass() override;
 };
 } // namespace
 
diff --git a/lib/Target/PowerPC/PPCTargetMachine.h b/lib/Target/PowerPC/PPCTargetMachine.h
index 606ccb3141..9e924945d8 100644
--- a/lib/Target/PowerPC/PPCTargetMachine.h
+++ b/lib/Target/PowerPC/PPCTargetMachine.h
@@ -43,34 +43,34 @@ public:
                    Reloc::Model RM, CodeModel::Model CM,
                    CodeGenOpt::Level OL, bool is64Bit);
 
-  virtual const PPCInstrInfo      *getInstrInfo() const { return &InstrInfo; }
-  virtual const PPCFrameLowering  *getFrameLowering() const {
+  const PPCInstrInfo      *getInstrInfo() const override { return &InstrInfo; }
+  const PPCFrameLowering  *getFrameLowering() const override {
     return &FrameLowering;
   }
-  virtual       PPCJITInfo        *getJITInfo()         { return &JITInfo; }
-  virtual const PPCTargetLowering *getTargetLowering() const {
+        PPCJITInfo        *getJITInfo() override         { return &JITInfo; }
+  const PPCTargetLowering *getTargetLowering() const override {
    return &TLInfo;
   }
-  virtual const PPCSelectionDAGInfo* getSelectionDAGInfo() const {
+  const PPCSelectionDAGInfo* getSelectionDAGInfo() const override {
     return &TSInfo;
   }
-  virtual const PPCRegisterInfo   *getRegisterInfo() const {
+  const PPCRegisterInfo   *getRegisterInfo() const override {
     return &InstrInfo.getRegisterInfo();
   }
 
-  virtual const DataLayout    *getDataLayout() const    { return &DL; }
-  virtual const PPCSubtarget  *getSubtargetImpl() const { return &Subtarget; }
-  virtual const InstrItineraryData *getInstrItineraryData() const {
+  const DataLayout    *getDataLayout() const override    { return &DL; }
+  const PPCSubtarget  *getSubtargetImpl() const override { return &Subtarget; }
+  const InstrItineraryData *getInstrItineraryData() const override {
     return &InstrItins;
   }
 
   // Pass Pipeline Configuration
-  virtual TargetPassConfig *createPassConfig(PassManagerBase &PM);
-  virtual bool addCodeEmitter(PassManagerBase &PM,
-                              JITCodeEmitter &JCE);
+  TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
+  bool addCodeEmitter(PassManagerBase &PM,
+                      JITCodeEmitter &JCE) override;
 
   /// \brief Register PPC analysis passes with a pass manager.
-  virtual void addAnalysisPasses(PassManagerBase &PM);
+  void addAnalysisPasses(PassManagerBase &PM) override;
 };
 
 /// PPC32TargetMachine - PowerPC 32-bit target machine.
diff --git a/lib/Target/R600/AMDGPU.h b/lib/Target/R600/AMDGPU.h
index 3e1848b5f8..5d0cf81c40 100644
--- a/lib/Target/R600/AMDGPU.h
+++ b/lib/Target/R600/AMDGPU.h
@@ -37,11 +37,15 @@ FunctionPass *createAMDGPUCFGStructurizerPass();
 // SI Passes
 FunctionPass *createSITypeRewriter();
 FunctionPass *createSIAnnotateControlFlowPass();
+FunctionPass *createSILowerI1CopiesPass();
 FunctionPass *createSILowerControlFlowPass(TargetMachine &tm);
 FunctionPass *createSIFixSGPRCopiesPass(TargetMachine &tm);
 FunctionPass *createSICodeEmitterPass(formatted_raw_ostream &OS);
 FunctionPass *createSIInsertWaits(TargetMachine &tm);
 
+void initializeSILowerI1CopiesPass(PassRegistry &);
+extern char &SILowerI1CopiesID;
+
 // Passes common to R600 and SI
 Pass *createAMDGPUStructurizeCFGPass();
 FunctionPass *createAMDGPUConvertToISAPass(TargetMachine &tm);
diff --git a/lib/Target/R600/AMDGPUAsmPrinter.h b/lib/Target/R600/AMDGPUAsmPrinter.h
index 60e3b08095..71adc9a4d1 100644
--- a/lib/Target/R600/AMDGPUAsmPrinter.h
+++ b/lib/Target/R600/AMDGPUAsmPrinter.h
@@ -47,14 +47,14 @@ private:
 public:
   explicit AMDGPUAsmPrinter(TargetMachine &TM, MCStreamer &Streamer);
 
-  virtual bool runOnMachineFunction(MachineFunction &MF);
+  bool runOnMachineFunction(MachineFunction &MF) override;
 
-  virtual const char *getPassName() const {
+  const char *getPassName() const override {
     return "AMDGPU Assembly Printer";
   }
 
   /// Implemented in AMDGPUMCInstLower.cpp
-  virtual void EmitInstruction(const MachineInstr *MI);
+  void EmitInstruction(const MachineInstr *MI) override;
 
 protected:
   bool DisasmEnabled;
diff --git a/lib/Target/R600/AMDGPUConvertToISA.cpp b/lib/Target/R600/AMDGPUConvertToISA.cpp
index 50297d1f60..91aeee2fc5 100644
--- a/lib/Target/R600/AMDGPUConvertToISA.cpp
+++ b/lib/Target/R600/AMDGPUConvertToISA.cpp
@@ -31,9 +31,9 @@ public:
   AMDGPUConvertToISAPass(TargetMachine &tm) :
     MachineFunctionPass(ID), TM(tm) { }
 
-  virtual bool runOnMachineFunction(MachineFunction &MF);
+  bool runOnMachineFunction(MachineFunction &MF) override;
 
-  virtual const char *getPassName() const {return "AMDGPU Convert to ISA";}
+  const char *getPassName() const override {return "AMDGPU Convert to ISA";}
 
 };
 
diff --git a/lib/Target/R600/AMDGPUFrameLowering.h b/lib/Target/R600/AMDGPUFrameLowering.h
index cf5742ee09..d18ede5004 100644
--- a/lib/Target/R600/AMDGPUFrameLowering.h
+++ b/lib/Target/R600/AMDGPUFrameLowering.h
@@ -33,12 +33,13 @@ public:
 
   /// \returns The number of 32-bit sub-registers that are used when storing
   /// values to the stack.
-  virtual unsigned getStackWidth(const MachineFunction &MF) const;
-  virtual int getFrameIndexOffset(const MachineFunction &MF, int FI) const;
-  virtual const SpillSlot *getCalleeSavedSpillSlots(unsigned &NumEntries) const;
-  virtual void emitPrologue(MachineFunction &MF) const;
-  virtual void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
-  virtual bool hasFP(const MachineFunction &MF) const;
+  unsigned getStackWidth(const MachineFunction &MF) const;
+  int getFrameIndexOffset(const MachineFunction &MF, int FI) const override;
+  const SpillSlot *
+    getCalleeSavedSpillSlots(unsigned &NumEntries) const override;
+  void emitPrologue(MachineFunction &MF) const override;
+  void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override;
+  bool hasFP(const MachineFunction &MF) const override;
 };
 } // namespace llvm
 #endif // AMDILFRAME_LOWERING_H
diff --git a/lib/Target/R600/AMDGPUISelDAGToDAG.cpp b/lib/Target/R600/AMDGPUISelDAGToDAG.cpp
index 841cbda94f..ba705db69d 100644
--- a/lib/Target/R600/AMDGPUISelDAGToDAG.cpp
+++ b/lib/Target/R600/AMDGPUISelDAGToDAG.cpp
@@ -16,9 +16,11 @@
 #include "AMDGPURegisterInfo.h"
 #include "R600InstrInfo.h"
 #include "SIISelLowering.h"
+#include "llvm/CodeGen/FunctionLoweringInfo.h"
 #include "llvm/CodeGen/PseudoSourceValue.h"
 #include "llvm/CodeGen/SelectionDAG.h"
 #include "llvm/CodeGen/SelectionDAGISel.h"
+#include "llvm/IR/Function.h"
 
 using namespace llvm;
 
@@ -37,9 +39,9 @@ public:
   AMDGPUDAGToDAGISel(TargetMachine &TM);
   virtual ~AMDGPUDAGToDAGISel();
 
-  SDNode *Select(SDNode *N);
-  virtual const char *getPassName() const;
-  virtual void PostprocessISelDAG();
+  SDNode *Select(SDNode *N) override;
+  const char *getPassName() const override;
+  void PostprocessISelDAG() override;
 
 private:
   bool isInlineImmediate(SDNode *N) const;
@@ -70,6 +72,11 @@ private:
   bool isLocalLoad(const LoadSDNode *N) const;
   bool isRegionLoad(const LoadSDNode *N) const;
 
+  /// \returns True if the current basic block being selected is at control
+  ///          flow depth 0.  Meaning that the current block dominates the
+  //           exit block.
+  bool isCFDepth0() const;
+
   const TargetRegisterClass *getOperandRegClass(SDNode *N, unsigned OpNo) const;
   bool SelectGlobalValueConstantOffset(SDValue Addr, SDValue& IntPtr);
   bool SelectGlobalValueVariableOffset(SDValue Addr, SDValue &BaseReg,
@@ -565,6 +572,14 @@ bool AMDGPUDAGToDAGISel::isPrivateLoad(const LoadSDNode *N) const {
   return false;
 }
 
+bool AMDGPUDAGToDAGISel::isCFDepth0() const {
+  // FIXME: Figure out a way to use DominatorTree analysis here.
+  const BasicBlock *CurBlock = FuncInfo->MBB->getBasicBlock();
+  const Function *Fn = FuncInfo->Fn;
+  return &Fn->front() == CurBlock || &Fn->back() == CurBlock;
+}
+
+
 const char *AMDGPUDAGToDAGISel::getPassName() const {
   return "AMDGPU DAG->DAG Pattern Instruction Selection";
 }
diff --git a/lib/Target/R600/AMDGPUISelLowering.cpp b/lib/Target/R600/AMDGPUISelLowering.cpp
index 5a534627bc..52a500c0d5 100644
--- a/lib/Target/R600/AMDGPUISelLowering.cpp
+++ b/lib/Target/R600/AMDGPUISelLowering.cpp
@@ -203,6 +203,7 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM) :
 
   setOperationAction(ISD::UDIV, MVT::i32, Expand);
   setOperationAction(ISD::UDIVREM, MVT::i32, Custom);
+  setOperationAction(ISD::UDIVREM, MVT::i64, Custom);
   setOperationAction(ISD::UREM, MVT::i32, Expand);
   setOperationAction(ISD::VSELECT, MVT::v2f32, Expand);
   setOperationAction(ISD::VSELECT, MVT::v4f32, Expand);
@@ -408,7 +409,96 @@ void AMDGPUTargetLowering::ReplaceNodeResults(SDNode *N,
     // ReplaceNodeResults to sext_in_reg to an illegal type, so we'll just do
     // nothing here and let the illegal result integer be handled normally.
     return;
+  case ISD::UDIV: {
+    SDValue Op = SDValue(N, 0);
+    SDLoc DL(Op);
+    EVT VT = Op.getValueType();
+    SDValue UDIVREM = DAG.getNode(ISD::UDIVREM, DL, DAG.getVTList(VT, VT),
+      N->getOperand(0), N->getOperand(1));
+    Results.push_back(UDIVREM);
+    break;
+  }
+  case ISD::UREM: {
+    SDValue Op = SDValue(N, 0);
+    SDLoc DL(Op);
+    EVT VT = Op.getValueType();
+    SDValue UDIVREM = DAG.getNode(ISD::UDIVREM, DL, DAG.getVTList(VT, VT),
+      N->getOperand(0), N->getOperand(1));
+    Results.push_back(UDIVREM.getValue(1));
+    break;
+  }
+  case ISD::UDIVREM: {
+    SDValue Op = SDValue(N, 0);
+    SDLoc DL(Op);
+    EVT VT = Op.getValueType();
+    EVT HalfVT = VT.getHalfSizedIntegerVT(*DAG.getContext());
+
+    SDValue one = DAG.getConstant(1, HalfVT);
+    SDValue zero = DAG.getConstant(0, HalfVT);
+
+    //HiLo split
+    SDValue LHS = N->getOperand(0);
+    SDValue LHS_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, LHS, zero);
+    SDValue LHS_Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, LHS, one);
+
+    SDValue RHS = N->getOperand(1);
+    SDValue RHS_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, RHS, zero);
+    SDValue RHS_Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, RHS, one);
+
+    // Get Speculative values
+    SDValue DIV_Part = DAG.getNode(ISD::UDIV, DL, HalfVT, LHS_Hi, RHS_Lo);
+    SDValue REM_Part = DAG.getNode(ISD::UREM, DL, HalfVT, LHS_Hi, RHS_Lo);
+
+    SDValue REM_Hi = zero;
+    SDValue REM_Lo = DAG.getSelectCC(DL, RHS_Hi, zero, REM_Part, LHS_Hi, ISD::SETEQ);
+
+    SDValue DIV_Hi = DAG.getSelectCC(DL, RHS_Hi, zero, DIV_Part, zero, ISD::SETEQ);
+    SDValue DIV_Lo = zero;
+
+    const unsigned halfBitWidth = HalfVT.getSizeInBits();
+
+    for (unsigned i = 0; i < halfBitWidth; ++i) {
+      SDValue POS = DAG.getConstant(halfBitWidth - i - 1, HalfVT);
+      // Get Value of high bit
+      SDValue HBit;
+      if (halfBitWidth == 32 && Subtarget->hasBFE()) {
+        HBit = DAG.getNode(AMDGPUISD::BFE_U32, DL, HalfVT, LHS_Lo, POS, one);
+      } else {
+        HBit = DAG.getNode(ISD::SRL, DL, HalfVT, LHS_Lo, POS);
+        HBit = DAG.getNode(ISD::AND, DL, HalfVT, HBit, one);
+      }
+
+      SDValue Carry = DAG.getNode(ISD::SRL, DL, HalfVT, REM_Lo,
+        DAG.getConstant(halfBitWidth - 1, HalfVT));
+      REM_Hi = DAG.getNode(ISD::SHL, DL, HalfVT, REM_Hi, one);
+      REM_Hi = DAG.getNode(ISD::OR, DL, HalfVT, REM_Hi, Carry);
+
+      REM_Lo = DAG.getNode(ISD::SHL, DL, HalfVT, REM_Lo, one);
+      REM_Lo = DAG.getNode(ISD::OR, DL, HalfVT, REM_Lo, HBit);
+
+
+      SDValue REM = DAG.getNode(ISD::BUILD_PAIR, DL, VT, REM_Lo, REM_Hi);
 
+      SDValue BIT = DAG.getConstant(1 << (halfBitWidth - i - 1), HalfVT);
+      SDValue realBIT = DAG.getSelectCC(DL, REM, RHS, BIT, zero, ISD::SETGE);
+
+      DIV_Lo = DAG.getNode(ISD::OR, DL, HalfVT, DIV_Lo, realBIT);
+
+      // Update REM
+
+      SDValue REM_sub = DAG.getNode(ISD::SUB, DL, VT, REM, RHS);
+
+      REM = DAG.getSelectCC(DL, REM, RHS, REM_sub, REM, ISD::SETGE);
+      REM_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, REM, zero);
+      REM_Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, REM, one);
+    }
+
+    SDValue REM = DAG.getNode(ISD::BUILD_PAIR, DL, VT, REM_Lo, REM_Hi);
+    SDValue DIV = DAG.getNode(ISD::BUILD_PAIR, DL, VT, DIV_Lo, DIV_Hi);
+    Results.push_back(DIV);
+    Results.push_back(REM);
+    break;
+  }
   default:
     return;
   }
@@ -952,8 +1042,6 @@ SDValue AMDGPUTargetLowering::LowerUDIVREM(SDValue Op,
   SDValue Num = Op.getOperand(0);
   SDValue Den = Op.getOperand(1);
 
-  SmallVector<SDValue, 8> Results;
-
   // RCP =  URECIP(Den) = 2^32 / Den + e
   // e is rounding error.
   SDValue RCP = DAG.getNode(AMDGPUISD::URECIP, DL, VT, Den);
diff --git a/lib/Target/R600/AMDGPUISelLowering.h b/lib/Target/R600/AMDGPUISelLowering.h
index 2537a85012..8db476cacf 100644
--- a/lib/Target/R600/AMDGPUISelLowering.h
+++ b/lib/Target/R600/AMDGPUISelLowering.h
@@ -80,61 +80,62 @@ protected:
 public:
   AMDGPUTargetLowering(TargetMachine &TM);
 
-  virtual bool isFAbsFree(EVT VT) const override;
-  virtual bool isFNegFree(EVT VT) const override;
-  virtual bool isTruncateFree(EVT Src, EVT Dest) const override;
-  virtual bool isTruncateFree(Type *Src, Type *Dest) const override;
-
-  virtual bool isZExtFree(Type *Src, Type *Dest) const override;
-  virtual bool isZExtFree(EVT Src, EVT Dest) const override;
-
-  virtual bool isNarrowingProfitable(EVT VT1, EVT VT2) const override;
-
-  virtual MVT getVectorIdxTy() const override;
-  virtual bool isLoadBitCastBeneficial(EVT, EVT) const override;
-  virtual SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv,
-                              bool isVarArg,
-                              const SmallVectorImpl<ISD::OutputArg> &Outs,
-                              const SmallVectorImpl<SDValue> &OutVals,
-                              SDLoc DL, SelectionDAG &DAG) const;
-  virtual SDValue LowerCall(CallLoweringInfo &CLI,
-                            SmallVectorImpl<SDValue> &InVals) const;
-
-  virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
-  virtual void ReplaceNodeResults(SDNode * N,
-                                  SmallVectorImpl<SDValue> &Results,
-                                  SelectionDAG &DAG) const override;
+  bool isFAbsFree(EVT VT) const override;
+  bool isFNegFree(EVT VT) const override;
+  bool isTruncateFree(EVT Src, EVT Dest) const override;
+  bool isTruncateFree(Type *Src, Type *Dest) const override;
+
+  bool isZExtFree(Type *Src, Type *Dest) const override;
+  bool isZExtFree(EVT Src, EVT Dest) const override;
+
+  bool isNarrowingProfitable(EVT VT1, EVT VT2) const override;
+
+  MVT getVectorIdxTy() const override;
+  bool isLoadBitCastBeneficial(EVT, EVT) const override;
+  SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv,
+                      bool isVarArg,
+                      const SmallVectorImpl<ISD::OutputArg> &Outs,
+                      const SmallVectorImpl<SDValue> &OutVals,
+                      SDLoc DL, SelectionDAG &DAG) const override;
+  SDValue LowerCall(CallLoweringInfo &CLI,
+                    SmallVectorImpl<SDValue> &InVals) const override;
+
+  SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
+  void ReplaceNodeResults(SDNode * N,
+                          SmallVectorImpl<SDValue> &Results,
+                          SelectionDAG &DAG) const override;
 
   SDValue LowerIntrinsicIABS(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerIntrinsicLRP(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerMinMax(SDValue Op, SelectionDAG &DAG) const;
-  virtual const char* getTargetNodeName(unsigned Opcode) const;
+  const char* getTargetNodeName(unsigned Opcode) const override;
 
-  virtual SDNode *PostISelFolding(MachineSDNode *N, SelectionDAG &DAG) const {
+  virtual SDNode *PostISelFolding(MachineSDNode *N,
+                                  SelectionDAG &DAG) const {
     return N;
   }
 
   /// \brief Determine which of the bits specified in \p Mask are known to be
   /// either zero or one and return them in the \p KnownZero and \p KnownOne
   /// bitsets.
-  virtual void computeMaskedBitsForTargetNode(const SDValue Op,
-                                              APInt &KnownZero,
-                                              APInt &KnownOne,
-                                              const SelectionDAG &DAG,
-                                              unsigned Depth = 0) const override;
+  void computeMaskedBitsForTargetNode(const SDValue Op,
+                                      APInt &KnownZero,
+                                      APInt &KnownOne,
+                                      const SelectionDAG &DAG,
+                                      unsigned Depth = 0) const override;
 
 // Functions defined in AMDILISelLowering.cpp
 public:
-  virtual bool getTgtMemIntrinsic(IntrinsicInfo &Info,
-                                  const CallInst &I, unsigned Intrinsic) const;
+  bool getTgtMemIntrinsic(IntrinsicInfo &Info,
+                          const CallInst &I, unsigned Intrinsic) const override;
 
   /// We want to mark f32/f64 floating point values as legal.
-  bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
+  bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
 
   /// We don't want to shrink f64/f32 constants.
-  bool ShouldShrinkFPConstant(EVT VT) const;
+  bool ShouldShrinkFPConstant(EVT VT) const override;
 
-  SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
+  SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
 
 private:
   void InitAMDILLowering();
diff --git a/lib/Target/R600/AMDGPUInstrInfo.h b/lib/Target/R600/AMDGPUInstrInfo.h
index c23960bf32..74baf6b2a6 100644
--- a/lib/Target/R600/AMDGPUInstrInfo.h
+++ b/lib/Target/R600/AMDGPUInstrInfo.h
@@ -52,14 +52,15 @@ public:
   virtual const AMDGPURegisterInfo &getRegisterInfo() const = 0;
 
   bool isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg,
-                             unsigned &DstReg, unsigned &SubIdx) const;
+                             unsigned &DstReg, unsigned &SubIdx) const override;
 
-  unsigned isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const;
+  unsigned isLoadFromStackSlot(const MachineInstr *MI,
+                               int &FrameIndex) const override;
   unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI,
-                                     int &FrameIndex) const;
+                                     int &FrameIndex) const override;
   bool hasLoadFromStackSlot(const MachineInstr *MI,
                             const MachineMemOperand *&MMO,
-                            int &FrameIndex) const;
+                            int &FrameIndex) const override;
   unsigned isStoreFromStackSlot(const MachineInstr *MI, int &FrameIndex) const;
   unsigned isStoreFromStackSlotPostFE(const MachineInstr *MI,
                                       int &FrameIndex) const;
@@ -70,7 +71,7 @@ public:
   MachineInstr *
   convertToThreeAddress(MachineFunction::iterator &MFI,
                         MachineBasicBlock::iterator &MBBI,
-                        LiveVariables *LV) const;
+                        LiveVariables *LV) const override;
 
 
   virtual void copyPhysReg(MachineBasicBlock &MBB,
@@ -78,61 +79,62 @@ public:
                            unsigned DestReg, unsigned SrcReg,
                            bool KillSrc) const = 0;
 
-  virtual bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const;
+  bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const override;
 
-  virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
-                                   MachineBasicBlock::iterator MI,
-                                   unsigned SrcReg, bool isKill, int FrameIndex,
-                                   const TargetRegisterClass *RC,
-                                   const TargetRegisterInfo *TRI) const;
-  virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
-                                    MachineBasicBlock::iterator MI,
-                                    unsigned DestReg, int FrameIndex,
-                                    const TargetRegisterClass *RC,
-                                    const TargetRegisterInfo *TRI) const;
+  void storeRegToStackSlot(MachineBasicBlock &MBB,
+                           MachineBasicBlock::iterator MI,
+                           unsigned SrcReg, bool isKill, int FrameIndex,
+                           const TargetRegisterClass *RC,
+                           const TargetRegisterInfo *TRI) const override;
+  void loadRegFromStackSlot(MachineBasicBlock &MBB,
+                            MachineBasicBlock::iterator MI,
+                            unsigned DestReg, int FrameIndex,
+                            const TargetRegisterClass *RC,
+                            const TargetRegisterInfo *TRI) const override;
 
 protected:
   MachineInstr *foldMemoryOperandImpl(MachineFunction &MF,
                                       MachineInstr *MI,
                                       const SmallVectorImpl<unsigned> &Ops,
-                                      int FrameIndex) const;
+                                      int FrameIndex) const override;
   MachineInstr *foldMemoryOperandImpl(MachineFunction &MF,
                                       MachineInstr *MI,
                                       const SmallVectorImpl<unsigned> &Ops,
-                                      MachineInstr *LoadMI) const;
+                                      MachineInstr *LoadMI) const override;
   /// \returns the smallest register index that will be accessed by an indirect
   /// read or write or -1 if indirect addressing is not used by this program.
-  virtual int getIndirectIndexBegin(const MachineFunction &MF) const;
+  int getIndirectIndexBegin(const MachineFunction &MF) const;
 
   /// \returns the largest register index that will be accessed by an indirect
   /// read or write or -1 if indirect addressing is not used by this program.
-  virtual int getIndirectIndexEnd(const MachineFunction &MF) const;
+  int getIndirectIndexEnd(const MachineFunction &MF) const;
 
 public:
   bool canFoldMemoryOperand(const MachineInstr *MI,
-                            const SmallVectorImpl<unsigned> &Ops) const;
+                           const SmallVectorImpl<unsigned> &Ops) const override;
   bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
-                           unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
-                           SmallVectorImpl<MachineInstr *> &NewMIs) const;
+                        unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
+                        SmallVectorImpl<MachineInstr *> &NewMIs) const override;
   bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
-                           SmallVectorImpl<SDNode *> &NewNodes) const;
+                           SmallVectorImpl<SDNode *> &NewNodes) const override;
   unsigned getOpcodeAfterMemoryUnfold(unsigned Opc,
-                                      bool UnfoldLoad, bool UnfoldStore,
-                                      unsigned *LoadRegIndex = nullptr) const;
+                               bool UnfoldLoad, bool UnfoldStore,
+                               unsigned *LoadRegIndex = nullptr) const override;
   bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
                                int64_t Offset1, int64_t Offset2,
-                               unsigned NumLoads) const;
+                               unsigned NumLoads) const override;
 
-  bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
+  bool
+  ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
   void insertNoop(MachineBasicBlock &MBB,
-                  MachineBasicBlock::iterator MI) const;
-  bool isPredicated(const MachineInstr *MI) const;
+                  MachineBasicBlock::iterator MI) const override;
+  bool isPredicated(const MachineInstr *MI) const override;
   bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
-                         const SmallVectorImpl<MachineOperand> &Pred2) const;
+                   const SmallVectorImpl<MachineOperand> &Pred2) const override;
   bool DefinesPredicate(MachineInstr *MI,
-                        std::vector<MachineOperand> &Pred) const;
-  bool isPredicable(MachineInstr *MI) const;
-  bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const;
+                        std::vector<MachineOperand> &Pred) const override;
+  bool isPredicable(MachineInstr *MI) const override;
+  bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const override;
 
   // Helper functions that check the opcode for status information
   bool isLoadInst(llvm::MachineInstr *MI) const;
@@ -186,8 +188,7 @@ public:
 
   /// \brief Convert the AMDIL MachineInstr to a supported ISA
   /// MachineInstr
-  virtual void convertToISA(MachineInstr & MI, MachineFunction &MF,
-    DebugLoc DL) const;
+  void convertToISA(MachineInstr & MI, MachineFunction &MF, DebugLoc DL) const;
 
   /// \brief Build a MOV instruction.
   virtual MachineInstr *buildMovInstr(MachineBasicBlock *MBB,
diff --git a/lib/Target/R600/AMDGPURegisterInfo.h b/lib/Target/R600/AMDGPURegisterInfo.h
index 168d55b962..a7cba0d250 100644
--- a/lib/Target/R600/AMDGPURegisterInfo.h
+++ b/lib/Target/R600/AMDGPURegisterInfo.h
@@ -34,7 +34,7 @@ struct AMDGPURegisterInfo : public AMDGPUGenRegisterInfo {
 
   AMDGPURegisterInfo(TargetMachine &tm);
 
-  virtual BitVector getReservedRegs(const MachineFunction &MF) const {
+  BitVector getReservedRegs(const MachineFunction &MF) const override {
     assert(!"Unimplemented");  return BitVector();
   }
 
@@ -58,11 +58,11 @@ struct AMDGPURegisterInfo : public AMDGPUGenRegisterInfo {
   /// (e.g. getSubRegFromChannel(0) -> AMDGPU::sub0)
   unsigned getSubRegFromChannel(unsigned Channel) const;
 
-  const MCPhysReg* getCalleeSavedRegs(const MachineFunction *MF) const;
+  const MCPhysReg* getCalleeSavedRegs(const MachineFunction *MF) const override;
   void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj,
                            unsigned FIOperandNum,
-                           RegScavenger *RS) const;
-  unsigned getFrameRegister(const MachineFunction &MF) const;
+                           RegScavenger *RS) const override;
+  unsigned getFrameRegister(const MachineFunction &MF) const override;
 
   unsigned getIndirectSubReg(unsigned IndirectIndex) const;
 
diff --git a/lib/Target/R600/AMDGPUSubtarget.cpp b/lib/Target/R600/AMDGPUSubtarget.cpp
index fc34eef7fd..f3b993204a 100644
--- a/lib/Target/R600/AMDGPUSubtarget.cpp
+++ b/lib/Target/R600/AMDGPUSubtarget.cpp
@@ -30,9 +30,6 @@ AMDGPUSubtarget::AMDGPUSubtarget(StringRef TT, StringRef CPU, StringRef FS) :
   // Default card
   StringRef GPU = CPU;
   Is64bit = false;
-  DefaultSize[0] = 64;
-  DefaultSize[1] = 1;
-  DefaultSize[2] = 1;
   HasVertexCache = false;
   TexVTXClauseSize = 0;
   Gen = AMDGPUSubtarget::R600;
@@ -108,14 +105,6 @@ bool
 AMDGPUSubtarget::isTargetELF() const {
   return false;
 }
-size_t
-AMDGPUSubtarget::getDefaultSize(uint32_t dim) const {
-  if (dim > 2) {
-    return 1;
-  } else {
-    return DefaultSize[dim];
-  }
-}
 
 std::string
 AMDGPUSubtarget::getDeviceName() const {
diff --git a/lib/Target/R600/AMDGPUSubtarget.h b/lib/Target/R600/AMDGPUSubtarget.h
index 7cf102cff6..1b041d6bd2 100644
--- a/lib/Target/R600/AMDGPUSubtarget.h
+++ b/lib/Target/R600/AMDGPUSubtarget.h
@@ -38,7 +38,6 @@ public:
   };
 
 private:
-  size_t DefaultSize[3];
   std::string DevName;
   bool Is64bit;
   bool Is32on64bit;
@@ -60,7 +59,7 @@ public:
   AMDGPUSubtarget(StringRef TT, StringRef CPU, StringRef FS);
 
   const InstrItineraryData &getInstrItineraryData() const { return InstrItins; }
-  virtual void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
+  void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
 
   bool is64bit() const;
   bool hasVertexCache() const;
@@ -92,14 +91,13 @@ public:
   unsigned getStackEntrySize() const;
   bool hasCFAluBug() const;
 
-  virtual bool enableMachineScheduler() const {
+  bool enableMachineScheduler() const override {
     return getGeneration() <= NORTHERN_ISLANDS;
   }
 
   // Helper functions to simplify if statements
   bool isTargetELF() const;
   std::string getDeviceName() const;
-  virtual size_t getDefaultSize(uint32_t dim) const;
   bool dumpCode() const { return DumpCode; }
   bool r600ALUEncoding() const { return R600ALUInst; }
 
diff --git a/lib/Target/R600/AMDGPUTargetMachine.cpp b/lib/Target/R600/AMDGPUTargetMachine.cpp
index 402fdbfd2e..6b68c2abe3 100644
--- a/lib/Target/R600/AMDGPUTargetMachine.cpp
+++ b/lib/Target/R600/AMDGPUTargetMachine.cpp
@@ -103,20 +103,20 @@ public:
     return getTM<AMDGPUTargetMachine>();
   }
 
-  virtual ScheduleDAGInstrs *
-  createMachineScheduler(MachineSchedContext *C) const {
+  ScheduleDAGInstrs *
+  createMachineScheduler(MachineSchedContext *C) const override {
     const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>();
     if (ST.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
       return createR600MachineScheduler(C);
     return nullptr;
   }
 
-  virtual bool addPreISel();
-  virtual bool addInstSelector();
-  virtual bool addPreRegAlloc();
-  virtual bool addPostRegAlloc();
-  virtual bool addPreSched2();
-  virtual bool addPreEmitPass();
+  bool addPreISel() override;
+  bool addInstSelector() override;
+  bool addPreRegAlloc() override;
+  bool addPostRegAlloc() override;
+  bool addPreSched2() override;
+  bool addPreEmitPass() override;
 };
 } // End of anonymous namespace
 
@@ -154,6 +154,7 @@ AMDGPUPassConfig::addPreISel() {
 
 bool AMDGPUPassConfig::addInstSelector() {
   addPass(createAMDGPUISelDag(getAMDGPUTargetMachine()));
+  addPass(createSILowerI1CopiesPass());
   return false;
 }
 
diff --git a/lib/Target/R600/AMDGPUTargetMachine.h b/lib/Target/R600/AMDGPUTargetMachine.h
index 783c556713..1287e134b5 100644
--- a/lib/Target/R600/AMDGPUTargetMachine.h
+++ b/lib/Target/R600/AMDGPUTargetMachine.h
@@ -39,30 +39,32 @@ public:
                       StringRef CPU, TargetOptions Options, Reloc::Model RM,
                       CodeModel::Model CM, CodeGenOpt::Level OL);
   ~AMDGPUTargetMachine();
-  virtual const AMDGPUFrameLowering *getFrameLowering() const {
+  const AMDGPUFrameLowering *getFrameLowering() const override {
     return &FrameLowering;
   }
-  virtual const AMDGPUIntrinsicInfo *getIntrinsicInfo() const {
+  const AMDGPUIntrinsicInfo *getIntrinsicInfo() const override {
     return &IntrinsicInfo;
   }
-  virtual const AMDGPUInstrInfo *getInstrInfo() const {
+  const AMDGPUInstrInfo *getInstrInfo() const override {
     return InstrInfo.get();
   }
-  virtual const AMDGPUSubtarget *getSubtargetImpl() const { return &Subtarget; }
-  virtual const AMDGPURegisterInfo *getRegisterInfo() const {
+  const AMDGPUSubtarget *getSubtargetImpl() const override {
+    return &Subtarget;
+  }
+  const AMDGPURegisterInfo *getRegisterInfo() const override {
     return &InstrInfo->getRegisterInfo();
   }
-  virtual AMDGPUTargetLowering *getTargetLowering() const {
+  AMDGPUTargetLowering *getTargetLowering() const override {
     return TLInfo.get();
   }
-  virtual const InstrItineraryData *getInstrItineraryData() const {
+  const InstrItineraryData *getInstrItineraryData() const override {
     return InstrItins;
   }
-  virtual const DataLayout *getDataLayout() const { return &Layout; }
-  virtual TargetPassConfig *createPassConfig(PassManagerBase &PM);
+  const DataLayout *getDataLayout() const override { return &Layout; }
+  TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
 
   /// \brief Register R600 analysis passes with a pass manager.
-  virtual void addAnalysisPasses(PassManagerBase &PM);
+  void addAnalysisPasses(PassManagerBase &PM) override;
 };
 
 } // End namespace llvm
diff --git a/lib/Target/R600/AMDGPUTargetTransformInfo.cpp b/lib/Target/R600/AMDGPUTargetTransformInfo.cpp
index 96174e95f9..ea78f43158 100644
--- a/lib/Target/R600/AMDGPUTargetTransformInfo.cpp
+++ b/lib/Target/R600/AMDGPUTargetTransformInfo.cpp
@@ -56,9 +56,9 @@ public:
     initializeAMDGPUTTIPass(*PassRegistry::getPassRegistry());
   }
 
-  virtual void initializePass() override { pushTTIStack(this); }
+  void initializePass() override { pushTTIStack(this); }
 
-  virtual void getAnalysisUsage(AnalysisUsage &AU) const override {
+  void getAnalysisUsage(AnalysisUsage &AU) const override {
     TargetTransformInfo::getAnalysisUsage(AU);
   }
 
@@ -66,15 +66,16 @@ public:
   static char ID;
 
   /// Provide necessary pointer adjustments for the two base classes.
-  virtual void *getAdjustedAnalysisPointer(const void *ID) override {
+  void *getAdjustedAnalysisPointer(const void *ID) override {
     if (ID == &TargetTransformInfo::ID)
       return (TargetTransformInfo *)this;
     return this;
   }
 
-  virtual bool hasBranchDivergence() const override;
+  bool hasBranchDivergence() const override;
 
-  virtual void getUnrollingPreferences(Loop *L, UnrollingPreferences &UP) const;
+  void getUnrollingPreferences(Loop *L,
+                               UnrollingPreferences &UP) const override;
 
   /// @}
 };
diff --git a/lib/Target/R600/AMDILCFGStructurizer.cpp b/lib/Target/R600/AMDILCFGStructurizer.cpp
index 9828a04681..f3a0391439 100644
--- a/lib/Target/R600/AMDILCFGStructurizer.cpp
+++ b/lib/Target/R600/AMDILCFGStructurizer.cpp
@@ -139,11 +139,11 @@ public:
     initializeAMDGPUCFGStructurizerPass(*PassRegistry::getPassRegistry());
   }
 
-   const char *getPassName() const {
+   const char *getPassName() const override {
     return "AMDGPU Control Flow Graph structurizer Pass";
   }
 
-  void getAnalysisUsage(AnalysisUsage &AU) const {
+  void getAnalysisUsage(AnalysisUsage &AU) const override {
     AU.addPreserved<MachineFunctionAnalysis>();
     AU.addRequired<MachineFunctionAnalysis>();
     AU.addRequired<MachineDominatorTree>();
@@ -159,7 +159,7 @@ public:
   /// sure all loops have an exit block
   bool prepare();
 
-  bool runOnMachineFunction(MachineFunction &MF) {
+  bool runOnMachineFunction(MachineFunction &MF) override {
     TII = static_cast<const R600InstrInfo *>(MF.getTarget().getInstrInfo());
     TRI = &TII->getRegisterInfo();
     DEBUG(MF.dump(););
diff --git a/lib/Target/R600/AMDILIntrinsicInfo.h b/lib/Target/R600/AMDILIntrinsicInfo.h
index a81354efb9..924275aec2 100644
--- a/lib/Target/R600/AMDILIntrinsicInfo.h
+++ b/lib/Target/R600/AMDILIntrinsicInfo.h
@@ -35,12 +35,12 @@ class AMDGPUIntrinsicInfo : public TargetIntrinsicInfo {
 public:
   AMDGPUIntrinsicInfo(TargetMachine *tm);
   std::string getName(unsigned int IntrId, Type **Tys = nullptr,
-                      unsigned int numTys = 0) const;
-  unsigned int lookupName(const char *Name, unsigned int Len) const;
-  bool isOverloaded(unsigned int IID) const;
+                      unsigned int numTys = 0) const override;
+  unsigned int lookupName(const char *Name, unsigned int Len) const override;
+  bool isOverloaded(unsigned int IID) const override;
   Function *getDeclaration(Module *M, unsigned int ID,
                            Type **Tys = nullptr,
-                           unsigned int numTys = 0) const;
+                           unsigned int numTys = 0) const override;
 };
 
 } // end namespace llvm
diff --git a/lib/Target/R600/CMakeLists.txt b/lib/Target/R600/CMakeLists.txt
index 93a5117975..3c6fa5a7ae 100644
--- a/lib/Target/R600/CMakeLists.txt
+++ b/lib/Target/R600/CMakeLists.txt
@@ -45,6 +45,7 @@ add_llvm_target(R600CodeGen
   SIInstrInfo.cpp
   SIISelLowering.cpp
   SILowerControlFlow.cpp
+  SILowerI1Copies.cpp
   SIMachineFunctionInfo.cpp
   SIRegisterInfo.cpp
   SITypeRewriter.cpp
diff --git a/lib/Target/R600/InstPrinter/AMDGPUInstPrinter.h b/lib/Target/R600/InstPrinter/AMDGPUInstPrinter.h
index 47bd030c90..f30fc49ab0 100644
--- a/lib/Target/R600/InstPrinter/AMDGPUInstPrinter.h
+++ b/lib/Target/R600/InstPrinter/AMDGPUInstPrinter.h
@@ -29,7 +29,7 @@ public:
   void printInstruction(const MCInst *MI, raw_ostream &O);
   static const char *getRegisterName(unsigned RegNo);
 
-  virtual void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot);
+  void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot) override;
 
 private:
   void printU8ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
diff --git a/lib/Target/R600/MCTargetDesc/AMDGPUAsmBackend.cpp b/lib/Target/R600/MCTargetDesc/AMDGPUAsmBackend.cpp
index a6bb59f3a0..489cec742b 100644
--- a/lib/Target/R600/MCTargetDesc/AMDGPUAsmBackend.cpp
+++ b/lib/Target/R600/MCTargetDesc/AMDGPUAsmBackend.cpp
@@ -23,8 +23,8 @@ namespace {
 class AMDGPUMCObjectWriter : public MCObjectWriter {
 public:
   AMDGPUMCObjectWriter(raw_ostream &OS) : MCObjectWriter(OS, true) { }
-  virtual void ExecutePostLayoutBinding(MCAssembler &Asm,
-                                        const MCAsmLayout &Layout) {
+  void ExecutePostLayoutBinding(MCAssembler &Asm,
+                                const MCAsmLayout &Layout) override {
     //XXX: Implement if necessary.
   }
   void RecordRelocation(const MCAssembler &Asm, const MCAsmLayout &Layout,
@@ -34,7 +34,7 @@ public:
     assert(!"Not implemented");
   }
 
-  virtual void WriteObject(MCAssembler &Asm, const MCAsmLayout &Layout);
+  void WriteObject(MCAssembler &Asm, const MCAsmLayout &Layout) override;
 
 };
 
@@ -43,19 +43,19 @@ public:
   AMDGPUAsmBackend(const Target &T)
     : MCAsmBackend() {}
 
-  virtual unsigned getNumFixupKinds() const { return 0; };
-  virtual void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
-                          uint64_t Value, bool IsPCRel) const;
-  virtual bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value,
-                                    const MCRelaxableFragment *DF,
-                                    const MCAsmLayout &Layout) const {
+  unsigned getNumFixupKinds() const override { return 0; };
+  void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
+                  uint64_t Value, bool IsPCRel) const override;
+  bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value,
+                            const MCRelaxableFragment *DF,
+                            const MCAsmLayout &Layout) const override {
     return false;
   }
-  virtual void relaxInstruction(const MCInst &Inst, MCInst &Res) const {
+  void relaxInstruction(const MCInst &Inst, MCInst &Res) const override {
     assert(!"Not implemented");
   }
-  virtual bool mayNeedRelaxation(const MCInst &Inst) const { return false; }
-  virtual bool writeNopData(uint64_t Count, MCObjectWriter *OW) const {
+  bool mayNeedRelaxation(const MCInst &Inst) const override { return false; }
+  bool writeNopData(uint64_t Count, MCObjectWriter *OW) const override {
     return true;
   }
 };
@@ -88,7 +88,7 @@ class ELFAMDGPUAsmBackend : public AMDGPUAsmBackend {
 public:
   ELFAMDGPUAsmBackend(const Target &T) : AMDGPUAsmBackend(T) { }
 
-  MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
+  MCObjectWriter *createObjectWriter(raw_ostream &OS) const override {
     return createAMDGPUELFObjectWriter(OS);
   }
 };
diff --git a/lib/Target/R600/MCTargetDesc/AMDGPUMCAsmInfo.h b/lib/Target/R600/MCTargetDesc/AMDGPUMCAsmInfo.h
index 22afd636ab..59aebece54 100644
--- a/lib/Target/R600/MCTargetDesc/AMDGPUMCAsmInfo.h
+++ b/lib/Target/R600/MCTargetDesc/AMDGPUMCAsmInfo.h
@@ -22,7 +22,7 @@ class StringRef;
 class AMDGPUMCAsmInfo : public MCAsmInfo {
 public:
   explicit AMDGPUMCAsmInfo(StringRef &TT);
-  const MCSection* getNonexecutableStackSection(MCContext &CTX) const;
+  const MCSection* getNonexecutableStackSection(MCContext &CTX) const override;
 };
 } // namespace llvm
 #endif // AMDGPUMCASMINFO_H
diff --git a/lib/Target/R600/MCTargetDesc/R600MCCodeEmitter.cpp b/lib/Target/R600/MCTargetDesc/R600MCCodeEmitter.cpp
index 286c7d1105..5e7cefed0a 100644
--- a/lib/Target/R600/MCTargetDesc/R600MCCodeEmitter.cpp
+++ b/lib/Target/R600/MCTargetDesc/R600MCCodeEmitter.cpp
@@ -41,14 +41,14 @@ public:
     : MCII(mcii), MRI(mri) { }
 
   /// \brief Encode the instruction and write it to the OS.
-  virtual void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
+  void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
                          SmallVectorImpl<MCFixup> &Fixups,
-                         const MCSubtargetInfo &STI) const;
+                         const MCSubtargetInfo &STI) const override;
 
   /// \returns the encoding for an MCOperand.
-  virtual uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO,
-                                     SmallVectorImpl<MCFixup> &Fixups,
-                                     const MCSubtargetInfo &STI) const;
+  uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO,
+                             SmallVectorImpl<MCFixup> &Fixups,
+                             const MCSubtargetInfo &STI) const override;
 private:
 
   void EmitByte(unsigned int byte, raw_ostream &OS) const;
diff --git a/lib/Target/R600/MCTargetDesc/SIMCCodeEmitter.cpp b/lib/Target/R600/MCTargetDesc/SIMCCodeEmitter.cpp
index f42e978be1..ee021115de 100644
--- a/lib/Target/R600/MCTargetDesc/SIMCCodeEmitter.cpp
+++ b/lib/Target/R600/MCTargetDesc/SIMCCodeEmitter.cpp
@@ -54,14 +54,14 @@ public:
   ~SIMCCodeEmitter() { }
 
   /// \brief Encode the instruction and write it to the OS.
-  virtual void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
+  void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
                          SmallVectorImpl<MCFixup> &Fixups,
-                         const MCSubtargetInfo &STI) const;
+                         const MCSubtargetInfo &STI) const override;
 
   /// \returns the encoding for an MCOperand.
-  virtual uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO,
-                                     SmallVectorImpl<MCFixup> &Fixups,
-                                     const MCSubtargetInfo &STI) const;
+  uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO,
+                             SmallVectorImpl<MCFixup> &Fixups,
+                             const MCSubtargetInfo &STI) const override;
 };
 
 } // End anonymous namespace
diff --git a/lib/Target/R600/R600ClauseMergePass.cpp b/lib/Target/R600/R600ClauseMergePass.cpp
index 3f113623d0..92bf0df962 100644
--- a/lib/Target/R600/R600ClauseMergePass.cpp
+++ b/lib/Target/R600/R600ClauseMergePass.cpp
@@ -63,9 +63,9 @@ private:
 public:
   R600ClauseMergePass(TargetMachine &tm) : MachineFunctionPass(ID) { }
 
-  virtual bool runOnMachineFunction(MachineFunction &MF);
+  bool runOnMachineFunction(MachineFunction &MF) override;
 
-  const char *getPassName() const;
+  const char *getPassName() const override;
 };
 
 char R600ClauseMergePass::ID = 0;
diff --git a/lib/Target/R600/R600ControlFlowFinalizer.cpp b/lib/Target/R600/R600ControlFlowFinalizer.cpp
index ef9b8cea01..d255e96905 100644
--- a/lib/Target/R600/R600ControlFlowFinalizer.cpp
+++ b/lib/Target/R600/R600ControlFlowFinalizer.cpp
@@ -475,7 +475,7 @@ public:
       MaxFetchInst = ST.getTexVTXClauseSize();
   }
 
-  virtual bool runOnMachineFunction(MachineFunction &MF) {
+  bool runOnMachineFunction(MachineFunction &MF) override {
     TII=static_cast<const R600InstrInfo *>(MF.getTarget().getInstrInfo());
     TRI=static_cast<const R600RegisterInfo *>(MF.getTarget().getRegisterInfo());
     R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();
@@ -666,7 +666,7 @@ public:
     return false;
   }
 
-  const char *getPassName() const {
+  const char *getPassName() const override {
     return "R600 Control Flow Finalizer Pass";
   }
 };
diff --git a/lib/Target/R600/R600EmitClauseMarkers.cpp b/lib/Target/R600/R600EmitClauseMarkers.cpp
index 660ce0c2db..38afebef40 100644
--- a/lib/Target/R600/R600EmitClauseMarkers.cpp
+++ b/lib/Target/R600/R600EmitClauseMarkers.cpp
@@ -296,7 +296,7 @@ public:
     initializeR600EmitClauseMarkersPass(*PassRegistry::getPassRegistry());
   }
 
-  virtual bool runOnMachineFunction(MachineFunction &MF) {
+  bool runOnMachineFunction(MachineFunction &MF) override {
     TII = static_cast<const R600InstrInfo *>(MF.getTarget().getInstrInfo());
 
     for (MachineFunction::iterator BB = MF.begin(), BB_E = MF.end();
@@ -315,7 +315,7 @@ public:
     return false;
   }
 
-  const char *getPassName() const {
+  const char *getPassName() const override {
     return "R600 Emit Clause Markers Pass";
   }
 };
diff --git a/lib/Target/R600/R600ExpandSpecialInstrs.cpp b/lib/Target/R600/R600ExpandSpecialInstrs.cpp
index 0a130e1365..732b06dc15 100644
--- a/lib/Target/R600/R600ExpandSpecialInstrs.cpp
+++ b/lib/Target/R600/R600ExpandSpecialInstrs.cpp
@@ -40,9 +40,9 @@ public:
   R600ExpandSpecialInstrsPass(TargetMachine &tm) : MachineFunctionPass(ID),
     TII(nullptr) { }
 
-  virtual bool runOnMachineFunction(MachineFunction &MF);
+  bool runOnMachineFunction(MachineFunction &MF) override;
 
-  const char *getPassName() const {
+  const char *getPassName() const override {
     return "R600 Expand special instructions pass";
   }
 };
diff --git a/lib/Target/R600/R600ISelLowering.cpp b/lib/Target/R600/R600ISelLowering.cpp
index ecee4d5cf9..b40cb6724d 100644
--- a/lib/Target/R600/R600ISelLowering.cpp
+++ b/lib/Target/R600/R600ISelLowering.cpp
@@ -82,9 +82,7 @@ R600TargetLowering::R600TargetLowering(TargetMachine &TM) :
   setOperationAction(ISD::SELECT, MVT::i32, Expand);
   setOperationAction(ISD::SELECT, MVT::f32, Expand);
   setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
-  setOperationAction(ISD::SELECT, MVT::v2f32, Expand);
   setOperationAction(ISD::SELECT, MVT::v4i32, Expand);
-  setOperationAction(ISD::SELECT, MVT::v4f32, Expand);
 
   // Expand sign extension of vectors
   if (!Subtarget->hasBFE())
@@ -141,6 +139,11 @@ R600TargetLowering::R600TargetLowering(TargetMachine &TM) :
   setTargetDAGCombine(ISD::SELECT_CC);
   setTargetDAGCombine(ISD::INSERT_VECTOR_ELT);
 
+  // These should be replaced by UDVIREM, but it does not happen automatically
+  // during Type Legalization
+  setOperationAction(ISD::UDIV, MVT::i64, Custom);
+  setOperationAction(ISD::UREM, MVT::i64, Custom);
+
   setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
 
   setBooleanContents(ZeroOrNegativeOneBooleanContent);
@@ -1277,7 +1280,7 @@ SDValue R600TargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const
         NumElements = VT.getVectorNumElements();
       }
       Result = DAG.getNode(ISD::BUILD_VECTOR, DL, NewVT,
-                           ArrayRef<SDValue>(Slots, NumElements));
+                           makeArrayRef(Slots, NumElements));
     } else {
       // non-constant ptr can't be folded, keeps it as a v4f32 load
       Result = DAG.getNode(AMDGPUISD::CONST_ADDRESS, DL, MVT::v4i32,
diff --git a/lib/Target/R600/R600ISelLowering.h b/lib/Target/R600/R600ISelLowering.h
index 22ef72873e..a8a464f338 100644
--- a/lib/Target/R600/R600ISelLowering.h
+++ b/lib/Target/R600/R600ISelLowering.h
@@ -24,21 +24,21 @@ class R600InstrInfo;
 class R600TargetLowering : public AMDGPUTargetLowering {
 public:
   R600TargetLowering(TargetMachine &TM);
-  virtual MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr *MI,
-      MachineBasicBlock * BB) const;
-  virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
-  virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
-  virtual void ReplaceNodeResults(SDNode * N,
-                                  SmallVectorImpl<SDValue> &Results,
-                                  SelectionDAG &DAG) const override;
-  virtual SDValue LowerFormalArguments(
-                                      SDValue Chain,
-                                      CallingConv::ID CallConv,
-                                      bool isVarArg,
-                                      const SmallVectorImpl<ISD::InputArg> &Ins,
-                                      SDLoc DL, SelectionDAG &DAG,
-                                      SmallVectorImpl<SDValue> &InVals) const;
-  virtual EVT getSetCCResultType(LLVMContext &, EVT VT) const;
+  MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr *MI,
+      MachineBasicBlock * BB) const override;
+  SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
+  SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
+  void ReplaceNodeResults(SDNode * N,
+                          SmallVectorImpl<SDValue> &Results,
+                          SelectionDAG &DAG) const override;
+  SDValue LowerFormalArguments(
+                              SDValue Chain,
+                              CallingConv::ID CallConv,
+                              bool isVarArg,
+                              const SmallVectorImpl<ISD::InputArg> &Ins,
+                              SDLoc DL, SelectionDAG &DAG,
+                              SmallVectorImpl<SDValue> &InVals) const override;
+  EVT getSetCCResultType(LLVMContext &, EVT VT) const override;
 private:
   unsigned Gen;
   /// Each OpenCL kernel has nine implicit parameters that are stored in the
@@ -66,7 +66,7 @@ private:
   void getStackAddress(unsigned StackWidth, unsigned ElemIdx,
                        unsigned &Channel, unsigned &PtrIncr) const;
   bool isZero(SDValue Op) const;
-  virtual SDNode *PostISelFolding(MachineSDNode *N, SelectionDAG &DAG) const;
+  SDNode *PostISelFolding(MachineSDNode *N, SelectionDAG &DAG) const override;
 };
 
 } // End namespace llvm;
diff --git a/lib/Target/R600/R600InstrInfo.h b/lib/Target/R600/R600InstrInfo.h
index baee6e002b..b5304a0edf 100644
--- a/lib/Target/R600/R600InstrInfo.h
+++ b/lib/Target/R600/R600InstrInfo.h
@@ -50,13 +50,13 @@ namespace llvm {
 
   explicit R600InstrInfo(AMDGPUTargetMachine &tm);
 
-  const R600RegisterInfo &getRegisterInfo() const;
-  virtual void copyPhysReg(MachineBasicBlock &MBB,
-                           MachineBasicBlock::iterator MI, DebugLoc DL,
-                           unsigned DestReg, unsigned SrcReg,
-                           bool KillSrc) const;
+  const R600RegisterInfo &getRegisterInfo() const override;
+  void copyPhysReg(MachineBasicBlock &MBB,
+                   MachineBasicBlock::iterator MI, DebugLoc DL,
+                   unsigned DestReg, unsigned SrcReg,
+                   bool KillSrc) const override;
   bool isLegalToSplitMBBAt(MachineBasicBlock &MBB,
-                           MachineBasicBlock::iterator MBBI) const;
+                           MachineBasicBlock::iterator MBBI) const override;
 
   bool isTrig(const MachineInstr &MI) const;
   bool isPlaceHolderOpcode(unsigned opcode) const;
@@ -142,79 +142,79 @@ namespace llvm {
   /// instruction slots within an instruction group.
   bool isVector(const MachineInstr &MI) const;
 
-  virtual unsigned getIEQOpcode() const;
-  virtual bool isMov(unsigned Opcode) const;
+  unsigned getIEQOpcode() const override;
+  bool isMov(unsigned Opcode) const override;
 
   DFAPacketizer *CreateTargetScheduleState(const TargetMachine *TM,
-                                           const ScheduleDAG *DAG) const;
+                                           const ScheduleDAG *DAG) const override;
 
-  bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
+  bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
 
   bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB,
-                     SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const;
+                     SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const override;
 
-  unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const;
+  unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const override;
 
-  unsigned RemoveBranch(MachineBasicBlock &MBB) const;
+  unsigned RemoveBranch(MachineBasicBlock &MBB) const override;
 
-  bool isPredicated(const MachineInstr *MI) const;
+  bool isPredicated(const MachineInstr *MI) const override;
 
-  bool isPredicable(MachineInstr *MI) const;
+  bool isPredicable(MachineInstr *MI) const override;
 
   bool
    isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCyles,
-                             const BranchProbability &Probability) const;
+                             const BranchProbability &Probability) const override;
 
   bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCyles,
                            unsigned ExtraPredCycles,
-                           const BranchProbability &Probability) const ;
+                           const BranchProbability &Probability) const override ;
 
   bool
    isProfitableToIfCvt(MachineBasicBlock &TMBB,
                        unsigned NumTCycles, unsigned ExtraTCycles,
                        MachineBasicBlock &FMBB,
                        unsigned NumFCycles, unsigned ExtraFCycles,
-                       const BranchProbability &Probability) const;
+                       const BranchProbability &Probability) const override;
 
   bool DefinesPredicate(MachineInstr *MI,
-                                  std::vector<MachineOperand> &Pred) const;
+                                  std::vector<MachineOperand> &Pred) const override;
 
   bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
-                         const SmallVectorImpl<MachineOperand> &Pred2) const;
+                         const SmallVectorImpl<MachineOperand> &Pred2) const override;
 
   bool isProfitableToUnpredicate(MachineBasicBlock &TMBB,
-                                          MachineBasicBlock &FMBB) const;
+                                          MachineBasicBlock &FMBB) const override;
 
   bool PredicateInstruction(MachineInstr *MI,
-                        const SmallVectorImpl<MachineOperand> &Pred) const;
+                        const SmallVectorImpl<MachineOperand> &Pred) const override;
 
-  unsigned int getPredicationCost(const MachineInstr *) const;
+  unsigned int getPredicationCost(const MachineInstr *) const override;
 
   unsigned int getInstrLatency(const InstrItineraryData *ItinData,
                                const MachineInstr *MI,
-                               unsigned *PredCost = nullptr) const;
+                               unsigned *PredCost = nullptr) const override;
 
-  virtual int getInstrLatency(const InstrItineraryData *ItinData,
-                              SDNode *Node) const { return 1;}
+  int getInstrLatency(const InstrItineraryData *ItinData,
+                      SDNode *Node) const override { return 1;}
 
   /// \brief Reserve the registers that may be accesed using indirect addressing.
   void reserveIndirectRegisters(BitVector &Reserved,
                                 const MachineFunction &MF) const;
 
-  virtual unsigned calculateIndirectAddress(unsigned RegIndex,
-                                            unsigned Channel) const;
+  unsigned calculateIndirectAddress(unsigned RegIndex,
+                                    unsigned Channel) const override;
 
-  virtual const TargetRegisterClass *getIndirectAddrRegClass() const;
+  const TargetRegisterClass *getIndirectAddrRegClass() const override;
 
-  virtual MachineInstrBuilder buildIndirectWrite(MachineBasicBlock *MBB,
-                                  MachineBasicBlock::iterator I,
-                                  unsigned ValueReg, unsigned Address,
-                                  unsigned OffsetReg) const;
+  MachineInstrBuilder buildIndirectWrite(MachineBasicBlock *MBB,
+                          MachineBasicBlock::iterator I,
+                          unsigned ValueReg, unsigned Address,
+                          unsigned OffsetReg) const override;
 
-  virtual MachineInstrBuilder buildIndirectRead(MachineBasicBlock *MBB,
-                                  MachineBasicBlock::iterator I,
-                                  unsigned ValueReg, unsigned Address,
-                                  unsigned OffsetReg) const;
+  MachineInstrBuilder buildIndirectRead(MachineBasicBlock *MBB,
+                                        MachineBasicBlock::iterator I,
+                                        unsigned ValueReg, unsigned Address,
+                                        unsigned OffsetReg) const override;
 
   unsigned getMaxAlusPerClause() const;
 
@@ -244,7 +244,7 @@ namespace llvm {
 
   MachineInstr *buildMovInstr(MachineBasicBlock *MBB,
                               MachineBasicBlock::iterator I,
-                              unsigned DstReg, unsigned SrcReg) const;
+                              unsigned DstReg, unsigned SrcReg) const override;
 
   /// \brief Get the index of Op in the MachineInstr.
   ///
diff --git a/lib/Target/R600/R600MachineFunctionInfo.h b/lib/Target/R600/R600MachineFunctionInfo.h
index c1bec0aae7..b0ae22e806 100644
--- a/lib/Target/R600/R600MachineFunctionInfo.h
+++ b/lib/Target/R600/R600MachineFunctionInfo.h
@@ -21,7 +21,7 @@
 namespace llvm {
 
 class R600MachineFunctionInfo : public AMDGPUMachineFunction {
-  virtual void anchor();
+  void anchor() override;
 public:
   R600MachineFunctionInfo(const MachineFunction &MF);
   SmallVector<unsigned, 4> LiveOuts;
diff --git a/lib/Target/R600/R600MachineScheduler.h b/lib/Target/R600/R600MachineScheduler.h
index 390abbb4dc..fd475af2bf 100644
--- a/lib/Target/R600/R600MachineScheduler.h
+++ b/lib/Target/R600/R600MachineScheduler.h
@@ -71,14 +71,13 @@ public:
     DAG(nullptr), TII(nullptr), TRI(nullptr), MRI(nullptr) {
   }
 
-  virtual ~R600SchedStrategy() {
-  }
+  virtual ~R600SchedStrategy() {}
 
-  virtual void initialize(ScheduleDAGMI *dag);
-  virtual SUnit *pickNode(bool &IsTopNode);
-  virtual void schedNode(SUnit *SU, bool IsTopNode);
-  virtual void releaseTopNode(SUnit *SU);
-  virtual void releaseBottomNode(SUnit *SU);
+  void initialize(ScheduleDAGMI *dag) override;
+  SUnit *pickNode(bool &IsTopNode) override;
+  void schedNode(SUnit *SU, bool IsTopNode) override;
+  void releaseTopNode(SUnit *SU) override;
+  void releaseBottomNode(SUnit *SU) override;
 
 private:
   std::vector<MachineInstr *> InstructionsGroupCandidate;
diff --git a/lib/Target/R600/R600OptimizeVectorRegisters.cpp b/lib/Target/R600/R600OptimizeVectorRegisters.cpp
index 86c7561392..2314136f22 100644
--- a/lib/Target/R600/R600OptimizeVectorRegisters.cpp
+++ b/lib/Target/R600/R600OptimizeVectorRegisters.cpp
@@ -110,7 +110,7 @@ public:
   R600VectorRegMerger(TargetMachine &tm) : MachineFunctionPass(ID),
   TII(nullptr) { }
 
-  void getAnalysisUsage(AnalysisUsage &AU) const {
+  void getAnalysisUsage(AnalysisUsage &AU) const override {
     AU.setPreservesCFG();
     AU.addRequired<MachineDominatorTree>();
     AU.addPreserved<MachineDominatorTree>();
@@ -119,11 +119,11 @@ public:
     MachineFunctionPass::getAnalysisUsage(AU);
   }
 
-  const char *getPassName() const {
+  const char *getPassName() const override {
     return "R600 Vector Registers Merge Pass";
   }
 
-  bool runOnMachineFunction(MachineFunction &Fn);
+  bool runOnMachineFunction(MachineFunction &Fn) override;
 };
 
 char R600VectorRegMerger::ID = 0;
diff --git a/lib/Target/R600/R600Packetizer.cpp b/lib/Target/R600/R600Packetizer.cpp
index 8793e9fb55..c2f6c03320 100644
--- a/lib/Target/R600/R600Packetizer.cpp
+++ b/lib/Target/R600/R600Packetizer.cpp
@@ -37,7 +37,7 @@ public:
   static char ID;
   R600Packetizer(const TargetMachine &TM) : MachineFunctionPass(ID) {}
 
-  void getAnalysisUsage(AnalysisUsage &AU) const {
+  void getAnalysisUsage(AnalysisUsage &AU) const override {
     AU.setPreservesCFG();
     AU.addRequired<MachineDominatorTree>();
     AU.addPreserved<MachineDominatorTree>();
@@ -46,11 +46,11 @@ public:
     MachineFunctionPass::getAnalysisUsage(AU);
   }
 
-  const char *getPassName() const {
+  const char *getPassName() const override {
     return "R600 Packetizer";
   }
 
-  bool runOnMachineFunction(MachineFunction &Fn);
+  bool runOnMachineFunction(MachineFunction &Fn) override;
 };
 char R600Packetizer::ID = 0;
 
@@ -156,18 +156,19 @@ public:
   }
 
   // initPacketizerState - initialize some internal flags.
-  void initPacketizerState() {
+  void initPacketizerState() override {
     ConsideredInstUsesAlreadyWrittenVectorElement = false;
   }
 
   // ignorePseudoInstruction - Ignore bundling of pseudo instructions.
-  bool ignorePseudoInstruction(MachineInstr *MI, MachineBasicBlock *MBB) {
+  bool ignorePseudoInstruction(MachineInstr *MI,
+                               MachineBasicBlock *MBB) override {
     return false;
   }
 
   // isSoloInstruction - return true if instruction MI can not be packetized
   // with any other instruction, which means that MI itself is a packet.
-  bool isSoloInstruction(MachineInstr *MI) {
+  bool isSoloInstruction(MachineInstr *MI) override {
     if (TII->isVector(*MI))
       return true;
     if (!TII->isALUInstr(MI->getOpcode()))
@@ -183,7 +184,7 @@ public:
 
   // isLegalToPacketizeTogether - Is it legal to packetize SUI and SUJ
   // together.
-  bool isLegalToPacketizeTogether(SUnit *SUI, SUnit *SUJ) {
+  bool isLegalToPacketizeTogether(SUnit *SUI, SUnit *SUJ) override {
     MachineInstr *MII = SUI->getInstr(), *MIJ = SUJ->getInstr();
     if (getSlot(MII) == getSlot(MIJ))
       ConsideredInstUsesAlreadyWrittenVectorElement = true;
@@ -220,7 +221,9 @@ public:
 
   // isLegalToPruneDependencies - Is it legal to prune dependece between SUI
   // and SUJ.
-  bool isLegalToPruneDependencies(SUnit *SUI, SUnit *SUJ) {return false;}
+  bool isLegalToPruneDependencies(SUnit *SUI, SUnit *SUJ) override {
+    return false;
+  }
 
   void setIsLastBit(MachineInstr *MI, unsigned Bit) const {
     unsigned LastOp = TII->getOperandIdx(MI->getOpcode(), AMDGPU::OpName::last);
@@ -289,7 +292,7 @@ public:
     return true;
   }
 
-  MachineBasicBlock::iterator addToPacket(MachineInstr *MI) {
+  MachineBasicBlock::iterator addToPacket(MachineInstr *MI) override {
     MachineBasicBlock::iterator FirstInBundle =
         CurrentPacketMIs.empty() ? MI : CurrentPacketMIs.front();
     const DenseMap<unsigned, unsigned> &PV =
diff --git a/lib/Target/R600/R600RegisterInfo.h b/lib/Target/R600/R600RegisterInfo.h
index c74c49ecdc..52e1a4bed9 100644
--- a/lib/Target/R600/R600RegisterInfo.h
+++ b/lib/Target/R600/R600RegisterInfo.h
@@ -28,27 +28,28 @@ struct R600RegisterInfo : public AMDGPURegisterInfo {
 
   R600RegisterInfo(AMDGPUTargetMachine &tm);
 
-  virtual BitVector getReservedRegs(const MachineFunction &MF) const;
+  BitVector getReservedRegs(const MachineFunction &MF) const override;
 
   /// \param RC is an AMDIL reg class.
   ///
   /// \returns the R600 reg class that is equivalent to \p RC.
-  virtual const TargetRegisterClass *getISARegClass(
-    const TargetRegisterClass *RC) const;
+  const TargetRegisterClass *getISARegClass(
+    const TargetRegisterClass *RC) const override;
 
   /// \brief get the HW encoding for a register's channel.
   unsigned getHWRegChan(unsigned reg) const;
 
-  virtual unsigned getHWRegIndex(unsigned Reg) const;
+  unsigned getHWRegIndex(unsigned Reg) const override;
 
   /// \brief get the register class of the specified type to use in the
   /// CFGStructurizer
-  virtual const TargetRegisterClass * getCFGStructurizerRegClass(MVT VT) const;
+  const TargetRegisterClass * getCFGStructurizerRegClass(MVT VT) const override;
 
-  virtual const RegClassWeight &getRegClassWeight(const TargetRegisterClass *RC) const;
+  const RegClassWeight &
+    getRegClassWeight(const TargetRegisterClass *RC) const override;
 
   // \returns true if \p Reg can be defined in one ALU caluse and used in another.
-  virtual bool isPhysRegLiveAcrossClauses(unsigned Reg) const;
+  bool isPhysRegLiveAcrossClauses(unsigned Reg) const;
 };
 
 } // End namespace llvm
diff --git a/lib/Target/R600/R600TextureIntrinsicsReplacer.cpp b/lib/Target/R600/R600TextureIntrinsicsReplacer.cpp
index 9d2440474c..419ec8b3d7 100644
--- a/lib/Target/R600/R600TextureIntrinsicsReplacer.cpp
+++ b/lib/Target/R600/R600TextureIntrinsicsReplacer.cpp
@@ -209,7 +209,7 @@ public:
     FunctionPass(ID) {
   }
 
-  virtual bool doInitialization(Module &M) {
+  bool doInitialization(Module &M) override {
     LLVMContext &Ctx = M.getContext();
     Mod = &M;
     FloatType = Type::getFloatTy(Ctx);
@@ -245,16 +245,16 @@ public:
     return false;
   }
 
-  virtual bool runOnFunction(Function &F) {
+  bool runOnFunction(Function &F) override {
     visit(F);
     return false;
   }
 
-  virtual const char *getPassName() const {
+  const char *getPassName() const override {
     return "R600 Texture Intrinsics Replacer";
   }
 
-  void getAnalysisUsage(AnalysisUsage &AU) const {
+  void getAnalysisUsage(AnalysisUsage &AU) const override {
   }
 
   void visitCallInst(CallInst &I) {
diff --git a/lib/Target/R600/SIAnnotateControlFlow.cpp b/lib/Target/R600/SIAnnotateControlFlow.cpp
index 1186a62956..d6e445136f 100644
--- a/lib/Target/R600/SIAnnotateControlFlow.cpp
+++ b/lib/Target/R600/SIAnnotateControlFlow.cpp
@@ -91,15 +91,15 @@ public:
   SIAnnotateControlFlow():
     FunctionPass(ID) { }
 
-  virtual bool doInitialization(Module &M);
+  bool doInitialization(Module &M) override;
 
-  virtual bool runOnFunction(Function &F);
+  bool runOnFunction(Function &F) override;
 
-  virtual const char *getPassName() const {
+  const char *getPassName() const override {
     return "SI annotate control flow";
   }
 
-  virtual void getAnalysisUsage(AnalysisUsage &AU) const {
+  void getAnalysisUsage(AnalysisUsage &AU) const override {
     AU.addRequired<DominatorTreeWrapperPass>();
     AU.addPreserved<DominatorTreeWrapperPass>();
     FunctionPass::getAnalysisUsage(AU);
diff --git a/lib/Target/R600/SIFixSGPRCopies.cpp b/lib/Target/R600/SIFixSGPRCopies.cpp
index d524f443ee..f6b8b783d0 100644
--- a/lib/Target/R600/SIFixSGPRCopies.cpp
+++ b/lib/Target/R600/SIFixSGPRCopies.cpp
@@ -98,9 +98,9 @@ private:
 public:
   SIFixSGPRCopies(TargetMachine &tm) : MachineFunctionPass(ID) { }
 
-  virtual bool runOnMachineFunction(MachineFunction &MF);
+  bool runOnMachineFunction(MachineFunction &MF) override;
 
-  const char *getPassName() const {
+  const char *getPassName() const override {
     return "SI Fix SGPR copies";
   }
 
@@ -185,7 +185,8 @@ bool SIFixSGPRCopies::isVGPRToSGPRCopy(const MachineInstr &Copy,
   const TargetRegisterClass *SrcRC;
 
   if (!TargetRegisterInfo::isVirtualRegister(SrcReg) ||
-      DstRC == &AMDGPU::M0RegRegClass)
+      DstRC == &AMDGPU::M0RegRegClass ||
+      MRI.getRegClass(SrcReg) == &AMDGPU::VReg_1RegClass)
     return false;
 
   SrcRC = TRI->getSubRegClass(MRI.getRegClass(SrcReg), SrcSubReg);
diff --git a/lib/Target/R600/SIISelLowering.cpp b/lib/Target/R600/SIISelLowering.cpp
index 2990d6850d..e688048507 100644
--- a/lib/Target/R600/SIISelLowering.cpp
+++ b/lib/Target/R600/SIISelLowering.cpp
@@ -29,7 +29,7 @@ using namespace llvm;
 
 SITargetLowering::SITargetLowering(TargetMachine &TM) :
     AMDGPUTargetLowering(TM) {
-  addRegisterClass(MVT::i1, &AMDGPU::SReg_64RegClass);
+  addRegisterClass(MVT::i1, &AMDGPU::VReg_1RegClass);
   addRegisterClass(MVT::i64, &AMDGPU::VSrc_64RegClass);
 
   addRegisterClass(MVT::v32i8, &AMDGPU::SReg_256RegClass);
@@ -169,6 +169,10 @@ SITargetLowering::SITargetLowering(TargetMachine &TM) :
   setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
   setOperationAction(ISD::FrameIndex, MVT::i32, Custom);
 
+  // These should use UDIVREM, so set them to expand
+  setOperationAction(ISD::UDIV, MVT::i64, Expand);
+  setOperationAction(ISD::UREM, MVT::i64, Expand);
+
   // We only support LOAD/STORE and vector manipulation ops for vectors
   // with > 4 elements.
   MVT VecTypes[] = {
@@ -440,19 +444,48 @@ SDValue SITargetLowering::LowerFormalArguments(
   return Chain;
 }
 
+/// Usually ISel will insert a copy between terminator insturction that output
+/// a value and the S_BRANCH* at the end of the block.  This causes
+/// MachineBasicBlock::getFirstTerminator() to return the incorrect value,
+/// so we want to make sure there are no copies between terminators at the
+/// end of blocks.
+static void LowerTerminatorWithOutput(unsigned Opcode, MachineBasicBlock *BB,
+                                      MachineInstr *MI,
+                                      const TargetInstrInfo *TII,
+                                      MachineRegisterInfo &MRI) {
+  unsigned DstReg = MI->getOperand(0).getReg();
+  // Usually ISel will insert a copy between the SI_IF_NON_TERM instruction
+  // and the S_BRANCH* terminator.  We want to replace SI_IF_NO_TERM with
+  // SI_IF and we can't have any instructions between S_BRANCH* and SI_IF,
+  // since they are both terminators
+  assert(MRI.hasOneUse(DstReg));
+  MachineOperand &Use = *MRI.use_begin(DstReg);
+  MachineInstr *UseMI = Use.getParent();
+  assert(UseMI->getOpcode() == AMDGPU::COPY);
+
+  MRI.replaceRegWith(UseMI->getOperand(0).getReg(), DstReg);
+  UseMI->eraseFromParent();
+  BuildMI(*BB, BB->getFirstTerminator(), MI->getDebugLoc(),
+          TII->get(Opcode))
+          .addOperand(MI->getOperand(0))
+          .addOperand(MI->getOperand(1))
+          .addOperand(MI->getOperand(2));
+  MI->eraseFromParent();
+}
+
 MachineBasicBlock * SITargetLowering::EmitInstrWithCustomInserter(
     MachineInstr * MI, MachineBasicBlock * BB) const {
 
   MachineBasicBlock::iterator I = *MI;
+  const SIInstrInfo *TII =
+    static_cast<const SIInstrInfo*>(getTargetMachine().getInstrInfo());
+  MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
 
   switch (MI->getOpcode()) {
   default:
     return AMDGPUTargetLowering::EmitInstrWithCustomInserter(MI, BB);
   case AMDGPU::BRANCH: return BB;
   case AMDGPU::SI_ADDR64_RSRC: {
-    const SIInstrInfo *TII =
-      static_cast<const SIInstrInfo*>(getTargetMachine().getInstrInfo());
-    MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
     unsigned SuperReg = MI->getOperand(0).getReg();
     unsigned SubRegLo = MRI.createVirtualRegister(&AMDGPU::SGPR_64RegClass);
     unsigned SubRegHi = MRI.createVirtualRegister(&AMDGPU::SGPR_64RegClass);
@@ -477,9 +510,13 @@ MachineBasicBlock * SITargetLowering::EmitInstrWithCustomInserter(
     MI->eraseFromParent();
     break;
   }
-  case AMDGPU::V_SUB_F64: {
-    const SIInstrInfo *TII =
-      static_cast<const SIInstrInfo*>(getTargetMachine().getInstrInfo());
+  case AMDGPU::SI_IF_NON_TERM:
+    LowerTerminatorWithOutput(AMDGPU::SI_IF, BB, MI, TII, MRI);
+    break;
+  case AMDGPU::SI_ELSE_NON_TERM:
+    LowerTerminatorWithOutput(AMDGPU::SI_ELSE, BB, MI, TII, MRI);
+    break;
+  case AMDGPU::V_SUB_F64:
     BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::V_ADD_F64),
             MI->getOperand(0).getReg())
             .addReg(MI->getOperand(1).getReg())
@@ -491,11 +528,9 @@ MachineBasicBlock * SITargetLowering::EmitInstrWithCustomInserter(
             .addImm(2); /* NEG */
     MI->eraseFromParent();
     break;
-  }
+
   case AMDGPU::SI_RegisterStorePseudo: {
     MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
-    const SIInstrInfo *TII =
-      static_cast<const SIInstrInfo*>(getTargetMachine().getInstrInfo());
     unsigned Reg = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
     MachineInstrBuilder MIB =
         BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::SI_RegisterStore),
diff --git a/lib/Target/R600/SIISelLowering.h b/lib/Target/R600/SIISelLowering.h
index ff90831067..c6eaa812e4 100644
--- a/lib/Target/R600/SIISelLowering.h
+++ b/lib/Target/R600/SIISelLowering.h
@@ -48,32 +48,33 @@ class SITargetLowering : public AMDGPUTargetLowering {
 
 public:
   SITargetLowering(TargetMachine &tm);
-  bool allowsUnalignedMemoryAccesses(EVT VT, unsigned AS, bool *IsFast) const;
-  virtual bool shouldSplitVectorType(EVT VT) const override;
+  bool allowsUnalignedMemoryAccesses(EVT VT, unsigned AS,
+                                     bool *IsFast) const override;
+  bool shouldSplitVectorType(EVT VT) const override;
 
-  virtual bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
-                                                 Type *Ty) const override;
+  bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
+                                        Type *Ty) const override;
 
   SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
                                bool isVarArg,
                                const SmallVectorImpl<ISD::InputArg> &Ins,
                                SDLoc DL, SelectionDAG &DAG,
-                               SmallVectorImpl<SDValue> &InVals) const;
+                               SmallVectorImpl<SDValue> &InVals) const override;
 
-  virtual MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr * MI,
-                                              MachineBasicBlock * BB) const;
-  virtual EVT getSetCCResultType(LLVMContext &Context, EVT VT) const;
-  virtual MVT getScalarShiftAmountTy(EVT VT) const;
-  virtual bool isFMAFasterThanFMulAndFAdd(EVT VT) const;
-  virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
-  virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
-  virtual SDNode *PostISelFolding(MachineSDNode *N, SelectionDAG &DAG) const;
-  virtual void AdjustInstrPostInstrSelection(MachineInstr *MI,
-                                             SDNode *Node) const;
+  MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr * MI,
+                                      MachineBasicBlock * BB) const override;
+  EVT getSetCCResultType(LLVMContext &Context, EVT VT) const override;
+  MVT getScalarShiftAmountTy(EVT VT) const override;
+  bool isFMAFasterThanFMulAndFAdd(EVT VT) const override;
+  SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
+  SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
+  SDNode *PostISelFolding(MachineSDNode *N, SelectionDAG &DAG) const override;
+  void AdjustInstrPostInstrSelection(MachineInstr *MI,
+                                     SDNode *Node) const override;
 
   int32_t analyzeImmediate(const SDNode *N) const;
   SDValue CreateLiveInRegister(SelectionDAG &DAG, const TargetRegisterClass *RC,
-                               unsigned Reg, EVT VT) const;
+                               unsigned Reg, EVT VT) const override;
 };
 
 } // End namespace llvm
diff --git a/lib/Target/R600/SIInsertWaits.cpp b/lib/Target/R600/SIInsertWaits.cpp
index f48a55431a..a17fed7e7e 100644
--- a/lib/Target/R600/SIInsertWaits.cpp
+++ b/lib/Target/R600/SIInsertWaits.cpp
@@ -101,9 +101,9 @@ public:
     TRI(nullptr),
     ExpInstrTypesSeen(0) { }
 
-  virtual bool runOnMachineFunction(MachineFunction &MF);
+  bool runOnMachineFunction(MachineFunction &MF) override;
 
-  const char *getPassName() const {
+  const char *getPassName() const override {
     return "SI insert wait  instructions";
   }
 
diff --git a/lib/Target/R600/SIInstrInfo.cpp b/lib/Target/R600/SIInstrInfo.cpp
index 4c57d16c7f..5d08b91ea7 100644
--- a/lib/Target/R600/SIInstrInfo.cpp
+++ b/lib/Target/R600/SIInstrInfo.cpp
@@ -548,6 +548,9 @@ unsigned SIInstrInfo::getVALUOp(const MachineInstr &MI) {
   case AMDGPU::S_CMP_GE_I32: return AMDGPU::V_CMP_GE_I32_e32;
   case AMDGPU::S_CMP_LT_I32: return AMDGPU::V_CMP_LT_I32_e32;
   case AMDGPU::S_CMP_LE_I32: return AMDGPU::V_CMP_LE_I32_e32;
+  case AMDGPU::S_LOAD_DWORD_SGPR: return AMDGPU::BUFFER_LOAD_DWORD_ADDR64;
+  case AMDGPU::S_LOAD_DWORDX2_SGPR: return AMDGPU::BUFFER_LOAD_DWORDX2_ADDR64;
+  case AMDGPU::S_LOAD_DWORDX4_SGPR: return AMDGPU::BUFFER_LOAD_DWORDX4_ADDR64;
   }
 }
 
@@ -910,6 +913,44 @@ void SIInstrInfo::legalizeOperands(MachineInstr *MI) const {
   }
 }
 
+void SIInstrInfo::moveSMRDToVALU(MachineInstr *MI, MachineRegisterInfo &MRI) const {
+  MachineBasicBlock *MBB = MI->getParent();
+  switch (MI->getOpcode()) {
+    case AMDGPU::S_LOAD_DWORD_SGPR:
+    case AMDGPU::S_LOAD_DWORDX2_SGPR:
+    case AMDGPU::S_LOAD_DWORDX4_SGPR:
+      unsigned NewOpcode = getVALUOp(*MI);
+      unsigned Offset = MI->getOperand(2).getReg();
+
+
+      unsigned SRsrc = MRI.createVirtualRegister(&AMDGPU::SReg_128RegClass);
+      unsigned DWord0 = Offset;
+      unsigned DWord1 = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
+      unsigned DWord2 = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
+      unsigned DWord3 = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
+
+      BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32), DWord1)
+              .addImm(0);
+      BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32), DWord2)
+              .addImm(AMDGPU::RSRC_DATA_FORMAT & 0xFFFFFFFF);
+      BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32), DWord3)
+              .addImm(AMDGPU::RSRC_DATA_FORMAT >> 32);
+      BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::REG_SEQUENCE), SRsrc)
+              .addReg(DWord0)
+              .addImm(AMDGPU::sub0)
+              .addReg(DWord1)
+              .addImm(AMDGPU::sub1)
+              .addReg(DWord2)
+              .addImm(AMDGPU::sub2)
+              .addReg(DWord3)
+              .addImm(AMDGPU::sub3);
+     MI->setDesc(get(NewOpcode));
+     MI->getOperand(2).setReg(MI->getOperand(1).getReg());
+     MI->getOperand(1).setReg(SRsrc);
+     MI->addOperand(*MBB->getParent(), MachineOperand::CreateImm(0));
+  }
+}
+
 void SIInstrInfo::moveToVALU(MachineInstr &TopInst) const {
   SmallVector<MachineInstr *, 128> Worklist;
   Worklist.push_back(&TopInst);
@@ -920,9 +961,15 @@ void SIInstrInfo::moveToVALU(MachineInstr &TopInst) const {
     MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
 
     unsigned Opcode = Inst->getOpcode();
+    unsigned NewOpcode = getVALUOp(*Inst);
 
     // Handle some special cases
     switch (Opcode) {
+    default:
+      if (isSMRD(Inst->getOpcode())) {
+        moveSMRDToVALU(Inst, MRI);
+      }
+      break;
     case AMDGPU::S_MOV_B64: {
       DebugLoc DL = Inst->getDebugLoc();
 
@@ -973,7 +1020,6 @@ void SIInstrInfo::moveToVALU(MachineInstr &TopInst) const {
       llvm_unreachable("Moving this op to VALU not implemented");
     }
 
-    unsigned NewOpcode = getVALUOp(*Inst);
     if (NewOpcode == AMDGPU::INSTRUCTION_LIST_END) {
       // We cannot move this instruction to the VALU, so we should try to
       // legalize its operands instead.
diff --git a/lib/Target/R600/SIInstrInfo.h b/lib/Target/R600/SIInstrInfo.h
index 415f31bfd6..63f1d7fdee 100644
--- a/lib/Target/R600/SIInstrInfo.h
+++ b/lib/Target/R600/SIInstrInfo.h
@@ -52,45 +52,45 @@ private:
 public:
   explicit SIInstrInfo(AMDGPUTargetMachine &tm);
 
-  const SIRegisterInfo &getRegisterInfo() const {
+  const SIRegisterInfo &getRegisterInfo() const override {
     return RI;
   }
 
-  virtual void copyPhysReg(MachineBasicBlock &MBB,
-                           MachineBasicBlock::iterator MI, DebugLoc DL,
-                           unsigned DestReg, unsigned SrcReg,
-                           bool KillSrc) const;
+  void copyPhysReg(MachineBasicBlock &MBB,
+                   MachineBasicBlock::iterator MI, DebugLoc DL,
+                   unsigned DestReg, unsigned SrcReg,
+                   bool KillSrc) const override;
 
   void storeRegToStackSlot(MachineBasicBlock &MBB,
                            MachineBasicBlock::iterator MI,
                            unsigned SrcReg, bool isKill, int FrameIndex,
                            const TargetRegisterClass *RC,
-                           const TargetRegisterInfo *TRI) const;
+                           const TargetRegisterInfo *TRI) const override;
 
   void loadRegFromStackSlot(MachineBasicBlock &MBB,
                             MachineBasicBlock::iterator MI,
                             unsigned DestReg, int FrameIndex,
                             const TargetRegisterClass *RC,
-                            const TargetRegisterInfo *TRI) const;
+                            const TargetRegisterInfo *TRI) const override;
 
   unsigned commuteOpcode(unsigned Opcode) const;
 
-  virtual MachineInstr *commuteInstruction(MachineInstr *MI,
-                                           bool NewMI=false) const;
+  MachineInstr *commuteInstruction(MachineInstr *MI,
+                                   bool NewMI=false) const override;
 
   bool isTriviallyReMaterializable(const MachineInstr *MI,
                                    AliasAnalysis *AA = nullptr) const;
 
-  virtual unsigned getIEQOpcode() const {
+  unsigned getIEQOpcode() const override {
     llvm_unreachable("Unimplemented");
   }
 
   MachineInstr *buildMovInstr(MachineBasicBlock *MBB,
                               MachineBasicBlock::iterator I,
-                              unsigned DstReg, unsigned SrcReg) const;
-  virtual bool isMov(unsigned Opcode) const;
+                              unsigned DstReg, unsigned SrcReg) const override;
+  bool isMov(unsigned Opcode) const override;
 
-  virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const;
+  bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const override;
   bool isDS(uint16_t Opcode) const;
   int isMIMG(uint16_t Opcode) const;
   int isSMRD(uint16_t Opcode) const;
@@ -102,8 +102,8 @@ public:
   bool isInlineConstant(const MachineOperand &MO) const;
   bool isLiteralConstant(const MachineOperand &MO) const;
 
-  virtual bool verifyInstruction(const MachineInstr *MI,
-                                 StringRef &ErrInfo) const;
+  bool verifyInstruction(const MachineInstr *MI,
+                         StringRef &ErrInfo) const override;
 
   bool isSALUInstr(const MachineInstr &MI) const;
   static unsigned getVALUOp(const MachineInstr &MI);
@@ -137,27 +137,29 @@ public:
   /// create new instruction and insert them before \p MI.
   void legalizeOperands(MachineInstr *MI) const;
 
+  void moveSMRDToVALU(MachineInstr *MI, MachineRegisterInfo &MRI) const;
+
   /// \brief Replace this instruction's opcode with the equivalent VALU
   /// opcode.  This function will also move the users of \p MI to the
   /// VALU if necessary.
   void moveToVALU(MachineInstr &MI) const;
 
-  virtual unsigned calculateIndirectAddress(unsigned RegIndex,
-                                            unsigned Channel) const;
+  unsigned calculateIndirectAddress(unsigned RegIndex,
+                                    unsigned Channel) const override;
 
-  virtual const TargetRegisterClass *getIndirectAddrRegClass() const;
+  const TargetRegisterClass *getIndirectAddrRegClass() const override;
 
-  virtual MachineInstrBuilder buildIndirectWrite(MachineBasicBlock *MBB,
-                                                 MachineBasicBlock::iterator I,
-                                                 unsigned ValueReg,
-                                                 unsigned Address,
-                                                 unsigned OffsetReg) const;
+  MachineInstrBuilder buildIndirectWrite(MachineBasicBlock *MBB,
+                                         MachineBasicBlock::iterator I,
+                                         unsigned ValueReg,
+                                         unsigned Address,
+                                         unsigned OffsetReg) const override;
 
-  virtual MachineInstrBuilder buildIndirectRead(MachineBasicBlock *MBB,
-                                                MachineBasicBlock::iterator I,
-                                                unsigned ValueReg,
-                                                unsigned Address,
-                                                unsigned OffsetReg) const;
+  MachineInstrBuilder buildIndirectRead(MachineBasicBlock *MBB,
+                                        MachineBasicBlock::iterator I,
+                                        unsigned ValueReg,
+                                        unsigned Address,
+                                        unsigned OffsetReg) const override;
   void reserveIndirectRegisters(BitVector &Reserved,
                                 const MachineFunction &MF) const;
 
diff --git a/lib/Target/R600/SIInstructions.td b/lib/Target/R600/SIInstructions.td
index 80897f2f41..27e7abe1a3 100644
--- a/lib/Target/R600/SIInstructions.td
+++ b/lib/Target/R600/SIInstructions.td
@@ -32,14 +32,16 @@ def isSI : Predicate<"Subtarget.getGeneration() "
 def isCI : Predicate<"Subtarget.getGeneration() "
                       ">= AMDGPUSubtarget::SEA_ISLANDS">;
 
-def WAIT_FLAG : InstFlag<"printWaitFlag">;
+def isCFDepth0 : Predicate<"isCFDepth0()">;
 
-let Predicates = [isSI] in {
+def WAIT_FLAG : InstFlag<"printWaitFlag">;
 
 //===----------------------------------------------------------------------===//
 // SMRD Instructions
 //===----------------------------------------------------------------------===//
 
+let Predicates = [isSI, isCFDepth0] in {
+
 let mayLoad = 1 in {
 
 // We are using the SGPR_32 and not the SReg_32 register class for 32-bit
@@ -76,10 +78,14 @@ defm S_BUFFER_LOAD_DWORDX16 : SMRD_Helper <
 //def S_MEMTIME : SMRD_ <0x0000001e, "S_MEMTIME", []>;
 //def S_DCACHE_INV : SMRD_ <0x0000001f, "S_DCACHE_INV", []>;
 
+} // let Predicates = [isSI, isCFDepth0]
+
 //===----------------------------------------------------------------------===//
 // SOP1 Instructions
 //===----------------------------------------------------------------------===//
 
+let Predicates = [isSI, isCFDepth0] in {
+
 let neverHasSideEffects = 1 in {
 
 let isMoveImm = 1 in {
@@ -152,10 +158,14 @@ def S_MOV_REGRD_B32 : SOP1_32 <0x00000033, "S_MOV_REGRD_B32", []>;
 def S_ABS_I32 : SOP1_32 <0x00000034, "S_ABS_I32", []>;
 def S_MOV_FED_B32 : SOP1_32 <0x00000035, "S_MOV_FED_B32", []>;
 
+} // let Predicates = [isSI, isCFDepth0]
+
 //===----------------------------------------------------------------------===//
 // SOP2 Instructions
 //===----------------------------------------------------------------------===//
 
+let Predicates = [isSI, isCFDepth0] in {
+
 let Defs = [SCC] in { // Carry out goes to SCC
 let isCommutable = 1 in {
 def S_ADD_U32 : SOP2_32 <0x00000000, "S_ADD_U32", []>;
@@ -209,11 +219,6 @@ def S_AND_B64 : SOP2_64 <0x0000000f, "S_AND_B64",
   [(set i64:$dst, (and i64:$src0, i64:$src1))]
 >;
 
-def : Pat <
-  (i1 (and i1:$src0, i1:$src1)),
-  (S_AND_B64 $src0, $src1)
->;
-
 def S_OR_B32 : SOP2_32 <0x00000010, "S_OR_B32",
   [(set i32:$dst, (or i32:$src0, i32:$src1))]
 >;
@@ -222,17 +227,12 @@ def S_OR_B64 : SOP2_64 <0x00000011, "S_OR_B64",
   [(set i64:$dst, (or i64:$src0, i64:$src1))]
 >;
 
-def : Pat <
-  (i1 (or i1:$src0, i1:$src1)),
-  (S_OR_B64 $src0, $src1)
->;
-
 def S_XOR_B32 : SOP2_32 <0x00000012, "S_XOR_B32",
   [(set i32:$dst, (xor i32:$src0, i32:$src1))]
 >;
 
 def S_XOR_B64 : SOP2_64 <0x00000013, "S_XOR_B64",
-  [(set i1:$dst, (xor i1:$src0, i1:$src1))]
+  [(set i64:$dst, (xor i64:$src0, i64:$src1))]
 >;
 def S_ANDN2_B32 : SOP2_32 <0x00000014, "S_ANDN2_B32", []>;
 def S_ANDN2_B64 : SOP2_64 <0x00000015, "S_ANDN2_B64", []>;
@@ -279,10 +279,14 @@ def S_BFE_I64 : SOP2_64 <0x0000002a, "S_BFE_I64", []>;
 //def S_CBRANCH_G_FORK : SOP2_ <0x0000002b, "S_CBRANCH_G_FORK", []>;
 def S_ABSDIFF_I32 : SOP2_32 <0x0000002c, "S_ABSDIFF_I32", []>;
 
+} // let Predicates = [isSI, isCFDepth0]
+
 //===----------------------------------------------------------------------===//
 // SOPC Instructions
 //===----------------------------------------------------------------------===//
 
+let Predicates = [isSI, isCFDepth0] in {
+
 def S_CMP_EQ_I32 : SOPC_32 <0x00000000, "S_CMP_EQ_I32">;
 def S_CMP_LG_I32 : SOPC_32 <0x00000001, "S_CMP_LG_I32">;
 def S_CMP_GT_I32 : SOPC_32 <0x00000002, "S_CMP_GT_I32">;
@@ -301,10 +305,14 @@ def S_CMP_LE_U32 : SOPC_32 <0x0000000b, "S_CMP_LE_U32">;
 ////def S_BITCMP1_B64 : SOPC_BITCMP1 <0x0000000f, "S_BITCMP1_B64", []>;
 //def S_SETVSKIP : SOPC_ <0x00000010, "S_SETVSKIP", []>;
 
+} // let Predicates = [isSI, isCFDepth0]
+
 //===----------------------------------------------------------------------===//
 // SOPK Instructions
 //===----------------------------------------------------------------------===//
 
+let Predicates = [isSI, isCFDepth0] in {
+
 def S_MOVK_I32 : SOPK_32 <0x00000000, "S_MOVK_I32", []>;
 def S_CMOVK_I32 : SOPK_32 <0x00000002, "S_CMOVK_I32", []>;
 
@@ -353,10 +361,14 @@ def S_GETREG_REGRD_B32 : SOPK_32 <0x00000014, "S_GETREG_REGRD_B32", []>;
 //def S_SETREG_IMM32_B32 : SOPK_32 <0x00000015, "S_SETREG_IMM32_B32", []>;
 //def EXP : EXP_ <0x00000000, "EXP", []>;
 
+} // let Predicates = [isSI, isCFDepth0]
+
 //===----------------------------------------------------------------------===//
 // SOPP Instructions
 //===----------------------------------------------------------------------===//
 
+let Predicates = [isSI] in {
+
 //def S_NOP : SOPP_ <0x00000000, "S_NOP", []>;
 
 let isTerminator = 1 in {
@@ -449,6 +461,10 @@ let Uses = [EXEC] in {
 //def S_TTRACEDATA : SOPP_ <0x00000016, "S_TTRACEDATA", []>;
 } // End hasSideEffects
 
+} // let Predicates = [isSI, isCFDepth0]
+
+let Predicates = [isSI] in {
+
 //===----------------------------------------------------------------------===//
 // VOPC Instructions
 //===----------------------------------------------------------------------===//
@@ -1173,27 +1189,43 @@ defm V_MAX_LEGACY_F32 : VOP2_32 <0x0000000e, "V_MAX_LEGACY_F32",
 
 defm V_MIN_F32 : VOP2_32 <0x0000000f, "V_MIN_F32", []>;
 defm V_MAX_F32 : VOP2_32 <0x00000010, "V_MAX_F32", []>;
-defm V_MIN_I32 : VOP2_32 <0x00000011, "V_MIN_I32", []>;
-defm V_MAX_I32 : VOP2_32 <0x00000012, "V_MAX_I32", []>;
-defm V_MIN_U32 : VOP2_32 <0x00000013, "V_MIN_U32", []>;
-defm V_MAX_U32 : VOP2_32 <0x00000014, "V_MAX_U32", []>;
+defm V_MIN_I32 : VOP2_32 <0x00000011, "V_MIN_I32",
+  [(set i32:$dst, (AMDGPUsmin i32:$src0, i32:$src1))]>;
+defm V_MAX_I32 : VOP2_32 <0x00000012, "V_MAX_I32",
+  [(set i32:$dst, (AMDGPUsmax i32:$src0, i32:$src1))]>;
+defm V_MIN_U32 : VOP2_32 <0x00000013, "V_MIN_U32",
+  [(set i32:$dst, (AMDGPUumin i32:$src0, i32:$src1))]>;
+defm V_MAX_U32 : VOP2_32 <0x00000014, "V_MAX_U32",
+  [(set i32:$dst, (AMDGPUumax i32:$src0, i32:$src1))]>;
+
+defm V_LSHR_B32 : VOP2_32 <0x00000015, "V_LSHR_B32",
+  [(set i32:$dst, (srl i32:$src0, i32:$src1))]
+>;
 
-defm V_LSHR_B32 : VOP2_32 <0x00000015, "V_LSHR_B32", []>;
 defm V_LSHRREV_B32 : VOP2_32 <0x00000016, "V_LSHRREV_B32", [], "V_LSHR_B32">;
 
-defm V_ASHR_I32 : VOP2_32 <0x00000017, "V_ASHR_I32", []>;
+defm V_ASHR_I32 : VOP2_32 <0x00000017, "V_ASHR_I32",
+  [(set i32:$dst, (sra i32:$src0, i32:$src1))]
+>;
 defm V_ASHRREV_I32 : VOP2_32 <0x00000018, "V_ASHRREV_I32", [], "V_ASHR_I32">;
 
 let hasPostISelHook = 1 in {
 
-defm V_LSHL_B32 : VOP2_32 <0x00000019, "V_LSHL_B32", []>;
+defm V_LSHL_B32 : VOP2_32 <0x00000019, "V_LSHL_B32",
+  [(set i32:$dst, (shl i32:$src0, i32:$src1))]
+>;
 
 }
 defm V_LSHLREV_B32 : VOP2_32 <0x0000001a, "V_LSHLREV_B32", [], "V_LSHL_B32">;
 
-defm V_AND_B32 : VOP2_32 <0x0000001b, "V_AND_B32", []>;
-defm V_OR_B32 : VOP2_32 <0x0000001c, "V_OR_B32", []>;
-defm V_XOR_B32 : VOP2_32 <0x0000001d, "V_XOR_B32", []>;
+defm V_AND_B32 : VOP2_32 <0x0000001b, "V_AND_B32",
+  [(set i32:$dst, (and i32:$src0, i32:$src1))]>;
+defm V_OR_B32 : VOP2_32 <0x0000001c, "V_OR_B32",
+  [(set i32:$dst, (or i32:$src0, i32:$src1))]
+>;
+defm V_XOR_B32 : VOP2_32 <0x0000001d, "V_XOR_B32",
+  [(set i32:$dst, (xor i32:$src0, i32:$src1))]
+>;
 
 } // End isCommutable = 1
 
@@ -1209,14 +1241,18 @@ defm V_MBCNT_HI_U32_B32 : VOP2_32 <0x00000024, "V_MBCNT_HI_U32_B32", []>;
 let isCommutable = 1, Defs = [VCC] in { // Carry-out goes to VCC
 // No patterns so that the scalar instructions are always selected.
 // The scalar versions will be replaced with vector when needed later.
-defm V_ADD_I32 : VOP2b_32 <0x00000025, "V_ADD_I32", [], VSrc_32>;
-defm V_SUB_I32 : VOP2b_32 <0x00000026, "V_SUB_I32", [], VSrc_32>;
+defm V_ADD_I32 : VOP2b_32 <0x00000025, "V_ADD_I32",
+  [(set i32:$dst, (add i32:$src0, i32:$src1))], VSrc_32>;
+defm V_SUB_I32 : VOP2b_32 <0x00000026, "V_SUB_I32",
+  [(set i32:$dst, (sub i32:$src0, i32:$src1))], VSrc_32>;
 defm V_SUBREV_I32 : VOP2b_32 <0x00000027, "V_SUBREV_I32", [], VSrc_32,
                               "V_SUB_I32">;
 
 let Uses = [VCC] in { // Carry-in comes from VCC
-defm V_ADDC_U32 : VOP2b_32 <0x00000028, "V_ADDC_U32", [], VReg_32>;
-defm V_SUBB_U32 : VOP2b_32 <0x00000029, "V_SUBB_U32", [], VReg_32>;
+defm V_ADDC_U32 : VOP2b_32 <0x00000028, "V_ADDC_U32",
+  [(set i32:$dst, (adde i32:$src0, i32:$src1))], VReg_32>;
+defm V_SUBB_U32 : VOP2b_32 <0x00000029, "V_SUBB_U32",
+  [(set i32:$dst, (sube i32:$src0, i32:$src1))], VReg_32>;
 defm V_SUBBREV_U32 : VOP2b_32 <0x0000002a, "V_SUBBREV_U32", [], VReg_32,
                                "V_SUBB_U32">;
 } // End Uses = [VCC]
@@ -1362,6 +1398,12 @@ def V_TRIG_PREOP_F64 : VOP3_64 <0x00000174, "V_TRIG_PREOP_F64", []>;
 
 let isCodeGenOnly = 1, isPseudo = 1 in {
 
+def V_MOV_I1 : InstSI <
+  (outs VReg_1:$dst),
+  (ins i1imm:$src),
+  "", [(set i1:$dst, (imm:$src))]
+>;
+
 def LOAD_CONST : AMDGPUShaderInst <
   (outs GPRF32:$dst),
   (ins i32imm:$src),
@@ -1375,21 +1417,38 @@ def LOAD_CONST : AMDGPUShaderInst <
 let mayLoad = 1, mayStore = 1, hasSideEffects = 1,
     Uses = [EXEC], Defs = [EXEC] in {
 
+let usesCustomInserter = 1 in {
+
+def SI_IF_NON_TERM : InstSI <
+  (outs SReg_64:$dst),
+  (ins SReg_64:$vcc, brtarget:$target), "",
+  [(set i64:$dst, (int_SI_if i1:$vcc, bb:$target))]
+>;
+
+def SI_ELSE_NON_TERM : InstSI <
+  (outs SReg_64:$dst),
+  (ins SReg_64:$src, brtarget:$target),
+  "",
+  [(set i64:$dst, (int_SI_else i64:$src, bb:$target))]
+> {
+  let Constraints = "$src = $dst";
+}
+
+} // usesCustomInserter = 1
+
 let isBranch = 1, isTerminator = 1 in {
 
-def SI_IF : InstSI <
+def SI_IF: InstSI <
   (outs SReg_64:$dst),
   (ins SReg_64:$vcc, brtarget:$target),
-  "SI_IF $dst, $vcc, $target",
-  [(set i64:$dst, (int_SI_if i1:$vcc, bb:$target))]
+  "", []
 >;
 
 def SI_ELSE : InstSI <
   (outs SReg_64:$dst),
   (ins SReg_64:$src, brtarget:$target),
-  "SI_ELSE $dst, $src, $target",
-  [(set i64:$dst, (int_SI_else i64:$src, bb:$target))]> {
-
+  "", []
+> {
   let Constraints = "$src = $dst";
 }
 
@@ -1592,6 +1651,45 @@ def : Pat <
   (S_BUFFER_LOAD_DWORD_SGPR $sbase, (S_MOV_B32 imm:$offset))
 >;
 
+//===----------------------------------------------------------------------===//
+// SOP2 Patterns
+//===----------------------------------------------------------------------===//
+
+def : Pat <
+  (i1 (and i1:$src0, i1:$src1)),
+  (S_AND_B64 $src0, $src1)
+>;
+
+def : Pat <
+  (i1 (or i1:$src0, i1:$src1)),
+  (S_OR_B64 $src0, $src1)
+>;
+
+def : Pat <
+  (i1 (xor i1:$src0, i1:$src1)),
+  (S_XOR_B64 $src0, $src1)
+>;
+
+//===----------------------------------------------------------------------===//
+// VOP2 Patterns
+//===----------------------------------------------------------------------===//
+
+def : Pat <
+  (or i64:$src0, i64:$src1),
+  (INSERT_SUBREG (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
+    (V_OR_B32_e32 (EXTRACT_SUBREG i64:$src0, sub0),
+                  (EXTRACT_SUBREG i64:$src1, sub0)), sub0),
+    (V_OR_B32_e32 (EXTRACT_SUBREG i64:$src0, sub1),
+                  (EXTRACT_SUBREG i64:$src1, sub1)), sub1)
+>;
+
+class SextInReg <ValueType vt, int ShiftAmt> : Pat <
+  (sext_inreg i32:$src0, vt),
+  (V_ASHRREV_I32_e32 ShiftAmt, (V_LSHLREV_B32_e32 ShiftAmt, $src0))
+>;
+
+def : SextInReg <i8, 24>;
+def : SextInReg <i16, 16>;
 
 /********** ======================= **********/
 /********** Image sampling patterns **********/
@@ -1889,11 +1987,6 @@ def : Pat <
 >;
 
 def : Pat <
-  (i1 imm:$imm),
-  (S_MOV_B64 imm:$imm)
->;
-
-def : Pat <
   (i64 InlineImm<i64>:$imm),
   (S_MOV_B64 InlineImm<i64>:$imm)
 >;
diff --git a/lib/Target/R600/SILowerControlFlow.cpp b/lib/Target/R600/SILowerControlFlow.cpp
index e3cbf02f29..6601f2a980 100644
--- a/lib/Target/R600/SILowerControlFlow.cpp
+++ b/lib/Target/R600/SILowerControlFlow.cpp
@@ -67,7 +67,7 @@ private:
   static const unsigned SkipThreshold = 12;
 
   static char ID;
-  const TargetRegisterInfo *TRI;
+  const SIRegisterInfo *TRI;
   const SIInstrInfo *TII;
 
   bool shouldSkip(MachineBasicBlock *From, MachineBasicBlock *To);
@@ -94,9 +94,9 @@ public:
   SILowerControlFlowPass(TargetMachine &tm) :
     MachineFunctionPass(ID), TRI(nullptr), TII(nullptr) { }
 
-  virtual bool runOnMachineFunction(MachineFunction &MF);
+  bool runOnMachineFunction(MachineFunction &MF) override;
 
-  const char *getPassName() const {
+  const char *getPassName() const override {
     return "SI Lower control flow instructions";
   }
 
@@ -427,7 +427,7 @@ void SILowerControlFlowPass::IndirectDst(MachineInstr &MI) {
 
 bool SILowerControlFlowPass::runOnMachineFunction(MachineFunction &MF) {
   TII = static_cast<const SIInstrInfo*>(MF.getTarget().getInstrInfo());
-  TRI = MF.getTarget().getRegisterInfo();
+  TRI = static_cast<const SIRegisterInfo*>(MF.getTarget().getRegisterInfo());
   SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
 
   bool HaveKill = false;
diff --git a/lib/Target/R600/SILowerI1Copies.cpp b/lib/Target/R600/SILowerI1Copies.cpp
new file mode 100644
index 0000000000..766380ead5
--- /dev/null
+++ b/lib/Target/R600/SILowerI1Copies.cpp
@@ -0,0 +1,130 @@
+//===-- SILowerI1Copies.cpp - Lower I1 Copies -----------------------------===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+/// i1 values are usually inserted by the CFG Structurize pass and they are
+/// unique in that they can be copied from VALU to SALU registers.
+/// This is not possible for any other value type.  Since there are no
+/// MOV instructions for i1, we to use V_CMP_* and V_CNDMASK to move the i1.
+///
+//===----------------------------------------------------------------------===//
+//
+
+#define DEBUG_TYPE "si-i1-copies"
+#include "AMDGPU.h"
+#include "SIInstrInfo.h"
+#include "llvm/CodeGen/LiveIntervalAnalysis.h"
+#include "llvm/CodeGen/MachineDominators.h"
+#include "llvm/CodeGen/MachineFunctionPass.h"
+#include "llvm/CodeGen/MachineInstrBuilder.h"
+#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/IR/LLVMContext.h"
+#include "llvm/IR/Function.h"
+#include "llvm/Support/Debug.h"
+#include "llvm/Target/TargetMachine.h"
+
+using namespace llvm;
+
+namespace {
+
+class SILowerI1Copies : public MachineFunctionPass {
+public:
+  static char ID;
+
+public:
+  SILowerI1Copies() : MachineFunctionPass(ID) {
+    initializeSILowerI1CopiesPass(*PassRegistry::getPassRegistry());
+  }
+
+  virtual bool runOnMachineFunction(MachineFunction &MF) override;
+
+  virtual const char *getPassName() const override {
+    return "SI Lower il Copies";
+  }
+
+  virtual void getAnalysisUsage(AnalysisUsage &AU) const override {
+  AU.addRequired<MachineDominatorTree>();
+    AU.setPreservesCFG();
+    MachineFunctionPass::getAnalysisUsage(AU);
+  }
+};
+
+} // End anonymous namespace.
+
+INITIALIZE_PASS_BEGIN(SILowerI1Copies, DEBUG_TYPE,
+                      "SI Lower il Copies", false, false)
+INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
+INITIALIZE_PASS_END(SILowerI1Copies, DEBUG_TYPE,
+                    "SI Lower il Copies", false, false)
+
+char SILowerI1Copies::ID = 0;
+
+char &llvm::SILowerI1CopiesID = SILowerI1Copies::ID;
+
+FunctionPass *llvm::createSILowerI1CopiesPass() {
+  return new SILowerI1Copies();
+}
+
+bool SILowerI1Copies::runOnMachineFunction(MachineFunction &MF) {
+  MachineRegisterInfo &MRI = MF.getRegInfo();
+  const SIInstrInfo *TII = static_cast<const SIInstrInfo *>(
+      MF.getTarget().getInstrInfo());
+  const TargetRegisterInfo *TRI = MF.getTarget().getRegisterInfo();
+
+  for (MachineFunction::iterator BI = MF.begin(), BE = MF.end();
+                                                  BI != BE; ++BI) {
+
+    MachineBasicBlock &MBB = *BI;
+    MachineBasicBlock::iterator I, Next;
+    for (I = MBB.begin(); I != MBB.end(); I = Next) {
+      Next = std::next(I);
+      MachineInstr &MI = *I;
+
+      if (MI.getOpcode() == AMDGPU::V_MOV_I1) {
+        MI.setDesc(TII->get(AMDGPU::V_MOV_B32_e32));
+        continue;
+      }
+
+      if (MI.getOpcode() != AMDGPU::COPY ||
+          !TargetRegisterInfo::isVirtualRegister(MI.getOperand(0).getReg()) ||
+          !TargetRegisterInfo::isVirtualRegister(MI.getOperand(1).getReg()))
+        continue;
+
+
+      const TargetRegisterClass *DstRC =
+          MRI.getRegClass(MI.getOperand(0).getReg());
+      const TargetRegisterClass *SrcRC =
+          MRI.getRegClass(MI.getOperand(1).getReg());
+
+      if (DstRC == &AMDGPU::VReg_1RegClass &&
+          TRI->getCommonSubClass(SrcRC, &AMDGPU::SGPR_64RegClass)) {
+        BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(AMDGPU::V_CNDMASK_B32_e64))
+                .addOperand(MI.getOperand(0))
+                .addImm(0)
+                .addImm(-1)
+                .addOperand(MI.getOperand(1))
+                .addImm(0)
+                .addImm(0)
+                .addImm(0)
+                .addImm(0);
+        MI.eraseFromParent();
+      } else if (TRI->getCommonSubClass(DstRC, &AMDGPU::SGPR_64RegClass) &&
+                 SrcRC == &AMDGPU::VReg_1RegClass) {
+        BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(AMDGPU::V_CMP_NE_I32_e64))
+                .addOperand(MI.getOperand(0))
+                .addImm(0)
+                .addOperand(MI.getOperand(1))
+                .addImm(0)
+                .addImm(0)
+                .addImm(0)
+                .addImm(0);
+        MI.eraseFromParent();
+      }
+
+    }
+  }
+  return false;
+}
diff --git a/lib/Target/R600/SIMachineFunctionInfo.h b/lib/Target/R600/SIMachineFunctionInfo.h
index 8dc82a0b42..ef38270d51 100644
--- a/lib/Target/R600/SIMachineFunctionInfo.h
+++ b/lib/Target/R600/SIMachineFunctionInfo.h
@@ -25,7 +25,7 @@ class MachineRegisterInfo;
 /// This class keeps track of the SPI_SP_INPUT_ADDR config register, which
 /// tells the hardware which interpolation parameters to load.
 class SIMachineFunctionInfo : public AMDGPUMachineFunction {
-  virtual void anchor();
+  void anchor() override;
 public:
 
   struct SpilledReg {
diff --git a/lib/Target/R600/SIRegisterInfo.h b/lib/Target/R600/SIRegisterInfo.h
index 8148f7fa47..54717c184b 100644
--- a/lib/Target/R600/SIRegisterInfo.h
+++ b/lib/Target/R600/SIRegisterInfo.h
@@ -27,22 +27,22 @@ struct SIRegisterInfo : public AMDGPURegisterInfo {
 
   SIRegisterInfo(AMDGPUTargetMachine &tm);
 
-  virtual BitVector getReservedRegs(const MachineFunction &MF) const;
+  BitVector getReservedRegs(const MachineFunction &MF) const override;
 
-  virtual unsigned getRegPressureLimit(const TargetRegisterClass *RC,
-                                       MachineFunction &MF) const;
+  unsigned getRegPressureLimit(const TargetRegisterClass *RC,
+                               MachineFunction &MF) const override;
 
   /// \param RC is an AMDIL reg class.
   ///
   /// \returns the SI register class that is equivalent to \p RC.
-  virtual const TargetRegisterClass *
-    getISARegClass(const TargetRegisterClass *RC) const;
+  const TargetRegisterClass *
+    getISARegClass(const TargetRegisterClass *RC) const override;
 
   /// \brief get the register class of the specified type to use in the
   /// CFGStructurizer
-  virtual const TargetRegisterClass * getCFGStructurizerRegClass(MVT VT) const;
+  const TargetRegisterClass * getCFGStructurizerRegClass(MVT VT) const override;
 
-  virtual unsigned getHWRegIndex(unsigned Reg) const;
+  unsigned getHWRegIndex(unsigned Reg) const override;
 
   /// \brief Return the 'base' register class for this register.
   /// e.g. SGPR0 => SReg_32, VGPR => VReg_32 SGPR0_SGPR1 -> SReg_32, etc.
diff --git a/lib/Target/R600/SIRegisterInfo.td b/lib/Target/R600/SIRegisterInfo.td
index 6d6d8b9bd8..f1f01deaf3 100644
--- a/lib/Target/R600/SIRegisterInfo.td
+++ b/lib/Target/R600/SIRegisterInfo.td
@@ -189,6 +189,8 @@ def VReg_256 : RegisterClass<"AMDGPU", [v32i8, v8i32, v8f32], 256, (add VGPR_256
 
 def VReg_512 : RegisterClass<"AMDGPU", [v16i32, v16f32], 512, (add VGPR_512)>;
 
+def VReg_1 : RegisterClass<"AMDGPU", [i1], 32, (add VGPR_32)>;
+
 //===----------------------------------------------------------------------===//
 //  [SV]Src_(32|64) register classes, can have either an immediate or an register
 //===----------------------------------------------------------------------===//
diff --git a/lib/Target/R600/SITypeRewriter.cpp b/lib/Target/R600/SITypeRewriter.cpp
index fb374ca42d..a0b6907dd7 100644
--- a/lib/Target/R600/SITypeRewriter.cpp
+++ b/lib/Target/R600/SITypeRewriter.cpp
@@ -39,9 +39,9 @@ class SITypeRewriter : public FunctionPass,
 
 public:
   SITypeRewriter() : FunctionPass(ID) { }
-  virtual bool doInitialization(Module &M);
-  virtual bool runOnFunction(Function &F);
-  virtual const char *getPassName() const {
+  bool doInitialization(Module &M) override;
+  bool runOnFunction(Function &F) override;
+  const char *getPassName() const override {
     return "SI Type Rewriter";
   }
   void visitLoadInst(LoadInst &I);
diff --git a/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp b/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp
index 9f3ef1c4b2..da88820f52 100644
--- a/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp
+++ b/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp
@@ -49,15 +49,15 @@ class SparcAsmParser : public MCTargetAsmParser {
   bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
                                SmallVectorImpl<MCParsedAsmOperand*> &Operands,
                                MCStreamer &Out, unsigned &ErrorInfo,
-                               bool MatchingInlineAsm);
-  bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
+                               bool MatchingInlineAsm) override;
+  bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
   bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
                         SMLoc NameLoc,
-                        SmallVectorImpl<MCParsedAsmOperand*> &Operands);
-  bool ParseDirective(AsmToken DirectiveID);
+                        SmallVectorImpl<MCParsedAsmOperand*> &Operands) override;
+  bool ParseDirective(AsmToken DirectiveID) override;
 
-  virtual unsigned validateTargetOperandClass(MCParsedAsmOperand *Op,
-                                              unsigned Kind);
+  unsigned validateTargetOperandClass(MCParsedAsmOperand *Op,
+                                      unsigned Kind) override;
 
   // Custom parse functions for Sparc specific operands.
   OperandMatchResultTy
@@ -182,10 +182,10 @@ private:
     struct MemOp Mem;
   };
 public:
-  bool isToken() const { return Kind == k_Token; }
-  bool isReg() const { return Kind == k_Register; }
-  bool isImm() const { return Kind == k_Immediate; }
-  bool isMem() const { return isMEMrr() || isMEMri(); }
+  bool isToken() const override { return Kind == k_Token; }
+  bool isReg() const override { return Kind == k_Register; }
+  bool isImm() const override { return Kind == k_Immediate; }
+  bool isMem() const override { return isMEMrr() || isMEMri(); }
   bool isMEMrr() const { return Kind == k_MemoryReg; }
   bool isMEMri() const { return Kind == k_MemoryImm; }
 
@@ -204,7 +204,7 @@ public:
     return StringRef(Tok.Data, Tok.Length);
   }
 
-  unsigned getReg() const {
+  unsigned getReg() const override {
     assert((Kind == k_Register) && "Invalid access!");
     return Reg.RegNum;
   }
@@ -230,15 +230,15 @@ public:
   }
 
   /// getStartLoc - Get the location of the first token of this operand.
-  SMLoc getStartLoc() const {
+  SMLoc getStartLoc() const override {
     return StartLoc;
   }
   /// getEndLoc - Get the location of the last token of this operand.
-  SMLoc getEndLoc() const {
+  SMLoc getEndLoc() const override {
     return EndLoc;
   }
 
-  virtual void print(raw_ostream &OS) const {
+  void print(raw_ostream &OS) const override {
     switch (Kind) {
     case k_Token:     OS << "Token: " << getToken() << "\n"; break;
     case k_Register:  OS << "Reg: #" << getReg() << "\n"; break;
diff --git a/lib/Target/Sparc/DelaySlotFiller.cpp b/lib/Target/Sparc/DelaySlotFiller.cpp
index 7a82843359..f3441ffcf6 100644
--- a/lib/Target/Sparc/DelaySlotFiller.cpp
+++ b/lib/Target/Sparc/DelaySlotFiller.cpp
@@ -50,12 +50,12 @@ namespace {
         Subtarget(&TM.getSubtarget<SparcSubtarget>()) {
     }
 
-    virtual const char *getPassName() const {
+    const char *getPassName() const override {
       return "SPARC Delay Slot Filler";
     }
 
     bool runOnMachineBasicBlock(MachineBasicBlock &MBB);
-    bool runOnMachineFunction(MachineFunction &F) {
+    bool runOnMachineFunction(MachineFunction &F) override {
       bool Changed = false;
 
       // This pass invalidates liveness information when it reorders
diff --git a/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp b/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp
index f769c31c05..4df09904c9 100644
--- a/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp
+++ b/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp
@@ -38,12 +38,12 @@ public:
   virtual ~SparcDisassembler() {}
 
   /// getInstruction - See MCDisassembler.
-  virtual DecodeStatus getInstruction(MCInst &instr,
-                                      uint64_t &size,
-                                      const MemoryObject &region,
-                                      uint64_t address,
-                                      raw_ostream &vStream,
-                                      raw_ostream &cStream) const;
+  DecodeStatus getInstruction(MCInst &instr,
+                              uint64_t &size,
+                              const MemoryObject &region,
+                              uint64_t address,
+                              raw_ostream &vStream,
+                              raw_ostream &cStream) const override;
 };
 
 }
diff --git a/lib/Target/Sparc/InstPrinter/SparcInstPrinter.h b/lib/Target/Sparc/InstPrinter/SparcInstPrinter.h
index 056542096b..d9b0779621 100644
--- a/lib/Target/Sparc/InstPrinter/SparcInstPrinter.h
+++ b/lib/Target/Sparc/InstPrinter/SparcInstPrinter.h
@@ -30,8 +30,8 @@ public:
                   const MCSubtargetInfo &sti)
    : MCInstPrinter(MAI, MII, MRI), STI(sti) {}
 
-  virtual void printRegName(raw_ostream &OS, unsigned RegNo) const;
-  virtual void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot);
+  void printRegName(raw_ostream &OS, unsigned RegNo) const override;
+  void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot) override;
   bool printSparcAliasInstr(const MCInst *MI, raw_ostream &OS);
   bool isV9() const;
 
diff --git a/lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp b/lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp
index 39c9996459..7d517b699b 100644
--- a/lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp
+++ b/lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp
@@ -102,11 +102,11 @@ namespace {
   public:
     SparcAsmBackend(const Target &T) : MCAsmBackend(), TheTarget(T) {}
 
-    unsigned getNumFixupKinds() const {
+    unsigned getNumFixupKinds() const override {
       return Sparc::NumTargetFixupKinds;
     }
 
-    const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const {
+    const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override {
       const static MCFixupKindInfo Infos[Sparc::NumTargetFixupKinds] = {
         // name                    offset bits  flags
         { "fixup_sparc_call30",     2,     30,  MCFixupKindInfo::FKF_IsPCRel },
@@ -184,7 +184,7 @@ namespace {
       }
     }
 
-    bool mayNeedRelaxation(const MCInst &Inst) const {
+    bool mayNeedRelaxation(const MCInst &Inst) const override {
       // FIXME.
       return false;
     }
@@ -194,17 +194,17 @@ namespace {
     bool fixupNeedsRelaxation(const MCFixup &Fixup,
                               uint64_t Value,
                               const MCRelaxableFragment *DF,
-                              const MCAsmLayout &Layout) const {
+                              const MCAsmLayout &Layout) const override {
       // FIXME.
       assert(0 && "fixupNeedsRelaxation() unimplemented");
       return false;
     }
-    void relaxInstruction(const MCInst &Inst, MCInst &Res) const {
+    void relaxInstruction(const MCInst &Inst, MCInst &Res) const override {
       // FIXME.
       assert(0 && "relaxInstruction() unimplemented");
     }
 
-    bool writeNopData(uint64_t Count, MCObjectWriter *OW) const {
+    bool writeNopData(uint64_t Count, MCObjectWriter *OW) const override {
       // Cannot emit NOP with size not multiple of 32 bits.
       if (Count % 4 != 0)
         return false;
@@ -229,7 +229,7 @@ namespace {
       SparcAsmBackend(T), OSType(OSType) { }
 
     void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
-                    uint64_t Value, bool IsPCRel) const {
+                    uint64_t Value, bool IsPCRel) const override {
 
       Value = adjustFixupValue(Fixup.getKind(), Value);
       if (!Value) return;           // Doesn't change encoding.
@@ -244,7 +244,7 @@ namespace {
 
     }
 
-    MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
+    MCObjectWriter *createObjectWriter(raw_ostream &OS) const override {
       uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(OSType);
       return createSparcELFObjectWriter(OS, is64Bit(), OSABI);
     }
diff --git a/lib/Target/Sparc/MCTargetDesc/SparcMCAsmInfo.h b/lib/Target/Sparc/MCTargetDesc/SparcMCAsmInfo.h
index d53d09deee..e126b687af 100644
--- a/lib/Target/Sparc/MCTargetDesc/SparcMCAsmInfo.h
+++ b/lib/Target/Sparc/MCTargetDesc/SparcMCAsmInfo.h
@@ -20,15 +20,15 @@ namespace llvm {
 class StringRef;
 
 class SparcELFMCAsmInfo : public MCAsmInfoELF {
-  virtual void anchor();
+  void anchor() override;
 public:
   explicit SparcELFMCAsmInfo(StringRef TT);
-  virtual const MCExpr* getExprForPersonalitySymbol(const MCSymbol *Sym,
-                                                    unsigned Encoding,
-                                                    MCStreamer &Streamer) const;
-  virtual const MCExpr* getExprForFDESymbol(const MCSymbol *Sym,
-                                            unsigned Encoding,
-                                            MCStreamer &Streamer) const;
+  const MCExpr*
+  getExprForPersonalitySymbol(const MCSymbol *Sym, unsigned Encoding,
+                              MCStreamer &Streamer) const override;
+  const MCExpr* getExprForFDESymbol(const MCSymbol *Sym,
+                                    unsigned Encoding,
+                                    MCStreamer &Streamer) const override;
 
 };
 
diff --git a/lib/Target/Sparc/MCTargetDesc/SparcMCCodeEmitter.cpp b/lib/Target/Sparc/MCTargetDesc/SparcMCCodeEmitter.cpp
index 7731308916..b19ad7b45c 100644
--- a/lib/Target/Sparc/MCTargetDesc/SparcMCCodeEmitter.cpp
+++ b/lib/Target/Sparc/MCTargetDesc/SparcMCCodeEmitter.cpp
@@ -42,7 +42,7 @@ public:
 
   void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
                          SmallVectorImpl<MCFixup> &Fixups,
-                         const MCSubtargetInfo &STI) const;
+                         const MCSubtargetInfo &STI) const override;
 
   // getBinaryCodeForInstr - TableGen'erated function for getting the
   // binary encoding for an instruction.
diff --git a/lib/Target/Sparc/MCTargetDesc/SparcMCExpr.h b/lib/Target/Sparc/MCTargetDesc/SparcMCExpr.h
index be6526e8ad..78dd945e22 100644
--- a/lib/Target/Sparc/MCTargetDesc/SparcMCExpr.h
+++ b/lib/Target/Sparc/MCTargetDesc/SparcMCExpr.h
@@ -85,15 +85,15 @@ public:
   Sparc::Fixups getFixupKind() const { return getFixupKind(Kind); }
 
   /// @}
-  void PrintImpl(raw_ostream &OS) const;
+  void PrintImpl(raw_ostream &OS) const override;
   bool EvaluateAsRelocatableImpl(MCValue &Res,
-                                 const MCAsmLayout *Layout) const;
-  void AddValueSymbols(MCAssembler *) const;
-  const MCSection *FindAssociatedSection() const {
+                                 const MCAsmLayout *Layout) const override;
+  void AddValueSymbols(MCAssembler *) const override;
+  const MCSection *FindAssociatedSection() const override {
     return getSubExpr()->FindAssociatedSection();
   }
 
-  void fixELFSymbolsInTLSFixups(MCAssembler &Asm) const;
+  void fixELFSymbolsInTLSFixups(MCAssembler &Asm) const override;
 
   static bool classof(const MCExpr *E) {
     return E->getKind() == MCExpr::Target;
diff --git a/lib/Target/Sparc/SparcAsmPrinter.cpp b/lib/Target/Sparc/SparcAsmPrinter.cpp
index e185a7a507..1b7330e8c5 100644
--- a/lib/Target/Sparc/SparcAsmPrinter.cpp
+++ b/lib/Target/Sparc/SparcAsmPrinter.cpp
@@ -46,7 +46,7 @@ namespace {
     explicit SparcAsmPrinter(TargetMachine &TM, MCStreamer &Streamer)
       : AsmPrinter(TM, Streamer) {}
 
-    virtual const char *getPassName() const {
+    const char *getPassName() const override {
       return "Sparc Assembly Printer";
     }
 
@@ -55,9 +55,9 @@ namespace {
                          const char *Modifier = nullptr);
     void printCCOperand(const MachineInstr *MI, int opNum, raw_ostream &OS);
 
-    virtual void EmitFunctionBodyStart();
-    virtual void EmitInstruction(const MachineInstr *MI);
-    virtual void EmitEndOfAsmFile(Module &M);
+    void EmitFunctionBodyStart() override;
+    void EmitInstruction(const MachineInstr *MI) override;
+    void EmitEndOfAsmFile(Module &M) override;
 
     static const char *getRegisterName(unsigned RegNo) {
       return SparcInstPrinter::getRegisterName(RegNo);
@@ -65,10 +65,10 @@ namespace {
 
     bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
                          unsigned AsmVariant, const char *ExtraCode,
-                         raw_ostream &O);
+                         raw_ostream &O) override;
     bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo,
                                unsigned AsmVariant, const char *ExtraCode,
-                               raw_ostream &O);
+                               raw_ostream &O) override;
 
     void LowerGETPCXAndEmitMCInsts(const MachineInstr *MI,
                                    const MCSubtargetInfo &STI);
diff --git a/lib/Target/Sparc/SparcCodeEmitter.cpp b/lib/Target/Sparc/SparcCodeEmitter.cpp
index 4011ca5d5e..247da2a957 100644
--- a/lib/Target/Sparc/SparcCodeEmitter.cpp
+++ b/lib/Target/Sparc/SparcCodeEmitter.cpp
@@ -40,7 +40,7 @@ class SparcCodeEmitter : public MachineFunctionPass {
   const std::vector<MachineConstantPoolEntry> *MCPEs;
   bool IsPIC;
 
-  void getAnalysisUsage(AnalysisUsage &AU) const {
+  void getAnalysisUsage(AnalysisUsage &AU) const override {
     AU.addRequired<MachineModuleInfo> ();
     MachineFunctionPass::getAnalysisUsage(AU);
   }
@@ -53,9 +53,9 @@ public:
       TM(tm), MCE(mce), MCPEs(nullptr),
       IsPIC(TM.getRelocationModel() == Reloc::PIC_) {}
 
-  bool runOnMachineFunction(MachineFunction &MF);
+  bool runOnMachineFunction(MachineFunction &MF) override;
 
-  virtual const char *getPassName() const {
+  const char *getPassName() const override {
     return "Sparc Machine Code Emitter";
   }
 
diff --git a/lib/Target/Sparc/SparcFrameLowering.cpp b/lib/Target/Sparc/SparcFrameLowering.cpp
index d96a4c0649..a37da94df1 100644
--- a/lib/Target/Sparc/SparcFrameLowering.cpp
+++ b/lib/Target/Sparc/SparcFrameLowering.cpp
@@ -109,18 +109,21 @@ void SparcFrameLowering::emitPrologue(MachineFunction &MF) const {
   // Emit ".cfi_def_cfa_register 30".
   unsigned CFIIndex =
       MMI.addFrameInst(MCCFIInstruction::createDefCfaRegister(nullptr, regFP));
-  BuildMI(MBB, MBBI, dl, TII.get(SP::CFI_INSTRUCTION)).addCFIIndex(CFIIndex);
+  BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
+      .addCFIIndex(CFIIndex);
 
   // Emit ".cfi_window_save".
   CFIIndex = MMI.addFrameInst(MCCFIInstruction::createWindowSave(nullptr));
-  BuildMI(MBB, MBBI, dl, TII.get(SP::CFI_INSTRUCTION)).addCFIIndex(CFIIndex);
+  BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
+      .addCFIIndex(CFIIndex);
 
   unsigned regInRA = MRI->getDwarfRegNum(SP::I7, true);
   unsigned regOutRA = MRI->getDwarfRegNum(SP::O7, true);
   // Emit ".cfi_register 15, 31".
   CFIIndex = MMI.addFrameInst(
       MCCFIInstruction::createRegister(nullptr, regOutRA, regInRA));
-  BuildMI(MBB, MBBI, dl, TII.get(SP::CFI_INSTRUCTION)).addCFIIndex(CFIIndex);
+  BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
+      .addCFIIndex(CFIIndex);
 }
 
 void SparcFrameLowering::
diff --git a/lib/Target/Sparc/SparcFrameLowering.h b/lib/Target/Sparc/SparcFrameLowering.h
index c13ca1a014..bda7b7cd18 100644
--- a/lib/Target/Sparc/SparcFrameLowering.h
+++ b/lib/Target/Sparc/SparcFrameLowering.h
@@ -31,17 +31,18 @@ public:
 
   /// emitProlog/emitEpilog - These methods insert prolog and epilog code into
   /// the function.
-  void emitPrologue(MachineFunction &MF) const;
-  void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
+  void emitPrologue(MachineFunction &MF) const override;
+  void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override;
 
-  void eliminateCallFramePseudoInstr(MachineFunction &MF,
-                                     MachineBasicBlock &MBB,
-                                     MachineBasicBlock::iterator I) const;
+  void
+  eliminateCallFramePseudoInstr(MachineFunction &MF,
+                                MachineBasicBlock &MBB,
+                                MachineBasicBlock::iterator I) const override;
 
-  bool hasReservedCallFrame(const MachineFunction &MF) const;
-  bool hasFP(const MachineFunction &MF) const;
+  bool hasReservedCallFrame(const MachineFunction &MF) const override;
+  bool hasFP(const MachineFunction &MF) const override;
   void processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
-                                            RegScavenger *RS = nullptr) const;
+                                     RegScavenger *RS = nullptr) const override;
 
 private:
   // Remap input registers to output registers for leaf procedure.
diff --git a/lib/Target/Sparc/SparcISelDAGToDAG.cpp b/lib/Target/Sparc/SparcISelDAGToDAG.cpp
index 1946c0f998..2fade27f2d 100644
--- a/lib/Target/Sparc/SparcISelDAGToDAG.cpp
+++ b/lib/Target/Sparc/SparcISelDAGToDAG.cpp
@@ -41,7 +41,7 @@ public:
       TM(tm) {
   }
 
-  SDNode *Select(SDNode *N);
+  SDNode *Select(SDNode *N) override;
 
   // Complex Pattern Selectors.
   bool SelectADDRrr(SDValue N, SDValue &R1, SDValue &R2);
@@ -49,11 +49,11 @@ public:
 
   /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
   /// inline asm expressions.
-  virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
-                                            char ConstraintCode,
-                                            std::vector<SDValue> &OutOps);
+  bool SelectInlineAsmMemoryOperand(const SDValue &Op,
+                                    char ConstraintCode,
+                                    std::vector<SDValue> &OutOps) override;
 
-  virtual const char *getPassName() const {
+  const char *getPassName() const override {
     return "SPARC DAG->DAG Pattern Instruction Selection";
   }
 
diff --git a/lib/Target/Sparc/SparcISelLowering.h b/lib/Target/Sparc/SparcISelLowering.h
index f7b45d0677..6fb894026a 100644
--- a/lib/Target/Sparc/SparcISelLowering.h
+++ b/lib/Target/Sparc/SparcISelLowering.h
@@ -55,47 +55,47 @@ namespace llvm {
     const SparcSubtarget *Subtarget;
   public:
     SparcTargetLowering(TargetMachine &TM);
-    virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
+    SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
 
     /// computeMaskedBitsForTargetNode - Determine which of the bits specified
     /// in Mask are known to be either zero or one and return them in the
     /// KnownZero/KnownOne bitsets.
-    virtual void computeMaskedBitsForTargetNode(const SDValue Op,
-                                                APInt &KnownZero,
-                                                APInt &KnownOne,
-                                                const SelectionDAG &DAG,
-                                                unsigned Depth = 0) const;
+    void computeMaskedBitsForTargetNode(const SDValue Op,
+                                        APInt &KnownZero,
+                                        APInt &KnownOne,
+                                        const SelectionDAG &DAG,
+                                        unsigned Depth = 0) const override;
 
-    virtual MachineBasicBlock *
+    MachineBasicBlock *
       EmitInstrWithCustomInserter(MachineInstr *MI,
-                                  MachineBasicBlock *MBB) const;
+                                  MachineBasicBlock *MBB) const override;
 
-    virtual const char *getTargetNodeName(unsigned Opcode) const;
+    const char *getTargetNodeName(unsigned Opcode) const override;
 
-    ConstraintType getConstraintType(const std::string &Constraint) const;
+    ConstraintType getConstraintType(const std::string &Constraint) const override;
     ConstraintWeight
     getSingleConstraintMatchWeight(AsmOperandInfo &info,
-                                   const char *constraint) const;
+                                   const char *constraint) const override;
     void LowerAsmOperandForConstraint(SDValue Op,
                                       std::string &Constraint,
                                       std::vector<SDValue> &Ops,
-                                      SelectionDAG &DAG) const;
+                                      SelectionDAG &DAG) const override;
     std::pair<unsigned, const TargetRegisterClass*>
-    getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const;
+    getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const override;
 
-    virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
-    virtual MVT getScalarShiftAmountTy(EVT LHSTy) const { return MVT::i32; }
+    bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
+    MVT getScalarShiftAmountTy(EVT LHSTy) const override { return MVT::i32; }
 
     /// getSetCCResultType - Return the ISD::SETCC ValueType
-    virtual EVT getSetCCResultType(LLVMContext &Context, EVT VT) const;
+    EVT getSetCCResultType(LLVMContext &Context, EVT VT) const override;
 
-    virtual SDValue
+    SDValue
       LowerFormalArguments(SDValue Chain,
                            CallingConv::ID CallConv,
                            bool isVarArg,
                            const SmallVectorImpl<ISD::InputArg> &Ins,
                            SDLoc dl, SelectionDAG &DAG,
-                           SmallVectorImpl<SDValue> &InVals) const;
+                           SmallVectorImpl<SDValue> &InVals) const override;
     SDValue LowerFormalArguments_32(SDValue Chain,
                                     CallingConv::ID CallConv,
                                     bool isVarArg,
@@ -109,20 +109,20 @@ namespace llvm {
                                     SDLoc dl, SelectionDAG &DAG,
                                     SmallVectorImpl<SDValue> &InVals) const;
 
-    virtual SDValue
+    SDValue
       LowerCall(TargetLowering::CallLoweringInfo &CLI,
-                SmallVectorImpl<SDValue> &InVals) const;
+                SmallVectorImpl<SDValue> &InVals) const override;
     SDValue LowerCall_32(TargetLowering::CallLoweringInfo &CLI,
                          SmallVectorImpl<SDValue> &InVals) const;
     SDValue LowerCall_64(TargetLowering::CallLoweringInfo &CLI,
                          SmallVectorImpl<SDValue> &InVals) const;
 
-    virtual SDValue
+    SDValue
       LowerReturn(SDValue Chain,
                   CallingConv::ID CallConv, bool isVarArg,
                   const SmallVectorImpl<ISD::OutputArg> &Outs,
                   const SmallVectorImpl<SDValue> &OutVals,
-                  SDLoc dl, SelectionDAG &DAG) const;
+                  SDLoc dl, SelectionDAG &DAG) const override;
     SDValue LowerReturn_32(SDValue Chain,
                            CallingConv::ID CallConv, bool IsVarArg,
                            const SmallVectorImpl<ISD::OutputArg> &Outs,
@@ -156,15 +156,15 @@ namespace llvm {
                              SDLoc DL,
                              SelectionDAG &DAG) const;
 
-    bool ShouldShrinkFPConstant(EVT VT) const {
+    bool ShouldShrinkFPConstant(EVT VT) const override {
       // Do not shrink FP constpool if VT == MVT::f128.
       // (ldd, call _Q_fdtoq) is more expensive than two ldds.
       return VT != MVT::f128;
     }
 
-    virtual void ReplaceNodeResults(SDNode *N,
+    void ReplaceNodeResults(SDNode *N,
                                     SmallVectorImpl<SDValue>& Results,
-                                    SelectionDAG &DAG) const;
+                                    SelectionDAG &DAG) const override;
 
     MachineBasicBlock *expandSelectCC(MachineInstr *MI, MachineBasicBlock *BB,
                                       unsigned BROpcode) const;
diff --git a/lib/Target/Sparc/SparcInstrInfo.h b/lib/Target/Sparc/SparcInstrInfo.h
index a86cbcb1c4..3a1472ee9b 100644
--- a/lib/Target/Sparc/SparcInstrInfo.h
+++ b/lib/Target/Sparc/SparcInstrInfo.h
@@ -45,52 +45,52 @@ public:
   /// such, whenever a client has an instance of instruction info, it should
   /// always be able to get register info as well (through this method).
   ///
-  virtual const SparcRegisterInfo &getRegisterInfo() const { return RI; }
+  const SparcRegisterInfo &getRegisterInfo() const { return RI; }
 
   /// isLoadFromStackSlot - If the specified machine instruction is a direct
   /// load from a stack slot, return the virtual or physical register number of
   /// the destination along with the FrameIndex of the loaded stack slot.  If
   /// not, return 0.  This predicate must return 0 if the instruction has
   /// any side effects other than loading from the stack slot.
-  virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
-                                       int &FrameIndex) const;
+  unsigned isLoadFromStackSlot(const MachineInstr *MI,
+                               int &FrameIndex) const override;
 
   /// isStoreToStackSlot - If the specified machine instruction is a direct
   /// store to a stack slot, return the virtual or physical register number of
   /// the source reg along with the FrameIndex of the loaded stack slot.  If
   /// not, return 0.  This predicate must return 0 if the instruction has
   /// any side effects other than storing to the stack slot.
-  virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
-                                      int &FrameIndex) const;
-
-  virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
-                             MachineBasicBlock *&FBB,
-                             SmallVectorImpl<MachineOperand> &Cond,
-                             bool AllowModify = false) const ;
-
-  virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
-
-  virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
-                                MachineBasicBlock *FBB,
-                                const SmallVectorImpl<MachineOperand> &Cond,
-                                DebugLoc DL) const;
-
-  virtual void copyPhysReg(MachineBasicBlock &MBB,
-                           MachineBasicBlock::iterator I, DebugLoc DL,
-                           unsigned DestReg, unsigned SrcReg,
-                           bool KillSrc) const;
-
-  virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
-                                   MachineBasicBlock::iterator MBBI,
-                                   unsigned SrcReg, bool isKill, int FrameIndex,
-                                   const TargetRegisterClass *RC,
-                                   const TargetRegisterInfo *TRI) const;
-
-  virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
-                                    MachineBasicBlock::iterator MBBI,
-                                    unsigned DestReg, int FrameIndex,
-                                    const TargetRegisterClass *RC,
-                                    const TargetRegisterInfo *TRI) const;
+  unsigned isStoreToStackSlot(const MachineInstr *MI,
+                              int &FrameIndex) const override;
+
+  bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
+                     MachineBasicBlock *&FBB,
+                     SmallVectorImpl<MachineOperand> &Cond,
+                     bool AllowModify = false) const override ;
+
+  unsigned RemoveBranch(MachineBasicBlock &MBB) const override;
+
+  unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
+                        MachineBasicBlock *FBB,
+                        const SmallVectorImpl<MachineOperand> &Cond,
+                        DebugLoc DL) const override;
+
+  void copyPhysReg(MachineBasicBlock &MBB,
+                   MachineBasicBlock::iterator I, DebugLoc DL,
+                   unsigned DestReg, unsigned SrcReg,
+                   bool KillSrc) const override;
+
+  void storeRegToStackSlot(MachineBasicBlock &MBB,
+                           MachineBasicBlock::iterator MBBI,
+                           unsigned SrcReg, bool isKill, int FrameIndex,
+                           const TargetRegisterClass *RC,
+                           const TargetRegisterInfo *TRI) const override;
+
+  void loadRegFromStackSlot(MachineBasicBlock &MBB,
+                            MachineBasicBlock::iterator MBBI,
+                            unsigned DestReg, int FrameIndex,
+                            const TargetRegisterClass *RC,
+                            const TargetRegisterInfo *TRI) const override;
 
   unsigned getGlobalBaseReg(MachineFunction *MF) const;
 };
diff --git a/lib/Target/Sparc/SparcJITInfo.h b/lib/Target/Sparc/SparcJITInfo.h
index 9c6e488e48..ff1b43a7f6 100644
--- a/lib/Target/Sparc/SparcJITInfo.h
+++ b/lib/Target/Sparc/SparcJITInfo.h
@@ -34,27 +34,27 @@ class SparcJITInfo : public TargetJITInfo {
   /// overwriting OLD with a branch to NEW.  This is used for self-modifying
   /// code.
   ///
-  virtual void replaceMachineCodeForFunction(void *Old, void *New);
+  void replaceMachineCodeForFunction(void *Old, void *New) override;
 
   // getStubLayout - Returns the size and alignment of the largest call stub
   // on Sparc.
-  virtual StubLayout getStubLayout();
+  StubLayout getStubLayout() override;
 
 
   /// emitFunctionStub - Use the specified JITCodeEmitter object to emit a
   /// small native function that simply calls the function at the specified
   /// address.
-  virtual void *emitFunctionStub(const Function *F, void *Fn,
-                                 JITCodeEmitter &JCE);
+  void *emitFunctionStub(const Function *F, void *Fn,
+                         JITCodeEmitter &JCE) override;
 
   /// getLazyResolverFunction - Expose the lazy resolver to the JIT.
-  virtual LazyResolverFn getLazyResolverFunction(JITCompilerFn);
+  LazyResolverFn getLazyResolverFunction(JITCompilerFn) override;
 
   /// relocate - Before the JIT can run a block of code that has been emitted,
   /// it must rewrite the code to contain the actual addresses of any
   /// referenced global symbols.
-  virtual void relocate(void *Function, MachineRelocation *MR,
-                        unsigned NumRelocs, unsigned char *GOTBase);
+  void relocate(void *Function, MachineRelocation *MR,
+                unsigned NumRelocs, unsigned char *GOTBase) override;
 
   /// Initialize - Initialize internal stage for the function being JITted.
   void Initialize(const MachineFunction &MF, bool isPIC) {
diff --git a/lib/Target/Sparc/SparcRegisterInfo.h b/lib/Target/Sparc/SparcRegisterInfo.h
index d3b9d60cdd..77f879a8be 100644
--- a/lib/Target/Sparc/SparcRegisterInfo.h
+++ b/lib/Target/Sparc/SparcRegisterInfo.h
@@ -31,25 +31,26 @@ struct SparcRegisterInfo : public SparcGenRegisterInfo {
   SparcRegisterInfo(SparcSubtarget &st);
 
   /// Code Generation virtual methods...
-  const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF =nullptr) const;
-  const uint32_t* getCallPreservedMask(CallingConv::ID CC) const;
+  const MCPhysReg *
+  getCalleeSavedRegs(const MachineFunction *MF =nullptr) const override;
+  const uint32_t* getCallPreservedMask(CallingConv::ID CC) const override;
 
   const uint32_t* getRTCallPreservedMask(CallingConv::ID CC) const;
 
-  BitVector getReservedRegs(const MachineFunction &MF) const;
+  BitVector getReservedRegs(const MachineFunction &MF) const override;
 
   const TargetRegisterClass *getPointerRegClass(const MachineFunction &MF,
-                                                unsigned Kind) const;
+                                                unsigned Kind) const override;
 
   void eliminateFrameIndex(MachineBasicBlock::iterator II,
                            int SPAdj, unsigned FIOperandNum,
-                           RegScavenger *RS = nullptr) const;
+                           RegScavenger *RS = nullptr) const override;
 
   void processFunctionBeforeFrameFinalized(MachineFunction &MF,
                                        RegScavenger *RS = nullptr) const;
 
   // Debug information queries.
-  unsigned getFrameRegister(const MachineFunction &MF) const;
+  unsigned getFrameRegister(const MachineFunction &MF) const override;
 };
 
 } // end namespace llvm
diff --git a/lib/Target/Sparc/SparcTargetMachine.cpp b/lib/Target/Sparc/SparcTargetMachine.cpp
index 83f3474759..2469d9312c 100644
--- a/lib/Target/Sparc/SparcTargetMachine.cpp
+++ b/lib/Target/Sparc/SparcTargetMachine.cpp
@@ -77,8 +77,8 @@ public:
     return getTM<SparcTargetMachine>();
   }
 
-  virtual bool addInstSelector();
-  virtual bool addPreEmitPass();
+  bool addInstSelector() override;
+  bool addPreEmitPass() override;
 };
 } // namespace
 
diff --git a/lib/Target/Sparc/SparcTargetMachine.h b/lib/Target/Sparc/SparcTargetMachine.h
index 8c9bcd36bf..b759e9ae75 100644
--- a/lib/Target/Sparc/SparcTargetMachine.h
+++ b/lib/Target/Sparc/SparcTargetMachine.h
@@ -40,28 +40,28 @@ public:
                      Reloc::Model RM, CodeModel::Model CM,
                      CodeGenOpt::Level OL, bool is64bit);
 
-  virtual const SparcInstrInfo *getInstrInfo() const { return &InstrInfo; }
-  virtual const TargetFrameLowering  *getFrameLowering() const {
+  const SparcInstrInfo *getInstrInfo() const override { return &InstrInfo; }
+  const TargetFrameLowering  *getFrameLowering() const override {
     return &FrameLowering;
   }
-  virtual const SparcSubtarget   *getSubtargetImpl() const{ return &Subtarget; }
-  virtual const SparcRegisterInfo *getRegisterInfo() const {
+  const SparcSubtarget   *getSubtargetImpl() const override{ return &Subtarget; }
+  const SparcRegisterInfo *getRegisterInfo() const override {
     return &InstrInfo.getRegisterInfo();
   }
-  virtual const SparcTargetLowering* getTargetLowering() const {
+  const SparcTargetLowering* getTargetLowering() const override {
     return &TLInfo;
   }
-  virtual const SparcSelectionDAGInfo* getSelectionDAGInfo() const {
+  const SparcSelectionDAGInfo* getSelectionDAGInfo() const override {
     return &TSInfo;
   }
-  virtual SparcJITInfo *getJITInfo() {
+  SparcJITInfo *getJITInfo() override {
     return &JITInfo;
   }
-  virtual const DataLayout       *getDataLayout() const { return &DL; }
+  const DataLayout       *getDataLayout() const override { return &DL; }
 
   // Pass Pipeline Configuration
-  virtual TargetPassConfig *createPassConfig(PassManagerBase &PM);
-  virtual bool addCodeEmitter(PassManagerBase &PM, JITCodeEmitter &JCE);
+  TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
+  bool addCodeEmitter(PassManagerBase &PM, JITCodeEmitter &JCE) override;
 };
 
 /// SparcV8TargetMachine - Sparc 32-bit target machine
diff --git a/lib/Target/Sparc/SparcTargetStreamer.h b/lib/Target/Sparc/SparcTargetStreamer.h
index 503ebd969c..3767d8e27b 100644
--- a/lib/Target/Sparc/SparcTargetStreamer.h
+++ b/lib/Target/Sparc/SparcTargetStreamer.h
@@ -31,8 +31,8 @@ class SparcTargetAsmStreamer : public SparcTargetStreamer {
 
 public:
   SparcTargetAsmStreamer(MCStreamer &S, formatted_raw_ostream &OS);
-  virtual void emitSparcRegisterIgnore(unsigned reg);
-  virtual void emitSparcRegisterScratch(unsigned reg);
+  void emitSparcRegisterIgnore(unsigned reg) override;
+  void emitSparcRegisterScratch(unsigned reg) override;
 
 };
 
@@ -41,8 +41,8 @@ class SparcTargetELFStreamer : public SparcTargetStreamer {
 public:
   SparcTargetELFStreamer(MCStreamer &S);
   MCELFStreamer &getStreamer();
-  virtual void emitSparcRegisterIgnore(unsigned reg) {}
-  virtual void emitSparcRegisterScratch(unsigned reg) {}
+  void emitSparcRegisterIgnore(unsigned reg) override {}
+  void emitSparcRegisterScratch(unsigned reg) override {}
 };
 } // end namespace llvm
 
diff --git a/lib/Target/SystemZ/SystemZElimCompare.cpp b/lib/Target/SystemZ/SystemZElimCompare.cpp
index cb1789733c..dc210d6086 100644
--- a/lib/Target/SystemZ/SystemZElimCompare.cpp
+++ b/lib/Target/SystemZ/SystemZElimCompare.cpp
@@ -71,7 +71,7 @@ public:
   }
 
   bool processBlock(MachineBasicBlock &MBB);
-  bool runOnMachineFunction(MachineFunction &F);
+  bool runOnMachineFunction(MachineFunction &F) override;
 
 private:
   Reference getRegReferences(MachineInstr *MI, unsigned Reg);
diff --git a/lib/Target/SystemZ/SystemZISelLowering.cpp b/lib/Target/SystemZ/SystemZISelLowering.cpp
index 19da96a04b..a99647a01f 100644
--- a/lib/Target/SystemZ/SystemZISelLowering.cpp
+++ b/lib/Target/SystemZ/SystemZISelLowering.cpp
@@ -772,8 +772,8 @@ LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
       }
       // Join the stores, which are independent of one another.
       Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
-                          ArrayRef<SDValue>(&MemOps[NumFixedFPRs],
-                                            SystemZ::NumArgFPRs-NumFixedFPRs));
+                          makeArrayRef(&MemOps[NumFixedFPRs],
+                                       SystemZ::NumArgFPRs-NumFixedFPRs));
     }
   }
 
diff --git a/lib/Target/SystemZ/SystemZLongBranch.cpp b/lib/Target/SystemZ/SystemZLongBranch.cpp
index 760f115b1d..8081334324 100644
--- a/lib/Target/SystemZ/SystemZLongBranch.cpp
+++ b/lib/Target/SystemZ/SystemZLongBranch.cpp
@@ -138,7 +138,7 @@ public:
     return "SystemZ Long Branch";
   }
 
-  bool runOnMachineFunction(MachineFunction &F);
+  bool runOnMachineFunction(MachineFunction &F) override;
 
 private:
   void skipNonTerminators(BlockPosition &Position, MBBInfo &Block);
diff --git a/lib/Target/SystemZ/SystemZShortenInst.cpp b/lib/Target/SystemZ/SystemZShortenInst.cpp
index 05f3c2e025..aad899c41c 100644
--- a/lib/Target/SystemZ/SystemZShortenInst.cpp
+++ b/lib/Target/SystemZ/SystemZShortenInst.cpp
@@ -31,7 +31,7 @@ public:
   }
 
   bool processBlock(MachineBasicBlock &MBB);
-  bool runOnMachineFunction(MachineFunction &F);
+  bool runOnMachineFunction(MachineFunction &F) override;
 
 private:
   bool shortenIIF(MachineInstr &MI, unsigned *GPRMap, unsigned LiveOther,
diff --git a/lib/Target/TargetMachineC.cpp b/lib/Target/TargetMachineC.cpp
index fa3e67a880..f2ac93e768 100644
--- a/lib/Target/TargetMachineC.cpp
+++ b/lib/Target/TargetMachineC.cpp
@@ -18,6 +18,7 @@
 #include "llvm/IR/Module.h"
 #include "llvm/PassManager.h"
 #include "llvm/Support/CodeGen.h"
+#include "llvm/Support/FileSystem.h"
 #include "llvm/Support/FormattedStream.h"
 #include "llvm/Support/Host.h"
 #include "llvm/Support/TargetRegistry.h"
diff --git a/lib/Target/X86/AsmParser/X86AsmInstrumentation.cpp b/lib/Target/X86/AsmParser/X86AsmInstrumentation.cpp
index 030778af7e..c8b541f3af 100644
--- a/lib/Target/X86/AsmParser/X86AsmInstrumentation.cpp
+++ b/lib/Target/X86/AsmParser/X86AsmInstrumentation.cpp
@@ -11,6 +11,7 @@
 #include "X86AsmInstrumentation.h"
 #include "X86Operand.h"
 #include "llvm/ADT/StringExtras.h"
+#include "llvm/ADT/Triple.h"
 #include "llvm/IR/Function.h"
 #include "llvm/MC/MCContext.h"
 #include "llvm/MC/MCInst.h"
@@ -207,9 +208,11 @@ void X86AsmInstrumentation::InstrumentInstruction(
     MCContext &Ctx, const MCInstrInfo &MII, MCStreamer &Out) {}
 
 X86AsmInstrumentation *
-CreateX86AsmInstrumentation(const MCTargetOptions &MCOptions, const MCContext &Ctx,
-                            const MCSubtargetInfo &STI) {
-  if (MCOptions.SanitizeAddress) {
+CreateX86AsmInstrumentation(const MCTargetOptions &MCOptions,
+                            const MCContext &Ctx, const MCSubtargetInfo &STI) {
+  Triple T(STI.getTargetTriple());
+  const bool hasCompilerRTSupport = T.isOSLinux();
+  if (hasCompilerRTSupport && MCOptions.SanitizeAddress) {
     if ((STI.getFeatureBits() & X86::Mode32Bit) != 0)
       return new X86AddressSanitizer32(STI);
     if ((STI.getFeatureBits() & X86::Mode64Bit) != 0)
diff --git a/lib/Target/X86/X86AsmPrinter.cpp b/lib/Target/X86/X86AsmPrinter.cpp
index c0c6f2148f..fd2cc7a3dc 100644
--- a/lib/Target/X86/X86AsmPrinter.cpp
+++ b/lib/Target/X86/X86AsmPrinter.cpp
@@ -527,6 +527,30 @@ void X86AsmPrinter::EmitStartOfAsmFile(Module &M) {
   }
 }
 
+static void
+emitNonLazySymbolPointer(MCStreamer &OutStreamer, MCSymbol *StubLabel,
+                         MachineModuleInfoImpl::StubValueTy &MCSym) {
+  // L_foo$stub:
+  OutStreamer.EmitLabel(StubLabel);
+  //   .indirect_symbol _foo
+  OutStreamer.EmitSymbolAttribute(MCSym.getPointer(), MCSA_IndirectSymbol);
+
+  if (MCSym.getInt())
+    // External to current translation unit.
+    OutStreamer.EmitIntValue(0, 4/*size*/);
+  else
+    // Internal to current translation unit.
+    //
+    // When we place the LSDA into the TEXT section, the type info
+    // pointers need to be indirect and pc-rel. We accomplish this by
+    // using NLPs; however, sometimes the types are local to the file.
+    // We need to fill in the value for the NLP in those cases.
+    OutStreamer.EmitValue(
+        MCSymbolRefExpr::Create(MCSym.getPointer(), OutStreamer.getContext()),
+        4 /*size*/);
+}
+
+
 
 void X86AsmPrinter::EmitEndOfAsmFile(Module &M) {
   if (Subtarget->isTargetMacho()) {
@@ -571,44 +595,24 @@ void X86AsmPrinter::EmitEndOfAsmFile(Module &M) {
                                    SectionKind::getMetadata());
       OutStreamer.SwitchSection(TheSection);
 
-      for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
-        // L_foo$non_lazy_ptr:
-        OutStreamer.EmitLabel(Stubs[i].first);
-        // .indirect_symbol _foo
-        MachineModuleInfoImpl::StubValueTy &MCSym = Stubs[i].second;
-        OutStreamer.EmitSymbolAttribute(MCSym.getPointer(),
-                                        MCSA_IndirectSymbol);
-        // .long 0
-        if (MCSym.getInt())
-          // External to current translation unit.
-          OutStreamer.EmitIntValue(0, 4/*size*/);
-        else
-          // Internal to current translation unit.
-          //
-          // When we place the LSDA into the TEXT section, the type info
-          // pointers need to be indirect and pc-rel. We accomplish this by
-          // using NLPs.  However, sometimes the types are local to the file. So
-          // we need to fill in the value for the NLP in those cases.
-          OutStreamer.EmitValue(MCSymbolRefExpr::Create(MCSym.getPointer(),
-                                                        OutContext), 4/*size*/);
-      }
+      for (auto &Stub : Stubs)
+        emitNonLazySymbolPointer(OutStreamer, Stub.first, Stub.second);
+
       Stubs.clear();
       OutStreamer.AddBlankLine();
     }
 
     Stubs = MMIMacho.GetHiddenGVStubList();
     if (!Stubs.empty()) {
-      OutStreamer.SwitchSection(getObjFileLowering().getDataSection());
-      EmitAlignment(2);
+      const MCSection *TheSection =
+        OutContext.getMachOSection("__IMPORT", "__pointers",
+                                   MachO::S_NON_LAZY_SYMBOL_POINTERS,
+                                   SectionKind::getMetadata());
+      OutStreamer.SwitchSection(TheSection);
+
+      for (auto &Stub : Stubs)
+        emitNonLazySymbolPointer(OutStreamer, Stub.first, Stub.second);
 
-      for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
-        // L_foo$non_lazy_ptr:
-        OutStreamer.EmitLabel(Stubs[i].first);
-        // .long _foo
-        OutStreamer.EmitValue(MCSymbolRefExpr::
-                              Create(Stubs[i].second.getPointer(),
-                                     OutContext), 4/*size*/);
-      }
       Stubs.clear();
       OutStreamer.AddBlankLine();
     }
diff --git a/lib/Target/X86/X86FrameLowering.cpp b/lib/Target/X86/X86FrameLowering.cpp
index 71d4e4cfa7..1c1b06623b 100644
--- a/lib/Target/X86/X86FrameLowering.cpp
+++ b/lib/Target/X86/X86FrameLowering.cpp
@@ -225,7 +225,8 @@ void mergeSPUpdatesUp(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
   }
 }
 
-/// mergeSPUpdatesDown - Merge two stack-manipulating instructions lower iterator.
+/// mergeSPUpdatesDown - Merge two stack-manipulating instructions lower
+/// iterator.
 static
 void mergeSPUpdatesDown(MachineBasicBlock &MBB,
                         MachineBasicBlock::iterator &MBBI,
@@ -257,13 +258,12 @@ void mergeSPUpdatesDown(MachineBasicBlock &MBB,
 }
 
 /// mergeSPUpdates - Checks the instruction before/after the passed
-/// instruction. If it is an ADD/SUB/LEA instruction it is deleted argument and the
-/// stack adjustment is returned as a positive value for ADD/LEA and a negative for
-/// SUB.
+/// instruction. If it is an ADD/SUB/LEA instruction it is deleted argument and
+/// the stack adjustment is returned as a positive value for ADD/LEA and a
+/// negative for SUB.
 static int mergeSPUpdates(MachineBasicBlock &MBB,
-                           MachineBasicBlock::iterator &MBBI,
-                           unsigned StackPtr,
-                           bool doMergeWithPrevious) {
+                          MachineBasicBlock::iterator &MBBI, unsigned StackPtr,
+                          bool doMergeWithPrevious) {
   if ((doMergeWithPrevious && MBBI == MBB.begin()) ||
       (!doMergeWithPrevious && MBBI == MBB.end()))
     return 0;
@@ -369,7 +369,8 @@ void X86FrameLowering::emitCalleeSavedFrameMoves(
     unsigned CFIIndex =
         MMI.addFrameInst(MCCFIInstruction::createOffset(nullptr, DwarfReg,
                                                         Offset));
-    BuildMI(MBB, MBBI, DL, TII.get(X86::CFI_INSTRUCTION)).addCFIIndex(CFIIndex);
+    BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
+        .addCFIIndex(CFIIndex);
   }
 }
 
@@ -514,7 +515,7 @@ void X86FrameLowering::emitPrologue(MachineFunction &MF) const {
       assert(StackSize);
       unsigned CFIIndex = MMI.addFrameInst(
           MCCFIInstruction::createDefCfaOffset(nullptr, 2 * stackGrowth));
-      BuildMI(MBB, MBBI, DL, TII.get(X86::CFI_INSTRUCTION))
+      BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
           .addCFIIndex(CFIIndex);
 
       // Change the rule for the FramePtr to be an "offset" rule.
@@ -522,7 +523,7 @@ void X86FrameLowering::emitPrologue(MachineFunction &MF) const {
       CFIIndex = MMI.addFrameInst(
           MCCFIInstruction::createOffset(nullptr,
                                          DwarfFramePtr, 2 * stackGrowth));
-      BuildMI(MBB, MBBI, DL, TII.get(X86::CFI_INSTRUCTION))
+      BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
           .addCFIIndex(CFIIndex);
     }
 
@@ -538,7 +539,7 @@ void X86FrameLowering::emitPrologue(MachineFunction &MF) const {
       unsigned DwarfFramePtr = RegInfo->getDwarfRegNum(FramePtr, true);
       unsigned CFIIndex = MMI.addFrameInst(
           MCCFIInstruction::createDefCfaRegister(nullptr, DwarfFramePtr));
-      BuildMI(MBB, MBBI, DL, TII.get(X86::CFI_INSTRUCTION))
+      BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
           .addCFIIndex(CFIIndex);
     }
 
@@ -567,7 +568,7 @@ void X86FrameLowering::emitPrologue(MachineFunction &MF) const {
       assert(StackSize);
       unsigned CFIIndex = MMI.addFrameInst(
           MCCFIInstruction::createDefCfaOffset(nullptr, StackOffset));
-      BuildMI(MBB, MBBI, DL, TII.get(X86::CFI_INSTRUCTION))
+      BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
           .addCFIIndex(CFIIndex);
       StackOffset += stackGrowth;
     }
@@ -704,7 +705,7 @@ void X86FrameLowering::emitPrologue(MachineFunction &MF) const {
           MCCFIInstruction::createDefCfaOffset(nullptr,
                                                -StackSize + stackGrowth));
 
-      BuildMI(MBB, MBBI, DL, TII.get(X86::CFI_INSTRUCTION))
+      BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
           .addCFIIndex(CFIIndex);
     }
 
@@ -909,7 +910,8 @@ void X86FrameLowering::emitEpilogue(MachineFunction &MF,
   }
 }
 
-int X86FrameLowering::getFrameIndexOffset(const MachineFunction &MF, int FI) const {
+int X86FrameLowering::getFrameIndexOffset(const MachineFunction &MF,
+                                          int FI) const {
   const X86RegisterInfo *RegInfo =
     static_cast<const X86RegisterInfo*>(MF.getTarget().getRegisterInfo());
   const MachineFrameInfo *MFI = MF.getFrameInfo();
@@ -1260,22 +1262,23 @@ X86FrameLowering::adjustForSegmentedStacks(MachineFunction &MF) const {
         .addReg(0).addImm(0).addReg(0).addImm(TlsOffset).addReg(TlsReg);
     } else if (STI.isTargetDarwin()) {
 
-      // TlsOffset doesn't fit into a mod r/m byte so we need an extra register
+      // TlsOffset doesn't fit into a mod r/m byte so we need an extra register.
       unsigned ScratchReg2;
       bool SaveScratch2;
       if (CompareStackPointer) {
-        // The primary scratch register is available for holding the TLS offset
+        // The primary scratch register is available for holding the TLS offset.
         ScratchReg2 = GetScratchRegister(Is64Bit, MF, true);
         SaveScratch2 = false;
       } else {
         // Need to use a second register to hold the TLS offset
         ScratchReg2 = GetScratchRegister(Is64Bit, MF, false);
 
-        // Unfortunately, with fastcc the second scratch register may hold an arg
+        // Unfortunately, with fastcc the second scratch register may hold an
+        // argument.
         SaveScratch2 = MF.getRegInfo().isLiveIn(ScratchReg2);
       }
 
-      // If Scratch2 is live-in then it needs to be saved
+      // If Scratch2 is live-in then it needs to be saved.
       assert((!MF.getRegInfo().isLiveIn(ScratchReg2) || SaveScratch2) &&
              "Scratch register is live-in and not saved");
 
@@ -1352,14 +1355,14 @@ X86FrameLowering::adjustForSegmentedStacks(MachineFunction &MF) const {
 /// http://publications.uu.se/uu/fulltext/nbn_se_uu_diva-2688.pdf)
 ///
 /// CheckStack:
-///	  temp0 = sp - MaxStack
-///	  if( temp0 < SP_LIMIT(P) ) goto IncStack else goto OldStart
+///       temp0 = sp - MaxStack
+///       if( temp0 < SP_LIMIT(P) ) goto IncStack else goto OldStart
 /// OldStart:
-///	  ...
+///       ...
 /// IncStack:
-///	  call inc_stack   # doubles the stack space
-///	  temp0 = sp - MaxStack
-///	  if( temp0 < SP_LIMIT(P) ) goto IncStack else goto OldStart
+///       call inc_stack   # doubles the stack space
+///       temp0 = sp - MaxStack
+///       if( temp0 < SP_LIMIT(P) ) goto IncStack else goto OldStart
 void X86FrameLowering::adjustForHiPEPrologue(MachineFunction &MF) const {
   const X86InstrInfo &TII = *TM.getInstrInfo();
   MachineFrameInfo *MFI = MF.getFrameInfo();
diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index 5b0882b2ef..0ed30f5a6f 100644
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -85,8 +85,8 @@ static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
   // If the input is a buildvector just emit a smaller one.
   if (Vec.getOpcode() == ISD::BUILD_VECTOR)
     return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
-                       ArrayRef<SDUse>(Vec->op_begin()+NormalizedIdxVal,
-                                       ElemsPerChunk));
+                       makeArrayRef(Vec->op_begin()+NormalizedIdxVal,
+                                    ElemsPerChunk));
 
   SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
   SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
@@ -2498,10 +2498,10 @@ X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
 
 /// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call
 /// optimization is performed and it is required (FPDiff!=0).
-static SDValue
-EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF,
-                         SDValue Chain, SDValue RetAddrFrIdx, EVT PtrVT,
-                         unsigned SlotSize, int FPDiff, SDLoc dl) {
+static SDValue EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunction &MF,
+                                        SDValue Chain, SDValue RetAddrFrIdx,
+                                        EVT PtrVT, unsigned SlotSize,
+                                        int FPDiff, SDLoc dl) {
   // Store the return address to the appropriate stack slot.
   if (!FPDiff) return Chain;
   // Calculate the new stack slot for the return address.
@@ -2538,17 +2538,19 @@ X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
   if (MF.getTarget().Options.DisableTailCalls)
     isTailCall = false;
 
-  if (isTailCall) {
+  bool IsMustTail = CLI.CS && CLI.CS->isMustTailCall();
+  if (IsMustTail) {
+    // Force this to be a tail call.  The verifier rules are enough to ensure
+    // that we can lower this successfully without moving the return address
+    // around.
+    isTailCall = true;
+  } else if (isTailCall) {
     // Check if it's really possible to do a tail call.
     isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
                     isVarArg, SR != NotStructReturn,
                     MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
                     Outs, OutVals, Ins, DAG);
 
-    if (!isTailCall && CLI.CS && CLI.CS->isMustTailCall())
-      report_fatal_error("failed to perform tail call elimination on a call "
-                         "site marked musttail");
-
     // Sibcalls are automatically detected tailcalls which do not require
     // ABI changes.
     if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
@@ -2583,7 +2585,7 @@ X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
     NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
 
   int FPDiff = 0;
-  if (isTailCall && !IsSibcall) {
+  if (isTailCall && !IsSibcall && !IsMustTail) {
     // Lower arguments at fp - stackoffset + fpdiff.
     X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
     unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
@@ -2746,8 +2748,10 @@ X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
                                         DAG.getConstant(NumXMMRegs, MVT::i8)));
   }
 
-  // For tail calls lower the arguments to the 'real' stack slot.
-  if (isTailCall) {
+  // For tail calls lower the arguments to the 'real' stack slots.  Sibcalls
+  // don't need this because the eligibility check rejects calls that require
+  // shuffling arguments passed in memory.
+  if (!IsSibcall && isTailCall) {
     // Force all the incoming stack arguments to be loaded from the stack
     // before any new outgoing arguments are stored to the stack, because the
     // outgoing stack slots may alias the incoming argument stack slots, and
@@ -2759,39 +2763,40 @@ X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
     SmallVector<SDValue, 8> MemOpChains2;
     SDValue FIN;
     int FI = 0;
-    if (getTargetMachine().Options.GuaranteedTailCallOpt) {
-      for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
-        CCValAssign &VA = ArgLocs[i];
-        if (VA.isRegLoc())
-          continue;
-        assert(VA.isMemLoc());
-        SDValue Arg = OutVals[i];
-        ISD::ArgFlagsTy Flags = Outs[i].Flags;
-        // Create frame index.
-        int32_t Offset = VA.getLocMemOffset()+FPDiff;
-        uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
-        FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
-        FIN = DAG.getFrameIndex(FI, getPointerTy());
-
-        if (Flags.isByVal()) {
-          // Copy relative to framepointer.
-          SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
-          if (!StackPtr.getNode())
-            StackPtr = DAG.getCopyFromReg(Chain, dl,
-                                          RegInfo->getStackRegister(),
-                                          getPointerTy());
-          Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
-
-          MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
-                                                           ArgChain,
-                                                           Flags, DAG, dl));
-        } else {
-          // Store relative to framepointer.
-          MemOpChains2.push_back(
-            DAG.getStore(ArgChain, dl, Arg, FIN,
-                         MachinePointerInfo::getFixedStack(FI),
-                         false, false, 0));
-        }
+    for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
+      CCValAssign &VA = ArgLocs[i];
+      if (VA.isRegLoc())
+        continue;
+      assert(VA.isMemLoc());
+      SDValue Arg = OutVals[i];
+      ISD::ArgFlagsTy Flags = Outs[i].Flags;
+      // Skip inalloca arguments.  They don't require any work.
+      if (Flags.isInAlloca())
+        continue;
+      // Create frame index.
+      int32_t Offset = VA.getLocMemOffset()+FPDiff;
+      uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
+      FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
+      FIN = DAG.getFrameIndex(FI, getPointerTy());
+
+      if (Flags.isByVal()) {
+        // Copy relative to framepointer.
+        SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
+        if (!StackPtr.getNode())
+          StackPtr = DAG.getCopyFromReg(Chain, dl,
+                                        RegInfo->getStackRegister(),
+                                        getPointerTy());
+        Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
+
+        MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
+                                                         ArgChain,
+                                                         Flags, DAG, dl));
+      } else {
+        // Store relative to framepointer.
+        MemOpChains2.push_back(
+          DAG.getStore(ArgChain, dl, Arg, FIN,
+                       MachinePointerInfo::getFixedStack(FI),
+                       false, false, 0));
       }
     }
 
@@ -4172,6 +4177,29 @@ static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
   return true;
 }
 
+// Match for INSERTI64x4 INSERTF64x4 instructions (src0[0], src1[0]) or
+// (src1[0], src0[1]), manipulation with 256-bit sub-vectors
+static bool isINSERT64x4Mask(ArrayRef<int> Mask, MVT VT, unsigned int *Imm) {
+  if (!VT.is512BitVector())
+    return false;
+
+  unsigned NumElts = VT.getVectorNumElements();
+  unsigned HalfSize = NumElts/2;
+  if (isSequentialOrUndefInRange(Mask, 0, HalfSize, 0)) {
+    if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, NumElts)) {
+      *Imm = 1;
+      return true;
+    }
+  }
+  if (isSequentialOrUndefInRange(Mask, 0, HalfSize, NumElts)) {
+    if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, HalfSize)) {
+      *Imm = 0;
+      return true;
+    }
+  }
+  return false;
+}
+
 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
 /// specifies a shuffle of elements that is suitable for input to MOVSS,
 /// MOVSD, and MOVD, i.e. setting the lowest element.
@@ -6112,10 +6140,9 @@ X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
 
     // Build both the lower and upper subvector.
     SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
-                                ArrayRef<SDValue>(&V[0], NumElems/2));
+                                makeArrayRef(&V[0], NumElems/2));
     SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
-                                ArrayRef<SDValue>(&V[NumElems / 2],
-                                                  NumElems/2));
+                                makeArrayRef(&V[NumElems / 2], NumElems/2));
 
     // Recreate the wider vector with the lower and upper part.
     if (VT.is256BitVector())
@@ -7755,6 +7782,11 @@ X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
                                 getShuffleSHUFImmediate(SVOp), DAG);
   }
 
+  unsigned Idx;
+  if (VT.is512BitVector() && isINSERT64x4Mask(M, VT, &Idx))
+    return Insert256BitVector(V1, Extract256BitVector(V2, 0, DAG, dl),
+                              Idx*(NumElems/2), DAG, dl);
+
   // Handle VPERM2F128/VPERM2I128 permutations
   if (isVPERM2X128Mask(M, VT, HasFp256))
     return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1,
@@ -20833,8 +20865,22 @@ int X86TargetLowering::getScalingFactorCost(const AddrMode &AM,
                                             Type *Ty) const {
   // Scaling factors are not free at all.
   // An indexed folded instruction, i.e., inst (reg1, reg2, scale),
-  // will take 2 allocations instead of 1 for plain addressing mode,
-  // i.e. inst (reg1).
+  // will take 2 allocations in the out of order engine instead of 1
+  // for plain addressing mode, i.e. inst (reg1).
+  // E.g.,
+  // vaddps (%rsi,%drx), %ymm0, %ymm1
+  // Requires two allocations (one for the load, one for the computation)
+  // whereas:
+  // vaddps (%rsi), %ymm0, %ymm1
+  // Requires just 1 allocation, i.e., freeing allocations for other operations
+  // and having less micro operations to execute.
+  //
+  // For some X86 architectures, this is even worse because for instance for
+  // stores, the complex addressing mode forces the instruction to use the
+  // "load" ports instead of the dedicated "store" port.
+  // E.g., on Haswell:
+  // vmovaps %ymm1, (%r8, %rdi) can use port 2 or 3.
+  // vmovaps %ymm1, (%r8) can use port 2, 3, or 7.   
   if (isLegalAddressingMode(AM, Ty))
     // Scale represents reg2 * scale, thus account for 1
     // as soon as we use a second register.
diff --git a/lib/Target/X86/X86ISelLowering.h b/lib/Target/X86/X86ISelLowering.h
index 4533404b32..78b0d01452 100644
--- a/lib/Target/X86/X86ISelLowering.h
+++ b/lib/Target/X86/X86ISelLowering.h
@@ -782,7 +782,7 @@ namespace llvm {
                                            Type *Ty) const override;
 
     /// Intel processors have a unified instruction and data cache
-    const char * getClearCacheBuiltinName() const {
+    const char * getClearCacheBuiltinName() const override {
       return nullptr; // nothing to do, move along.
     }
 
diff --git a/lib/Target/X86/X86InstrAVX512.td b/lib/Target/X86/X86InstrAVX512.td
index d7f05bc9e3..72f5aff569 100644
--- a/lib/Target/X86/X86InstrAVX512.td
+++ b/lib/Target/X86/X86InstrAVX512.td
@@ -621,6 +621,22 @@ defm VPERMT2PS : avx512_perm_3src<0x7F, "vpermt2ps",  VR512, memopv16f32, i512me
                                X86VPermv3, v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
 defm VPERMT2PD : avx512_perm_3src<0x7F, "vpermt2pd",  VR512, memopv8f64, i512mem, 
                                X86VPermv3, v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
+
+def : Pat<(v16f32 (int_x86_avx512_mask_vpermt_ps_512 (v16i32 VR512:$idx),
+                   (v16f32 VR512:$src1), (v16f32 VR512:$src2), (i16 -1))),
+          (VPERMT2PSrr VR512:$src1, VR512:$idx, VR512:$src2)>;
+
+def : Pat<(v16i32 (int_x86_avx512_mask_vpermt_d_512 (v16i32 VR512:$idx),
+                   (v16i32 VR512:$src1), (v16i32 VR512:$src2), (i16 -1))),
+          (VPERMT2Drr VR512:$src1, VR512:$idx, VR512:$src2)>;
+
+def : Pat<(v8f64 (int_x86_avx512_mask_vpermt_pd_512 (v8i64 VR512:$idx),
+                   (v8f64 VR512:$src1), (v8f64 VR512:$src2), (i8 -1))),
+          (VPERMT2PDrr VR512:$src1, VR512:$idx, VR512:$src2)>;
+
+def : Pat<(v8i64 (int_x86_avx512_mask_vpermt_q_512 (v8i64 VR512:$idx),
+                   (v8i64 VR512:$src1), (v8i64 VR512:$src2), (i8 -1))),
+          (VPERMT2Qrr VR512:$src1, VR512:$idx, VR512:$src2)>;
 //===----------------------------------------------------------------------===//
 // AVX-512 - BLEND using mask
 //
diff --git a/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp b/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp
index 0fe62f6d8e..7fef7960a8 100644
--- a/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp
+++ b/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp
@@ -42,7 +42,7 @@ public:
                                       const MemoryObject &region,
                                       uint64_t address,
                                       raw_ostream &vStream,
-                                      raw_ostream &cStream) const;
+                                      raw_ostream &cStream) const override;
 
 };
 }
diff --git a/lib/Target/XCore/InstPrinter/XCoreInstPrinter.h b/lib/Target/XCore/InstPrinter/XCoreInstPrinter.h
index 772c515b5c..98e7c98653 100644
--- a/lib/Target/XCore/InstPrinter/XCoreInstPrinter.h
+++ b/lib/Target/XCore/InstPrinter/XCoreInstPrinter.h
@@ -31,8 +31,8 @@ public:
   void printInstruction(const MCInst *MI, raw_ostream &O);
   static const char *getRegisterName(unsigned RegNo);
 
-  virtual void printRegName(raw_ostream &OS, unsigned RegNo) const;
-  virtual void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot);
+  void printRegName(raw_ostream &OS, unsigned RegNo) const override;
+  void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot) override;
 private:
   void printInlineJT(const MCInst *MI, int opNum, raw_ostream &O);
   void printInlineJT32(const MCInst *MI, int opNum, raw_ostream &O);
diff --git a/lib/Target/XCore/MCTargetDesc/XCoreMCAsmInfo.h b/lib/Target/XCore/MCTargetDesc/XCoreMCAsmInfo.h
index e53c96b8f7..da2689a640 100644
--- a/lib/Target/XCore/MCTargetDesc/XCoreMCAsmInfo.h
+++ b/lib/Target/XCore/MCTargetDesc/XCoreMCAsmInfo.h
@@ -21,7 +21,7 @@ namespace llvm {
   class Target;
 
   class XCoreMCAsmInfo : public MCAsmInfoELF {
-    virtual void anchor();
+    void anchor() override;
   public:
     explicit XCoreMCAsmInfo(StringRef TT);
   };
diff --git a/lib/Target/XCore/XCoreAsmPrinter.cpp b/lib/Target/XCore/XCoreAsmPrinter.cpp
index 2a52766e37..e98d4f933d 100644
--- a/lib/Target/XCore/XCoreAsmPrinter.cpp
+++ b/lib/Target/XCore/XCoreAsmPrinter.cpp
@@ -59,7 +59,7 @@ namespace {
       : AsmPrinter(TM, Streamer), Subtarget(TM.getSubtarget<XCoreSubtarget>()),
         MCInstLowering(*this) {}
 
-    virtual const char *getPassName() const {
+    const char *getPassName() const override {
       return "XCore Assembly Printer";
     }
 
@@ -71,18 +71,18 @@ namespace {
     void printOperand(const MachineInstr *MI, int opNum, raw_ostream &O);
     bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
                          unsigned AsmVariant, const char *ExtraCode,
-                         raw_ostream &O);
+                         raw_ostream &O) override;
     bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum,
                                unsigned AsmVariant, const char *ExtraCode,
                                raw_ostream &O) override;
 
     void emitArrayBound(MCSymbol *Sym, const GlobalVariable *GV);
-    virtual void EmitGlobalVariable(const GlobalVariable *GV);
+    void EmitGlobalVariable(const GlobalVariable *GV) override;
 
-    void EmitFunctionEntryLabel();
-    void EmitInstruction(const MachineInstr *MI);
-    void EmitFunctionBodyStart();
-    void EmitFunctionBodyEnd();
+    void EmitFunctionEntryLabel() override;
+    void EmitInstruction(const MachineInstr *MI) override;
+    void EmitFunctionBodyStart() override;
+    void EmitFunctionBodyEnd() override;
   };
 } // end of anonymous namespace
 
diff --git a/lib/Target/XCore/XCoreFrameLowering.cpp b/lib/Target/XCore/XCoreFrameLowering.cpp
index 5461a3f5cf..5499aba351 100644
--- a/lib/Target/XCore/XCoreFrameLowering.cpp
+++ b/lib/Target/XCore/XCoreFrameLowering.cpp
@@ -64,7 +64,8 @@ static void EmitDefCfaRegister(MachineBasicBlock &MBB,
                                MachineModuleInfo *MMI, unsigned DRegNum) {
   unsigned CFIIndex = MMI->addFrameInst(
       MCCFIInstruction::createDefCfaRegister(nullptr, DRegNum));
-  BuildMI(MBB, MBBI, dl, TII.get(XCore::CFI_INSTRUCTION)).addCFIIndex(CFIIndex);
+  BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
+      .addCFIIndex(CFIIndex);
 }
 
 static void EmitDefCfaOffset(MachineBasicBlock &MBB,
@@ -73,7 +74,8 @@ static void EmitDefCfaOffset(MachineBasicBlock &MBB,
                              MachineModuleInfo *MMI, int Offset) {
   unsigned CFIIndex =
       MMI->addFrameInst(MCCFIInstruction::createDefCfaOffset(nullptr, -Offset));
-  BuildMI(MBB, MBBI, dl, TII.get(XCore::CFI_INSTRUCTION)).addCFIIndex(CFIIndex);
+  BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
+      .addCFIIndex(CFIIndex);
 }
 
 static void EmitCfiOffset(MachineBasicBlock &MBB,
@@ -82,7 +84,8 @@ static void EmitCfiOffset(MachineBasicBlock &MBB,
                           unsigned DRegNum, int Offset) {
   unsigned CFIIndex = MMI->addFrameInst(
       MCCFIInstruction::createOffset(nullptr, DRegNum, Offset));
-  BuildMI(MBB, MBBI, dl, TII.get(XCore::CFI_INSTRUCTION)).addCFIIndex(CFIIndex);
+  BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
+      .addCFIIndex(CFIIndex);
 }
 
 /// The SP register is moved in steps of 'MaxImmU16' towards the bottom of the
@@ -113,7 +116,8 @@ static void IfNeededExtSP(MachineBasicBlock &MBB,
 /// IfNeededLDAWSP emits the necessary LDAWSP instructions to move the SP only
 /// as far as to make 'OffsetFromTop' reachable using an LDAWSP_lru6.
 /// \param OffsetFromTop the spill offset from the top of the frame.
-/// \param [in,out] RemainingAdj the current SP offset from the top of the frame.
+/// \param [in,out] RemainingAdj the current SP offset from the top of the
+/// frame.
 static void IfNeededLDAWSP(MachineBasicBlock &MBB,
                            MachineBasicBlock::iterator MBBI, DebugLoc dl,
                            const TargetInstrInfo &TII, int OffsetFromTop,
@@ -346,7 +350,8 @@ void XCoreFrameLowering::emitEpilogue(MachineFunction &MF,
   RemainingAdj /= 4;
 
   if (RetOpcode == XCore::EH_RETURN) {
-    // 'Restore' the exception info the unwinder has placed into the stack slots.
+    // 'Restore' the exception info the unwinder has placed into the stack
+    // slots.
     SmallVector<StackSlotInfo,2> SpillList;
     GetEHSpillList(SpillList, MFI, XFI, MF.getTarget().getTargetLowering());
     RestoreSpillList(MBB, MBBI, dl, TII, RemainingAdj, SpillList);
@@ -514,7 +519,7 @@ eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
       MBB.insert(I, New);
     }
   }
-  
+
   MBB.erase(I);
 }
 
diff --git a/lib/Target/XCore/XCoreFrameLowering.h b/lib/Target/XCore/XCoreFrameLowering.h
index 34571d335b..e4f806a452 100644
--- a/lib/Target/XCore/XCoreFrameLowering.h
+++ b/lib/Target/XCore/XCoreFrameLowering.h
@@ -27,29 +27,30 @@ namespace llvm {
 
     /// emitProlog/emitEpilog - These methods insert prolog and epilog code into
     /// the function.
-    void emitPrologue(MachineFunction &MF) const;
-    void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
+    void emitPrologue(MachineFunction &MF) const override;
+    void emitEpilogue(MachineFunction &MF,
+                      MachineBasicBlock &MBB) const override;
 
     bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
-                                   MachineBasicBlock::iterator MI,
-                                   const std::vector<CalleeSavedInfo> &CSI,
-                                   const TargetRegisterInfo *TRI) const;
+                                  MachineBasicBlock::iterator MI,
+                                  const std::vector<CalleeSavedInfo> &CSI,
+                                  const TargetRegisterInfo *TRI) const override;
     bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
-                                     MachineBasicBlock::iterator MI,
-                                     const std::vector<CalleeSavedInfo> &CSI,
-                                     const TargetRegisterInfo *TRI) const;
+                                  MachineBasicBlock::iterator MI,
+                                  const std::vector<CalleeSavedInfo> &CSI,
+                                  const TargetRegisterInfo *TRI) const override;
 
     void eliminateCallFramePseudoInstr(MachineFunction &MF,
-                                       MachineBasicBlock &MBB,
-                                       MachineBasicBlock::iterator I) const;
+                                  MachineBasicBlock &MBB,
+                                  MachineBasicBlock::iterator I) const override;
 
-    bool hasFP(const MachineFunction &MF) const;
+    bool hasFP(const MachineFunction &MF) const override;
 
     void processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
-                                              RegScavenger *RS = nullptr) const;
+                                     RegScavenger *RS = nullptr) const override;
 
     void processFunctionBeforeFrameFinalized(MachineFunction &MF,
-                                             RegScavenger *RS = nullptr) const;
+                                     RegScavenger *RS = nullptr) const override;
 
     //! Stack slot size (4 bytes)
     static int stackSlotSize() {
diff --git a/lib/Target/XCore/XCoreFrameToArgsOffsetElim.cpp b/lib/Target/XCore/XCoreFrameToArgsOffsetElim.cpp
index c18eff941b..30c7b59098 100644
--- a/lib/Target/XCore/XCoreFrameToArgsOffsetElim.cpp
+++ b/lib/Target/XCore/XCoreFrameToArgsOffsetElim.cpp
@@ -26,9 +26,9 @@ namespace {
     static char ID;
     XCoreFTAOElim() : MachineFunctionPass(ID) {}
 
-    virtual bool runOnMachineFunction(MachineFunction &Fn);
+    bool runOnMachineFunction(MachineFunction &Fn) override;
 
-    virtual const char *getPassName() const {
+    const char *getPassName() const override {
       return "XCore FRAME_TO_ARGS_OFFSET Elimination";
     }
   };
diff --git a/lib/Target/XCore/XCoreISelDAGToDAG.cpp b/lib/Target/XCore/XCoreISelDAGToDAG.cpp
index 5682f9dbad..86bc6f27ca 100644
--- a/lib/Target/XCore/XCoreISelDAGToDAG.cpp
+++ b/lib/Target/XCore/XCoreISelDAGToDAG.cpp
@@ -44,7 +44,7 @@ namespace {
       : SelectionDAGISel(TM, OptLevel),
         Subtarget(*TM.getSubtargetImpl()) { }
 
-    SDNode *Select(SDNode *N);
+    SDNode *Select(SDNode *N) override;
     SDNode *SelectBRIND(SDNode *N);
 
     /// getI32Imm - Return a target constant with the specified value, of type
@@ -70,7 +70,7 @@ namespace {
     bool SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
                                       std::vector<SDValue> &OutOps) override;
 
-    virtual const char *getPassName() const {
+    const char *getPassName() const override {
       return "XCore DAG->DAG Pattern Instruction Selection";
     } 
     
diff --git a/lib/Target/XCore/XCoreISelLowering.h b/lib/Target/XCore/XCoreISelLowering.h
index 65e2bad4f0..4e662fc4cc 100644
--- a/lib/Target/XCore/XCoreISelLowering.h
+++ b/lib/Target/XCore/XCoreISelLowering.h
@@ -97,31 +97,30 @@ namespace llvm {
     explicit XCoreTargetLowering(XCoreTargetMachine &TM);
 
     using TargetLowering::isZExtFree;
-    virtual bool isZExtFree(SDValue Val, EVT VT2) const;
+    bool isZExtFree(SDValue Val, EVT VT2) const override;
 
 
-    virtual unsigned getJumpTableEncoding() const;
-    virtual MVT getScalarShiftAmountTy(EVT LHSTy) const { return MVT::i32; }
+    unsigned getJumpTableEncoding() const override;
+    MVT getScalarShiftAmountTy(EVT LHSTy) const override { return MVT::i32; }
 
     /// LowerOperation - Provide custom lowering hooks for some operations.
-    virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
+    SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
 
     /// ReplaceNodeResults - Replace the results of node with an illegal result
     /// type with new values built out of custom code.
     ///
-    virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
-                                    SelectionDAG &DAG) const;
+    void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
+                            SelectionDAG &DAG) const override;
 
     /// getTargetNodeName - This method returns the name of a target specific
     //  DAG node.
-    virtual const char *getTargetNodeName(unsigned Opcode) const;
+    const char *getTargetNodeName(unsigned Opcode) const override;
 
-    virtual MachineBasicBlock *
+    MachineBasicBlock *
       EmitInstrWithCustomInserter(MachineInstr *MI,
-                                  MachineBasicBlock *MBB) const;
+                                  MachineBasicBlock *MBB) const override;
 
-    virtual bool isLegalAddressingMode(const AddrMode &AM,
-                                       Type *Ty) const;
+    bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const override;
 
   private:
     const XCoreTargetMachine &TM;
@@ -176,44 +175,44 @@ namespace llvm {
     // Inline asm support
     std::pair<unsigned, const TargetRegisterClass*>
     getRegForInlineAsmConstraint(const std::string &Constraint,
-                                 MVT VT) const;
+                                 MVT VT) const override;
 
     // Expand specifics
     SDValue TryExpandADDWithMul(SDNode *Op, SelectionDAG &DAG) const;
     SDValue ExpandADDSUB(SDNode *Op, SelectionDAG &DAG) const;
 
-    virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
+    SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
 
-    virtual void computeMaskedBitsForTargetNode(const SDValue Op,
-                                                APInt &KnownZero,
-                                                APInt &KnownOne,
-                                                const SelectionDAG &DAG,
-                                                unsigned Depth = 0) const;
+    void computeMaskedBitsForTargetNode(const SDValue Op,
+                                        APInt &KnownZero,
+                                        APInt &KnownOne,
+                                        const SelectionDAG &DAG,
+                                        unsigned Depth = 0) const override;
 
-    virtual SDValue
+    SDValue
       LowerFormalArguments(SDValue Chain,
                            CallingConv::ID CallConv,
                            bool isVarArg,
                            const SmallVectorImpl<ISD::InputArg> &Ins,
                            SDLoc dl, SelectionDAG &DAG,
-                           SmallVectorImpl<SDValue> &InVals) const;
+                           SmallVectorImpl<SDValue> &InVals) const override;
 
-    virtual SDValue
+    SDValue
       LowerCall(TargetLowering::CallLoweringInfo &CLI,
-                SmallVectorImpl<SDValue> &InVals) const;
+                SmallVectorImpl<SDValue> &InVals) const override;
 
-    virtual SDValue
+    SDValue
       LowerReturn(SDValue Chain,
                   CallingConv::ID CallConv, bool isVarArg,
                   const SmallVectorImpl<ISD::OutputArg> &Outs,
                   const SmallVectorImpl<SDValue> &OutVals,
-                  SDLoc dl, SelectionDAG &DAG) const;
+                  SDLoc dl, SelectionDAG &DAG) const override;
 
-    virtual bool
+    bool
       CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
                      bool isVarArg,
                      const SmallVectorImpl<ISD::OutputArg> &ArgsFlags,
-                     LLVMContext &Context) const;
+                     LLVMContext &Context) const override;
   };
 }
 
diff --git a/lib/Target/XCore/XCoreInstrInfo.h b/lib/Target/XCore/XCoreInstrInfo.h
index 48c9cb5d3e..e0be96b6ad 100644
--- a/lib/Target/XCore/XCoreInstrInfo.h
+++ b/lib/Target/XCore/XCoreInstrInfo.h
@@ -32,55 +32,55 @@ public:
   /// such, whenever a client has an instance of instruction info, it should
   /// always be able to get register info as well (through this method).
   ///
-  virtual const TargetRegisterInfo &getRegisterInfo() const { return RI; }
+  const TargetRegisterInfo &getRegisterInfo() const { return RI; }
 
   /// isLoadFromStackSlot - If the specified machine instruction is a direct
   /// load from a stack slot, return the virtual or physical register number of
   /// the destination along with the FrameIndex of the loaded stack slot.  If
   /// not, return 0.  This predicate must return 0 if the instruction has
   /// any side effects other than loading from the stack slot.
-  virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
-                                       int &FrameIndex) const;
-  
+  unsigned isLoadFromStackSlot(const MachineInstr *MI,
+                               int &FrameIndex) const override;
+
   /// isStoreToStackSlot - If the specified machine instruction is a direct
   /// store to a stack slot, return the virtual or physical register number of
   /// the source reg along with the FrameIndex of the loaded stack slot.  If
   /// not, return 0.  This predicate must return 0 if the instruction has
   /// any side effects other than storing to the stack slot.
-  virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
-                                      int &FrameIndex) const;
-  
-  virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
-                             MachineBasicBlock *&FBB,
-                             SmallVectorImpl<MachineOperand> &Cond,
-                             bool AllowModify) const;
-  
-  virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
-                                MachineBasicBlock *FBB,
-                                const SmallVectorImpl<MachineOperand> &Cond,
-                                DebugLoc DL) const;
-  
-  virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
-
-  virtual void copyPhysReg(MachineBasicBlock &MBB,
-                           MachineBasicBlock::iterator I, DebugLoc DL,
-                           unsigned DestReg, unsigned SrcReg,
-                           bool KillSrc) const;
-
-  virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
-                                   MachineBasicBlock::iterator MI,
-                                   unsigned SrcReg, bool isKill, int FrameIndex,
-                                   const TargetRegisterClass *RC,
-                                   const TargetRegisterInfo *TRI) const;
-
-  virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
-                                    MachineBasicBlock::iterator MI,
-                                    unsigned DestReg, int FrameIndex,
-                                    const TargetRegisterClass *RC,
-                                    const TargetRegisterInfo *TRI) const;
-
-  virtual bool ReverseBranchCondition(
-                            SmallVectorImpl<MachineOperand> &Cond) const;
+  unsigned isStoreToStackSlot(const MachineInstr *MI,
+                              int &FrameIndex) const override;
+
+  bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
+                     MachineBasicBlock *&FBB,
+                     SmallVectorImpl<MachineOperand> &Cond,
+                     bool AllowModify) const override;
+
+  unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
+                        MachineBasicBlock *FBB,
+                        const SmallVectorImpl<MachineOperand> &Cond,
+                        DebugLoc DL) const override;
+
+  unsigned RemoveBranch(MachineBasicBlock &MBB) const override;
+
+  void copyPhysReg(MachineBasicBlock &MBB,
+                   MachineBasicBlock::iterator I, DebugLoc DL,
+                   unsigned DestReg, unsigned SrcReg,
+                   bool KillSrc) const override;
+
+  void storeRegToStackSlot(MachineBasicBlock &MBB,
+                           MachineBasicBlock::iterator MI,
+                           unsigned SrcReg, bool isKill, int FrameIndex,
+                           const TargetRegisterClass *RC,
+                           const TargetRegisterInfo *TRI) const override;
+
+  void loadRegFromStackSlot(MachineBasicBlock &MBB,
+                            MachineBasicBlock::iterator MI,
+                            unsigned DestReg, int FrameIndex,
+                            const TargetRegisterClass *RC,
+                            const TargetRegisterInfo *TRI) const override;
+
+  bool ReverseBranchCondition(
+                          SmallVectorImpl<MachineOperand> &Cond) const override;
 
   // Emit code before MBBI to load immediate value into physical register Reg.
   // Returns an iterator to the new instruction.
diff --git a/lib/Target/XCore/XCoreLowerThreadLocal.cpp b/lib/Target/XCore/XCoreLowerThreadLocal.cpp
index b5aebbe0d5..ac3bae577b 100644
--- a/lib/Target/XCore/XCoreLowerThreadLocal.cpp
+++ b/lib/Target/XCore/XCoreLowerThreadLocal.cpp
@@ -48,7 +48,7 @@ namespace {
 
     bool lowerGlobal(GlobalVariable *GV);
 
-    bool runOnModule(Module &M);
+    bool runOnModule(Module &M) override;
   };
 }
 
diff --git a/lib/Target/XCore/XCoreRegisterInfo.h b/lib/Target/XCore/XCoreRegisterInfo.h
index ff9b95697a..aa617a0106 100644
--- a/lib/Target/XCore/XCoreRegisterInfo.h
+++ b/lib/Target/XCore/XCoreRegisterInfo.h
@@ -29,22 +29,23 @@ public:
 
   /// Code Generation virtual methods...
 
-  const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF =nullptr) const;
+  const MCPhysReg *
+  getCalleeSavedRegs(const MachineFunction *MF =nullptr) const override;
 
-  BitVector getReservedRegs(const MachineFunction &MF) const;
+  BitVector getReservedRegs(const MachineFunction &MF) const override;
   
-  bool requiresRegisterScavenging(const MachineFunction &MF) const;
+  bool requiresRegisterScavenging(const MachineFunction &MF) const override;
 
-  bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const;
+  bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override;
 
-  bool useFPForScavengingIndex(const MachineFunction &MF) const;
+  bool useFPForScavengingIndex(const MachineFunction &MF) const override;
 
   void eliminateFrameIndex(MachineBasicBlock::iterator II,
                            int SPAdj, unsigned FIOperandNum,
-                           RegScavenger *RS = nullptr) const;
+                           RegScavenger *RS = nullptr) const override;
 
   // Debug information queries.
-  unsigned getFrameRegister(const MachineFunction &MF) const;
+  unsigned getFrameRegister(const MachineFunction &MF) const override;
 
   //! Return whether to emit frame moves
   static bool needsFrameMoves(const MachineFunction &MF);
diff --git a/lib/Target/XCore/XCoreSelectionDAGInfo.h b/lib/Target/XCore/XCoreSelectionDAGInfo.h
index 31704f388a..ea6af980c0 100644
--- a/lib/Target/XCore/XCoreSelectionDAGInfo.h
+++ b/lib/Target/XCore/XCoreSelectionDAGInfo.h
@@ -25,14 +25,14 @@ public:
   explicit XCoreSelectionDAGInfo(const XCoreTargetMachine &TM);
   ~XCoreSelectionDAGInfo();
 
-  virtual SDValue
+  SDValue
   EmitTargetCodeForMemcpy(SelectionDAG &DAG, SDLoc dl,
                           SDValue Chain,
                           SDValue Op1, SDValue Op2,
                           SDValue Op3, unsigned Align, bool isVolatile,
                           bool AlwaysInline,
                           MachinePointerInfo DstPtrInfo,
-                          MachinePointerInfo SrcPtrInfo) const;
+                          MachinePointerInfo SrcPtrInfo) const override;
 };
 
 }
diff --git a/lib/Target/XCore/XCoreTargetMachine.cpp b/lib/Target/XCore/XCoreTargetMachine.cpp
index 781a87b1e9..0fb21c5d7d 100644
--- a/lib/Target/XCore/XCoreTargetMachine.cpp
+++ b/lib/Target/XCore/XCoreTargetMachine.cpp
@@ -46,9 +46,9 @@ public:
     return getTM<XCoreTargetMachine>();
   }
 
-  virtual bool addPreISel();
-  virtual bool addInstSelector();
-  virtual bool addPreEmitPass();
+  bool addPreISel() override;
+  bool addInstSelector() override;
+  bool addPreEmitPass() override;
 };
 } // namespace
 
diff --git a/lib/Target/XCore/XCoreTargetMachine.h b/lib/Target/XCore/XCoreTargetMachine.h
index a19a67727f..a57ca55f3c 100644
--- a/lib/Target/XCore/XCoreTargetMachine.h
+++ b/lib/Target/XCore/XCoreTargetMachine.h
@@ -37,28 +37,28 @@ public:
                      Reloc::Model RM, CodeModel::Model CM,
                      CodeGenOpt::Level OL);
 
-  virtual const XCoreInstrInfo *getInstrInfo() const { return &InstrInfo; }
-  virtual const XCoreFrameLowering *getFrameLowering() const {
+  const XCoreInstrInfo *getInstrInfo() const override { return &InstrInfo; }
+  const XCoreFrameLowering *getFrameLowering() const override {
     return &FrameLowering;
   }
-  virtual const XCoreSubtarget *getSubtargetImpl() const { return &Subtarget; }
-  virtual const XCoreTargetLowering *getTargetLowering() const {
+  const XCoreSubtarget *getSubtargetImpl() const override { return &Subtarget; }
+  const XCoreTargetLowering *getTargetLowering() const override {
     return &TLInfo;
   }
 
-  virtual const XCoreSelectionDAGInfo* getSelectionDAGInfo() const {
+  const XCoreSelectionDAGInfo* getSelectionDAGInfo() const override {
     return &TSInfo;
   }
 
-  virtual const TargetRegisterInfo *getRegisterInfo() const {
+  const TargetRegisterInfo *getRegisterInfo() const override {
     return &InstrInfo.getRegisterInfo();
   }
-  virtual const DataLayout       *getDataLayout() const { return &DL; }
+  const DataLayout       *getDataLayout() const override { return &DL; }
 
   // Pass Pipeline Configuration
-  virtual TargetPassConfig *createPassConfig(PassManagerBase &PM);
+  TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
 
-  virtual void addAnalysisPasses(PassManagerBase &PM);
+  void addAnalysisPasses(PassManagerBase &PM) override;
 };
 
 } // end namespace llvm
diff --git a/lib/Target/XCore/XCoreTargetObjectFile.h b/lib/Target/XCore/XCoreTargetObjectFile.h
index 733e6d384b..34d756edc3 100644
--- a/lib/Target/XCore/XCoreTargetObjectFile.h
+++ b/lib/Target/XCore/XCoreTargetObjectFile.h
@@ -22,7 +22,7 @@ static const unsigned CodeModelLargeSize = 256;
    const MCSection *ReadOnlySectionLarge;
    const MCSection *DataRelROSectionLarge;
   public:
-    void Initialize(MCContext &Ctx, const TargetMachine &TM);
+    void Initialize(MCContext &Ctx, const TargetMachine &TM) override;
 
     const MCSection *
       getExplicitSectionGlobal(const GlobalValue *GV,
diff --git a/lib/Transforms/IPO/DeadArgumentElimination.cpp b/lib/Transforms/IPO/DeadArgumentElimination.cpp
index d0a42664a6..284b896407 100644
--- a/lib/Transforms/IPO/DeadArgumentElimination.cpp
+++ b/lib/Transforms/IPO/DeadArgumentElimination.cpp
@@ -37,6 +37,7 @@
 #include "llvm/Support/raw_ostream.h"
 #include <map>
 #include <set>
+#include <tuple>
 using namespace llvm;
 
 #define DEBUG_TYPE "deadargelim"
diff --git a/lib/Transforms/IPO/PassManagerBuilder.cpp b/lib/Transforms/IPO/PassManagerBuilder.cpp
index 01ab31deca..10c51ab553 100644
--- a/lib/Transforms/IPO/PassManagerBuilder.cpp
+++ b/lib/Transforms/IPO/PassManagerBuilder.cpp
@@ -341,6 +341,9 @@ void PassManagerBuilder::populateLTOPassManager(PassManagerBase &PM,
   PM.add(createLoopDeletionPass());
   PM.add(createLoopVectorizePass(true, true));
 
+  // More scalar chains could be vectorized due to more alias information
+  PM.add(createSLPVectorizerPass()); // Vectorize parallel scalar chains.
+
   // Cleanup and simplify the code after the scalar optimizations.
   PM.add(createInstructionCombiningPass());
 
diff --git a/lib/Transforms/InstCombine/InstCombineCalls.cpp b/lib/Transforms/InstCombine/InstCombineCalls.cpp
index df217f19ac..eafdf6e7b0 100644
--- a/lib/Transforms/InstCombine/InstCombineCalls.cpp
+++ b/lib/Transforms/InstCombine/InstCombineCalls.cpp
@@ -724,13 +724,38 @@ Instruction *InstCombiner::visitCallInst(CallInst &CI) {
   case Intrinsic::x86_avx_vpermilvar_pd_256: {
     // Convert vpermil* to shufflevector if the mask is constant.
     Value *V = II->getArgOperand(1);
+    unsigned Size = cast<VectorType>(V->getType())->getNumElements();
+    assert(Size == 8 || Size == 4 || Size == 2);
+    uint32_t Indexes[8];
     if (auto C = dyn_cast<ConstantDataVector>(V)) {
-      auto V1 = II->getArgOperand(0);
-      auto V2 = UndefValue::get(V1->getType());
-      auto Shuffle = Builder->CreateShuffleVector(V1, V2, C);
-      return ReplaceInstUsesWith(CI, Shuffle);
+      // The intrinsics only read one or two bits, clear the rest.
+      for (unsigned I = 0; I < Size; ++I) {
+        uint32_t Index = C->getElementAsInteger(I) & 0x3;
+        if (II->getIntrinsicID() == Intrinsic::x86_avx_vpermilvar_pd ||
+            II->getIntrinsicID() == Intrinsic::x86_avx_vpermilvar_pd_256)
+          Index >>= 1;
+        Indexes[I] = Index;
+      }
+    } else if (isa<ConstantAggregateZero>(V)) {
+      for (unsigned I = 0; I < Size; ++I)
+        Indexes[I] = 0;
+    } else {
+      break;
     }
-    break;
+    // The _256 variants are a bit trickier since the mask bits always index
+    // into the corresponding 128 half. In order to convert to a generic
+    // shuffle, we have to make that explicit.
+    if (II->getIntrinsicID() == Intrinsic::x86_avx_vpermilvar_ps_256 ||
+        II->getIntrinsicID() == Intrinsic::x86_avx_vpermilvar_pd_256) {
+      for (unsigned I = Size / 2; I < Size; ++I)
+        Indexes[I] += Size / 2;
+    }
+    auto NewC =
+        ConstantDataVector::get(V->getContext(), makeArrayRef(Indexes, Size));
+    auto V1 = II->getArgOperand(0);
+    auto V2 = UndefValue::get(V1->getType());
+    auto Shuffle = Builder->CreateShuffleVector(V1, V2, NewC);
+    return ReplaceInstUsesWith(CI, Shuffle);
   }
 
   case Intrinsic::ppc_altivec_vperm:
diff --git a/lib/Transforms/Scalar/ConstantHoisting.cpp b/lib/Transforms/Scalar/ConstantHoisting.cpp
index 7c3a260947..763d02b9fc 100644
--- a/lib/Transforms/Scalar/ConstantHoisting.cpp
+++ b/lib/Transforms/Scalar/ConstantHoisting.cpp
@@ -43,6 +43,7 @@
 #include "llvm/IR/IntrinsicInst.h"
 #include "llvm/Pass.h"
 #include "llvm/Support/Debug.h"
+#include <tuple>
 
 using namespace llvm;
 
diff --git a/lib/Transforms/Scalar/LoopIdiomRecognize.cpp b/lib/Transforms/Scalar/LoopIdiomRecognize.cpp
index eaa73572e2..26a83dfdc3 100644
--- a/lib/Transforms/Scalar/LoopIdiomRecognize.cpp
+++ b/lib/Transforms/Scalar/LoopIdiomRecognize.cpp
@@ -115,7 +115,7 @@ namespace {
     Value *matchCondition (BranchInst *Br, BasicBlock *NonZeroTarget) const;
 
     /// Return true iff the idiom is detected in the loop. and 1) \p CntInst
-    /// is set to the instruction counting the pupulation bit. 2) \p CntPhi
+    /// is set to the instruction counting the population bit. 2) \p CntPhi
     /// is set to the corresponding phi node. 3) \p Var is set to the value
     /// whose population bits are being counted.
     bool detectIdiom
@@ -342,8 +342,8 @@ bool NclPopcountRecognize::preliminaryScreen() {
   return true;
 }
 
-Value *NclPopcountRecognize::matchCondition (BranchInst *Br,
-                                             BasicBlock *LoopEntry) const {
+Value *NclPopcountRecognize::matchCondition(BranchInst *Br,
+                                            BasicBlock *LoopEntry) const {
   if (!Br || !Br->isConditional())
     return nullptr;
 
diff --git a/lib/Transforms/Utils/LoopSimplify.cpp b/lib/Transforms/Utils/LoopSimplify.cpp
index bd825eb864..f7787dafd5 100644
--- a/lib/Transforms/Utils/LoopSimplify.cpp
+++ b/lib/Transforms/Utils/LoopSimplify.cpp
@@ -778,7 +778,7 @@ INITIALIZE_PASS_END(LoopSimplify, "loop-simplify",
 char &llvm::LoopSimplifyID = LoopSimplify::ID;
 Pass *llvm::createLoopSimplifyPass() { return new LoopSimplify(); }
 
-/// runOnLoop - Run down all loops in the CFG (recursively, but we could do
+/// runOnFunction - Run down all loops in the CFG (recursively, but we could do
 /// it in any convenient order) inserting preheaders...
 ///
 bool LoopSimplify::runOnFunction(Function &F) {
diff --git a/lib/Transforms/Utils/LoopUnroll.cpp b/lib/Transforms/Utils/LoopUnroll.cpp
index 668324881e..faaab5c12e 100644
--- a/lib/Transforms/Utils/LoopUnroll.cpp
+++ b/lib/Transforms/Utils/LoopUnroll.cpp
@@ -24,6 +24,7 @@
 #include "llvm/Analysis/ScalarEvolution.h"
 #include "llvm/IR/BasicBlock.h"
 #include "llvm/IR/Dominators.h"
+#include "llvm/IR/LLVMContext.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/raw_ostream.h"
 #include "llvm/Transforms/Utils/BasicBlockUtils.h"
@@ -228,20 +229,33 @@ bool llvm::UnrollLoop(Loop *L, unsigned Count, unsigned TripCount,
       (unsigned)GreatestCommonDivisor64(Count, TripMultiple);
   }
 
+  // Report the unrolling decision.
+  DebugLoc LoopLoc = L->getStartLoc();
+  Function *F = Header->getParent();
+  LLVMContext &Ctx = F->getContext();
+
   if (CompletelyUnroll) {
     DEBUG(dbgs() << "COMPLETELY UNROLLING loop %" << Header->getName()
           << " with trip count " << TripCount << "!\n");
+    Ctx.emitOptimizationRemark(DEBUG_TYPE, *F, LoopLoc,
+                               Twine("completely unrolled loop with ") +
+                                   Twine(TripCount) + " iterations");
   } else {
     DEBUG(dbgs() << "UNROLLING loop %" << Header->getName()
           << " by " << Count);
+    Twine DiagMsg("unrolled loop by a factor of " + Twine(Count));
     if (TripMultiple == 0 || BreakoutTrip != TripMultiple) {
       DEBUG(dbgs() << " with a breakout at trip " << BreakoutTrip);
+      DiagMsg.concat(" with a breakout at trip " + Twine(BreakoutTrip));
     } else if (TripMultiple != 1) {
       DEBUG(dbgs() << " with " << TripMultiple << " trips per branch");
+      DiagMsg.concat(" with " + Twine(TripMultiple) + " trips per branch");
     } else if (RuntimeTripCount) {
       DEBUG(dbgs() << " with run-time trip count");
+      DiagMsg.concat(" with run-time trip count");
     }
     DEBUG(dbgs() << "!\n");
+    Ctx.emitOptimizationRemark(DEBUG_TYPE, *F, LoopLoc, DiagMsg);
   }
 
   bool ContinueOnTrue = L->contains(BI->getSuccessor(0));
diff --git a/lib/Transforms/Vectorize/LoopVectorize.cpp b/lib/Transforms/Vectorize/LoopVectorize.cpp
index 843e9e90c2..7e8a1b7d3d 100644
--- a/lib/Transforms/Vectorize/LoopVectorize.cpp
+++ b/lib/Transforms/Vectorize/LoopVectorize.cpp
@@ -92,6 +92,7 @@
 #include "llvm/Transforms/Utils/VectorUtils.h"
 #include <algorithm>
 #include <map>
+#include <tuple>
 
 using namespace llvm;
 using namespace llvm::PatternMatch;
@@ -819,7 +820,8 @@ public:
   /// then this vectorization factor will be selected if vectorization is
   /// possible.
   VectorizationFactor selectVectorizationFactor(bool OptForSize,
-                                                unsigned UserVF);
+                                                unsigned UserVF,
+                                                bool ForceVectorization);
 
   /// \return The size (in bits) of the widest type in the code that
   /// needs to be vectorized. We ignore values that remain scalar such as
@@ -891,13 +893,17 @@ struct LoopVectorizeHints {
   unsigned Width;
   /// Vectorization unroll factor.
   unsigned Unroll;
-  /// Vectorization forced (-1 not selected, 0 force disabled, 1 force enabled)
-  int Force;
+  /// Vectorization forced
+  enum ForceKind {
+    FK_Undefined = -1, ///< Not selected.
+    FK_Disabled = 0,   ///< Forcing disabled.
+    FK_Enabled = 1,    ///< Forcing enabled.
+  } Force;
 
   LoopVectorizeHints(const Loop *L, bool DisableUnrolling)
   : Width(VectorizationFactor)
   , Unroll(DisableUnrolling ? 1 : VectorizationUnroll)
-  , Force(-1)
+  , Force(FK_Undefined)
   , LoopID(L->getLoopID()) {
     getHints(L);
     // The command line options override any loop metadata except for when
@@ -1010,7 +1016,8 @@ private:
         DEBUG(dbgs() << "LV: ignoring invalid unroll hint metadata\n");
     } else if (Hint == "enable") {
       if (C->getBitWidth() == 1)
-        Force = Val;
+        Force = Val == 1 ? LoopVectorizeHints::FK_Enabled
+                         : LoopVectorizeHints::FK_Disabled;
       else
         DEBUG(dbgs() << "LV: ignoring invalid enable hint metadata\n");
     } else {
@@ -1106,18 +1113,20 @@ struct LoopVectorize : public FunctionPass {
     LoopVectorizeHints Hints(L, DisableUnrolling);
 
     DEBUG(dbgs() << "LV: Loop hints:"
-                 << " force=" << (Hints.Force == 0
-                                      ? "disabled"
-                                      : (Hints.Force == 1 ? "enabled" : "?"))
-                 << " width=" << Hints.Width << " unroll=" << Hints.Unroll
-                 << "\n");
-
-    if (Hints.Force == 0) {
+                 << " force="
+                 << (Hints.Force == LoopVectorizeHints::FK_Disabled
+                         ? "disabled"
+                         : (Hints.Force == LoopVectorizeHints::FK_Enabled
+                                ? "enabled"
+                                : "?")) << " width=" << Hints.Width
+                 << " unroll=" << Hints.Unroll << "\n");
+
+    if (Hints.Force == LoopVectorizeHints::FK_Disabled) {
       DEBUG(dbgs() << "LV: Not vectorizing: #pragma vectorize disable.\n");
       return false;
     }
 
-    if (!AlwaysVectorize && Hints.Force != 1) {
+    if (!AlwaysVectorize && Hints.Force != LoopVectorizeHints::FK_Enabled) {
       DEBUG(dbgs() << "LV: Not vectorizing: No #pragma vectorize enable.\n");
       return false;
     }
@@ -1127,6 +1136,21 @@ struct LoopVectorize : public FunctionPass {
       return false;
     }
 
+    // Check the loop for a trip count threshold:
+    // do not vectorize loops with a tiny trip count.
+    BasicBlock *Latch = L->getLoopLatch();
+    const unsigned TC = SE->getSmallConstantTripCount(L, Latch);
+    if (TC > 0u && TC < TinyTripCountVectorThreshold) {
+      DEBUG(dbgs() << "LV: Found a loop with a very small trip count. "
+                   << "This loop is not worth vectorizing.");
+      if (Hints.Force == LoopVectorizeHints::FK_Enabled)
+        DEBUG(dbgs() << " But vectorizing was explicitly forced.\n");
+      else {
+        DEBUG(dbgs() << "\n");
+        return false;
+      }
+    }
+
     // Check if it is legal to vectorize the loop.
     LoopVectorizationLegality LVL(L, SE, DL, DT, TLI);
     if (!LVL.canVectorize()) {
@@ -1140,8 +1164,8 @@ struct LoopVectorize : public FunctionPass {
     // Check the function attributes to find out if this function should be
     // optimized for size.
     Function *F = L->getHeader()->getParent();
-    bool OptForSize =
-        Hints.Force != 1 && F->hasFnAttribute(Attribute::OptimizeForSize);
+    bool OptForSize = Hints.Force != LoopVectorizeHints::FK_Enabled &&
+                      F->hasFnAttribute(Attribute::OptimizeForSize);
 
     // Compute the weighted frequency of this loop being executed and see if it
     // is less than 20% of the function entry baseline frequency. Note that we
@@ -1150,7 +1174,8 @@ struct LoopVectorize : public FunctionPass {
     // exactly what block frequency models.
     if (LoopVectorizeWithBlockFrequency) {
       BlockFrequency LoopEntryFreq = BFI->getBlockFreq(L->getLoopPreheader());
-      if (Hints.Force != 1 && LoopEntryFreq < ColdEntryFreq)
+      if (Hints.Force != LoopVectorizeHints::FK_Enabled &&
+          LoopEntryFreq < ColdEntryFreq)
         OptForSize = true;
     }
 
@@ -1166,7 +1191,10 @@ struct LoopVectorize : public FunctionPass {
 
     // Select the optimal vectorization factor.
     const LoopVectorizationCostModel::VectorizationFactor VF =
-                          CM.selectVectorizationFactor(OptForSize, Hints.Width);
+        CM.selectVectorizationFactor(OptForSize, Hints.Width,
+                                     Hints.Force ==
+                                         LoopVectorizeHints::FK_Enabled);
+
     // Select the unroll factor.
     const unsigned UF = CM.selectUnrollFactor(OptForSize, Hints.Unroll, VF.Width,
                                         VF.Cost);
@@ -1182,6 +1210,13 @@ struct LoopVectorize : public FunctionPass {
       if (UF == 1)
         return false;
       DEBUG(dbgs() << "LV: Trying to at least unroll the loops.\n");
+
+      // Report the unrolling decision.
+      F->getContext().emitOptimizationRemark(
+          DEBUG_TYPE, *F, L->getStartLoc(),
+          Twine("unrolled with interleaving factor " + Twine(UF) +
+                " (vectorization not beneficial)"));
+
       // We decided not to vectorize, but we may want to unroll.
       InnerLoopUnroller Unroller(L, SE, LI, DT, DL, TLI, UF);
       Unroller.vectorize(&LVL);
@@ -1190,6 +1225,12 @@ struct LoopVectorize : public FunctionPass {
       InnerLoopVectorizer LB(L, SE, LI, DT, DL, TLI, VF.Width, UF);
       LB.vectorize(&LVL);
       ++LoopsVectorized;
+
+      // Report the vectorization decision.
+      F->getContext().emitOptimizationRemark(
+          DEBUG_TYPE, *F, L->getStartLoc(),
+          Twine("vectorized loop (vectorization factor: ") + Twine(VF.Width) +
+              ", unrolling interleave factor: " + Twine(UF) + ")");
     }
 
     // Mark the loop as already vectorized to avoid vectorizing again.
@@ -3300,15 +3341,6 @@ bool LoopVectorizationLegality::canVectorize() {
     return false;
   }
 
-  // Do not loop-vectorize loops with a tiny trip count.
-  BasicBlock *Latch = TheLoop->getLoopLatch();
-  unsigned TC = SE->getSmallConstantTripCount(TheLoop, Latch);
-  if (TC > 0u && TC < TinyTripCountVectorThreshold) {
-    DEBUG(dbgs() << "LV: Found a loop with a very small trip count. " <<
-          "This loop is not worth vectorizing.\n");
-    return false;
-  }
-
   // Check if we can vectorize the instructions and CFG in this loop.
   if (!canVectorizeInstrs()) {
     DEBUG(dbgs() << "LV: Can't vectorize the instructions or CFG\n");
@@ -5007,7 +5039,8 @@ bool LoopVectorizationLegality::blockCanBePredicated(BasicBlock *BB,
 
 LoopVectorizationCostModel::VectorizationFactor
 LoopVectorizationCostModel::selectVectorizationFactor(bool OptForSize,
-                                                      unsigned UserVF) {
+                                                      unsigned UserVF,
+                                                      bool ForceVectorization) {
   // Width 1 means no vectorize
   VectorizationFactor Factor = { 1U, 0U };
   if (OptForSize && Legal->getRuntimePointerCheck()->Need) {
@@ -5077,8 +5110,18 @@ LoopVectorizationCostModel::selectVectorizationFactor(bool OptForSize,
   }
 
   float Cost = expectedCost(1);
+#ifndef NDEBUG
+  const float ScalarCost = Cost;
+#endif /* NDEBUG */
   unsigned Width = 1;
-  DEBUG(dbgs() << "LV: Scalar loop costs: " << (int)Cost << ".\n");
+  DEBUG(dbgs() << "LV: Scalar loop costs: " << (int)ScalarCost << ".\n");
+
+  // Ignore scalar width, because the user explicitly wants vectorization.
+  if (ForceVectorization && VF > 1) {
+    Width = 2;
+    Cost = expectedCost(Width) / (float)Width;
+  }
+
   for (unsigned i=2; i <= VF; i*=2) {
     // Notice that the vector loop needs to be executed less times, so
     // we need to divide the cost of the vector loops by the width of
@@ -5092,6 +5135,9 @@ LoopVectorizationCostModel::selectVectorizationFactor(bool OptForSize,
     }
   }
 
+  DEBUG(if (ForceVectorization && Width > 1 && Cost >= ScalarCost) dbgs()
+        << "LV: Vectorization seems to be not beneficial, "
+        << "but was forced by a user.\n");
   DEBUG(dbgs() << "LV: Selecting VF: "<< Width << ".\n");
   Factor.Width = Width;
   Factor.Cost = Width * Cost;
diff --git a/lib/Transforms/Vectorize/SLPVectorizer.cpp b/lib/Transforms/Vectorize/SLPVectorizer.cpp
index 21a727bfb3..53feb959c8 100644
--- a/lib/Transforms/Vectorize/SLPVectorizer.cpp
+++ b/lib/Transforms/Vectorize/SLPVectorizer.cpp
@@ -2116,7 +2116,7 @@ unsigned SLPVectorizer::collectStores(BasicBlock *BB, BoUpSLP &R) {
     // Check that the pointer points to scalars.
     Type *Ty = SI->getValueOperand()->getType();
     if (Ty->isAggregateType() || Ty->isVectorTy())
-      return 0;
+      continue;
 
     // Find the base pointer.
     Value *Ptr = GetUnderlyingObject(SI->getPointerOperand(), DL);
diff --git a/test/Analysis/BlockFrequencyInfo/irreducible.ll b/test/Analysis/BlockFrequencyInfo/irreducible.ll
index dd4dd9ed79..af4ad15d9c 100644
--- a/test/Analysis/BlockFrequencyInfo/irreducible.ll
+++ b/test/Analysis/BlockFrequencyInfo/irreducible.ll
@@ -34,16 +34,28 @@ return:
 !0 = metadata !{metadata !"branch_weights", i32 1, i32 7}
 !1 = metadata !{metadata !"branch_weights", i32 3, i32 4}
 
-; The current BlockFrequencyInfo algorithm doesn't handle multiple entrances
-; into a loop very well.  The frequencies assigned to blocks in the loop are
-; predictable (and not absurd), but also not correct and therefore not worth
-; testing.
+; Irreducible control flow
+; ========================
 ;
-; There are two testcases below.
+; LoopInfo defines a loop as a non-trivial SCC dominated by a single block,
+; called the header.  A given loop, L, can have sub-loops, which are loops
+; within the subgraph of L that excludes the header.
 ;
-; For each testcase, I use a CHECK-NEXT/NOT combo like an XFAIL with the
-; granularity of a single check.  If/when this behaviour is fixed, we'll know
-; about it, and the test should be updated.
+; In addition to loops, -block-freq has limited support for irreducible SCCs,
+; which are SCCs with multiple entry blocks.  Irreducible SCCs are discovered
+; on they fly, and modelled as loops with multiple headers.
+;
+; The headers of irreducible sub-SCCs consist of its entry blocks and all nodes
+; that are targets of a backedge within it (excluding backedges within true
+; sub-loops).
+;
+; -block-freq is currently designed to act like a block is inserted that
+; intercepts all the edges to the headers.  All backedges and entries point to
+; this block.  Its successors are the headers, which split the frequency
+; evenly.
+;
+; There are a number of testcases below.  Only the first two have detailed
+; explanations.
 ;
 ; Testcase #1
 ; ===========
@@ -77,36 +89,31 @@ return:
 ; loop as a whole is 1/4, so the loop scale should be 4.  Summing c1 and c2
 ; gives 28/7, or 4.0, which is nice confirmation of the math above.
 ;
-; However, assuming c1 precedes c2 in reverse post-order, the current algorithm
-; returns 3/4 and 13/16, respectively.  LoopInfo ignores edges between loops
-; (and doesn't see any loops here at all), and -block-freq ignores the
-; irreducible edge from c2 to c1.
-;
+; -block-freq currently treats the two nodes as equals.
+define void @multientry(i1 %x) {
 ; CHECK-LABEL: Printing analysis {{.*}} for function 'multientry':
 ; CHECK-NEXT: block-frequency-info: multientry
-define void @multientry(i1 %x) {
-; CHECK-NEXT: entry: float = 1.0, int = [[ENTRY:[0-9]+]]
 entry:
+; CHECK-NEXT: entry: float = 1.0, int = [[ENTRY:[0-9]+]]
   br i1 %x, label %c1, label %c2, !prof !2
 
-; This is like a single-line XFAIL (see above).
-; CHECK-NEXT: c1:
-; CHECK-NOT: float = 2.142857{{[0-9]*}},
 c1:
+; CHECK-NEXT: c1: float = 2.0,
+; The "correct" answer is: float = 2.142857{{[0-9]*}},
   br i1 %x, label %c2, label %exit, !prof !2
 
-; This is like a single-line XFAIL (see above).
-; CHECK-NEXT: c2:
-; CHECK-NOT: float = 1.857142{{[0-9]*}},
 c2:
+; CHECK-NEXT: c2: float = 2.0,
+; The "correct" answer is: float = 1.857142{{[0-9]*}},
   br i1 %x, label %c1, label %exit, !prof !2
 
-; We still shouldn't lose any frequency.
-; CHECK-NEXT: exit: float = 1.0, int = [[ENTRY]]
 exit:
+; CHECK-NEXT: exit: float = 1.0, int = [[ENTRY]]
   ret void
 }
 
+!2 = metadata !{metadata !"branch_weights", i32 3, i32 1}
+
 ; Testcase #2
 ; ===========
 ;
@@ -124,73 +131,291 @@ exit:
 ; step, c1 and c2 each get 1/3 of what's left in c1 and c2 combined.  This
 ; infinite series sums to 1.
 ;
-; However, assuming c1 precedes c2 in reverse post-order, the current algorithm
-; returns 1/2 and 3/4, respectively.  LoopInfo ignores edges between loops (and
-; treats c1 and c2 as self-loops only), and -block-freq ignores the irreducible
-; edge from c2 to c1.
-;
-; Below I use a CHECK-NEXT/NOT combo like an XFAIL with the granularity of a
-; single check.  If/when this behaviour is fixed, we'll know about it, and the
-; test should be updated.
-;
+; Since the currently algorithm *always* assumes entry blocks are equal,
+; -block-freq gets the right answers here.
+define void @crossloops(i2 %x) {
 ; CHECK-LABEL: Printing analysis {{.*}} for function 'crossloops':
 ; CHECK-NEXT: block-frequency-info: crossloops
-define void @crossloops(i2 %x) {
-; CHECK-NEXT: entry: float = 1.0, int = [[ENTRY:[0-9]+]]
 entry:
+; CHECK-NEXT: entry: float = 1.0, int = [[ENTRY:[0-9]+]]
   switch i2 %x, label %exit [ i2 1, label %c1
                               i2 2, label %c2 ], !prof !3
 
-; This is like a single-line XFAIL (see above).
-; CHECK-NEXT: c1:
-; CHECK-NOT: float = 1.0,
 c1:
+; CHECK-NEXT: c1: float = 1.0,
   switch i2 %x, label %exit [ i2 1, label %c1
                               i2 2, label %c2 ], !prof !3
 
-; This is like a single-line XFAIL (see above).
-; CHECK-NEXT: c2:
-; CHECK-NOT: float = 1.0,
 c2:
+; CHECK-NEXT: c2: float = 1.0,
   switch i2 %x, label %exit [ i2 1, label %c1
                               i2 2, label %c2 ], !prof !3
 
-; We still shouldn't lose any frequency.
-; CHECK-NEXT: exit: float = 1.0, int = [[ENTRY]]
 exit:
+; CHECK-NEXT: exit: float = 1.0, int = [[ENTRY]]
   ret void
 }
 
-!2 = metadata !{metadata !"branch_weights", i32 3, i32 1}
 !3 = metadata !{metadata !"branch_weights", i32 2, i32 2, i32 2}
 
-; A reducible loop with irreducible control flow inside should still have
-; correct exit frequency.
-;
+; A true loop with irreducible control flow inside.
+define void @loop_around_irreducible(i1 %x) {
 ; CHECK-LABEL: Printing analysis {{.*}} for function 'loop_around_irreducible':
 ; CHECK-NEXT: block-frequency-info: loop_around_irreducible
-define void @loop_around_irreducible(i1 %x) {
+entry:
+; CHECK-NEXT: entry: float = 1.0, int = [[ENTRY:[0-9]+]]
+  br label %loop
+
+loop:
+; CHECK-NEXT: loop: float = 4.0, int = [[HEAD:[0-9]+]]
+  br i1 %x, label %left, label %right, !prof !4
+
+left:
+; CHECK-NEXT: left: float = 8.0,
+  br i1 %x, label %right, label %loop.end, !prof !5
+
+right:
+; CHECK-NEXT: right: float = 8.0,
+  br i1 %x, label %left, label %loop.end, !prof !5
+
+loop.end:
+; CHECK-NEXT: loop.end: float = 4.0, int = [[HEAD]]
+  br i1 %x, label %loop, label %exit, !prof !5
+
+exit:
+; CHECK-NEXT: exit: float = 1.0, int = [[ENTRY]]
+  ret void
+}
+!4 = metadata !{metadata !"branch_weights", i32 1, i32 1}
+!5 = metadata !{metadata !"branch_weights", i32 3, i32 1}
+
+; Two unrelated irreducible SCCs.
+define void @two_sccs(i1 %x) {
+; CHECK-LABEL: Printing analysis {{.*}} for function 'two_sccs':
+; CHECK-NEXT: block-frequency-info: two_sccs
+entry:
+; CHECK-NEXT: entry: float = 1.0, int = [[ENTRY:[0-9]+]]
+  br i1 %x, label %a, label %b, !prof !6
+
+a:
+; CHECK-NEXT: a: float = 0.75,
+  br i1 %x, label %a.left, label %a.right, !prof !7
+
+a.left:
+; CHECK-NEXT: a.left: float = 1.5,
+  br i1 %x, label %a.right, label %exit, !prof !6
+
+a.right:
+; CHECK-NEXT: a.right: float = 1.5,
+  br i1 %x, label %a.left, label %exit, !prof !6
+
+b:
+; CHECK-NEXT: b: float = 0.25,
+  br i1 %x, label %b.left, label %b.right, !prof !7
+
+b.left:
+; CHECK-NEXT: b.left: float = 0.625,
+  br i1 %x, label %b.right, label %exit, !prof !8
+
+b.right:
+; CHECK-NEXT: b.right: float = 0.625,
+  br i1 %x, label %b.left, label %exit, !prof !8
+
+exit:
+; CHECK-NEXT: exit: float = 1.0, int = [[ENTRY]]
+  ret void
+}
+!6 = metadata !{metadata !"branch_weights", i32 3, i32 1}
+!7 = metadata !{metadata !"branch_weights", i32 1, i32 1}
+!8 = metadata !{metadata !"branch_weights", i32 4, i32 1}
+
+; A true loop inside irreducible control flow.
+define void @loop_inside_irreducible(i1 %x) {
+; CHECK-LABEL: Printing analysis {{.*}} for function 'loop_inside_irreducible':
+; CHECK-NEXT: block-frequency-info: loop_inside_irreducible
+entry:
+; CHECK-NEXT: entry: float = 1.0, int = [[ENTRY:[0-9]+]]
+  br i1 %x, label %left, label %right, !prof !9
+
+left:
+; CHECK-NEXT: left: float = 2.0,
+  br i1 %x, label %right, label %exit, !prof !10
+
+right:
+; CHECK-NEXT: right: float = 2.0, int = [[RIGHT:[0-9]+]]
+  br label %loop
+
+loop:
+; CHECK-NEXT: loop: float = 6.0,
+  br i1 %x, label %loop, label %right.end, !prof !11
+
+right.end:
+; CHECK-NEXT: right.end: float = 2.0, int = [[RIGHT]]
+  br i1 %x, label %left, label %exit, !prof !10
+
+exit:
+; CHECK-NEXT: exit: float = 1.0, int = [[ENTRY]]
+  ret void
+}
+!9 = metadata !{metadata !"branch_weights", i32 1, i32 1}
+!10 = metadata !{metadata !"branch_weights", i32 3, i32 1}
+!11 = metadata !{metadata !"branch_weights", i32 2, i32 1}
+
+; Irreducible control flow in a branch that's in a true loop.
+define void @loop_around_branch_with_irreducible(i1 %x) {
+; CHECK-LABEL: Printing analysis {{.*}} for function 'loop_around_branch_with_irreducible':
+; CHECK-NEXT: block-frequency-info: loop_around_branch_with_irreducible
+entry:
 ; CHECK-NEXT: entry: float = 1.0, int = [[ENTRY:[0-9]+]]
+  br label %loop
+
+loop:
+; CHECK-NEXT: loop: float = 2.0, int = [[LOOP:[0-9]+]]
+  br i1 %x, label %normal, label %irreducible.entry, !prof !12
+
+normal:
+; CHECK-NEXT: normal: float = 1.5,
+  br label %loop.end
+
+irreducible.entry:
+; CHECK-NEXT: irreducible.entry: float = 0.5, int = [[IRREDUCIBLE:[0-9]+]]
+  br i1 %x, label %left, label %right, !prof !13
+
+left:
+; CHECK-NEXT: left: float = 1.0,
+  br i1 %x, label %right, label %irreducible.exit, !prof !12
+
+right:
+; CHECK-NEXT: right: float = 1.0,
+  br i1 %x, label %left, label %irreducible.exit, !prof !12
+
+irreducible.exit:
+; CHECK-NEXT: irreducible.exit: float = 0.5, int = [[IRREDUCIBLE]]
+  br label %loop.end
+
+loop.end:
+; CHECK-NEXT: loop.end: float = 2.0, int = [[LOOP]]
+  br i1 %x, label %loop, label %exit, !prof !13
+
+exit:
+; CHECK-NEXT: exit: float = 1.0, int = [[ENTRY]]
+  ret void
+}
+!12 = metadata !{metadata !"branch_weights", i32 3, i32 1}
+!13 = metadata !{metadata !"branch_weights", i32 1, i32 1}
+
+; Irreducible control flow between two true loops.
+define void @loop_around_branch_with_irreducible_around_loop(i1 %x) {
+; CHECK-LABEL: Printing analysis {{.*}} for function 'loop_around_branch_with_irreducible_around_loop':
+; CHECK-NEXT: block-frequency-info: loop_around_branch_with_irreducible_around_loop
 entry:
+; CHECK-NEXT: entry: float = 1.0, int = [[ENTRY:[0-9]+]]
   br label %loop
 
-; CHECK-NEXT: loop: float = [[HEAD:[0-9.]+]], int = [[HEADINT:[0-9]+]]
 loop:
-  br i1 %x, label %left, label %right
+; CHECK-NEXT: loop: float = 3.0, int = [[LOOP:[0-9]+]]
+  br i1 %x, label %normal, label %irreducible, !prof !14
+
+normal:
+; CHECK-NEXT: normal: float = 2.0,
+  br label %loop.end
+
+irreducible:
+; CHECK-NEXT: irreducible: float = 1.0,
+  br i1 %x, label %left, label %right, !prof !15
 
-; CHECK-NEXT: left:
 left:
-  br i1 %x, label %right, label %loop.end
+; CHECK-NEXT: left: float = 2.0,
+  br i1 %x, label %right, label %loop.end, !prof !16
 
-; CHECK-NEXT: right:
 right:
-  br i1 %x, label %left, label %loop.end
+; CHECK-NEXT: right: float = 2.0, int = [[RIGHT:[0-9]+]]
+  br label %right.loop
+
+right.loop:
+; CHECK-NEXT: right.loop: float = 10.0,
+  br i1 %x, label %right.loop, label %right.end, !prof !17
+
+right.end:
+; CHECK-NEXT: right.end: float = 2.0, int = [[RIGHT]]
+  br i1 %x, label %left, label %loop.end, !prof !16
 
-; CHECK-NEXT: loop.end: float = [[HEAD]], int = [[HEADINT]]
 loop.end:
-  br i1 %x, label %loop, label %exit
+; CHECK-NEXT: loop.end: float = 3.0, int = [[LOOP]]
+  br i1 %x, label %loop, label %exit, !prof !14
+
+exit:
+; CHECK-NEXT: exit: float = 1.0, int = [[ENTRY]]
+  ret void
+}
+!14 = metadata !{metadata !"branch_weights", i32 2, i32 1}
+!15 = metadata !{metadata !"branch_weights", i32 1, i32 1}
+!16 = metadata !{metadata !"branch_weights", i32 3, i32 1}
+!17 = metadata !{metadata !"branch_weights", i32 4, i32 1}
+
+; An irreducible SCC with a non-header.
+define void @nonheader(i1 %x) {
+; CHECK-LABEL: Printing analysis {{.*}} for function 'nonheader':
+; CHECK-NEXT: block-frequency-info: nonheader
+entry:
+; CHECK-NEXT: entry: float = 1.0, int = [[ENTRY:[0-9]+]]
+  br i1 %x, label %left, label %right, !prof !18
+
+left:
+; CHECK-NEXT: left: float = 1.0,
+  br i1 %x, label %bottom, label %exit, !prof !19
+
+right:
+; CHECK-NEXT: right: float = 1.0,
+  br i1 %x, label %bottom, label %exit, !prof !20
+
+bottom:
+; CHECK-NEXT: bottom: float = 1.0,
+  br i1 %x, label %left, label %right, !prof !18
 
-; CHECK-NEXT: float = 1.0, int = [[ENTRY]]
 exit:
+; CHECK-NEXT: exit: float = 1.0, int = [[ENTRY]]
+  ret void
+}
+!18 = metadata !{metadata !"branch_weights", i32 1, i32 1}
+!19 = metadata !{metadata !"branch_weights", i32 1, i32 3}
+!20 = metadata !{metadata !"branch_weights", i32 3, i32 1}
+
+; An irreducible SCC with an irreducible sub-SCC.  In the current version of
+; -block-freq, this means an extra header.
+;
+; This testcases uses non-trivial branch weights.  The CHECK statements here
+; will start to fail if we change -block-freq to be more accurate.  Currently,
+; we expect left, right and top to be treated as equal headers.
+define void @nonentry_header(i1 %x, i2 %y) {
+; CHECK-LABEL: Printing analysis {{.*}} for function 'nonentry_header':
+; CHECK-NEXT: block-frequency-info: nonentry_header
+entry:
+; CHECK-NEXT: entry: float = 1.0, int = [[ENTRY:[0-9]+]]
+  br i1 %x, label %left, label %right, !prof !21
+
+left:
+; CHECK-NEXT: left: float = 3.0,
+  br i1 %x, label %top, label %bottom, !prof !22
+
+right:
+; CHECK-NEXT: right: float = 3.0,
+  br i1 %x, label %top, label %bottom, !prof !22
+
+top:
+; CHECK-NEXT: top: float = 3.0,
+  switch i2 %y, label %exit [ i2 0, label %left
+                              i2 1, label %right
+                              i2 2, label %bottom ], !prof !23
+
+bottom:
+; CHECK-NEXT: bottom: float = 4.5,
+  br label %top
+
+exit:
+; CHECK-NEXT: exit: float = 1.0, int = [[ENTRY]]
   ret void
 }
+!21 = metadata !{metadata !"branch_weights", i32 2, i32 1}
+!22 = metadata !{metadata !"branch_weights", i32 1, i32 1}
+!23 = metadata !{metadata !"branch_weights", i32 8, i32 1, i32 3, i32 12}
diff --git a/test/CodeGen/AArch64/addsub.ll b/test/CodeGen/AArch64/addsub.ll
index f9c1cc0dd5..b64ad2a83d 100644
--- a/test/CodeGen/AArch64/addsub.ll
+++ b/test/CodeGen/AArch64/addsub.ll
@@ -87,7 +87,7 @@ define void @testing() {
 
 test2:
 ; CHECK: cmp {{w[0-9]+}}, {{#3567, lsl #12|#14610432}}
-; CHECK: b.{{cc|lo}} [[RET]]
+; CHECK: b.lo [[RET]]
   %newval2 = add i32 %val, 1
   store i32 %newval2, i32* @var_i32
   %cmp_pos_big = icmp ult i32 %val, 14610432
diff --git a/test/CodeGen/AArch64/alloca.ll b/test/CodeGen/AArch64/alloca.ll
index 5d7b6250d7..f73365b20c 100644
--- a/test/CodeGen/AArch64/alloca.ll
+++ b/test/CodeGen/AArch64/alloca.ll
@@ -136,7 +136,7 @@ define void @test_alloca_large_frame(i64 %n) {
 ; CHECK-ARM64: stp     x20, x19, [sp, #-32]!
 ; CHECK-ARM64: stp     x29, x30, [sp, #16]
 ; CHECK-ARM64: add     x29, sp, #16
-; CHECK-ARM64: sub     sp, sp, #7999488
+; CHECK-ARM64: sub     sp, sp, #1953, lsl #12
 ; CHECK-ARM64: sub     sp, sp, #512
 
   %addr1 = alloca i8, i64 %n
diff --git a/test/CodeGen/AArch64/cond-sel.ll b/test/CodeGen/AArch64/cond-sel.ll
index 8d6ec8605a..febb220466 100644
--- a/test/CodeGen/AArch64/cond-sel.ll
+++ b/test/CodeGen/AArch64/cond-sel.ll
@@ -12,8 +12,8 @@ define void @test_csel(i32 %lhs32, i32 %rhs32, i64 %lhs64) minsize {
   %tst1 = icmp ugt i32 %lhs32, %rhs32
   %val1 = select i1 %tst1, i32 42, i32 52
   store i32 %val1, i32* @var32
-; CHECK-DAG: movz [[W52:w[0-9]+]], #52
-; CHECK-DAG: movz [[W42:w[0-9]+]], #42
+; CHECK-DAG: movz [[W52:w[0-9]+]], #{{52|0x34}}
+; CHECK-DAG: movz [[W42:w[0-9]+]], #{{42|0x2a}}
 ; CHECK: csel {{w[0-9]+}}, [[W42]], [[W52]], hi
 
   %rhs64 = sext i32 %rhs32 to i64
@@ -36,8 +36,8 @@ define void @test_floatcsel(float %lhs32, float %rhs32, double %lhs64, double %r
 ; CHECK-NOFP-NOT: fcmp
   %val1 = select i1 %tst1, i32 42, i32 52
   store i32 %val1, i32* @var32
-; CHECK: movz [[W52:w[0-9]+]], #52
-; CHECK: movz [[W42:w[0-9]+]], #42
+; CHECK: movz [[W52:w[0-9]+]], #{{52|0x34}}
+; CHECK: movz [[W42:w[0-9]+]], #{{42|0x2a}}
 ; CHECK: csel [[MAYBETRUE:w[0-9]+]], [[W42]], [[W52]], mi
 ; CHECK: csel {{w[0-9]+}}, [[W42]], [[MAYBETRUE]], gt
 
@@ -49,7 +49,7 @@ define void @test_floatcsel(float %lhs32, float %rhs32, double %lhs64, double %r
   store i64 %val2, i64* @var64
 ; CHECK-AARCH64: movz x[[CONST15:[0-9]+]], #15
 ; CHECK-ARM64: orr w[[CONST15:[0-9]+]], wzr, #0xf
-; CHECK: movz {{[wx]}}[[CONST9:[0-9]+]], #9
+; CHECK: movz {{[wx]}}[[CONST9:[0-9]+]], #{{9|0x9}}
 ; CHECK: csel [[MAYBETRUE:x[0-9]+]], x[[CONST9]], x[[CONST15]], eq
 ; CHECK: csel {{x[0-9]+}}, x[[CONST9]], [[MAYBETRUE]], vs
 
diff --git a/test/CodeGen/AArch64/func-calls.ll b/test/CodeGen/AArch64/func-calls.ll
index 538cf0bb60..26c705700a 100644
--- a/test/CodeGen/AArch64/func-calls.ll
+++ b/test/CodeGen/AArch64/func-calls.ll
@@ -114,10 +114,10 @@ define void @check_stack_args() {
 ; CHECK-AARCH64: mov x0, sp
 ; CHECK-AARCH64: str d[[STACKEDREG]], [x0]
 
-; CHECK-ARM64:  movz [[SIXTY_FOUR:w[0-9]+]], #17024, lsl #16
+; CHECK-ARM64:  movz [[SIXTY_FOUR:w[0-9]+]], #0x4280, lsl #16
 ; CHECK-ARM64: str [[SIXTY_FOUR]], [sp]
 
-; CHECK-ARM64-NONEON:  movz [[SIXTY_FOUR:w[0-9]+]], #17024, lsl #16
+; CHECK-ARM64-NONEON:  movz [[SIXTY_FOUR:w[0-9]+]], #0x4280, lsl #16
 ; CHECK-ARM64-NONEON: str [[SIXTY_FOUR]], [sp]
 
 ; CHECK: bl stacked_fpu
diff --git a/test/CodeGen/AArch64/movw-consts.ll b/test/CodeGen/AArch64/movw-consts.ll
index e783b988b5..876eb52df6 100644
--- a/test/CodeGen/AArch64/movw-consts.ll
+++ b/test/CodeGen/AArch64/movw-consts.ll
@@ -61,7 +61,7 @@ define i64 @test7() {
 ; couldn't. Useful even for i64
 define i64 @test8() {
 ; CHECK-LABEL: test8:
-; CHECK: movn w0, #60875
+; CHECK: movn w0, #{{60875|0xedcb}}
   ret i64 4294906420
 }
 
@@ -73,7 +73,7 @@ define i64 @test9() {
 
 define i64 @test10() {
 ; CHECK-LABEL: test10:
-; CHECK: movn x0, #60875, lsl #16
+; CHECK: movn x0, #{{60875|0xedcb}}, lsl #16
   ret i64 18446744069720047615
 }
 
diff --git a/test/CodeGen/AArch64/neon-idiv.ll b/test/CodeGen/AArch64/neon-idiv.ll
new file mode 100644
index 0000000000..9c9758a81f
--- /dev/null
+++ b/test/CodeGen/AArch64/neon-idiv.ll
@@ -0,0 +1,14 @@
+; RUN: llc -mtriple=aarch64-none-linux-gnu < %s -mattr=+neon | FileCheck %s
+; RUN: llc -mtriple=arm64-none-linux-gnu < %s -mattr=+neon | FileCheck %s
+
+define <4 x i32> @test1(<4 x i32> %a) {
+  %rem = srem <4 x i32> %a, <i32 7, i32 7, i32 7, i32 7>
+  ret <4 x i32> %rem
+; CHECK-LABEL: test1
+; FIXME: Can we lower this more efficiently?
+; CHECK: mul
+; CHECK: mul
+; CHECK: mul
+; CHECK: mul
+}
+
diff --git a/test/CodeGen/AArch64/pic-eh-stubs.ll b/test/CodeGen/AArch64/pic-eh-stubs.ll
index 6a7788ddf4..399d1c1123 100644
--- a/test/CodeGen/AArch64/pic-eh-stubs.ll
+++ b/test/CodeGen/AArch64/pic-eh-stubs.ll
@@ -1,6 +1,7 @@
 ; RUN: llc -mtriple=aarch64-none-linux-gnu -relocation-model=pic -o - %s | FileCheck %s
 ; RUN: llc -mtriple=aarch64_be-none-linux-gnu -relocation-model=pic -o - %s | FileCheck %s
 ; RUN: llc -mtriple=arm64-none-linux-gnu -relocation-model=pic -o - %s | FileCheck %s
+; RUN: llc -mtriple=arm64_be-none-linux-gnu -relocation-model=pic -o - %s | FileCheck %s
 
 ; Make sure exception-handling PIC code can be linked correctly. An alternative
 ; to the sequence described below would have .gcc_except_table itself writable
diff --git a/test/CodeGen/ARM/Windows/chkstk.ll b/test/CodeGen/ARM/Windows/chkstk.ll
new file mode 100644
index 0000000000..9c58fa08d3
--- /dev/null
+++ b/test/CodeGen/ARM/Windows/chkstk.ll
@@ -0,0 +1,24 @@
+; RUN: llc -mtriple=thumbv7-windows -mcpu=cortex-a9 %s -o - \
+; RUN:  | FileCheck -check-prefix CHECK-DEFAULT-CODE-MODEL %s
+
+; RUN: llc -mtriple=thumbv7-windows -mcpu=cortex-a9 -code-model=large %s -o - \
+; RUN:  | FileCheck -check-prefix CHECK-LARGE-CODE-MODEL %s
+
+define arm_aapcs_vfpcc void @check_watermark() {
+entry:
+  %buffer = alloca [4096 x i8], align 1
+  ret void
+}
+
+; CHECK-DEFAULT-CODE-MODEL: check_watermark:
+; CHECK-DEFAULT-CODE-MODEL: 	movw r4, #1024
+; CHECK-DEFAULT-CODE-MODEL: 	bl __chkstk
+; CHECK-DEFAULT-CODE-MODEL: 	sub.w sp, sp, r4
+
+; CHECK-LARGE-CODE-MODEL: check_watermark:
+; CHECK-LARGE-CODE-MODEL: 	movw r4, #1024
+; CHECK-LARGE-CODE-MODEL: 	movw r12, :lower16:__chkstk
+; CHECK-LARGE-CODE-MODEL: 	movt r12, :upper16:__chkstk
+; CHECK-LARGE-CODE-MODEL: 	blx r12
+; CHECK-LARGE-CODE-MODEL: 	sub.w sp, sp, r4
+
diff --git a/test/CodeGen/ARM/Windows/movw-movt-relocations.ll b/test/CodeGen/ARM/Windows/movw-movt-relocations.ll
new file mode 100644
index 0000000000..3ae6428d3a
--- /dev/null
+++ b/test/CodeGen/ARM/Windows/movw-movt-relocations.ll
@@ -0,0 +1,27 @@
+; RUN: llc -mtriple=thumbv7-windows -o - %s \
+; RUN:   | FileCheck %s -check-prefix CHECK-WINDOWS
+
+; RUN: llc -mtriple=thumbv7-eabi -o - %s \
+; RUN:   | FileCheck %s -check-prefix CHECK-EABI
+
+@i = common global i32 0, align 4
+@j = common global i32 0, align 4
+
+; Function Attrs: nounwind optsize readonly
+define i32 @relocation(i32 %j, i32 %k) {
+entry:
+  %0 = load i32* @i, align 4
+  %1 = load i32* @j, align 4
+  %add = add nsw i32 %1, %0
+  ret i32 %add
+}
+
+; CHECK-WINDOWS: movw r[[i:[0-4]]], :lower16:i
+; CHECK-WINDOWS-NEXT: movt r[[i]], :upper16:i
+; CHECK-WINDOWS: movw r[[j:[0-4]]], :lower16:j
+; CHECK-WINDOWS-NEXT: movt r[[j]], :upper16:j
+
+; CHECK-EABI: movw r[[i:[0-4]]], :lower16:i
+; CHECK-EABI: movw r[[j:[0-4]]], :lower16:j
+; CHECK-EABI-NEXT: movt r[[i]], :upper16:i
+; CHECK-EABI-NEXT: movt r[[j]], :upper16:j
diff --git a/test/CodeGen/ARM/available_externally.ll b/test/CodeGen/ARM/available_externally.ll
index 0f646d582e..d925b5c777 100644
--- a/test/CodeGen/ARM/available_externally.ll
+++ b/test/CodeGen/ARM/available_externally.ll
@@ -11,6 +11,8 @@ define i32 @t1() {
 }
 
 ; CHECK:      L_A$non_lazy_ptr:
-; CHECK-NEXT: .long _A
+; CHECK-NEXT: .indirect_symbol _A
+; CHECK-NEXT: .long 0
 ; CHECK:      L_B$non_lazy_ptr:
-; CHECK-NEXT: .long _B
+; CHECK-NEXT: .indirect_symbol _B
+; CHECK-NEXT: .long 0
diff --git a/test/CodeGen/ARM/indirect-hidden.ll b/test/CodeGen/ARM/indirect-hidden.ll
new file mode 100644
index 0000000000..ae1c505bb6
--- /dev/null
+++ b/test/CodeGen/ARM/indirect-hidden.ll
@@ -0,0 +1,22 @@
+; RUN: llc -mtriple=thumbv7s-apple-ios7.0 -o - %s | FileCheck %s
+
+@var = external global i32
+@var_hidden = external hidden global i32
+
+define i32* @get_var() {
+  ret i32* @var
+}
+
+define i32* @get_var_hidden() {
+  ret i32* @var_hidden
+}
+
+; CHECK: .section __DATA,__nl_symbol_ptr,non_lazy_symbol_pointers
+
+; CHECK: .indirect_symbol _var
+; CHECK-NEXT: .long 0
+
+; CHECK-NOT: __DATA,__data
+
+; CHECK: .indirect_symbol _var_hidden
+; CHECK-NEXT: .long 0
\ No newline at end of file
diff --git a/test/CodeGen/ARM64/2011-10-18-LdStOptBug.ll b/test/CodeGen/ARM64/2011-10-18-LdStOptBug.ll
index ea1cd02ca2..8f99bc30a5 100644
--- a/test/CodeGen/ARM64/2011-10-18-LdStOptBug.ll
+++ b/test/CodeGen/ARM64/2011-10-18-LdStOptBug.ll
@@ -14,7 +14,7 @@ for.body:
 ; CHECK: for.body
 ; CHECK: ldr w{{[0-9]+}}, [x{{[0-9]+}}]
 ; CHECK: add x[[REG:[0-9]+]],
-; CHECK:                      x[[REG]], #4096
+; CHECK:                      x[[REG]], #1, lsl  #12
   %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
   %0 = shl nsw i64 %indvars.iv, 12
   %add = add nsw i64 %0, 34628173824
diff --git a/test/CodeGen/ARM64/2014-04-29-EXT-undef-mask.ll b/test/CodeGen/ARM64/2014-04-29-EXT-undef-mask.ll
new file mode 100644
index 0000000000..b0ab9fda22
--- /dev/null
+++ b/test/CodeGen/ARM64/2014-04-29-EXT-undef-mask.ll
@@ -0,0 +1,23 @@
+; RUN: llc < %s -O0 -march=arm64 -arm64-neon-syntax=apple | FileCheck %s
+
+; The following 2 test cases test shufflevector with beginning UNDEF mask.
+define <8 x i16> @test_vext_undef_traverse(<8 x i16> %in) {
+;CHECK-LABEL: test_vext_undef_traverse:
+;CHECK: {{ext.16b.*v0, #4}}
+  %vext = shufflevector <8 x i16> <i16 undef, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef, i16 0, i16 0>, <8 x i16> %in, <8 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 6, i32 7, i32 8, i32 9>
+  ret <8 x i16> %vext
+}
+
+define <8 x i16> @test_vext_undef_traverse2(<8 x i16> %in) {
+;CHECK-LABEL: test_vext_undef_traverse2:
+;CHECK: {{ext.16b.*v0, #6}}
+  %vext = shufflevector <8 x i16> %in, <8 x i16> <i16 undef, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef>, <8 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 0, i32 1, i32 2>
+  ret <8 x i16> %vext
+}
+
+define <8 x i8> @test_vext_undef_traverse3(<8 x i8> %in) {
+;CHECK-LABEL: test_vext_undef_traverse3:
+;CHECK: {{ext.8b.*v0, #6}}
+  %vext = shufflevector <8 x i8> %in, <8 x i8> <i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef>, <8 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 2, i32 3, i32 4, i32 5>
+  ret <8 x i8> %vext
+}
diff --git a/test/CodeGen/ARM64/aarch64-large-frame.ll b/test/CodeGen/ARM64/aarch64-large-frame.ll
index 011affa178..5a53da6938 100644
--- a/test/CodeGen/ARM64/aarch64-large-frame.ll
+++ b/test/CodeGen/ARM64/aarch64-large-frame.ll
@@ -11,23 +11,23 @@ define void @test_bigframe() {
   %var2 = alloca i8, i32 16
   %var3 = alloca i8, i32 20000000
 
-; CHECK: sub sp, sp, #16773120
-; CHECK: sub sp, sp, #16773120
-; CHECK: sub sp, sp, #6451200
+; CHECK: sub sp, sp, #4095, lsl #12
+; CHECK: sub sp, sp, #4095, lsl #12
+; CHECK: sub sp, sp, #1575, lsl #12
 ; CHECK: sub sp, sp, #2576
 ; CHECK: .cfi_def_cfa_offset 40000032
 
 
-; CHECK: add [[TMP:x[0-9]+]], sp, #16773120
-; CHECK: add [[TMP1:x[0-9]+]], [[TMP]], #3223552
+; CHECK: add [[TMP:x[0-9]+]], sp, #4095, lsl #12
+; CHECK: add [[TMP1:x[0-9]+]], [[TMP]], #787, lsl #12
 ; CHECK: add {{x[0-9]+}}, [[TMP1]], #3344
   store volatile i8* %var1, i8** @addr
 
   %var1plus2 = getelementptr i8* %var1, i32 2
   store volatile i8* %var1plus2, i8** @addr
 
-; CHECK: add [[TMP:x[0-9]+]], sp, #16773120
-; CHECK: add [[TMP1:x[0-9]+]], [[TMP]], #3223552
+; CHECK: add [[TMP:x[0-9]+]], sp, #4095, lsl #12
+; CHECK: add [[TMP1:x[0-9]+]], [[TMP]], #787, lsl #12
 ; CHECK: add {{x[0-9]+}}, [[TMP1]], #3328
   store volatile i8* %var2, i8** @addr
 
@@ -39,9 +39,9 @@ define void @test_bigframe() {
   %var3plus2 = getelementptr i8* %var3, i32 2
   store volatile i8* %var3plus2, i8** @addr
 
-; CHECK: add sp, sp, #16773120
-; CHECK: add sp, sp, #16773120
-; CHECK: add sp, sp, #6451200
+; CHECK: add sp, sp, #4095, lsl #12
+; CHECK: add sp, sp, #4095, lsl #12
+; CHECK: add sp, sp, #1575, lsl #12
 ; CHECK: add sp, sp, #2576
 ; CHECK: .cfi_endproc
   ret void
@@ -52,18 +52,18 @@ define void @test_mediumframe() {
   %var1 = alloca i8, i32 1000000
   %var2 = alloca i8, i32 16
   %var3 = alloca i8, i32 1000000
-; CHECK: sub sp, sp, #1998848
+; CHECK: sub sp, sp, #488, lsl #12
 ; CHECK-NEXT: sub sp, sp, #1168
 
   store volatile i8* %var1, i8** @addr
-; CHECK: add     [[VAR1ADDR:x[0-9]+]], sp, #999424
+; CHECK: add     [[VAR1ADDR:x[0-9]+]], sp, #244, lsl #12
 ; CHECK: add     [[VAR1ADDR]], [[VAR1ADDR]], #592
 
-; CHECK: add [[VAR2ADDR:x[0-9]+]], sp, #999424
+; CHECK: add [[VAR2ADDR:x[0-9]+]], sp, #244, lsl #12
 ; CHECK: add [[VAR2ADDR]], [[VAR2ADDR]], #576
 
   store volatile i8* %var2, i8** @addr
-; CHECK: add     sp, sp, #1998848
+; CHECK: add     sp, sp, #488, lsl #12
 ; CHECK: add     sp, sp, #1168
   ret void
 }
diff --git a/test/CodeGen/ARM64/aarch64-neon-copy.ll b/test/CodeGen/ARM64/aarch64-neon-copy.ll
index ce851525da..3b4cc6cc4f 100644
--- a/test/CodeGen/ARM64/aarch64-neon-copy.ll
+++ b/test/CodeGen/ARM64/aarch64-neon-copy.ll
@@ -1369,7 +1369,7 @@ define <4 x i16> @concat_vector_v4i16_const() {
 
 define <4 x i16> @concat_vector_v4i16_const_one() {
 ; CHECK-LABEL: concat_vector_v4i16_const_one:
-; CHECK: movi {{v[0-9]+}}.4h, #1
+; CHECK: movi {{v[0-9]+}}.4h, #0x1
  %r = shufflevector <1 x i16> <i16 1>, <1 x i16> undef, <4 x i32> zeroinitializer
  ret <4 x i16> %r
 }
@@ -1397,7 +1397,7 @@ define <8 x i16> @concat_vector_v8i16_const() {
 
 define <8 x i16> @concat_vector_v8i16_const_one() {
 ; CHECK-LABEL: concat_vector_v8i16_const_one:
-; CHECK: movi {{v[0-9]+}}.8h, #1
+; CHECK: movi {{v[0-9]+}}.8h, #0x1
  %r = shufflevector <1 x i16> <i16 1>, <1 x i16> undef, <8 x i32> zeroinitializer
  ret <8 x i16> %r
 }
diff --git a/test/CodeGen/ARM64/abi_align.ll b/test/CodeGen/ARM64/abi_align.ll
index d8ec3958ba..13a2a394f3 100644
--- a/test/CodeGen/ARM64/abi_align.ll
+++ b/test/CodeGen/ARM64/abi_align.ll
@@ -74,7 +74,7 @@ define i32 @caller38_stack() #1 {
 entry:
 ; CHECK: caller38_stack
 ; CHECK: stp {{x[0-9]+}}, {{x[0-9]+}}, [sp, #8]
-; CHECK: movz w[[C:[0-9]+]], #9
+; CHECK: movz w[[C:[0-9]+]], #0x9
 ; CHECK: str w[[C]], [sp]
   %0 = load i64* bitcast (%struct.s38* @g38 to i64*), align 4
   %1 = load i64* bitcast (%struct.s38* @g38_2 to i64*), align 4
@@ -128,7 +128,7 @@ entry:
 ; CHECK: caller39_stack
 ; CHECK: stp {{x[0-9]+}}, {{x[0-9]+}}, [sp, #32]
 ; CHECK: stp {{x[0-9]+}}, {{x[0-9]+}}, [sp, #16]
-; CHECK: movz w[[C:[0-9]+]], #9
+; CHECK: movz w[[C:[0-9]+]], #0x9
 ; CHECK: str w[[C]], [sp]
   %0 = load i128* bitcast (%struct.s39* @g39 to i128*), align 16
   %1 = load i128* bitcast (%struct.s39* @g39_2 to i128*), align 16
@@ -184,7 +184,7 @@ entry:
 ; CHECK: caller40_stack
 ; CHECK: stp {{x[0-9]+}}, {{x[0-9]+}}, [sp, #24]
 ; CHECK: stp {{x[0-9]+}}, {{x[0-9]+}}, [sp, #8]
-; CHECK: movz w[[C:[0-9]+]], #9
+; CHECK: movz w[[C:[0-9]+]], #0x9
 ; CHECK: str w[[C]], [sp]
   %0 = load [2 x i64]* bitcast (%struct.s40* @g40 to [2 x i64]*), align 4
   %1 = load [2 x i64]* bitcast (%struct.s40* @g40_2 to [2 x i64]*), align 4
@@ -238,7 +238,7 @@ entry:
 ; CHECK: caller41_stack
 ; CHECK: stp {{x[0-9]+}}, {{x[0-9]+}}, [sp, #32]
 ; CHECK: stp {{x[0-9]+}}, {{x[0-9]+}}, [sp, #16]
-; CHECK: movz w[[C:[0-9]+]], #9
+; CHECK: movz w[[C:[0-9]+]], #0x9
 ; CHECK: str w[[C]], [sp]
   %0 = load i128* bitcast (%struct.s41* @g41 to i128*), align 16
   %1 = load i128* bitcast (%struct.s41* @g41_2 to i128*), align 16
@@ -330,7 +330,7 @@ entry:
 ; CHECK: sub x[[A:[0-9]+]], x29, #32
 ; Address of s1 is passed on stack at sp+8
 ; CHECK: str x[[A]], [sp, #8]
-; CHECK: movz w[[C:[0-9]+]], #9
+; CHECK: movz w[[C:[0-9]+]], #0x9
 ; CHECK: str w[[C]], [sp]
 
 ; FAST: caller42_stack
@@ -442,7 +442,7 @@ entry:
 ; CHECK: sub x[[A:[0-9]+]], x29, #32
 ; Address of s1 is passed on stack at sp+8
 ; CHECK: str x[[A]], [sp, #8]
-; CHECK: movz w[[C:[0-9]+]], #9
+; CHECK: movz w[[C:[0-9]+]], #0x9
 ; CHECK: str w[[C]], [sp]
 
 ; FAST: caller43_stack
diff --git a/test/CodeGen/ARM64/addrmode.ll b/test/CodeGen/ARM64/addrmode.ll
index e1312376e2..700fba8014 100644
--- a/test/CodeGen/ARM64/addrmode.ll
+++ b/test/CodeGen/ARM64/addrmode.ll
@@ -37,7 +37,7 @@ define void @t3() {
 
 ; base + unsigned offset (> imm12 * size of type in bytes)
 ; CHECK: @t4
-; CHECK: add [[ADDREG:x[0-9]+]], x{{[0-9]+}}, #32768
+; CHECK: add [[ADDREG:x[0-9]+]], x{{[0-9]+}}, #8, lsl #12
 ; CHECK: ldr xzr, [
 ; CHECK: [[ADDREG]]]
 ; CHECK: ret
@@ -60,7 +60,7 @@ define void @t5(i64 %a) {
 ; base + reg + imm
 ; CHECK: @t6
 ; CHECK: add [[ADDREG:x[0-9]+]], x{{[0-9]+}}, x{{[0-9]+}}, lsl #3
-; CHECK-NEXT: add [[ADDREG]], [[ADDREG]], #32768
+; CHECK-NEXT: add [[ADDREG]], [[ADDREG]], #8, lsl #12
 ; CHECK: ldr xzr, [
 ; CHECK: [[ADDREG]]]
 ; CHECK: ret
diff --git a/test/CodeGen/ARM64/arith.ll b/test/CodeGen/ARM64/arith.ll
index db528f7601..803af6cb8c 100644
--- a/test/CodeGen/ARM64/arith.ll
+++ b/test/CodeGen/ARM64/arith.ll
@@ -48,7 +48,7 @@ entry:
 define i32 @t6(i32 %a, i32 %b) nounwind readnone ssp {
 entry:
 ; CHECK-LABEL: t6:
-; CHECK: lslv w0, w0, w1
+; CHECK: lsl w0, w0, w1
 ; CHECK: ret
   %shl = shl i32 %a, %b
   ret i32 %shl
@@ -57,7 +57,7 @@ entry:
 define i64 @t7(i64 %a, i64 %b) nounwind readnone ssp {
 entry:
 ; CHECK-LABEL: t7:
-; CHECK: lslv x0, x0, x1
+; CHECK: lsl x0, x0, x1
 ; CHECK: ret
   %shl = shl i64 %a, %b
   ret i64 %shl
@@ -66,7 +66,7 @@ entry:
 define i32 @t8(i32 %a, i32 %b) nounwind readnone ssp {
 entry:
 ; CHECK-LABEL: t8:
-; CHECK: lsrv w0, w0, w1
+; CHECK: lsr w0, w0, w1
 ; CHECK: ret
   %lshr = lshr i32 %a, %b
   ret i32 %lshr
@@ -75,7 +75,7 @@ entry:
 define i64 @t9(i64 %a, i64 %b) nounwind readnone ssp {
 entry:
 ; CHECK-LABEL: t9:
-; CHECK: lsrv x0, x0, x1
+; CHECK: lsr x0, x0, x1
 ; CHECK: ret
   %lshr = lshr i64 %a, %b
   ret i64 %lshr
@@ -84,7 +84,7 @@ entry:
 define i32 @t10(i32 %a, i32 %b) nounwind readnone ssp {
 entry:
 ; CHECK-LABEL: t10:
-; CHECK: asrv w0, w0, w1
+; CHECK: asr w0, w0, w1
 ; CHECK: ret
   %ashr = ashr i32 %a, %b
   ret i32 %ashr
@@ -93,7 +93,7 @@ entry:
 define i64 @t11(i64 %a, i64 %b) nounwind readnone ssp {
 entry:
 ; CHECK-LABEL: t11:
-; CHECK: asrv x0, x0, x1
+; CHECK: asr x0, x0, x1
 ; CHECK: ret
   %ashr = ashr i64 %a, %b
   ret i64 %ashr
diff --git a/test/CodeGen/ARM64/atomic.ll b/test/CodeGen/ARM64/atomic.ll
index dbdc95c428..aa9b284410 100644
--- a/test/CodeGen/ARM64/atomic.ll
+++ b/test/CodeGen/ARM64/atomic.ll
@@ -57,7 +57,7 @@ define i64 @fetch_and_nand_64(i64* %p) {
 
 define i32 @fetch_and_or(i32* %p) {
 ; CHECK-LABEL: fetch_and_or:
-; CHECK: movz   [[OLDVAL_REG:w[0-9]+]], #5
+; CHECK: movz   [[OLDVAL_REG:w[0-9]+]], #0x5
 ; CHECK: [[LABEL:.?LBB[0-9]+_[0-9]+]]:
 ; CHECK: ldaxr   w[[DEST_REG:[0-9]+]], [x0]
 ; CHECK: orr    [[SCRATCH2_REG:w[0-9]+]], w[[DEST_REG]], [[OLDVAL_REG]]
@@ -128,7 +128,7 @@ define i8 @atomic_load_relaxed_8(i8* %p, i32 %off32) {
   %ptr_random = getelementptr i8* %p, i32 1191936 ; 0x123000 (i.e. ADD imm)
   %val_random = load atomic i8* %ptr_random unordered, align 1
   %tot3 = add i8 %tot2, %val_random
-; CHECK: add x[[ADDR:[0-9]+]], x0, #1191936
+; CHECK: add x[[ADDR:[0-9]+]], x0, #291, lsl #12
 ; CHECK: ldrb {{w[0-9]+}}, [x[[ADDR]]]
 
   ret i8 %tot3
@@ -153,7 +153,7 @@ define i16 @atomic_load_relaxed_16(i16* %p, i32 %off32) {
   %ptr_random = getelementptr i16* %p, i32 595968 ; 0x123000/2 (i.e. ADD imm)
   %val_random = load atomic i16* %ptr_random unordered, align 2
   %tot3 = add i16 %tot2, %val_random
-; CHECK: add x[[ADDR:[0-9]+]], x0, #1191936
+; CHECK: add x[[ADDR:[0-9]+]], x0, #291, lsl #12
 ; CHECK: ldrh {{w[0-9]+}}, [x[[ADDR]]]
 
   ret i16 %tot3
@@ -178,7 +178,7 @@ define i32 @atomic_load_relaxed_32(i32* %p, i32 %off32) {
   %ptr_random = getelementptr i32* %p, i32 297984 ; 0x123000/4 (i.e. ADD imm)
   %val_random = load atomic i32* %ptr_random unordered, align 4
   %tot3 = add i32 %tot2, %val_random
-; CHECK: add x[[ADDR:[0-9]+]], x0, #1191936
+; CHECK: add x[[ADDR:[0-9]+]], x0, #291, lsl #12
 ; CHECK: ldr {{w[0-9]+}}, [x[[ADDR]]]
 
   ret i32 %tot3
@@ -203,7 +203,7 @@ define i64 @atomic_load_relaxed_64(i64* %p, i32 %off32) {
   %ptr_random = getelementptr i64* %p, i32 148992 ; 0x123000/8 (i.e. ADD imm)
   %val_random = load atomic i64* %ptr_random unordered, align 8
   %tot3 = add i64 %tot2, %val_random
-; CHECK: add x[[ADDR:[0-9]+]], x0, #1191936
+; CHECK: add x[[ADDR:[0-9]+]], x0, #291, lsl #12
 ; CHECK: ldr {{x[0-9]+}}, [x[[ADDR]]]
 
   ret i64 %tot3
@@ -233,7 +233,7 @@ define void @atomic_store_relaxed_8(i8* %p, i32 %off32, i8 %val) {
 
   %ptr_random = getelementptr i8* %p, i32 1191936 ; 0x123000 (i.e. ADD imm)
   store atomic i8 %val, i8* %ptr_random unordered, align 1
-; CHECK: add x[[ADDR:[0-9]+]], x0, #1191936
+; CHECK: add x[[ADDR:[0-9]+]], x0, #291, lsl #12
 ; CHECK: strb {{w[0-9]+}}, [x[[ADDR]]]
 
   ret void
@@ -255,7 +255,7 @@ define void @atomic_store_relaxed_16(i16* %p, i32 %off32, i16 %val) {
 
   %ptr_random = getelementptr i16* %p, i32 595968 ; 0x123000/2 (i.e. ADD imm)
   store atomic i16 %val, i16* %ptr_random unordered, align 2
-; CHECK: add x[[ADDR:[0-9]+]], x0, #1191936
+; CHECK: add x[[ADDR:[0-9]+]], x0, #291, lsl #12
 ; CHECK: strh {{w[0-9]+}}, [x[[ADDR]]]
 
   ret void
@@ -277,7 +277,7 @@ define void @atomic_store_relaxed_32(i32* %p, i32 %off32, i32 %val) {
 
   %ptr_random = getelementptr i32* %p, i32 297984 ; 0x123000/4 (i.e. ADD imm)
   store atomic i32 %val, i32* %ptr_random unordered, align 4
-; CHECK: add x[[ADDR:[0-9]+]], x0, #1191936
+; CHECK: add x[[ADDR:[0-9]+]], x0, #291, lsl #12
 ; CHECK: str {{w[0-9]+}}, [x[[ADDR]]]
 
   ret void
@@ -299,7 +299,7 @@ define void @atomic_store_relaxed_64(i64* %p, i32 %off32, i64 %val) {
 
   %ptr_random = getelementptr i64* %p, i32 148992 ; 0x123000/8 (i.e. ADD imm)
   store atomic i64 %val, i64* %ptr_random unordered, align 8
-; CHECK: add x[[ADDR:[0-9]+]], x0, #1191936
+; CHECK: add x[[ADDR:[0-9]+]], x0, #291, lsl #12
 ; CHECK: str {{x[0-9]+}}, [x[[ADDR]]]
 
   ret void
diff --git a/test/CodeGen/ARM64/big-stack.ll b/test/CodeGen/ARM64/big-stack.ll
index 56ca30c17b..3f91bb3c24 100644
--- a/test/CodeGen/ARM64/big-stack.ll
+++ b/test/CodeGen/ARM64/big-stack.ll
@@ -7,9 +7,9 @@ target triple = "arm64-apple-macosx10"
 ; shift left (up to 12). I.e., 16773120 is the biggest value.
 ; <rdar://12513931>
 ; CHECK-LABEL: foo:
-; CHECK: sub sp, sp, #16773120
-; CHECK: sub sp, sp, #16773120
-; CHECK: sub sp, sp, #8192
+; CHECK: sub sp, sp, #4095, lsl #12
+; CHECK: sub sp, sp, #4095, lsl #12
+; CHECK: sub sp, sp, #2, lsl #12
 define void @foo() nounwind ssp {
 entry:
   %buffer = alloca [33554432 x i8], align 1
diff --git a/test/CodeGen/ARM64/bitfield-extract.ll b/test/CodeGen/ARM64/bitfield-extract.ll
index 143aebc577..6de563c1eb 100644
--- a/test/CodeGen/ARM64/bitfield-extract.ll
+++ b/test/CodeGen/ARM64/bitfield-extract.ll
@@ -348,8 +348,8 @@ entry:
 ; CHECK-LABEL: fct16:
 ; CHECK: ldr [[REG1:w[0-9]+]],
 ; Create the constant
-; CHECK: movz [[REGCST:w[0-9]+]], #26, lsl #16
-; CHECK: movk [[REGCST]], #33120
+; CHECK: movz [[REGCST:w[0-9]+]], #0x1a, lsl #16
+; CHECK: movk [[REGCST]], #0x8160
 ; Do the masking
 ; CHECK: and [[REG2:w[0-9]+]], [[REG1]], [[REGCST]]
 ; CHECK-NEXT: bfm [[REG2]], w1, #16, #18
@@ -377,8 +377,8 @@ entry:
 ; CHECK-LABEL: fct17:
 ; CHECK: ldr [[REG1:x[0-9]+]],
 ; Create the constant
-; CHECK: movz w[[REGCST:[0-9]+]], #26, lsl #16
-; CHECK: movk w[[REGCST]], #33120
+; CHECK: movz w[[REGCST:[0-9]+]], #0x1a, lsl #16
+; CHECK: movk w[[REGCST]], #0x8160
 ; Do the masking
 ; CHECK: and [[REG2:x[0-9]+]], [[REG1]], x[[REGCST]]
 ; CHECK-NEXT: bfm [[REG2]], x1, #16, #18
diff --git a/test/CodeGen/ARM64/const-addr.ll b/test/CodeGen/ARM64/const-addr.ll
index 977628a092..c55a9226cc 100644
--- a/test/CodeGen/ARM64/const-addr.ll
+++ b/test/CodeGen/ARM64/const-addr.ll
@@ -5,8 +5,8 @@
 ; Test if the constant base address gets only materialized once.
 define i32 @test1() nounwind {
 ; CHECK-LABEL:  test1
-; CHECK:        movz  w8, #1039, lsl #16
-; CHECK-NEXT:   movk  w8, #49152
+; CHECK:        movz  w8, #0x40f, lsl #16
+; CHECK-NEXT:   movk  w8, #0xc000
 ; CHECK-NEXT:   ldp w9, w10, [x8, #4]
 ; CHECK:        ldr w8, [x8, #12]
   %at = inttoptr i64 68141056 to %T*
diff --git a/test/CodeGen/ARM64/dead-def-frame-index.ll b/test/CodeGen/ARM64/dead-def-frame-index.ll
index 4f8cc859ee..9bb4b71207 100644
--- a/test/CodeGen/ARM64/dead-def-frame-index.ll
+++ b/test/CodeGen/ARM64/dead-def-frame-index.ll
@@ -13,6 +13,6 @@ define i32 @test1() #0 {
   ret i32 %tmp4
 
   ; CHECK-LABEL: test1
-  ; CHECK:   adds [[TEMP:[a-z0-9]+]], sp, #16384
+  ; CHECK:   adds [[TEMP:[a-z0-9]+]], sp, #4, lsl #12
   ; CHECK:   adds [[TEMP]], [[TEMP]], #15
 }
diff --git a/test/CodeGen/ARM64/ext.ll b/test/CodeGen/ARM64/ext.ll
index 57d6e0c67b..d368eef172 100644
--- a/test/CodeGen/ARM64/ext.ll
+++ b/test/CodeGen/ARM64/ext.ll
@@ -65,6 +65,15 @@ define <8 x i8> @test_vextd_undef(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 	ret <8 x i8> %tmp3
 }
 
+define <8 x i8> @test_vextd_undef2(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+;CHECK-LABEL: test_vextd_undef2:
+;CHECK: {{ext.8b.*#6}}
+  %tmp1 = load <8 x i8>* %A
+  %tmp2 = load <8 x i8>* %B
+  %tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 2, i32 3, i32 4, i32 5>
+  ret <8 x i8> %tmp3
+}
+
 define <16 x i8> @test_vextRq_undef(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 ;CHECK-LABEL: test_vextRq_undef:
 ;CHECK: {{ext.16b.*#7}}
@@ -74,6 +83,14 @@ define <16 x i8> @test_vextRq_undef(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 	ret <16 x i8> %tmp3
 }
 
+define <8 x i16> @test_vextRq_undef2(<8 x i16>* %A) nounwind {
+;CHECK-LABEL: test_vextRq_undef2:
+;CHECK: {{ext.16b.*#10}}
+  %tmp1 = load <8 x i16>* %A
+  %vext = shufflevector <8 x i16> %tmp1, <8 x i16> undef, <8 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 1, i32 2, i32 3, i32 4>
+  ret <8 x i16> %vext;
+}
+
 ; Tests for ReconstructShuffle function. Indices have to be carefully
 ; chosen to reach lowering phase as a BUILD_VECTOR.
 
diff --git a/test/CodeGen/ARM64/fast-isel-addr-offset.ll b/test/CodeGen/ARM64/fast-isel-addr-offset.ll
index a4326dc2b8..ebd847e0f7 100644
--- a/test/CodeGen/ARM64/fast-isel-addr-offset.ll
+++ b/test/CodeGen/ARM64/fast-isel-addr-offset.ll
@@ -9,7 +9,7 @@ entry:
 ; CHECK: @foo
 ; CHECK: adrp x[[REG:[0-9]+]], _sortlist@GOTPAGE
 ; CHECK: ldr x[[REG1:[0-9]+]], [x[[REG]], _sortlist@GOTPAGEOFF]
-; CHECK: movz x[[REG2:[0-9]+]], #20000
+; CHECK: movz x[[REG2:[0-9]+]], #0x4e20
 ; CHECK: add x[[REG3:[0-9]+]], x[[REG1]], x[[REG2]]
 ; CHECK: ldr w0, [x[[REG3]]]
 ; CHECK: ret
@@ -22,7 +22,7 @@ entry:
 ; CHECK: @foo2
 ; CHECK: adrp x[[REG:[0-9]+]], _sortlist2@GOTPAGE
 ; CHECK: ldr x[[REG1:[0-9]+]], [x[[REG]], _sortlist2@GOTPAGEOFF]
-; CHECK: movz x[[REG2:[0-9]+]], #40000
+; CHECK: movz x[[REG2:[0-9]+]], #0x9c40
 ; CHECK: add x[[REG3:[0-9]+]], x[[REG1]], x[[REG2]]
 ; CHECK: ldr x0, [x[[REG3]]]
 ; CHECK: ret
@@ -37,9 +37,9 @@ entry:
 define signext i8 @foo3() nounwind ssp {
 entry:
 ; CHECK: @foo3
-; CHECK: movz x[[REG:[0-9]+]], #2874, lsl #32
-; CHECK: movk x[[REG]], #29646, lsl #16
-; CHECK: movk x[[REG]], #12274
+; CHECK: movz x[[REG:[0-9]+]], #0xb3a, lsl #32
+; CHECK: movk x[[REG]], #0x73ce, lsl #16
+; CHECK: movk x[[REG]], #0x2ff2
   %0 = load i8** @pd2, align 8
   %arrayidx = getelementptr inbounds i8* %0, i64 12345678901234
   %1 = load i8* %arrayidx, align 1
diff --git a/test/CodeGen/ARM64/fast-isel-conversion.ll b/test/CodeGen/ARM64/fast-isel-conversion.ll
index cf1dd86569..067979dd3d 100644
--- a/test/CodeGen/ARM64/fast-isel-conversion.ll
+++ b/test/CodeGen/ARM64/fast-isel-conversion.ll
@@ -57,7 +57,8 @@ entry:
 ; CHECK: uxth w0, w0
 ; CHECK: str w0, [sp, #8]
 ; CHECK: ldr w0, [sp, #8]
-; CHECK: ubfx x3, w0, #0, #32
+; CHECK: mov x3, x0
+; CHECK: ubfx x3, x3, #0, #32
 ; CHECK: str x3, [sp]
 ; CHECK: ldr x0, [sp], #16
 ; CHECK: ret
@@ -113,7 +114,8 @@ entry:
 ; CHECK: sxth w0, w0
 ; CHECK: str w0, [sp, #8]
 ; CHECK: ldr w0, [sp, #8]
-; CHECK: sxtw x3, w0
+; CHECK: mov x3, x0
+; CHECK: sxtw x3, w3
 ; CHECK: str x3, [sp]
 ; CHECK: ldr x0, [sp], #16
 ; CHECK: ret
@@ -139,12 +141,21 @@ entry:
 }
 
 ; Test sext i8 to i64
-define i64 @sext_2(i8 signext %a) nounwind ssp {
-entry:
-; CHECK: sext_2
-; CHECK: sxtb x0, w0
-  %conv = sext i8 %a to i64
-  ret i64 %conv
+
+define zeroext i64 @sext_i8_i64(i8 zeroext %in) {
+; CHECK-LABEL: sext_i8_i64:
+; CHECK: mov x[[TMP:[0-9]+]], x0
+; CHECK: sxtb x0, w[[TMP]]
+  %big = sext i8 %in to i64
+  ret i64 %big
+}
+
+define zeroext i64 @sext_i16_i64(i16 zeroext %in) {
+; CHECK-LABEL: sext_i16_i64:
+; CHECK: mov x[[TMP:[0-9]+]], x0
+; CHECK: sxth x0, w[[TMP]]
+  %big = sext i16 %in to i64
+  ret i64 %big
 }
 
 ; Test sext i1 to i32
@@ -414,3 +425,18 @@ define void @stack_trunc() nounwind {
   store i8 %d, i8* %a, align 1
   ret void
 }
+
+define zeroext i64 @zext_i8_i64(i8 zeroext %in) {
+; CHECK-LABEL: zext_i8_i64:
+; CHECK: mov x[[TMP:[0-9]+]], x0
+; CHECK: ubfx x0, x[[TMP]], #0, #8
+  %big = zext i8 %in to i64
+  ret i64 %big
+}
+define zeroext i64 @zext_i16_i64(i16 zeroext %in) {
+; CHECK-LABEL: zext_i16_i64:
+; CHECK: mov x[[TMP:[0-9]+]], x0
+; CHECK: ubfx x0, x[[TMP]], #0, #16
+  %big = zext i16 %in to i64
+  ret i64 %big
+}
diff --git a/test/CodeGen/ARM64/fast-isel-gv.ll b/test/CodeGen/ARM64/fast-isel-gv.ll
index cb3df1412c..dc4d8953c2 100644
--- a/test/CodeGen/ARM64/fast-isel-gv.ll
+++ b/test/CodeGen/ARM64/fast-isel-gv.ll
@@ -18,10 +18,10 @@ entry:
 ; CHECK: @Rand
 ; CHECK: adrp x[[REG:[0-9]+]], _seed@GOTPAGE
 ; CHECK: ldr x[[REG2:[0-9]+]], [x[[REG]], _seed@GOTPAGEOFF]
-; CHECK: movz x[[REG3:[0-9]+]], #1309
+; CHECK: movz x[[REG3:[0-9]+]], #0x51d
 ; CHECK: ldr x[[REG4:[0-9]+]], [x[[REG2]]]
 ; CHECK: mul x[[REG5:[0-9]+]], x[[REG4]], x[[REG3]]
-; CHECK: movz x[[REG6:[0-9]+]], #13849
+; CHECK: movz x[[REG6:[0-9]+]], #0x3619
 ; CHECK: add x[[REG7:[0-9]+]], x[[REG5]], x[[REG6]]
 ; CHECK: orr x[[REG8:[0-9]+]], xzr, #0xffff
 ; CHECK: and x[[REG9:[0-9]+]], x[[REG7]], x[[REG8]]
diff --git a/test/CodeGen/ARM64/fast-isel-icmp.ll b/test/CodeGen/ARM64/fast-isel-icmp.ll
index 22af5428d9..68a76c9e3e 100644
--- a/test/CodeGen/ARM64/fast-isel-icmp.ll
+++ b/test/CodeGen/ARM64/fast-isel-icmp.ll
@@ -54,7 +54,7 @@ define i32 @icmp_uge(i32 %a, i32 %b) nounwind ssp {
 entry:
 ; CHECK: icmp_uge
 ; CHECK: cmp  w0, w1
-; CHECK: csinc w0, wzr, wzr, cc
+; CHECK: csinc w0, wzr, wzr, lo
   %cmp = icmp uge i32 %a, %b
   %conv = zext i1 %cmp to i32
   ret i32 %conv
@@ -64,7 +64,7 @@ define i32 @icmp_ult(i32 %a, i32 %b) nounwind ssp {
 entry:
 ; CHECK: icmp_ult
 ; CHECK: cmp  w0, w1
-; CHECK: csinc w0, wzr, wzr, cs
+; CHECK: csinc w0, wzr, wzr, hs
   %cmp = icmp ult i32 %a, %b
   %conv = zext i1 %cmp to i32
   ret i32 %conv
@@ -158,7 +158,7 @@ entry:
 ; CHECK: uxth w0, w0
 ; CHECK: uxth w1, w1
 ; CHECK: cmp  w0, w1
-; CHECK: csinc w0, wzr, wzr, cs
+; CHECK: csinc w0, wzr, wzr, hs
   %cmp = icmp ult i16 %a, %b
   %conv2 = zext i1 %cmp to i32
   ret i32 %conv2
@@ -206,7 +206,7 @@ entry:
 ; CHECK: icmp_i1_unsigned_const
 ; CHECK: and w0, w0, #0x1
 ; CHECK: cmp  w0, #0
-; CHECK: csinc w0, wzr, wzr, cs
+; CHECK: csinc w0, wzr, wzr, hs
 ; CHECK: and w0, w0, #0x1
   %cmp = icmp ult i1 %a, 0
   %conv2 = zext i1 %cmp to i32
diff --git a/test/CodeGen/ARM64/fast-isel-intrinsic.ll b/test/CodeGen/ARM64/fast-isel-intrinsic.ll
index 6443d82e2c..a3d5f6c3c5 100644
--- a/test/CodeGen/ARM64/fast-isel-intrinsic.ll
+++ b/test/CodeGen/ARM64/fast-isel-intrinsic.ll
@@ -4,11 +4,11 @@
 @temp = common global [80 x i8] zeroinitializer, align 16
 
 define void @t1() {
-; ARM64: t1
+; ARM64-LABEL: t1
 ; ARM64: adrp x8, _message@PAGE
 ; ARM64: add x0, x8, _message@PAGEOFF
 ; ARM64: movz w9, #0
-; ARM64: movz x2, #80
+; ARM64: movz x2, #0x50
 ; ARM64: uxtb w1, w9
 ; ARM64: bl _memset
   call void @llvm.memset.p0i8.i64(i8* getelementptr inbounds ([80 x i8]* @message, i32 0, i32 0), i8 0, i64 80, i32 16, i1 false)
@@ -18,12 +18,12 @@ define void @t1() {
 declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i32, i1)
 
 define void @t2() {
-; ARM64: t2
+; ARM64-LABEL: t2
 ; ARM64: adrp x8, _temp@GOTPAGE
 ; ARM64: ldr x0, [x8, _temp@GOTPAGEOFF]
 ; ARM64: adrp x8, _message@PAGE
 ; ARM64: add x1, x8, _message@PAGEOFF
-; ARM64: movz x2, #80
+; ARM64: movz x2, #0x50
 ; ARM64: bl _memcpy
   call void @llvm.memcpy.p0i8.p0i8.i64(i8* getelementptr inbounds ([80 x i8]* @temp, i32 0, i32 0), i8* getelementptr inbounds ([80 x i8]* @message, i32 0, i32 0), i64 80, i32 16, i1 false)
   ret void
@@ -32,12 +32,12 @@ define void @t2() {
 declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i32, i1)
 
 define void @t3() {
-; ARM64: t3
+; ARM64-LABEL: t3
 ; ARM64: adrp x8, _temp@GOTPAGE
 ; ARM64: ldr x0, [x8, _temp@GOTPAGEOFF]
 ; ARM64: adrp x8, _message@PAGE
 ; ARM64: add x1, x8, _message@PAGEOFF
-; ARM64: movz x2, #20
+; ARM64: movz x2, #0x14
 ; ARM64: bl _memmove
   call void @llvm.memmove.p0i8.p0i8.i64(i8* getelementptr inbounds ([80 x i8]* @temp, i32 0, i32 0), i8* getelementptr inbounds ([80 x i8]* @message, i32 0, i32 0), i64 20, i32 16, i1 false)
   ret void
@@ -46,7 +46,7 @@ define void @t3() {
 declare void @llvm.memmove.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i32, i1)
 
 define void @t4() {
-; ARM64: t4
+; ARM64-LABEL: t4
 ; ARM64: adrp x8, _temp@GOTPAGE
 ; ARM64: ldr x8, [x8, _temp@GOTPAGEOFF]
 ; ARM64: adrp x9, _message@PAGE
@@ -63,7 +63,7 @@ define void @t4() {
 }
 
 define void @t5() {
-; ARM64: t5
+; ARM64-LABEL: t5
 ; ARM64: adrp x8, _temp@GOTPAGE
 ; ARM64: ldr x8, [x8, _temp@GOTPAGEOFF]
 ; ARM64: adrp x9, _message@PAGE
@@ -80,7 +80,7 @@ define void @t5() {
 }
 
 define void @t6() {
-; ARM64: t6
+; ARM64-LABEL: t6
 ; ARM64: adrp x8, _temp@GOTPAGE
 ; ARM64: ldr x8, [x8, _temp@GOTPAGEOFF]
 ; ARM64: adrp x9, _message@PAGE
@@ -97,7 +97,7 @@ define void @t6() {
 }
 
 define void @t7() {
-; ARM64: t7
+; ARM64-LABEL: t7
 ; ARM64: adrp x8, _temp@GOTPAGE
 ; ARM64: ldr x8, [x8, _temp@GOTPAGEOFF]
 ; ARM64: adrp x9, _message@PAGE
@@ -116,7 +116,7 @@ define void @t7() {
 }
 
 define void @t8() {
-; ARM64: t8
+; ARM64-LABEL: t8
 ; ARM64: adrp x8, _temp@GOTPAGE
 ; ARM64: ldr x8, [x8, _temp@GOTPAGEOFF]
 ; ARM64: adrp x9, _message@PAGE
diff --git a/test/CodeGen/ARM64/fast-isel-materialize.ll b/test/CodeGen/ARM64/fast-isel-materialize.ll
index fa2daf73db..ffac131f0c 100644
--- a/test/CodeGen/ARM64/fast-isel-materialize.ll
+++ b/test/CodeGen/ARM64/fast-isel-materialize.ll
@@ -3,14 +3,14 @@
 ; Materialize using fmov
 define void @float_(float* %value) {
 ; CHECK: @float_
-; CHECK: fmov s0, #1.250000e+00
+; CHECK: fmov s0, #1.25000000
   store float 1.250000e+00, float* %value, align 4
   ret void
 }
 
 define void @double_(double* %value) {
 ; CHECK: @double_
-; CHECK: fmov d0, #1.250000e+00
+; CHECK: fmov d0, #1.25000000
   store double 1.250000e+00, double* %value, align 8
   ret void
 }
diff --git a/test/CodeGen/ARM64/fast-isel-noconvert.ll b/test/CodeGen/ARM64/fast-isel-noconvert.ll
index 3517970016..483d1799f9 100644
--- a/test/CodeGen/ARM64/fast-isel-noconvert.ll
+++ b/test/CodeGen/ARM64/fast-isel-noconvert.ll
@@ -33,4 +33,36 @@ define <2 x i64> @test_fptosi(<2 x double> %in) {
 
   %res = fptosi <2 x double> %in to <2 x i64>
   ret <2 x i64> %res
-}
\ No newline at end of file
+}
+
+define fp128 @uitofp_i32_fp128(i32 %a) {
+entry:
+; CHECK-LABEL: uitofp_i32_fp128
+; CHECK: bl ___floatunsitf
+  %conv = uitofp i32 %a to fp128
+  ret fp128 %conv
+}
+
+define fp128 @uitofp_i64_fp128(i64 %a) {
+entry:
+; CHECK-LABEL: uitofp_i64_fp128
+; CHECK: bl ___floatunditf
+  %conv = uitofp i64 %a to fp128
+  ret fp128 %conv
+}
+
+define i32 @uitofp_fp128_i32(fp128 %a) {
+entry:
+; CHECK-LABEL: uitofp_fp128_i32
+; CHECK: ___fixunstfsi
+  %conv = fptoui fp128 %a to i32
+  ret i32 %conv
+}
+
+define i64 @uitofp_fp128_i64(fp128 %a) {
+entry:
+; CHECK-LABEL: uitofp_fp128_i64
+; CHECK: ___fixunstfdi
+  %conv = fptoui fp128 %a to i64
+  ret i64 %conv
+}
diff --git a/test/CodeGen/ARM64/fast-isel.ll b/test/CodeGen/ARM64/fast-isel.ll
index ba718d3a95..0194b3a6c2 100644
--- a/test/CodeGen/ARM64/fast-isel.ll
+++ b/test/CodeGen/ARM64/fast-isel.ll
@@ -87,7 +87,7 @@ entry:
 
 define void @t6() nounwind {
 ; CHECK: t6
-; CHECK: brk #1
+; CHECK: brk #0x1
   tail call void @llvm.trap()
   ret void
 }
diff --git a/test/CodeGen/ARM64/fcopysign.ll b/test/CodeGen/ARM64/fcopysign.ll
index 094ce7aa5b..66241df944 100644
--- a/test/CodeGen/ARM64/fcopysign.ll
+++ b/test/CodeGen/ARM64/fcopysign.ll
@@ -5,7 +5,7 @@
 define float @test1(float %x, float %y) nounwind {
 entry:
 ; CHECK-LABEL: test1:
-; CHECK: movi.4s	v2, #128, lsl #24
+; CHECK: movi.4s	v2, #0x80, lsl #24
 ; CHECK: bit.16b	v0, v1, v2
   %0 = tail call float @copysignf(float %x, float %y) nounwind readnone
   ret float %0
@@ -37,7 +37,7 @@ define float @test4() nounwind {
 entry:
 ; CHECK-LABEL: test4:
 ; CHECK: fcvt s0, d0
-; CHECK: movi.4s v[[CONST:[0-9]+]], #128, lsl #24
+; CHECK: movi.4s v[[CONST:[0-9]+]], #0x80, lsl #24
 ; CHECK: bit.16b v{{[0-9]+}}, v0, v[[CONST]]
   %0 = tail call double (...)* @bar() nounwind
   %1 = fptrunc double %0 to float
diff --git a/test/CodeGen/ARM64/fp128.ll b/test/CodeGen/ARM64/fp128.ll
index a1a956d231..a481c79cca 100644
--- a/test/CodeGen/ARM64/fp128.ll
+++ b/test/CodeGen/ARM64/fp128.ll
@@ -186,13 +186,13 @@ define i32 @test_br_cc() {
 iftrue:
   ret i32 42
 ; CHECK-NEXT: BB#
-; CHECK-NEXT: movz w0, #42
+; CHECK-NEXT: movz w0, #0x2a
 ; CHECK-NEXT: b [[REALRET:.LBB[0-9]+_[0-9]+]]
 
 iffalse:
   ret i32 29
 ; CHECK: [[RET29]]:
-; CHECK-NEXT: movz w0, #29
+; CHECK-NEXT: movz w0, #0x1d
 ; CHECK-NEXT: [[REALRET]]:
 ; CHECK: ret
 }
diff --git a/test/CodeGen/ARM64/long-shift.ll b/test/CodeGen/ARM64/long-shift.ll
index caa486a815..d5baf16bdd 100644
--- a/test/CodeGen/ARM64/long-shift.ll
+++ b/test/CodeGen/ARM64/long-shift.ll
@@ -2,16 +2,16 @@
 
 define i128 @shl(i128 %r, i128 %s) nounwind readnone {
 ; CHECK-LABEL: shl:
-; CHECK: lslv  [[XREG_0:x[0-9]+]], x1, x2
+; CHECK: lsl  [[XREG_0:x[0-9]+]], x1, x2
 ; CHECK-NEXT: orr w[[XREG_1:[0-9]+]], wzr, #0x40
 ; CHECK-NEXT: sub [[XREG_2:x[0-9]+]], x[[XREG_1]], x2
-; CHECK-NEXT: lsrv  [[XREG_3:x[0-9]+]], x0, [[XREG_2]]
+; CHECK-NEXT: lsr  [[XREG_3:x[0-9]+]], x0, [[XREG_2]]
 ; CHECK-NEXT: orr [[XREG_6:x[0-9]+]], [[XREG_3]], [[XREG_0]]
 ; CHECK-NEXT: sub [[XREG_4:x[0-9]+]], x2, #64
-; CHECK-NEXT: lslv  [[XREG_5:x[0-9]+]], x0, [[XREG_4]]
+; CHECK-NEXT: lsl  [[XREG_5:x[0-9]+]], x0, [[XREG_4]]
 ; CHECK-NEXT: cmp   [[XREG_4]], #0
 ; CHECK-NEXT: csel  x1, [[XREG_5]], [[XREG_6]], ge
-; CHECK-NEXT: lslv  [[SMALLSHIFT_LO:x[0-9]+]], x0, x2
+; CHECK-NEXT: lsl  [[SMALLSHIFT_LO:x[0-9]+]], x0, x2
 ; CHECK-NEXT: csel  x0, xzr, [[SMALLSHIFT_LO]], ge
 ; CHECK-NEXT: ret
 
@@ -21,16 +21,16 @@ define i128 @shl(i128 %r, i128 %s) nounwind readnone {
 
 define i128 @ashr(i128 %r, i128 %s) nounwind readnone {
 ; CHECK-LABEL: ashr:
-; CHECK: lsrv  [[XREG_0:x[0-9]+]], x0, x2
+; CHECK: lsr  [[XREG_0:x[0-9]+]], x0, x2
 ; CHECK-NEXT: orr w[[XREG_1:[0-9]+]], wzr, #0x40
 ; CHECK-NEXT: sub [[XREG_2:x[0-9]+]], x[[XREG_1]], x2
-; CHECK-NEXT: lslv  [[XREG_3:x[0-9]+]], x1, [[XREG_2]]
+; CHECK-NEXT: lsl  [[XREG_3:x[0-9]+]], x1, [[XREG_2]]
 ; CHECK-NEXT: orr [[XREG_4:x[0-9]+]], [[XREG_0]], [[XREG_3]]
 ; CHECK-NEXT: sub [[XREG_5:x[0-9]+]], x2, #64
-; CHECK-NEXT: asrv  [[XREG_6:x[0-9]+]], x1, [[XREG_5]]
+; CHECK-NEXT: asr  [[XREG_6:x[0-9]+]], x1, [[XREG_5]]
 ; CHECK-NEXT: cmp   [[XREG_5]], #0
 ; CHECK-NEXT: csel  x0, [[XREG_6]], [[XREG_4]], ge
-; CHECK-NEXT: asrv  [[SMALLSHIFT_HI:x[0-9]+]], x1, x2
+; CHECK-NEXT: asr  [[SMALLSHIFT_HI:x[0-9]+]], x1, x2
 ; CHECK-NEXT: asr [[BIGSHIFT_HI:x[0-9]+]], x1, #63
 ; CHECK-NEXT: csel x1, [[BIGSHIFT_HI]], [[SMALLSHIFT_HI]], ge
 ; CHECK-NEXT: ret
@@ -41,16 +41,16 @@ define i128 @ashr(i128 %r, i128 %s) nounwind readnone {
 
 define i128 @lshr(i128 %r, i128 %s) nounwind readnone {
 ; CHECK-LABEL: lshr:
-; CHECK: lsrv  [[XREG_0:x[0-9]+]], x0, x2
+; CHECK: lsr  [[XREG_0:x[0-9]+]], x0, x2
 ; CHECK-NEXT: orr w[[XREG_1:[0-9]+]], wzr, #0x40
 ; CHECK-NEXT: sub [[XREG_2:x[0-9]+]], x[[XREG_1]], x2
-; CHECK-NEXT: lslv  [[XREG_3:x[0-9]+]], x1, [[XREG_2]]
+; CHECK-NEXT: lsl  [[XREG_3:x[0-9]+]], x1, [[XREG_2]]
 ; CHECK-NEXT: orr [[XREG_4:x[0-9]+]], [[XREG_0]], [[XREG_3]]
 ; CHECK-NEXT: sub [[XREG_5:x[0-9]+]], x2, #64
-; CHECK-NEXT: lsrv  [[XREG_6:x[0-9]+]], x1, [[XREG_5]]
+; CHECK-NEXT: lsr  [[XREG_6:x[0-9]+]], x1, [[XREG_5]]
 ; CHECK-NEXT: cmp   [[XREG_5]], #0
 ; CHECK-NEXT: csel  x0, [[XREG_6]], [[XREG_4]], ge
-; CHECK-NEXT: lsrv  [[SMALLSHIFT_HI:x[0-9]+]], x1, x2
+; CHECK-NEXT: lsr  [[SMALLSHIFT_HI:x[0-9]+]], x1, x2
 ; CHECK-NEXT: csel x1, xzr, [[SMALLSHIFT_HI]], ge
 ; CHECK-NEXT: ret
 
diff --git a/test/CodeGen/ARM64/memcpy-inline.ll b/test/CodeGen/ARM64/memcpy-inline.ll
index 26f5166894..f921a59245 100644
--- a/test/CodeGen/ARM64/memcpy-inline.ll
+++ b/test/CodeGen/ARM64/memcpy-inline.ll
@@ -75,7 +75,7 @@ define void @t5(i8* nocapture %C) nounwind {
 entry:
 ; CHECK-LABEL: t5:
 ; CHECK: strb wzr, [x0, #6]
-; CHECK: movz [[REG7:w[0-9]+]], #21587
+; CHECK: movz [[REG7:w[0-9]+]], #0x5453
 ; CHECK: strh [[REG7]], [x0, #4]
 ; CHECK: movz [[REG8:w[0-9]+]],
 ; CHECK: movk [[REG8]],
diff --git a/test/CodeGen/ARM64/movi.ll b/test/CodeGen/ARM64/movi.ll
index 8fcecccd5b..2cd368d909 100644
--- a/test/CodeGen/ARM64/movi.ll
+++ b/test/CodeGen/ARM64/movi.ll
@@ -6,35 +6,35 @@
 
 ; 64-bit immed with 32-bit pattern size, rotated by 0.
 define i64 @test64_32_rot0() nounwind {
-; CHECK: test64_32_rot0
+; CHECK-LABEL: test64_32_rot0:
 ; CHECK: orr x0, xzr, #0x700000007
   ret i64 30064771079
 }
 
 ; 64-bit immed with 32-bit pattern size, rotated by 2.
 define i64 @test64_32_rot2() nounwind {
-; CHECK: test64_32_rot2
+; CHECK-LABEL: test64_32_rot2:
 ; CHECK: orr x0, xzr, #0xc0000003c0000003
   ret i64 13835058071388291075
 }
 
 ; 64-bit immed with 4-bit pattern size, rotated by 3.
 define i64 @test64_4_rot3() nounwind {
-; CHECK: test64_4_rot3
+; CHECK-LABEL: test64_4_rot3:
 ; CHECK: orr  x0, xzr, #0xeeeeeeeeeeeeeeee
   ret i64 17216961135462248174
 }
 
 ; 32-bit immed with 32-bit pattern size, rotated by 16.
 define i32 @test32_32_rot16() nounwind {
-; CHECK: test32_32_rot16
+; CHECK-LABEL: test32_32_rot16:
 ; CHECK: orr w0, wzr, #0xff0000
   ret i32 16711680
 }
 
 ; 32-bit immed with 2-bit pattern size, rotated by 1.
 define i32 @test32_2_rot1() nounwind {
-; CHECK: test32_2_rot1
+; CHECK-LABEL: test32_2_rot1:
 ; CHECK: orr w0, wzr, #0xaaaaaaaa
   ret i32 2863311530
 }
@@ -44,31 +44,31 @@ define i32 @test32_2_rot1() nounwind {
 ;==--------------------------------------------------------------------------==
 
 define i32 @movz() nounwind {
-; CHECK: movz
-; CHECK: movz w0, #5
+; CHECK-LABEL: movz:
+; CHECK: movz w0, #0x5
   ret i32 5
 }
 
 define i64 @movz_3movk() nounwind {
-; CHECK: movz_3movk
-; CHECK:      movz x0, #5, lsl #48
-; CHECK-NEXT: movk x0, #4660, lsl #32
-; CHECK-NEXT: movk x0, #43981, lsl #16
-; CHECK-NEXT: movk x0, #22136
+; CHECK-LABEL: movz_3movk:
+; CHECK:      movz x0, #0x5, lsl #48
+; CHECK-NEXT: movk x0, #0x1234, lsl #32
+; CHECK-NEXT: movk x0, #0xabcd, lsl #16
+; CHECK-NEXT: movk x0, #0x5678
   ret i64 1427392313513592
 }
 
 define i64 @movz_movk_skip1() nounwind {
-; CHECK: movz_movk_skip1
-; CHECK:      movz x0, #5, lsl #32
-; CHECK-NEXT: movk x0, #17185, lsl #16
+; CHECK-LABEL: movz_movk_skip1:
+; CHECK:      movz x0, #0x5, lsl #32
+; CHECK-NEXT: movk x0, #0x4321, lsl #16
   ret i64 22601072640
 }
 
 define i64 @movz_skip1_movk() nounwind {
-; CHECK: movz_skip1_movk
-; CHECK:      movz x0, #34388, lsl #32
-; CHECK-NEXT: movk x0, #4660
+; CHECK-LABEL: movz_skip1_movk:
+; CHECK:      movz x0, #0x8654, lsl #32
+; CHECK-NEXT: movk x0, #0x1234
   ret i64 147695335379508
 }
 
@@ -77,15 +77,15 @@ define i64 @movz_skip1_movk() nounwind {
 ;==--------------------------------------------------------------------------==
 
 define i64 @movn() nounwind {
-; CHECK: movn
-; CHECK: movn x0, #41
+; CHECK-LABEL: movn:
+; CHECK: movn x0, #0x29
   ret i64 -42
 }
 
 define i64 @movn_skip1_movk() nounwind {
-; CHECK: movn_skip1_movk
-; CHECK:      movn x0, #41, lsl #32
-; CHECK-NEXT: movk x0, #4660
+; CHECK-LABEL: movn_skip1_movk:
+; CHECK:      movn x0, #0x29, lsl #32
+; CHECK-NEXT: movk x0, #0x1234
   ret i64 -176093720012
 }
 
@@ -95,108 +95,108 @@ define i64 @movn_skip1_movk() nounwind {
 ; rdar://14987673
 
 define i64 @orr_movk1() nounwind {
-; CHECK: orr_movk1
+; CHECK-LABEL: orr_movk1:
 ; CHECK: orr x0, xzr, #0xffff0000ffff0
-; CHECK: movk x0, #57005, lsl #16
+; CHECK: movk x0, #0xdead, lsl #16
   ret i64 72056498262245120
 }
 
 define i64 @orr_movk2() nounwind {
-; CHECK: orr_movk2
+; CHECK-LABEL: orr_movk2:
 ; CHECK: orr x0, xzr, #0xffff0000ffff0
-; CHECK: movk x0, #57005, lsl #48
+; CHECK: movk x0, #0xdead, lsl #48
   ret i64 -2400982650836746496
 }
 
 define i64 @orr_movk3() nounwind {
-; CHECK: orr_movk3
+; CHECK-LABEL: orr_movk3:
 ; CHECK: orr x0, xzr, #0xffff0000ffff0
-; CHECK: movk x0, #57005, lsl #32
+; CHECK: movk x0, #0xdead, lsl #32
   ret i64 72020953688702720
 }
 
 define i64 @orr_movk4() nounwind {
-; CHECK: orr_movk4
+; CHECK-LABEL: orr_movk4:
 ; CHECK: orr x0, xzr, #0xffff0000ffff0
-; CHECK: movk x0, #57005
+; CHECK: movk x0, #0xdead
   ret i64 72056494543068845
 }
 
 ; rdar://14987618
 define i64 @orr_movk5() nounwind {
-; CHECK: orr_movk5
+; CHECK-LABEL: orr_movk5:
 ; CHECK: orr x0, xzr, #0xff00ff00ff00ff00
-; CHECK: movk x0, #57005, lsl #16
+; CHECK: movk x0, #0xdead, lsl #16
   ret i64 -71777214836900096
 }
 
 define i64 @orr_movk6() nounwind {
-; CHECK: orr_movk6
+; CHECK-LABEL: orr_movk6:
 ; CHECK: orr x0, xzr, #0xff00ff00ff00ff00
-; CHECK: movk x0, #57005, lsl #16
-; CHECK: movk x0, #57005, lsl #48
+; CHECK: movk x0, #0xdead, lsl #16
+; CHECK: movk x0, #0xdead, lsl #48
   ret i64 -2400982647117578496
 }
 
 define i64 @orr_movk7() nounwind {
-; CHECK: orr_movk7
+; CHECK-LABEL: orr_movk7:
 ; CHECK: orr x0, xzr, #0xff00ff00ff00ff00
-; CHECK: movk x0, #57005, lsl #48
+; CHECK: movk x0, #0xdead, lsl #48
   ret i64 -2400982646575268096
 }
 
 define i64 @orr_movk8() nounwind {
-; CHECK: orr_movk8
+; CHECK-LABEL: orr_movk8:
 ; CHECK: orr x0, xzr, #0xff00ff00ff00ff00
-; CHECK: movk x0, #57005
-; CHECK: movk x0, #57005, lsl #48
+; CHECK: movk x0, #0xdead
+; CHECK: movk x0, #0xdead, lsl #48
   ret i64 -2400982646575276371
 }
 
 ; rdar://14987715
 define i64 @orr_movk9() nounwind {
-; CHECK: orr_movk9
+; CHECK-LABEL: orr_movk9:
 ; CHECK: orr x0, xzr, #0xffffff000000000
-; CHECK: movk x0, #65280
-; CHECK: movk x0, #57005, lsl #16
+; CHECK: movk x0, #0xff00
+; CHECK: movk x0, #0xdead, lsl #16
   ret i64 1152921439623315200
 }
 
 define i64 @orr_movk10() nounwind {
-; CHECK: orr_movk10
+; CHECK-LABEL: orr_movk10:
 ; CHECK: orr x0, xzr, #0xfffffffffffff00
-; CHECK: movk x0, #57005, lsl #16
+; CHECK: movk x0, #0xdead, lsl #16
   ret i64 1152921504047824640
 }
 
 define i64 @orr_movk11() nounwind {
-; CHECK: orr_movk11
+; CHECK-LABEL: orr_movk11:
 ; CHECK: orr x0, xzr, #0xfff00000000000ff
-; CHECK: movk x0, #57005, lsl #16
-; CHECK: movk x0, #65535, lsl #32
+; CHECK: movk x0, #0xdead, lsl #16
+; CHECK: movk x0, #0xffff, lsl #32
   ret i64 -4222125209747201
 }
 
 define i64 @orr_movk12() nounwind {
-; CHECK: orr_movk12
+; CHECK-LABEL: orr_movk12:
 ; CHECK: orr x0, xzr, #0xfff00000000000ff
-; CHECK: movk x0, #57005, lsl #32
+; CHECK: movk x0, #0xdead, lsl #32
   ret i64 -4258765016661761
 }
 
 define i64 @orr_movk13() nounwind {
-; CHECK: orr_movk13
+; CHECK-LABEL: orr_movk13:
 ; CHECK: orr x0, xzr, #0xfffff000000
-; CHECK: movk x0, #57005
-; CHECK: movk x0, #57005, lsl #48
+; CHECK: movk x0, #0xdead
+; CHECK: movk x0, #0xdead, lsl #48
   ret i64 -2401245434149282131
 }
 
 ; rdar://13944082
 define i64 @g() nounwind {
-; CHECK: g
-; CHECK: movz x0, #65535, lsl #48
-; CHECK: movk x0, #2
+; CHECK-LABEL: g:
+; CHECK: movz x0, #0xffff, lsl #48
+; CHECK: movk x0, #0x2
 entry:
   ret i64 -281474976710654
 }
diff --git a/test/CodeGen/ARM64/patchpoint.ll b/test/CodeGen/ARM64/patchpoint.ll
index dd555b0f3e..9ef1d778a3 100644
--- a/test/CodeGen/ARM64/patchpoint.ll
+++ b/test/CodeGen/ARM64/patchpoint.ll
@@ -5,13 +5,13 @@
 define i64 @trivial_patchpoint_codegen(i64 %p1, i64 %p2, i64 %p3, i64 %p4) {
 entry:
 ; CHECK-LABEL: trivial_patchpoint_codegen:
-; CHECK:       movz x16, #57005, lsl #32
-; CHECK-NEXT:  movk x16, #48879, lsl #16
-; CHECK-NEXT:  movk x16, #51966
+; CHECK:       movz x16, #0xdead, lsl #32
+; CHECK-NEXT:  movk x16, #0xbeef, lsl #16
+; CHECK-NEXT:  movk x16, #0xcafe
 ; CHECK-NEXT:  blr  x16
-; CHECK:       movz x16, #57005, lsl #32
-; CHECK-NEXT:  movk x16, #48879, lsl #16
-; CHECK-NEXT:  movk x16, #51967
+; CHECK:       movz x16, #0xdead, lsl #32
+; CHECK-NEXT:  movk x16, #0xbeef, lsl #16
+; CHECK-NEXT:  movk x16, #0xcaff
 ; CHECK-NEXT:  blr  x16
 ; CHECK:       ret
   %resolveCall2 = inttoptr i64 244837814094590 to i8*
@@ -51,9 +51,9 @@ entry:
 ; CHECK:      str x{{.+}}, [sp]
 ; CHECK-NEXT: mov  x0, x{{.+}}
 ; CHECK:      Ltmp
-; CHECK-NEXT: movz  x16, #65535, lsl #32
-; CHECK-NEXT: movk  x16, #57005, lsl #16
-; CHECK-NEXT: movk  x16, #48879
+; CHECK-NEXT: movz  x16, #0xffff, lsl #32
+; CHECK-NEXT: movk  x16, #0xdead, lsl #16
+; CHECK-NEXT: movk  x16, #0xbeef
 ; CHECK-NEXT: blr x16
   %resolveCall2 = inttoptr i64 281474417671919 to i8*
   %result = tail call webkit_jscc i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 5, i32 20, i8* %resolveCall2, i32 2, i64 %p4, i64 %p2)
@@ -74,9 +74,9 @@ entry:
 ; CHECK-NEXT: orr w{{.+}}, wzr, #0x2
 ; CHECK-NEXT: str x{{.+}}, [sp]
 ; CHECK:      Ltmp
-; CHECK-NEXT: movz  x16, #65535, lsl #32
-; CHECK-NEXT: movk  x16, #57005, lsl #16
-; CHECK-NEXT: movk  x16, #48879
+; CHECK-NEXT: movz  x16, #0xffff, lsl #32
+; CHECK-NEXT: movk  x16, #0xdead, lsl #16
+; CHECK-NEXT: movk  x16, #0xbeef
 ; CHECK-NEXT: blr x16
   %call = inttoptr i64 281474417671919 to i8*
   %result = call webkit_jscc i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 7, i32 20, i8* %call, i32 6, i64 %callee, i64 2, i64 undef, i32 4, i32 undef, i64 6)
@@ -88,7 +88,7 @@ define i64 @jscall_patchpoint_codegen3(i64 %callee) {
 entry:
 ; CHECK-LABEL: jscall_patchpoint_codegen3:
 ; CHECK:      Ltmp
-; CHECK:      movz  w{{.+}}, #10
+; CHECK:      movz  w{{.+}}, #0xa
 ; CHECK-NEXT: str x{{.+}}, [sp, #48]
 ; CHECK-NEXT: orr w{{.+}}, wzr, #0x8
 ; CHECK-NEXT: str w{{.+}}, [sp, #36]
@@ -99,9 +99,9 @@ entry:
 ; CHECK-NEXT: orr w{{.+}}, wzr, #0x2
 ; CHECK-NEXT: str x{{.+}}, [sp]
 ; CHECK:      Ltmp
-; CHECK-NEXT: movz  x16, #65535, lsl #32
-; CHECK-NEXT: movk  x16, #57005, lsl #16
-; CHECK-NEXT: movk  x16, #48879
+; CHECK-NEXT: movz  x16, #0xffff, lsl #32
+; CHECK-NEXT: movk  x16, #0xdead, lsl #16
+; CHECK-NEXT: movk  x16, #0xbeef
 ; CHECK-NEXT: blr x16
   %call = inttoptr i64 281474417671919 to i8*
   %result = call webkit_jscc i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 7, i32 20, i8* %call, i32 10, i64 %callee, i64 2, i64 undef, i32 4, i32 undef, i64 6, i32 undef, i32 8, i32 undef, i64 10)
diff --git a/test/CodeGen/ARM64/register-pairing.ll b/test/CodeGen/ARM64/register-pairing.ll
index 4de80d2d2e..99defb1aad 100644
--- a/test/CodeGen/ARM64/register-pairing.ll
+++ b/test/CodeGen/ARM64/register-pairing.ll
@@ -13,7 +13,7 @@ define void @odd() nounwind {
 ; CHECK: stp x24, x23, [sp, #96]
 ; CHECK: stp x22, x21, [sp, #112]
 ; CHECK: stp x20, x19, [sp, #128]
-; CHECK: movz x0, #42
+; CHECK: movz x0, #0x2a
 ; CHECK: ldp x20, x19, [sp, #128]
 ; CHECK: ldp x22, x21, [sp, #112]
 ; CHECK: ldp x24, x23, [sp, #96]
@@ -38,7 +38,7 @@ define void @even() nounwind {
 ; CHECK: stp x24, x23, [sp, #96]
 ; CHECK: stp x22, x21, [sp, #112]
 ; CHECK: stp x20, x19, [sp, #128]
-; CHECK: movz x0, #42
+; CHECK: movz x0, #0x2a
 ; CHECK: ldp x20, x19, [sp, #128]
 ; CHECK: ldp x22, x21, [sp, #112]
 ; CHECK: ldp x24, x23, [sp, #96]
diff --git a/test/CodeGen/ARM64/trap.ll b/test/CodeGen/ARM64/trap.ll
index c9e0beabfc..5e99c32c57 100644
--- a/test/CodeGen/ARM64/trap.ll
+++ b/test/CodeGen/ARM64/trap.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=arm64 | FileCheck %s
 define void @foo() nounwind {
 ; CHECK: foo
-; CHECK: brk #1
+; CHECK: brk #0x1
   tail call void @llvm.trap()
   ret void
 }
diff --git a/test/CodeGen/ARM64/variadic-aapcs.ll b/test/CodeGen/ARM64/variadic-aapcs.ll
index ac66902fa6..36a7bfd925 100644
--- a/test/CodeGen/ARM64/variadic-aapcs.ll
+++ b/test/CodeGen/ARM64/variadic-aapcs.ll
@@ -32,7 +32,7 @@ define void @test_simple(i32 %n, ...) {
 ; CHECK: add [[VR_TOP:x[0-9]+]], [[VR_TOPTMP]], #128
 ; CHECK: str [[VR_TOP]], [x[[VA_LIST]], #16]
 
-; CHECK: movn [[GR_OFFS:w[0-9]+]], #55
+; CHECK: movn [[GR_OFFS:w[0-9]+]], #0x37
 ; CHECK: str [[GR_OFFS]], [x[[VA_LIST]], #24]
 
 ; CHECK: orr [[VR_OFFS:w[0-9]+]], wzr, #0xffffff80
@@ -70,10 +70,10 @@ define void @test_fewargs(i32 %n, i32 %n1, i32 %n2, float %m, ...) {
 ; CHECK: add [[VR_TOP:x[0-9]+]], [[VR_TOPTMP]], #112
 ; CHECK: str [[VR_TOP]], [x[[VA_LIST]], #16]
 
-; CHECK: movn [[GR_OFFS:w[0-9]+]], #39
+; CHECK: movn [[GR_OFFS:w[0-9]+]], #0x27
 ; CHECK: str [[GR_OFFS]], [x[[VA_LIST]], #24]
 
-; CHECK: movn [[VR_OFFS:w[0-9]+]], #111
+; CHECK: movn [[VR_OFFS:w[0-9]+]], #0x6f
 ; CHECK: str [[VR_OFFS]], [x[[VA_LIST]], #28]
 
   %addr = bitcast %va_list* @var to i8*
diff --git a/test/CodeGen/ARM64/vector-ext.ll b/test/CodeGen/ARM64/vector-ext.ll
index 88889fdef3..9cc0555d8c 100644
--- a/test/CodeGen/ARM64/vector-ext.ll
+++ b/test/CodeGen/ARM64/vector-ext.ll
@@ -2,7 +2,7 @@
 
 ;CHECK: @func30
 ;CHECK: ushll.4s  v0, v0, #0
-;CHECK: movi.4s v1, #1
+;CHECK: movi.4s v1, #0x1
 ;CHECK: and.16b v0, v0, v1
 ;CHECK: str  q0, [x0]
 ;CHECK: ret
diff --git a/test/CodeGen/ARM64/vector-imm.ll b/test/CodeGen/ARM64/vector-imm.ll
index f1fc3ccf84..a84f804c8c 100644
--- a/test/CodeGen/ARM64/vector-imm.ll
+++ b/test/CodeGen/ARM64/vector-imm.ll
@@ -42,7 +42,7 @@ define <16 x i8> @v_bicimmQ(<16 x i8>* %A) nounwind {
 
 define <2 x double> @foo(<2 x double> %bar) nounwind {
 ; CHECK: foo
-; CHECK: fmov.2d	v1, #1.000000e+00
+; CHECK: fmov.2d	v1, #1.0000000
   %add = fadd <2 x double> %bar, <double 1.0, double 1.0>
   ret <2 x double> %add
 }
@@ -50,35 +50,35 @@ define <2 x double> @foo(<2 x double> %bar) nounwind {
 define <4 x i32> @movi_4s_imm_t1() nounwind readnone ssp {
 entry:
 ; CHECK-LABEL: movi_4s_imm_t1:
-; CHECK: movi.4s v0, #75
+; CHECK: movi.4s v0, #0x4b
   ret <4 x i32> <i32 75, i32 75, i32 75, i32 75>
 }
 
 define <4 x i32> @movi_4s_imm_t2() nounwind readnone ssp {
 entry:
 ; CHECK-LABEL: movi_4s_imm_t2:
-; CHECK: movi.4s v0, #75, lsl #8
+; CHECK: movi.4s v0, #0x4b, lsl #8
   ret <4 x i32> <i32 19200, i32 19200, i32 19200, i32 19200>
 }
 
 define <4 x i32> @movi_4s_imm_t3() nounwind readnone ssp {
 entry:
 ; CHECK-LABEL: movi_4s_imm_t3:
-; CHECK: movi.4s v0, #75, lsl #16
+; CHECK: movi.4s v0, #0x4b, lsl #16
   ret <4 x i32> <i32 4915200, i32 4915200, i32 4915200, i32 4915200>
 }
 
 define <4 x i32> @movi_4s_imm_t4() nounwind readnone ssp {
 entry:
 ; CHECK-LABEL: movi_4s_imm_t4:
-; CHECK: movi.4s v0, #75, lsl #24
+; CHECK: movi.4s v0, #0x4b, lsl #24
   ret <4 x i32> <i32 1258291200, i32 1258291200, i32 1258291200, i32 1258291200>
 }
 
 define <8 x i16> @movi_8h_imm_t5() nounwind readnone ssp {
 entry:
 ; CHECK-LABEL: movi_8h_imm_t5:
-; CHECK: movi.8h v0, #75
+; CHECK: movi.8h v0, #0x4b
   ret <8 x i16> <i16 75, i16 75, i16 75, i16 75, i16 75, i16 75, i16 75, i16 75>
 }
 
@@ -86,28 +86,28 @@ entry:
 define <8 x i16> @movi_8h_imm_t6() nounwind readnone ssp {
 entry:
 ; CHECK-LABEL: movi_8h_imm_t6:
-; CHECK: movi.8h v0, #75, lsl #8
+; CHECK: movi.8h v0, #0x4b, lsl #8
   ret <8 x i16> <i16 19200, i16 19200, i16 19200, i16 19200, i16 19200, i16 19200, i16 19200, i16 19200>
 }
 
 define <4 x i32> @movi_4s_imm_t7() nounwind readnone ssp {
 entry:
 ; CHECK-LABEL: movi_4s_imm_t7:
-; CHECK: movi.4s v0, #75, msl #8
+; CHECK: movi.4s v0, #0x4b, msl #8
 ret <4 x i32> <i32 19455, i32 19455, i32 19455, i32 19455>
 }
 
 define <4 x i32> @movi_4s_imm_t8() nounwind readnone ssp {
 entry:
 ; CHECK-LABEL: movi_4s_imm_t8:
-; CHECK: movi.4s v0, #75, msl #16
+; CHECK: movi.4s v0, #0x4b, msl #16
 ret <4 x i32> <i32 4980735, i32 4980735, i32 4980735, i32 4980735>
 }
 
 define <16 x i8> @movi_16b_imm_t9() nounwind readnone ssp {
 entry:
 ; CHECK-LABEL: movi_16b_imm_t9:
-; CHECK: movi.16b v0, #75
+; CHECK: movi.16b v0, #0x4b
 ret <16 x i8> <i8 75, i8 75, i8 75, i8 75, i8 75, i8 75, i8 75, i8 75,
                i8 75, i8 75, i8 75, i8 75, i8 75, i8 75, i8 75, i8 75>
 }
@@ -122,13 +122,13 @@ ret <2 x i64> <i64 71777214294589695, i64 71777214294589695>
 define <4 x i32> @movi_4s_imm_t11() nounwind readnone ssp {
 entry:
 ; CHECK-LABEL: movi_4s_imm_t11:
-; CHECK: fmov.4s v0, #-3.281250e-01
+; CHECK: fmov.4s v0, #-0.32812500
 ret <4 x i32> <i32 3198681088, i32 3198681088, i32 3198681088, i32 3198681088>
 }
 
 define <2 x i64> @movi_2d_imm_t12() nounwind readnone ssp {
 entry:
 ; CHECK-LABEL: movi_2d_imm_t12:
-; CHECK: fmov.2d v0, #-1.718750e-01
+; CHECK: fmov.2d v0, #-0.17187500
 ret <2 x i64> <i64 13818732506632945664, i64 13818732506632945664>
 }
diff --git a/test/CodeGen/ARM64/vector-insertion.ll b/test/CodeGen/ARM64/vector-insertion.ll
index b9f3fc131e..0926bcfde9 100644
--- a/test/CodeGen/ARM64/vector-insertion.ll
+++ b/test/CodeGen/ARM64/vector-insertion.ll
@@ -25,7 +25,7 @@ entry:
   ret void
 
   ; CHECK-LABEL: test1f
-  ; CHECK: fmov  s[[TEMP:[0-9]+]], #1.000000e+00
+  ; CHECK: fmov  s[[TEMP:[0-9]+]], #1.0000000
   ; CHECK: dup.4s  v[[TEMP2:[0-9]+]], v[[TEMP]][0]
   ; CHECK: ins.s v[[TEMP2]][0], v0[0]
   ; CHECK: str q[[TEMP2]], [x0]
diff --git a/test/CodeGen/ARM64/vshuffle.ll b/test/CodeGen/ARM64/vshuffle.ll
index fb1227daad..62fd96102d 100644
--- a/test/CodeGen/ARM64/vshuffle.ll
+++ b/test/CodeGen/ARM64/vshuffle.ll
@@ -15,7 +15,7 @@
 ; CHECK:  .byte   0                       ; 0x0
 ; CHECK: test1
 ; CHECK: ldr d[[REG0:[0-9]+]], [{{.*}}, lCPI0_0
-; CHECK: movi.8h v[[REG1:[0-9]+]], #1, lsl #8
+; CHECK: movi.8h v[[REG1:[0-9]+]], #0x1, lsl #8
 ; CHECK: tbl.8b  v{{[0-9]+}}, { v[[REG1]] }, v[[REG0]]
 define <8 x i1> @test1() {
 entry:
diff --git a/test/CodeGen/ARM64/xaluo.ll b/test/CodeGen/ARM64/xaluo.ll
index 6a8520d1c1..bda41b10c3 100644
--- a/test/CodeGen/ARM64/xaluo.ll
+++ b/test/CodeGen/ARM64/xaluo.ll
@@ -31,7 +31,7 @@ define i1 @uaddo.i32(i32 %v1, i32 %v2, i32* %res) {
 entry:
 ; CHECK-LABEL:  uaddo.i32
 ; CHECK:        adds w8, w0, w1
-; CHECK-NEXT:   csinc w0, wzr, wzr, cc
+; CHECK-NEXT:   csinc w0, wzr, wzr, lo
   %t = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %v1, i32 %v2)
   %val = extractvalue {i32, i1} %t, 0
   %obit = extractvalue {i32, i1} %t, 1
@@ -43,7 +43,7 @@ define i1 @uaddo.i64(i64 %v1, i64 %v2, i64* %res) {
 entry:
 ; CHECK-LABEL:  uaddo.i64
 ; CHECK:        adds x8, x0, x1
-; CHECK-NEXT:   csinc w0, wzr, wzr, cc
+; CHECK-NEXT:   csinc w0, wzr, wzr, lo
   %t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %v1, i64 %v2)
   %val = extractvalue {i64, i1} %t, 0
   %obit = extractvalue {i64, i1} %t, 1
@@ -79,7 +79,7 @@ define i1 @usubo.i32(i32 %v1, i32 %v2, i32* %res) {
 entry:
 ; CHECK-LABEL:  usubo.i32
 ; CHECK:        subs w8, w0, w1
-; CHECK-NEXT:   csinc w0, wzr, wzr, cs
+; CHECK-NEXT:   csinc w0, wzr, wzr, hs
   %t = call {i32, i1} @llvm.usub.with.overflow.i32(i32 %v1, i32 %v2)
   %val = extractvalue {i32, i1} %t, 0
   %obit = extractvalue {i32, i1} %t, 1
@@ -91,7 +91,7 @@ define i1 @usubo.i64(i64 %v1, i64 %v2, i64* %res) {
 entry:
 ; CHECK-LABEL:  usubo.i64
 ; CHECK:        subs x8, x0, x1
-; CHECK-NEXT:   csinc w0, wzr, wzr, cs
+; CHECK-NEXT:   csinc w0, wzr, wzr, hs
   %t = call {i64, i1} @llvm.usub.with.overflow.i64(i64 %v1, i64 %v2)
   %val = extractvalue {i64, i1} %t, 0
   %obit = extractvalue {i64, i1} %t, 1
@@ -184,7 +184,7 @@ define i32 @uaddo.select.i32(i32 %v1, i32 %v2) {
 entry:
 ; CHECK-LABEL:  uaddo.select.i32
 ; CHECK:        cmn w0, w1
-; CHECK-NEXT:   csel w0, w0, w1, cs
+; CHECK-NEXT:   csel w0, w0, w1, hs
   %t = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %v1, i32 %v2)
   %obit = extractvalue {i32, i1} %t, 1
   %ret = select i1 %obit, i32 %v1, i32 %v2
@@ -195,7 +195,7 @@ define i64 @uaddo.select.i64(i64 %v1, i64 %v2) {
 entry:
 ; CHECK-LABEL:  uaddo.select.i64
 ; CHECK:        cmn x0, x1
-; CHECK-NEXT:   csel x0, x0, x1, cs
+; CHECK-NEXT:   csel x0, x0, x1, hs
   %t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %v1, i64 %v2)
   %obit = extractvalue {i64, i1} %t, 1
   %ret = select i1 %obit, i64 %v1, i64 %v2
@@ -228,7 +228,7 @@ define i32 @usubo.select.i32(i32 %v1, i32 %v2) {
 entry:
 ; CHECK-LABEL:  usubo.select.i32
 ; CHECK:        cmp w0, w1
-; CHECK-NEXT:   csel w0, w0, w1, cc
+; CHECK-NEXT:   csel w0, w0, w1, lo
   %t = call {i32, i1} @llvm.usub.with.overflow.i32(i32 %v1, i32 %v2)
   %obit = extractvalue {i32, i1} %t, 1
   %ret = select i1 %obit, i32 %v1, i32 %v2
@@ -239,7 +239,7 @@ define i64 @usubo.select.i64(i64 %v1, i64 %v2) {
 entry:
 ; CHECK-LABEL:  usubo.select.i64
 ; CHECK:        cmp x0, x1
-; CHECK-NEXT:   csel x0, x0, x1, cc
+; CHECK-NEXT:   csel x0, x0, x1, lo
   %t = call {i64, i1} @llvm.usub.with.overflow.i64(i64 %v1, i64 %v2)
   %obit = extractvalue {i64, i1} %t, 1
   %ret = select i1 %obit, i64 %v1, i64 %v2
@@ -338,7 +338,7 @@ define i1 @uaddo.br.i32(i32 %v1, i32 %v2) {
 entry:
 ; CHECK-LABEL:  uaddo.br.i32
 ; CHECK:        cmn w0, w1
-; CHECK-NEXT:   b.cc
+; CHECK-NEXT:   b.lo
   %t = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %v1, i32 %v2)
   %val = extractvalue {i32, i1} %t, 0
   %obit = extractvalue {i32, i1} %t, 1
@@ -355,7 +355,7 @@ define i1 @uaddo.br.i64(i64 %v1, i64 %v2) {
 entry:
 ; CHECK-LABEL:  uaddo.br.i64
 ; CHECK:        cmn x0, x1
-; CHECK-NEXT:   b.cc
+; CHECK-NEXT:   b.lo
   %t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %v1, i64 %v2)
   %val = extractvalue {i64, i1} %t, 0
   %obit = extractvalue {i64, i1} %t, 1
@@ -406,7 +406,7 @@ define i1 @usubo.br.i32(i32 %v1, i32 %v2) {
 entry:
 ; CHECK-LABEL:  usubo.br.i32
 ; CHECK:        cmp w0, w1
-; CHECK-NEXT:   b.cs
+; CHECK-NEXT:   b.hs
   %t = call {i32, i1} @llvm.usub.with.overflow.i32(i32 %v1, i32 %v2)
   %val = extractvalue {i32, i1} %t, 0
   %obit = extractvalue {i32, i1} %t, 1
@@ -423,7 +423,7 @@ define i1 @usubo.br.i64(i64 %v1, i64 %v2) {
 entry:
 ; CHECK-LABEL:  usubo.br.i64
 ; CHECK:        cmp x0, x1
-; CHECK-NEXT:   b.cs
+; CHECK-NEXT:   b.hs
   %t = call {i64, i1} @llvm.usub.with.overflow.i64(i64 %v1, i64 %v2)
   %val = extractvalue {i64, i1} %t, 0
   %obit = extractvalue {i64, i1} %t, 1
diff --git a/test/CodeGen/Mips/Fast-ISel/nullvoid.ll b/test/CodeGen/Mips/Fast-ISel/nullvoid.ll
new file mode 100644
index 0000000000..eeaff878bf
--- /dev/null
+++ b/test/CodeGen/Mips/Fast-ISel/nullvoid.ll
@@ -0,0 +1,9 @@
+; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32r2 \
+; RUN:     < %s | FileCheck %s
+
+; Function Attrs: nounwind
+define void @foo() {
+entry:
+  ret void
+; CHECK: jr	$ra
+}
diff --git a/test/CodeGen/Mips/longbranch.ll b/test/CodeGen/Mips/longbranch.ll
index 39e32bde4f..f998094064 100644
--- a/test/CodeGen/Mips/longbranch.ll
+++ b/test/CodeGen/Mips/longbranch.ll
@@ -1,36 +1,132 @@
-; RUN: llc -march=mipsel -force-mips-long-branch -disable-mips-delay-filler < %s | FileCheck %s -check-prefix=O32
-; RUN: llc -march=mips64el -mcpu=mips4 -mattr=n64  -force-mips-long-branch -disable-mips-delay-filler < %s | FileCheck %s -check-prefix=N64
-; RUN: llc -march=mips64el -mcpu=mips64 -mattr=n64  -force-mips-long-branch -disable-mips-delay-filler < %s | FileCheck %s -check-prefix=N64
+; RUN: llc -march=mipsel < %s | FileCheck %s
+; RUN: llc -march=mipsel -force-mips-long-branch -O3 < %s \
+; RUN:   | FileCheck %s -check-prefix=O32
+; RUN: llc -march=mips64el -mcpu=mips4 -mattr=n64 -force-mips-long-branch -O3 \
+; RUN:   < %s | FileCheck %s -check-prefix=N64
+; RUN: llc -march=mips64el -mcpu=mips64 -mattr=n64 -force-mips-long-branch -O3 \
+; RUN:   < %s | FileCheck %s -check-prefix=N64
+; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=micromips \
+; RUN:   -force-mips-long-branch -O3 < %s | FileCheck %s -check-prefix=MICROMIPS
 
-@g0 = external global i32
 
-define void @foo1(i32 %s) nounwind {
+@x = external global i32
+
+define void @test1(i32 %s) {
 entry:
-; O32: nop
-; O32: addiu $sp, $sp, -8
-; O32: bal
-; O32: lui $1, 0
-; O32: addiu $1, $1, {{[0-9]+}} 
-; N64: nop
-; N64: daddiu $sp, $sp, -16
-; N64: lui $1, 0
-; N64: daddiu $1, $1, 0
-; N64: dsll $1, $1, 16
-; N64: daddiu $1, $1, 0
-; N64: bal
-; N64: dsll $1, $1, 16
-; N64: daddiu $1, $1, {{[0-9]+}}  
-
-  %tobool = icmp eq i32 %s, 0
-  br i1 %tobool, label %if.end, label %if.then
-
-if.then:                                          ; preds = %entry
-  %0 = load i32* @g0, align 4
-  %add = add nsw i32 %0, 12
-  store i32 %add, i32* @g0, align 4
-  br label %if.end
-
-if.end:                                           ; preds = %entry, %if.then
+  %cmp = icmp eq i32 %s, 0
+  br i1 %cmp, label %end, label %then
+
+then:
+  store i32 1, i32* @x, align 4
+  br label %end
+
+end:
   ret void
-}
 
+
+; First check the normal version (without long branch).  beqz jumps to return,
+; and fallthrough block stores 1 to global variable.
+
+; CHECK:        lui     $[[R0:[0-9]+]], %hi(_gp_disp)
+; CHECK:        addiu   $[[R0]], $[[R0]], %lo(_gp_disp)
+; CHECK:        beqz    $4, $[[BB0:BB[0-9_]+]]
+; CHECK:        addu    $[[GP:[0-9]+]], $[[R0]], $25
+; CHECK:        lw      $[[R1:[0-9]+]], %got(x)($[[GP]])
+; CHECK:        addiu   $[[R2:[0-9]+]], $zero, 1
+; CHECK:        sw      $[[R2]], 0($[[R1]])
+; CHECK:   $[[BB0]]:
+; CHECK:        jr      $ra
+; CHECK:        nop
+
+
+; Check the MIPS32 version.  Check that branch logic is inverted, so that the
+; target of the new branch (bnez) is the fallthrough block of the original
+; branch.  Check that fallthrough block of the new branch contains long branch
+; expansion which at the end indirectly jumps to the target of the original
+; branch.
+
+; O32:        lui     $[[R0:[0-9]+]], %hi(_gp_disp)
+; O32:        addiu   $[[R0]], $[[R0]], %lo(_gp_disp)
+; O32:        bnez    $4, $[[BB0:BB[0-9_]+]]
+; O32:        addu    $[[GP:[0-9]+]], $[[R0]], $25
+
+; Check for long branch expansion:
+; O32:             addiu   $sp, $sp, -8
+; O32-NEXT:        sw      $ra, 0($sp)
+; O32-NEXT:        lui     $1, %hi(($[[BB2:BB[0-9_]+]])-($[[BB1:BB[0-9_]+]]))
+; O32-NEXT:        bal     $[[BB1]]
+; O32-NEXT:        addiu   $1, $1, %lo(($[[BB2]])-($[[BB1]]))
+; O32-NEXT:   $[[BB1]]:
+; O32-NEXT:        addu    $1, $ra, $1
+; O32-NEXT:        lw      $ra, 0($sp)
+; O32-NEXT:        jr      $1
+; O32-NEXT:        addiu   $sp, $sp, 8
+
+; O32:   $[[BB0]]:
+; O32:        lw      $[[R1:[0-9]+]], %got(x)($[[GP]])
+; O32:        addiu   $[[R2:[0-9]+]], $zero, 1
+; O32:        sw      $[[R2]], 0($[[R1]])
+; O32:   $[[BB2]]:
+; O32:        jr      $ra
+; O32:        nop
+
+
+; Check the MIPS64 version.
+
+; N64:        lui     $[[R0:[0-9]+]], %hi(%neg(%gp_rel(test1)))
+; N64:        bnez    $4, $[[BB0:BB[0-9_]+]]
+; N64:        daddu   $[[R1:[0-9]+]], $[[R0]], $25
+
+; Check for long branch expansion:
+; N64:           daddiu  $sp, $sp, -16
+; N64-NEXT:      sd      $ra, 0($sp)
+; N64-NEXT:      lui     $1, %highest(($[[BB2:BB[0-9_]+]])-($[[BB1:BB[0-9_]+]]))
+; N64-NEXT:      daddiu  $1, $1, %higher(($[[BB2]])-($[[BB1]]))
+; N64-NEXT:      dsll    $1, $1, 16
+; N64-NEXT:      daddiu  $1, $1, %hi(($[[BB2]])-($[[BB1]]))
+; N64-NEXT:      dsll    $1, $1, 16
+; N64-NEXT:      bal     $[[BB1]]
+; N64-NEXT:      daddiu  $1, $1, %lo(($[[BB2]])-($[[BB1]]))
+; N64-NEXT:  $[[BB1]]:
+; N64-NEXT:      daddu   $1, $ra, $1
+; N64-NEXT:      ld      $ra, 0($sp)
+; N64-NEXT:      jr      $1
+; N64-NEXT:      daddiu  $sp, $sp, 16
+
+; N64:   $[[BB0]]:
+; N64:        daddiu  $[[GP:[0-9]+]], $[[R1]], %lo(%neg(%gp_rel(test1)))
+; N64:        ld      $[[R2:[0-9]+]], %got_disp(x)($[[GP]])
+; N64:        addiu   $[[R3:[0-9]+]], $zero, 1
+; N64:        sw      $[[R3]], 0($[[R2]])
+; N64:   $[[BB2]]:
+; N64:        jr      $ra
+; N64:        nop
+
+
+; Check the microMIPS version.
+
+; MICROMIPS:        lui     $[[R0:[0-9]+]], %hi(_gp_disp)
+; MICROMIPS:        addiu   $[[R0]], $[[R0]], %lo(_gp_disp)
+; MICROMIPS:        bnez    $4, $[[BB0:BB[0-9_]+]]
+; MICROMIPS:        addu    $[[GP:[0-9]+]], $[[R0]], $25
+
+; Check for long branch expansion:
+; MICROMIPS:          addiu   $sp, $sp, -8
+; MICROMIPS-NEXT:     sw      $ra, 0($sp)
+; MICROMIPS-NEXT:     lui     $1, %hi(($[[BB2:BB[0-9_]+]])-($[[BB1:BB[0-9_]+]]))
+; MICROMIPS-NEXT:     bal     $[[BB1]]
+; MICROMIPS-NEXT:     addiu   $1, $1, %lo(($[[BB2]])-($[[BB1]]))
+; MICROMIPS-NEXT:  $[[BB1]]:
+; MICROMIPS-NEXT:     addu    $1, $ra, $1
+; MICROMIPS-NEXT:     lw      $ra, 0($sp)
+; MICROMIPS-NEXT:     jr      $1
+; MICROMIPS-NEXT:     addiu   $sp, $sp, 8
+
+; MICROMIPS:   $[[BB0]]:
+; MICROMIPS:        lw      $[[R1:[0-9]+]], %got(x)($[[GP]])
+; MICROMIPS:        addiu   $[[R2:[0-9]+]], $zero, 1
+; MICROMIPS:        sw      $[[R2]], 0($[[R1]])
+; MICROMIPS:   $[[BB2]]:
+; MICROMIPS:        jr      $ra
+; MICROMIPS:        nop
+}
diff --git a/test/CodeGen/Mips/micromips-long-branch.ll b/test/CodeGen/Mips/micromips-long-branch.ll
deleted file mode 100644
index 3267f4a729..0000000000
--- a/test/CodeGen/Mips/micromips-long-branch.ll
+++ /dev/null
@@ -1,16437 +0,0 @@
-; RUN: llc %s -march=mipsel -mcpu=mips32r2 -mattr=micromips -filetype=asm \
-; RUN: -relocation-model=pic -O3 -o - | FileCheck %s
-
-@a = common global [10 x i32] zeroinitializer, align 16
-
-; Function Attrs: nounwind uwtable
-define i32 @main() #0 {
-entry:
-  %retval = alloca i32, align 4
-  %i = alloca i32, align 4
-  store i32 0, i32* %retval
-  store i32 0, i32* %i, align 4
-  br label %for.cond
-
-for.cond:
-  %0 = load i32* %i, align 4
-  %cmp = icmp slt i32 %0, 10
-  br i1 %cmp, label %for.body, label %for.end
-
-; CHECK:  addiu $sp, $sp, -8
-; CHECK:  sw  $ra, 0($sp)
-; CHECK:  lui $[[REG1:[0-9]+]], 2
-; CHECK:  addiu $[[REG1]], $[[REG1]], 0
-; CHECK:  addu  $[[REG1]], $ra, $[[REG1]]
-; CHECK:  lw  $ra, 0($sp)
-; CHECK:  jr  $[[REG1]]
-; CHECK:  addiu $sp, $sp, 8
-
-for.body:
-  %1 = load i32* %i, align 4
-  %2 = load i32* %i, align 4
-  %idxprom = sext i32 %2 to i64
-  %arrayidx = getelementptr inbounds [10 x i32]* @a, i32 0, i64 %idxprom
-  store i32 %1, i32* %arrayidx, align 4  %nop0 = alloca i1, i1 0
-  %nop1 = alloca i1, i1 0
-  %nop2 = alloca i1, i1 0
-  %nop3 = alloca i1, i1 0
-  %nop4 = alloca i1, i1 0
-  %nop5 = alloca i1, i1 0
-  %nop6 = alloca i1, i1 0
-  %nop7 = alloca i1, i1 0
-  %nop8 = alloca i1, i1 0
-  %nop9 = alloca i1, i1 0
-  %nop10 = alloca i1, i1 0
-  %nop11 = alloca i1, i1 0
-  %nop12 = alloca i1, i1 0
-  %nop13 = alloca i1, i1 0
-  %nop14 = alloca i1, i1 0
-  %nop15 = alloca i1, i1 0
-  %nop16 = alloca i1, i1 0
-  %nop17 = alloca i1, i1 0
-  %nop18 = alloca i1, i1 0
-  %nop19 = alloca i1, i1 0
-  %nop20 = alloca i1, i1 0
-  %nop21 = alloca i1, i1 0
-  %nop22 = alloca i1, i1 0
-  %nop23 = alloca i1, i1 0
-  %nop24 = alloca i1, i1 0
-  %nop25 = alloca i1, i1 0
-  %nop26 = alloca i1, i1 0
-  %nop27 = alloca i1, i1 0
-  %nop28 = alloca i1, i1 0
-  %nop29 = alloca i1, i1 0
-  %nop30 = alloca i1, i1 0
-  %nop31 = alloca i1, i1 0
-  %nop32 = alloca i1, i1 0
-  %nop33 = alloca i1, i1 0
-  %nop34 = alloca i1, i1 0
-  %nop35 = alloca i1, i1 0
-  %nop36 = alloca i1, i1 0
-  %nop37 = alloca i1, i1 0
-  %nop38 = alloca i1, i1 0
-  %nop39 = alloca i1, i1 0
-  %nop40 = alloca i1, i1 0
-  %nop41 = alloca i1, i1 0
-  %nop42 = alloca i1, i1 0
-  %nop43 = alloca i1, i1 0
-  %nop44 = alloca i1, i1 0
-  %nop45 = alloca i1, i1 0
-  %nop46 = alloca i1, i1 0
-  %nop47 = alloca i1, i1 0
-  %nop48 = alloca i1, i1 0
-  %nop49 = alloca i1, i1 0
-  %nop50 = alloca i1, i1 0
-  %nop51 = alloca i1, i1 0
-  %nop52 = alloca i1, i1 0
-  %nop53 = alloca i1, i1 0
-  %nop54 = alloca i1, i1 0
-  %nop55 = alloca i1, i1 0
-  %nop56 = alloca i1, i1 0
-  %nop57 = alloca i1, i1 0
-  %nop58 = alloca i1, i1 0
-  %nop59 = alloca i1, i1 0
-  %nop60 = alloca i1, i1 0
-  %nop61 = alloca i1, i1 0
-  %nop62 = alloca i1, i1 0
-  %nop63 = alloca i1, i1 0
-  %nop64 = alloca i1, i1 0
-  %nop65 = alloca i1, i1 0
-  %nop66 = alloca i1, i1 0
-  %nop67 = alloca i1, i1 0
-  %nop68 = alloca i1, i1 0
-  %nop69 = alloca i1, i1 0
-  %nop70 = alloca i1, i1 0
-  %nop71 = alloca i1, i1 0
-  %nop72 = alloca i1, i1 0
-  %nop73 = alloca i1, i1 0
-  %nop74 = alloca i1, i1 0
-  %nop75 = alloca i1, i1 0
-  %nop76 = alloca i1, i1 0
-  %nop77 = alloca i1, i1 0
-  %nop78 = alloca i1, i1 0
-  %nop79 = alloca i1, i1 0
-  %nop80 = alloca i1, i1 0
-  %nop81 = alloca i1, i1 0
-  %nop82 = alloca i1, i1 0
-  %nop83 = alloca i1, i1 0
-  %nop84 = alloca i1, i1 0
-  %nop85 = alloca i1, i1 0
-  %nop86 = alloca i1, i1 0
-  %nop87 = alloca i1, i1 0
-  %nop88 = alloca i1, i1 0
-  %nop89 = alloca i1, i1 0
-  %nop90 = alloca i1, i1 0
-  %nop91 = alloca i1, i1 0
-  %nop92 = alloca i1, i1 0
-  %nop93 = alloca i1, i1 0
-  %nop94 = alloca i1, i1 0
-  %nop95 = alloca i1, i1 0
-  %nop96 = alloca i1, i1 0
-  %nop97 = alloca i1, i1 0
-  %nop98 = alloca i1, i1 0
-  %nop99 = alloca i1, i1 0
-  %nop100 = alloca i1, i1 0
-  %nop101 = alloca i1, i1 0
-  %nop102 = alloca i1, i1 0
-  %nop103 = alloca i1, i1 0
-  %nop104 = alloca i1, i1 0
-  %nop105 = alloca i1, i1 0
-  %nop106 = alloca i1, i1 0
-  %nop107 = alloca i1, i1 0
-  %nop108 = alloca i1, i1 0
-  %nop109 = alloca i1, i1 0
-  %nop110 = alloca i1, i1 0
-  %nop111 = alloca i1, i1 0
-  %nop112 = alloca i1, i1 0
-  %nop113 = alloca i1, i1 0
-  %nop114 = alloca i1, i1 0
-  %nop115 = alloca i1, i1 0
-  %nop116 = alloca i1, i1 0
-  %nop117 = alloca i1, i1 0
-  %nop118 = alloca i1, i1 0
-  %nop119 = alloca i1, i1 0
-  %nop120 = alloca i1, i1 0
-  %nop121 = alloca i1, i1 0
-  %nop122 = alloca i1, i1 0
-  %nop123 = alloca i1, i1 0
-  %nop124 = alloca i1, i1 0
-  %nop125 = alloca i1, i1 0
-  %nop126 = alloca i1, i1 0
-  %nop127 = alloca i1, i1 0
-  %nop128 = alloca i1, i1 0
-  %nop129 = alloca i1, i1 0
-  %nop130 = alloca i1, i1 0
-  %nop131 = alloca i1, i1 0
-  %nop132 = alloca i1, i1 0
-  %nop133 = alloca i1, i1 0
-  %nop134 = alloca i1, i1 0
-  %nop135 = alloca i1, i1 0
-  %nop136 = alloca i1, i1 0
-  %nop137 = alloca i1, i1 0
-  %nop138 = alloca i1, i1 0
-  %nop139 = alloca i1, i1 0
-  %nop140 = alloca i1, i1 0
-  %nop141 = alloca i1, i1 0
-  %nop142 = alloca i1, i1 0
-  %nop143 = alloca i1, i1 0
-  %nop144 = alloca i1, i1 0
-  %nop145 = alloca i1, i1 0
-  %nop146 = alloca i1, i1 0
-  %nop147 = alloca i1, i1 0
-  %nop148 = alloca i1, i1 0
-  %nop149 = alloca i1, i1 0
-  %nop150 = alloca i1, i1 0
-  %nop151 = alloca i1, i1 0
-  %nop152 = alloca i1, i1 0
-  %nop153 = alloca i1, i1 0
-  %nop154 = alloca i1, i1 0
-  %nop155 = alloca i1, i1 0
-  %nop156 = alloca i1, i1 0
-  %nop157 = alloca i1, i1 0
-  %nop158 = alloca i1, i1 0
-  %nop159 = alloca i1, i1 0
-  %nop160 = alloca i1, i1 0
-  %nop161 = alloca i1, i1 0
-  %nop162 = alloca i1, i1 0
-  %nop163 = alloca i1, i1 0
-  %nop164 = alloca i1, i1 0
-  %nop165 = alloca i1, i1 0
-  %nop166 = alloca i1, i1 0
-  %nop167 = alloca i1, i1 0
-  %nop168 = alloca i1, i1 0
-  %nop169 = alloca i1, i1 0
-  %nop170 = alloca i1, i1 0
-  %nop171 = alloca i1, i1 0
-  %nop172 = alloca i1, i1 0
-  %nop173 = alloca i1, i1 0
-  %nop174 = alloca i1, i1 0
-  %nop175 = alloca i1, i1 0
-  %nop176 = alloca i1, i1 0
-  %nop177 = alloca i1, i1 0
-  %nop178 = alloca i1, i1 0
-  %nop179 = alloca i1, i1 0
-  %nop180 = alloca i1, i1 0
-  %nop181 = alloca i1, i1 0
-  %nop182 = alloca i1, i1 0
-  %nop183 = alloca i1, i1 0
-  %nop184 = alloca i1, i1 0
-  %nop185 = alloca i1, i1 0
-  %nop186 = alloca i1, i1 0
-  %nop187 = alloca i1, i1 0
-  %nop188 = alloca i1, i1 0
-  %nop189 = alloca i1, i1 0
-  %nop190 = alloca i1, i1 0
-  %nop191 = alloca i1, i1 0
-  %nop192 = alloca i1, i1 0
-  %nop193 = alloca i1, i1 0
-  %nop194 = alloca i1, i1 0
-  %nop195 = alloca i1, i1 0
-  %nop196 = alloca i1, i1 0
-  %nop197 = alloca i1, i1 0
-  %nop198 = alloca i1, i1 0
-  %nop199 = alloca i1, i1 0
-  %nop200 = alloca i1, i1 0
-  %nop201 = alloca i1, i1 0
-  %nop202 = alloca i1, i1 0
-  %nop203 = alloca i1, i1 0
-  %nop204 = alloca i1, i1 0
-  %nop205 = alloca i1, i1 0
-  %nop206 = alloca i1, i1 0
-  %nop207 = alloca i1, i1 0
-  %nop208 = alloca i1, i1 0
-  %nop209 = alloca i1, i1 0
-  %nop210 = alloca i1, i1 0
-  %nop211 = alloca i1, i1 0
-  %nop212 = alloca i1, i1 0
-  %nop213 = alloca i1, i1 0
-  %nop214 = alloca i1, i1 0
-  %nop215 = alloca i1, i1 0
-  %nop216 = alloca i1, i1 0
-  %nop217 = alloca i1, i1 0
-  %nop218 = alloca i1, i1 0
-  %nop219 = alloca i1, i1 0
-  %nop220 = alloca i1, i1 0
-  %nop221 = alloca i1, i1 0
-  %nop222 = alloca i1, i1 0
-  %nop223 = alloca i1, i1 0
-  %nop224 = alloca i1, i1 0
-  %nop225 = alloca i1, i1 0
-  %nop226 = alloca i1, i1 0
-  %nop227 = alloca i1, i1 0
-  %nop228 = alloca i1, i1 0
-  %nop229 = alloca i1, i1 0
-  %nop230 = alloca i1, i1 0
-  %nop231 = alloca i1, i1 0
-  %nop232 = alloca i1, i1 0
-  %nop233 = alloca i1, i1 0
-  %nop234 = alloca i1, i1 0
-  %nop235 = alloca i1, i1 0
-  %nop236 = alloca i1, i1 0
-  %nop237 = alloca i1, i1 0
-  %nop238 = alloca i1, i1 0
-  %nop239 = alloca i1, i1 0
-  %nop240 = alloca i1, i1 0
-  %nop241 = alloca i1, i1 0
-  %nop242 = alloca i1, i1 0
-  %nop243 = alloca i1, i1 0
-  %nop244 = alloca i1, i1 0
-  %nop245 = alloca i1, i1 0
-  %nop246 = alloca i1, i1 0
-  %nop247 = alloca i1, i1 0
-  %nop248 = alloca i1, i1 0
-  %nop249 = alloca i1, i1 0
-  %nop250 = alloca i1, i1 0
-  %nop251 = alloca i1, i1 0
-  %nop252 = alloca i1, i1 0
-  %nop253 = alloca i1, i1 0
-  %nop254 = alloca i1, i1 0
-  %nop255 = alloca i1, i1 0
-  %nop256 = alloca i1, i1 0
-  %nop257 = alloca i1, i1 0
-  %nop258 = alloca i1, i1 0
-  %nop259 = alloca i1, i1 0
-  %nop260 = alloca i1, i1 0
-  %nop261 = alloca i1, i1 0
-  %nop262 = alloca i1, i1 0
-  %nop263 = alloca i1, i1 0
-  %nop264 = alloca i1, i1 0
-  %nop265 = alloca i1, i1 0
-  %nop266 = alloca i1, i1 0
-  %nop267 = alloca i1, i1 0
-  %nop268 = alloca i1, i1 0
-  %nop269 = alloca i1, i1 0
-  %nop270 = alloca i1, i1 0
-  %nop271 = alloca i1, i1 0
-  %nop272 = alloca i1, i1 0
-  %nop273 = alloca i1, i1 0
-  %nop274 = alloca i1, i1 0
-  %nop275 = alloca i1, i1 0
-  %nop276 = alloca i1, i1 0
-  %nop277 = alloca i1, i1 0
-  %nop278 = alloca i1, i1 0
-  %nop279 = alloca i1, i1 0
-  %nop280 = alloca i1, i1 0
-  %nop281 = alloca i1, i1 0
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-  %nop305 = alloca i1, i1 0
-  %nop306 = alloca i1, i1 0
-  %nop307 = alloca i1, i1 0
-  %nop308 = alloca i1, i1 0
-  %nop309 = alloca i1, i1 0
-  %nop310 = alloca i1, i1 0
-  %nop311 = alloca i1, i1 0
-  %nop312 = alloca i1, i1 0
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-  %nop314 = alloca i1, i1 0
-  %nop315 = alloca i1, i1 0
-  %nop316 = alloca i1, i1 0
-  %nop317 = alloca i1, i1 0
-  %nop318 = alloca i1, i1 0
-  %nop319 = alloca i1, i1 0
-  %nop320 = alloca i1, i1 0
-  %nop321 = alloca i1, i1 0
-  %nop322 = alloca i1, i1 0
-  %nop323 = alloca i1, i1 0
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-  %nop327 = alloca i1, i1 0
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-  %nop337 = alloca i1, i1 0
-  %nop338 = alloca i1, i1 0
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-  %nop341 = alloca i1, i1 0
-  %nop342 = alloca i1, i1 0
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-  %nop386 = alloca i1, i1 0
-  %nop387 = alloca i1, i1 0
-  %nop388 = alloca i1, i1 0
-  %nop389 = alloca i1, i1 0
-  %nop390 = alloca i1, i1 0
-  %nop391 = alloca i1, i1 0
-  %nop392 = alloca i1, i1 0
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-  %nop401 = alloca i1, i1 0
-  %nop402 = alloca i1, i1 0
-  %nop403 = alloca i1, i1 0
-  %nop404 = alloca i1, i1 0
-  %nop405 = alloca i1, i1 0
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-  %nop407 = alloca i1, i1 0
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-  %nop409 = alloca i1, i1 0
-  %nop410 = alloca i1, i1 0
-  %nop411 = alloca i1, i1 0
-  %nop412 = alloca i1, i1 0
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-  %nop437 = alloca i1, i1 0
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-  %nop468 = alloca i1, i1 0
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-  %nop509 = alloca i1, i1 0
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-  %nop511 = alloca i1, i1 0
-  %nop512 = alloca i1, i1 0
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-  %nop528 = alloca i1, i1 0
-  %nop529 = alloca i1, i1 0
-  %nop530 = alloca i1, i1 0
-  %nop531 = alloca i1, i1 0
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-  %nop535 = alloca i1, i1 0
-  %nop536 = alloca i1, i1 0
-  %nop537 = alloca i1, i1 0
-  %nop538 = alloca i1, i1 0
-  %nop539 = alloca i1, i1 0
-  %nop540 = alloca i1, i1 0
-  %nop541 = alloca i1, i1 0
-  %nop542 = alloca i1, i1 0
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-  %nop567 = alloca i1, i1 0
-  %nop568 = alloca i1, i1 0
-  %nop569 = alloca i1, i1 0
-  %nop570 = alloca i1, i1 0
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-  %nop582 = alloca i1, i1 0
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-  %nop610 = alloca i1, i1 0
-  %nop611 = alloca i1, i1 0
-  %nop612 = alloca i1, i1 0
-  %nop613 = alloca i1, i1 0
-  %nop614 = alloca i1, i1 0
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-  %nop617 = alloca i1, i1 0
-  %nop618 = alloca i1, i1 0
-  %nop619 = alloca i1, i1 0
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-  %nop621 = alloca i1, i1 0
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-  %nop628 = alloca i1, i1 0
-  %nop629 = alloca i1, i1 0
-  %nop630 = alloca i1, i1 0
-  %nop631 = alloca i1, i1 0
-  %nop632 = alloca i1, i1 0
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-  %nop634 = alloca i1, i1 0
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-  %nop786 = alloca i1, i1 0
-  %nop787 = alloca i1, i1 0
-  %nop788 = alloca i1, i1 0
-  %nop789 = alloca i1, i1 0
-  %nop790 = alloca i1, i1 0
-  %nop791 = alloca i1, i1 0
-  %nop792 = alloca i1, i1 0
-  %nop793 = alloca i1, i1 0
-  %nop794 = alloca i1, i1 0
-  %nop795 = alloca i1, i1 0
-  %nop796 = alloca i1, i1 0
-  %nop797 = alloca i1, i1 0
-  %nop798 = alloca i1, i1 0
-  %nop799 = alloca i1, i1 0
-  %nop800 = alloca i1, i1 0
-  %nop801 = alloca i1, i1 0
-  %nop802 = alloca i1, i1 0
-  %nop803 = alloca i1, i1 0
-  %nop804 = alloca i1, i1 0
-  %nop805 = alloca i1, i1 0
-  %nop806 = alloca i1, i1 0
-  %nop807 = alloca i1, i1 0
-  %nop808 = alloca i1, i1 0
-  %nop809 = alloca i1, i1 0
-  %nop810 = alloca i1, i1 0
-  %nop811 = alloca i1, i1 0
-  %nop812 = alloca i1, i1 0
-  %nop813 = alloca i1, i1 0
-  %nop814 = alloca i1, i1 0
-  %nop815 = alloca i1, i1 0
-  %nop816 = alloca i1, i1 0
-  %nop817 = alloca i1, i1 0
-  %nop818 = alloca i1, i1 0
-  %nop819 = alloca i1, i1 0
-  %nop820 = alloca i1, i1 0
-  %nop821 = alloca i1, i1 0
-  %nop822 = alloca i1, i1 0
-  %nop823 = alloca i1, i1 0
-  %nop824 = alloca i1, i1 0
-  %nop825 = alloca i1, i1 0
-  %nop826 = alloca i1, i1 0
-  %nop827 = alloca i1, i1 0
-  %nop828 = alloca i1, i1 0
-  %nop829 = alloca i1, i1 0
-  %nop830 = alloca i1, i1 0
-  %nop831 = alloca i1, i1 0
-  %nop832 = alloca i1, i1 0
-  %nop833 = alloca i1, i1 0
-  %nop834 = alloca i1, i1 0
-  %nop835 = alloca i1, i1 0
-  %nop836 = alloca i1, i1 0
-  %nop837 = alloca i1, i1 0
-  %nop838 = alloca i1, i1 0
-  %nop839 = alloca i1, i1 0
-  %nop840 = alloca i1, i1 0
-  %nop841 = alloca i1, i1 0
-  %nop842 = alloca i1, i1 0
-  %nop843 = alloca i1, i1 0
-  %nop844 = alloca i1, i1 0
-  %nop845 = alloca i1, i1 0
-  %nop846 = alloca i1, i1 0
-  %nop847 = alloca i1, i1 0
-  %nop848 = alloca i1, i1 0
-  %nop849 = alloca i1, i1 0
-  %nop850 = alloca i1, i1 0
-  %nop851 = alloca i1, i1 0
-  %nop852 = alloca i1, i1 0
-  %nop853 = alloca i1, i1 0
-  %nop854 = alloca i1, i1 0
-  %nop855 = alloca i1, i1 0
-  %nop856 = alloca i1, i1 0
-  %nop857 = alloca i1, i1 0
-  %nop858 = alloca i1, i1 0
-  %nop859 = alloca i1, i1 0
-  %nop860 = alloca i1, i1 0
-  %nop861 = alloca i1, i1 0
-  %nop862 = alloca i1, i1 0
-  %nop863 = alloca i1, i1 0
-  %nop864 = alloca i1, i1 0
-  %nop865 = alloca i1, i1 0
-  %nop866 = alloca i1, i1 0
-  %nop867 = alloca i1, i1 0
-  %nop868 = alloca i1, i1 0
-  %nop869 = alloca i1, i1 0
-  %nop870 = alloca i1, i1 0
-  %nop871 = alloca i1, i1 0
-  %nop872 = alloca i1, i1 0
-  %nop873 = alloca i1, i1 0
-  %nop874 = alloca i1, i1 0
-  %nop875 = alloca i1, i1 0
-  %nop876 = alloca i1, i1 0
-  %nop877 = alloca i1, i1 0
-  %nop878 = alloca i1, i1 0
-  %nop879 = alloca i1, i1 0
-  %nop880 = alloca i1, i1 0
-  %nop881 = alloca i1, i1 0
-  %nop882 = alloca i1, i1 0
-  %nop883 = alloca i1, i1 0
-  %nop884 = alloca i1, i1 0
-  %nop885 = alloca i1, i1 0
-  %nop886 = alloca i1, i1 0
-  %nop887 = alloca i1, i1 0
-  %nop888 = alloca i1, i1 0
-  %nop889 = alloca i1, i1 0
-  %nop890 = alloca i1, i1 0
-  %nop891 = alloca i1, i1 0
-  %nop892 = alloca i1, i1 0
-  %nop893 = alloca i1, i1 0
-  %nop894 = alloca i1, i1 0
-  %nop895 = alloca i1, i1 0
-  %nop896 = alloca i1, i1 0
-  %nop897 = alloca i1, i1 0
-  %nop898 = alloca i1, i1 0
-  %nop899 = alloca i1, i1 0
-  %nop900 = alloca i1, i1 0
-  %nop901 = alloca i1, i1 0
-  %nop902 = alloca i1, i1 0
-  %nop903 = alloca i1, i1 0
-  %nop904 = alloca i1, i1 0
-  %nop905 = alloca i1, i1 0
-  %nop906 = alloca i1, i1 0
-  %nop907 = alloca i1, i1 0
-  %nop908 = alloca i1, i1 0
-  %nop909 = alloca i1, i1 0
-  %nop910 = alloca i1, i1 0
-  %nop911 = alloca i1, i1 0
-  %nop912 = alloca i1, i1 0
-  %nop913 = alloca i1, i1 0
-  %nop914 = alloca i1, i1 0
-  %nop915 = alloca i1, i1 0
-  %nop916 = alloca i1, i1 0
-  %nop917 = alloca i1, i1 0
-  %nop918 = alloca i1, i1 0
-  %nop919 = alloca i1, i1 0
-  %nop920 = alloca i1, i1 0
-  %nop921 = alloca i1, i1 0
-  %nop922 = alloca i1, i1 0
-  %nop923 = alloca i1, i1 0
-  %nop924 = alloca i1, i1 0
-  %nop925 = alloca i1, i1 0
-  %nop926 = alloca i1, i1 0
-  %nop927 = alloca i1, i1 0
-  %nop928 = alloca i1, i1 0
-  %nop929 = alloca i1, i1 0
-  %nop930 = alloca i1, i1 0
-  %nop931 = alloca i1, i1 0
-  %nop932 = alloca i1, i1 0
-  %nop933 = alloca i1, i1 0
-  %nop934 = alloca i1, i1 0
-  %nop935 = alloca i1, i1 0
-  %nop936 = alloca i1, i1 0
-  %nop937 = alloca i1, i1 0
-  %nop938 = alloca i1, i1 0
-  %nop939 = alloca i1, i1 0
-  %nop940 = alloca i1, i1 0
-  %nop941 = alloca i1, i1 0
-  %nop942 = alloca i1, i1 0
-  %nop943 = alloca i1, i1 0
-  %nop944 = alloca i1, i1 0
-  %nop945 = alloca i1, i1 0
-  %nop946 = alloca i1, i1 0
-  %nop947 = alloca i1, i1 0
-  %nop948 = alloca i1, i1 0
-  %nop949 = alloca i1, i1 0
-  %nop950 = alloca i1, i1 0
-  %nop951 = alloca i1, i1 0
-  %nop952 = alloca i1, i1 0
-  %nop953 = alloca i1, i1 0
-  %nop954 = alloca i1, i1 0
-  %nop955 = alloca i1, i1 0
-  %nop956 = alloca i1, i1 0
-  %nop957 = alloca i1, i1 0
-  %nop958 = alloca i1, i1 0
-  %nop959 = alloca i1, i1 0
-  %nop960 = alloca i1, i1 0
-  %nop961 = alloca i1, i1 0
-  %nop962 = alloca i1, i1 0
-  %nop963 = alloca i1, i1 0
-  %nop964 = alloca i1, i1 0
-  %nop965 = alloca i1, i1 0
-  %nop966 = alloca i1, i1 0
-  %nop967 = alloca i1, i1 0
-  %nop968 = alloca i1, i1 0
-  %nop969 = alloca i1, i1 0
-  %nop970 = alloca i1, i1 0
-  %nop971 = alloca i1, i1 0
-  %nop972 = alloca i1, i1 0
-  %nop973 = alloca i1, i1 0
-  %nop974 = alloca i1, i1 0
-  %nop975 = alloca i1, i1 0
-  %nop976 = alloca i1, i1 0
-  %nop977 = alloca i1, i1 0
-  %nop978 = alloca i1, i1 0
-  %nop979 = alloca i1, i1 0
-  %nop980 = alloca i1, i1 0
-  %nop981 = alloca i1, i1 0
-  %nop982 = alloca i1, i1 0
-  %nop983 = alloca i1, i1 0
-  %nop984 = alloca i1, i1 0
-  %nop985 = alloca i1, i1 0
-  %nop986 = alloca i1, i1 0
-  %nop987 = alloca i1, i1 0
-  %nop988 = alloca i1, i1 0
-  %nop989 = alloca i1, i1 0
-  %nop990 = alloca i1, i1 0
-  %nop991 = alloca i1, i1 0
-  %nop992 = alloca i1, i1 0
-  %nop993 = alloca i1, i1 0
-  %nop994 = alloca i1, i1 0
-  %nop995 = alloca i1, i1 0
-  %nop996 = alloca i1, i1 0
-  %nop997 = alloca i1, i1 0
-  %nop998 = alloca i1, i1 0
-  %nop999 = alloca i1, i1 0
-  %nop1000 = alloca i1, i1 0
-  %nop1001 = alloca i1, i1 0
-  %nop1002 = alloca i1, i1 0
-  %nop1003 = alloca i1, i1 0
-  %nop1004 = alloca i1, i1 0
-  %nop1005 = alloca i1, i1 0
-  %nop1006 = alloca i1, i1 0
-  %nop1007 = alloca i1, i1 0
-  %nop1008 = alloca i1, i1 0
-  %nop1009 = alloca i1, i1 0
-  %nop1010 = alloca i1, i1 0
-  %nop1011 = alloca i1, i1 0
-  %nop1012 = alloca i1, i1 0
-  %nop1013 = alloca i1, i1 0
-  %nop1014 = alloca i1, i1 0
-  %nop1015 = alloca i1, i1 0
-  %nop1016 = alloca i1, i1 0
-  %nop1017 = alloca i1, i1 0
-  %nop1018 = alloca i1, i1 0
-  %nop1019 = alloca i1, i1 0
-  %nop1020 = alloca i1, i1 0
-  %nop1021 = alloca i1, i1 0
-  %nop1022 = alloca i1, i1 0
-  %nop1023 = alloca i1, i1 0
-  %nop1024 = alloca i1, i1 0
-  %nop1025 = alloca i1, i1 0
-  %nop1026 = alloca i1, i1 0
-  %nop1027 = alloca i1, i1 0
-  %nop1028 = alloca i1, i1 0
-  %nop1029 = alloca i1, i1 0
-  %nop1030 = alloca i1, i1 0
-  %nop1031 = alloca i1, i1 0
-  %nop1032 = alloca i1, i1 0
-  %nop1033 = alloca i1, i1 0
-  %nop1034 = alloca i1, i1 0
-  %nop1035 = alloca i1, i1 0
-  %nop1036 = alloca i1, i1 0
-  %nop1037 = alloca i1, i1 0
-  %nop1038 = alloca i1, i1 0
-  %nop1039 = alloca i1, i1 0
-  %nop1040 = alloca i1, i1 0
-  %nop1041 = alloca i1, i1 0
-  %nop1042 = alloca i1, i1 0
-  %nop1043 = alloca i1, i1 0
-  %nop1044 = alloca i1, i1 0
-  %nop1045 = alloca i1, i1 0
-  %nop1046 = alloca i1, i1 0
-  %nop1047 = alloca i1, i1 0
-  %nop1048 = alloca i1, i1 0
-  %nop1049 = alloca i1, i1 0
-  %nop1050 = alloca i1, i1 0
-  %nop1051 = alloca i1, i1 0
-  %nop1052 = alloca i1, i1 0
-  %nop1053 = alloca i1, i1 0
-  %nop1054 = alloca i1, i1 0
-  %nop1055 = alloca i1, i1 0
-  %nop1056 = alloca i1, i1 0
-  %nop1057 = alloca i1, i1 0
-  %nop1058 = alloca i1, i1 0
-  %nop1059 = alloca i1, i1 0
-  %nop1060 = alloca i1, i1 0
-  %nop1061 = alloca i1, i1 0
-  %nop1062 = alloca i1, i1 0
-  %nop1063 = alloca i1, i1 0
-  %nop1064 = alloca i1, i1 0
-  %nop1065 = alloca i1, i1 0
-  %nop1066 = alloca i1, i1 0
-  %nop1067 = alloca i1, i1 0
-  %nop1068 = alloca i1, i1 0
-  %nop1069 = alloca i1, i1 0
-  %nop1070 = alloca i1, i1 0
-  %nop1071 = alloca i1, i1 0
-  %nop1072 = alloca i1, i1 0
-  %nop1073 = alloca i1, i1 0
-  %nop1074 = alloca i1, i1 0
-  %nop1075 = alloca i1, i1 0
-  %nop1076 = alloca i1, i1 0
-  %nop1077 = alloca i1, i1 0
-  %nop1078 = alloca i1, i1 0
-  %nop1079 = alloca i1, i1 0
-  %nop1080 = alloca i1, i1 0
-  %nop1081 = alloca i1, i1 0
-  %nop1082 = alloca i1, i1 0
-  %nop1083 = alloca i1, i1 0
-  %nop1084 = alloca i1, i1 0
-  %nop1085 = alloca i1, i1 0
-  %nop1086 = alloca i1, i1 0
-  %nop1087 = alloca i1, i1 0
-  %nop1088 = alloca i1, i1 0
-  %nop1089 = alloca i1, i1 0
-  %nop1090 = alloca i1, i1 0
-  %nop1091 = alloca i1, i1 0
-  %nop1092 = alloca i1, i1 0
-  %nop1093 = alloca i1, i1 0
-  %nop1094 = alloca i1, i1 0
-  %nop1095 = alloca i1, i1 0
-  %nop1096 = alloca i1, i1 0
-  %nop1097 = alloca i1, i1 0
-  %nop1098 = alloca i1, i1 0
-  %nop1099 = alloca i1, i1 0
-  %nop1100 = alloca i1, i1 0
-  %nop1101 = alloca i1, i1 0
-  %nop1102 = alloca i1, i1 0
-  %nop1103 = alloca i1, i1 0
-  %nop1104 = alloca i1, i1 0
-  %nop1105 = alloca i1, i1 0
-  %nop1106 = alloca i1, i1 0
-  %nop1107 = alloca i1, i1 0
-  %nop1108 = alloca i1, i1 0
-  %nop1109 = alloca i1, i1 0
-  %nop1110 = alloca i1, i1 0
-  %nop1111 = alloca i1, i1 0
-  %nop1112 = alloca i1, i1 0
-  %nop1113 = alloca i1, i1 0
-  %nop1114 = alloca i1, i1 0
-  %nop1115 = alloca i1, i1 0
-  %nop1116 = alloca i1, i1 0
-  %nop1117 = alloca i1, i1 0
-  %nop1118 = alloca i1, i1 0
-  %nop1119 = alloca i1, i1 0
-  %nop1120 = alloca i1, i1 0
-  %nop1121 = alloca i1, i1 0
-  %nop1122 = alloca i1, i1 0
-  %nop1123 = alloca i1, i1 0
-  %nop1124 = alloca i1, i1 0
-  %nop1125 = alloca i1, i1 0
-  %nop1126 = alloca i1, i1 0
-  %nop1127 = alloca i1, i1 0
-  %nop1128 = alloca i1, i1 0
-  %nop1129 = alloca i1, i1 0
-  %nop1130 = alloca i1, i1 0
-  %nop1131 = alloca i1, i1 0
-  %nop1132 = alloca i1, i1 0
-  %nop1133 = alloca i1, i1 0
-  %nop1134 = alloca i1, i1 0
-  %nop1135 = alloca i1, i1 0
-  %nop1136 = alloca i1, i1 0
-  %nop1137 = alloca i1, i1 0
-  %nop1138 = alloca i1, i1 0
-  %nop1139 = alloca i1, i1 0
-  %nop1140 = alloca i1, i1 0
-  %nop1141 = alloca i1, i1 0
-  %nop1142 = alloca i1, i1 0
-  %nop1143 = alloca i1, i1 0
-  %nop1144 = alloca i1, i1 0
-  %nop1145 = alloca i1, i1 0
-  %nop1146 = alloca i1, i1 0
-  %nop1147 = alloca i1, i1 0
-  %nop1148 = alloca i1, i1 0
-  %nop1149 = alloca i1, i1 0
-  %nop1150 = alloca i1, i1 0
-  %nop1151 = alloca i1, i1 0
-  %nop1152 = alloca i1, i1 0
-  %nop1153 = alloca i1, i1 0
-  %nop1154 = alloca i1, i1 0
-  %nop1155 = alloca i1, i1 0
-  %nop1156 = alloca i1, i1 0
-  %nop1157 = alloca i1, i1 0
-  %nop1158 = alloca i1, i1 0
-  %nop1159 = alloca i1, i1 0
-  %nop1160 = alloca i1, i1 0
-  %nop1161 = alloca i1, i1 0
-  %nop1162 = alloca i1, i1 0
-  %nop1163 = alloca i1, i1 0
-  %nop1164 = alloca i1, i1 0
-  %nop1165 = alloca i1, i1 0
-  %nop1166 = alloca i1, i1 0
-  %nop1167 = alloca i1, i1 0
-  %nop1168 = alloca i1, i1 0
-  %nop1169 = alloca i1, i1 0
-  %nop1170 = alloca i1, i1 0
-  %nop1171 = alloca i1, i1 0
-  %nop1172 = alloca i1, i1 0
-  %nop1173 = alloca i1, i1 0
-  %nop1174 = alloca i1, i1 0
-  %nop1175 = alloca i1, i1 0
-  %nop1176 = alloca i1, i1 0
-  %nop1177 = alloca i1, i1 0
-  %nop1178 = alloca i1, i1 0
-  %nop1179 = alloca i1, i1 0
-  %nop1180 = alloca i1, i1 0
-  %nop1181 = alloca i1, i1 0
-  %nop1182 = alloca i1, i1 0
-  %nop1183 = alloca i1, i1 0
-  %nop1184 = alloca i1, i1 0
-  %nop1185 = alloca i1, i1 0
-  %nop1186 = alloca i1, i1 0
-  %nop1187 = alloca i1, i1 0
-  %nop1188 = alloca i1, i1 0
-  %nop1189 = alloca i1, i1 0
-  %nop1190 = alloca i1, i1 0
-  %nop1191 = alloca i1, i1 0
-  %nop1192 = alloca i1, i1 0
-  %nop1193 = alloca i1, i1 0
-  %nop1194 = alloca i1, i1 0
-  %nop1195 = alloca i1, i1 0
-  %nop1196 = alloca i1, i1 0
-  %nop1197 = alloca i1, i1 0
-  %nop1198 = alloca i1, i1 0
-  %nop1199 = alloca i1, i1 0
-  %nop1200 = alloca i1, i1 0
-  %nop1201 = alloca i1, i1 0
-  %nop1202 = alloca i1, i1 0
-  %nop1203 = alloca i1, i1 0
-  %nop1204 = alloca i1, i1 0
-  %nop1205 = alloca i1, i1 0
-  %nop1206 = alloca i1, i1 0
-  %nop1207 = alloca i1, i1 0
-  %nop1208 = alloca i1, i1 0
-  %nop1209 = alloca i1, i1 0
-  %nop1210 = alloca i1, i1 0
-  %nop1211 = alloca i1, i1 0
-  %nop1212 = alloca i1, i1 0
-  %nop1213 = alloca i1, i1 0
-  %nop1214 = alloca i1, i1 0
-  %nop1215 = alloca i1, i1 0
-  %nop1216 = alloca i1, i1 0
-  %nop1217 = alloca i1, i1 0
-  %nop1218 = alloca i1, i1 0
-  %nop1219 = alloca i1, i1 0
-  %nop1220 = alloca i1, i1 0
-  %nop1221 = alloca i1, i1 0
-  %nop1222 = alloca i1, i1 0
-  %nop1223 = alloca i1, i1 0
-  %nop1224 = alloca i1, i1 0
-  %nop1225 = alloca i1, i1 0
-  %nop1226 = alloca i1, i1 0
-  %nop1227 = alloca i1, i1 0
-  %nop1228 = alloca i1, i1 0
-  %nop1229 = alloca i1, i1 0
-  %nop1230 = alloca i1, i1 0
-  %nop1231 = alloca i1, i1 0
-  %nop1232 = alloca i1, i1 0
-  %nop1233 = alloca i1, i1 0
-  %nop1234 = alloca i1, i1 0
-  %nop1235 = alloca i1, i1 0
-  %nop1236 = alloca i1, i1 0
-  %nop1237 = alloca i1, i1 0
-  %nop1238 = alloca i1, i1 0
-  %nop1239 = alloca i1, i1 0
-  %nop1240 = alloca i1, i1 0
-  %nop1241 = alloca i1, i1 0
-  %nop1242 = alloca i1, i1 0
-  %nop1243 = alloca i1, i1 0
-  %nop1244 = alloca i1, i1 0
-  %nop1245 = alloca i1, i1 0
-  %nop1246 = alloca i1, i1 0
-  %nop1247 = alloca i1, i1 0
-  %nop1248 = alloca i1, i1 0
-  %nop1249 = alloca i1, i1 0
-  %nop1250 = alloca i1, i1 0
-  %nop1251 = alloca i1, i1 0
-  %nop1252 = alloca i1, i1 0
-  %nop1253 = alloca i1, i1 0
-  %nop1254 = alloca i1, i1 0
-  %nop1255 = alloca i1, i1 0
-  %nop1256 = alloca i1, i1 0
-  %nop1257 = alloca i1, i1 0
-  %nop1258 = alloca i1, i1 0
-  %nop1259 = alloca i1, i1 0
-  %nop1260 = alloca i1, i1 0
-  %nop1261 = alloca i1, i1 0
-  %nop1262 = alloca i1, i1 0
-  %nop1263 = alloca i1, i1 0
-  %nop1264 = alloca i1, i1 0
-  %nop1265 = alloca i1, i1 0
-  %nop1266 = alloca i1, i1 0
-  %nop1267 = alloca i1, i1 0
-  %nop1268 = alloca i1, i1 0
-  %nop1269 = alloca i1, i1 0
-  %nop1270 = alloca i1, i1 0
-  %nop1271 = alloca i1, i1 0
-  %nop1272 = alloca i1, i1 0
-  %nop1273 = alloca i1, i1 0
-  %nop1274 = alloca i1, i1 0
-  %nop1275 = alloca i1, i1 0
-  %nop1276 = alloca i1, i1 0
-  %nop1277 = alloca i1, i1 0
-  %nop1278 = alloca i1, i1 0
-  %nop1279 = alloca i1, i1 0
-  %nop1280 = alloca i1, i1 0
-  %nop1281 = alloca i1, i1 0
-  %nop1282 = alloca i1, i1 0
-  %nop1283 = alloca i1, i1 0
-  %nop1284 = alloca i1, i1 0
-  %nop1285 = alloca i1, i1 0
-  %nop1286 = alloca i1, i1 0
-  %nop1287 = alloca i1, i1 0
-  %nop1288 = alloca i1, i1 0
-  %nop1289 = alloca i1, i1 0
-  %nop1290 = alloca i1, i1 0
-  %nop1291 = alloca i1, i1 0
-  %nop1292 = alloca i1, i1 0
-  %nop1293 = alloca i1, i1 0
-  %nop1294 = alloca i1, i1 0
-  %nop1295 = alloca i1, i1 0
-  %nop1296 = alloca i1, i1 0
-  %nop1297 = alloca i1, i1 0
-  %nop1298 = alloca i1, i1 0
-  %nop1299 = alloca i1, i1 0
-  %nop1300 = alloca i1, i1 0
-  %nop1301 = alloca i1, i1 0
-  %nop1302 = alloca i1, i1 0
-  %nop1303 = alloca i1, i1 0
-  %nop1304 = alloca i1, i1 0
-  %nop1305 = alloca i1, i1 0
-  %nop1306 = alloca i1, i1 0
-  %nop1307 = alloca i1, i1 0
-  %nop1308 = alloca i1, i1 0
-  %nop1309 = alloca i1, i1 0
-  %nop1310 = alloca i1, i1 0
-  %nop1311 = alloca i1, i1 0
-  %nop1312 = alloca i1, i1 0
-  %nop1313 = alloca i1, i1 0
-  %nop1314 = alloca i1, i1 0
-  %nop1315 = alloca i1, i1 0
-  %nop1316 = alloca i1, i1 0
-  %nop1317 = alloca i1, i1 0
-  %nop1318 = alloca i1, i1 0
-  %nop1319 = alloca i1, i1 0
-  %nop1320 = alloca i1, i1 0
-  %nop1321 = alloca i1, i1 0
-  %nop1322 = alloca i1, i1 0
-  %nop1323 = alloca i1, i1 0
-  %nop1324 = alloca i1, i1 0
-  %nop1325 = alloca i1, i1 0
-  %nop1326 = alloca i1, i1 0
-  %nop1327 = alloca i1, i1 0
-  %nop1328 = alloca i1, i1 0
-  %nop1329 = alloca i1, i1 0
-  %nop1330 = alloca i1, i1 0
-  %nop1331 = alloca i1, i1 0
-  %nop1332 = alloca i1, i1 0
-  %nop1333 = alloca i1, i1 0
-  %nop1334 = alloca i1, i1 0
-  %nop1335 = alloca i1, i1 0
-  %nop1336 = alloca i1, i1 0
-  %nop1337 = alloca i1, i1 0
-  %nop1338 = alloca i1, i1 0
-  %nop1339 = alloca i1, i1 0
-  %nop1340 = alloca i1, i1 0
-  %nop1341 = alloca i1, i1 0
-  %nop1342 = alloca i1, i1 0
-  %nop1343 = alloca i1, i1 0
-  %nop1344 = alloca i1, i1 0
-  %nop1345 = alloca i1, i1 0
-  %nop1346 = alloca i1, i1 0
-  %nop1347 = alloca i1, i1 0
-  %nop1348 = alloca i1, i1 0
-  %nop1349 = alloca i1, i1 0
-  %nop1350 = alloca i1, i1 0
-  %nop1351 = alloca i1, i1 0
-  %nop1352 = alloca i1, i1 0
-  %nop1353 = alloca i1, i1 0
-  %nop1354 = alloca i1, i1 0
-  %nop1355 = alloca i1, i1 0
-  %nop1356 = alloca i1, i1 0
-  %nop1357 = alloca i1, i1 0
-  %nop1358 = alloca i1, i1 0
-  %nop1359 = alloca i1, i1 0
-  %nop1360 = alloca i1, i1 0
-  %nop1361 = alloca i1, i1 0
-  %nop1362 = alloca i1, i1 0
-  %nop1363 = alloca i1, i1 0
-  %nop1364 = alloca i1, i1 0
-  %nop1365 = alloca i1, i1 0
-  %nop1366 = alloca i1, i1 0
-  %nop1367 = alloca i1, i1 0
-  %nop1368 = alloca i1, i1 0
-  %nop1369 = alloca i1, i1 0
-  %nop1370 = alloca i1, i1 0
-  %nop1371 = alloca i1, i1 0
-  %nop1372 = alloca i1, i1 0
-  %nop1373 = alloca i1, i1 0
-  %nop1374 = alloca i1, i1 0
-  %nop1375 = alloca i1, i1 0
-  %nop1376 = alloca i1, i1 0
-  %nop1377 = alloca i1, i1 0
-  %nop1378 = alloca i1, i1 0
-  %nop1379 = alloca i1, i1 0
-  %nop1380 = alloca i1, i1 0
-  %nop1381 = alloca i1, i1 0
-  %nop1382 = alloca i1, i1 0
-  %nop1383 = alloca i1, i1 0
-  %nop1384 = alloca i1, i1 0
-  %nop1385 = alloca i1, i1 0
-  %nop1386 = alloca i1, i1 0
-  %nop1387 = alloca i1, i1 0
-  %nop1388 = alloca i1, i1 0
-  %nop1389 = alloca i1, i1 0
-  %nop1390 = alloca i1, i1 0
-  %nop1391 = alloca i1, i1 0
-  %nop1392 = alloca i1, i1 0
-  %nop1393 = alloca i1, i1 0
-  %nop1394 = alloca i1, i1 0
-  %nop1395 = alloca i1, i1 0
-  %nop1396 = alloca i1, i1 0
-  %nop1397 = alloca i1, i1 0
-  %nop1398 = alloca i1, i1 0
-  %nop1399 = alloca i1, i1 0
-  %nop1400 = alloca i1, i1 0
-  %nop1401 = alloca i1, i1 0
-  %nop1402 = alloca i1, i1 0
-  %nop1403 = alloca i1, i1 0
-  %nop1404 = alloca i1, i1 0
-  %nop1405 = alloca i1, i1 0
-  %nop1406 = alloca i1, i1 0
-  %nop1407 = alloca i1, i1 0
-  %nop1408 = alloca i1, i1 0
-  %nop1409 = alloca i1, i1 0
-  %nop1410 = alloca i1, i1 0
-  %nop1411 = alloca i1, i1 0
-  %nop1412 = alloca i1, i1 0
-  %nop1413 = alloca i1, i1 0
-  %nop1414 = alloca i1, i1 0
-  %nop1415 = alloca i1, i1 0
-  %nop1416 = alloca i1, i1 0
-  %nop1417 = alloca i1, i1 0
-  %nop1418 = alloca i1, i1 0
-  %nop1419 = alloca i1, i1 0
-  %nop1420 = alloca i1, i1 0
-  %nop1421 = alloca i1, i1 0
-  %nop1422 = alloca i1, i1 0
-  %nop1423 = alloca i1, i1 0
-  %nop1424 = alloca i1, i1 0
-  %nop1425 = alloca i1, i1 0
-  %nop1426 = alloca i1, i1 0
-  %nop1427 = alloca i1, i1 0
-  %nop1428 = alloca i1, i1 0
-  %nop1429 = alloca i1, i1 0
-  %nop1430 = alloca i1, i1 0
-  %nop1431 = alloca i1, i1 0
-  %nop1432 = alloca i1, i1 0
-  %nop1433 = alloca i1, i1 0
-  %nop1434 = alloca i1, i1 0
-  %nop1435 = alloca i1, i1 0
-  %nop1436 = alloca i1, i1 0
-  %nop1437 = alloca i1, i1 0
-  %nop1438 = alloca i1, i1 0
-  %nop1439 = alloca i1, i1 0
-  %nop1440 = alloca i1, i1 0
-  %nop1441 = alloca i1, i1 0
-  %nop1442 = alloca i1, i1 0
-  %nop1443 = alloca i1, i1 0
-  %nop1444 = alloca i1, i1 0
-  %nop1445 = alloca i1, i1 0
-  %nop1446 = alloca i1, i1 0
-  %nop1447 = alloca i1, i1 0
-  %nop1448 = alloca i1, i1 0
-  %nop1449 = alloca i1, i1 0
-  %nop1450 = alloca i1, i1 0
-  %nop1451 = alloca i1, i1 0
-  %nop1452 = alloca i1, i1 0
-  %nop1453 = alloca i1, i1 0
-  %nop1454 = alloca i1, i1 0
-  %nop1455 = alloca i1, i1 0
-  %nop1456 = alloca i1, i1 0
-  %nop1457 = alloca i1, i1 0
-  %nop1458 = alloca i1, i1 0
-  %nop1459 = alloca i1, i1 0
-  %nop1460 = alloca i1, i1 0
-  %nop1461 = alloca i1, i1 0
-  %nop1462 = alloca i1, i1 0
-  %nop1463 = alloca i1, i1 0
-  %nop1464 = alloca i1, i1 0
-  %nop1465 = alloca i1, i1 0
-  %nop1466 = alloca i1, i1 0
-  %nop1467 = alloca i1, i1 0
-  %nop1468 = alloca i1, i1 0
-  %nop1469 = alloca i1, i1 0
-  %nop1470 = alloca i1, i1 0
-  %nop1471 = alloca i1, i1 0
-  %nop1472 = alloca i1, i1 0
-  %nop1473 = alloca i1, i1 0
-  %nop1474 = alloca i1, i1 0
-  %nop1475 = alloca i1, i1 0
-  %nop1476 = alloca i1, i1 0
-  %nop1477 = alloca i1, i1 0
-  %nop1478 = alloca i1, i1 0
-  %nop1479 = alloca i1, i1 0
-  %nop1480 = alloca i1, i1 0
-  %nop1481 = alloca i1, i1 0
-  %nop1482 = alloca i1, i1 0
-  %nop1483 = alloca i1, i1 0
-  %nop1484 = alloca i1, i1 0
-  %nop1485 = alloca i1, i1 0
-  %nop1486 = alloca i1, i1 0
-  %nop1487 = alloca i1, i1 0
-  %nop1488 = alloca i1, i1 0
-  %nop1489 = alloca i1, i1 0
-  %nop1490 = alloca i1, i1 0
-  %nop1491 = alloca i1, i1 0
-  %nop1492 = alloca i1, i1 0
-  %nop1493 = alloca i1, i1 0
-  %nop1494 = alloca i1, i1 0
-  %nop1495 = alloca i1, i1 0
-  %nop1496 = alloca i1, i1 0
-  %nop1497 = alloca i1, i1 0
-  %nop1498 = alloca i1, i1 0
-  %nop1499 = alloca i1, i1 0
-  %nop1500 = alloca i1, i1 0
-  %nop1501 = alloca i1, i1 0
-  %nop1502 = alloca i1, i1 0
-  %nop1503 = alloca i1, i1 0
-  %nop1504 = alloca i1, i1 0
-  %nop1505 = alloca i1, i1 0
-  %nop1506 = alloca i1, i1 0
-  %nop1507 = alloca i1, i1 0
-  %nop1508 = alloca i1, i1 0
-  %nop1509 = alloca i1, i1 0
-  %nop1510 = alloca i1, i1 0
-  %nop1511 = alloca i1, i1 0
-  %nop1512 = alloca i1, i1 0
-  %nop1513 = alloca i1, i1 0
-  %nop1514 = alloca i1, i1 0
-  %nop1515 = alloca i1, i1 0
-  %nop1516 = alloca i1, i1 0
-  %nop1517 = alloca i1, i1 0
-  %nop1518 = alloca i1, i1 0
-  %nop1519 = alloca i1, i1 0
-  %nop1520 = alloca i1, i1 0
-  %nop1521 = alloca i1, i1 0
-  %nop1522 = alloca i1, i1 0
-  %nop1523 = alloca i1, i1 0
-  %nop1524 = alloca i1, i1 0
-  %nop1525 = alloca i1, i1 0
-  %nop1526 = alloca i1, i1 0
-  %nop1527 = alloca i1, i1 0
-  %nop1528 = alloca i1, i1 0
-  %nop1529 = alloca i1, i1 0
-  %nop1530 = alloca i1, i1 0
-  %nop1531 = alloca i1, i1 0
-  %nop1532 = alloca i1, i1 0
-  %nop1533 = alloca i1, i1 0
-  %nop1534 = alloca i1, i1 0
-  %nop1535 = alloca i1, i1 0
-  %nop1536 = alloca i1, i1 0
-  %nop1537 = alloca i1, i1 0
-  %nop1538 = alloca i1, i1 0
-  %nop1539 = alloca i1, i1 0
-  %nop1540 = alloca i1, i1 0
-  %nop1541 = alloca i1, i1 0
-  %nop1542 = alloca i1, i1 0
-  %nop1543 = alloca i1, i1 0
-  %nop1544 = alloca i1, i1 0
-  %nop1545 = alloca i1, i1 0
-  %nop1546 = alloca i1, i1 0
-  %nop1547 = alloca i1, i1 0
-  %nop1548 = alloca i1, i1 0
-  %nop1549 = alloca i1, i1 0
-  %nop1550 = alloca i1, i1 0
-  %nop1551 = alloca i1, i1 0
-  %nop1552 = alloca i1, i1 0
-  %nop1553 = alloca i1, i1 0
-  %nop1554 = alloca i1, i1 0
-  %nop1555 = alloca i1, i1 0
-  %nop1556 = alloca i1, i1 0
-  %nop1557 = alloca i1, i1 0
-  %nop1558 = alloca i1, i1 0
-  %nop1559 = alloca i1, i1 0
-  %nop1560 = alloca i1, i1 0
-  %nop1561 = alloca i1, i1 0
-  %nop1562 = alloca i1, i1 0
-  %nop1563 = alloca i1, i1 0
-  %nop1564 = alloca i1, i1 0
-  %nop1565 = alloca i1, i1 0
-  %nop1566 = alloca i1, i1 0
-  %nop1567 = alloca i1, i1 0
-  %nop1568 = alloca i1, i1 0
-  %nop1569 = alloca i1, i1 0
-  %nop1570 = alloca i1, i1 0
-  %nop1571 = alloca i1, i1 0
-  %nop1572 = alloca i1, i1 0
-  %nop1573 = alloca i1, i1 0
-  %nop1574 = alloca i1, i1 0
-  %nop1575 = alloca i1, i1 0
-  %nop1576 = alloca i1, i1 0
-  %nop1577 = alloca i1, i1 0
-  %nop1578 = alloca i1, i1 0
-  %nop1579 = alloca i1, i1 0
-  %nop1580 = alloca i1, i1 0
-  %nop1581 = alloca i1, i1 0
-  %nop1582 = alloca i1, i1 0
-  %nop1583 = alloca i1, i1 0
-  %nop1584 = alloca i1, i1 0
-  %nop1585 = alloca i1, i1 0
-  %nop1586 = alloca i1, i1 0
-  %nop1587 = alloca i1, i1 0
-  %nop1588 = alloca i1, i1 0
-  %nop1589 = alloca i1, i1 0
-  %nop1590 = alloca i1, i1 0
-  %nop1591 = alloca i1, i1 0
-  %nop1592 = alloca i1, i1 0
-  %nop1593 = alloca i1, i1 0
-  %nop1594 = alloca i1, i1 0
-  %nop1595 = alloca i1, i1 0
-  %nop1596 = alloca i1, i1 0
-  %nop1597 = alloca i1, i1 0
-  %nop1598 = alloca i1, i1 0
-  %nop1599 = alloca i1, i1 0
-  %nop1600 = alloca i1, i1 0
-  %nop1601 = alloca i1, i1 0
-  %nop1602 = alloca i1, i1 0
-  %nop1603 = alloca i1, i1 0
-  %nop1604 = alloca i1, i1 0
-  %nop1605 = alloca i1, i1 0
-  %nop1606 = alloca i1, i1 0
-  %nop1607 = alloca i1, i1 0
-  %nop1608 = alloca i1, i1 0
-  %nop1609 = alloca i1, i1 0
-  %nop1610 = alloca i1, i1 0
-  %nop1611 = alloca i1, i1 0
-  %nop1612 = alloca i1, i1 0
-  %nop1613 = alloca i1, i1 0
-  %nop1614 = alloca i1, i1 0
-  %nop1615 = alloca i1, i1 0
-  %nop1616 = alloca i1, i1 0
-  %nop1617 = alloca i1, i1 0
-  %nop1618 = alloca i1, i1 0
-  %nop1619 = alloca i1, i1 0
-  %nop1620 = alloca i1, i1 0
-  %nop1621 = alloca i1, i1 0
-  %nop1622 = alloca i1, i1 0
-  %nop1623 = alloca i1, i1 0
-  %nop1624 = alloca i1, i1 0
-  %nop1625 = alloca i1, i1 0
-  %nop1626 = alloca i1, i1 0
-  %nop1627 = alloca i1, i1 0
-  %nop1628 = alloca i1, i1 0
-  %nop1629 = alloca i1, i1 0
-  %nop1630 = alloca i1, i1 0
-  %nop1631 = alloca i1, i1 0
-  %nop1632 = alloca i1, i1 0
-  %nop1633 = alloca i1, i1 0
-  %nop1634 = alloca i1, i1 0
-  %nop1635 = alloca i1, i1 0
-  %nop1636 = alloca i1, i1 0
-  %nop1637 = alloca i1, i1 0
-  %nop1638 = alloca i1, i1 0
-  %nop1639 = alloca i1, i1 0
-  %nop1640 = alloca i1, i1 0
-  %nop1641 = alloca i1, i1 0
-  %nop1642 = alloca i1, i1 0
-  %nop1643 = alloca i1, i1 0
-  %nop1644 = alloca i1, i1 0
-  %nop1645 = alloca i1, i1 0
-  %nop1646 = alloca i1, i1 0
-  %nop1647 = alloca i1, i1 0
-  %nop1648 = alloca i1, i1 0
-  %nop1649 = alloca i1, i1 0
-  %nop1650 = alloca i1, i1 0
-  %nop1651 = alloca i1, i1 0
-  %nop1652 = alloca i1, i1 0
-  %nop1653 = alloca i1, i1 0
-  %nop1654 = alloca i1, i1 0
-  %nop1655 = alloca i1, i1 0
-  %nop1656 = alloca i1, i1 0
-  %nop1657 = alloca i1, i1 0
-  %nop1658 = alloca i1, i1 0
-  %nop1659 = alloca i1, i1 0
-  %nop1660 = alloca i1, i1 0
-  %nop1661 = alloca i1, i1 0
-  %nop1662 = alloca i1, i1 0
-  %nop1663 = alloca i1, i1 0
-  %nop1664 = alloca i1, i1 0
-  %nop1665 = alloca i1, i1 0
-  %nop1666 = alloca i1, i1 0
-  %nop1667 = alloca i1, i1 0
-  %nop1668 = alloca i1, i1 0
-  %nop1669 = alloca i1, i1 0
-  %nop1670 = alloca i1, i1 0
-  %nop1671 = alloca i1, i1 0
-  %nop1672 = alloca i1, i1 0
-  %nop1673 = alloca i1, i1 0
-  %nop1674 = alloca i1, i1 0
-  %nop1675 = alloca i1, i1 0
-  %nop1676 = alloca i1, i1 0
-  %nop1677 = alloca i1, i1 0
-  %nop1678 = alloca i1, i1 0
-  %nop1679 = alloca i1, i1 0
-  %nop1680 = alloca i1, i1 0
-  %nop1681 = alloca i1, i1 0
-  %nop1682 = alloca i1, i1 0
-  %nop1683 = alloca i1, i1 0
-  %nop1684 = alloca i1, i1 0
-  %nop1685 = alloca i1, i1 0
-  %nop1686 = alloca i1, i1 0
-  %nop1687 = alloca i1, i1 0
-  %nop1688 = alloca i1, i1 0
-  %nop1689 = alloca i1, i1 0
-  %nop1690 = alloca i1, i1 0
-  %nop1691 = alloca i1, i1 0
-  %nop1692 = alloca i1, i1 0
-  %nop1693 = alloca i1, i1 0
-  %nop1694 = alloca i1, i1 0
-  %nop1695 = alloca i1, i1 0
-  %nop1696 = alloca i1, i1 0
-  %nop1697 = alloca i1, i1 0
-  %nop1698 = alloca i1, i1 0
-  %nop1699 = alloca i1, i1 0
-  %nop1700 = alloca i1, i1 0
-  %nop1701 = alloca i1, i1 0
-  %nop1702 = alloca i1, i1 0
-  %nop1703 = alloca i1, i1 0
-  %nop1704 = alloca i1, i1 0
-  %nop1705 = alloca i1, i1 0
-  %nop1706 = alloca i1, i1 0
-  %nop1707 = alloca i1, i1 0
-  %nop1708 = alloca i1, i1 0
-  %nop1709 = alloca i1, i1 0
-  %nop1710 = alloca i1, i1 0
-  %nop1711 = alloca i1, i1 0
-  %nop1712 = alloca i1, i1 0
-  %nop1713 = alloca i1, i1 0
-  %nop1714 = alloca i1, i1 0
-  %nop1715 = alloca i1, i1 0
-  %nop1716 = alloca i1, i1 0
-  %nop1717 = alloca i1, i1 0
-  %nop1718 = alloca i1, i1 0
-  %nop1719 = alloca i1, i1 0
-  %nop1720 = alloca i1, i1 0
-  %nop1721 = alloca i1, i1 0
-  %nop1722 = alloca i1, i1 0
-  %nop1723 = alloca i1, i1 0
-  %nop1724 = alloca i1, i1 0
-  %nop1725 = alloca i1, i1 0
-  %nop1726 = alloca i1, i1 0
-  %nop1727 = alloca i1, i1 0
-  %nop1728 = alloca i1, i1 0
-  %nop1729 = alloca i1, i1 0
-  %nop1730 = alloca i1, i1 0
-  %nop1731 = alloca i1, i1 0
-  %nop1732 = alloca i1, i1 0
-  %nop1733 = alloca i1, i1 0
-  %nop1734 = alloca i1, i1 0
-  %nop1735 = alloca i1, i1 0
-  %nop1736 = alloca i1, i1 0
-  %nop1737 = alloca i1, i1 0
-  %nop1738 = alloca i1, i1 0
-  %nop1739 = alloca i1, i1 0
-  %nop1740 = alloca i1, i1 0
-  %nop1741 = alloca i1, i1 0
-  %nop1742 = alloca i1, i1 0
-  %nop1743 = alloca i1, i1 0
-  %nop1744 = alloca i1, i1 0
-  %nop1745 = alloca i1, i1 0
-  %nop1746 = alloca i1, i1 0
-  %nop1747 = alloca i1, i1 0
-  %nop1748 = alloca i1, i1 0
-  %nop1749 = alloca i1, i1 0
-  %nop1750 = alloca i1, i1 0
-  %nop1751 = alloca i1, i1 0
-  %nop1752 = alloca i1, i1 0
-  %nop1753 = alloca i1, i1 0
-  %nop1754 = alloca i1, i1 0
-  %nop1755 = alloca i1, i1 0
-  %nop1756 = alloca i1, i1 0
-  %nop1757 = alloca i1, i1 0
-  %nop1758 = alloca i1, i1 0
-  %nop1759 = alloca i1, i1 0
-  %nop1760 = alloca i1, i1 0
-  %nop1761 = alloca i1, i1 0
-  %nop1762 = alloca i1, i1 0
-  %nop1763 = alloca i1, i1 0
-  %nop1764 = alloca i1, i1 0
-  %nop1765 = alloca i1, i1 0
-  %nop1766 = alloca i1, i1 0
-  %nop1767 = alloca i1, i1 0
-  %nop1768 = alloca i1, i1 0
-  %nop1769 = alloca i1, i1 0
-  %nop1770 = alloca i1, i1 0
-  %nop1771 = alloca i1, i1 0
-  %nop1772 = alloca i1, i1 0
-  %nop1773 = alloca i1, i1 0
-  %nop1774 = alloca i1, i1 0
-  %nop1775 = alloca i1, i1 0
-  %nop1776 = alloca i1, i1 0
-  %nop1777 = alloca i1, i1 0
-  %nop1778 = alloca i1, i1 0
-  %nop1779 = alloca i1, i1 0
-  %nop1780 = alloca i1, i1 0
-  %nop1781 = alloca i1, i1 0
-  %nop1782 = alloca i1, i1 0
-  %nop1783 = alloca i1, i1 0
-  %nop1784 = alloca i1, i1 0
-  %nop1785 = alloca i1, i1 0
-  %nop1786 = alloca i1, i1 0
-  %nop1787 = alloca i1, i1 0
-  %nop1788 = alloca i1, i1 0
-  %nop1789 = alloca i1, i1 0
-  %nop1790 = alloca i1, i1 0
-  %nop1791 = alloca i1, i1 0
-  %nop1792 = alloca i1, i1 0
-  %nop1793 = alloca i1, i1 0
-  %nop1794 = alloca i1, i1 0
-  %nop1795 = alloca i1, i1 0
-  %nop1796 = alloca i1, i1 0
-  %nop1797 = alloca i1, i1 0
-  %nop1798 = alloca i1, i1 0
-  %nop1799 = alloca i1, i1 0
-  %nop1800 = alloca i1, i1 0
-  %nop1801 = alloca i1, i1 0
-  %nop1802 = alloca i1, i1 0
-  %nop1803 = alloca i1, i1 0
-  %nop1804 = alloca i1, i1 0
-  %nop1805 = alloca i1, i1 0
-  %nop1806 = alloca i1, i1 0
-  %nop1807 = alloca i1, i1 0
-  %nop1808 = alloca i1, i1 0
-  %nop1809 = alloca i1, i1 0
-  %nop1810 = alloca i1, i1 0
-  %nop1811 = alloca i1, i1 0
-  %nop1812 = alloca i1, i1 0
-  %nop1813 = alloca i1, i1 0
-  %nop1814 = alloca i1, i1 0
-  %nop1815 = alloca i1, i1 0
-  %nop1816 = alloca i1, i1 0
-  %nop1817 = alloca i1, i1 0
-  %nop1818 = alloca i1, i1 0
-  %nop1819 = alloca i1, i1 0
-  %nop1820 = alloca i1, i1 0
-  %nop1821 = alloca i1, i1 0
-  %nop1822 = alloca i1, i1 0
-  %nop1823 = alloca i1, i1 0
-  %nop1824 = alloca i1, i1 0
-  %nop1825 = alloca i1, i1 0
-  %nop1826 = alloca i1, i1 0
-  %nop1827 = alloca i1, i1 0
-  %nop1828 = alloca i1, i1 0
-  %nop1829 = alloca i1, i1 0
-  %nop1830 = alloca i1, i1 0
-  %nop1831 = alloca i1, i1 0
-  %nop1832 = alloca i1, i1 0
-  %nop1833 = alloca i1, i1 0
-  %nop1834 = alloca i1, i1 0
-  %nop1835 = alloca i1, i1 0
-  %nop1836 = alloca i1, i1 0
-  %nop1837 = alloca i1, i1 0
-  %nop1838 = alloca i1, i1 0
-  %nop1839 = alloca i1, i1 0
-  %nop1840 = alloca i1, i1 0
-  %nop1841 = alloca i1, i1 0
-  %nop1842 = alloca i1, i1 0
-  %nop1843 = alloca i1, i1 0
-  %nop1844 = alloca i1, i1 0
-  %nop1845 = alloca i1, i1 0
-  %nop1846 = alloca i1, i1 0
-  %nop1847 = alloca i1, i1 0
-  %nop1848 = alloca i1, i1 0
-  %nop1849 = alloca i1, i1 0
-  %nop1850 = alloca i1, i1 0
-  %nop1851 = alloca i1, i1 0
-  %nop1852 = alloca i1, i1 0
-  %nop1853 = alloca i1, i1 0
-  %nop1854 = alloca i1, i1 0
-  %nop1855 = alloca i1, i1 0
-  %nop1856 = alloca i1, i1 0
-  %nop1857 = alloca i1, i1 0
-  %nop1858 = alloca i1, i1 0
-  %nop1859 = alloca i1, i1 0
-  %nop1860 = alloca i1, i1 0
-  %nop1861 = alloca i1, i1 0
-  %nop1862 = alloca i1, i1 0
-  %nop1863 = alloca i1, i1 0
-  %nop1864 = alloca i1, i1 0
-  %nop1865 = alloca i1, i1 0
-  %nop1866 = alloca i1, i1 0
-  %nop1867 = alloca i1, i1 0
-  %nop1868 = alloca i1, i1 0
-  %nop1869 = alloca i1, i1 0
-  %nop1870 = alloca i1, i1 0
-  %nop1871 = alloca i1, i1 0
-  %nop1872 = alloca i1, i1 0
-  %nop1873 = alloca i1, i1 0
-  %nop1874 = alloca i1, i1 0
-  %nop1875 = alloca i1, i1 0
-  %nop1876 = alloca i1, i1 0
-  %nop1877 = alloca i1, i1 0
-  %nop1878 = alloca i1, i1 0
-  %nop1879 = alloca i1, i1 0
-  %nop1880 = alloca i1, i1 0
-  %nop1881 = alloca i1, i1 0
-  %nop1882 = alloca i1, i1 0
-  %nop1883 = alloca i1, i1 0
-  %nop1884 = alloca i1, i1 0
-  %nop1885 = alloca i1, i1 0
-  %nop1886 = alloca i1, i1 0
-  %nop1887 = alloca i1, i1 0
-  %nop1888 = alloca i1, i1 0
-  %nop1889 = alloca i1, i1 0
-  %nop1890 = alloca i1, i1 0
-  %nop1891 = alloca i1, i1 0
-  %nop1892 = alloca i1, i1 0
-  %nop1893 = alloca i1, i1 0
-  %nop1894 = alloca i1, i1 0
-  %nop1895 = alloca i1, i1 0
-  %nop1896 = alloca i1, i1 0
-  %nop1897 = alloca i1, i1 0
-  %nop1898 = alloca i1, i1 0
-  %nop1899 = alloca i1, i1 0
-  %nop1900 = alloca i1, i1 0
-  %nop1901 = alloca i1, i1 0
-  %nop1902 = alloca i1, i1 0
-  %nop1903 = alloca i1, i1 0
-  %nop1904 = alloca i1, i1 0
-  %nop1905 = alloca i1, i1 0
-  %nop1906 = alloca i1, i1 0
-  %nop1907 = alloca i1, i1 0
-  %nop1908 = alloca i1, i1 0
-  %nop1909 = alloca i1, i1 0
-  %nop1910 = alloca i1, i1 0
-  %nop1911 = alloca i1, i1 0
-  %nop1912 = alloca i1, i1 0
-  %nop1913 = alloca i1, i1 0
-  %nop1914 = alloca i1, i1 0
-  %nop1915 = alloca i1, i1 0
-  %nop1916 = alloca i1, i1 0
-  %nop1917 = alloca i1, i1 0
-  %nop1918 = alloca i1, i1 0
-  %nop1919 = alloca i1, i1 0
-  %nop1920 = alloca i1, i1 0
-  %nop1921 = alloca i1, i1 0
-  %nop1922 = alloca i1, i1 0
-  %nop1923 = alloca i1, i1 0
-  %nop1924 = alloca i1, i1 0
-  %nop1925 = alloca i1, i1 0
-  %nop1926 = alloca i1, i1 0
-  %nop1927 = alloca i1, i1 0
-  %nop1928 = alloca i1, i1 0
-  %nop1929 = alloca i1, i1 0
-  %nop1930 = alloca i1, i1 0
-  %nop1931 = alloca i1, i1 0
-  %nop1932 = alloca i1, i1 0
-  %nop1933 = alloca i1, i1 0
-  %nop1934 = alloca i1, i1 0
-  %nop1935 = alloca i1, i1 0
-  %nop1936 = alloca i1, i1 0
-  %nop1937 = alloca i1, i1 0
-  %nop1938 = alloca i1, i1 0
-  %nop1939 = alloca i1, i1 0
-  %nop1940 = alloca i1, i1 0
-  %nop1941 = alloca i1, i1 0
-  %nop1942 = alloca i1, i1 0
-  %nop1943 = alloca i1, i1 0
-  %nop1944 = alloca i1, i1 0
-  %nop1945 = alloca i1, i1 0
-  %nop1946 = alloca i1, i1 0
-  %nop1947 = alloca i1, i1 0
-  %nop1948 = alloca i1, i1 0
-  %nop1949 = alloca i1, i1 0
-  %nop1950 = alloca i1, i1 0
-  %nop1951 = alloca i1, i1 0
-  %nop1952 = alloca i1, i1 0
-  %nop1953 = alloca i1, i1 0
-  %nop1954 = alloca i1, i1 0
-  %nop1955 = alloca i1, i1 0
-  %nop1956 = alloca i1, i1 0
-  %nop1957 = alloca i1, i1 0
-  %nop1958 = alloca i1, i1 0
-  %nop1959 = alloca i1, i1 0
-  %nop1960 = alloca i1, i1 0
-  %nop1961 = alloca i1, i1 0
-  %nop1962 = alloca i1, i1 0
-  %nop1963 = alloca i1, i1 0
-  %nop1964 = alloca i1, i1 0
-  %nop1965 = alloca i1, i1 0
-  %nop1966 = alloca i1, i1 0
-  %nop1967 = alloca i1, i1 0
-  %nop1968 = alloca i1, i1 0
-  %nop1969 = alloca i1, i1 0
-  %nop1970 = alloca i1, i1 0
-  %nop1971 = alloca i1, i1 0
-  %nop1972 = alloca i1, i1 0
-  %nop1973 = alloca i1, i1 0
-  %nop1974 = alloca i1, i1 0
-  %nop1975 = alloca i1, i1 0
-  %nop1976 = alloca i1, i1 0
-  %nop1977 = alloca i1, i1 0
-  %nop1978 = alloca i1, i1 0
-  %nop1979 = alloca i1, i1 0
-  %nop1980 = alloca i1, i1 0
-  %nop1981 = alloca i1, i1 0
-  %nop1982 = alloca i1, i1 0
-  %nop1983 = alloca i1, i1 0
-  %nop1984 = alloca i1, i1 0
-  %nop1985 = alloca i1, i1 0
-  %nop1986 = alloca i1, i1 0
-  %nop1987 = alloca i1, i1 0
-  %nop1988 = alloca i1, i1 0
-  %nop1989 = alloca i1, i1 0
-  %nop1990 = alloca i1, i1 0
-  %nop1991 = alloca i1, i1 0
-  %nop1992 = alloca i1, i1 0
-  %nop1993 = alloca i1, i1 0
-  %nop1994 = alloca i1, i1 0
-  %nop1995 = alloca i1, i1 0
-  %nop1996 = alloca i1, i1 0
-  %nop1997 = alloca i1, i1 0
-  %nop1998 = alloca i1, i1 0
-  %nop1999 = alloca i1, i1 0
-  %nop2000 = alloca i1, i1 0
-  %nop2001 = alloca i1, i1 0
-  %nop2002 = alloca i1, i1 0
-  %nop2003 = alloca i1, i1 0
-  %nop2004 = alloca i1, i1 0
-  %nop2005 = alloca i1, i1 0
-  %nop2006 = alloca i1, i1 0
-  %nop2007 = alloca i1, i1 0
-  %nop2008 = alloca i1, i1 0
-  %nop2009 = alloca i1, i1 0
-  %nop2010 = alloca i1, i1 0
-  %nop2011 = alloca i1, i1 0
-  %nop2012 = alloca i1, i1 0
-  %nop2013 = alloca i1, i1 0
-  %nop2014 = alloca i1, i1 0
-  %nop2015 = alloca i1, i1 0
-  %nop2016 = alloca i1, i1 0
-  %nop2017 = alloca i1, i1 0
-  %nop2018 = alloca i1, i1 0
-  %nop2019 = alloca i1, i1 0
-  %nop2020 = alloca i1, i1 0
-  %nop2021 = alloca i1, i1 0
-  %nop2022 = alloca i1, i1 0
-  %nop2023 = alloca i1, i1 0
-  %nop2024 = alloca i1, i1 0
-  %nop2025 = alloca i1, i1 0
-  %nop2026 = alloca i1, i1 0
-  %nop2027 = alloca i1, i1 0
-  %nop2028 = alloca i1, i1 0
-  %nop2029 = alloca i1, i1 0
-  %nop2030 = alloca i1, i1 0
-  %nop2031 = alloca i1, i1 0
-  %nop2032 = alloca i1, i1 0
-  %nop2033 = alloca i1, i1 0
-  %nop2034 = alloca i1, i1 0
-  %nop2035 = alloca i1, i1 0
-  %nop2036 = alloca i1, i1 0
-  %nop2037 = alloca i1, i1 0
-  %nop2038 = alloca i1, i1 0
-  %nop2039 = alloca i1, i1 0
-  %nop2040 = alloca i1, i1 0
-  %nop2041 = alloca i1, i1 0
-  %nop2042 = alloca i1, i1 0
-  %nop2043 = alloca i1, i1 0
-  %nop2044 = alloca i1, i1 0
-  %nop2045 = alloca i1, i1 0
-  %nop2046 = alloca i1, i1 0
-  %nop2047 = alloca i1, i1 0
-  %nop2048 = alloca i1, i1 0
-  %nop2049 = alloca i1, i1 0
-  %nop2050 = alloca i1, i1 0
-  %nop2051 = alloca i1, i1 0
-  %nop2052 = alloca i1, i1 0
-  %nop2053 = alloca i1, i1 0
-  %nop2054 = alloca i1, i1 0
-  %nop2055 = alloca i1, i1 0
-  %nop2056 = alloca i1, i1 0
-  %nop2057 = alloca i1, i1 0
-  %nop2058 = alloca i1, i1 0
-  %nop2059 = alloca i1, i1 0
-  %nop2060 = alloca i1, i1 0
-  %nop2061 = alloca i1, i1 0
-  %nop2062 = alloca i1, i1 0
-  %nop2063 = alloca i1, i1 0
-  %nop2064 = alloca i1, i1 0
-  %nop2065 = alloca i1, i1 0
-  %nop2066 = alloca i1, i1 0
-  %nop2067 = alloca i1, i1 0
-  %nop2068 = alloca i1, i1 0
-  %nop2069 = alloca i1, i1 0
-  %nop2070 = alloca i1, i1 0
-  %nop2071 = alloca i1, i1 0
-  %nop2072 = alloca i1, i1 0
-  %nop2073 = alloca i1, i1 0
-  %nop2074 = alloca i1, i1 0
-  %nop2075 = alloca i1, i1 0
-  %nop2076 = alloca i1, i1 0
-  %nop2077 = alloca i1, i1 0
-  %nop2078 = alloca i1, i1 0
-  %nop2079 = alloca i1, i1 0
-  %nop2080 = alloca i1, i1 0
-  %nop2081 = alloca i1, i1 0
-  %nop2082 = alloca i1, i1 0
-  %nop2083 = alloca i1, i1 0
-  %nop2084 = alloca i1, i1 0
-  %nop2085 = alloca i1, i1 0
-  %nop2086 = alloca i1, i1 0
-  %nop2087 = alloca i1, i1 0
-  %nop2088 = alloca i1, i1 0
-  %nop2089 = alloca i1, i1 0
-  %nop2090 = alloca i1, i1 0
-  %nop2091 = alloca i1, i1 0
-  %nop2092 = alloca i1, i1 0
-  %nop2093 = alloca i1, i1 0
-  %nop2094 = alloca i1, i1 0
-  %nop2095 = alloca i1, i1 0
-  %nop2096 = alloca i1, i1 0
-  %nop2097 = alloca i1, i1 0
-  %nop2098 = alloca i1, i1 0
-  %nop2099 = alloca i1, i1 0
-  %nop2100 = alloca i1, i1 0
-  %nop2101 = alloca i1, i1 0
-  %nop2102 = alloca i1, i1 0
-  %nop2103 = alloca i1, i1 0
-  %nop2104 = alloca i1, i1 0
-  %nop2105 = alloca i1, i1 0
-  %nop2106 = alloca i1, i1 0
-  %nop2107 = alloca i1, i1 0
-  %nop2108 = alloca i1, i1 0
-  %nop2109 = alloca i1, i1 0
-  %nop2110 = alloca i1, i1 0
-  %nop2111 = alloca i1, i1 0
-  %nop2112 = alloca i1, i1 0
-  %nop2113 = alloca i1, i1 0
-  %nop2114 = alloca i1, i1 0
-  %nop2115 = alloca i1, i1 0
-  %nop2116 = alloca i1, i1 0
-  %nop2117 = alloca i1, i1 0
-  %nop2118 = alloca i1, i1 0
-  %nop2119 = alloca i1, i1 0
-  %nop2120 = alloca i1, i1 0
-  %nop2121 = alloca i1, i1 0
-  %nop2122 = alloca i1, i1 0
-  %nop2123 = alloca i1, i1 0
-  %nop2124 = alloca i1, i1 0
-  %nop2125 = alloca i1, i1 0
-  %nop2126 = alloca i1, i1 0
-  %nop2127 = alloca i1, i1 0
-  %nop2128 = alloca i1, i1 0
-  %nop2129 = alloca i1, i1 0
-  %nop2130 = alloca i1, i1 0
-  %nop2131 = alloca i1, i1 0
-  %nop2132 = alloca i1, i1 0
-  %nop2133 = alloca i1, i1 0
-  %nop2134 = alloca i1, i1 0
-  %nop2135 = alloca i1, i1 0
-  %nop2136 = alloca i1, i1 0
-  %nop2137 = alloca i1, i1 0
-  %nop2138 = alloca i1, i1 0
-  %nop2139 = alloca i1, i1 0
-  %nop2140 = alloca i1, i1 0
-  %nop2141 = alloca i1, i1 0
-  %nop2142 = alloca i1, i1 0
-  %nop2143 = alloca i1, i1 0
-  %nop2144 = alloca i1, i1 0
-  %nop2145 = alloca i1, i1 0
-  %nop2146 = alloca i1, i1 0
-  %nop2147 = alloca i1, i1 0
-  %nop2148 = alloca i1, i1 0
-  %nop2149 = alloca i1, i1 0
-  %nop2150 = alloca i1, i1 0
-  %nop2151 = alloca i1, i1 0
-  %nop2152 = alloca i1, i1 0
-  %nop2153 = alloca i1, i1 0
-  %nop2154 = alloca i1, i1 0
-  %nop2155 = alloca i1, i1 0
-  %nop2156 = alloca i1, i1 0
-  %nop2157 = alloca i1, i1 0
-  %nop2158 = alloca i1, i1 0
-  %nop2159 = alloca i1, i1 0
-  %nop2160 = alloca i1, i1 0
-  %nop2161 = alloca i1, i1 0
-  %nop2162 = alloca i1, i1 0
-  %nop2163 = alloca i1, i1 0
-  %nop2164 = alloca i1, i1 0
-  %nop2165 = alloca i1, i1 0
-  %nop2166 = alloca i1, i1 0
-  %nop2167 = alloca i1, i1 0
-  %nop2168 = alloca i1, i1 0
-  %nop2169 = alloca i1, i1 0
-  %nop2170 = alloca i1, i1 0
-  %nop2171 = alloca i1, i1 0
-  %nop2172 = alloca i1, i1 0
-  %nop2173 = alloca i1, i1 0
-  %nop2174 = alloca i1, i1 0
-  %nop2175 = alloca i1, i1 0
-  %nop2176 = alloca i1, i1 0
-  %nop2177 = alloca i1, i1 0
-  %nop2178 = alloca i1, i1 0
-  %nop2179 = alloca i1, i1 0
-  %nop2180 = alloca i1, i1 0
-  %nop2181 = alloca i1, i1 0
-  %nop2182 = alloca i1, i1 0
-  %nop2183 = alloca i1, i1 0
-  %nop2184 = alloca i1, i1 0
-  %nop2185 = alloca i1, i1 0
-  %nop2186 = alloca i1, i1 0
-  %nop2187 = alloca i1, i1 0
-  %nop2188 = alloca i1, i1 0
-  %nop2189 = alloca i1, i1 0
-  %nop2190 = alloca i1, i1 0
-  %nop2191 = alloca i1, i1 0
-  %nop2192 = alloca i1, i1 0
-  %nop2193 = alloca i1, i1 0
-  %nop2194 = alloca i1, i1 0
-  %nop2195 = alloca i1, i1 0
-  %nop2196 = alloca i1, i1 0
-  %nop2197 = alloca i1, i1 0
-  %nop2198 = alloca i1, i1 0
-  %nop2199 = alloca i1, i1 0
-  %nop2200 = alloca i1, i1 0
-  %nop2201 = alloca i1, i1 0
-  %nop2202 = alloca i1, i1 0
-  %nop2203 = alloca i1, i1 0
-  %nop2204 = alloca i1, i1 0
-  %nop2205 = alloca i1, i1 0
-  %nop2206 = alloca i1, i1 0
-  %nop2207 = alloca i1, i1 0
-  %nop2208 = alloca i1, i1 0
-  %nop2209 = alloca i1, i1 0
-  %nop2210 = alloca i1, i1 0
-  %nop2211 = alloca i1, i1 0
-  %nop2212 = alloca i1, i1 0
-  %nop2213 = alloca i1, i1 0
-  %nop2214 = alloca i1, i1 0
-  %nop2215 = alloca i1, i1 0
-  %nop2216 = alloca i1, i1 0
-  %nop2217 = alloca i1, i1 0
-  %nop2218 = alloca i1, i1 0
-  %nop2219 = alloca i1, i1 0
-  %nop2220 = alloca i1, i1 0
-  %nop2221 = alloca i1, i1 0
-  %nop2222 = alloca i1, i1 0
-  %nop2223 = alloca i1, i1 0
-  %nop2224 = alloca i1, i1 0
-  %nop2225 = alloca i1, i1 0
-  %nop2226 = alloca i1, i1 0
-  %nop2227 = alloca i1, i1 0
-  %nop2228 = alloca i1, i1 0
-  %nop2229 = alloca i1, i1 0
-  %nop2230 = alloca i1, i1 0
-  %nop2231 = alloca i1, i1 0
-  %nop2232 = alloca i1, i1 0
-  %nop2233 = alloca i1, i1 0
-  %nop2234 = alloca i1, i1 0
-  %nop2235 = alloca i1, i1 0
-  %nop2236 = alloca i1, i1 0
-  %nop2237 = alloca i1, i1 0
-  %nop2238 = alloca i1, i1 0
-  %nop2239 = alloca i1, i1 0
-  %nop2240 = alloca i1, i1 0
-  %nop2241 = alloca i1, i1 0
-  %nop2242 = alloca i1, i1 0
-  %nop2243 = alloca i1, i1 0
-  %nop2244 = alloca i1, i1 0
-  %nop2245 = alloca i1, i1 0
-  %nop2246 = alloca i1, i1 0
-  %nop2247 = alloca i1, i1 0
-  %nop2248 = alloca i1, i1 0
-  %nop2249 = alloca i1, i1 0
-  %nop2250 = alloca i1, i1 0
-  %nop2251 = alloca i1, i1 0
-  %nop2252 = alloca i1, i1 0
-  %nop2253 = alloca i1, i1 0
-  %nop2254 = alloca i1, i1 0
-  %nop2255 = alloca i1, i1 0
-  %nop2256 = alloca i1, i1 0
-  %nop2257 = alloca i1, i1 0
-  %nop2258 = alloca i1, i1 0
-  %nop2259 = alloca i1, i1 0
-  %nop2260 = alloca i1, i1 0
-  %nop2261 = alloca i1, i1 0
-  %nop2262 = alloca i1, i1 0
-  %nop2263 = alloca i1, i1 0
-  %nop2264 = alloca i1, i1 0
-  %nop2265 = alloca i1, i1 0
-  %nop2266 = alloca i1, i1 0
-  %nop2267 = alloca i1, i1 0
-  %nop2268 = alloca i1, i1 0
-  %nop2269 = alloca i1, i1 0
-  %nop2270 = alloca i1, i1 0
-  %nop2271 = alloca i1, i1 0
-  %nop2272 = alloca i1, i1 0
-  %nop2273 = alloca i1, i1 0
-  %nop2274 = alloca i1, i1 0
-  %nop2275 = alloca i1, i1 0
-  %nop2276 = alloca i1, i1 0
-  %nop2277 = alloca i1, i1 0
-  %nop2278 = alloca i1, i1 0
-  %nop2279 = alloca i1, i1 0
-  %nop2280 = alloca i1, i1 0
-  %nop2281 = alloca i1, i1 0
-  %nop2282 = alloca i1, i1 0
-  %nop2283 = alloca i1, i1 0
-  %nop2284 = alloca i1, i1 0
-  %nop2285 = alloca i1, i1 0
-  %nop2286 = alloca i1, i1 0
-  %nop2287 = alloca i1, i1 0
-  %nop2288 = alloca i1, i1 0
-  %nop2289 = alloca i1, i1 0
-  %nop2290 = alloca i1, i1 0
-  %nop2291 = alloca i1, i1 0
-  %nop2292 = alloca i1, i1 0
-  %nop2293 = alloca i1, i1 0
-  %nop2294 = alloca i1, i1 0
-  %nop2295 = alloca i1, i1 0
-  %nop2296 = alloca i1, i1 0
-  %nop2297 = alloca i1, i1 0
-  %nop2298 = alloca i1, i1 0
-  %nop2299 = alloca i1, i1 0
-  %nop2300 = alloca i1, i1 0
-  %nop2301 = alloca i1, i1 0
-  %nop2302 = alloca i1, i1 0
-  %nop2303 = alloca i1, i1 0
-  %nop2304 = alloca i1, i1 0
-  %nop2305 = alloca i1, i1 0
-  %nop2306 = alloca i1, i1 0
-  %nop2307 = alloca i1, i1 0
-  %nop2308 = alloca i1, i1 0
-  %nop2309 = alloca i1, i1 0
-  %nop2310 = alloca i1, i1 0
-  %nop2311 = alloca i1, i1 0
-  %nop2312 = alloca i1, i1 0
-  %nop2313 = alloca i1, i1 0
-  %nop2314 = alloca i1, i1 0
-  %nop2315 = alloca i1, i1 0
-  %nop2316 = alloca i1, i1 0
-  %nop2317 = alloca i1, i1 0
-  %nop2318 = alloca i1, i1 0
-  %nop2319 = alloca i1, i1 0
-  %nop2320 = alloca i1, i1 0
-  %nop2321 = alloca i1, i1 0
-  %nop2322 = alloca i1, i1 0
-  %nop2323 = alloca i1, i1 0
-  %nop2324 = alloca i1, i1 0
-  %nop2325 = alloca i1, i1 0
-  %nop2326 = alloca i1, i1 0
-  %nop2327 = alloca i1, i1 0
-  %nop2328 = alloca i1, i1 0
-  %nop2329 = alloca i1, i1 0
-  %nop2330 = alloca i1, i1 0
-  %nop2331 = alloca i1, i1 0
-  %nop2332 = alloca i1, i1 0
-  %nop2333 = alloca i1, i1 0
-  %nop2334 = alloca i1, i1 0
-  %nop2335 = alloca i1, i1 0
-  %nop2336 = alloca i1, i1 0
-  %nop2337 = alloca i1, i1 0
-  %nop2338 = alloca i1, i1 0
-  %nop2339 = alloca i1, i1 0
-  %nop2340 = alloca i1, i1 0
-  %nop2341 = alloca i1, i1 0
-  %nop2342 = alloca i1, i1 0
-  %nop2343 = alloca i1, i1 0
-  %nop2344 = alloca i1, i1 0
-  %nop2345 = alloca i1, i1 0
-  %nop2346 = alloca i1, i1 0
-  %nop2347 = alloca i1, i1 0
-  %nop2348 = alloca i1, i1 0
-  %nop2349 = alloca i1, i1 0
-  %nop2350 = alloca i1, i1 0
-  %nop2351 = alloca i1, i1 0
-  %nop2352 = alloca i1, i1 0
-  %nop2353 = alloca i1, i1 0
-  %nop2354 = alloca i1, i1 0
-  %nop2355 = alloca i1, i1 0
-  %nop2356 = alloca i1, i1 0
-  %nop2357 = alloca i1, i1 0
-  %nop2358 = alloca i1, i1 0
-  %nop2359 = alloca i1, i1 0
-  %nop2360 = alloca i1, i1 0
-  %nop2361 = alloca i1, i1 0
-  %nop2362 = alloca i1, i1 0
-  %nop2363 = alloca i1, i1 0
-  %nop2364 = alloca i1, i1 0
-  %nop2365 = alloca i1, i1 0
-  %nop2366 = alloca i1, i1 0
-  %nop2367 = alloca i1, i1 0
-  %nop2368 = alloca i1, i1 0
-  %nop2369 = alloca i1, i1 0
-  %nop2370 = alloca i1, i1 0
-  %nop2371 = alloca i1, i1 0
-  %nop2372 = alloca i1, i1 0
-  %nop2373 = alloca i1, i1 0
-  %nop2374 = alloca i1, i1 0
-  %nop2375 = alloca i1, i1 0
-  %nop2376 = alloca i1, i1 0
-  %nop2377 = alloca i1, i1 0
-  %nop2378 = alloca i1, i1 0
-  %nop2379 = alloca i1, i1 0
-  %nop2380 = alloca i1, i1 0
-  %nop2381 = alloca i1, i1 0
-  %nop2382 = alloca i1, i1 0
-  %nop2383 = alloca i1, i1 0
-  %nop2384 = alloca i1, i1 0
-  %nop2385 = alloca i1, i1 0
-  %nop2386 = alloca i1, i1 0
-  %nop2387 = alloca i1, i1 0
-  %nop2388 = alloca i1, i1 0
-  %nop2389 = alloca i1, i1 0
-  %nop2390 = alloca i1, i1 0
-  %nop2391 = alloca i1, i1 0
-  %nop2392 = alloca i1, i1 0
-  %nop2393 = alloca i1, i1 0
-  %nop2394 = alloca i1, i1 0
-  %nop2395 = alloca i1, i1 0
-  %nop2396 = alloca i1, i1 0
-  %nop2397 = alloca i1, i1 0
-  %nop2398 = alloca i1, i1 0
-  %nop2399 = alloca i1, i1 0
-  %nop2400 = alloca i1, i1 0
-  %nop2401 = alloca i1, i1 0
-  %nop2402 = alloca i1, i1 0
-  %nop2403 = alloca i1, i1 0
-  %nop2404 = alloca i1, i1 0
-  %nop2405 = alloca i1, i1 0
-  %nop2406 = alloca i1, i1 0
-  %nop2407 = alloca i1, i1 0
-  %nop2408 = alloca i1, i1 0
-  %nop2409 = alloca i1, i1 0
-  %nop2410 = alloca i1, i1 0
-  %nop2411 = alloca i1, i1 0
-  %nop2412 = alloca i1, i1 0
-  %nop2413 = alloca i1, i1 0
-  %nop2414 = alloca i1, i1 0
-  %nop2415 = alloca i1, i1 0
-  %nop2416 = alloca i1, i1 0
-  %nop2417 = alloca i1, i1 0
-  %nop2418 = alloca i1, i1 0
-  %nop2419 = alloca i1, i1 0
-  %nop2420 = alloca i1, i1 0
-  %nop2421 = alloca i1, i1 0
-  %nop2422 = alloca i1, i1 0
-  %nop2423 = alloca i1, i1 0
-  %nop2424 = alloca i1, i1 0
-  %nop2425 = alloca i1, i1 0
-  %nop2426 = alloca i1, i1 0
-  %nop2427 = alloca i1, i1 0
-  %nop2428 = alloca i1, i1 0
-  %nop2429 = alloca i1, i1 0
-  %nop2430 = alloca i1, i1 0
-  %nop2431 = alloca i1, i1 0
-  %nop2432 = alloca i1, i1 0
-  %nop2433 = alloca i1, i1 0
-  %nop2434 = alloca i1, i1 0
-  %nop2435 = alloca i1, i1 0
-  %nop2436 = alloca i1, i1 0
-  %nop2437 = alloca i1, i1 0
-  %nop2438 = alloca i1, i1 0
-  %nop2439 = alloca i1, i1 0
-  %nop2440 = alloca i1, i1 0
-  %nop2441 = alloca i1, i1 0
-  %nop2442 = alloca i1, i1 0
-  %nop2443 = alloca i1, i1 0
-  %nop2444 = alloca i1, i1 0
-  %nop2445 = alloca i1, i1 0
-  %nop2446 = alloca i1, i1 0
-  %nop2447 = alloca i1, i1 0
-  %nop2448 = alloca i1, i1 0
-  %nop2449 = alloca i1, i1 0
-  %nop2450 = alloca i1, i1 0
-  %nop2451 = alloca i1, i1 0
-  %nop2452 = alloca i1, i1 0
-  %nop2453 = alloca i1, i1 0
-  %nop2454 = alloca i1, i1 0
-  %nop2455 = alloca i1, i1 0
-  %nop2456 = alloca i1, i1 0
-  %nop2457 = alloca i1, i1 0
-  %nop2458 = alloca i1, i1 0
-  %nop2459 = alloca i1, i1 0
-  %nop2460 = alloca i1, i1 0
-  %nop2461 = alloca i1, i1 0
-  %nop2462 = alloca i1, i1 0
-  %nop2463 = alloca i1, i1 0
-  %nop2464 = alloca i1, i1 0
-  %nop2465 = alloca i1, i1 0
-  %nop2466 = alloca i1, i1 0
-  %nop2467 = alloca i1, i1 0
-  %nop2468 = alloca i1, i1 0
-  %nop2469 = alloca i1, i1 0
-  %nop2470 = alloca i1, i1 0
-  %nop2471 = alloca i1, i1 0
-  %nop2472 = alloca i1, i1 0
-  %nop2473 = alloca i1, i1 0
-  %nop2474 = alloca i1, i1 0
-  %nop2475 = alloca i1, i1 0
-  %nop2476 = alloca i1, i1 0
-  %nop2477 = alloca i1, i1 0
-  %nop2478 = alloca i1, i1 0
-  %nop2479 = alloca i1, i1 0
-  %nop2480 = alloca i1, i1 0
-  %nop2481 = alloca i1, i1 0
-  %nop2482 = alloca i1, i1 0
-  %nop2483 = alloca i1, i1 0
-  %nop2484 = alloca i1, i1 0
-  %nop2485 = alloca i1, i1 0
-  %nop2486 = alloca i1, i1 0
-  %nop2487 = alloca i1, i1 0
-  %nop2488 = alloca i1, i1 0
-  %nop2489 = alloca i1, i1 0
-  %nop2490 = alloca i1, i1 0
-  %nop2491 = alloca i1, i1 0
-  %nop2492 = alloca i1, i1 0
-  %nop2493 = alloca i1, i1 0
-  %nop2494 = alloca i1, i1 0
-  %nop2495 = alloca i1, i1 0
-  %nop2496 = alloca i1, i1 0
-  %nop2497 = alloca i1, i1 0
-  %nop2498 = alloca i1, i1 0
-  %nop2499 = alloca i1, i1 0
-  %nop2500 = alloca i1, i1 0
-  %nop2501 = alloca i1, i1 0
-  %nop2502 = alloca i1, i1 0
-  %nop2503 = alloca i1, i1 0
-  %nop2504 = alloca i1, i1 0
-  %nop2505 = alloca i1, i1 0
-  %nop2506 = alloca i1, i1 0
-  %nop2507 = alloca i1, i1 0
-  %nop2508 = alloca i1, i1 0
-  %nop2509 = alloca i1, i1 0
-  %nop2510 = alloca i1, i1 0
-  %nop2511 = alloca i1, i1 0
-  %nop2512 = alloca i1, i1 0
-  %nop2513 = alloca i1, i1 0
-  %nop2514 = alloca i1, i1 0
-  %nop2515 = alloca i1, i1 0
-  %nop2516 = alloca i1, i1 0
-  %nop2517 = alloca i1, i1 0
-  %nop2518 = alloca i1, i1 0
-  %nop2519 = alloca i1, i1 0
-  %nop2520 = alloca i1, i1 0
-  %nop2521 = alloca i1, i1 0
-  %nop2522 = alloca i1, i1 0
-  %nop2523 = alloca i1, i1 0
-  %nop2524 = alloca i1, i1 0
-  %nop2525 = alloca i1, i1 0
-  %nop2526 = alloca i1, i1 0
-  %nop2527 = alloca i1, i1 0
-  %nop2528 = alloca i1, i1 0
-  %nop2529 = alloca i1, i1 0
-  %nop2530 = alloca i1, i1 0
-  %nop2531 = alloca i1, i1 0
-  %nop2532 = alloca i1, i1 0
-  %nop2533 = alloca i1, i1 0
-  %nop2534 = alloca i1, i1 0
-  %nop2535 = alloca i1, i1 0
-  %nop2536 = alloca i1, i1 0
-  %nop2537 = alloca i1, i1 0
-  %nop2538 = alloca i1, i1 0
-  %nop2539 = alloca i1, i1 0
-  %nop2540 = alloca i1, i1 0
-  %nop2541 = alloca i1, i1 0
-  %nop2542 = alloca i1, i1 0
-  %nop2543 = alloca i1, i1 0
-  %nop2544 = alloca i1, i1 0
-  %nop2545 = alloca i1, i1 0
-  %nop2546 = alloca i1, i1 0
-  %nop2547 = alloca i1, i1 0
-  %nop2548 = alloca i1, i1 0
-  %nop2549 = alloca i1, i1 0
-  %nop2550 = alloca i1, i1 0
-  %nop2551 = alloca i1, i1 0
-  %nop2552 = alloca i1, i1 0
-  %nop2553 = alloca i1, i1 0
-  %nop2554 = alloca i1, i1 0
-  %nop2555 = alloca i1, i1 0
-  %nop2556 = alloca i1, i1 0
-  %nop2557 = alloca i1, i1 0
-  %nop2558 = alloca i1, i1 0
-  %nop2559 = alloca i1, i1 0
-  %nop2560 = alloca i1, i1 0
-  %nop2561 = alloca i1, i1 0
-  %nop2562 = alloca i1, i1 0
-  %nop2563 = alloca i1, i1 0
-  %nop2564 = alloca i1, i1 0
-  %nop2565 = alloca i1, i1 0
-  %nop2566 = alloca i1, i1 0
-  %nop2567 = alloca i1, i1 0
-  %nop2568 = alloca i1, i1 0
-  %nop2569 = alloca i1, i1 0
-  %nop2570 = alloca i1, i1 0
-  %nop2571 = alloca i1, i1 0
-  %nop2572 = alloca i1, i1 0
-  %nop2573 = alloca i1, i1 0
-  %nop2574 = alloca i1, i1 0
-  %nop2575 = alloca i1, i1 0
-  %nop2576 = alloca i1, i1 0
-  %nop2577 = alloca i1, i1 0
-  %nop2578 = alloca i1, i1 0
-  %nop2579 = alloca i1, i1 0
-  %nop2580 = alloca i1, i1 0
-  %nop2581 = alloca i1, i1 0
-  %nop2582 = alloca i1, i1 0
-  %nop2583 = alloca i1, i1 0
-  %nop2584 = alloca i1, i1 0
-  %nop2585 = alloca i1, i1 0
-  %nop2586 = alloca i1, i1 0
-  %nop2587 = alloca i1, i1 0
-  %nop2588 = alloca i1, i1 0
-  %nop2589 = alloca i1, i1 0
-  %nop2590 = alloca i1, i1 0
-  %nop2591 = alloca i1, i1 0
-  %nop2592 = alloca i1, i1 0
-  %nop2593 = alloca i1, i1 0
-  %nop2594 = alloca i1, i1 0
-  %nop2595 = alloca i1, i1 0
-  %nop2596 = alloca i1, i1 0
-  %nop2597 = alloca i1, i1 0
-  %nop2598 = alloca i1, i1 0
-  %nop2599 = alloca i1, i1 0
-  %nop2600 = alloca i1, i1 0
-  %nop2601 = alloca i1, i1 0
-  %nop2602 = alloca i1, i1 0
-  %nop2603 = alloca i1, i1 0
-  %nop2604 = alloca i1, i1 0
-  %nop2605 = alloca i1, i1 0
-  %nop2606 = alloca i1, i1 0
-  %nop2607 = alloca i1, i1 0
-  %nop2608 = alloca i1, i1 0
-  %nop2609 = alloca i1, i1 0
-  %nop2610 = alloca i1, i1 0
-  %nop2611 = alloca i1, i1 0
-  %nop2612 = alloca i1, i1 0
-  %nop2613 = alloca i1, i1 0
-  %nop2614 = alloca i1, i1 0
-  %nop2615 = alloca i1, i1 0
-  %nop2616 = alloca i1, i1 0
-  %nop2617 = alloca i1, i1 0
-  %nop2618 = alloca i1, i1 0
-  %nop2619 = alloca i1, i1 0
-  %nop2620 = alloca i1, i1 0
-  %nop2621 = alloca i1, i1 0
-  %nop2622 = alloca i1, i1 0
-  %nop2623 = alloca i1, i1 0
-  %nop2624 = alloca i1, i1 0
-  %nop2625 = alloca i1, i1 0
-  %nop2626 = alloca i1, i1 0
-  %nop2627 = alloca i1, i1 0
-  %nop2628 = alloca i1, i1 0
-  %nop2629 = alloca i1, i1 0
-  %nop2630 = alloca i1, i1 0
-  %nop2631 = alloca i1, i1 0
-  %nop2632 = alloca i1, i1 0
-  %nop2633 = alloca i1, i1 0
-  %nop2634 = alloca i1, i1 0
-  %nop2635 = alloca i1, i1 0
-  %nop2636 = alloca i1, i1 0
-  %nop2637 = alloca i1, i1 0
-  %nop2638 = alloca i1, i1 0
-  %nop2639 = alloca i1, i1 0
-  %nop2640 = alloca i1, i1 0
-  %nop2641 = alloca i1, i1 0
-  %nop2642 = alloca i1, i1 0
-  %nop2643 = alloca i1, i1 0
-  %nop2644 = alloca i1, i1 0
-  %nop2645 = alloca i1, i1 0
-  %nop2646 = alloca i1, i1 0
-  %nop2647 = alloca i1, i1 0
-  %nop2648 = alloca i1, i1 0
-  %nop2649 = alloca i1, i1 0
-  %nop2650 = alloca i1, i1 0
-  %nop2651 = alloca i1, i1 0
-  %nop2652 = alloca i1, i1 0
-  %nop2653 = alloca i1, i1 0
-  %nop2654 = alloca i1, i1 0
-  %nop2655 = alloca i1, i1 0
-  %nop2656 = alloca i1, i1 0
-  %nop2657 = alloca i1, i1 0
-  %nop2658 = alloca i1, i1 0
-  %nop2659 = alloca i1, i1 0
-  %nop2660 = alloca i1, i1 0
-  %nop2661 = alloca i1, i1 0
-  %nop2662 = alloca i1, i1 0
-  %nop2663 = alloca i1, i1 0
-  %nop2664 = alloca i1, i1 0
-  %nop2665 = alloca i1, i1 0
-  %nop2666 = alloca i1, i1 0
-  %nop2667 = alloca i1, i1 0
-  %nop2668 = alloca i1, i1 0
-  %nop2669 = alloca i1, i1 0
-  %nop2670 = alloca i1, i1 0
-  %nop2671 = alloca i1, i1 0
-  %nop2672 = alloca i1, i1 0
-  %nop2673 = alloca i1, i1 0
-  %nop2674 = alloca i1, i1 0
-  %nop2675 = alloca i1, i1 0
-  %nop2676 = alloca i1, i1 0
-  %nop2677 = alloca i1, i1 0
-  %nop2678 = alloca i1, i1 0
-  %nop2679 = alloca i1, i1 0
-  %nop2680 = alloca i1, i1 0
-  %nop2681 = alloca i1, i1 0
-  %nop2682 = alloca i1, i1 0
-  %nop2683 = alloca i1, i1 0
-  %nop2684 = alloca i1, i1 0
-  %nop2685 = alloca i1, i1 0
-  %nop2686 = alloca i1, i1 0
-  %nop2687 = alloca i1, i1 0
-  %nop2688 = alloca i1, i1 0
-  %nop2689 = alloca i1, i1 0
-  %nop2690 = alloca i1, i1 0
-  %nop2691 = alloca i1, i1 0
-  %nop2692 = alloca i1, i1 0
-  %nop2693 = alloca i1, i1 0
-  %nop2694 = alloca i1, i1 0
-  %nop2695 = alloca i1, i1 0
-  %nop2696 = alloca i1, i1 0
-  %nop2697 = alloca i1, i1 0
-  %nop2698 = alloca i1, i1 0
-  %nop2699 = alloca i1, i1 0
-  %nop2700 = alloca i1, i1 0
-  %nop2701 = alloca i1, i1 0
-  %nop2702 = alloca i1, i1 0
-  %nop2703 = alloca i1, i1 0
-  %nop2704 = alloca i1, i1 0
-  %nop2705 = alloca i1, i1 0
-  %nop2706 = alloca i1, i1 0
-  %nop2707 = alloca i1, i1 0
-  %nop2708 = alloca i1, i1 0
-  %nop2709 = alloca i1, i1 0
-  %nop2710 = alloca i1, i1 0
-  %nop2711 = alloca i1, i1 0
-  %nop2712 = alloca i1, i1 0
-  %nop2713 = alloca i1, i1 0
-  %nop2714 = alloca i1, i1 0
-  %nop2715 = alloca i1, i1 0
-  %nop2716 = alloca i1, i1 0
-  %nop2717 = alloca i1, i1 0
-  %nop2718 = alloca i1, i1 0
-  %nop2719 = alloca i1, i1 0
-  %nop2720 = alloca i1, i1 0
-  %nop2721 = alloca i1, i1 0
-  %nop2722 = alloca i1, i1 0
-  %nop2723 = alloca i1, i1 0
-  %nop2724 = alloca i1, i1 0
-  %nop2725 = alloca i1, i1 0
-  %nop2726 = alloca i1, i1 0
-  %nop2727 = alloca i1, i1 0
-  %nop2728 = alloca i1, i1 0
-  %nop2729 = alloca i1, i1 0
-  %nop2730 = alloca i1, i1 0
-  %nop2731 = alloca i1, i1 0
-  %nop2732 = alloca i1, i1 0
-  %nop2733 = alloca i1, i1 0
-  %nop2734 = alloca i1, i1 0
-  %nop2735 = alloca i1, i1 0
-  %nop2736 = alloca i1, i1 0
-  %nop2737 = alloca i1, i1 0
-  %nop2738 = alloca i1, i1 0
-  %nop2739 = alloca i1, i1 0
-  %nop2740 = alloca i1, i1 0
-  %nop2741 = alloca i1, i1 0
-  %nop2742 = alloca i1, i1 0
-  %nop2743 = alloca i1, i1 0
-  %nop2744 = alloca i1, i1 0
-  %nop2745 = alloca i1, i1 0
-  %nop2746 = alloca i1, i1 0
-  %nop2747 = alloca i1, i1 0
-  %nop2748 = alloca i1, i1 0
-  %nop2749 = alloca i1, i1 0
-  %nop2750 = alloca i1, i1 0
-  %nop2751 = alloca i1, i1 0
-  %nop2752 = alloca i1, i1 0
-  %nop2753 = alloca i1, i1 0
-  %nop2754 = alloca i1, i1 0
-  %nop2755 = alloca i1, i1 0
-  %nop2756 = alloca i1, i1 0
-  %nop2757 = alloca i1, i1 0
-  %nop2758 = alloca i1, i1 0
-  %nop2759 = alloca i1, i1 0
-  %nop2760 = alloca i1, i1 0
-  %nop2761 = alloca i1, i1 0
-  %nop2762 = alloca i1, i1 0
-  %nop2763 = alloca i1, i1 0
-  %nop2764 = alloca i1, i1 0
-  %nop2765 = alloca i1, i1 0
-  %nop2766 = alloca i1, i1 0
-  %nop2767 = alloca i1, i1 0
-  %nop2768 = alloca i1, i1 0
-  %nop2769 = alloca i1, i1 0
-  %nop2770 = alloca i1, i1 0
-  %nop2771 = alloca i1, i1 0
-  %nop2772 = alloca i1, i1 0
-  %nop2773 = alloca i1, i1 0
-  %nop2774 = alloca i1, i1 0
-  %nop2775 = alloca i1, i1 0
-  %nop2776 = alloca i1, i1 0
-  %nop2777 = alloca i1, i1 0
-  %nop2778 = alloca i1, i1 0
-  %nop2779 = alloca i1, i1 0
-  %nop2780 = alloca i1, i1 0
-  %nop2781 = alloca i1, i1 0
-  %nop2782 = alloca i1, i1 0
-  %nop2783 = alloca i1, i1 0
-  %nop2784 = alloca i1, i1 0
-  %nop2785 = alloca i1, i1 0
-  %nop2786 = alloca i1, i1 0
-  %nop2787 = alloca i1, i1 0
-  %nop2788 = alloca i1, i1 0
-  %nop2789 = alloca i1, i1 0
-  %nop2790 = alloca i1, i1 0
-  %nop2791 = alloca i1, i1 0
-  %nop2792 = alloca i1, i1 0
-  %nop2793 = alloca i1, i1 0
-  %nop2794 = alloca i1, i1 0
-  %nop2795 = alloca i1, i1 0
-  %nop2796 = alloca i1, i1 0
-  %nop2797 = alloca i1, i1 0
-  %nop2798 = alloca i1, i1 0
-  %nop2799 = alloca i1, i1 0
-  %nop2800 = alloca i1, i1 0
-  %nop2801 = alloca i1, i1 0
-  %nop2802 = alloca i1, i1 0
-  %nop2803 = alloca i1, i1 0
-  %nop2804 = alloca i1, i1 0
-  %nop2805 = alloca i1, i1 0
-  %nop2806 = alloca i1, i1 0
-  %nop2807 = alloca i1, i1 0
-  %nop2808 = alloca i1, i1 0
-  %nop2809 = alloca i1, i1 0
-  %nop2810 = alloca i1, i1 0
-  %nop2811 = alloca i1, i1 0
-  %nop2812 = alloca i1, i1 0
-  %nop2813 = alloca i1, i1 0
-  %nop2814 = alloca i1, i1 0
-  %nop2815 = alloca i1, i1 0
-  %nop2816 = alloca i1, i1 0
-  %nop2817 = alloca i1, i1 0
-  %nop2818 = alloca i1, i1 0
-  %nop2819 = alloca i1, i1 0
-  %nop2820 = alloca i1, i1 0
-  %nop2821 = alloca i1, i1 0
-  %nop2822 = alloca i1, i1 0
-  %nop2823 = alloca i1, i1 0
-  %nop2824 = alloca i1, i1 0
-  %nop2825 = alloca i1, i1 0
-  %nop2826 = alloca i1, i1 0
-  %nop2827 = alloca i1, i1 0
-  %nop2828 = alloca i1, i1 0
-  %nop2829 = alloca i1, i1 0
-  %nop2830 = alloca i1, i1 0
-  %nop2831 = alloca i1, i1 0
-  %nop2832 = alloca i1, i1 0
-  %nop2833 = alloca i1, i1 0
-  %nop2834 = alloca i1, i1 0
-  %nop2835 = alloca i1, i1 0
-  %nop2836 = alloca i1, i1 0
-  %nop2837 = alloca i1, i1 0
-  %nop2838 = alloca i1, i1 0
-  %nop2839 = alloca i1, i1 0
-  %nop2840 = alloca i1, i1 0
-  %nop2841 = alloca i1, i1 0
-  %nop2842 = alloca i1, i1 0
-  %nop2843 = alloca i1, i1 0
-  %nop2844 = alloca i1, i1 0
-  %nop2845 = alloca i1, i1 0
-  %nop2846 = alloca i1, i1 0
-  %nop2847 = alloca i1, i1 0
-  %nop2848 = alloca i1, i1 0
-  %nop2849 = alloca i1, i1 0
-  %nop2850 = alloca i1, i1 0
-  %nop2851 = alloca i1, i1 0
-  %nop2852 = alloca i1, i1 0
-  %nop2853 = alloca i1, i1 0
-  %nop2854 = alloca i1, i1 0
-  %nop2855 = alloca i1, i1 0
-  %nop2856 = alloca i1, i1 0
-  %nop2857 = alloca i1, i1 0
-  %nop2858 = alloca i1, i1 0
-  %nop2859 = alloca i1, i1 0
-  %nop2860 = alloca i1, i1 0
-  %nop2861 = alloca i1, i1 0
-  %nop2862 = alloca i1, i1 0
-  %nop2863 = alloca i1, i1 0
-  %nop2864 = alloca i1, i1 0
-  %nop2865 = alloca i1, i1 0
-  %nop2866 = alloca i1, i1 0
-  %nop2867 = alloca i1, i1 0
-  %nop2868 = alloca i1, i1 0
-  %nop2869 = alloca i1, i1 0
-  %nop2870 = alloca i1, i1 0
-  %nop2871 = alloca i1, i1 0
-  %nop2872 = alloca i1, i1 0
-  %nop2873 = alloca i1, i1 0
-  %nop2874 = alloca i1, i1 0
-  %nop2875 = alloca i1, i1 0
-  %nop2876 = alloca i1, i1 0
-  %nop2877 = alloca i1, i1 0
-  %nop2878 = alloca i1, i1 0
-  %nop2879 = alloca i1, i1 0
-  %nop2880 = alloca i1, i1 0
-  %nop2881 = alloca i1, i1 0
-  %nop2882 = alloca i1, i1 0
-  %nop2883 = alloca i1, i1 0
-  %nop2884 = alloca i1, i1 0
-  %nop2885 = alloca i1, i1 0
-  %nop2886 = alloca i1, i1 0
-  %nop2887 = alloca i1, i1 0
-  %nop2888 = alloca i1, i1 0
-  %nop2889 = alloca i1, i1 0
-  %nop2890 = alloca i1, i1 0
-  %nop2891 = alloca i1, i1 0
-  %nop2892 = alloca i1, i1 0
-  %nop2893 = alloca i1, i1 0
-  %nop2894 = alloca i1, i1 0
-  %nop2895 = alloca i1, i1 0
-  %nop2896 = alloca i1, i1 0
-  %nop2897 = alloca i1, i1 0
-  %nop2898 = alloca i1, i1 0
-  %nop2899 = alloca i1, i1 0
-  %nop2900 = alloca i1, i1 0
-  %nop2901 = alloca i1, i1 0
-  %nop2902 = alloca i1, i1 0
-  %nop2903 = alloca i1, i1 0
-  %nop2904 = alloca i1, i1 0
-  %nop2905 = alloca i1, i1 0
-  %nop2906 = alloca i1, i1 0
-  %nop2907 = alloca i1, i1 0
-  %nop2908 = alloca i1, i1 0
-  %nop2909 = alloca i1, i1 0
-  %nop2910 = alloca i1, i1 0
-  %nop2911 = alloca i1, i1 0
-  %nop2912 = alloca i1, i1 0
-  %nop2913 = alloca i1, i1 0
-  %nop2914 = alloca i1, i1 0
-  %nop2915 = alloca i1, i1 0
-  %nop2916 = alloca i1, i1 0
-  %nop2917 = alloca i1, i1 0
-  %nop2918 = alloca i1, i1 0
-  %nop2919 = alloca i1, i1 0
-  %nop2920 = alloca i1, i1 0
-  %nop2921 = alloca i1, i1 0
-  %nop2922 = alloca i1, i1 0
-  %nop2923 = alloca i1, i1 0
-  %nop2924 = alloca i1, i1 0
-  %nop2925 = alloca i1, i1 0
-  %nop2926 = alloca i1, i1 0
-  %nop2927 = alloca i1, i1 0
-  %nop2928 = alloca i1, i1 0
-  %nop2929 = alloca i1, i1 0
-  %nop2930 = alloca i1, i1 0
-  %nop2931 = alloca i1, i1 0
-  %nop2932 = alloca i1, i1 0
-  %nop2933 = alloca i1, i1 0
-  %nop2934 = alloca i1, i1 0
-  %nop2935 = alloca i1, i1 0
-  %nop2936 = alloca i1, i1 0
-  %nop2937 = alloca i1, i1 0
-  %nop2938 = alloca i1, i1 0
-  %nop2939 = alloca i1, i1 0
-  %nop2940 = alloca i1, i1 0
-  %nop2941 = alloca i1, i1 0
-  %nop2942 = alloca i1, i1 0
-  %nop2943 = alloca i1, i1 0
-  %nop2944 = alloca i1, i1 0
-  %nop2945 = alloca i1, i1 0
-  %nop2946 = alloca i1, i1 0
-  %nop2947 = alloca i1, i1 0
-  %nop2948 = alloca i1, i1 0
-  %nop2949 = alloca i1, i1 0
-  %nop2950 = alloca i1, i1 0
-  %nop2951 = alloca i1, i1 0
-  %nop2952 = alloca i1, i1 0
-  %nop2953 = alloca i1, i1 0
-  %nop2954 = alloca i1, i1 0
-  %nop2955 = alloca i1, i1 0
-  %nop2956 = alloca i1, i1 0
-  %nop2957 = alloca i1, i1 0
-  %nop2958 = alloca i1, i1 0
-  %nop2959 = alloca i1, i1 0
-  %nop2960 = alloca i1, i1 0
-  %nop2961 = alloca i1, i1 0
-  %nop2962 = alloca i1, i1 0
-  %nop2963 = alloca i1, i1 0
-  %nop2964 = alloca i1, i1 0
-  %nop2965 = alloca i1, i1 0
-  %nop2966 = alloca i1, i1 0
-  %nop2967 = alloca i1, i1 0
-  %nop2968 = alloca i1, i1 0
-  %nop2969 = alloca i1, i1 0
-  %nop2970 = alloca i1, i1 0
-  %nop2971 = alloca i1, i1 0
-  %nop2972 = alloca i1, i1 0
-  %nop2973 = alloca i1, i1 0
-  %nop2974 = alloca i1, i1 0
-  %nop2975 = alloca i1, i1 0
-  %nop2976 = alloca i1, i1 0
-  %nop2977 = alloca i1, i1 0
-  %nop2978 = alloca i1, i1 0
-  %nop2979 = alloca i1, i1 0
-  %nop2980 = alloca i1, i1 0
-  %nop2981 = alloca i1, i1 0
-  %nop2982 = alloca i1, i1 0
-  %nop2983 = alloca i1, i1 0
-  %nop2984 = alloca i1, i1 0
-  %nop2985 = alloca i1, i1 0
-  %nop2986 = alloca i1, i1 0
-  %nop2987 = alloca i1, i1 0
-  %nop2988 = alloca i1, i1 0
-  %nop2989 = alloca i1, i1 0
-  %nop2990 = alloca i1, i1 0
-  %nop2991 = alloca i1, i1 0
-  %nop2992 = alloca i1, i1 0
-  %nop2993 = alloca i1, i1 0
-  %nop2994 = alloca i1, i1 0
-  %nop2995 = alloca i1, i1 0
-  %nop2996 = alloca i1, i1 0
-  %nop2997 = alloca i1, i1 0
-  %nop2998 = alloca i1, i1 0
-  %nop2999 = alloca i1, i1 0
-  %nop3000 = alloca i1, i1 0
-  %nop3001 = alloca i1, i1 0
-  %nop3002 = alloca i1, i1 0
-  %nop3003 = alloca i1, i1 0
-  %nop3004 = alloca i1, i1 0
-  %nop3005 = alloca i1, i1 0
-  %nop3006 = alloca i1, i1 0
-  %nop3007 = alloca i1, i1 0
-  %nop3008 = alloca i1, i1 0
-  %nop3009 = alloca i1, i1 0
-  %nop3010 = alloca i1, i1 0
-  %nop3011 = alloca i1, i1 0
-  %nop3012 = alloca i1, i1 0
-  %nop3013 = alloca i1, i1 0
-  %nop3014 = alloca i1, i1 0
-  %nop3015 = alloca i1, i1 0
-  %nop3016 = alloca i1, i1 0
-  %nop3017 = alloca i1, i1 0
-  %nop3018 = alloca i1, i1 0
-  %nop3019 = alloca i1, i1 0
-  %nop3020 = alloca i1, i1 0
-  %nop3021 = alloca i1, i1 0
-  %nop3022 = alloca i1, i1 0
-  %nop3023 = alloca i1, i1 0
-  %nop3024 = alloca i1, i1 0
-  %nop3025 = alloca i1, i1 0
-  %nop3026 = alloca i1, i1 0
-  %nop3027 = alloca i1, i1 0
-  %nop3028 = alloca i1, i1 0
-  %nop3029 = alloca i1, i1 0
-  %nop3030 = alloca i1, i1 0
-  %nop3031 = alloca i1, i1 0
-  %nop3032 = alloca i1, i1 0
-  %nop3033 = alloca i1, i1 0
-  %nop3034 = alloca i1, i1 0
-  %nop3035 = alloca i1, i1 0
-  %nop3036 = alloca i1, i1 0
-  %nop3037 = alloca i1, i1 0
-  %nop3038 = alloca i1, i1 0
-  %nop3039 = alloca i1, i1 0
-  %nop3040 = alloca i1, i1 0
-  %nop3041 = alloca i1, i1 0
-  %nop3042 = alloca i1, i1 0
-  %nop3043 = alloca i1, i1 0
-  %nop3044 = alloca i1, i1 0
-  %nop3045 = alloca i1, i1 0
-  %nop3046 = alloca i1, i1 0
-  %nop3047 = alloca i1, i1 0
-  %nop3048 = alloca i1, i1 0
-  %nop3049 = alloca i1, i1 0
-  %nop3050 = alloca i1, i1 0
-  %nop3051 = alloca i1, i1 0
-  %nop3052 = alloca i1, i1 0
-  %nop3053 = alloca i1, i1 0
-  %nop3054 = alloca i1, i1 0
-  %nop3055 = alloca i1, i1 0
-  %nop3056 = alloca i1, i1 0
-  %nop3057 = alloca i1, i1 0
-  %nop3058 = alloca i1, i1 0
-  %nop3059 = alloca i1, i1 0
-  %nop3060 = alloca i1, i1 0
-  %nop3061 = alloca i1, i1 0
-  %nop3062 = alloca i1, i1 0
-  %nop3063 = alloca i1, i1 0
-  %nop3064 = alloca i1, i1 0
-  %nop3065 = alloca i1, i1 0
-  %nop3066 = alloca i1, i1 0
-  %nop3067 = alloca i1, i1 0
-  %nop3068 = alloca i1, i1 0
-  %nop3069 = alloca i1, i1 0
-  %nop3070 = alloca i1, i1 0
-  %nop3071 = alloca i1, i1 0
-  %nop3072 = alloca i1, i1 0
-  %nop3073 = alloca i1, i1 0
-  %nop3074 = alloca i1, i1 0
-  %nop3075 = alloca i1, i1 0
-  %nop3076 = alloca i1, i1 0
-  %nop3077 = alloca i1, i1 0
-  %nop3078 = alloca i1, i1 0
-  %nop3079 = alloca i1, i1 0
-  %nop3080 = alloca i1, i1 0
-  %nop3081 = alloca i1, i1 0
-  %nop3082 = alloca i1, i1 0
-  %nop3083 = alloca i1, i1 0
-  %nop3084 = alloca i1, i1 0
-  %nop3085 = alloca i1, i1 0
-  %nop3086 = alloca i1, i1 0
-  %nop3087 = alloca i1, i1 0
-  %nop3088 = alloca i1, i1 0
-  %nop3089 = alloca i1, i1 0
-  %nop3090 = alloca i1, i1 0
-  %nop3091 = alloca i1, i1 0
-  %nop3092 = alloca i1, i1 0
-  %nop3093 = alloca i1, i1 0
-  %nop3094 = alloca i1, i1 0
-  %nop3095 = alloca i1, i1 0
-  %nop3096 = alloca i1, i1 0
-  %nop3097 = alloca i1, i1 0
-  %nop3098 = alloca i1, i1 0
-  %nop3099 = alloca i1, i1 0
-  %nop3100 = alloca i1, i1 0
-  %nop3101 = alloca i1, i1 0
-  %nop3102 = alloca i1, i1 0
-  %nop3103 = alloca i1, i1 0
-  %nop3104 = alloca i1, i1 0
-  %nop3105 = alloca i1, i1 0
-  %nop3106 = alloca i1, i1 0
-  %nop3107 = alloca i1, i1 0
-  %nop3108 = alloca i1, i1 0
-  %nop3109 = alloca i1, i1 0
-  %nop3110 = alloca i1, i1 0
-  %nop3111 = alloca i1, i1 0
-  %nop3112 = alloca i1, i1 0
-  %nop3113 = alloca i1, i1 0
-  %nop3114 = alloca i1, i1 0
-  %nop3115 = alloca i1, i1 0
-  %nop3116 = alloca i1, i1 0
-  %nop3117 = alloca i1, i1 0
-  %nop3118 = alloca i1, i1 0
-  %nop3119 = alloca i1, i1 0
-  %nop3120 = alloca i1, i1 0
-  %nop3121 = alloca i1, i1 0
-  %nop3122 = alloca i1, i1 0
-  %nop3123 = alloca i1, i1 0
-  %nop3124 = alloca i1, i1 0
-  %nop3125 = alloca i1, i1 0
-  %nop3126 = alloca i1, i1 0
-  %nop3127 = alloca i1, i1 0
-  %nop3128 = alloca i1, i1 0
-  %nop3129 = alloca i1, i1 0
-  %nop3130 = alloca i1, i1 0
-  %nop3131 = alloca i1, i1 0
-  %nop3132 = alloca i1, i1 0
-  %nop3133 = alloca i1, i1 0
-  %nop3134 = alloca i1, i1 0
-  %nop3135 = alloca i1, i1 0
-  %nop3136 = alloca i1, i1 0
-  %nop3137 = alloca i1, i1 0
-  %nop3138 = alloca i1, i1 0
-  %nop3139 = alloca i1, i1 0
-  %nop3140 = alloca i1, i1 0
-  %nop3141 = alloca i1, i1 0
-  %nop3142 = alloca i1, i1 0
-  %nop3143 = alloca i1, i1 0
-  %nop3144 = alloca i1, i1 0
-  %nop3145 = alloca i1, i1 0
-  %nop3146 = alloca i1, i1 0
-  %nop3147 = alloca i1, i1 0
-  %nop3148 = alloca i1, i1 0
-  %nop3149 = alloca i1, i1 0
-  %nop3150 = alloca i1, i1 0
-  %nop3151 = alloca i1, i1 0
-  %nop3152 = alloca i1, i1 0
-  %nop3153 = alloca i1, i1 0
-  %nop3154 = alloca i1, i1 0
-  %nop3155 = alloca i1, i1 0
-  %nop3156 = alloca i1, i1 0
-  %nop3157 = alloca i1, i1 0
-  %nop3158 = alloca i1, i1 0
-  %nop3159 = alloca i1, i1 0
-  %nop3160 = alloca i1, i1 0
-  %nop3161 = alloca i1, i1 0
-  %nop3162 = alloca i1, i1 0
-  %nop3163 = alloca i1, i1 0
-  %nop3164 = alloca i1, i1 0
-  %nop3165 = alloca i1, i1 0
-  %nop3166 = alloca i1, i1 0
-  %nop3167 = alloca i1, i1 0
-  %nop3168 = alloca i1, i1 0
-  %nop3169 = alloca i1, i1 0
-  %nop3170 = alloca i1, i1 0
-  %nop3171 = alloca i1, i1 0
-  %nop3172 = alloca i1, i1 0
-  %nop3173 = alloca i1, i1 0
-  %nop3174 = alloca i1, i1 0
-  %nop3175 = alloca i1, i1 0
-  %nop3176 = alloca i1, i1 0
-  %nop3177 = alloca i1, i1 0
-  %nop3178 = alloca i1, i1 0
-  %nop3179 = alloca i1, i1 0
-  %nop3180 = alloca i1, i1 0
-  %nop3181 = alloca i1, i1 0
-  %nop3182 = alloca i1, i1 0
-  %nop3183 = alloca i1, i1 0
-  %nop3184 = alloca i1, i1 0
-  %nop3185 = alloca i1, i1 0
-  %nop3186 = alloca i1, i1 0
-  %nop3187 = alloca i1, i1 0
-  %nop3188 = alloca i1, i1 0
-  %nop3189 = alloca i1, i1 0
-  %nop3190 = alloca i1, i1 0
-  %nop3191 = alloca i1, i1 0
-  %nop3192 = alloca i1, i1 0
-  %nop3193 = alloca i1, i1 0
-  %nop3194 = alloca i1, i1 0
-  %nop3195 = alloca i1, i1 0
-  %nop3196 = alloca i1, i1 0
-  %nop3197 = alloca i1, i1 0
-  %nop3198 = alloca i1, i1 0
-  %nop3199 = alloca i1, i1 0
-  %nop3200 = alloca i1, i1 0
-  %nop3201 = alloca i1, i1 0
-  %nop3202 = alloca i1, i1 0
-  %nop3203 = alloca i1, i1 0
-  %nop3204 = alloca i1, i1 0
-  %nop3205 = alloca i1, i1 0
-  %nop3206 = alloca i1, i1 0
-  %nop3207 = alloca i1, i1 0
-  %nop3208 = alloca i1, i1 0
-  %nop3209 = alloca i1, i1 0
-  %nop3210 = alloca i1, i1 0
-  %nop3211 = alloca i1, i1 0
-  %nop3212 = alloca i1, i1 0
-  %nop3213 = alloca i1, i1 0
-  %nop3214 = alloca i1, i1 0
-  %nop3215 = alloca i1, i1 0
-  %nop3216 = alloca i1, i1 0
-  %nop3217 = alloca i1, i1 0
-  %nop3218 = alloca i1, i1 0
-  %nop3219 = alloca i1, i1 0
-  %nop3220 = alloca i1, i1 0
-  %nop3221 = alloca i1, i1 0
-  %nop3222 = alloca i1, i1 0
-  %nop3223 = alloca i1, i1 0
-  %nop3224 = alloca i1, i1 0
-  %nop3225 = alloca i1, i1 0
-  %nop3226 = alloca i1, i1 0
-  %nop3227 = alloca i1, i1 0
-  %nop3228 = alloca i1, i1 0
-  %nop3229 = alloca i1, i1 0
-  %nop3230 = alloca i1, i1 0
-  %nop3231 = alloca i1, i1 0
-  %nop3232 = alloca i1, i1 0
-  %nop3233 = alloca i1, i1 0
-  %nop3234 = alloca i1, i1 0
-  %nop3235 = alloca i1, i1 0
-  %nop3236 = alloca i1, i1 0
-  %nop3237 = alloca i1, i1 0
-  %nop3238 = alloca i1, i1 0
-  %nop3239 = alloca i1, i1 0
-  %nop3240 = alloca i1, i1 0
-  %nop3241 = alloca i1, i1 0
-  %nop3242 = alloca i1, i1 0
-  %nop3243 = alloca i1, i1 0
-  %nop3244 = alloca i1, i1 0
-  %nop3245 = alloca i1, i1 0
-  %nop3246 = alloca i1, i1 0
-  %nop3247 = alloca i1, i1 0
-  %nop3248 = alloca i1, i1 0
-  %nop3249 = alloca i1, i1 0
-  %nop3250 = alloca i1, i1 0
-  %nop3251 = alloca i1, i1 0
-  %nop3252 = alloca i1, i1 0
-  %nop3253 = alloca i1, i1 0
-  %nop3254 = alloca i1, i1 0
-  %nop3255 = alloca i1, i1 0
-  %nop3256 = alloca i1, i1 0
-  %nop3257 = alloca i1, i1 0
-  %nop3258 = alloca i1, i1 0
-  %nop3259 = alloca i1, i1 0
-  %nop3260 = alloca i1, i1 0
-  %nop3261 = alloca i1, i1 0
-  %nop3262 = alloca i1, i1 0
-  %nop3263 = alloca i1, i1 0
-  %nop3264 = alloca i1, i1 0
-  %nop3265 = alloca i1, i1 0
-  %nop3266 = alloca i1, i1 0
-  %nop3267 = alloca i1, i1 0
-  %nop3268 = alloca i1, i1 0
-  %nop3269 = alloca i1, i1 0
-  %nop3270 = alloca i1, i1 0
-  %nop3271 = alloca i1, i1 0
-  %nop3272 = alloca i1, i1 0
-  %nop3273 = alloca i1, i1 0
-  %nop3274 = alloca i1, i1 0
-  %nop3275 = alloca i1, i1 0
-  %nop3276 = alloca i1, i1 0
-  %nop3277 = alloca i1, i1 0
-  %nop3278 = alloca i1, i1 0
-  %nop3279 = alloca i1, i1 0
-  %nop3280 = alloca i1, i1 0
-  %nop3281 = alloca i1, i1 0
-  %nop3282 = alloca i1, i1 0
-  %nop3283 = alloca i1, i1 0
-  %nop3284 = alloca i1, i1 0
-  %nop3285 = alloca i1, i1 0
-  %nop3286 = alloca i1, i1 0
-  %nop3287 = alloca i1, i1 0
-  %nop3288 = alloca i1, i1 0
-  %nop3289 = alloca i1, i1 0
-  %nop3290 = alloca i1, i1 0
-  %nop3291 = alloca i1, i1 0
-  %nop3292 = alloca i1, i1 0
-  %nop3293 = alloca i1, i1 0
-  %nop3294 = alloca i1, i1 0
-  %nop3295 = alloca i1, i1 0
-  %nop3296 = alloca i1, i1 0
-  %nop3297 = alloca i1, i1 0
-  %nop3298 = alloca i1, i1 0
-  %nop3299 = alloca i1, i1 0
-  %nop3300 = alloca i1, i1 0
-  %nop3301 = alloca i1, i1 0
-  %nop3302 = alloca i1, i1 0
-  %nop3303 = alloca i1, i1 0
-  %nop3304 = alloca i1, i1 0
-  %nop3305 = alloca i1, i1 0
-  %nop3306 = alloca i1, i1 0
-  %nop3307 = alloca i1, i1 0
-  %nop3308 = alloca i1, i1 0
-  %nop3309 = alloca i1, i1 0
-  %nop3310 = alloca i1, i1 0
-  %nop3311 = alloca i1, i1 0
-  %nop3312 = alloca i1, i1 0
-  %nop3313 = alloca i1, i1 0
-  %nop3314 = alloca i1, i1 0
-  %nop3315 = alloca i1, i1 0
-  %nop3316 = alloca i1, i1 0
-  %nop3317 = alloca i1, i1 0
-  %nop3318 = alloca i1, i1 0
-  %nop3319 = alloca i1, i1 0
-  %nop3320 = alloca i1, i1 0
-  %nop3321 = alloca i1, i1 0
-  %nop3322 = alloca i1, i1 0
-  %nop3323 = alloca i1, i1 0
-  %nop3324 = alloca i1, i1 0
-  %nop3325 = alloca i1, i1 0
-  %nop3326 = alloca i1, i1 0
-  %nop3327 = alloca i1, i1 0
-  %nop3328 = alloca i1, i1 0
-  %nop3329 = alloca i1, i1 0
-  %nop3330 = alloca i1, i1 0
-  %nop3331 = alloca i1, i1 0
-  %nop3332 = alloca i1, i1 0
-  %nop3333 = alloca i1, i1 0
-  %nop3334 = alloca i1, i1 0
-  %nop3335 = alloca i1, i1 0
-  %nop3336 = alloca i1, i1 0
-  %nop3337 = alloca i1, i1 0
-  %nop3338 = alloca i1, i1 0
-  %nop3339 = alloca i1, i1 0
-  %nop3340 = alloca i1, i1 0
-  %nop3341 = alloca i1, i1 0
-  %nop3342 = alloca i1, i1 0
-  %nop3343 = alloca i1, i1 0
-  %nop3344 = alloca i1, i1 0
-  %nop3345 = alloca i1, i1 0
-  %nop3346 = alloca i1, i1 0
-  %nop3347 = alloca i1, i1 0
-  %nop3348 = alloca i1, i1 0
-  %nop3349 = alloca i1, i1 0
-  %nop3350 = alloca i1, i1 0
-  %nop3351 = alloca i1, i1 0
-  %nop3352 = alloca i1, i1 0
-  %nop3353 = alloca i1, i1 0
-  %nop3354 = alloca i1, i1 0
-  %nop3355 = alloca i1, i1 0
-  %nop3356 = alloca i1, i1 0
-  %nop3357 = alloca i1, i1 0
-  %nop3358 = alloca i1, i1 0
-  %nop3359 = alloca i1, i1 0
-  %nop3360 = alloca i1, i1 0
-  %nop3361 = alloca i1, i1 0
-  %nop3362 = alloca i1, i1 0
-  %nop3363 = alloca i1, i1 0
-  %nop3364 = alloca i1, i1 0
-  %nop3365 = alloca i1, i1 0
-  %nop3366 = alloca i1, i1 0
-  %nop3367 = alloca i1, i1 0
-  %nop3368 = alloca i1, i1 0
-  %nop3369 = alloca i1, i1 0
-  %nop3370 = alloca i1, i1 0
-  %nop3371 = alloca i1, i1 0
-  %nop3372 = alloca i1, i1 0
-  %nop3373 = alloca i1, i1 0
-  %nop3374 = alloca i1, i1 0
-  %nop3375 = alloca i1, i1 0
-  %nop3376 = alloca i1, i1 0
-  %nop3377 = alloca i1, i1 0
-  %nop3378 = alloca i1, i1 0
-  %nop3379 = alloca i1, i1 0
-  %nop3380 = alloca i1, i1 0
-  %nop3381 = alloca i1, i1 0
-  %nop3382 = alloca i1, i1 0
-  %nop3383 = alloca i1, i1 0
-  %nop3384 = alloca i1, i1 0
-  %nop3385 = alloca i1, i1 0
-  %nop3386 = alloca i1, i1 0
-  %nop3387 = alloca i1, i1 0
-  %nop3388 = alloca i1, i1 0
-  %nop3389 = alloca i1, i1 0
-  %nop3390 = alloca i1, i1 0
-  %nop3391 = alloca i1, i1 0
-  %nop3392 = alloca i1, i1 0
-  %nop3393 = alloca i1, i1 0
-  %nop3394 = alloca i1, i1 0
-  %nop3395 = alloca i1, i1 0
-  %nop3396 = alloca i1, i1 0
-  %nop3397 = alloca i1, i1 0
-  %nop3398 = alloca i1, i1 0
-  %nop3399 = alloca i1, i1 0
-  %nop3400 = alloca i1, i1 0
-  %nop3401 = alloca i1, i1 0
-  %nop3402 = alloca i1, i1 0
-  %nop3403 = alloca i1, i1 0
-  %nop3404 = alloca i1, i1 0
-  %nop3405 = alloca i1, i1 0
-  %nop3406 = alloca i1, i1 0
-  %nop3407 = alloca i1, i1 0
-  %nop3408 = alloca i1, i1 0
-  %nop3409 = alloca i1, i1 0
-  %nop3410 = alloca i1, i1 0
-  %nop3411 = alloca i1, i1 0
-  %nop3412 = alloca i1, i1 0
-  %nop3413 = alloca i1, i1 0
-  %nop3414 = alloca i1, i1 0
-  %nop3415 = alloca i1, i1 0
-  %nop3416 = alloca i1, i1 0
-  %nop3417 = alloca i1, i1 0
-  %nop3418 = alloca i1, i1 0
-  %nop3419 = alloca i1, i1 0
-  %nop3420 = alloca i1, i1 0
-  %nop3421 = alloca i1, i1 0
-  %nop3422 = alloca i1, i1 0
-  %nop3423 = alloca i1, i1 0
-  %nop3424 = alloca i1, i1 0
-  %nop3425 = alloca i1, i1 0
-  %nop3426 = alloca i1, i1 0
-  %nop3427 = alloca i1, i1 0
-  %nop3428 = alloca i1, i1 0
-  %nop3429 = alloca i1, i1 0
-  %nop3430 = alloca i1, i1 0
-  %nop3431 = alloca i1, i1 0
-  %nop3432 = alloca i1, i1 0
-  %nop3433 = alloca i1, i1 0
-  %nop3434 = alloca i1, i1 0
-  %nop3435 = alloca i1, i1 0
-  %nop3436 = alloca i1, i1 0
-  %nop3437 = alloca i1, i1 0
-  %nop3438 = alloca i1, i1 0
-  %nop3439 = alloca i1, i1 0
-  %nop3440 = alloca i1, i1 0
-  %nop3441 = alloca i1, i1 0
-  %nop3442 = alloca i1, i1 0
-  %nop3443 = alloca i1, i1 0
-  %nop3444 = alloca i1, i1 0
-  %nop3445 = alloca i1, i1 0
-  %nop3446 = alloca i1, i1 0
-  %nop3447 = alloca i1, i1 0
-  %nop3448 = alloca i1, i1 0
-  %nop3449 = alloca i1, i1 0
-  %nop3450 = alloca i1, i1 0
-  %nop3451 = alloca i1, i1 0
-  %nop3452 = alloca i1, i1 0
-  %nop3453 = alloca i1, i1 0
-  %nop3454 = alloca i1, i1 0
-  %nop3455 = alloca i1, i1 0
-  %nop3456 = alloca i1, i1 0
-  %nop3457 = alloca i1, i1 0
-  %nop3458 = alloca i1, i1 0
-  %nop3459 = alloca i1, i1 0
-  %nop3460 = alloca i1, i1 0
-  %nop3461 = alloca i1, i1 0
-  %nop3462 = alloca i1, i1 0
-  %nop3463 = alloca i1, i1 0
-  %nop3464 = alloca i1, i1 0
-  %nop3465 = alloca i1, i1 0
-  %nop3466 = alloca i1, i1 0
-  %nop3467 = alloca i1, i1 0
-  %nop3468 = alloca i1, i1 0
-  %nop3469 = alloca i1, i1 0
-  %nop3470 = alloca i1, i1 0
-  %nop3471 = alloca i1, i1 0
-  %nop3472 = alloca i1, i1 0
-  %nop3473 = alloca i1, i1 0
-  %nop3474 = alloca i1, i1 0
-  %nop3475 = alloca i1, i1 0
-  %nop3476 = alloca i1, i1 0
-  %nop3477 = alloca i1, i1 0
-  %nop3478 = alloca i1, i1 0
-  %nop3479 = alloca i1, i1 0
-  %nop3480 = alloca i1, i1 0
-  %nop3481 = alloca i1, i1 0
-  %nop3482 = alloca i1, i1 0
-  %nop3483 = alloca i1, i1 0
-  %nop3484 = alloca i1, i1 0
-  %nop3485 = alloca i1, i1 0
-  %nop3486 = alloca i1, i1 0
-  %nop3487 = alloca i1, i1 0
-  %nop3488 = alloca i1, i1 0
-  %nop3489 = alloca i1, i1 0
-  %nop3490 = alloca i1, i1 0
-  %nop3491 = alloca i1, i1 0
-  %nop3492 = alloca i1, i1 0
-  %nop3493 = alloca i1, i1 0
-  %nop3494 = alloca i1, i1 0
-  %nop3495 = alloca i1, i1 0
-  %nop3496 = alloca i1, i1 0
-  %nop3497 = alloca i1, i1 0
-  %nop3498 = alloca i1, i1 0
-  %nop3499 = alloca i1, i1 0
-  %nop3500 = alloca i1, i1 0
-  %nop3501 = alloca i1, i1 0
-  %nop3502 = alloca i1, i1 0
-  %nop3503 = alloca i1, i1 0
-  %nop3504 = alloca i1, i1 0
-  %nop3505 = alloca i1, i1 0
-  %nop3506 = alloca i1, i1 0
-  %nop3507 = alloca i1, i1 0
-  %nop3508 = alloca i1, i1 0
-  %nop3509 = alloca i1, i1 0
-  %nop3510 = alloca i1, i1 0
-  %nop3511 = alloca i1, i1 0
-  %nop3512 = alloca i1, i1 0
-  %nop3513 = alloca i1, i1 0
-  %nop3514 = alloca i1, i1 0
-  %nop3515 = alloca i1, i1 0
-  %nop3516 = alloca i1, i1 0
-  %nop3517 = alloca i1, i1 0
-  %nop3518 = alloca i1, i1 0
-  %nop3519 = alloca i1, i1 0
-  %nop3520 = alloca i1, i1 0
-  %nop3521 = alloca i1, i1 0
-  %nop3522 = alloca i1, i1 0
-  %nop3523 = alloca i1, i1 0
-  %nop3524 = alloca i1, i1 0
-  %nop3525 = alloca i1, i1 0
-  %nop3526 = alloca i1, i1 0
-  %nop3527 = alloca i1, i1 0
-  %nop3528 = alloca i1, i1 0
-  %nop3529 = alloca i1, i1 0
-  %nop3530 = alloca i1, i1 0
-  %nop3531 = alloca i1, i1 0
-  %nop3532 = alloca i1, i1 0
-  %nop3533 = alloca i1, i1 0
-  %nop3534 = alloca i1, i1 0
-  %nop3535 = alloca i1, i1 0
-  %nop3536 = alloca i1, i1 0
-  %nop3537 = alloca i1, i1 0
-  %nop3538 = alloca i1, i1 0
-  %nop3539 = alloca i1, i1 0
-  %nop3540 = alloca i1, i1 0
-  %nop3541 = alloca i1, i1 0
-  %nop3542 = alloca i1, i1 0
-  %nop3543 = alloca i1, i1 0
-  %nop3544 = alloca i1, i1 0
-  %nop3545 = alloca i1, i1 0
-  %nop3546 = alloca i1, i1 0
-  %nop3547 = alloca i1, i1 0
-  %nop3548 = alloca i1, i1 0
-  %nop3549 = alloca i1, i1 0
-  %nop3550 = alloca i1, i1 0
-  %nop3551 = alloca i1, i1 0
-  %nop3552 = alloca i1, i1 0
-  %nop3553 = alloca i1, i1 0
-  %nop3554 = alloca i1, i1 0
-  %nop3555 = alloca i1, i1 0
-  %nop3556 = alloca i1, i1 0
-  %nop3557 = alloca i1, i1 0
-  %nop3558 = alloca i1, i1 0
-  %nop3559 = alloca i1, i1 0
-  %nop3560 = alloca i1, i1 0
-  %nop3561 = alloca i1, i1 0
-  %nop3562 = alloca i1, i1 0
-  %nop3563 = alloca i1, i1 0
-  %nop3564 = alloca i1, i1 0
-  %nop3565 = alloca i1, i1 0
-  %nop3566 = alloca i1, i1 0
-  %nop3567 = alloca i1, i1 0
-  %nop3568 = alloca i1, i1 0
-  %nop3569 = alloca i1, i1 0
-  %nop3570 = alloca i1, i1 0
-  %nop3571 = alloca i1, i1 0
-  %nop3572 = alloca i1, i1 0
-  %nop3573 = alloca i1, i1 0
-  %nop3574 = alloca i1, i1 0
-  %nop3575 = alloca i1, i1 0
-  %nop3576 = alloca i1, i1 0
-  %nop3577 = alloca i1, i1 0
-  %nop3578 = alloca i1, i1 0
-  %nop3579 = alloca i1, i1 0
-  %nop3580 = alloca i1, i1 0
-  %nop3581 = alloca i1, i1 0
-  %nop3582 = alloca i1, i1 0
-  %nop3583 = alloca i1, i1 0
-  %nop3584 = alloca i1, i1 0
-  %nop3585 = alloca i1, i1 0
-  %nop3586 = alloca i1, i1 0
-  %nop3587 = alloca i1, i1 0
-  %nop3588 = alloca i1, i1 0
-  %nop3589 = alloca i1, i1 0
-  %nop3590 = alloca i1, i1 0
-  %nop3591 = alloca i1, i1 0
-  %nop3592 = alloca i1, i1 0
-  %nop3593 = alloca i1, i1 0
-  %nop3594 = alloca i1, i1 0
-  %nop3595 = alloca i1, i1 0
-  %nop3596 = alloca i1, i1 0
-  %nop3597 = alloca i1, i1 0
-  %nop3598 = alloca i1, i1 0
-  %nop3599 = alloca i1, i1 0
-  %nop3600 = alloca i1, i1 0
-  %nop3601 = alloca i1, i1 0
-  %nop3602 = alloca i1, i1 0
-  %nop3603 = alloca i1, i1 0
-  %nop3604 = alloca i1, i1 0
-  %nop3605 = alloca i1, i1 0
-  %nop3606 = alloca i1, i1 0
-  %nop3607 = alloca i1, i1 0
-  %nop3608 = alloca i1, i1 0
-  %nop3609 = alloca i1, i1 0
-  %nop3610 = alloca i1, i1 0
-  %nop3611 = alloca i1, i1 0
-  %nop3612 = alloca i1, i1 0
-  %nop3613 = alloca i1, i1 0
-  %nop3614 = alloca i1, i1 0
-  %nop3615 = alloca i1, i1 0
-  %nop3616 = alloca i1, i1 0
-  %nop3617 = alloca i1, i1 0
-  %nop3618 = alloca i1, i1 0
-  %nop3619 = alloca i1, i1 0
-  %nop3620 = alloca i1, i1 0
-  %nop3621 = alloca i1, i1 0
-  %nop3622 = alloca i1, i1 0
-  %nop3623 = alloca i1, i1 0
-  %nop3624 = alloca i1, i1 0
-  %nop3625 = alloca i1, i1 0
-  %nop3626 = alloca i1, i1 0
-  %nop3627 = alloca i1, i1 0
-  %nop3628 = alloca i1, i1 0
-  %nop3629 = alloca i1, i1 0
-  %nop3630 = alloca i1, i1 0
-  %nop3631 = alloca i1, i1 0
-  %nop3632 = alloca i1, i1 0
-  %nop3633 = alloca i1, i1 0
-  %nop3634 = alloca i1, i1 0
-  %nop3635 = alloca i1, i1 0
-  %nop3636 = alloca i1, i1 0
-  %nop3637 = alloca i1, i1 0
-  %nop3638 = alloca i1, i1 0
-  %nop3639 = alloca i1, i1 0
-  %nop3640 = alloca i1, i1 0
-  %nop3641 = alloca i1, i1 0
-  %nop3642 = alloca i1, i1 0
-  %nop3643 = alloca i1, i1 0
-  %nop3644 = alloca i1, i1 0
-  %nop3645 = alloca i1, i1 0
-  %nop3646 = alloca i1, i1 0
-  %nop3647 = alloca i1, i1 0
-  %nop3648 = alloca i1, i1 0
-  %nop3649 = alloca i1, i1 0
-  %nop3650 = alloca i1, i1 0
-  %nop3651 = alloca i1, i1 0
-  %nop3652 = alloca i1, i1 0
-  %nop3653 = alloca i1, i1 0
-  %nop3654 = alloca i1, i1 0
-  %nop3655 = alloca i1, i1 0
-  %nop3656 = alloca i1, i1 0
-  %nop3657 = alloca i1, i1 0
-  %nop3658 = alloca i1, i1 0
-  %nop3659 = alloca i1, i1 0
-  %nop3660 = alloca i1, i1 0
-  %nop3661 = alloca i1, i1 0
-  %nop3662 = alloca i1, i1 0
-  %nop3663 = alloca i1, i1 0
-  %nop3664 = alloca i1, i1 0
-  %nop3665 = alloca i1, i1 0
-  %nop3666 = alloca i1, i1 0
-  %nop3667 = alloca i1, i1 0
-  %nop3668 = alloca i1, i1 0
-  %nop3669 = alloca i1, i1 0
-  %nop3670 = alloca i1, i1 0
-  %nop3671 = alloca i1, i1 0
-  %nop3672 = alloca i1, i1 0
-  %nop3673 = alloca i1, i1 0
-  %nop3674 = alloca i1, i1 0
-  %nop3675 = alloca i1, i1 0
-  %nop3676 = alloca i1, i1 0
-  %nop3677 = alloca i1, i1 0
-  %nop3678 = alloca i1, i1 0
-  %nop3679 = alloca i1, i1 0
-  %nop3680 = alloca i1, i1 0
-  %nop3681 = alloca i1, i1 0
-  %nop3682 = alloca i1, i1 0
-  %nop3683 = alloca i1, i1 0
-  %nop3684 = alloca i1, i1 0
-  %nop3685 = alloca i1, i1 0
-  %nop3686 = alloca i1, i1 0
-  %nop3687 = alloca i1, i1 0
-  %nop3688 = alloca i1, i1 0
-  %nop3689 = alloca i1, i1 0
-  %nop3690 = alloca i1, i1 0
-  %nop3691 = alloca i1, i1 0
-  %nop3692 = alloca i1, i1 0
-  %nop3693 = alloca i1, i1 0
-  %nop3694 = alloca i1, i1 0
-  %nop3695 = alloca i1, i1 0
-  %nop3696 = alloca i1, i1 0
-  %nop3697 = alloca i1, i1 0
-  %nop3698 = alloca i1, i1 0
-  %nop3699 = alloca i1, i1 0
-  %nop3700 = alloca i1, i1 0
-  %nop3701 = alloca i1, i1 0
-  %nop3702 = alloca i1, i1 0
-  %nop3703 = alloca i1, i1 0
-  %nop3704 = alloca i1, i1 0
-  %nop3705 = alloca i1, i1 0
-  %nop3706 = alloca i1, i1 0
-  %nop3707 = alloca i1, i1 0
-  %nop3708 = alloca i1, i1 0
-  %nop3709 = alloca i1, i1 0
-  %nop3710 = alloca i1, i1 0
-  %nop3711 = alloca i1, i1 0
-  %nop3712 = alloca i1, i1 0
-  %nop3713 = alloca i1, i1 0
-  %nop3714 = alloca i1, i1 0
-  %nop3715 = alloca i1, i1 0
-  %nop3716 = alloca i1, i1 0
-  %nop3717 = alloca i1, i1 0
-  %nop3718 = alloca i1, i1 0
-  %nop3719 = alloca i1, i1 0
-  %nop3720 = alloca i1, i1 0
-  %nop3721 = alloca i1, i1 0
-  %nop3722 = alloca i1, i1 0
-  %nop3723 = alloca i1, i1 0
-  %nop3724 = alloca i1, i1 0
-  %nop3725 = alloca i1, i1 0
-  %nop3726 = alloca i1, i1 0
-  %nop3727 = alloca i1, i1 0
-  %nop3728 = alloca i1, i1 0
-  %nop3729 = alloca i1, i1 0
-  %nop3730 = alloca i1, i1 0
-  %nop3731 = alloca i1, i1 0
-  %nop3732 = alloca i1, i1 0
-  %nop3733 = alloca i1, i1 0
-  %nop3734 = alloca i1, i1 0
-  %nop3735 = alloca i1, i1 0
-  %nop3736 = alloca i1, i1 0
-  %nop3737 = alloca i1, i1 0
-  %nop3738 = alloca i1, i1 0
-  %nop3739 = alloca i1, i1 0
-  %nop3740 = alloca i1, i1 0
-  %nop3741 = alloca i1, i1 0
-  %nop3742 = alloca i1, i1 0
-  %nop3743 = alloca i1, i1 0
-  %nop3744 = alloca i1, i1 0
-  %nop3745 = alloca i1, i1 0
-  %nop3746 = alloca i1, i1 0
-  %nop3747 = alloca i1, i1 0
-  %nop3748 = alloca i1, i1 0
-  %nop3749 = alloca i1, i1 0
-  %nop3750 = alloca i1, i1 0
-  %nop3751 = alloca i1, i1 0
-  %nop3752 = alloca i1, i1 0
-  %nop3753 = alloca i1, i1 0
-  %nop3754 = alloca i1, i1 0
-  %nop3755 = alloca i1, i1 0
-  %nop3756 = alloca i1, i1 0
-  %nop3757 = alloca i1, i1 0
-  %nop3758 = alloca i1, i1 0
-  %nop3759 = alloca i1, i1 0
-  %nop3760 = alloca i1, i1 0
-  %nop3761 = alloca i1, i1 0
-  %nop3762 = alloca i1, i1 0
-  %nop3763 = alloca i1, i1 0
-  %nop3764 = alloca i1, i1 0
-  %nop3765 = alloca i1, i1 0
-  %nop3766 = alloca i1, i1 0
-  %nop3767 = alloca i1, i1 0
-  %nop3768 = alloca i1, i1 0
-  %nop3769 = alloca i1, i1 0
-  %nop3770 = alloca i1, i1 0
-  %nop3771 = alloca i1, i1 0
-  %nop3772 = alloca i1, i1 0
-  %nop3773 = alloca i1, i1 0
-  %nop3774 = alloca i1, i1 0
-  %nop3775 = alloca i1, i1 0
-  %nop3776 = alloca i1, i1 0
-  %nop3777 = alloca i1, i1 0
-  %nop3778 = alloca i1, i1 0
-  %nop3779 = alloca i1, i1 0
-  %nop3780 = alloca i1, i1 0
-  %nop3781 = alloca i1, i1 0
-  %nop3782 = alloca i1, i1 0
-  %nop3783 = alloca i1, i1 0
-  %nop3784 = alloca i1, i1 0
-  %nop3785 = alloca i1, i1 0
-  %nop3786 = alloca i1, i1 0
-  %nop3787 = alloca i1, i1 0
-  %nop3788 = alloca i1, i1 0
-  %nop3789 = alloca i1, i1 0
-  %nop3790 = alloca i1, i1 0
-  %nop3791 = alloca i1, i1 0
-  %nop3792 = alloca i1, i1 0
-  %nop3793 = alloca i1, i1 0
-  %nop3794 = alloca i1, i1 0
-  %nop3795 = alloca i1, i1 0
-  %nop3796 = alloca i1, i1 0
-  %nop3797 = alloca i1, i1 0
-  %nop3798 = alloca i1, i1 0
-  %nop3799 = alloca i1, i1 0
-  %nop3800 = alloca i1, i1 0
-  %nop3801 = alloca i1, i1 0
-  %nop3802 = alloca i1, i1 0
-  %nop3803 = alloca i1, i1 0
-  %nop3804 = alloca i1, i1 0
-  %nop3805 = alloca i1, i1 0
-  %nop3806 = alloca i1, i1 0
-  %nop3807 = alloca i1, i1 0
-  %nop3808 = alloca i1, i1 0
-  %nop3809 = alloca i1, i1 0
-  %nop3810 = alloca i1, i1 0
-  %nop3811 = alloca i1, i1 0
-  %nop3812 = alloca i1, i1 0
-  %nop3813 = alloca i1, i1 0
-  %nop3814 = alloca i1, i1 0
-  %nop3815 = alloca i1, i1 0
-  %nop3816 = alloca i1, i1 0
-  %nop3817 = alloca i1, i1 0
-  %nop3818 = alloca i1, i1 0
-  %nop3819 = alloca i1, i1 0
-  %nop3820 = alloca i1, i1 0
-  %nop3821 = alloca i1, i1 0
-  %nop3822 = alloca i1, i1 0
-  %nop3823 = alloca i1, i1 0
-  %nop3824 = alloca i1, i1 0
-  %nop3825 = alloca i1, i1 0
-  %nop3826 = alloca i1, i1 0
-  %nop3827 = alloca i1, i1 0
-  %nop3828 = alloca i1, i1 0
-  %nop3829 = alloca i1, i1 0
-  %nop3830 = alloca i1, i1 0
-  %nop3831 = alloca i1, i1 0
-  %nop3832 = alloca i1, i1 0
-  %nop3833 = alloca i1, i1 0
-  %nop3834 = alloca i1, i1 0
-  %nop3835 = alloca i1, i1 0
-  %nop3836 = alloca i1, i1 0
-  %nop3837 = alloca i1, i1 0
-  %nop3838 = alloca i1, i1 0
-  %nop3839 = alloca i1, i1 0
-  %nop3840 = alloca i1, i1 0
-  %nop3841 = alloca i1, i1 0
-  %nop3842 = alloca i1, i1 0
-  %nop3843 = alloca i1, i1 0
-  %nop3844 = alloca i1, i1 0
-  %nop3845 = alloca i1, i1 0
-  %nop3846 = alloca i1, i1 0
-  %nop3847 = alloca i1, i1 0
-  %nop3848 = alloca i1, i1 0
-  %nop3849 = alloca i1, i1 0
-  %nop3850 = alloca i1, i1 0
-  %nop3851 = alloca i1, i1 0
-  %nop3852 = alloca i1, i1 0
-  %nop3853 = alloca i1, i1 0
-  %nop3854 = alloca i1, i1 0
-  %nop3855 = alloca i1, i1 0
-  %nop3856 = alloca i1, i1 0
-  %nop3857 = alloca i1, i1 0
-  %nop3858 = alloca i1, i1 0
-  %nop3859 = alloca i1, i1 0
-  %nop3860 = alloca i1, i1 0
-  %nop3861 = alloca i1, i1 0
-  %nop3862 = alloca i1, i1 0
-  %nop3863 = alloca i1, i1 0
-  %nop3864 = alloca i1, i1 0
-  %nop3865 = alloca i1, i1 0
-  %nop3866 = alloca i1, i1 0
-  %nop3867 = alloca i1, i1 0
-  %nop3868 = alloca i1, i1 0
-  %nop3869 = alloca i1, i1 0
-  %nop3870 = alloca i1, i1 0
-  %nop3871 = alloca i1, i1 0
-  %nop3872 = alloca i1, i1 0
-  %nop3873 = alloca i1, i1 0
-  %nop3874 = alloca i1, i1 0
-  %nop3875 = alloca i1, i1 0
-  %nop3876 = alloca i1, i1 0
-  %nop3877 = alloca i1, i1 0
-  %nop3878 = alloca i1, i1 0
-  %nop3879 = alloca i1, i1 0
-  %nop3880 = alloca i1, i1 0
-  %nop3881 = alloca i1, i1 0
-  %nop3882 = alloca i1, i1 0
-  %nop3883 = alloca i1, i1 0
-  %nop3884 = alloca i1, i1 0
-  %nop3885 = alloca i1, i1 0
-  %nop3886 = alloca i1, i1 0
-  %nop3887 = alloca i1, i1 0
-  %nop3888 = alloca i1, i1 0
-  %nop3889 = alloca i1, i1 0
-  %nop3890 = alloca i1, i1 0
-  %nop3891 = alloca i1, i1 0
-  %nop3892 = alloca i1, i1 0
-  %nop3893 = alloca i1, i1 0
-  %nop3894 = alloca i1, i1 0
-  %nop3895 = alloca i1, i1 0
-  %nop3896 = alloca i1, i1 0
-  %nop3897 = alloca i1, i1 0
-  %nop3898 = alloca i1, i1 0
-  %nop3899 = alloca i1, i1 0
-  %nop3900 = alloca i1, i1 0
-  %nop3901 = alloca i1, i1 0
-  %nop3902 = alloca i1, i1 0
-  %nop3903 = alloca i1, i1 0
-  %nop3904 = alloca i1, i1 0
-  %nop3905 = alloca i1, i1 0
-  %nop3906 = alloca i1, i1 0
-  %nop3907 = alloca i1, i1 0
-  %nop3908 = alloca i1, i1 0
-  %nop3909 = alloca i1, i1 0
-  %nop3910 = alloca i1, i1 0
-  %nop3911 = alloca i1, i1 0
-  %nop3912 = alloca i1, i1 0
-  %nop3913 = alloca i1, i1 0
-  %nop3914 = alloca i1, i1 0
-  %nop3915 = alloca i1, i1 0
-  %nop3916 = alloca i1, i1 0
-  %nop3917 = alloca i1, i1 0
-  %nop3918 = alloca i1, i1 0
-  %nop3919 = alloca i1, i1 0
-  %nop3920 = alloca i1, i1 0
-  %nop3921 = alloca i1, i1 0
-  %nop3922 = alloca i1, i1 0
-  %nop3923 = alloca i1, i1 0
-  %nop3924 = alloca i1, i1 0
-  %nop3925 = alloca i1, i1 0
-  %nop3926 = alloca i1, i1 0
-  %nop3927 = alloca i1, i1 0
-  %nop3928 = alloca i1, i1 0
-  %nop3929 = alloca i1, i1 0
-  %nop3930 = alloca i1, i1 0
-  %nop3931 = alloca i1, i1 0
-  %nop3932 = alloca i1, i1 0
-  %nop3933 = alloca i1, i1 0
-  %nop3934 = alloca i1, i1 0
-  %nop3935 = alloca i1, i1 0
-  %nop3936 = alloca i1, i1 0
-  %nop3937 = alloca i1, i1 0
-  %nop3938 = alloca i1, i1 0
-  %nop3939 = alloca i1, i1 0
-  %nop3940 = alloca i1, i1 0
-  %nop3941 = alloca i1, i1 0
-  %nop3942 = alloca i1, i1 0
-  %nop3943 = alloca i1, i1 0
-  %nop3944 = alloca i1, i1 0
-  %nop3945 = alloca i1, i1 0
-  %nop3946 = alloca i1, i1 0
-  %nop3947 = alloca i1, i1 0
-  %nop3948 = alloca i1, i1 0
-  %nop3949 = alloca i1, i1 0
-  %nop3950 = alloca i1, i1 0
-  %nop3951 = alloca i1, i1 0
-  %nop3952 = alloca i1, i1 0
-  %nop3953 = alloca i1, i1 0
-  %nop3954 = alloca i1, i1 0
-  %nop3955 = alloca i1, i1 0
-  %nop3956 = alloca i1, i1 0
-  %nop3957 = alloca i1, i1 0
-  %nop3958 = alloca i1, i1 0
-  %nop3959 = alloca i1, i1 0
-  %nop3960 = alloca i1, i1 0
-  %nop3961 = alloca i1, i1 0
-  %nop3962 = alloca i1, i1 0
-  %nop3963 = alloca i1, i1 0
-  %nop3964 = alloca i1, i1 0
-  %nop3965 = alloca i1, i1 0
-  %nop3966 = alloca i1, i1 0
-  %nop3967 = alloca i1, i1 0
-  %nop3968 = alloca i1, i1 0
-  %nop3969 = alloca i1, i1 0
-  %nop3970 = alloca i1, i1 0
-  %nop3971 = alloca i1, i1 0
-  %nop3972 = alloca i1, i1 0
-  %nop3973 = alloca i1, i1 0
-  %nop3974 = alloca i1, i1 0
-  %nop3975 = alloca i1, i1 0
-  %nop3976 = alloca i1, i1 0
-  %nop3977 = alloca i1, i1 0
-  %nop3978 = alloca i1, i1 0
-  %nop3979 = alloca i1, i1 0
-  %nop3980 = alloca i1, i1 0
-  %nop3981 = alloca i1, i1 0
-  %nop3982 = alloca i1, i1 0
-  %nop3983 = alloca i1, i1 0
-  %nop3984 = alloca i1, i1 0
-  %nop3985 = alloca i1, i1 0
-  %nop3986 = alloca i1, i1 0
-  %nop3987 = alloca i1, i1 0
-  %nop3988 = alloca i1, i1 0
-  %nop3989 = alloca i1, i1 0
-  %nop3990 = alloca i1, i1 0
-  %nop3991 = alloca i1, i1 0
-  %nop3992 = alloca i1, i1 0
-  %nop3993 = alloca i1, i1 0
-  %nop3994 = alloca i1, i1 0
-  %nop3995 = alloca i1, i1 0
-  %nop3996 = alloca i1, i1 0
-  %nop3997 = alloca i1, i1 0
-  %nop3998 = alloca i1, i1 0
-  %nop3999 = alloca i1, i1 0
-  %nop4000 = alloca i1, i1 0
-  %nop4001 = alloca i1, i1 0
-  %nop4002 = alloca i1, i1 0
-  %nop4003 = alloca i1, i1 0
-  %nop4004 = alloca i1, i1 0
-  %nop4005 = alloca i1, i1 0
-  %nop4006 = alloca i1, i1 0
-  %nop4007 = alloca i1, i1 0
-  %nop4008 = alloca i1, i1 0
-  %nop4009 = alloca i1, i1 0
-  %nop4010 = alloca i1, i1 0
-  %nop4011 = alloca i1, i1 0
-  %nop4012 = alloca i1, i1 0
-  %nop4013 = alloca i1, i1 0
-  %nop4014 = alloca i1, i1 0
-  %nop4015 = alloca i1, i1 0
-  %nop4016 = alloca i1, i1 0
-  %nop4017 = alloca i1, i1 0
-  %nop4018 = alloca i1, i1 0
-  %nop4019 = alloca i1, i1 0
-  %nop4020 = alloca i1, i1 0
-  %nop4021 = alloca i1, i1 0
-  %nop4022 = alloca i1, i1 0
-  %nop4023 = alloca i1, i1 0
-  %nop4024 = alloca i1, i1 0
-  %nop4025 = alloca i1, i1 0
-  %nop4026 = alloca i1, i1 0
-  %nop4027 = alloca i1, i1 0
-  %nop4028 = alloca i1, i1 0
-  %nop4029 = alloca i1, i1 0
-  %nop4030 = alloca i1, i1 0
-  %nop4031 = alloca i1, i1 0
-  %nop4032 = alloca i1, i1 0
-  %nop4033 = alloca i1, i1 0
-  %nop4034 = alloca i1, i1 0
-  %nop4035 = alloca i1, i1 0
-  %nop4036 = alloca i1, i1 0
-  %nop4037 = alloca i1, i1 0
-  %nop4038 = alloca i1, i1 0
-  %nop4039 = alloca i1, i1 0
-  %nop4040 = alloca i1, i1 0
-  %nop4041 = alloca i1, i1 0
-  %nop4042 = alloca i1, i1 0
-  %nop4043 = alloca i1, i1 0
-  %nop4044 = alloca i1, i1 0
-  %nop4045 = alloca i1, i1 0
-  %nop4046 = alloca i1, i1 0
-  %nop4047 = alloca i1, i1 0
-  %nop4048 = alloca i1, i1 0
-  %nop4049 = alloca i1, i1 0
-  %nop4050 = alloca i1, i1 0
-  %nop4051 = alloca i1, i1 0
-  %nop4052 = alloca i1, i1 0
-  %nop4053 = alloca i1, i1 0
-  %nop4054 = alloca i1, i1 0
-  %nop4055 = alloca i1, i1 0
-  %nop4056 = alloca i1, i1 0
-  %nop4057 = alloca i1, i1 0
-  %nop4058 = alloca i1, i1 0
-  %nop4059 = alloca i1, i1 0
-  %nop4060 = alloca i1, i1 0
-  %nop4061 = alloca i1, i1 0
-  %nop4062 = alloca i1, i1 0
-  %nop4063 = alloca i1, i1 0
-  %nop4064 = alloca i1, i1 0
-  %nop4065 = alloca i1, i1 0
-  %nop4066 = alloca i1, i1 0
-  %nop4067 = alloca i1, i1 0
-  %nop4068 = alloca i1, i1 0
-  %nop4069 = alloca i1, i1 0
-  %nop4070 = alloca i1, i1 0
-  %nop4071 = alloca i1, i1 0
-  %nop4072 = alloca i1, i1 0
-  %nop4073 = alloca i1, i1 0
-  %nop4074 = alloca i1, i1 0
-  %nop4075 = alloca i1, i1 0
-  %nop4076 = alloca i1, i1 0
-  %nop4077 = alloca i1, i1 0
-  %nop4078 = alloca i1, i1 0
-  %nop4079 = alloca i1, i1 0
-  %nop4080 = alloca i1, i1 0
-  %nop4081 = alloca i1, i1 0
-  %nop4082 = alloca i1, i1 0
-  %nop4083 = alloca i1, i1 0
-  %nop4084 = alloca i1, i1 0
-  %nop4085 = alloca i1, i1 0
-  %nop4086 = alloca i1, i1 0
-  %nop4087 = alloca i1, i1 0
-  %nop4088 = alloca i1, i1 0
-  %nop4089 = alloca i1, i1 0
-  %nop4090 = alloca i1, i1 0
-  %nop4091 = alloca i1, i1 0
-  %nop4092 = alloca i1, i1 0
-  %nop4093 = alloca i1, i1 0
-  %nop4094 = alloca i1, i1 0
-  %nop4095 = alloca i1, i1 0
-  %nop4096 = alloca i1, i1 0
-  %nop4097 = alloca i1, i1 0
-  %nop4098 = alloca i1, i1 0
-  %nop4099 = alloca i1, i1 0
-  %nop4100 = alloca i1, i1 0
-  %nop4101 = alloca i1, i1 0
-  %nop4102 = alloca i1, i1 0
-  %nop4103 = alloca i1, i1 0
-  %nop4104 = alloca i1, i1 0
-  %nop4105 = alloca i1, i1 0
-  %nop4106 = alloca i1, i1 0
-  %nop4107 = alloca i1, i1 0
-  %nop4108 = alloca i1, i1 0
-  %nop4109 = alloca i1, i1 0
-  %nop4110 = alloca i1, i1 0
-  %nop4111 = alloca i1, i1 0
-  %nop4112 = alloca i1, i1 0
-  %nop4113 = alloca i1, i1 0
-  %nop4114 = alloca i1, i1 0
-  %nop4115 = alloca i1, i1 0
-  %nop4116 = alloca i1, i1 0
-  %nop4117 = alloca i1, i1 0
-  %nop4118 = alloca i1, i1 0
-  %nop4119 = alloca i1, i1 0
-  %nop4120 = alloca i1, i1 0
-  %nop4121 = alloca i1, i1 0
-  %nop4122 = alloca i1, i1 0
-  %nop4123 = alloca i1, i1 0
-  %nop4124 = alloca i1, i1 0
-  %nop4125 = alloca i1, i1 0
-  %nop4126 = alloca i1, i1 0
-  %nop4127 = alloca i1, i1 0
-  %nop4128 = alloca i1, i1 0
-  %nop4129 = alloca i1, i1 0
-  %nop4130 = alloca i1, i1 0
-  %nop4131 = alloca i1, i1 0
-  %nop4132 = alloca i1, i1 0
-  %nop4133 = alloca i1, i1 0
-  %nop4134 = alloca i1, i1 0
-  %nop4135 = alloca i1, i1 0
-  %nop4136 = alloca i1, i1 0
-  %nop4137 = alloca i1, i1 0
-  %nop4138 = alloca i1, i1 0
-  %nop4139 = alloca i1, i1 0
-  %nop4140 = alloca i1, i1 0
-  %nop4141 = alloca i1, i1 0
-  %nop4142 = alloca i1, i1 0
-  %nop4143 = alloca i1, i1 0
-  %nop4144 = alloca i1, i1 0
-  %nop4145 = alloca i1, i1 0
-  %nop4146 = alloca i1, i1 0
-  %nop4147 = alloca i1, i1 0
-  %nop4148 = alloca i1, i1 0
-  %nop4149 = alloca i1, i1 0
-  %nop4150 = alloca i1, i1 0
-  %nop4151 = alloca i1, i1 0
-  %nop4152 = alloca i1, i1 0
-  %nop4153 = alloca i1, i1 0
-  %nop4154 = alloca i1, i1 0
-  %nop4155 = alloca i1, i1 0
-  %nop4156 = alloca i1, i1 0
-  %nop4157 = alloca i1, i1 0
-  %nop4158 = alloca i1, i1 0
-  %nop4159 = alloca i1, i1 0
-  %nop4160 = alloca i1, i1 0
-  %nop4161 = alloca i1, i1 0
-  %nop4162 = alloca i1, i1 0
-  %nop4163 = alloca i1, i1 0
-  %nop4164 = alloca i1, i1 0
-  %nop4165 = alloca i1, i1 0
-  %nop4166 = alloca i1, i1 0
-  %nop4167 = alloca i1, i1 0
-  %nop4168 = alloca i1, i1 0
-  %nop4169 = alloca i1, i1 0
-  %nop4170 = alloca i1, i1 0
-  %nop4171 = alloca i1, i1 0
-  %nop4172 = alloca i1, i1 0
-  %nop4173 = alloca i1, i1 0
-  %nop4174 = alloca i1, i1 0
-  %nop4175 = alloca i1, i1 0
-  %nop4176 = alloca i1, i1 0
-  %nop4177 = alloca i1, i1 0
-  %nop4178 = alloca i1, i1 0
-  %nop4179 = alloca i1, i1 0
-  %nop4180 = alloca i1, i1 0
-  %nop4181 = alloca i1, i1 0
-  %nop4182 = alloca i1, i1 0
-  %nop4183 = alloca i1, i1 0
-  %nop4184 = alloca i1, i1 0
-  %nop4185 = alloca i1, i1 0
-  %nop4186 = alloca i1, i1 0
-  %nop4187 = alloca i1, i1 0
-  %nop4188 = alloca i1, i1 0
-  %nop4189 = alloca i1, i1 0
-  %nop4190 = alloca i1, i1 0
-  %nop4191 = alloca i1, i1 0
-  %nop4192 = alloca i1, i1 0
-  %nop4193 = alloca i1, i1 0
-  %nop4194 = alloca i1, i1 0
-  %nop4195 = alloca i1, i1 0
-  %nop4196 = alloca i1, i1 0
-  %nop4197 = alloca i1, i1 0
-  %nop4198 = alloca i1, i1 0
-  %nop4199 = alloca i1, i1 0
-  %nop4200 = alloca i1, i1 0
-  %nop4201 = alloca i1, i1 0
-  %nop4202 = alloca i1, i1 0
-  %nop4203 = alloca i1, i1 0
-  %nop4204 = alloca i1, i1 0
-  %nop4205 = alloca i1, i1 0
-  %nop4206 = alloca i1, i1 0
-  %nop4207 = alloca i1, i1 0
-  %nop4208 = alloca i1, i1 0
-  %nop4209 = alloca i1, i1 0
-  %nop4210 = alloca i1, i1 0
-  %nop4211 = alloca i1, i1 0
-  %nop4212 = alloca i1, i1 0
-  %nop4213 = alloca i1, i1 0
-  %nop4214 = alloca i1, i1 0
-  %nop4215 = alloca i1, i1 0
-  %nop4216 = alloca i1, i1 0
-  %nop4217 = alloca i1, i1 0
-  %nop4218 = alloca i1, i1 0
-  %nop4219 = alloca i1, i1 0
-  %nop4220 = alloca i1, i1 0
-  %nop4221 = alloca i1, i1 0
-  %nop4222 = alloca i1, i1 0
-  %nop4223 = alloca i1, i1 0
-  %nop4224 = alloca i1, i1 0
-  %nop4225 = alloca i1, i1 0
-  %nop4226 = alloca i1, i1 0
-  %nop4227 = alloca i1, i1 0
-  %nop4228 = alloca i1, i1 0
-  %nop4229 = alloca i1, i1 0
-  %nop4230 = alloca i1, i1 0
-  %nop4231 = alloca i1, i1 0
-  %nop4232 = alloca i1, i1 0
-  %nop4233 = alloca i1, i1 0
-  %nop4234 = alloca i1, i1 0
-  %nop4235 = alloca i1, i1 0
-  %nop4236 = alloca i1, i1 0
-  %nop4237 = alloca i1, i1 0
-  %nop4238 = alloca i1, i1 0
-  %nop4239 = alloca i1, i1 0
-  %nop4240 = alloca i1, i1 0
-  %nop4241 = alloca i1, i1 0
-  %nop4242 = alloca i1, i1 0
-  %nop4243 = alloca i1, i1 0
-  %nop4244 = alloca i1, i1 0
-  %nop4245 = alloca i1, i1 0
-  %nop4246 = alloca i1, i1 0
-  %nop4247 = alloca i1, i1 0
-  %nop4248 = alloca i1, i1 0
-  %nop4249 = alloca i1, i1 0
-  %nop4250 = alloca i1, i1 0
-  %nop4251 = alloca i1, i1 0
-  %nop4252 = alloca i1, i1 0
-  %nop4253 = alloca i1, i1 0
-  %nop4254 = alloca i1, i1 0
-  %nop4255 = alloca i1, i1 0
-  %nop4256 = alloca i1, i1 0
-  %nop4257 = alloca i1, i1 0
-  %nop4258 = alloca i1, i1 0
-  %nop4259 = alloca i1, i1 0
-  %nop4260 = alloca i1, i1 0
-  %nop4261 = alloca i1, i1 0
-  %nop4262 = alloca i1, i1 0
-  %nop4263 = alloca i1, i1 0
-  %nop4264 = alloca i1, i1 0
-  %nop4265 = alloca i1, i1 0
-  %nop4266 = alloca i1, i1 0
-  %nop4267 = alloca i1, i1 0
-  %nop4268 = alloca i1, i1 0
-  %nop4269 = alloca i1, i1 0
-  %nop4270 = alloca i1, i1 0
-  %nop4271 = alloca i1, i1 0
-  %nop4272 = alloca i1, i1 0
-  %nop4273 = alloca i1, i1 0
-  %nop4274 = alloca i1, i1 0
-  %nop4275 = alloca i1, i1 0
-  %nop4276 = alloca i1, i1 0
-  %nop4277 = alloca i1, i1 0
-  %nop4278 = alloca i1, i1 0
-  %nop4279 = alloca i1, i1 0
-  %nop4280 = alloca i1, i1 0
-  %nop4281 = alloca i1, i1 0
-  %nop4282 = alloca i1, i1 0
-  %nop4283 = alloca i1, i1 0
-  %nop4284 = alloca i1, i1 0
-  %nop4285 = alloca i1, i1 0
-  %nop4286 = alloca i1, i1 0
-  %nop4287 = alloca i1, i1 0
-  %nop4288 = alloca i1, i1 0
-  %nop4289 = alloca i1, i1 0
-  %nop4290 = alloca i1, i1 0
-  %nop4291 = alloca i1, i1 0
-  %nop4292 = alloca i1, i1 0
-  %nop4293 = alloca i1, i1 0
-  %nop4294 = alloca i1, i1 0
-  %nop4295 = alloca i1, i1 0
-  %nop4296 = alloca i1, i1 0
-  %nop4297 = alloca i1, i1 0
-  %nop4298 = alloca i1, i1 0
-  %nop4299 = alloca i1, i1 0
-  %nop4300 = alloca i1, i1 0
-  %nop4301 = alloca i1, i1 0
-  %nop4302 = alloca i1, i1 0
-  %nop4303 = alloca i1, i1 0
-  %nop4304 = alloca i1, i1 0
-  %nop4305 = alloca i1, i1 0
-  %nop4306 = alloca i1, i1 0
-  %nop4307 = alloca i1, i1 0
-  %nop4308 = alloca i1, i1 0
-  %nop4309 = alloca i1, i1 0
-  %nop4310 = alloca i1, i1 0
-  %nop4311 = alloca i1, i1 0
-  %nop4312 = alloca i1, i1 0
-  %nop4313 = alloca i1, i1 0
-  %nop4314 = alloca i1, i1 0
-  %nop4315 = alloca i1, i1 0
-  %nop4316 = alloca i1, i1 0
-  %nop4317 = alloca i1, i1 0
-  %nop4318 = alloca i1, i1 0
-  %nop4319 = alloca i1, i1 0
-  %nop4320 = alloca i1, i1 0
-  %nop4321 = alloca i1, i1 0
-  %nop4322 = alloca i1, i1 0
-  %nop4323 = alloca i1, i1 0
-  %nop4324 = alloca i1, i1 0
-  %nop4325 = alloca i1, i1 0
-  %nop4326 = alloca i1, i1 0
-  %nop4327 = alloca i1, i1 0
-  %nop4328 = alloca i1, i1 0
-  %nop4329 = alloca i1, i1 0
-  %nop4330 = alloca i1, i1 0
-  %nop4331 = alloca i1, i1 0
-  %nop4332 = alloca i1, i1 0
-  %nop4333 = alloca i1, i1 0
-  %nop4334 = alloca i1, i1 0
-  %nop4335 = alloca i1, i1 0
-  %nop4336 = alloca i1, i1 0
-  %nop4337 = alloca i1, i1 0
-  %nop4338 = alloca i1, i1 0
-  %nop4339 = alloca i1, i1 0
-  %nop4340 = alloca i1, i1 0
-  %nop4341 = alloca i1, i1 0
-  %nop4342 = alloca i1, i1 0
-  %nop4343 = alloca i1, i1 0
-  %nop4344 = alloca i1, i1 0
-  %nop4345 = alloca i1, i1 0
-  %nop4346 = alloca i1, i1 0
-  %nop4347 = alloca i1, i1 0
-  %nop4348 = alloca i1, i1 0
-  %nop4349 = alloca i1, i1 0
-  %nop4350 = alloca i1, i1 0
-  %nop4351 = alloca i1, i1 0
-  %nop4352 = alloca i1, i1 0
-  %nop4353 = alloca i1, i1 0
-  %nop4354 = alloca i1, i1 0
-  %nop4355 = alloca i1, i1 0
-  %nop4356 = alloca i1, i1 0
-  %nop4357 = alloca i1, i1 0
-  %nop4358 = alloca i1, i1 0
-  %nop4359 = alloca i1, i1 0
-  %nop4360 = alloca i1, i1 0
-  %nop4361 = alloca i1, i1 0
-  %nop4362 = alloca i1, i1 0
-  %nop4363 = alloca i1, i1 0
-  %nop4364 = alloca i1, i1 0
-  %nop4365 = alloca i1, i1 0
-  %nop4366 = alloca i1, i1 0
-  %nop4367 = alloca i1, i1 0
-  %nop4368 = alloca i1, i1 0
-  %nop4369 = alloca i1, i1 0
-  %nop4370 = alloca i1, i1 0
-  %nop4371 = alloca i1, i1 0
-  %nop4372 = alloca i1, i1 0
-  %nop4373 = alloca i1, i1 0
-  %nop4374 = alloca i1, i1 0
-  %nop4375 = alloca i1, i1 0
-  %nop4376 = alloca i1, i1 0
-  %nop4377 = alloca i1, i1 0
-  %nop4378 = alloca i1, i1 0
-  %nop4379 = alloca i1, i1 0
-  %nop4380 = alloca i1, i1 0
-  %nop4381 = alloca i1, i1 0
-  %nop4382 = alloca i1, i1 0
-  %nop4383 = alloca i1, i1 0
-  %nop4384 = alloca i1, i1 0
-  %nop4385 = alloca i1, i1 0
-  %nop4386 = alloca i1, i1 0
-  %nop4387 = alloca i1, i1 0
-  %nop4388 = alloca i1, i1 0
-  %nop4389 = alloca i1, i1 0
-  %nop4390 = alloca i1, i1 0
-  %nop4391 = alloca i1, i1 0
-  %nop4392 = alloca i1, i1 0
-  %nop4393 = alloca i1, i1 0
-  %nop4394 = alloca i1, i1 0
-  %nop4395 = alloca i1, i1 0
-  %nop4396 = alloca i1, i1 0
-  %nop4397 = alloca i1, i1 0
-  %nop4398 = alloca i1, i1 0
-  %nop4399 = alloca i1, i1 0
-  %nop4400 = alloca i1, i1 0
-  %nop4401 = alloca i1, i1 0
-  %nop4402 = alloca i1, i1 0
-  %nop4403 = alloca i1, i1 0
-  %nop4404 = alloca i1, i1 0
-  %nop4405 = alloca i1, i1 0
-  %nop4406 = alloca i1, i1 0
-  %nop4407 = alloca i1, i1 0
-  %nop4408 = alloca i1, i1 0
-  %nop4409 = alloca i1, i1 0
-  %nop4410 = alloca i1, i1 0
-  %nop4411 = alloca i1, i1 0
-  %nop4412 = alloca i1, i1 0
-  %nop4413 = alloca i1, i1 0
-  %nop4414 = alloca i1, i1 0
-  %nop4415 = alloca i1, i1 0
-  %nop4416 = alloca i1, i1 0
-  %nop4417 = alloca i1, i1 0
-  %nop4418 = alloca i1, i1 0
-  %nop4419 = alloca i1, i1 0
-  %nop4420 = alloca i1, i1 0
-  %nop4421 = alloca i1, i1 0
-  %nop4422 = alloca i1, i1 0
-  %nop4423 = alloca i1, i1 0
-  %nop4424 = alloca i1, i1 0
-  %nop4425 = alloca i1, i1 0
-  %nop4426 = alloca i1, i1 0
-  %nop4427 = alloca i1, i1 0
-  %nop4428 = alloca i1, i1 0
-  %nop4429 = alloca i1, i1 0
-  %nop4430 = alloca i1, i1 0
-  %nop4431 = alloca i1, i1 0
-  %nop4432 = alloca i1, i1 0
-  %nop4433 = alloca i1, i1 0
-  %nop4434 = alloca i1, i1 0
-  %nop4435 = alloca i1, i1 0
-  %nop4436 = alloca i1, i1 0
-  %nop4437 = alloca i1, i1 0
-  %nop4438 = alloca i1, i1 0
-  %nop4439 = alloca i1, i1 0
-  %nop4440 = alloca i1, i1 0
-  %nop4441 = alloca i1, i1 0
-  %nop4442 = alloca i1, i1 0
-  %nop4443 = alloca i1, i1 0
-  %nop4444 = alloca i1, i1 0
-  %nop4445 = alloca i1, i1 0
-  %nop4446 = alloca i1, i1 0
-  %nop4447 = alloca i1, i1 0
-  %nop4448 = alloca i1, i1 0
-  %nop4449 = alloca i1, i1 0
-  %nop4450 = alloca i1, i1 0
-  %nop4451 = alloca i1, i1 0
-  %nop4452 = alloca i1, i1 0
-  %nop4453 = alloca i1, i1 0
-  %nop4454 = alloca i1, i1 0
-  %nop4455 = alloca i1, i1 0
-  %nop4456 = alloca i1, i1 0
-  %nop4457 = alloca i1, i1 0
-  %nop4458 = alloca i1, i1 0
-  %nop4459 = alloca i1, i1 0
-  %nop4460 = alloca i1, i1 0
-  %nop4461 = alloca i1, i1 0
-  %nop4462 = alloca i1, i1 0
-  %nop4463 = alloca i1, i1 0
-  %nop4464 = alloca i1, i1 0
-  %nop4465 = alloca i1, i1 0
-  %nop4466 = alloca i1, i1 0
-  %nop4467 = alloca i1, i1 0
-  %nop4468 = alloca i1, i1 0
-  %nop4469 = alloca i1, i1 0
-  %nop4470 = alloca i1, i1 0
-  %nop4471 = alloca i1, i1 0
-  %nop4472 = alloca i1, i1 0
-  %nop4473 = alloca i1, i1 0
-  %nop4474 = alloca i1, i1 0
-  %nop4475 = alloca i1, i1 0
-  %nop4476 = alloca i1, i1 0
-  %nop4477 = alloca i1, i1 0
-  %nop4478 = alloca i1, i1 0
-  %nop4479 = alloca i1, i1 0
-  %nop4480 = alloca i1, i1 0
-  %nop4481 = alloca i1, i1 0
-  %nop4482 = alloca i1, i1 0
-  %nop4483 = alloca i1, i1 0
-  %nop4484 = alloca i1, i1 0
-  %nop4485 = alloca i1, i1 0
-  %nop4486 = alloca i1, i1 0
-  %nop4487 = alloca i1, i1 0
-  %nop4488 = alloca i1, i1 0
-  %nop4489 = alloca i1, i1 0
-  %nop4490 = alloca i1, i1 0
-  %nop4491 = alloca i1, i1 0
-  %nop4492 = alloca i1, i1 0
-  %nop4493 = alloca i1, i1 0
-  %nop4494 = alloca i1, i1 0
-  %nop4495 = alloca i1, i1 0
-  %nop4496 = alloca i1, i1 0
-  %nop4497 = alloca i1, i1 0
-  %nop4498 = alloca i1, i1 0
-  %nop4499 = alloca i1, i1 0
-  %nop4500 = alloca i1, i1 0
-  %nop4501 = alloca i1, i1 0
-  %nop4502 = alloca i1, i1 0
-  %nop4503 = alloca i1, i1 0
-  %nop4504 = alloca i1, i1 0
-  %nop4505 = alloca i1, i1 0
-  %nop4506 = alloca i1, i1 0
-  %nop4507 = alloca i1, i1 0
-  %nop4508 = alloca i1, i1 0
-  %nop4509 = alloca i1, i1 0
-  %nop4510 = alloca i1, i1 0
-  %nop4511 = alloca i1, i1 0
-  %nop4512 = alloca i1, i1 0
-  %nop4513 = alloca i1, i1 0
-  %nop4514 = alloca i1, i1 0
-  %nop4515 = alloca i1, i1 0
-  %nop4516 = alloca i1, i1 0
-  %nop4517 = alloca i1, i1 0
-  %nop4518 = alloca i1, i1 0
-  %nop4519 = alloca i1, i1 0
-  %nop4520 = alloca i1, i1 0
-  %nop4521 = alloca i1, i1 0
-  %nop4522 = alloca i1, i1 0
-  %nop4523 = alloca i1, i1 0
-  %nop4524 = alloca i1, i1 0
-  %nop4525 = alloca i1, i1 0
-  %nop4526 = alloca i1, i1 0
-  %nop4527 = alloca i1, i1 0
-  %nop4528 = alloca i1, i1 0
-  %nop4529 = alloca i1, i1 0
-  %nop4530 = alloca i1, i1 0
-  %nop4531 = alloca i1, i1 0
-  %nop4532 = alloca i1, i1 0
-  %nop4533 = alloca i1, i1 0
-  %nop4534 = alloca i1, i1 0
-  %nop4535 = alloca i1, i1 0
-  %nop4536 = alloca i1, i1 0
-  %nop4537 = alloca i1, i1 0
-  %nop4538 = alloca i1, i1 0
-  %nop4539 = alloca i1, i1 0
-  %nop4540 = alloca i1, i1 0
-  %nop4541 = alloca i1, i1 0
-  %nop4542 = alloca i1, i1 0
-  %nop4543 = alloca i1, i1 0
-  %nop4544 = alloca i1, i1 0
-  %nop4545 = alloca i1, i1 0
-  %nop4546 = alloca i1, i1 0
-  %nop4547 = alloca i1, i1 0
-  %nop4548 = alloca i1, i1 0
-  %nop4549 = alloca i1, i1 0
-  %nop4550 = alloca i1, i1 0
-  %nop4551 = alloca i1, i1 0
-  %nop4552 = alloca i1, i1 0
-  %nop4553 = alloca i1, i1 0
-  %nop4554 = alloca i1, i1 0
-  %nop4555 = alloca i1, i1 0
-  %nop4556 = alloca i1, i1 0
-  %nop4557 = alloca i1, i1 0
-  %nop4558 = alloca i1, i1 0
-  %nop4559 = alloca i1, i1 0
-  %nop4560 = alloca i1, i1 0
-  %nop4561 = alloca i1, i1 0
-  %nop4562 = alloca i1, i1 0
-  %nop4563 = alloca i1, i1 0
-  %nop4564 = alloca i1, i1 0
-  %nop4565 = alloca i1, i1 0
-  %nop4566 = alloca i1, i1 0
-  %nop4567 = alloca i1, i1 0
-  %nop4568 = alloca i1, i1 0
-  %nop4569 = alloca i1, i1 0
-  %nop4570 = alloca i1, i1 0
-  %nop4571 = alloca i1, i1 0
-  %nop4572 = alloca i1, i1 0
-  %nop4573 = alloca i1, i1 0
-  %nop4574 = alloca i1, i1 0
-  %nop4575 = alloca i1, i1 0
-  %nop4576 = alloca i1, i1 0
-  %nop4577 = alloca i1, i1 0
-  %nop4578 = alloca i1, i1 0
-  %nop4579 = alloca i1, i1 0
-  %nop4580 = alloca i1, i1 0
-  %nop4581 = alloca i1, i1 0
-  %nop4582 = alloca i1, i1 0
-  %nop4583 = alloca i1, i1 0
-  %nop4584 = alloca i1, i1 0
-  %nop4585 = alloca i1, i1 0
-  %nop4586 = alloca i1, i1 0
-  %nop4587 = alloca i1, i1 0
-  %nop4588 = alloca i1, i1 0
-  %nop4589 = alloca i1, i1 0
-  %nop4590 = alloca i1, i1 0
-  %nop4591 = alloca i1, i1 0
-  %nop4592 = alloca i1, i1 0
-  %nop4593 = alloca i1, i1 0
-  %nop4594 = alloca i1, i1 0
-  %nop4595 = alloca i1, i1 0
-  %nop4596 = alloca i1, i1 0
-  %nop4597 = alloca i1, i1 0
-  %nop4598 = alloca i1, i1 0
-  %nop4599 = alloca i1, i1 0
-  %nop4600 = alloca i1, i1 0
-  %nop4601 = alloca i1, i1 0
-  %nop4602 = alloca i1, i1 0
-  %nop4603 = alloca i1, i1 0
-  %nop4604 = alloca i1, i1 0
-  %nop4605 = alloca i1, i1 0
-  %nop4606 = alloca i1, i1 0
-  %nop4607 = alloca i1, i1 0
-  %nop4608 = alloca i1, i1 0
-  %nop4609 = alloca i1, i1 0
-  %nop4610 = alloca i1, i1 0
-  %nop4611 = alloca i1, i1 0
-  %nop4612 = alloca i1, i1 0
-  %nop4613 = alloca i1, i1 0
-  %nop4614 = alloca i1, i1 0
-  %nop4615 = alloca i1, i1 0
-  %nop4616 = alloca i1, i1 0
-  %nop4617 = alloca i1, i1 0
-  %nop4618 = alloca i1, i1 0
-  %nop4619 = alloca i1, i1 0
-  %nop4620 = alloca i1, i1 0
-  %nop4621 = alloca i1, i1 0
-  %nop4622 = alloca i1, i1 0
-  %nop4623 = alloca i1, i1 0
-  %nop4624 = alloca i1, i1 0
-  %nop4625 = alloca i1, i1 0
-  %nop4626 = alloca i1, i1 0
-  %nop4627 = alloca i1, i1 0
-  %nop4628 = alloca i1, i1 0
-  %nop4629 = alloca i1, i1 0
-  %nop4630 = alloca i1, i1 0
-  %nop4631 = alloca i1, i1 0
-  %nop4632 = alloca i1, i1 0
-  %nop4633 = alloca i1, i1 0
-  %nop4634 = alloca i1, i1 0
-  %nop4635 = alloca i1, i1 0
-  %nop4636 = alloca i1, i1 0
-  %nop4637 = alloca i1, i1 0
-  %nop4638 = alloca i1, i1 0
-  %nop4639 = alloca i1, i1 0
-  %nop4640 = alloca i1, i1 0
-  %nop4641 = alloca i1, i1 0
-  %nop4642 = alloca i1, i1 0
-  %nop4643 = alloca i1, i1 0
-  %nop4644 = alloca i1, i1 0
-  %nop4645 = alloca i1, i1 0
-  %nop4646 = alloca i1, i1 0
-  %nop4647 = alloca i1, i1 0
-  %nop4648 = alloca i1, i1 0
-  %nop4649 = alloca i1, i1 0
-  %nop4650 = alloca i1, i1 0
-  %nop4651 = alloca i1, i1 0
-  %nop4652 = alloca i1, i1 0
-  %nop4653 = alloca i1, i1 0
-  %nop4654 = alloca i1, i1 0
-  %nop4655 = alloca i1, i1 0
-  %nop4656 = alloca i1, i1 0
-  %nop4657 = alloca i1, i1 0
-  %nop4658 = alloca i1, i1 0
-  %nop4659 = alloca i1, i1 0
-  %nop4660 = alloca i1, i1 0
-  %nop4661 = alloca i1, i1 0
-  %nop4662 = alloca i1, i1 0
-  %nop4663 = alloca i1, i1 0
-  %nop4664 = alloca i1, i1 0
-  %nop4665 = alloca i1, i1 0
-  %nop4666 = alloca i1, i1 0
-  %nop4667 = alloca i1, i1 0
-  %nop4668 = alloca i1, i1 0
-  %nop4669 = alloca i1, i1 0
-  %nop4670 = alloca i1, i1 0
-  %nop4671 = alloca i1, i1 0
-  %nop4672 = alloca i1, i1 0
-  %nop4673 = alloca i1, i1 0
-  %nop4674 = alloca i1, i1 0
-  %nop4675 = alloca i1, i1 0
-  %nop4676 = alloca i1, i1 0
-  %nop4677 = alloca i1, i1 0
-  %nop4678 = alloca i1, i1 0
-  %nop4679 = alloca i1, i1 0
-  %nop4680 = alloca i1, i1 0
-  %nop4681 = alloca i1, i1 0
-  %nop4682 = alloca i1, i1 0
-  %nop4683 = alloca i1, i1 0
-  %nop4684 = alloca i1, i1 0
-  %nop4685 = alloca i1, i1 0
-  %nop4686 = alloca i1, i1 0
-  %nop4687 = alloca i1, i1 0
-  %nop4688 = alloca i1, i1 0
-  %nop4689 = alloca i1, i1 0
-  %nop4690 = alloca i1, i1 0
-  %nop4691 = alloca i1, i1 0
-  %nop4692 = alloca i1, i1 0
-  %nop4693 = alloca i1, i1 0
-  %nop4694 = alloca i1, i1 0
-  %nop4695 = alloca i1, i1 0
-  %nop4696 = alloca i1, i1 0
-  %nop4697 = alloca i1, i1 0
-  %nop4698 = alloca i1, i1 0
-  %nop4699 = alloca i1, i1 0
-  %nop4700 = alloca i1, i1 0
-  %nop4701 = alloca i1, i1 0
-  %nop4702 = alloca i1, i1 0
-  %nop4703 = alloca i1, i1 0
-  %nop4704 = alloca i1, i1 0
-  %nop4705 = alloca i1, i1 0
-  %nop4706 = alloca i1, i1 0
-  %nop4707 = alloca i1, i1 0
-  %nop4708 = alloca i1, i1 0
-  %nop4709 = alloca i1, i1 0
-  %nop4710 = alloca i1, i1 0
-  %nop4711 = alloca i1, i1 0
-  %nop4712 = alloca i1, i1 0
-  %nop4713 = alloca i1, i1 0
-  %nop4714 = alloca i1, i1 0
-  %nop4715 = alloca i1, i1 0
-  %nop4716 = alloca i1, i1 0
-  %nop4717 = alloca i1, i1 0
-  %nop4718 = alloca i1, i1 0
-  %nop4719 = alloca i1, i1 0
-  %nop4720 = alloca i1, i1 0
-  %nop4721 = alloca i1, i1 0
-  %nop4722 = alloca i1, i1 0
-  %nop4723 = alloca i1, i1 0
-  %nop4724 = alloca i1, i1 0
-  %nop4725 = alloca i1, i1 0
-  %nop4726 = alloca i1, i1 0
-  %nop4727 = alloca i1, i1 0
-  %nop4728 = alloca i1, i1 0
-  %nop4729 = alloca i1, i1 0
-  %nop4730 = alloca i1, i1 0
-  %nop4731 = alloca i1, i1 0
-  %nop4732 = alloca i1, i1 0
-  %nop4733 = alloca i1, i1 0
-  %nop4734 = alloca i1, i1 0
-  %nop4735 = alloca i1, i1 0
-  %nop4736 = alloca i1, i1 0
-  %nop4737 = alloca i1, i1 0
-  %nop4738 = alloca i1, i1 0
-  %nop4739 = alloca i1, i1 0
-  %nop4740 = alloca i1, i1 0
-  %nop4741 = alloca i1, i1 0
-  %nop4742 = alloca i1, i1 0
-  %nop4743 = alloca i1, i1 0
-  %nop4744 = alloca i1, i1 0
-  %nop4745 = alloca i1, i1 0
-  %nop4746 = alloca i1, i1 0
-  %nop4747 = alloca i1, i1 0
-  %nop4748 = alloca i1, i1 0
-  %nop4749 = alloca i1, i1 0
-  %nop4750 = alloca i1, i1 0
-  %nop4751 = alloca i1, i1 0
-  %nop4752 = alloca i1, i1 0
-  %nop4753 = alloca i1, i1 0
-  %nop4754 = alloca i1, i1 0
-  %nop4755 = alloca i1, i1 0
-  %nop4756 = alloca i1, i1 0
-  %nop4757 = alloca i1, i1 0
-  %nop4758 = alloca i1, i1 0
-  %nop4759 = alloca i1, i1 0
-  %nop4760 = alloca i1, i1 0
-  %nop4761 = alloca i1, i1 0
-  %nop4762 = alloca i1, i1 0
-  %nop4763 = alloca i1, i1 0
-  %nop4764 = alloca i1, i1 0
-  %nop4765 = alloca i1, i1 0
-  %nop4766 = alloca i1, i1 0
-  %nop4767 = alloca i1, i1 0
-  %nop4768 = alloca i1, i1 0
-  %nop4769 = alloca i1, i1 0
-  %nop4770 = alloca i1, i1 0
-  %nop4771 = alloca i1, i1 0
-  %nop4772 = alloca i1, i1 0
-  %nop4773 = alloca i1, i1 0
-  %nop4774 = alloca i1, i1 0
-  %nop4775 = alloca i1, i1 0
-  %nop4776 = alloca i1, i1 0
-  %nop4777 = alloca i1, i1 0
-  %nop4778 = alloca i1, i1 0
-  %nop4779 = alloca i1, i1 0
-  %nop4780 = alloca i1, i1 0
-  %nop4781 = alloca i1, i1 0
-  %nop4782 = alloca i1, i1 0
-  %nop4783 = alloca i1, i1 0
-  %nop4784 = alloca i1, i1 0
-  %nop4785 = alloca i1, i1 0
-  %nop4786 = alloca i1, i1 0
-  %nop4787 = alloca i1, i1 0
-  %nop4788 = alloca i1, i1 0
-  %nop4789 = alloca i1, i1 0
-  %nop4790 = alloca i1, i1 0
-  %nop4791 = alloca i1, i1 0
-  %nop4792 = alloca i1, i1 0
-  %nop4793 = alloca i1, i1 0
-  %nop4794 = alloca i1, i1 0
-  %nop4795 = alloca i1, i1 0
-  %nop4796 = alloca i1, i1 0
-  %nop4797 = alloca i1, i1 0
-  %nop4798 = alloca i1, i1 0
-  %nop4799 = alloca i1, i1 0
-  %nop4800 = alloca i1, i1 0
-  %nop4801 = alloca i1, i1 0
-  %nop4802 = alloca i1, i1 0
-  %nop4803 = alloca i1, i1 0
-  %nop4804 = alloca i1, i1 0
-  %nop4805 = alloca i1, i1 0
-  %nop4806 = alloca i1, i1 0
-  %nop4807 = alloca i1, i1 0
-  %nop4808 = alloca i1, i1 0
-  %nop4809 = alloca i1, i1 0
-  %nop4810 = alloca i1, i1 0
-  %nop4811 = alloca i1, i1 0
-  %nop4812 = alloca i1, i1 0
-  %nop4813 = alloca i1, i1 0
-  %nop4814 = alloca i1, i1 0
-  %nop4815 = alloca i1, i1 0
-  %nop4816 = alloca i1, i1 0
-  %nop4817 = alloca i1, i1 0
-  %nop4818 = alloca i1, i1 0
-  %nop4819 = alloca i1, i1 0
-  %nop4820 = alloca i1, i1 0
-  %nop4821 = alloca i1, i1 0
-  %nop4822 = alloca i1, i1 0
-  %nop4823 = alloca i1, i1 0
-  %nop4824 = alloca i1, i1 0
-  %nop4825 = alloca i1, i1 0
-  %nop4826 = alloca i1, i1 0
-  %nop4827 = alloca i1, i1 0
-  %nop4828 = alloca i1, i1 0
-  %nop4829 = alloca i1, i1 0
-  %nop4830 = alloca i1, i1 0
-  %nop4831 = alloca i1, i1 0
-  %nop4832 = alloca i1, i1 0
-  %nop4833 = alloca i1, i1 0
-  %nop4834 = alloca i1, i1 0
-  %nop4835 = alloca i1, i1 0
-  %nop4836 = alloca i1, i1 0
-  %nop4837 = alloca i1, i1 0
-  %nop4838 = alloca i1, i1 0
-  %nop4839 = alloca i1, i1 0
-  %nop4840 = alloca i1, i1 0
-  %nop4841 = alloca i1, i1 0
-  %nop4842 = alloca i1, i1 0
-  %nop4843 = alloca i1, i1 0
-  %nop4844 = alloca i1, i1 0
-  %nop4845 = alloca i1, i1 0
-  %nop4846 = alloca i1, i1 0
-  %nop4847 = alloca i1, i1 0
-  %nop4848 = alloca i1, i1 0
-  %nop4849 = alloca i1, i1 0
-  %nop4850 = alloca i1, i1 0
-  %nop4851 = alloca i1, i1 0
-  %nop4852 = alloca i1, i1 0
-  %nop4853 = alloca i1, i1 0
-  %nop4854 = alloca i1, i1 0
-  %nop4855 = alloca i1, i1 0
-  %nop4856 = alloca i1, i1 0
-  %nop4857 = alloca i1, i1 0
-  %nop4858 = alloca i1, i1 0
-  %nop4859 = alloca i1, i1 0
-  %nop4860 = alloca i1, i1 0
-  %nop4861 = alloca i1, i1 0
-  %nop4862 = alloca i1, i1 0
-  %nop4863 = alloca i1, i1 0
-  %nop4864 = alloca i1, i1 0
-  %nop4865 = alloca i1, i1 0
-  %nop4866 = alloca i1, i1 0
-  %nop4867 = alloca i1, i1 0
-  %nop4868 = alloca i1, i1 0
-  %nop4869 = alloca i1, i1 0
-  %nop4870 = alloca i1, i1 0
-  %nop4871 = alloca i1, i1 0
-  %nop4872 = alloca i1, i1 0
-  %nop4873 = alloca i1, i1 0
-  %nop4874 = alloca i1, i1 0
-  %nop4875 = alloca i1, i1 0
-  %nop4876 = alloca i1, i1 0
-  %nop4877 = alloca i1, i1 0
-  %nop4878 = alloca i1, i1 0
-  %nop4879 = alloca i1, i1 0
-  %nop4880 = alloca i1, i1 0
-  %nop4881 = alloca i1, i1 0
-  %nop4882 = alloca i1, i1 0
-  %nop4883 = alloca i1, i1 0
-  %nop4884 = alloca i1, i1 0
-  %nop4885 = alloca i1, i1 0
-  %nop4886 = alloca i1, i1 0
-  %nop4887 = alloca i1, i1 0
-  %nop4888 = alloca i1, i1 0
-  %nop4889 = alloca i1, i1 0
-  %nop4890 = alloca i1, i1 0
-  %nop4891 = alloca i1, i1 0
-  %nop4892 = alloca i1, i1 0
-  %nop4893 = alloca i1, i1 0
-  %nop4894 = alloca i1, i1 0
-  %nop4895 = alloca i1, i1 0
-  %nop4896 = alloca i1, i1 0
-  %nop4897 = alloca i1, i1 0
-  %nop4898 = alloca i1, i1 0
-  %nop4899 = alloca i1, i1 0
-  %nop4900 = alloca i1, i1 0
-  %nop4901 = alloca i1, i1 0
-  %nop4902 = alloca i1, i1 0
-  %nop4903 = alloca i1, i1 0
-  %nop4904 = alloca i1, i1 0
-  %nop4905 = alloca i1, i1 0
-  %nop4906 = alloca i1, i1 0
-  %nop4907 = alloca i1, i1 0
-  %nop4908 = alloca i1, i1 0
-  %nop4909 = alloca i1, i1 0
-  %nop4910 = alloca i1, i1 0
-  %nop4911 = alloca i1, i1 0
-  %nop4912 = alloca i1, i1 0
-  %nop4913 = alloca i1, i1 0
-  %nop4914 = alloca i1, i1 0
-  %nop4915 = alloca i1, i1 0
-  %nop4916 = alloca i1, i1 0
-  %nop4917 = alloca i1, i1 0
-  %nop4918 = alloca i1, i1 0
-  %nop4919 = alloca i1, i1 0
-  %nop4920 = alloca i1, i1 0
-  %nop4921 = alloca i1, i1 0
-  %nop4922 = alloca i1, i1 0
-  %nop4923 = alloca i1, i1 0
-  %nop4924 = alloca i1, i1 0
-  %nop4925 = alloca i1, i1 0
-  %nop4926 = alloca i1, i1 0
-  %nop4927 = alloca i1, i1 0
-  %nop4928 = alloca i1, i1 0
-  %nop4929 = alloca i1, i1 0
-  %nop4930 = alloca i1, i1 0
-  %nop4931 = alloca i1, i1 0
-  %nop4932 = alloca i1, i1 0
-  %nop4933 = alloca i1, i1 0
-  %nop4934 = alloca i1, i1 0
-  %nop4935 = alloca i1, i1 0
-  %nop4936 = alloca i1, i1 0
-  %nop4937 = alloca i1, i1 0
-  %nop4938 = alloca i1, i1 0
-  %nop4939 = alloca i1, i1 0
-  %nop4940 = alloca i1, i1 0
-  %nop4941 = alloca i1, i1 0
-  %nop4942 = alloca i1, i1 0
-  %nop4943 = alloca i1, i1 0
-  %nop4944 = alloca i1, i1 0
-  %nop4945 = alloca i1, i1 0
-  %nop4946 = alloca i1, i1 0
-  %nop4947 = alloca i1, i1 0
-  %nop4948 = alloca i1, i1 0
-  %nop4949 = alloca i1, i1 0
-  %nop4950 = alloca i1, i1 0
-  %nop4951 = alloca i1, i1 0
-  %nop4952 = alloca i1, i1 0
-  %nop4953 = alloca i1, i1 0
-  %nop4954 = alloca i1, i1 0
-  %nop4955 = alloca i1, i1 0
-  %nop4956 = alloca i1, i1 0
-  %nop4957 = alloca i1, i1 0
-  %nop4958 = alloca i1, i1 0
-  %nop4959 = alloca i1, i1 0
-  %nop4960 = alloca i1, i1 0
-  %nop4961 = alloca i1, i1 0
-  %nop4962 = alloca i1, i1 0
-  %nop4963 = alloca i1, i1 0
-  %nop4964 = alloca i1, i1 0
-  %nop4965 = alloca i1, i1 0
-  %nop4966 = alloca i1, i1 0
-  %nop4967 = alloca i1, i1 0
-  %nop4968 = alloca i1, i1 0
-  %nop4969 = alloca i1, i1 0
-  %nop4970 = alloca i1, i1 0
-  %nop4971 = alloca i1, i1 0
-  %nop4972 = alloca i1, i1 0
-  %nop4973 = alloca i1, i1 0
-  %nop4974 = alloca i1, i1 0
-  %nop4975 = alloca i1, i1 0
-  %nop4976 = alloca i1, i1 0
-  %nop4977 = alloca i1, i1 0
-  %nop4978 = alloca i1, i1 0
-  %nop4979 = alloca i1, i1 0
-  %nop4980 = alloca i1, i1 0
-  %nop4981 = alloca i1, i1 0
-  %nop4982 = alloca i1, i1 0
-  %nop4983 = alloca i1, i1 0
-  %nop4984 = alloca i1, i1 0
-  %nop4985 = alloca i1, i1 0
-  %nop4986 = alloca i1, i1 0
-  %nop4987 = alloca i1, i1 0
-  %nop4988 = alloca i1, i1 0
-  %nop4989 = alloca i1, i1 0
-  %nop4990 = alloca i1, i1 0
-  %nop4991 = alloca i1, i1 0
-  %nop4992 = alloca i1, i1 0
-  %nop4993 = alloca i1, i1 0
-  %nop4994 = alloca i1, i1 0
-  %nop4995 = alloca i1, i1 0
-  %nop4996 = alloca i1, i1 0
-  %nop4997 = alloca i1, i1 0
-  %nop4998 = alloca i1, i1 0
-  %nop4999 = alloca i1, i1 0
-  %nop5000 = alloca i1, i1 0
-  %nop5001 = alloca i1, i1 0
-  %nop5002 = alloca i1, i1 0
-  %nop5003 = alloca i1, i1 0
-  %nop5004 = alloca i1, i1 0
-  %nop5005 = alloca i1, i1 0
-  %nop5006 = alloca i1, i1 0
-  %nop5007 = alloca i1, i1 0
-  %nop5008 = alloca i1, i1 0
-  %nop5009 = alloca i1, i1 0
-  %nop5010 = alloca i1, i1 0
-  %nop5011 = alloca i1, i1 0
-  %nop5012 = alloca i1, i1 0
-  %nop5013 = alloca i1, i1 0
-  %nop5014 = alloca i1, i1 0
-  %nop5015 = alloca i1, i1 0
-  %nop5016 = alloca i1, i1 0
-  %nop5017 = alloca i1, i1 0
-  %nop5018 = alloca i1, i1 0
-  %nop5019 = alloca i1, i1 0
-  %nop5020 = alloca i1, i1 0
-  %nop5021 = alloca i1, i1 0
-  %nop5022 = alloca i1, i1 0
-  %nop5023 = alloca i1, i1 0
-  %nop5024 = alloca i1, i1 0
-  %nop5025 = alloca i1, i1 0
-  %nop5026 = alloca i1, i1 0
-  %nop5027 = alloca i1, i1 0
-  %nop5028 = alloca i1, i1 0
-  %nop5029 = alloca i1, i1 0
-  %nop5030 = alloca i1, i1 0
-  %nop5031 = alloca i1, i1 0
-  %nop5032 = alloca i1, i1 0
-  %nop5033 = alloca i1, i1 0
-  %nop5034 = alloca i1, i1 0
-  %nop5035 = alloca i1, i1 0
-  %nop5036 = alloca i1, i1 0
-  %nop5037 = alloca i1, i1 0
-  %nop5038 = alloca i1, i1 0
-  %nop5039 = alloca i1, i1 0
-  %nop5040 = alloca i1, i1 0
-  %nop5041 = alloca i1, i1 0
-  %nop5042 = alloca i1, i1 0
-  %nop5043 = alloca i1, i1 0
-  %nop5044 = alloca i1, i1 0
-  %nop5045 = alloca i1, i1 0
-  %nop5046 = alloca i1, i1 0
-  %nop5047 = alloca i1, i1 0
-  %nop5048 = alloca i1, i1 0
-  %nop5049 = alloca i1, i1 0
-  %nop5050 = alloca i1, i1 0
-  %nop5051 = alloca i1, i1 0
-  %nop5052 = alloca i1, i1 0
-  %nop5053 = alloca i1, i1 0
-  %nop5054 = alloca i1, i1 0
-  %nop5055 = alloca i1, i1 0
-  %nop5056 = alloca i1, i1 0
-  %nop5057 = alloca i1, i1 0
-  %nop5058 = alloca i1, i1 0
-  %nop5059 = alloca i1, i1 0
-  %nop5060 = alloca i1, i1 0
-  %nop5061 = alloca i1, i1 0
-  %nop5062 = alloca i1, i1 0
-  %nop5063 = alloca i1, i1 0
-  %nop5064 = alloca i1, i1 0
-  %nop5065 = alloca i1, i1 0
-  %nop5066 = alloca i1, i1 0
-  %nop5067 = alloca i1, i1 0
-  %nop5068 = alloca i1, i1 0
-  %nop5069 = alloca i1, i1 0
-  %nop5070 = alloca i1, i1 0
-  %nop5071 = alloca i1, i1 0
-  %nop5072 = alloca i1, i1 0
-  %nop5073 = alloca i1, i1 0
-  %nop5074 = alloca i1, i1 0
-  %nop5075 = alloca i1, i1 0
-  %nop5076 = alloca i1, i1 0
-  %nop5077 = alloca i1, i1 0
-  %nop5078 = alloca i1, i1 0
-  %nop5079 = alloca i1, i1 0
-  %nop5080 = alloca i1, i1 0
-  %nop5081 = alloca i1, i1 0
-  %nop5082 = alloca i1, i1 0
-  %nop5083 = alloca i1, i1 0
-  %nop5084 = alloca i1, i1 0
-  %nop5085 = alloca i1, i1 0
-  %nop5086 = alloca i1, i1 0
-  %nop5087 = alloca i1, i1 0
-  %nop5088 = alloca i1, i1 0
-  %nop5089 = alloca i1, i1 0
-  %nop5090 = alloca i1, i1 0
-  %nop5091 = alloca i1, i1 0
-  %nop5092 = alloca i1, i1 0
-  %nop5093 = alloca i1, i1 0
-  %nop5094 = alloca i1, i1 0
-  %nop5095 = alloca i1, i1 0
-  %nop5096 = alloca i1, i1 0
-  %nop5097 = alloca i1, i1 0
-  %nop5098 = alloca i1, i1 0
-  %nop5099 = alloca i1, i1 0
-  %nop5100 = alloca i1, i1 0
-  %nop5101 = alloca i1, i1 0
-  %nop5102 = alloca i1, i1 0
-  %nop5103 = alloca i1, i1 0
-  %nop5104 = alloca i1, i1 0
-  %nop5105 = alloca i1, i1 0
-  %nop5106 = alloca i1, i1 0
-  %nop5107 = alloca i1, i1 0
-  %nop5108 = alloca i1, i1 0
-  %nop5109 = alloca i1, i1 0
-  %nop5110 = alloca i1, i1 0
-  %nop5111 = alloca i1, i1 0
-  %nop5112 = alloca i1, i1 0
-  %nop5113 = alloca i1, i1 0
-  %nop5114 = alloca i1, i1 0
-  %nop5115 = alloca i1, i1 0
-  %nop5116 = alloca i1, i1 0
-  %nop5117 = alloca i1, i1 0
-  %nop5118 = alloca i1, i1 0
-  %nop5119 = alloca i1, i1 0
-  %nop5120 = alloca i1, i1 0
-  %nop5121 = alloca i1, i1 0
-  %nop5122 = alloca i1, i1 0
-  %nop5123 = alloca i1, i1 0
-  %nop5124 = alloca i1, i1 0
-  %nop5125 = alloca i1, i1 0
-  %nop5126 = alloca i1, i1 0
-  %nop5127 = alloca i1, i1 0
-  %nop5128 = alloca i1, i1 0
-  %nop5129 = alloca i1, i1 0
-  %nop5130 = alloca i1, i1 0
-  %nop5131 = alloca i1, i1 0
-  %nop5132 = alloca i1, i1 0
-  %nop5133 = alloca i1, i1 0
-  %nop5134 = alloca i1, i1 0
-  %nop5135 = alloca i1, i1 0
-  %nop5136 = alloca i1, i1 0
-  %nop5137 = alloca i1, i1 0
-  %nop5138 = alloca i1, i1 0
-  %nop5139 = alloca i1, i1 0
-  %nop5140 = alloca i1, i1 0
-  %nop5141 = alloca i1, i1 0
-  %nop5142 = alloca i1, i1 0
-  %nop5143 = alloca i1, i1 0
-  %nop5144 = alloca i1, i1 0
-  %nop5145 = alloca i1, i1 0
-  %nop5146 = alloca i1, i1 0
-  %nop5147 = alloca i1, i1 0
-  %nop5148 = alloca i1, i1 0
-  %nop5149 = alloca i1, i1 0
-  %nop5150 = alloca i1, i1 0
-  %nop5151 = alloca i1, i1 0
-  %nop5152 = alloca i1, i1 0
-  %nop5153 = alloca i1, i1 0
-  %nop5154 = alloca i1, i1 0
-  %nop5155 = alloca i1, i1 0
-  %nop5156 = alloca i1, i1 0
-  %nop5157 = alloca i1, i1 0
-  %nop5158 = alloca i1, i1 0
-  %nop5159 = alloca i1, i1 0
-  %nop5160 = alloca i1, i1 0
-  %nop5161 = alloca i1, i1 0
-  %nop5162 = alloca i1, i1 0
-  %nop5163 = alloca i1, i1 0
-  %nop5164 = alloca i1, i1 0
-  %nop5165 = alloca i1, i1 0
-  %nop5166 = alloca i1, i1 0
-  %nop5167 = alloca i1, i1 0
-  %nop5168 = alloca i1, i1 0
-  %nop5169 = alloca i1, i1 0
-  %nop5170 = alloca i1, i1 0
-  %nop5171 = alloca i1, i1 0
-  %nop5172 = alloca i1, i1 0
-  %nop5173 = alloca i1, i1 0
-  %nop5174 = alloca i1, i1 0
-  %nop5175 = alloca i1, i1 0
-  %nop5176 = alloca i1, i1 0
-  %nop5177 = alloca i1, i1 0
-  %nop5178 = alloca i1, i1 0
-  %nop5179 = alloca i1, i1 0
-  %nop5180 = alloca i1, i1 0
-  %nop5181 = alloca i1, i1 0
-  %nop5182 = alloca i1, i1 0
-  %nop5183 = alloca i1, i1 0
-  %nop5184 = alloca i1, i1 0
-  %nop5185 = alloca i1, i1 0
-  %nop5186 = alloca i1, i1 0
-  %nop5187 = alloca i1, i1 0
-  %nop5188 = alloca i1, i1 0
-  %nop5189 = alloca i1, i1 0
-  %nop5190 = alloca i1, i1 0
-  %nop5191 = alloca i1, i1 0
-  %nop5192 = alloca i1, i1 0
-  %nop5193 = alloca i1, i1 0
-  %nop5194 = alloca i1, i1 0
-  %nop5195 = alloca i1, i1 0
-  %nop5196 = alloca i1, i1 0
-  %nop5197 = alloca i1, i1 0
-  %nop5198 = alloca i1, i1 0
-  %nop5199 = alloca i1, i1 0
-  %nop5200 = alloca i1, i1 0
-  %nop5201 = alloca i1, i1 0
-  %nop5202 = alloca i1, i1 0
-  %nop5203 = alloca i1, i1 0
-  %nop5204 = alloca i1, i1 0
-  %nop5205 = alloca i1, i1 0
-  %nop5206 = alloca i1, i1 0
-  %nop5207 = alloca i1, i1 0
-  %nop5208 = alloca i1, i1 0
-  %nop5209 = alloca i1, i1 0
-  %nop5210 = alloca i1, i1 0
-  %nop5211 = alloca i1, i1 0
-  %nop5212 = alloca i1, i1 0
-  %nop5213 = alloca i1, i1 0
-  %nop5214 = alloca i1, i1 0
-  %nop5215 = alloca i1, i1 0
-  %nop5216 = alloca i1, i1 0
-  %nop5217 = alloca i1, i1 0
-  %nop5218 = alloca i1, i1 0
-  %nop5219 = alloca i1, i1 0
-  %nop5220 = alloca i1, i1 0
-  %nop5221 = alloca i1, i1 0
-  %nop5222 = alloca i1, i1 0
-  %nop5223 = alloca i1, i1 0
-  %nop5224 = alloca i1, i1 0
-  %nop5225 = alloca i1, i1 0
-  %nop5226 = alloca i1, i1 0
-  %nop5227 = alloca i1, i1 0
-  %nop5228 = alloca i1, i1 0
-  %nop5229 = alloca i1, i1 0
-  %nop5230 = alloca i1, i1 0
-  %nop5231 = alloca i1, i1 0
-  %nop5232 = alloca i1, i1 0
-  %nop5233 = alloca i1, i1 0
-  %nop5234 = alloca i1, i1 0
-  %nop5235 = alloca i1, i1 0
-  %nop5236 = alloca i1, i1 0
-  %nop5237 = alloca i1, i1 0
-  %nop5238 = alloca i1, i1 0
-  %nop5239 = alloca i1, i1 0
-  %nop5240 = alloca i1, i1 0
-  %nop5241 = alloca i1, i1 0
-  %nop5242 = alloca i1, i1 0
-  %nop5243 = alloca i1, i1 0
-  %nop5244 = alloca i1, i1 0
-  %nop5245 = alloca i1, i1 0
-  %nop5246 = alloca i1, i1 0
-  %nop5247 = alloca i1, i1 0
-  %nop5248 = alloca i1, i1 0
-  %nop5249 = alloca i1, i1 0
-  %nop5250 = alloca i1, i1 0
-  %nop5251 = alloca i1, i1 0
-  %nop5252 = alloca i1, i1 0
-  %nop5253 = alloca i1, i1 0
-  %nop5254 = alloca i1, i1 0
-  %nop5255 = alloca i1, i1 0
-  %nop5256 = alloca i1, i1 0
-  %nop5257 = alloca i1, i1 0
-  %nop5258 = alloca i1, i1 0
-  %nop5259 = alloca i1, i1 0
-  %nop5260 = alloca i1, i1 0
-  %nop5261 = alloca i1, i1 0
-  %nop5262 = alloca i1, i1 0
-  %nop5263 = alloca i1, i1 0
-  %nop5264 = alloca i1, i1 0
-  %nop5265 = alloca i1, i1 0
-  %nop5266 = alloca i1, i1 0
-  %nop5267 = alloca i1, i1 0
-  %nop5268 = alloca i1, i1 0
-  %nop5269 = alloca i1, i1 0
-  %nop5270 = alloca i1, i1 0
-  %nop5271 = alloca i1, i1 0
-  %nop5272 = alloca i1, i1 0
-  %nop5273 = alloca i1, i1 0
-  %nop5274 = alloca i1, i1 0
-  %nop5275 = alloca i1, i1 0
-  %nop5276 = alloca i1, i1 0
-  %nop5277 = alloca i1, i1 0
-  %nop5278 = alloca i1, i1 0
-  %nop5279 = alloca i1, i1 0
-  %nop5280 = alloca i1, i1 0
-  %nop5281 = alloca i1, i1 0
-  %nop5282 = alloca i1, i1 0
-  %nop5283 = alloca i1, i1 0
-  %nop5284 = alloca i1, i1 0
-  %nop5285 = alloca i1, i1 0
-  %nop5286 = alloca i1, i1 0
-  %nop5287 = alloca i1, i1 0
-  %nop5288 = alloca i1, i1 0
-  %nop5289 = alloca i1, i1 0
-  %nop5290 = alloca i1, i1 0
-  %nop5291 = alloca i1, i1 0
-  %nop5292 = alloca i1, i1 0
-  %nop5293 = alloca i1, i1 0
-  %nop5294 = alloca i1, i1 0
-  %nop5295 = alloca i1, i1 0
-  %nop5296 = alloca i1, i1 0
-  %nop5297 = alloca i1, i1 0
-  %nop5298 = alloca i1, i1 0
-  %nop5299 = alloca i1, i1 0
-  %nop5300 = alloca i1, i1 0
-  %nop5301 = alloca i1, i1 0
-  %nop5302 = alloca i1, i1 0
-  %nop5303 = alloca i1, i1 0
-  %nop5304 = alloca i1, i1 0
-  %nop5305 = alloca i1, i1 0
-  %nop5306 = alloca i1, i1 0
-  %nop5307 = alloca i1, i1 0
-  %nop5308 = alloca i1, i1 0
-  %nop5309 = alloca i1, i1 0
-  %nop5310 = alloca i1, i1 0
-  %nop5311 = alloca i1, i1 0
-  %nop5312 = alloca i1, i1 0
-  %nop5313 = alloca i1, i1 0
-  %nop5314 = alloca i1, i1 0
-  %nop5315 = alloca i1, i1 0
-  %nop5316 = alloca i1, i1 0
-  %nop5317 = alloca i1, i1 0
-  %nop5318 = alloca i1, i1 0
-  %nop5319 = alloca i1, i1 0
-  %nop5320 = alloca i1, i1 0
-  %nop5321 = alloca i1, i1 0
-  %nop5322 = alloca i1, i1 0
-  %nop5323 = alloca i1, i1 0
-  %nop5324 = alloca i1, i1 0
-  %nop5325 = alloca i1, i1 0
-  %nop5326 = alloca i1, i1 0
-  %nop5327 = alloca i1, i1 0
-  %nop5328 = alloca i1, i1 0
-  %nop5329 = alloca i1, i1 0
-  %nop5330 = alloca i1, i1 0
-  %nop5331 = alloca i1, i1 0
-  %nop5332 = alloca i1, i1 0
-  %nop5333 = alloca i1, i1 0
-  %nop5334 = alloca i1, i1 0
-  %nop5335 = alloca i1, i1 0
-  %nop5336 = alloca i1, i1 0
-  %nop5337 = alloca i1, i1 0
-  %nop5338 = alloca i1, i1 0
-  %nop5339 = alloca i1, i1 0
-  %nop5340 = alloca i1, i1 0
-  %nop5341 = alloca i1, i1 0
-  %nop5342 = alloca i1, i1 0
-  %nop5343 = alloca i1, i1 0
-  %nop5344 = alloca i1, i1 0
-  %nop5345 = alloca i1, i1 0
-  %nop5346 = alloca i1, i1 0
-  %nop5347 = alloca i1, i1 0
-  %nop5348 = alloca i1, i1 0
-  %nop5349 = alloca i1, i1 0
-  %nop5350 = alloca i1, i1 0
-  %nop5351 = alloca i1, i1 0
-  %nop5352 = alloca i1, i1 0
-  %nop5353 = alloca i1, i1 0
-  %nop5354 = alloca i1, i1 0
-  %nop5355 = alloca i1, i1 0
-  %nop5356 = alloca i1, i1 0
-  %nop5357 = alloca i1, i1 0
-  %nop5358 = alloca i1, i1 0
-  %nop5359 = alloca i1, i1 0
-  %nop5360 = alloca i1, i1 0
-  %nop5361 = alloca i1, i1 0
-  %nop5362 = alloca i1, i1 0
-  %nop5363 = alloca i1, i1 0
-  %nop5364 = alloca i1, i1 0
-  %nop5365 = alloca i1, i1 0
-  %nop5366 = alloca i1, i1 0
-  %nop5367 = alloca i1, i1 0
-  %nop5368 = alloca i1, i1 0
-  %nop5369 = alloca i1, i1 0
-  %nop5370 = alloca i1, i1 0
-  %nop5371 = alloca i1, i1 0
-  %nop5372 = alloca i1, i1 0
-  %nop5373 = alloca i1, i1 0
-  %nop5374 = alloca i1, i1 0
-  %nop5375 = alloca i1, i1 0
-  %nop5376 = alloca i1, i1 0
-  %nop5377 = alloca i1, i1 0
-  %nop5378 = alloca i1, i1 0
-  %nop5379 = alloca i1, i1 0
-  %nop5380 = alloca i1, i1 0
-  %nop5381 = alloca i1, i1 0
-  %nop5382 = alloca i1, i1 0
-  %nop5383 = alloca i1, i1 0
-  %nop5384 = alloca i1, i1 0
-  %nop5385 = alloca i1, i1 0
-  %nop5386 = alloca i1, i1 0
-  %nop5387 = alloca i1, i1 0
-  %nop5388 = alloca i1, i1 0
-  %nop5389 = alloca i1, i1 0
-  %nop5390 = alloca i1, i1 0
-  %nop5391 = alloca i1, i1 0
-  %nop5392 = alloca i1, i1 0
-  %nop5393 = alloca i1, i1 0
-  %nop5394 = alloca i1, i1 0
-  %nop5395 = alloca i1, i1 0
-  %nop5396 = alloca i1, i1 0
-  %nop5397 = alloca i1, i1 0
-  %nop5398 = alloca i1, i1 0
-  %nop5399 = alloca i1, i1 0
-  %nop5400 = alloca i1, i1 0
-  %nop5401 = alloca i1, i1 0
-  %nop5402 = alloca i1, i1 0
-  %nop5403 = alloca i1, i1 0
-  %nop5404 = alloca i1, i1 0
-  %nop5405 = alloca i1, i1 0
-  %nop5406 = alloca i1, i1 0
-  %nop5407 = alloca i1, i1 0
-  %nop5408 = alloca i1, i1 0
-  %nop5409 = alloca i1, i1 0
-  %nop5410 = alloca i1, i1 0
-  %nop5411 = alloca i1, i1 0
-  %nop5412 = alloca i1, i1 0
-  %nop5413 = alloca i1, i1 0
-  %nop5414 = alloca i1, i1 0
-  %nop5415 = alloca i1, i1 0
-  %nop5416 = alloca i1, i1 0
-  %nop5417 = alloca i1, i1 0
-  %nop5418 = alloca i1, i1 0
-  %nop5419 = alloca i1, i1 0
-  %nop5420 = alloca i1, i1 0
-  %nop5421 = alloca i1, i1 0
-  %nop5422 = alloca i1, i1 0
-  %nop5423 = alloca i1, i1 0
-  %nop5424 = alloca i1, i1 0
-  %nop5425 = alloca i1, i1 0
-  %nop5426 = alloca i1, i1 0
-  %nop5427 = alloca i1, i1 0
-  %nop5428 = alloca i1, i1 0
-  %nop5429 = alloca i1, i1 0
-  %nop5430 = alloca i1, i1 0
-  %nop5431 = alloca i1, i1 0
-  %nop5432 = alloca i1, i1 0
-  %nop5433 = alloca i1, i1 0
-  %nop5434 = alloca i1, i1 0
-  %nop5435 = alloca i1, i1 0
-  %nop5436 = alloca i1, i1 0
-  %nop5437 = alloca i1, i1 0
-  %nop5438 = alloca i1, i1 0
-  %nop5439 = alloca i1, i1 0
-  %nop5440 = alloca i1, i1 0
-  %nop5441 = alloca i1, i1 0
-  %nop5442 = alloca i1, i1 0
-  %nop5443 = alloca i1, i1 0
-  %nop5444 = alloca i1, i1 0
-  %nop5445 = alloca i1, i1 0
-  %nop5446 = alloca i1, i1 0
-  %nop5447 = alloca i1, i1 0
-  %nop5448 = alloca i1, i1 0
-  %nop5449 = alloca i1, i1 0
-  %nop5450 = alloca i1, i1 0
-  %nop5451 = alloca i1, i1 0
-  %nop5452 = alloca i1, i1 0
-  %nop5453 = alloca i1, i1 0
-  %nop5454 = alloca i1, i1 0
-  %nop5455 = alloca i1, i1 0
-  %nop5456 = alloca i1, i1 0
-  %nop5457 = alloca i1, i1 0
-  %nop5458 = alloca i1, i1 0
-  %nop5459 = alloca i1, i1 0
-  %nop5460 = alloca i1, i1 0
-  %nop5461 = alloca i1, i1 0
-  %nop5462 = alloca i1, i1 0
-  %nop5463 = alloca i1, i1 0
-  %nop5464 = alloca i1, i1 0
-  %nop5465 = alloca i1, i1 0
-  %nop5466 = alloca i1, i1 0
-  %nop5467 = alloca i1, i1 0
-  %nop5468 = alloca i1, i1 0
-  %nop5469 = alloca i1, i1 0
-  %nop5470 = alloca i1, i1 0
-  %nop5471 = alloca i1, i1 0
-  %nop5472 = alloca i1, i1 0
-  %nop5473 = alloca i1, i1 0
-  %nop5474 = alloca i1, i1 0
-  %nop5475 = alloca i1, i1 0
-  %nop5476 = alloca i1, i1 0
-  %nop5477 = alloca i1, i1 0
-  %nop5478 = alloca i1, i1 0
-  %nop5479 = alloca i1, i1 0
-  %nop5480 = alloca i1, i1 0
-  %nop5481 = alloca i1, i1 0
-  %nop5482 = alloca i1, i1 0
-  %nop5483 = alloca i1, i1 0
-  %nop5484 = alloca i1, i1 0
-  %nop5485 = alloca i1, i1 0
-  %nop5486 = alloca i1, i1 0
-  %nop5487 = alloca i1, i1 0
-  %nop5488 = alloca i1, i1 0
-  %nop5489 = alloca i1, i1 0
-  %nop5490 = alloca i1, i1 0
-  %nop5491 = alloca i1, i1 0
-  %nop5492 = alloca i1, i1 0
-  %nop5493 = alloca i1, i1 0
-  %nop5494 = alloca i1, i1 0
-  %nop5495 = alloca i1, i1 0
-  %nop5496 = alloca i1, i1 0
-  %nop5497 = alloca i1, i1 0
-  %nop5498 = alloca i1, i1 0
-  %nop5499 = alloca i1, i1 0
-  %nop5500 = alloca i1, i1 0
-  %nop5501 = alloca i1, i1 0
-  %nop5502 = alloca i1, i1 0
-  %nop5503 = alloca i1, i1 0
-  %nop5504 = alloca i1, i1 0
-  %nop5505 = alloca i1, i1 0
-  %nop5506 = alloca i1, i1 0
-  %nop5507 = alloca i1, i1 0
-  %nop5508 = alloca i1, i1 0
-  %nop5509 = alloca i1, i1 0
-  %nop5510 = alloca i1, i1 0
-  %nop5511 = alloca i1, i1 0
-  %nop5512 = alloca i1, i1 0
-  %nop5513 = alloca i1, i1 0
-  %nop5514 = alloca i1, i1 0
-  %nop5515 = alloca i1, i1 0
-  %nop5516 = alloca i1, i1 0
-  %nop5517 = alloca i1, i1 0
-  %nop5518 = alloca i1, i1 0
-  %nop5519 = alloca i1, i1 0
-  %nop5520 = alloca i1, i1 0
-  %nop5521 = alloca i1, i1 0
-  %nop5522 = alloca i1, i1 0
-  %nop5523 = alloca i1, i1 0
-  %nop5524 = alloca i1, i1 0
-  %nop5525 = alloca i1, i1 0
-  %nop5526 = alloca i1, i1 0
-  %nop5527 = alloca i1, i1 0
-  %nop5528 = alloca i1, i1 0
-  %nop5529 = alloca i1, i1 0
-  %nop5530 = alloca i1, i1 0
-  %nop5531 = alloca i1, i1 0
-  %nop5532 = alloca i1, i1 0
-  %nop5533 = alloca i1, i1 0
-  %nop5534 = alloca i1, i1 0
-  %nop5535 = alloca i1, i1 0
-  %nop5536 = alloca i1, i1 0
-  %nop5537 = alloca i1, i1 0
-  %nop5538 = alloca i1, i1 0
-  %nop5539 = alloca i1, i1 0
-  %nop5540 = alloca i1, i1 0
-  %nop5541 = alloca i1, i1 0
-  %nop5542 = alloca i1, i1 0
-  %nop5543 = alloca i1, i1 0
-  %nop5544 = alloca i1, i1 0
-  %nop5545 = alloca i1, i1 0
-  %nop5546 = alloca i1, i1 0
-  %nop5547 = alloca i1, i1 0
-  %nop5548 = alloca i1, i1 0
-  %nop5549 = alloca i1, i1 0
-  %nop5550 = alloca i1, i1 0
-  %nop5551 = alloca i1, i1 0
-  %nop5552 = alloca i1, i1 0
-  %nop5553 = alloca i1, i1 0
-  %nop5554 = alloca i1, i1 0
-  %nop5555 = alloca i1, i1 0
-  %nop5556 = alloca i1, i1 0
-  %nop5557 = alloca i1, i1 0
-  %nop5558 = alloca i1, i1 0
-  %nop5559 = alloca i1, i1 0
-  %nop5560 = alloca i1, i1 0
-  %nop5561 = alloca i1, i1 0
-  %nop5562 = alloca i1, i1 0
-  %nop5563 = alloca i1, i1 0
-  %nop5564 = alloca i1, i1 0
-  %nop5565 = alloca i1, i1 0
-  %nop5566 = alloca i1, i1 0
-  %nop5567 = alloca i1, i1 0
-  %nop5568 = alloca i1, i1 0
-  %nop5569 = alloca i1, i1 0
-  %nop5570 = alloca i1, i1 0
-  %nop5571 = alloca i1, i1 0
-  %nop5572 = alloca i1, i1 0
-  %nop5573 = alloca i1, i1 0
-  %nop5574 = alloca i1, i1 0
-  %nop5575 = alloca i1, i1 0
-  %nop5576 = alloca i1, i1 0
-  %nop5577 = alloca i1, i1 0
-  %nop5578 = alloca i1, i1 0
-  %nop5579 = alloca i1, i1 0
-  %nop5580 = alloca i1, i1 0
-  %nop5581 = alloca i1, i1 0
-  %nop5582 = alloca i1, i1 0
-  %nop5583 = alloca i1, i1 0
-  %nop5584 = alloca i1, i1 0
-  %nop5585 = alloca i1, i1 0
-  %nop5586 = alloca i1, i1 0
-  %nop5587 = alloca i1, i1 0
-  %nop5588 = alloca i1, i1 0
-  %nop5589 = alloca i1, i1 0
-  %nop5590 = alloca i1, i1 0
-  %nop5591 = alloca i1, i1 0
-  %nop5592 = alloca i1, i1 0
-  %nop5593 = alloca i1, i1 0
-  %nop5594 = alloca i1, i1 0
-  %nop5595 = alloca i1, i1 0
-  %nop5596 = alloca i1, i1 0
-  %nop5597 = alloca i1, i1 0
-  %nop5598 = alloca i1, i1 0
-  %nop5599 = alloca i1, i1 0
-  %nop5600 = alloca i1, i1 0
-  %nop5601 = alloca i1, i1 0
-  %nop5602 = alloca i1, i1 0
-  %nop5603 = alloca i1, i1 0
-  %nop5604 = alloca i1, i1 0
-  %nop5605 = alloca i1, i1 0
-  %nop5606 = alloca i1, i1 0
-  %nop5607 = alloca i1, i1 0
-  %nop5608 = alloca i1, i1 0
-  %nop5609 = alloca i1, i1 0
-  %nop5610 = alloca i1, i1 0
-  %nop5611 = alloca i1, i1 0
-  %nop5612 = alloca i1, i1 0
-  %nop5613 = alloca i1, i1 0
-  %nop5614 = alloca i1, i1 0
-  %nop5615 = alloca i1, i1 0
-  %nop5616 = alloca i1, i1 0
-  %nop5617 = alloca i1, i1 0
-  %nop5618 = alloca i1, i1 0
-  %nop5619 = alloca i1, i1 0
-  %nop5620 = alloca i1, i1 0
-  %nop5621 = alloca i1, i1 0
-  %nop5622 = alloca i1, i1 0
-  %nop5623 = alloca i1, i1 0
-  %nop5624 = alloca i1, i1 0
-  %nop5625 = alloca i1, i1 0
-  %nop5626 = alloca i1, i1 0
-  %nop5627 = alloca i1, i1 0
-  %nop5628 = alloca i1, i1 0
-  %nop5629 = alloca i1, i1 0
-  %nop5630 = alloca i1, i1 0
-  %nop5631 = alloca i1, i1 0
-  %nop5632 = alloca i1, i1 0
-  %nop5633 = alloca i1, i1 0
-  %nop5634 = alloca i1, i1 0
-  %nop5635 = alloca i1, i1 0
-  %nop5636 = alloca i1, i1 0
-  %nop5637 = alloca i1, i1 0
-  %nop5638 = alloca i1, i1 0
-  %nop5639 = alloca i1, i1 0
-  %nop5640 = alloca i1, i1 0
-  %nop5641 = alloca i1, i1 0
-  %nop5642 = alloca i1, i1 0
-  %nop5643 = alloca i1, i1 0
-  %nop5644 = alloca i1, i1 0
-  %nop5645 = alloca i1, i1 0
-  %nop5646 = alloca i1, i1 0
-  %nop5647 = alloca i1, i1 0
-  %nop5648 = alloca i1, i1 0
-  %nop5649 = alloca i1, i1 0
-  %nop5650 = alloca i1, i1 0
-  %nop5651 = alloca i1, i1 0
-  %nop5652 = alloca i1, i1 0
-  %nop5653 = alloca i1, i1 0
-  %nop5654 = alloca i1, i1 0
-  %nop5655 = alloca i1, i1 0
-  %nop5656 = alloca i1, i1 0
-  %nop5657 = alloca i1, i1 0
-  %nop5658 = alloca i1, i1 0
-  %nop5659 = alloca i1, i1 0
-  %nop5660 = alloca i1, i1 0
-  %nop5661 = alloca i1, i1 0
-  %nop5662 = alloca i1, i1 0
-  %nop5663 = alloca i1, i1 0
-  %nop5664 = alloca i1, i1 0
-  %nop5665 = alloca i1, i1 0
-  %nop5666 = alloca i1, i1 0
-  %nop5667 = alloca i1, i1 0
-  %nop5668 = alloca i1, i1 0
-  %nop5669 = alloca i1, i1 0
-  %nop5670 = alloca i1, i1 0
-  %nop5671 = alloca i1, i1 0
-  %nop5672 = alloca i1, i1 0
-  %nop5673 = alloca i1, i1 0
-  %nop5674 = alloca i1, i1 0
-  %nop5675 = alloca i1, i1 0
-  %nop5676 = alloca i1, i1 0
-  %nop5677 = alloca i1, i1 0
-  %nop5678 = alloca i1, i1 0
-  %nop5679 = alloca i1, i1 0
-  %nop5680 = alloca i1, i1 0
-  %nop5681 = alloca i1, i1 0
-  %nop5682 = alloca i1, i1 0
-  %nop5683 = alloca i1, i1 0
-  %nop5684 = alloca i1, i1 0
-  %nop5685 = alloca i1, i1 0
-  %nop5686 = alloca i1, i1 0
-  %nop5687 = alloca i1, i1 0
-  %nop5688 = alloca i1, i1 0
-  %nop5689 = alloca i1, i1 0
-  %nop5690 = alloca i1, i1 0
-  %nop5691 = alloca i1, i1 0
-  %nop5692 = alloca i1, i1 0
-  %nop5693 = alloca i1, i1 0
-  %nop5694 = alloca i1, i1 0
-  %nop5695 = alloca i1, i1 0
-  %nop5696 = alloca i1, i1 0
-  %nop5697 = alloca i1, i1 0
-  %nop5698 = alloca i1, i1 0
-  %nop5699 = alloca i1, i1 0
-  %nop5700 = alloca i1, i1 0
-  %nop5701 = alloca i1, i1 0
-  %nop5702 = alloca i1, i1 0
-  %nop5703 = alloca i1, i1 0
-  %nop5704 = alloca i1, i1 0
-  %nop5705 = alloca i1, i1 0
-  %nop5706 = alloca i1, i1 0
-  %nop5707 = alloca i1, i1 0
-  %nop5708 = alloca i1, i1 0
-  %nop5709 = alloca i1, i1 0
-  %nop5710 = alloca i1, i1 0
-  %nop5711 = alloca i1, i1 0
-  %nop5712 = alloca i1, i1 0
-  %nop5713 = alloca i1, i1 0
-  %nop5714 = alloca i1, i1 0
-  %nop5715 = alloca i1, i1 0
-  %nop5716 = alloca i1, i1 0
-  %nop5717 = alloca i1, i1 0
-  %nop5718 = alloca i1, i1 0
-  %nop5719 = alloca i1, i1 0
-  %nop5720 = alloca i1, i1 0
-  %nop5721 = alloca i1, i1 0
-  %nop5722 = alloca i1, i1 0
-  %nop5723 = alloca i1, i1 0
-  %nop5724 = alloca i1, i1 0
-  %nop5725 = alloca i1, i1 0
-  %nop5726 = alloca i1, i1 0
-  %nop5727 = alloca i1, i1 0
-  %nop5728 = alloca i1, i1 0
-  %nop5729 = alloca i1, i1 0
-  %nop5730 = alloca i1, i1 0
-  %nop5731 = alloca i1, i1 0
-  %nop5732 = alloca i1, i1 0
-  %nop5733 = alloca i1, i1 0
-  %nop5734 = alloca i1, i1 0
-  %nop5735 = alloca i1, i1 0
-  %nop5736 = alloca i1, i1 0
-  %nop5737 = alloca i1, i1 0
-  %nop5738 = alloca i1, i1 0
-  %nop5739 = alloca i1, i1 0
-  %nop5740 = alloca i1, i1 0
-  %nop5741 = alloca i1, i1 0
-  %nop5742 = alloca i1, i1 0
-  %nop5743 = alloca i1, i1 0
-  %nop5744 = alloca i1, i1 0
-  %nop5745 = alloca i1, i1 0
-  %nop5746 = alloca i1, i1 0
-  %nop5747 = alloca i1, i1 0
-  %nop5748 = alloca i1, i1 0
-  %nop5749 = alloca i1, i1 0
-  %nop5750 = alloca i1, i1 0
-  %nop5751 = alloca i1, i1 0
-  %nop5752 = alloca i1, i1 0
-  %nop5753 = alloca i1, i1 0
-  %nop5754 = alloca i1, i1 0
-  %nop5755 = alloca i1, i1 0
-  %nop5756 = alloca i1, i1 0
-  %nop5757 = alloca i1, i1 0
-  %nop5758 = alloca i1, i1 0
-  %nop5759 = alloca i1, i1 0
-  %nop5760 = alloca i1, i1 0
-  %nop5761 = alloca i1, i1 0
-  %nop5762 = alloca i1, i1 0
-  %nop5763 = alloca i1, i1 0
-  %nop5764 = alloca i1, i1 0
-  %nop5765 = alloca i1, i1 0
-  %nop5766 = alloca i1, i1 0
-  %nop5767 = alloca i1, i1 0
-  %nop5768 = alloca i1, i1 0
-  %nop5769 = alloca i1, i1 0
-  %nop5770 = alloca i1, i1 0
-  %nop5771 = alloca i1, i1 0
-  %nop5772 = alloca i1, i1 0
-  %nop5773 = alloca i1, i1 0
-  %nop5774 = alloca i1, i1 0
-  %nop5775 = alloca i1, i1 0
-  %nop5776 = alloca i1, i1 0
-  %nop5777 = alloca i1, i1 0
-  %nop5778 = alloca i1, i1 0
-  %nop5779 = alloca i1, i1 0
-  %nop5780 = alloca i1, i1 0
-  %nop5781 = alloca i1, i1 0
-  %nop5782 = alloca i1, i1 0
-  %nop5783 = alloca i1, i1 0
-  %nop5784 = alloca i1, i1 0
-  %nop5785 = alloca i1, i1 0
-  %nop5786 = alloca i1, i1 0
-  %nop5787 = alloca i1, i1 0
-  %nop5788 = alloca i1, i1 0
-  %nop5789 = alloca i1, i1 0
-  %nop5790 = alloca i1, i1 0
-  %nop5791 = alloca i1, i1 0
-  %nop5792 = alloca i1, i1 0
-  %nop5793 = alloca i1, i1 0
-  %nop5794 = alloca i1, i1 0
-  %nop5795 = alloca i1, i1 0
-  %nop5796 = alloca i1, i1 0
-  %nop5797 = alloca i1, i1 0
-  %nop5798 = alloca i1, i1 0
-  %nop5799 = alloca i1, i1 0
-  %nop5800 = alloca i1, i1 0
-  %nop5801 = alloca i1, i1 0
-  %nop5802 = alloca i1, i1 0
-  %nop5803 = alloca i1, i1 0
-  %nop5804 = alloca i1, i1 0
-  %nop5805 = alloca i1, i1 0
-  %nop5806 = alloca i1, i1 0
-  %nop5807 = alloca i1, i1 0
-  %nop5808 = alloca i1, i1 0
-  %nop5809 = alloca i1, i1 0
-  %nop5810 = alloca i1, i1 0
-  %nop5811 = alloca i1, i1 0
-  %nop5812 = alloca i1, i1 0
-  %nop5813 = alloca i1, i1 0
-  %nop5814 = alloca i1, i1 0
-  %nop5815 = alloca i1, i1 0
-  %nop5816 = alloca i1, i1 0
-  %nop5817 = alloca i1, i1 0
-  %nop5818 = alloca i1, i1 0
-  %nop5819 = alloca i1, i1 0
-  %nop5820 = alloca i1, i1 0
-  %nop5821 = alloca i1, i1 0
-  %nop5822 = alloca i1, i1 0
-  %nop5823 = alloca i1, i1 0
-  %nop5824 = alloca i1, i1 0
-  %nop5825 = alloca i1, i1 0
-  %nop5826 = alloca i1, i1 0
-  %nop5827 = alloca i1, i1 0
-  %nop5828 = alloca i1, i1 0
-  %nop5829 = alloca i1, i1 0
-  %nop5830 = alloca i1, i1 0
-  %nop5831 = alloca i1, i1 0
-  %nop5832 = alloca i1, i1 0
-  %nop5833 = alloca i1, i1 0
-  %nop5834 = alloca i1, i1 0
-  %nop5835 = alloca i1, i1 0
-  %nop5836 = alloca i1, i1 0
-  %nop5837 = alloca i1, i1 0
-  %nop5838 = alloca i1, i1 0
-  %nop5839 = alloca i1, i1 0
-  %nop5840 = alloca i1, i1 0
-  %nop5841 = alloca i1, i1 0
-  %nop5842 = alloca i1, i1 0
-  %nop5843 = alloca i1, i1 0
-  %nop5844 = alloca i1, i1 0
-  %nop5845 = alloca i1, i1 0
-  %nop5846 = alloca i1, i1 0
-  %nop5847 = alloca i1, i1 0
-  %nop5848 = alloca i1, i1 0
-  %nop5849 = alloca i1, i1 0
-  %nop5850 = alloca i1, i1 0
-  %nop5851 = alloca i1, i1 0
-  %nop5852 = alloca i1, i1 0
-  %nop5853 = alloca i1, i1 0
-  %nop5854 = alloca i1, i1 0
-  %nop5855 = alloca i1, i1 0
-  %nop5856 = alloca i1, i1 0
-  %nop5857 = alloca i1, i1 0
-  %nop5858 = alloca i1, i1 0
-  %nop5859 = alloca i1, i1 0
-  %nop5860 = alloca i1, i1 0
-  %nop5861 = alloca i1, i1 0
-  %nop5862 = alloca i1, i1 0
-  %nop5863 = alloca i1, i1 0
-  %nop5864 = alloca i1, i1 0
-  %nop5865 = alloca i1, i1 0
-  %nop5866 = alloca i1, i1 0
-  %nop5867 = alloca i1, i1 0
-  %nop5868 = alloca i1, i1 0
-  %nop5869 = alloca i1, i1 0
-  %nop5870 = alloca i1, i1 0
-  %nop5871 = alloca i1, i1 0
-  %nop5872 = alloca i1, i1 0
-  %nop5873 = alloca i1, i1 0
-  %nop5874 = alloca i1, i1 0
-  %nop5875 = alloca i1, i1 0
-  %nop5876 = alloca i1, i1 0
-  %nop5877 = alloca i1, i1 0
-  %nop5878 = alloca i1, i1 0
-  %nop5879 = alloca i1, i1 0
-  %nop5880 = alloca i1, i1 0
-  %nop5881 = alloca i1, i1 0
-  %nop5882 = alloca i1, i1 0
-  %nop5883 = alloca i1, i1 0
-  %nop5884 = alloca i1, i1 0
-  %nop5885 = alloca i1, i1 0
-  %nop5886 = alloca i1, i1 0
-  %nop5887 = alloca i1, i1 0
-  %nop5888 = alloca i1, i1 0
-  %nop5889 = alloca i1, i1 0
-  %nop5890 = alloca i1, i1 0
-  %nop5891 = alloca i1, i1 0
-  %nop5892 = alloca i1, i1 0
-  %nop5893 = alloca i1, i1 0
-  %nop5894 = alloca i1, i1 0
-  %nop5895 = alloca i1, i1 0
-  %nop5896 = alloca i1, i1 0
-  %nop5897 = alloca i1, i1 0
-  %nop5898 = alloca i1, i1 0
-  %nop5899 = alloca i1, i1 0
-  %nop5900 = alloca i1, i1 0
-  %nop5901 = alloca i1, i1 0
-  %nop5902 = alloca i1, i1 0
-  %nop5903 = alloca i1, i1 0
-  %nop5904 = alloca i1, i1 0
-  %nop5905 = alloca i1, i1 0
-  %nop5906 = alloca i1, i1 0
-  %nop5907 = alloca i1, i1 0
-  %nop5908 = alloca i1, i1 0
-  %nop5909 = alloca i1, i1 0
-  %nop5910 = alloca i1, i1 0
-  %nop5911 = alloca i1, i1 0
-  %nop5912 = alloca i1, i1 0
-  %nop5913 = alloca i1, i1 0
-  %nop5914 = alloca i1, i1 0
-  %nop5915 = alloca i1, i1 0
-  %nop5916 = alloca i1, i1 0
-  %nop5917 = alloca i1, i1 0
-  %nop5918 = alloca i1, i1 0
-  %nop5919 = alloca i1, i1 0
-  %nop5920 = alloca i1, i1 0
-  %nop5921 = alloca i1, i1 0
-  %nop5922 = alloca i1, i1 0
-  %nop5923 = alloca i1, i1 0
-  %nop5924 = alloca i1, i1 0
-  %nop5925 = alloca i1, i1 0
-  %nop5926 = alloca i1, i1 0
-  %nop5927 = alloca i1, i1 0
-  %nop5928 = alloca i1, i1 0
-  %nop5929 = alloca i1, i1 0
-  %nop5930 = alloca i1, i1 0
-  %nop5931 = alloca i1, i1 0
-  %nop5932 = alloca i1, i1 0
-  %nop5933 = alloca i1, i1 0
-  %nop5934 = alloca i1, i1 0
-  %nop5935 = alloca i1, i1 0
-  %nop5936 = alloca i1, i1 0
-  %nop5937 = alloca i1, i1 0
-  %nop5938 = alloca i1, i1 0
-  %nop5939 = alloca i1, i1 0
-  %nop5940 = alloca i1, i1 0
-  %nop5941 = alloca i1, i1 0
-  %nop5942 = alloca i1, i1 0
-  %nop5943 = alloca i1, i1 0
-  %nop5944 = alloca i1, i1 0
-  %nop5945 = alloca i1, i1 0
-  %nop5946 = alloca i1, i1 0
-  %nop5947 = alloca i1, i1 0
-  %nop5948 = alloca i1, i1 0
-  %nop5949 = alloca i1, i1 0
-  %nop5950 = alloca i1, i1 0
-  %nop5951 = alloca i1, i1 0
-  %nop5952 = alloca i1, i1 0
-  %nop5953 = alloca i1, i1 0
-  %nop5954 = alloca i1, i1 0
-  %nop5955 = alloca i1, i1 0
-  %nop5956 = alloca i1, i1 0
-  %nop5957 = alloca i1, i1 0
-  %nop5958 = alloca i1, i1 0
-  %nop5959 = alloca i1, i1 0
-  %nop5960 = alloca i1, i1 0
-  %nop5961 = alloca i1, i1 0
-  %nop5962 = alloca i1, i1 0
-  %nop5963 = alloca i1, i1 0
-  %nop5964 = alloca i1, i1 0
-  %nop5965 = alloca i1, i1 0
-  %nop5966 = alloca i1, i1 0
-  %nop5967 = alloca i1, i1 0
-  %nop5968 = alloca i1, i1 0
-  %nop5969 = alloca i1, i1 0
-  %nop5970 = alloca i1, i1 0
-  %nop5971 = alloca i1, i1 0
-  %nop5972 = alloca i1, i1 0
-  %nop5973 = alloca i1, i1 0
-  %nop5974 = alloca i1, i1 0
-  %nop5975 = alloca i1, i1 0
-  %nop5976 = alloca i1, i1 0
-  %nop5977 = alloca i1, i1 0
-  %nop5978 = alloca i1, i1 0
-  %nop5979 = alloca i1, i1 0
-  %nop5980 = alloca i1, i1 0
-  %nop5981 = alloca i1, i1 0
-  %nop5982 = alloca i1, i1 0
-  %nop5983 = alloca i1, i1 0
-  %nop5984 = alloca i1, i1 0
-  %nop5985 = alloca i1, i1 0
-  %nop5986 = alloca i1, i1 0
-  %nop5987 = alloca i1, i1 0
-  %nop5988 = alloca i1, i1 0
-  %nop5989 = alloca i1, i1 0
-  %nop5990 = alloca i1, i1 0
-  %nop5991 = alloca i1, i1 0
-  %nop5992 = alloca i1, i1 0
-  %nop5993 = alloca i1, i1 0
-  %nop5994 = alloca i1, i1 0
-  %nop5995 = alloca i1, i1 0
-  %nop5996 = alloca i1, i1 0
-  %nop5997 = alloca i1, i1 0
-  %nop5998 = alloca i1, i1 0
-  %nop5999 = alloca i1, i1 0
-  %nop6000 = alloca i1, i1 0
-  %nop6001 = alloca i1, i1 0
-  %nop6002 = alloca i1, i1 0
-  %nop6003 = alloca i1, i1 0
-  %nop6004 = alloca i1, i1 0
-  %nop6005 = alloca i1, i1 0
-  %nop6006 = alloca i1, i1 0
-  %nop6007 = alloca i1, i1 0
-  %nop6008 = alloca i1, i1 0
-  %nop6009 = alloca i1, i1 0
-  %nop6010 = alloca i1, i1 0
-  %nop6011 = alloca i1, i1 0
-  %nop6012 = alloca i1, i1 0
-  %nop6013 = alloca i1, i1 0
-  %nop6014 = alloca i1, i1 0
-  %nop6015 = alloca i1, i1 0
-  %nop6016 = alloca i1, i1 0
-  %nop6017 = alloca i1, i1 0
-  %nop6018 = alloca i1, i1 0
-  %nop6019 = alloca i1, i1 0
-  %nop6020 = alloca i1, i1 0
-  %nop6021 = alloca i1, i1 0
-  %nop6022 = alloca i1, i1 0
-  %nop6023 = alloca i1, i1 0
-  %nop6024 = alloca i1, i1 0
-  %nop6025 = alloca i1, i1 0
-  %nop6026 = alloca i1, i1 0
-  %nop6027 = alloca i1, i1 0
-  %nop6028 = alloca i1, i1 0
-  %nop6029 = alloca i1, i1 0
-  %nop6030 = alloca i1, i1 0
-  %nop6031 = alloca i1, i1 0
-  %nop6032 = alloca i1, i1 0
-  %nop6033 = alloca i1, i1 0
-  %nop6034 = alloca i1, i1 0
-  %nop6035 = alloca i1, i1 0
-  %nop6036 = alloca i1, i1 0
-  %nop6037 = alloca i1, i1 0
-  %nop6038 = alloca i1, i1 0
-  %nop6039 = alloca i1, i1 0
-  %nop6040 = alloca i1, i1 0
-  %nop6041 = alloca i1, i1 0
-  %nop6042 = alloca i1, i1 0
-  %nop6043 = alloca i1, i1 0
-  %nop6044 = alloca i1, i1 0
-  %nop6045 = alloca i1, i1 0
-  %nop6046 = alloca i1, i1 0
-  %nop6047 = alloca i1, i1 0
-  %nop6048 = alloca i1, i1 0
-  %nop6049 = alloca i1, i1 0
-  %nop6050 = alloca i1, i1 0
-  %nop6051 = alloca i1, i1 0
-  %nop6052 = alloca i1, i1 0
-  %nop6053 = alloca i1, i1 0
-  %nop6054 = alloca i1, i1 0
-  %nop6055 = alloca i1, i1 0
-  %nop6056 = alloca i1, i1 0
-  %nop6057 = alloca i1, i1 0
-  %nop6058 = alloca i1, i1 0
-  %nop6059 = alloca i1, i1 0
-  %nop6060 = alloca i1, i1 0
-  %nop6061 = alloca i1, i1 0
-  %nop6062 = alloca i1, i1 0
-  %nop6063 = alloca i1, i1 0
-  %nop6064 = alloca i1, i1 0
-  %nop6065 = alloca i1, i1 0
-  %nop6066 = alloca i1, i1 0
-  %nop6067 = alloca i1, i1 0
-  %nop6068 = alloca i1, i1 0
-  %nop6069 = alloca i1, i1 0
-  %nop6070 = alloca i1, i1 0
-  %nop6071 = alloca i1, i1 0
-  %nop6072 = alloca i1, i1 0
-  %nop6073 = alloca i1, i1 0
-  %nop6074 = alloca i1, i1 0
-  %nop6075 = alloca i1, i1 0
-  %nop6076 = alloca i1, i1 0
-  %nop6077 = alloca i1, i1 0
-  %nop6078 = alloca i1, i1 0
-  %nop6079 = alloca i1, i1 0
-  %nop6080 = alloca i1, i1 0
-  %nop6081 = alloca i1, i1 0
-  %nop6082 = alloca i1, i1 0
-  %nop6083 = alloca i1, i1 0
-  %nop6084 = alloca i1, i1 0
-  %nop6085 = alloca i1, i1 0
-  %nop6086 = alloca i1, i1 0
-  %nop6087 = alloca i1, i1 0
-  %nop6088 = alloca i1, i1 0
-  %nop6089 = alloca i1, i1 0
-  %nop6090 = alloca i1, i1 0
-  %nop6091 = alloca i1, i1 0
-  %nop6092 = alloca i1, i1 0
-  %nop6093 = alloca i1, i1 0
-  %nop6094 = alloca i1, i1 0
-  %nop6095 = alloca i1, i1 0
-  %nop6096 = alloca i1, i1 0
-  %nop6097 = alloca i1, i1 0
-  %nop6098 = alloca i1, i1 0
-  %nop6099 = alloca i1, i1 0
-  %nop6100 = alloca i1, i1 0
-  %nop6101 = alloca i1, i1 0
-  %nop6102 = alloca i1, i1 0
-  %nop6103 = alloca i1, i1 0
-  %nop6104 = alloca i1, i1 0
-  %nop6105 = alloca i1, i1 0
-  %nop6106 = alloca i1, i1 0
-  %nop6107 = alloca i1, i1 0
-  %nop6108 = alloca i1, i1 0
-  %nop6109 = alloca i1, i1 0
-  %nop6110 = alloca i1, i1 0
-  %nop6111 = alloca i1, i1 0
-  %nop6112 = alloca i1, i1 0
-  %nop6113 = alloca i1, i1 0
-  %nop6114 = alloca i1, i1 0
-  %nop6115 = alloca i1, i1 0
-  %nop6116 = alloca i1, i1 0
-  %nop6117 = alloca i1, i1 0
-  %nop6118 = alloca i1, i1 0
-  %nop6119 = alloca i1, i1 0
-  %nop6120 = alloca i1, i1 0
-  %nop6121 = alloca i1, i1 0
-  %nop6122 = alloca i1, i1 0
-  %nop6123 = alloca i1, i1 0
-  %nop6124 = alloca i1, i1 0
-  %nop6125 = alloca i1, i1 0
-  %nop6126 = alloca i1, i1 0
-  %nop6127 = alloca i1, i1 0
-  %nop6128 = alloca i1, i1 0
-  %nop6129 = alloca i1, i1 0
-  %nop6130 = alloca i1, i1 0
-  %nop6131 = alloca i1, i1 0
-  %nop6132 = alloca i1, i1 0
-  %nop6133 = alloca i1, i1 0
-  %nop6134 = alloca i1, i1 0
-  %nop6135 = alloca i1, i1 0
-  %nop6136 = alloca i1, i1 0
-  %nop6137 = alloca i1, i1 0
-  %nop6138 = alloca i1, i1 0
-  %nop6139 = alloca i1, i1 0
-  %nop6140 = alloca i1, i1 0
-  %nop6141 = alloca i1, i1 0
-  %nop6142 = alloca i1, i1 0
-  %nop6143 = alloca i1, i1 0
-  %nop6144 = alloca i1, i1 0
-  %nop6145 = alloca i1, i1 0
-  %nop6146 = alloca i1, i1 0
-  %nop6147 = alloca i1, i1 0
-  %nop6148 = alloca i1, i1 0
-  %nop6149 = alloca i1, i1 0
-  %nop6150 = alloca i1, i1 0
-  %nop6151 = alloca i1, i1 0
-  %nop6152 = alloca i1, i1 0
-  %nop6153 = alloca i1, i1 0
-  %nop6154 = alloca i1, i1 0
-  %nop6155 = alloca i1, i1 0
-  %nop6156 = alloca i1, i1 0
-  %nop6157 = alloca i1, i1 0
-  %nop6158 = alloca i1, i1 0
-  %nop6159 = alloca i1, i1 0
-  %nop6160 = alloca i1, i1 0
-  %nop6161 = alloca i1, i1 0
-  %nop6162 = alloca i1, i1 0
-  %nop6163 = alloca i1, i1 0
-  %nop6164 = alloca i1, i1 0
-  %nop6165 = alloca i1, i1 0
-  %nop6166 = alloca i1, i1 0
-  %nop6167 = alloca i1, i1 0
-  %nop6168 = alloca i1, i1 0
-  %nop6169 = alloca i1, i1 0
-  %nop6170 = alloca i1, i1 0
-  %nop6171 = alloca i1, i1 0
-  %nop6172 = alloca i1, i1 0
-  %nop6173 = alloca i1, i1 0
-  %nop6174 = alloca i1, i1 0
-  %nop6175 = alloca i1, i1 0
-  %nop6176 = alloca i1, i1 0
-  %nop6177 = alloca i1, i1 0
-  %nop6178 = alloca i1, i1 0
-  %nop6179 = alloca i1, i1 0
-  %nop6180 = alloca i1, i1 0
-  %nop6181 = alloca i1, i1 0
-  %nop6182 = alloca i1, i1 0
-  %nop6183 = alloca i1, i1 0
-  %nop6184 = alloca i1, i1 0
-  %nop6185 = alloca i1, i1 0
-  %nop6186 = alloca i1, i1 0
-  %nop6187 = alloca i1, i1 0
-  %nop6188 = alloca i1, i1 0
-  %nop6189 = alloca i1, i1 0
-  %nop6190 = alloca i1, i1 0
-  %nop6191 = alloca i1, i1 0
-  %nop6192 = alloca i1, i1 0
-  %nop6193 = alloca i1, i1 0
-  %nop6194 = alloca i1, i1 0
-  %nop6195 = alloca i1, i1 0
-  %nop6196 = alloca i1, i1 0
-  %nop6197 = alloca i1, i1 0
-  %nop6198 = alloca i1, i1 0
-  %nop6199 = alloca i1, i1 0
-  %nop6200 = alloca i1, i1 0
-  %nop6201 = alloca i1, i1 0
-  %nop6202 = alloca i1, i1 0
-  %nop6203 = alloca i1, i1 0
-  %nop6204 = alloca i1, i1 0
-  %nop6205 = alloca i1, i1 0
-  %nop6206 = alloca i1, i1 0
-  %nop6207 = alloca i1, i1 0
-  %nop6208 = alloca i1, i1 0
-  %nop6209 = alloca i1, i1 0
-  %nop6210 = alloca i1, i1 0
-  %nop6211 = alloca i1, i1 0
-  %nop6212 = alloca i1, i1 0
-  %nop6213 = alloca i1, i1 0
-  %nop6214 = alloca i1, i1 0
-  %nop6215 = alloca i1, i1 0
-  %nop6216 = alloca i1, i1 0
-  %nop6217 = alloca i1, i1 0
-  %nop6218 = alloca i1, i1 0
-  %nop6219 = alloca i1, i1 0
-  %nop6220 = alloca i1, i1 0
-  %nop6221 = alloca i1, i1 0
-  %nop6222 = alloca i1, i1 0
-  %nop6223 = alloca i1, i1 0
-  %nop6224 = alloca i1, i1 0
-  %nop6225 = alloca i1, i1 0
-  %nop6226 = alloca i1, i1 0
-  %nop6227 = alloca i1, i1 0
-  %nop6228 = alloca i1, i1 0
-  %nop6229 = alloca i1, i1 0
-  %nop6230 = alloca i1, i1 0
-  %nop6231 = alloca i1, i1 0
-  %nop6232 = alloca i1, i1 0
-  %nop6233 = alloca i1, i1 0
-  %nop6234 = alloca i1, i1 0
-  %nop6235 = alloca i1, i1 0
-  %nop6236 = alloca i1, i1 0
-  %nop6237 = alloca i1, i1 0
-  %nop6238 = alloca i1, i1 0
-  %nop6239 = alloca i1, i1 0
-  %nop6240 = alloca i1, i1 0
-  %nop6241 = alloca i1, i1 0
-  %nop6242 = alloca i1, i1 0
-  %nop6243 = alloca i1, i1 0
-  %nop6244 = alloca i1, i1 0
-  %nop6245 = alloca i1, i1 0
-  %nop6246 = alloca i1, i1 0
-  %nop6247 = alloca i1, i1 0
-  %nop6248 = alloca i1, i1 0
-  %nop6249 = alloca i1, i1 0
-  %nop6250 = alloca i1, i1 0
-  %nop6251 = alloca i1, i1 0
-  %nop6252 = alloca i1, i1 0
-  %nop6253 = alloca i1, i1 0
-  %nop6254 = alloca i1, i1 0
-  %nop6255 = alloca i1, i1 0
-  %nop6256 = alloca i1, i1 0
-  %nop6257 = alloca i1, i1 0
-  %nop6258 = alloca i1, i1 0
-  %nop6259 = alloca i1, i1 0
-  %nop6260 = alloca i1, i1 0
-  %nop6261 = alloca i1, i1 0
-  %nop6262 = alloca i1, i1 0
-  %nop6263 = alloca i1, i1 0
-  %nop6264 = alloca i1, i1 0
-  %nop6265 = alloca i1, i1 0
-  %nop6266 = alloca i1, i1 0
-  %nop6267 = alloca i1, i1 0
-  %nop6268 = alloca i1, i1 0
-  %nop6269 = alloca i1, i1 0
-  %nop6270 = alloca i1, i1 0
-  %nop6271 = alloca i1, i1 0
-  %nop6272 = alloca i1, i1 0
-  %nop6273 = alloca i1, i1 0
-  %nop6274 = alloca i1, i1 0
-  %nop6275 = alloca i1, i1 0
-  %nop6276 = alloca i1, i1 0
-  %nop6277 = alloca i1, i1 0
-  %nop6278 = alloca i1, i1 0
-  %nop6279 = alloca i1, i1 0
-  %nop6280 = alloca i1, i1 0
-  %nop6281 = alloca i1, i1 0
-  %nop6282 = alloca i1, i1 0
-  %nop6283 = alloca i1, i1 0
-  %nop6284 = alloca i1, i1 0
-  %nop6285 = alloca i1, i1 0
-  %nop6286 = alloca i1, i1 0
-  %nop6287 = alloca i1, i1 0
-  %nop6288 = alloca i1, i1 0
-  %nop6289 = alloca i1, i1 0
-  %nop6290 = alloca i1, i1 0
-  %nop6291 = alloca i1, i1 0
-  %nop6292 = alloca i1, i1 0
-  %nop6293 = alloca i1, i1 0
-  %nop6294 = alloca i1, i1 0
-  %nop6295 = alloca i1, i1 0
-  %nop6296 = alloca i1, i1 0
-  %nop6297 = alloca i1, i1 0
-  %nop6298 = alloca i1, i1 0
-  %nop6299 = alloca i1, i1 0
-  %nop6300 = alloca i1, i1 0
-  %nop6301 = alloca i1, i1 0
-  %nop6302 = alloca i1, i1 0
-  %nop6303 = alloca i1, i1 0
-  %nop6304 = alloca i1, i1 0
-  %nop6305 = alloca i1, i1 0
-  %nop6306 = alloca i1, i1 0
-  %nop6307 = alloca i1, i1 0
-  %nop6308 = alloca i1, i1 0
-  %nop6309 = alloca i1, i1 0
-  %nop6310 = alloca i1, i1 0
-  %nop6311 = alloca i1, i1 0
-  %nop6312 = alloca i1, i1 0
-  %nop6313 = alloca i1, i1 0
-  %nop6314 = alloca i1, i1 0
-  %nop6315 = alloca i1, i1 0
-  %nop6316 = alloca i1, i1 0
-  %nop6317 = alloca i1, i1 0
-  %nop6318 = alloca i1, i1 0
-  %nop6319 = alloca i1, i1 0
-  %nop6320 = alloca i1, i1 0
-  %nop6321 = alloca i1, i1 0
-  %nop6322 = alloca i1, i1 0
-  %nop6323 = alloca i1, i1 0
-  %nop6324 = alloca i1, i1 0
-  %nop6325 = alloca i1, i1 0
-  %nop6326 = alloca i1, i1 0
-  %nop6327 = alloca i1, i1 0
-  %nop6328 = alloca i1, i1 0
-  %nop6329 = alloca i1, i1 0
-  %nop6330 = alloca i1, i1 0
-  %nop6331 = alloca i1, i1 0
-  %nop6332 = alloca i1, i1 0
-  %nop6333 = alloca i1, i1 0
-  %nop6334 = alloca i1, i1 0
-  %nop6335 = alloca i1, i1 0
-  %nop6336 = alloca i1, i1 0
-  %nop6337 = alloca i1, i1 0
-  %nop6338 = alloca i1, i1 0
-  %nop6339 = alloca i1, i1 0
-  %nop6340 = alloca i1, i1 0
-  %nop6341 = alloca i1, i1 0
-  %nop6342 = alloca i1, i1 0
-  %nop6343 = alloca i1, i1 0
-  %nop6344 = alloca i1, i1 0
-  %nop6345 = alloca i1, i1 0
-  %nop6346 = alloca i1, i1 0
-  %nop6347 = alloca i1, i1 0
-  %nop6348 = alloca i1, i1 0
-  %nop6349 = alloca i1, i1 0
-  %nop6350 = alloca i1, i1 0
-  %nop6351 = alloca i1, i1 0
-  %nop6352 = alloca i1, i1 0
-  %nop6353 = alloca i1, i1 0
-  %nop6354 = alloca i1, i1 0
-  %nop6355 = alloca i1, i1 0
-  %nop6356 = alloca i1, i1 0
-  %nop6357 = alloca i1, i1 0
-  %nop6358 = alloca i1, i1 0
-  %nop6359 = alloca i1, i1 0
-  %nop6360 = alloca i1, i1 0
-  %nop6361 = alloca i1, i1 0
-  %nop6362 = alloca i1, i1 0
-  %nop6363 = alloca i1, i1 0
-  %nop6364 = alloca i1, i1 0
-  %nop6365 = alloca i1, i1 0
-  %nop6366 = alloca i1, i1 0
-  %nop6367 = alloca i1, i1 0
-  %nop6368 = alloca i1, i1 0
-  %nop6369 = alloca i1, i1 0
-  %nop6370 = alloca i1, i1 0
-  %nop6371 = alloca i1, i1 0
-  %nop6372 = alloca i1, i1 0
-  %nop6373 = alloca i1, i1 0
-  %nop6374 = alloca i1, i1 0
-  %nop6375 = alloca i1, i1 0
-  %nop6376 = alloca i1, i1 0
-  %nop6377 = alloca i1, i1 0
-  %nop6378 = alloca i1, i1 0
-  %nop6379 = alloca i1, i1 0
-  %nop6380 = alloca i1, i1 0
-  %nop6381 = alloca i1, i1 0
-  %nop6382 = alloca i1, i1 0
-  %nop6383 = alloca i1, i1 0
-  %nop6384 = alloca i1, i1 0
-  %nop6385 = alloca i1, i1 0
-  %nop6386 = alloca i1, i1 0
-  %nop6387 = alloca i1, i1 0
-  %nop6388 = alloca i1, i1 0
-  %nop6389 = alloca i1, i1 0
-  %nop6390 = alloca i1, i1 0
-  %nop6391 = alloca i1, i1 0
-  %nop6392 = alloca i1, i1 0
-  %nop6393 = alloca i1, i1 0
-  %nop6394 = alloca i1, i1 0
-  %nop6395 = alloca i1, i1 0
-  %nop6396 = alloca i1, i1 0
-  %nop6397 = alloca i1, i1 0
-  %nop6398 = alloca i1, i1 0
-  %nop6399 = alloca i1, i1 0
-  %nop6400 = alloca i1, i1 0
-  %nop6401 = alloca i1, i1 0
-  %nop6402 = alloca i1, i1 0
-  %nop6403 = alloca i1, i1 0
-  %nop6404 = alloca i1, i1 0
-  %nop6405 = alloca i1, i1 0
-  %nop6406 = alloca i1, i1 0
-  %nop6407 = alloca i1, i1 0
-  %nop6408 = alloca i1, i1 0
-  %nop6409 = alloca i1, i1 0
-  %nop6410 = alloca i1, i1 0
-  %nop6411 = alloca i1, i1 0
-  %nop6412 = alloca i1, i1 0
-  %nop6413 = alloca i1, i1 0
-  %nop6414 = alloca i1, i1 0
-  %nop6415 = alloca i1, i1 0
-  %nop6416 = alloca i1, i1 0
-  %nop6417 = alloca i1, i1 0
-  %nop6418 = alloca i1, i1 0
-  %nop6419 = alloca i1, i1 0
-  %nop6420 = alloca i1, i1 0
-  %nop6421 = alloca i1, i1 0
-  %nop6422 = alloca i1, i1 0
-  %nop6423 = alloca i1, i1 0
-  %nop6424 = alloca i1, i1 0
-  %nop6425 = alloca i1, i1 0
-  %nop6426 = alloca i1, i1 0
-  %nop6427 = alloca i1, i1 0
-  %nop6428 = alloca i1, i1 0
-  %nop6429 = alloca i1, i1 0
-  %nop6430 = alloca i1, i1 0
-  %nop6431 = alloca i1, i1 0
-  %nop6432 = alloca i1, i1 0
-  %nop6433 = alloca i1, i1 0
-  %nop6434 = alloca i1, i1 0
-  %nop6435 = alloca i1, i1 0
-  %nop6436 = alloca i1, i1 0
-  %nop6437 = alloca i1, i1 0
-  %nop6438 = alloca i1, i1 0
-  %nop6439 = alloca i1, i1 0
-  %nop6440 = alloca i1, i1 0
-  %nop6441 = alloca i1, i1 0
-  %nop6442 = alloca i1, i1 0
-  %nop6443 = alloca i1, i1 0
-  %nop6444 = alloca i1, i1 0
-  %nop6445 = alloca i1, i1 0
-  %nop6446 = alloca i1, i1 0
-  %nop6447 = alloca i1, i1 0
-  %nop6448 = alloca i1, i1 0
-  %nop6449 = alloca i1, i1 0
-  %nop6450 = alloca i1, i1 0
-  %nop6451 = alloca i1, i1 0
-  %nop6452 = alloca i1, i1 0
-  %nop6453 = alloca i1, i1 0
-  %nop6454 = alloca i1, i1 0
-  %nop6455 = alloca i1, i1 0
-  %nop6456 = alloca i1, i1 0
-  %nop6457 = alloca i1, i1 0
-  %nop6458 = alloca i1, i1 0
-  %nop6459 = alloca i1, i1 0
-  %nop6460 = alloca i1, i1 0
-  %nop6461 = alloca i1, i1 0
-  %nop6462 = alloca i1, i1 0
-  %nop6463 = alloca i1, i1 0
-  %nop6464 = alloca i1, i1 0
-  %nop6465 = alloca i1, i1 0
-  %nop6466 = alloca i1, i1 0
-  %nop6467 = alloca i1, i1 0
-  %nop6468 = alloca i1, i1 0
-  %nop6469 = alloca i1, i1 0
-  %nop6470 = alloca i1, i1 0
-  %nop6471 = alloca i1, i1 0
-  %nop6472 = alloca i1, i1 0
-  %nop6473 = alloca i1, i1 0
-  %nop6474 = alloca i1, i1 0
-  %nop6475 = alloca i1, i1 0
-  %nop6476 = alloca i1, i1 0
-  %nop6477 = alloca i1, i1 0
-  %nop6478 = alloca i1, i1 0
-  %nop6479 = alloca i1, i1 0
-  %nop6480 = alloca i1, i1 0
-  %nop6481 = alloca i1, i1 0
-  %nop6482 = alloca i1, i1 0
-  %nop6483 = alloca i1, i1 0
-  %nop6484 = alloca i1, i1 0
-  %nop6485 = alloca i1, i1 0
-  %nop6486 = alloca i1, i1 0
-  %nop6487 = alloca i1, i1 0
-  %nop6488 = alloca i1, i1 0
-  %nop6489 = alloca i1, i1 0
-  %nop6490 = alloca i1, i1 0
-  %nop6491 = alloca i1, i1 0
-  %nop6492 = alloca i1, i1 0
-  %nop6493 = alloca i1, i1 0
-  %nop6494 = alloca i1, i1 0
-  %nop6495 = alloca i1, i1 0
-  %nop6496 = alloca i1, i1 0
-  %nop6497 = alloca i1, i1 0
-  %nop6498 = alloca i1, i1 0
-  %nop6499 = alloca i1, i1 0
-  %nop6500 = alloca i1, i1 0
-  %nop6501 = alloca i1, i1 0
-  %nop6502 = alloca i1, i1 0
-  %nop6503 = alloca i1, i1 0
-  %nop6504 = alloca i1, i1 0
-  %nop6505 = alloca i1, i1 0
-  %nop6506 = alloca i1, i1 0
-  %nop6507 = alloca i1, i1 0
-  %nop6508 = alloca i1, i1 0
-  %nop6509 = alloca i1, i1 0
-  %nop6510 = alloca i1, i1 0
-  %nop6511 = alloca i1, i1 0
-  %nop6512 = alloca i1, i1 0
-  %nop6513 = alloca i1, i1 0
-  %nop6514 = alloca i1, i1 0
-  %nop6515 = alloca i1, i1 0
-  %nop6516 = alloca i1, i1 0
-  %nop6517 = alloca i1, i1 0
-  %nop6518 = alloca i1, i1 0
-  %nop6519 = alloca i1, i1 0
-  %nop6520 = alloca i1, i1 0
-  %nop6521 = alloca i1, i1 0
-  %nop6522 = alloca i1, i1 0
-  %nop6523 = alloca i1, i1 0
-  %nop6524 = alloca i1, i1 0
-  %nop6525 = alloca i1, i1 0
-  %nop6526 = alloca i1, i1 0
-  %nop6527 = alloca i1, i1 0
-  %nop6528 = alloca i1, i1 0
-  %nop6529 = alloca i1, i1 0
-  %nop6530 = alloca i1, i1 0
-  %nop6531 = alloca i1, i1 0
-  %nop6532 = alloca i1, i1 0
-  %nop6533 = alloca i1, i1 0
-  %nop6534 = alloca i1, i1 0
-  %nop6535 = alloca i1, i1 0
-  %nop6536 = alloca i1, i1 0
-  %nop6537 = alloca i1, i1 0
-  %nop6538 = alloca i1, i1 0
-  %nop6539 = alloca i1, i1 0
-  %nop6540 = alloca i1, i1 0
-  %nop6541 = alloca i1, i1 0
-  %nop6542 = alloca i1, i1 0
-  %nop6543 = alloca i1, i1 0
-  %nop6544 = alloca i1, i1 0
-  %nop6545 = alloca i1, i1 0
-  %nop6546 = alloca i1, i1 0
-  %nop6547 = alloca i1, i1 0
-  %nop6548 = alloca i1, i1 0
-  %nop6549 = alloca i1, i1 0
-  %nop6550 = alloca i1, i1 0
-  %nop6551 = alloca i1, i1 0
-  %nop6552 = alloca i1, i1 0
-  %nop6553 = alloca i1, i1 0
-  %nop6554 = alloca i1, i1 0
-  %nop6555 = alloca i1, i1 0
-  %nop6556 = alloca i1, i1 0
-  %nop6557 = alloca i1, i1 0
-  %nop6558 = alloca i1, i1 0
-  %nop6559 = alloca i1, i1 0
-  %nop6560 = alloca i1, i1 0
-  %nop6561 = alloca i1, i1 0
-  %nop6562 = alloca i1, i1 0
-  %nop6563 = alloca i1, i1 0
-  %nop6564 = alloca i1, i1 0
-  %nop6565 = alloca i1, i1 0
-  %nop6566 = alloca i1, i1 0
-  %nop6567 = alloca i1, i1 0
-  %nop6568 = alloca i1, i1 0
-  %nop6569 = alloca i1, i1 0
-  %nop6570 = alloca i1, i1 0
-  %nop6571 = alloca i1, i1 0
-  %nop6572 = alloca i1, i1 0
-  %nop6573 = alloca i1, i1 0
-  %nop6574 = alloca i1, i1 0
-  %nop6575 = alloca i1, i1 0
-  %nop6576 = alloca i1, i1 0
-  %nop6577 = alloca i1, i1 0
-  %nop6578 = alloca i1, i1 0
-  %nop6579 = alloca i1, i1 0
-  %nop6580 = alloca i1, i1 0
-  %nop6581 = alloca i1, i1 0
-  %nop6582 = alloca i1, i1 0
-  %nop6583 = alloca i1, i1 0
-  %nop6584 = alloca i1, i1 0
-  %nop6585 = alloca i1, i1 0
-  %nop6586 = alloca i1, i1 0
-  %nop6587 = alloca i1, i1 0
-  %nop6588 = alloca i1, i1 0
-  %nop6589 = alloca i1, i1 0
-  %nop6590 = alloca i1, i1 0
-  %nop6591 = alloca i1, i1 0
-  %nop6592 = alloca i1, i1 0
-  %nop6593 = alloca i1, i1 0
-  %nop6594 = alloca i1, i1 0
-  %nop6595 = alloca i1, i1 0
-  %nop6596 = alloca i1, i1 0
-  %nop6597 = alloca i1, i1 0
-  %nop6598 = alloca i1, i1 0
-  %nop6599 = alloca i1, i1 0
-  %nop6600 = alloca i1, i1 0
-  %nop6601 = alloca i1, i1 0
-  %nop6602 = alloca i1, i1 0
-  %nop6603 = alloca i1, i1 0
-  %nop6604 = alloca i1, i1 0
-  %nop6605 = alloca i1, i1 0
-  %nop6606 = alloca i1, i1 0
-  %nop6607 = alloca i1, i1 0
-  %nop6608 = alloca i1, i1 0
-  %nop6609 = alloca i1, i1 0
-  %nop6610 = alloca i1, i1 0
-  %nop6611 = alloca i1, i1 0
-  %nop6612 = alloca i1, i1 0
-  %nop6613 = alloca i1, i1 0
-  %nop6614 = alloca i1, i1 0
-  %nop6615 = alloca i1, i1 0
-  %nop6616 = alloca i1, i1 0
-  %nop6617 = alloca i1, i1 0
-  %nop6618 = alloca i1, i1 0
-  %nop6619 = alloca i1, i1 0
-  %nop6620 = alloca i1, i1 0
-  %nop6621 = alloca i1, i1 0
-  %nop6622 = alloca i1, i1 0
-  %nop6623 = alloca i1, i1 0
-  %nop6624 = alloca i1, i1 0
-  %nop6625 = alloca i1, i1 0
-  %nop6626 = alloca i1, i1 0
-  %nop6627 = alloca i1, i1 0
-  %nop6628 = alloca i1, i1 0
-  %nop6629 = alloca i1, i1 0
-  %nop6630 = alloca i1, i1 0
-  %nop6631 = alloca i1, i1 0
-  %nop6632 = alloca i1, i1 0
-  %nop6633 = alloca i1, i1 0
-  %nop6634 = alloca i1, i1 0
-  %nop6635 = alloca i1, i1 0
-  %nop6636 = alloca i1, i1 0
-  %nop6637 = alloca i1, i1 0
-  %nop6638 = alloca i1, i1 0
-  %nop6639 = alloca i1, i1 0
-  %nop6640 = alloca i1, i1 0
-  %nop6641 = alloca i1, i1 0
-  %nop6642 = alloca i1, i1 0
-  %nop6643 = alloca i1, i1 0
-  %nop6644 = alloca i1, i1 0
-  %nop6645 = alloca i1, i1 0
-  %nop6646 = alloca i1, i1 0
-  %nop6647 = alloca i1, i1 0
-  %nop6648 = alloca i1, i1 0
-  %nop6649 = alloca i1, i1 0
-  %nop6650 = alloca i1, i1 0
-  %nop6651 = alloca i1, i1 0
-  %nop6652 = alloca i1, i1 0
-  %nop6653 = alloca i1, i1 0
-  %nop6654 = alloca i1, i1 0
-  %nop6655 = alloca i1, i1 0
-  %nop6656 = alloca i1, i1 0
-  %nop6657 = alloca i1, i1 0
-  %nop6658 = alloca i1, i1 0
-  %nop6659 = alloca i1, i1 0
-  %nop6660 = alloca i1, i1 0
-  %nop6661 = alloca i1, i1 0
-  %nop6662 = alloca i1, i1 0
-  %nop6663 = alloca i1, i1 0
-  %nop6664 = alloca i1, i1 0
-  %nop6665 = alloca i1, i1 0
-  %nop6666 = alloca i1, i1 0
-  %nop6667 = alloca i1, i1 0
-  %nop6668 = alloca i1, i1 0
-  %nop6669 = alloca i1, i1 0
-  %nop6670 = alloca i1, i1 0
-  %nop6671 = alloca i1, i1 0
-  %nop6672 = alloca i1, i1 0
-  %nop6673 = alloca i1, i1 0
-  %nop6674 = alloca i1, i1 0
-  %nop6675 = alloca i1, i1 0
-  %nop6676 = alloca i1, i1 0
-  %nop6677 = alloca i1, i1 0
-  %nop6678 = alloca i1, i1 0
-  %nop6679 = alloca i1, i1 0
-  %nop6680 = alloca i1, i1 0
-  %nop6681 = alloca i1, i1 0
-  %nop6682 = alloca i1, i1 0
-  %nop6683 = alloca i1, i1 0
-  %nop6684 = alloca i1, i1 0
-  %nop6685 = alloca i1, i1 0
-  %nop6686 = alloca i1, i1 0
-  %nop6687 = alloca i1, i1 0
-  %nop6688 = alloca i1, i1 0
-  %nop6689 = alloca i1, i1 0
-  %nop6690 = alloca i1, i1 0
-  %nop6691 = alloca i1, i1 0
-  %nop6692 = alloca i1, i1 0
-  %nop6693 = alloca i1, i1 0
-  %nop6694 = alloca i1, i1 0
-  %nop6695 = alloca i1, i1 0
-  %nop6696 = alloca i1, i1 0
-  %nop6697 = alloca i1, i1 0
-  %nop6698 = alloca i1, i1 0
-  %nop6699 = alloca i1, i1 0
-  %nop6700 = alloca i1, i1 0
-  %nop6701 = alloca i1, i1 0
-  %nop6702 = alloca i1, i1 0
-  %nop6703 = alloca i1, i1 0
-  %nop6704 = alloca i1, i1 0
-  %nop6705 = alloca i1, i1 0
-  %nop6706 = alloca i1, i1 0
-  %nop6707 = alloca i1, i1 0
-  %nop6708 = alloca i1, i1 0
-  %nop6709 = alloca i1, i1 0
-  %nop6710 = alloca i1, i1 0
-  %nop6711 = alloca i1, i1 0
-  %nop6712 = alloca i1, i1 0
-  %nop6713 = alloca i1, i1 0
-  %nop6714 = alloca i1, i1 0
-  %nop6715 = alloca i1, i1 0
-  %nop6716 = alloca i1, i1 0
-  %nop6717 = alloca i1, i1 0
-  %nop6718 = alloca i1, i1 0
-  %nop6719 = alloca i1, i1 0
-  %nop6720 = alloca i1, i1 0
-  %nop6721 = alloca i1, i1 0
-  %nop6722 = alloca i1, i1 0
-  %nop6723 = alloca i1, i1 0
-  %nop6724 = alloca i1, i1 0
-  %nop6725 = alloca i1, i1 0
-  %nop6726 = alloca i1, i1 0
-  %nop6727 = alloca i1, i1 0
-  %nop6728 = alloca i1, i1 0
-  %nop6729 = alloca i1, i1 0
-  %nop6730 = alloca i1, i1 0
-  %nop6731 = alloca i1, i1 0
-  %nop6732 = alloca i1, i1 0
-  %nop6733 = alloca i1, i1 0
-  %nop6734 = alloca i1, i1 0
-  %nop6735 = alloca i1, i1 0
-  %nop6736 = alloca i1, i1 0
-  %nop6737 = alloca i1, i1 0
-  %nop6738 = alloca i1, i1 0
-  %nop6739 = alloca i1, i1 0
-  %nop6740 = alloca i1, i1 0
-  %nop6741 = alloca i1, i1 0
-  %nop6742 = alloca i1, i1 0
-  %nop6743 = alloca i1, i1 0
-  %nop6744 = alloca i1, i1 0
-  %nop6745 = alloca i1, i1 0
-  %nop6746 = alloca i1, i1 0
-  %nop6747 = alloca i1, i1 0
-  %nop6748 = alloca i1, i1 0
-  %nop6749 = alloca i1, i1 0
-  %nop6750 = alloca i1, i1 0
-  %nop6751 = alloca i1, i1 0
-  %nop6752 = alloca i1, i1 0
-  %nop6753 = alloca i1, i1 0
-  %nop6754 = alloca i1, i1 0
-  %nop6755 = alloca i1, i1 0
-  %nop6756 = alloca i1, i1 0
-  %nop6757 = alloca i1, i1 0
-  %nop6758 = alloca i1, i1 0
-  %nop6759 = alloca i1, i1 0
-  %nop6760 = alloca i1, i1 0
-  %nop6761 = alloca i1, i1 0
-  %nop6762 = alloca i1, i1 0
-  %nop6763 = alloca i1, i1 0
-  %nop6764 = alloca i1, i1 0
-  %nop6765 = alloca i1, i1 0
-  %nop6766 = alloca i1, i1 0
-  %nop6767 = alloca i1, i1 0
-  %nop6768 = alloca i1, i1 0
-  %nop6769 = alloca i1, i1 0
-  %nop6770 = alloca i1, i1 0
-  %nop6771 = alloca i1, i1 0
-  %nop6772 = alloca i1, i1 0
-  %nop6773 = alloca i1, i1 0
-  %nop6774 = alloca i1, i1 0
-  %nop6775 = alloca i1, i1 0
-  %nop6776 = alloca i1, i1 0
-  %nop6777 = alloca i1, i1 0
-  %nop6778 = alloca i1, i1 0
-  %nop6779 = alloca i1, i1 0
-  %nop6780 = alloca i1, i1 0
-  %nop6781 = alloca i1, i1 0
-  %nop6782 = alloca i1, i1 0
-  %nop6783 = alloca i1, i1 0
-  %nop6784 = alloca i1, i1 0
-  %nop6785 = alloca i1, i1 0
-  %nop6786 = alloca i1, i1 0
-  %nop6787 = alloca i1, i1 0
-  %nop6788 = alloca i1, i1 0
-  %nop6789 = alloca i1, i1 0
-  %nop6790 = alloca i1, i1 0
-  %nop6791 = alloca i1, i1 0
-  %nop6792 = alloca i1, i1 0
-  %nop6793 = alloca i1, i1 0
-  %nop6794 = alloca i1, i1 0
-  %nop6795 = alloca i1, i1 0
-  %nop6796 = alloca i1, i1 0
-  %nop6797 = alloca i1, i1 0
-  %nop6798 = alloca i1, i1 0
-  %nop6799 = alloca i1, i1 0
-  %nop6800 = alloca i1, i1 0
-  %nop6801 = alloca i1, i1 0
-  %nop6802 = alloca i1, i1 0
-  %nop6803 = alloca i1, i1 0
-  %nop6804 = alloca i1, i1 0
-  %nop6805 = alloca i1, i1 0
-  %nop6806 = alloca i1, i1 0
-  %nop6807 = alloca i1, i1 0
-  %nop6808 = alloca i1, i1 0
-  %nop6809 = alloca i1, i1 0
-  %nop6810 = alloca i1, i1 0
-  %nop6811 = alloca i1, i1 0
-  %nop6812 = alloca i1, i1 0
-  %nop6813 = alloca i1, i1 0
-  %nop6814 = alloca i1, i1 0
-  %nop6815 = alloca i1, i1 0
-  %nop6816 = alloca i1, i1 0
-  %nop6817 = alloca i1, i1 0
-  %nop6818 = alloca i1, i1 0
-  %nop6819 = alloca i1, i1 0
-  %nop6820 = alloca i1, i1 0
-  %nop6821 = alloca i1, i1 0
-  %nop6822 = alloca i1, i1 0
-  %nop6823 = alloca i1, i1 0
-  %nop6824 = alloca i1, i1 0
-  %nop6825 = alloca i1, i1 0
-  %nop6826 = alloca i1, i1 0
-  %nop6827 = alloca i1, i1 0
-  %nop6828 = alloca i1, i1 0
-  %nop6829 = alloca i1, i1 0
-  %nop6830 = alloca i1, i1 0
-  %nop6831 = alloca i1, i1 0
-  %nop6832 = alloca i1, i1 0
-  %nop6833 = alloca i1, i1 0
-  %nop6834 = alloca i1, i1 0
-  %nop6835 = alloca i1, i1 0
-  %nop6836 = alloca i1, i1 0
-  %nop6837 = alloca i1, i1 0
-  %nop6838 = alloca i1, i1 0
-  %nop6839 = alloca i1, i1 0
-  %nop6840 = alloca i1, i1 0
-  %nop6841 = alloca i1, i1 0
-  %nop6842 = alloca i1, i1 0
-  %nop6843 = alloca i1, i1 0
-  %nop6844 = alloca i1, i1 0
-  %nop6845 = alloca i1, i1 0
-  %nop6846 = alloca i1, i1 0
-  %nop6847 = alloca i1, i1 0
-  %nop6848 = alloca i1, i1 0
-  %nop6849 = alloca i1, i1 0
-  %nop6850 = alloca i1, i1 0
-  %nop6851 = alloca i1, i1 0
-  %nop6852 = alloca i1, i1 0
-  %nop6853 = alloca i1, i1 0
-  %nop6854 = alloca i1, i1 0
-  %nop6855 = alloca i1, i1 0
-  %nop6856 = alloca i1, i1 0
-  %nop6857 = alloca i1, i1 0
-  %nop6858 = alloca i1, i1 0
-  %nop6859 = alloca i1, i1 0
-  %nop6860 = alloca i1, i1 0
-  %nop6861 = alloca i1, i1 0
-  %nop6862 = alloca i1, i1 0
-  %nop6863 = alloca i1, i1 0
-  %nop6864 = alloca i1, i1 0
-  %nop6865 = alloca i1, i1 0
-  %nop6866 = alloca i1, i1 0
-  %nop6867 = alloca i1, i1 0
-  %nop6868 = alloca i1, i1 0
-  %nop6869 = alloca i1, i1 0
-  %nop6870 = alloca i1, i1 0
-  %nop6871 = alloca i1, i1 0
-  %nop6872 = alloca i1, i1 0
-  %nop6873 = alloca i1, i1 0
-  %nop6874 = alloca i1, i1 0
-  %nop6875 = alloca i1, i1 0
-  %nop6876 = alloca i1, i1 0
-  %nop6877 = alloca i1, i1 0
-  %nop6878 = alloca i1, i1 0
-  %nop6879 = alloca i1, i1 0
-  %nop6880 = alloca i1, i1 0
-  %nop6881 = alloca i1, i1 0
-  %nop6882 = alloca i1, i1 0
-  %nop6883 = alloca i1, i1 0
-  %nop6884 = alloca i1, i1 0
-  %nop6885 = alloca i1, i1 0
-  %nop6886 = alloca i1, i1 0
-  %nop6887 = alloca i1, i1 0
-  %nop6888 = alloca i1, i1 0
-  %nop6889 = alloca i1, i1 0
-  %nop6890 = alloca i1, i1 0
-  %nop6891 = alloca i1, i1 0
-  %nop6892 = alloca i1, i1 0
-  %nop6893 = alloca i1, i1 0
-  %nop6894 = alloca i1, i1 0
-  %nop6895 = alloca i1, i1 0
-  %nop6896 = alloca i1, i1 0
-  %nop6897 = alloca i1, i1 0
-  %nop6898 = alloca i1, i1 0
-  %nop6899 = alloca i1, i1 0
-  %nop6900 = alloca i1, i1 0
-  %nop6901 = alloca i1, i1 0
-  %nop6902 = alloca i1, i1 0
-  %nop6903 = alloca i1, i1 0
-  %nop6904 = alloca i1, i1 0
-  %nop6905 = alloca i1, i1 0
-  %nop6906 = alloca i1, i1 0
-  %nop6907 = alloca i1, i1 0
-  %nop6908 = alloca i1, i1 0
-  %nop6909 = alloca i1, i1 0
-  %nop6910 = alloca i1, i1 0
-  %nop6911 = alloca i1, i1 0
-  %nop6912 = alloca i1, i1 0
-  %nop6913 = alloca i1, i1 0
-  %nop6914 = alloca i1, i1 0
-  %nop6915 = alloca i1, i1 0
-  %nop6916 = alloca i1, i1 0
-  %nop6917 = alloca i1, i1 0
-  %nop6918 = alloca i1, i1 0
-  %nop6919 = alloca i1, i1 0
-  %nop6920 = alloca i1, i1 0
-  %nop6921 = alloca i1, i1 0
-  %nop6922 = alloca i1, i1 0
-  %nop6923 = alloca i1, i1 0
-  %nop6924 = alloca i1, i1 0
-  %nop6925 = alloca i1, i1 0
-  %nop6926 = alloca i1, i1 0
-  %nop6927 = alloca i1, i1 0
-  %nop6928 = alloca i1, i1 0
-  %nop6929 = alloca i1, i1 0
-  %nop6930 = alloca i1, i1 0
-  %nop6931 = alloca i1, i1 0
-  %nop6932 = alloca i1, i1 0
-  %nop6933 = alloca i1, i1 0
-  %nop6934 = alloca i1, i1 0
-  %nop6935 = alloca i1, i1 0
-  %nop6936 = alloca i1, i1 0
-  %nop6937 = alloca i1, i1 0
-  %nop6938 = alloca i1, i1 0
-  %nop6939 = alloca i1, i1 0
-  %nop6940 = alloca i1, i1 0
-  %nop6941 = alloca i1, i1 0
-  %nop6942 = alloca i1, i1 0
-  %nop6943 = alloca i1, i1 0
-  %nop6944 = alloca i1, i1 0
-  %nop6945 = alloca i1, i1 0
-  %nop6946 = alloca i1, i1 0
-  %nop6947 = alloca i1, i1 0
-  %nop6948 = alloca i1, i1 0
-  %nop6949 = alloca i1, i1 0
-  %nop6950 = alloca i1, i1 0
-  %nop6951 = alloca i1, i1 0
-  %nop6952 = alloca i1, i1 0
-  %nop6953 = alloca i1, i1 0
-  %nop6954 = alloca i1, i1 0
-  %nop6955 = alloca i1, i1 0
-  %nop6956 = alloca i1, i1 0
-  %nop6957 = alloca i1, i1 0
-  %nop6958 = alloca i1, i1 0
-  %nop6959 = alloca i1, i1 0
-  %nop6960 = alloca i1, i1 0
-  %nop6961 = alloca i1, i1 0
-  %nop6962 = alloca i1, i1 0
-  %nop6963 = alloca i1, i1 0
-  %nop6964 = alloca i1, i1 0
-  %nop6965 = alloca i1, i1 0
-  %nop6966 = alloca i1, i1 0
-  %nop6967 = alloca i1, i1 0
-  %nop6968 = alloca i1, i1 0
-  %nop6969 = alloca i1, i1 0
-  %nop6970 = alloca i1, i1 0
-  %nop6971 = alloca i1, i1 0
-  %nop6972 = alloca i1, i1 0
-  %nop6973 = alloca i1, i1 0
-  %nop6974 = alloca i1, i1 0
-  %nop6975 = alloca i1, i1 0
-  %nop6976 = alloca i1, i1 0
-  %nop6977 = alloca i1, i1 0
-  %nop6978 = alloca i1, i1 0
-  %nop6979 = alloca i1, i1 0
-  %nop6980 = alloca i1, i1 0
-  %nop6981 = alloca i1, i1 0
-  %nop6982 = alloca i1, i1 0
-  %nop6983 = alloca i1, i1 0
-  %nop6984 = alloca i1, i1 0
-  %nop6985 = alloca i1, i1 0
-  %nop6986 = alloca i1, i1 0
-  %nop6987 = alloca i1, i1 0
-  %nop6988 = alloca i1, i1 0
-  %nop6989 = alloca i1, i1 0
-  %nop6990 = alloca i1, i1 0
-  %nop6991 = alloca i1, i1 0
-  %nop6992 = alloca i1, i1 0
-  %nop6993 = alloca i1, i1 0
-  %nop6994 = alloca i1, i1 0
-  %nop6995 = alloca i1, i1 0
-  %nop6996 = alloca i1, i1 0
-  %nop6997 = alloca i1, i1 0
-  %nop6998 = alloca i1, i1 0
-  %nop6999 = alloca i1, i1 0
-  %nop7000 = alloca i1, i1 0
-  %nop7001 = alloca i1, i1 0
-  %nop7002 = alloca i1, i1 0
-  %nop7003 = alloca i1, i1 0
-  %nop7004 = alloca i1, i1 0
-  %nop7005 = alloca i1, i1 0
-  %nop7006 = alloca i1, i1 0
-  %nop7007 = alloca i1, i1 0
-  %nop7008 = alloca i1, i1 0
-  %nop7009 = alloca i1, i1 0
-  %nop7010 = alloca i1, i1 0
-  %nop7011 = alloca i1, i1 0
-  %nop7012 = alloca i1, i1 0
-  %nop7013 = alloca i1, i1 0
-  %nop7014 = alloca i1, i1 0
-  %nop7015 = alloca i1, i1 0
-  %nop7016 = alloca i1, i1 0
-  %nop7017 = alloca i1, i1 0
-  %nop7018 = alloca i1, i1 0
-  %nop7019 = alloca i1, i1 0
-  %nop7020 = alloca i1, i1 0
-  %nop7021 = alloca i1, i1 0
-  %nop7022 = alloca i1, i1 0
-  %nop7023 = alloca i1, i1 0
-  %nop7024 = alloca i1, i1 0
-  %nop7025 = alloca i1, i1 0
-  %nop7026 = alloca i1, i1 0
-  %nop7027 = alloca i1, i1 0
-  %nop7028 = alloca i1, i1 0
-  %nop7029 = alloca i1, i1 0
-  %nop7030 = alloca i1, i1 0
-  %nop7031 = alloca i1, i1 0
-  %nop7032 = alloca i1, i1 0
-  %nop7033 = alloca i1, i1 0
-  %nop7034 = alloca i1, i1 0
-  %nop7035 = alloca i1, i1 0
-  %nop7036 = alloca i1, i1 0
-  %nop7037 = alloca i1, i1 0
-  %nop7038 = alloca i1, i1 0
-  %nop7039 = alloca i1, i1 0
-  %nop7040 = alloca i1, i1 0
-  %nop7041 = alloca i1, i1 0
-  %nop7042 = alloca i1, i1 0
-  %nop7043 = alloca i1, i1 0
-  %nop7044 = alloca i1, i1 0
-  %nop7045 = alloca i1, i1 0
-  %nop7046 = alloca i1, i1 0
-  %nop7047 = alloca i1, i1 0
-  %nop7048 = alloca i1, i1 0
-  %nop7049 = alloca i1, i1 0
-  %nop7050 = alloca i1, i1 0
-  %nop7051 = alloca i1, i1 0
-  %nop7052 = alloca i1, i1 0
-  %nop7053 = alloca i1, i1 0
-  %nop7054 = alloca i1, i1 0
-  %nop7055 = alloca i1, i1 0
-  %nop7056 = alloca i1, i1 0
-  %nop7057 = alloca i1, i1 0
-  %nop7058 = alloca i1, i1 0
-  %nop7059 = alloca i1, i1 0
-  %nop7060 = alloca i1, i1 0
-  %nop7061 = alloca i1, i1 0
-  %nop7062 = alloca i1, i1 0
-  %nop7063 = alloca i1, i1 0
-  %nop7064 = alloca i1, i1 0
-  %nop7065 = alloca i1, i1 0
-  %nop7066 = alloca i1, i1 0
-  %nop7067 = alloca i1, i1 0
-  %nop7068 = alloca i1, i1 0
-  %nop7069 = alloca i1, i1 0
-  %nop7070 = alloca i1, i1 0
-  %nop7071 = alloca i1, i1 0
-  %nop7072 = alloca i1, i1 0
-  %nop7073 = alloca i1, i1 0
-  %nop7074 = alloca i1, i1 0
-  %nop7075 = alloca i1, i1 0
-  %nop7076 = alloca i1, i1 0
-  %nop7077 = alloca i1, i1 0
-  %nop7078 = alloca i1, i1 0
-  %nop7079 = alloca i1, i1 0
-  %nop7080 = alloca i1, i1 0
-  %nop7081 = alloca i1, i1 0
-  %nop7082 = alloca i1, i1 0
-  %nop7083 = alloca i1, i1 0
-  %nop7084 = alloca i1, i1 0
-  %nop7085 = alloca i1, i1 0
-  %nop7086 = alloca i1, i1 0
-  %nop7087 = alloca i1, i1 0
-  %nop7088 = alloca i1, i1 0
-  %nop7089 = alloca i1, i1 0
-  %nop7090 = alloca i1, i1 0
-  %nop7091 = alloca i1, i1 0
-  %nop7092 = alloca i1, i1 0
-  %nop7093 = alloca i1, i1 0
-  %nop7094 = alloca i1, i1 0
-  %nop7095 = alloca i1, i1 0
-  %nop7096 = alloca i1, i1 0
-  %nop7097 = alloca i1, i1 0
-  %nop7098 = alloca i1, i1 0
-  %nop7099 = alloca i1, i1 0
-  %nop7100 = alloca i1, i1 0
-  %nop7101 = alloca i1, i1 0
-  %nop7102 = alloca i1, i1 0
-  %nop7103 = alloca i1, i1 0
-  %nop7104 = alloca i1, i1 0
-  %nop7105 = alloca i1, i1 0
-  %nop7106 = alloca i1, i1 0
-  %nop7107 = alloca i1, i1 0
-  %nop7108 = alloca i1, i1 0
-  %nop7109 = alloca i1, i1 0
-  %nop7110 = alloca i1, i1 0
-  %nop7111 = alloca i1, i1 0
-  %nop7112 = alloca i1, i1 0
-  %nop7113 = alloca i1, i1 0
-  %nop7114 = alloca i1, i1 0
-  %nop7115 = alloca i1, i1 0
-  %nop7116 = alloca i1, i1 0
-  %nop7117 = alloca i1, i1 0
-  %nop7118 = alloca i1, i1 0
-  %nop7119 = alloca i1, i1 0
-  %nop7120 = alloca i1, i1 0
-  %nop7121 = alloca i1, i1 0
-  %nop7122 = alloca i1, i1 0
-  %nop7123 = alloca i1, i1 0
-  %nop7124 = alloca i1, i1 0
-  %nop7125 = alloca i1, i1 0
-  %nop7126 = alloca i1, i1 0
-  %nop7127 = alloca i1, i1 0
-  %nop7128 = alloca i1, i1 0
-  %nop7129 = alloca i1, i1 0
-  %nop7130 = alloca i1, i1 0
-  %nop7131 = alloca i1, i1 0
-  %nop7132 = alloca i1, i1 0
-  %nop7133 = alloca i1, i1 0
-  %nop7134 = alloca i1, i1 0
-  %nop7135 = alloca i1, i1 0
-  %nop7136 = alloca i1, i1 0
-  %nop7137 = alloca i1, i1 0
-  %nop7138 = alloca i1, i1 0
-  %nop7139 = alloca i1, i1 0
-  %nop7140 = alloca i1, i1 0
-  %nop7141 = alloca i1, i1 0
-  %nop7142 = alloca i1, i1 0
-  %nop7143 = alloca i1, i1 0
-  %nop7144 = alloca i1, i1 0
-  %nop7145 = alloca i1, i1 0
-  %nop7146 = alloca i1, i1 0
-  %nop7147 = alloca i1, i1 0
-  %nop7148 = alloca i1, i1 0
-  %nop7149 = alloca i1, i1 0
-  %nop7150 = alloca i1, i1 0
-  %nop7151 = alloca i1, i1 0
-  %nop7152 = alloca i1, i1 0
-  %nop7153 = alloca i1, i1 0
-  %nop7154 = alloca i1, i1 0
-  %nop7155 = alloca i1, i1 0
-  %nop7156 = alloca i1, i1 0
-  %nop7157 = alloca i1, i1 0
-  %nop7158 = alloca i1, i1 0
-  %nop7159 = alloca i1, i1 0
-  %nop7160 = alloca i1, i1 0
-  %nop7161 = alloca i1, i1 0
-  %nop7162 = alloca i1, i1 0
-  %nop7163 = alloca i1, i1 0
-  %nop7164 = alloca i1, i1 0
-  %nop7165 = alloca i1, i1 0
-  %nop7166 = alloca i1, i1 0
-  %nop7167 = alloca i1, i1 0
-  %nop7168 = alloca i1, i1 0
-  %nop7169 = alloca i1, i1 0
-  %nop7170 = alloca i1, i1 0
-  %nop7171 = alloca i1, i1 0
-  %nop7172 = alloca i1, i1 0
-  %nop7173 = alloca i1, i1 0
-  %nop7174 = alloca i1, i1 0
-  %nop7175 = alloca i1, i1 0
-  %nop7176 = alloca i1, i1 0
-  %nop7177 = alloca i1, i1 0
-  %nop7178 = alloca i1, i1 0
-  %nop7179 = alloca i1, i1 0
-  %nop7180 = alloca i1, i1 0
-  %nop7181 = alloca i1, i1 0
-  %nop7182 = alloca i1, i1 0
-  %nop7183 = alloca i1, i1 0
-  %nop7184 = alloca i1, i1 0
-  %nop7185 = alloca i1, i1 0
-  %nop7186 = alloca i1, i1 0
-  %nop7187 = alloca i1, i1 0
-  %nop7188 = alloca i1, i1 0
-  %nop7189 = alloca i1, i1 0
-  %nop7190 = alloca i1, i1 0
-  %nop7191 = alloca i1, i1 0
-  %nop7192 = alloca i1, i1 0
-  %nop7193 = alloca i1, i1 0
-  %nop7194 = alloca i1, i1 0
-  %nop7195 = alloca i1, i1 0
-  %nop7196 = alloca i1, i1 0
-  %nop7197 = alloca i1, i1 0
-  %nop7198 = alloca i1, i1 0
-  %nop7199 = alloca i1, i1 0
-  %nop7200 = alloca i1, i1 0
-  %nop7201 = alloca i1, i1 0
-  %nop7202 = alloca i1, i1 0
-  %nop7203 = alloca i1, i1 0
-  %nop7204 = alloca i1, i1 0
-  %nop7205 = alloca i1, i1 0
-  %nop7206 = alloca i1, i1 0
-  %nop7207 = alloca i1, i1 0
-  %nop7208 = alloca i1, i1 0
-  %nop7209 = alloca i1, i1 0
-  %nop7210 = alloca i1, i1 0
-  %nop7211 = alloca i1, i1 0
-  %nop7212 = alloca i1, i1 0
-  %nop7213 = alloca i1, i1 0
-  %nop7214 = alloca i1, i1 0
-  %nop7215 = alloca i1, i1 0
-  %nop7216 = alloca i1, i1 0
-  %nop7217 = alloca i1, i1 0
-  %nop7218 = alloca i1, i1 0
-  %nop7219 = alloca i1, i1 0
-  %nop7220 = alloca i1, i1 0
-  %nop7221 = alloca i1, i1 0
-  %nop7222 = alloca i1, i1 0
-  %nop7223 = alloca i1, i1 0
-  %nop7224 = alloca i1, i1 0
-  %nop7225 = alloca i1, i1 0
-  %nop7226 = alloca i1, i1 0
-  %nop7227 = alloca i1, i1 0
-  %nop7228 = alloca i1, i1 0
-  %nop7229 = alloca i1, i1 0
-  %nop7230 = alloca i1, i1 0
-  %nop7231 = alloca i1, i1 0
-  %nop7232 = alloca i1, i1 0
-  %nop7233 = alloca i1, i1 0
-  %nop7234 = alloca i1, i1 0
-  %nop7235 = alloca i1, i1 0
-  %nop7236 = alloca i1, i1 0
-  %nop7237 = alloca i1, i1 0
-  %nop7238 = alloca i1, i1 0
-  %nop7239 = alloca i1, i1 0
-  %nop7240 = alloca i1, i1 0
-  %nop7241 = alloca i1, i1 0
-  %nop7242 = alloca i1, i1 0
-  %nop7243 = alloca i1, i1 0
-  %nop7244 = alloca i1, i1 0
-  %nop7245 = alloca i1, i1 0
-  %nop7246 = alloca i1, i1 0
-  %nop7247 = alloca i1, i1 0
-  %nop7248 = alloca i1, i1 0
-  %nop7249 = alloca i1, i1 0
-  %nop7250 = alloca i1, i1 0
-  %nop7251 = alloca i1, i1 0
-  %nop7252 = alloca i1, i1 0
-  %nop7253 = alloca i1, i1 0
-  %nop7254 = alloca i1, i1 0
-  %nop7255 = alloca i1, i1 0
-  %nop7256 = alloca i1, i1 0
-  %nop7257 = alloca i1, i1 0
-  %nop7258 = alloca i1, i1 0
-  %nop7259 = alloca i1, i1 0
-  %nop7260 = alloca i1, i1 0
-  %nop7261 = alloca i1, i1 0
-  %nop7262 = alloca i1, i1 0
-  %nop7263 = alloca i1, i1 0
-  %nop7264 = alloca i1, i1 0
-  %nop7265 = alloca i1, i1 0
-  %nop7266 = alloca i1, i1 0
-  %nop7267 = alloca i1, i1 0
-  %nop7268 = alloca i1, i1 0
-  %nop7269 = alloca i1, i1 0
-  %nop7270 = alloca i1, i1 0
-  %nop7271 = alloca i1, i1 0
-  %nop7272 = alloca i1, i1 0
-  %nop7273 = alloca i1, i1 0
-  %nop7274 = alloca i1, i1 0
-  %nop7275 = alloca i1, i1 0
-  %nop7276 = alloca i1, i1 0
-  %nop7277 = alloca i1, i1 0
-  %nop7278 = alloca i1, i1 0
-  %nop7279 = alloca i1, i1 0
-  %nop7280 = alloca i1, i1 0
-  %nop7281 = alloca i1, i1 0
-  %nop7282 = alloca i1, i1 0
-  %nop7283 = alloca i1, i1 0
-  %nop7284 = alloca i1, i1 0
-  %nop7285 = alloca i1, i1 0
-  %nop7286 = alloca i1, i1 0
-  %nop7287 = alloca i1, i1 0
-  %nop7288 = alloca i1, i1 0
-  %nop7289 = alloca i1, i1 0
-  %nop7290 = alloca i1, i1 0
-  %nop7291 = alloca i1, i1 0
-  %nop7292 = alloca i1, i1 0
-  %nop7293 = alloca i1, i1 0
-  %nop7294 = alloca i1, i1 0
-  %nop7295 = alloca i1, i1 0
-  %nop7296 = alloca i1, i1 0
-  %nop7297 = alloca i1, i1 0
-  %nop7298 = alloca i1, i1 0
-  %nop7299 = alloca i1, i1 0
-  %nop7300 = alloca i1, i1 0
-  %nop7301 = alloca i1, i1 0
-  %nop7302 = alloca i1, i1 0
-  %nop7303 = alloca i1, i1 0
-  %nop7304 = alloca i1, i1 0
-  %nop7305 = alloca i1, i1 0
-  %nop7306 = alloca i1, i1 0
-  %nop7307 = alloca i1, i1 0
-  %nop7308 = alloca i1, i1 0
-  %nop7309 = alloca i1, i1 0
-  %nop7310 = alloca i1, i1 0
-  %nop7311 = alloca i1, i1 0
-  %nop7312 = alloca i1, i1 0
-  %nop7313 = alloca i1, i1 0
-  %nop7314 = alloca i1, i1 0
-  %nop7315 = alloca i1, i1 0
-  %nop7316 = alloca i1, i1 0
-  %nop7317 = alloca i1, i1 0
-  %nop7318 = alloca i1, i1 0
-  %nop7319 = alloca i1, i1 0
-  %nop7320 = alloca i1, i1 0
-  %nop7321 = alloca i1, i1 0
-  %nop7322 = alloca i1, i1 0
-  %nop7323 = alloca i1, i1 0
-  %nop7324 = alloca i1, i1 0
-  %nop7325 = alloca i1, i1 0
-  %nop7326 = alloca i1, i1 0
-  %nop7327 = alloca i1, i1 0
-  %nop7328 = alloca i1, i1 0
-  %nop7329 = alloca i1, i1 0
-  %nop7330 = alloca i1, i1 0
-  %nop7331 = alloca i1, i1 0
-  %nop7332 = alloca i1, i1 0
-  %nop7333 = alloca i1, i1 0
-  %nop7334 = alloca i1, i1 0
-  %nop7335 = alloca i1, i1 0
-  %nop7336 = alloca i1, i1 0
-  %nop7337 = alloca i1, i1 0
-  %nop7338 = alloca i1, i1 0
-  %nop7339 = alloca i1, i1 0
-  %nop7340 = alloca i1, i1 0
-  %nop7341 = alloca i1, i1 0
-  %nop7342 = alloca i1, i1 0
-  %nop7343 = alloca i1, i1 0
-  %nop7344 = alloca i1, i1 0
-  %nop7345 = alloca i1, i1 0
-  %nop7346 = alloca i1, i1 0
-  %nop7347 = alloca i1, i1 0
-  %nop7348 = alloca i1, i1 0
-  %nop7349 = alloca i1, i1 0
-  %nop7350 = alloca i1, i1 0
-  %nop7351 = alloca i1, i1 0
-  %nop7352 = alloca i1, i1 0
-  %nop7353 = alloca i1, i1 0
-  %nop7354 = alloca i1, i1 0
-  %nop7355 = alloca i1, i1 0
-  %nop7356 = alloca i1, i1 0
-  %nop7357 = alloca i1, i1 0
-  %nop7358 = alloca i1, i1 0
-  %nop7359 = alloca i1, i1 0
-  %nop7360 = alloca i1, i1 0
-  %nop7361 = alloca i1, i1 0
-  %nop7362 = alloca i1, i1 0
-  %nop7363 = alloca i1, i1 0
-  %nop7364 = alloca i1, i1 0
-  %nop7365 = alloca i1, i1 0
-  %nop7366 = alloca i1, i1 0
-  %nop7367 = alloca i1, i1 0
-  %nop7368 = alloca i1, i1 0
-  %nop7369 = alloca i1, i1 0
-  %nop7370 = alloca i1, i1 0
-  %nop7371 = alloca i1, i1 0
-  %nop7372 = alloca i1, i1 0
-  %nop7373 = alloca i1, i1 0
-  %nop7374 = alloca i1, i1 0
-  %nop7375 = alloca i1, i1 0
-  %nop7376 = alloca i1, i1 0
-  %nop7377 = alloca i1, i1 0
-  %nop7378 = alloca i1, i1 0
-  %nop7379 = alloca i1, i1 0
-  %nop7380 = alloca i1, i1 0
-  %nop7381 = alloca i1, i1 0
-  %nop7382 = alloca i1, i1 0
-  %nop7383 = alloca i1, i1 0
-  %nop7384 = alloca i1, i1 0
-  %nop7385 = alloca i1, i1 0
-  %nop7386 = alloca i1, i1 0
-  %nop7387 = alloca i1, i1 0
-  %nop7388 = alloca i1, i1 0
-  %nop7389 = alloca i1, i1 0
-  %nop7390 = alloca i1, i1 0
-  %nop7391 = alloca i1, i1 0
-  %nop7392 = alloca i1, i1 0
-  %nop7393 = alloca i1, i1 0
-  %nop7394 = alloca i1, i1 0
-  %nop7395 = alloca i1, i1 0
-  %nop7396 = alloca i1, i1 0
-  %nop7397 = alloca i1, i1 0
-  %nop7398 = alloca i1, i1 0
-  %nop7399 = alloca i1, i1 0
-  %nop7400 = alloca i1, i1 0
-  %nop7401 = alloca i1, i1 0
-  %nop7402 = alloca i1, i1 0
-  %nop7403 = alloca i1, i1 0
-  %nop7404 = alloca i1, i1 0
-  %nop7405 = alloca i1, i1 0
-  %nop7406 = alloca i1, i1 0
-  %nop7407 = alloca i1, i1 0
-  %nop7408 = alloca i1, i1 0
-  %nop7409 = alloca i1, i1 0
-  %nop7410 = alloca i1, i1 0
-  %nop7411 = alloca i1, i1 0
-  %nop7412 = alloca i1, i1 0
-  %nop7413 = alloca i1, i1 0
-  %nop7414 = alloca i1, i1 0
-  %nop7415 = alloca i1, i1 0
-  %nop7416 = alloca i1, i1 0
-  %nop7417 = alloca i1, i1 0
-  %nop7418 = alloca i1, i1 0
-  %nop7419 = alloca i1, i1 0
-  %nop7420 = alloca i1, i1 0
-  %nop7421 = alloca i1, i1 0
-  %nop7422 = alloca i1, i1 0
-  %nop7423 = alloca i1, i1 0
-  %nop7424 = alloca i1, i1 0
-  %nop7425 = alloca i1, i1 0
-  %nop7426 = alloca i1, i1 0
-  %nop7427 = alloca i1, i1 0
-  %nop7428 = alloca i1, i1 0
-  %nop7429 = alloca i1, i1 0
-  %nop7430 = alloca i1, i1 0
-  %nop7431 = alloca i1, i1 0
-  %nop7432 = alloca i1, i1 0
-  %nop7433 = alloca i1, i1 0
-  %nop7434 = alloca i1, i1 0
-  %nop7435 = alloca i1, i1 0
-  %nop7436 = alloca i1, i1 0
-  %nop7437 = alloca i1, i1 0
-  %nop7438 = alloca i1, i1 0
-  %nop7439 = alloca i1, i1 0
-  %nop7440 = alloca i1, i1 0
-  %nop7441 = alloca i1, i1 0
-  %nop7442 = alloca i1, i1 0
-  %nop7443 = alloca i1, i1 0
-  %nop7444 = alloca i1, i1 0
-  %nop7445 = alloca i1, i1 0
-  %nop7446 = alloca i1, i1 0
-  %nop7447 = alloca i1, i1 0
-  %nop7448 = alloca i1, i1 0
-  %nop7449 = alloca i1, i1 0
-  %nop7450 = alloca i1, i1 0
-  %nop7451 = alloca i1, i1 0
-  %nop7452 = alloca i1, i1 0
-  %nop7453 = alloca i1, i1 0
-  %nop7454 = alloca i1, i1 0
-  %nop7455 = alloca i1, i1 0
-  %nop7456 = alloca i1, i1 0
-  %nop7457 = alloca i1, i1 0
-  %nop7458 = alloca i1, i1 0
-  %nop7459 = alloca i1, i1 0
-  %nop7460 = alloca i1, i1 0
-  %nop7461 = alloca i1, i1 0
-  %nop7462 = alloca i1, i1 0
-  %nop7463 = alloca i1, i1 0
-  %nop7464 = alloca i1, i1 0
-  %nop7465 = alloca i1, i1 0
-  %nop7466 = alloca i1, i1 0
-  %nop7467 = alloca i1, i1 0
-  %nop7468 = alloca i1, i1 0
-  %nop7469 = alloca i1, i1 0
-  %nop7470 = alloca i1, i1 0
-  %nop7471 = alloca i1, i1 0
-  %nop7472 = alloca i1, i1 0
-  %nop7473 = alloca i1, i1 0
-  %nop7474 = alloca i1, i1 0
-  %nop7475 = alloca i1, i1 0
-  %nop7476 = alloca i1, i1 0
-  %nop7477 = alloca i1, i1 0
-  %nop7478 = alloca i1, i1 0
-  %nop7479 = alloca i1, i1 0
-  %nop7480 = alloca i1, i1 0
-  %nop7481 = alloca i1, i1 0
-  %nop7482 = alloca i1, i1 0
-  %nop7483 = alloca i1, i1 0
-  %nop7484 = alloca i1, i1 0
-  %nop7485 = alloca i1, i1 0
-  %nop7486 = alloca i1, i1 0
-  %nop7487 = alloca i1, i1 0
-  %nop7488 = alloca i1, i1 0
-  %nop7489 = alloca i1, i1 0
-  %nop7490 = alloca i1, i1 0
-  %nop7491 = alloca i1, i1 0
-  %nop7492 = alloca i1, i1 0
-  %nop7493 = alloca i1, i1 0
-  %nop7494 = alloca i1, i1 0
-  %nop7495 = alloca i1, i1 0
-  %nop7496 = alloca i1, i1 0
-  %nop7497 = alloca i1, i1 0
-  %nop7498 = alloca i1, i1 0
-  %nop7499 = alloca i1, i1 0
-  %nop7500 = alloca i1, i1 0
-  %nop7501 = alloca i1, i1 0
-  %nop7502 = alloca i1, i1 0
-  %nop7503 = alloca i1, i1 0
-  %nop7504 = alloca i1, i1 0
-  %nop7505 = alloca i1, i1 0
-  %nop7506 = alloca i1, i1 0
-  %nop7507 = alloca i1, i1 0
-  %nop7508 = alloca i1, i1 0
-  %nop7509 = alloca i1, i1 0
-  %nop7510 = alloca i1, i1 0
-  %nop7511 = alloca i1, i1 0
-  %nop7512 = alloca i1, i1 0
-  %nop7513 = alloca i1, i1 0
-  %nop7514 = alloca i1, i1 0
-  %nop7515 = alloca i1, i1 0
-  %nop7516 = alloca i1, i1 0
-  %nop7517 = alloca i1, i1 0
-  %nop7518 = alloca i1, i1 0
-  %nop7519 = alloca i1, i1 0
-  %nop7520 = alloca i1, i1 0
-  %nop7521 = alloca i1, i1 0
-  %nop7522 = alloca i1, i1 0
-  %nop7523 = alloca i1, i1 0
-  %nop7524 = alloca i1, i1 0
-  %nop7525 = alloca i1, i1 0
-  %nop7526 = alloca i1, i1 0
-  %nop7527 = alloca i1, i1 0
-  %nop7528 = alloca i1, i1 0
-  %nop7529 = alloca i1, i1 0
-  %nop7530 = alloca i1, i1 0
-  %nop7531 = alloca i1, i1 0
-  %nop7532 = alloca i1, i1 0
-  %nop7533 = alloca i1, i1 0
-  %nop7534 = alloca i1, i1 0
-  %nop7535 = alloca i1, i1 0
-  %nop7536 = alloca i1, i1 0
-  %nop7537 = alloca i1, i1 0
-  %nop7538 = alloca i1, i1 0
-  %nop7539 = alloca i1, i1 0
-  %nop7540 = alloca i1, i1 0
-  %nop7541 = alloca i1, i1 0
-  %nop7542 = alloca i1, i1 0
-  %nop7543 = alloca i1, i1 0
-  %nop7544 = alloca i1, i1 0
-  %nop7545 = alloca i1, i1 0
-  %nop7546 = alloca i1, i1 0
-  %nop7547 = alloca i1, i1 0
-  %nop7548 = alloca i1, i1 0
-  %nop7549 = alloca i1, i1 0
-  %nop7550 = alloca i1, i1 0
-  %nop7551 = alloca i1, i1 0
-  %nop7552 = alloca i1, i1 0
-  %nop7553 = alloca i1, i1 0
-  %nop7554 = alloca i1, i1 0
-  %nop7555 = alloca i1, i1 0
-  %nop7556 = alloca i1, i1 0
-  %nop7557 = alloca i1, i1 0
-  %nop7558 = alloca i1, i1 0
-  %nop7559 = alloca i1, i1 0
-  %nop7560 = alloca i1, i1 0
-  %nop7561 = alloca i1, i1 0
-  %nop7562 = alloca i1, i1 0
-  %nop7563 = alloca i1, i1 0
-  %nop7564 = alloca i1, i1 0
-  %nop7565 = alloca i1, i1 0
-  %nop7566 = alloca i1, i1 0
-  %nop7567 = alloca i1, i1 0
-  %nop7568 = alloca i1, i1 0
-  %nop7569 = alloca i1, i1 0
-  %nop7570 = alloca i1, i1 0
-  %nop7571 = alloca i1, i1 0
-  %nop7572 = alloca i1, i1 0
-  %nop7573 = alloca i1, i1 0
-  %nop7574 = alloca i1, i1 0
-  %nop7575 = alloca i1, i1 0
-  %nop7576 = alloca i1, i1 0
-  %nop7577 = alloca i1, i1 0
-  %nop7578 = alloca i1, i1 0
-  %nop7579 = alloca i1, i1 0
-  %nop7580 = alloca i1, i1 0
-  %nop7581 = alloca i1, i1 0
-  %nop7582 = alloca i1, i1 0
-  %nop7583 = alloca i1, i1 0
-  %nop7584 = alloca i1, i1 0
-  %nop7585 = alloca i1, i1 0
-  %nop7586 = alloca i1, i1 0
-  %nop7587 = alloca i1, i1 0
-  %nop7588 = alloca i1, i1 0
-  %nop7589 = alloca i1, i1 0
-  %nop7590 = alloca i1, i1 0
-  %nop7591 = alloca i1, i1 0
-  %nop7592 = alloca i1, i1 0
-  %nop7593 = alloca i1, i1 0
-  %nop7594 = alloca i1, i1 0
-  %nop7595 = alloca i1, i1 0
-  %nop7596 = alloca i1, i1 0
-  %nop7597 = alloca i1, i1 0
-  %nop7598 = alloca i1, i1 0
-  %nop7599 = alloca i1, i1 0
-  %nop7600 = alloca i1, i1 0
-  %nop7601 = alloca i1, i1 0
-  %nop7602 = alloca i1, i1 0
-  %nop7603 = alloca i1, i1 0
-  %nop7604 = alloca i1, i1 0
-  %nop7605 = alloca i1, i1 0
-  %nop7606 = alloca i1, i1 0
-  %nop7607 = alloca i1, i1 0
-  %nop7608 = alloca i1, i1 0
-  %nop7609 = alloca i1, i1 0
-  %nop7610 = alloca i1, i1 0
-  %nop7611 = alloca i1, i1 0
-  %nop7612 = alloca i1, i1 0
-  %nop7613 = alloca i1, i1 0
-  %nop7614 = alloca i1, i1 0
-  %nop7615 = alloca i1, i1 0
-  %nop7616 = alloca i1, i1 0
-  %nop7617 = alloca i1, i1 0
-  %nop7618 = alloca i1, i1 0
-  %nop7619 = alloca i1, i1 0
-  %nop7620 = alloca i1, i1 0
-  %nop7621 = alloca i1, i1 0
-  %nop7622 = alloca i1, i1 0
-  %nop7623 = alloca i1, i1 0
-  %nop7624 = alloca i1, i1 0
-  %nop7625 = alloca i1, i1 0
-  %nop7626 = alloca i1, i1 0
-  %nop7627 = alloca i1, i1 0
-  %nop7628 = alloca i1, i1 0
-  %nop7629 = alloca i1, i1 0
-  %nop7630 = alloca i1, i1 0
-  %nop7631 = alloca i1, i1 0
-  %nop7632 = alloca i1, i1 0
-  %nop7633 = alloca i1, i1 0
-  %nop7634 = alloca i1, i1 0
-  %nop7635 = alloca i1, i1 0
-  %nop7636 = alloca i1, i1 0
-  %nop7637 = alloca i1, i1 0
-  %nop7638 = alloca i1, i1 0
-  %nop7639 = alloca i1, i1 0
-  %nop7640 = alloca i1, i1 0
-  %nop7641 = alloca i1, i1 0
-  %nop7642 = alloca i1, i1 0
-  %nop7643 = alloca i1, i1 0
-  %nop7644 = alloca i1, i1 0
-  %nop7645 = alloca i1, i1 0
-  %nop7646 = alloca i1, i1 0
-  %nop7647 = alloca i1, i1 0
-  %nop7648 = alloca i1, i1 0
-  %nop7649 = alloca i1, i1 0
-  %nop7650 = alloca i1, i1 0
-  %nop7651 = alloca i1, i1 0
-  %nop7652 = alloca i1, i1 0
-  %nop7653 = alloca i1, i1 0
-  %nop7654 = alloca i1, i1 0
-  %nop7655 = alloca i1, i1 0
-  %nop7656 = alloca i1, i1 0
-  %nop7657 = alloca i1, i1 0
-  %nop7658 = alloca i1, i1 0
-  %nop7659 = alloca i1, i1 0
-  %nop7660 = alloca i1, i1 0
-  %nop7661 = alloca i1, i1 0
-  %nop7662 = alloca i1, i1 0
-  %nop7663 = alloca i1, i1 0
-  %nop7664 = alloca i1, i1 0
-  %nop7665 = alloca i1, i1 0
-  %nop7666 = alloca i1, i1 0
-  %nop7667 = alloca i1, i1 0
-  %nop7668 = alloca i1, i1 0
-  %nop7669 = alloca i1, i1 0
-  %nop7670 = alloca i1, i1 0
-  %nop7671 = alloca i1, i1 0
-  %nop7672 = alloca i1, i1 0
-  %nop7673 = alloca i1, i1 0
-  %nop7674 = alloca i1, i1 0
-  %nop7675 = alloca i1, i1 0
-  %nop7676 = alloca i1, i1 0
-  %nop7677 = alloca i1, i1 0
-  %nop7678 = alloca i1, i1 0
-  %nop7679 = alloca i1, i1 0
-  %nop7680 = alloca i1, i1 0
-  %nop7681 = alloca i1, i1 0
-  %nop7682 = alloca i1, i1 0
-  %nop7683 = alloca i1, i1 0
-  %nop7684 = alloca i1, i1 0
-  %nop7685 = alloca i1, i1 0
-  %nop7686 = alloca i1, i1 0
-  %nop7687 = alloca i1, i1 0
-  %nop7688 = alloca i1, i1 0
-  %nop7689 = alloca i1, i1 0
-  %nop7690 = alloca i1, i1 0
-  %nop7691 = alloca i1, i1 0
-  %nop7692 = alloca i1, i1 0
-  %nop7693 = alloca i1, i1 0
-  %nop7694 = alloca i1, i1 0
-  %nop7695 = alloca i1, i1 0
-  %nop7696 = alloca i1, i1 0
-  %nop7697 = alloca i1, i1 0
-  %nop7698 = alloca i1, i1 0
-  %nop7699 = alloca i1, i1 0
-  %nop7700 = alloca i1, i1 0
-  %nop7701 = alloca i1, i1 0
-  %nop7702 = alloca i1, i1 0
-  %nop7703 = alloca i1, i1 0
-  %nop7704 = alloca i1, i1 0
-  %nop7705 = alloca i1, i1 0
-  %nop7706 = alloca i1, i1 0
-  %nop7707 = alloca i1, i1 0
-  %nop7708 = alloca i1, i1 0
-  %nop7709 = alloca i1, i1 0
-  %nop7710 = alloca i1, i1 0
-  %nop7711 = alloca i1, i1 0
-  %nop7712 = alloca i1, i1 0
-  %nop7713 = alloca i1, i1 0
-  %nop7714 = alloca i1, i1 0
-  %nop7715 = alloca i1, i1 0
-  %nop7716 = alloca i1, i1 0
-  %nop7717 = alloca i1, i1 0
-  %nop7718 = alloca i1, i1 0
-  %nop7719 = alloca i1, i1 0
-  %nop7720 = alloca i1, i1 0
-  %nop7721 = alloca i1, i1 0
-  %nop7722 = alloca i1, i1 0
-  %nop7723 = alloca i1, i1 0
-  %nop7724 = alloca i1, i1 0
-  %nop7725 = alloca i1, i1 0
-  %nop7726 = alloca i1, i1 0
-  %nop7727 = alloca i1, i1 0
-  %nop7728 = alloca i1, i1 0
-  %nop7729 = alloca i1, i1 0
-  %nop7730 = alloca i1, i1 0
-  %nop7731 = alloca i1, i1 0
-  %nop7732 = alloca i1, i1 0
-  %nop7733 = alloca i1, i1 0
-  %nop7734 = alloca i1, i1 0
-  %nop7735 = alloca i1, i1 0
-  %nop7736 = alloca i1, i1 0
-  %nop7737 = alloca i1, i1 0
-  %nop7738 = alloca i1, i1 0
-  %nop7739 = alloca i1, i1 0
-  %nop7740 = alloca i1, i1 0
-  %nop7741 = alloca i1, i1 0
-  %nop7742 = alloca i1, i1 0
-  %nop7743 = alloca i1, i1 0
-  %nop7744 = alloca i1, i1 0
-  %nop7745 = alloca i1, i1 0
-  %nop7746 = alloca i1, i1 0
-  %nop7747 = alloca i1, i1 0
-  %nop7748 = alloca i1, i1 0
-  %nop7749 = alloca i1, i1 0
-  %nop7750 = alloca i1, i1 0
-  %nop7751 = alloca i1, i1 0
-  %nop7752 = alloca i1, i1 0
-  %nop7753 = alloca i1, i1 0
-  %nop7754 = alloca i1, i1 0
-  %nop7755 = alloca i1, i1 0
-  %nop7756 = alloca i1, i1 0
-  %nop7757 = alloca i1, i1 0
-  %nop7758 = alloca i1, i1 0
-  %nop7759 = alloca i1, i1 0
-  %nop7760 = alloca i1, i1 0
-  %nop7761 = alloca i1, i1 0
-  %nop7762 = alloca i1, i1 0
-  %nop7763 = alloca i1, i1 0
-  %nop7764 = alloca i1, i1 0
-  %nop7765 = alloca i1, i1 0
-  %nop7766 = alloca i1, i1 0
-  %nop7767 = alloca i1, i1 0
-  %nop7768 = alloca i1, i1 0
-  %nop7769 = alloca i1, i1 0
-  %nop7770 = alloca i1, i1 0
-  %nop7771 = alloca i1, i1 0
-  %nop7772 = alloca i1, i1 0
-  %nop7773 = alloca i1, i1 0
-  %nop7774 = alloca i1, i1 0
-  %nop7775 = alloca i1, i1 0
-  %nop7776 = alloca i1, i1 0
-  %nop7777 = alloca i1, i1 0
-  %nop7778 = alloca i1, i1 0
-  %nop7779 = alloca i1, i1 0
-  %nop7780 = alloca i1, i1 0
-  %nop7781 = alloca i1, i1 0
-  %nop7782 = alloca i1, i1 0
-  %nop7783 = alloca i1, i1 0
-  %nop7784 = alloca i1, i1 0
-  %nop7785 = alloca i1, i1 0
-  %nop7786 = alloca i1, i1 0
-  %nop7787 = alloca i1, i1 0
-  %nop7788 = alloca i1, i1 0
-  %nop7789 = alloca i1, i1 0
-  %nop7790 = alloca i1, i1 0
-  %nop7791 = alloca i1, i1 0
-  %nop7792 = alloca i1, i1 0
-  %nop7793 = alloca i1, i1 0
-  %nop7794 = alloca i1, i1 0
-  %nop7795 = alloca i1, i1 0
-  %nop7796 = alloca i1, i1 0
-  %nop7797 = alloca i1, i1 0
-  %nop7798 = alloca i1, i1 0
-  %nop7799 = alloca i1, i1 0
-  %nop7800 = alloca i1, i1 0
-  %nop7801 = alloca i1, i1 0
-  %nop7802 = alloca i1, i1 0
-  %nop7803 = alloca i1, i1 0
-  %nop7804 = alloca i1, i1 0
-  %nop7805 = alloca i1, i1 0
-  %nop7806 = alloca i1, i1 0
-  %nop7807 = alloca i1, i1 0
-  %nop7808 = alloca i1, i1 0
-  %nop7809 = alloca i1, i1 0
-  %nop7810 = alloca i1, i1 0
-  %nop7811 = alloca i1, i1 0
-  %nop7812 = alloca i1, i1 0
-  %nop7813 = alloca i1, i1 0
-  %nop7814 = alloca i1, i1 0
-  %nop7815 = alloca i1, i1 0
-  %nop7816 = alloca i1, i1 0
-  %nop7817 = alloca i1, i1 0
-  %nop7818 = alloca i1, i1 0
-  %nop7819 = alloca i1, i1 0
-  %nop7820 = alloca i1, i1 0
-  %nop7821 = alloca i1, i1 0
-  %nop7822 = alloca i1, i1 0
-  %nop7823 = alloca i1, i1 0
-  %nop7824 = alloca i1, i1 0
-  %nop7825 = alloca i1, i1 0
-  %nop7826 = alloca i1, i1 0
-  %nop7827 = alloca i1, i1 0
-  %nop7828 = alloca i1, i1 0
-  %nop7829 = alloca i1, i1 0
-  %nop7830 = alloca i1, i1 0
-  %nop7831 = alloca i1, i1 0
-  %nop7832 = alloca i1, i1 0
-  %nop7833 = alloca i1, i1 0
-  %nop7834 = alloca i1, i1 0
-  %nop7835 = alloca i1, i1 0
-  %nop7836 = alloca i1, i1 0
-  %nop7837 = alloca i1, i1 0
-  %nop7838 = alloca i1, i1 0
-  %nop7839 = alloca i1, i1 0
-  %nop7840 = alloca i1, i1 0
-  %nop7841 = alloca i1, i1 0
-  %nop7842 = alloca i1, i1 0
-  %nop7843 = alloca i1, i1 0
-  %nop7844 = alloca i1, i1 0
-  %nop7845 = alloca i1, i1 0
-  %nop7846 = alloca i1, i1 0
-  %nop7847 = alloca i1, i1 0
-  %nop7848 = alloca i1, i1 0
-  %nop7849 = alloca i1, i1 0
-  %nop7850 = alloca i1, i1 0
-  %nop7851 = alloca i1, i1 0
-  %nop7852 = alloca i1, i1 0
-  %nop7853 = alloca i1, i1 0
-  %nop7854 = alloca i1, i1 0
-  %nop7855 = alloca i1, i1 0
-  %nop7856 = alloca i1, i1 0
-  %nop7857 = alloca i1, i1 0
-  %nop7858 = alloca i1, i1 0
-  %nop7859 = alloca i1, i1 0
-  %nop7860 = alloca i1, i1 0
-  %nop7861 = alloca i1, i1 0
-  %nop7862 = alloca i1, i1 0
-  %nop7863 = alloca i1, i1 0
-  %nop7864 = alloca i1, i1 0
-  %nop7865 = alloca i1, i1 0
-  %nop7866 = alloca i1, i1 0
-  %nop7867 = alloca i1, i1 0
-  %nop7868 = alloca i1, i1 0
-  %nop7869 = alloca i1, i1 0
-  %nop7870 = alloca i1, i1 0
-  %nop7871 = alloca i1, i1 0
-  %nop7872 = alloca i1, i1 0
-  %nop7873 = alloca i1, i1 0
-  %nop7874 = alloca i1, i1 0
-  %nop7875 = alloca i1, i1 0
-  %nop7876 = alloca i1, i1 0
-  %nop7877 = alloca i1, i1 0
-  %nop7878 = alloca i1, i1 0
-  %nop7879 = alloca i1, i1 0
-  %nop7880 = alloca i1, i1 0
-  %nop7881 = alloca i1, i1 0
-  %nop7882 = alloca i1, i1 0
-  %nop7883 = alloca i1, i1 0
-  %nop7884 = alloca i1, i1 0
-  %nop7885 = alloca i1, i1 0
-  %nop7886 = alloca i1, i1 0
-  %nop7887 = alloca i1, i1 0
-  %nop7888 = alloca i1, i1 0
-  %nop7889 = alloca i1, i1 0
-  %nop7890 = alloca i1, i1 0
-  %nop7891 = alloca i1, i1 0
-  %nop7892 = alloca i1, i1 0
-  %nop7893 = alloca i1, i1 0
-  %nop7894 = alloca i1, i1 0
-  %nop7895 = alloca i1, i1 0
-  %nop7896 = alloca i1, i1 0
-  %nop7897 = alloca i1, i1 0
-  %nop7898 = alloca i1, i1 0
-  %nop7899 = alloca i1, i1 0
-  %nop7900 = alloca i1, i1 0
-  %nop7901 = alloca i1, i1 0
-  %nop7902 = alloca i1, i1 0
-  %nop7903 = alloca i1, i1 0
-  %nop7904 = alloca i1, i1 0
-  %nop7905 = alloca i1, i1 0
-  %nop7906 = alloca i1, i1 0
-  %nop7907 = alloca i1, i1 0
-  %nop7908 = alloca i1, i1 0
-  %nop7909 = alloca i1, i1 0
-  %nop7910 = alloca i1, i1 0
-  %nop7911 = alloca i1, i1 0
-  %nop7912 = alloca i1, i1 0
-  %nop7913 = alloca i1, i1 0
-  %nop7914 = alloca i1, i1 0
-  %nop7915 = alloca i1, i1 0
-  %nop7916 = alloca i1, i1 0
-  %nop7917 = alloca i1, i1 0
-  %nop7918 = alloca i1, i1 0
-  %nop7919 = alloca i1, i1 0
-  %nop7920 = alloca i1, i1 0
-  %nop7921 = alloca i1, i1 0
-  %nop7922 = alloca i1, i1 0
-  %nop7923 = alloca i1, i1 0
-  %nop7924 = alloca i1, i1 0
-  %nop7925 = alloca i1, i1 0
-  %nop7926 = alloca i1, i1 0
-  %nop7927 = alloca i1, i1 0
-  %nop7928 = alloca i1, i1 0
-  %nop7929 = alloca i1, i1 0
-  %nop7930 = alloca i1, i1 0
-  %nop7931 = alloca i1, i1 0
-  %nop7932 = alloca i1, i1 0
-  %nop7933 = alloca i1, i1 0
-  %nop7934 = alloca i1, i1 0
-  %nop7935 = alloca i1, i1 0
-  %nop7936 = alloca i1, i1 0
-  %nop7937 = alloca i1, i1 0
-  %nop7938 = alloca i1, i1 0
-  %nop7939 = alloca i1, i1 0
-  %nop7940 = alloca i1, i1 0
-  %nop7941 = alloca i1, i1 0
-  %nop7942 = alloca i1, i1 0
-  %nop7943 = alloca i1, i1 0
-  %nop7944 = alloca i1, i1 0
-  %nop7945 = alloca i1, i1 0
-  %nop7946 = alloca i1, i1 0
-  %nop7947 = alloca i1, i1 0
-  %nop7948 = alloca i1, i1 0
-  %nop7949 = alloca i1, i1 0
-  %nop7950 = alloca i1, i1 0
-  %nop7951 = alloca i1, i1 0
-  %nop7952 = alloca i1, i1 0
-  %nop7953 = alloca i1, i1 0
-  %nop7954 = alloca i1, i1 0
-  %nop7955 = alloca i1, i1 0
-  %nop7956 = alloca i1, i1 0
-  %nop7957 = alloca i1, i1 0
-  %nop7958 = alloca i1, i1 0
-  %nop7959 = alloca i1, i1 0
-  %nop7960 = alloca i1, i1 0
-  %nop7961 = alloca i1, i1 0
-  %nop7962 = alloca i1, i1 0
-  %nop7963 = alloca i1, i1 0
-  %nop7964 = alloca i1, i1 0
-  %nop7965 = alloca i1, i1 0
-  %nop7966 = alloca i1, i1 0
-  %nop7967 = alloca i1, i1 0
-  %nop7968 = alloca i1, i1 0
-  %nop7969 = alloca i1, i1 0
-  %nop7970 = alloca i1, i1 0
-  %nop7971 = alloca i1, i1 0
-  %nop7972 = alloca i1, i1 0
-  %nop7973 = alloca i1, i1 0
-  %nop7974 = alloca i1, i1 0
-  %nop7975 = alloca i1, i1 0
-  %nop7976 = alloca i1, i1 0
-  %nop7977 = alloca i1, i1 0
-  %nop7978 = alloca i1, i1 0
-  %nop7979 = alloca i1, i1 0
-  %nop7980 = alloca i1, i1 0
-  %nop7981 = alloca i1, i1 0
-  %nop7982 = alloca i1, i1 0
-  %nop7983 = alloca i1, i1 0
-  %nop7984 = alloca i1, i1 0
-  %nop7985 = alloca i1, i1 0
-  %nop7986 = alloca i1, i1 0
-  %nop7987 = alloca i1, i1 0
-  %nop7988 = alloca i1, i1 0
-  %nop7989 = alloca i1, i1 0
-  %nop7990 = alloca i1, i1 0
-  %nop7991 = alloca i1, i1 0
-  %nop7992 = alloca i1, i1 0
-  %nop7993 = alloca i1, i1 0
-  %nop7994 = alloca i1, i1 0
-  %nop7995 = alloca i1, i1 0
-  %nop7996 = alloca i1, i1 0
-  %nop7997 = alloca i1, i1 0
-  %nop7998 = alloca i1, i1 0
-  %nop7999 = alloca i1, i1 0
-  %nop8000 = alloca i1, i1 0
-  %nop8001 = alloca i1, i1 0
-  %nop8002 = alloca i1, i1 0
-  %nop8003 = alloca i1, i1 0
-  %nop8004 = alloca i1, i1 0
-  %nop8005 = alloca i1, i1 0
-  %nop8006 = alloca i1, i1 0
-  %nop8007 = alloca i1, i1 0
-  %nop8008 = alloca i1, i1 0
-  %nop8009 = alloca i1, i1 0
-  %nop8010 = alloca i1, i1 0
-  %nop8011 = alloca i1, i1 0
-  %nop8012 = alloca i1, i1 0
-  %nop8013 = alloca i1, i1 0
-  %nop8014 = alloca i1, i1 0
-  %nop8015 = alloca i1, i1 0
-  %nop8016 = alloca i1, i1 0
-  %nop8017 = alloca i1, i1 0
-  %nop8018 = alloca i1, i1 0
-  %nop8019 = alloca i1, i1 0
-  %nop8020 = alloca i1, i1 0
-  %nop8021 = alloca i1, i1 0
-  %nop8022 = alloca i1, i1 0
-  %nop8023 = alloca i1, i1 0
-  %nop8024 = alloca i1, i1 0
-  %nop8025 = alloca i1, i1 0
-  %nop8026 = alloca i1, i1 0
-  %nop8027 = alloca i1, i1 0
-  %nop8028 = alloca i1, i1 0
-  %nop8029 = alloca i1, i1 0
-  %nop8030 = alloca i1, i1 0
-  %nop8031 = alloca i1, i1 0
-  %nop8032 = alloca i1, i1 0
-  %nop8033 = alloca i1, i1 0
-  %nop8034 = alloca i1, i1 0
-  %nop8035 = alloca i1, i1 0
-  %nop8036 = alloca i1, i1 0
-  %nop8037 = alloca i1, i1 0
-  %nop8038 = alloca i1, i1 0
-  %nop8039 = alloca i1, i1 0
-  %nop8040 = alloca i1, i1 0
-  %nop8041 = alloca i1, i1 0
-  %nop8042 = alloca i1, i1 0
-  %nop8043 = alloca i1, i1 0
-  %nop8044 = alloca i1, i1 0
-  %nop8045 = alloca i1, i1 0
-  %nop8046 = alloca i1, i1 0
-  %nop8047 = alloca i1, i1 0
-  %nop8048 = alloca i1, i1 0
-  %nop8049 = alloca i1, i1 0
-  %nop8050 = alloca i1, i1 0
-  %nop8051 = alloca i1, i1 0
-  %nop8052 = alloca i1, i1 0
-  %nop8053 = alloca i1, i1 0
-  %nop8054 = alloca i1, i1 0
-  %nop8055 = alloca i1, i1 0
-  %nop8056 = alloca i1, i1 0
-  %nop8057 = alloca i1, i1 0
-  %nop8058 = alloca i1, i1 0
-  %nop8059 = alloca i1, i1 0
-  %nop8060 = alloca i1, i1 0
-  %nop8061 = alloca i1, i1 0
-  %nop8062 = alloca i1, i1 0
-  %nop8063 = alloca i1, i1 0
-  %nop8064 = alloca i1, i1 0
-  %nop8065 = alloca i1, i1 0
-  %nop8066 = alloca i1, i1 0
-  %nop8067 = alloca i1, i1 0
-  %nop8068 = alloca i1, i1 0
-  %nop8069 = alloca i1, i1 0
-  %nop8070 = alloca i1, i1 0
-  %nop8071 = alloca i1, i1 0
-  %nop8072 = alloca i1, i1 0
-  %nop8073 = alloca i1, i1 0
-  %nop8074 = alloca i1, i1 0
-  %nop8075 = alloca i1, i1 0
-  %nop8076 = alloca i1, i1 0
-  %nop8077 = alloca i1, i1 0
-  %nop8078 = alloca i1, i1 0
-  %nop8079 = alloca i1, i1 0
-  %nop8080 = alloca i1, i1 0
-  %nop8081 = alloca i1, i1 0
-  %nop8082 = alloca i1, i1 0
-  %nop8083 = alloca i1, i1 0
-  %nop8084 = alloca i1, i1 0
-  %nop8085 = alloca i1, i1 0
-  %nop8086 = alloca i1, i1 0
-  %nop8087 = alloca i1, i1 0
-  %nop8088 = alloca i1, i1 0
-  %nop8089 = alloca i1, i1 0
-  %nop8090 = alloca i1, i1 0
-  %nop8091 = alloca i1, i1 0
-  %nop8092 = alloca i1, i1 0
-  %nop8093 = alloca i1, i1 0
-  %nop8094 = alloca i1, i1 0
-  %nop8095 = alloca i1, i1 0
-  %nop8096 = alloca i1, i1 0
-  %nop8097 = alloca i1, i1 0
-  %nop8098 = alloca i1, i1 0
-  %nop8099 = alloca i1, i1 0
-  %nop8100 = alloca i1, i1 0
-  %nop8101 = alloca i1, i1 0
-  %nop8102 = alloca i1, i1 0
-  %nop8103 = alloca i1, i1 0
-  %nop8104 = alloca i1, i1 0
-  %nop8105 = alloca i1, i1 0
-  %nop8106 = alloca i1, i1 0
-  %nop8107 = alloca i1, i1 0
-  %nop8108 = alloca i1, i1 0
-  %nop8109 = alloca i1, i1 0
-  %nop8110 = alloca i1, i1 0
-  %nop8111 = alloca i1, i1 0
-  %nop8112 = alloca i1, i1 0
-  %nop8113 = alloca i1, i1 0
-  %nop8114 = alloca i1, i1 0
-  %nop8115 = alloca i1, i1 0
-  %nop8116 = alloca i1, i1 0
-  %nop8117 = alloca i1, i1 0
-  %nop8118 = alloca i1, i1 0
-  %nop8119 = alloca i1, i1 0
-  %nop8120 = alloca i1, i1 0
-  %nop8121 = alloca i1, i1 0
-  %nop8122 = alloca i1, i1 0
-  %nop8123 = alloca i1, i1 0
-  %nop8124 = alloca i1, i1 0
-  %nop8125 = alloca i1, i1 0
-  %nop8126 = alloca i1, i1 0
-  %nop8127 = alloca i1, i1 0
-  %nop8128 = alloca i1, i1 0
-  %nop8129 = alloca i1, i1 0
-  %nop8130 = alloca i1, i1 0
-  %nop8131 = alloca i1, i1 0
-  %nop8132 = alloca i1, i1 0
-  %nop8133 = alloca i1, i1 0
-  %nop8134 = alloca i1, i1 0
-  %nop8135 = alloca i1, i1 0
-  %nop8136 = alloca i1, i1 0
-  %nop8137 = alloca i1, i1 0
-  %nop8138 = alloca i1, i1 0
-  %nop8139 = alloca i1, i1 0
-  %nop8140 = alloca i1, i1 0
-  %nop8141 = alloca i1, i1 0
-  %nop8142 = alloca i1, i1 0
-  %nop8143 = alloca i1, i1 0
-  %nop8144 = alloca i1, i1 0
-  %nop8145 = alloca i1, i1 0
-  %nop8146 = alloca i1, i1 0
-  %nop8147 = alloca i1, i1 0
-  %nop8148 = alloca i1, i1 0
-  %nop8149 = alloca i1, i1 0
-  %nop8150 = alloca i1, i1 0
-  %nop8151 = alloca i1, i1 0
-  %nop8152 = alloca i1, i1 0
-  %nop8153 = alloca i1, i1 0
-  %nop8154 = alloca i1, i1 0
-  %nop8155 = alloca i1, i1 0
-  %nop8156 = alloca i1, i1 0
-  %nop8157 = alloca i1, i1 0
-  %nop8158 = alloca i1, i1 0
-  %nop8159 = alloca i1, i1 0
-  %nop8160 = alloca i1, i1 0
-  %nop8161 = alloca i1, i1 0
-  %nop8162 = alloca i1, i1 0
-  %nop8163 = alloca i1, i1 0
-  %nop8164 = alloca i1, i1 0
-  %nop8165 = alloca i1, i1 0
-  %nop8166 = alloca i1, i1 0
-  %nop8167 = alloca i1, i1 0
-  %nop8168 = alloca i1, i1 0
-  %nop8169 = alloca i1, i1 0
-  %nop8170 = alloca i1, i1 0
-  %nop8171 = alloca i1, i1 0
-  %nop8172 = alloca i1, i1 0
-  %nop8173 = alloca i1, i1 0
-  %nop8174 = alloca i1, i1 0
-  %nop8175 = alloca i1, i1 0
-  %nop8176 = alloca i1, i1 0
-  %nop8177 = alloca i1, i1 0
-  %nop8178 = alloca i1, i1 0
-  %nop8179 = alloca i1, i1 0
-  %nop8180 = alloca i1, i1 0
-  %nop8181 = alloca i1, i1 0
-  %nop8182 = alloca i1, i1 0
-  %nop8183 = alloca i1, i1 0
-  %nop8184 = alloca i1, i1 0
-  %nop8185 = alloca i1, i1 0
-  %nop8186 = alloca i1, i1 0
-  %nop8187 = alloca i1, i1 0
-  %nop8188 = alloca i1, i1 0
-  %nop8189 = alloca i1, i1 0
-  %nop8190 = alloca i1, i1 0
-  %nop8191 = alloca i1, i1 0
-  %nop8192 = alloca i1, i1 0
-  %nop8193 = alloca i1, i1 0
-  %nop8194 = alloca i1, i1 0
-  %nop8195 = alloca i1, i1 0
-  %nop8196 = alloca i1, i1 0
-  %nop8197 = alloca i1, i1 0
-  %nop8198 = alloca i1, i1 0
-  %nop8199 = alloca i1, i1 0
-  %nop8200 = alloca i1, i1 0
-  %nop8201 = alloca i1, i1 0
-  %nop8202 = alloca i1, i1 0
-  %nop8203 = alloca i1, i1 0
-  %nop8204 = alloca i1, i1 0
-  %nop8205 = alloca i1, i1 0
-  %nop8206 = alloca i1, i1 0
-  %nop8207 = alloca i1, i1 0
-  %nop8208 = alloca i1, i1 0
-  %nop8209 = alloca i1, i1 0
-  %nop8210 = alloca i1, i1 0
-  %nop8211 = alloca i1, i1 0
-  %nop8212 = alloca i1, i1 0
-  %nop8213 = alloca i1, i1 0
-  %nop8214 = alloca i1, i1 0
-  %nop8215 = alloca i1, i1 0
-  %nop8216 = alloca i1, i1 0
-  %nop8217 = alloca i1, i1 0
-  %nop8218 = alloca i1, i1 0
-  %nop8219 = alloca i1, i1 0
-  %nop8220 = alloca i1, i1 0
-  %nop8221 = alloca i1, i1 0
-  %nop8222 = alloca i1, i1 0
-  %nop8223 = alloca i1, i1 0
-  %nop8224 = alloca i1, i1 0
-  %nop8225 = alloca i1, i1 0
-  %nop8226 = alloca i1, i1 0
-  %nop8227 = alloca i1, i1 0
-  %nop8228 = alloca i1, i1 0
-  %nop8229 = alloca i1, i1 0
-  %nop8230 = alloca i1, i1 0
-  %nop8231 = alloca i1, i1 0
-  %nop8232 = alloca i1, i1 0
-  %nop8233 = alloca i1, i1 0
-  %nop8234 = alloca i1, i1 0
-  %nop8235 = alloca i1, i1 0
-  %nop8236 = alloca i1, i1 0
-  %nop8237 = alloca i1, i1 0
-  %nop8238 = alloca i1, i1 0
-  %nop8239 = alloca i1, i1 0
-  %nop8240 = alloca i1, i1 0
-  %nop8241 = alloca i1, i1 0
-  %nop8242 = alloca i1, i1 0
-  %nop8243 = alloca i1, i1 0
-  %nop8244 = alloca i1, i1 0
-  %nop8245 = alloca i1, i1 0
-  %nop8246 = alloca i1, i1 0
-  %nop8247 = alloca i1, i1 0
-  %nop8248 = alloca i1, i1 0
-  %nop8249 = alloca i1, i1 0
-  %nop8250 = alloca i1, i1 0
-  %nop8251 = alloca i1, i1 0
-  %nop8252 = alloca i1, i1 0
-  %nop8253 = alloca i1, i1 0
-  %nop8254 = alloca i1, i1 0
-  %nop8255 = alloca i1, i1 0
-  %nop8256 = alloca i1, i1 0
-  %nop8257 = alloca i1, i1 0
-  %nop8258 = alloca i1, i1 0
-  %nop8259 = alloca i1, i1 0
-  %nop8260 = alloca i1, i1 0
-  %nop8261 = alloca i1, i1 0
-  %nop8262 = alloca i1, i1 0
-  %nop8263 = alloca i1, i1 0
-  %nop8264 = alloca i1, i1 0
-  %nop8265 = alloca i1, i1 0
-  %nop8266 = alloca i1, i1 0
-  %nop8267 = alloca i1, i1 0
-  %nop8268 = alloca i1, i1 0
-  %nop8269 = alloca i1, i1 0
-  %nop8270 = alloca i1, i1 0
-  %nop8271 = alloca i1, i1 0
-  %nop8272 = alloca i1, i1 0
-  %nop8273 = alloca i1, i1 0
-  %nop8274 = alloca i1, i1 0
-  %nop8275 = alloca i1, i1 0
-  %nop8276 = alloca i1, i1 0
-  %nop8277 = alloca i1, i1 0
-  %nop8278 = alloca i1, i1 0
-  %nop8279 = alloca i1, i1 0
-  %nop8280 = alloca i1, i1 0
-  %nop8281 = alloca i1, i1 0
-  %nop8282 = alloca i1, i1 0
-  %nop8283 = alloca i1, i1 0
-  %nop8284 = alloca i1, i1 0
-  %nop8285 = alloca i1, i1 0
-  %nop8286 = alloca i1, i1 0
-  %nop8287 = alloca i1, i1 0
-  %nop8288 = alloca i1, i1 0
-  %nop8289 = alloca i1, i1 0
-  %nop8290 = alloca i1, i1 0
-  %nop8291 = alloca i1, i1 0
-  %nop8292 = alloca i1, i1 0
-  %nop8293 = alloca i1, i1 0
-  %nop8294 = alloca i1, i1 0
-  %nop8295 = alloca i1, i1 0
-  %nop8296 = alloca i1, i1 0
-  %nop8297 = alloca i1, i1 0
-  %nop8298 = alloca i1, i1 0
-  %nop8299 = alloca i1, i1 0
-  %nop8300 = alloca i1, i1 0
-  %nop8301 = alloca i1, i1 0
-  %nop8302 = alloca i1, i1 0
-  %nop8303 = alloca i1, i1 0
-  %nop8304 = alloca i1, i1 0
-  %nop8305 = alloca i1, i1 0
-  %nop8306 = alloca i1, i1 0
-  %nop8307 = alloca i1, i1 0
-  %nop8308 = alloca i1, i1 0
-  %nop8309 = alloca i1, i1 0
-  %nop8310 = alloca i1, i1 0
-  %nop8311 = alloca i1, i1 0
-  %nop8312 = alloca i1, i1 0
-  %nop8313 = alloca i1, i1 0
-  %nop8314 = alloca i1, i1 0
-  %nop8315 = alloca i1, i1 0
-  %nop8316 = alloca i1, i1 0
-  %nop8317 = alloca i1, i1 0
-  %nop8318 = alloca i1, i1 0
-  %nop8319 = alloca i1, i1 0
-  %nop8320 = alloca i1, i1 0
-  %nop8321 = alloca i1, i1 0
-  %nop8322 = alloca i1, i1 0
-  %nop8323 = alloca i1, i1 0
-  %nop8324 = alloca i1, i1 0
-  %nop8325 = alloca i1, i1 0
-  %nop8326 = alloca i1, i1 0
-  %nop8327 = alloca i1, i1 0
-  %nop8328 = alloca i1, i1 0
-  %nop8329 = alloca i1, i1 0
-  %nop8330 = alloca i1, i1 0
-  %nop8331 = alloca i1, i1 0
-  %nop8332 = alloca i1, i1 0
-  %nop8333 = alloca i1, i1 0
-  %nop8334 = alloca i1, i1 0
-  %nop8335 = alloca i1, i1 0
-  %nop8336 = alloca i1, i1 0
-  %nop8337 = alloca i1, i1 0
-  %nop8338 = alloca i1, i1 0
-  %nop8339 = alloca i1, i1 0
-  %nop8340 = alloca i1, i1 0
-  %nop8341 = alloca i1, i1 0
-  %nop8342 = alloca i1, i1 0
-  %nop8343 = alloca i1, i1 0
-  %nop8344 = alloca i1, i1 0
-  %nop8345 = alloca i1, i1 0
-  %nop8346 = alloca i1, i1 0
-  %nop8347 = alloca i1, i1 0
-  %nop8348 = alloca i1, i1 0
-  %nop8349 = alloca i1, i1 0
-  %nop8350 = alloca i1, i1 0
-  %nop8351 = alloca i1, i1 0
-  %nop8352 = alloca i1, i1 0
-  %nop8353 = alloca i1, i1 0
-  %nop8354 = alloca i1, i1 0
-  %nop8355 = alloca i1, i1 0
-  %nop8356 = alloca i1, i1 0
-  %nop8357 = alloca i1, i1 0
-  %nop8358 = alloca i1, i1 0
-  %nop8359 = alloca i1, i1 0
-  %nop8360 = alloca i1, i1 0
-  %nop8361 = alloca i1, i1 0
-  %nop8362 = alloca i1, i1 0
-  %nop8363 = alloca i1, i1 0
-  %nop8364 = alloca i1, i1 0
-  %nop8365 = alloca i1, i1 0
-  %nop8366 = alloca i1, i1 0
-  %nop8367 = alloca i1, i1 0
-  %nop8368 = alloca i1, i1 0
-  %nop8369 = alloca i1, i1 0
-  %nop8370 = alloca i1, i1 0
-  %nop8371 = alloca i1, i1 0
-  %nop8372 = alloca i1, i1 0
-  %nop8373 = alloca i1, i1 0
-  %nop8374 = alloca i1, i1 0
-  %nop8375 = alloca i1, i1 0
-  %nop8376 = alloca i1, i1 0
-  %nop8377 = alloca i1, i1 0
-  %nop8378 = alloca i1, i1 0
-  %nop8379 = alloca i1, i1 0
-  %nop8380 = alloca i1, i1 0
-  %nop8381 = alloca i1, i1 0
-  %nop8382 = alloca i1, i1 0
-  %nop8383 = alloca i1, i1 0
-  %nop8384 = alloca i1, i1 0
-  %nop8385 = alloca i1, i1 0
-  %nop8386 = alloca i1, i1 0
-  %nop8387 = alloca i1, i1 0
-  %nop8388 = alloca i1, i1 0
-  %nop8389 = alloca i1, i1 0
-  %nop8390 = alloca i1, i1 0
-  %nop8391 = alloca i1, i1 0
-  %nop8392 = alloca i1, i1 0
-  %nop8393 = alloca i1, i1 0
-  %nop8394 = alloca i1, i1 0
-  %nop8395 = alloca i1, i1 0
-  %nop8396 = alloca i1, i1 0
-  %nop8397 = alloca i1, i1 0
-  %nop8398 = alloca i1, i1 0
-  %nop8399 = alloca i1, i1 0
-  %nop8400 = alloca i1, i1 0
-  %nop8401 = alloca i1, i1 0
-  %nop8402 = alloca i1, i1 0
-  %nop8403 = alloca i1, i1 0
-  %nop8404 = alloca i1, i1 0
-  %nop8405 = alloca i1, i1 0
-  %nop8406 = alloca i1, i1 0
-  %nop8407 = alloca i1, i1 0
-  %nop8408 = alloca i1, i1 0
-  %nop8409 = alloca i1, i1 0
-  %nop8410 = alloca i1, i1 0
-  %nop8411 = alloca i1, i1 0
-  %nop8412 = alloca i1, i1 0
-  %nop8413 = alloca i1, i1 0
-  %nop8414 = alloca i1, i1 0
-  %nop8415 = alloca i1, i1 0
-  %nop8416 = alloca i1, i1 0
-  %nop8417 = alloca i1, i1 0
-  %nop8418 = alloca i1, i1 0
-  %nop8419 = alloca i1, i1 0
-  %nop8420 = alloca i1, i1 0
-  %nop8421 = alloca i1, i1 0
-  %nop8422 = alloca i1, i1 0
-  %nop8423 = alloca i1, i1 0
-  %nop8424 = alloca i1, i1 0
-  %nop8425 = alloca i1, i1 0
-  %nop8426 = alloca i1, i1 0
-  %nop8427 = alloca i1, i1 0
-  %nop8428 = alloca i1, i1 0
-  %nop8429 = alloca i1, i1 0
-  %nop8430 = alloca i1, i1 0
-  %nop8431 = alloca i1, i1 0
-  %nop8432 = alloca i1, i1 0
-  %nop8433 = alloca i1, i1 0
-  %nop8434 = alloca i1, i1 0
-  %nop8435 = alloca i1, i1 0
-  %nop8436 = alloca i1, i1 0
-  %nop8437 = alloca i1, i1 0
-  %nop8438 = alloca i1, i1 0
-  %nop8439 = alloca i1, i1 0
-  %nop8440 = alloca i1, i1 0
-  %nop8441 = alloca i1, i1 0
-  %nop8442 = alloca i1, i1 0
-  %nop8443 = alloca i1, i1 0
-  %nop8444 = alloca i1, i1 0
-  %nop8445 = alloca i1, i1 0
-  %nop8446 = alloca i1, i1 0
-  %nop8447 = alloca i1, i1 0
-  %nop8448 = alloca i1, i1 0
-  %nop8449 = alloca i1, i1 0
-  %nop8450 = alloca i1, i1 0
-  %nop8451 = alloca i1, i1 0
-  %nop8452 = alloca i1, i1 0
-  %nop8453 = alloca i1, i1 0
-  %nop8454 = alloca i1, i1 0
-  %nop8455 = alloca i1, i1 0
-  %nop8456 = alloca i1, i1 0
-  %nop8457 = alloca i1, i1 0
-  %nop8458 = alloca i1, i1 0
-  %nop8459 = alloca i1, i1 0
-  %nop8460 = alloca i1, i1 0
-  %nop8461 = alloca i1, i1 0
-  %nop8462 = alloca i1, i1 0
-  %nop8463 = alloca i1, i1 0
-  %nop8464 = alloca i1, i1 0
-  %nop8465 = alloca i1, i1 0
-  %nop8466 = alloca i1, i1 0
-  %nop8467 = alloca i1, i1 0
-  %nop8468 = alloca i1, i1 0
-  %nop8469 = alloca i1, i1 0
-  %nop8470 = alloca i1, i1 0
-  %nop8471 = alloca i1, i1 0
-  %nop8472 = alloca i1, i1 0
-  %nop8473 = alloca i1, i1 0
-  %nop8474 = alloca i1, i1 0
-  %nop8475 = alloca i1, i1 0
-  %nop8476 = alloca i1, i1 0
-  %nop8477 = alloca i1, i1 0
-  %nop8478 = alloca i1, i1 0
-  %nop8479 = alloca i1, i1 0
-  %nop8480 = alloca i1, i1 0
-  %nop8481 = alloca i1, i1 0
-  %nop8482 = alloca i1, i1 0
-  %nop8483 = alloca i1, i1 0
-  %nop8484 = alloca i1, i1 0
-  %nop8485 = alloca i1, i1 0
-  %nop8486 = alloca i1, i1 0
-  %nop8487 = alloca i1, i1 0
-  %nop8488 = alloca i1, i1 0
-  %nop8489 = alloca i1, i1 0
-  %nop8490 = alloca i1, i1 0
-  %nop8491 = alloca i1, i1 0
-  %nop8492 = alloca i1, i1 0
-  %nop8493 = alloca i1, i1 0
-  %nop8494 = alloca i1, i1 0
-  %nop8495 = alloca i1, i1 0
-  %nop8496 = alloca i1, i1 0
-  %nop8497 = alloca i1, i1 0
-  %nop8498 = alloca i1, i1 0
-  %nop8499 = alloca i1, i1 0
-  %nop8500 = alloca i1, i1 0
-  %nop8501 = alloca i1, i1 0
-  %nop8502 = alloca i1, i1 0
-  %nop8503 = alloca i1, i1 0
-  %nop8504 = alloca i1, i1 0
-  %nop8505 = alloca i1, i1 0
-  %nop8506 = alloca i1, i1 0
-  %nop8507 = alloca i1, i1 0
-  %nop8508 = alloca i1, i1 0
-  %nop8509 = alloca i1, i1 0
-  %nop8510 = alloca i1, i1 0
-  %nop8511 = alloca i1, i1 0
-  %nop8512 = alloca i1, i1 0
-  %nop8513 = alloca i1, i1 0
-  %nop8514 = alloca i1, i1 0
-  %nop8515 = alloca i1, i1 0
-  %nop8516 = alloca i1, i1 0
-  %nop8517 = alloca i1, i1 0
-  %nop8518 = alloca i1, i1 0
-  %nop8519 = alloca i1, i1 0
-  %nop8520 = alloca i1, i1 0
-  %nop8521 = alloca i1, i1 0
-  %nop8522 = alloca i1, i1 0
-  %nop8523 = alloca i1, i1 0
-  %nop8524 = alloca i1, i1 0
-  %nop8525 = alloca i1, i1 0
-  %nop8526 = alloca i1, i1 0
-  %nop8527 = alloca i1, i1 0
-  %nop8528 = alloca i1, i1 0
-  %nop8529 = alloca i1, i1 0
-  %nop8530 = alloca i1, i1 0
-  %nop8531 = alloca i1, i1 0
-  %nop8532 = alloca i1, i1 0
-  %nop8533 = alloca i1, i1 0
-  %nop8534 = alloca i1, i1 0
-  %nop8535 = alloca i1, i1 0
-  %nop8536 = alloca i1, i1 0
-  %nop8537 = alloca i1, i1 0
-  %nop8538 = alloca i1, i1 0
-  %nop8539 = alloca i1, i1 0
-  %nop8540 = alloca i1, i1 0
-  %nop8541 = alloca i1, i1 0
-  %nop8542 = alloca i1, i1 0
-  %nop8543 = alloca i1, i1 0
-  %nop8544 = alloca i1, i1 0
-  %nop8545 = alloca i1, i1 0
-  %nop8546 = alloca i1, i1 0
-  %nop8547 = alloca i1, i1 0
-  %nop8548 = alloca i1, i1 0
-  %nop8549 = alloca i1, i1 0
-  %nop8550 = alloca i1, i1 0
-  %nop8551 = alloca i1, i1 0
-  %nop8552 = alloca i1, i1 0
-  %nop8553 = alloca i1, i1 0
-  %nop8554 = alloca i1, i1 0
-  %nop8555 = alloca i1, i1 0
-  %nop8556 = alloca i1, i1 0
-  %nop8557 = alloca i1, i1 0
-  %nop8558 = alloca i1, i1 0
-  %nop8559 = alloca i1, i1 0
-  %nop8560 = alloca i1, i1 0
-  %nop8561 = alloca i1, i1 0
-  %nop8562 = alloca i1, i1 0
-  %nop8563 = alloca i1, i1 0
-  %nop8564 = alloca i1, i1 0
-  %nop8565 = alloca i1, i1 0
-  %nop8566 = alloca i1, i1 0
-  %nop8567 = alloca i1, i1 0
-  %nop8568 = alloca i1, i1 0
-  %nop8569 = alloca i1, i1 0
-  %nop8570 = alloca i1, i1 0
-  %nop8571 = alloca i1, i1 0
-  %nop8572 = alloca i1, i1 0
-  %nop8573 = alloca i1, i1 0
-  %nop8574 = alloca i1, i1 0
-  %nop8575 = alloca i1, i1 0
-  %nop8576 = alloca i1, i1 0
-  %nop8577 = alloca i1, i1 0
-  %nop8578 = alloca i1, i1 0
-  %nop8579 = alloca i1, i1 0
-  %nop8580 = alloca i1, i1 0
-  %nop8581 = alloca i1, i1 0
-  %nop8582 = alloca i1, i1 0
-  %nop8583 = alloca i1, i1 0
-  %nop8584 = alloca i1, i1 0
-  %nop8585 = alloca i1, i1 0
-  %nop8586 = alloca i1, i1 0
-  %nop8587 = alloca i1, i1 0
-  %nop8588 = alloca i1, i1 0
-  %nop8589 = alloca i1, i1 0
-  %nop8590 = alloca i1, i1 0
-  %nop8591 = alloca i1, i1 0
-  %nop8592 = alloca i1, i1 0
-  %nop8593 = alloca i1, i1 0
-  %nop8594 = alloca i1, i1 0
-  %nop8595 = alloca i1, i1 0
-  %nop8596 = alloca i1, i1 0
-  %nop8597 = alloca i1, i1 0
-  %nop8598 = alloca i1, i1 0
-  %nop8599 = alloca i1, i1 0
-  %nop8600 = alloca i1, i1 0
-  %nop8601 = alloca i1, i1 0
-  %nop8602 = alloca i1, i1 0
-  %nop8603 = alloca i1, i1 0
-  %nop8604 = alloca i1, i1 0
-  %nop8605 = alloca i1, i1 0
-  %nop8606 = alloca i1, i1 0
-  %nop8607 = alloca i1, i1 0
-  %nop8608 = alloca i1, i1 0
-  %nop8609 = alloca i1, i1 0
-  %nop8610 = alloca i1, i1 0
-  %nop8611 = alloca i1, i1 0
-  %nop8612 = alloca i1, i1 0
-  %nop8613 = alloca i1, i1 0
-  %nop8614 = alloca i1, i1 0
-  %nop8615 = alloca i1, i1 0
-  %nop8616 = alloca i1, i1 0
-  %nop8617 = alloca i1, i1 0
-  %nop8618 = alloca i1, i1 0
-  %nop8619 = alloca i1, i1 0
-  %nop8620 = alloca i1, i1 0
-  %nop8621 = alloca i1, i1 0
-  %nop8622 = alloca i1, i1 0
-  %nop8623 = alloca i1, i1 0
-  %nop8624 = alloca i1, i1 0
-  %nop8625 = alloca i1, i1 0
-  %nop8626 = alloca i1, i1 0
-  %nop8627 = alloca i1, i1 0
-  %nop8628 = alloca i1, i1 0
-  %nop8629 = alloca i1, i1 0
-  %nop8630 = alloca i1, i1 0
-  %nop8631 = alloca i1, i1 0
-  %nop8632 = alloca i1, i1 0
-  %nop8633 = alloca i1, i1 0
-  %nop8634 = alloca i1, i1 0
-  %nop8635 = alloca i1, i1 0
-  %nop8636 = alloca i1, i1 0
-  %nop8637 = alloca i1, i1 0
-  %nop8638 = alloca i1, i1 0
-  %nop8639 = alloca i1, i1 0
-  %nop8640 = alloca i1, i1 0
-  %nop8641 = alloca i1, i1 0
-  %nop8642 = alloca i1, i1 0
-  %nop8643 = alloca i1, i1 0
-  %nop8644 = alloca i1, i1 0
-  %nop8645 = alloca i1, i1 0
-  %nop8646 = alloca i1, i1 0
-  %nop8647 = alloca i1, i1 0
-  %nop8648 = alloca i1, i1 0
-  %nop8649 = alloca i1, i1 0
-  %nop8650 = alloca i1, i1 0
-  %nop8651 = alloca i1, i1 0
-  %nop8652 = alloca i1, i1 0
-  %nop8653 = alloca i1, i1 0
-  %nop8654 = alloca i1, i1 0
-  %nop8655 = alloca i1, i1 0
-  %nop8656 = alloca i1, i1 0
-  %nop8657 = alloca i1, i1 0
-  %nop8658 = alloca i1, i1 0
-  %nop8659 = alloca i1, i1 0
-  %nop8660 = alloca i1, i1 0
-  %nop8661 = alloca i1, i1 0
-  %nop8662 = alloca i1, i1 0
-  %nop8663 = alloca i1, i1 0
-  %nop8664 = alloca i1, i1 0
-  %nop8665 = alloca i1, i1 0
-  %nop8666 = alloca i1, i1 0
-  %nop8667 = alloca i1, i1 0
-  %nop8668 = alloca i1, i1 0
-  %nop8669 = alloca i1, i1 0
-  %nop8670 = alloca i1, i1 0
-  %nop8671 = alloca i1, i1 0
-  %nop8672 = alloca i1, i1 0
-  %nop8673 = alloca i1, i1 0
-  %nop8674 = alloca i1, i1 0
-  %nop8675 = alloca i1, i1 0
-  %nop8676 = alloca i1, i1 0
-  %nop8677 = alloca i1, i1 0
-  %nop8678 = alloca i1, i1 0
-  %nop8679 = alloca i1, i1 0
-  %nop8680 = alloca i1, i1 0
-  %nop8681 = alloca i1, i1 0
-  %nop8682 = alloca i1, i1 0
-  %nop8683 = alloca i1, i1 0
-  %nop8684 = alloca i1, i1 0
-  %nop8685 = alloca i1, i1 0
-  %nop8686 = alloca i1, i1 0
-  %nop8687 = alloca i1, i1 0
-  %nop8688 = alloca i1, i1 0
-  %nop8689 = alloca i1, i1 0
-  %nop8690 = alloca i1, i1 0
-  %nop8691 = alloca i1, i1 0
-  %nop8692 = alloca i1, i1 0
-  %nop8693 = alloca i1, i1 0
-  %nop8694 = alloca i1, i1 0
-  %nop8695 = alloca i1, i1 0
-  %nop8696 = alloca i1, i1 0
-  %nop8697 = alloca i1, i1 0
-  %nop8698 = alloca i1, i1 0
-  %nop8699 = alloca i1, i1 0
-  %nop8700 = alloca i1, i1 0
-  %nop8701 = alloca i1, i1 0
-  %nop8702 = alloca i1, i1 0
-  %nop8703 = alloca i1, i1 0
-  %nop8704 = alloca i1, i1 0
-  %nop8705 = alloca i1, i1 0
-  %nop8706 = alloca i1, i1 0
-  %nop8707 = alloca i1, i1 0
-  %nop8708 = alloca i1, i1 0
-  %nop8709 = alloca i1, i1 0
-  %nop8710 = alloca i1, i1 0
-  %nop8711 = alloca i1, i1 0
-  %nop8712 = alloca i1, i1 0
-  %nop8713 = alloca i1, i1 0
-  %nop8714 = alloca i1, i1 0
-  %nop8715 = alloca i1, i1 0
-  %nop8716 = alloca i1, i1 0
-  %nop8717 = alloca i1, i1 0
-  %nop8718 = alloca i1, i1 0
-  %nop8719 = alloca i1, i1 0
-  %nop8720 = alloca i1, i1 0
-  %nop8721 = alloca i1, i1 0
-  %nop8722 = alloca i1, i1 0
-  %nop8723 = alloca i1, i1 0
-  %nop8724 = alloca i1, i1 0
-  %nop8725 = alloca i1, i1 0
-  %nop8726 = alloca i1, i1 0
-  %nop8727 = alloca i1, i1 0
-  %nop8728 = alloca i1, i1 0
-  %nop8729 = alloca i1, i1 0
-  %nop8730 = alloca i1, i1 0
-  %nop8731 = alloca i1, i1 0
-  %nop8732 = alloca i1, i1 0
-  %nop8733 = alloca i1, i1 0
-  %nop8734 = alloca i1, i1 0
-  %nop8735 = alloca i1, i1 0
-  %nop8736 = alloca i1, i1 0
-  %nop8737 = alloca i1, i1 0
-  %nop8738 = alloca i1, i1 0
-  %nop8739 = alloca i1, i1 0
-  %nop8740 = alloca i1, i1 0
-  %nop8741 = alloca i1, i1 0
-  %nop8742 = alloca i1, i1 0
-  %nop8743 = alloca i1, i1 0
-  %nop8744 = alloca i1, i1 0
-  %nop8745 = alloca i1, i1 0
-  %nop8746 = alloca i1, i1 0
-  %nop8747 = alloca i1, i1 0
-  %nop8748 = alloca i1, i1 0
-  %nop8749 = alloca i1, i1 0
-  %nop8750 = alloca i1, i1 0
-  %nop8751 = alloca i1, i1 0
-  %nop8752 = alloca i1, i1 0
-  %nop8753 = alloca i1, i1 0
-  %nop8754 = alloca i1, i1 0
-  %nop8755 = alloca i1, i1 0
-  %nop8756 = alloca i1, i1 0
-  %nop8757 = alloca i1, i1 0
-  %nop8758 = alloca i1, i1 0
-  %nop8759 = alloca i1, i1 0
-  %nop8760 = alloca i1, i1 0
-  %nop8761 = alloca i1, i1 0
-  %nop8762 = alloca i1, i1 0
-  %nop8763 = alloca i1, i1 0
-  %nop8764 = alloca i1, i1 0
-  %nop8765 = alloca i1, i1 0
-  %nop8766 = alloca i1, i1 0
-  %nop8767 = alloca i1, i1 0
-  %nop8768 = alloca i1, i1 0
-  %nop8769 = alloca i1, i1 0
-  %nop8770 = alloca i1, i1 0
-  %nop8771 = alloca i1, i1 0
-  %nop8772 = alloca i1, i1 0
-  %nop8773 = alloca i1, i1 0
-  %nop8774 = alloca i1, i1 0
-  %nop8775 = alloca i1, i1 0
-  %nop8776 = alloca i1, i1 0
-  %nop8777 = alloca i1, i1 0
-  %nop8778 = alloca i1, i1 0
-  %nop8779 = alloca i1, i1 0
-  %nop8780 = alloca i1, i1 0
-  %nop8781 = alloca i1, i1 0
-  %nop8782 = alloca i1, i1 0
-  %nop8783 = alloca i1, i1 0
-  %nop8784 = alloca i1, i1 0
-  %nop8785 = alloca i1, i1 0
-  %nop8786 = alloca i1, i1 0
-  %nop8787 = alloca i1, i1 0
-  %nop8788 = alloca i1, i1 0
-  %nop8789 = alloca i1, i1 0
-  %nop8790 = alloca i1, i1 0
-  %nop8791 = alloca i1, i1 0
-  %nop8792 = alloca i1, i1 0
-  %nop8793 = alloca i1, i1 0
-  %nop8794 = alloca i1, i1 0
-  %nop8795 = alloca i1, i1 0
-  %nop8796 = alloca i1, i1 0
-  %nop8797 = alloca i1, i1 0
-  %nop8798 = alloca i1, i1 0
-  %nop8799 = alloca i1, i1 0
-  %nop8800 = alloca i1, i1 0
-  %nop8801 = alloca i1, i1 0
-  %nop8802 = alloca i1, i1 0
-  %nop8803 = alloca i1, i1 0
-  %nop8804 = alloca i1, i1 0
-  %nop8805 = alloca i1, i1 0
-  %nop8806 = alloca i1, i1 0
-  %nop8807 = alloca i1, i1 0
-  %nop8808 = alloca i1, i1 0
-  %nop8809 = alloca i1, i1 0
-  %nop8810 = alloca i1, i1 0
-  %nop8811 = alloca i1, i1 0
-  %nop8812 = alloca i1, i1 0
-  %nop8813 = alloca i1, i1 0
-  %nop8814 = alloca i1, i1 0
-  %nop8815 = alloca i1, i1 0
-  %nop8816 = alloca i1, i1 0
-  %nop8817 = alloca i1, i1 0
-  %nop8818 = alloca i1, i1 0
-  %nop8819 = alloca i1, i1 0
-  %nop8820 = alloca i1, i1 0
-  %nop8821 = alloca i1, i1 0
-  %nop8822 = alloca i1, i1 0
-  %nop8823 = alloca i1, i1 0
-  %nop8824 = alloca i1, i1 0
-  %nop8825 = alloca i1, i1 0
-  %nop8826 = alloca i1, i1 0
-  %nop8827 = alloca i1, i1 0
-  %nop8828 = alloca i1, i1 0
-  %nop8829 = alloca i1, i1 0
-  %nop8830 = alloca i1, i1 0
-  %nop8831 = alloca i1, i1 0
-  %nop8832 = alloca i1, i1 0
-  %nop8833 = alloca i1, i1 0
-  %nop8834 = alloca i1, i1 0
-  %nop8835 = alloca i1, i1 0
-  %nop8836 = alloca i1, i1 0
-  %nop8837 = alloca i1, i1 0
-  %nop8838 = alloca i1, i1 0
-  %nop8839 = alloca i1, i1 0
-  %nop8840 = alloca i1, i1 0
-  %nop8841 = alloca i1, i1 0
-  %nop8842 = alloca i1, i1 0
-  %nop8843 = alloca i1, i1 0
-  %nop8844 = alloca i1, i1 0
-  %nop8845 = alloca i1, i1 0
-  %nop8846 = alloca i1, i1 0
-  %nop8847 = alloca i1, i1 0
-  %nop8848 = alloca i1, i1 0
-  %nop8849 = alloca i1, i1 0
-  %nop8850 = alloca i1, i1 0
-  %nop8851 = alloca i1, i1 0
-  %nop8852 = alloca i1, i1 0
-  %nop8853 = alloca i1, i1 0
-  %nop8854 = alloca i1, i1 0
-  %nop8855 = alloca i1, i1 0
-  %nop8856 = alloca i1, i1 0
-  %nop8857 = alloca i1, i1 0
-  %nop8858 = alloca i1, i1 0
-  %nop8859 = alloca i1, i1 0
-  %nop8860 = alloca i1, i1 0
-  %nop8861 = alloca i1, i1 0
-  %nop8862 = alloca i1, i1 0
-  %nop8863 = alloca i1, i1 0
-  %nop8864 = alloca i1, i1 0
-  %nop8865 = alloca i1, i1 0
-  %nop8866 = alloca i1, i1 0
-  %nop8867 = alloca i1, i1 0
-  %nop8868 = alloca i1, i1 0
-  %nop8869 = alloca i1, i1 0
-  %nop8870 = alloca i1, i1 0
-  %nop8871 = alloca i1, i1 0
-  %nop8872 = alloca i1, i1 0
-  %nop8873 = alloca i1, i1 0
-  %nop8874 = alloca i1, i1 0
-  %nop8875 = alloca i1, i1 0
-  %nop8876 = alloca i1, i1 0
-  %nop8877 = alloca i1, i1 0
-  %nop8878 = alloca i1, i1 0
-  %nop8879 = alloca i1, i1 0
-  %nop8880 = alloca i1, i1 0
-  %nop8881 = alloca i1, i1 0
-  %nop8882 = alloca i1, i1 0
-  %nop8883 = alloca i1, i1 0
-  %nop8884 = alloca i1, i1 0
-  %nop8885 = alloca i1, i1 0
-  %nop8886 = alloca i1, i1 0
-  %nop8887 = alloca i1, i1 0
-  %nop8888 = alloca i1, i1 0
-  %nop8889 = alloca i1, i1 0
-  %nop8890 = alloca i1, i1 0
-  %nop8891 = alloca i1, i1 0
-  %nop8892 = alloca i1, i1 0
-  %nop8893 = alloca i1, i1 0
-  %nop8894 = alloca i1, i1 0
-  %nop8895 = alloca i1, i1 0
-  %nop8896 = alloca i1, i1 0
-  %nop8897 = alloca i1, i1 0
-  %nop8898 = alloca i1, i1 0
-  %nop8899 = alloca i1, i1 0
-  %nop8900 = alloca i1, i1 0
-  %nop8901 = alloca i1, i1 0
-  %nop8902 = alloca i1, i1 0
-  %nop8903 = alloca i1, i1 0
-  %nop8904 = alloca i1, i1 0
-  %nop8905 = alloca i1, i1 0
-  %nop8906 = alloca i1, i1 0
-  %nop8907 = alloca i1, i1 0
-  %nop8908 = alloca i1, i1 0
-  %nop8909 = alloca i1, i1 0
-  %nop8910 = alloca i1, i1 0
-  %nop8911 = alloca i1, i1 0
-  %nop8912 = alloca i1, i1 0
-  %nop8913 = alloca i1, i1 0
-  %nop8914 = alloca i1, i1 0
-  %nop8915 = alloca i1, i1 0
-  %nop8916 = alloca i1, i1 0
-  %nop8917 = alloca i1, i1 0
-  %nop8918 = alloca i1, i1 0
-  %nop8919 = alloca i1, i1 0
-  %nop8920 = alloca i1, i1 0
-  %nop8921 = alloca i1, i1 0
-  %nop8922 = alloca i1, i1 0
-  %nop8923 = alloca i1, i1 0
-  %nop8924 = alloca i1, i1 0
-  %nop8925 = alloca i1, i1 0
-  %nop8926 = alloca i1, i1 0
-  %nop8927 = alloca i1, i1 0
-  %nop8928 = alloca i1, i1 0
-  %nop8929 = alloca i1, i1 0
-  %nop8930 = alloca i1, i1 0
-  %nop8931 = alloca i1, i1 0
-  %nop8932 = alloca i1, i1 0
-  %nop8933 = alloca i1, i1 0
-  %nop8934 = alloca i1, i1 0
-  %nop8935 = alloca i1, i1 0
-  %nop8936 = alloca i1, i1 0
-  %nop8937 = alloca i1, i1 0
-  %nop8938 = alloca i1, i1 0
-  %nop8939 = alloca i1, i1 0
-  %nop8940 = alloca i1, i1 0
-  %nop8941 = alloca i1, i1 0
-  %nop8942 = alloca i1, i1 0
-  %nop8943 = alloca i1, i1 0
-  %nop8944 = alloca i1, i1 0
-  %nop8945 = alloca i1, i1 0
-  %nop8946 = alloca i1, i1 0
-  %nop8947 = alloca i1, i1 0
-  %nop8948 = alloca i1, i1 0
-  %nop8949 = alloca i1, i1 0
-  %nop8950 = alloca i1, i1 0
-  %nop8951 = alloca i1, i1 0
-  %nop8952 = alloca i1, i1 0
-  %nop8953 = alloca i1, i1 0
-  %nop8954 = alloca i1, i1 0
-  %nop8955 = alloca i1, i1 0
-  %nop8956 = alloca i1, i1 0
-  %nop8957 = alloca i1, i1 0
-  %nop8958 = alloca i1, i1 0
-  %nop8959 = alloca i1, i1 0
-  %nop8960 = alloca i1, i1 0
-  %nop8961 = alloca i1, i1 0
-  %nop8962 = alloca i1, i1 0
-  %nop8963 = alloca i1, i1 0
-  %nop8964 = alloca i1, i1 0
-  %nop8965 = alloca i1, i1 0
-  %nop8966 = alloca i1, i1 0
-  %nop8967 = alloca i1, i1 0
-  %nop8968 = alloca i1, i1 0
-  %nop8969 = alloca i1, i1 0
-  %nop8970 = alloca i1, i1 0
-  %nop8971 = alloca i1, i1 0
-  %nop8972 = alloca i1, i1 0
-  %nop8973 = alloca i1, i1 0
-  %nop8974 = alloca i1, i1 0
-  %nop8975 = alloca i1, i1 0
-  %nop8976 = alloca i1, i1 0
-  %nop8977 = alloca i1, i1 0
-  %nop8978 = alloca i1, i1 0
-  %nop8979 = alloca i1, i1 0
-  %nop8980 = alloca i1, i1 0
-  %nop8981 = alloca i1, i1 0
-  %nop8982 = alloca i1, i1 0
-  %nop8983 = alloca i1, i1 0
-  %nop8984 = alloca i1, i1 0
-  %nop8985 = alloca i1, i1 0
-  %nop8986 = alloca i1, i1 0
-  %nop8987 = alloca i1, i1 0
-  %nop8988 = alloca i1, i1 0
-  %nop8989 = alloca i1, i1 0
-  %nop8990 = alloca i1, i1 0
-  %nop8991 = alloca i1, i1 0
-  %nop8992 = alloca i1, i1 0
-  %nop8993 = alloca i1, i1 0
-  %nop8994 = alloca i1, i1 0
-  %nop8995 = alloca i1, i1 0
-  %nop8996 = alloca i1, i1 0
-  %nop8997 = alloca i1, i1 0
-  %nop8998 = alloca i1, i1 0
-  %nop8999 = alloca i1, i1 0
-  %nop9000 = alloca i1, i1 0
-  %nop9001 = alloca i1, i1 0
-  %nop9002 = alloca i1, i1 0
-  %nop9003 = alloca i1, i1 0
-  %nop9004 = alloca i1, i1 0
-  %nop9005 = alloca i1, i1 0
-  %nop9006 = alloca i1, i1 0
-  %nop9007 = alloca i1, i1 0
-  %nop9008 = alloca i1, i1 0
-  %nop9009 = alloca i1, i1 0
-  %nop9010 = alloca i1, i1 0
-  %nop9011 = alloca i1, i1 0
-  %nop9012 = alloca i1, i1 0
-  %nop9013 = alloca i1, i1 0
-  %nop9014 = alloca i1, i1 0
-  %nop9015 = alloca i1, i1 0
-  %nop9016 = alloca i1, i1 0
-  %nop9017 = alloca i1, i1 0
-  %nop9018 = alloca i1, i1 0
-  %nop9019 = alloca i1, i1 0
-  %nop9020 = alloca i1, i1 0
-  %nop9021 = alloca i1, i1 0
-  %nop9022 = alloca i1, i1 0
-  %nop9023 = alloca i1, i1 0
-  %nop9024 = alloca i1, i1 0
-  %nop9025 = alloca i1, i1 0
-  %nop9026 = alloca i1, i1 0
-  %nop9027 = alloca i1, i1 0
-  %nop9028 = alloca i1, i1 0
-  %nop9029 = alloca i1, i1 0
-  %nop9030 = alloca i1, i1 0
-  %nop9031 = alloca i1, i1 0
-  %nop9032 = alloca i1, i1 0
-  %nop9033 = alloca i1, i1 0
-  %nop9034 = alloca i1, i1 0
-  %nop9035 = alloca i1, i1 0
-  %nop9036 = alloca i1, i1 0
-  %nop9037 = alloca i1, i1 0
-  %nop9038 = alloca i1, i1 0
-  %nop9039 = alloca i1, i1 0
-  %nop9040 = alloca i1, i1 0
-  %nop9041 = alloca i1, i1 0
-  %nop9042 = alloca i1, i1 0
-  %nop9043 = alloca i1, i1 0
-  %nop9044 = alloca i1, i1 0
-  %nop9045 = alloca i1, i1 0
-  %nop9046 = alloca i1, i1 0
-  %nop9047 = alloca i1, i1 0
-  %nop9048 = alloca i1, i1 0
-  %nop9049 = alloca i1, i1 0
-  %nop9050 = alloca i1, i1 0
-  %nop9051 = alloca i1, i1 0
-  %nop9052 = alloca i1, i1 0
-  %nop9053 = alloca i1, i1 0
-  %nop9054 = alloca i1, i1 0
-  %nop9055 = alloca i1, i1 0
-  %nop9056 = alloca i1, i1 0
-  %nop9057 = alloca i1, i1 0
-  %nop9058 = alloca i1, i1 0
-  %nop9059 = alloca i1, i1 0
-  %nop9060 = alloca i1, i1 0
-  %nop9061 = alloca i1, i1 0
-  %nop9062 = alloca i1, i1 0
-  %nop9063 = alloca i1, i1 0
-  %nop9064 = alloca i1, i1 0
-  %nop9065 = alloca i1, i1 0
-  %nop9066 = alloca i1, i1 0
-  %nop9067 = alloca i1, i1 0
-  %nop9068 = alloca i1, i1 0
-  %nop9069 = alloca i1, i1 0
-  %nop9070 = alloca i1, i1 0
-  %nop9071 = alloca i1, i1 0
-  %nop9072 = alloca i1, i1 0
-  %nop9073 = alloca i1, i1 0
-  %nop9074 = alloca i1, i1 0
-  %nop9075 = alloca i1, i1 0
-  %nop9076 = alloca i1, i1 0
-  %nop9077 = alloca i1, i1 0
-  %nop9078 = alloca i1, i1 0
-  %nop9079 = alloca i1, i1 0
-  %nop9080 = alloca i1, i1 0
-  %nop9081 = alloca i1, i1 0
-  %nop9082 = alloca i1, i1 0
-  %nop9083 = alloca i1, i1 0
-  %nop9084 = alloca i1, i1 0
-  %nop9085 = alloca i1, i1 0
-  %nop9086 = alloca i1, i1 0
-  %nop9087 = alloca i1, i1 0
-  %nop9088 = alloca i1, i1 0
-  %nop9089 = alloca i1, i1 0
-  %nop9090 = alloca i1, i1 0
-  %nop9091 = alloca i1, i1 0
-  %nop9092 = alloca i1, i1 0
-  %nop9093 = alloca i1, i1 0
-  %nop9094 = alloca i1, i1 0
-  %nop9095 = alloca i1, i1 0
-  %nop9096 = alloca i1, i1 0
-  %nop9097 = alloca i1, i1 0
-  %nop9098 = alloca i1, i1 0
-  %nop9099 = alloca i1, i1 0
-  %nop9100 = alloca i1, i1 0
-  %nop9101 = alloca i1, i1 0
-  %nop9102 = alloca i1, i1 0
-  %nop9103 = alloca i1, i1 0
-  %nop9104 = alloca i1, i1 0
-  %nop9105 = alloca i1, i1 0
-  %nop9106 = alloca i1, i1 0
-  %nop9107 = alloca i1, i1 0
-  %nop9108 = alloca i1, i1 0
-  %nop9109 = alloca i1, i1 0
-  %nop9110 = alloca i1, i1 0
-  %nop9111 = alloca i1, i1 0
-  %nop9112 = alloca i1, i1 0
-  %nop9113 = alloca i1, i1 0
-  %nop9114 = alloca i1, i1 0
-  %nop9115 = alloca i1, i1 0
-  %nop9116 = alloca i1, i1 0
-  %nop9117 = alloca i1, i1 0
-  %nop9118 = alloca i1, i1 0
-  %nop9119 = alloca i1, i1 0
-  %nop9120 = alloca i1, i1 0
-  %nop9121 = alloca i1, i1 0
-  %nop9122 = alloca i1, i1 0
-  %nop9123 = alloca i1, i1 0
-  %nop9124 = alloca i1, i1 0
-  %nop9125 = alloca i1, i1 0
-  %nop9126 = alloca i1, i1 0
-  %nop9127 = alloca i1, i1 0
-  %nop9128 = alloca i1, i1 0
-  %nop9129 = alloca i1, i1 0
-  %nop9130 = alloca i1, i1 0
-  %nop9131 = alloca i1, i1 0
-  %nop9132 = alloca i1, i1 0
-  %nop9133 = alloca i1, i1 0
-  %nop9134 = alloca i1, i1 0
-  %nop9135 = alloca i1, i1 0
-  %nop9136 = alloca i1, i1 0
-  %nop9137 = alloca i1, i1 0
-  %nop9138 = alloca i1, i1 0
-  %nop9139 = alloca i1, i1 0
-  %nop9140 = alloca i1, i1 0
-  %nop9141 = alloca i1, i1 0
-  %nop9142 = alloca i1, i1 0
-  %nop9143 = alloca i1, i1 0
-  %nop9144 = alloca i1, i1 0
-  %nop9145 = alloca i1, i1 0
-  %nop9146 = alloca i1, i1 0
-  %nop9147 = alloca i1, i1 0
-  %nop9148 = alloca i1, i1 0
-  %nop9149 = alloca i1, i1 0
-  %nop9150 = alloca i1, i1 0
-  %nop9151 = alloca i1, i1 0
-  %nop9152 = alloca i1, i1 0
-  %nop9153 = alloca i1, i1 0
-  %nop9154 = alloca i1, i1 0
-  %nop9155 = alloca i1, i1 0
-  %nop9156 = alloca i1, i1 0
-  %nop9157 = alloca i1, i1 0
-  %nop9158 = alloca i1, i1 0
-  %nop9159 = alloca i1, i1 0
-  %nop9160 = alloca i1, i1 0
-  %nop9161 = alloca i1, i1 0
-  %nop9162 = alloca i1, i1 0
-  %nop9163 = alloca i1, i1 0
-  %nop9164 = alloca i1, i1 0
-  %nop9165 = alloca i1, i1 0
-  %nop9166 = alloca i1, i1 0
-  %nop9167 = alloca i1, i1 0
-  %nop9168 = alloca i1, i1 0
-  %nop9169 = alloca i1, i1 0
-  %nop9170 = alloca i1, i1 0
-  %nop9171 = alloca i1, i1 0
-  %nop9172 = alloca i1, i1 0
-  %nop9173 = alloca i1, i1 0
-  %nop9174 = alloca i1, i1 0
-  %nop9175 = alloca i1, i1 0
-  %nop9176 = alloca i1, i1 0
-  %nop9177 = alloca i1, i1 0
-  %nop9178 = alloca i1, i1 0
-  %nop9179 = alloca i1, i1 0
-  %nop9180 = alloca i1, i1 0
-  %nop9181 = alloca i1, i1 0
-  %nop9182 = alloca i1, i1 0
-  %nop9183 = alloca i1, i1 0
-  %nop9184 = alloca i1, i1 0
-  %nop9185 = alloca i1, i1 0
-  %nop9186 = alloca i1, i1 0
-  %nop9187 = alloca i1, i1 0
-  %nop9188 = alloca i1, i1 0
-  %nop9189 = alloca i1, i1 0
-  %nop9190 = alloca i1, i1 0
-  %nop9191 = alloca i1, i1 0
-  %nop9192 = alloca i1, i1 0
-  %nop9193 = alloca i1, i1 0
-  %nop9194 = alloca i1, i1 0
-  %nop9195 = alloca i1, i1 0
-  %nop9196 = alloca i1, i1 0
-  %nop9197 = alloca i1, i1 0
-  %nop9198 = alloca i1, i1 0
-  %nop9199 = alloca i1, i1 0
-  %nop9200 = alloca i1, i1 0
-  %nop9201 = alloca i1, i1 0
-  %nop9202 = alloca i1, i1 0
-  %nop9203 = alloca i1, i1 0
-  %nop9204 = alloca i1, i1 0
-  %nop9205 = alloca i1, i1 0
-  %nop9206 = alloca i1, i1 0
-  %nop9207 = alloca i1, i1 0
-  %nop9208 = alloca i1, i1 0
-  %nop9209 = alloca i1, i1 0
-  %nop9210 = alloca i1, i1 0
-  %nop9211 = alloca i1, i1 0
-  %nop9212 = alloca i1, i1 0
-  %nop9213 = alloca i1, i1 0
-  %nop9214 = alloca i1, i1 0
-  %nop9215 = alloca i1, i1 0
-  %nop9216 = alloca i1, i1 0
-  %nop9217 = alloca i1, i1 0
-  %nop9218 = alloca i1, i1 0
-  %nop9219 = alloca i1, i1 0
-  %nop9220 = alloca i1, i1 0
-  %nop9221 = alloca i1, i1 0
-  %nop9222 = alloca i1, i1 0
-  %nop9223 = alloca i1, i1 0
-  %nop9224 = alloca i1, i1 0
-  %nop9225 = alloca i1, i1 0
-  %nop9226 = alloca i1, i1 0
-  %nop9227 = alloca i1, i1 0
-  %nop9228 = alloca i1, i1 0
-  %nop9229 = alloca i1, i1 0
-  %nop9230 = alloca i1, i1 0
-  %nop9231 = alloca i1, i1 0
-  %nop9232 = alloca i1, i1 0
-  %nop9233 = alloca i1, i1 0
-  %nop9234 = alloca i1, i1 0
-  %nop9235 = alloca i1, i1 0
-  %nop9236 = alloca i1, i1 0
-  %nop9237 = alloca i1, i1 0
-  %nop9238 = alloca i1, i1 0
-  %nop9239 = alloca i1, i1 0
-  %nop9240 = alloca i1, i1 0
-  %nop9241 = alloca i1, i1 0
-  %nop9242 = alloca i1, i1 0
-  %nop9243 = alloca i1, i1 0
-  %nop9244 = alloca i1, i1 0
-  %nop9245 = alloca i1, i1 0
-  %nop9246 = alloca i1, i1 0
-  %nop9247 = alloca i1, i1 0
-  %nop9248 = alloca i1, i1 0
-  %nop9249 = alloca i1, i1 0
-  %nop9250 = alloca i1, i1 0
-  %nop9251 = alloca i1, i1 0
-  %nop9252 = alloca i1, i1 0
-  %nop9253 = alloca i1, i1 0
-  %nop9254 = alloca i1, i1 0
-  %nop9255 = alloca i1, i1 0
-  %nop9256 = alloca i1, i1 0
-  %nop9257 = alloca i1, i1 0
-  %nop9258 = alloca i1, i1 0
-  %nop9259 = alloca i1, i1 0
-  %nop9260 = alloca i1, i1 0
-  %nop9261 = alloca i1, i1 0
-  %nop9262 = alloca i1, i1 0
-  %nop9263 = alloca i1, i1 0
-  %nop9264 = alloca i1, i1 0
-  %nop9265 = alloca i1, i1 0
-  %nop9266 = alloca i1, i1 0
-  %nop9267 = alloca i1, i1 0
-  %nop9268 = alloca i1, i1 0
-  %nop9269 = alloca i1, i1 0
-  %nop9270 = alloca i1, i1 0
-  %nop9271 = alloca i1, i1 0
-  %nop9272 = alloca i1, i1 0
-  %nop9273 = alloca i1, i1 0
-  %nop9274 = alloca i1, i1 0
-  %nop9275 = alloca i1, i1 0
-  %nop9276 = alloca i1, i1 0
-  %nop9277 = alloca i1, i1 0
-  %nop9278 = alloca i1, i1 0
-  %nop9279 = alloca i1, i1 0
-  %nop9280 = alloca i1, i1 0
-  %nop9281 = alloca i1, i1 0
-  %nop9282 = alloca i1, i1 0
-  %nop9283 = alloca i1, i1 0
-  %nop9284 = alloca i1, i1 0
-  %nop9285 = alloca i1, i1 0
-  %nop9286 = alloca i1, i1 0
-  %nop9287 = alloca i1, i1 0
-  %nop9288 = alloca i1, i1 0
-  %nop9289 = alloca i1, i1 0
-  %nop9290 = alloca i1, i1 0
-  %nop9291 = alloca i1, i1 0
-  %nop9292 = alloca i1, i1 0
-  %nop9293 = alloca i1, i1 0
-  %nop9294 = alloca i1, i1 0
-  %nop9295 = alloca i1, i1 0
-  %nop9296 = alloca i1, i1 0
-  %nop9297 = alloca i1, i1 0
-  %nop9298 = alloca i1, i1 0
-  %nop9299 = alloca i1, i1 0
-  %nop9300 = alloca i1, i1 0
-  %nop9301 = alloca i1, i1 0
-  %nop9302 = alloca i1, i1 0
-  %nop9303 = alloca i1, i1 0
-  %nop9304 = alloca i1, i1 0
-  %nop9305 = alloca i1, i1 0
-  %nop9306 = alloca i1, i1 0
-  %nop9307 = alloca i1, i1 0
-  %nop9308 = alloca i1, i1 0
-  %nop9309 = alloca i1, i1 0
-  %nop9310 = alloca i1, i1 0
-  %nop9311 = alloca i1, i1 0
-  %nop9312 = alloca i1, i1 0
-  %nop9313 = alloca i1, i1 0
-  %nop9314 = alloca i1, i1 0
-  %nop9315 = alloca i1, i1 0
-  %nop9316 = alloca i1, i1 0
-  %nop9317 = alloca i1, i1 0
-  %nop9318 = alloca i1, i1 0
-  %nop9319 = alloca i1, i1 0
-  %nop9320 = alloca i1, i1 0
-  %nop9321 = alloca i1, i1 0
-  %nop9322 = alloca i1, i1 0
-  %nop9323 = alloca i1, i1 0
-  %nop9324 = alloca i1, i1 0
-  %nop9325 = alloca i1, i1 0
-  %nop9326 = alloca i1, i1 0
-  %nop9327 = alloca i1, i1 0
-  %nop9328 = alloca i1, i1 0
-  %nop9329 = alloca i1, i1 0
-  %nop9330 = alloca i1, i1 0
-  %nop9331 = alloca i1, i1 0
-  %nop9332 = alloca i1, i1 0
-  %nop9333 = alloca i1, i1 0
-  %nop9334 = alloca i1, i1 0
-  %nop9335 = alloca i1, i1 0
-  %nop9336 = alloca i1, i1 0
-  %nop9337 = alloca i1, i1 0
-  %nop9338 = alloca i1, i1 0
-  %nop9339 = alloca i1, i1 0
-  %nop9340 = alloca i1, i1 0
-  %nop9341 = alloca i1, i1 0
-  %nop9342 = alloca i1, i1 0
-  %nop9343 = alloca i1, i1 0
-  %nop9344 = alloca i1, i1 0
-  %nop9345 = alloca i1, i1 0
-  %nop9346 = alloca i1, i1 0
-  %nop9347 = alloca i1, i1 0
-  %nop9348 = alloca i1, i1 0
-  %nop9349 = alloca i1, i1 0
-  %nop9350 = alloca i1, i1 0
-  %nop9351 = alloca i1, i1 0
-  %nop9352 = alloca i1, i1 0
-  %nop9353 = alloca i1, i1 0
-  %nop9354 = alloca i1, i1 0
-  %nop9355 = alloca i1, i1 0
-  %nop9356 = alloca i1, i1 0
-  %nop9357 = alloca i1, i1 0
-  %nop9358 = alloca i1, i1 0
-  %nop9359 = alloca i1, i1 0
-  %nop9360 = alloca i1, i1 0
-  %nop9361 = alloca i1, i1 0
-  %nop9362 = alloca i1, i1 0
-  %nop9363 = alloca i1, i1 0
-  %nop9364 = alloca i1, i1 0
-  %nop9365 = alloca i1, i1 0
-  %nop9366 = alloca i1, i1 0
-  %nop9367 = alloca i1, i1 0
-  %nop9368 = alloca i1, i1 0
-  %nop9369 = alloca i1, i1 0
-  %nop9370 = alloca i1, i1 0
-  %nop9371 = alloca i1, i1 0
-  %nop9372 = alloca i1, i1 0
-  %nop9373 = alloca i1, i1 0
-  %nop9374 = alloca i1, i1 0
-  %nop9375 = alloca i1, i1 0
-  %nop9376 = alloca i1, i1 0
-  %nop9377 = alloca i1, i1 0
-  %nop9378 = alloca i1, i1 0
-  %nop9379 = alloca i1, i1 0
-  %nop9380 = alloca i1, i1 0
-  %nop9381 = alloca i1, i1 0
-  %nop9382 = alloca i1, i1 0
-  %nop9383 = alloca i1, i1 0
-  %nop9384 = alloca i1, i1 0
-  %nop9385 = alloca i1, i1 0
-  %nop9386 = alloca i1, i1 0
-  %nop9387 = alloca i1, i1 0
-  %nop9388 = alloca i1, i1 0
-  %nop9389 = alloca i1, i1 0
-  %nop9390 = alloca i1, i1 0
-  %nop9391 = alloca i1, i1 0
-  %nop9392 = alloca i1, i1 0
-  %nop9393 = alloca i1, i1 0
-  %nop9394 = alloca i1, i1 0
-  %nop9395 = alloca i1, i1 0
-  %nop9396 = alloca i1, i1 0
-  %nop9397 = alloca i1, i1 0
-  %nop9398 = alloca i1, i1 0
-  %nop9399 = alloca i1, i1 0
-  %nop9400 = alloca i1, i1 0
-  %nop9401 = alloca i1, i1 0
-  %nop9402 = alloca i1, i1 0
-  %nop9403 = alloca i1, i1 0
-  %nop9404 = alloca i1, i1 0
-  %nop9405 = alloca i1, i1 0
-  %nop9406 = alloca i1, i1 0
-  %nop9407 = alloca i1, i1 0
-  %nop9408 = alloca i1, i1 0
-  %nop9409 = alloca i1, i1 0
-  %nop9410 = alloca i1, i1 0
-  %nop9411 = alloca i1, i1 0
-  %nop9412 = alloca i1, i1 0
-  %nop9413 = alloca i1, i1 0
-  %nop9414 = alloca i1, i1 0
-  %nop9415 = alloca i1, i1 0
-  %nop9416 = alloca i1, i1 0
-  %nop9417 = alloca i1, i1 0
-  %nop9418 = alloca i1, i1 0
-  %nop9419 = alloca i1, i1 0
-  %nop9420 = alloca i1, i1 0
-  %nop9421 = alloca i1, i1 0
-  %nop9422 = alloca i1, i1 0
-  %nop9423 = alloca i1, i1 0
-  %nop9424 = alloca i1, i1 0
-  %nop9425 = alloca i1, i1 0
-  %nop9426 = alloca i1, i1 0
-  %nop9427 = alloca i1, i1 0
-  %nop9428 = alloca i1, i1 0
-  %nop9429 = alloca i1, i1 0
-  %nop9430 = alloca i1, i1 0
-  %nop9431 = alloca i1, i1 0
-  %nop9432 = alloca i1, i1 0
-  %nop9433 = alloca i1, i1 0
-  %nop9434 = alloca i1, i1 0
-  %nop9435 = alloca i1, i1 0
-  %nop9436 = alloca i1, i1 0
-  %nop9437 = alloca i1, i1 0
-  %nop9438 = alloca i1, i1 0
-  %nop9439 = alloca i1, i1 0
-  %nop9440 = alloca i1, i1 0
-  %nop9441 = alloca i1, i1 0
-  %nop9442 = alloca i1, i1 0
-  %nop9443 = alloca i1, i1 0
-  %nop9444 = alloca i1, i1 0
-  %nop9445 = alloca i1, i1 0
-  %nop9446 = alloca i1, i1 0
-  %nop9447 = alloca i1, i1 0
-  %nop9448 = alloca i1, i1 0
-  %nop9449 = alloca i1, i1 0
-  %nop9450 = alloca i1, i1 0
-  %nop9451 = alloca i1, i1 0
-  %nop9452 = alloca i1, i1 0
-  %nop9453 = alloca i1, i1 0
-  %nop9454 = alloca i1, i1 0
-  %nop9455 = alloca i1, i1 0
-  %nop9456 = alloca i1, i1 0
-  %nop9457 = alloca i1, i1 0
-  %nop9458 = alloca i1, i1 0
-  %nop9459 = alloca i1, i1 0
-  %nop9460 = alloca i1, i1 0
-  %nop9461 = alloca i1, i1 0
-  %nop9462 = alloca i1, i1 0
-  %nop9463 = alloca i1, i1 0
-  %nop9464 = alloca i1, i1 0
-  %nop9465 = alloca i1, i1 0
-  %nop9466 = alloca i1, i1 0
-  %nop9467 = alloca i1, i1 0
-  %nop9468 = alloca i1, i1 0
-  %nop9469 = alloca i1, i1 0
-  %nop9470 = alloca i1, i1 0
-  %nop9471 = alloca i1, i1 0
-  %nop9472 = alloca i1, i1 0
-  %nop9473 = alloca i1, i1 0
-  %nop9474 = alloca i1, i1 0
-  %nop9475 = alloca i1, i1 0
-  %nop9476 = alloca i1, i1 0
-  %nop9477 = alloca i1, i1 0
-  %nop9478 = alloca i1, i1 0
-  %nop9479 = alloca i1, i1 0
-  %nop9480 = alloca i1, i1 0
-  %nop9481 = alloca i1, i1 0
-  %nop9482 = alloca i1, i1 0
-  %nop9483 = alloca i1, i1 0
-  %nop9484 = alloca i1, i1 0
-  %nop9485 = alloca i1, i1 0
-  %nop9486 = alloca i1, i1 0
-  %nop9487 = alloca i1, i1 0
-  %nop9488 = alloca i1, i1 0
-  %nop9489 = alloca i1, i1 0
-  %nop9490 = alloca i1, i1 0
-  %nop9491 = alloca i1, i1 0
-  %nop9492 = alloca i1, i1 0
-  %nop9493 = alloca i1, i1 0
-  %nop9494 = alloca i1, i1 0
-  %nop9495 = alloca i1, i1 0
-  %nop9496 = alloca i1, i1 0
-  %nop9497 = alloca i1, i1 0
-  %nop9498 = alloca i1, i1 0
-  %nop9499 = alloca i1, i1 0
-  %nop9500 = alloca i1, i1 0
-  %nop9501 = alloca i1, i1 0
-  %nop9502 = alloca i1, i1 0
-  %nop9503 = alloca i1, i1 0
-  %nop9504 = alloca i1, i1 0
-  %nop9505 = alloca i1, i1 0
-  %nop9506 = alloca i1, i1 0
-  %nop9507 = alloca i1, i1 0
-  %nop9508 = alloca i1, i1 0
-  %nop9509 = alloca i1, i1 0
-  %nop9510 = alloca i1, i1 0
-  %nop9511 = alloca i1, i1 0
-  %nop9512 = alloca i1, i1 0
-  %nop9513 = alloca i1, i1 0
-  %nop9514 = alloca i1, i1 0
-  %nop9515 = alloca i1, i1 0
-  %nop9516 = alloca i1, i1 0
-  %nop9517 = alloca i1, i1 0
-  %nop9518 = alloca i1, i1 0
-  %nop9519 = alloca i1, i1 0
-  %nop9520 = alloca i1, i1 0
-  %nop9521 = alloca i1, i1 0
-  %nop9522 = alloca i1, i1 0
-  %nop9523 = alloca i1, i1 0
-  %nop9524 = alloca i1, i1 0
-  %nop9525 = alloca i1, i1 0
-  %nop9526 = alloca i1, i1 0
-  %nop9527 = alloca i1, i1 0
-  %nop9528 = alloca i1, i1 0
-  %nop9529 = alloca i1, i1 0
-  %nop9530 = alloca i1, i1 0
-  %nop9531 = alloca i1, i1 0
-  %nop9532 = alloca i1, i1 0
-  %nop9533 = alloca i1, i1 0
-  %nop9534 = alloca i1, i1 0
-  %nop9535 = alloca i1, i1 0
-  %nop9536 = alloca i1, i1 0
-  %nop9537 = alloca i1, i1 0
-  %nop9538 = alloca i1, i1 0
-  %nop9539 = alloca i1, i1 0
-  %nop9540 = alloca i1, i1 0
-  %nop9541 = alloca i1, i1 0
-  %nop9542 = alloca i1, i1 0
-  %nop9543 = alloca i1, i1 0
-  %nop9544 = alloca i1, i1 0
-  %nop9545 = alloca i1, i1 0
-  %nop9546 = alloca i1, i1 0
-  %nop9547 = alloca i1, i1 0
-  %nop9548 = alloca i1, i1 0
-  %nop9549 = alloca i1, i1 0
-  %nop9550 = alloca i1, i1 0
-  %nop9551 = alloca i1, i1 0
-  %nop9552 = alloca i1, i1 0
-  %nop9553 = alloca i1, i1 0
-  %nop9554 = alloca i1, i1 0
-  %nop9555 = alloca i1, i1 0
-  %nop9556 = alloca i1, i1 0
-  %nop9557 = alloca i1, i1 0
-  %nop9558 = alloca i1, i1 0
-  %nop9559 = alloca i1, i1 0
-  %nop9560 = alloca i1, i1 0
-  %nop9561 = alloca i1, i1 0
-  %nop9562 = alloca i1, i1 0
-  %nop9563 = alloca i1, i1 0
-  %nop9564 = alloca i1, i1 0
-  %nop9565 = alloca i1, i1 0
-  %nop9566 = alloca i1, i1 0
-  %nop9567 = alloca i1, i1 0
-  %nop9568 = alloca i1, i1 0
-  %nop9569 = alloca i1, i1 0
-  %nop9570 = alloca i1, i1 0
-  %nop9571 = alloca i1, i1 0
-  %nop9572 = alloca i1, i1 0
-  %nop9573 = alloca i1, i1 0
-  %nop9574 = alloca i1, i1 0
-  %nop9575 = alloca i1, i1 0
-  %nop9576 = alloca i1, i1 0
-  %nop9577 = alloca i1, i1 0
-  %nop9578 = alloca i1, i1 0
-  %nop9579 = alloca i1, i1 0
-  %nop9580 = alloca i1, i1 0
-  %nop9581 = alloca i1, i1 0
-  %nop9582 = alloca i1, i1 0
-  %nop9583 = alloca i1, i1 0
-  %nop9584 = alloca i1, i1 0
-  %nop9585 = alloca i1, i1 0
-  %nop9586 = alloca i1, i1 0
-  %nop9587 = alloca i1, i1 0
-  %nop9588 = alloca i1, i1 0
-  %nop9589 = alloca i1, i1 0
-  %nop9590 = alloca i1, i1 0
-  %nop9591 = alloca i1, i1 0
-  %nop9592 = alloca i1, i1 0
-  %nop9593 = alloca i1, i1 0
-  %nop9594 = alloca i1, i1 0
-  %nop9595 = alloca i1, i1 0
-  %nop9596 = alloca i1, i1 0
-  %nop9597 = alloca i1, i1 0
-  %nop9598 = alloca i1, i1 0
-  %nop9599 = alloca i1, i1 0
-  %nop9600 = alloca i1, i1 0
-  %nop9601 = alloca i1, i1 0
-  %nop9602 = alloca i1, i1 0
-  %nop9603 = alloca i1, i1 0
-  %nop9604 = alloca i1, i1 0
-  %nop9605 = alloca i1, i1 0
-  %nop9606 = alloca i1, i1 0
-  %nop9607 = alloca i1, i1 0
-  %nop9608 = alloca i1, i1 0
-  %nop9609 = alloca i1, i1 0
-  %nop9610 = alloca i1, i1 0
-  %nop9611 = alloca i1, i1 0
-  %nop9612 = alloca i1, i1 0
-  %nop9613 = alloca i1, i1 0
-  %nop9614 = alloca i1, i1 0
-  %nop9615 = alloca i1, i1 0
-  %nop9616 = alloca i1, i1 0
-  %nop9617 = alloca i1, i1 0
-  %nop9618 = alloca i1, i1 0
-  %nop9619 = alloca i1, i1 0
-  %nop9620 = alloca i1, i1 0
-  %nop9621 = alloca i1, i1 0
-  %nop9622 = alloca i1, i1 0
-  %nop9623 = alloca i1, i1 0
-  %nop9624 = alloca i1, i1 0
-  %nop9625 = alloca i1, i1 0
-  %nop9626 = alloca i1, i1 0
-  %nop9627 = alloca i1, i1 0
-  %nop9628 = alloca i1, i1 0
-  %nop9629 = alloca i1, i1 0
-  %nop9630 = alloca i1, i1 0
-  %nop9631 = alloca i1, i1 0
-  %nop9632 = alloca i1, i1 0
-  %nop9633 = alloca i1, i1 0
-  %nop9634 = alloca i1, i1 0
-  %nop9635 = alloca i1, i1 0
-  %nop9636 = alloca i1, i1 0
-  %nop9637 = alloca i1, i1 0
-  %nop9638 = alloca i1, i1 0
-  %nop9639 = alloca i1, i1 0
-  %nop9640 = alloca i1, i1 0
-  %nop9641 = alloca i1, i1 0
-  %nop9642 = alloca i1, i1 0
-  %nop9643 = alloca i1, i1 0
-  %nop9644 = alloca i1, i1 0
-  %nop9645 = alloca i1, i1 0
-  %nop9646 = alloca i1, i1 0
-  %nop9647 = alloca i1, i1 0
-  %nop9648 = alloca i1, i1 0
-  %nop9649 = alloca i1, i1 0
-  %nop9650 = alloca i1, i1 0
-  %nop9651 = alloca i1, i1 0
-  %nop9652 = alloca i1, i1 0
-  %nop9653 = alloca i1, i1 0
-  %nop9654 = alloca i1, i1 0
-  %nop9655 = alloca i1, i1 0
-  %nop9656 = alloca i1, i1 0
-  %nop9657 = alloca i1, i1 0
-  %nop9658 = alloca i1, i1 0
-  %nop9659 = alloca i1, i1 0
-  %nop9660 = alloca i1, i1 0
-  %nop9661 = alloca i1, i1 0
-  %nop9662 = alloca i1, i1 0
-  %nop9663 = alloca i1, i1 0
-  %nop9664 = alloca i1, i1 0
-  %nop9665 = alloca i1, i1 0
-  %nop9666 = alloca i1, i1 0
-  %nop9667 = alloca i1, i1 0
-  %nop9668 = alloca i1, i1 0
-  %nop9669 = alloca i1, i1 0
-  %nop9670 = alloca i1, i1 0
-  %nop9671 = alloca i1, i1 0
-  %nop9672 = alloca i1, i1 0
-  %nop9673 = alloca i1, i1 0
-  %nop9674 = alloca i1, i1 0
-  %nop9675 = alloca i1, i1 0
-  %nop9676 = alloca i1, i1 0
-  %nop9677 = alloca i1, i1 0
-  %nop9678 = alloca i1, i1 0
-  %nop9679 = alloca i1, i1 0
-  %nop9680 = alloca i1, i1 0
-  %nop9681 = alloca i1, i1 0
-  %nop9682 = alloca i1, i1 0
-  %nop9683 = alloca i1, i1 0
-  %nop9684 = alloca i1, i1 0
-  %nop9685 = alloca i1, i1 0
-  %nop9686 = alloca i1, i1 0
-  %nop9687 = alloca i1, i1 0
-  %nop9688 = alloca i1, i1 0
-  %nop9689 = alloca i1, i1 0
-  %nop9690 = alloca i1, i1 0
-  %nop9691 = alloca i1, i1 0
-  %nop9692 = alloca i1, i1 0
-  %nop9693 = alloca i1, i1 0
-  %nop9694 = alloca i1, i1 0
-  %nop9695 = alloca i1, i1 0
-  %nop9696 = alloca i1, i1 0
-  %nop9697 = alloca i1, i1 0
-  %nop9698 = alloca i1, i1 0
-  %nop9699 = alloca i1, i1 0
-  %nop9700 = alloca i1, i1 0
-  %nop9701 = alloca i1, i1 0
-  %nop9702 = alloca i1, i1 0
-  %nop9703 = alloca i1, i1 0
-  %nop9704 = alloca i1, i1 0
-  %nop9705 = alloca i1, i1 0
-  %nop9706 = alloca i1, i1 0
-  %nop9707 = alloca i1, i1 0
-  %nop9708 = alloca i1, i1 0
-  %nop9709 = alloca i1, i1 0
-  %nop9710 = alloca i1, i1 0
-  %nop9711 = alloca i1, i1 0
-  %nop9712 = alloca i1, i1 0
-  %nop9713 = alloca i1, i1 0
-  %nop9714 = alloca i1, i1 0
-  %nop9715 = alloca i1, i1 0
-  %nop9716 = alloca i1, i1 0
-  %nop9717 = alloca i1, i1 0
-  %nop9718 = alloca i1, i1 0
-  %nop9719 = alloca i1, i1 0
-  %nop9720 = alloca i1, i1 0
-  %nop9721 = alloca i1, i1 0
-  %nop9722 = alloca i1, i1 0
-  %nop9723 = alloca i1, i1 0
-  %nop9724 = alloca i1, i1 0
-  %nop9725 = alloca i1, i1 0
-  %nop9726 = alloca i1, i1 0
-  %nop9727 = alloca i1, i1 0
-  %nop9728 = alloca i1, i1 0
-  %nop9729 = alloca i1, i1 0
-  %nop9730 = alloca i1, i1 0
-  %nop9731 = alloca i1, i1 0
-  %nop9732 = alloca i1, i1 0
-  %nop9733 = alloca i1, i1 0
-  %nop9734 = alloca i1, i1 0
-  %nop9735 = alloca i1, i1 0
-  %nop9736 = alloca i1, i1 0
-  %nop9737 = alloca i1, i1 0
-  %nop9738 = alloca i1, i1 0
-  %nop9739 = alloca i1, i1 0
-  %nop9740 = alloca i1, i1 0
-  %nop9741 = alloca i1, i1 0
-  %nop9742 = alloca i1, i1 0
-  %nop9743 = alloca i1, i1 0
-  %nop9744 = alloca i1, i1 0
-  %nop9745 = alloca i1, i1 0
-  %nop9746 = alloca i1, i1 0
-  %nop9747 = alloca i1, i1 0
-  %nop9748 = alloca i1, i1 0
-  %nop9749 = alloca i1, i1 0
-  %nop9750 = alloca i1, i1 0
-  %nop9751 = alloca i1, i1 0
-  %nop9752 = alloca i1, i1 0
-  %nop9753 = alloca i1, i1 0
-  %nop9754 = alloca i1, i1 0
-  %nop9755 = alloca i1, i1 0
-  %nop9756 = alloca i1, i1 0
-  %nop9757 = alloca i1, i1 0
-  %nop9758 = alloca i1, i1 0
-  %nop9759 = alloca i1, i1 0
-  %nop9760 = alloca i1, i1 0
-  %nop9761 = alloca i1, i1 0
-  %nop9762 = alloca i1, i1 0
-  %nop9763 = alloca i1, i1 0
-  %nop9764 = alloca i1, i1 0
-  %nop9765 = alloca i1, i1 0
-  %nop9766 = alloca i1, i1 0
-  %nop9767 = alloca i1, i1 0
-  %nop9768 = alloca i1, i1 0
-  %nop9769 = alloca i1, i1 0
-  %nop9770 = alloca i1, i1 0
-  %nop9771 = alloca i1, i1 0
-  %nop9772 = alloca i1, i1 0
-  %nop9773 = alloca i1, i1 0
-  %nop9774 = alloca i1, i1 0
-  %nop9775 = alloca i1, i1 0
-  %nop9776 = alloca i1, i1 0
-  %nop9777 = alloca i1, i1 0
-  %nop9778 = alloca i1, i1 0
-  %nop9779 = alloca i1, i1 0
-  %nop9780 = alloca i1, i1 0
-  %nop9781 = alloca i1, i1 0
-  %nop9782 = alloca i1, i1 0
-  %nop9783 = alloca i1, i1 0
-  %nop9784 = alloca i1, i1 0
-  %nop9785 = alloca i1, i1 0
-  %nop9786 = alloca i1, i1 0
-  %nop9787 = alloca i1, i1 0
-  %nop9788 = alloca i1, i1 0
-  %nop9789 = alloca i1, i1 0
-  %nop9790 = alloca i1, i1 0
-  %nop9791 = alloca i1, i1 0
-  %nop9792 = alloca i1, i1 0
-  %nop9793 = alloca i1, i1 0
-  %nop9794 = alloca i1, i1 0
-  %nop9795 = alloca i1, i1 0
-  %nop9796 = alloca i1, i1 0
-  %nop9797 = alloca i1, i1 0
-  %nop9798 = alloca i1, i1 0
-  %nop9799 = alloca i1, i1 0
-  %nop9800 = alloca i1, i1 0
-  %nop9801 = alloca i1, i1 0
-  %nop9802 = alloca i1, i1 0
-  %nop9803 = alloca i1, i1 0
-  %nop9804 = alloca i1, i1 0
-  %nop9805 = alloca i1, i1 0
-  %nop9806 = alloca i1, i1 0
-  %nop9807 = alloca i1, i1 0
-  %nop9808 = alloca i1, i1 0
-  %nop9809 = alloca i1, i1 0
-  %nop9810 = alloca i1, i1 0
-  %nop9811 = alloca i1, i1 0
-  %nop9812 = alloca i1, i1 0
-  %nop9813 = alloca i1, i1 0
-  %nop9814 = alloca i1, i1 0
-  %nop9815 = alloca i1, i1 0
-  %nop9816 = alloca i1, i1 0
-  %nop9817 = alloca i1, i1 0
-  %nop9818 = alloca i1, i1 0
-  %nop9819 = alloca i1, i1 0
-  %nop9820 = alloca i1, i1 0
-  %nop9821 = alloca i1, i1 0
-  %nop9822 = alloca i1, i1 0
-  %nop9823 = alloca i1, i1 0
-  %nop9824 = alloca i1, i1 0
-  %nop9825 = alloca i1, i1 0
-  %nop9826 = alloca i1, i1 0
-  %nop9827 = alloca i1, i1 0
-  %nop9828 = alloca i1, i1 0
-  %nop9829 = alloca i1, i1 0
-  %nop9830 = alloca i1, i1 0
-  %nop9831 = alloca i1, i1 0
-  %nop9832 = alloca i1, i1 0
-  %nop9833 = alloca i1, i1 0
-  %nop9834 = alloca i1, i1 0
-  %nop9835 = alloca i1, i1 0
-  %nop9836 = alloca i1, i1 0
-  %nop9837 = alloca i1, i1 0
-  %nop9838 = alloca i1, i1 0
-  %nop9839 = alloca i1, i1 0
-  %nop9840 = alloca i1, i1 0
-  %nop9841 = alloca i1, i1 0
-  %nop9842 = alloca i1, i1 0
-  %nop9843 = alloca i1, i1 0
-  %nop9844 = alloca i1, i1 0
-  %nop9845 = alloca i1, i1 0
-  %nop9846 = alloca i1, i1 0
-  %nop9847 = alloca i1, i1 0
-  %nop9848 = alloca i1, i1 0
-  %nop9849 = alloca i1, i1 0
-  %nop9850 = alloca i1, i1 0
-  %nop9851 = alloca i1, i1 0
-  %nop9852 = alloca i1, i1 0
-  %nop9853 = alloca i1, i1 0
-  %nop9854 = alloca i1, i1 0
-  %nop9855 = alloca i1, i1 0
-  %nop9856 = alloca i1, i1 0
-  %nop9857 = alloca i1, i1 0
-  %nop9858 = alloca i1, i1 0
-  %nop9859 = alloca i1, i1 0
-  %nop9860 = alloca i1, i1 0
-  %nop9861 = alloca i1, i1 0
-  %nop9862 = alloca i1, i1 0
-  %nop9863 = alloca i1, i1 0
-  %nop9864 = alloca i1, i1 0
-  %nop9865 = alloca i1, i1 0
-  %nop9866 = alloca i1, i1 0
-  %nop9867 = alloca i1, i1 0
-  %nop9868 = alloca i1, i1 0
-  %nop9869 = alloca i1, i1 0
-  %nop9870 = alloca i1, i1 0
-  %nop9871 = alloca i1, i1 0
-  %nop9872 = alloca i1, i1 0
-  %nop9873 = alloca i1, i1 0
-  %nop9874 = alloca i1, i1 0
-  %nop9875 = alloca i1, i1 0
-  %nop9876 = alloca i1, i1 0
-  %nop9877 = alloca i1, i1 0
-  %nop9878 = alloca i1, i1 0
-  %nop9879 = alloca i1, i1 0
-  %nop9880 = alloca i1, i1 0
-  %nop9881 = alloca i1, i1 0
-  %nop9882 = alloca i1, i1 0
-  %nop9883 = alloca i1, i1 0
-  %nop9884 = alloca i1, i1 0
-  %nop9885 = alloca i1, i1 0
-  %nop9886 = alloca i1, i1 0
-  %nop9887 = alloca i1, i1 0
-  %nop9888 = alloca i1, i1 0
-  %nop9889 = alloca i1, i1 0
-  %nop9890 = alloca i1, i1 0
-  %nop9891 = alloca i1, i1 0
-  %nop9892 = alloca i1, i1 0
-  %nop9893 = alloca i1, i1 0
-  %nop9894 = alloca i1, i1 0
-  %nop9895 = alloca i1, i1 0
-  %nop9896 = alloca i1, i1 0
-  %nop9897 = alloca i1, i1 0
-  %nop9898 = alloca i1, i1 0
-  %nop9899 = alloca i1, i1 0
-  %nop9900 = alloca i1, i1 0
-  %nop9901 = alloca i1, i1 0
-  %nop9902 = alloca i1, i1 0
-  %nop9903 = alloca i1, i1 0
-  %nop9904 = alloca i1, i1 0
-  %nop9905 = alloca i1, i1 0
-  %nop9906 = alloca i1, i1 0
-  %nop9907 = alloca i1, i1 0
-  %nop9908 = alloca i1, i1 0
-  %nop9909 = alloca i1, i1 0
-  %nop9910 = alloca i1, i1 0
-  %nop9911 = alloca i1, i1 0
-  %nop9912 = alloca i1, i1 0
-  %nop9913 = alloca i1, i1 0
-  %nop9914 = alloca i1, i1 0
-  %nop9915 = alloca i1, i1 0
-  %nop9916 = alloca i1, i1 0
-  %nop9917 = alloca i1, i1 0
-  %nop9918 = alloca i1, i1 0
-  %nop9919 = alloca i1, i1 0
-  %nop9920 = alloca i1, i1 0
-  %nop9921 = alloca i1, i1 0
-  %nop9922 = alloca i1, i1 0
-  %nop9923 = alloca i1, i1 0
-  %nop9924 = alloca i1, i1 0
-  %nop9925 = alloca i1, i1 0
-  %nop9926 = alloca i1, i1 0
-  %nop9927 = alloca i1, i1 0
-  %nop9928 = alloca i1, i1 0
-  %nop9929 = alloca i1, i1 0
-  %nop9930 = alloca i1, i1 0
-  %nop9931 = alloca i1, i1 0
-  %nop9932 = alloca i1, i1 0
-  %nop9933 = alloca i1, i1 0
-  %nop9934 = alloca i1, i1 0
-  %nop9935 = alloca i1, i1 0
-  %nop9936 = alloca i1, i1 0
-  %nop9937 = alloca i1, i1 0
-  %nop9938 = alloca i1, i1 0
-  %nop9939 = alloca i1, i1 0
-  %nop9940 = alloca i1, i1 0
-  %nop9941 = alloca i1, i1 0
-  %nop9942 = alloca i1, i1 0
-  %nop9943 = alloca i1, i1 0
-  %nop9944 = alloca i1, i1 0
-  %nop9945 = alloca i1, i1 0
-  %nop9946 = alloca i1, i1 0
-  %nop9947 = alloca i1, i1 0
-  %nop9948 = alloca i1, i1 0
-  %nop9949 = alloca i1, i1 0
-  %nop9950 = alloca i1, i1 0
-  %nop9951 = alloca i1, i1 0
-  %nop9952 = alloca i1, i1 0
-  %nop9953 = alloca i1, i1 0
-  %nop9954 = alloca i1, i1 0
-  %nop9955 = alloca i1, i1 0
-  %nop9956 = alloca i1, i1 0
-  %nop9957 = alloca i1, i1 0
-  %nop9958 = alloca i1, i1 0
-  %nop9959 = alloca i1, i1 0
-  %nop9960 = alloca i1, i1 0
-  %nop9961 = alloca i1, i1 0
-  %nop9962 = alloca i1, i1 0
-  %nop9963 = alloca i1, i1 0
-  %nop9964 = alloca i1, i1 0
-  %nop9965 = alloca i1, i1 0
-  %nop9966 = alloca i1, i1 0
-  %nop9967 = alloca i1, i1 0
-  %nop9968 = alloca i1, i1 0
-  %nop9969 = alloca i1, i1 0
-  %nop9970 = alloca i1, i1 0
-  %nop9971 = alloca i1, i1 0
-  %nop9972 = alloca i1, i1 0
-  %nop9973 = alloca i1, i1 0
-  %nop9974 = alloca i1, i1 0
-  %nop9975 = alloca i1, i1 0
-  %nop9976 = alloca i1, i1 0
-  %nop9977 = alloca i1, i1 0
-  %nop9978 = alloca i1, i1 0
-  %nop9979 = alloca i1, i1 0
-  %nop9980 = alloca i1, i1 0
-  %nop9981 = alloca i1, i1 0
-  %nop9982 = alloca i1, i1 0
-  %nop9983 = alloca i1, i1 0
-  %nop9984 = alloca i1, i1 0
-  %nop9985 = alloca i1, i1 0
-  %nop9986 = alloca i1, i1 0
-  %nop9987 = alloca i1, i1 0
-  %nop9988 = alloca i1, i1 0
-  %nop9989 = alloca i1, i1 0
-  %nop9990 = alloca i1, i1 0
-  %nop9991 = alloca i1, i1 0
-  %nop9992 = alloca i1, i1 0
-  %nop9993 = alloca i1, i1 0
-  %nop9994 = alloca i1, i1 0
-  %nop9995 = alloca i1, i1 0
-  %nop9996 = alloca i1, i1 0
-  %nop9997 = alloca i1, i1 0
-  %nop9998 = alloca i1, i1 0
-  %nop9999 = alloca i1, i1 0
-  %nop10000 = alloca i1, i1 0
-  %nop10001 = alloca i1, i1 0
-  %nop10002 = alloca i1, i1 0
-  %nop10003 = alloca i1, i1 0
-  %nop10004 = alloca i1, i1 0
-  %nop10005 = alloca i1, i1 0
-  %nop10006 = alloca i1, i1 0
-  %nop10007 = alloca i1, i1 0
-  %nop10008 = alloca i1, i1 0
-  %nop10009 = alloca i1, i1 0
-  %nop10010 = alloca i1, i1 0
-  %nop10011 = alloca i1, i1 0
-  %nop10012 = alloca i1, i1 0
-  %nop10013 = alloca i1, i1 0
-  %nop10014 = alloca i1, i1 0
-  %nop10015 = alloca i1, i1 0
-  %nop10016 = alloca i1, i1 0
-  %nop10017 = alloca i1, i1 0
-  %nop10018 = alloca i1, i1 0
-  %nop10019 = alloca i1, i1 0
-  %nop10020 = alloca i1, i1 0
-  %nop10021 = alloca i1, i1 0
-  %nop10022 = alloca i1, i1 0
-  %nop10023 = alloca i1, i1 0
-  %nop10024 = alloca i1, i1 0
-  %nop10025 = alloca i1, i1 0
-  %nop10026 = alloca i1, i1 0
-  %nop10027 = alloca i1, i1 0
-  %nop10028 = alloca i1, i1 0
-  %nop10029 = alloca i1, i1 0
-  %nop10030 = alloca i1, i1 0
-  %nop10031 = alloca i1, i1 0
-  %nop10032 = alloca i1, i1 0
-  %nop10033 = alloca i1, i1 0
-  %nop10034 = alloca i1, i1 0
-  %nop10035 = alloca i1, i1 0
-  %nop10036 = alloca i1, i1 0
-  %nop10037 = alloca i1, i1 0
-  %nop10038 = alloca i1, i1 0
-  %nop10039 = alloca i1, i1 0
-  %nop10040 = alloca i1, i1 0
-  %nop10041 = alloca i1, i1 0
-  %nop10042 = alloca i1, i1 0
-  %nop10043 = alloca i1, i1 0
-  %nop10044 = alloca i1, i1 0
-  %nop10045 = alloca i1, i1 0
-  %nop10046 = alloca i1, i1 0
-  %nop10047 = alloca i1, i1 0
-  %nop10048 = alloca i1, i1 0
-  %nop10049 = alloca i1, i1 0
-  %nop10050 = alloca i1, i1 0
-  %nop10051 = alloca i1, i1 0
-  %nop10052 = alloca i1, i1 0
-  %nop10053 = alloca i1, i1 0
-  %nop10054 = alloca i1, i1 0
-  %nop10055 = alloca i1, i1 0
-  %nop10056 = alloca i1, i1 0
-  %nop10057 = alloca i1, i1 0
-  %nop10058 = alloca i1, i1 0
-  %nop10059 = alloca i1, i1 0
-  %nop10060 = alloca i1, i1 0
-  %nop10061 = alloca i1, i1 0
-  %nop10062 = alloca i1, i1 0
-  %nop10063 = alloca i1, i1 0
-  %nop10064 = alloca i1, i1 0
-  %nop10065 = alloca i1, i1 0
-  %nop10066 = alloca i1, i1 0
-  %nop10067 = alloca i1, i1 0
-  %nop10068 = alloca i1, i1 0
-  %nop10069 = alloca i1, i1 0
-  %nop10070 = alloca i1, i1 0
-  %nop10071 = alloca i1, i1 0
-  %nop10072 = alloca i1, i1 0
-  %nop10073 = alloca i1, i1 0
-  %nop10074 = alloca i1, i1 0
-  %nop10075 = alloca i1, i1 0
-  %nop10076 = alloca i1, i1 0
-  %nop10077 = alloca i1, i1 0
-  %nop10078 = alloca i1, i1 0
-  %nop10079 = alloca i1, i1 0
-  %nop10080 = alloca i1, i1 0
-  %nop10081 = alloca i1, i1 0
-  %nop10082 = alloca i1, i1 0
-  %nop10083 = alloca i1, i1 0
-  %nop10084 = alloca i1, i1 0
-  %nop10085 = alloca i1, i1 0
-  %nop10086 = alloca i1, i1 0
-  %nop10087 = alloca i1, i1 0
-  %nop10088 = alloca i1, i1 0
-  %nop10089 = alloca i1, i1 0
-  %nop10090 = alloca i1, i1 0
-  %nop10091 = alloca i1, i1 0
-  %nop10092 = alloca i1, i1 0
-  %nop10093 = alloca i1, i1 0
-  %nop10094 = alloca i1, i1 0
-  %nop10095 = alloca i1, i1 0
-  %nop10096 = alloca i1, i1 0
-  %nop10097 = alloca i1, i1 0
-  %nop10098 = alloca i1, i1 0
-  %nop10099 = alloca i1, i1 0
-  %nop10100 = alloca i1, i1 0
-  %nop10101 = alloca i1, i1 0
-  %nop10102 = alloca i1, i1 0
-  %nop10103 = alloca i1, i1 0
-  %nop10104 = alloca i1, i1 0
-  %nop10105 = alloca i1, i1 0
-  %nop10106 = alloca i1, i1 0
-  %nop10107 = alloca i1, i1 0
-  %nop10108 = alloca i1, i1 0
-  %nop10109 = alloca i1, i1 0
-  %nop10110 = alloca i1, i1 0
-  %nop10111 = alloca i1, i1 0
-  %nop10112 = alloca i1, i1 0
-  %nop10113 = alloca i1, i1 0
-  %nop10114 = alloca i1, i1 0
-  %nop10115 = alloca i1, i1 0
-  %nop10116 = alloca i1, i1 0
-  %nop10117 = alloca i1, i1 0
-  %nop10118 = alloca i1, i1 0
-  %nop10119 = alloca i1, i1 0
-  %nop10120 = alloca i1, i1 0
-  %nop10121 = alloca i1, i1 0
-  %nop10122 = alloca i1, i1 0
-  %nop10123 = alloca i1, i1 0
-  %nop10124 = alloca i1, i1 0
-  %nop10125 = alloca i1, i1 0
-  %nop10126 = alloca i1, i1 0
-  %nop10127 = alloca i1, i1 0
-  %nop10128 = alloca i1, i1 0
-  %nop10129 = alloca i1, i1 0
-  %nop10130 = alloca i1, i1 0
-  %nop10131 = alloca i1, i1 0
-  %nop10132 = alloca i1, i1 0
-  %nop10133 = alloca i1, i1 0
-  %nop10134 = alloca i1, i1 0
-  %nop10135 = alloca i1, i1 0
-  %nop10136 = alloca i1, i1 0
-  %nop10137 = alloca i1, i1 0
-  %nop10138 = alloca i1, i1 0
-  %nop10139 = alloca i1, i1 0
-  %nop10140 = alloca i1, i1 0
-  %nop10141 = alloca i1, i1 0
-  %nop10142 = alloca i1, i1 0
-  %nop10143 = alloca i1, i1 0
-  %nop10144 = alloca i1, i1 0
-  %nop10145 = alloca i1, i1 0
-  %nop10146 = alloca i1, i1 0
-  %nop10147 = alloca i1, i1 0
-  %nop10148 = alloca i1, i1 0
-  %nop10149 = alloca i1, i1 0
-  %nop10150 = alloca i1, i1 0
-  %nop10151 = alloca i1, i1 0
-  %nop10152 = alloca i1, i1 0
-  %nop10153 = alloca i1, i1 0
-  %nop10154 = alloca i1, i1 0
-  %nop10155 = alloca i1, i1 0
-  %nop10156 = alloca i1, i1 0
-  %nop10157 = alloca i1, i1 0
-  %nop10158 = alloca i1, i1 0
-  %nop10159 = alloca i1, i1 0
-  %nop10160 = alloca i1, i1 0
-  %nop10161 = alloca i1, i1 0
-  %nop10162 = alloca i1, i1 0
-  %nop10163 = alloca i1, i1 0
-  %nop10164 = alloca i1, i1 0
-  %nop10165 = alloca i1, i1 0
-  %nop10166 = alloca i1, i1 0
-  %nop10167 = alloca i1, i1 0
-  %nop10168 = alloca i1, i1 0
-  %nop10169 = alloca i1, i1 0
-  %nop10170 = alloca i1, i1 0
-  %nop10171 = alloca i1, i1 0
-  %nop10172 = alloca i1, i1 0
-  %nop10173 = alloca i1, i1 0
-  %nop10174 = alloca i1, i1 0
-  %nop10175 = alloca i1, i1 0
-  %nop10176 = alloca i1, i1 0
-  %nop10177 = alloca i1, i1 0
-  %nop10178 = alloca i1, i1 0
-  %nop10179 = alloca i1, i1 0
-  %nop10180 = alloca i1, i1 0
-  %nop10181 = alloca i1, i1 0
-  %nop10182 = alloca i1, i1 0
-  %nop10183 = alloca i1, i1 0
-  %nop10184 = alloca i1, i1 0
-  %nop10185 = alloca i1, i1 0
-  %nop10186 = alloca i1, i1 0
-  %nop10187 = alloca i1, i1 0
-  %nop10188 = alloca i1, i1 0
-  %nop10189 = alloca i1, i1 0
-  %nop10190 = alloca i1, i1 0
-  %nop10191 = alloca i1, i1 0
-  %nop10192 = alloca i1, i1 0
-  %nop10193 = alloca i1, i1 0
-  %nop10194 = alloca i1, i1 0
-  %nop10195 = alloca i1, i1 0
-  %nop10196 = alloca i1, i1 0
-  %nop10197 = alloca i1, i1 0
-  %nop10198 = alloca i1, i1 0
-  %nop10199 = alloca i1, i1 0
-  %nop10200 = alloca i1, i1 0
-  %nop10201 = alloca i1, i1 0
-  %nop10202 = alloca i1, i1 0
-  %nop10203 = alloca i1, i1 0
-  %nop10204 = alloca i1, i1 0
-  %nop10205 = alloca i1, i1 0
-  %nop10206 = alloca i1, i1 0
-  %nop10207 = alloca i1, i1 0
-  %nop10208 = alloca i1, i1 0
-  %nop10209 = alloca i1, i1 0
-  %nop10210 = alloca i1, i1 0
-  %nop10211 = alloca i1, i1 0
-  %nop10212 = alloca i1, i1 0
-  %nop10213 = alloca i1, i1 0
-  %nop10214 = alloca i1, i1 0
-  %nop10215 = alloca i1, i1 0
-  %nop10216 = alloca i1, i1 0
-  %nop10217 = alloca i1, i1 0
-  %nop10218 = alloca i1, i1 0
-  %nop10219 = alloca i1, i1 0
-  %nop10220 = alloca i1, i1 0
-  %nop10221 = alloca i1, i1 0
-  %nop10222 = alloca i1, i1 0
-  %nop10223 = alloca i1, i1 0
-  %nop10224 = alloca i1, i1 0
-  %nop10225 = alloca i1, i1 0
-  %nop10226 = alloca i1, i1 0
-  %nop10227 = alloca i1, i1 0
-  %nop10228 = alloca i1, i1 0
-  %nop10229 = alloca i1, i1 0
-  %nop10230 = alloca i1, i1 0
-  %nop10231 = alloca i1, i1 0
-  %nop10232 = alloca i1, i1 0
-  %nop10233 = alloca i1, i1 0
-  %nop10234 = alloca i1, i1 0
-  %nop10235 = alloca i1, i1 0
-  %nop10236 = alloca i1, i1 0
-  %nop10237 = alloca i1, i1 0
-  %nop10238 = alloca i1, i1 0
-  %nop10239 = alloca i1, i1 0
-  %nop10240 = alloca i1, i1 0
-  %nop10241 = alloca i1, i1 0
-  %nop10242 = alloca i1, i1 0
-  %nop10243 = alloca i1, i1 0
-  %nop10244 = alloca i1, i1 0
-  %nop10245 = alloca i1, i1 0
-  %nop10246 = alloca i1, i1 0
-  %nop10247 = alloca i1, i1 0
-  %nop10248 = alloca i1, i1 0
-  %nop10249 = alloca i1, i1 0
-  %nop10250 = alloca i1, i1 0
-  %nop10251 = alloca i1, i1 0
-  %nop10252 = alloca i1, i1 0
-  %nop10253 = alloca i1, i1 0
-  %nop10254 = alloca i1, i1 0
-  %nop10255 = alloca i1, i1 0
-  %nop10256 = alloca i1, i1 0
-  %nop10257 = alloca i1, i1 0
-  %nop10258 = alloca i1, i1 0
-  %nop10259 = alloca i1, i1 0
-  %nop10260 = alloca i1, i1 0
-  %nop10261 = alloca i1, i1 0
-  %nop10262 = alloca i1, i1 0
-  %nop10263 = alloca i1, i1 0
-  %nop10264 = alloca i1, i1 0
-  %nop10265 = alloca i1, i1 0
-  %nop10266 = alloca i1, i1 0
-  %nop10267 = alloca i1, i1 0
-  %nop10268 = alloca i1, i1 0
-  %nop10269 = alloca i1, i1 0
-  %nop10270 = alloca i1, i1 0
-  %nop10271 = alloca i1, i1 0
-  %nop10272 = alloca i1, i1 0
-  %nop10273 = alloca i1, i1 0
-  %nop10274 = alloca i1, i1 0
-  %nop10275 = alloca i1, i1 0
-  %nop10276 = alloca i1, i1 0
-  %nop10277 = alloca i1, i1 0
-  %nop10278 = alloca i1, i1 0
-  %nop10279 = alloca i1, i1 0
-  %nop10280 = alloca i1, i1 0
-  %nop10281 = alloca i1, i1 0
-  %nop10282 = alloca i1, i1 0
-  %nop10283 = alloca i1, i1 0
-  %nop10284 = alloca i1, i1 0
-  %nop10285 = alloca i1, i1 0
-  %nop10286 = alloca i1, i1 0
-  %nop10287 = alloca i1, i1 0
-  %nop10288 = alloca i1, i1 0
-  %nop10289 = alloca i1, i1 0
-  %nop10290 = alloca i1, i1 0
-  %nop10291 = alloca i1, i1 0
-  %nop10292 = alloca i1, i1 0
-  %nop10293 = alloca i1, i1 0
-  %nop10294 = alloca i1, i1 0
-  %nop10295 = alloca i1, i1 0
-  %nop10296 = alloca i1, i1 0
-  %nop10297 = alloca i1, i1 0
-  %nop10298 = alloca i1, i1 0
-  %nop10299 = alloca i1, i1 0
-  %nop10300 = alloca i1, i1 0
-  %nop10301 = alloca i1, i1 0
-  %nop10302 = alloca i1, i1 0
-  %nop10303 = alloca i1, i1 0
-  %nop10304 = alloca i1, i1 0
-  %nop10305 = alloca i1, i1 0
-  %nop10306 = alloca i1, i1 0
-  %nop10307 = alloca i1, i1 0
-  %nop10308 = alloca i1, i1 0
-  %nop10309 = alloca i1, i1 0
-  %nop10310 = alloca i1, i1 0
-  %nop10311 = alloca i1, i1 0
-  %nop10312 = alloca i1, i1 0
-  %nop10313 = alloca i1, i1 0
-  %nop10314 = alloca i1, i1 0
-  %nop10315 = alloca i1, i1 0
-  %nop10316 = alloca i1, i1 0
-  %nop10317 = alloca i1, i1 0
-  %nop10318 = alloca i1, i1 0
-  %nop10319 = alloca i1, i1 0
-  %nop10320 = alloca i1, i1 0
-  %nop10321 = alloca i1, i1 0
-  %nop10322 = alloca i1, i1 0
-  %nop10323 = alloca i1, i1 0
-  %nop10324 = alloca i1, i1 0
-  %nop10325 = alloca i1, i1 0
-  %nop10326 = alloca i1, i1 0
-  %nop10327 = alloca i1, i1 0
-  %nop10328 = alloca i1, i1 0
-  %nop10329 = alloca i1, i1 0
-  %nop10330 = alloca i1, i1 0
-  %nop10331 = alloca i1, i1 0
-  %nop10332 = alloca i1, i1 0
-  %nop10333 = alloca i1, i1 0
-  %nop10334 = alloca i1, i1 0
-  %nop10335 = alloca i1, i1 0
-  %nop10336 = alloca i1, i1 0
-  %nop10337 = alloca i1, i1 0
-  %nop10338 = alloca i1, i1 0
-  %nop10339 = alloca i1, i1 0
-  %nop10340 = alloca i1, i1 0
-  %nop10341 = alloca i1, i1 0
-  %nop10342 = alloca i1, i1 0
-  %nop10343 = alloca i1, i1 0
-  %nop10344 = alloca i1, i1 0
-  %nop10345 = alloca i1, i1 0
-  %nop10346 = alloca i1, i1 0
-  %nop10347 = alloca i1, i1 0
-  %nop10348 = alloca i1, i1 0
-  %nop10349 = alloca i1, i1 0
-  %nop10350 = alloca i1, i1 0
-  %nop10351 = alloca i1, i1 0
-  %nop10352 = alloca i1, i1 0
-  %nop10353 = alloca i1, i1 0
-  %nop10354 = alloca i1, i1 0
-  %nop10355 = alloca i1, i1 0
-  %nop10356 = alloca i1, i1 0
-  %nop10357 = alloca i1, i1 0
-  %nop10358 = alloca i1, i1 0
-  %nop10359 = alloca i1, i1 0
-  %nop10360 = alloca i1, i1 0
-  %nop10361 = alloca i1, i1 0
-  %nop10362 = alloca i1, i1 0
-  %nop10363 = alloca i1, i1 0
-  %nop10364 = alloca i1, i1 0
-  %nop10365 = alloca i1, i1 0
-  %nop10366 = alloca i1, i1 0
-  %nop10367 = alloca i1, i1 0
-  %nop10368 = alloca i1, i1 0
-  %nop10369 = alloca i1, i1 0
-  %nop10370 = alloca i1, i1 0
-  %nop10371 = alloca i1, i1 0
-  %nop10372 = alloca i1, i1 0
-  %nop10373 = alloca i1, i1 0
-  %nop10374 = alloca i1, i1 0
-  %nop10375 = alloca i1, i1 0
-  %nop10376 = alloca i1, i1 0
-  %nop10377 = alloca i1, i1 0
-  %nop10378 = alloca i1, i1 0
-  %nop10379 = alloca i1, i1 0
-  %nop10380 = alloca i1, i1 0
-  %nop10381 = alloca i1, i1 0
-  %nop10382 = alloca i1, i1 0
-  %nop10383 = alloca i1, i1 0
-  %nop10384 = alloca i1, i1 0
-  %nop10385 = alloca i1, i1 0
-  %nop10386 = alloca i1, i1 0
-  %nop10387 = alloca i1, i1 0
-  %nop10388 = alloca i1, i1 0
-  %nop10389 = alloca i1, i1 0
-  %nop10390 = alloca i1, i1 0
-  %nop10391 = alloca i1, i1 0
-  %nop10392 = alloca i1, i1 0
-  %nop10393 = alloca i1, i1 0
-  %nop10394 = alloca i1, i1 0
-  %nop10395 = alloca i1, i1 0
-  %nop10396 = alloca i1, i1 0
-  %nop10397 = alloca i1, i1 0
-  %nop10398 = alloca i1, i1 0
-  %nop10399 = alloca i1, i1 0
-  %nop10400 = alloca i1, i1 0
-  %nop10401 = alloca i1, i1 0
-  %nop10402 = alloca i1, i1 0
-  %nop10403 = alloca i1, i1 0
-  %nop10404 = alloca i1, i1 0
-  %nop10405 = alloca i1, i1 0
-  %nop10406 = alloca i1, i1 0
-  %nop10407 = alloca i1, i1 0
-  %nop10408 = alloca i1, i1 0
-  %nop10409 = alloca i1, i1 0
-  %nop10410 = alloca i1, i1 0
-  %nop10411 = alloca i1, i1 0
-  %nop10412 = alloca i1, i1 0
-  %nop10413 = alloca i1, i1 0
-  %nop10414 = alloca i1, i1 0
-  %nop10415 = alloca i1, i1 0
-  %nop10416 = alloca i1, i1 0
-  %nop10417 = alloca i1, i1 0
-  %nop10418 = alloca i1, i1 0
-  %nop10419 = alloca i1, i1 0
-  %nop10420 = alloca i1, i1 0
-  %nop10421 = alloca i1, i1 0
-  %nop10422 = alloca i1, i1 0
-  %nop10423 = alloca i1, i1 0
-  %nop10424 = alloca i1, i1 0
-  %nop10425 = alloca i1, i1 0
-  %nop10426 = alloca i1, i1 0
-  %nop10427 = alloca i1, i1 0
-  %nop10428 = alloca i1, i1 0
-  %nop10429 = alloca i1, i1 0
-  %nop10430 = alloca i1, i1 0
-  %nop10431 = alloca i1, i1 0
-  %nop10432 = alloca i1, i1 0
-  %nop10433 = alloca i1, i1 0
-  %nop10434 = alloca i1, i1 0
-  %nop10435 = alloca i1, i1 0
-  %nop10436 = alloca i1, i1 0
-  %nop10437 = alloca i1, i1 0
-  %nop10438 = alloca i1, i1 0
-  %nop10439 = alloca i1, i1 0
-  %nop10440 = alloca i1, i1 0
-  %nop10441 = alloca i1, i1 0
-  %nop10442 = alloca i1, i1 0
-  %nop10443 = alloca i1, i1 0
-  %nop10444 = alloca i1, i1 0
-  %nop10445 = alloca i1, i1 0
-  %nop10446 = alloca i1, i1 0
-  %nop10447 = alloca i1, i1 0
-  %nop10448 = alloca i1, i1 0
-  %nop10449 = alloca i1, i1 0
-  %nop10450 = alloca i1, i1 0
-  %nop10451 = alloca i1, i1 0
-  %nop10452 = alloca i1, i1 0
-  %nop10453 = alloca i1, i1 0
-  %nop10454 = alloca i1, i1 0
-  %nop10455 = alloca i1, i1 0
-  %nop10456 = alloca i1, i1 0
-  %nop10457 = alloca i1, i1 0
-  %nop10458 = alloca i1, i1 0
-  %nop10459 = alloca i1, i1 0
-  %nop10460 = alloca i1, i1 0
-  %nop10461 = alloca i1, i1 0
-  %nop10462 = alloca i1, i1 0
-  %nop10463 = alloca i1, i1 0
-  %nop10464 = alloca i1, i1 0
-  %nop10465 = alloca i1, i1 0
-  %nop10466 = alloca i1, i1 0
-  %nop10467 = alloca i1, i1 0
-  %nop10468 = alloca i1, i1 0
-  %nop10469 = alloca i1, i1 0
-  %nop10470 = alloca i1, i1 0
-  %nop10471 = alloca i1, i1 0
-  %nop10472 = alloca i1, i1 0
-  %nop10473 = alloca i1, i1 0
-  %nop10474 = alloca i1, i1 0
-  %nop10475 = alloca i1, i1 0
-  %nop10476 = alloca i1, i1 0
-  %nop10477 = alloca i1, i1 0
-  %nop10478 = alloca i1, i1 0
-  %nop10479 = alloca i1, i1 0
-  %nop10480 = alloca i1, i1 0
-  %nop10481 = alloca i1, i1 0
-  %nop10482 = alloca i1, i1 0
-  %nop10483 = alloca i1, i1 0
-  %nop10484 = alloca i1, i1 0
-  %nop10485 = alloca i1, i1 0
-  %nop10486 = alloca i1, i1 0
-  %nop10487 = alloca i1, i1 0
-  %nop10488 = alloca i1, i1 0
-  %nop10489 = alloca i1, i1 0
-  %nop10490 = alloca i1, i1 0
-  %nop10491 = alloca i1, i1 0
-  %nop10492 = alloca i1, i1 0
-  %nop10493 = alloca i1, i1 0
-  %nop10494 = alloca i1, i1 0
-  %nop10495 = alloca i1, i1 0
-  %nop10496 = alloca i1, i1 0
-  %nop10497 = alloca i1, i1 0
-  %nop10498 = alloca i1, i1 0
-  %nop10499 = alloca i1, i1 0
-  %nop10500 = alloca i1, i1 0
-  %nop10501 = alloca i1, i1 0
-  %nop10502 = alloca i1, i1 0
-  %nop10503 = alloca i1, i1 0
-  %nop10504 = alloca i1, i1 0
-  %nop10505 = alloca i1, i1 0
-  %nop10506 = alloca i1, i1 0
-  %nop10507 = alloca i1, i1 0
-  %nop10508 = alloca i1, i1 0
-  %nop10509 = alloca i1, i1 0
-  %nop10510 = alloca i1, i1 0
-  %nop10511 = alloca i1, i1 0
-  %nop10512 = alloca i1, i1 0
-  %nop10513 = alloca i1, i1 0
-  %nop10514 = alloca i1, i1 0
-  %nop10515 = alloca i1, i1 0
-  %nop10516 = alloca i1, i1 0
-  %nop10517 = alloca i1, i1 0
-  %nop10518 = alloca i1, i1 0
-  %nop10519 = alloca i1, i1 0
-  %nop10520 = alloca i1, i1 0
-  %nop10521 = alloca i1, i1 0
-  %nop10522 = alloca i1, i1 0
-  %nop10523 = alloca i1, i1 0
-  %nop10524 = alloca i1, i1 0
-  %nop10525 = alloca i1, i1 0
-  %nop10526 = alloca i1, i1 0
-  %nop10527 = alloca i1, i1 0
-  %nop10528 = alloca i1, i1 0
-  %nop10529 = alloca i1, i1 0
-  %nop10530 = alloca i1, i1 0
-  %nop10531 = alloca i1, i1 0
-  %nop10532 = alloca i1, i1 0
-  %nop10533 = alloca i1, i1 0
-  %nop10534 = alloca i1, i1 0
-  %nop10535 = alloca i1, i1 0
-  %nop10536 = alloca i1, i1 0
-  %nop10537 = alloca i1, i1 0
-  %nop10538 = alloca i1, i1 0
-  %nop10539 = alloca i1, i1 0
-  %nop10540 = alloca i1, i1 0
-  %nop10541 = alloca i1, i1 0
-  %nop10542 = alloca i1, i1 0
-  %nop10543 = alloca i1, i1 0
-  %nop10544 = alloca i1, i1 0
-  %nop10545 = alloca i1, i1 0
-  %nop10546 = alloca i1, i1 0
-  %nop10547 = alloca i1, i1 0
-  %nop10548 = alloca i1, i1 0
-  %nop10549 = alloca i1, i1 0
-  %nop10550 = alloca i1, i1 0
-  %nop10551 = alloca i1, i1 0
-  %nop10552 = alloca i1, i1 0
-  %nop10553 = alloca i1, i1 0
-  %nop10554 = alloca i1, i1 0
-  %nop10555 = alloca i1, i1 0
-  %nop10556 = alloca i1, i1 0
-  %nop10557 = alloca i1, i1 0
-  %nop10558 = alloca i1, i1 0
-  %nop10559 = alloca i1, i1 0
-  %nop10560 = alloca i1, i1 0
-  %nop10561 = alloca i1, i1 0
-  %nop10562 = alloca i1, i1 0
-  %nop10563 = alloca i1, i1 0
-  %nop10564 = alloca i1, i1 0
-  %nop10565 = alloca i1, i1 0
-  %nop10566 = alloca i1, i1 0
-  %nop10567 = alloca i1, i1 0
-  %nop10568 = alloca i1, i1 0
-  %nop10569 = alloca i1, i1 0
-  %nop10570 = alloca i1, i1 0
-  %nop10571 = alloca i1, i1 0
-  %nop10572 = alloca i1, i1 0
-  %nop10573 = alloca i1, i1 0
-  %nop10574 = alloca i1, i1 0
-  %nop10575 = alloca i1, i1 0
-  %nop10576 = alloca i1, i1 0
-  %nop10577 = alloca i1, i1 0
-  %nop10578 = alloca i1, i1 0
-  %nop10579 = alloca i1, i1 0
-  %nop10580 = alloca i1, i1 0
-  %nop10581 = alloca i1, i1 0
-  %nop10582 = alloca i1, i1 0
-  %nop10583 = alloca i1, i1 0
-  %nop10584 = alloca i1, i1 0
-  %nop10585 = alloca i1, i1 0
-  %nop10586 = alloca i1, i1 0
-  %nop10587 = alloca i1, i1 0
-  %nop10588 = alloca i1, i1 0
-  %nop10589 = alloca i1, i1 0
-  %nop10590 = alloca i1, i1 0
-  %nop10591 = alloca i1, i1 0
-  %nop10592 = alloca i1, i1 0
-  %nop10593 = alloca i1, i1 0
-  %nop10594 = alloca i1, i1 0
-  %nop10595 = alloca i1, i1 0
-  %nop10596 = alloca i1, i1 0
-  %nop10597 = alloca i1, i1 0
-  %nop10598 = alloca i1, i1 0
-  %nop10599 = alloca i1, i1 0
-  %nop10600 = alloca i1, i1 0
-  %nop10601 = alloca i1, i1 0
-  %nop10602 = alloca i1, i1 0
-  %nop10603 = alloca i1, i1 0
-  %nop10604 = alloca i1, i1 0
-  %nop10605 = alloca i1, i1 0
-  %nop10606 = alloca i1, i1 0
-  %nop10607 = alloca i1, i1 0
-  %nop10608 = alloca i1, i1 0
-  %nop10609 = alloca i1, i1 0
-  %nop10610 = alloca i1, i1 0
-  %nop10611 = alloca i1, i1 0
-  %nop10612 = alloca i1, i1 0
-  %nop10613 = alloca i1, i1 0
-  %nop10614 = alloca i1, i1 0
-  %nop10615 = alloca i1, i1 0
-  %nop10616 = alloca i1, i1 0
-  %nop10617 = alloca i1, i1 0
-  %nop10618 = alloca i1, i1 0
-  %nop10619 = alloca i1, i1 0
-  %nop10620 = alloca i1, i1 0
-  %nop10621 = alloca i1, i1 0
-  %nop10622 = alloca i1, i1 0
-  %nop10623 = alloca i1, i1 0
-  %nop10624 = alloca i1, i1 0
-  %nop10625 = alloca i1, i1 0
-  %nop10626 = alloca i1, i1 0
-  %nop10627 = alloca i1, i1 0
-  %nop10628 = alloca i1, i1 0
-  %nop10629 = alloca i1, i1 0
-  %nop10630 = alloca i1, i1 0
-  %nop10631 = alloca i1, i1 0
-  %nop10632 = alloca i1, i1 0
-  %nop10633 = alloca i1, i1 0
-  %nop10634 = alloca i1, i1 0
-  %nop10635 = alloca i1, i1 0
-  %nop10636 = alloca i1, i1 0
-  %nop10637 = alloca i1, i1 0
-  %nop10638 = alloca i1, i1 0
-  %nop10639 = alloca i1, i1 0
-  %nop10640 = alloca i1, i1 0
-  %nop10641 = alloca i1, i1 0
-  %nop10642 = alloca i1, i1 0
-  %nop10643 = alloca i1, i1 0
-  %nop10644 = alloca i1, i1 0
-  %nop10645 = alloca i1, i1 0
-  %nop10646 = alloca i1, i1 0
-  %nop10647 = alloca i1, i1 0
-  %nop10648 = alloca i1, i1 0
-  %nop10649 = alloca i1, i1 0
-  %nop10650 = alloca i1, i1 0
-  %nop10651 = alloca i1, i1 0
-  %nop10652 = alloca i1, i1 0
-  %nop10653 = alloca i1, i1 0
-  %nop10654 = alloca i1, i1 0
-  %nop10655 = alloca i1, i1 0
-  %nop10656 = alloca i1, i1 0
-  %nop10657 = alloca i1, i1 0
-  %nop10658 = alloca i1, i1 0
-  %nop10659 = alloca i1, i1 0
-  %nop10660 = alloca i1, i1 0
-  %nop10661 = alloca i1, i1 0
-  %nop10662 = alloca i1, i1 0
-  %nop10663 = alloca i1, i1 0
-  %nop10664 = alloca i1, i1 0
-  %nop10665 = alloca i1, i1 0
-  %nop10666 = alloca i1, i1 0
-  %nop10667 = alloca i1, i1 0
-  %nop10668 = alloca i1, i1 0
-  %nop10669 = alloca i1, i1 0
-  %nop10670 = alloca i1, i1 0
-  %nop10671 = alloca i1, i1 0
-  %nop10672 = alloca i1, i1 0
-  %nop10673 = alloca i1, i1 0
-  %nop10674 = alloca i1, i1 0
-  %nop10675 = alloca i1, i1 0
-  %nop10676 = alloca i1, i1 0
-  %nop10677 = alloca i1, i1 0
-  %nop10678 = alloca i1, i1 0
-  %nop10679 = alloca i1, i1 0
-  %nop10680 = alloca i1, i1 0
-  %nop10681 = alloca i1, i1 0
-  %nop10682 = alloca i1, i1 0
-  %nop10683 = alloca i1, i1 0
-  %nop10684 = alloca i1, i1 0
-  %nop10685 = alloca i1, i1 0
-  %nop10686 = alloca i1, i1 0
-  %nop10687 = alloca i1, i1 0
-  %nop10688 = alloca i1, i1 0
-  %nop10689 = alloca i1, i1 0
-  %nop10690 = alloca i1, i1 0
-  %nop10691 = alloca i1, i1 0
-  %nop10692 = alloca i1, i1 0
-  %nop10693 = alloca i1, i1 0
-  %nop10694 = alloca i1, i1 0
-  %nop10695 = alloca i1, i1 0
-  %nop10696 = alloca i1, i1 0
-  %nop10697 = alloca i1, i1 0
-  %nop10698 = alloca i1, i1 0
-  %nop10699 = alloca i1, i1 0
-  %nop10700 = alloca i1, i1 0
-  %nop10701 = alloca i1, i1 0
-  %nop10702 = alloca i1, i1 0
-  %nop10703 = alloca i1, i1 0
-  %nop10704 = alloca i1, i1 0
-  %nop10705 = alloca i1, i1 0
-  %nop10706 = alloca i1, i1 0
-  %nop10707 = alloca i1, i1 0
-  %nop10708 = alloca i1, i1 0
-  %nop10709 = alloca i1, i1 0
-  %nop10710 = alloca i1, i1 0
-  %nop10711 = alloca i1, i1 0
-  %nop10712 = alloca i1, i1 0
-  %nop10713 = alloca i1, i1 0
-  %nop10714 = alloca i1, i1 0
-  %nop10715 = alloca i1, i1 0
-  %nop10716 = alloca i1, i1 0
-  %nop10717 = alloca i1, i1 0
-  %nop10718 = alloca i1, i1 0
-  %nop10719 = alloca i1, i1 0
-  %nop10720 = alloca i1, i1 0
-  %nop10721 = alloca i1, i1 0
-  %nop10722 = alloca i1, i1 0
-  %nop10723 = alloca i1, i1 0
-  %nop10724 = alloca i1, i1 0
-  %nop10725 = alloca i1, i1 0
-  %nop10726 = alloca i1, i1 0
-  %nop10727 = alloca i1, i1 0
-  %nop10728 = alloca i1, i1 0
-  %nop10729 = alloca i1, i1 0
-  %nop10730 = alloca i1, i1 0
-  %nop10731 = alloca i1, i1 0
-  %nop10732 = alloca i1, i1 0
-  %nop10733 = alloca i1, i1 0
-  %nop10734 = alloca i1, i1 0
-  %nop10735 = alloca i1, i1 0
-  %nop10736 = alloca i1, i1 0
-  %nop10737 = alloca i1, i1 0
-  %nop10738 = alloca i1, i1 0
-  %nop10739 = alloca i1, i1 0
-  %nop10740 = alloca i1, i1 0
-  %nop10741 = alloca i1, i1 0
-  %nop10742 = alloca i1, i1 0
-  %nop10743 = alloca i1, i1 0
-  %nop10744 = alloca i1, i1 0
-  %nop10745 = alloca i1, i1 0
-  %nop10746 = alloca i1, i1 0
-  %nop10747 = alloca i1, i1 0
-  %nop10748 = alloca i1, i1 0
-  %nop10749 = alloca i1, i1 0
-  %nop10750 = alloca i1, i1 0
-  %nop10751 = alloca i1, i1 0
-  %nop10752 = alloca i1, i1 0
-  %nop10753 = alloca i1, i1 0
-  %nop10754 = alloca i1, i1 0
-  %nop10755 = alloca i1, i1 0
-  %nop10756 = alloca i1, i1 0
-  %nop10757 = alloca i1, i1 0
-  %nop10758 = alloca i1, i1 0
-  %nop10759 = alloca i1, i1 0
-  %nop10760 = alloca i1, i1 0
-  %nop10761 = alloca i1, i1 0
-  %nop10762 = alloca i1, i1 0
-  %nop10763 = alloca i1, i1 0
-  %nop10764 = alloca i1, i1 0
-  %nop10765 = alloca i1, i1 0
-  %nop10766 = alloca i1, i1 0
-  %nop10767 = alloca i1, i1 0
-  %nop10768 = alloca i1, i1 0
-  %nop10769 = alloca i1, i1 0
-  %nop10770 = alloca i1, i1 0
-  %nop10771 = alloca i1, i1 0
-  %nop10772 = alloca i1, i1 0
-  %nop10773 = alloca i1, i1 0
-  %nop10774 = alloca i1, i1 0
-  %nop10775 = alloca i1, i1 0
-  %nop10776 = alloca i1, i1 0
-  %nop10777 = alloca i1, i1 0
-  %nop10778 = alloca i1, i1 0
-  %nop10779 = alloca i1, i1 0
-  %nop10780 = alloca i1, i1 0
-  %nop10781 = alloca i1, i1 0
-  %nop10782 = alloca i1, i1 0
-  %nop10783 = alloca i1, i1 0
-  %nop10784 = alloca i1, i1 0
-  %nop10785 = alloca i1, i1 0
-  %nop10786 = alloca i1, i1 0
-  %nop10787 = alloca i1, i1 0
-  %nop10788 = alloca i1, i1 0
-  %nop10789 = alloca i1, i1 0
-  %nop10790 = alloca i1, i1 0
-  %nop10791 = alloca i1, i1 0
-  %nop10792 = alloca i1, i1 0
-  %nop10793 = alloca i1, i1 0
-  %nop10794 = alloca i1, i1 0
-  %nop10795 = alloca i1, i1 0
-  %nop10796 = alloca i1, i1 0
-  %nop10797 = alloca i1, i1 0
-  %nop10798 = alloca i1, i1 0
-  %nop10799 = alloca i1, i1 0
-  %nop10800 = alloca i1, i1 0
-  %nop10801 = alloca i1, i1 0
-  %nop10802 = alloca i1, i1 0
-  %nop10803 = alloca i1, i1 0
-  %nop10804 = alloca i1, i1 0
-  %nop10805 = alloca i1, i1 0
-  %nop10806 = alloca i1, i1 0
-  %nop10807 = alloca i1, i1 0
-  %nop10808 = alloca i1, i1 0
-  %nop10809 = alloca i1, i1 0
-  %nop10810 = alloca i1, i1 0
-  %nop10811 = alloca i1, i1 0
-  %nop10812 = alloca i1, i1 0
-  %nop10813 = alloca i1, i1 0
-  %nop10814 = alloca i1, i1 0
-  %nop10815 = alloca i1, i1 0
-  %nop10816 = alloca i1, i1 0
-  %nop10817 = alloca i1, i1 0
-  %nop10818 = alloca i1, i1 0
-  %nop10819 = alloca i1, i1 0
-  %nop10820 = alloca i1, i1 0
-  %nop10821 = alloca i1, i1 0
-  %nop10822 = alloca i1, i1 0
-  %nop10823 = alloca i1, i1 0
-  %nop10824 = alloca i1, i1 0
-  %nop10825 = alloca i1, i1 0
-  %nop10826 = alloca i1, i1 0
-  %nop10827 = alloca i1, i1 0
-  %nop10828 = alloca i1, i1 0
-  %nop10829 = alloca i1, i1 0
-  %nop10830 = alloca i1, i1 0
-  %nop10831 = alloca i1, i1 0
-  %nop10832 = alloca i1, i1 0
-  %nop10833 = alloca i1, i1 0
-  %nop10834 = alloca i1, i1 0
-  %nop10835 = alloca i1, i1 0
-  %nop10836 = alloca i1, i1 0
-  %nop10837 = alloca i1, i1 0
-  %nop10838 = alloca i1, i1 0
-  %nop10839 = alloca i1, i1 0
-  %nop10840 = alloca i1, i1 0
-  %nop10841 = alloca i1, i1 0
-  %nop10842 = alloca i1, i1 0
-  %nop10843 = alloca i1, i1 0
-  %nop10844 = alloca i1, i1 0
-  %nop10845 = alloca i1, i1 0
-  %nop10846 = alloca i1, i1 0
-  %nop10847 = alloca i1, i1 0
-  %nop10848 = alloca i1, i1 0
-  %nop10849 = alloca i1, i1 0
-  %nop10850 = alloca i1, i1 0
-  %nop10851 = alloca i1, i1 0
-  %nop10852 = alloca i1, i1 0
-  %nop10853 = alloca i1, i1 0
-  %nop10854 = alloca i1, i1 0
-  %nop10855 = alloca i1, i1 0
-  %nop10856 = alloca i1, i1 0
-  %nop10857 = alloca i1, i1 0
-  %nop10858 = alloca i1, i1 0
-  %nop10859 = alloca i1, i1 0
-  %nop10860 = alloca i1, i1 0
-  %nop10861 = alloca i1, i1 0
-  %nop10862 = alloca i1, i1 0
-  %nop10863 = alloca i1, i1 0
-  %nop10864 = alloca i1, i1 0
-  %nop10865 = alloca i1, i1 0
-  %nop10866 = alloca i1, i1 0
-  %nop10867 = alloca i1, i1 0
-  %nop10868 = alloca i1, i1 0
-  %nop10869 = alloca i1, i1 0
-  %nop10870 = alloca i1, i1 0
-  %nop10871 = alloca i1, i1 0
-  %nop10872 = alloca i1, i1 0
-  %nop10873 = alloca i1, i1 0
-  %nop10874 = alloca i1, i1 0
-  %nop10875 = alloca i1, i1 0
-  %nop10876 = alloca i1, i1 0
-  %nop10877 = alloca i1, i1 0
-  %nop10878 = alloca i1, i1 0
-  %nop10879 = alloca i1, i1 0
-  %nop10880 = alloca i1, i1 0
-  %nop10881 = alloca i1, i1 0
-  %nop10882 = alloca i1, i1 0
-  %nop10883 = alloca i1, i1 0
-  %nop10884 = alloca i1, i1 0
-  %nop10885 = alloca i1, i1 0
-  %nop10886 = alloca i1, i1 0
-  %nop10887 = alloca i1, i1 0
-  %nop10888 = alloca i1, i1 0
-  %nop10889 = alloca i1, i1 0
-  %nop10890 = alloca i1, i1 0
-  %nop10891 = alloca i1, i1 0
-  %nop10892 = alloca i1, i1 0
-  %nop10893 = alloca i1, i1 0
-  %nop10894 = alloca i1, i1 0
-  %nop10895 = alloca i1, i1 0
-  %nop10896 = alloca i1, i1 0
-  %nop10897 = alloca i1, i1 0
-  %nop10898 = alloca i1, i1 0
-  %nop10899 = alloca i1, i1 0
-  %nop10900 = alloca i1, i1 0
-  %nop10901 = alloca i1, i1 0
-  %nop10902 = alloca i1, i1 0
-  %nop10903 = alloca i1, i1 0
-  %nop10904 = alloca i1, i1 0
-  %nop10905 = alloca i1, i1 0
-  %nop10906 = alloca i1, i1 0
-  %nop10907 = alloca i1, i1 0
-  %nop10908 = alloca i1, i1 0
-  %nop10909 = alloca i1, i1 0
-  %nop10910 = alloca i1, i1 0
-  %nop10911 = alloca i1, i1 0
-  %nop10912 = alloca i1, i1 0
-  %nop10913 = alloca i1, i1 0
-  %nop10914 = alloca i1, i1 0
-  %nop10915 = alloca i1, i1 0
-  %nop10916 = alloca i1, i1 0
-  %nop10917 = alloca i1, i1 0
-  %nop10918 = alloca i1, i1 0
-  %nop10919 = alloca i1, i1 0
-  %nop10920 = alloca i1, i1 0
-  %nop10921 = alloca i1, i1 0
-  %nop10922 = alloca i1, i1 0
-  %nop10923 = alloca i1, i1 0
-  %nop10924 = alloca i1, i1 0
-  %nop10925 = alloca i1, i1 0
-  %nop10926 = alloca i1, i1 0
-  %nop10927 = alloca i1, i1 0
-  %nop10928 = alloca i1, i1 0
-  %nop10929 = alloca i1, i1 0
-  %nop10930 = alloca i1, i1 0
-  %nop10931 = alloca i1, i1 0
-  %nop10932 = alloca i1, i1 0
-  %nop10933 = alloca i1, i1 0
-  %nop10934 = alloca i1, i1 0
-  %nop10935 = alloca i1, i1 0
-  %nop10936 = alloca i1, i1 0
-  %nop10937 = alloca i1, i1 0
-  %nop10938 = alloca i1, i1 0
-  %nop10939 = alloca i1, i1 0
-  %nop10940 = alloca i1, i1 0
-  %nop10941 = alloca i1, i1 0
-  %nop10942 = alloca i1, i1 0
-  %nop10943 = alloca i1, i1 0
-  %nop10944 = alloca i1, i1 0
-  %nop10945 = alloca i1, i1 0
-  %nop10946 = alloca i1, i1 0
-  %nop10947 = alloca i1, i1 0
-  %nop10948 = alloca i1, i1 0
-  %nop10949 = alloca i1, i1 0
-  %nop10950 = alloca i1, i1 0
-  %nop10951 = alloca i1, i1 0
-  %nop10952 = alloca i1, i1 0
-  %nop10953 = alloca i1, i1 0
-  %nop10954 = alloca i1, i1 0
-  %nop10955 = alloca i1, i1 0
-  %nop10956 = alloca i1, i1 0
-  %nop10957 = alloca i1, i1 0
-  %nop10958 = alloca i1, i1 0
-  %nop10959 = alloca i1, i1 0
-  %nop10960 = alloca i1, i1 0
-  %nop10961 = alloca i1, i1 0
-  %nop10962 = alloca i1, i1 0
-  %nop10963 = alloca i1, i1 0
-  %nop10964 = alloca i1, i1 0
-  %nop10965 = alloca i1, i1 0
-  %nop10966 = alloca i1, i1 0
-  %nop10967 = alloca i1, i1 0
-  %nop10968 = alloca i1, i1 0
-  %nop10969 = alloca i1, i1 0
-  %nop10970 = alloca i1, i1 0
-  %nop10971 = alloca i1, i1 0
-  %nop10972 = alloca i1, i1 0
-  %nop10973 = alloca i1, i1 0
-  %nop10974 = alloca i1, i1 0
-  %nop10975 = alloca i1, i1 0
-  %nop10976 = alloca i1, i1 0
-  %nop10977 = alloca i1, i1 0
-  %nop10978 = alloca i1, i1 0
-  %nop10979 = alloca i1, i1 0
-  %nop10980 = alloca i1, i1 0
-  %nop10981 = alloca i1, i1 0
-  %nop10982 = alloca i1, i1 0
-  %nop10983 = alloca i1, i1 0
-  %nop10984 = alloca i1, i1 0
-  %nop10985 = alloca i1, i1 0
-  %nop10986 = alloca i1, i1 0
-  %nop10987 = alloca i1, i1 0
-  %nop10988 = alloca i1, i1 0
-  %nop10989 = alloca i1, i1 0
-  %nop10990 = alloca i1, i1 0
-  %nop10991 = alloca i1, i1 0
-  %nop10992 = alloca i1, i1 0
-  %nop10993 = alloca i1, i1 0
-  %nop10994 = alloca i1, i1 0
-  %nop10995 = alloca i1, i1 0
-  %nop10996 = alloca i1, i1 0
-  %nop10997 = alloca i1, i1 0
-  %nop10998 = alloca i1, i1 0
-  %nop10999 = alloca i1, i1 0
-  %nop11000 = alloca i1, i1 0
-  %nop11001 = alloca i1, i1 0
-  %nop11002 = alloca i1, i1 0
-  %nop11003 = alloca i1, i1 0
-  %nop11004 = alloca i1, i1 0
-  %nop11005 = alloca i1, i1 0
-  %nop11006 = alloca i1, i1 0
-  %nop11007 = alloca i1, i1 0
-  %nop11008 = alloca i1, i1 0
-  %nop11009 = alloca i1, i1 0
-  %nop11010 = alloca i1, i1 0
-  %nop11011 = alloca i1, i1 0
-  %nop11012 = alloca i1, i1 0
-  %nop11013 = alloca i1, i1 0
-  %nop11014 = alloca i1, i1 0
-  %nop11015 = alloca i1, i1 0
-  %nop11016 = alloca i1, i1 0
-  %nop11017 = alloca i1, i1 0
-  %nop11018 = alloca i1, i1 0
-  %nop11019 = alloca i1, i1 0
-  %nop11020 = alloca i1, i1 0
-  %nop11021 = alloca i1, i1 0
-  %nop11022 = alloca i1, i1 0
-  %nop11023 = alloca i1, i1 0
-  %nop11024 = alloca i1, i1 0
-  %nop11025 = alloca i1, i1 0
-  %nop11026 = alloca i1, i1 0
-  %nop11027 = alloca i1, i1 0
-  %nop11028 = alloca i1, i1 0
-  %nop11029 = alloca i1, i1 0
-  %nop11030 = alloca i1, i1 0
-  %nop11031 = alloca i1, i1 0
-  %nop11032 = alloca i1, i1 0
-  %nop11033 = alloca i1, i1 0
-  %nop11034 = alloca i1, i1 0
-  %nop11035 = alloca i1, i1 0
-  %nop11036 = alloca i1, i1 0
-  %nop11037 = alloca i1, i1 0
-  %nop11038 = alloca i1, i1 0
-  %nop11039 = alloca i1, i1 0
-  %nop11040 = alloca i1, i1 0
-  %nop11041 = alloca i1, i1 0
-  %nop11042 = alloca i1, i1 0
-  %nop11043 = alloca i1, i1 0
-  %nop11044 = alloca i1, i1 0
-  %nop11045 = alloca i1, i1 0
-  %nop11046 = alloca i1, i1 0
-  %nop11047 = alloca i1, i1 0
-  %nop11048 = alloca i1, i1 0
-  %nop11049 = alloca i1, i1 0
-  %nop11050 = alloca i1, i1 0
-  %nop11051 = alloca i1, i1 0
-  %nop11052 = alloca i1, i1 0
-  %nop11053 = alloca i1, i1 0
-  %nop11054 = alloca i1, i1 0
-  %nop11055 = alloca i1, i1 0
-  %nop11056 = alloca i1, i1 0
-  %nop11057 = alloca i1, i1 0
-  %nop11058 = alloca i1, i1 0
-  %nop11059 = alloca i1, i1 0
-  %nop11060 = alloca i1, i1 0
-  %nop11061 = alloca i1, i1 0
-  %nop11062 = alloca i1, i1 0
-  %nop11063 = alloca i1, i1 0
-  %nop11064 = alloca i1, i1 0
-  %nop11065 = alloca i1, i1 0
-  %nop11066 = alloca i1, i1 0
-  %nop11067 = alloca i1, i1 0
-  %nop11068 = alloca i1, i1 0
-  %nop11069 = alloca i1, i1 0
-  %nop11070 = alloca i1, i1 0
-  %nop11071 = alloca i1, i1 0
-  %nop11072 = alloca i1, i1 0
-  %nop11073 = alloca i1, i1 0
-  %nop11074 = alloca i1, i1 0
-  %nop11075 = alloca i1, i1 0
-  %nop11076 = alloca i1, i1 0
-  %nop11077 = alloca i1, i1 0
-  %nop11078 = alloca i1, i1 0
-  %nop11079 = alloca i1, i1 0
-  %nop11080 = alloca i1, i1 0
-  %nop11081 = alloca i1, i1 0
-  %nop11082 = alloca i1, i1 0
-  %nop11083 = alloca i1, i1 0
-  %nop11084 = alloca i1, i1 0
-  %nop11085 = alloca i1, i1 0
-  %nop11086 = alloca i1, i1 0
-  %nop11087 = alloca i1, i1 0
-  %nop11088 = alloca i1, i1 0
-  %nop11089 = alloca i1, i1 0
-  %nop11090 = alloca i1, i1 0
-  %nop11091 = alloca i1, i1 0
-  %nop11092 = alloca i1, i1 0
-  %nop11093 = alloca i1, i1 0
-  %nop11094 = alloca i1, i1 0
-  %nop11095 = alloca i1, i1 0
-  %nop11096 = alloca i1, i1 0
-  %nop11097 = alloca i1, i1 0
-  %nop11098 = alloca i1, i1 0
-  %nop11099 = alloca i1, i1 0
-  %nop11100 = alloca i1, i1 0
-  %nop11101 = alloca i1, i1 0
-  %nop11102 = alloca i1, i1 0
-  %nop11103 = alloca i1, i1 0
-  %nop11104 = alloca i1, i1 0
-  %nop11105 = alloca i1, i1 0
-  %nop11106 = alloca i1, i1 0
-  %nop11107 = alloca i1, i1 0
-  %nop11108 = alloca i1, i1 0
-  %nop11109 = alloca i1, i1 0
-  %nop11110 = alloca i1, i1 0
-  %nop11111 = alloca i1, i1 0
-  %nop11112 = alloca i1, i1 0
-  %nop11113 = alloca i1, i1 0
-  %nop11114 = alloca i1, i1 0
-  %nop11115 = alloca i1, i1 0
-  %nop11116 = alloca i1, i1 0
-  %nop11117 = alloca i1, i1 0
-  %nop11118 = alloca i1, i1 0
-  %nop11119 = alloca i1, i1 0
-  %nop11120 = alloca i1, i1 0
-  %nop11121 = alloca i1, i1 0
-  %nop11122 = alloca i1, i1 0
-  %nop11123 = alloca i1, i1 0
-  %nop11124 = alloca i1, i1 0
-  %nop11125 = alloca i1, i1 0
-  %nop11126 = alloca i1, i1 0
-  %nop11127 = alloca i1, i1 0
-  %nop11128 = alloca i1, i1 0
-  %nop11129 = alloca i1, i1 0
-  %nop11130 = alloca i1, i1 0
-  %nop11131 = alloca i1, i1 0
-  %nop11132 = alloca i1, i1 0
-  %nop11133 = alloca i1, i1 0
-  %nop11134 = alloca i1, i1 0
-  %nop11135 = alloca i1, i1 0
-  %nop11136 = alloca i1, i1 0
-  %nop11137 = alloca i1, i1 0
-  %nop11138 = alloca i1, i1 0
-  %nop11139 = alloca i1, i1 0
-  %nop11140 = alloca i1, i1 0
-  %nop11141 = alloca i1, i1 0
-  %nop11142 = alloca i1, i1 0
-  %nop11143 = alloca i1, i1 0
-  %nop11144 = alloca i1, i1 0
-  %nop11145 = alloca i1, i1 0
-  %nop11146 = alloca i1, i1 0
-  %nop11147 = alloca i1, i1 0
-  %nop11148 = alloca i1, i1 0
-  %nop11149 = alloca i1, i1 0
-  %nop11150 = alloca i1, i1 0
-  %nop11151 = alloca i1, i1 0
-  %nop11152 = alloca i1, i1 0
-  %nop11153 = alloca i1, i1 0
-  %nop11154 = alloca i1, i1 0
-  %nop11155 = alloca i1, i1 0
-  %nop11156 = alloca i1, i1 0
-  %nop11157 = alloca i1, i1 0
-  %nop11158 = alloca i1, i1 0
-  %nop11159 = alloca i1, i1 0
-  %nop11160 = alloca i1, i1 0
-  %nop11161 = alloca i1, i1 0
-  %nop11162 = alloca i1, i1 0
-  %nop11163 = alloca i1, i1 0
-  %nop11164 = alloca i1, i1 0
-  %nop11165 = alloca i1, i1 0
-  %nop11166 = alloca i1, i1 0
-  %nop11167 = alloca i1, i1 0
-  %nop11168 = alloca i1, i1 0
-  %nop11169 = alloca i1, i1 0
-  %nop11170 = alloca i1, i1 0
-  %nop11171 = alloca i1, i1 0
-  %nop11172 = alloca i1, i1 0
-  %nop11173 = alloca i1, i1 0
-  %nop11174 = alloca i1, i1 0
-  %nop11175 = alloca i1, i1 0
-  %nop11176 = alloca i1, i1 0
-  %nop11177 = alloca i1, i1 0
-  %nop11178 = alloca i1, i1 0
-  %nop11179 = alloca i1, i1 0
-  %nop11180 = alloca i1, i1 0
-  %nop11181 = alloca i1, i1 0
-  %nop11182 = alloca i1, i1 0
-  %nop11183 = alloca i1, i1 0
-  %nop11184 = alloca i1, i1 0
-  %nop11185 = alloca i1, i1 0
-  %nop11186 = alloca i1, i1 0
-  %nop11187 = alloca i1, i1 0
-  %nop11188 = alloca i1, i1 0
-  %nop11189 = alloca i1, i1 0
-  %nop11190 = alloca i1, i1 0
-  %nop11191 = alloca i1, i1 0
-  %nop11192 = alloca i1, i1 0
-  %nop11193 = alloca i1, i1 0
-  %nop11194 = alloca i1, i1 0
-  %nop11195 = alloca i1, i1 0
-  %nop11196 = alloca i1, i1 0
-  %nop11197 = alloca i1, i1 0
-  %nop11198 = alloca i1, i1 0
-  %nop11199 = alloca i1, i1 0
-  %nop11200 = alloca i1, i1 0
-  %nop11201 = alloca i1, i1 0
-  %nop11202 = alloca i1, i1 0
-  %nop11203 = alloca i1, i1 0
-  %nop11204 = alloca i1, i1 0
-  %nop11205 = alloca i1, i1 0
-  %nop11206 = alloca i1, i1 0
-  %nop11207 = alloca i1, i1 0
-  %nop11208 = alloca i1, i1 0
-  %nop11209 = alloca i1, i1 0
-  %nop11210 = alloca i1, i1 0
-  %nop11211 = alloca i1, i1 0
-  %nop11212 = alloca i1, i1 0
-  %nop11213 = alloca i1, i1 0
-  %nop11214 = alloca i1, i1 0
-  %nop11215 = alloca i1, i1 0
-  %nop11216 = alloca i1, i1 0
-  %nop11217 = alloca i1, i1 0
-  %nop11218 = alloca i1, i1 0
-  %nop11219 = alloca i1, i1 0
-  %nop11220 = alloca i1, i1 0
-  %nop11221 = alloca i1, i1 0
-  %nop11222 = alloca i1, i1 0
-  %nop11223 = alloca i1, i1 0
-  %nop11224 = alloca i1, i1 0
-  %nop11225 = alloca i1, i1 0
-  %nop11226 = alloca i1, i1 0
-  %nop11227 = alloca i1, i1 0
-  %nop11228 = alloca i1, i1 0
-  %nop11229 = alloca i1, i1 0
-  %nop11230 = alloca i1, i1 0
-  %nop11231 = alloca i1, i1 0
-  %nop11232 = alloca i1, i1 0
-  %nop11233 = alloca i1, i1 0
-  %nop11234 = alloca i1, i1 0
-  %nop11235 = alloca i1, i1 0
-  %nop11236 = alloca i1, i1 0
-  %nop11237 = alloca i1, i1 0
-  %nop11238 = alloca i1, i1 0
-  %nop11239 = alloca i1, i1 0
-  %nop11240 = alloca i1, i1 0
-  %nop11241 = alloca i1, i1 0
-  %nop11242 = alloca i1, i1 0
-  %nop11243 = alloca i1, i1 0
-  %nop11244 = alloca i1, i1 0
-  %nop11245 = alloca i1, i1 0
-  %nop11246 = alloca i1, i1 0
-  %nop11247 = alloca i1, i1 0
-  %nop11248 = alloca i1, i1 0
-  %nop11249 = alloca i1, i1 0
-  %nop11250 = alloca i1, i1 0
-  %nop11251 = alloca i1, i1 0
-  %nop11252 = alloca i1, i1 0
-  %nop11253 = alloca i1, i1 0
-  %nop11254 = alloca i1, i1 0
-  %nop11255 = alloca i1, i1 0
-  %nop11256 = alloca i1, i1 0
-  %nop11257 = alloca i1, i1 0
-  %nop11258 = alloca i1, i1 0
-  %nop11259 = alloca i1, i1 0
-  %nop11260 = alloca i1, i1 0
-  %nop11261 = alloca i1, i1 0
-  %nop11262 = alloca i1, i1 0
-  %nop11263 = alloca i1, i1 0
-  %nop11264 = alloca i1, i1 0
-  %nop11265 = alloca i1, i1 0
-  %nop11266 = alloca i1, i1 0
-  %nop11267 = alloca i1, i1 0
-  %nop11268 = alloca i1, i1 0
-  %nop11269 = alloca i1, i1 0
-  %nop11270 = alloca i1, i1 0
-  %nop11271 = alloca i1, i1 0
-  %nop11272 = alloca i1, i1 0
-  %nop11273 = alloca i1, i1 0
-  %nop11274 = alloca i1, i1 0
-  %nop11275 = alloca i1, i1 0
-  %nop11276 = alloca i1, i1 0
-  %nop11277 = alloca i1, i1 0
-  %nop11278 = alloca i1, i1 0
-  %nop11279 = alloca i1, i1 0
-  %nop11280 = alloca i1, i1 0
-  %nop11281 = alloca i1, i1 0
-  %nop11282 = alloca i1, i1 0
-  %nop11283 = alloca i1, i1 0
-  %nop11284 = alloca i1, i1 0
-  %nop11285 = alloca i1, i1 0
-  %nop11286 = alloca i1, i1 0
-  %nop11287 = alloca i1, i1 0
-  %nop11288 = alloca i1, i1 0
-  %nop11289 = alloca i1, i1 0
-  %nop11290 = alloca i1, i1 0
-  %nop11291 = alloca i1, i1 0
-  %nop11292 = alloca i1, i1 0
-  %nop11293 = alloca i1, i1 0
-  %nop11294 = alloca i1, i1 0
-  %nop11295 = alloca i1, i1 0
-  %nop11296 = alloca i1, i1 0
-  %nop11297 = alloca i1, i1 0
-  %nop11298 = alloca i1, i1 0
-  %nop11299 = alloca i1, i1 0
-  %nop11300 = alloca i1, i1 0
-  %nop11301 = alloca i1, i1 0
-  %nop11302 = alloca i1, i1 0
-  %nop11303 = alloca i1, i1 0
-  %nop11304 = alloca i1, i1 0
-  %nop11305 = alloca i1, i1 0
-  %nop11306 = alloca i1, i1 0
-  %nop11307 = alloca i1, i1 0
-  %nop11308 = alloca i1, i1 0
-  %nop11309 = alloca i1, i1 0
-  %nop11310 = alloca i1, i1 0
-  %nop11311 = alloca i1, i1 0
-  %nop11312 = alloca i1, i1 0
-  %nop11313 = alloca i1, i1 0
-  %nop11314 = alloca i1, i1 0
-  %nop11315 = alloca i1, i1 0
-  %nop11316 = alloca i1, i1 0
-  %nop11317 = alloca i1, i1 0
-  %nop11318 = alloca i1, i1 0
-  %nop11319 = alloca i1, i1 0
-  %nop11320 = alloca i1, i1 0
-  %nop11321 = alloca i1, i1 0
-  %nop11322 = alloca i1, i1 0
-  %nop11323 = alloca i1, i1 0
-  %nop11324 = alloca i1, i1 0
-  %nop11325 = alloca i1, i1 0
-  %nop11326 = alloca i1, i1 0
-  %nop11327 = alloca i1, i1 0
-  %nop11328 = alloca i1, i1 0
-  %nop11329 = alloca i1, i1 0
-  %nop11330 = alloca i1, i1 0
-  %nop11331 = alloca i1, i1 0
-  %nop11332 = alloca i1, i1 0
-  %nop11333 = alloca i1, i1 0
-  %nop11334 = alloca i1, i1 0
-  %nop11335 = alloca i1, i1 0
-  %nop11336 = alloca i1, i1 0
-  %nop11337 = alloca i1, i1 0
-  %nop11338 = alloca i1, i1 0
-  %nop11339 = alloca i1, i1 0
-  %nop11340 = alloca i1, i1 0
-  %nop11341 = alloca i1, i1 0
-  %nop11342 = alloca i1, i1 0
-  %nop11343 = alloca i1, i1 0
-  %nop11344 = alloca i1, i1 0
-  %nop11345 = alloca i1, i1 0
-  %nop11346 = alloca i1, i1 0
-  %nop11347 = alloca i1, i1 0
-  %nop11348 = alloca i1, i1 0
-  %nop11349 = alloca i1, i1 0
-  %nop11350 = alloca i1, i1 0
-  %nop11351 = alloca i1, i1 0
-  %nop11352 = alloca i1, i1 0
-  %nop11353 = alloca i1, i1 0
-  %nop11354 = alloca i1, i1 0
-  %nop11355 = alloca i1, i1 0
-  %nop11356 = alloca i1, i1 0
-  %nop11357 = alloca i1, i1 0
-  %nop11358 = alloca i1, i1 0
-  %nop11359 = alloca i1, i1 0
-  %nop11360 = alloca i1, i1 0
-  %nop11361 = alloca i1, i1 0
-  %nop11362 = alloca i1, i1 0
-  %nop11363 = alloca i1, i1 0
-  %nop11364 = alloca i1, i1 0
-  %nop11365 = alloca i1, i1 0
-  %nop11366 = alloca i1, i1 0
-  %nop11367 = alloca i1, i1 0
-  %nop11368 = alloca i1, i1 0
-  %nop11369 = alloca i1, i1 0
-  %nop11370 = alloca i1, i1 0
-  %nop11371 = alloca i1, i1 0
-  %nop11372 = alloca i1, i1 0
-  %nop11373 = alloca i1, i1 0
-  %nop11374 = alloca i1, i1 0
-  %nop11375 = alloca i1, i1 0
-  %nop11376 = alloca i1, i1 0
-  %nop11377 = alloca i1, i1 0
-  %nop11378 = alloca i1, i1 0
-  %nop11379 = alloca i1, i1 0
-  %nop11380 = alloca i1, i1 0
-  %nop11381 = alloca i1, i1 0
-  %nop11382 = alloca i1, i1 0
-  %nop11383 = alloca i1, i1 0
-  %nop11384 = alloca i1, i1 0
-  %nop11385 = alloca i1, i1 0
-  %nop11386 = alloca i1, i1 0
-  %nop11387 = alloca i1, i1 0
-  %nop11388 = alloca i1, i1 0
-  %nop11389 = alloca i1, i1 0
-  %nop11390 = alloca i1, i1 0
-  %nop11391 = alloca i1, i1 0
-  %nop11392 = alloca i1, i1 0
-  %nop11393 = alloca i1, i1 0
-  %nop11394 = alloca i1, i1 0
-  %nop11395 = alloca i1, i1 0
-  %nop11396 = alloca i1, i1 0
-  %nop11397 = alloca i1, i1 0
-  %nop11398 = alloca i1, i1 0
-  %nop11399 = alloca i1, i1 0
-  %nop11400 = alloca i1, i1 0
-  %nop11401 = alloca i1, i1 0
-  %nop11402 = alloca i1, i1 0
-  %nop11403 = alloca i1, i1 0
-  %nop11404 = alloca i1, i1 0
-  %nop11405 = alloca i1, i1 0
-  %nop11406 = alloca i1, i1 0
-  %nop11407 = alloca i1, i1 0
-  %nop11408 = alloca i1, i1 0
-  %nop11409 = alloca i1, i1 0
-  %nop11410 = alloca i1, i1 0
-  %nop11411 = alloca i1, i1 0
-  %nop11412 = alloca i1, i1 0
-  %nop11413 = alloca i1, i1 0
-  %nop11414 = alloca i1, i1 0
-  %nop11415 = alloca i1, i1 0
-  %nop11416 = alloca i1, i1 0
-  %nop11417 = alloca i1, i1 0
-  %nop11418 = alloca i1, i1 0
-  %nop11419 = alloca i1, i1 0
-  %nop11420 = alloca i1, i1 0
-  %nop11421 = alloca i1, i1 0
-  %nop11422 = alloca i1, i1 0
-  %nop11423 = alloca i1, i1 0
-  %nop11424 = alloca i1, i1 0
-  %nop11425 = alloca i1, i1 0
-  %nop11426 = alloca i1, i1 0
-  %nop11427 = alloca i1, i1 0
-  %nop11428 = alloca i1, i1 0
-  %nop11429 = alloca i1, i1 0
-  %nop11430 = alloca i1, i1 0
-  %nop11431 = alloca i1, i1 0
-  %nop11432 = alloca i1, i1 0
-  %nop11433 = alloca i1, i1 0
-  %nop11434 = alloca i1, i1 0
-  %nop11435 = alloca i1, i1 0
-  %nop11436 = alloca i1, i1 0
-  %nop11437 = alloca i1, i1 0
-  %nop11438 = alloca i1, i1 0
-  %nop11439 = alloca i1, i1 0
-  %nop11440 = alloca i1, i1 0
-  %nop11441 = alloca i1, i1 0
-  %nop11442 = alloca i1, i1 0
-  %nop11443 = alloca i1, i1 0
-  %nop11444 = alloca i1, i1 0
-  %nop11445 = alloca i1, i1 0
-  %nop11446 = alloca i1, i1 0
-  %nop11447 = alloca i1, i1 0
-  %nop11448 = alloca i1, i1 0
-  %nop11449 = alloca i1, i1 0
-  %nop11450 = alloca i1, i1 0
-  %nop11451 = alloca i1, i1 0
-  %nop11452 = alloca i1, i1 0
-  %nop11453 = alloca i1, i1 0
-  %nop11454 = alloca i1, i1 0
-  %nop11455 = alloca i1, i1 0
-  %nop11456 = alloca i1, i1 0
-  %nop11457 = alloca i1, i1 0
-  %nop11458 = alloca i1, i1 0
-  %nop11459 = alloca i1, i1 0
-  %nop11460 = alloca i1, i1 0
-  %nop11461 = alloca i1, i1 0
-  %nop11462 = alloca i1, i1 0
-  %nop11463 = alloca i1, i1 0
-  %nop11464 = alloca i1, i1 0
-  %nop11465 = alloca i1, i1 0
-  %nop11466 = alloca i1, i1 0
-  %nop11467 = alloca i1, i1 0
-  %nop11468 = alloca i1, i1 0
-  %nop11469 = alloca i1, i1 0
-  %nop11470 = alloca i1, i1 0
-  %nop11471 = alloca i1, i1 0
-  %nop11472 = alloca i1, i1 0
-  %nop11473 = alloca i1, i1 0
-  %nop11474 = alloca i1, i1 0
-  %nop11475 = alloca i1, i1 0
-  %nop11476 = alloca i1, i1 0
-  %nop11477 = alloca i1, i1 0
-  %nop11478 = alloca i1, i1 0
-  %nop11479 = alloca i1, i1 0
-  %nop11480 = alloca i1, i1 0
-  %nop11481 = alloca i1, i1 0
-  %nop11482 = alloca i1, i1 0
-  %nop11483 = alloca i1, i1 0
-  %nop11484 = alloca i1, i1 0
-  %nop11485 = alloca i1, i1 0
-  %nop11486 = alloca i1, i1 0
-  %nop11487 = alloca i1, i1 0
-  %nop11488 = alloca i1, i1 0
-  %nop11489 = alloca i1, i1 0
-  %nop11490 = alloca i1, i1 0
-  %nop11491 = alloca i1, i1 0
-  %nop11492 = alloca i1, i1 0
-  %nop11493 = alloca i1, i1 0
-  %nop11494 = alloca i1, i1 0
-  %nop11495 = alloca i1, i1 0
-  %nop11496 = alloca i1, i1 0
-  %nop11497 = alloca i1, i1 0
-  %nop11498 = alloca i1, i1 0
-  %nop11499 = alloca i1, i1 0
-  %nop11500 = alloca i1, i1 0
-  %nop11501 = alloca i1, i1 0
-  %nop11502 = alloca i1, i1 0
-  %nop11503 = alloca i1, i1 0
-  %nop11504 = alloca i1, i1 0
-  %nop11505 = alloca i1, i1 0
-  %nop11506 = alloca i1, i1 0
-  %nop11507 = alloca i1, i1 0
-  %nop11508 = alloca i1, i1 0
-  %nop11509 = alloca i1, i1 0
-  %nop11510 = alloca i1, i1 0
-  %nop11511 = alloca i1, i1 0
-  %nop11512 = alloca i1, i1 0
-  %nop11513 = alloca i1, i1 0
-  %nop11514 = alloca i1, i1 0
-  %nop11515 = alloca i1, i1 0
-  %nop11516 = alloca i1, i1 0
-  %nop11517 = alloca i1, i1 0
-  %nop11518 = alloca i1, i1 0
-  %nop11519 = alloca i1, i1 0
-  %nop11520 = alloca i1, i1 0
-  %nop11521 = alloca i1, i1 0
-  %nop11522 = alloca i1, i1 0
-  %nop11523 = alloca i1, i1 0
-  %nop11524 = alloca i1, i1 0
-  %nop11525 = alloca i1, i1 0
-  %nop11526 = alloca i1, i1 0
-  %nop11527 = alloca i1, i1 0
-  %nop11528 = alloca i1, i1 0
-  %nop11529 = alloca i1, i1 0
-  %nop11530 = alloca i1, i1 0
-  %nop11531 = alloca i1, i1 0
-  %nop11532 = alloca i1, i1 0
-  %nop11533 = alloca i1, i1 0
-  %nop11534 = alloca i1, i1 0
-  %nop11535 = alloca i1, i1 0
-  %nop11536 = alloca i1, i1 0
-  %nop11537 = alloca i1, i1 0
-  %nop11538 = alloca i1, i1 0
-  %nop11539 = alloca i1, i1 0
-  %nop11540 = alloca i1, i1 0
-  %nop11541 = alloca i1, i1 0
-  %nop11542 = alloca i1, i1 0
-  %nop11543 = alloca i1, i1 0
-  %nop11544 = alloca i1, i1 0
-  %nop11545 = alloca i1, i1 0
-  %nop11546 = alloca i1, i1 0
-  %nop11547 = alloca i1, i1 0
-  %nop11548 = alloca i1, i1 0
-  %nop11549 = alloca i1, i1 0
-  %nop11550 = alloca i1, i1 0
-  %nop11551 = alloca i1, i1 0
-  %nop11552 = alloca i1, i1 0
-  %nop11553 = alloca i1, i1 0
-  %nop11554 = alloca i1, i1 0
-  %nop11555 = alloca i1, i1 0
-  %nop11556 = alloca i1, i1 0
-  %nop11557 = alloca i1, i1 0
-  %nop11558 = alloca i1, i1 0
-  %nop11559 = alloca i1, i1 0
-  %nop11560 = alloca i1, i1 0
-  %nop11561 = alloca i1, i1 0
-  %nop11562 = alloca i1, i1 0
-  %nop11563 = alloca i1, i1 0
-  %nop11564 = alloca i1, i1 0
-  %nop11565 = alloca i1, i1 0
-  %nop11566 = alloca i1, i1 0
-  %nop11567 = alloca i1, i1 0
-  %nop11568 = alloca i1, i1 0
-  %nop11569 = alloca i1, i1 0
-  %nop11570 = alloca i1, i1 0
-  %nop11571 = alloca i1, i1 0
-  %nop11572 = alloca i1, i1 0
-  %nop11573 = alloca i1, i1 0
-  %nop11574 = alloca i1, i1 0
-  %nop11575 = alloca i1, i1 0
-  %nop11576 = alloca i1, i1 0
-  %nop11577 = alloca i1, i1 0
-  %nop11578 = alloca i1, i1 0
-  %nop11579 = alloca i1, i1 0
-  %nop11580 = alloca i1, i1 0
-  %nop11581 = alloca i1, i1 0
-  %nop11582 = alloca i1, i1 0
-  %nop11583 = alloca i1, i1 0
-  %nop11584 = alloca i1, i1 0
-  %nop11585 = alloca i1, i1 0
-  %nop11586 = alloca i1, i1 0
-  %nop11587 = alloca i1, i1 0
-  %nop11588 = alloca i1, i1 0
-  %nop11589 = alloca i1, i1 0
-  %nop11590 = alloca i1, i1 0
-  %nop11591 = alloca i1, i1 0
-  %nop11592 = alloca i1, i1 0
-  %nop11593 = alloca i1, i1 0
-  %nop11594 = alloca i1, i1 0
-  %nop11595 = alloca i1, i1 0
-  %nop11596 = alloca i1, i1 0
-  %nop11597 = alloca i1, i1 0
-  %nop11598 = alloca i1, i1 0
-  %nop11599 = alloca i1, i1 0
-  %nop11600 = alloca i1, i1 0
-  %nop11601 = alloca i1, i1 0
-  %nop11602 = alloca i1, i1 0
-  %nop11603 = alloca i1, i1 0
-  %nop11604 = alloca i1, i1 0
-  %nop11605 = alloca i1, i1 0
-  %nop11606 = alloca i1, i1 0
-  %nop11607 = alloca i1, i1 0
-  %nop11608 = alloca i1, i1 0
-  %nop11609 = alloca i1, i1 0
-  %nop11610 = alloca i1, i1 0
-  %nop11611 = alloca i1, i1 0
-  %nop11612 = alloca i1, i1 0
-  %nop11613 = alloca i1, i1 0
-  %nop11614 = alloca i1, i1 0
-  %nop11615 = alloca i1, i1 0
-  %nop11616 = alloca i1, i1 0
-  %nop11617 = alloca i1, i1 0
-  %nop11618 = alloca i1, i1 0
-  %nop11619 = alloca i1, i1 0
-  %nop11620 = alloca i1, i1 0
-  %nop11621 = alloca i1, i1 0
-  %nop11622 = alloca i1, i1 0
-  %nop11623 = alloca i1, i1 0
-  %nop11624 = alloca i1, i1 0
-  %nop11625 = alloca i1, i1 0
-  %nop11626 = alloca i1, i1 0
-  %nop11627 = alloca i1, i1 0
-  %nop11628 = alloca i1, i1 0
-  %nop11629 = alloca i1, i1 0
-  %nop11630 = alloca i1, i1 0
-  %nop11631 = alloca i1, i1 0
-  %nop11632 = alloca i1, i1 0
-  %nop11633 = alloca i1, i1 0
-  %nop11634 = alloca i1, i1 0
-  %nop11635 = alloca i1, i1 0
-  %nop11636 = alloca i1, i1 0
-  %nop11637 = alloca i1, i1 0
-  %nop11638 = alloca i1, i1 0
-  %nop11639 = alloca i1, i1 0
-  %nop11640 = alloca i1, i1 0
-  %nop11641 = alloca i1, i1 0
-  %nop11642 = alloca i1, i1 0
-  %nop11643 = alloca i1, i1 0
-  %nop11644 = alloca i1, i1 0
-  %nop11645 = alloca i1, i1 0
-  %nop11646 = alloca i1, i1 0
-  %nop11647 = alloca i1, i1 0
-  %nop11648 = alloca i1, i1 0
-  %nop11649 = alloca i1, i1 0
-  %nop11650 = alloca i1, i1 0
-  %nop11651 = alloca i1, i1 0
-  %nop11652 = alloca i1, i1 0
-  %nop11653 = alloca i1, i1 0
-  %nop11654 = alloca i1, i1 0
-  %nop11655 = alloca i1, i1 0
-  %nop11656 = alloca i1, i1 0
-  %nop11657 = alloca i1, i1 0
-  %nop11658 = alloca i1, i1 0
-  %nop11659 = alloca i1, i1 0
-  %nop11660 = alloca i1, i1 0
-  %nop11661 = alloca i1, i1 0
-  %nop11662 = alloca i1, i1 0
-  %nop11663 = alloca i1, i1 0
-  %nop11664 = alloca i1, i1 0
-  %nop11665 = alloca i1, i1 0
-  %nop11666 = alloca i1, i1 0
-  %nop11667 = alloca i1, i1 0
-  %nop11668 = alloca i1, i1 0
-  %nop11669 = alloca i1, i1 0
-  %nop11670 = alloca i1, i1 0
-  %nop11671 = alloca i1, i1 0
-  %nop11672 = alloca i1, i1 0
-  %nop11673 = alloca i1, i1 0
-  %nop11674 = alloca i1, i1 0
-  %nop11675 = alloca i1, i1 0
-  %nop11676 = alloca i1, i1 0
-  %nop11677 = alloca i1, i1 0
-  %nop11678 = alloca i1, i1 0
-  %nop11679 = alloca i1, i1 0
-  %nop11680 = alloca i1, i1 0
-  %nop11681 = alloca i1, i1 0
-  %nop11682 = alloca i1, i1 0
-  %nop11683 = alloca i1, i1 0
-  %nop11684 = alloca i1, i1 0
-  %nop11685 = alloca i1, i1 0
-  %nop11686 = alloca i1, i1 0
-  %nop11687 = alloca i1, i1 0
-  %nop11688 = alloca i1, i1 0
-  %nop11689 = alloca i1, i1 0
-  %nop11690 = alloca i1, i1 0
-  %nop11691 = alloca i1, i1 0
-  %nop11692 = alloca i1, i1 0
-  %nop11693 = alloca i1, i1 0
-  %nop11694 = alloca i1, i1 0
-  %nop11695 = alloca i1, i1 0
-  %nop11696 = alloca i1, i1 0
-  %nop11697 = alloca i1, i1 0
-  %nop11698 = alloca i1, i1 0
-  %nop11699 = alloca i1, i1 0
-  %nop11700 = alloca i1, i1 0
-  %nop11701 = alloca i1, i1 0
-  %nop11702 = alloca i1, i1 0
-  %nop11703 = alloca i1, i1 0
-  %nop11704 = alloca i1, i1 0
-  %nop11705 = alloca i1, i1 0
-  %nop11706 = alloca i1, i1 0
-  %nop11707 = alloca i1, i1 0
-  %nop11708 = alloca i1, i1 0
-  %nop11709 = alloca i1, i1 0
-  %nop11710 = alloca i1, i1 0
-  %nop11711 = alloca i1, i1 0
-  %nop11712 = alloca i1, i1 0
-  %nop11713 = alloca i1, i1 0
-  %nop11714 = alloca i1, i1 0
-  %nop11715 = alloca i1, i1 0
-  %nop11716 = alloca i1, i1 0
-  %nop11717 = alloca i1, i1 0
-  %nop11718 = alloca i1, i1 0
-  %nop11719 = alloca i1, i1 0
-  %nop11720 = alloca i1, i1 0
-  %nop11721 = alloca i1, i1 0
-  %nop11722 = alloca i1, i1 0
-  %nop11723 = alloca i1, i1 0
-  %nop11724 = alloca i1, i1 0
-  %nop11725 = alloca i1, i1 0
-  %nop11726 = alloca i1, i1 0
-  %nop11727 = alloca i1, i1 0
-  %nop11728 = alloca i1, i1 0
-  %nop11729 = alloca i1, i1 0
-  %nop11730 = alloca i1, i1 0
-  %nop11731 = alloca i1, i1 0
-  %nop11732 = alloca i1, i1 0
-  %nop11733 = alloca i1, i1 0
-  %nop11734 = alloca i1, i1 0
-  %nop11735 = alloca i1, i1 0
-  %nop11736 = alloca i1, i1 0
-  %nop11737 = alloca i1, i1 0
-  %nop11738 = alloca i1, i1 0
-  %nop11739 = alloca i1, i1 0
-  %nop11740 = alloca i1, i1 0
-  %nop11741 = alloca i1, i1 0
-  %nop11742 = alloca i1, i1 0
-  %nop11743 = alloca i1, i1 0
-  %nop11744 = alloca i1, i1 0
-  %nop11745 = alloca i1, i1 0
-  %nop11746 = alloca i1, i1 0
-  %nop11747 = alloca i1, i1 0
-  %nop11748 = alloca i1, i1 0
-  %nop11749 = alloca i1, i1 0
-  %nop11750 = alloca i1, i1 0
-  %nop11751 = alloca i1, i1 0
-  %nop11752 = alloca i1, i1 0
-  %nop11753 = alloca i1, i1 0
-  %nop11754 = alloca i1, i1 0
-  %nop11755 = alloca i1, i1 0
-  %nop11756 = alloca i1, i1 0
-  %nop11757 = alloca i1, i1 0
-  %nop11758 = alloca i1, i1 0
-  %nop11759 = alloca i1, i1 0
-  %nop11760 = alloca i1, i1 0
-  %nop11761 = alloca i1, i1 0
-  %nop11762 = alloca i1, i1 0
-  %nop11763 = alloca i1, i1 0
-  %nop11764 = alloca i1, i1 0
-  %nop11765 = alloca i1, i1 0
-  %nop11766 = alloca i1, i1 0
-  %nop11767 = alloca i1, i1 0
-  %nop11768 = alloca i1, i1 0
-  %nop11769 = alloca i1, i1 0
-  %nop11770 = alloca i1, i1 0
-  %nop11771 = alloca i1, i1 0
-  %nop11772 = alloca i1, i1 0
-  %nop11773 = alloca i1, i1 0
-  %nop11774 = alloca i1, i1 0
-  %nop11775 = alloca i1, i1 0
-  %nop11776 = alloca i1, i1 0
-  %nop11777 = alloca i1, i1 0
-  %nop11778 = alloca i1, i1 0
-  %nop11779 = alloca i1, i1 0
-  %nop11780 = alloca i1, i1 0
-  %nop11781 = alloca i1, i1 0
-  %nop11782 = alloca i1, i1 0
-  %nop11783 = alloca i1, i1 0
-  %nop11784 = alloca i1, i1 0
-  %nop11785 = alloca i1, i1 0
-  %nop11786 = alloca i1, i1 0
-  %nop11787 = alloca i1, i1 0
-  %nop11788 = alloca i1, i1 0
-  %nop11789 = alloca i1, i1 0
-  %nop11790 = alloca i1, i1 0
-  %nop11791 = alloca i1, i1 0
-  %nop11792 = alloca i1, i1 0
-  %nop11793 = alloca i1, i1 0
-  %nop11794 = alloca i1, i1 0
-  %nop11795 = alloca i1, i1 0
-  %nop11796 = alloca i1, i1 0
-  %nop11797 = alloca i1, i1 0
-  %nop11798 = alloca i1, i1 0
-  %nop11799 = alloca i1, i1 0
-  %nop11800 = alloca i1, i1 0
-  %nop11801 = alloca i1, i1 0
-  %nop11802 = alloca i1, i1 0
-  %nop11803 = alloca i1, i1 0
-  %nop11804 = alloca i1, i1 0
-  %nop11805 = alloca i1, i1 0
-  %nop11806 = alloca i1, i1 0
-  %nop11807 = alloca i1, i1 0
-  %nop11808 = alloca i1, i1 0
-  %nop11809 = alloca i1, i1 0
-  %nop11810 = alloca i1, i1 0
-  %nop11811 = alloca i1, i1 0
-  %nop11812 = alloca i1, i1 0
-  %nop11813 = alloca i1, i1 0
-  %nop11814 = alloca i1, i1 0
-  %nop11815 = alloca i1, i1 0
-  %nop11816 = alloca i1, i1 0
-  %nop11817 = alloca i1, i1 0
-  %nop11818 = alloca i1, i1 0
-  %nop11819 = alloca i1, i1 0
-  %nop11820 = alloca i1, i1 0
-  %nop11821 = alloca i1, i1 0
-  %nop11822 = alloca i1, i1 0
-  %nop11823 = alloca i1, i1 0
-  %nop11824 = alloca i1, i1 0
-  %nop11825 = alloca i1, i1 0
-  %nop11826 = alloca i1, i1 0
-  %nop11827 = alloca i1, i1 0
-  %nop11828 = alloca i1, i1 0
-  %nop11829 = alloca i1, i1 0
-  %nop11830 = alloca i1, i1 0
-  %nop11831 = alloca i1, i1 0
-  %nop11832 = alloca i1, i1 0
-  %nop11833 = alloca i1, i1 0
-  %nop11834 = alloca i1, i1 0
-  %nop11835 = alloca i1, i1 0
-  %nop11836 = alloca i1, i1 0
-  %nop11837 = alloca i1, i1 0
-  %nop11838 = alloca i1, i1 0
-  %nop11839 = alloca i1, i1 0
-  %nop11840 = alloca i1, i1 0
-  %nop11841 = alloca i1, i1 0
-  %nop11842 = alloca i1, i1 0
-  %nop11843 = alloca i1, i1 0
-  %nop11844 = alloca i1, i1 0
-  %nop11845 = alloca i1, i1 0
-  %nop11846 = alloca i1, i1 0
-  %nop11847 = alloca i1, i1 0
-  %nop11848 = alloca i1, i1 0
-  %nop11849 = alloca i1, i1 0
-  %nop11850 = alloca i1, i1 0
-  %nop11851 = alloca i1, i1 0
-  %nop11852 = alloca i1, i1 0
-  %nop11853 = alloca i1, i1 0
-  %nop11854 = alloca i1, i1 0
-  %nop11855 = alloca i1, i1 0
-  %nop11856 = alloca i1, i1 0
-  %nop11857 = alloca i1, i1 0
-  %nop11858 = alloca i1, i1 0
-  %nop11859 = alloca i1, i1 0
-  %nop11860 = alloca i1, i1 0
-  %nop11861 = alloca i1, i1 0
-  %nop11862 = alloca i1, i1 0
-  %nop11863 = alloca i1, i1 0
-  %nop11864 = alloca i1, i1 0
-  %nop11865 = alloca i1, i1 0
-  %nop11866 = alloca i1, i1 0
-  %nop11867 = alloca i1, i1 0
-  %nop11868 = alloca i1, i1 0
-  %nop11869 = alloca i1, i1 0
-  %nop11870 = alloca i1, i1 0
-  %nop11871 = alloca i1, i1 0
-  %nop11872 = alloca i1, i1 0
-  %nop11873 = alloca i1, i1 0
-  %nop11874 = alloca i1, i1 0
-  %nop11875 = alloca i1, i1 0
-  %nop11876 = alloca i1, i1 0
-  %nop11877 = alloca i1, i1 0
-  %nop11878 = alloca i1, i1 0
-  %nop11879 = alloca i1, i1 0
-  %nop11880 = alloca i1, i1 0
-  %nop11881 = alloca i1, i1 0
-  %nop11882 = alloca i1, i1 0
-  %nop11883 = alloca i1, i1 0
-  %nop11884 = alloca i1, i1 0
-  %nop11885 = alloca i1, i1 0
-  %nop11886 = alloca i1, i1 0
-  %nop11887 = alloca i1, i1 0
-  %nop11888 = alloca i1, i1 0
-  %nop11889 = alloca i1, i1 0
-  %nop11890 = alloca i1, i1 0
-  %nop11891 = alloca i1, i1 0
-  %nop11892 = alloca i1, i1 0
-  %nop11893 = alloca i1, i1 0
-  %nop11894 = alloca i1, i1 0
-  %nop11895 = alloca i1, i1 0
-  %nop11896 = alloca i1, i1 0
-  %nop11897 = alloca i1, i1 0
-  %nop11898 = alloca i1, i1 0
-  %nop11899 = alloca i1, i1 0
-  %nop11900 = alloca i1, i1 0
-  %nop11901 = alloca i1, i1 0
-  %nop11902 = alloca i1, i1 0
-  %nop11903 = alloca i1, i1 0
-  %nop11904 = alloca i1, i1 0
-  %nop11905 = alloca i1, i1 0
-  %nop11906 = alloca i1, i1 0
-  %nop11907 = alloca i1, i1 0
-  %nop11908 = alloca i1, i1 0
-  %nop11909 = alloca i1, i1 0
-  %nop11910 = alloca i1, i1 0
-  %nop11911 = alloca i1, i1 0
-  %nop11912 = alloca i1, i1 0
-  %nop11913 = alloca i1, i1 0
-  %nop11914 = alloca i1, i1 0
-  %nop11915 = alloca i1, i1 0
-  %nop11916 = alloca i1, i1 0
-  %nop11917 = alloca i1, i1 0
-  %nop11918 = alloca i1, i1 0
-  %nop11919 = alloca i1, i1 0
-  %nop11920 = alloca i1, i1 0
-  %nop11921 = alloca i1, i1 0
-  %nop11922 = alloca i1, i1 0
-  %nop11923 = alloca i1, i1 0
-  %nop11924 = alloca i1, i1 0
-  %nop11925 = alloca i1, i1 0
-  %nop11926 = alloca i1, i1 0
-  %nop11927 = alloca i1, i1 0
-  %nop11928 = alloca i1, i1 0
-  %nop11929 = alloca i1, i1 0
-  %nop11930 = alloca i1, i1 0
-  %nop11931 = alloca i1, i1 0
-  %nop11932 = alloca i1, i1 0
-  %nop11933 = alloca i1, i1 0
-  %nop11934 = alloca i1, i1 0
-  %nop11935 = alloca i1, i1 0
-  %nop11936 = alloca i1, i1 0
-  %nop11937 = alloca i1, i1 0
-  %nop11938 = alloca i1, i1 0
-  %nop11939 = alloca i1, i1 0
-  %nop11940 = alloca i1, i1 0
-  %nop11941 = alloca i1, i1 0
-  %nop11942 = alloca i1, i1 0
-  %nop11943 = alloca i1, i1 0
-  %nop11944 = alloca i1, i1 0
-  %nop11945 = alloca i1, i1 0
-  %nop11946 = alloca i1, i1 0
-  %nop11947 = alloca i1, i1 0
-  %nop11948 = alloca i1, i1 0
-  %nop11949 = alloca i1, i1 0
-  %nop11950 = alloca i1, i1 0
-  %nop11951 = alloca i1, i1 0
-  %nop11952 = alloca i1, i1 0
-  %nop11953 = alloca i1, i1 0
-  %nop11954 = alloca i1, i1 0
-  %nop11955 = alloca i1, i1 0
-  %nop11956 = alloca i1, i1 0
-  %nop11957 = alloca i1, i1 0
-  %nop11958 = alloca i1, i1 0
-  %nop11959 = alloca i1, i1 0
-  %nop11960 = alloca i1, i1 0
-  %nop11961 = alloca i1, i1 0
-  %nop11962 = alloca i1, i1 0
-  %nop11963 = alloca i1, i1 0
-  %nop11964 = alloca i1, i1 0
-  %nop11965 = alloca i1, i1 0
-  %nop11966 = alloca i1, i1 0
-  %nop11967 = alloca i1, i1 0
-  %nop11968 = alloca i1, i1 0
-  %nop11969 = alloca i1, i1 0
-  %nop11970 = alloca i1, i1 0
-  %nop11971 = alloca i1, i1 0
-  %nop11972 = alloca i1, i1 0
-  %nop11973 = alloca i1, i1 0
-  %nop11974 = alloca i1, i1 0
-  %nop11975 = alloca i1, i1 0
-  %nop11976 = alloca i1, i1 0
-  %nop11977 = alloca i1, i1 0
-  %nop11978 = alloca i1, i1 0
-  %nop11979 = alloca i1, i1 0
-  %nop11980 = alloca i1, i1 0
-  %nop11981 = alloca i1, i1 0
-  %nop11982 = alloca i1, i1 0
-  %nop11983 = alloca i1, i1 0
-  %nop11984 = alloca i1, i1 0
-  %nop11985 = alloca i1, i1 0
-  %nop11986 = alloca i1, i1 0
-  %nop11987 = alloca i1, i1 0
-  %nop11988 = alloca i1, i1 0
-  %nop11989 = alloca i1, i1 0
-  %nop11990 = alloca i1, i1 0
-  %nop11991 = alloca i1, i1 0
-  %nop11992 = alloca i1, i1 0
-  %nop11993 = alloca i1, i1 0
-  %nop11994 = alloca i1, i1 0
-  %nop11995 = alloca i1, i1 0
-  %nop11996 = alloca i1, i1 0
-  %nop11997 = alloca i1, i1 0
-  %nop11998 = alloca i1, i1 0
-  %nop11999 = alloca i1, i1 0
-  %nop12000 = alloca i1, i1 0
-  %nop12001 = alloca i1, i1 0
-  %nop12002 = alloca i1, i1 0
-  %nop12003 = alloca i1, i1 0
-  %nop12004 = alloca i1, i1 0
-  %nop12005 = alloca i1, i1 0
-  %nop12006 = alloca i1, i1 0
-  %nop12007 = alloca i1, i1 0
-  %nop12008 = alloca i1, i1 0
-  %nop12009 = alloca i1, i1 0
-  %nop12010 = alloca i1, i1 0
-  %nop12011 = alloca i1, i1 0
-  %nop12012 = alloca i1, i1 0
-  %nop12013 = alloca i1, i1 0
-  %nop12014 = alloca i1, i1 0
-  %nop12015 = alloca i1, i1 0
-  %nop12016 = alloca i1, i1 0
-  %nop12017 = alloca i1, i1 0
-  %nop12018 = alloca i1, i1 0
-  %nop12019 = alloca i1, i1 0
-  %nop12020 = alloca i1, i1 0
-  %nop12021 = alloca i1, i1 0
-  %nop12022 = alloca i1, i1 0
-  %nop12023 = alloca i1, i1 0
-  %nop12024 = alloca i1, i1 0
-  %nop12025 = alloca i1, i1 0
-  %nop12026 = alloca i1, i1 0
-  %nop12027 = alloca i1, i1 0
-  %nop12028 = alloca i1, i1 0
-  %nop12029 = alloca i1, i1 0
-  %nop12030 = alloca i1, i1 0
-  %nop12031 = alloca i1, i1 0
-  %nop12032 = alloca i1, i1 0
-  %nop12033 = alloca i1, i1 0
-  %nop12034 = alloca i1, i1 0
-  %nop12035 = alloca i1, i1 0
-  %nop12036 = alloca i1, i1 0
-  %nop12037 = alloca i1, i1 0
-  %nop12038 = alloca i1, i1 0
-  %nop12039 = alloca i1, i1 0
-  %nop12040 = alloca i1, i1 0
-  %nop12041 = alloca i1, i1 0
-  %nop12042 = alloca i1, i1 0
-  %nop12043 = alloca i1, i1 0
-  %nop12044 = alloca i1, i1 0
-  %nop12045 = alloca i1, i1 0
-  %nop12046 = alloca i1, i1 0
-  %nop12047 = alloca i1, i1 0
-  %nop12048 = alloca i1, i1 0
-  %nop12049 = alloca i1, i1 0
-  %nop12050 = alloca i1, i1 0
-  %nop12051 = alloca i1, i1 0
-  %nop12052 = alloca i1, i1 0
-  %nop12053 = alloca i1, i1 0
-  %nop12054 = alloca i1, i1 0
-  %nop12055 = alloca i1, i1 0
-  %nop12056 = alloca i1, i1 0
-  %nop12057 = alloca i1, i1 0
-  %nop12058 = alloca i1, i1 0
-  %nop12059 = alloca i1, i1 0
-  %nop12060 = alloca i1, i1 0
-  %nop12061 = alloca i1, i1 0
-  %nop12062 = alloca i1, i1 0
-  %nop12063 = alloca i1, i1 0
-  %nop12064 = alloca i1, i1 0
-  %nop12065 = alloca i1, i1 0
-  %nop12066 = alloca i1, i1 0
-  %nop12067 = alloca i1, i1 0
-  %nop12068 = alloca i1, i1 0
-  %nop12069 = alloca i1, i1 0
-  %nop12070 = alloca i1, i1 0
-  %nop12071 = alloca i1, i1 0
-  %nop12072 = alloca i1, i1 0
-  %nop12073 = alloca i1, i1 0
-  %nop12074 = alloca i1, i1 0
-  %nop12075 = alloca i1, i1 0
-  %nop12076 = alloca i1, i1 0
-  %nop12077 = alloca i1, i1 0
-  %nop12078 = alloca i1, i1 0
-  %nop12079 = alloca i1, i1 0
-  %nop12080 = alloca i1, i1 0
-  %nop12081 = alloca i1, i1 0
-  %nop12082 = alloca i1, i1 0
-  %nop12083 = alloca i1, i1 0
-  %nop12084 = alloca i1, i1 0
-  %nop12085 = alloca i1, i1 0
-  %nop12086 = alloca i1, i1 0
-  %nop12087 = alloca i1, i1 0
-  %nop12088 = alloca i1, i1 0
-  %nop12089 = alloca i1, i1 0
-  %nop12090 = alloca i1, i1 0
-  %nop12091 = alloca i1, i1 0
-  %nop12092 = alloca i1, i1 0
-  %nop12093 = alloca i1, i1 0
-  %nop12094 = alloca i1, i1 0
-  %nop12095 = alloca i1, i1 0
-  %nop12096 = alloca i1, i1 0
-  %nop12097 = alloca i1, i1 0
-  %nop12098 = alloca i1, i1 0
-  %nop12099 = alloca i1, i1 0
-  %nop12100 = alloca i1, i1 0
-  %nop12101 = alloca i1, i1 0
-  %nop12102 = alloca i1, i1 0
-  %nop12103 = alloca i1, i1 0
-  %nop12104 = alloca i1, i1 0
-  %nop12105 = alloca i1, i1 0
-  %nop12106 = alloca i1, i1 0
-  %nop12107 = alloca i1, i1 0
-  %nop12108 = alloca i1, i1 0
-  %nop12109 = alloca i1, i1 0
-  %nop12110 = alloca i1, i1 0
-  %nop12111 = alloca i1, i1 0
-  %nop12112 = alloca i1, i1 0
-  %nop12113 = alloca i1, i1 0
-  %nop12114 = alloca i1, i1 0
-  %nop12115 = alloca i1, i1 0
-  %nop12116 = alloca i1, i1 0
-  %nop12117 = alloca i1, i1 0
-  %nop12118 = alloca i1, i1 0
-  %nop12119 = alloca i1, i1 0
-  %nop12120 = alloca i1, i1 0
-  %nop12121 = alloca i1, i1 0
-  %nop12122 = alloca i1, i1 0
-  %nop12123 = alloca i1, i1 0
-  %nop12124 = alloca i1, i1 0
-  %nop12125 = alloca i1, i1 0
-  %nop12126 = alloca i1, i1 0
-  %nop12127 = alloca i1, i1 0
-  %nop12128 = alloca i1, i1 0
-  %nop12129 = alloca i1, i1 0
-  %nop12130 = alloca i1, i1 0
-  %nop12131 = alloca i1, i1 0
-  %nop12132 = alloca i1, i1 0
-  %nop12133 = alloca i1, i1 0
-  %nop12134 = alloca i1, i1 0
-  %nop12135 = alloca i1, i1 0
-  %nop12136 = alloca i1, i1 0
-  %nop12137 = alloca i1, i1 0
-  %nop12138 = alloca i1, i1 0
-  %nop12139 = alloca i1, i1 0
-  %nop12140 = alloca i1, i1 0
-  %nop12141 = alloca i1, i1 0
-  %nop12142 = alloca i1, i1 0
-  %nop12143 = alloca i1, i1 0
-  %nop12144 = alloca i1, i1 0
-  %nop12145 = alloca i1, i1 0
-  %nop12146 = alloca i1, i1 0
-  %nop12147 = alloca i1, i1 0
-  %nop12148 = alloca i1, i1 0
-  %nop12149 = alloca i1, i1 0
-  %nop12150 = alloca i1, i1 0
-  %nop12151 = alloca i1, i1 0
-  %nop12152 = alloca i1, i1 0
-  %nop12153 = alloca i1, i1 0
-  %nop12154 = alloca i1, i1 0
-  %nop12155 = alloca i1, i1 0
-  %nop12156 = alloca i1, i1 0
-  %nop12157 = alloca i1, i1 0
-  %nop12158 = alloca i1, i1 0
-  %nop12159 = alloca i1, i1 0
-  %nop12160 = alloca i1, i1 0
-  %nop12161 = alloca i1, i1 0
-  %nop12162 = alloca i1, i1 0
-  %nop12163 = alloca i1, i1 0
-  %nop12164 = alloca i1, i1 0
-  %nop12165 = alloca i1, i1 0
-  %nop12166 = alloca i1, i1 0
-  %nop12167 = alloca i1, i1 0
-  %nop12168 = alloca i1, i1 0
-  %nop12169 = alloca i1, i1 0
-  %nop12170 = alloca i1, i1 0
-  %nop12171 = alloca i1, i1 0
-  %nop12172 = alloca i1, i1 0
-  %nop12173 = alloca i1, i1 0
-  %nop12174 = alloca i1, i1 0
-  %nop12175 = alloca i1, i1 0
-  %nop12176 = alloca i1, i1 0
-  %nop12177 = alloca i1, i1 0
-  %nop12178 = alloca i1, i1 0
-  %nop12179 = alloca i1, i1 0
-  %nop12180 = alloca i1, i1 0
-  %nop12181 = alloca i1, i1 0
-  %nop12182 = alloca i1, i1 0
-  %nop12183 = alloca i1, i1 0
-  %nop12184 = alloca i1, i1 0
-  %nop12185 = alloca i1, i1 0
-  %nop12186 = alloca i1, i1 0
-  %nop12187 = alloca i1, i1 0
-  %nop12188 = alloca i1, i1 0
-  %nop12189 = alloca i1, i1 0
-  %nop12190 = alloca i1, i1 0
-  %nop12191 = alloca i1, i1 0
-  %nop12192 = alloca i1, i1 0
-  %nop12193 = alloca i1, i1 0
-  %nop12194 = alloca i1, i1 0
-  %nop12195 = alloca i1, i1 0
-  %nop12196 = alloca i1, i1 0
-  %nop12197 = alloca i1, i1 0
-  %nop12198 = alloca i1, i1 0
-  %nop12199 = alloca i1, i1 0
-  %nop12200 = alloca i1, i1 0
-  %nop12201 = alloca i1, i1 0
-  %nop12202 = alloca i1, i1 0
-  %nop12203 = alloca i1, i1 0
-  %nop12204 = alloca i1, i1 0
-  %nop12205 = alloca i1, i1 0
-  %nop12206 = alloca i1, i1 0
-  %nop12207 = alloca i1, i1 0
-  %nop12208 = alloca i1, i1 0
-  %nop12209 = alloca i1, i1 0
-  %nop12210 = alloca i1, i1 0
-  %nop12211 = alloca i1, i1 0
-  %nop12212 = alloca i1, i1 0
-  %nop12213 = alloca i1, i1 0
-  %nop12214 = alloca i1, i1 0
-  %nop12215 = alloca i1, i1 0
-  %nop12216 = alloca i1, i1 0
-  %nop12217 = alloca i1, i1 0
-  %nop12218 = alloca i1, i1 0
-  %nop12219 = alloca i1, i1 0
-  %nop12220 = alloca i1, i1 0
-  %nop12221 = alloca i1, i1 0
-  %nop12222 = alloca i1, i1 0
-  %nop12223 = alloca i1, i1 0
-  %nop12224 = alloca i1, i1 0
-  %nop12225 = alloca i1, i1 0
-  %nop12226 = alloca i1, i1 0
-  %nop12227 = alloca i1, i1 0
-  %nop12228 = alloca i1, i1 0
-  %nop12229 = alloca i1, i1 0
-  %nop12230 = alloca i1, i1 0
-  %nop12231 = alloca i1, i1 0
-  %nop12232 = alloca i1, i1 0
-  %nop12233 = alloca i1, i1 0
-  %nop12234 = alloca i1, i1 0
-  %nop12235 = alloca i1, i1 0
-  %nop12236 = alloca i1, i1 0
-  %nop12237 = alloca i1, i1 0
-  %nop12238 = alloca i1, i1 0
-  %nop12239 = alloca i1, i1 0
-  %nop12240 = alloca i1, i1 0
-  %nop12241 = alloca i1, i1 0
-  %nop12242 = alloca i1, i1 0
-  %nop12243 = alloca i1, i1 0
-  %nop12244 = alloca i1, i1 0
-  %nop12245 = alloca i1, i1 0
-  %nop12246 = alloca i1, i1 0
-  %nop12247 = alloca i1, i1 0
-  %nop12248 = alloca i1, i1 0
-  %nop12249 = alloca i1, i1 0
-  %nop12250 = alloca i1, i1 0
-  %nop12251 = alloca i1, i1 0
-  %nop12252 = alloca i1, i1 0
-  %nop12253 = alloca i1, i1 0
-  %nop12254 = alloca i1, i1 0
-  %nop12255 = alloca i1, i1 0
-  %nop12256 = alloca i1, i1 0
-  %nop12257 = alloca i1, i1 0
-  %nop12258 = alloca i1, i1 0
-  %nop12259 = alloca i1, i1 0
-  %nop12260 = alloca i1, i1 0
-  %nop12261 = alloca i1, i1 0
-  %nop12262 = alloca i1, i1 0
-  %nop12263 = alloca i1, i1 0
-  %nop12264 = alloca i1, i1 0
-  %nop12265 = alloca i1, i1 0
-  %nop12266 = alloca i1, i1 0
-  %nop12267 = alloca i1, i1 0
-  %nop12268 = alloca i1, i1 0
-  %nop12269 = alloca i1, i1 0
-  %nop12270 = alloca i1, i1 0
-  %nop12271 = alloca i1, i1 0
-  %nop12272 = alloca i1, i1 0
-  %nop12273 = alloca i1, i1 0
-  %nop12274 = alloca i1, i1 0
-  %nop12275 = alloca i1, i1 0
-  %nop12276 = alloca i1, i1 0
-  %nop12277 = alloca i1, i1 0
-  %nop12278 = alloca i1, i1 0
-  %nop12279 = alloca i1, i1 0
-  %nop12280 = alloca i1, i1 0
-  %nop12281 = alloca i1, i1 0
-  %nop12282 = alloca i1, i1 0
-  %nop12283 = alloca i1, i1 0
-  %nop12284 = alloca i1, i1 0
-  %nop12285 = alloca i1, i1 0
-  %nop12286 = alloca i1, i1 0
-  %nop12287 = alloca i1, i1 0
-  %nop12288 = alloca i1, i1 0
-  %nop12289 = alloca i1, i1 0
-  %nop12290 = alloca i1, i1 0
-  %nop12291 = alloca i1, i1 0
-  %nop12292 = alloca i1, i1 0
-  %nop12293 = alloca i1, i1 0
-  %nop12294 = alloca i1, i1 0
-  %nop12295 = alloca i1, i1 0
-  %nop12296 = alloca i1, i1 0
-  %nop12297 = alloca i1, i1 0
-  %nop12298 = alloca i1, i1 0
-  %nop12299 = alloca i1, i1 0
-  %nop12300 = alloca i1, i1 0
-  %nop12301 = alloca i1, i1 0
-  %nop12302 = alloca i1, i1 0
-  %nop12303 = alloca i1, i1 0
-  %nop12304 = alloca i1, i1 0
-  %nop12305 = alloca i1, i1 0
-  %nop12306 = alloca i1, i1 0
-  %nop12307 = alloca i1, i1 0
-  %nop12308 = alloca i1, i1 0
-  %nop12309 = alloca i1, i1 0
-  %nop12310 = alloca i1, i1 0
-  %nop12311 = alloca i1, i1 0
-  %nop12312 = alloca i1, i1 0
-  %nop12313 = alloca i1, i1 0
-  %nop12314 = alloca i1, i1 0
-  %nop12315 = alloca i1, i1 0
-  %nop12316 = alloca i1, i1 0
-  %nop12317 = alloca i1, i1 0
-  %nop12318 = alloca i1, i1 0
-  %nop12319 = alloca i1, i1 0
-  %nop12320 = alloca i1, i1 0
-  %nop12321 = alloca i1, i1 0
-  %nop12322 = alloca i1, i1 0
-  %nop12323 = alloca i1, i1 0
-  %nop12324 = alloca i1, i1 0
-  %nop12325 = alloca i1, i1 0
-  %nop12326 = alloca i1, i1 0
-  %nop12327 = alloca i1, i1 0
-  %nop12328 = alloca i1, i1 0
-  %nop12329 = alloca i1, i1 0
-  %nop12330 = alloca i1, i1 0
-  %nop12331 = alloca i1, i1 0
-  %nop12332 = alloca i1, i1 0
-  %nop12333 = alloca i1, i1 0
-  %nop12334 = alloca i1, i1 0
-  %nop12335 = alloca i1, i1 0
-  %nop12336 = alloca i1, i1 0
-  %nop12337 = alloca i1, i1 0
-  %nop12338 = alloca i1, i1 0
-  %nop12339 = alloca i1, i1 0
-  %nop12340 = alloca i1, i1 0
-  %nop12341 = alloca i1, i1 0
-  %nop12342 = alloca i1, i1 0
-  %nop12343 = alloca i1, i1 0
-  %nop12344 = alloca i1, i1 0
-  %nop12345 = alloca i1, i1 0
-  %nop12346 = alloca i1, i1 0
-  %nop12347 = alloca i1, i1 0
-  %nop12348 = alloca i1, i1 0
-  %nop12349 = alloca i1, i1 0
-  %nop12350 = alloca i1, i1 0
-  %nop12351 = alloca i1, i1 0
-  %nop12352 = alloca i1, i1 0
-  %nop12353 = alloca i1, i1 0
-  %nop12354 = alloca i1, i1 0
-  %nop12355 = alloca i1, i1 0
-  %nop12356 = alloca i1, i1 0
-  %nop12357 = alloca i1, i1 0
-  %nop12358 = alloca i1, i1 0
-  %nop12359 = alloca i1, i1 0
-  %nop12360 = alloca i1, i1 0
-  %nop12361 = alloca i1, i1 0
-  %nop12362 = alloca i1, i1 0
-  %nop12363 = alloca i1, i1 0
-  %nop12364 = alloca i1, i1 0
-  %nop12365 = alloca i1, i1 0
-  %nop12366 = alloca i1, i1 0
-  %nop12367 = alloca i1, i1 0
-  %nop12368 = alloca i1, i1 0
-  %nop12369 = alloca i1, i1 0
-  %nop12370 = alloca i1, i1 0
-  %nop12371 = alloca i1, i1 0
-  %nop12372 = alloca i1, i1 0
-  %nop12373 = alloca i1, i1 0
-  %nop12374 = alloca i1, i1 0
-  %nop12375 = alloca i1, i1 0
-  %nop12376 = alloca i1, i1 0
-  %nop12377 = alloca i1, i1 0
-  %nop12378 = alloca i1, i1 0
-  %nop12379 = alloca i1, i1 0
-  %nop12380 = alloca i1, i1 0
-  %nop12381 = alloca i1, i1 0
-  %nop12382 = alloca i1, i1 0
-  %nop12383 = alloca i1, i1 0
-  %nop12384 = alloca i1, i1 0
-  %nop12385 = alloca i1, i1 0
-  %nop12386 = alloca i1, i1 0
-  %nop12387 = alloca i1, i1 0
-  %nop12388 = alloca i1, i1 0
-  %nop12389 = alloca i1, i1 0
-  %nop12390 = alloca i1, i1 0
-  %nop12391 = alloca i1, i1 0
-  %nop12392 = alloca i1, i1 0
-  %nop12393 = alloca i1, i1 0
-  %nop12394 = alloca i1, i1 0
-  %nop12395 = alloca i1, i1 0
-  %nop12396 = alloca i1, i1 0
-  %nop12397 = alloca i1, i1 0
-  %nop12398 = alloca i1, i1 0
-  %nop12399 = alloca i1, i1 0
-  %nop12400 = alloca i1, i1 0
-  %nop12401 = alloca i1, i1 0
-  %nop12402 = alloca i1, i1 0
-  %nop12403 = alloca i1, i1 0
-  %nop12404 = alloca i1, i1 0
-  %nop12405 = alloca i1, i1 0
-  %nop12406 = alloca i1, i1 0
-  %nop12407 = alloca i1, i1 0
-  %nop12408 = alloca i1, i1 0
-  %nop12409 = alloca i1, i1 0
-  %nop12410 = alloca i1, i1 0
-  %nop12411 = alloca i1, i1 0
-  %nop12412 = alloca i1, i1 0
-  %nop12413 = alloca i1, i1 0
-  %nop12414 = alloca i1, i1 0
-  %nop12415 = alloca i1, i1 0
-  %nop12416 = alloca i1, i1 0
-  %nop12417 = alloca i1, i1 0
-  %nop12418 = alloca i1, i1 0
-  %nop12419 = alloca i1, i1 0
-  %nop12420 = alloca i1, i1 0
-  %nop12421 = alloca i1, i1 0
-  %nop12422 = alloca i1, i1 0
-  %nop12423 = alloca i1, i1 0
-  %nop12424 = alloca i1, i1 0
-  %nop12425 = alloca i1, i1 0
-  %nop12426 = alloca i1, i1 0
-  %nop12427 = alloca i1, i1 0
-  %nop12428 = alloca i1, i1 0
-  %nop12429 = alloca i1, i1 0
-  %nop12430 = alloca i1, i1 0
-  %nop12431 = alloca i1, i1 0
-  %nop12432 = alloca i1, i1 0
-  %nop12433 = alloca i1, i1 0
-  %nop12434 = alloca i1, i1 0
-  %nop12435 = alloca i1, i1 0
-  %nop12436 = alloca i1, i1 0
-  %nop12437 = alloca i1, i1 0
-  %nop12438 = alloca i1, i1 0
-  %nop12439 = alloca i1, i1 0
-  %nop12440 = alloca i1, i1 0
-  %nop12441 = alloca i1, i1 0
-  %nop12442 = alloca i1, i1 0
-  %nop12443 = alloca i1, i1 0
-  %nop12444 = alloca i1, i1 0
-  %nop12445 = alloca i1, i1 0
-  %nop12446 = alloca i1, i1 0
-  %nop12447 = alloca i1, i1 0
-  %nop12448 = alloca i1, i1 0
-  %nop12449 = alloca i1, i1 0
-  %nop12450 = alloca i1, i1 0
-  %nop12451 = alloca i1, i1 0
-  %nop12452 = alloca i1, i1 0
-  %nop12453 = alloca i1, i1 0
-  %nop12454 = alloca i1, i1 0
-  %nop12455 = alloca i1, i1 0
-  %nop12456 = alloca i1, i1 0
-  %nop12457 = alloca i1, i1 0
-  %nop12458 = alloca i1, i1 0
-  %nop12459 = alloca i1, i1 0
-  %nop12460 = alloca i1, i1 0
-  %nop12461 = alloca i1, i1 0
-  %nop12462 = alloca i1, i1 0
-  %nop12463 = alloca i1, i1 0
-  %nop12464 = alloca i1, i1 0
-  %nop12465 = alloca i1, i1 0
-  %nop12466 = alloca i1, i1 0
-  %nop12467 = alloca i1, i1 0
-  %nop12468 = alloca i1, i1 0
-  %nop12469 = alloca i1, i1 0
-  %nop12470 = alloca i1, i1 0
-  %nop12471 = alloca i1, i1 0
-  %nop12472 = alloca i1, i1 0
-  %nop12473 = alloca i1, i1 0
-  %nop12474 = alloca i1, i1 0
-  %nop12475 = alloca i1, i1 0
-  %nop12476 = alloca i1, i1 0
-  %nop12477 = alloca i1, i1 0
-  %nop12478 = alloca i1, i1 0
-  %nop12479 = alloca i1, i1 0
-  %nop12480 = alloca i1, i1 0
-  %nop12481 = alloca i1, i1 0
-  %nop12482 = alloca i1, i1 0
-  %nop12483 = alloca i1, i1 0
-  %nop12484 = alloca i1, i1 0
-  %nop12485 = alloca i1, i1 0
-  %nop12486 = alloca i1, i1 0
-  %nop12487 = alloca i1, i1 0
-  %nop12488 = alloca i1, i1 0
-  %nop12489 = alloca i1, i1 0
-  %nop12490 = alloca i1, i1 0
-  %nop12491 = alloca i1, i1 0
-  %nop12492 = alloca i1, i1 0
-  %nop12493 = alloca i1, i1 0
-  %nop12494 = alloca i1, i1 0
-  %nop12495 = alloca i1, i1 0
-  %nop12496 = alloca i1, i1 0
-  %nop12497 = alloca i1, i1 0
-  %nop12498 = alloca i1, i1 0
-  %nop12499 = alloca i1, i1 0
-  %nop12500 = alloca i1, i1 0
-  %nop12501 = alloca i1, i1 0
-  %nop12502 = alloca i1, i1 0
-  %nop12503 = alloca i1, i1 0
-  %nop12504 = alloca i1, i1 0
-  %nop12505 = alloca i1, i1 0
-  %nop12506 = alloca i1, i1 0
-  %nop12507 = alloca i1, i1 0
-  %nop12508 = alloca i1, i1 0
-  %nop12509 = alloca i1, i1 0
-  %nop12510 = alloca i1, i1 0
-  %nop12511 = alloca i1, i1 0
-  %nop12512 = alloca i1, i1 0
-  %nop12513 = alloca i1, i1 0
-  %nop12514 = alloca i1, i1 0
-  %nop12515 = alloca i1, i1 0
-  %nop12516 = alloca i1, i1 0
-  %nop12517 = alloca i1, i1 0
-  %nop12518 = alloca i1, i1 0
-  %nop12519 = alloca i1, i1 0
-  %nop12520 = alloca i1, i1 0
-  %nop12521 = alloca i1, i1 0
-  %nop12522 = alloca i1, i1 0
-  %nop12523 = alloca i1, i1 0
-  %nop12524 = alloca i1, i1 0
-  %nop12525 = alloca i1, i1 0
-  %nop12526 = alloca i1, i1 0
-  %nop12527 = alloca i1, i1 0
-  %nop12528 = alloca i1, i1 0
-  %nop12529 = alloca i1, i1 0
-  %nop12530 = alloca i1, i1 0
-  %nop12531 = alloca i1, i1 0
-  %nop12532 = alloca i1, i1 0
-  %nop12533 = alloca i1, i1 0
-  %nop12534 = alloca i1, i1 0
-  %nop12535 = alloca i1, i1 0
-  %nop12536 = alloca i1, i1 0
-  %nop12537 = alloca i1, i1 0
-  %nop12538 = alloca i1, i1 0
-  %nop12539 = alloca i1, i1 0
-  %nop12540 = alloca i1, i1 0
-  %nop12541 = alloca i1, i1 0
-  %nop12542 = alloca i1, i1 0
-  %nop12543 = alloca i1, i1 0
-  %nop12544 = alloca i1, i1 0
-  %nop12545 = alloca i1, i1 0
-  %nop12546 = alloca i1, i1 0
-  %nop12547 = alloca i1, i1 0
-  %nop12548 = alloca i1, i1 0
-  %nop12549 = alloca i1, i1 0
-  %nop12550 = alloca i1, i1 0
-  %nop12551 = alloca i1, i1 0
-  %nop12552 = alloca i1, i1 0
-  %nop12553 = alloca i1, i1 0
-  %nop12554 = alloca i1, i1 0
-  %nop12555 = alloca i1, i1 0
-  %nop12556 = alloca i1, i1 0
-  %nop12557 = alloca i1, i1 0
-  %nop12558 = alloca i1, i1 0
-  %nop12559 = alloca i1, i1 0
-  %nop12560 = alloca i1, i1 0
-  %nop12561 = alloca i1, i1 0
-  %nop12562 = alloca i1, i1 0
-  %nop12563 = alloca i1, i1 0
-  %nop12564 = alloca i1, i1 0
-  %nop12565 = alloca i1, i1 0
-  %nop12566 = alloca i1, i1 0
-  %nop12567 = alloca i1, i1 0
-  %nop12568 = alloca i1, i1 0
-  %nop12569 = alloca i1, i1 0
-  %nop12570 = alloca i1, i1 0
-  %nop12571 = alloca i1, i1 0
-  %nop12572 = alloca i1, i1 0
-  %nop12573 = alloca i1, i1 0
-  %nop12574 = alloca i1, i1 0
-  %nop12575 = alloca i1, i1 0
-  %nop12576 = alloca i1, i1 0
-  %nop12577 = alloca i1, i1 0
-  %nop12578 = alloca i1, i1 0
-  %nop12579 = alloca i1, i1 0
-  %nop12580 = alloca i1, i1 0
-  %nop12581 = alloca i1, i1 0
-  %nop12582 = alloca i1, i1 0
-  %nop12583 = alloca i1, i1 0
-  %nop12584 = alloca i1, i1 0
-  %nop12585 = alloca i1, i1 0
-  %nop12586 = alloca i1, i1 0
-  %nop12587 = alloca i1, i1 0
-  %nop12588 = alloca i1, i1 0
-  %nop12589 = alloca i1, i1 0
-  %nop12590 = alloca i1, i1 0
-  %nop12591 = alloca i1, i1 0
-  %nop12592 = alloca i1, i1 0
-  %nop12593 = alloca i1, i1 0
-  %nop12594 = alloca i1, i1 0
-  %nop12595 = alloca i1, i1 0
-  %nop12596 = alloca i1, i1 0
-  %nop12597 = alloca i1, i1 0
-  %nop12598 = alloca i1, i1 0
-  %nop12599 = alloca i1, i1 0
-  %nop12600 = alloca i1, i1 0
-  %nop12601 = alloca i1, i1 0
-  %nop12602 = alloca i1, i1 0
-  %nop12603 = alloca i1, i1 0
-  %nop12604 = alloca i1, i1 0
-  %nop12605 = alloca i1, i1 0
-  %nop12606 = alloca i1, i1 0
-  %nop12607 = alloca i1, i1 0
-  %nop12608 = alloca i1, i1 0
-  %nop12609 = alloca i1, i1 0
-  %nop12610 = alloca i1, i1 0
-  %nop12611 = alloca i1, i1 0
-  %nop12612 = alloca i1, i1 0
-  %nop12613 = alloca i1, i1 0
-  %nop12614 = alloca i1, i1 0
-  %nop12615 = alloca i1, i1 0
-  %nop12616 = alloca i1, i1 0
-  %nop12617 = alloca i1, i1 0
-  %nop12618 = alloca i1, i1 0
-  %nop12619 = alloca i1, i1 0
-  %nop12620 = alloca i1, i1 0
-  %nop12621 = alloca i1, i1 0
-  %nop12622 = alloca i1, i1 0
-  %nop12623 = alloca i1, i1 0
-  %nop12624 = alloca i1, i1 0
-  %nop12625 = alloca i1, i1 0
-  %nop12626 = alloca i1, i1 0
-  %nop12627 = alloca i1, i1 0
-  %nop12628 = alloca i1, i1 0
-  %nop12629 = alloca i1, i1 0
-  %nop12630 = alloca i1, i1 0
-  %nop12631 = alloca i1, i1 0
-  %nop12632 = alloca i1, i1 0
-  %nop12633 = alloca i1, i1 0
-  %nop12634 = alloca i1, i1 0
-  %nop12635 = alloca i1, i1 0
-  %nop12636 = alloca i1, i1 0
-  %nop12637 = alloca i1, i1 0
-  %nop12638 = alloca i1, i1 0
-  %nop12639 = alloca i1, i1 0
-  %nop12640 = alloca i1, i1 0
-  %nop12641 = alloca i1, i1 0
-  %nop12642 = alloca i1, i1 0
-  %nop12643 = alloca i1, i1 0
-  %nop12644 = alloca i1, i1 0
-  %nop12645 = alloca i1, i1 0
-  %nop12646 = alloca i1, i1 0
-  %nop12647 = alloca i1, i1 0
-  %nop12648 = alloca i1, i1 0
-  %nop12649 = alloca i1, i1 0
-  %nop12650 = alloca i1, i1 0
-  %nop12651 = alloca i1, i1 0
-  %nop12652 = alloca i1, i1 0
-  %nop12653 = alloca i1, i1 0
-  %nop12654 = alloca i1, i1 0
-  %nop12655 = alloca i1, i1 0
-  %nop12656 = alloca i1, i1 0
-  %nop12657 = alloca i1, i1 0
-  %nop12658 = alloca i1, i1 0
-  %nop12659 = alloca i1, i1 0
-  %nop12660 = alloca i1, i1 0
-  %nop12661 = alloca i1, i1 0
-  %nop12662 = alloca i1, i1 0
-  %nop12663 = alloca i1, i1 0
-  %nop12664 = alloca i1, i1 0
-  %nop12665 = alloca i1, i1 0
-  %nop12666 = alloca i1, i1 0
-  %nop12667 = alloca i1, i1 0
-  %nop12668 = alloca i1, i1 0
-  %nop12669 = alloca i1, i1 0
-  %nop12670 = alloca i1, i1 0
-  %nop12671 = alloca i1, i1 0
-  %nop12672 = alloca i1, i1 0
-  %nop12673 = alloca i1, i1 0
-  %nop12674 = alloca i1, i1 0
-  %nop12675 = alloca i1, i1 0
-  %nop12676 = alloca i1, i1 0
-  %nop12677 = alloca i1, i1 0
-  %nop12678 = alloca i1, i1 0
-  %nop12679 = alloca i1, i1 0
-  %nop12680 = alloca i1, i1 0
-  %nop12681 = alloca i1, i1 0
-  %nop12682 = alloca i1, i1 0
-  %nop12683 = alloca i1, i1 0
-  %nop12684 = alloca i1, i1 0
-  %nop12685 = alloca i1, i1 0
-  %nop12686 = alloca i1, i1 0
-  %nop12687 = alloca i1, i1 0
-  %nop12688 = alloca i1, i1 0
-  %nop12689 = alloca i1, i1 0
-  %nop12690 = alloca i1, i1 0
-  %nop12691 = alloca i1, i1 0
-  %nop12692 = alloca i1, i1 0
-  %nop12693 = alloca i1, i1 0
-  %nop12694 = alloca i1, i1 0
-  %nop12695 = alloca i1, i1 0
-  %nop12696 = alloca i1, i1 0
-  %nop12697 = alloca i1, i1 0
-  %nop12698 = alloca i1, i1 0
-  %nop12699 = alloca i1, i1 0
-  %nop12700 = alloca i1, i1 0
-  %nop12701 = alloca i1, i1 0
-  %nop12702 = alloca i1, i1 0
-  %nop12703 = alloca i1, i1 0
-  %nop12704 = alloca i1, i1 0
-  %nop12705 = alloca i1, i1 0
-  %nop12706 = alloca i1, i1 0
-  %nop12707 = alloca i1, i1 0
-  %nop12708 = alloca i1, i1 0
-  %nop12709 = alloca i1, i1 0
-  %nop12710 = alloca i1, i1 0
-  %nop12711 = alloca i1, i1 0
-  %nop12712 = alloca i1, i1 0
-  %nop12713 = alloca i1, i1 0
-  %nop12714 = alloca i1, i1 0
-  %nop12715 = alloca i1, i1 0
-  %nop12716 = alloca i1, i1 0
-  %nop12717 = alloca i1, i1 0
-  %nop12718 = alloca i1, i1 0
-  %nop12719 = alloca i1, i1 0
-  %nop12720 = alloca i1, i1 0
-  %nop12721 = alloca i1, i1 0
-  %nop12722 = alloca i1, i1 0
-  %nop12723 = alloca i1, i1 0
-  %nop12724 = alloca i1, i1 0
-  %nop12725 = alloca i1, i1 0
-  %nop12726 = alloca i1, i1 0
-  %nop12727 = alloca i1, i1 0
-  %nop12728 = alloca i1, i1 0
-  %nop12729 = alloca i1, i1 0
-  %nop12730 = alloca i1, i1 0
-  %nop12731 = alloca i1, i1 0
-  %nop12732 = alloca i1, i1 0
-  %nop12733 = alloca i1, i1 0
-  %nop12734 = alloca i1, i1 0
-  %nop12735 = alloca i1, i1 0
-  %nop12736 = alloca i1, i1 0
-  %nop12737 = alloca i1, i1 0
-  %nop12738 = alloca i1, i1 0
-  %nop12739 = alloca i1, i1 0
-  %nop12740 = alloca i1, i1 0
-  %nop12741 = alloca i1, i1 0
-  %nop12742 = alloca i1, i1 0
-  %nop12743 = alloca i1, i1 0
-  %nop12744 = alloca i1, i1 0
-  %nop12745 = alloca i1, i1 0
-  %nop12746 = alloca i1, i1 0
-  %nop12747 = alloca i1, i1 0
-  %nop12748 = alloca i1, i1 0
-  %nop12749 = alloca i1, i1 0
-  %nop12750 = alloca i1, i1 0
-  %nop12751 = alloca i1, i1 0
-  %nop12752 = alloca i1, i1 0
-  %nop12753 = alloca i1, i1 0
-  %nop12754 = alloca i1, i1 0
-  %nop12755 = alloca i1, i1 0
-  %nop12756 = alloca i1, i1 0
-  %nop12757 = alloca i1, i1 0
-  %nop12758 = alloca i1, i1 0
-  %nop12759 = alloca i1, i1 0
-  %nop12760 = alloca i1, i1 0
-  %nop12761 = alloca i1, i1 0
-  %nop12762 = alloca i1, i1 0
-  %nop12763 = alloca i1, i1 0
-  %nop12764 = alloca i1, i1 0
-  %nop12765 = alloca i1, i1 0
-  %nop12766 = alloca i1, i1 0
-  %nop12767 = alloca i1, i1 0
-  %nop12768 = alloca i1, i1 0
-  %nop12769 = alloca i1, i1 0
-  %nop12770 = alloca i1, i1 0
-  %nop12771 = alloca i1, i1 0
-  %nop12772 = alloca i1, i1 0
-  %nop12773 = alloca i1, i1 0
-  %nop12774 = alloca i1, i1 0
-  %nop12775 = alloca i1, i1 0
-  %nop12776 = alloca i1, i1 0
-  %nop12777 = alloca i1, i1 0
-  %nop12778 = alloca i1, i1 0
-  %nop12779 = alloca i1, i1 0
-  %nop12780 = alloca i1, i1 0
-  %nop12781 = alloca i1, i1 0
-  %nop12782 = alloca i1, i1 0
-  %nop12783 = alloca i1, i1 0
-  %nop12784 = alloca i1, i1 0
-  %nop12785 = alloca i1, i1 0
-  %nop12786 = alloca i1, i1 0
-  %nop12787 = alloca i1, i1 0
-  %nop12788 = alloca i1, i1 0
-  %nop12789 = alloca i1, i1 0
-  %nop12790 = alloca i1, i1 0
-  %nop12791 = alloca i1, i1 0
-  %nop12792 = alloca i1, i1 0
-  %nop12793 = alloca i1, i1 0
-  %nop12794 = alloca i1, i1 0
-  %nop12795 = alloca i1, i1 0
-  %nop12796 = alloca i1, i1 0
-  %nop12797 = alloca i1, i1 0
-  %nop12798 = alloca i1, i1 0
-  %nop12799 = alloca i1, i1 0
-  %nop12800 = alloca i1, i1 0
-  %nop12801 = alloca i1, i1 0
-  %nop12802 = alloca i1, i1 0
-  %nop12803 = alloca i1, i1 0
-  %nop12804 = alloca i1, i1 0
-  %nop12805 = alloca i1, i1 0
-  %nop12806 = alloca i1, i1 0
-  %nop12807 = alloca i1, i1 0
-  %nop12808 = alloca i1, i1 0
-  %nop12809 = alloca i1, i1 0
-  %nop12810 = alloca i1, i1 0
-  %nop12811 = alloca i1, i1 0
-  %nop12812 = alloca i1, i1 0
-  %nop12813 = alloca i1, i1 0
-  %nop12814 = alloca i1, i1 0
-  %nop12815 = alloca i1, i1 0
-  %nop12816 = alloca i1, i1 0
-  %nop12817 = alloca i1, i1 0
-  %nop12818 = alloca i1, i1 0
-  %nop12819 = alloca i1, i1 0
-  %nop12820 = alloca i1, i1 0
-  %nop12821 = alloca i1, i1 0
-  %nop12822 = alloca i1, i1 0
-  %nop12823 = alloca i1, i1 0
-  %nop12824 = alloca i1, i1 0
-  %nop12825 = alloca i1, i1 0
-  %nop12826 = alloca i1, i1 0
-  %nop12827 = alloca i1, i1 0
-  %nop12828 = alloca i1, i1 0
-  %nop12829 = alloca i1, i1 0
-  %nop12830 = alloca i1, i1 0
-  %nop12831 = alloca i1, i1 0
-  %nop12832 = alloca i1, i1 0
-  %nop12833 = alloca i1, i1 0
-  %nop12834 = alloca i1, i1 0
-  %nop12835 = alloca i1, i1 0
-  %nop12836 = alloca i1, i1 0
-  %nop12837 = alloca i1, i1 0
-  %nop12838 = alloca i1, i1 0
-  %nop12839 = alloca i1, i1 0
-  %nop12840 = alloca i1, i1 0
-  %nop12841 = alloca i1, i1 0
-  %nop12842 = alloca i1, i1 0
-  %nop12843 = alloca i1, i1 0
-  %nop12844 = alloca i1, i1 0
-  %nop12845 = alloca i1, i1 0
-  %nop12846 = alloca i1, i1 0
-  %nop12847 = alloca i1, i1 0
-  %nop12848 = alloca i1, i1 0
-  %nop12849 = alloca i1, i1 0
-  %nop12850 = alloca i1, i1 0
-  %nop12851 = alloca i1, i1 0
-  %nop12852 = alloca i1, i1 0
-  %nop12853 = alloca i1, i1 0
-  %nop12854 = alloca i1, i1 0
-  %nop12855 = alloca i1, i1 0
-  %nop12856 = alloca i1, i1 0
-  %nop12857 = alloca i1, i1 0
-  %nop12858 = alloca i1, i1 0
-  %nop12859 = alloca i1, i1 0
-  %nop12860 = alloca i1, i1 0
-  %nop12861 = alloca i1, i1 0
-  %nop12862 = alloca i1, i1 0
-  %nop12863 = alloca i1, i1 0
-  %nop12864 = alloca i1, i1 0
-  %nop12865 = alloca i1, i1 0
-  %nop12866 = alloca i1, i1 0
-  %nop12867 = alloca i1, i1 0
-  %nop12868 = alloca i1, i1 0
-  %nop12869 = alloca i1, i1 0
-  %nop12870 = alloca i1, i1 0
-  %nop12871 = alloca i1, i1 0
-  %nop12872 = alloca i1, i1 0
-  %nop12873 = alloca i1, i1 0
-  %nop12874 = alloca i1, i1 0
-  %nop12875 = alloca i1, i1 0
-  %nop12876 = alloca i1, i1 0
-  %nop12877 = alloca i1, i1 0
-  %nop12878 = alloca i1, i1 0
-  %nop12879 = alloca i1, i1 0
-  %nop12880 = alloca i1, i1 0
-  %nop12881 = alloca i1, i1 0
-  %nop12882 = alloca i1, i1 0
-  %nop12883 = alloca i1, i1 0
-  %nop12884 = alloca i1, i1 0
-  %nop12885 = alloca i1, i1 0
-  %nop12886 = alloca i1, i1 0
-  %nop12887 = alloca i1, i1 0
-  %nop12888 = alloca i1, i1 0
-  %nop12889 = alloca i1, i1 0
-  %nop12890 = alloca i1, i1 0
-  %nop12891 = alloca i1, i1 0
-  %nop12892 = alloca i1, i1 0
-  %nop12893 = alloca i1, i1 0
-  %nop12894 = alloca i1, i1 0
-  %nop12895 = alloca i1, i1 0
-  %nop12896 = alloca i1, i1 0
-  %nop12897 = alloca i1, i1 0
-  %nop12898 = alloca i1, i1 0
-  %nop12899 = alloca i1, i1 0
-  %nop12900 = alloca i1, i1 0
-  %nop12901 = alloca i1, i1 0
-  %nop12902 = alloca i1, i1 0
-  %nop12903 = alloca i1, i1 0
-  %nop12904 = alloca i1, i1 0
-  %nop12905 = alloca i1, i1 0
-  %nop12906 = alloca i1, i1 0
-  %nop12907 = alloca i1, i1 0
-  %nop12908 = alloca i1, i1 0
-  %nop12909 = alloca i1, i1 0
-  %nop12910 = alloca i1, i1 0
-  %nop12911 = alloca i1, i1 0
-  %nop12912 = alloca i1, i1 0
-  %nop12913 = alloca i1, i1 0
-  %nop12914 = alloca i1, i1 0
-  %nop12915 = alloca i1, i1 0
-  %nop12916 = alloca i1, i1 0
-  %nop12917 = alloca i1, i1 0
-  %nop12918 = alloca i1, i1 0
-  %nop12919 = alloca i1, i1 0
-  %nop12920 = alloca i1, i1 0
-  %nop12921 = alloca i1, i1 0
-  %nop12922 = alloca i1, i1 0
-  %nop12923 = alloca i1, i1 0
-  %nop12924 = alloca i1, i1 0
-  %nop12925 = alloca i1, i1 0
-  %nop12926 = alloca i1, i1 0
-  %nop12927 = alloca i1, i1 0
-  %nop12928 = alloca i1, i1 0
-  %nop12929 = alloca i1, i1 0
-  %nop12930 = alloca i1, i1 0
-  %nop12931 = alloca i1, i1 0
-  %nop12932 = alloca i1, i1 0
-  %nop12933 = alloca i1, i1 0
-  %nop12934 = alloca i1, i1 0
-  %nop12935 = alloca i1, i1 0
-  %nop12936 = alloca i1, i1 0
-  %nop12937 = alloca i1, i1 0
-  %nop12938 = alloca i1, i1 0
-  %nop12939 = alloca i1, i1 0
-  %nop12940 = alloca i1, i1 0
-  %nop12941 = alloca i1, i1 0
-  %nop12942 = alloca i1, i1 0
-  %nop12943 = alloca i1, i1 0
-  %nop12944 = alloca i1, i1 0
-  %nop12945 = alloca i1, i1 0
-  %nop12946 = alloca i1, i1 0
-  %nop12947 = alloca i1, i1 0
-  %nop12948 = alloca i1, i1 0
-  %nop12949 = alloca i1, i1 0
-  %nop12950 = alloca i1, i1 0
-  %nop12951 = alloca i1, i1 0
-  %nop12952 = alloca i1, i1 0
-  %nop12953 = alloca i1, i1 0
-  %nop12954 = alloca i1, i1 0
-  %nop12955 = alloca i1, i1 0
-  %nop12956 = alloca i1, i1 0
-  %nop12957 = alloca i1, i1 0
-  %nop12958 = alloca i1, i1 0
-  %nop12959 = alloca i1, i1 0
-  %nop12960 = alloca i1, i1 0
-  %nop12961 = alloca i1, i1 0
-  %nop12962 = alloca i1, i1 0
-  %nop12963 = alloca i1, i1 0
-  %nop12964 = alloca i1, i1 0
-  %nop12965 = alloca i1, i1 0
-  %nop12966 = alloca i1, i1 0
-  %nop12967 = alloca i1, i1 0
-  %nop12968 = alloca i1, i1 0
-  %nop12969 = alloca i1, i1 0
-  %nop12970 = alloca i1, i1 0
-  %nop12971 = alloca i1, i1 0
-  %nop12972 = alloca i1, i1 0
-  %nop12973 = alloca i1, i1 0
-  %nop12974 = alloca i1, i1 0
-  %nop12975 = alloca i1, i1 0
-  %nop12976 = alloca i1, i1 0
-  %nop12977 = alloca i1, i1 0
-  %nop12978 = alloca i1, i1 0
-  %nop12979 = alloca i1, i1 0
-  %nop12980 = alloca i1, i1 0
-  %nop12981 = alloca i1, i1 0
-  %nop12982 = alloca i1, i1 0
-  %nop12983 = alloca i1, i1 0
-  %nop12984 = alloca i1, i1 0
-  %nop12985 = alloca i1, i1 0
-  %nop12986 = alloca i1, i1 0
-  %nop12987 = alloca i1, i1 0
-  %nop12988 = alloca i1, i1 0
-  %nop12989 = alloca i1, i1 0
-  %nop12990 = alloca i1, i1 0
-  %nop12991 = alloca i1, i1 0
-  %nop12992 = alloca i1, i1 0
-  %nop12993 = alloca i1, i1 0
-  %nop12994 = alloca i1, i1 0
-  %nop12995 = alloca i1, i1 0
-  %nop12996 = alloca i1, i1 0
-  %nop12997 = alloca i1, i1 0
-  %nop12998 = alloca i1, i1 0
-  %nop12999 = alloca i1, i1 0
-  %nop13000 = alloca i1, i1 0
-  %nop13001 = alloca i1, i1 0
-  %nop13002 = alloca i1, i1 0
-  %nop13003 = alloca i1, i1 0
-  %nop13004 = alloca i1, i1 0
-  %nop13005 = alloca i1, i1 0
-  %nop13006 = alloca i1, i1 0
-  %nop13007 = alloca i1, i1 0
-  %nop13008 = alloca i1, i1 0
-  %nop13009 = alloca i1, i1 0
-  %nop13010 = alloca i1, i1 0
-  %nop13011 = alloca i1, i1 0
-  %nop13012 = alloca i1, i1 0
-  %nop13013 = alloca i1, i1 0
-  %nop13014 = alloca i1, i1 0
-  %nop13015 = alloca i1, i1 0
-  %nop13016 = alloca i1, i1 0
-  %nop13017 = alloca i1, i1 0
-  %nop13018 = alloca i1, i1 0
-  %nop13019 = alloca i1, i1 0
-  %nop13020 = alloca i1, i1 0
-  %nop13021 = alloca i1, i1 0
-  %nop13022 = alloca i1, i1 0
-  %nop13023 = alloca i1, i1 0
-  %nop13024 = alloca i1, i1 0
-  %nop13025 = alloca i1, i1 0
-  %nop13026 = alloca i1, i1 0
-  %nop13027 = alloca i1, i1 0
-  %nop13028 = alloca i1, i1 0
-  %nop13029 = alloca i1, i1 0
-  %nop13030 = alloca i1, i1 0
-  %nop13031 = alloca i1, i1 0
-  %nop13032 = alloca i1, i1 0
-  %nop13033 = alloca i1, i1 0
-  %nop13034 = alloca i1, i1 0
-  %nop13035 = alloca i1, i1 0
-  %nop13036 = alloca i1, i1 0
-  %nop13037 = alloca i1, i1 0
-  %nop13038 = alloca i1, i1 0
-  %nop13039 = alloca i1, i1 0
-  %nop13040 = alloca i1, i1 0
-  %nop13041 = alloca i1, i1 0
-  %nop13042 = alloca i1, i1 0
-  %nop13043 = alloca i1, i1 0
-  %nop13044 = alloca i1, i1 0
-  %nop13045 = alloca i1, i1 0
-  %nop13046 = alloca i1, i1 0
-  %nop13047 = alloca i1, i1 0
-  %nop13048 = alloca i1, i1 0
-  %nop13049 = alloca i1, i1 0
-  %nop13050 = alloca i1, i1 0
-  %nop13051 = alloca i1, i1 0
-  %nop13052 = alloca i1, i1 0
-  %nop13053 = alloca i1, i1 0
-  %nop13054 = alloca i1, i1 0
-  %nop13055 = alloca i1, i1 0
-  %nop13056 = alloca i1, i1 0
-  %nop13057 = alloca i1, i1 0
-  %nop13058 = alloca i1, i1 0
-  %nop13059 = alloca i1, i1 0
-  %nop13060 = alloca i1, i1 0
-  %nop13061 = alloca i1, i1 0
-  %nop13062 = alloca i1, i1 0
-  %nop13063 = alloca i1, i1 0
-  %nop13064 = alloca i1, i1 0
-  %nop13065 = alloca i1, i1 0
-  %nop13066 = alloca i1, i1 0
-  %nop13067 = alloca i1, i1 0
-  %nop13068 = alloca i1, i1 0
-  %nop13069 = alloca i1, i1 0
-  %nop13070 = alloca i1, i1 0
-  %nop13071 = alloca i1, i1 0
-  %nop13072 = alloca i1, i1 0
-  %nop13073 = alloca i1, i1 0
-  %nop13074 = alloca i1, i1 0
-  %nop13075 = alloca i1, i1 0
-  %nop13076 = alloca i1, i1 0
-  %nop13077 = alloca i1, i1 0
-  %nop13078 = alloca i1, i1 0
-  %nop13079 = alloca i1, i1 0
-  %nop13080 = alloca i1, i1 0
-  %nop13081 = alloca i1, i1 0
-  %nop13082 = alloca i1, i1 0
-  %nop13083 = alloca i1, i1 0
-  %nop13084 = alloca i1, i1 0
-  %nop13085 = alloca i1, i1 0
-  %nop13086 = alloca i1, i1 0
-  %nop13087 = alloca i1, i1 0
-  %nop13088 = alloca i1, i1 0
-  %nop13089 = alloca i1, i1 0
-  %nop13090 = alloca i1, i1 0
-  %nop13091 = alloca i1, i1 0
-  %nop13092 = alloca i1, i1 0
-  %nop13093 = alloca i1, i1 0
-  %nop13094 = alloca i1, i1 0
-  %nop13095 = alloca i1, i1 0
-  %nop13096 = alloca i1, i1 0
-  %nop13097 = alloca i1, i1 0
-  %nop13098 = alloca i1, i1 0
-  %nop13099 = alloca i1, i1 0
-  %nop13100 = alloca i1, i1 0
-  %nop13101 = alloca i1, i1 0
-  %nop13102 = alloca i1, i1 0
-  %nop13103 = alloca i1, i1 0
-  %nop13104 = alloca i1, i1 0
-  %nop13105 = alloca i1, i1 0
-  %nop13106 = alloca i1, i1 0
-  %nop13107 = alloca i1, i1 0
-  %nop13108 = alloca i1, i1 0
-  %nop13109 = alloca i1, i1 0
-  %nop13110 = alloca i1, i1 0
-  %nop13111 = alloca i1, i1 0
-  %nop13112 = alloca i1, i1 0
-  %nop13113 = alloca i1, i1 0
-  %nop13114 = alloca i1, i1 0
-  %nop13115 = alloca i1, i1 0
-  %nop13116 = alloca i1, i1 0
-  %nop13117 = alloca i1, i1 0
-  %nop13118 = alloca i1, i1 0
-  %nop13119 = alloca i1, i1 0
-  %nop13120 = alloca i1, i1 0
-  %nop13121 = alloca i1, i1 0
-  %nop13122 = alloca i1, i1 0
-  %nop13123 = alloca i1, i1 0
-  %nop13124 = alloca i1, i1 0
-  %nop13125 = alloca i1, i1 0
-  %nop13126 = alloca i1, i1 0
-  %nop13127 = alloca i1, i1 0
-  %nop13128 = alloca i1, i1 0
-  %nop13129 = alloca i1, i1 0
-  %nop13130 = alloca i1, i1 0
-  %nop13131 = alloca i1, i1 0
-  %nop13132 = alloca i1, i1 0
-  %nop13133 = alloca i1, i1 0
-  %nop13134 = alloca i1, i1 0
-  %nop13135 = alloca i1, i1 0
-  %nop13136 = alloca i1, i1 0
-  %nop13137 = alloca i1, i1 0
-  %nop13138 = alloca i1, i1 0
-  %nop13139 = alloca i1, i1 0
-  %nop13140 = alloca i1, i1 0
-  %nop13141 = alloca i1, i1 0
-  %nop13142 = alloca i1, i1 0
-  %nop13143 = alloca i1, i1 0
-  %nop13144 = alloca i1, i1 0
-  %nop13145 = alloca i1, i1 0
-  %nop13146 = alloca i1, i1 0
-  %nop13147 = alloca i1, i1 0
-  %nop13148 = alloca i1, i1 0
-  %nop13149 = alloca i1, i1 0
-  %nop13150 = alloca i1, i1 0
-  %nop13151 = alloca i1, i1 0
-  %nop13152 = alloca i1, i1 0
-  %nop13153 = alloca i1, i1 0
-  %nop13154 = alloca i1, i1 0
-  %nop13155 = alloca i1, i1 0
-  %nop13156 = alloca i1, i1 0
-  %nop13157 = alloca i1, i1 0
-  %nop13158 = alloca i1, i1 0
-  %nop13159 = alloca i1, i1 0
-  %nop13160 = alloca i1, i1 0
-  %nop13161 = alloca i1, i1 0
-  %nop13162 = alloca i1, i1 0
-  %nop13163 = alloca i1, i1 0
-  %nop13164 = alloca i1, i1 0
-  %nop13165 = alloca i1, i1 0
-  %nop13166 = alloca i1, i1 0
-  %nop13167 = alloca i1, i1 0
-  %nop13168 = alloca i1, i1 0
-  %nop13169 = alloca i1, i1 0
-  %nop13170 = alloca i1, i1 0
-  %nop13171 = alloca i1, i1 0
-  %nop13172 = alloca i1, i1 0
-  %nop13173 = alloca i1, i1 0
-  %nop13174 = alloca i1, i1 0
-  %nop13175 = alloca i1, i1 0
-  %nop13176 = alloca i1, i1 0
-  %nop13177 = alloca i1, i1 0
-  %nop13178 = alloca i1, i1 0
-  %nop13179 = alloca i1, i1 0
-  %nop13180 = alloca i1, i1 0
-  %nop13181 = alloca i1, i1 0
-  %nop13182 = alloca i1, i1 0
-  %nop13183 = alloca i1, i1 0
-  %nop13184 = alloca i1, i1 0
-  %nop13185 = alloca i1, i1 0
-  %nop13186 = alloca i1, i1 0
-  %nop13187 = alloca i1, i1 0
-  %nop13188 = alloca i1, i1 0
-  %nop13189 = alloca i1, i1 0
-  %nop13190 = alloca i1, i1 0
-  %nop13191 = alloca i1, i1 0
-  %nop13192 = alloca i1, i1 0
-  %nop13193 = alloca i1, i1 0
-  %nop13194 = alloca i1, i1 0
-  %nop13195 = alloca i1, i1 0
-  %nop13196 = alloca i1, i1 0
-  %nop13197 = alloca i1, i1 0
-  %nop13198 = alloca i1, i1 0
-  %nop13199 = alloca i1, i1 0
-  %nop13200 = alloca i1, i1 0
-  %nop13201 = alloca i1, i1 0
-  %nop13202 = alloca i1, i1 0
-  %nop13203 = alloca i1, i1 0
-  %nop13204 = alloca i1, i1 0
-  %nop13205 = alloca i1, i1 0
-  %nop13206 = alloca i1, i1 0
-  %nop13207 = alloca i1, i1 0
-  %nop13208 = alloca i1, i1 0
-  %nop13209 = alloca i1, i1 0
-  %nop13210 = alloca i1, i1 0
-  %nop13211 = alloca i1, i1 0
-  %nop13212 = alloca i1, i1 0
-  %nop13213 = alloca i1, i1 0
-  %nop13214 = alloca i1, i1 0
-  %nop13215 = alloca i1, i1 0
-  %nop13216 = alloca i1, i1 0
-  %nop13217 = alloca i1, i1 0
-  %nop13218 = alloca i1, i1 0
-  %nop13219 = alloca i1, i1 0
-  %nop13220 = alloca i1, i1 0
-  %nop13221 = alloca i1, i1 0
-  %nop13222 = alloca i1, i1 0
-  %nop13223 = alloca i1, i1 0
-  %nop13224 = alloca i1, i1 0
-  %nop13225 = alloca i1, i1 0
-  %nop13226 = alloca i1, i1 0
-  %nop13227 = alloca i1, i1 0
-  %nop13228 = alloca i1, i1 0
-  %nop13229 = alloca i1, i1 0
-  %nop13230 = alloca i1, i1 0
-  %nop13231 = alloca i1, i1 0
-  %nop13232 = alloca i1, i1 0
-  %nop13233 = alloca i1, i1 0
-  %nop13234 = alloca i1, i1 0
-  %nop13235 = alloca i1, i1 0
-  %nop13236 = alloca i1, i1 0
-  %nop13237 = alloca i1, i1 0
-  %nop13238 = alloca i1, i1 0
-  %nop13239 = alloca i1, i1 0
-  %nop13240 = alloca i1, i1 0
-  %nop13241 = alloca i1, i1 0
-  %nop13242 = alloca i1, i1 0
-  %nop13243 = alloca i1, i1 0
-  %nop13244 = alloca i1, i1 0
-  %nop13245 = alloca i1, i1 0
-  %nop13246 = alloca i1, i1 0
-  %nop13247 = alloca i1, i1 0
-  %nop13248 = alloca i1, i1 0
-  %nop13249 = alloca i1, i1 0
-  %nop13250 = alloca i1, i1 0
-  %nop13251 = alloca i1, i1 0
-  %nop13252 = alloca i1, i1 0
-  %nop13253 = alloca i1, i1 0
-  %nop13254 = alloca i1, i1 0
-  %nop13255 = alloca i1, i1 0
-  %nop13256 = alloca i1, i1 0
-  %nop13257 = alloca i1, i1 0
-  %nop13258 = alloca i1, i1 0
-  %nop13259 = alloca i1, i1 0
-  %nop13260 = alloca i1, i1 0
-  %nop13261 = alloca i1, i1 0
-  %nop13262 = alloca i1, i1 0
-  %nop13263 = alloca i1, i1 0
-  %nop13264 = alloca i1, i1 0
-  %nop13265 = alloca i1, i1 0
-  %nop13266 = alloca i1, i1 0
-  %nop13267 = alloca i1, i1 0
-  %nop13268 = alloca i1, i1 0
-  %nop13269 = alloca i1, i1 0
-  %nop13270 = alloca i1, i1 0
-  %nop13271 = alloca i1, i1 0
-  %nop13272 = alloca i1, i1 0
-  %nop13273 = alloca i1, i1 0
-  %nop13274 = alloca i1, i1 0
-  %nop13275 = alloca i1, i1 0
-  %nop13276 = alloca i1, i1 0
-  %nop13277 = alloca i1, i1 0
-  %nop13278 = alloca i1, i1 0
-  %nop13279 = alloca i1, i1 0
-  %nop13280 = alloca i1, i1 0
-  %nop13281 = alloca i1, i1 0
-  %nop13282 = alloca i1, i1 0
-  %nop13283 = alloca i1, i1 0
-  %nop13284 = alloca i1, i1 0
-  %nop13285 = alloca i1, i1 0
-  %nop13286 = alloca i1, i1 0
-  %nop13287 = alloca i1, i1 0
-  %nop13288 = alloca i1, i1 0
-  %nop13289 = alloca i1, i1 0
-  %nop13290 = alloca i1, i1 0
-  %nop13291 = alloca i1, i1 0
-  %nop13292 = alloca i1, i1 0
-  %nop13293 = alloca i1, i1 0
-  %nop13294 = alloca i1, i1 0
-  %nop13295 = alloca i1, i1 0
-  %nop13296 = alloca i1, i1 0
-  %nop13297 = alloca i1, i1 0
-  %nop13298 = alloca i1, i1 0
-  %nop13299 = alloca i1, i1 0
-  %nop13300 = alloca i1, i1 0
-  %nop13301 = alloca i1, i1 0
-  %nop13302 = alloca i1, i1 0
-  %nop13303 = alloca i1, i1 0
-  %nop13304 = alloca i1, i1 0
-  %nop13305 = alloca i1, i1 0
-  %nop13306 = alloca i1, i1 0
-  %nop13307 = alloca i1, i1 0
-  %nop13308 = alloca i1, i1 0
-  %nop13309 = alloca i1, i1 0
-  %nop13310 = alloca i1, i1 0
-  %nop13311 = alloca i1, i1 0
-  %nop13312 = alloca i1, i1 0
-  %nop13313 = alloca i1, i1 0
-  %nop13314 = alloca i1, i1 0
-  %nop13315 = alloca i1, i1 0
-  %nop13316 = alloca i1, i1 0
-  %nop13317 = alloca i1, i1 0
-  %nop13318 = alloca i1, i1 0
-  %nop13319 = alloca i1, i1 0
-  %nop13320 = alloca i1, i1 0
-  %nop13321 = alloca i1, i1 0
-  %nop13322 = alloca i1, i1 0
-  %nop13323 = alloca i1, i1 0
-  %nop13324 = alloca i1, i1 0
-  %nop13325 = alloca i1, i1 0
-  %nop13326 = alloca i1, i1 0
-  %nop13327 = alloca i1, i1 0
-  %nop13328 = alloca i1, i1 0
-  %nop13329 = alloca i1, i1 0
-  %nop13330 = alloca i1, i1 0
-  %nop13331 = alloca i1, i1 0
-  %nop13332 = alloca i1, i1 0
-  %nop13333 = alloca i1, i1 0
-  %nop13334 = alloca i1, i1 0
-  %nop13335 = alloca i1, i1 0
-  %nop13336 = alloca i1, i1 0
-  %nop13337 = alloca i1, i1 0
-  %nop13338 = alloca i1, i1 0
-  %nop13339 = alloca i1, i1 0
-  %nop13340 = alloca i1, i1 0
-  %nop13341 = alloca i1, i1 0
-  %nop13342 = alloca i1, i1 0
-  %nop13343 = alloca i1, i1 0
-  %nop13344 = alloca i1, i1 0
-  %nop13345 = alloca i1, i1 0
-  %nop13346 = alloca i1, i1 0
-  %nop13347 = alloca i1, i1 0
-  %nop13348 = alloca i1, i1 0
-  %nop13349 = alloca i1, i1 0
-  %nop13350 = alloca i1, i1 0
-  %nop13351 = alloca i1, i1 0
-  %nop13352 = alloca i1, i1 0
-  %nop13353 = alloca i1, i1 0
-  %nop13354 = alloca i1, i1 0
-  %nop13355 = alloca i1, i1 0
-  %nop13356 = alloca i1, i1 0
-  %nop13357 = alloca i1, i1 0
-  %nop13358 = alloca i1, i1 0
-  %nop13359 = alloca i1, i1 0
-  %nop13360 = alloca i1, i1 0
-  %nop13361 = alloca i1, i1 0
-  %nop13362 = alloca i1, i1 0
-  %nop13363 = alloca i1, i1 0
-  %nop13364 = alloca i1, i1 0
-  %nop13365 = alloca i1, i1 0
-  %nop13366 = alloca i1, i1 0
-  %nop13367 = alloca i1, i1 0
-  %nop13368 = alloca i1, i1 0
-  %nop13369 = alloca i1, i1 0
-  %nop13370 = alloca i1, i1 0
-  %nop13371 = alloca i1, i1 0
-  %nop13372 = alloca i1, i1 0
-  %nop13373 = alloca i1, i1 0
-  %nop13374 = alloca i1, i1 0
-  %nop13375 = alloca i1, i1 0
-  %nop13376 = alloca i1, i1 0
-  %nop13377 = alloca i1, i1 0
-  %nop13378 = alloca i1, i1 0
-  %nop13379 = alloca i1, i1 0
-  %nop13380 = alloca i1, i1 0
-  %nop13381 = alloca i1, i1 0
-  %nop13382 = alloca i1, i1 0
-  %nop13383 = alloca i1, i1 0
-  %nop13384 = alloca i1, i1 0
-  %nop13385 = alloca i1, i1 0
-  %nop13386 = alloca i1, i1 0
-  %nop13387 = alloca i1, i1 0
-  %nop13388 = alloca i1, i1 0
-  %nop13389 = alloca i1, i1 0
-  %nop13390 = alloca i1, i1 0
-  %nop13391 = alloca i1, i1 0
-  %nop13392 = alloca i1, i1 0
-  %nop13393 = alloca i1, i1 0
-  %nop13394 = alloca i1, i1 0
-  %nop13395 = alloca i1, i1 0
-  %nop13396 = alloca i1, i1 0
-  %nop13397 = alloca i1, i1 0
-  %nop13398 = alloca i1, i1 0
-  %nop13399 = alloca i1, i1 0
-  %nop13400 = alloca i1, i1 0
-  %nop13401 = alloca i1, i1 0
-  %nop13402 = alloca i1, i1 0
-  %nop13403 = alloca i1, i1 0
-  %nop13404 = alloca i1, i1 0
-  %nop13405 = alloca i1, i1 0
-  %nop13406 = alloca i1, i1 0
-  %nop13407 = alloca i1, i1 0
-  %nop13408 = alloca i1, i1 0
-  %nop13409 = alloca i1, i1 0
-  %nop13410 = alloca i1, i1 0
-  %nop13411 = alloca i1, i1 0
-  %nop13412 = alloca i1, i1 0
-  %nop13413 = alloca i1, i1 0
-  %nop13414 = alloca i1, i1 0
-  %nop13415 = alloca i1, i1 0
-  %nop13416 = alloca i1, i1 0
-  %nop13417 = alloca i1, i1 0
-  %nop13418 = alloca i1, i1 0
-  %nop13419 = alloca i1, i1 0
-  %nop13420 = alloca i1, i1 0
-  %nop13421 = alloca i1, i1 0
-  %nop13422 = alloca i1, i1 0
-  %nop13423 = alloca i1, i1 0
-  %nop13424 = alloca i1, i1 0
-  %nop13425 = alloca i1, i1 0
-  %nop13426 = alloca i1, i1 0
-  %nop13427 = alloca i1, i1 0
-  %nop13428 = alloca i1, i1 0
-  %nop13429 = alloca i1, i1 0
-  %nop13430 = alloca i1, i1 0
-  %nop13431 = alloca i1, i1 0
-  %nop13432 = alloca i1, i1 0
-  %nop13433 = alloca i1, i1 0
-  %nop13434 = alloca i1, i1 0
-  %nop13435 = alloca i1, i1 0
-  %nop13436 = alloca i1, i1 0
-  %nop13437 = alloca i1, i1 0
-  %nop13438 = alloca i1, i1 0
-  %nop13439 = alloca i1, i1 0
-  %nop13440 = alloca i1, i1 0
-  %nop13441 = alloca i1, i1 0
-  %nop13442 = alloca i1, i1 0
-  %nop13443 = alloca i1, i1 0
-  %nop13444 = alloca i1, i1 0
-  %nop13445 = alloca i1, i1 0
-  %nop13446 = alloca i1, i1 0
-  %nop13447 = alloca i1, i1 0
-  %nop13448 = alloca i1, i1 0
-  %nop13449 = alloca i1, i1 0
-  %nop13450 = alloca i1, i1 0
-  %nop13451 = alloca i1, i1 0
-  %nop13452 = alloca i1, i1 0
-  %nop13453 = alloca i1, i1 0
-  %nop13454 = alloca i1, i1 0
-  %nop13455 = alloca i1, i1 0
-  %nop13456 = alloca i1, i1 0
-  %nop13457 = alloca i1, i1 0
-  %nop13458 = alloca i1, i1 0
-  %nop13459 = alloca i1, i1 0
-  %nop13460 = alloca i1, i1 0
-  %nop13461 = alloca i1, i1 0
-  %nop13462 = alloca i1, i1 0
-  %nop13463 = alloca i1, i1 0
-  %nop13464 = alloca i1, i1 0
-  %nop13465 = alloca i1, i1 0
-  %nop13466 = alloca i1, i1 0
-  %nop13467 = alloca i1, i1 0
-  %nop13468 = alloca i1, i1 0
-  %nop13469 = alloca i1, i1 0
-  %nop13470 = alloca i1, i1 0
-  %nop13471 = alloca i1, i1 0
-  %nop13472 = alloca i1, i1 0
-  %nop13473 = alloca i1, i1 0
-  %nop13474 = alloca i1, i1 0
-  %nop13475 = alloca i1, i1 0
-  %nop13476 = alloca i1, i1 0
-  %nop13477 = alloca i1, i1 0
-  %nop13478 = alloca i1, i1 0
-  %nop13479 = alloca i1, i1 0
-  %nop13480 = alloca i1, i1 0
-  %nop13481 = alloca i1, i1 0
-  %nop13482 = alloca i1, i1 0
-  %nop13483 = alloca i1, i1 0
-  %nop13484 = alloca i1, i1 0
-  %nop13485 = alloca i1, i1 0
-  %nop13486 = alloca i1, i1 0
-  %nop13487 = alloca i1, i1 0
-  %nop13488 = alloca i1, i1 0
-  %nop13489 = alloca i1, i1 0
-  %nop13490 = alloca i1, i1 0
-  %nop13491 = alloca i1, i1 0
-  %nop13492 = alloca i1, i1 0
-  %nop13493 = alloca i1, i1 0
-  %nop13494 = alloca i1, i1 0
-  %nop13495 = alloca i1, i1 0
-  %nop13496 = alloca i1, i1 0
-  %nop13497 = alloca i1, i1 0
-  %nop13498 = alloca i1, i1 0
-  %nop13499 = alloca i1, i1 0
-  %nop13500 = alloca i1, i1 0
-  %nop13501 = alloca i1, i1 0
-  %nop13502 = alloca i1, i1 0
-  %nop13503 = alloca i1, i1 0
-  %nop13504 = alloca i1, i1 0
-  %nop13505 = alloca i1, i1 0
-  %nop13506 = alloca i1, i1 0
-  %nop13507 = alloca i1, i1 0
-  %nop13508 = alloca i1, i1 0
-  %nop13509 = alloca i1, i1 0
-  %nop13510 = alloca i1, i1 0
-  %nop13511 = alloca i1, i1 0
-  %nop13512 = alloca i1, i1 0
-  %nop13513 = alloca i1, i1 0
-  %nop13514 = alloca i1, i1 0
-  %nop13515 = alloca i1, i1 0
-  %nop13516 = alloca i1, i1 0
-  %nop13517 = alloca i1, i1 0
-  %nop13518 = alloca i1, i1 0
-  %nop13519 = alloca i1, i1 0
-  %nop13520 = alloca i1, i1 0
-  %nop13521 = alloca i1, i1 0
-  %nop13522 = alloca i1, i1 0
-  %nop13523 = alloca i1, i1 0
-  %nop13524 = alloca i1, i1 0
-  %nop13525 = alloca i1, i1 0
-  %nop13526 = alloca i1, i1 0
-  %nop13527 = alloca i1, i1 0
-  %nop13528 = alloca i1, i1 0
-  %nop13529 = alloca i1, i1 0
-  %nop13530 = alloca i1, i1 0
-  %nop13531 = alloca i1, i1 0
-  %nop13532 = alloca i1, i1 0
-  %nop13533 = alloca i1, i1 0
-  %nop13534 = alloca i1, i1 0
-  %nop13535 = alloca i1, i1 0
-  %nop13536 = alloca i1, i1 0
-  %nop13537 = alloca i1, i1 0
-  %nop13538 = alloca i1, i1 0
-  %nop13539 = alloca i1, i1 0
-  %nop13540 = alloca i1, i1 0
-  %nop13541 = alloca i1, i1 0
-  %nop13542 = alloca i1, i1 0
-  %nop13543 = alloca i1, i1 0
-  %nop13544 = alloca i1, i1 0
-  %nop13545 = alloca i1, i1 0
-  %nop13546 = alloca i1, i1 0
-  %nop13547 = alloca i1, i1 0
-  %nop13548 = alloca i1, i1 0
-  %nop13549 = alloca i1, i1 0
-  %nop13550 = alloca i1, i1 0
-  %nop13551 = alloca i1, i1 0
-  %nop13552 = alloca i1, i1 0
-  %nop13553 = alloca i1, i1 0
-  %nop13554 = alloca i1, i1 0
-  %nop13555 = alloca i1, i1 0
-  %nop13556 = alloca i1, i1 0
-  %nop13557 = alloca i1, i1 0
-  %nop13558 = alloca i1, i1 0
-  %nop13559 = alloca i1, i1 0
-  %nop13560 = alloca i1, i1 0
-  %nop13561 = alloca i1, i1 0
-  %nop13562 = alloca i1, i1 0
-  %nop13563 = alloca i1, i1 0
-  %nop13564 = alloca i1, i1 0
-  %nop13565 = alloca i1, i1 0
-  %nop13566 = alloca i1, i1 0
-  %nop13567 = alloca i1, i1 0
-  %nop13568 = alloca i1, i1 0
-  %nop13569 = alloca i1, i1 0
-  %nop13570 = alloca i1, i1 0
-  %nop13571 = alloca i1, i1 0
-  %nop13572 = alloca i1, i1 0
-  %nop13573 = alloca i1, i1 0
-  %nop13574 = alloca i1, i1 0
-  %nop13575 = alloca i1, i1 0
-  %nop13576 = alloca i1, i1 0
-  %nop13577 = alloca i1, i1 0
-  %nop13578 = alloca i1, i1 0
-  %nop13579 = alloca i1, i1 0
-  %nop13580 = alloca i1, i1 0
-  %nop13581 = alloca i1, i1 0
-  %nop13582 = alloca i1, i1 0
-  %nop13583 = alloca i1, i1 0
-  %nop13584 = alloca i1, i1 0
-  %nop13585 = alloca i1, i1 0
-  %nop13586 = alloca i1, i1 0
-  %nop13587 = alloca i1, i1 0
-  %nop13588 = alloca i1, i1 0
-  %nop13589 = alloca i1, i1 0
-  %nop13590 = alloca i1, i1 0
-  %nop13591 = alloca i1, i1 0
-  %nop13592 = alloca i1, i1 0
-  %nop13593 = alloca i1, i1 0
-  %nop13594 = alloca i1, i1 0
-  %nop13595 = alloca i1, i1 0
-  %nop13596 = alloca i1, i1 0
-  %nop13597 = alloca i1, i1 0
-  %nop13598 = alloca i1, i1 0
-  %nop13599 = alloca i1, i1 0
-  %nop13600 = alloca i1, i1 0
-  %nop13601 = alloca i1, i1 0
-  %nop13602 = alloca i1, i1 0
-  %nop13603 = alloca i1, i1 0
-  %nop13604 = alloca i1, i1 0
-  %nop13605 = alloca i1, i1 0
-  %nop13606 = alloca i1, i1 0
-  %nop13607 = alloca i1, i1 0
-  %nop13608 = alloca i1, i1 0
-  %nop13609 = alloca i1, i1 0
-  %nop13610 = alloca i1, i1 0
-  %nop13611 = alloca i1, i1 0
-  %nop13612 = alloca i1, i1 0
-  %nop13613 = alloca i1, i1 0
-  %nop13614 = alloca i1, i1 0
-  %nop13615 = alloca i1, i1 0
-  %nop13616 = alloca i1, i1 0
-  %nop13617 = alloca i1, i1 0
-  %nop13618 = alloca i1, i1 0
-  %nop13619 = alloca i1, i1 0
-  %nop13620 = alloca i1, i1 0
-  %nop13621 = alloca i1, i1 0
-  %nop13622 = alloca i1, i1 0
-  %nop13623 = alloca i1, i1 0
-  %nop13624 = alloca i1, i1 0
-  %nop13625 = alloca i1, i1 0
-  %nop13626 = alloca i1, i1 0
-  %nop13627 = alloca i1, i1 0
-  %nop13628 = alloca i1, i1 0
-  %nop13629 = alloca i1, i1 0
-  %nop13630 = alloca i1, i1 0
-  %nop13631 = alloca i1, i1 0
-  %nop13632 = alloca i1, i1 0
-  %nop13633 = alloca i1, i1 0
-  %nop13634 = alloca i1, i1 0
-  %nop13635 = alloca i1, i1 0
-  %nop13636 = alloca i1, i1 0
-  %nop13637 = alloca i1, i1 0
-  %nop13638 = alloca i1, i1 0
-  %nop13639 = alloca i1, i1 0
-  %nop13640 = alloca i1, i1 0
-  %nop13641 = alloca i1, i1 0
-  %nop13642 = alloca i1, i1 0
-  %nop13643 = alloca i1, i1 0
-  %nop13644 = alloca i1, i1 0
-  %nop13645 = alloca i1, i1 0
-  %nop13646 = alloca i1, i1 0
-  %nop13647 = alloca i1, i1 0
-  %nop13648 = alloca i1, i1 0
-  %nop13649 = alloca i1, i1 0
-  %nop13650 = alloca i1, i1 0
-  %nop13651 = alloca i1, i1 0
-  %nop13652 = alloca i1, i1 0
-  %nop13653 = alloca i1, i1 0
-  %nop13654 = alloca i1, i1 0
-  %nop13655 = alloca i1, i1 0
-  %nop13656 = alloca i1, i1 0
-  %nop13657 = alloca i1, i1 0
-  %nop13658 = alloca i1, i1 0
-  %nop13659 = alloca i1, i1 0
-  %nop13660 = alloca i1, i1 0
-  %nop13661 = alloca i1, i1 0
-  %nop13662 = alloca i1, i1 0
-  %nop13663 = alloca i1, i1 0
-  %nop13664 = alloca i1, i1 0
-  %nop13665 = alloca i1, i1 0
-  %nop13666 = alloca i1, i1 0
-  %nop13667 = alloca i1, i1 0
-  %nop13668 = alloca i1, i1 0
-  %nop13669 = alloca i1, i1 0
-  %nop13670 = alloca i1, i1 0
-  %nop13671 = alloca i1, i1 0
-  %nop13672 = alloca i1, i1 0
-  %nop13673 = alloca i1, i1 0
-  %nop13674 = alloca i1, i1 0
-  %nop13675 = alloca i1, i1 0
-  %nop13676 = alloca i1, i1 0
-  %nop13677 = alloca i1, i1 0
-  %nop13678 = alloca i1, i1 0
-  %nop13679 = alloca i1, i1 0
-  %nop13680 = alloca i1, i1 0
-  %nop13681 = alloca i1, i1 0
-  %nop13682 = alloca i1, i1 0
-  %nop13683 = alloca i1, i1 0
-  %nop13684 = alloca i1, i1 0
-  %nop13685 = alloca i1, i1 0
-  %nop13686 = alloca i1, i1 0
-  %nop13687 = alloca i1, i1 0
-  %nop13688 = alloca i1, i1 0
-  %nop13689 = alloca i1, i1 0
-  %nop13690 = alloca i1, i1 0
-  %nop13691 = alloca i1, i1 0
-  %nop13692 = alloca i1, i1 0
-  %nop13693 = alloca i1, i1 0
-  %nop13694 = alloca i1, i1 0
-  %nop13695 = alloca i1, i1 0
-  %nop13696 = alloca i1, i1 0
-  %nop13697 = alloca i1, i1 0
-  %nop13698 = alloca i1, i1 0
-  %nop13699 = alloca i1, i1 0
-  %nop13700 = alloca i1, i1 0
-  %nop13701 = alloca i1, i1 0
-  %nop13702 = alloca i1, i1 0
-  %nop13703 = alloca i1, i1 0
-  %nop13704 = alloca i1, i1 0
-  %nop13705 = alloca i1, i1 0
-  %nop13706 = alloca i1, i1 0
-  %nop13707 = alloca i1, i1 0
-  %nop13708 = alloca i1, i1 0
-  %nop13709 = alloca i1, i1 0
-  %nop13710 = alloca i1, i1 0
-  %nop13711 = alloca i1, i1 0
-  %nop13712 = alloca i1, i1 0
-  %nop13713 = alloca i1, i1 0
-  %nop13714 = alloca i1, i1 0
-  %nop13715 = alloca i1, i1 0
-  %nop13716 = alloca i1, i1 0
-  %nop13717 = alloca i1, i1 0
-  %nop13718 = alloca i1, i1 0
-  %nop13719 = alloca i1, i1 0
-  %nop13720 = alloca i1, i1 0
-  %nop13721 = alloca i1, i1 0
-  %nop13722 = alloca i1, i1 0
-  %nop13723 = alloca i1, i1 0
-  %nop13724 = alloca i1, i1 0
-  %nop13725 = alloca i1, i1 0
-  %nop13726 = alloca i1, i1 0
-  %nop13727 = alloca i1, i1 0
-  %nop13728 = alloca i1, i1 0
-  %nop13729 = alloca i1, i1 0
-  %nop13730 = alloca i1, i1 0
-  %nop13731 = alloca i1, i1 0
-  %nop13732 = alloca i1, i1 0
-  %nop13733 = alloca i1, i1 0
-  %nop13734 = alloca i1, i1 0
-  %nop13735 = alloca i1, i1 0
-  %nop13736 = alloca i1, i1 0
-  %nop13737 = alloca i1, i1 0
-  %nop13738 = alloca i1, i1 0
-  %nop13739 = alloca i1, i1 0
-  %nop13740 = alloca i1, i1 0
-  %nop13741 = alloca i1, i1 0
-  %nop13742 = alloca i1, i1 0
-  %nop13743 = alloca i1, i1 0
-  %nop13744 = alloca i1, i1 0
-  %nop13745 = alloca i1, i1 0
-  %nop13746 = alloca i1, i1 0
-  %nop13747 = alloca i1, i1 0
-  %nop13748 = alloca i1, i1 0
-  %nop13749 = alloca i1, i1 0
-  %nop13750 = alloca i1, i1 0
-  %nop13751 = alloca i1, i1 0
-  %nop13752 = alloca i1, i1 0
-  %nop13753 = alloca i1, i1 0
-  %nop13754 = alloca i1, i1 0
-  %nop13755 = alloca i1, i1 0
-  %nop13756 = alloca i1, i1 0
-  %nop13757 = alloca i1, i1 0
-  %nop13758 = alloca i1, i1 0
-  %nop13759 = alloca i1, i1 0
-  %nop13760 = alloca i1, i1 0
-  %nop13761 = alloca i1, i1 0
-  %nop13762 = alloca i1, i1 0
-  %nop13763 = alloca i1, i1 0
-  %nop13764 = alloca i1, i1 0
-  %nop13765 = alloca i1, i1 0
-  %nop13766 = alloca i1, i1 0
-  %nop13767 = alloca i1, i1 0
-  %nop13768 = alloca i1, i1 0
-  %nop13769 = alloca i1, i1 0
-  %nop13770 = alloca i1, i1 0
-  %nop13771 = alloca i1, i1 0
-  %nop13772 = alloca i1, i1 0
-  %nop13773 = alloca i1, i1 0
-  %nop13774 = alloca i1, i1 0
-  %nop13775 = alloca i1, i1 0
-  %nop13776 = alloca i1, i1 0
-  %nop13777 = alloca i1, i1 0
-  %nop13778 = alloca i1, i1 0
-  %nop13779 = alloca i1, i1 0
-  %nop13780 = alloca i1, i1 0
-  %nop13781 = alloca i1, i1 0
-  %nop13782 = alloca i1, i1 0
-  %nop13783 = alloca i1, i1 0
-  %nop13784 = alloca i1, i1 0
-  %nop13785 = alloca i1, i1 0
-  %nop13786 = alloca i1, i1 0
-  %nop13787 = alloca i1, i1 0
-  %nop13788 = alloca i1, i1 0
-  %nop13789 = alloca i1, i1 0
-  %nop13790 = alloca i1, i1 0
-  %nop13791 = alloca i1, i1 0
-  %nop13792 = alloca i1, i1 0
-  %nop13793 = alloca i1, i1 0
-  %nop13794 = alloca i1, i1 0
-  %nop13795 = alloca i1, i1 0
-  %nop13796 = alloca i1, i1 0
-  %nop13797 = alloca i1, i1 0
-  %nop13798 = alloca i1, i1 0
-  %nop13799 = alloca i1, i1 0
-  %nop13800 = alloca i1, i1 0
-  %nop13801 = alloca i1, i1 0
-  %nop13802 = alloca i1, i1 0
-  %nop13803 = alloca i1, i1 0
-  %nop13804 = alloca i1, i1 0
-  %nop13805 = alloca i1, i1 0
-  %nop13806 = alloca i1, i1 0
-  %nop13807 = alloca i1, i1 0
-  %nop13808 = alloca i1, i1 0
-  %nop13809 = alloca i1, i1 0
-  %nop13810 = alloca i1, i1 0
-  %nop13811 = alloca i1, i1 0
-  %nop13812 = alloca i1, i1 0
-  %nop13813 = alloca i1, i1 0
-  %nop13814 = alloca i1, i1 0
-  %nop13815 = alloca i1, i1 0
-  %nop13816 = alloca i1, i1 0
-  %nop13817 = alloca i1, i1 0
-  %nop13818 = alloca i1, i1 0
-  %nop13819 = alloca i1, i1 0
-  %nop13820 = alloca i1, i1 0
-  %nop13821 = alloca i1, i1 0
-  %nop13822 = alloca i1, i1 0
-  %nop13823 = alloca i1, i1 0
-  %nop13824 = alloca i1, i1 0
-  %nop13825 = alloca i1, i1 0
-  %nop13826 = alloca i1, i1 0
-  %nop13827 = alloca i1, i1 0
-  %nop13828 = alloca i1, i1 0
-  %nop13829 = alloca i1, i1 0
-  %nop13830 = alloca i1, i1 0
-  %nop13831 = alloca i1, i1 0
-  %nop13832 = alloca i1, i1 0
-  %nop13833 = alloca i1, i1 0
-  %nop13834 = alloca i1, i1 0
-  %nop13835 = alloca i1, i1 0
-  %nop13836 = alloca i1, i1 0
-  %nop13837 = alloca i1, i1 0
-  %nop13838 = alloca i1, i1 0
-  %nop13839 = alloca i1, i1 0
-  %nop13840 = alloca i1, i1 0
-  %nop13841 = alloca i1, i1 0
-  %nop13842 = alloca i1, i1 0
-  %nop13843 = alloca i1, i1 0
-  %nop13844 = alloca i1, i1 0
-  %nop13845 = alloca i1, i1 0
-  %nop13846 = alloca i1, i1 0
-  %nop13847 = alloca i1, i1 0
-  %nop13848 = alloca i1, i1 0
-  %nop13849 = alloca i1, i1 0
-  %nop13850 = alloca i1, i1 0
-  %nop13851 = alloca i1, i1 0
-  %nop13852 = alloca i1, i1 0
-  %nop13853 = alloca i1, i1 0
-  %nop13854 = alloca i1, i1 0
-  %nop13855 = alloca i1, i1 0
-  %nop13856 = alloca i1, i1 0
-  %nop13857 = alloca i1, i1 0
-  %nop13858 = alloca i1, i1 0
-  %nop13859 = alloca i1, i1 0
-  %nop13860 = alloca i1, i1 0
-  %nop13861 = alloca i1, i1 0
-  %nop13862 = alloca i1, i1 0
-  %nop13863 = alloca i1, i1 0
-  %nop13864 = alloca i1, i1 0
-  %nop13865 = alloca i1, i1 0
-  %nop13866 = alloca i1, i1 0
-  %nop13867 = alloca i1, i1 0
-  %nop13868 = alloca i1, i1 0
-  %nop13869 = alloca i1, i1 0
-  %nop13870 = alloca i1, i1 0
-  %nop13871 = alloca i1, i1 0
-  %nop13872 = alloca i1, i1 0
-  %nop13873 = alloca i1, i1 0
-  %nop13874 = alloca i1, i1 0
-  %nop13875 = alloca i1, i1 0
-  %nop13876 = alloca i1, i1 0
-  %nop13877 = alloca i1, i1 0
-  %nop13878 = alloca i1, i1 0
-  %nop13879 = alloca i1, i1 0
-  %nop13880 = alloca i1, i1 0
-  %nop13881 = alloca i1, i1 0
-  %nop13882 = alloca i1, i1 0
-  %nop13883 = alloca i1, i1 0
-  %nop13884 = alloca i1, i1 0
-  %nop13885 = alloca i1, i1 0
-  %nop13886 = alloca i1, i1 0
-  %nop13887 = alloca i1, i1 0
-  %nop13888 = alloca i1, i1 0
-  %nop13889 = alloca i1, i1 0
-  %nop13890 = alloca i1, i1 0
-  %nop13891 = alloca i1, i1 0
-  %nop13892 = alloca i1, i1 0
-  %nop13893 = alloca i1, i1 0
-  %nop13894 = alloca i1, i1 0
-  %nop13895 = alloca i1, i1 0
-  %nop13896 = alloca i1, i1 0
-  %nop13897 = alloca i1, i1 0
-  %nop13898 = alloca i1, i1 0
-  %nop13899 = alloca i1, i1 0
-  %nop13900 = alloca i1, i1 0
-  %nop13901 = alloca i1, i1 0
-  %nop13902 = alloca i1, i1 0
-  %nop13903 = alloca i1, i1 0
-  %nop13904 = alloca i1, i1 0
-  %nop13905 = alloca i1, i1 0
-  %nop13906 = alloca i1, i1 0
-  %nop13907 = alloca i1, i1 0
-  %nop13908 = alloca i1, i1 0
-  %nop13909 = alloca i1, i1 0
-  %nop13910 = alloca i1, i1 0
-  %nop13911 = alloca i1, i1 0
-  %nop13912 = alloca i1, i1 0
-  %nop13913 = alloca i1, i1 0
-  %nop13914 = alloca i1, i1 0
-  %nop13915 = alloca i1, i1 0
-  %nop13916 = alloca i1, i1 0
-  %nop13917 = alloca i1, i1 0
-  %nop13918 = alloca i1, i1 0
-  %nop13919 = alloca i1, i1 0
-  %nop13920 = alloca i1, i1 0
-  %nop13921 = alloca i1, i1 0
-  %nop13922 = alloca i1, i1 0
-  %nop13923 = alloca i1, i1 0
-  %nop13924 = alloca i1, i1 0
-  %nop13925 = alloca i1, i1 0
-  %nop13926 = alloca i1, i1 0
-  %nop13927 = alloca i1, i1 0
-  %nop13928 = alloca i1, i1 0
-  %nop13929 = alloca i1, i1 0
-  %nop13930 = alloca i1, i1 0
-  %nop13931 = alloca i1, i1 0
-  %nop13932 = alloca i1, i1 0
-  %nop13933 = alloca i1, i1 0
-  %nop13934 = alloca i1, i1 0
-  %nop13935 = alloca i1, i1 0
-  %nop13936 = alloca i1, i1 0
-  %nop13937 = alloca i1, i1 0
-  %nop13938 = alloca i1, i1 0
-  %nop13939 = alloca i1, i1 0
-  %nop13940 = alloca i1, i1 0
-  %nop13941 = alloca i1, i1 0
-  %nop13942 = alloca i1, i1 0
-  %nop13943 = alloca i1, i1 0
-  %nop13944 = alloca i1, i1 0
-  %nop13945 = alloca i1, i1 0
-  %nop13946 = alloca i1, i1 0
-  %nop13947 = alloca i1, i1 0
-  %nop13948 = alloca i1, i1 0
-  %nop13949 = alloca i1, i1 0
-  %nop13950 = alloca i1, i1 0
-  %nop13951 = alloca i1, i1 0
-  %nop13952 = alloca i1, i1 0
-  %nop13953 = alloca i1, i1 0
-  %nop13954 = alloca i1, i1 0
-  %nop13955 = alloca i1, i1 0
-  %nop13956 = alloca i1, i1 0
-  %nop13957 = alloca i1, i1 0
-  %nop13958 = alloca i1, i1 0
-  %nop13959 = alloca i1, i1 0
-  %nop13960 = alloca i1, i1 0
-  %nop13961 = alloca i1, i1 0
-  %nop13962 = alloca i1, i1 0
-  %nop13963 = alloca i1, i1 0
-  %nop13964 = alloca i1, i1 0
-  %nop13965 = alloca i1, i1 0
-  %nop13966 = alloca i1, i1 0
-  %nop13967 = alloca i1, i1 0
-  %nop13968 = alloca i1, i1 0
-  %nop13969 = alloca i1, i1 0
-  %nop13970 = alloca i1, i1 0
-  %nop13971 = alloca i1, i1 0
-  %nop13972 = alloca i1, i1 0
-  %nop13973 = alloca i1, i1 0
-  %nop13974 = alloca i1, i1 0
-  %nop13975 = alloca i1, i1 0
-  %nop13976 = alloca i1, i1 0
-  %nop13977 = alloca i1, i1 0
-  %nop13978 = alloca i1, i1 0
-  %nop13979 = alloca i1, i1 0
-  %nop13980 = alloca i1, i1 0
-  %nop13981 = alloca i1, i1 0
-  %nop13982 = alloca i1, i1 0
-  %nop13983 = alloca i1, i1 0
-  %nop13984 = alloca i1, i1 0
-  %nop13985 = alloca i1, i1 0
-  %nop13986 = alloca i1, i1 0
-  %nop13987 = alloca i1, i1 0
-  %nop13988 = alloca i1, i1 0
-  %nop13989 = alloca i1, i1 0
-  %nop13990 = alloca i1, i1 0
-  %nop13991 = alloca i1, i1 0
-  %nop13992 = alloca i1, i1 0
-  %nop13993 = alloca i1, i1 0
-  %nop13994 = alloca i1, i1 0
-  %nop13995 = alloca i1, i1 0
-  %nop13996 = alloca i1, i1 0
-  %nop13997 = alloca i1, i1 0
-  %nop13998 = alloca i1, i1 0
-  %nop13999 = alloca i1, i1 0
-  %nop14000 = alloca i1, i1 0
-  %nop14001 = alloca i1, i1 0
-  %nop14002 = alloca i1, i1 0
-  %nop14003 = alloca i1, i1 0
-  %nop14004 = alloca i1, i1 0
-  %nop14005 = alloca i1, i1 0
-  %nop14006 = alloca i1, i1 0
-  %nop14007 = alloca i1, i1 0
-  %nop14008 = alloca i1, i1 0
-  %nop14009 = alloca i1, i1 0
-  %nop14010 = alloca i1, i1 0
-  %nop14011 = alloca i1, i1 0
-  %nop14012 = alloca i1, i1 0
-  %nop14013 = alloca i1, i1 0
-  %nop14014 = alloca i1, i1 0
-  %nop14015 = alloca i1, i1 0
-  %nop14016 = alloca i1, i1 0
-  %nop14017 = alloca i1, i1 0
-  %nop14018 = alloca i1, i1 0
-  %nop14019 = alloca i1, i1 0
-  %nop14020 = alloca i1, i1 0
-  %nop14021 = alloca i1, i1 0
-  %nop14022 = alloca i1, i1 0
-  %nop14023 = alloca i1, i1 0
-  %nop14024 = alloca i1, i1 0
-  %nop14025 = alloca i1, i1 0
-  %nop14026 = alloca i1, i1 0
-  %nop14027 = alloca i1, i1 0
-  %nop14028 = alloca i1, i1 0
-  %nop14029 = alloca i1, i1 0
-  %nop14030 = alloca i1, i1 0
-  %nop14031 = alloca i1, i1 0
-  %nop14032 = alloca i1, i1 0
-  %nop14033 = alloca i1, i1 0
-  %nop14034 = alloca i1, i1 0
-  %nop14035 = alloca i1, i1 0
-  %nop14036 = alloca i1, i1 0
-  %nop14037 = alloca i1, i1 0
-  %nop14038 = alloca i1, i1 0
-  %nop14039 = alloca i1, i1 0
-  %nop14040 = alloca i1, i1 0
-  %nop14041 = alloca i1, i1 0
-  %nop14042 = alloca i1, i1 0
-  %nop14043 = alloca i1, i1 0
-  %nop14044 = alloca i1, i1 0
-  %nop14045 = alloca i1, i1 0
-  %nop14046 = alloca i1, i1 0
-  %nop14047 = alloca i1, i1 0
-  %nop14048 = alloca i1, i1 0
-  %nop14049 = alloca i1, i1 0
-  %nop14050 = alloca i1, i1 0
-  %nop14051 = alloca i1, i1 0
-  %nop14052 = alloca i1, i1 0
-  %nop14053 = alloca i1, i1 0
-  %nop14054 = alloca i1, i1 0
-  %nop14055 = alloca i1, i1 0
-  %nop14056 = alloca i1, i1 0
-  %nop14057 = alloca i1, i1 0
-  %nop14058 = alloca i1, i1 0
-  %nop14059 = alloca i1, i1 0
-  %nop14060 = alloca i1, i1 0
-  %nop14061 = alloca i1, i1 0
-  %nop14062 = alloca i1, i1 0
-  %nop14063 = alloca i1, i1 0
-  %nop14064 = alloca i1, i1 0
-  %nop14065 = alloca i1, i1 0
-  %nop14066 = alloca i1, i1 0
-  %nop14067 = alloca i1, i1 0
-  %nop14068 = alloca i1, i1 0
-  %nop14069 = alloca i1, i1 0
-  %nop14070 = alloca i1, i1 0
-  %nop14071 = alloca i1, i1 0
-  %nop14072 = alloca i1, i1 0
-  %nop14073 = alloca i1, i1 0
-  %nop14074 = alloca i1, i1 0
-  %nop14075 = alloca i1, i1 0
-  %nop14076 = alloca i1, i1 0
-  %nop14077 = alloca i1, i1 0
-  %nop14078 = alloca i1, i1 0
-  %nop14079 = alloca i1, i1 0
-  %nop14080 = alloca i1, i1 0
-  %nop14081 = alloca i1, i1 0
-  %nop14082 = alloca i1, i1 0
-  %nop14083 = alloca i1, i1 0
-  %nop14084 = alloca i1, i1 0
-  %nop14085 = alloca i1, i1 0
-  %nop14086 = alloca i1, i1 0
-  %nop14087 = alloca i1, i1 0
-  %nop14088 = alloca i1, i1 0
-  %nop14089 = alloca i1, i1 0
-  %nop14090 = alloca i1, i1 0
-  %nop14091 = alloca i1, i1 0
-  %nop14092 = alloca i1, i1 0
-  %nop14093 = alloca i1, i1 0
-  %nop14094 = alloca i1, i1 0
-  %nop14095 = alloca i1, i1 0
-  %nop14096 = alloca i1, i1 0
-  %nop14097 = alloca i1, i1 0
-  %nop14098 = alloca i1, i1 0
-  %nop14099 = alloca i1, i1 0
-  %nop14100 = alloca i1, i1 0
-  %nop14101 = alloca i1, i1 0
-  %nop14102 = alloca i1, i1 0
-  %nop14103 = alloca i1, i1 0
-  %nop14104 = alloca i1, i1 0
-  %nop14105 = alloca i1, i1 0
-  %nop14106 = alloca i1, i1 0
-  %nop14107 = alloca i1, i1 0
-  %nop14108 = alloca i1, i1 0
-  %nop14109 = alloca i1, i1 0
-  %nop14110 = alloca i1, i1 0
-  %nop14111 = alloca i1, i1 0
-  %nop14112 = alloca i1, i1 0
-  %nop14113 = alloca i1, i1 0
-  %nop14114 = alloca i1, i1 0
-  %nop14115 = alloca i1, i1 0
-  %nop14116 = alloca i1, i1 0
-  %nop14117 = alloca i1, i1 0
-  %nop14118 = alloca i1, i1 0
-  %nop14119 = alloca i1, i1 0
-  %nop14120 = alloca i1, i1 0
-  %nop14121 = alloca i1, i1 0
-  %nop14122 = alloca i1, i1 0
-  %nop14123 = alloca i1, i1 0
-  %nop14124 = alloca i1, i1 0
-  %nop14125 = alloca i1, i1 0
-  %nop14126 = alloca i1, i1 0
-  %nop14127 = alloca i1, i1 0
-  %nop14128 = alloca i1, i1 0
-  %nop14129 = alloca i1, i1 0
-  %nop14130 = alloca i1, i1 0
-  %nop14131 = alloca i1, i1 0
-  %nop14132 = alloca i1, i1 0
-  %nop14133 = alloca i1, i1 0
-  %nop14134 = alloca i1, i1 0
-  %nop14135 = alloca i1, i1 0
-  %nop14136 = alloca i1, i1 0
-  %nop14137 = alloca i1, i1 0
-  %nop14138 = alloca i1, i1 0
-  %nop14139 = alloca i1, i1 0
-  %nop14140 = alloca i1, i1 0
-  %nop14141 = alloca i1, i1 0
-  %nop14142 = alloca i1, i1 0
-  %nop14143 = alloca i1, i1 0
-  %nop14144 = alloca i1, i1 0
-  %nop14145 = alloca i1, i1 0
-  %nop14146 = alloca i1, i1 0
-  %nop14147 = alloca i1, i1 0
-  %nop14148 = alloca i1, i1 0
-  %nop14149 = alloca i1, i1 0
-  %nop14150 = alloca i1, i1 0
-  %nop14151 = alloca i1, i1 0
-  %nop14152 = alloca i1, i1 0
-  %nop14153 = alloca i1, i1 0
-  %nop14154 = alloca i1, i1 0
-  %nop14155 = alloca i1, i1 0
-  %nop14156 = alloca i1, i1 0
-  %nop14157 = alloca i1, i1 0
-  %nop14158 = alloca i1, i1 0
-  %nop14159 = alloca i1, i1 0
-  %nop14160 = alloca i1, i1 0
-  %nop14161 = alloca i1, i1 0
-  %nop14162 = alloca i1, i1 0
-  %nop14163 = alloca i1, i1 0
-  %nop14164 = alloca i1, i1 0
-  %nop14165 = alloca i1, i1 0
-  %nop14166 = alloca i1, i1 0
-  %nop14167 = alloca i1, i1 0
-  %nop14168 = alloca i1, i1 0
-  %nop14169 = alloca i1, i1 0
-  %nop14170 = alloca i1, i1 0
-  %nop14171 = alloca i1, i1 0
-  %nop14172 = alloca i1, i1 0
-  %nop14173 = alloca i1, i1 0
-  %nop14174 = alloca i1, i1 0
-  %nop14175 = alloca i1, i1 0
-  %nop14176 = alloca i1, i1 0
-  %nop14177 = alloca i1, i1 0
-  %nop14178 = alloca i1, i1 0
-  %nop14179 = alloca i1, i1 0
-  %nop14180 = alloca i1, i1 0
-  %nop14181 = alloca i1, i1 0
-  %nop14182 = alloca i1, i1 0
-  %nop14183 = alloca i1, i1 0
-  %nop14184 = alloca i1, i1 0
-  %nop14185 = alloca i1, i1 0
-  %nop14186 = alloca i1, i1 0
-  %nop14187 = alloca i1, i1 0
-  %nop14188 = alloca i1, i1 0
-  %nop14189 = alloca i1, i1 0
-  %nop14190 = alloca i1, i1 0
-  %nop14191 = alloca i1, i1 0
-  %nop14192 = alloca i1, i1 0
-  %nop14193 = alloca i1, i1 0
-  %nop14194 = alloca i1, i1 0
-  %nop14195 = alloca i1, i1 0
-  %nop14196 = alloca i1, i1 0
-  %nop14197 = alloca i1, i1 0
-  %nop14198 = alloca i1, i1 0
-  %nop14199 = alloca i1, i1 0
-  %nop14200 = alloca i1, i1 0
-  %nop14201 = alloca i1, i1 0
-  %nop14202 = alloca i1, i1 0
-  %nop14203 = alloca i1, i1 0
-  %nop14204 = alloca i1, i1 0
-  %nop14205 = alloca i1, i1 0
-  %nop14206 = alloca i1, i1 0
-  %nop14207 = alloca i1, i1 0
-  %nop14208 = alloca i1, i1 0
-  %nop14209 = alloca i1, i1 0
-  %nop14210 = alloca i1, i1 0
-  %nop14211 = alloca i1, i1 0
-  %nop14212 = alloca i1, i1 0
-  %nop14213 = alloca i1, i1 0
-  %nop14214 = alloca i1, i1 0
-  %nop14215 = alloca i1, i1 0
-  %nop14216 = alloca i1, i1 0
-  %nop14217 = alloca i1, i1 0
-  %nop14218 = alloca i1, i1 0
-  %nop14219 = alloca i1, i1 0
-  %nop14220 = alloca i1, i1 0
-  %nop14221 = alloca i1, i1 0
-  %nop14222 = alloca i1, i1 0
-  %nop14223 = alloca i1, i1 0
-  %nop14224 = alloca i1, i1 0
-  %nop14225 = alloca i1, i1 0
-  %nop14226 = alloca i1, i1 0
-  %nop14227 = alloca i1, i1 0
-  %nop14228 = alloca i1, i1 0
-  %nop14229 = alloca i1, i1 0
-  %nop14230 = alloca i1, i1 0
-  %nop14231 = alloca i1, i1 0
-  %nop14232 = alloca i1, i1 0
-  %nop14233 = alloca i1, i1 0
-  %nop14234 = alloca i1, i1 0
-  %nop14235 = alloca i1, i1 0
-  %nop14236 = alloca i1, i1 0
-  %nop14237 = alloca i1, i1 0
-  %nop14238 = alloca i1, i1 0
-  %nop14239 = alloca i1, i1 0
-  %nop14240 = alloca i1, i1 0
-  %nop14241 = alloca i1, i1 0
-  %nop14242 = alloca i1, i1 0
-  %nop14243 = alloca i1, i1 0
-  %nop14244 = alloca i1, i1 0
-  %nop14245 = alloca i1, i1 0
-  %nop14246 = alloca i1, i1 0
-  %nop14247 = alloca i1, i1 0
-  %nop14248 = alloca i1, i1 0
-  %nop14249 = alloca i1, i1 0
-  %nop14250 = alloca i1, i1 0
-  %nop14251 = alloca i1, i1 0
-  %nop14252 = alloca i1, i1 0
-  %nop14253 = alloca i1, i1 0
-  %nop14254 = alloca i1, i1 0
-  %nop14255 = alloca i1, i1 0
-  %nop14256 = alloca i1, i1 0
-  %nop14257 = alloca i1, i1 0
-  %nop14258 = alloca i1, i1 0
-  %nop14259 = alloca i1, i1 0
-  %nop14260 = alloca i1, i1 0
-  %nop14261 = alloca i1, i1 0
-  %nop14262 = alloca i1, i1 0
-  %nop14263 = alloca i1, i1 0
-  %nop14264 = alloca i1, i1 0
-  %nop14265 = alloca i1, i1 0
-  %nop14266 = alloca i1, i1 0
-  %nop14267 = alloca i1, i1 0
-  %nop14268 = alloca i1, i1 0
-  %nop14269 = alloca i1, i1 0
-  %nop14270 = alloca i1, i1 0
-  %nop14271 = alloca i1, i1 0
-  %nop14272 = alloca i1, i1 0
-  %nop14273 = alloca i1, i1 0
-  %nop14274 = alloca i1, i1 0
-  %nop14275 = alloca i1, i1 0
-  %nop14276 = alloca i1, i1 0
-  %nop14277 = alloca i1, i1 0
-  %nop14278 = alloca i1, i1 0
-  %nop14279 = alloca i1, i1 0
-  %nop14280 = alloca i1, i1 0
-  %nop14281 = alloca i1, i1 0
-  %nop14282 = alloca i1, i1 0
-  %nop14283 = alloca i1, i1 0
-  %nop14284 = alloca i1, i1 0
-  %nop14285 = alloca i1, i1 0
-  %nop14286 = alloca i1, i1 0
-  %nop14287 = alloca i1, i1 0
-  %nop14288 = alloca i1, i1 0
-  %nop14289 = alloca i1, i1 0
-  %nop14290 = alloca i1, i1 0
-  %nop14291 = alloca i1, i1 0
-  %nop14292 = alloca i1, i1 0
-  %nop14293 = alloca i1, i1 0
-  %nop14294 = alloca i1, i1 0
-  %nop14295 = alloca i1, i1 0
-  %nop14296 = alloca i1, i1 0
-  %nop14297 = alloca i1, i1 0
-  %nop14298 = alloca i1, i1 0
-  %nop14299 = alloca i1, i1 0
-  %nop14300 = alloca i1, i1 0
-  %nop14301 = alloca i1, i1 0
-  %nop14302 = alloca i1, i1 0
-  %nop14303 = alloca i1, i1 0
-  %nop14304 = alloca i1, i1 0
-  %nop14305 = alloca i1, i1 0
-  %nop14306 = alloca i1, i1 0
-  %nop14307 = alloca i1, i1 0
-  %nop14308 = alloca i1, i1 0
-  %nop14309 = alloca i1, i1 0
-  %nop14310 = alloca i1, i1 0
-  %nop14311 = alloca i1, i1 0
-  %nop14312 = alloca i1, i1 0
-  %nop14313 = alloca i1, i1 0
-  %nop14314 = alloca i1, i1 0
-  %nop14315 = alloca i1, i1 0
-  %nop14316 = alloca i1, i1 0
-  %nop14317 = alloca i1, i1 0
-  %nop14318 = alloca i1, i1 0
-  %nop14319 = alloca i1, i1 0
-  %nop14320 = alloca i1, i1 0
-  %nop14321 = alloca i1, i1 0
-  %nop14322 = alloca i1, i1 0
-  %nop14323 = alloca i1, i1 0
-  %nop14324 = alloca i1, i1 0
-  %nop14325 = alloca i1, i1 0
-  %nop14326 = alloca i1, i1 0
-  %nop14327 = alloca i1, i1 0
-  %nop14328 = alloca i1, i1 0
-  %nop14329 = alloca i1, i1 0
-  %nop14330 = alloca i1, i1 0
-  %nop14331 = alloca i1, i1 0
-  %nop14332 = alloca i1, i1 0
-  %nop14333 = alloca i1, i1 0
-  %nop14334 = alloca i1, i1 0
-  %nop14335 = alloca i1, i1 0
-  %nop14336 = alloca i1, i1 0
-  %nop14337 = alloca i1, i1 0
-  %nop14338 = alloca i1, i1 0
-  %nop14339 = alloca i1, i1 0
-  %nop14340 = alloca i1, i1 0
-  %nop14341 = alloca i1, i1 0
-  %nop14342 = alloca i1, i1 0
-  %nop14343 = alloca i1, i1 0
-  %nop14344 = alloca i1, i1 0
-  %nop14345 = alloca i1, i1 0
-  %nop14346 = alloca i1, i1 0
-  %nop14347 = alloca i1, i1 0
-  %nop14348 = alloca i1, i1 0
-  %nop14349 = alloca i1, i1 0
-  %nop14350 = alloca i1, i1 0
-  %nop14351 = alloca i1, i1 0
-  %nop14352 = alloca i1, i1 0
-  %nop14353 = alloca i1, i1 0
-  %nop14354 = alloca i1, i1 0
-  %nop14355 = alloca i1, i1 0
-  %nop14356 = alloca i1, i1 0
-  %nop14357 = alloca i1, i1 0
-  %nop14358 = alloca i1, i1 0
-  %nop14359 = alloca i1, i1 0
-  %nop14360 = alloca i1, i1 0
-  %nop14361 = alloca i1, i1 0
-  %nop14362 = alloca i1, i1 0
-  %nop14363 = alloca i1, i1 0
-  %nop14364 = alloca i1, i1 0
-  %nop14365 = alloca i1, i1 0
-  %nop14366 = alloca i1, i1 0
-  %nop14367 = alloca i1, i1 0
-  %nop14368 = alloca i1, i1 0
-  %nop14369 = alloca i1, i1 0
-  %nop14370 = alloca i1, i1 0
-  %nop14371 = alloca i1, i1 0
-  %nop14372 = alloca i1, i1 0
-  %nop14373 = alloca i1, i1 0
-  %nop14374 = alloca i1, i1 0
-  %nop14375 = alloca i1, i1 0
-  %nop14376 = alloca i1, i1 0
-  %nop14377 = alloca i1, i1 0
-  %nop14378 = alloca i1, i1 0
-  %nop14379 = alloca i1, i1 0
-  %nop14380 = alloca i1, i1 0
-  %nop14381 = alloca i1, i1 0
-  %nop14382 = alloca i1, i1 0
-  %nop14383 = alloca i1, i1 0
-  %nop14384 = alloca i1, i1 0
-  %nop14385 = alloca i1, i1 0
-  %nop14386 = alloca i1, i1 0
-  %nop14387 = alloca i1, i1 0
-  %nop14388 = alloca i1, i1 0
-  %nop14389 = alloca i1, i1 0
-  %nop14390 = alloca i1, i1 0
-  %nop14391 = alloca i1, i1 0
-  %nop14392 = alloca i1, i1 0
-  %nop14393 = alloca i1, i1 0
-  %nop14394 = alloca i1, i1 0
-  %nop14395 = alloca i1, i1 0
-  %nop14396 = alloca i1, i1 0
-  %nop14397 = alloca i1, i1 0
-  %nop14398 = alloca i1, i1 0
-  %nop14399 = alloca i1, i1 0
-  %nop14400 = alloca i1, i1 0
-  %nop14401 = alloca i1, i1 0
-  %nop14402 = alloca i1, i1 0
-  %nop14403 = alloca i1, i1 0
-  %nop14404 = alloca i1, i1 0
-  %nop14405 = alloca i1, i1 0
-  %nop14406 = alloca i1, i1 0
-  %nop14407 = alloca i1, i1 0
-  %nop14408 = alloca i1, i1 0
-  %nop14409 = alloca i1, i1 0
-  %nop14410 = alloca i1, i1 0
-  %nop14411 = alloca i1, i1 0
-  %nop14412 = alloca i1, i1 0
-  %nop14413 = alloca i1, i1 0
-  %nop14414 = alloca i1, i1 0
-  %nop14415 = alloca i1, i1 0
-  %nop14416 = alloca i1, i1 0
-  %nop14417 = alloca i1, i1 0
-  %nop14418 = alloca i1, i1 0
-  %nop14419 = alloca i1, i1 0
-  %nop14420 = alloca i1, i1 0
-  %nop14421 = alloca i1, i1 0
-  %nop14422 = alloca i1, i1 0
-  %nop14423 = alloca i1, i1 0
-  %nop14424 = alloca i1, i1 0
-  %nop14425 = alloca i1, i1 0
-  %nop14426 = alloca i1, i1 0
-  %nop14427 = alloca i1, i1 0
-  %nop14428 = alloca i1, i1 0
-  %nop14429 = alloca i1, i1 0
-  %nop14430 = alloca i1, i1 0
-  %nop14431 = alloca i1, i1 0
-  %nop14432 = alloca i1, i1 0
-  %nop14433 = alloca i1, i1 0
-  %nop14434 = alloca i1, i1 0
-  %nop14435 = alloca i1, i1 0
-  %nop14436 = alloca i1, i1 0
-  %nop14437 = alloca i1, i1 0
-  %nop14438 = alloca i1, i1 0
-  %nop14439 = alloca i1, i1 0
-  %nop14440 = alloca i1, i1 0
-  %nop14441 = alloca i1, i1 0
-  %nop14442 = alloca i1, i1 0
-  %nop14443 = alloca i1, i1 0
-  %nop14444 = alloca i1, i1 0
-  %nop14445 = alloca i1, i1 0
-  %nop14446 = alloca i1, i1 0
-  %nop14447 = alloca i1, i1 0
-  %nop14448 = alloca i1, i1 0
-  %nop14449 = alloca i1, i1 0
-  %nop14450 = alloca i1, i1 0
-  %nop14451 = alloca i1, i1 0
-  %nop14452 = alloca i1, i1 0
-  %nop14453 = alloca i1, i1 0
-  %nop14454 = alloca i1, i1 0
-  %nop14455 = alloca i1, i1 0
-  %nop14456 = alloca i1, i1 0
-  %nop14457 = alloca i1, i1 0
-  %nop14458 = alloca i1, i1 0
-  %nop14459 = alloca i1, i1 0
-  %nop14460 = alloca i1, i1 0
-  %nop14461 = alloca i1, i1 0
-  %nop14462 = alloca i1, i1 0
-  %nop14463 = alloca i1, i1 0
-  %nop14464 = alloca i1, i1 0
-  %nop14465 = alloca i1, i1 0
-  %nop14466 = alloca i1, i1 0
-  %nop14467 = alloca i1, i1 0
-  %nop14468 = alloca i1, i1 0
-  %nop14469 = alloca i1, i1 0
-  %nop14470 = alloca i1, i1 0
-  %nop14471 = alloca i1, i1 0
-  %nop14472 = alloca i1, i1 0
-  %nop14473 = alloca i1, i1 0
-  %nop14474 = alloca i1, i1 0
-  %nop14475 = alloca i1, i1 0
-  %nop14476 = alloca i1, i1 0
-  %nop14477 = alloca i1, i1 0
-  %nop14478 = alloca i1, i1 0
-  %nop14479 = alloca i1, i1 0
-  %nop14480 = alloca i1, i1 0
-  %nop14481 = alloca i1, i1 0
-  %nop14482 = alloca i1, i1 0
-  %nop14483 = alloca i1, i1 0
-  %nop14484 = alloca i1, i1 0
-  %nop14485 = alloca i1, i1 0
-  %nop14486 = alloca i1, i1 0
-  %nop14487 = alloca i1, i1 0
-  %nop14488 = alloca i1, i1 0
-  %nop14489 = alloca i1, i1 0
-  %nop14490 = alloca i1, i1 0
-  %nop14491 = alloca i1, i1 0
-  %nop14492 = alloca i1, i1 0
-  %nop14493 = alloca i1, i1 0
-  %nop14494 = alloca i1, i1 0
-  %nop14495 = alloca i1, i1 0
-  %nop14496 = alloca i1, i1 0
-  %nop14497 = alloca i1, i1 0
-  %nop14498 = alloca i1, i1 0
-  %nop14499 = alloca i1, i1 0
-  %nop14500 = alloca i1, i1 0
-  %nop14501 = alloca i1, i1 0
-  %nop14502 = alloca i1, i1 0
-  %nop14503 = alloca i1, i1 0
-  %nop14504 = alloca i1, i1 0
-  %nop14505 = alloca i1, i1 0
-  %nop14506 = alloca i1, i1 0
-  %nop14507 = alloca i1, i1 0
-  %nop14508 = alloca i1, i1 0
-  %nop14509 = alloca i1, i1 0
-  %nop14510 = alloca i1, i1 0
-  %nop14511 = alloca i1, i1 0
-  %nop14512 = alloca i1, i1 0
-  %nop14513 = alloca i1, i1 0
-  %nop14514 = alloca i1, i1 0
-  %nop14515 = alloca i1, i1 0
-  %nop14516 = alloca i1, i1 0
-  %nop14517 = alloca i1, i1 0
-  %nop14518 = alloca i1, i1 0
-  %nop14519 = alloca i1, i1 0
-  %nop14520 = alloca i1, i1 0
-  %nop14521 = alloca i1, i1 0
-  %nop14522 = alloca i1, i1 0
-  %nop14523 = alloca i1, i1 0
-  %nop14524 = alloca i1, i1 0
-  %nop14525 = alloca i1, i1 0
-  %nop14526 = alloca i1, i1 0
-  %nop14527 = alloca i1, i1 0
-  %nop14528 = alloca i1, i1 0
-  %nop14529 = alloca i1, i1 0
-  %nop14530 = alloca i1, i1 0
-  %nop14531 = alloca i1, i1 0
-  %nop14532 = alloca i1, i1 0
-  %nop14533 = alloca i1, i1 0
-  %nop14534 = alloca i1, i1 0
-  %nop14535 = alloca i1, i1 0
-  %nop14536 = alloca i1, i1 0
-  %nop14537 = alloca i1, i1 0
-  %nop14538 = alloca i1, i1 0
-  %nop14539 = alloca i1, i1 0
-  %nop14540 = alloca i1, i1 0
-  %nop14541 = alloca i1, i1 0
-  %nop14542 = alloca i1, i1 0
-  %nop14543 = alloca i1, i1 0
-  %nop14544 = alloca i1, i1 0
-  %nop14545 = alloca i1, i1 0
-  %nop14546 = alloca i1, i1 0
-  %nop14547 = alloca i1, i1 0
-  %nop14548 = alloca i1, i1 0
-  %nop14549 = alloca i1, i1 0
-  %nop14550 = alloca i1, i1 0
-  %nop14551 = alloca i1, i1 0
-  %nop14552 = alloca i1, i1 0
-  %nop14553 = alloca i1, i1 0
-  %nop14554 = alloca i1, i1 0
-  %nop14555 = alloca i1, i1 0
-  %nop14556 = alloca i1, i1 0
-  %nop14557 = alloca i1, i1 0
-  %nop14558 = alloca i1, i1 0
-  %nop14559 = alloca i1, i1 0
-  %nop14560 = alloca i1, i1 0
-  %nop14561 = alloca i1, i1 0
-  %nop14562 = alloca i1, i1 0
-  %nop14563 = alloca i1, i1 0
-  %nop14564 = alloca i1, i1 0
-  %nop14565 = alloca i1, i1 0
-  %nop14566 = alloca i1, i1 0
-  %nop14567 = alloca i1, i1 0
-  %nop14568 = alloca i1, i1 0
-  %nop14569 = alloca i1, i1 0
-  %nop14570 = alloca i1, i1 0
-  %nop14571 = alloca i1, i1 0
-  %nop14572 = alloca i1, i1 0
-  %nop14573 = alloca i1, i1 0
-  %nop14574 = alloca i1, i1 0
-  %nop14575 = alloca i1, i1 0
-  %nop14576 = alloca i1, i1 0
-  %nop14577 = alloca i1, i1 0
-  %nop14578 = alloca i1, i1 0
-  %nop14579 = alloca i1, i1 0
-  %nop14580 = alloca i1, i1 0
-  %nop14581 = alloca i1, i1 0
-  %nop14582 = alloca i1, i1 0
-  %nop14583 = alloca i1, i1 0
-  %nop14584 = alloca i1, i1 0
-  %nop14585 = alloca i1, i1 0
-  %nop14586 = alloca i1, i1 0
-  %nop14587 = alloca i1, i1 0
-  %nop14588 = alloca i1, i1 0
-  %nop14589 = alloca i1, i1 0
-  %nop14590 = alloca i1, i1 0
-  %nop14591 = alloca i1, i1 0
-  %nop14592 = alloca i1, i1 0
-  %nop14593 = alloca i1, i1 0
-  %nop14594 = alloca i1, i1 0
-  %nop14595 = alloca i1, i1 0
-  %nop14596 = alloca i1, i1 0
-  %nop14597 = alloca i1, i1 0
-  %nop14598 = alloca i1, i1 0
-  %nop14599 = alloca i1, i1 0
-  %nop14600 = alloca i1, i1 0
-  %nop14601 = alloca i1, i1 0
-  %nop14602 = alloca i1, i1 0
-  %nop14603 = alloca i1, i1 0
-  %nop14604 = alloca i1, i1 0
-  %nop14605 = alloca i1, i1 0
-  %nop14606 = alloca i1, i1 0
-  %nop14607 = alloca i1, i1 0
-  %nop14608 = alloca i1, i1 0
-  %nop14609 = alloca i1, i1 0
-  %nop14610 = alloca i1, i1 0
-  %nop14611 = alloca i1, i1 0
-  %nop14612 = alloca i1, i1 0
-  %nop14613 = alloca i1, i1 0
-  %nop14614 = alloca i1, i1 0
-  %nop14615 = alloca i1, i1 0
-  %nop14616 = alloca i1, i1 0
-  %nop14617 = alloca i1, i1 0
-  %nop14618 = alloca i1, i1 0
-  %nop14619 = alloca i1, i1 0
-  %nop14620 = alloca i1, i1 0
-  %nop14621 = alloca i1, i1 0
-  %nop14622 = alloca i1, i1 0
-  %nop14623 = alloca i1, i1 0
-  %nop14624 = alloca i1, i1 0
-  %nop14625 = alloca i1, i1 0
-  %nop14626 = alloca i1, i1 0
-  %nop14627 = alloca i1, i1 0
-  %nop14628 = alloca i1, i1 0
-  %nop14629 = alloca i1, i1 0
-  %nop14630 = alloca i1, i1 0
-  %nop14631 = alloca i1, i1 0
-  %nop14632 = alloca i1, i1 0
-  %nop14633 = alloca i1, i1 0
-  %nop14634 = alloca i1, i1 0
-  %nop14635 = alloca i1, i1 0
-  %nop14636 = alloca i1, i1 0
-  %nop14637 = alloca i1, i1 0
-  %nop14638 = alloca i1, i1 0
-  %nop14639 = alloca i1, i1 0
-  %nop14640 = alloca i1, i1 0
-  %nop14641 = alloca i1, i1 0
-  %nop14642 = alloca i1, i1 0
-  %nop14643 = alloca i1, i1 0
-  %nop14644 = alloca i1, i1 0
-  %nop14645 = alloca i1, i1 0
-  %nop14646 = alloca i1, i1 0
-  %nop14647 = alloca i1, i1 0
-  %nop14648 = alloca i1, i1 0
-  %nop14649 = alloca i1, i1 0
-  %nop14650 = alloca i1, i1 0
-  %nop14651 = alloca i1, i1 0
-  %nop14652 = alloca i1, i1 0
-  %nop14653 = alloca i1, i1 0
-  %nop14654 = alloca i1, i1 0
-  %nop14655 = alloca i1, i1 0
-  %nop14656 = alloca i1, i1 0
-  %nop14657 = alloca i1, i1 0
-  %nop14658 = alloca i1, i1 0
-  %nop14659 = alloca i1, i1 0
-  %nop14660 = alloca i1, i1 0
-  %nop14661 = alloca i1, i1 0
-  %nop14662 = alloca i1, i1 0
-  %nop14663 = alloca i1, i1 0
-  %nop14664 = alloca i1, i1 0
-  %nop14665 = alloca i1, i1 0
-  %nop14666 = alloca i1, i1 0
-  %nop14667 = alloca i1, i1 0
-  %nop14668 = alloca i1, i1 0
-  %nop14669 = alloca i1, i1 0
-  %nop14670 = alloca i1, i1 0
-  %nop14671 = alloca i1, i1 0
-  %nop14672 = alloca i1, i1 0
-  %nop14673 = alloca i1, i1 0
-  %nop14674 = alloca i1, i1 0
-  %nop14675 = alloca i1, i1 0
-  %nop14676 = alloca i1, i1 0
-  %nop14677 = alloca i1, i1 0
-  %nop14678 = alloca i1, i1 0
-  %nop14679 = alloca i1, i1 0
-  %nop14680 = alloca i1, i1 0
-  %nop14681 = alloca i1, i1 0
-  %nop14682 = alloca i1, i1 0
-  %nop14683 = alloca i1, i1 0
-  %nop14684 = alloca i1, i1 0
-  %nop14685 = alloca i1, i1 0
-  %nop14686 = alloca i1, i1 0
-  %nop14687 = alloca i1, i1 0
-  %nop14688 = alloca i1, i1 0
-  %nop14689 = alloca i1, i1 0
-  %nop14690 = alloca i1, i1 0
-  %nop14691 = alloca i1, i1 0
-  %nop14692 = alloca i1, i1 0
-  %nop14693 = alloca i1, i1 0
-  %nop14694 = alloca i1, i1 0
-  %nop14695 = alloca i1, i1 0
-  %nop14696 = alloca i1, i1 0
-  %nop14697 = alloca i1, i1 0
-  %nop14698 = alloca i1, i1 0
-  %nop14699 = alloca i1, i1 0
-  %nop14700 = alloca i1, i1 0
-  %nop14701 = alloca i1, i1 0
-  %nop14702 = alloca i1, i1 0
-  %nop14703 = alloca i1, i1 0
-  %nop14704 = alloca i1, i1 0
-  %nop14705 = alloca i1, i1 0
-  %nop14706 = alloca i1, i1 0
-  %nop14707 = alloca i1, i1 0
-  %nop14708 = alloca i1, i1 0
-  %nop14709 = alloca i1, i1 0
-  %nop14710 = alloca i1, i1 0
-  %nop14711 = alloca i1, i1 0
-  %nop14712 = alloca i1, i1 0
-  %nop14713 = alloca i1, i1 0
-  %nop14714 = alloca i1, i1 0
-  %nop14715 = alloca i1, i1 0
-  %nop14716 = alloca i1, i1 0
-  %nop14717 = alloca i1, i1 0
-  %nop14718 = alloca i1, i1 0
-  %nop14719 = alloca i1, i1 0
-  %nop14720 = alloca i1, i1 0
-  %nop14721 = alloca i1, i1 0
-  %nop14722 = alloca i1, i1 0
-  %nop14723 = alloca i1, i1 0
-  %nop14724 = alloca i1, i1 0
-  %nop14725 = alloca i1, i1 0
-  %nop14726 = alloca i1, i1 0
-  %nop14727 = alloca i1, i1 0
-  %nop14728 = alloca i1, i1 0
-  %nop14729 = alloca i1, i1 0
-  %nop14730 = alloca i1, i1 0
-  %nop14731 = alloca i1, i1 0
-  %nop14732 = alloca i1, i1 0
-  %nop14733 = alloca i1, i1 0
-  %nop14734 = alloca i1, i1 0
-  %nop14735 = alloca i1, i1 0
-  %nop14736 = alloca i1, i1 0
-  %nop14737 = alloca i1, i1 0
-  %nop14738 = alloca i1, i1 0
-  %nop14739 = alloca i1, i1 0
-  %nop14740 = alloca i1, i1 0
-  %nop14741 = alloca i1, i1 0
-  %nop14742 = alloca i1, i1 0
-  %nop14743 = alloca i1, i1 0
-  %nop14744 = alloca i1, i1 0
-  %nop14745 = alloca i1, i1 0
-  %nop14746 = alloca i1, i1 0
-  %nop14747 = alloca i1, i1 0
-  %nop14748 = alloca i1, i1 0
-  %nop14749 = alloca i1, i1 0
-  %nop14750 = alloca i1, i1 0
-  %nop14751 = alloca i1, i1 0
-  %nop14752 = alloca i1, i1 0
-  %nop14753 = alloca i1, i1 0
-  %nop14754 = alloca i1, i1 0
-  %nop14755 = alloca i1, i1 0
-  %nop14756 = alloca i1, i1 0
-  %nop14757 = alloca i1, i1 0
-  %nop14758 = alloca i1, i1 0
-  %nop14759 = alloca i1, i1 0
-  %nop14760 = alloca i1, i1 0
-  %nop14761 = alloca i1, i1 0
-  %nop14762 = alloca i1, i1 0
-  %nop14763 = alloca i1, i1 0
-  %nop14764 = alloca i1, i1 0
-  %nop14765 = alloca i1, i1 0
-  %nop14766 = alloca i1, i1 0
-  %nop14767 = alloca i1, i1 0
-  %nop14768 = alloca i1, i1 0
-  %nop14769 = alloca i1, i1 0
-  %nop14770 = alloca i1, i1 0
-  %nop14771 = alloca i1, i1 0
-  %nop14772 = alloca i1, i1 0
-  %nop14773 = alloca i1, i1 0
-  %nop14774 = alloca i1, i1 0
-  %nop14775 = alloca i1, i1 0
-  %nop14776 = alloca i1, i1 0
-  %nop14777 = alloca i1, i1 0
-  %nop14778 = alloca i1, i1 0
-  %nop14779 = alloca i1, i1 0
-  %nop14780 = alloca i1, i1 0
-  %nop14781 = alloca i1, i1 0
-  %nop14782 = alloca i1, i1 0
-  %nop14783 = alloca i1, i1 0
-  %nop14784 = alloca i1, i1 0
-  %nop14785 = alloca i1, i1 0
-  %nop14786 = alloca i1, i1 0
-  %nop14787 = alloca i1, i1 0
-  %nop14788 = alloca i1, i1 0
-  %nop14789 = alloca i1, i1 0
-  %nop14790 = alloca i1, i1 0
-  %nop14791 = alloca i1, i1 0
-  %nop14792 = alloca i1, i1 0
-  %nop14793 = alloca i1, i1 0
-  %nop14794 = alloca i1, i1 0
-  %nop14795 = alloca i1, i1 0
-  %nop14796 = alloca i1, i1 0
-  %nop14797 = alloca i1, i1 0
-  %nop14798 = alloca i1, i1 0
-  %nop14799 = alloca i1, i1 0
-  %nop14800 = alloca i1, i1 0
-  %nop14801 = alloca i1, i1 0
-  %nop14802 = alloca i1, i1 0
-  %nop14803 = alloca i1, i1 0
-  %nop14804 = alloca i1, i1 0
-  %nop14805 = alloca i1, i1 0
-  %nop14806 = alloca i1, i1 0
-  %nop14807 = alloca i1, i1 0
-  %nop14808 = alloca i1, i1 0
-  %nop14809 = alloca i1, i1 0
-  %nop14810 = alloca i1, i1 0
-  %nop14811 = alloca i1, i1 0
-  %nop14812 = alloca i1, i1 0
-  %nop14813 = alloca i1, i1 0
-  %nop14814 = alloca i1, i1 0
-  %nop14815 = alloca i1, i1 0
-  %nop14816 = alloca i1, i1 0
-  %nop14817 = alloca i1, i1 0
-  %nop14818 = alloca i1, i1 0
-  %nop14819 = alloca i1, i1 0
-  %nop14820 = alloca i1, i1 0
-  %nop14821 = alloca i1, i1 0
-  %nop14822 = alloca i1, i1 0
-  %nop14823 = alloca i1, i1 0
-  %nop14824 = alloca i1, i1 0
-  %nop14825 = alloca i1, i1 0
-  %nop14826 = alloca i1, i1 0
-  %nop14827 = alloca i1, i1 0
-  %nop14828 = alloca i1, i1 0
-  %nop14829 = alloca i1, i1 0
-  %nop14830 = alloca i1, i1 0
-  %nop14831 = alloca i1, i1 0
-  %nop14832 = alloca i1, i1 0
-  %nop14833 = alloca i1, i1 0
-  %nop14834 = alloca i1, i1 0
-  %nop14835 = alloca i1, i1 0
-  %nop14836 = alloca i1, i1 0
-  %nop14837 = alloca i1, i1 0
-  %nop14838 = alloca i1, i1 0
-  %nop14839 = alloca i1, i1 0
-  %nop14840 = alloca i1, i1 0
-  %nop14841 = alloca i1, i1 0
-  %nop14842 = alloca i1, i1 0
-  %nop14843 = alloca i1, i1 0
-  %nop14844 = alloca i1, i1 0
-  %nop14845 = alloca i1, i1 0
-  %nop14846 = alloca i1, i1 0
-  %nop14847 = alloca i1, i1 0
-  %nop14848 = alloca i1, i1 0
-  %nop14849 = alloca i1, i1 0
-  %nop14850 = alloca i1, i1 0
-  %nop14851 = alloca i1, i1 0
-  %nop14852 = alloca i1, i1 0
-  %nop14853 = alloca i1, i1 0
-  %nop14854 = alloca i1, i1 0
-  %nop14855 = alloca i1, i1 0
-  %nop14856 = alloca i1, i1 0
-  %nop14857 = alloca i1, i1 0
-  %nop14858 = alloca i1, i1 0
-  %nop14859 = alloca i1, i1 0
-  %nop14860 = alloca i1, i1 0
-  %nop14861 = alloca i1, i1 0
-  %nop14862 = alloca i1, i1 0
-  %nop14863 = alloca i1, i1 0
-  %nop14864 = alloca i1, i1 0
-  %nop14865 = alloca i1, i1 0
-  %nop14866 = alloca i1, i1 0
-  %nop14867 = alloca i1, i1 0
-  %nop14868 = alloca i1, i1 0
-  %nop14869 = alloca i1, i1 0
-  %nop14870 = alloca i1, i1 0
-  %nop14871 = alloca i1, i1 0
-  %nop14872 = alloca i1, i1 0
-  %nop14873 = alloca i1, i1 0
-  %nop14874 = alloca i1, i1 0
-  %nop14875 = alloca i1, i1 0
-  %nop14876 = alloca i1, i1 0
-  %nop14877 = alloca i1, i1 0
-  %nop14878 = alloca i1, i1 0
-  %nop14879 = alloca i1, i1 0
-  %nop14880 = alloca i1, i1 0
-  %nop14881 = alloca i1, i1 0
-  %nop14882 = alloca i1, i1 0
-  %nop14883 = alloca i1, i1 0
-  %nop14884 = alloca i1, i1 0
-  %nop14885 = alloca i1, i1 0
-  %nop14886 = alloca i1, i1 0
-  %nop14887 = alloca i1, i1 0
-  %nop14888 = alloca i1, i1 0
-  %nop14889 = alloca i1, i1 0
-  %nop14890 = alloca i1, i1 0
-  %nop14891 = alloca i1, i1 0
-  %nop14892 = alloca i1, i1 0
-  %nop14893 = alloca i1, i1 0
-  %nop14894 = alloca i1, i1 0
-  %nop14895 = alloca i1, i1 0
-  %nop14896 = alloca i1, i1 0
-  %nop14897 = alloca i1, i1 0
-  %nop14898 = alloca i1, i1 0
-  %nop14899 = alloca i1, i1 0
-  %nop14900 = alloca i1, i1 0
-  %nop14901 = alloca i1, i1 0
-  %nop14902 = alloca i1, i1 0
-  %nop14903 = alloca i1, i1 0
-  %nop14904 = alloca i1, i1 0
-  %nop14905 = alloca i1, i1 0
-  %nop14906 = alloca i1, i1 0
-  %nop14907 = alloca i1, i1 0
-  %nop14908 = alloca i1, i1 0
-  %nop14909 = alloca i1, i1 0
-  %nop14910 = alloca i1, i1 0
-  %nop14911 = alloca i1, i1 0
-  %nop14912 = alloca i1, i1 0
-  %nop14913 = alloca i1, i1 0
-  %nop14914 = alloca i1, i1 0
-  %nop14915 = alloca i1, i1 0
-  %nop14916 = alloca i1, i1 0
-  %nop14917 = alloca i1, i1 0
-  %nop14918 = alloca i1, i1 0
-  %nop14919 = alloca i1, i1 0
-  %nop14920 = alloca i1, i1 0
-  %nop14921 = alloca i1, i1 0
-  %nop14922 = alloca i1, i1 0
-  %nop14923 = alloca i1, i1 0
-  %nop14924 = alloca i1, i1 0
-  %nop14925 = alloca i1, i1 0
-  %nop14926 = alloca i1, i1 0
-  %nop14927 = alloca i1, i1 0
-  %nop14928 = alloca i1, i1 0
-  %nop14929 = alloca i1, i1 0
-  %nop14930 = alloca i1, i1 0
-  %nop14931 = alloca i1, i1 0
-  %nop14932 = alloca i1, i1 0
-  %nop14933 = alloca i1, i1 0
-  %nop14934 = alloca i1, i1 0
-  %nop14935 = alloca i1, i1 0
-  %nop14936 = alloca i1, i1 0
-  %nop14937 = alloca i1, i1 0
-  %nop14938 = alloca i1, i1 0
-  %nop14939 = alloca i1, i1 0
-  %nop14940 = alloca i1, i1 0
-  %nop14941 = alloca i1, i1 0
-  %nop14942 = alloca i1, i1 0
-  %nop14943 = alloca i1, i1 0
-  %nop14944 = alloca i1, i1 0
-  %nop14945 = alloca i1, i1 0
-  %nop14946 = alloca i1, i1 0
-  %nop14947 = alloca i1, i1 0
-  %nop14948 = alloca i1, i1 0
-  %nop14949 = alloca i1, i1 0
-  %nop14950 = alloca i1, i1 0
-  %nop14951 = alloca i1, i1 0
-  %nop14952 = alloca i1, i1 0
-  %nop14953 = alloca i1, i1 0
-  %nop14954 = alloca i1, i1 0
-  %nop14955 = alloca i1, i1 0
-  %nop14956 = alloca i1, i1 0
-  %nop14957 = alloca i1, i1 0
-  %nop14958 = alloca i1, i1 0
-  %nop14959 = alloca i1, i1 0
-  %nop14960 = alloca i1, i1 0
-  %nop14961 = alloca i1, i1 0
-  %nop14962 = alloca i1, i1 0
-  %nop14963 = alloca i1, i1 0
-  %nop14964 = alloca i1, i1 0
-  %nop14965 = alloca i1, i1 0
-  %nop14966 = alloca i1, i1 0
-  %nop14967 = alloca i1, i1 0
-  %nop14968 = alloca i1, i1 0
-  %nop14969 = alloca i1, i1 0
-  %nop14970 = alloca i1, i1 0
-  %nop14971 = alloca i1, i1 0
-  %nop14972 = alloca i1, i1 0
-  %nop14973 = alloca i1, i1 0
-  %nop14974 = alloca i1, i1 0
-  %nop14975 = alloca i1, i1 0
-  %nop14976 = alloca i1, i1 0
-  %nop14977 = alloca i1, i1 0
-  %nop14978 = alloca i1, i1 0
-  %nop14979 = alloca i1, i1 0
-  %nop14980 = alloca i1, i1 0
-  %nop14981 = alloca i1, i1 0
-  %nop14982 = alloca i1, i1 0
-  %nop14983 = alloca i1, i1 0
-  %nop14984 = alloca i1, i1 0
-  %nop14985 = alloca i1, i1 0
-  %nop14986 = alloca i1, i1 0
-  %nop14987 = alloca i1, i1 0
-  %nop14988 = alloca i1, i1 0
-  %nop14989 = alloca i1, i1 0
-  %nop14990 = alloca i1, i1 0
-  %nop14991 = alloca i1, i1 0
-  %nop14992 = alloca i1, i1 0
-  %nop14993 = alloca i1, i1 0
-  %nop14994 = alloca i1, i1 0
-  %nop14995 = alloca i1, i1 0
-  %nop14996 = alloca i1, i1 0
-  %nop14997 = alloca i1, i1 0
-  %nop14998 = alloca i1, i1 0
-  %nop14999 = alloca i1, i1 0
-  %nop15000 = alloca i1, i1 0
-  %nop15001 = alloca i1, i1 0
-  %nop15002 = alloca i1, i1 0
-  %nop15003 = alloca i1, i1 0
-  %nop15004 = alloca i1, i1 0
-  %nop15005 = alloca i1, i1 0
-  %nop15006 = alloca i1, i1 0
-  %nop15007 = alloca i1, i1 0
-  %nop15008 = alloca i1, i1 0
-  %nop15009 = alloca i1, i1 0
-  %nop15010 = alloca i1, i1 0
-  %nop15011 = alloca i1, i1 0
-  %nop15012 = alloca i1, i1 0
-  %nop15013 = alloca i1, i1 0
-  %nop15014 = alloca i1, i1 0
-  %nop15015 = alloca i1, i1 0
-  %nop15016 = alloca i1, i1 0
-  %nop15017 = alloca i1, i1 0
-  %nop15018 = alloca i1, i1 0
-  %nop15019 = alloca i1, i1 0
-  %nop15020 = alloca i1, i1 0
-  %nop15021 = alloca i1, i1 0
-  %nop15022 = alloca i1, i1 0
-  %nop15023 = alloca i1, i1 0
-  %nop15024 = alloca i1, i1 0
-  %nop15025 = alloca i1, i1 0
-  %nop15026 = alloca i1, i1 0
-  %nop15027 = alloca i1, i1 0
-  %nop15028 = alloca i1, i1 0
-  %nop15029 = alloca i1, i1 0
-  %nop15030 = alloca i1, i1 0
-  %nop15031 = alloca i1, i1 0
-  %nop15032 = alloca i1, i1 0
-  %nop15033 = alloca i1, i1 0
-  %nop15034 = alloca i1, i1 0
-  %nop15035 = alloca i1, i1 0
-  %nop15036 = alloca i1, i1 0
-  %nop15037 = alloca i1, i1 0
-  %nop15038 = alloca i1, i1 0
-  %nop15039 = alloca i1, i1 0
-  %nop15040 = alloca i1, i1 0
-  %nop15041 = alloca i1, i1 0
-  %nop15042 = alloca i1, i1 0
-  %nop15043 = alloca i1, i1 0
-  %nop15044 = alloca i1, i1 0
-  %nop15045 = alloca i1, i1 0
-  %nop15046 = alloca i1, i1 0
-  %nop15047 = alloca i1, i1 0
-  %nop15048 = alloca i1, i1 0
-  %nop15049 = alloca i1, i1 0
-  %nop15050 = alloca i1, i1 0
-  %nop15051 = alloca i1, i1 0
-  %nop15052 = alloca i1, i1 0
-  %nop15053 = alloca i1, i1 0
-  %nop15054 = alloca i1, i1 0
-  %nop15055 = alloca i1, i1 0
-  %nop15056 = alloca i1, i1 0
-  %nop15057 = alloca i1, i1 0
-  %nop15058 = alloca i1, i1 0
-  %nop15059 = alloca i1, i1 0
-  %nop15060 = alloca i1, i1 0
-  %nop15061 = alloca i1, i1 0
-  %nop15062 = alloca i1, i1 0
-  %nop15063 = alloca i1, i1 0
-  %nop15064 = alloca i1, i1 0
-  %nop15065 = alloca i1, i1 0
-  %nop15066 = alloca i1, i1 0
-  %nop15067 = alloca i1, i1 0
-  %nop15068 = alloca i1, i1 0
-  %nop15069 = alloca i1, i1 0
-  %nop15070 = alloca i1, i1 0
-  %nop15071 = alloca i1, i1 0
-  %nop15072 = alloca i1, i1 0
-  %nop15073 = alloca i1, i1 0
-  %nop15074 = alloca i1, i1 0
-  %nop15075 = alloca i1, i1 0
-  %nop15076 = alloca i1, i1 0
-  %nop15077 = alloca i1, i1 0
-  %nop15078 = alloca i1, i1 0
-  %nop15079 = alloca i1, i1 0
-  %nop15080 = alloca i1, i1 0
-  %nop15081 = alloca i1, i1 0
-  %nop15082 = alloca i1, i1 0
-  %nop15083 = alloca i1, i1 0
-  %nop15084 = alloca i1, i1 0
-  %nop15085 = alloca i1, i1 0
-  %nop15086 = alloca i1, i1 0
-  %nop15087 = alloca i1, i1 0
-  %nop15088 = alloca i1, i1 0
-  %nop15089 = alloca i1, i1 0
-  %nop15090 = alloca i1, i1 0
-  %nop15091 = alloca i1, i1 0
-  %nop15092 = alloca i1, i1 0
-  %nop15093 = alloca i1, i1 0
-  %nop15094 = alloca i1, i1 0
-  %nop15095 = alloca i1, i1 0
-  %nop15096 = alloca i1, i1 0
-  %nop15097 = alloca i1, i1 0
-  %nop15098 = alloca i1, i1 0
-  %nop15099 = alloca i1, i1 0
-  %nop15100 = alloca i1, i1 0
-  %nop15101 = alloca i1, i1 0
-  %nop15102 = alloca i1, i1 0
-  %nop15103 = alloca i1, i1 0
-  %nop15104 = alloca i1, i1 0
-  %nop15105 = alloca i1, i1 0
-  %nop15106 = alloca i1, i1 0
-  %nop15107 = alloca i1, i1 0
-  %nop15108 = alloca i1, i1 0
-  %nop15109 = alloca i1, i1 0
-  %nop15110 = alloca i1, i1 0
-  %nop15111 = alloca i1, i1 0
-  %nop15112 = alloca i1, i1 0
-  %nop15113 = alloca i1, i1 0
-  %nop15114 = alloca i1, i1 0
-  %nop15115 = alloca i1, i1 0
-  %nop15116 = alloca i1, i1 0
-  %nop15117 = alloca i1, i1 0
-  %nop15118 = alloca i1, i1 0
-  %nop15119 = alloca i1, i1 0
-  %nop15120 = alloca i1, i1 0
-  %nop15121 = alloca i1, i1 0
-  %nop15122 = alloca i1, i1 0
-  %nop15123 = alloca i1, i1 0
-  %nop15124 = alloca i1, i1 0
-  %nop15125 = alloca i1, i1 0
-  %nop15126 = alloca i1, i1 0
-  %nop15127 = alloca i1, i1 0
-  %nop15128 = alloca i1, i1 0
-  %nop15129 = alloca i1, i1 0
-  %nop15130 = alloca i1, i1 0
-  %nop15131 = alloca i1, i1 0
-  %nop15132 = alloca i1, i1 0
-  %nop15133 = alloca i1, i1 0
-  %nop15134 = alloca i1, i1 0
-  %nop15135 = alloca i1, i1 0
-  %nop15136 = alloca i1, i1 0
-  %nop15137 = alloca i1, i1 0
-  %nop15138 = alloca i1, i1 0
-  %nop15139 = alloca i1, i1 0
-  %nop15140 = alloca i1, i1 0
-  %nop15141 = alloca i1, i1 0
-  %nop15142 = alloca i1, i1 0
-  %nop15143 = alloca i1, i1 0
-  %nop15144 = alloca i1, i1 0
-  %nop15145 = alloca i1, i1 0
-  %nop15146 = alloca i1, i1 0
-  %nop15147 = alloca i1, i1 0
-  %nop15148 = alloca i1, i1 0
-  %nop15149 = alloca i1, i1 0
-  %nop15150 = alloca i1, i1 0
-  %nop15151 = alloca i1, i1 0
-  %nop15152 = alloca i1, i1 0
-  %nop15153 = alloca i1, i1 0
-  %nop15154 = alloca i1, i1 0
-  %nop15155 = alloca i1, i1 0
-  %nop15156 = alloca i1, i1 0
-  %nop15157 = alloca i1, i1 0
-  %nop15158 = alloca i1, i1 0
-  %nop15159 = alloca i1, i1 0
-  %nop15160 = alloca i1, i1 0
-  %nop15161 = alloca i1, i1 0
-  %nop15162 = alloca i1, i1 0
-  %nop15163 = alloca i1, i1 0
-  %nop15164 = alloca i1, i1 0
-  %nop15165 = alloca i1, i1 0
-  %nop15166 = alloca i1, i1 0
-  %nop15167 = alloca i1, i1 0
-  %nop15168 = alloca i1, i1 0
-  %nop15169 = alloca i1, i1 0
-  %nop15170 = alloca i1, i1 0
-  %nop15171 = alloca i1, i1 0
-  %nop15172 = alloca i1, i1 0
-  %nop15173 = alloca i1, i1 0
-  %nop15174 = alloca i1, i1 0
-  %nop15175 = alloca i1, i1 0
-  %nop15176 = alloca i1, i1 0
-  %nop15177 = alloca i1, i1 0
-  %nop15178 = alloca i1, i1 0
-  %nop15179 = alloca i1, i1 0
-  %nop15180 = alloca i1, i1 0
-  %nop15181 = alloca i1, i1 0
-  %nop15182 = alloca i1, i1 0
-  %nop15183 = alloca i1, i1 0
-  %nop15184 = alloca i1, i1 0
-  %nop15185 = alloca i1, i1 0
-  %nop15186 = alloca i1, i1 0
-  %nop15187 = alloca i1, i1 0
-  %nop15188 = alloca i1, i1 0
-  %nop15189 = alloca i1, i1 0
-  %nop15190 = alloca i1, i1 0
-  %nop15191 = alloca i1, i1 0
-  %nop15192 = alloca i1, i1 0
-  %nop15193 = alloca i1, i1 0
-  %nop15194 = alloca i1, i1 0
-  %nop15195 = alloca i1, i1 0
-  %nop15196 = alloca i1, i1 0
-  %nop15197 = alloca i1, i1 0
-  %nop15198 = alloca i1, i1 0
-  %nop15199 = alloca i1, i1 0
-  %nop15200 = alloca i1, i1 0
-  %nop15201 = alloca i1, i1 0
-  %nop15202 = alloca i1, i1 0
-  %nop15203 = alloca i1, i1 0
-  %nop15204 = alloca i1, i1 0
-  %nop15205 = alloca i1, i1 0
-  %nop15206 = alloca i1, i1 0
-  %nop15207 = alloca i1, i1 0
-  %nop15208 = alloca i1, i1 0
-  %nop15209 = alloca i1, i1 0
-  %nop15210 = alloca i1, i1 0
-  %nop15211 = alloca i1, i1 0
-  %nop15212 = alloca i1, i1 0
-  %nop15213 = alloca i1, i1 0
-  %nop15214 = alloca i1, i1 0
-  %nop15215 = alloca i1, i1 0
-  %nop15216 = alloca i1, i1 0
-  %nop15217 = alloca i1, i1 0
-  %nop15218 = alloca i1, i1 0
-  %nop15219 = alloca i1, i1 0
-  %nop15220 = alloca i1, i1 0
-  %nop15221 = alloca i1, i1 0
-  %nop15222 = alloca i1, i1 0
-  %nop15223 = alloca i1, i1 0
-  %nop15224 = alloca i1, i1 0
-  %nop15225 = alloca i1, i1 0
-  %nop15226 = alloca i1, i1 0
-  %nop15227 = alloca i1, i1 0
-  %nop15228 = alloca i1, i1 0
-  %nop15229 = alloca i1, i1 0
-  %nop15230 = alloca i1, i1 0
-  %nop15231 = alloca i1, i1 0
-  %nop15232 = alloca i1, i1 0
-  %nop15233 = alloca i1, i1 0
-  %nop15234 = alloca i1, i1 0
-  %nop15235 = alloca i1, i1 0
-  %nop15236 = alloca i1, i1 0
-  %nop15237 = alloca i1, i1 0
-  %nop15238 = alloca i1, i1 0
-  %nop15239 = alloca i1, i1 0
-  %nop15240 = alloca i1, i1 0
-  %nop15241 = alloca i1, i1 0
-  %nop15242 = alloca i1, i1 0
-  %nop15243 = alloca i1, i1 0
-  %nop15244 = alloca i1, i1 0
-  %nop15245 = alloca i1, i1 0
-  %nop15246 = alloca i1, i1 0
-  %nop15247 = alloca i1, i1 0
-  %nop15248 = alloca i1, i1 0
-  %nop15249 = alloca i1, i1 0
-  %nop15250 = alloca i1, i1 0
-  %nop15251 = alloca i1, i1 0
-  %nop15252 = alloca i1, i1 0
-  %nop15253 = alloca i1, i1 0
-  %nop15254 = alloca i1, i1 0
-  %nop15255 = alloca i1, i1 0
-  %nop15256 = alloca i1, i1 0
-  %nop15257 = alloca i1, i1 0
-  %nop15258 = alloca i1, i1 0
-  %nop15259 = alloca i1, i1 0
-  %nop15260 = alloca i1, i1 0
-  %nop15261 = alloca i1, i1 0
-  %nop15262 = alloca i1, i1 0
-  %nop15263 = alloca i1, i1 0
-  %nop15264 = alloca i1, i1 0
-  %nop15265 = alloca i1, i1 0
-  %nop15266 = alloca i1, i1 0
-  %nop15267 = alloca i1, i1 0
-  %nop15268 = alloca i1, i1 0
-  %nop15269 = alloca i1, i1 0
-  %nop15270 = alloca i1, i1 0
-  %nop15271 = alloca i1, i1 0
-  %nop15272 = alloca i1, i1 0
-  %nop15273 = alloca i1, i1 0
-  %nop15274 = alloca i1, i1 0
-  %nop15275 = alloca i1, i1 0
-  %nop15276 = alloca i1, i1 0
-  %nop15277 = alloca i1, i1 0
-  %nop15278 = alloca i1, i1 0
-  %nop15279 = alloca i1, i1 0
-  %nop15280 = alloca i1, i1 0
-  %nop15281 = alloca i1, i1 0
-  %nop15282 = alloca i1, i1 0
-  %nop15283 = alloca i1, i1 0
-  %nop15284 = alloca i1, i1 0
-  %nop15285 = alloca i1, i1 0
-  %nop15286 = alloca i1, i1 0
-  %nop15287 = alloca i1, i1 0
-  %nop15288 = alloca i1, i1 0
-  %nop15289 = alloca i1, i1 0
-  %nop15290 = alloca i1, i1 0
-  %nop15291 = alloca i1, i1 0
-  %nop15292 = alloca i1, i1 0
-  %nop15293 = alloca i1, i1 0
-  %nop15294 = alloca i1, i1 0
-  %nop15295 = alloca i1, i1 0
-  %nop15296 = alloca i1, i1 0
-  %nop15297 = alloca i1, i1 0
-  %nop15298 = alloca i1, i1 0
-  %nop15299 = alloca i1, i1 0
-  %nop15300 = alloca i1, i1 0
-  %nop15301 = alloca i1, i1 0
-  %nop15302 = alloca i1, i1 0
-  %nop15303 = alloca i1, i1 0
-  %nop15304 = alloca i1, i1 0
-  %nop15305 = alloca i1, i1 0
-  %nop15306 = alloca i1, i1 0
-  %nop15307 = alloca i1, i1 0
-  %nop15308 = alloca i1, i1 0
-  %nop15309 = alloca i1, i1 0
-  %nop15310 = alloca i1, i1 0
-  %nop15311 = alloca i1, i1 0
-  %nop15312 = alloca i1, i1 0
-  %nop15313 = alloca i1, i1 0
-  %nop15314 = alloca i1, i1 0
-  %nop15315 = alloca i1, i1 0
-  %nop15316 = alloca i1, i1 0
-  %nop15317 = alloca i1, i1 0
-  %nop15318 = alloca i1, i1 0
-  %nop15319 = alloca i1, i1 0
-  %nop15320 = alloca i1, i1 0
-  %nop15321 = alloca i1, i1 0
-  %nop15322 = alloca i1, i1 0
-  %nop15323 = alloca i1, i1 0
-  %nop15324 = alloca i1, i1 0
-  %nop15325 = alloca i1, i1 0
-  %nop15326 = alloca i1, i1 0
-  %nop15327 = alloca i1, i1 0
-  %nop15328 = alloca i1, i1 0
-  %nop15329 = alloca i1, i1 0
-  %nop15330 = alloca i1, i1 0
-  %nop15331 = alloca i1, i1 0
-  %nop15332 = alloca i1, i1 0
-  %nop15333 = alloca i1, i1 0
-  %nop15334 = alloca i1, i1 0
-  %nop15335 = alloca i1, i1 0
-  %nop15336 = alloca i1, i1 0
-  %nop15337 = alloca i1, i1 0
-  %nop15338 = alloca i1, i1 0
-  %nop15339 = alloca i1, i1 0
-  %nop15340 = alloca i1, i1 0
-  %nop15341 = alloca i1, i1 0
-  %nop15342 = alloca i1, i1 0
-  %nop15343 = alloca i1, i1 0
-  %nop15344 = alloca i1, i1 0
-  %nop15345 = alloca i1, i1 0
-  %nop15346 = alloca i1, i1 0
-  %nop15347 = alloca i1, i1 0
-  %nop15348 = alloca i1, i1 0
-  %nop15349 = alloca i1, i1 0
-  %nop15350 = alloca i1, i1 0
-  %nop15351 = alloca i1, i1 0
-  %nop15352 = alloca i1, i1 0
-  %nop15353 = alloca i1, i1 0
-  %nop15354 = alloca i1, i1 0
-  %nop15355 = alloca i1, i1 0
-  %nop15356 = alloca i1, i1 0
-  %nop15357 = alloca i1, i1 0
-  %nop15358 = alloca i1, i1 0
-  %nop15359 = alloca i1, i1 0
-  %nop15360 = alloca i1, i1 0
-  %nop15361 = alloca i1, i1 0
-  %nop15362 = alloca i1, i1 0
-  %nop15363 = alloca i1, i1 0
-  %nop15364 = alloca i1, i1 0
-  %nop15365 = alloca i1, i1 0
-  %nop15366 = alloca i1, i1 0
-  %nop15367 = alloca i1, i1 0
-  %nop15368 = alloca i1, i1 0
-  %nop15369 = alloca i1, i1 0
-  %nop15370 = alloca i1, i1 0
-  %nop15371 = alloca i1, i1 0
-  %nop15372 = alloca i1, i1 0
-  %nop15373 = alloca i1, i1 0
-  %nop15374 = alloca i1, i1 0
-  %nop15375 = alloca i1, i1 0
-  %nop15376 = alloca i1, i1 0
-  %nop15377 = alloca i1, i1 0
-  %nop15378 = alloca i1, i1 0
-  %nop15379 = alloca i1, i1 0
-  %nop15380 = alloca i1, i1 0
-  %nop15381 = alloca i1, i1 0
-  %nop15382 = alloca i1, i1 0
-  %nop15383 = alloca i1, i1 0
-  %nop15384 = alloca i1, i1 0
-  %nop15385 = alloca i1, i1 0
-  %nop15386 = alloca i1, i1 0
-  %nop15387 = alloca i1, i1 0
-  %nop15388 = alloca i1, i1 0
-  %nop15389 = alloca i1, i1 0
-  %nop15390 = alloca i1, i1 0
-  %nop15391 = alloca i1, i1 0
-  %nop15392 = alloca i1, i1 0
-  %nop15393 = alloca i1, i1 0
-  %nop15394 = alloca i1, i1 0
-  %nop15395 = alloca i1, i1 0
-  %nop15396 = alloca i1, i1 0
-  %nop15397 = alloca i1, i1 0
-  %nop15398 = alloca i1, i1 0
-  %nop15399 = alloca i1, i1 0
-  %nop15400 = alloca i1, i1 0
-  %nop15401 = alloca i1, i1 0
-  %nop15402 = alloca i1, i1 0
-  %nop15403 = alloca i1, i1 0
-  %nop15404 = alloca i1, i1 0
-  %nop15405 = alloca i1, i1 0
-  %nop15406 = alloca i1, i1 0
-  %nop15407 = alloca i1, i1 0
-  %nop15408 = alloca i1, i1 0
-  %nop15409 = alloca i1, i1 0
-  %nop15410 = alloca i1, i1 0
-  %nop15411 = alloca i1, i1 0
-  %nop15412 = alloca i1, i1 0
-  %nop15413 = alloca i1, i1 0
-  %nop15414 = alloca i1, i1 0
-  %nop15415 = alloca i1, i1 0
-  %nop15416 = alloca i1, i1 0
-  %nop15417 = alloca i1, i1 0
-  %nop15418 = alloca i1, i1 0
-  %nop15419 = alloca i1, i1 0
-  %nop15420 = alloca i1, i1 0
-  %nop15421 = alloca i1, i1 0
-  %nop15422 = alloca i1, i1 0
-  %nop15423 = alloca i1, i1 0
-  %nop15424 = alloca i1, i1 0
-  %nop15425 = alloca i1, i1 0
-  %nop15426 = alloca i1, i1 0
-  %nop15427 = alloca i1, i1 0
-  %nop15428 = alloca i1, i1 0
-  %nop15429 = alloca i1, i1 0
-  %nop15430 = alloca i1, i1 0
-  %nop15431 = alloca i1, i1 0
-  %nop15432 = alloca i1, i1 0
-  %nop15433 = alloca i1, i1 0
-  %nop15434 = alloca i1, i1 0
-  %nop15435 = alloca i1, i1 0
-  %nop15436 = alloca i1, i1 0
-  %nop15437 = alloca i1, i1 0
-  %nop15438 = alloca i1, i1 0
-  %nop15439 = alloca i1, i1 0
-  %nop15440 = alloca i1, i1 0
-  %nop15441 = alloca i1, i1 0
-  %nop15442 = alloca i1, i1 0
-  %nop15443 = alloca i1, i1 0
-  %nop15444 = alloca i1, i1 0
-  %nop15445 = alloca i1, i1 0
-  %nop15446 = alloca i1, i1 0
-  %nop15447 = alloca i1, i1 0
-  %nop15448 = alloca i1, i1 0
-  %nop15449 = alloca i1, i1 0
-  %nop15450 = alloca i1, i1 0
-  %nop15451 = alloca i1, i1 0
-  %nop15452 = alloca i1, i1 0
-  %nop15453 = alloca i1, i1 0
-  %nop15454 = alloca i1, i1 0
-  %nop15455 = alloca i1, i1 0
-  %nop15456 = alloca i1, i1 0
-  %nop15457 = alloca i1, i1 0
-  %nop15458 = alloca i1, i1 0
-  %nop15459 = alloca i1, i1 0
-  %nop15460 = alloca i1, i1 0
-  %nop15461 = alloca i1, i1 0
-  %nop15462 = alloca i1, i1 0
-  %nop15463 = alloca i1, i1 0
-  %nop15464 = alloca i1, i1 0
-  %nop15465 = alloca i1, i1 0
-  %nop15466 = alloca i1, i1 0
-  %nop15467 = alloca i1, i1 0
-  %nop15468 = alloca i1, i1 0
-  %nop15469 = alloca i1, i1 0
-  %nop15470 = alloca i1, i1 0
-  %nop15471 = alloca i1, i1 0
-  %nop15472 = alloca i1, i1 0
-  %nop15473 = alloca i1, i1 0
-  %nop15474 = alloca i1, i1 0
-  %nop15475 = alloca i1, i1 0
-  %nop15476 = alloca i1, i1 0
-  %nop15477 = alloca i1, i1 0
-  %nop15478 = alloca i1, i1 0
-  %nop15479 = alloca i1, i1 0
-  %nop15480 = alloca i1, i1 0
-  %nop15481 = alloca i1, i1 0
-  %nop15482 = alloca i1, i1 0
-  %nop15483 = alloca i1, i1 0
-  %nop15484 = alloca i1, i1 0
-  %nop15485 = alloca i1, i1 0
-  %nop15486 = alloca i1, i1 0
-  %nop15487 = alloca i1, i1 0
-  %nop15488 = alloca i1, i1 0
-  %nop15489 = alloca i1, i1 0
-  %nop15490 = alloca i1, i1 0
-  %nop15491 = alloca i1, i1 0
-  %nop15492 = alloca i1, i1 0
-  %nop15493 = alloca i1, i1 0
-  %nop15494 = alloca i1, i1 0
-  %nop15495 = alloca i1, i1 0
-  %nop15496 = alloca i1, i1 0
-  %nop15497 = alloca i1, i1 0
-  %nop15498 = alloca i1, i1 0
-  %nop15499 = alloca i1, i1 0
-  %nop15500 = alloca i1, i1 0
-  %nop15501 = alloca i1, i1 0
-  %nop15502 = alloca i1, i1 0
-  %nop15503 = alloca i1, i1 0
-  %nop15504 = alloca i1, i1 0
-  %nop15505 = alloca i1, i1 0
-  %nop15506 = alloca i1, i1 0
-  %nop15507 = alloca i1, i1 0
-  %nop15508 = alloca i1, i1 0
-  %nop15509 = alloca i1, i1 0
-  %nop15510 = alloca i1, i1 0
-  %nop15511 = alloca i1, i1 0
-  %nop15512 = alloca i1, i1 0
-  %nop15513 = alloca i1, i1 0
-  %nop15514 = alloca i1, i1 0
-  %nop15515 = alloca i1, i1 0
-  %nop15516 = alloca i1, i1 0
-  %nop15517 = alloca i1, i1 0
-  %nop15518 = alloca i1, i1 0
-  %nop15519 = alloca i1, i1 0
-  %nop15520 = alloca i1, i1 0
-  %nop15521 = alloca i1, i1 0
-  %nop15522 = alloca i1, i1 0
-  %nop15523 = alloca i1, i1 0
-  %nop15524 = alloca i1, i1 0
-  %nop15525 = alloca i1, i1 0
-  %nop15526 = alloca i1, i1 0
-  %nop15527 = alloca i1, i1 0
-  %nop15528 = alloca i1, i1 0
-  %nop15529 = alloca i1, i1 0
-  %nop15530 = alloca i1, i1 0
-  %nop15531 = alloca i1, i1 0
-  %nop15532 = alloca i1, i1 0
-  %nop15533 = alloca i1, i1 0
-  %nop15534 = alloca i1, i1 0
-  %nop15535 = alloca i1, i1 0
-  %nop15536 = alloca i1, i1 0
-  %nop15537 = alloca i1, i1 0
-  %nop15538 = alloca i1, i1 0
-  %nop15539 = alloca i1, i1 0
-  %nop15540 = alloca i1, i1 0
-  %nop15541 = alloca i1, i1 0
-  %nop15542 = alloca i1, i1 0
-  %nop15543 = alloca i1, i1 0
-  %nop15544 = alloca i1, i1 0
-  %nop15545 = alloca i1, i1 0
-  %nop15546 = alloca i1, i1 0
-  %nop15547 = alloca i1, i1 0
-  %nop15548 = alloca i1, i1 0
-  %nop15549 = alloca i1, i1 0
-  %nop15550 = alloca i1, i1 0
-  %nop15551 = alloca i1, i1 0
-  %nop15552 = alloca i1, i1 0
-  %nop15553 = alloca i1, i1 0
-  %nop15554 = alloca i1, i1 0
-  %nop15555 = alloca i1, i1 0
-  %nop15556 = alloca i1, i1 0
-  %nop15557 = alloca i1, i1 0
-  %nop15558 = alloca i1, i1 0
-  %nop15559 = alloca i1, i1 0
-  %nop15560 = alloca i1, i1 0
-  %nop15561 = alloca i1, i1 0
-  %nop15562 = alloca i1, i1 0
-  %nop15563 = alloca i1, i1 0
-  %nop15564 = alloca i1, i1 0
-  %nop15565 = alloca i1, i1 0
-  %nop15566 = alloca i1, i1 0
-  %nop15567 = alloca i1, i1 0
-  %nop15568 = alloca i1, i1 0
-  %nop15569 = alloca i1, i1 0
-  %nop15570 = alloca i1, i1 0
-  %nop15571 = alloca i1, i1 0
-  %nop15572 = alloca i1, i1 0
-  %nop15573 = alloca i1, i1 0
-  %nop15574 = alloca i1, i1 0
-  %nop15575 = alloca i1, i1 0
-  %nop15576 = alloca i1, i1 0
-  %nop15577 = alloca i1, i1 0
-  %nop15578 = alloca i1, i1 0
-  %nop15579 = alloca i1, i1 0
-  %nop15580 = alloca i1, i1 0
-  %nop15581 = alloca i1, i1 0
-  %nop15582 = alloca i1, i1 0
-  %nop15583 = alloca i1, i1 0
-  %nop15584 = alloca i1, i1 0
-  %nop15585 = alloca i1, i1 0
-  %nop15586 = alloca i1, i1 0
-  %nop15587 = alloca i1, i1 0
-  %nop15588 = alloca i1, i1 0
-  %nop15589 = alloca i1, i1 0
-  %nop15590 = alloca i1, i1 0
-  %nop15591 = alloca i1, i1 0
-  %nop15592 = alloca i1, i1 0
-  %nop15593 = alloca i1, i1 0
-  %nop15594 = alloca i1, i1 0
-  %nop15595 = alloca i1, i1 0
-  %nop15596 = alloca i1, i1 0
-  %nop15597 = alloca i1, i1 0
-  %nop15598 = alloca i1, i1 0
-  %nop15599 = alloca i1, i1 0
-  %nop15600 = alloca i1, i1 0
-  %nop15601 = alloca i1, i1 0
-  %nop15602 = alloca i1, i1 0
-  %nop15603 = alloca i1, i1 0
-  %nop15604 = alloca i1, i1 0
-  %nop15605 = alloca i1, i1 0
-  %nop15606 = alloca i1, i1 0
-  %nop15607 = alloca i1, i1 0
-  %nop15608 = alloca i1, i1 0
-  %nop15609 = alloca i1, i1 0
-  %nop15610 = alloca i1, i1 0
-  %nop15611 = alloca i1, i1 0
-  %nop15612 = alloca i1, i1 0
-  %nop15613 = alloca i1, i1 0
-  %nop15614 = alloca i1, i1 0
-  %nop15615 = alloca i1, i1 0
-  %nop15616 = alloca i1, i1 0
-  %nop15617 = alloca i1, i1 0
-  %nop15618 = alloca i1, i1 0
-  %nop15619 = alloca i1, i1 0
-  %nop15620 = alloca i1, i1 0
-  %nop15621 = alloca i1, i1 0
-  %nop15622 = alloca i1, i1 0
-  %nop15623 = alloca i1, i1 0
-  %nop15624 = alloca i1, i1 0
-  %nop15625 = alloca i1, i1 0
-  %nop15626 = alloca i1, i1 0
-  %nop15627 = alloca i1, i1 0
-  %nop15628 = alloca i1, i1 0
-  %nop15629 = alloca i1, i1 0
-  %nop15630 = alloca i1, i1 0
-  %nop15631 = alloca i1, i1 0
-  %nop15632 = alloca i1, i1 0
-  %nop15633 = alloca i1, i1 0
-  %nop15634 = alloca i1, i1 0
-  %nop15635 = alloca i1, i1 0
-  %nop15636 = alloca i1, i1 0
-  %nop15637 = alloca i1, i1 0
-  %nop15638 = alloca i1, i1 0
-  %nop15639 = alloca i1, i1 0
-  %nop15640 = alloca i1, i1 0
-  %nop15641 = alloca i1, i1 0
-  %nop15642 = alloca i1, i1 0
-  %nop15643 = alloca i1, i1 0
-  %nop15644 = alloca i1, i1 0
-  %nop15645 = alloca i1, i1 0
-  %nop15646 = alloca i1, i1 0
-  %nop15647 = alloca i1, i1 0
-  %nop15648 = alloca i1, i1 0
-  %nop15649 = alloca i1, i1 0
-  %nop15650 = alloca i1, i1 0
-  %nop15651 = alloca i1, i1 0
-  %nop15652 = alloca i1, i1 0
-  %nop15653 = alloca i1, i1 0
-  %nop15654 = alloca i1, i1 0
-  %nop15655 = alloca i1, i1 0
-  %nop15656 = alloca i1, i1 0
-  %nop15657 = alloca i1, i1 0
-  %nop15658 = alloca i1, i1 0
-  %nop15659 = alloca i1, i1 0
-  %nop15660 = alloca i1, i1 0
-  %nop15661 = alloca i1, i1 0
-  %nop15662 = alloca i1, i1 0
-  %nop15663 = alloca i1, i1 0
-  %nop15664 = alloca i1, i1 0
-  %nop15665 = alloca i1, i1 0
-  %nop15666 = alloca i1, i1 0
-  %nop15667 = alloca i1, i1 0
-  %nop15668 = alloca i1, i1 0
-  %nop15669 = alloca i1, i1 0
-  %nop15670 = alloca i1, i1 0
-  %nop15671 = alloca i1, i1 0
-  %nop15672 = alloca i1, i1 0
-  %nop15673 = alloca i1, i1 0
-  %nop15674 = alloca i1, i1 0
-  %nop15675 = alloca i1, i1 0
-  %nop15676 = alloca i1, i1 0
-  %nop15677 = alloca i1, i1 0
-  %nop15678 = alloca i1, i1 0
-  %nop15679 = alloca i1, i1 0
-  %nop15680 = alloca i1, i1 0
-  %nop15681 = alloca i1, i1 0
-  %nop15682 = alloca i1, i1 0
-  %nop15683 = alloca i1, i1 0
-  %nop15684 = alloca i1, i1 0
-  %nop15685 = alloca i1, i1 0
-  %nop15686 = alloca i1, i1 0
-  %nop15687 = alloca i1, i1 0
-  %nop15688 = alloca i1, i1 0
-  %nop15689 = alloca i1, i1 0
-  %nop15690 = alloca i1, i1 0
-  %nop15691 = alloca i1, i1 0
-  %nop15692 = alloca i1, i1 0
-  %nop15693 = alloca i1, i1 0
-  %nop15694 = alloca i1, i1 0
-  %nop15695 = alloca i1, i1 0
-  %nop15696 = alloca i1, i1 0
-  %nop15697 = alloca i1, i1 0
-  %nop15698 = alloca i1, i1 0
-  %nop15699 = alloca i1, i1 0
-  %nop15700 = alloca i1, i1 0
-  %nop15701 = alloca i1, i1 0
-  %nop15702 = alloca i1, i1 0
-  %nop15703 = alloca i1, i1 0
-  %nop15704 = alloca i1, i1 0
-  %nop15705 = alloca i1, i1 0
-  %nop15706 = alloca i1, i1 0
-  %nop15707 = alloca i1, i1 0
-  %nop15708 = alloca i1, i1 0
-  %nop15709 = alloca i1, i1 0
-  %nop15710 = alloca i1, i1 0
-  %nop15711 = alloca i1, i1 0
-  %nop15712 = alloca i1, i1 0
-  %nop15713 = alloca i1, i1 0
-  %nop15714 = alloca i1, i1 0
-  %nop15715 = alloca i1, i1 0
-  %nop15716 = alloca i1, i1 0
-  %nop15717 = alloca i1, i1 0
-  %nop15718 = alloca i1, i1 0
-  %nop15719 = alloca i1, i1 0
-  %nop15720 = alloca i1, i1 0
-  %nop15721 = alloca i1, i1 0
-  %nop15722 = alloca i1, i1 0
-  %nop15723 = alloca i1, i1 0
-  %nop15724 = alloca i1, i1 0
-  %nop15725 = alloca i1, i1 0
-  %nop15726 = alloca i1, i1 0
-  %nop15727 = alloca i1, i1 0
-  %nop15728 = alloca i1, i1 0
-  %nop15729 = alloca i1, i1 0
-  %nop15730 = alloca i1, i1 0
-  %nop15731 = alloca i1, i1 0
-  %nop15732 = alloca i1, i1 0
-  %nop15733 = alloca i1, i1 0
-  %nop15734 = alloca i1, i1 0
-  %nop15735 = alloca i1, i1 0
-  %nop15736 = alloca i1, i1 0
-  %nop15737 = alloca i1, i1 0
-  %nop15738 = alloca i1, i1 0
-  %nop15739 = alloca i1, i1 0
-  %nop15740 = alloca i1, i1 0
-  %nop15741 = alloca i1, i1 0
-  %nop15742 = alloca i1, i1 0
-  %nop15743 = alloca i1, i1 0
-  %nop15744 = alloca i1, i1 0
-  %nop15745 = alloca i1, i1 0
-  %nop15746 = alloca i1, i1 0
-  %nop15747 = alloca i1, i1 0
-  %nop15748 = alloca i1, i1 0
-  %nop15749 = alloca i1, i1 0
-  %nop15750 = alloca i1, i1 0
-  %nop15751 = alloca i1, i1 0
-  %nop15752 = alloca i1, i1 0
-  %nop15753 = alloca i1, i1 0
-  %nop15754 = alloca i1, i1 0
-  %nop15755 = alloca i1, i1 0
-  %nop15756 = alloca i1, i1 0
-  %nop15757 = alloca i1, i1 0
-  %nop15758 = alloca i1, i1 0
-  %nop15759 = alloca i1, i1 0
-  %nop15760 = alloca i1, i1 0
-  %nop15761 = alloca i1, i1 0
-  %nop15762 = alloca i1, i1 0
-  %nop15763 = alloca i1, i1 0
-  %nop15764 = alloca i1, i1 0
-  %nop15765 = alloca i1, i1 0
-  %nop15766 = alloca i1, i1 0
-  %nop15767 = alloca i1, i1 0
-  %nop15768 = alloca i1, i1 0
-  %nop15769 = alloca i1, i1 0
-  %nop15770 = alloca i1, i1 0
-  %nop15771 = alloca i1, i1 0
-  %nop15772 = alloca i1, i1 0
-  %nop15773 = alloca i1, i1 0
-  %nop15774 = alloca i1, i1 0
-  %nop15775 = alloca i1, i1 0
-  %nop15776 = alloca i1, i1 0
-  %nop15777 = alloca i1, i1 0
-  %nop15778 = alloca i1, i1 0
-  %nop15779 = alloca i1, i1 0
-  %nop15780 = alloca i1, i1 0
-  %nop15781 = alloca i1, i1 0
-  %nop15782 = alloca i1, i1 0
-  %nop15783 = alloca i1, i1 0
-  %nop15784 = alloca i1, i1 0
-  %nop15785 = alloca i1, i1 0
-  %nop15786 = alloca i1, i1 0
-  %nop15787 = alloca i1, i1 0
-  %nop15788 = alloca i1, i1 0
-  %nop15789 = alloca i1, i1 0
-  %nop15790 = alloca i1, i1 0
-  %nop15791 = alloca i1, i1 0
-  %nop15792 = alloca i1, i1 0
-  %nop15793 = alloca i1, i1 0
-  %nop15794 = alloca i1, i1 0
-  %nop15795 = alloca i1, i1 0
-  %nop15796 = alloca i1, i1 0
-  %nop15797 = alloca i1, i1 0
-  %nop15798 = alloca i1, i1 0
-  %nop15799 = alloca i1, i1 0
-  %nop15800 = alloca i1, i1 0
-  %nop15801 = alloca i1, i1 0
-  %nop15802 = alloca i1, i1 0
-  %nop15803 = alloca i1, i1 0
-  %nop15804 = alloca i1, i1 0
-  %nop15805 = alloca i1, i1 0
-  %nop15806 = alloca i1, i1 0
-  %nop15807 = alloca i1, i1 0
-  %nop15808 = alloca i1, i1 0
-  %nop15809 = alloca i1, i1 0
-  %nop15810 = alloca i1, i1 0
-  %nop15811 = alloca i1, i1 0
-  %nop15812 = alloca i1, i1 0
-  %nop15813 = alloca i1, i1 0
-  %nop15814 = alloca i1, i1 0
-  %nop15815 = alloca i1, i1 0
-  %nop15816 = alloca i1, i1 0
-  %nop15817 = alloca i1, i1 0
-  %nop15818 = alloca i1, i1 0
-  %nop15819 = alloca i1, i1 0
-  %nop15820 = alloca i1, i1 0
-  %nop15821 = alloca i1, i1 0
-  %nop15822 = alloca i1, i1 0
-  %nop15823 = alloca i1, i1 0
-  %nop15824 = alloca i1, i1 0
-  %nop15825 = alloca i1, i1 0
-  %nop15826 = alloca i1, i1 0
-  %nop15827 = alloca i1, i1 0
-  %nop15828 = alloca i1, i1 0
-  %nop15829 = alloca i1, i1 0
-  %nop15830 = alloca i1, i1 0
-  %nop15831 = alloca i1, i1 0
-  %nop15832 = alloca i1, i1 0
-  %nop15833 = alloca i1, i1 0
-  %nop15834 = alloca i1, i1 0
-  %nop15835 = alloca i1, i1 0
-  %nop15836 = alloca i1, i1 0
-  %nop15837 = alloca i1, i1 0
-  %nop15838 = alloca i1, i1 0
-  %nop15839 = alloca i1, i1 0
-  %nop15840 = alloca i1, i1 0
-  %nop15841 = alloca i1, i1 0
-  %nop15842 = alloca i1, i1 0
-  %nop15843 = alloca i1, i1 0
-  %nop15844 = alloca i1, i1 0
-  %nop15845 = alloca i1, i1 0
-  %nop15846 = alloca i1, i1 0
-  %nop15847 = alloca i1, i1 0
-  %nop15848 = alloca i1, i1 0
-  %nop15849 = alloca i1, i1 0
-  %nop15850 = alloca i1, i1 0
-  %nop15851 = alloca i1, i1 0
-  %nop15852 = alloca i1, i1 0
-  %nop15853 = alloca i1, i1 0
-  %nop15854 = alloca i1, i1 0
-  %nop15855 = alloca i1, i1 0
-  %nop15856 = alloca i1, i1 0
-  %nop15857 = alloca i1, i1 0
-  %nop15858 = alloca i1, i1 0
-  %nop15859 = alloca i1, i1 0
-  %nop15860 = alloca i1, i1 0
-  %nop15861 = alloca i1, i1 0
-  %nop15862 = alloca i1, i1 0
-  %nop15863 = alloca i1, i1 0
-  %nop15864 = alloca i1, i1 0
-  %nop15865 = alloca i1, i1 0
-  %nop15866 = alloca i1, i1 0
-  %nop15867 = alloca i1, i1 0
-  %nop15868 = alloca i1, i1 0
-  %nop15869 = alloca i1, i1 0
-  %nop15870 = alloca i1, i1 0
-  %nop15871 = alloca i1, i1 0
-  %nop15872 = alloca i1, i1 0
-  %nop15873 = alloca i1, i1 0
-  %nop15874 = alloca i1, i1 0
-  %nop15875 = alloca i1, i1 0
-  %nop15876 = alloca i1, i1 0
-  %nop15877 = alloca i1, i1 0
-  %nop15878 = alloca i1, i1 0
-  %nop15879 = alloca i1, i1 0
-  %nop15880 = alloca i1, i1 0
-  %nop15881 = alloca i1, i1 0
-  %nop15882 = alloca i1, i1 0
-  %nop15883 = alloca i1, i1 0
-  %nop15884 = alloca i1, i1 0
-  %nop15885 = alloca i1, i1 0
-  %nop15886 = alloca i1, i1 0
-  %nop15887 = alloca i1, i1 0
-  %nop15888 = alloca i1, i1 0
-  %nop15889 = alloca i1, i1 0
-  %nop15890 = alloca i1, i1 0
-  %nop15891 = alloca i1, i1 0
-  %nop15892 = alloca i1, i1 0
-  %nop15893 = alloca i1, i1 0
-  %nop15894 = alloca i1, i1 0
-  %nop15895 = alloca i1, i1 0
-  %nop15896 = alloca i1, i1 0
-  %nop15897 = alloca i1, i1 0
-  %nop15898 = alloca i1, i1 0
-  %nop15899 = alloca i1, i1 0
-  %nop15900 = alloca i1, i1 0
-  %nop15901 = alloca i1, i1 0
-  %nop15902 = alloca i1, i1 0
-  %nop15903 = alloca i1, i1 0
-  %nop15904 = alloca i1, i1 0
-  %nop15905 = alloca i1, i1 0
-  %nop15906 = alloca i1, i1 0
-  %nop15907 = alloca i1, i1 0
-  %nop15908 = alloca i1, i1 0
-  %nop15909 = alloca i1, i1 0
-  %nop15910 = alloca i1, i1 0
-  %nop15911 = alloca i1, i1 0
-  %nop15912 = alloca i1, i1 0
-  %nop15913 = alloca i1, i1 0
-  %nop15914 = alloca i1, i1 0
-  %nop15915 = alloca i1, i1 0
-  %nop15916 = alloca i1, i1 0
-  %nop15917 = alloca i1, i1 0
-  %nop15918 = alloca i1, i1 0
-  %nop15919 = alloca i1, i1 0
-  %nop15920 = alloca i1, i1 0
-  %nop15921 = alloca i1, i1 0
-  %nop15922 = alloca i1, i1 0
-  %nop15923 = alloca i1, i1 0
-  %nop15924 = alloca i1, i1 0
-  %nop15925 = alloca i1, i1 0
-  %nop15926 = alloca i1, i1 0
-  %nop15927 = alloca i1, i1 0
-  %nop15928 = alloca i1, i1 0
-  %nop15929 = alloca i1, i1 0
-  %nop15930 = alloca i1, i1 0
-  %nop15931 = alloca i1, i1 0
-  %nop15932 = alloca i1, i1 0
-  %nop15933 = alloca i1, i1 0
-  %nop15934 = alloca i1, i1 0
-  %nop15935 = alloca i1, i1 0
-  %nop15936 = alloca i1, i1 0
-  %nop15937 = alloca i1, i1 0
-  %nop15938 = alloca i1, i1 0
-  %nop15939 = alloca i1, i1 0
-  %nop15940 = alloca i1, i1 0
-  %nop15941 = alloca i1, i1 0
-  %nop15942 = alloca i1, i1 0
-  %nop15943 = alloca i1, i1 0
-  %nop15944 = alloca i1, i1 0
-  %nop15945 = alloca i1, i1 0
-  %nop15946 = alloca i1, i1 0
-  %nop15947 = alloca i1, i1 0
-  %nop15948 = alloca i1, i1 0
-  %nop15949 = alloca i1, i1 0
-  %nop15950 = alloca i1, i1 0
-  %nop15951 = alloca i1, i1 0
-  %nop15952 = alloca i1, i1 0
-  %nop15953 = alloca i1, i1 0
-  %nop15954 = alloca i1, i1 0
-  %nop15955 = alloca i1, i1 0
-  %nop15956 = alloca i1, i1 0
-  %nop15957 = alloca i1, i1 0
-  %nop15958 = alloca i1, i1 0
-  %nop15959 = alloca i1, i1 0
-  %nop15960 = alloca i1, i1 0
-  %nop15961 = alloca i1, i1 0
-  %nop15962 = alloca i1, i1 0
-  %nop15963 = alloca i1, i1 0
-  %nop15964 = alloca i1, i1 0
-  %nop15965 = alloca i1, i1 0
-  %nop15966 = alloca i1, i1 0
-  %nop15967 = alloca i1, i1 0
-  %nop15968 = alloca i1, i1 0
-  %nop15969 = alloca i1, i1 0
-  %nop15970 = alloca i1, i1 0
-  %nop15971 = alloca i1, i1 0
-  %nop15972 = alloca i1, i1 0
-  %nop15973 = alloca i1, i1 0
-  %nop15974 = alloca i1, i1 0
-  %nop15975 = alloca i1, i1 0
-  %nop15976 = alloca i1, i1 0
-  %nop15977 = alloca i1, i1 0
-  %nop15978 = alloca i1, i1 0
-  %nop15979 = alloca i1, i1 0
-  %nop15980 = alloca i1, i1 0
-  %nop15981 = alloca i1, i1 0
-  %nop15982 = alloca i1, i1 0
-  %nop15983 = alloca i1, i1 0
-  %nop15984 = alloca i1, i1 0
-  %nop15985 = alloca i1, i1 0
-  %nop15986 = alloca i1, i1 0
-  %nop15987 = alloca i1, i1 0
-  %nop15988 = alloca i1, i1 0
-  %nop15989 = alloca i1, i1 0
-  %nop15990 = alloca i1, i1 0
-  %nop15991 = alloca i1, i1 0
-  %nop15992 = alloca i1, i1 0
-  %nop15993 = alloca i1, i1 0
-  %nop15994 = alloca i1, i1 0
-  %nop15995 = alloca i1, i1 0
-  %nop15996 = alloca i1, i1 0
-  %nop15997 = alloca i1, i1 0
-  %nop15998 = alloca i1, i1 0
-  %nop15999 = alloca i1, i1 0
-  %nop16000 = alloca i1, i1 0
-  %nop16001 = alloca i1, i1 0
-  %nop16002 = alloca i1, i1 0
-  %nop16003 = alloca i1, i1 0
-  %nop16004 = alloca i1, i1 0
-  %nop16005 = alloca i1, i1 0
-  %nop16006 = alloca i1, i1 0
-  %nop16007 = alloca i1, i1 0
-  %nop16008 = alloca i1, i1 0
-  %nop16009 = alloca i1, i1 0
-  %nop16010 = alloca i1, i1 0
-  %nop16011 = alloca i1, i1 0
-  %nop16012 = alloca i1, i1 0
-  %nop16013 = alloca i1, i1 0
-  %nop16014 = alloca i1, i1 0
-  %nop16015 = alloca i1, i1 0
-  %nop16016 = alloca i1, i1 0
-  %nop16017 = alloca i1, i1 0
-  %nop16018 = alloca i1, i1 0
-  %nop16019 = alloca i1, i1 0
-  %nop16020 = alloca i1, i1 0
-  %nop16021 = alloca i1, i1 0
-  %nop16022 = alloca i1, i1 0
-  %nop16023 = alloca i1, i1 0
-  %nop16024 = alloca i1, i1 0
-  %nop16025 = alloca i1, i1 0
-  %nop16026 = alloca i1, i1 0
-  %nop16027 = alloca i1, i1 0
-  %nop16028 = alloca i1, i1 0
-  %nop16029 = alloca i1, i1 0
-  %nop16030 = alloca i1, i1 0
-  %nop16031 = alloca i1, i1 0
-  %nop16032 = alloca i1, i1 0
-  %nop16033 = alloca i1, i1 0
-  %nop16034 = alloca i1, i1 0
-  %nop16035 = alloca i1, i1 0
-  %nop16036 = alloca i1, i1 0
-  %nop16037 = alloca i1, i1 0
-  %nop16038 = alloca i1, i1 0
-  %nop16039 = alloca i1, i1 0
-  %nop16040 = alloca i1, i1 0
-  %nop16041 = alloca i1, i1 0
-  %nop16042 = alloca i1, i1 0
-  %nop16043 = alloca i1, i1 0
-  %nop16044 = alloca i1, i1 0
-  %nop16045 = alloca i1, i1 0
-  %nop16046 = alloca i1, i1 0
-  %nop16047 = alloca i1, i1 0
-  %nop16048 = alloca i1, i1 0
-  %nop16049 = alloca i1, i1 0
-  %nop16050 = alloca i1, i1 0
-  %nop16051 = alloca i1, i1 0
-  %nop16052 = alloca i1, i1 0
-  %nop16053 = alloca i1, i1 0
-  %nop16054 = alloca i1, i1 0
-  %nop16055 = alloca i1, i1 0
-  %nop16056 = alloca i1, i1 0
-  %nop16057 = alloca i1, i1 0
-  %nop16058 = alloca i1, i1 0
-  %nop16059 = alloca i1, i1 0
-  %nop16060 = alloca i1, i1 0
-  %nop16061 = alloca i1, i1 0
-  %nop16062 = alloca i1, i1 0
-  %nop16063 = alloca i1, i1 0
-  %nop16064 = alloca i1, i1 0
-  %nop16065 = alloca i1, i1 0
-  %nop16066 = alloca i1, i1 0
-  %nop16067 = alloca i1, i1 0
-  %nop16068 = alloca i1, i1 0
-  %nop16069 = alloca i1, i1 0
-  %nop16070 = alloca i1, i1 0
-  %nop16071 = alloca i1, i1 0
-  %nop16072 = alloca i1, i1 0
-  %nop16073 = alloca i1, i1 0
-  %nop16074 = alloca i1, i1 0
-  %nop16075 = alloca i1, i1 0
-  %nop16076 = alloca i1, i1 0
-  %nop16077 = alloca i1, i1 0
-  %nop16078 = alloca i1, i1 0
-  %nop16079 = alloca i1, i1 0
-  %nop16080 = alloca i1, i1 0
-  %nop16081 = alloca i1, i1 0
-  %nop16082 = alloca i1, i1 0
-  %nop16083 = alloca i1, i1 0
-  %nop16084 = alloca i1, i1 0
-  %nop16085 = alloca i1, i1 0
-  %nop16086 = alloca i1, i1 0
-  %nop16087 = alloca i1, i1 0
-  %nop16088 = alloca i1, i1 0
-  %nop16089 = alloca i1, i1 0
-  %nop16090 = alloca i1, i1 0
-  %nop16091 = alloca i1, i1 0
-  %nop16092 = alloca i1, i1 0
-  %nop16093 = alloca i1, i1 0
-  %nop16094 = alloca i1, i1 0
-  %nop16095 = alloca i1, i1 0
-  %nop16096 = alloca i1, i1 0
-  %nop16097 = alloca i1, i1 0
-  %nop16098 = alloca i1, i1 0
-  %nop16099 = alloca i1, i1 0
-  %nop16100 = alloca i1, i1 0
-  %nop16101 = alloca i1, i1 0
-  %nop16102 = alloca i1, i1 0
-  %nop16103 = alloca i1, i1 0
-  %nop16104 = alloca i1, i1 0
-  %nop16105 = alloca i1, i1 0
-  %nop16106 = alloca i1, i1 0
-  %nop16107 = alloca i1, i1 0
-  %nop16108 = alloca i1, i1 0
-  %nop16109 = alloca i1, i1 0
-  %nop16110 = alloca i1, i1 0
-  %nop16111 = alloca i1, i1 0
-  %nop16112 = alloca i1, i1 0
-  %nop16113 = alloca i1, i1 0
-  %nop16114 = alloca i1, i1 0
-  %nop16115 = alloca i1, i1 0
-  %nop16116 = alloca i1, i1 0
-  %nop16117 = alloca i1, i1 0
-  %nop16118 = alloca i1, i1 0
-  %nop16119 = alloca i1, i1 0
-  %nop16120 = alloca i1, i1 0
-  %nop16121 = alloca i1, i1 0
-  %nop16122 = alloca i1, i1 0
-  %nop16123 = alloca i1, i1 0
-  %nop16124 = alloca i1, i1 0
-  %nop16125 = alloca i1, i1 0
-  %nop16126 = alloca i1, i1 0
-  %nop16127 = alloca i1, i1 0
-  %nop16128 = alloca i1, i1 0
-  %nop16129 = alloca i1, i1 0
-  %nop16130 = alloca i1, i1 0
-  %nop16131 = alloca i1, i1 0
-  %nop16132 = alloca i1, i1 0
-  %nop16133 = alloca i1, i1 0
-  %nop16134 = alloca i1, i1 0
-  %nop16135 = alloca i1, i1 0
-  %nop16136 = alloca i1, i1 0
-  %nop16137 = alloca i1, i1 0
-  %nop16138 = alloca i1, i1 0
-  %nop16139 = alloca i1, i1 0
-  %nop16140 = alloca i1, i1 0
-  %nop16141 = alloca i1, i1 0
-  %nop16142 = alloca i1, i1 0
-  %nop16143 = alloca i1, i1 0
-  %nop16144 = alloca i1, i1 0
-  %nop16145 = alloca i1, i1 0
-  %nop16146 = alloca i1, i1 0
-  %nop16147 = alloca i1, i1 0
-  %nop16148 = alloca i1, i1 0
-  %nop16149 = alloca i1, i1 0
-  %nop16150 = alloca i1, i1 0
-  %nop16151 = alloca i1, i1 0
-  %nop16152 = alloca i1, i1 0
-  %nop16153 = alloca i1, i1 0
-  %nop16154 = alloca i1, i1 0
-  %nop16155 = alloca i1, i1 0
-  %nop16156 = alloca i1, i1 0
-  %nop16157 = alloca i1, i1 0
-  %nop16158 = alloca i1, i1 0
-  %nop16159 = alloca i1, i1 0
-  %nop16160 = alloca i1, i1 0
-  %nop16161 = alloca i1, i1 0
-  %nop16162 = alloca i1, i1 0
-  %nop16163 = alloca i1, i1 0
-  %nop16164 = alloca i1, i1 0
-  %nop16165 = alloca i1, i1 0
-  %nop16166 = alloca i1, i1 0
-  %nop16167 = alloca i1, i1 0
-  %nop16168 = alloca i1, i1 0
-  %nop16169 = alloca i1, i1 0
-  %nop16170 = alloca i1, i1 0
-  %nop16171 = alloca i1, i1 0
-  %nop16172 = alloca i1, i1 0
-  %nop16173 = alloca i1, i1 0
-  %nop16174 = alloca i1, i1 0
-  %nop16175 = alloca i1, i1 0
-  %nop16176 = alloca i1, i1 0
-  %nop16177 = alloca i1, i1 0
-  %nop16178 = alloca i1, i1 0
-  %nop16179 = alloca i1, i1 0
-  %nop16180 = alloca i1, i1 0
-  %nop16181 = alloca i1, i1 0
-  %nop16182 = alloca i1, i1 0
-  %nop16183 = alloca i1, i1 0
-  %nop16184 = alloca i1, i1 0
-  %nop16185 = alloca i1, i1 0
-  %nop16186 = alloca i1, i1 0
-  %nop16187 = alloca i1, i1 0
-  %nop16188 = alloca i1, i1 0
-  %nop16189 = alloca i1, i1 0
-  %nop16190 = alloca i1, i1 0
-  %nop16191 = alloca i1, i1 0
-  %nop16192 = alloca i1, i1 0
-  %nop16193 = alloca i1, i1 0
-  %nop16194 = alloca i1, i1 0
-  %nop16195 = alloca i1, i1 0
-  %nop16196 = alloca i1, i1 0
-  %nop16197 = alloca i1, i1 0
-  %nop16198 = alloca i1, i1 0
-  %nop16199 = alloca i1, i1 0
-  %nop16200 = alloca i1, i1 0
-  %nop16201 = alloca i1, i1 0
-  %nop16202 = alloca i1, i1 0
-  %nop16203 = alloca i1, i1 0
-  %nop16204 = alloca i1, i1 0
-  %nop16205 = alloca i1, i1 0
-  %nop16206 = alloca i1, i1 0
-  %nop16207 = alloca i1, i1 0
-  %nop16208 = alloca i1, i1 0
-  %nop16209 = alloca i1, i1 0
-  %nop16210 = alloca i1, i1 0
-  %nop16211 = alloca i1, i1 0
-  %nop16212 = alloca i1, i1 0
-  %nop16213 = alloca i1, i1 0
-  %nop16214 = alloca i1, i1 0
-  %nop16215 = alloca i1, i1 0
-  %nop16216 = alloca i1, i1 0
-  %nop16217 = alloca i1, i1 0
-  %nop16218 = alloca i1, i1 0
-  %nop16219 = alloca i1, i1 0
-  %nop16220 = alloca i1, i1 0
-  %nop16221 = alloca i1, i1 0
-  %nop16222 = alloca i1, i1 0
-  %nop16223 = alloca i1, i1 0
-  %nop16224 = alloca i1, i1 0
-  %nop16225 = alloca i1, i1 0
-  %nop16226 = alloca i1, i1 0
-  %nop16227 = alloca i1, i1 0
-  %nop16228 = alloca i1, i1 0
-  %nop16229 = alloca i1, i1 0
-  %nop16230 = alloca i1, i1 0
-  %nop16231 = alloca i1, i1 0
-  %nop16232 = alloca i1, i1 0
-  %nop16233 = alloca i1, i1 0
-  %nop16234 = alloca i1, i1 0
-  %nop16235 = alloca i1, i1 0
-  %nop16236 = alloca i1, i1 0
-  %nop16237 = alloca i1, i1 0
-  %nop16238 = alloca i1, i1 0
-  %nop16239 = alloca i1, i1 0
-  %nop16240 = alloca i1, i1 0
-  %nop16241 = alloca i1, i1 0
-  %nop16242 = alloca i1, i1 0
-  %nop16243 = alloca i1, i1 0
-  %nop16244 = alloca i1, i1 0
-  %nop16245 = alloca i1, i1 0
-  %nop16246 = alloca i1, i1 0
-  %nop16247 = alloca i1, i1 0
-  %nop16248 = alloca i1, i1 0
-  %nop16249 = alloca i1, i1 0
-  %nop16250 = alloca i1, i1 0
-  %nop16251 = alloca i1, i1 0
-  %nop16252 = alloca i1, i1 0
-  %nop16253 = alloca i1, i1 0
-  %nop16254 = alloca i1, i1 0
-  %nop16255 = alloca i1, i1 0
-  %nop16256 = alloca i1, i1 0
-  %nop16257 = alloca i1, i1 0
-  %nop16258 = alloca i1, i1 0
-  %nop16259 = alloca i1, i1 0
-  %nop16260 = alloca i1, i1 0
-  %nop16261 = alloca i1, i1 0
-  %nop16262 = alloca i1, i1 0
-  %nop16263 = alloca i1, i1 0
-  %nop16264 = alloca i1, i1 0
-  %nop16265 = alloca i1, i1 0
-  %nop16266 = alloca i1, i1 0
-  %nop16267 = alloca i1, i1 0
-  %nop16268 = alloca i1, i1 0
-  %nop16269 = alloca i1, i1 0
-  %nop16270 = alloca i1, i1 0
-  %nop16271 = alloca i1, i1 0
-  %nop16272 = alloca i1, i1 0
-  %nop16273 = alloca i1, i1 0
-  %nop16274 = alloca i1, i1 0
-  %nop16275 = alloca i1, i1 0
-  %nop16276 = alloca i1, i1 0
-  %nop16277 = alloca i1, i1 0
-  %nop16278 = alloca i1, i1 0
-  %nop16279 = alloca i1, i1 0
-  %nop16280 = alloca i1, i1 0
-  %nop16281 = alloca i1, i1 0
-  %nop16282 = alloca i1, i1 0
-  %nop16283 = alloca i1, i1 0
-  %nop16284 = alloca i1, i1 0
-  %nop16285 = alloca i1, i1 0
-  %nop16286 = alloca i1, i1 0
-  %nop16287 = alloca i1, i1 0
-  %nop16288 = alloca i1, i1 0
-  %nop16289 = alloca i1, i1 0
-  %nop16290 = alloca i1, i1 0
-  %nop16291 = alloca i1, i1 0
-  %nop16292 = alloca i1, i1 0
-  %nop16293 = alloca i1, i1 0
-  %nop16294 = alloca i1, i1 0
-  %nop16295 = alloca i1, i1 0
-  %nop16296 = alloca i1, i1 0
-  %nop16297 = alloca i1, i1 0
-  %nop16298 = alloca i1, i1 0
-  %nop16299 = alloca i1, i1 0
-  %nop16300 = alloca i1, i1 0
-  %nop16301 = alloca i1, i1 0
-  %nop16302 = alloca i1, i1 0
-  %nop16303 = alloca i1, i1 0
-  %nop16304 = alloca i1, i1 0
-  %nop16305 = alloca i1, i1 0
-  %nop16306 = alloca i1, i1 0
-  %nop16307 = alloca i1, i1 0
-  %nop16308 = alloca i1, i1 0
-  %nop16309 = alloca i1, i1 0
-  %nop16310 = alloca i1, i1 0
-  %nop16311 = alloca i1, i1 0
-  %nop16312 = alloca i1, i1 0
-  %nop16313 = alloca i1, i1 0
-  %nop16314 = alloca i1, i1 0
-  %nop16315 = alloca i1, i1 0
-  %nop16316 = alloca i1, i1 0
-  %nop16317 = alloca i1, i1 0
-  %nop16318 = alloca i1, i1 0
-  %nop16319 = alloca i1, i1 0
-  %nop16320 = alloca i1, i1 0
-  %nop16321 = alloca i1, i1 0
-  %nop16322 = alloca i1, i1 0
-  %nop16323 = alloca i1, i1 0
-  %nop16324 = alloca i1, i1 0
-  %nop16325 = alloca i1, i1 0
-  %nop16326 = alloca i1, i1 0
-  %nop16327 = alloca i1, i1 0
-  %nop16328 = alloca i1, i1 0
-  %nop16329 = alloca i1, i1 0
-  %nop16330 = alloca i1, i1 0
-  %nop16331 = alloca i1, i1 0
-  %nop16332 = alloca i1, i1 0
-  %nop16333 = alloca i1, i1 0
-  %nop16334 = alloca i1, i1 0
-  %nop16335 = alloca i1, i1 0
-  %nop16336 = alloca i1, i1 0
-  %nop16337 = alloca i1, i1 0
-  %nop16338 = alloca i1, i1 0
-  %nop16339 = alloca i1, i1 0
-  %nop16340 = alloca i1, i1 0
-  %nop16341 = alloca i1, i1 0
-  %nop16342 = alloca i1, i1 0
-  %nop16343 = alloca i1, i1 0
-  %nop16344 = alloca i1, i1 0
-  %nop16345 = alloca i1, i1 0
-  %nop16346 = alloca i1, i1 0
-  %nop16347 = alloca i1, i1 0
-  %nop16348 = alloca i1, i1 0
-  %nop16349 = alloca i1, i1 0
-  %nop16350 = alloca i1, i1 0
-  %nop16351 = alloca i1, i1 0
-  %nop16352 = alloca i1, i1 0
-  %nop16353 = alloca i1, i1 0
-  %nop16354 = alloca i1, i1 0
-  %nop16355 = alloca i1, i1 0
-  %nop16356 = alloca i1, i1 0
-  %nop16357 = alloca i1, i1 0
-  %nop16358 = alloca i1, i1 0
-  %nop16359 = alloca i1, i1 0
-  %nop16360 = alloca i1, i1 0
-  %nop16361 = alloca i1, i1 0
-  %nop16362 = alloca i1, i1 0
-  %nop16363 = alloca i1, i1 0
-  %nop16364 = alloca i1, i1 0
-  %nop16365 = alloca i1, i1 0
-  %nop16366 = alloca i1, i1 0
-  %nop16367 = alloca i1, i1 0
-  %nop16368 = alloca i1, i1 0
-  %nop16369 = alloca i1, i1 0
-  %nop16370 = alloca i1, i1 0
-  %nop16371 = alloca i1, i1 0
-  %nop16372 = alloca i1, i1 0
-  %nop16373 = alloca i1, i1 0
-  %nop16374 = alloca i1, i1 0
-  %nop16375 = alloca i1, i1 0
-  %nop16376 = alloca i1, i1 0
-  %nop16377 = alloca i1, i1 0
-  br label %for.inc
-
-for.inc:
-  %3 = load i32* %i, align 4
-  %inc = add nsw i32 %3, 1
-  store i32 %inc, i32* %i, align 4
-  br label %for.cond
-
-; CHECK:  addiu $sp, $sp, -8
-; CHECK:  sw  $ra, 0($sp)
-; CHECK:  lui $[[REG1:[0-9]+]], 65534
-; CHECK:  addiu $[[REG1]], $[[REG1]], -12
-; CHECK:  addu  $[[REG1]], $ra, $[[REG1]]
-; CHECK:  lw  $ra, 0($sp)
-; CHECK:  jr  $[[REG1]]
-; CHECK:  addiu $sp, $sp, 8
-
-for.end:
-  ret i32 0
-}
-
-attributes #0 = { nounwind uwtable "less-precise-fpmad"="false"
-  "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf"
-  "no-infs-fp-math"="false" "no-nans-fp-math"="false"
-  "stack-protector-buffer-size"="8" "unsafe-fp-math"="false"
-  "use-soft-float"="false" }
diff --git a/test/CodeGen/Mips/msa/basic_operations.ll b/test/CodeGen/Mips/msa/basic_operations.ll
index 2725e9aac8..dbdf42be49 100644
--- a/test/CodeGen/Mips/msa/basic_operations.ll
+++ b/test/CodeGen/Mips/msa/basic_operations.ll
@@ -6,10 +6,11 @@
 @v8i16 = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>
 @v4i32 = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>
 @v2i64 = global <2 x i64> <i64 0, i64 0>
+@i32 = global i32 0
 @i64 = global i64 0
 
 define void @const_v16i8() nounwind {
-  ; MIPS32-AE: const_v16i8:
+  ; MIPS32-AE-LABEL: const_v16i8:
 
   store volatile <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, <16 x i8>*@v16i8
   ; MIPS32-AE: ldi.b [[R1:\$w[0-9]+]], 0
@@ -45,7 +46,7 @@ define void @const_v16i8() nounwind {
 }
 
 define void @const_v8i16() nounwind {
-  ; MIPS32-AE: const_v8i16:
+  ; MIPS32-AE-LABEL: const_v8i16:
 
   store volatile <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, <8 x i16>*@v8i16
   ; MIPS32-AE: ldi.b [[R1:\$w[0-9]+]], 0
@@ -76,7 +77,7 @@ define void @const_v8i16() nounwind {
 }
 
 define void @const_v4i32() nounwind {
-  ; MIPS32-AE: const_v4i32:
+  ; MIPS32-AE-LABEL: const_v4i32:
 
   store volatile <4 x i32> <i32 0, i32 0, i32 0, i32 0>, <4 x i32>*@v4i32
   ; MIPS32-AE: ldi.b [[R1:\$w[0-9]+]], 0
@@ -107,7 +108,7 @@ define void @const_v4i32() nounwind {
 }
 
 define void @const_v2i64() nounwind {
-  ; MIPS32-AE: const_v2i64:
+  ; MIPS32-AE-LABEL: const_v2i64:
 
   store volatile <2 x i64> <i64 0, i64 0>, <2 x i64>*@v2i64
   ; MIPS32-AE: ldi.b [[R1:\$w[0-9]+]], 0
@@ -137,7 +138,7 @@ define void @const_v2i64() nounwind {
 }
 
 define void @nonconst_v16i8(i8 %a, i8 %b, i8 %c, i8 %d, i8 %e, i8 %f, i8 %g, i8 %h) nounwind {
-  ; MIPS32-AE: nonconst_v16i8:
+  ; MIPS32-AE-LABEL: nonconst_v16i8:
 
   %1 = insertelement <16 x i8> undef, i8 %a, i32 0
   %2 = insertelement <16 x i8> %1, i8 %b, i32 1
@@ -187,7 +188,7 @@ define void @nonconst_v16i8(i8 %a, i8 %b, i8 %c, i8 %d, i8 %e, i8 %f, i8 %g, i8
 }
 
 define void @nonconst_v8i16(i16 %a, i16 %b, i16 %c, i16 %d, i16 %e, i16 %f, i16 %g, i16 %h) nounwind {
-  ; MIPS32-AE: nonconst_v8i16:
+  ; MIPS32-AE-LABEL: nonconst_v8i16:
 
   %1 = insertelement <8 x i16> undef, i16 %a, i32 0
   %2 = insertelement <8 x i16> %1, i16 %b, i32 1
@@ -221,7 +222,7 @@ define void @nonconst_v8i16(i16 %a, i16 %b, i16 %c, i16 %d, i16 %e, i16 %f, i16
 }
 
 define void @nonconst_v4i32(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
-  ; MIPS32-AE: nonconst_v4i32:
+  ; MIPS32-AE-LABEL: nonconst_v4i32:
 
   %1 = insertelement <4 x i32> undef, i32 %a, i32 0
   %2 = insertelement <4 x i32> %1, i32 %b, i32 1
@@ -239,7 +240,7 @@ define void @nonconst_v4i32(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
 }
 
 define void @nonconst_v2i64(i64 %a, i64 %b) nounwind {
-  ; MIPS32-AE: nonconst_v2i64:
+  ; MIPS32-AE-LABEL: nonconst_v2i64:
 
   %1 = insertelement <2 x i64> undef, i64 %a, i32 0
   %2 = insertelement <2 x i64> %1, i64 %b, i32 1
@@ -255,7 +256,7 @@ define void @nonconst_v2i64(i64 %a, i64 %b) nounwind {
 }
 
 define i32 @extract_sext_v16i8() nounwind {
-  ; MIPS32-AE: extract_sext_v16i8:
+  ; MIPS32-AE-LABEL: extract_sext_v16i8:
 
   %1 = load <16 x i8>* @v16i8
   ; MIPS32-AE-DAG: ld.b [[R1:\$w[0-9]+]],
@@ -274,7 +275,7 @@ define i32 @extract_sext_v16i8() nounwind {
 }
 
 define i32 @extract_sext_v8i16() nounwind {
-  ; MIPS32-AE: extract_sext_v8i16:
+  ; MIPS32-AE-LABEL: extract_sext_v8i16:
 
   %1 = load <8 x i16>* @v8i16
   ; MIPS32-AE-DAG: ld.h [[R1:\$w[0-9]+]],
@@ -293,7 +294,7 @@ define i32 @extract_sext_v8i16() nounwind {
 }
 
 define i32 @extract_sext_v4i32() nounwind {
-  ; MIPS32-AE: extract_sext_v4i32:
+  ; MIPS32-AE-LABEL: extract_sext_v4i32:
 
   %1 = load <4 x i32>* @v4i32
   ; MIPS32-AE-DAG: ld.w [[R1:\$w[0-9]+]],
@@ -309,7 +310,7 @@ define i32 @extract_sext_v4i32() nounwind {
 }
 
 define i64 @extract_sext_v2i64() nounwind {
-  ; MIPS32-AE: extract_sext_v2i64:
+  ; MIPS32-AE-LABEL: extract_sext_v2i64:
 
   %1 = load <2 x i64>* @v2i64
   ; MIPS32-AE-DAG: ld.d [[R1:\$w[0-9]+]],
@@ -328,7 +329,7 @@ define i64 @extract_sext_v2i64() nounwind {
 }
 
 define i32 @extract_zext_v16i8() nounwind {
-  ; MIPS32-AE: extract_zext_v16i8:
+  ; MIPS32-AE-LABEL: extract_zext_v16i8:
 
   %1 = load <16 x i8>* @v16i8
   ; MIPS32-AE-DAG: ld.b [[R1:\$w[0-9]+]],
@@ -346,7 +347,7 @@ define i32 @extract_zext_v16i8() nounwind {
 }
 
 define i32 @extract_zext_v8i16() nounwind {
-  ; MIPS32-AE: extract_zext_v8i16:
+  ; MIPS32-AE-LABEL: extract_zext_v8i16:
 
   %1 = load <8 x i16>* @v8i16
   ; MIPS32-AE-DAG: ld.h [[R1:\$w[0-9]+]],
@@ -364,7 +365,7 @@ define i32 @extract_zext_v8i16() nounwind {
 }
 
 define i32 @extract_zext_v4i32() nounwind {
-  ; MIPS32-AE: extract_zext_v4i32:
+  ; MIPS32-AE-LABEL: extract_zext_v4i32:
 
   %1 = load <4 x i32>* @v4i32
   ; MIPS32-AE-DAG: ld.w [[R1:\$w[0-9]+]],
@@ -380,7 +381,7 @@ define i32 @extract_zext_v4i32() nounwind {
 }
 
 define i64 @extract_zext_v2i64() nounwind {
-  ; MIPS32-AE: extract_zext_v2i64:
+  ; MIPS32-AE-LABEL: extract_zext_v2i64:
 
   %1 = load <2 x i64>* @v2i64
   ; MIPS32-AE-DAG: ld.d [[R1:\$w[0-9]+]],
@@ -397,8 +398,200 @@ define i64 @extract_zext_v2i64() nounwind {
   ; MIPS32-AE: .size extract_zext_v2i64
 }
 
+define i32 @extract_sext_v16i8_vidx() nounwind {
+  ; MIPS32-AE-LABEL: extract_sext_v16i8_vidx:
+
+  %1 = load <16 x i8>* @v16i8
+  ; MIPS32-AE-DAG: lw [[PTR_V:\$[0-9]+]], %got(v16i8)(
+  ; MIPS32-AE-DAG: ld.b [[R1:\$w[0-9]+]], 0([[PTR_V]])
+
+  %2 = add <16 x i8> %1, %1
+  ; MIPS32-AE-DAG: addv.b [[R2:\$w[0-9]+]], [[R1]], [[R1]]
+
+  %3 = load i32* @i32
+  ; MIPS32-AE-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)(
+  ; MIPS32-AE-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]])
+
+  %4 = extractelement <16 x i8> %2, i32 %3
+  %5 = sext i8 %4 to i32
+  ; MIPS32-AE-DAG: splat.b $w[[R3:[0-9]+]], [[R1]]{{\[}}[[IDX]]]
+  ; MIPS32-AE-DAG: mfc1 [[R5:\$[0-9]+]], $f[[R3]]
+  ; MIPS32-AE-DAG: sra [[R6:\$[0-9]+]], [[R5]], 24
+
+  ret i32 %5
+  ; MIPS32-AE: .size extract_sext_v16i8_vidx
+}
+
+define i32 @extract_sext_v8i16_vidx() nounwind {
+  ; MIPS32-AE-LABEL: extract_sext_v8i16_vidx:
+
+  %1 = load <8 x i16>* @v8i16
+  ; MIPS32-AE-DAG: lw [[PTR_V:\$[0-9]+]], %got(v8i16)(
+  ; MIPS32-AE-DAG: ld.h [[R1:\$w[0-9]+]], 0([[PTR_V]])
+
+  %2 = add <8 x i16> %1, %1
+  ; MIPS32-AE-DAG: addv.h [[R2:\$w[0-9]+]], [[R1]], [[R1]]
+
+  %3 = load i32* @i32
+  ; MIPS32-AE-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)(
+  ; MIPS32-AE-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]])
+
+  %4 = extractelement <8 x i16> %2, i32 %3
+  %5 = sext i16 %4 to i32
+  ; MIPS32-AE-DAG: splat.h $w[[R3:[0-9]+]], [[R1]]{{\[}}[[IDX]]]
+  ; MIPS32-AE-DAG: mfc1 [[R5:\$[0-9]+]], $f[[R3]]
+  ; MIPS32-AE-DAG: sra [[R6:\$[0-9]+]], [[R5]], 16
+
+  ret i32 %5
+  ; MIPS32-AE: .size extract_sext_v8i16_vidx
+}
+
+define i32 @extract_sext_v4i32_vidx() nounwind {
+  ; MIPS32-AE-LABEL: extract_sext_v4i32_vidx:
+
+  %1 = load <4 x i32>* @v4i32
+  ; MIPS32-AE-DAG: lw [[PTR_V:\$[0-9]+]], %got(v4i32)(
+  ; MIPS32-AE-DAG: ld.w [[R1:\$w[0-9]+]], 0([[PTR_V]])
+
+  %2 = add <4 x i32> %1, %1
+  ; MIPS32-AE-DAG: addv.w [[R2:\$w[0-9]+]], [[R1]], [[R1]]
+
+  %3 = load i32* @i32
+  ; MIPS32-AE-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)(
+  ; MIPS32-AE-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]])
+
+  %4 = extractelement <4 x i32> %2, i32 %3
+  ; MIPS32-AE-DAG: splat.w $w[[R3:[0-9]+]], [[R1]]{{\[}}[[IDX]]]
+  ; MIPS32-AE-DAG: mfc1 [[R5:\$[0-9]+]], $f[[R3]]
+  ; MIPS32-AE-NOT: sra
+
+  ret i32 %4
+  ; MIPS32-AE: .size extract_sext_v4i32_vidx
+}
+
+define i64 @extract_sext_v2i64_vidx() nounwind {
+  ; MIPS32-AE-LABEL: extract_sext_v2i64_vidx:
+
+  %1 = load <2 x i64>* @v2i64
+  ; MIPS32-AE-DAG: lw [[PTR_V:\$[0-9]+]], %got(v2i64)(
+  ; MIPS32-AE-DAG: ld.d [[R1:\$w[0-9]+]], 0([[PTR_V]])
+
+  %2 = add <2 x i64> %1, %1
+  ; MIPS32-AE-DAG: addv.d [[R2:\$w[0-9]+]], [[R1]], [[R1]]
+
+  %3 = load i32* @i32
+  ; MIPS32-AE-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)(
+  ; MIPS32-AE-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]])
+
+  %4 = extractelement <2 x i64> %2, i32 %3
+  ; MIPS32-AE-DAG: splat.w $w[[R3:[0-9]+]], [[R1]]{{\[}}[[IDX]]]
+  ; MIPS32-AE-DAG: mfc1 [[R5:\$[0-9]+]], $f[[R3]]
+  ; MIPS32-AE-DAG: splat.w $w[[R4:[0-9]+]], [[R1]]{{\[}}[[IDX]]]
+  ; MIPS32-AE-DAG: mfc1 [[R6:\$[0-9]+]], $f[[R4]]
+  ; MIPS32-AE-NOT: sra
+
+  ret i64 %4
+  ; MIPS32-AE: .size extract_sext_v2i64_vidx
+}
+
+define i32 @extract_zext_v16i8_vidx() nounwind {
+  ; MIPS32-AE-LABEL: extract_zext_v16i8_vidx:
+
+  %1 = load <16 x i8>* @v16i8
+  ; MIPS32-AE-DAG: lw [[PTR_V:\$[0-9]+]], %got(v16i8)(
+  ; MIPS32-AE-DAG: ld.b [[R1:\$w[0-9]+]], 0([[PTR_V]])
+
+  %2 = add <16 x i8> %1, %1
+  ; MIPS32-AE-DAG: addv.b [[R2:\$w[0-9]+]], [[R1]], [[R1]]
+
+  %3 = load i32* @i32
+  ; MIPS32-AE-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)(
+  ; MIPS32-AE-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]])
+
+  %4 = extractelement <16 x i8> %2, i32 %3
+  %5 = zext i8 %4 to i32
+  ; MIPS32-AE-DAG: splat.b $w[[R3:[0-9]+]], [[R1]]{{\[}}[[IDX]]]
+  ; MIPS32-AE-DAG: mfc1 [[R5:\$[0-9]+]], $f[[R3]]
+  ; MIPS32-AE-DAG: srl [[R6:\$[0-9]+]], [[R5]], 24
+
+  ret i32 %5
+  ; MIPS32-AE: .size extract_zext_v16i8_vidx
+}
+
+define i32 @extract_zext_v8i16_vidx() nounwind {
+  ; MIPS32-AE-LABEL: extract_zext_v8i16_vidx:
+
+  %1 = load <8 x i16>* @v8i16
+  ; MIPS32-AE-DAG: lw [[PTR_V:\$[0-9]+]], %got(v8i16)(
+  ; MIPS32-AE-DAG: ld.h [[R1:\$w[0-9]+]], 0([[PTR_V]])
+
+  %2 = add <8 x i16> %1, %1
+  ; MIPS32-AE-DAG: addv.h [[R2:\$w[0-9]+]], [[R1]], [[R1]]
+
+  %3 = load i32* @i32
+  ; MIPS32-AE-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)(
+  ; MIPS32-AE-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]])
+
+  %4 = extractelement <8 x i16> %2, i32 %3
+  %5 = zext i16 %4 to i32
+  ; MIPS32-AE-DAG: splat.h $w[[R3:[0-9]+]], [[R1]]{{\[}}[[IDX]]]
+  ; MIPS32-AE-DAG: mfc1 [[R5:\$[0-9]+]], $f[[R3]]
+  ; MIPS32-AE-DAG: srl [[R6:\$[0-9]+]], [[R5]], 16
+
+  ret i32 %5
+  ; MIPS32-AE: .size extract_zext_v8i16_vidx
+}
+
+define i32 @extract_zext_v4i32_vidx() nounwind {
+  ; MIPS32-AE-LABEL: extract_zext_v4i32_vidx:
+
+  %1 = load <4 x i32>* @v4i32
+  ; MIPS32-AE-DAG: lw [[PTR_V:\$[0-9]+]], %got(v4i32)(
+  ; MIPS32-AE-DAG: ld.w [[R1:\$w[0-9]+]], 0([[PTR_V]])
+
+  %2 = add <4 x i32> %1, %1
+  ; MIPS32-AE-DAG: addv.w [[R2:\$w[0-9]+]], [[R1]], [[R1]]
+
+  %3 = load i32* @i32
+  ; MIPS32-AE-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)(
+  ; MIPS32-AE-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]])
+
+  %4 = extractelement <4 x i32> %2, i32 %3
+  ; MIPS32-AE-DAG: splat.w $w[[R3:[0-9]+]], [[R1]]{{\[}}[[IDX]]]
+  ; MIPS32-AE-DAG: mfc1 [[R5:\$[0-9]+]], $f[[R3]]
+  ; MIPS32-AE-NOT: srl
+
+  ret i32 %4
+  ; MIPS32-AE: .size extract_zext_v4i32_vidx
+}
+
+define i64 @extract_zext_v2i64_vidx() nounwind {
+  ; MIPS32-AE-LABEL: extract_zext_v2i64_vidx:
+
+  %1 = load <2 x i64>* @v2i64
+  ; MIPS32-AE-DAG: lw [[PTR_V:\$[0-9]+]], %got(v2i64)(
+  ; MIPS32-AE-DAG: ld.d [[R1:\$w[0-9]+]], 0([[PTR_V]])
+
+  %2 = add <2 x i64> %1, %1
+  ; MIPS32-AE-DAG: addv.d [[R2:\$w[0-9]+]], [[R1]], [[R1]]
+
+  %3 = load i32* @i32
+  ; MIPS32-AE-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)(
+  ; MIPS32-AE-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]])
+
+  %4 = extractelement <2 x i64> %2, i32 %3
+  ; MIPS32-AE-DAG: splat.w $w[[R3:[0-9]+]], [[R1]]{{\[}}[[IDX]]]
+  ; MIPS32-AE-DAG: mfc1 [[R5:\$[0-9]+]], $f[[R3]]
+  ; MIPS32-AE-DAG: splat.w $w[[R4:[0-9]+]], [[R1]]{{\[}}[[IDX]]]
+  ; MIPS32-AE-DAG: mfc1 [[R6:\$[0-9]+]], $f[[R4]]
+  ; MIPS32-AE-NOT: srl
+
+  ret i64 %4
+  ; MIPS32-AE: .size extract_zext_v2i64_vidx
+}
+
 define void @insert_v16i8(i32 %a) nounwind {
-  ; MIPS32-AE: insert_v16i8:
+  ; MIPS32-AE-LABEL: insert_v16i8:
 
   %1 = load <16 x i8>* @v16i8
   ; MIPS32-AE-DAG: ld.b [[R1:\$w[0-9]+]],
@@ -420,7 +613,7 @@ define void @insert_v16i8(i32 %a) nounwind {
 }
 
 define void @insert_v8i16(i32 %a) nounwind {
-  ; MIPS32-AE: insert_v8i16:
+  ; MIPS32-AE-LABEL: insert_v8i16:
 
   %1 = load <8 x i16>* @v8i16
   ; MIPS32-AE-DAG: ld.h [[R1:\$w[0-9]+]],
@@ -442,7 +635,7 @@ define void @insert_v8i16(i32 %a) nounwind {
 }
 
 define void @insert_v4i32(i32 %a) nounwind {
-  ; MIPS32-AE: insert_v4i32:
+  ; MIPS32-AE-LABEL: insert_v4i32:
 
   %1 = load <4 x i32>* @v4i32
   ; MIPS32-AE-DAG: ld.w [[R1:\$w[0-9]+]],
@@ -461,7 +654,7 @@ define void @insert_v4i32(i32 %a) nounwind {
 }
 
 define void @insert_v2i64(i64 %a) nounwind {
-  ; MIPS32-AE: insert_v2i64:
+  ; MIPS32-AE-LABEL: insert_v2i64:
 
   %1 = load <2 x i64>* @v2i64
   ; MIPS32-AE-DAG: ld.w [[R1:\$w[0-9]+]],
@@ -480,8 +673,131 @@ define void @insert_v2i64(i64 %a) nounwind {
   ; MIPS32-AE: .size insert_v2i64
 }
 
+define void @insert_v16i8_vidx(i32 %a) nounwind {
+  ; MIPS32-AE: insert_v16i8_vidx:
+
+  %1 = load <16 x i8>* @v16i8
+  ; MIPS32-AE-DAG: ld.b [[R1:\$w[0-9]+]],
+
+  %2 = load i32* @i32
+  ; MIPS32-AE-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)(
+  ; MIPS32-AE-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]])
+
+  %a2 = trunc i32 %a to i8
+  %a3 = sext i8 %a2 to i32
+  %a4 = trunc i32 %a3 to i8
+  ; MIPS32-AE-NOT: andi
+  ; MIPS32-AE-NOT: sra
+
+  %3 = insertelement <16 x i8> %1, i8 %a4, i32 %2
+  ; MIPS32-AE-DAG: sld.b [[R1]], [[R1]]{{\[}}[[IDX]]]
+  ; MIPS32-AE-DAG: insert.b [[R1]][0], $4
+  ; MIPS32-AE-DAG: neg [[NIDX:\$[0-9]+]], [[IDX]]
+  ; MIPS32-AE-DAG: sld.b [[R1]], [[R1]]{{\[}}[[NIDX]]]
+
+  store <16 x i8> %3, <16 x i8>* @v16i8
+  ; MIPS32-AE-DAG: st.b [[R1]]
+
+  ret void
+  ; MIPS32-AE: .size insert_v16i8_vidx
+}
+
+define void @insert_v8i16_vidx(i32 %a) nounwind {
+  ; MIPS32-AE: insert_v8i16_vidx:
+
+  %1 = load <8 x i16>* @v8i16
+  ; MIPS32-AE-DAG: ld.h [[R1:\$w[0-9]+]],
+
+  %2 = load i32* @i32
+  ; MIPS32-AE-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)(
+  ; MIPS32-AE-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]])
+
+  %a2 = trunc i32 %a to i16
+  %a3 = sext i16 %a2 to i32
+  %a4 = trunc i32 %a3 to i16
+  ; MIPS32-AE-NOT: andi
+  ; MIPS32-AE-NOT: sra
+
+  %3 = insertelement <8 x i16> %1, i16 %a4, i32 %2
+  ; MIPS32-AE-DAG: sll [[BIDX:\$[0-9]+]], [[IDX]], 1
+  ; MIPS32-AE-DAG: sld.b [[R1]], [[R1]]{{\[}}[[BIDX]]]
+  ; MIPS32-AE-DAG: insert.h [[R1]][0], $4
+  ; MIPS32-AE-DAG: neg [[NIDX:\$[0-9]+]], [[BIDX]]
+  ; MIPS32-AE-DAG: sld.b [[R1]], [[R1]]{{\[}}[[NIDX]]]
+
+  store <8 x i16> %3, <8 x i16>* @v8i16
+  ; MIPS32-AE-DAG: st.h [[R1]]
+
+  ret void
+  ; MIPS32-AE: .size insert_v8i16_vidx
+}
+
+define void @insert_v4i32_vidx(i32 %a) nounwind {
+  ; MIPS32-AE: insert_v4i32_vidx:
+
+  %1 = load <4 x i32>* @v4i32
+  ; MIPS32-AE-DAG: ld.w [[R1:\$w[0-9]+]],
+
+  %2 = load i32* @i32
+  ; MIPS32-AE-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)(
+  ; MIPS32-AE-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]])
+
+  ; MIPS32-AE-NOT: andi
+  ; MIPS32-AE-NOT: sra
+
+  %3 = insertelement <4 x i32> %1, i32 %a, i32 %2
+  ; MIPS32-AE-DAG: sll [[BIDX:\$[0-9]+]], [[IDX]], 2
+  ; MIPS32-AE-DAG: sld.b [[R1]], [[R1]]{{\[}}[[BIDX]]]
+  ; MIPS32-AE-DAG: insert.w [[R1]][0], $4
+  ; MIPS32-AE-DAG: neg [[NIDX:\$[0-9]+]], [[BIDX]]
+  ; MIPS32-AE-DAG: sld.b [[R1]], [[R1]]{{\[}}[[NIDX]]]
+
+  store <4 x i32> %3, <4 x i32>* @v4i32
+  ; MIPS32-AE-DAG: st.w [[R1]]
+
+  ret void
+  ; MIPS32-AE: .size insert_v4i32_vidx
+}
+
+define void @insert_v2i64_vidx(i64 %a) nounwind {
+  ; MIPS32-AE: insert_v2i64_vidx:
+
+  %1 = load <2 x i64>* @v2i64
+  ; MIPS32-AE-DAG: ld.w [[R1:\$w[0-9]+]],
+
+  %2 = load i32* @i32
+  ; MIPS32-AE-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)(
+  ; MIPS32-AE-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]])
+
+  ; MIPS32-AE-NOT: andi
+  ; MIPS32-AE-NOT: sra
+
+  %3 = insertelement <2 x i64> %1, i64 %a, i32 %2
+  ; TODO: This code could be a lot better but it works. The legalizer splits
+  ; 64-bit inserts into two 32-bit inserts because there is no i64 type on
+  ; MIPS32. The obvious optimisation is to perform both insert.w's at once while
+  ; the vector is rotated.
+  ; MIPS32-AE-DAG: sll [[BIDX:\$[0-9]+]], [[IDX]], 2
+  ; MIPS32-AE-DAG: sld.b [[R1]], [[R1]]{{\[}}[[BIDX]]]
+  ; MIPS32-AE-DAG: insert.w [[R1]][0], $4
+  ; MIPS32-AE-DAG: neg [[NIDX:\$[0-9]+]], [[BIDX]]
+  ; MIPS32-AE-DAG: sld.b [[R1]], [[R1]]{{\[}}[[NIDX]]]
+  ; MIPS32-AE-DAG: addiu [[IDX2:\$[0-9]+]], [[IDX]], 1
+  ; MIPS32-AE-DAG: sll [[BIDX:\$[0-9]+]], [[IDX2]], 2
+  ; MIPS32-AE-DAG: sld.b [[R1]], [[R1]]{{\[}}[[BIDX]]]
+  ; MIPS32-AE-DAG: insert.w [[R1]][0], $5
+  ; MIPS32-AE-DAG: neg [[NIDX:\$[0-9]+]], [[BIDX]]
+  ; MIPS32-AE-DAG: sld.b [[R1]], [[R1]]{{\[}}[[NIDX]]]
+
+  store <2 x i64> %3, <2 x i64>* @v2i64
+  ; MIPS32-AE-DAG: st.w [[R1]]
+
+  ret void
+  ; MIPS32-AE: .size insert_v2i64_vidx
+}
+
 define void @truncstore() nounwind {
-  ; MIPS32-AE: truncstore:
+  ; MIPS32-AE-LABEL: truncstore:
 
   store volatile <4 x i8> <i8 -1, i8 -1, i8 -1, i8 -1>, <4 x i8>*@v4i8
   ; TODO: What code should be emitted?
diff --git a/test/CodeGen/Mips/msa/basic_operations_float.ll b/test/CodeGen/Mips/msa/basic_operations_float.ll
index c8cef44909..a0c9d29e23 100644
--- a/test/CodeGen/Mips/msa/basic_operations_float.ll
+++ b/test/CodeGen/Mips/msa/basic_operations_float.ll
@@ -3,11 +3,12 @@
 
 @v4f32 = global <4 x float> <float 0.0, float 0.0, float 0.0, float 0.0>
 @v2f64 = global <2 x double> <double 0.0, double 0.0>
+@i32 = global i32 0
 @f32 = global float 0.0
 @f64 = global double 0.0
 
 define void @const_v4f32() nounwind {
-  ; MIPS32: const_v4f32:
+  ; MIPS32-LABEL: const_v4f32:
 
   store volatile <4 x float> <float 0.0, float 0.0, float 0.0, float 0.0>, <4 x float>*@v4f32
   ; MIPS32: ldi.b  [[R1:\$w[0-9]+]], 0
@@ -38,7 +39,7 @@ define void @const_v4f32() nounwind {
 }
 
 define void @const_v2f64() nounwind {
-  ; MIPS32: const_v2f64:
+  ; MIPS32-LABEL: const_v2f64:
 
   store volatile <2 x double> <double 0.0, double 0.0>, <2 x double>*@v2f64
   ; MIPS32: ldi.b  [[R1:\$w[0-9]+]], 0
@@ -72,7 +73,7 @@ define void @const_v2f64() nounwind {
 }
 
 define void @nonconst_v4f32() nounwind {
-  ; MIPS32: nonconst_v4f32:
+  ; MIPS32-LABEL: nonconst_v4f32:
 
   %1 = load float *@f32
   %2 = insertelement <4 x float> undef, float %1, i32 0
@@ -88,7 +89,7 @@ define void @nonconst_v4f32() nounwind {
 }
 
 define void @nonconst_v2f64() nounwind {
-  ; MIPS32: nonconst_v2f64:
+  ; MIPS32-LABEL: nonconst_v2f64:
 
   %1 = load double *@f64
   %2 = insertelement <2 x double> undef, double %1, i32 0
@@ -102,7 +103,7 @@ define void @nonconst_v2f64() nounwind {
 }
 
 define float @extract_v4f32() nounwind {
-  ; MIPS32: extract_v4f32:
+  ; MIPS32-LABEL: extract_v4f32:
 
   %1 = load <4 x float>* @v4f32
   ; MIPS32-DAG: ld.w [[R1:\$w[0-9]+]],
@@ -120,7 +121,7 @@ define float @extract_v4f32() nounwind {
 }
 
 define float @extract_v4f32_elt0() nounwind {
-  ; MIPS32: extract_v4f32_elt0:
+  ; MIPS32-LABEL: extract_v4f32_elt0:
 
   %1 = load <4 x float>* @v4f32
   ; MIPS32-DAG: ld.w [[R1:\$w[0-9]+]],
@@ -138,7 +139,7 @@ define float @extract_v4f32_elt0() nounwind {
 }
 
 define float @extract_v4f32_elt2() nounwind {
-  ; MIPS32: extract_v4f32_elt2:
+  ; MIPS32-LABEL: extract_v4f32_elt2:
 
   %1 = load <4 x float>* @v4f32
   ; MIPS32-DAG: ld.w [[R1:\$w[0-9]+]],
@@ -155,8 +156,29 @@ define float @extract_v4f32_elt2() nounwind {
   ; MIPS32: .size extract_v4f32_elt2
 }
 
+define float @extract_v4f32_vidx() nounwind {
+  ; MIPS32-LABEL: extract_v4f32_vidx:
+
+  %1 = load <4 x float>* @v4f32
+  ; MIPS32-DAG: lw [[PTR_V:\$[0-9]+]], %got(v4f32)(
+  ; MIPS32-DAG: ld.w [[R1:\$w[0-9]+]], 0([[PTR_V]])
+
+  %2 = fadd <4 x float> %1, %1
+  ; MIPS32-DAG: fadd.w [[R2:\$w[0-9]+]], [[R1]], [[R1]]
+
+  %3 = load i32* @i32
+  ; MIPS32-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)(
+  ; MIPS32-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]])
+
+  %4 = extractelement <4 x float> %2, i32 %3
+  ; MIPS32-DAG: splat.w $w0, [[R1]]{{\[}}[[IDX]]]
+
+  ret float %4
+  ; MIPS32: .size extract_v4f32_vidx
+}
+
 define double @extract_v2f64() nounwind {
-  ; MIPS32: extract_v2f64:
+  ; MIPS32-LABEL: extract_v2f64:
 
   %1 = load <2 x double>* @v2f64
   ; MIPS32-DAG: ld.d [[R1:\$w[0-9]+]],
@@ -179,7 +201,7 @@ define double @extract_v2f64() nounwind {
 }
 
 define double @extract_v2f64_elt0() nounwind {
-  ; MIPS32: extract_v2f64_elt0:
+  ; MIPS32-LABEL: extract_v2f64_elt0:
 
   %1 = load <2 x double>* @v2f64
   ; MIPS32-DAG: ld.d [[R1:\$w[0-9]+]],
@@ -199,8 +221,29 @@ define double @extract_v2f64_elt0() nounwind {
   ; MIPS32: .size extract_v2f64_elt0
 }
 
+define double @extract_v2f64_vidx() nounwind {
+  ; MIPS32-LABEL: extract_v2f64_vidx:
+
+  %1 = load <2 x double>* @v2f64
+  ; MIPS32-DAG: lw [[PTR_V:\$[0-9]+]], %got(v2f64)(
+  ; MIPS32-DAG: ld.d [[R1:\$w[0-9]+]], 0([[PTR_V]])
+
+  %2 = fadd <2 x double> %1, %1
+  ; MIPS32-DAG: fadd.d [[R2:\$w[0-9]+]], [[R1]], [[R1]]
+
+  %3 = load i32* @i32
+  ; MIPS32-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)(
+  ; MIPS32-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]])
+
+  %4 = extractelement <2 x double> %2, i32 %3
+  ; MIPS32-DAG: splat.d $w0, [[R1]]{{\[}}[[IDX]]]
+
+  ret double %4
+  ; MIPS32: .size extract_v2f64_vidx
+}
+
 define void @insert_v4f32(float %a) nounwind {
-  ; MIPS32: insert_v4f32:
+  ; MIPS32-LABEL: insert_v4f32:
 
   %1 = load <4 x float>* @v4f32
   ; MIPS32-DAG: ld.w [[R1:\$w[0-9]+]],
@@ -217,7 +260,7 @@ define void @insert_v4f32(float %a) nounwind {
 }
 
 define void @insert_v2f64(double %a) nounwind {
-  ; MIPS32: insert_v2f64:
+  ; MIPS32-LABEL: insert_v2f64:
 
   %1 = load <2 x double>* @v2f64
   ; MIPS32-DAG: ld.d [[R1:\$w[0-9]+]],
@@ -232,3 +275,55 @@ define void @insert_v2f64(double %a) nounwind {
   ret void
   ; MIPS32: .size insert_v2f64
 }
+
+define void @insert_v4f32_vidx(float %a) nounwind {
+  ; MIPS32-LABEL: insert_v4f32_vidx:
+
+  %1 = load <4 x float>* @v4f32
+  ; MIPS32-DAG: lw [[PTR_V:\$[0-9]+]], %got(v4f32)(
+  ; MIPS32-DAG: ld.w [[R1:\$w[0-9]+]], 0([[PTR_V]])
+
+  %2 = load i32* @i32
+  ; MIPS32-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)(
+  ; MIPS32-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]])
+
+  %3 = insertelement <4 x float> %1, float %a, i32 %2
+  ; float argument passed in $f12
+  ; MIPS32-DAG: sll [[BIDX:\$[0-9]+]], [[IDX]], 2
+  ; MIPS32-DAG: sld.b [[R1]], [[R1]]{{\[}}[[BIDX]]]
+  ; MIPS32-DAG: insve.w [[R1]][0], $w12[0]
+  ; MIPS32-DAG: neg [[NIDX:\$[0-9]+]], [[BIDX]]
+  ; MIPS32-DAG: sld.b [[R1]], [[R1]]{{\[}}[[NIDX]]]
+
+  store <4 x float> %3, <4 x float>* @v4f32
+  ; MIPS32-DAG: st.w [[R1]]
+
+  ret void
+  ; MIPS32: .size insert_v4f32_vidx
+}
+
+define void @insert_v2f64_vidx(double %a) nounwind {
+  ; MIPS32-LABEL: insert_v2f64_vidx:
+
+  %1 = load <2 x double>* @v2f64
+  ; MIPS32-DAG: lw [[PTR_V:\$[0-9]+]], %got(v2f64)(
+  ; MIPS32-DAG: ld.d [[R1:\$w[0-9]+]], 0([[PTR_V]])
+
+  %2 = load i32* @i32
+  ; MIPS32-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)(
+  ; MIPS32-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]])
+
+  %3 = insertelement <2 x double> %1, double %a, i32 %2
+  ; double argument passed in $f12
+  ; MIPS32-DAG: sll [[BIDX:\$[0-9]+]], [[IDX]], 3
+  ; MIPS32-DAG: sld.b [[R1]], [[R1]]{{\[}}[[BIDX]]]
+  ; MIPS32-DAG: insve.d [[R1]][0], $w12[0]
+  ; MIPS32-DAG: neg [[NIDX:\$[0-9]+]], [[BIDX]]
+  ; MIPS32-DAG: sld.b [[R1]], [[R1]]{{\[}}[[NIDX]]]
+
+  store <2 x double> %3, <2 x double>* @v2f64
+  ; MIPS32-DAG: st.d [[R1]]
+
+  ret void
+  ; MIPS32: .size insert_v2f64_vidx
+}
diff --git a/test/CodeGen/R600/add_i64.ll b/test/CodeGen/R600/add_i64.ll
index 7081b077d0..c9eaedae4a 100644
--- a/test/CodeGen/R600/add_i64.ll
+++ b/test/CodeGen/R600/add_i64.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=r600 -mcpu=SI < %s | FileCheck -check-prefix=SI %s
+; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs< %s | FileCheck -check-prefix=SI %s
 
 
 declare i32 @llvm.r600.read.tidig.x() readnone
diff --git a/test/CodeGen/R600/address-space.ll b/test/CodeGen/R600/address-space.ll
index 9ebf3fc07b..f75a8ac5e6 100644
--- a/test/CodeGen/R600/address-space.ll
+++ b/test/CodeGen/R600/address-space.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=r600 -mcpu=SI < %s | FileCheck %s
+; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs< %s | FileCheck %s
 
 ; Test that codegenprepare understands address space sizes
 
diff --git a/test/CodeGen/R600/array-ptr-calc-i64.ll b/test/CodeGen/R600/array-ptr-calc-i64.ll
index 652bbfe2a4..e254c5f646 100644
--- a/test/CodeGen/R600/array-ptr-calc-i64.ll
+++ b/test/CodeGen/R600/array-ptr-calc-i64.ll
@@ -1,5 +1,5 @@
 ; XFAIL: *
-; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck --check-prefix=SI %s
+; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs| FileCheck --check-prefix=SI %s
 
 declare i32 @llvm.SI.tid() readnone
 
diff --git a/test/CodeGen/R600/call.ll b/test/CodeGen/R600/call.ll
index c8350b85f4..d80347490b 100644
--- a/test/CodeGen/R600/call.ll
+++ b/test/CodeGen/R600/call.ll
@@ -1,4 +1,4 @@
-; RUN: not llc -march=r600 -mcpu=SI < %s 2>&1 | FileCheck %s
+; RUN: not llc -march=r600 -mcpu=SI -verify-machineinstrs< %s 2>&1 | FileCheck %s
 ; RUN: not llc -march=r600 -mcpu=cypress < %s 2>&1 | FileCheck %s
 
 ; CHECK: error: unsupported call to function defined_function in test_call
diff --git a/test/CodeGen/R600/extload.ll b/test/CodeGen/R600/extload.ll
index daa76857a1..dc056e0ecd 100644
--- a/test/CodeGen/R600/extload.ll
+++ b/test/CodeGen/R600/extload.ll
@@ -1,5 +1,5 @@
 ; RUN: llc -march=r600 -mcpu=cypress < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
-; RUN: llc -march=r600 -mcpu=SI < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
+; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs< %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
 
 ; FUNC-LABEL: @anyext_load_i8:
 ; EG: AND_INT
diff --git a/test/CodeGen/R600/extract_vector_elt_i16.ll b/test/CodeGen/R600/extract_vector_elt_i16.ll
index e1b038a139..5cd1b04bd1 100644
--- a/test/CodeGen/R600/extract_vector_elt_i16.ll
+++ b/test/CodeGen/R600/extract_vector_elt_i16.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=r600 -mcpu=SI < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
+; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs< %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
 
 ; FUNC-LABEL: @extract_vector_elt_v2i16
 ; SI: BUFFER_LOAD_USHORT
diff --git a/test/CodeGen/R600/gep-address-space.ll b/test/CodeGen/R600/gep-address-space.ll
index b36f6122ee..ab2c0bf92f 100644
--- a/test/CodeGen/R600/gep-address-space.ll
+++ b/test/CodeGen/R600/gep-address-space.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=r600 -mcpu=SI < %s | FileCheck %s
+; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs< %s | FileCheck %s
 
 define void @use_gep_address_space([1024 x i32] addrspace(3)* %array) nounwind {
 ; CHECK-LABEL: @use_gep_address_space:
diff --git a/test/CodeGen/R600/insert_vector_elt_f64.ll b/test/CodeGen/R600/insert_vector_elt_f64.ll
index e334be1749..595bc59655 100644
--- a/test/CodeGen/R600/insert_vector_elt_f64.ll
+++ b/test/CodeGen/R600/insert_vector_elt_f64.ll
@@ -1,6 +1,6 @@
 ; REQUIRES: asserts
 ; XFAIL: *
-; RUN: llc -march=r600 -mcpu=SI < %s | FileCheck -check-prefix=SI %s
+; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs< %s | FileCheck -check-prefix=SI %s
 
 
 ; SI-LABEL: @dynamic_insertelement_v2f64:
diff --git a/test/CodeGen/R600/llvm.sqrt.ll b/test/CodeGen/R600/llvm.sqrt.ll
index 0d0d186189..4eee37ffbe 100644
--- a/test/CodeGen/R600/llvm.sqrt.ll
+++ b/test/CodeGen/R600/llvm.sqrt.ll
@@ -1,5 +1,5 @@
 ; RUN: llc < %s -march=r600 --mcpu=redwood | FileCheck %s --check-prefix=R600-CHECK
-; RUN: llc < %s -march=r600 --mcpu=SI | FileCheck %s --check-prefix=SI-CHECK
+; RUN: llc < %s -march=r600 --mcpu=SI -verify-machineinstrs| FileCheck %s --check-prefix=SI-CHECK
 
 ; R600-CHECK-LABEL: @sqrt_f32
 ; R600-CHECK: RECIPSQRT_CLAMPED * T{{[0-9]\.[XYZW]}}, KC0[2].Z
diff --git a/test/CodeGen/R600/load-i1.ll b/test/CodeGen/R600/load-i1.ll
index 685ceb2e60..9ba81b85f5 100644
--- a/test/CodeGen/R600/load-i1.ll
+++ b/test/CodeGen/R600/load-i1.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=r600 -mcpu=SI < %s | FileCheck -check-prefix=SI %s
+; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs< %s | FileCheck -check-prefix=SI %s
 
 
 ; SI-LABEL: @global_copy_i1_to_i1
diff --git a/test/CodeGen/R600/local-64.ll b/test/CodeGen/R600/local-64.ll
index 38e5289f57..c52b41bb1b 100644
--- a/test/CodeGen/R600/local-64.ll
+++ b/test/CodeGen/R600/local-64.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=r600 -mcpu=SI < %s | FileCheck -check-prefix=SI %s
+; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs< %s | FileCheck -check-prefix=SI %s
 
 ; SI-LABEL: @local_i32_load
 ; SI: DS_READ_B32 [[REG:v[0-9]+]], v{{[0-9]+}}, 0x1c, [M0]
diff --git a/test/CodeGen/R600/loop-idiom.ll b/test/CodeGen/R600/loop-idiom.ll
index 8a9cba2796..128f661077 100644
--- a/test/CodeGen/R600/loop-idiom.ll
+++ b/test/CodeGen/R600/loop-idiom.ll
@@ -1,5 +1,5 @@
 ; RUN: opt -basicaa -loop-idiom -S < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=R600 --check-prefix=FUNC %s
-; RUN: opt -basicaa -loop-idiom -S < %s -march=r600 -mcpu=SI | FileCheck --check-prefix=SI --check-prefix=FUNC %s
+; RUN: opt -basicaa -loop-idiom -S < %s -march=r600 -mcpu=SI -verify-machineinstrs| FileCheck --check-prefix=SI --check-prefix=FUNC %s
 
 target datalayout = "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:32:32-p5:64:64-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"
 target triple = "r600--"
diff --git a/test/CodeGen/R600/register-count-comments.ll b/test/CodeGen/R600/register-count-comments.ll
index a64b2804bd..329077cde5 100644
--- a/test/CodeGen/R600/register-count-comments.ll
+++ b/test/CodeGen/R600/register-count-comments.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=r600 -mcpu=SI < %s | FileCheck -check-prefix=SI %s
+; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs< %s | FileCheck -check-prefix=SI %s
 
 declare i32 @llvm.SI.tid() nounwind readnone
 
diff --git a/test/CodeGen/R600/salu-to-valu.ll b/test/CodeGen/R600/salu-to-valu.ll
index e461bf9ace..3fd0db3459 100644
--- a/test/CodeGen/R600/salu-to-valu.ll
+++ b/test/CodeGen/R600/salu-to-valu.ll
@@ -46,3 +46,31 @@ declare i32 @llvm.r600.read.tidig.x() #1
 declare i32 @llvm.r600.read.tidig.y() #1
 
 attributes #1 = { nounwind readnone }
+
+; Test moving an SMRD instruction to the VALU
+
+; CHECK-LABEL: @smrd_valu
+; CHECK: BUFFER_LOAD_DWORD [[OUT:v[0-9]+]]
+; CHECK: BUFFER_STORE_DWORD [[OUT]]
+
+define void @smrd_valu(i32 addrspace(2)* addrspace(1)* %in, i32 %a, i32 addrspace(1)* %out) {
+entry:
+  %0 = icmp ne i32 %a, 0
+  br i1 %0, label %if, label %else
+
+if:
+  %1 = load i32 addrspace(2)* addrspace(1)* %in
+  br label %endif
+
+else:
+  %2 = getelementptr i32 addrspace(2)* addrspace(1)* %in
+  %3 = load i32 addrspace(2)* addrspace(1)* %2
+  br label %endif
+
+endif:
+  %4 = phi i32 addrspace(2)*  [%1, %if], [%3, %else]
+  %5 = getelementptr i32 addrspace(2)* %4, i32 3000
+  %6 = load i32 addrspace(2)* %5
+  store i32 %6, i32 addrspace(1)* %out
+  ret void
+}
diff --git a/test/CodeGen/R600/schedule-vs-if-nested-loop-failure.ll b/test/CodeGen/R600/schedule-vs-if-nested-loop-failure.ll
index 2a286d1b47..3d2142d53e 100644
--- a/test/CodeGen/R600/schedule-vs-if-nested-loop-failure.ll
+++ b/test/CodeGen/R600/schedule-vs-if-nested-loop-failure.ll
@@ -1,6 +1,6 @@
 ; XFAIL: *
 ; REQUIRES: asserts
-; RUN: llc -O0 -march=r600 -mcpu=SI < %s | FileCheck %s -check-prefix=SI
+; RUN: llc -O0 -march=r600 -mcpu=SI -verify-machineinstrs< %s | FileCheck %s -check-prefix=SI
 
 declare void @llvm.AMDGPU.barrier.local() nounwind noduplicate
 
diff --git a/test/CodeGen/R600/setcc.ll b/test/CodeGen/R600/setcc.ll
index 8d34c4ad4f..ad72732cab 100644
--- a/test/CodeGen/R600/setcc.ll
+++ b/test/CodeGen/R600/setcc.ll
@@ -1,5 +1,5 @@
 ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=R600 --check-prefix=FUNC %s
-;RUN: llc < %s -march=r600 -mcpu=SI | FileCheck --check-prefix=SI --check-prefix=FUNC %s
+;RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs| FileCheck --check-prefix=SI --check-prefix=FUNC %s
 
 ; FUNC-LABEL: @setcc_v2i32
 ; R600-DAG: SETE_INT * T{{[0-9]+\.[XYZW]}}, KC0[3].X, KC0[3].Z
diff --git a/test/CodeGen/R600/setcc64.ll b/test/CodeGen/R600/setcc64.ll
index 9202fc01f5..c137125183 100644
--- a/test/CodeGen/R600/setcc64.ll
+++ b/test/CodeGen/R600/setcc64.ll
@@ -1,4 +1,4 @@
-;RUN: llc < %s -march=r600 -mcpu=SI | FileCheck --check-prefix=SI --check-prefix=FUNC %s
+;RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs| FileCheck --check-prefix=SI --check-prefix=FUNC %s
 
 ; XXX: Merge this into setcc, once R600 supports 64-bit operations
 
diff --git a/test/CodeGen/R600/sgpr-control-flow.ll b/test/CodeGen/R600/sgpr-control-flow.ll
new file mode 100644
index 0000000000..06ad24d959
--- /dev/null
+++ b/test/CodeGen/R600/sgpr-control-flow.ll
@@ -0,0 +1,27 @@
+; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs< %s | FileCheck -check-prefix=SI %s
+;
+;
+; Most SALU instructions ignore control flow, so we need to make sure
+; they don't overwrite values from other blocks.
+
+; SI-NOT: S_ADD
+
+define void @sgpr_if_else(i32 addrspace(1)* %out, i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+entry:
+  %0 = icmp eq i32 %a, 0
+  br i1 %0, label %if, label %else
+
+if:
+  %1 = add i32 %b, %c
+  br label %endif
+
+else:
+  %2 = add i32 %d, %e
+  br label %endif
+
+endif:
+  %3 = phi i32 [%1, %if], [%2, %else]
+  %4 = add i32 %3, %a
+  store i32 %4, i32 addrspace(1)* %out
+  ret void
+}
diff --git a/test/CodeGen/R600/sgpr-copy-duplicate-operand.ll b/test/CodeGen/R600/sgpr-copy-duplicate-operand.ll
index d74161bf6d..9d8a623125 100644
--- a/test/CodeGen/R600/sgpr-copy-duplicate-operand.ll
+++ b/test/CodeGen/R600/sgpr-copy-duplicate-operand.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=r600 -mcpu=SI < %s | FileCheck -check-prefix=SI %s
+; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs< %s | FileCheck -check-prefix=SI %s
 
 ; Copy VGPR -> SGPR used twice as an instruction operand, which is then
 ; used in an REG_SEQUENCE that also needs to be handled.
diff --git a/test/CodeGen/R600/sgpr-copy.ll b/test/CodeGen/R600/sgpr-copy.ll
index 5472c1bb1c..c581d86b99 100644
--- a/test/CodeGen/R600/sgpr-copy.ll
+++ b/test/CodeGen/R600/sgpr-copy.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=r600 -mcpu=SI  | FileCheck %s
+; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck %s
 
 ; This test checks that no VGPR to SGPR copies are created by the register
 ; allocator.
diff --git a/test/CodeGen/R600/si-annotate-cf-assertion.ll b/test/CodeGen/R600/si-annotate-cf-assertion.ll
index cd3ba2b222..daa4667150 100644
--- a/test/CodeGen/R600/si-annotate-cf-assertion.ll
+++ b/test/CodeGen/R600/si-annotate-cf-assertion.ll
@@ -1,6 +1,6 @@
 ; REQUIRES: asserts
 ; XFAIL: *
-; RUN: llc -march=r600 -mcpu=SI -asm-verbose=false < %s | FileCheck %s
+; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs-asm-verbose=false < %s | FileCheck %s
 
 
 define void @test(i32 addrspace(1)* %g, i8 addrspace(3)* %l, i32 %x) nounwind {
diff --git a/test/CodeGen/R600/store-v3i64.ll b/test/CodeGen/R600/store-v3i64.ll
index 58229f6048..58d28b567b 100644
--- a/test/CodeGen/R600/store-v3i64.ll
+++ b/test/CodeGen/R600/store-v3i64.ll
@@ -1,5 +1,5 @@
 ; XFAIL: *
-; RUN: llc -march=r600 -mcpu=SI < %s | FileCheck -check-prefix=SI
+; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs< %s | FileCheck -check-prefix=SI
 
 ; SI-LABEL: @global_store_v3i64:
 ; SI: BUFFER_STORE_DWORDX4
diff --git a/test/CodeGen/R600/store-vector-ptrs.ll b/test/CodeGen/R600/store-vector-ptrs.ll
index 3af7d919c6..41c5edc280 100644
--- a/test/CodeGen/R600/store-vector-ptrs.ll
+++ b/test/CodeGen/R600/store-vector-ptrs.ll
@@ -1,6 +1,6 @@
 ; REQUIRES: asserts
 ; XFAIL: *
-; RUN: llc -march=r600 -mcpu=SI < %s
+; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs< %s
 
 define void @store_vector_ptrs(<4 x i32*>* %out, <4 x [1024 x i32]*> %array) nounwind {
   %p = getelementptr <4 x [1024 x i32]*> %array, <4 x i16> zeroinitializer, <4 x i16> <i16 16, i16 16, i16 16, i16 16>
diff --git a/test/CodeGen/R600/trunc-store-i1.ll b/test/CodeGen/R600/trunc-store-i1.ll
index a88894325b..a3975c8b8e 100644
--- a/test/CodeGen/R600/trunc-store-i1.ll
+++ b/test/CodeGen/R600/trunc-store-i1.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=r600 -mcpu=SI < %s | FileCheck -check-prefix=SI %s
+; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs< %s | FileCheck -check-prefix=SI %s
 
 
 ; SI-LABEL: @global_truncstore_i32_to_i1
diff --git a/test/CodeGen/R600/uaddo.ll b/test/CodeGen/R600/uaddo.ll
index 4f24c85f1a..3b69687b36 100644
--- a/test/CodeGen/R600/uaddo.ll
+++ b/test/CodeGen/R600/uaddo.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=r600 -mcpu=SI < %s | FileCheck -check-prefix=SI %s
+; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs< %s | FileCheck -check-prefix=SI %s
 
 declare { i64, i1 } @llvm.uadd.with.overflow.i64(i64, i64) nounwind readnone
 
diff --git a/test/CodeGen/R600/udivrem64.ll b/test/CodeGen/R600/udivrem64.ll
new file mode 100644
index 0000000000..b3caebf123
--- /dev/null
+++ b/test/CodeGen/R600/udivrem64.ll
@@ -0,0 +1,84 @@
+;XUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs| FileCheck --check-prefix=SI --check-prefix=FUNC %s
+;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG --check-prefix=FUNC %s
+
+;FUNC-LABEL: @test_udiv
+;EG: RECIP_UINT
+;EG: BFE_UINT
+;EG: BFE_UINT
+;EG: BFE_UINT
+;EG: BFE_UINT
+;EG: BFE_UINT
+;EG: BFE_UINT
+;EG: BFE_UINT
+;EG: BFE_UINT
+;EG: BFE_UINT
+;EG: BFE_UINT
+;EG: BFE_UINT
+;EG: BFE_UINT
+;EG: BFE_UINT
+;EG: BFE_UINT
+;EG: BFE_UINT
+;EG: BFE_UINT
+;EG: BFE_UINT
+;EG: BFE_UINT
+;EG: BFE_UINT
+;EG: BFE_UINT
+;EG: BFE_UINT
+;EG: BFE_UINT
+;EG: BFE_UINT
+;EG: BFE_UINT
+;EG: BFE_UINT
+;EG: BFE_UINT
+;EG: BFE_UINT
+;EG: BFE_UINT
+;EG: BFE_UINT
+;EG: BFE_UINT
+;EG: BFE_UINT
+;EG: BFE_UINT
+;SI: S_ENDPGM
+define void @test_udiv(i64 addrspace(1)* %out, i64 %x, i64 %y) {
+  %result = udiv i64 %x, %y
+  store i64 %result, i64 addrspace(1)* %out
+  ret void
+}
+
+;FUNC-LABEL: @test_urem
+;EG: RECIP_UINT
+;EG: BFE_UINT
+;EG: BFE_UINT
+;EG: BFE_UINT
+;EG: BFE_UINT
+;EG: BFE_UINT
+;EG: BFE_UINT
+;EG: BFE_UINT
+;EG: BFE_UINT
+;EG: BFE_UINT
+;EG: BFE_UINT
+;EG: BFE_UINT
+;EG: BFE_UINT
+;EG: BFE_UINT
+;EG: BFE_UINT
+;EG: BFE_UINT
+;EG: BFE_UINT
+;EG: BFE_UINT
+;EG: BFE_UINT
+;EG: BFE_UINT
+;EG: BFE_UINT
+;EG: BFE_UINT
+;EG: BFE_UINT
+;EG: BFE_UINT
+;EG: BFE_UINT
+;EG: BFE_UINT
+;EG: BFE_UINT
+;EG: BFE_UINT
+;EG: BFE_UINT
+;EG: BFE_UINT
+;EG: BFE_UINT
+;EG: BFE_UINT
+;EG: BFE_UINT
+;SI: S_ENDPGM
+define void @test_urem(i64 addrspace(1)* %out, i64 %x, i64 %y) {
+  %result = urem i64 %x, %y
+  store i64 %result, i64 addrspace(1)* %out
+  ret void
+}
diff --git a/test/CodeGen/R600/unaligned-load-store.ll b/test/CodeGen/R600/unaligned-load-store.ll
index 2824ff8a88..4df69d1e5f 100644
--- a/test/CodeGen/R600/unaligned-load-store.ll
+++ b/test/CodeGen/R600/unaligned-load-store.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=r600 -mcpu=SI < %s | FileCheck -check-prefix=SI %s
+; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs< %s | FileCheck -check-prefix=SI %s
 
 ; SI-LABEL: @unaligned_load_store_i32:
 ; DS_READ_U32 {{v[0-9]+}}, 0, [[REG]]
diff --git a/test/CodeGen/R600/valu-i1.ll b/test/CodeGen/R600/valu-i1.ll
new file mode 100644
index 0000000000..5d5e3ff63a
--- /dev/null
+++ b/test/CodeGen/R600/valu-i1.ll
@@ -0,0 +1,39 @@
+; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck --check-prefix=SI %s
+
+; Make sure the i1 values created by the cfg structurizer pass are
+; moved using VALU instructions
+; SI-NOT: S_MOV_B64 s[{{[0-9]:[0-9]}}], -1
+; SI: V_MOV_B32_e32 v{{[0-9]}}, -1
+define void @test_if(i32 %a, i32 %b, i32 addrspace(1)* %src, i32 addrspace(1)* %dst) {
+entry:
+  switch i32 %a, label %default [
+    i32 0, label %case0
+    i32 1, label %case1
+  ]
+
+case0:
+  %arrayidx1 = getelementptr i32 addrspace(1)* %dst, i32 %b
+  store i32 0, i32 addrspace(1)* %arrayidx1, align 4
+  br label %end
+
+case1:
+  %arrayidx5 = getelementptr i32 addrspace(1)* %dst, i32 %b
+  store i32 1, i32 addrspace(1)* %arrayidx5, align 4
+  br label %end
+
+default:
+  %cmp8 = icmp eq i32 %a, 2
+  %arrayidx10 = getelementptr i32 addrspace(1)* %dst, i32 %b
+  br i1 %cmp8, label %if, label %else
+
+if:
+  store i32 2, i32 addrspace(1)* %arrayidx10, align 4
+  br label %end
+
+else:
+  store i32 3, i32 addrspace(1)* %arrayidx10, align 4
+  br label %end
+
+end:
+  ret void
+}
diff --git a/test/CodeGen/X86/avx512-intrinsics.ll b/test/CodeGen/X86/avx512-intrinsics.ll
index 3fb38edee5..2c57944861 100644
--- a/test/CodeGen/X86/avx512-intrinsics.ll
+++ b/test/CodeGen/X86/avx512-intrinsics.ll
@@ -536,4 +536,12 @@ define void @test_store2(<8 x double> %data, i8* %ptr, i8 %mask) {
   ret void
 }
 
-declare void @llvm.x86.avx512.mask.storeu.pd.512(i8*, <8 x double>, i8 )
\ No newline at end of file
+declare void @llvm.x86.avx512.mask.storeu.pd.512(i8*, <8 x double>, i8 )
+
+define <16 x float> @test_vpermt2ps(<16 x float>%x, <16 x float>%y, <16 x i32>%perm) {
+; CHECK: vpermt2ps {{.*}}encoding: [0x62,0xf2,0x6d,0x48,0x7f,0xc1]
+  %res = call <16 x float> @llvm.x86.avx512.mask.vpermt.ps.512(<16 x i32>%perm, <16 x float>%x, <16 x float>%y, i16 -1)
+  ret <16 x float> %res
+}
+
+declare <16 x float> @llvm.x86.avx512.mask.vpermt.ps.512(<16 x i32>, <16 x float>, <16 x float>, i16)
diff --git a/test/CodeGen/X86/avx512-shuffle.ll b/test/CodeGen/X86/avx512-shuffle.ll
index 59d7010c8d..23ddc3a6c1 100644
--- a/test/CodeGen/X86/avx512-shuffle.ll
+++ b/test/CodeGen/X86/avx512-shuffle.ll
@@ -231,3 +231,22 @@ define <16 x i32> @test27(<4 x i32>%a) {
  %res = shufflevector <4 x i32> %a, <4 x i32> undef, <16 x i32> <i32 0, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
  ret <16 x i32> %res
 }
+
+; CHECK-LABEL: @test28
+; CHECK: vinserti64x4 $1
+; CHECK: ret
+define <16 x i32> @test28(<16 x i32>%x, <16 x i32>%y) {
+ %res = shufflevector <16 x i32>%x, <16 x i32>%y, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7,
+                                                              i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23>
+ ret <16 x i32> %res
+}
+
+; CHECK-LABEL: @test29
+; CHECK: vinserti64x4 $0
+; CHECK: ret
+define <16 x i32> @test29(<16 x i32>%x, <16 x i32>%y) {
+ %res = shufflevector <16 x i32>%x, <16 x i32>%y, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23,
+                                                              i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+ ret <16 x i32> %res
+}
+
diff --git a/test/CodeGen/X86/indirect-hidden.ll b/test/CodeGen/X86/indirect-hidden.ll
new file mode 100644
index 0000000000..309375d930
--- /dev/null
+++ b/test/CodeGen/X86/indirect-hidden.ll
@@ -0,0 +1,43 @@
+; RUN: llc -mtriple=i686-apple-macosx -o - %s | FileCheck %s
+
+; x86 doesn't normally use indirect symbols, particularly hidden ones, but it
+; can be tricked into it for exception-handling typeids.
+
+@hidden_typeid = external hidden constant i8*
+@normal_typeid = external constant i8*
+
+declare void @throws()
+
+define void @get_indirect_hidden() {
+  invoke void @throws() to label %end unwind label %lpad
+lpad:
+  %tmp = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*)
+          catch i8* bitcast (i8** @hidden_typeid to i8*)
+  br label %end
+
+end:
+  ret void
+}
+
+define void @get_indirect() {
+  invoke void @throws() to label %end unwind label %lpad
+lpad:
+  %tmp = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*)
+          catch i8* bitcast (i8** @normal_typeid to i8*)
+  br label %end
+
+end:
+  ret void
+}
+
+declare i32 @__gxx_personality_v0(...)
+
+; CHECK: .section __IMPORT,__pointers,non_lazy_symbol_pointers
+
+; CHECK-NOT: __DATA,__data
+; CHECK: .indirect_symbol _normal_typeid
+; CHECK-NEXT: .long 0
+
+; CHECK-NOT: __DATA,__data
+; CHECK: .indirect_symbol _hidden_typeid
+; CHECK-NEXT: .long 0
diff --git a/test/CodeGen/X86/musttail-indirect.ll b/test/CodeGen/X86/musttail-indirect.ll
new file mode 100644
index 0000000000..9d21b5ea5d
--- /dev/null
+++ b/test/CodeGen/X86/musttail-indirect.ll
@@ -0,0 +1,124 @@
+; RUN: llc < %s -mtriple=i686-win32 | FileCheck %s
+; RUN: llc < %s -mtriple=i686-win32 -O0 | FileCheck %s
+
+; IR simplified from the following C++ snippet compiled for i686-windows-msvc:
+
+; struct A { A(); ~A(); int a; };
+;
+; struct B {
+;   virtual int  f(int);
+;   virtual int  g(A, int, A);
+;   virtual void h(A, int, A);
+;   virtual A    i(A, int, A);
+;   virtual A    j(int);
+; };
+;
+; int  (B::*mp_f)(int)       = &B::f;
+; int  (B::*mp_g)(A, int, A) = &B::g;
+; void (B::*mp_h)(A, int, A) = &B::h;
+; A    (B::*mp_i)(A, int, A) = &B::i;
+; A    (B::*mp_j)(int)       = &B::j;
+
+; Each member pointer creates a thunk.  The ones with inalloca are required to
+; tail calls by the ABI, even at O0.
+
+%struct.B = type { i32 (...)** }
+%struct.A = type { i32 }
+
+; CHECK-LABEL: f_thunk:
+; CHECK: jmpl
+; CHECK-NOT: ret
+define x86_thiscallcc i32 @f_thunk(%struct.B* %this, i32) {
+entry:
+  %1 = bitcast %struct.B* %this to i32 (%struct.B*, i32)***
+  %vtable = load i32 (%struct.B*, i32)*** %1
+  %2 = load i32 (%struct.B*, i32)** %vtable
+  %3 = musttail call x86_thiscallcc i32 %2(%struct.B* %this, i32 %0)
+  ret i32 %3
+}
+
+; Inalloca thunks shouldn't require any stores to the stack.
+; CHECK-LABEL: g_thunk:
+; CHECK-NOT: mov %{{.*}}, {{.*(.*esp.*)}}
+; CHECK: jmpl
+; CHECK-NOT: ret
+define x86_thiscallcc i32 @g_thunk(%struct.B* %this, <{ %struct.A, i32, %struct.A }>* inalloca) {
+entry:
+  %1 = bitcast %struct.B* %this to i32 (%struct.B*, <{ %struct.A, i32, %struct.A }>*)***
+  %vtable = load i32 (%struct.B*, <{ %struct.A, i32, %struct.A }>*)*** %1
+  %vfn = getelementptr inbounds i32 (%struct.B*, <{ %struct.A, i32, %struct.A }>*)** %vtable, i32 1
+  %2 = load i32 (%struct.B*, <{ %struct.A, i32, %struct.A }>*)** %vfn
+  %3 = musttail call x86_thiscallcc i32 %2(%struct.B* %this, <{ %struct.A, i32, %struct.A }>* inalloca %0)
+  ret i32 %3
+}
+
+; CHECK-LABEL: h_thunk:
+; CHECK: jmpl
+; CHECK-NOT: mov %{{.*}}, {{.*(.*esp.*)}}
+; CHECK-NOT: ret
+define x86_thiscallcc void @h_thunk(%struct.B* %this, <{ %struct.A, i32, %struct.A }>* inalloca) {
+entry:
+  %1 = bitcast %struct.B* %this to void (%struct.B*, <{ %struct.A, i32, %struct.A }>*)***
+  %vtable = load void (%struct.B*, <{ %struct.A, i32, %struct.A }>*)*** %1
+  %vfn = getelementptr inbounds void (%struct.B*, <{ %struct.A, i32, %struct.A }>*)** %vtable, i32 2
+  %2 = load void (%struct.B*, <{ %struct.A, i32, %struct.A }>*)** %vfn
+  musttail call x86_thiscallcc void %2(%struct.B* %this, <{ %struct.A, i32, %struct.A }>* inalloca %0)
+  ret void
+}
+
+; CHECK-LABEL: i_thunk:
+; CHECK-NOT: mov %{{.*}}, {{.*(.*esp.*)}}
+; CHECK: jmpl
+; CHECK-NOT: ret
+define x86_thiscallcc %struct.A* @i_thunk(%struct.B* %this, <{ %struct.A*, %struct.A, i32, %struct.A }>* inalloca) {
+entry:
+  %1 = bitcast %struct.B* %this to %struct.A* (%struct.B*, <{ %struct.A*, %struct.A, i32, %struct.A }>*)***
+  %vtable = load %struct.A* (%struct.B*, <{ %struct.A*, %struct.A, i32, %struct.A }>*)*** %1
+  %vfn = getelementptr inbounds %struct.A* (%struct.B*, <{ %struct.A*, %struct.A, i32, %struct.A }>*)** %vtable, i32 3
+  %2 = load %struct.A* (%struct.B*, <{ %struct.A*, %struct.A, i32, %struct.A }>*)** %vfn
+  %3 = musttail call x86_thiscallcc %struct.A* %2(%struct.B* %this, <{ %struct.A*, %struct.A, i32, %struct.A }>* inalloca %0)
+  ret %struct.A* %3
+}
+
+; CHECK-LABEL: j_thunk:
+; CHECK: jmpl
+; CHECK-NOT: ret
+define x86_thiscallcc void @j_thunk(%struct.A* noalias sret %agg.result, %struct.B* %this, i32) {
+entry:
+  %1 = bitcast %struct.B* %this to void (%struct.A*, %struct.B*, i32)***
+  %vtable = load void (%struct.A*, %struct.B*, i32)*** %1
+  %vfn = getelementptr inbounds void (%struct.A*, %struct.B*, i32)** %vtable, i32 4
+  %2 = load void (%struct.A*, %struct.B*, i32)** %vfn
+  musttail call x86_thiscallcc void %2(%struct.A* sret %agg.result, %struct.B* %this, i32 %0)
+  ret void
+}
+
+; CHECK-LABEL: _stdcall_thunk@8:
+; CHECK-NOT: mov %{{.*}}, {{.*(.*esp.*)}}
+; CHECK: jmpl
+; CHECK-NOT: ret
+define x86_stdcallcc i32 @stdcall_thunk(<{ %struct.B*, %struct.A }>* inalloca) {
+entry:
+  %this_ptr = getelementptr inbounds <{ %struct.B*, %struct.A }>* %0, i32 0, i32 0
+  %this = load %struct.B** %this_ptr
+  %1 = bitcast %struct.B* %this to i32 (<{ %struct.B*, %struct.A }>*)***
+  %vtable = load i32 (<{ %struct.B*, %struct.A }>*)*** %1
+  %vfn = getelementptr inbounds i32 (<{ %struct.B*, %struct.A }>*)** %vtable, i32 1
+  %2 = load i32 (<{ %struct.B*, %struct.A }>*)** %vfn
+  %3 = musttail call x86_stdcallcc i32 %2(<{ %struct.B*, %struct.A }>* inalloca %0)
+  ret i32 %3
+}
+
+; CHECK-LABEL: @fastcall_thunk@8:
+; CHECK-NOT: mov %{{.*}}, {{.*(.*esp.*)}}
+; CHECK: jmpl
+; CHECK-NOT: ret
+define x86_fastcallcc i32 @fastcall_thunk(%struct.B* inreg %this, <{ %struct.A }>* inalloca) {
+entry:
+  %1 = bitcast %struct.B* %this to i32 (%struct.B*, <{ %struct.A }>*)***
+  %vtable = load i32 (%struct.B*, <{ %struct.A }>*)*** %1
+  %vfn = getelementptr inbounds i32 (%struct.B*, <{ %struct.A }>*)** %vtable, i32 1
+  %2 = load i32 (%struct.B*, <{ %struct.A }>*)** %vfn
+  %3 = musttail call x86_fastcallcc i32 %2(%struct.B* inreg %this, <{ %struct.A }>* inalloca %0)
+  ret i32 %3
+}
diff --git a/test/CodeGen/X86/musttail-thiscall.ll b/test/CodeGen/X86/musttail-thiscall.ll
new file mode 100644
index 0000000000..8ea12482e5
--- /dev/null
+++ b/test/CodeGen/X86/musttail-thiscall.ll
@@ -0,0 +1,31 @@
+; RUN: llc -march=x86 < %s | FileCheck %s
+; RUN: llc -march=x86 -O0 < %s | FileCheck %s
+
+; CHECK-LABEL: t1:
+; CHECK: jmp {{_?}}t1_callee
+define x86_thiscallcc void @t1(i8* %this) {
+  %adj = getelementptr i8* %this, i32 4
+  musttail call x86_thiscallcc void @t1_callee(i8* %adj)
+  ret void
+}
+declare x86_thiscallcc void @t1_callee(i8* %this)
+
+; CHECK-LABEL: t2:
+; CHECK: jmp {{_?}}t2_callee
+define x86_thiscallcc i32 @t2(i8* %this, i32 %a) {
+  %adj = getelementptr i8* %this, i32 4
+  %rv = musttail call x86_thiscallcc i32 @t2_callee(i8* %adj, i32 %a)
+  ret i32 %rv
+}
+declare x86_thiscallcc i32 @t2_callee(i8* %this, i32 %a)
+
+; CHECK-LABEL: t3:
+; CHECK: jmp {{_?}}t3_callee
+define x86_thiscallcc i8* @t3(i8* %this, <{ i8*, i32 }>* inalloca %args) {
+  %adj = getelementptr i8* %this, i32 4
+  %a_ptr = getelementptr <{ i8*, i32 }>* %args, i32 0, i32 1
+  store i32 0, i32* %a_ptr
+  %rv = musttail call x86_thiscallcc i8* @t3_callee(i8* %adj, <{ i8*, i32 }>* inalloca %args)
+  ret i8* %rv
+}
+declare x86_thiscallcc i8* @t3_callee(i8* %this, <{ i8*, i32 }>* inalloca %args);
diff --git a/test/CodeGen/X86/musttail.ll b/test/CodeGen/X86/musttail.ll
index 75b217f994..ca5d3119cf 100644
--- a/test/CodeGen/X86/musttail.ll
+++ b/test/CodeGen/X86/musttail.ll
@@ -1,8 +1,6 @@
 ; RUN: llc -march=x86 < %s | FileCheck %s
-
-; FIXME: Eliminate this tail call at -O0, since musttail is a correctness
-; requirement.
-; RUN: not llc -march=x86 -O0 < %s
+; RUN: llc -march=x86 -O0 < %s | FileCheck %s
+; RUN: llc -march=x86 -disable-tail-calls < %s | FileCheck %s
 
 declare void @t1_callee(i8*)
 define void @t1(i32* %a) {
@@ -21,3 +19,72 @@ define i32* @t2() {
   %w = bitcast i8* %v to i32*
   ret i32* %w
 }
+
+; Complex frame layout: stack realignment with dynamic alloca.
+define void @t3(i32 %n) alignstack(32) nounwind {
+entry:
+; CHECK: t3:
+; CHECK: pushl %ebp
+; CHECK: pushl %esi
+; CHECK: andl $-32, %esp
+; CHECK: movl %esp, %esi
+; CHECK: popl %esi
+; CHECK: popl %ebp
+; CHECK-NEXT: jmp {{_?}}t3_callee
+  %a = alloca i8, i32 %n
+  call void @capture(i8* %a)
+  musttail call void @t3_callee(i32 %n) nounwind
+  ret void
+}
+
+declare void @capture(i8*)
+declare void @t3_callee(i32)
+
+; Test that we actually copy in and out stack arguments that aren't forwarded
+; without modification.
+define i32 @t4({}* %fn, i32 %n, i32 %r) {
+; CHECK-LABEL: t4:
+; CHECK: incl %[[r:.*]]
+; CHECK: decl %[[n:.*]]
+; CHECK: movl %[[r]], {{[0-9]+}}(%esp)
+; CHECK: movl %[[n]], {{[0-9]+}}(%esp)
+; CHECK: jmpl *%{{.*}}
+
+entry:
+  %r1 = add i32 %r, 1
+  %n1 = sub i32 %n, 1
+  %fn_cast = bitcast {}* %fn to i32 ({}*, i32, i32)*
+  %r2 = musttail call i32 %fn_cast({}* %fn, i32 %n1, i32 %r1)
+  ret i32 %r2
+}
+
+; Combine the complex stack frame with the parameter modification.
+define i32 @t5({}* %fn, i32 %n, i32 %r) alignstack(32) {
+; CHECK-LABEL: t5:
+; CHECK: pushl %ebp
+; CHECK: movl %esp, %ebp
+; CHECK: pushl %esi
+; 	Align the stack.
+; CHECK: andl $-32, %esp
+; CHECK: movl %esp, %esi
+; 	Modify the args.
+; CHECK: incl %[[r:.*]]
+; CHECK: decl %[[n:.*]]
+; 	Store them through ebp, since that's the only stable arg pointer.
+; CHECK: movl %[[r]], {{[0-9]+}}(%ebp)
+; CHECK: movl %[[n]], {{[0-9]+}}(%ebp)
+; 	Epilogue.
+; CHECK: leal {{[-0-9]+}}(%ebp), %esp
+; CHECK: popl %esi
+; CHECK: popl %ebp
+; CHECK: jmpl *%{{.*}}
+
+entry:
+  %a = alloca i8, i32 %n
+  call void @capture(i8* %a)
+  %r1 = add i32 %r, 1
+  %n1 = sub i32 %n, 1
+  %fn_cast = bitcast {}* %fn to i32 ({}*, i32, i32)*
+  %r2 = musttail call i32 %fn_cast({}* %fn, i32 %n1, i32 %r1)
+  ret i32 %r2
+}
diff --git a/test/DebugInfo/X86/inline-member-function.ll b/test/DebugInfo/X86/inline-member-function.ll
new file mode 100644
index 0000000000..9821a076b5
--- /dev/null
+++ b/test/DebugInfo/X86/inline-member-function.ll
@@ -0,0 +1,90 @@
+; REQUIRES: object-emission
+
+; RUN: llc -mtriple=x86_64-linux -O0 -filetype=obj < %s | llvm-dwarfdump -debug-dump=info - | FileCheck %s
+
+; From source:
+; struct foo {
+;   int __attribute__((always_inline)) func(int x) { return x + 2; }
+; };
+
+; int i;
+
+; int main() {
+;   return foo().func(i);
+; }
+
+; Ensure we omit DW_AT_object_pointer on inlined subroutines.
+; CHECK: DW_TAG_inlined_subroutine
+; CHECK-NEXT: DW_AT_abstract_origin {{.*}}{[[ABSTRACT_ORIGIN:0x[0-9a-e]*]]}
+; CHECK-NOT: NULL
+; CHECK-NOT: DW_AT_object_pointer
+; CHECK: DW_TAG
+
+; But make sure we emit DW_AT_object_pointer on the abstract definition.
+; CHECK: [[ABSTRACT_ORIGIN]]: DW_TAG_subprogram
+; CHECK-NOT: NULL
+; CHECK-NOT: TAG
+; CHECK: DW_AT_object_pointer
+
+%struct.foo = type { i8 }
+
+@i = global i32 0, align 4
+
+; Function Attrs: uwtable
+define i32 @main() #0 {
+entry:
+  %this.addr.i = alloca %struct.foo*, align 8
+  %x.addr.i = alloca i32, align 4
+  %retval = alloca i32, align 4
+  %tmp = alloca %struct.foo, align 1
+  store i32 0, i32* %retval
+  %0 = load i32* @i, align 4, !dbg !23
+  store %struct.foo* %tmp, %struct.foo** %this.addr.i, align 8
+  call void @llvm.dbg.declare(metadata !{%struct.foo** %this.addr.i}, metadata !24), !dbg !26
+  store i32 %0, i32* %x.addr.i, align 4
+  call void @llvm.dbg.declare(metadata !{i32* %x.addr.i}, metadata !27), !dbg !28
+  %this1.i = load %struct.foo** %this.addr.i
+  %1 = load i32* %x.addr.i, align 4, !dbg !28
+  %add.i = add nsw i32 %1, 2, !dbg !28
+  ret i32 %add.i, !dbg !23
+}
+
+; Function Attrs: nounwind readnone
+declare void @llvm.dbg.declare(metadata, metadata) #1
+
+attributes #0 = { uwtable "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #1 = { nounwind readnone }
+
+!llvm.dbg.cu = !{!0}
+!llvm.module.flags = !{!20, !21}
+!llvm.ident = !{!22}
+
+!0 = metadata !{i32 786449, metadata !1, i32 4, metadata !"clang version 3.5.0 ", i1 false, metadata !"", i32 0, metadata !2, metadata !3, metadata !12, metadata !18, metadata !2, metadata !"", i32 1} ; [ DW_TAG_compile_unit ] [/tmp/dbginfo/inline.cpp] [DW_LANG_C_plus_plus]
+!1 = metadata !{metadata !"inline.cpp", metadata !"/tmp/dbginfo"}
+!2 = metadata !{}
+!3 = metadata !{metadata !4}
+!4 = metadata !{i32 786451, metadata !1, null, metadata !"foo", i32 1, i64 8, i64 8, i32 0, i32 0, null, metadata !5, i32 0, null, null, metadata !"_ZTS3foo"} ; [ DW_TAG_structure_type ] [foo] [line 1, size 8, align 8, offset 0] [def] [from ]
+!5 = metadata !{metadata !6}
+!6 = metadata !{i32 786478, metadata !1, metadata !"_ZTS3foo", metadata !"func", metadata !"func", metadata !"_ZN3foo4funcEi", i32 2, metadata !7, i1 false, i1 false, i32 0, i32 0, null, i32 256, i1 false, null, null, i32 0, metadata !11, i32 2} ; [ DW_TAG_subprogram ] [line 2] [func]
+!7 = metadata !{i32 786453, i32 0, null, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !8, i32 0, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!8 = metadata !{metadata !9, metadata !10, metadata !9}
+!9 = metadata !{i32 786468, null, null, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
+!10 = metadata !{i32 786447, null, null, metadata !"", i32 0, i64 64, i64 64, i64 0, i32 1088, metadata !"_ZTS3foo"} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [artificial] [from _ZTS3foo]
+!11 = metadata !{i32 786468}
+!12 = metadata !{metadata !13, metadata !17}
+!13 = metadata !{i32 786478, metadata !1, metadata !14, metadata !"main", metadata !"main", metadata !"", i32 7, metadata !15, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 false, i32 ()* @main, null, null, metadata !2, i32 7} ; [ DW_TAG_subprogram ] [line 7] [def] [main]
+!14 = metadata !{i32 786473, metadata !1}         ; [ DW_TAG_file_type ] [/tmp/dbginfo/inline.cpp]
+!15 = metadata !{i32 786453, i32 0, null, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !16, i32 0, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!16 = metadata !{metadata !9}
+!17 = metadata !{i32 786478, metadata !1, metadata !"_ZTS3foo", metadata !"func", metadata !"func", metadata !"_ZN3foo4funcEi", i32 2, metadata !7, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 false, null, null, metadata !6, metadata !2, i32 2} ; [ DW_TAG_subprogram ] [line 2] [def] [func]
+!18 = metadata !{metadata !19}
+!19 = metadata !{i32 786484, i32 0, null, metadata !"i", metadata !"i", metadata !"", metadata !14, i32 5, metadata !9, i32 0, i32 1, i32* @i, null} ; [ DW_TAG_variable ] [i] [line 5] [def]
+!20 = metadata !{i32 2, metadata !"Dwarf Version", i32 4}
+!21 = metadata !{i32 1, metadata !"Debug Info Version", i32 1}
+!22 = metadata !{metadata !"clang version 3.5.0 "}
+!23 = metadata !{i32 8, i32 0, metadata !13, null} ; [ DW_TAG_imported_declaration ]
+!24 = metadata !{i32 786689, metadata !17, metadata !"this", null, i32 16777216, metadata !25, i32 1088, i32 0} ; [ DW_TAG_arg_variable ] [this] [line 0]
+!25 = metadata !{i32 786447, null, null, metadata !"", i32 0, i64 64, i64 64, i64 0, i32 0, metadata !"_ZTS3foo"} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from _ZTS3foo]
+!26 = metadata !{i32 0, i32 0, metadata !17, metadata !23}
+!27 = metadata !{i32 786689, metadata !17, metadata !"x", metadata !14, i32 33554434, metadata !9, i32 0, i32 0} ; [ DW_TAG_arg_variable ] [x] [line 2]
+!28 = metadata !{i32 2, i32 0, metadata !17, metadata !23}
diff --git a/test/ExecutionEngine/lit.local.cfg b/test/ExecutionEngine/lit.local.cfg
index a198439335..7f0b69e544 100644
--- a/test/ExecutionEngine/lit.local.cfg
+++ b/test/ExecutionEngine/lit.local.cfg
@@ -1,9 +1,10 @@
-if config.root.host_arch in ['PowerPC', 'AArch64', 'SystemZ']:
+if config.root.host_arch in ['PowerPC', 'AArch64', 'ARM64', 'SystemZ']:
     config.unsupported = True
 
 # CMake and autoconf diverge in naming or host_arch
-if 'aarch64' in config.root.target_triple:
-    config.unsupported = True
+if 'aarch64' in config.root.target_triple \
+    or 'arm64' in config.root.target_triple:
+        config.unsupported = True
 
 if 'hexagon' in config.root.target_triple:
     config.unsupported = True
diff --git a/test/MC/AArch64/basic-a64-instructions.s b/test/MC/AArch64/basic-a64-instructions.s
index be00e14b9a..0919434747 100644
--- a/test/MC/AArch64/basic-a64-instructions.s
+++ b/test/MC/AArch64/basic-a64-instructions.s
@@ -1,4 +1,5 @@
-// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+fp-armv8 < %s | FileCheck %s
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+fp-armv8 < %s | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-AARCH64
+// RUN: llvm-mc -triple arm64-none-linux-gnu -show-encoding -mattr=+fp-armv8 < %s | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-ARM64
   .globl _func
 
 // Check that the assembler can handle the documented syntax from the ARM ARM.
@@ -108,9 +109,9 @@ _func:
 // CHECK: adds     x20, sp, w19, uxth #4      // encoding: [0xf4,0x33,0x33,0xab]
 // CHECK: adds     x12, x1, w20, uxtw         // encoding: [0x2c,0x40,0x34,0xab]
 // CHECK: adds     x20, x3, x13, uxtx         // encoding: [0x74,0x60,0x2d,0xab]
-// CHECK: adds     xzr, x25, w20, sxtb #3     // encoding: [0x3f,0x8f,0x34,0xab]
+// CHECK: {{adds xzr,|cmn}} x25, w20, sxtb #3     // encoding: [0x3f,0x8f,0x34,0xab]
 // CHECK: adds     x18, sp, w19, sxth         // encoding: [0xf2,0xa3,0x33,0xab]
-// CHECK: adds     xzr, x2, w3, sxtw          // encoding: [0x5f,0xc0,0x23,0xab]
+// CHECK: {{adds xzr,|cmn}} x2, w3, sxtw          // encoding: [0x5f,0xc0,0x23,0xab]
 // CHECK: adds     x3, x5, x9, sxtx #2        // encoding: [0xa3,0xe8,0x29,0xab]
 
         adds w2, w5, w7, uxtb
@@ -143,9 +144,9 @@ _func:
 // CHECK: subs     x20, sp, w19, uxth #4      // encoding: [0xf4,0x33,0x33,0xeb]
 // CHECK: subs     x12, x1, w20, uxtw         // encoding: [0x2c,0x40,0x34,0xeb]
 // CHECK: subs     x20, x3, x13, uxtx         // encoding: [0x74,0x60,0x2d,0xeb]
-// CHECK: subs     xzr, x25, w20, sxtb #3     // encoding: [0x3f,0x8f,0x34,0xeb]
+// CHECK: {{subs xzr,|cmp}} x25, w20, sxtb #3     // encoding: [0x3f,0x8f,0x34,0xeb]
 // CHECK: subs     x18, sp, w19, sxth         // encoding: [0xf2,0xa3,0x33,0xeb]
-// CHECK: subs     xzr, x2, w3, sxtw          // encoding: [0x5f,0xc0,0x23,0xeb]
+// CHECK: {{subs xzr,|cmp}} x2, w3, sxtw          // encoding: [0x5f,0xc0,0x23,0xeb]
 // CHECK: subs     x3, x5, x9, sxtx #2        // encoding: [0xa3,0xe8,0x29,0xeb]
 
         subs w2, w5, w7, uxtb
@@ -162,7 +163,7 @@ _func:
 // CHECK: subs     w19, w17, w1, uxtx         // encoding: [0x33,0x62,0x21,0x6b]
 // CHECK: subs     w2, w5, w1, sxtb #1        // encoding: [0xa2,0x84,0x21,0x6b]
 // CHECK: subs     w26, wsp, w19, sxth        // encoding: [0xfa,0xa3,0x33,0x6b]
-// CHECK: subs     wzr, w2, w3, sxtw          // encoding: [0x5f,0xc0,0x23,0x6b]
+// CHECK: {{subs wzr,|cmp}} w2, w3, sxtw          // encoding: [0x5f,0xc0,0x23,0x6b]
 // CHECK: subs     w2, w3, w5, sxtx           // encoding: [0x62,0xe0,0x25,0x6b]
 
         // cmp
@@ -227,14 +228,14 @@ _func:
         cmn wsp, w19, sxth
         cmn w2, w3, sxtw
         cmn w3, w5, sxtx
-// CHECK: cmn      w5, w7, uxtb               // encoding: [0xbf,0x00,0x27,0x2b]
-// CHECK: cmn      w15, w17, uxth             // encoding: [0xff,0x21,0x31,0x2b]
-// CHECK: cmn      w29, wzr, uxtw             // encoding: [0xbf,0x43,0x3f,0x2b]
-// CHECK: cmn      w17, w1, uxtx              // encoding: [0x3f,0x62,0x21,0x2b]
-// CHECK: cmn      w5, w1, sxtb #1            // encoding: [0xbf,0x84,0x21,0x2b]
-// CHECK: cmn      wsp, w19, sxth             // encoding: [0xff,0xa3,0x33,0x2b]
-// CHECK: cmn      w2, w3, sxtw               // encoding: [0x5f,0xc0,0x23,0x2b]
-// CHECK: cmn      w3, w5, sxtx               // encoding: [0x7f,0xe0,0x25,0x2b]
+// CHECK: {{cmn|adds wzr,}}      w5, w7, uxtb               // encoding: [0xbf,0x00,0x27,0x2b]
+// CHECK: {{cmn|adds wzr,}}      w15, w17, uxth             // encoding: [0xff,0x21,0x31,0x2b]
+// CHECK: {{cmn|adds wzr,}}      w29, wzr, uxtw             // encoding: [0xbf,0x43,0x3f,0x2b]
+// CHECK: {{cmn|adds wzr,}}      w17, w1, uxtx              // encoding: [0x3f,0x62,0x21,0x2b]
+// CHECK: {{cmn|adds wzr,}}      w5, w1, sxtb #1            // encoding: [0xbf,0x84,0x21,0x2b]
+// CHECK: {{cmn|adds wzr,}}      wsp, w19, sxth             // encoding: [0xff,0xa3,0x33,0x2b]
+// CHECK: {{cmn|adds wzr,}}      w2, w3, sxtw               // encoding: [0x5f,0xc0,0x23,0x2b]
+// CHECK: {{cmn|adds wzr,}}      w3, w5, sxtx               // encoding: [0x7f,0xe0,0x25,0x2b]
 
         // operands for cmp
         cmp x20, w29, uxtb #3
@@ -244,7 +245,7 @@ _func:
 // CHECK: cmp      x20, w29, uxtb #3          // encoding: [0x9f,0x0e,0x3d,0xeb]
 // CHECK: cmp      x12, x13, uxtx #4          // encoding: [0x9f,0x71,0x2d,0xeb]
 // CHECK: cmp      wsp, w1, uxtb              // encoding: [0xff,0x03,0x21,0x6b]
-// CHECK: cmn      wsp, wzr, sxtw             // encoding: [0xff,0xc3,0x3f,0x2b]
+// CHECK: {{cmn|adds wzr,}}      wsp, wzr, sxtw             // encoding: [0xff,0xc3,0x3f,0x2b]
 
         // LSL variant if sp involved
         sub sp, x3, x7, lsl #4
@@ -309,16 +310,16 @@ _func:
         adds w20, wsp, #0x0
         adds xzr, x3, #0x1, lsl #12          // FIXME: canonically should be cmn
 // CHECK: adds     w13, w23, #291, lsl #12    // encoding: [0xed,0x8e,0x44,0x31]
-// CHECK: adds     wzr, w2, #4095             // encoding: [0x5f,0xfc,0x3f,0x31]
+// CHECK: {{adds wzr,|cmn}} w2, #4095         // encoding: [0x5f,0xfc,0x3f,0x31]
 // CHECK: adds     w20, wsp, #0               // encoding: [0xf4,0x03,0x00,0x31]
-// CHECK: adds     xzr, x3, #1, lsl #12       // encoding: [0x7f,0x04,0x40,0xb1]
+// CHECK: {{adds xzr,|cmn}} x3, #1, lsl #12   // encoding: [0x7f,0x04,0x40,0xb1]
 
 // Checks for subs
         subs xzr, sp, #20, lsl #12           // FIXME: canonically should be cmp
         subs xzr, x30, #4095, lsl #0         // FIXME: canonically should be cmp
         subs x4, sp, #3822
-// CHECK: subs     xzr, sp, #20, lsl #12      // encoding: [0xff,0x53,0x40,0xf1]
-// CHECK: subs     xzr, x30, #4095            // encoding: [0xdf,0xff,0x3f,0xf1]
+// CHECK: {{subs xzr,|cmp}} sp, #20, lsl #12  // encoding: [0xff,0x53,0x40,0xf1]
+// CHECK: {{subs xzr,|cmp}} x30, #4095        // encoding: [0xdf,0xff,0x3f,0xf1]
 // CHECK: subs     x4, sp, #3822              // encoding: [0xe4,0xbb,0x3b,0xf1]
 
 // cmn is an alias for adds zr, ...
@@ -349,8 +350,10 @@ _func:
 
 // A relocation check (default to lo12, which is the only sane relocation anyway really)
         add x0, x4, #:lo12:var
-// CHECK: add     x0, x4, #:lo12:var         // encoding: [0x80'A',A,A,0x91'A']
-// CHECK:                                    //   fixup A - offset: 0, value: :lo12:var, kind: fixup_a64_add_lo12
+// CHECK-AARCH64: add     x0, x4, #:lo12:var         // encoding: [0x80'A',A,A,0x91'A']
+// CHECK-AARCH64:                                    //   fixup A - offset: 0, value: :lo12:var, kind: fixup_a64_add_lo12
+// CHECK-ARM64: add x0, x4, :lo12:var       // encoding: [0x80,0bAAAAAA00,0b00AAAAAA,0x91]
+// CHECK-ARM64:                             // fixup A - offset: 0, value: :lo12:var, kind: fixup_arm64_add_imm12
 
 //------------------------------------------------------------------------------
 // Add-sub (shifted register)
@@ -423,7 +426,7 @@ _func:
         adds w20, wzr, w4
         adds w4, w6, wzr
 // CHECK: adds     w3, w5, w7                 // encoding: [0xa3,0x00,0x07,0x2b]
-// CHECK: adds     wzr, w3, w5                // encoding: [0x7f,0x00,0x05,0x2b]
+// CHECK: {{adds wzr,|cmn}} w3, w5                // encoding: [0x7f,0x00,0x05,0x2b]
 // CHECK: adds     w20, wzr, w4               // encoding: [0xf4,0x03,0x04,0x2b]
 // CHECK: adds     w4, w6, wzr                // encoding: [0xc4,0x00,0x1f,0x2b]
 
@@ -453,7 +456,7 @@ _func:
         adds x20, xzr, x4
         adds x4, x6, xzr
 // CHECK: adds     x3, x5, x7                 // encoding: [0xa3,0x00,0x07,0xab]
-// CHECK: adds     xzr, x3, x5                // encoding: [0x7f,0x00,0x05,0xab]
+// CHECK: {{adds xzr,|cmn}} x3, x5                // encoding: [0x7f,0x00,0x05,0xab]
 // CHECK: adds     x20, xzr, x4               // encoding: [0xf4,0x03,0x04,0xab]
 // CHECK: adds     x4, x6, xzr                // encoding: [0xc4,0x00,0x1f,0xab]
 
@@ -484,7 +487,8 @@ _func:
         sub w4, w6, wzr
 // CHECK: sub      w3, w5, w7                 // encoding: [0xa3,0x00,0x07,0x4b]
 // CHECK: sub      wzr, w3, w5                // encoding: [0x7f,0x00,0x05,0x4b]
-// CHECK: sub      w20, wzr, w4               // encoding: [0xf4,0x03,0x04,0x4b]
+// CHECK-AARCH64: sub      w20, wzr, w4       // encoding: [0xf4,0x03,0x04,0x4b]
+// CHECK-ARM64: neg      w20, w4              // encoding: [0xf4,0x03,0x04,0x4b]
 // CHECK: sub      w4, w6, wzr                // encoding: [0xc4,0x00,0x1f,0x4b]
 
         sub w11, w13, w15, lsl #0
@@ -514,7 +518,8 @@ _func:
         sub x4, x6, xzr
 // CHECK: sub      x3, x5, x7                 // encoding: [0xa3,0x00,0x07,0xcb]
 // CHECK: sub      xzr, x3, x5                // encoding: [0x7f,0x00,0x05,0xcb]
-// CHECK: sub      x20, xzr, x4               // encoding: [0xf4,0x03,0x04,0xcb]
+// CHECK-AARCH64: sub      x20, xzr, x4       // encoding: [0xf4,0x03,0x04,0xcb]
+// CHECK-ARM64: neg      x20, x4              // encoding: [0xf4,0x03,0x04,0xcb]
 // CHECK: sub      x4, x6, xzr                // encoding: [0xc4,0x00,0x1f,0xcb]
 
         sub x11, x13, x15, lsl #0
@@ -543,8 +548,9 @@ _func:
         subs w20, wzr, w4
         subs w4, w6, wzr
 // CHECK: subs     w3, w5, w7                 // encoding: [0xa3,0x00,0x07,0x6b]
-// CHECK: subs     wzr, w3, w5                // encoding: [0x7f,0x00,0x05,0x6b]
-// CHECK: subs     w20, wzr, w4               // encoding: [0xf4,0x03,0x04,0x6b]
+// CHECK: {{subs wzr,|cmp}} w3, w5            // encoding: [0x7f,0x00,0x05,0x6b]
+// CHECK-AARCH64: subs     w20, wzr, w4       // encoding: [0xf4,0x03,0x04,0x6b]
+// CHECK-ARM64: negs     w20, w4              // encoding: [0xf4,0x03,0x04,0x6b]
 // CHECK: subs     w4, w6, wzr                // encoding: [0xc4,0x00,0x1f,0x6b]
 
         subs w11, w13, w15, lsl #0
@@ -573,8 +579,9 @@ _func:
         subs x20, xzr, x4
         subs x4, x6, xzr
 // CHECK: subs     x3, x5, x7                 // encoding: [0xa3,0x00,0x07,0xeb]
-// CHECK: subs     xzr, x3, x5                // encoding: [0x7f,0x00,0x05,0xeb]
-// CHECK: subs     x20, xzr, x4               // encoding: [0xf4,0x03,0x04,0xeb]
+// CHECK: {{subs xzr,|cmp}} x3, x5            // encoding: [0x7f,0x00,0x05,0xeb]
+// CHECK-AARCH64: subs     x20, xzr, x4       // encoding: [0xf4,0x03,0x04,0xeb]
+// CHECK-ARM64: negs     x20, x4              // encoding: [0xf4,0x03,0x04,0xeb]
 // CHECK: subs     x4, x6, xzr                // encoding: [0xc4,0x00,0x1f,0xeb]
 
         subs x11, x13, x15, lsl #0
@@ -713,14 +720,18 @@ _func:
         neg w29, w30
         neg w30, wzr
         neg wzr, w0
-// CHECK: sub      w29, wzr, w30              // encoding: [0xfd,0x03,0x1e,0x4b]
-// CHECK: sub      w30, wzr, wzr              // encoding: [0xfe,0x03,0x1f,0x4b]
-// CHECK: sub      wzr, wzr, w0                    // encoding: [0xff,0x03,0x00,0x4b]
+// CHECK-AARCH64: sub      w29, wzr, w30              // encoding: [0xfd,0x03,0x1e,0x4b]
+// CHECK-AARCH64: sub      w30, wzr, wzr              // encoding: [0xfe,0x03,0x1f,0x4b]
+// CHECK-AARCH64: sub      wzr, wzr, w0              // encoding: [0xff,0x03,0x00,0x4b]
+// CHECK-ARM64: neg      w29, w30              // encoding: [0xfd,0x03,0x1e,0x4b]
+// CHECK-ARM64: neg      w30, wzr              // encoding: [0xfe,0x03,0x1f,0x4b]
+// CHECK-ARM64: neg      wzr, w0               // encoding: [0xff,0x03,0x00,0x4b]
 
         neg w28, w27, lsl #0
         neg w26, w25, lsl #29
         neg w24, w23, lsl #31
-// CHECK: sub      w28, wzr, w27              // encoding: [0xfc,0x03,0x1b,0x4b]
+// CHECK-AARCH64: sub      w28, wzr, w27              // encoding: [0xfc,0x03,0x1b,0x4b]
+// CHECK-ARM64: neg      w28, w27              // encoding: [0xfc,0x03,0x1b,0x4b]
 // CHECK: sub      w26, wzr, w25, lsl #29     // encoding: [0xfa,0x77,0x19,0x4b]
 // CHECK: sub      w24, wzr, w23, lsl #31     // encoding: [0xf8,0x7f,0x17,0x4b]
 
@@ -741,14 +752,18 @@ _func:
         neg x29, x30
         neg x30, xzr
         neg xzr, x0
-// CHECK: sub      x29, xzr, x30              // encoding: [0xfd,0x03,0x1e,0xcb]
-// CHECK: sub      x30, xzr, xzr              // encoding: [0xfe,0x03,0x1f,0xcb]
-// CHECK: sub      xzr, xzr, x0               // encoding: [0xff,0x03,0x00,0xcb]
+// CHECK-AARCH64: sub      x29, xzr, x30              // encoding: [0xfd,0x03,0x1e,0xcb]
+// CHECK-AARCH64: sub      x30, xzr, xzr              // encoding: [0xfe,0x03,0x1f,0xcb]
+// CHECK-AARCH64: sub      xzr, xzr, x0               // encoding: [0xff,0x03,0x00,0xcb]
+// CHECK-ARM64: neg      x29, x30              // encoding: [0xfd,0x03,0x1e,0xcb]
+// CHECK-ARM64: neg      x30, xzr              // encoding: [0xfe,0x03,0x1f,0xcb]
+// CHECK-ARM64: neg      xzr, x0               // encoding: [0xff,0x03,0x00,0xcb]
 
         neg x28, x27, lsl #0
         neg x26, x25, lsl #29
         neg x24, x23, lsl #31
-// CHECK: sub      x28, xzr, x27              // encoding: [0xfc,0x03,0x1b,0xcb]
+// CHECK-AARCH64: sub      x28, xzr, x27              // encoding: [0xfc,0x03,0x1b,0xcb]
+// CHECK-ARM64: neg      x28, x27              // encoding: [0xfc,0x03,0x1b,0xcb]
 // CHECK: sub      x26, xzr, x25, lsl #29     // encoding: [0xfa,0x77,0x19,0xcb]
 // CHECK: sub      x24, xzr, x23, lsl #31     // encoding: [0xf8,0x7f,0x17,0xcb]
 
@@ -769,14 +784,18 @@ _func:
         negs w29, w30
         negs w30, wzr
         negs wzr, w0
-// CHECK: subs     w29, wzr, w30              // encoding: [0xfd,0x03,0x1e,0x6b]
-// CHECK: subs     w30, wzr, wzr              // encoding: [0xfe,0x03,0x1f,0x6b]
-// CHECK: subs     wzr, wzr, w0               // encoding: [0xff,0x03,0x00,0x6b]
+// CHECK-AARCH64: subs     w29, wzr, w30              // encoding: [0xfd,0x03,0x1e,0x6b]
+// CHECK-AARCH64: subs     w30, wzr, wzr              // encoding: [0xfe,0x03,0x1f,0x6b]
+// CHECK-AARCH64: subs     wzr, wzr, w0               // encoding: [0xff,0x03,0x00,0x6b]
+// CHECK-ARM64: negs     w29, w30              // encoding: [0xfd,0x03,0x1e,0x6b]
+// CHECK-ARM64: negs     w30, wzr              // encoding: [0xfe,0x03,0x1f,0x6b]
+// CHECK-ARM64: cmp      wzr, w0               // encoding: [0xff,0x03,0x00,0x6b]
 
         negs w28, w27, lsl #0
         negs w26, w25, lsl #29
         negs w24, w23, lsl #31
-// CHECK: subs     w28, wzr, w27              // encoding: [0xfc,0x03,0x1b,0x6b]
+// CHECK-AARCH64: subs     w28, wzr, w27      // encoding: [0xfc,0x03,0x1b,0x6b]
+// CHECK-ARM64: negs     w28, w27             // encoding: [0xfc,0x03,0x1b,0x6b]
 // CHECK: subs     w26, wzr, w25, lsl #29     // encoding: [0xfa,0x77,0x19,0x6b]
 // CHECK: subs     w24, wzr, w23, lsl #31     // encoding: [0xf8,0x7f,0x17,0x6b]
 
@@ -797,14 +816,18 @@ _func:
         negs x29, x30
         negs x30, xzr
         negs xzr, x0
-// CHECK: subs     x29, xzr, x30              // encoding: [0xfd,0x03,0x1e,0xeb]
-// CHECK: subs     x30, xzr, xzr              // encoding: [0xfe,0x03,0x1f,0xeb]
-// CHECK: subs     xzr, xzr, x0               // encoding: [0xff,0x03,0x00,0xeb]
+// CHECK-AARCH64: subs     x29, xzr, x30              // encoding: [0xfd,0x03,0x1e,0xeb]
+// CHECK-AARCH64: subs     x30, xzr, xzr              // encoding: [0xfe,0x03,0x1f,0xeb]
+// CHECK-AARCH64: subs     xzr, xzr, x0               // encoding: [0xff,0x03,0x00,0xeb]
+// CHECK-ARM64: negs     x29, x30              // encoding: [0xfd,0x03,0x1e,0xeb]
+// CHECK-ARM64: negs     x30, xzr              // encoding: [0xfe,0x03,0x1f,0xeb]
+// CHECK-ARM64: cmp     xzr, x0                // encoding: [0xff,0x03,0x00,0xeb]
 
         negs x28, x27, lsl #0
         negs x26, x25, lsl #29
         negs x24, x23, lsl #31
-// CHECK: subs     x28, xzr, x27              // encoding: [0xfc,0x03,0x1b,0xeb]
+// CHECK-AARCH64: subs     x28, xzr, x27              // encoding: [0xfc,0x03,0x1b,0xeb]
+// CHECK-ARM64: negs     x28, x27              // encoding: [0xfc,0x03,0x1b,0xeb]
 // CHECK: subs     x26, xzr, x25, lsl #29     // encoding: [0xfa,0x77,0x19,0xeb]
 // CHECK: subs     x24, xzr, x23, lsl #31     // encoding: [0xf8,0x7f,0x17,0xeb]
 
@@ -933,19 +956,28 @@ _func:
         sbfm x3, x4, #63, #63
         sbfm wzr, wzr, #31, #31
         sbfm w12, w9, #0, #0
-// CHECK: sbfm     x1, x2, #3, #4             // encoding: [0x41,0x10,0x43,0x93]
-// CHECK: sbfm     x3, x4, #63, #63           // encoding: [0x83,0xfc,0x7f,0x93]
-// CHECK: sbfm     wzr, wzr, #31, #31         // encoding: [0xff,0x7f,0x1f,0x13]
-// CHECK: sbfm     w12, w9, #0, #0            // encoding: [0x2c,0x01,0x00,0x13]
+// CHECK-AARCH64: sbfm     x1, x2, #3, #4     // encoding: [0x41,0x10,0x43,0x93]
+// CHECK-AARCH64: sbfm     x3, x4, #63, #63   // encoding: [0x83,0xfc,0x7f,0x93]
+// CHECK-AARCH64: sbfm     wzr, wzr, #31, #31 // encoding: [0xff,0x7f,0x1f,0x13]
+// CHECK-AARCH64: sbfm     w12, w9, #0, #0    // encoding: [0x2c,0x01,0x00,0x13]
+
+// CHECK-ARM64: sbfx     x1, x2, #3, #2       // encoding: [0x41,0x10,0x43,0x93]
+// CHECK-ARM64: asr      x3, x4, #63          // encoding: [0x83,0xfc,0x7f,0x93]
+// CHECK-ARM64: asr      wzr, wzr, #31        // encoding: [0xff,0x7f,0x1f,0x13]
+// CHECK-ARM64: sbfx     w12, w9, #0, #1      // encoding: [0x2c,0x01,0x00,0x13]
 
         ubfm x4, x5, #12, #10
         ubfm xzr, x4, #0, #0
         ubfm x4, xzr, #63, #5
         ubfm x5, x6, #12, #63
-// CHECK: ubfm     x4, x5, #12, #10           // encoding: [0xa4,0x28,0x4c,0xd3]
-// CHECK: ubfm     xzr, x4, #0, #0            // encoding: [0x9f,0x00,0x40,0xd3]
-// CHECK: ubfm     x4, xzr, #63, #5            // encoding: [0xe4,0x17,0x7f,0xd3]
-// CHECK: ubfm     x5, x6, #12, #63           // encoding: [0xc5,0xfc,0x4c,0xd3]
+// CHECK-AARCH64: ubfm     x4, x5, #12, #10           // encoding: [0xa4,0x28,0x4c,0xd3]
+// CHECK-AARCH64: ubfm     xzr, x4, #0, #0            // encoding: [0x9f,0x00,0x40,0xd3]
+// CHECK-AARCH64: ubfm     x4, xzr, #63, #5            // encoding: [0xe4,0x17,0x7f,0xd3]
+// CHECK-AARCH64: ubfm     x5, x6, #12, #63           // encoding: [0xc5,0xfc,0x4c,0xd3]
+// CHECK-ARM64: ubfiz    x4, x5, #52, #11        // encoding: [0xa4,0x28,0x4c,0xd3]
+// CHECK-ARM64: ubfx     xzr, x4, #0, #1         // encoding: [0x9f,0x00,0x40,0xd3]
+// CHECK-ARM64: ubfiz    x4, xzr, #1, #6         // encoding: [0xe4,0x17,0x7f,0xd3]
+// CHECK-ARM64: lsr      x5, x6, #12             // encoding: [0xc5,0xfc,0x4c,0xd3]
 
         bfm x4, x5, #12, #10
         bfm xzr, x4, #0, #0
@@ -955,7 +987,6 @@ _func:
 // CHECK: bfm      xzr, x4, #0, #0            // encoding: [0x9f,0x00,0x40,0xb3]
 // CHECK: bfm      x4, xzr, #63, #5            // encoding: [0xe4,0x17,0x7f,0xb3]
 // CHECK: bfm      x5, x6, #12, #63           // encoding: [0xc5,0xfc,0x4c,0xb3]
-
         sxtb w1, w2
         sxtb xzr, w3
         sxth w9, w10
@@ -972,9 +1003,9 @@ _func:
         uxth w9, w10
         uxth x0, w1
 // CHECK: uxtb     w1, w2                     // encoding: [0x41,0x1c,0x00,0x53]
-// CHECK: uxtb     xzr, w3                    // encoding: [0x7f,0x1c,0x00,0x53]
+// CHECK: uxtb     {{[wx]}}zr, w3             // encoding: [0x7f,0x1c,0x00,0x53]
 // CHECK: uxth     w9, w10                    // encoding: [0x49,0x3d,0x00,0x53]
-// CHECK: uxth     x0, w1                     // encoding: [0x20,0x3c,0x00,0x53]
+// CHECK: uxth     {{[wx]}}0, w1              // encoding: [0x20,0x3c,0x00,0x53]
 
         asr w3, w2, #0
         asr w9, w10, #31
@@ -998,7 +1029,7 @@ _func:
         lsl w9, w10, #31
         lsl x20, x21, #63
         lsl w1, wzr, #3
-// CHECK: lsl      w3, w2, #0                 // encoding: [0x43,0x7c,0x00,0x53]
+// CHECK: {{lsl|lsr}}      w3, w2, #0         // encoding: [0x43,0x7c,0x00,0x53]
 // CHECK: lsl      w9, w10, #31               // encoding: [0x49,0x01,0x01,0x53]
 // CHECK: lsl      x20, x21, #63              // encoding: [0xb4,0x02,0x41,0xd3]
 // CHECK: lsl      w1, wzr, #3                // encoding: [0xe1,0x73,0x1d,0x53]
@@ -1011,11 +1042,13 @@ _func:
         sbfiz w11, w12, #31, #1
         sbfiz w13, w14, #29, #3
         sbfiz xzr, xzr, #10, #11
-// CHECK: sbfiz    w9, w10, #0, #1            // encoding: [0x49,0x01,0x00,0x13]
+// CHECK: {{sbfiz|sbfx}}    w9, w10, #0, #1   // encoding: [0x49,0x01,0x00,0x13]
 // CHECK: sbfiz    x2, x3, #63, #1            // encoding: [0x62,0x00,0x41,0x93]
-// CHECK: sbfiz    x19, x20, #0, #64          // encoding: [0x93,0xfe,0x40,0x93]
+// CHECK-AARCH64: sbfiz    x19, x20, #0, #64  // encoding: [0x93,0xfe,0x40,0x93]
+// CHECK-ARM64: asr    x19, x20, #0           // encoding: [0x93,0xfe,0x40,0x93]
 // CHECK: sbfiz    x9, x10, #5, #59           // encoding: [0x49,0xe9,0x7b,0x93]
-// CHECK: sbfiz    w9, w10, #0, #32           // encoding: [0x49,0x7d,0x00,0x13]
+// CHECK-AARCH64: sbfiz    w9, w10, #0, #32   // encoding: [0x49,0x7d,0x00,0x13]
+// CHECK-ARM64: asr    w9, w10, #0            // encoding: [0x49,0x7d,0x00,0x13]
 // CHECK: sbfiz    w11, w12, #31, #1          // encoding: [0x8b,0x01,0x01,0x13]
 // CHECK: sbfiz    w13, w14, #29, #3          // encoding: [0xcd,0x09,0x03,0x13]
 // CHECK: sbfiz    xzr, xzr, #10, #11         // encoding: [0xff,0x2b,0x76,0x93]
@@ -1029,12 +1062,18 @@ _func:
         sbfx w13, w14, #29, #3
         sbfx xzr, xzr, #10, #11
 // CHECK: sbfx     w9, w10, #0, #1            // encoding: [0x49,0x01,0x00,0x13]
-// CHECK: sbfx     x2, x3, #63, #1            // encoding: [0x62,0xfc,0x7f,0x93]
-// CHECK: sbfx     x19, x20, #0, #64          // encoding: [0x93,0xfe,0x40,0x93]
-// CHECK: sbfx     x9, x10, #5, #59           // encoding: [0x49,0xfd,0x45,0x93]
-// CHECK: sbfx     w9, w10, #0, #32           // encoding: [0x49,0x7d,0x00,0x13]
-// CHECK: sbfx     w11, w12, #31, #1          // encoding: [0x8b,0x7d,0x1f,0x13]
-// CHECK: sbfx     w13, w14, #29, #3          // encoding: [0xcd,0x7d,0x1d,0x13]
+// CHECK-AARCH64: sbfx     x2, x3, #63, #1    // encoding: [0x62,0xfc,0x7f,0x93]
+// CHECK-ARM64: asr     x2, x3, #63           // encoding: [0x62,0xfc,0x7f,0x93]
+// CHECK-AARCH64: sbfx     x19, x20, #0, #64  // encoding: [0x93,0xfe,0x40,0x93]
+// CHECK-ARM64: asr     x19, x20, #0          // encoding: [0x93,0xfe,0x40,0x93]
+// CHECK-AARCH64: sbfx     x9, x10, #5, #59   // encoding: [0x49,0xfd,0x45,0x93]
+// CHECK-ARM64: asr     x9, x10, #5           // encoding: [0x49,0xfd,0x45,0x93]
+// CHECK-AARCH64: sbfx     w9, w10, #0, #32   // encoding: [0x49,0x7d,0x00,0x13]
+// CHECK-ARM64: asr     w9, w10, #0           // encoding: [0x49,0x7d,0x00,0x13]
+// CHECK-AARCH64: sbfx     w11, w12, #31, #1  // encoding: [0x8b,0x7d,0x1f,0x13]
+// CHECK-ARM64: asr     w11, w12, #31         // encoding: [0x8b,0x7d,0x1f,0x13]
+// CHECK-AARCH64: sbfx     w13, w14, #29, #3  // encoding: [0xcd,0x7d,0x1d,0x13]
+// CHECK-ARM64: asr     w13, w14, #29         // encoding: [0xcd,0x7d,0x1d,0x13]
 // CHECK: sbfx     xzr, xzr, #10, #11         // encoding: [0xff,0x53,0x4a,0x93]
 
         bfi w9, w10, #0, #1
@@ -1045,14 +1084,23 @@ _func:
         bfi w11, w12, #31, #1
         bfi w13, w14, #29, #3
         bfi xzr, xzr, #10, #11
-// CHECK: bfi      w9, w10, #0, #1            // encoding: [0x49,0x01,0x00,0x33]
-// CHECK: bfi      x2, x3, #63, #1            // encoding: [0x62,0x00,0x41,0xb3]
-// CHECK: bfi      x19, x20, #0, #64          // encoding: [0x93,0xfe,0x40,0xb3]
-// CHECK: bfi      x9, x10, #5, #59           // encoding: [0x49,0xe9,0x7b,0xb3]
-// CHECK: bfi      w9, w10, #0, #32           // encoding: [0x49,0x7d,0x00,0x33]
-// CHECK: bfi      w11, w12, #31, #1          // encoding: [0x8b,0x01,0x01,0x33]
-// CHECK: bfi      w13, w14, #29, #3          // encoding: [0xcd,0x09,0x03,0x33]
-// CHECK: bfi      xzr, xzr, #10, #11         // encoding: [0xff,0x2b,0x76,0xb3]
+// CHECK-AARCH64: bfi      w9, w10, #0, #1            // encoding: [0x49,0x01,0x00,0x33]
+// CHECK-AARCH64: bfi      x2, x3, #63, #1            // encoding: [0x62,0x00,0x41,0xb3]
+// CHECK-AARCH64: bfi      x19, x20, #0, #64          // encoding: [0x93,0xfe,0x40,0xb3]
+// CHECK-AARCH64: bfi      x9, x10, #5, #59           // encoding: [0x49,0xe9,0x7b,0xb3]
+// CHECK-AARCH64: bfi      w9, w10, #0, #32           // encoding: [0x49,0x7d,0x00,0x33]
+// CHECK-AARCH64: bfi      w11, w12, #31, #1          // encoding: [0x8b,0x01,0x01,0x33]
+// CHECK-AARCH64: bfi      w13, w14, #29, #3          // encoding: [0xcd,0x09,0x03,0x33]
+// CHECK-AARCH64: bfi      xzr, xzr, #10, #11         // encoding: [0xff,0x2b,0x76,0xb3]
+
+// CHECK-ARM64: bfm    w9, w10, #0, #0         // encoding: [0x49,0x01,0x00,0x33]
+// CHECK-ARM64: bfm    x2, x3, #1, #0          // encoding: [0x62,0x00,0x41,0xb3]
+// CHECK-ARM64: bfm    x19, x20, #0, #63       // encoding: [0x93,0xfe,0x40,0xb3]
+// CHECK-ARM64: bfm    x9, x10, #59, #58       // encoding: [0x49,0xe9,0x7b,0xb3]
+// CHECK-ARM64: bfm    w9, w10, #0, #31        // encoding: [0x49,0x7d,0x00,0x33]
+// CHECK-ARM64: bfm    w11, w12, #1, #0        // encoding: [0x8b,0x01,0x01,0x33]
+// CHECK-ARM64: bfm    w13, w14, #3, #2        // encoding: [0xcd,0x09,0x03,0x33]
+// CHECK-ARM64: bfm    xzr, xzr, #54, #10      // encoding: [0xff,0x2b,0x76,0xb3]
 
         bfxil w9, w10, #0, #1
         bfxil x2, x3, #63, #1
@@ -1062,14 +1110,23 @@ _func:
         bfxil w11, w12, #31, #1
         bfxil w13, w14, #29, #3
         bfxil xzr, xzr, #10, #11
-// CHECK: bfxil    w9, w10, #0, #1            // encoding: [0x49,0x01,0x00,0x33]
-// CHECK: bfxil    x2, x3, #63, #1            // encoding: [0x62,0xfc,0x7f,0xb3]
-// CHECK: bfxil    x19, x20, #0, #64          // encoding: [0x93,0xfe,0x40,0xb3]
-// CHECK: bfxil    x9, x10, #5, #59           // encoding: [0x49,0xfd,0x45,0xb3]
-// CHECK: bfxil    w9, w10, #0, #32           // encoding: [0x49,0x7d,0x00,0x33]
-// CHECK: bfxil    w11, w12, #31, #1          // encoding: [0x8b,0x7d,0x1f,0x33]
-// CHECK: bfxil    w13, w14, #29, #3          // encoding: [0xcd,0x7d,0x1d,0x33]
-// CHECK: bfxil    xzr, xzr, #10, #11         // encoding: [0xff,0x53,0x4a,0xb3]
+// CHECK-AARCH64: bfxil    w9, w10, #0, #1            // encoding: [0x49,0x01,0x00,0x33]
+// CHECK-AARCH64: bfxil    x2, x3, #63, #1            // encoding: [0x62,0xfc,0x7f,0xb3]
+// CHECK-AARCH64: bfxil    x19, x20, #0, #64          // encoding: [0x93,0xfe,0x40,0xb3]
+// CHECK-AARCH64: bfxil    x9, x10, #5, #59           // encoding: [0x49,0xfd,0x45,0xb3]
+// CHECK-AARCH64: bfxil    w9, w10, #0, #32           // encoding: [0x49,0x7d,0x00,0x33]
+// CHECK-AARCH64: bfxil    w11, w12, #31, #1          // encoding: [0x8b,0x7d,0x1f,0x33]
+// CHECK-AARCH64: bfxil    w13, w14, #29, #3          // encoding: [0xcd,0x7d,0x1d,0x33]
+// CHECK-AARCH64: bfxil    xzr, xzr, #10, #11         // encoding: [0xff,0x53,0x4a,0xb3]
+
+// CHECK-ARM64: bfm    w9, w10, #0, #0         // encoding: [0x49,0x01,0x00,0x33]
+// CHECK-ARM64: bfm    x2, x3, #63, #63        // encoding: [0x62,0xfc,0x7f,0xb3]
+// CHECK-ARM64: bfm    x19, x20, #0, #63       // encoding: [0x93,0xfe,0x40,0xb3]
+// CHECK-ARM64: bfm    x9, x10, #5, #63        // encoding: [0x49,0xfd,0x45,0xb3]
+// CHECK-ARM64: bfm    w9, w10, #0, #31        // encoding: [0x49,0x7d,0x00,0x33]
+// CHECK-ARM64: bfm    w11, w12, #31, #31      // encoding: [0x8b,0x7d,0x1f,0x33]
+// CHECK-ARM64: bfm    w13, w14, #29, #31      // encoding: [0xcd,0x7d,0x1d,0x33]
+// CHECK-ARM64: bfm    xzr, xzr, #10, #20      // encoding: [0xff,0x53,0x4a,0xb3]
 
         ubfiz w9, w10, #0, #1
         ubfiz x2, x3, #63, #1
@@ -1079,14 +1136,23 @@ _func:
         ubfiz w11, w12, #31, #1
         ubfiz w13, w14, #29, #3
         ubfiz xzr, xzr, #10, #11
-// CHECK: ubfiz    w9, w10, #0, #1            // encoding: [0x49,0x01,0x00,0x53]
-// CHECK: ubfiz    x2, x3, #63, #1            // encoding: [0x62,0x00,0x41,0xd3]
-// CHECK: ubfiz    x19, x20, #0, #64          // encoding: [0x93,0xfe,0x40,0xd3]
-// CHECK: ubfiz    x9, x10, #5, #59           // encoding: [0x49,0xe9,0x7b,0xd3]
-// CHECK: ubfiz    w9, w10, #0, #32           // encoding: [0x49,0x7d,0x00,0x53]
-// CHECK: ubfiz    w11, w12, #31, #1          // encoding: [0x8b,0x01,0x01,0x53]
-// CHECK: ubfiz    w13, w14, #29, #3          // encoding: [0xcd,0x09,0x03,0x53]
-// CHECK: ubfiz    xzr, xzr, #10, #11         // encoding: [0xff,0x2b,0x76,0xd3]
+// CHECK-AARCH64: ubfiz    w9, w10, #0, #1            // encoding: [0x49,0x01,0x00,0x53]
+// CHECK-AARCH64: ubfiz    x2, x3, #63, #1            // encoding: [0x62,0x00,0x41,0xd3]
+// CHECK-AARCH64: ubfiz    x19, x20, #0, #64          // encoding: [0x93,0xfe,0x40,0xd3]
+// CHECK-AARCH64: ubfiz    x9, x10, #5, #59           // encoding: [0x49,0xe9,0x7b,0xd3]
+// CHECK-AARCH64: ubfiz    w9, w10, #0, #32           // encoding: [0x49,0x7d,0x00,0x53]
+// CHECK-AARCH64: ubfiz    w11, w12, #31, #1          // encoding: [0x8b,0x01,0x01,0x53]
+// CHECK-AARCH64: ubfiz    w13, w14, #29, #3          // encoding: [0xcd,0x09,0x03,0x53]
+// CHECK-AARCH64: ubfiz    xzr, xzr, #10, #11         // encoding: [0xff,0x2b,0x76,0xd3]
+
+// CHECK-ARM64: ubfx     w9, w10, #0, #1         // encoding: [0x49,0x01,0x00,0x53]
+// CHECK-ARM64: lsl      x2, x3, #63             // encoding: [0x62,0x00,0x41,0xd3]
+// CHECK-ARM64: lsr      x19, x20, #0            // encoding: [0x93,0xfe,0x40,0xd3]
+// CHECK-ARM64: lsl      x9, x10, #5             // encoding: [0x49,0xe9,0x7b,0xd3]
+// CHECK-ARM64: lsr      w9, w10, #0             // encoding: [0x49,0x7d,0x00,0x53]
+// CHECK-ARM64: lsl      w11, w12, #31           // encoding: [0x8b,0x01,0x01,0x53]
+// CHECK-ARM64: lsl      w13, w14, #29           // encoding: [0xcd,0x09,0x03,0x53]
+// CHECK-ARM64: ubfiz    xzr, xzr, #10, #11      // encoding: [0xff,0x2b,0x76,0xd3]
 
         ubfx w9, w10, #0, #1
         ubfx x2, x3, #63, #1
@@ -1096,15 +1162,23 @@ _func:
         ubfx w11, w12, #31, #1
         ubfx w13, w14, #29, #3
         ubfx xzr, xzr, #10, #11
-// CHECK: ubfx     w9, w10, #0, #1            // encoding: [0x49,0x01,0x00,0x53]
-// CHECK: ubfx     x2, x3, #63, #1            // encoding: [0x62,0xfc,0x7f,0xd3]
-// CHECK: ubfx     x19, x20, #0, #64          // encoding: [0x93,0xfe,0x40,0xd3]
-// CHECK: ubfx     x9, x10, #5, #59           // encoding: [0x49,0xfd,0x45,0xd3]
-// CHECK: ubfx     w9, w10, #0, #32           // encoding: [0x49,0x7d,0x00,0x53]
-// CHECK: ubfx     w11, w12, #31, #1          // encoding: [0x8b,0x7d,0x1f,0x53]
-// CHECK: ubfx     w13, w14, #29, #3          // encoding: [0xcd,0x7d,0x1d,0x53]
-// CHECK: ubfx     xzr, xzr, #10, #11         // encoding: [0xff,0x53,0x4a,0xd3]
-
+// CHECK-AARCH64: ubfx     w9, w10, #0, #1            // encoding: [0x49,0x01,0x00,0x53]
+// CHECK-AARCH64: ubfx     x2, x3, #63, #1            // encoding: [0x62,0xfc,0x7f,0xd3]
+// CHECK-AARCH64: ubfx     x19, x20, #0, #64          // encoding: [0x93,0xfe,0x40,0xd3]
+// CHECK-AARCH64: ubfx     x9, x10, #5, #59           // encoding: [0x49,0xfd,0x45,0xd3]
+// CHECK-AARCH64: ubfx     w9, w10, #0, #32           // encoding: [0x49,0x7d,0x00,0x53]
+// CHECK-AARCH64: ubfx     w11, w12, #31, #1          // encoding: [0x8b,0x7d,0x1f,0x53]
+// CHECK-AARCH64: ubfx     w13, w14, #29, #3          // encoding: [0xcd,0x7d,0x1d,0x53]
+// CHECK-AARCH64: ubfx     xzr, xzr, #10, #11         // encoding: [0xff,0x53,0x4a,0xd3]
+
+// CHECK-ARM64: ubfx    w9, w10, #0, #1         // encoding: [0x49,0x01,0x00,0x53]
+// CHECK-ARM64: lsr     x2, x3, #63             // encoding: [0x62,0xfc,0x7f,0xd3]
+// CHECK-ARM64: lsr     x19, x20, #0            // encoding: [0x93,0xfe,0x40,0xd3]
+// CHECK-ARM64: lsr     x9, x10, #5             // encoding: [0x49,0xfd,0x45,0xd3]
+// CHECK-ARM64: lsr     w9, w10, #0             // encoding: [0x49,0x7d,0x00,0x53]
+// CHECK-ARM64: lsr     w11, w12, #31           // encoding: [0x8b,0x7d,0x1f,0x53]
+// CHECK-ARM64: lsr     w13, w14, #29           // encoding: [0xcd,0x7d,0x1d,0x53]
+// CHECK-ARM64: ubfx    xzr, xzr, #10, #11      // encoding: [0xff,0x53,0x4a,0xd3]
 //------------------------------------------------------------------------------
 // Compare & branch (immediate)
 //------------------------------------------------------------------------------
@@ -1113,21 +1187,34 @@ _func:
         cbz x5, lbl
         cbnz x2, lbl
         cbnz x26, lbl
-// CHECK: cbz      w5, lbl                // encoding: [0x05'A',A,A,0x34'A']
-// CHECK:                                 //   fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr
-// CHECK: cbz      x5, lbl                // encoding: [0x05'A',A,A,0xb4'A']
-// CHECK:                                 //   fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr
-// CHECK: cbnz     x2, lbl                // encoding: [0x02'A',A,A,0xb5'A']
-// CHECK:                                 //   fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr
-// CHECK: cbnz     x26, lbl               // encoding: [0x1a'A',A,A,0xb5'A']
-// CHECK:                                 //   fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr
+// CHECK-AARCH64: cbz      w5, lbl                // encoding: [0x05'A',A,A,0x34'A']
+// CHECK-AARCH64:                                 //   fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr
+// CHECK-AARCH64: cbz      x5, lbl                // encoding: [0x05'A',A,A,0xb4'A']
+// CHECK-AARCH64:                                 //   fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr
+// CHECK-AARCH64: cbnz     x2, lbl                // encoding: [0x02'A',A,A,0xb5'A']
+// CHECK-AARCH64:                                 //   fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr
+// CHECK-AARCH64: cbnz     x26, lbl               // encoding: [0x1a'A',A,A,0xb5'A']
+// CHECK-AARCH64:                                 //   fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr
+// CHECK-ARM64: cbz    w5, lbl                 // encoding: [0bAAA00101,A,A,0x34]
+// CHECK-ARM64:                                 //   fixup A - offset: 0, value: lbl, kind: fixup_arm64_pcrel_branch19
+// CHECK-ARM64: cbz    x5, lbl                 // encoding: [0bAAA00101,A,A,0xb4]
+// CHECK-ARM64:                                 //   fixup A - offset: 0, value: lbl, kind: fixup_arm64_pcrel_branch19
+// CHECK-ARM64: cbnz    x2, lbl                 // encoding: [0bAAA00010,A,A,0xb5]
+// CHECK-ARM64:                                 //   fixup A - offset: 0, value: lbl, kind: fixup_arm64_pcrel_branch19
+// CHECK-ARM64: cbnz    x26, lbl                // encoding: [0bAAA11010,A,A,0xb5]
+// CHECK-ARM64:                                 //   fixup A - offset: 0, value: lbl, kind: fixup_arm64_pcrel_branch19
 
         cbz wzr, lbl
         cbnz xzr, lbl
-// CHECK: cbz      wzr, lbl               // encoding: [0x1f'A',A,A,0x34'A']
-// CHECK:                                 //   fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr
-// CHECK: cbnz     xzr, lbl               // encoding: [0x1f'A',A,A,0xb5'A']
-// CHECK:                                 //   fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr
+// CHECK-AARCH64: cbz      wzr, lbl               // encoding: [0x1f'A',A,A,0x34'A']
+// CHECK-AARCH64:                                 //   fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr
+// CHECK-AARCH64: cbnz     xzr, lbl               // encoding: [0x1f'A',A,A,0xb5'A']
+// CHECK-AARCH64:                                 //   fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr
+
+// CHECK-ARM64: cbz    wzr, lbl                // encoding: [0bAAA11111,A,A,0x34]
+// CHECK-ARM64:                                 //   fixup A - offset: 0, value: lbl, kind: fixup_arm64_pcrel_branch19
+// CHECK-ARM64: cbnz    xzr, lbl                // encoding: [0bAAA11111,A,A,0xb5]
+// CHECK-ARM64:                                 //   fixup A - offset: 0, value: lbl, kind: fixup_arm64_pcrel_branch19
 
         cbz w5, #0
         cbnz x3, #-4
@@ -1159,41 +1246,77 @@ _func:
         b.gt lbl
         b.le lbl
         b.al lbl
-// CHECK: b.eq lbl                        // encoding: [A,A,A,0x54'A']
-// CHECK:                                 //   fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr
-// CHECK: b.ne lbl                        // encoding: [0x01'A',A,A,0x54'A']
-// CHECK:                                 //   fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr
-// CHECK: b.hs lbl                        // encoding: [0x02'A',A,A,0x54'A']
-// CHECK:                                 //   fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr
-// CHECK: b.hs lbl                        // encoding: [0x02'A',A,A,0x54'A']
-// CHECK:                                 //   fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr
-// CHECK: b.lo lbl                        // encoding: [0x03'A',A,A,0x54'A']
-// CHECK:                                 //   fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr
-// CHECK: b.lo lbl                        // encoding: [0x03'A',A,A,0x54'A']
-// CHECK:                                 //   fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr
-// CHECK: b.mi lbl                        // encoding: [0x04'A',A,A,0x54'A']
-// CHECK:                                 //   fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr
-// CHECK: b.pl lbl                        // encoding: [0x05'A',A,A,0x54'A']
-// CHECK:                                 //   fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr
-// CHECK: b.vs lbl                        // encoding: [0x06'A',A,A,0x54'A']
-// CHECK:                                 //   fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr
-// CHECK: b.vc lbl                        // encoding: [0x07'A',A,A,0x54'A']
-// CHECK:                                 //   fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr
-// CHECK: b.hi lbl                        // encoding: [0x08'A',A,A,0x54'A']
-// CHECK:                                 //   fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr
-// CHECK: b.ls lbl                        // encoding: [0x09'A',A,A,0x54'A']
-// CHECK:                                 //   fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr
-// CHECK: b.ge lbl                        // encoding: [0x0a'A',A,A,0x54'A']
-// CHECK:                                 //   fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr
-// CHECK: b.lt lbl                        // encoding: [0x0b'A',A,A,0x54'A']
-// CHECK:                                 //   fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr
-// CHECK: b.gt lbl                        // encoding: [0x0c'A',A,A,0x54'A']
-// CHECK:                                 //   fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr
-// CHECK: b.le lbl                        // encoding: [0x0d'A',A,A,0x54'A']
-// CHECK:                                 //   fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr
-// CHECK: b.al lbl                        // encoding: [0x0e'A',A,A,0x54'A']
-// CHECK:                                 //   fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr
-
+// CHECK-AARCH64: b.eq lbl                        // encoding: [A,A,A,0x54'A']
+// CHECK-AARCH64:                                 //   fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr
+// CHECK-AARCH64: b.ne lbl                        // encoding: [0x01'A',A,A,0x54'A']
+// CHECK-AARCH64:                                 //   fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr
+// CHECK-AARCH64: b.hs lbl                        // encoding: [0x02'A',A,A,0x54'A']
+// CHECK-AARCH64:                                 //   fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr
+// CHECK-AARCH64: b.hs lbl                        // encoding: [0x02'A',A,A,0x54'A']
+// CHECK-AARCH64:                                 //   fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr
+// CHECK-AARCH64: b.lo lbl                        // encoding: [0x03'A',A,A,0x54'A']
+// CHECK-AARCH64:                                 //   fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr
+// CHECK-AARCH64: b.lo lbl                        // encoding: [0x03'A',A,A,0x54'A']
+// CHECK-AARCH64:                                 //   fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr
+// CHECK-AARCH64: b.mi lbl                        // encoding: [0x04'A',A,A,0x54'A']
+// CHECK-AARCH64:                                 //   fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr
+// CHECK-AARCH64: b.pl lbl                        // encoding: [0x05'A',A,A,0x54'A']
+// CHECK-AARCH64:                                 //   fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr
+// CHECK-AARCH64: b.vs lbl                        // encoding: [0x06'A',A,A,0x54'A']
+// CHECK-AARCH64:                                 //   fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr
+// CHECK-AARCH64: b.vc lbl                        // encoding: [0x07'A',A,A,0x54'A']
+// CHECK-AARCH64:                                 //   fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr
+// CHECK-AARCH64: b.hi lbl                        // encoding: [0x08'A',A,A,0x54'A']
+// CHECK-AARCH64:                                 //   fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr
+// CHECK-AARCH64: b.ls lbl                        // encoding: [0x09'A',A,A,0x54'A']
+// CHECK-AARCH64:                                 //   fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr
+// CHECK-AARCH64: b.ge lbl                        // encoding: [0x0a'A',A,A,0x54'A']
+// CHECK-AARCH64:                                 //   fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr
+// CHECK-AARCH64: b.lt lbl                        // encoding: [0x0b'A',A,A,0x54'A']
+// CHECK-AARCH64:                                 //   fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr
+// CHECK-AARCH64: b.gt lbl                        // encoding: [0x0c'A',A,A,0x54'A']
+// CHECK-AARCH64:                                 //   fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr
+// CHECK-AARCH64: b.le lbl                        // encoding: [0x0d'A',A,A,0x54'A']
+// CHECK-AARCH64:                                 //   fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr
+// CHECK-AARCH64: b.al lbl                        // encoding: [0x0e'A',A,A,0x54'A']
+// CHECK-AARCH64:                                 //   fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr
+
+// CHECK-ARM64: b.eq lbl                     // encoding: [0bAAA00000,A,A,0x54]
+// CHECK-ARM64:                              //   fixup A - offset: 0, value: lbl, kind: fixup_arm64_pcrel_branch19
+// CHECK-ARM64: b.ne lbl                     // encoding: [0bAAA00001,A,A,0x54]
+// CHECK-ARM64:                              //   fixup A - offset: 0, value: lbl, kind: fixup_arm64_pcrel_branch19
+// CHECK-ARM64: b.hs lbl                     // encoding: [0bAAA00010,A,A,0x54]
+// CHECK-ARM64:                              //   fixup A - offset: 0, value: lbl, kind: fixup_arm64_pcrel_branch19
+// CHECK-ARM64: b.hs lbl                     // encoding: [0bAAA00010,A,A,0x54]
+// CHECK-ARM64:                              //   fixup A - offset: 0, value: lbl, kind: fixup_arm64_pcrel_branch19
+// CHECK-ARM64: b.lo lbl                     // encoding: [0bAAA00011,A,A,0x54]
+// CHECK-ARM64:                              //   fixup A - offset: 0, value: lbl, kind: fixup_arm64_pcrel_branch19
+// CHECK-ARM64: b.lo lbl                     // encoding: [0bAAA00011,A,A,0x54]
+// CHECK-ARM64:                              //   fixup A - offset: 0, value: lbl, kind: fixup_arm64_pcrel_branch19
+// CHECK-ARM64: b.mi lbl                     // encoding: [0bAAA00100,A,A,0x54]
+// CHECK-ARM64:                              //   fixup A - offset: 0, value: lbl, kind: fixup_arm64_pcrel_branch19
+// CHECK-ARM64: b.pl lbl                     // encoding: [0bAAA00101,A,A,0x54]
+// CHECK-ARM64:                              //   fixup A - offset: 0, value: lbl, kind: fixup_arm64_pcrel_branch19
+// CHECK-ARM64: b.vs lbl                     // encoding: [0bAAA00110,A,A,0x54]
+// CHECK-ARM64:                              //   fixup A - offset: 0, value: lbl, kind: fixup_arm64_pcrel_branch19
+// CHECK-ARM64: b.vc lbl                     // encoding: [0bAAA00111,A,A,0x54]
+// CHECK-ARM64:                              //   fixup A - offset: 0, value: lbl, kind: fixup_arm64_pcrel_branch19
+// CHECK-ARM64: b.hi lbl                     // encoding: [0bAAA01000,A,A,0x54]
+// CHECK-ARM64:                              //   fixup A - offset: 0, value: lbl, kind: fixup_arm64_pcrel_branch19
+// CHECK-ARM64: b.ls lbl                     // encoding: [0bAAA01001,A,A,0x54]
+// CHECK-ARM64:                              //   fixup A - offset: 0, value: lbl, kind: fixup_arm64_pcrel_branch19
+// CHECK-ARM64: b.ge lbl                     // encoding: [0bAAA01010,A,A,0x54]
+// CHECK-ARM64:                              //   fixup A - offset: 0, value: lbl, kind: fixup_arm64_pcrel_branch19
+// CHECK-ARM64: b.lt lbl                     // encoding: [0bAAA01011,A,A,0x54]
+// CHECK-ARM64:                              //   fixup A - offset: 0, value: lbl, kind: fixup_arm64_pcrel_branch19
+// CHECK-ARM64: b.gt lbl                     // encoding: [0bAAA01100,A,A,0x54]
+// CHECK-ARM64:                              //   fixup A - offset: 0, value: lbl, kind: fixup_arm64_pcrel_branch19
+// CHECK-ARM64: b.le lbl                     // encoding: [0bAAA01101,A,A,0x54]
+// CHECK-ARM64:                              //   fixup A - offset: 0, value: lbl, kind: fixup_arm64_pcrel_branch19
+// CHECK-ARM64: b.al lbl                     // encoding: [0bAAA01110,A,A,0x54]
+// CHECK-ARM64:                              //   fixup A - offset: 0, value: lbl, kind: fixup_arm64_pcrel_branch19
+
+        //  ARM64 has these in a separate file
         beq lbl
         bne lbl
         bcs lbl
@@ -1211,40 +1334,40 @@ _func:
         bgt lbl
         ble lbl
         bal lbl
-// CHECK: b.eq lbl                        // encoding: [A,A,A,0x54'A']
-// CHECK:                                 //   fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr
-// CHECK: b.ne lbl                        // encoding: [0x01'A',A,A,0x54'A']
-// CHECK:                                 //   fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr
-// CHECK: b.hs lbl                        // encoding: [0x02'A',A,A,0x54'A']
-// CHECK:                                 //   fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr
-// CHECK: b.hs lbl                        // encoding: [0x02'A',A,A,0x54'A']
-// CHECK:                                 //   fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr
-// CHECK: b.lo lbl                        // encoding: [0x03'A',A,A,0x54'A']
-// CHECK:                                 //   fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr
-// CHECK: b.lo lbl                        // encoding: [0x03'A',A,A,0x54'A']
-// CHECK:                                 //   fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr
-// CHECK: b.mi lbl                        // encoding: [0x04'A',A,A,0x54'A']
-// CHECK:                                 //   fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr
-// CHECK: b.pl lbl                        // encoding: [0x05'A',A,A,0x54'A']
-// CHECK:                                 //   fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr
-// CHECK: b.vs lbl                        // encoding: [0x06'A',A,A,0x54'A']
-// CHECK:                                 //   fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr
-// CHECK: b.vc lbl                        // encoding: [0x07'A',A,A,0x54'A']
-// CHECK:                                 //   fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr
-// CHECK: b.hi lbl                        // encoding: [0x08'A',A,A,0x54'A']
-// CHECK:                                 //   fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr
-// CHECK: b.ls lbl                        // encoding: [0x09'A',A,A,0x54'A']
-// CHECK:                                 //   fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr
-// CHECK: b.ge lbl                        // encoding: [0x0a'A',A,A,0x54'A']
-// CHECK:                                 //   fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr
-// CHECK: b.lt lbl                        // encoding: [0x0b'A',A,A,0x54'A']
-// CHECK:                                 //   fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr
-// CHECK: b.gt lbl                        // encoding: [0x0c'A',A,A,0x54'A']
-// CHECK:                                 //   fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr
-// CHECK: b.le lbl                        // encoding: [0x0d'A',A,A,0x54'A']
-// CHECK:                                 //   fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr
-// CHECK: b.al lbl                        // encoding: [0x0e'A',A,A,0x54'A']
-// CHECK:                                 //   fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr
+// CHECK-AARCH64: b.eq lbl                        // encoding: [A,A,A,0x54'A']
+// CHECK-AARCH64:                                 //   fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr
+// CHECK-AARCH64: b.ne lbl                        // encoding: [0x01'A',A,A,0x54'A']
+// CHECK-AARCH64:                                 //   fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr
+// CHECK-AARCH64: b.hs lbl                        // encoding: [0x02'A',A,A,0x54'A']
+// CHECK-AARCH64:                                 //   fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr
+// CHECK-AARCH64: b.hs lbl                        // encoding: [0x02'A',A,A,0x54'A']
+// CHECK-AARCH64:                                 //   fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr
+// CHECK-AARCH64: b.lo lbl                        // encoding: [0x03'A',A,A,0x54'A']
+// CHECK-AARCH64:                                 //   fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr
+// CHECK-AARCH64: b.lo lbl                        // encoding: [0x03'A',A,A,0x54'A']
+// CHECK-AARCH64:                                 //   fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr
+// CHECK-AARCH64: b.mi lbl                        // encoding: [0x04'A',A,A,0x54'A']
+// CHECK-AARCH64:                                 //   fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr
+// CHECK-AARCH64: b.pl lbl                        // encoding: [0x05'A',A,A,0x54'A']
+// CHECK-AARCH64:                                 //   fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr
+// CHECK-AARCH64: b.vs lbl                        // encoding: [0x06'A',A,A,0x54'A']
+// CHECK-AARCH64:                                 //   fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr
+// CHECK-AARCH64: b.vc lbl                        // encoding: [0x07'A',A,A,0x54'A']
+// CHECK-AARCH64:                                 //   fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr
+// CHECK-AARCH64: b.hi lbl                        // encoding: [0x08'A',A,A,0x54'A']
+// CHECK-AARCH64:                                 //   fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr
+// CHECK-AARCH64: b.ls lbl                        // encoding: [0x09'A',A,A,0x54'A']
+// CHECK-AARCH64:                                 //   fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr
+// CHECK-AARCH64: b.ge lbl                        // encoding: [0x0a'A',A,A,0x54'A']
+// CHECK-AARCH64:                                 //   fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr
+// CHECK-AARCH64: b.lt lbl                        // encoding: [0x0b'A',A,A,0x54'A']
+// CHECK-AARCH64:                                 //   fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr
+// CHECK-AARCH64: b.gt lbl                        // encoding: [0x0c'A',A,A,0x54'A']
+// CHECK-AARCH64:                                 //   fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr
+// CHECK-AARCH64: b.le lbl                        // encoding: [0x0d'A',A,A,0x54'A']
+// CHECK-AARCH64:                                 //   fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr
+// CHECK-AARCH64: b.al lbl                        // encoding: [0x0e'A',A,A,0x54'A']
+// CHECK-AARCH64:                                 //   fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr
 
         b.eq #0
         b.lt #-4
@@ -1699,23 +1822,23 @@ _func:
         svc #0
         svc #65535
 // CHECK: svc      #0                         // encoding: [0x01,0x00,0x00,0xd4]
-// CHECK: svc      #65535                     // encoding: [0xe1,0xff,0x1f,0xd4]
+// CHECK: svc      #{{65535|0xffff}}          // encoding: [0xe1,0xff,0x1f,0xd4]
 
         hvc #1
         smc #12000
         brk #12
         hlt #123
-// CHECK: hvc      #1                         // encoding: [0x22,0x00,0x00,0xd4]
-// CHECK: smc      #12000                     // encoding: [0x03,0xdc,0x05,0xd4]
-// CHECK: brk      #12                        // encoding: [0x80,0x01,0x20,0xd4]
-// CHECK: hlt      #123                       // encoding: [0x60,0x0f,0x40,0xd4]
+// CHECK: hvc      #{{1|0x1}}                 // encoding: [0x22,0x00,0x00,0xd4]
+// CHECK: smc      #{{12000|0x2ee0}}          // encoding: [0x03,0xdc,0x05,0xd4]
+// CHECK: brk      #{{12|0xc}}                // encoding: [0x80,0x01,0x20,0xd4]
+// CHECK: hlt      #{{123|0x7b}}              // encoding: [0x60,0x0f,0x40,0xd4]
 
         dcps1 #42
         dcps2 #9
         dcps3 #1000
-// CHECK: dcps1    #42                        // encoding: [0x41,0x05,0xa0,0xd4]
-// CHECK: dcps2    #9                         // encoding: [0x22,0x01,0xa0,0xd4]
-// CHECK: dcps3    #1000                      // encoding: [0x03,0x7d,0xa0,0xd4]
+// CHECK: dcps1    #{{42|0x2a}}               // encoding: [0x41,0x05,0xa0,0xd4]
+// CHECK: dcps2    #{{9|0x9}}                 // encoding: [0x22,0x01,0xa0,0xd4]
+// CHECK: dcps3    #{{1000|0x3e8}}            // encoding: [0x03,0x7d,0xa0,0xd4]
 
         dcps1
         dcps2
@@ -2176,7 +2299,7 @@ _func:
 
         fmov x3, v12.d[1]
         fmov v1.d[1], x19
-        fmov v3.2d[1], xzr
+        fmov v3.d[1], xzr
 // CHECK: fmov     x3, v12.d[1]               // encoding: [0x83,0x01,0xae,0x9e]
 // CHECK: fmov     v1.d[1], x19               // encoding: [0x61,0x02,0xaf,0x9e]
 // CHECK: fmov     v3.d[1], xzr               // encoding: [0xe3,0x03,0xaf,0x9e]
@@ -2188,20 +2311,20 @@ _func:
         fmov s2, #0.125
         fmov s3, #1.0
         fmov d30, #16.0
-// CHECK: fmov     s2, #0.12500000            // encoding: [0x02,0x10,0x28,0x1e]
-// CHECK: fmov     s3, #1.00000000            // encoding: [0x03,0x10,0x2e,0x1e]
-// CHECK: fmov     d30, #16.00000000          // encoding: [0x1e,0x10,0x66,0x1e]
+// CHECK: fmov     s2, #{{0.12500000|1.250*e-01}}            // encoding: [0x02,0x10,0x28,0x1e]
+// CHECK: fmov     s3, #{{1.00000000|1.0*e\+00}}            // encoding: [0x03,0x10,0x2e,0x1e]
+// CHECK: fmov     d30, #{{16.00000000|1.60*e\+01}}          // encoding: [0x1e,0x10,0x66,0x1e]
 
         fmov s4, #1.0625
         fmov d10, #1.9375
-// CHECK: fmov     s4, #1.06250000            // encoding: [0x04,0x30,0x2e,0x1e]
-// CHECK: fmov     d10, #1.93750000           // encoding: [0x0a,0xf0,0x6f,0x1e]
+// CHECK: fmov     s4, #{{1.06250*(e\+00)?}}            // encoding: [0x04,0x30,0x2e,0x1e]
+// CHECK: fmov     d10, #{{1.93750*(e\+00)?}}           // encoding: [0x0a,0xf0,0x6f,0x1e]
 
         fmov s12, #-1.0
-// CHECK: fmov     s12, #-1.00000000          // encoding: [0x0c,0x10,0x3e,0x1e]
+// CHECK: fmov     s12, #{{-1.0*(e\+00)?}}          // encoding: [0x0c,0x10,0x3e,0x1e]
 
         fmov d16, #8.5
-// CHECK: fmov     d16, #8.50000000           // encoding: [0x10,0x30,0x64,0x1e]
+// CHECK: fmov     d16, #{{8.50*(e\+00)?}}          // encoding: [0x10,0x30,0x64,0x1e]
 
 //------------------------------------------------------------------------------
 // Load-register (literal)
@@ -2209,22 +2332,36 @@ _func:
         ldr w3, here
         ldr x29, there
         ldrsw xzr, everywhere
-// CHECK: ldr     w3, here                // encoding: [0x03'A',A,A,0x18'A']
-// CHECK:                                 //   fixup A - offset: 0, value: here, kind: fixup_a64_ld_prel
-// CHECK: ldr     x29, there              // encoding: [0x1d'A',A,A,0x58'A']
-// CHECK:                                 //   fixup A - offset: 0, value: there, kind: fixup_a64_ld_prel
-// CHECK: ldrsw   xzr, everywhere         // encoding: [0x1f'A',A,A,0x98'A']
-// CHECK:                                 //   fixup A - offset: 0, value: everywhere, kind: fixup_a64_ld_prel
+// CHECK-AARCH64: ldr     w3, here                // encoding: [0x03'A',A,A,0x18'A']
+// CHECK-AARCH64:                                 //   fixup A - offset: 0, value: here, kind: fixup_a64_ld_prel
+// CHECK-AARCH64: ldr     x29, there              // encoding: [0x1d'A',A,A,0x58'A']
+// CHECK-AARCH64:                                 //   fixup A - offset: 0, value: there, kind: fixup_a64_ld_prel
+// CHECK-AARCH64: ldrsw   xzr, everywhere         // encoding: [0x1f'A',A,A,0x98'A']
+// CHECK-AARCH64:                                 //   fixup A - offset: 0, value: everywhere, kind: fixup_a64_ld_prel
+
+// CHECK-ARM64: ldr    w3, here                // encoding: [0bAAA00011,A,A,0x18]
+// CHECK-ARM64:                                 //   fixup A - offset: 0, value: here, kind: fixup_arm64_ldr_pcrel_imm19
+// CHECK-ARM64: ldr    x29, there              // encoding: [0bAAA11101,A,A,0x58]
+// CHECK-ARM64:                                 //   fixup A - offset: 0, value: there, kind: fixup_arm64_ldr_pcrel_imm19
+// CHECK-ARM64: ldrsw    xzr, everywhere         // encoding: [0bAAA11111,A,A,0x98]
+// CHECK-ARM64:                                 //   fixup A - offset: 0, value: everywhere, kind: fixup_arm64_ldr_pcrel_imm19
 
         ldr s0, who_knows
         ldr d0, i_dont
         ldr q0, there_must_be_a_better_way
-// CHECK: ldr     s0, who_knows           // encoding: [A,A,A,0x1c'A']
-// CHECK:                                 //   fixup A - offset: 0, value: who_knows, kind: fixup_a64_ld_prel
-// CHECK: ldr     d0, i_dont              // encoding: [A,A,A,0x5c'A']
-// CHECK:                                 //   fixup A - offset: 0, value: i_dont, kind: fixup_a64_ld_prel
-// CHECK: ldr     q0, there_must_be_a_better_way // encoding: [A,A,A,0x9c'A']
-// CHECK:                                 //   fixup A - offset: 0, value: there_must_be_a_better_way, kind: fixup_a64_ld_prel
+// CHECK-AARCH64: ldr     s0, who_knows           // encoding: [A,A,A,0x1c'A']
+// CHECK-AARCH64:                                 //   fixup A - offset: 0, value: who_knows, kind: fixup_a64_ld_prel
+// CHECK-AARCH64: ldr     d0, i_dont              // encoding: [A,A,A,0x5c'A']
+// CHECK-AARCH64:                                 //   fixup A - offset: 0, value: i_dont, kind: fixup_a64_ld_prel
+// CHECK-AARCH64: ldr     q0, there_must_be_a_better_way // encoding: [A,A,A,0x9c'A']
+// CHECK-AARCH64:                                 //   fixup A - offset: 0, value: there_must_be_a_better_way, kind: fixup_a64_ld_prel
+
+// CHECK-ARM64: ldr    s0, who_knows           // encoding: [0bAAA00000,A,A,0x1c]
+// CHECK-ARM64:                                 //   fixup A - offset: 0, value: who_knows, kind: fixup_arm64_ldr_pcrel_imm19
+// CHECK-ARM64: ldr    d0, i_dont              // encoding: [0bAAA00000,A,A,0x5c]
+// CHECK-ARM64:                                 //   fixup A - offset: 0, value: i_dont, kind: fixup_arm64_ldr_pcrel_imm19
+// CHECK-ARM64: ldr    q0, there_must_be_a_better_way // encoding: [0bAAA00000,A,A,0x9c]
+// CHECK-ARM64:                                 //   fixup A - offset: 0, value: there_must_be_a_better_way, kind: fixup_arm64_ldr_pcrel_imm19
 
         ldr w0, #1048572
         ldr x10, #-1048576
@@ -2233,32 +2370,15 @@ _func:
 
         prfm pldl1strm, nowhere
         prfm #22, somewhere
-// CHECK: prfm    pldl1strm, nowhere      // encoding: [0x01'A',A,A,0xd8'A']
-// CHECK:                                 //   fixup A - offset: 0, value: nowhere, kind: fixup_a64_ld_prel
-// CHECK: prfm    #22, somewhere          // encoding: [0x16'A',A,A,0xd8'A']
-// CHECK:                                 //   fixup A - offset: 0, value: somewhere, kind: fixup_a64_ld_prel
-
-//------------------------------------------------------------------------------
-// Floating-point immediate
-//------------------------------------------------------------------------------
-
-        fmov s2, #0.125
-        fmov s3, #1.0
-        fmov d30, #16.0
-// CHECK: fmov     s2, #0.12500000            // encoding: [0x02,0x10,0x28,0x1e]
-// CHECK: fmov     s3, #1.00000000            // encoding: [0x03,0x10,0x2e,0x1e]
-// CHECK: fmov     d30, #16.00000000          // encoding: [0x1e,0x10,0x66,0x1e]
-
-        fmov s4, #1.0625
-        fmov d10, #1.9375
-// CHECK: fmov     s4, #1.06250000            // encoding: [0x04,0x30,0x2e,0x1e]
-// CHECK: fmov     d10, #1.93750000           // encoding: [0x0a,0xf0,0x6f,0x1e]
+// CHECK-AARCH64: prfm    pldl1strm, nowhere      // encoding: [0x01'A',A,A,0xd8'A']
+// CHECK-AARCH64:                                 //   fixup A - offset: 0, value: nowhere, kind: fixup_a64_ld_prel
+// CHECK-AARCH64: prfm    #22, somewhere          // encoding: [0x16'A',A,A,0xd8'A']
+// CHECK-AARCH64:                                 //   fixup A - offset: 0, value: somewhere, kind: fixup_a64_ld_prel
 
-        fmov s12, #-1.0
-// CHECK: fmov     s12, #-1.00000000          // encoding: [0x0c,0x10,0x3e,0x1e]
-
-        fmov d16, #8.5
-// CHECK: fmov     d16, #8.50000000           // encoding: [0x10,0x30,0x64,0x1e]
+// CHECK-ARM64: prfm    pldl1strm, nowhere      // encoding: [0bAAA00001,A,A,0xd8]
+// CHECK-ARM64:                                 //   fixup A - offset: 0, value: nowhere, kind: fixup_arm64_ldr_pcrel_imm19
+// CHECK-ARM64: prfm    #22, somewhere          // encoding: [0bAAA10110,A,A,0xd8]
+// CHECK-ARM64:                                 //   fixup A - offset: 0, value: somewhere, kind: fixup_arm64_ldr_pcrel_imm19
 
 //------------------------------------------------------------------------------
 // Load/store exclusive
@@ -2473,18 +2593,31 @@ _func:
         ldrsw x15, [x5, #:lo12:sym]
         ldr x15, [x5, #:lo12:sym]
         ldr q3, [x2, #:lo12:sym]
-// CHECK: str     x15, [x5, #:lo12:sym]   // encoding: [0xaf'A',A,A,0xf9'A']
-// CHECK:                                         //   fixup A - offset: 0, value: :lo12:sym, kind: fixup_a64_ldst64_lo12
-// CHECK: ldrb    w15, [x5, #:lo12:sym]   // encoding: [0xaf'A',A,0x40'A',0x39'A']
-// CHECK:                                         //   fixup A - offset: 0, value: :lo12:sym, kind: fixup_a64_ldst8_lo12
-// CHECK: ldrsh   x15, [x5, #:lo12:sym]   // encoding: [0xaf'A',A,0x80'A',0x79'A']
-// CHECK:                                         //   fixup A - offset: 0, value: :lo12:sym, kind: fixup_a64_ldst16_lo12
-// CHECK: ldrsw   x15, [x5, #:lo12:sym]   // encoding: [0xaf'A',A,0x80'A',0xb9'A']
-// CHECK:                                         //   fixup A - offset: 0, value: :lo12:sym, kind: fixup_a64_ldst32_lo12
-// CHECK: ldr     x15, [x5, #:lo12:sym]   // encoding: [0xaf'A',A,0x40'A',0xf9'A']
-// CHECK:                                         //   fixup A - offset: 0, value: :lo12:sym, kind: fixup_a64_ldst64_lo12
-// CHECK: ldr     q3, [x2, #:lo12:sym]    // encoding: [0x43'A',A,0xc0'A',0x3d'A']
-// CHECK:                                         //   fixup A - offset: 0, value: :lo12:sym, kind: fixup_a64_ldst128_lo12
+// CHECK-AARCH64: str     x15, [x5, #:lo12:sym]   // encoding: [0xaf'A',A,A,0xf9'A']
+// CHECK-AARCH64:                                         //   fixup A - offset: 0, value: :lo12:sym, kind: fixup_a64_ldst64_lo12
+// CHECK-AARCH64: ldrb    w15, [x5, #:lo12:sym]   // encoding: [0xaf'A',A,0x40'A',0x39'A']
+// CHECK-AARCH64:                                         //   fixup A - offset: 0, value: :lo12:sym, kind: fixup_a64_ldst8_lo12
+// CHECK-AARCH64: ldrsh   x15, [x5, #:lo12:sym]   // encoding: [0xaf'A',A,0x80'A',0x79'A']
+// CHECK-AARCH64:                                         //   fixup A - offset: 0, value: :lo12:sym, kind: fixup_a64_ldst16_lo12
+// CHECK-AARCH64: ldrsw   x15, [x5, #:lo12:sym]   // encoding: [0xaf'A',A,0x80'A',0xb9'A']
+// CHECK-AARCH64:                                         //   fixup A - offset: 0, value: :lo12:sym, kind: fixup_a64_ldst32_lo12
+// CHECK-AARCH64: ldr     x15, [x5, #:lo12:sym]   // encoding: [0xaf'A',A,0x40'A',0xf9'A']
+// CHECK-AARCH64:                                         //   fixup A - offset: 0, value: :lo12:sym, kind: fixup_a64_ldst64_lo12
+// CHECK-AARCH64: ldr     q3, [x2, #:lo12:sym]    // encoding: [0x43'A',A,0xc0'A',0x3d'A']
+// CHECK-AARCH64:                                         //   fixup A - offset: 0, value: :lo12:sym, kind: fixup_a64_ldst128_lo12
+
+// CHECK-ARM64: str    x15, [x5, :lo12:sym]    // encoding: [0xaf,0bAAAAAA00,0b00AAAAAA,0xf9]
+// CHECK-ARM64:                                 //   fixup A - offset: 0, value: :lo12:sym, kind: fixup_arm64_ldst_imm12_scale8
+// CHECK-ARM64: ldrb    w15, [x5, :lo12:sym]    // encoding: [0xaf,0bAAAAAA00,0b01AAAAAA,0x39]
+// CHECK-ARM64:                                 //   fixup A - offset: 0, value: :lo12:sym, kind: fixup_arm64_ldst_imm12_scale1
+// CHECK-ARM64: ldrsh    x15, [x5, :lo12:sym]    // encoding: [0xaf,0bAAAAAA00,0b10AAAAAA,0x79]
+// CHECK-ARM64:                                 //   fixup A - offset: 0, value: :lo12:sym, kind: fixup_arm64_ldst_imm12_scale2
+// CHECK-ARM64: ldrsw    x15, [x5, :lo12:sym]    // encoding: [0xaf,0bAAAAAA00,0b10AAAAAA,0xb9]
+// CHECK-ARM64:                                 //   fixup A - offset: 0, value: :lo12:sym, kind: fixup_arm64_ldst_imm12_scale4
+// CHECK-ARM64: ldr    x15, [x5, :lo12:sym]    // encoding: [0xaf,0bAAAAAA00,0b01AAAAAA,0xf9]
+// CHECK-ARM64:                                 //   fixup A - offset: 0, value: :lo12:sym, kind: fixup_arm64_ldst_imm12_scale8
+// CHECK-ARM64: ldr    q3, [x2, :lo12:sym]     // encoding: [0x43,0bAAAAAA00,0b11AAAAAA,0x3d]
+// CHECK-ARM64:                                 //   fixup A - offset: 0, value: :lo12:sym, kind: fixup_arm64_ldst_imm12_scale16
 
         prfm pldl1keep, [sp, #8]
         prfm pldl1strm, [x3]
@@ -2506,24 +2639,24 @@ _func:
         prfm pstl3strm, [x6]
         prfm #15, [sp]
 // CHECK: prfm    pldl1keep, [sp, #8]     // encoding: [0xe0,0x07,0x80,0xf9]
-// CHECK: prfm    pldl1strm, [x3, #0]     // encoding: [0x61,0x00,0x80,0xf9]
+// CHECK: prfm    pldl1strm, [x3{{(, #0)?}}]     // encoding: [0x61,0x00,0x80,0xf9]
 // CHECK: prfm    pldl2keep, [x5, #16]    // encoding: [0xa2,0x08,0x80,0xf9]
-// CHECK: prfm    pldl2strm, [x2, #0]     // encoding: [0x43,0x00,0x80,0xf9]
-// CHECK: prfm    pldl3keep, [x5, #0]     // encoding: [0xa4,0x00,0x80,0xf9]
-// CHECK: prfm    pldl3strm, [x6, #0]     // encoding: [0xc5,0x00,0x80,0xf9]
+// CHECK: prfm    pldl2strm, [x2{{(, #0)?}}]     // encoding: [0x43,0x00,0x80,0xf9]
+// CHECK: prfm    pldl3keep, [x5{{(, #0)?}}]     // encoding: [0xa4,0x00,0x80,0xf9]
+// CHECK: prfm    pldl3strm, [x6{{(, #0)?}}]     // encoding: [0xc5,0x00,0x80,0xf9]
 // CHECK: prfm    plil1keep, [sp, #8]     // encoding: [0xe8,0x07,0x80,0xf9]
-// CHECK: prfm    plil1strm, [x3, #0]     // encoding: [0x69,0x00,0x80,0xf9]
+// CHECK: prfm    plil1strm, [x3{{(, #0)?}}]     // encoding: [0x69,0x00,0x80,0xf9]
 // CHECK: prfm    plil2keep, [x5, #16]    // encoding: [0xaa,0x08,0x80,0xf9]
-// CHECK: prfm    plil2strm, [x2, #0]     // encoding: [0x4b,0x00,0x80,0xf9]
-// CHECK: prfm    plil3keep, [x5, #0]     // encoding: [0xac,0x00,0x80,0xf9]
-// CHECK: prfm    plil3strm, [x6, #0]     // encoding: [0xcd,0x00,0x80,0xf9]
+// CHECK: prfm    plil2strm, [x2{{(, #0)?}}]     // encoding: [0x4b,0x00,0x80,0xf9]
+// CHECK: prfm    plil3keep, [x5{{(, #0)?}}]     // encoding: [0xac,0x00,0x80,0xf9]
+// CHECK: prfm    plil3strm, [x6{{(, #0)?}}]     // encoding: [0xcd,0x00,0x80,0xf9]
 // CHECK: prfm    pstl1keep, [sp, #8]     // encoding: [0xf0,0x07,0x80,0xf9]
-// CHECK: prfm    pstl1strm, [x3, #0]     // encoding: [0x71,0x00,0x80,0xf9]
+// CHECK: prfm    pstl1strm, [x3{{(, #0)?}}]     // encoding: [0x71,0x00,0x80,0xf9]
 // CHECK: prfm    pstl2keep, [x5, #16]    // encoding: [0xb2,0x08,0x80,0xf9]
-// CHECK: prfm    pstl2strm, [x2, #0]     // encoding: [0x53,0x00,0x80,0xf9]
-// CHECK: prfm    pstl3keep, [x5, #0]     // encoding: [0xb4,0x00,0x80,0xf9]
-// CHECK: prfm    pstl3strm, [x6, #0]     // encoding: [0xd5,0x00,0x80,0xf9]
-// CHECK: prfm    #15, [sp, #0]           // encoding: [0xef,0x03,0x80,0xf9]
+// CHECK: prfm    pstl2strm, [x2{{(, #0)?}}]     // encoding: [0x53,0x00,0x80,0xf9]
+// CHECK: prfm    pstl3keep, [x5{{(, #0)?}}]     // encoding: [0xb4,0x00,0x80,0xf9]
+// CHECK: prfm    pstl3strm, [x6{{(, #0)?}}]     // encoding: [0xd5,0x00,0x80,0xf9]
+// CHECK: prfm    #15, [sp{{(, #0)?}}]           // encoding: [0xef,0x03,0x80,0xf9]
 
 //// Floating-point versions
 
@@ -2636,7 +2769,7 @@ _func:
 // CHECK: ldr      x17, [x23, w9, sxtw]       // encoding: [0xf1,0xca,0x69,0xf8]
 // CHECK: ldr      x18, [x22, w10, sxtw]      // encoding: [0xd2,0xca,0x6a,0xf8]
 // CHECK: str      d19, [x21, wzr, sxtw #3]   // encoding: [0xb3,0xda,0x3f,0xfc]
-// CHECK: prfm     #6, [x0, x5, lsl #0]       // encoding: [0x06,0x68,0xa5,0xf8]
+// CHECK: prfm     #6, [x0, x5{{(, lsl #0)?}}]       // encoding: [0x06,0x68,0xa5,0xf8]
 
         ldr q3, [sp, x5]
         ldr q9, [x27, x6, lsl #0]
@@ -3218,15 +3351,15 @@ _func:
         ands wzr, w18, #0xcccccccc
         ands w19, w20, #0x33333333
         ands w21, w22, #0x99999999
-// CHECK: ands     wzr, w18, #0xcccccccc      // encoding: [0x5f,0xe6,0x02,0x72]
+// CHECK: {{ands wzr,|tst}} w18, #0xcccccccc      // encoding: [0x5f,0xe6,0x02,0x72]
 // CHECK: ands     w19, w20, #0x33333333      // encoding: [0x93,0xe6,0x00,0x72]
 // CHECK: ands     w21, w22, #0x99999999      // encoding: [0xd5,0xe6,0x01,0x72]
 
         // 2 bit replication width
         tst w3, #0xaaaaaaaa
         tst wzr, #0x55555555
-// CHECK: ands     wzr, w3, #0xaaaaaaaa       // encoding: [0x7f,0xf0,0x01,0x72]
-// CHECK: ands     wzr, wzr, #0x55555555      // encoding: [0xff,0xf3,0x00,0x72]
+// CHECK: {{ands wzr,|tst}} w3, #0xaaaaaaaa       // encoding: [0x7f,0xf0,0x01,0x72]
+// CHECK: {{ands wzr,|tst}} wzr, #0x55555555      // encoding: [0xff,0xf3,0x00,0x72]
 
         // 64 bit replication-width
         eor x3, x5, #0xffffffffc000000
@@ -3264,15 +3397,15 @@ _func:
         ands xzr, x18, #0xcccccccccccccccc
         ands x19, x20, #0x3333333333333333
         ands x21, x22, #0x9999999999999999
-// CHECK: ands     xzr, x18, #0xcccccccccccccccc // encoding: [0x5f,0xe6,0x02,0xf2]
+// CHECK: {{ands xzr,|tst}} x18, #0xcccccccccccccccc // encoding: [0x5f,0xe6,0x02,0xf2]
 // CHECK: ands     x19, x20, #0x3333333333333333 // encoding: [0x93,0xe6,0x00,0xf2]
 // CHECK: ands     x21, x22, #0x9999999999999999 // encoding: [0xd5,0xe6,0x01,0xf2]
 
         // 2 bit replication-width
         tst x3, #0xaaaaaaaaaaaaaaaa
         tst xzr, #0x5555555555555555
-// CHECK: ands     xzr, x3, #0xaaaaaaaaaaaaaaaa    // encoding: [0x7f,0xf0,0x01,0xf2]
-// CHECK: ands     xzr, xzr, #0x5555555555555555   // encoding: [0xff,0xf3,0x00,0xf2]
+// CHECK: {{ands xzr,|tst}} x3, #0xaaaaaaaaaaaaaaaa    // encoding: [0x7f,0xf0,0x01,0xf2]
+// CHECK: {{ands xzr,|tst}} xzr, #0x5555555555555555   // encoding: [0xff,0xf3,0x00,0xf2]
 
         mov w3, #0xf000f
         mov x10, #0xaaaaaaaaaaaaaaaa
@@ -3353,75 +3486,119 @@ _func:
         movz w1, #65535, lsl #0
         movz w2, #0, lsl #16
         movn w2, #1234, lsl #0
-// CHECK: movz     w1, #65535                 // encoding: [0xe1,0xff,0x9f,0x52]
+// CHECK: movz     w1, #{{65535|0xffff}}      // encoding: [0xe1,0xff,0x9f,0x52]
 // CHECK: movz     w2, #0, lsl #16            // encoding: [0x02,0x00,0xa0,0x52]
-// CHECK: movn     w2, #1234                  // encoding: [0x42,0x9a,0x80,0x12]
+// CHECK: movn     w2, #{{1234|0x4d2}}        // encoding: [0x42,0x9a,0x80,0x12]
 
         movz x2, #1234, lsl #32
         movk xzr, #4321, lsl #48
-// CHECK: movz     x2, #1234, lsl #32         // encoding: [0x42,0x9a,0xc0,0xd2]
-// CHECK: movk     xzr, #4321, lsl #48        // encoding: [0x3f,0x1c,0xe2,0xf2]
+// CHECK: movz     x2, #{{1234|0x4d2}}, lsl #32   // encoding: [0x42,0x9a,0xc0,0xd2]
+// CHECK: movk     xzr, #{{4321|0x10e1}}, lsl #48 // encoding: [0x3f,0x1c,0xe2,0xf2]
 
         movz x2, #:abs_g0:sym
         movk w3, #:abs_g0_nc:sym
-// CHECK: movz    x2, #:abs_g0:sym        // encoding: [0x02'A',A,0x80'A',0xd2'A']
-// CHECK-NEXT:                            //   fixup A - offset: 0, value: :abs_g0:sym, kind: fixup_a64_movw_uabs_g0
-// CHECK: movk     w3, #:abs_g0_nc:sym    // encoding: [0x03'A',A,0x80'A',0x72'A']
-// CHECK-NEXT:                            //   fixup A - offset: 0, value: :abs_g0_nc:sym, kind: fixup_a64_movw_uabs_g0_nc
+// CHECK-AARCH64: movz    x2, #:abs_g0:sym        // encoding: [0x02'A',A,0x80'A',0xd2'A']
+// CHECK-AARCH64-NEXT:                            //   fixup A - offset: 0, value: :abs_g0:sym, kind: fixup_a64_movw_uabs_g0
+// CHECK-AARCH64: movk     w3, #:abs_g0_nc:sym    // encoding: [0x03'A',A,0x80'A',0x72'A']
+// CHECK-AARCH64-NEXT:                            //   fixup A - offset: 0, value: :abs_g0_nc:sym, kind: fixup_a64_movw_uabs_g0_nc
+
+// CHECK-ARM64: movz    x2, #:abs_g0:sym        // encoding: [0bAAA00010,A,0b100AAAAA,0xd2]
+// CHECK-ARM64-NEXT:                                 //   fixup A - offset: 0, value: :abs_g0:sym, kind: fixup_arm64_movw
+// CHECK-ARM64: movk    w3, #:abs_g0_nc:sym     // encoding: [0bAAA00011,A,0b100AAAAA,0x72]
+// CHECK-ARM64-NEXT:                                 //   fixup A - offset: 0, value: :abs_g0_nc:sym, kind: fixup_arm64_movw
 
         movz x4, #:abs_g1:sym
         movk w5, #:abs_g1_nc:sym
-// CHECK: movz     x4, #:abs_g1:sym       // encoding: [0x04'A',A,0xa0'A',0xd2'A']
-// CHECK-NEXT:                            //   fixup A - offset: 0, value: :abs_g1:sym, kind: fixup_a64_movw_uabs_g1
-// CHECK: movk     w5, #:abs_g1_nc:sym    // encoding: [0x05'A',A,0xa0'A',0x72'A']
-// CHECK-NEXT:                            //   fixup A - offset: 0, value: :abs_g1_nc:sym, kind: fixup_a64_movw_uabs_g1_nc
+// CHECK-AARCH64: movz     x4, #:abs_g1:sym       // encoding: [0x04'A',A,0xa0'A',0xd2'A']
+// CHECK-AARCH64-NEXT:                            //   fixup A - offset: 0, value: :abs_g1:sym, kind: fixup_a64_movw_uabs_g1
+// CHECK-AARCH64: movk     w5, #:abs_g1_nc:sym    // encoding: [0x05'A',A,0xa0'A',0x72'A']
+// CHECK-AARCH64-NEXT:                            //   fixup A - offset: 0, value: :abs_g1_nc:sym, kind: fixup_a64_movw_uabs_g1_nc
+
+// CHECK-ARM64: movz    x4, #:abs_g1:sym        // encoding: [0bAAA00100,A,0b101AAAAA,0xd2]
+// CHECK-ARM64-NEXT:                                 //   fixup A - offset: 0, value: :abs_g1:sym, kind: fixup_arm64_movw
+// CHECK-ARM64: movk    w5, #:abs_g1_nc:sym     // encoding: [0bAAA00101,A,0b101AAAAA,0x72]
+// CHECK-ARM64-NEXT:                                 //   fixup A - offset: 0, value: :abs_g1_nc:sym, kind: fixup_arm64_movw
 
         movz x6, #:abs_g2:sym
         movk x7, #:abs_g2_nc:sym
-// CHECK: movz     x6, #:abs_g2:sym       // encoding: [0x06'A',A,0xc0'A',0xd2'A']
-// CHECK-NEXT:                            //   fixup A - offset: 0, value: :abs_g2:sym, kind: fixup_a64_movw_uabs_g2
-// CHECK: movk     x7, #:abs_g2_nc:sym    // encoding: [0x07'A',A,0xc0'A',0xf2'A']
-// CHECK-NEXT:                            //   fixup A - offset: 0, value: :abs_g2_nc:sym, kind: fixup_a64_movw_uabs_g2_nc
+// CHECK-AARCH64: movz     x6, #:abs_g2:sym       // encoding: [0x06'A',A,0xc0'A',0xd2'A']
+// CHECK-AARCH64-NEXT:                            //   fixup A - offset: 0, value: :abs_g2:sym, kind: fixup_a64_movw_uabs_g2
+// CHECK-AARCH64: movk     x7, #:abs_g2_nc:sym    // encoding: [0x07'A',A,0xc0'A',0xf2'A']
+// CHECK-AARCH64-NEXT:                            //   fixup A - offset: 0, value: :abs_g2_nc:sym, kind: fixup_a64_movw_uabs_g2_nc
+
+// CHECK-ARM64: movz    x6, #:abs_g2:sym        // encoding: [0bAAA00110,A,0b110AAAAA,0xd2]
+// CHECK-ARM64-NEXT:                                 //   fixup A - offset: 0, value: :abs_g2:sym, kind: fixup_arm64_movw
+// CHECK-ARM64: movk    x7, #:abs_g2_nc:sym     // encoding: [0bAAA00111,A,0b110AAAAA,0xf2]
+// CHECK-ARM64-NEXT:                                 //   fixup A - offset: 0, value: :abs_g2_nc:sym, kind: fixup_arm64_movw
 
         movz x8, #:abs_g3:sym
         movk x9, #:abs_g3:sym
-// CHECK: movz     x8, #:abs_g3:sym       // encoding: [0x08'A',A,0xe0'A',0xd2'A']
-// CHECK-NEXT:                            //   fixup A - offset: 0, value: :abs_g3:sym, kind: fixup_a64_movw_uabs_g3
-// CHECK: movk     x9, #:abs_g3:sym       // encoding: [0x09'A',A,0xe0'A',0xf2'A']
-// CHECK-NEXT:                            //   fixup A - offset: 0, value: :abs_g3:sym, kind: fixup_a64_movw_uabs_g3
+// CHECK-AARCH64: movz     x8, #:abs_g3:sym       // encoding: [0x08'A',A,0xe0'A',0xd2'A']
+// CHECK-AARCH64-NEXT:                            //   fixup A - offset: 0, value: :abs_g3:sym, kind: fixup_a64_movw_uabs_g3
+// CHECK-AARCH64: movk     x9, #:abs_g3:sym       // encoding: [0x09'A',A,0xe0'A',0xf2'A']
+// CHECK-AARCH64-NEXT:                            //   fixup A - offset: 0, value: :abs_g3:sym, kind: fixup_a64_movw_uabs_g3
+
+// CHECK-ARM64: movz    x8, #:abs_g3:sym        // encoding: [0bAAA01000,A,0b111AAAAA,0xd2]
+// CHECK-ARM64-NEXT:                                 //   fixup A - offset: 0, value: :abs_g3:sym, kind: fixup_arm64_movw
+// CHECK-ARM64: movk    x9, #:abs_g3:sym        // encoding: [0bAAA01001,A,0b111AAAAA,0xf2]
+// CHECK-ARM64-NEXT:                                 //   fixup A - offset: 0, value: :abs_g3:sym, kind: fixup_arm64_movw
+
 
         movn x30, #:abs_g0_s:sym
         movz x19, #:abs_g0_s:sym
         movn w10, #:abs_g0_s:sym
         movz w25, #:abs_g0_s:sym
-// CHECK: movn     x30, #:abs_g0_s:sym    // encoding: [0x1e'A',A,0x80'A',0x92'A']
-// CHECK-NEXT:                            //   fixup A - offset: 0, value: :abs_g0_s:sym, kind: fixup_a64_movw_sabs_g0
-// CHECK: movz     x19, #:abs_g0_s:sym    // encoding: [0x13'A',A,0x80'A',0x92'A']
-// CHECK-NEXT:                            //   fixup A - offset: 0, value: :abs_g0_s:sym, kind: fixup_a64_movw_sabs_g0
-// CHECK: movn     w10, #:abs_g0_s:sym    // encoding: [0x0a'A',A,0x80'A',0x12'A']
-// CHECK-NEXT:                            //   fixup A - offset: 0, value: :abs_g0_s:sym, kind: fixup_a64_movw_sabs_g0
-// CHECK: movz     w25, #:abs_g0_s:sym    // encoding: [0x19'A',A,0x80'A',0x12'A']
-// CHECK-NEXT:                            //   fixup A - offset: 0, value: :abs_g0_s:sym, kind: fixup_a64_movw_sabs_g0
+// CHECK-AARCH64: movn     x30, #:abs_g0_s:sym    // encoding: [0x1e'A',A,0x80'A',0x92'A']
+// CHECK-AARCH64-NEXT:                            //   fixup A - offset: 0, value: :abs_g0_s:sym, kind: fixup_a64_movw_sabs_g0
+// CHECK-AARCH64: movz     x19, #:abs_g0_s:sym    // encoding: [0x13'A',A,0x80'A',0x92'A']
+// CHECK-AARCH64-NEXT:                            //   fixup A - offset: 0, value: :abs_g0_s:sym, kind: fixup_a64_movw_sabs_g0
+// CHECK-AARCH64: movn     w10, #:abs_g0_s:sym    // encoding: [0x0a'A',A,0x80'A',0x12'A']
+// CHECK-AARCH64-NEXT:                            //   fixup A - offset: 0, value: :abs_g0_s:sym, kind: fixup_a64_movw_sabs_g0
+// CHECK-AARCH64: movz     w25, #:abs_g0_s:sym    // encoding: [0x19'A',A,0x80'A',0x12'A']
+// CHECK-AARCH64-NEXT:                            //   fixup A - offset: 0, value: :abs_g0_s:sym, kind: fixup_a64_movw_sabs_g0
+
+// CHECK-ARM64: movn    x30, #:abs_g0_s:sym     // encoding: [0bAAA11110,A,0b100AAAAA,0x92]
+// CHECK-ARM64-NEXT:                                 //   fixup A - offset: 0, value: :abs_g0_s:sym, kind: fixup_arm64_movw
+// CHECK-ARM64: movz    x19, #:abs_g0_s:sym     // encoding: [0bAAA10011,A,0b100AAAAA,0xd2]
+// CHECK-ARM64-NEXT:                                 //   fixup A - offset: 0, value: :abs_g0_s:sym, kind: fixup_arm64_movw
+// CHECK-ARM64: movn    w10, #:abs_g0_s:sym     // encoding: [0bAAA01010,A,0b100AAAAA,0x12]
+// CHECK-ARM64-NEXT:                                 //   fixup A - offset: 0, value: :abs_g0_s:sym, kind: fixup_arm64_movw
+// CHECK-ARM64: movz    w25, #:abs_g0_s:sym     // encoding: [0bAAA11001,A,0b100AAAAA,0x52]
+// CHECK-ARM64-NEXT:                                 //   fixup A - offset: 0, value: :abs_g0_s:sym, kind: fixup_arm64_movw
 
         movn x30, #:abs_g1_s:sym
         movz x19, #:abs_g1_s:sym
         movn w10, #:abs_g1_s:sym
         movz w25, #:abs_g1_s:sym
-// CHECK: movn     x30, #:abs_g1_s:sym    // encoding: [0x1e'A',A,0xa0'A',0x92'A']
-// CHECK-NEXT:                            //   fixup A - offset: 0, value: :abs_g1_s:sym, kind: fixup_a64_movw_sabs_g1
-// CHECK: movz     x19, #:abs_g1_s:sym    // encoding: [0x13'A',A,0xa0'A',0x92'A']
-// CHECK-NEXT:                            //   fixup A - offset: 0, value: :abs_g1_s:sym, kind: fixup_a64_movw_sabs_g1
-// CHECK: movn     w10, #:abs_g1_s:sym    // encoding: [0x0a'A',A,0xa0'A',0x12'A']
-// CHECK-NEXT:                            //   fixup A - offset: 0, value: :abs_g1_s:sym, kind: fixup_a64_movw_sabs_g1
-// CHECK: movz     w25, #:abs_g1_s:sym    // encoding: [0x19'A',A,0xa0'A',0x12'A']
-// CHECK-NEXT:                            //   fixup A - offset: 0, value: :abs_g1_s:sym, kind: fixup_a64_movw_sabs_g1
+// CHECK-AARCH64: movn     x30, #:abs_g1_s:sym    // encoding: [0x1e'A',A,0xa0'A',0x92'A']
+// CHECK-AARCH64-NEXT:                            //   fixup A - offset: 0, value: :abs_g1_s:sym, kind: fixup_a64_movw_sabs_g1
+// CHECK-AARCH64: movz     x19, #:abs_g1_s:sym    // encoding: [0x13'A',A,0xa0'A',0x92'A']
+// CHECK-AARCH64-NEXT:                            //   fixup A - offset: 0, value: :abs_g1_s:sym, kind: fixup_a64_movw_sabs_g1
+// CHECK-AARCH64: movn     w10, #:abs_g1_s:sym    // encoding: [0x0a'A',A,0xa0'A',0x12'A']
+// CHECK-AARCH64-NEXT:                            //   fixup A - offset: 0, value: :abs_g1_s:sym, kind: fixup_a64_movw_sabs_g1
+// CHECK-AARCH64: movz     w25, #:abs_g1_s:sym    // encoding: [0x19'A',A,0xa0'A',0x12'A']
+// CHECK-AARCH64-NEXT:                            //   fixup A - offset: 0, value: :abs_g1_s:sym, kind: fixup_a64_movw_sabs_g1
+
+// CHECK-ARM64: movn    x30, #:abs_g1_s:sym     // encoding: [0bAAA11110,A,0b101AAAAA,0x92]
+// CHECK-ARM64-NEXT:                                 //   fixup A - offset: 0, value: :abs_g1_s:sym, kind: fixup_arm64_movw
+// CHECK-ARM64: movz    x19, #:abs_g1_s:sym     // encoding: [0bAAA10011,A,0b101AAAAA,0xd2]
+// CHECK-ARM64-NEXT:                                 //   fixup A - offset: 0, value: :abs_g1_s:sym, kind: fixup_arm64_movw
+// CHECK-ARM64: movn    w10, #:abs_g1_s:sym     // encoding: [0bAAA01010,A,0b101AAAAA,0x12]
+// CHECK-ARM64-NEXT:                                 //   fixup A - offset: 0, value: :abs_g1_s:sym, kind: fixup_arm64_movw
+// CHECK-ARM64: movz    w25, #:abs_g1_s:sym     // encoding: [0bAAA11001,A,0b101AAAAA,0x52]
+// CHECK-ARM64-NEXT:                                 //   fixup A - offset: 0, value: :abs_g1_s:sym, kind: fixup_arm64_movw
 
         movn x30, #:abs_g2_s:sym
         movz x19, #:abs_g2_s:sym
-// CHECK: movn     x30, #:abs_g2_s:sym    // encoding: [0x1e'A',A,0xc0'A',0x92'A']
-// CHECK-NEXT:                            //   fixup A - offset: 0, value: :abs_g2_s:sym, kind: fixup_a64_movw_sabs_g2
-// CHECK: movz     x19, #:abs_g2_s:sym    // encoding: [0x13'A',A,0xc0'A',0x92'A']
-// CHECK-NEXT:                            //   fixup A - offset: 0, value: :abs_g2_s:sym, kind: fixup_a64_movw_sabs_g2
+// CHECK-AARCH64: movn     x30, #:abs_g2_s:sym    // encoding: [0x1e'A',A,0xc0'A',0x92'A']
+// CHECK-AARCH64-NEXT:                            //   fixup A - offset: 0, value: :abs_g2_s:sym, kind: fixup_a64_movw_sabs_g2
+// CHECK-AARCH64: movz     x19, #:abs_g2_s:sym    // encoding: [0x13'A',A,0xc0'A',0x92'A']
+// CHECK-AARCH64-NEXT:                            //   fixup A - offset: 0, value: :abs_g2_s:sym, kind: fixup_a64_movw_sabs_g2
+
+// CHECK-ARM64: movn    x30, #:abs_g2_s:sym     // encoding: [0bAAA11110,A,0b110AAAAA,0x92]
+// CHECK-ARM64-NEXT:                                 //   fixup A - offset: 0, value: :abs_g2_s:sym, kind: fixup_arm64_movw
+// CHECK-ARM64: movz    x19, #:abs_g2_s:sym     // encoding: [0bAAA10011,A,0b110AAAAA,0xd2]
+// CHECK-ARM64-NEXT:                                 //   fixup A - offset: 0, value: :abs_g2_s:sym, kind: fixup_arm64_movw
 
 //------------------------------------------------------------------------------
 // PC-relative addressing
@@ -3429,15 +3606,22 @@ _func:
 
         adr x2, loc
         adr xzr, loc
- // CHECK: adr     x2, loc                 // encoding: [0x02'A',A,A,0x10'A']
- // CHECK:                                 //   fixup A - offset: 0, value: loc, kind: fixup_a64_adr_prel
- // CHECK: adr     xzr, loc                // encoding: [0x1f'A',A,A,0x10'A']
- // CHECK:                                 //   fixup A - offset: 0, value: loc, kind: fixup_a64_adr_prel
+ // CHECK-AARCH64: adr     x2, loc                 // encoding: [0x02'A',A,A,0x10'A']
+ // CHECK-AARCH64:                                 //   fixup A - offset: 0, value: loc, kind: fixup_a64_adr_prel
+ // CHECK-AARCH64: adr     xzr, loc                // encoding: [0x1f'A',A,A,0x10'A']
+ // CHECK-AARCH64:                                 //   fixup A - offset: 0, value: loc, kind: fixup_a64_adr_prel
+
+// CHECK-ARM64: adr    x2, loc                 // encoding: [0x02'A',A,A,0x10'A']
+// CHECK-ARM64:                                 //   fixup A - offset: 0, value: loc, kind: fixup_arm64_pcrel_adr_imm21
+// CHECK-ARM64: adr    xzr, loc                // encoding: [0x1f'A',A,A,0x10'A']
+// CHECK-ARM64:                                 //   fixup A - offset: 0, value: loc, kind: fixup_arm64_pcrel_adr_imm21
 
         adrp x29, loc
- // CHECK: adrp    x29, loc                // encoding: [0x1d'A',A,A,0x90'A']
- // CHECK:                                 //   fixup A - offset: 0, value: loc, kind: fixup_a64_adr_prel_page
+ // CHECK-AARCH64: adrp    x29, loc                // encoding: [0x1d'A',A,A,0x90'A']
+ // CHECK-AARCH64:                                 //   fixup A - offset: 0, value: loc, kind: fixup_a64_adr_prel_page
 
+// CHECK-ARM64: adrp    x29, loc                // encoding: [0x1d'A',A,A,0x90'A']
+// CHECK-ARM64:                                 //   fixup A - offset: 0, value: loc, kind: fixup_arm64_pcrel_adrp_imm21
         adrp x30, #4096
         adr x20, #0
         adr x9, #-1
@@ -3463,7 +3647,7 @@ _func:
         hint #0
         hint #127
 // CHECK: nop                             // encoding: [0x1f,0x20,0x03,0xd5]
-// CHECK: hint    #127                    // encoding: [0xff,0x2f,0x03,0xd5]
+// CHECK: hint    #{{127|0x7f}}           // encoding: [0xff,0x2f,0x03,0xd5]
 
         nop
         yield
@@ -3560,9 +3744,9 @@ _func:
         msr spsel, #0
         msr daifset, #15
         msr daifclr, #12
-// CHECK: msr     spsel, #0               // encoding: [0xbf,0x40,0x00,0xd5]
-// CHECK: msr     daifset, #15            // encoding: [0xdf,0x4f,0x03,0xd5]
-// CHECK: msr     daifclr, #12            // encoding: [0xff,0x4c,0x03,0xd5]
+// CHECK: msr     {{spsel|SPSEL}}, #0               // encoding: [0xbf,0x40,0x00,0xd5]
+// CHECK: msr     {{daifset|DAIFSET}}, #15            // encoding: [0xdf,0x4f,0x03,0xd5]
+// CHECK: msr     {{daifclr|DAIFCLR}}, #12            // encoding: [0xff,0x4c,0x03,0xd5]
 
         sys #7, c5, c9, #7, x5
         sys #0, c15, c15, #2
@@ -3942,260 +4126,260 @@ _func:
 	msr PMEVTYPER28_EL0, x12
 	msr PMEVTYPER29_EL0, x12
 	msr PMEVTYPER30_EL0, x12
-// CHECK: msr      teecr32_el1, x12           // encoding: [0x0c,0x00,0x12,0xd5]
-// CHECK: msr      osdtrrx_el1, x12           // encoding: [0x4c,0x00,0x10,0xd5]
-// CHECK: msr      mdccint_el1, x12           // encoding: [0x0c,0x02,0x10,0xd5]
-// CHECK: msr      mdscr_el1, x12             // encoding: [0x4c,0x02,0x10,0xd5]
-// CHECK: msr      osdtrtx_el1, x12           // encoding: [0x4c,0x03,0x10,0xd5]
-// CHECK: msr      dbgdtr_el0, x12            // encoding: [0x0c,0x04,0x13,0xd5]
-// CHECK: msr      dbgdtrtx_el0, x12          // encoding: [0x0c,0x05,0x13,0xd5]
-// CHECK: msr      oseccr_el1, x12            // encoding: [0x4c,0x06,0x10,0xd5]
-// CHECK: msr      dbgvcr32_el2, x12          // encoding: [0x0c,0x07,0x14,0xd5]
-// CHECK: msr      dbgbvr0_el1, x12           // encoding: [0x8c,0x00,0x10,0xd5]
-// CHECK: msr      dbgbvr1_el1, x12           // encoding: [0x8c,0x01,0x10,0xd5]
-// CHECK: msr      dbgbvr2_el1, x12           // encoding: [0x8c,0x02,0x10,0xd5]
-// CHECK: msr      dbgbvr3_el1, x12           // encoding: [0x8c,0x03,0x10,0xd5]
-// CHECK: msr      dbgbvr4_el1, x12           // encoding: [0x8c,0x04,0x10,0xd5]
-// CHECK: msr      dbgbvr5_el1, x12           // encoding: [0x8c,0x05,0x10,0xd5]
-// CHECK: msr      dbgbvr6_el1, x12           // encoding: [0x8c,0x06,0x10,0xd5]
-// CHECK: msr      dbgbvr7_el1, x12           // encoding: [0x8c,0x07,0x10,0xd5]
-// CHECK: msr      dbgbvr8_el1, x12           // encoding: [0x8c,0x08,0x10,0xd5]
-// CHECK: msr      dbgbvr9_el1, x12           // encoding: [0x8c,0x09,0x10,0xd5]
-// CHECK: msr      dbgbvr10_el1, x12          // encoding: [0x8c,0x0a,0x10,0xd5]
-// CHECK: msr      dbgbvr11_el1, x12          // encoding: [0x8c,0x0b,0x10,0xd5]
-// CHECK: msr      dbgbvr12_el1, x12          // encoding: [0x8c,0x0c,0x10,0xd5]
-// CHECK: msr      dbgbvr13_el1, x12          // encoding: [0x8c,0x0d,0x10,0xd5]
-// CHECK: msr      dbgbvr14_el1, x12          // encoding: [0x8c,0x0e,0x10,0xd5]
-// CHECK: msr      dbgbvr15_el1, x12          // encoding: [0x8c,0x0f,0x10,0xd5]
-// CHECK: msr      dbgbcr0_el1, x12           // encoding: [0xac,0x00,0x10,0xd5]
-// CHECK: msr      dbgbcr1_el1, x12           // encoding: [0xac,0x01,0x10,0xd5]
-// CHECK: msr      dbgbcr2_el1, x12           // encoding: [0xac,0x02,0x10,0xd5]
-// CHECK: msr      dbgbcr3_el1, x12           // encoding: [0xac,0x03,0x10,0xd5]
-// CHECK: msr      dbgbcr4_el1, x12           // encoding: [0xac,0x04,0x10,0xd5]
-// CHECK: msr      dbgbcr5_el1, x12           // encoding: [0xac,0x05,0x10,0xd5]
-// CHECK: msr      dbgbcr6_el1, x12           // encoding: [0xac,0x06,0x10,0xd5]
-// CHECK: msr      dbgbcr7_el1, x12           // encoding: [0xac,0x07,0x10,0xd5]
-// CHECK: msr      dbgbcr8_el1, x12           // encoding: [0xac,0x08,0x10,0xd5]
-// CHECK: msr      dbgbcr9_el1, x12           // encoding: [0xac,0x09,0x10,0xd5]
-// CHECK: msr      dbgbcr10_el1, x12          // encoding: [0xac,0x0a,0x10,0xd5]
-// CHECK: msr      dbgbcr11_el1, x12          // encoding: [0xac,0x0b,0x10,0xd5]
-// CHECK: msr      dbgbcr12_el1, x12          // encoding: [0xac,0x0c,0x10,0xd5]
-// CHECK: msr      dbgbcr13_el1, x12          // encoding: [0xac,0x0d,0x10,0xd5]
-// CHECK: msr      dbgbcr14_el1, x12          // encoding: [0xac,0x0e,0x10,0xd5]
-// CHECK: msr      dbgbcr15_el1, x12          // encoding: [0xac,0x0f,0x10,0xd5]
-// CHECK: msr      dbgwvr0_el1, x12           // encoding: [0xcc,0x00,0x10,0xd5]
-// CHECK: msr      dbgwvr1_el1, x12           // encoding: [0xcc,0x01,0x10,0xd5]
-// CHECK: msr      dbgwvr2_el1, x12           // encoding: [0xcc,0x02,0x10,0xd5]
-// CHECK: msr      dbgwvr3_el1, x12           // encoding: [0xcc,0x03,0x10,0xd5]
-// CHECK: msr      dbgwvr4_el1, x12           // encoding: [0xcc,0x04,0x10,0xd5]
-// CHECK: msr      dbgwvr5_el1, x12           // encoding: [0xcc,0x05,0x10,0xd5]
-// CHECK: msr      dbgwvr6_el1, x12           // encoding: [0xcc,0x06,0x10,0xd5]
-// CHECK: msr      dbgwvr7_el1, x12           // encoding: [0xcc,0x07,0x10,0xd5]
-// CHECK: msr      dbgwvr8_el1, x12           // encoding: [0xcc,0x08,0x10,0xd5]
-// CHECK: msr      dbgwvr9_el1, x12           // encoding: [0xcc,0x09,0x10,0xd5]
-// CHECK: msr      dbgwvr10_el1, x12          // encoding: [0xcc,0x0a,0x10,0xd5]
-// CHECK: msr      dbgwvr11_el1, x12          // encoding: [0xcc,0x0b,0x10,0xd5]
-// CHECK: msr      dbgwvr12_el1, x12          // encoding: [0xcc,0x0c,0x10,0xd5]
-// CHECK: msr      dbgwvr13_el1, x12          // encoding: [0xcc,0x0d,0x10,0xd5]
-// CHECK: msr      dbgwvr14_el1, x12          // encoding: [0xcc,0x0e,0x10,0xd5]
-// CHECK: msr      dbgwvr15_el1, x12          // encoding: [0xcc,0x0f,0x10,0xd5]
-// CHECK: msr      dbgwcr0_el1, x12           // encoding: [0xec,0x00,0x10,0xd5]
-// CHECK: msr      dbgwcr1_el1, x12           // encoding: [0xec,0x01,0x10,0xd5]
-// CHECK: msr      dbgwcr2_el1, x12           // encoding: [0xec,0x02,0x10,0xd5]
-// CHECK: msr      dbgwcr3_el1, x12           // encoding: [0xec,0x03,0x10,0xd5]
-// CHECK: msr      dbgwcr4_el1, x12           // encoding: [0xec,0x04,0x10,0xd5]
-// CHECK: msr      dbgwcr5_el1, x12           // encoding: [0xec,0x05,0x10,0xd5]
-// CHECK: msr      dbgwcr6_el1, x12           // encoding: [0xec,0x06,0x10,0xd5]
-// CHECK: msr      dbgwcr7_el1, x12           // encoding: [0xec,0x07,0x10,0xd5]
-// CHECK: msr      dbgwcr8_el1, x12           // encoding: [0xec,0x08,0x10,0xd5]
-// CHECK: msr      dbgwcr9_el1, x12           // encoding: [0xec,0x09,0x10,0xd5]
-// CHECK: msr      dbgwcr10_el1, x12          // encoding: [0xec,0x0a,0x10,0xd5]
-// CHECK: msr      dbgwcr11_el1, x12          // encoding: [0xec,0x0b,0x10,0xd5]
-// CHECK: msr      dbgwcr12_el1, x12          // encoding: [0xec,0x0c,0x10,0xd5]
-// CHECK: msr      dbgwcr13_el1, x12          // encoding: [0xec,0x0d,0x10,0xd5]
-// CHECK: msr      dbgwcr14_el1, x12          // encoding: [0xec,0x0e,0x10,0xd5]
-// CHECK: msr      dbgwcr15_el1, x12          // encoding: [0xec,0x0f,0x10,0xd5]
-// CHECK: msr      teehbr32_el1, x12          // encoding: [0x0c,0x10,0x12,0xd5]
-// CHECK: msr      oslar_el1, x12             // encoding: [0x8c,0x10,0x10,0xd5]
-// CHECK: msr      osdlr_el1, x12             // encoding: [0x8c,0x13,0x10,0xd5]
-// CHECK: msr      dbgprcr_el1, x12           // encoding: [0x8c,0x14,0x10,0xd5]
-// CHECK: msr      dbgclaimset_el1, x12       // encoding: [0xcc,0x78,0x10,0xd5]
-// CHECK: msr      dbgclaimclr_el1, x12       // encoding: [0xcc,0x79,0x10,0xd5]
-// CHECK: msr      csselr_el1, x12            // encoding: [0x0c,0x00,0x1a,0xd5]
-// CHECK: msr      vpidr_el2, x12             // encoding: [0x0c,0x00,0x1c,0xd5]
-// CHECK: msr      vmpidr_el2, x12            // encoding: [0xac,0x00,0x1c,0xd5]
-// CHECK: msr      sctlr_el1, x12             // encoding: [0x0c,0x10,0x18,0xd5]
-// CHECK: msr      sctlr_el2, x12             // encoding: [0x0c,0x10,0x1c,0xd5]
-// CHECK: msr      sctlr_el3, x12             // encoding: [0x0c,0x10,0x1e,0xd5]
-// CHECK: msr      actlr_el1, x12             // encoding: [0x2c,0x10,0x18,0xd5]
-// CHECK: msr      actlr_el2, x12             // encoding: [0x2c,0x10,0x1c,0xd5]
-// CHECK: msr      actlr_el3, x12             // encoding: [0x2c,0x10,0x1e,0xd5]
-// CHECK: msr      cpacr_el1, x12             // encoding: [0x4c,0x10,0x18,0xd5]
-// CHECK: msr      hcr_el2, x12               // encoding: [0x0c,0x11,0x1c,0xd5]
-// CHECK: msr      scr_el3, x12               // encoding: [0x0c,0x11,0x1e,0xd5]
-// CHECK: msr      mdcr_el2, x12              // encoding: [0x2c,0x11,0x1c,0xd5]
-// CHECK: msr      sder32_el3, x12            // encoding: [0x2c,0x11,0x1e,0xd5]
-// CHECK: msr      cptr_el2, x12              // encoding: [0x4c,0x11,0x1c,0xd5]
-// CHECK: msr      cptr_el3, x12              // encoding: [0x4c,0x11,0x1e,0xd5]
-// CHECK: msr      hstr_el2, x12              // encoding: [0x6c,0x11,0x1c,0xd5]
-// CHECK: msr      hacr_el2, x12              // encoding: [0xec,0x11,0x1c,0xd5]
-// CHECK: msr      mdcr_el3, x12              // encoding: [0x2c,0x13,0x1e,0xd5]
-// CHECK: msr      ttbr0_el1, x12             // encoding: [0x0c,0x20,0x18,0xd5]
-// CHECK: msr      ttbr0_el2, x12             // encoding: [0x0c,0x20,0x1c,0xd5]
-// CHECK: msr      ttbr0_el3, x12             // encoding: [0x0c,0x20,0x1e,0xd5]
-// CHECK: msr      ttbr1_el1, x12             // encoding: [0x2c,0x20,0x18,0xd5]
-// CHECK: msr      tcr_el1, x12               // encoding: [0x4c,0x20,0x18,0xd5]
-// CHECK: msr      tcr_el2, x12               // encoding: [0x4c,0x20,0x1c,0xd5]
-// CHECK: msr      tcr_el3, x12               // encoding: [0x4c,0x20,0x1e,0xd5]
-// CHECK: msr      vttbr_el2, x12             // encoding: [0x0c,0x21,0x1c,0xd5]
-// CHECK: msr      vtcr_el2, x12              // encoding: [0x4c,0x21,0x1c,0xd5]
-// CHECK: msr      dacr32_el2, x12            // encoding: [0x0c,0x30,0x1c,0xd5]
-// CHECK: msr      spsr_el1, x12              // encoding: [0x0c,0x40,0x18,0xd5]
-// CHECK: msr      spsr_el2, x12              // encoding: [0x0c,0x40,0x1c,0xd5]
-// CHECK: msr      spsr_el3, x12              // encoding: [0x0c,0x40,0x1e,0xd5]
-// CHECK: msr      elr_el1, x12               // encoding: [0x2c,0x40,0x18,0xd5]
-// CHECK: msr      elr_el2, x12               // encoding: [0x2c,0x40,0x1c,0xd5]
-// CHECK: msr      elr_el3, x12               // encoding: [0x2c,0x40,0x1e,0xd5]
-// CHECK: msr      sp_el0, x12                // encoding: [0x0c,0x41,0x18,0xd5]
-// CHECK: msr      sp_el1, x12                // encoding: [0x0c,0x41,0x1c,0xd5]
-// CHECK: msr      sp_el2, x12                // encoding: [0x0c,0x41,0x1e,0xd5]
-// CHECK: msr      spsel, x12                 // encoding: [0x0c,0x42,0x18,0xd5]
-// CHECK: msr      nzcv, x12                  // encoding: [0x0c,0x42,0x1b,0xd5]
-// CHECK: msr      daif, x12                  // encoding: [0x2c,0x42,0x1b,0xd5]
-// CHECK: msr      currentel, x12             // encoding: [0x4c,0x42,0x18,0xd5]
-// CHECK: msr      spsr_irq, x12              // encoding: [0x0c,0x43,0x1c,0xd5]
-// CHECK: msr      spsr_abt, x12              // encoding: [0x2c,0x43,0x1c,0xd5]
-// CHECK: msr      spsr_und, x12              // encoding: [0x4c,0x43,0x1c,0xd5]
-// CHECK: msr      spsr_fiq, x12              // encoding: [0x6c,0x43,0x1c,0xd5]
-// CHECK: msr      fpcr, x12                  // encoding: [0x0c,0x44,0x1b,0xd5]
-// CHECK: msr      fpsr, x12                  // encoding: [0x2c,0x44,0x1b,0xd5]
-// CHECK: msr      dspsr_el0, x12             // encoding: [0x0c,0x45,0x1b,0xd5]
-// CHECK: msr      dlr_el0, x12               // encoding: [0x2c,0x45,0x1b,0xd5]
-// CHECK: msr      ifsr32_el2, x12            // encoding: [0x2c,0x50,0x1c,0xd5]
-// CHECK: msr      afsr0_el1, x12             // encoding: [0x0c,0x51,0x18,0xd5]
-// CHECK: msr      afsr0_el2, x12             // encoding: [0x0c,0x51,0x1c,0xd5]
-// CHECK: msr      afsr0_el3, x12             // encoding: [0x0c,0x51,0x1e,0xd5]
-// CHECK: msr      afsr1_el1, x12             // encoding: [0x2c,0x51,0x18,0xd5]
-// CHECK: msr      afsr1_el2, x12             // encoding: [0x2c,0x51,0x1c,0xd5]
-// CHECK: msr      afsr1_el3, x12             // encoding: [0x2c,0x51,0x1e,0xd5]
-// CHECK: msr      esr_el1, x12               // encoding: [0x0c,0x52,0x18,0xd5]
-// CHECK: msr      esr_el2, x12               // encoding: [0x0c,0x52,0x1c,0xd5]
-// CHECK: msr      esr_el3, x12               // encoding: [0x0c,0x52,0x1e,0xd5]
-// CHECK: msr      fpexc32_el2, x12           // encoding: [0x0c,0x53,0x1c,0xd5]
-// CHECK: msr      far_el1, x12               // encoding: [0x0c,0x60,0x18,0xd5]
-// CHECK: msr      far_el2, x12               // encoding: [0x0c,0x60,0x1c,0xd5]
-// CHECK: msr      far_el3, x12               // encoding: [0x0c,0x60,0x1e,0xd5]
-// CHECK: msr      hpfar_el2, x12             // encoding: [0x8c,0x60,0x1c,0xd5]
-// CHECK: msr      par_el1, x12               // encoding: [0x0c,0x74,0x18,0xd5]
-// CHECK: msr      pmcr_el0, x12              // encoding: [0x0c,0x9c,0x1b,0xd5]
-// CHECK: msr      pmcntenset_el0, x12        // encoding: [0x2c,0x9c,0x1b,0xd5]
-// CHECK: msr      pmcntenclr_el0, x12        // encoding: [0x4c,0x9c,0x1b,0xd5]
-// CHECK: msr      pmovsclr_el0, x12          // encoding: [0x6c,0x9c,0x1b,0xd5]
-// CHECK: msr      pmselr_el0, x12            // encoding: [0xac,0x9c,0x1b,0xd5]
-// CHECK: msr      pmccntr_el0, x12           // encoding: [0x0c,0x9d,0x1b,0xd5]
-// CHECK: msr      pmxevtyper_el0, x12        // encoding: [0x2c,0x9d,0x1b,0xd5]
-// CHECK: msr      pmxevcntr_el0, x12         // encoding: [0x4c,0x9d,0x1b,0xd5]
-// CHECK: msr      pmuserenr_el0, x12         // encoding: [0x0c,0x9e,0x1b,0xd5]
-// CHECK: msr      pmintenset_el1, x12        // encoding: [0x2c,0x9e,0x18,0xd5]
-// CHECK: msr      pmintenclr_el1, x12        // encoding: [0x4c,0x9e,0x18,0xd5]
-// CHECK: msr      pmovsset_el0, x12          // encoding: [0x6c,0x9e,0x1b,0xd5]
-// CHECK: msr      mair_el1, x12              // encoding: [0x0c,0xa2,0x18,0xd5]
-// CHECK: msr      mair_el2, x12              // encoding: [0x0c,0xa2,0x1c,0xd5]
-// CHECK: msr      mair_el3, x12              // encoding: [0x0c,0xa2,0x1e,0xd5]
-// CHECK: msr      amair_el1, x12             // encoding: [0x0c,0xa3,0x18,0xd5]
-// CHECK: msr      amair_el2, x12             // encoding: [0x0c,0xa3,0x1c,0xd5]
-// CHECK: msr      amair_el3, x12             // encoding: [0x0c,0xa3,0x1e,0xd5]
-// CHECK: msr      vbar_el1, x12              // encoding: [0x0c,0xc0,0x18,0xd5]
-// CHECK: msr      vbar_el2, x12              // encoding: [0x0c,0xc0,0x1c,0xd5]
-// CHECK: msr      vbar_el3, x12              // encoding: [0x0c,0xc0,0x1e,0xd5]
-// CHECK: msr      rmr_el1, x12               // encoding: [0x4c,0xc0,0x18,0xd5]
-// CHECK: msr      rmr_el2, x12               // encoding: [0x4c,0xc0,0x1c,0xd5]
-// CHECK: msr      rmr_el3, x12               // encoding: [0x4c,0xc0,0x1e,0xd5]
-// CHECK: msr      contextidr_el1, x12        // encoding: [0x2c,0xd0,0x18,0xd5]
-// CHECK: msr      tpidr_el0, x12             // encoding: [0x4c,0xd0,0x1b,0xd5]
-// CHECK: msr      tpidr_el2, x12             // encoding: [0x4c,0xd0,0x1c,0xd5]
-// CHECK: msr      tpidr_el3, x12             // encoding: [0x4c,0xd0,0x1e,0xd5]
-// CHECK: msr      tpidrro_el0, x12           // encoding: [0x6c,0xd0,0x1b,0xd5]
-// CHECK: msr      tpidr_el1, x12             // encoding: [0x8c,0xd0,0x18,0xd5]
-// CHECK: msr      cntfrq_el0, x12            // encoding: [0x0c,0xe0,0x1b,0xd5]
-// CHECK: msr      cntvoff_el2, x12           // encoding: [0x6c,0xe0,0x1c,0xd5]
-// CHECK: msr      cntkctl_el1, x12           // encoding: [0x0c,0xe1,0x18,0xd5]
-// CHECK: msr      cnthctl_el2, x12           // encoding: [0x0c,0xe1,0x1c,0xd5]
-// CHECK: msr      cntp_tval_el0, x12         // encoding: [0x0c,0xe2,0x1b,0xd5]
-// CHECK: msr      cnthp_tval_el2, x12        // encoding: [0x0c,0xe2,0x1c,0xd5]
-// CHECK: msr      cntps_tval_el1, x12        // encoding: [0x0c,0xe2,0x1f,0xd5]
-// CHECK: msr      cntp_ctl_el0, x12          // encoding: [0x2c,0xe2,0x1b,0xd5]
-// CHECK: msr      cnthp_ctl_el2, x12         // encoding: [0x2c,0xe2,0x1c,0xd5]
-// CHECK: msr      cntps_ctl_el1, x12         // encoding: [0x2c,0xe2,0x1f,0xd5]
-// CHECK: msr      cntp_cval_el0, x12         // encoding: [0x4c,0xe2,0x1b,0xd5]
-// CHECK: msr      cnthp_cval_el2, x12        // encoding: [0x4c,0xe2,0x1c,0xd5]
-// CHECK: msr      cntps_cval_el1, x12        // encoding: [0x4c,0xe2,0x1f,0xd5]
-// CHECK: msr      cntv_tval_el0, x12         // encoding: [0x0c,0xe3,0x1b,0xd5]
-// CHECK: msr      cntv_ctl_el0, x12          // encoding: [0x2c,0xe3,0x1b,0xd5]
-// CHECK: msr      cntv_cval_el0, x12         // encoding: [0x4c,0xe3,0x1b,0xd5]
-// CHECK: msr      pmevcntr0_el0, x12         // encoding: [0x0c,0xe8,0x1b,0xd5]
-// CHECK: msr      pmevcntr1_el0, x12         // encoding: [0x2c,0xe8,0x1b,0xd5]
-// CHECK: msr      pmevcntr2_el0, x12         // encoding: [0x4c,0xe8,0x1b,0xd5]
-// CHECK: msr      pmevcntr3_el0, x12         // encoding: [0x6c,0xe8,0x1b,0xd5]
-// CHECK: msr      pmevcntr4_el0, x12         // encoding: [0x8c,0xe8,0x1b,0xd5]
-// CHECK: msr      pmevcntr5_el0, x12         // encoding: [0xac,0xe8,0x1b,0xd5]
-// CHECK: msr      pmevcntr6_el0, x12         // encoding: [0xcc,0xe8,0x1b,0xd5]
-// CHECK: msr      pmevcntr7_el0, x12         // encoding: [0xec,0xe8,0x1b,0xd5]
-// CHECK: msr      pmevcntr8_el0, x12         // encoding: [0x0c,0xe9,0x1b,0xd5]
-// CHECK: msr      pmevcntr9_el0, x12         // encoding: [0x2c,0xe9,0x1b,0xd5]
-// CHECK: msr      pmevcntr10_el0, x12        // encoding: [0x4c,0xe9,0x1b,0xd5]
-// CHECK: msr      pmevcntr11_el0, x12        // encoding: [0x6c,0xe9,0x1b,0xd5]
-// CHECK: msr      pmevcntr12_el0, x12        // encoding: [0x8c,0xe9,0x1b,0xd5]
-// CHECK: msr      pmevcntr13_el0, x12        // encoding: [0xac,0xe9,0x1b,0xd5]
-// CHECK: msr      pmevcntr14_el0, x12        // encoding: [0xcc,0xe9,0x1b,0xd5]
-// CHECK: msr      pmevcntr15_el0, x12        // encoding: [0xec,0xe9,0x1b,0xd5]
-// CHECK: msr      pmevcntr16_el0, x12        // encoding: [0x0c,0xea,0x1b,0xd5]
-// CHECK: msr      pmevcntr17_el0, x12        // encoding: [0x2c,0xea,0x1b,0xd5]
-// CHECK: msr      pmevcntr18_el0, x12        // encoding: [0x4c,0xea,0x1b,0xd5]
-// CHECK: msr      pmevcntr19_el0, x12        // encoding: [0x6c,0xea,0x1b,0xd5]
-// CHECK: msr      pmevcntr20_el0, x12        // encoding: [0x8c,0xea,0x1b,0xd5]
-// CHECK: msr      pmevcntr21_el0, x12        // encoding: [0xac,0xea,0x1b,0xd5]
-// CHECK: msr      pmevcntr22_el0, x12        // encoding: [0xcc,0xea,0x1b,0xd5]
-// CHECK: msr      pmevcntr23_el0, x12        // encoding: [0xec,0xea,0x1b,0xd5]
-// CHECK: msr      pmevcntr24_el0, x12        // encoding: [0x0c,0xeb,0x1b,0xd5]
-// CHECK: msr      pmevcntr25_el0, x12        // encoding: [0x2c,0xeb,0x1b,0xd5]
-// CHECK: msr      pmevcntr26_el0, x12        // encoding: [0x4c,0xeb,0x1b,0xd5]
-// CHECK: msr      pmevcntr27_el0, x12        // encoding: [0x6c,0xeb,0x1b,0xd5]
-// CHECK: msr      pmevcntr28_el0, x12        // encoding: [0x8c,0xeb,0x1b,0xd5]
-// CHECK: msr      pmevcntr29_el0, x12        // encoding: [0xac,0xeb,0x1b,0xd5]
-// CHECK: msr      pmevcntr30_el0, x12        // encoding: [0xcc,0xeb,0x1b,0xd5]
-// CHECK: msr      pmccfiltr_el0, x12         // encoding: [0xec,0xef,0x1b,0xd5]
-// CHECK: msr      pmevtyper0_el0, x12        // encoding: [0x0c,0xec,0x1b,0xd5]
-// CHECK: msr      pmevtyper1_el0, x12        // encoding: [0x2c,0xec,0x1b,0xd5]
-// CHECK: msr      pmevtyper2_el0, x12        // encoding: [0x4c,0xec,0x1b,0xd5]
-// CHECK: msr      pmevtyper3_el0, x12        // encoding: [0x6c,0xec,0x1b,0xd5]
-// CHECK: msr      pmevtyper4_el0, x12        // encoding: [0x8c,0xec,0x1b,0xd5]
-// CHECK: msr      pmevtyper5_el0, x12        // encoding: [0xac,0xec,0x1b,0xd5]
-// CHECK: msr      pmevtyper6_el0, x12        // encoding: [0xcc,0xec,0x1b,0xd5]
-// CHECK: msr      pmevtyper7_el0, x12        // encoding: [0xec,0xec,0x1b,0xd5]
-// CHECK: msr      pmevtyper8_el0, x12        // encoding: [0x0c,0xed,0x1b,0xd5]
-// CHECK: msr      pmevtyper9_el0, x12        // encoding: [0x2c,0xed,0x1b,0xd5]
-// CHECK: msr      pmevtyper10_el0, x12       // encoding: [0x4c,0xed,0x1b,0xd5]
-// CHECK: msr      pmevtyper11_el0, x12       // encoding: [0x6c,0xed,0x1b,0xd5]
-// CHECK: msr      pmevtyper12_el0, x12       // encoding: [0x8c,0xed,0x1b,0xd5]
-// CHECK: msr      pmevtyper13_el0, x12       // encoding: [0xac,0xed,0x1b,0xd5]
-// CHECK: msr      pmevtyper14_el0, x12       // encoding: [0xcc,0xed,0x1b,0xd5]
-// CHECK: msr      pmevtyper15_el0, x12       // encoding: [0xec,0xed,0x1b,0xd5]
-// CHECK: msr      pmevtyper16_el0, x12       // encoding: [0x0c,0xee,0x1b,0xd5]
-// CHECK: msr      pmevtyper17_el0, x12       // encoding: [0x2c,0xee,0x1b,0xd5]
-// CHECK: msr      pmevtyper18_el0, x12       // encoding: [0x4c,0xee,0x1b,0xd5]
-// CHECK: msr      pmevtyper19_el0, x12       // encoding: [0x6c,0xee,0x1b,0xd5]
-// CHECK: msr      pmevtyper20_el0, x12       // encoding: [0x8c,0xee,0x1b,0xd5]
-// CHECK: msr      pmevtyper21_el0, x12       // encoding: [0xac,0xee,0x1b,0xd5]
-// CHECK: msr      pmevtyper22_el0, x12       // encoding: [0xcc,0xee,0x1b,0xd5]
-// CHECK: msr      pmevtyper23_el0, x12       // encoding: [0xec,0xee,0x1b,0xd5]
-// CHECK: msr      pmevtyper24_el0, x12       // encoding: [0x0c,0xef,0x1b,0xd5]
-// CHECK: msr      pmevtyper25_el0, x12       // encoding: [0x2c,0xef,0x1b,0xd5]
-// CHECK: msr      pmevtyper26_el0, x12       // encoding: [0x4c,0xef,0x1b,0xd5]
-// CHECK: msr      pmevtyper27_el0, x12       // encoding: [0x6c,0xef,0x1b,0xd5]
-// CHECK: msr      pmevtyper28_el0, x12       // encoding: [0x8c,0xef,0x1b,0xd5]
-// CHECK: msr      pmevtyper29_el0, x12       // encoding: [0xac,0xef,0x1b,0xd5]
-// CHECK: msr      pmevtyper30_el0, x12       // encoding: [0xcc,0xef,0x1b,0xd5]
+// CHECK: msr      {{teecr32_el1|TEECR32_EL1}}, x12           // encoding: [0x0c,0x00,0x12,0xd5]
+// CHECK: msr      {{osdtrrx_el1|OSDTRRX_EL1}}, x12           // encoding: [0x4c,0x00,0x10,0xd5]
+// CHECK: msr      {{mdccint_el1|MDCCINT_EL1}}, x12           // encoding: [0x0c,0x02,0x10,0xd5]
+// CHECK: msr      {{mdscr_el1|MDSCR_EL1}}, x12             // encoding: [0x4c,0x02,0x10,0xd5]
+// CHECK: msr      {{osdtrtx_el1|OSDTRTX_EL1}}, x12           // encoding: [0x4c,0x03,0x10,0xd5]
+// CHECK: msr      {{dbgdtr_el0|DBGDTR_EL0}}, x12            // encoding: [0x0c,0x04,0x13,0xd5]
+// CHECK: msr      {{dbgdtrtx_el0|DBGDTRTX_EL0}}, x12          // encoding: [0x0c,0x05,0x13,0xd5]
+// CHECK: msr      {{oseccr_el1|OSECCR_EL1}}, x12            // encoding: [0x4c,0x06,0x10,0xd5]
+// CHECK: msr      {{dbgvcr32_el2|DBGVCR32_EL2}}, x12          // encoding: [0x0c,0x07,0x14,0xd5]
+// CHECK: msr      {{dbgbvr0_el1|DBGBVR0_EL1}}, x12           // encoding: [0x8c,0x00,0x10,0xd5]
+// CHECK: msr      {{dbgbvr1_el1|DBGBVR1_EL1}}, x12           // encoding: [0x8c,0x01,0x10,0xd5]
+// CHECK: msr      {{dbgbvr2_el1|DBGBVR2_EL1}}, x12           // encoding: [0x8c,0x02,0x10,0xd5]
+// CHECK: msr      {{dbgbvr3_el1|DBGBVR3_EL1}}, x12           // encoding: [0x8c,0x03,0x10,0xd5]
+// CHECK: msr      {{dbgbvr4_el1|DBGBVR4_EL1}}, x12           // encoding: [0x8c,0x04,0x10,0xd5]
+// CHECK: msr      {{dbgbvr5_el1|DBGBVR5_EL1}}, x12           // encoding: [0x8c,0x05,0x10,0xd5]
+// CHECK: msr      {{dbgbvr6_el1|DBGBVR6_EL1}}, x12           // encoding: [0x8c,0x06,0x10,0xd5]
+// CHECK: msr      {{dbgbvr7_el1|DBGBVR7_EL1}}, x12           // encoding: [0x8c,0x07,0x10,0xd5]
+// CHECK: msr      {{dbgbvr8_el1|DBGBVR8_EL1}}, x12           // encoding: [0x8c,0x08,0x10,0xd5]
+// CHECK: msr      {{dbgbvr9_el1|DBGBVR9_EL1}}, x12           // encoding: [0x8c,0x09,0x10,0xd5]
+// CHECK: msr      {{dbgbvr10_el1|DBGBVR10_EL1}}, x12          // encoding: [0x8c,0x0a,0x10,0xd5]
+// CHECK: msr      {{dbgbvr11_el1|DBGBVR11_EL1}}, x12          // encoding: [0x8c,0x0b,0x10,0xd5]
+// CHECK: msr      {{dbgbvr12_el1|DBGBVR12_EL1}}, x12          // encoding: [0x8c,0x0c,0x10,0xd5]
+// CHECK: msr      {{dbgbvr13_el1|DBGBVR13_EL1}}, x12          // encoding: [0x8c,0x0d,0x10,0xd5]
+// CHECK: msr      {{dbgbvr14_el1|DBGBVR14_EL1}}, x12          // encoding: [0x8c,0x0e,0x10,0xd5]
+// CHECK: msr      {{dbgbvr15_el1|DBGBVR15_EL1}}, x12          // encoding: [0x8c,0x0f,0x10,0xd5]
+// CHECK: msr      {{dbgbcr0_el1|DBGBCR0_EL1}}, x12           // encoding: [0xac,0x00,0x10,0xd5]
+// CHECK: msr      {{dbgbcr1_el1|DBGBCR1_EL1}}, x12           // encoding: [0xac,0x01,0x10,0xd5]
+// CHECK: msr      {{dbgbcr2_el1|DBGBCR2_EL1}}, x12           // encoding: [0xac,0x02,0x10,0xd5]
+// CHECK: msr      {{dbgbcr3_el1|DBGBCR3_EL1}}, x12           // encoding: [0xac,0x03,0x10,0xd5]
+// CHECK: msr      {{dbgbcr4_el1|DBGBCR4_EL1}}, x12           // encoding: [0xac,0x04,0x10,0xd5]
+// CHECK: msr      {{dbgbcr5_el1|DBGBCR5_EL1}}, x12           // encoding: [0xac,0x05,0x10,0xd5]
+// CHECK: msr      {{dbgbcr6_el1|DBGBCR6_EL1}}, x12           // encoding: [0xac,0x06,0x10,0xd5]
+// CHECK: msr      {{dbgbcr7_el1|DBGBCR7_EL1}}, x12           // encoding: [0xac,0x07,0x10,0xd5]
+// CHECK: msr      {{dbgbcr8_el1|DBGBCR8_EL1}}, x12           // encoding: [0xac,0x08,0x10,0xd5]
+// CHECK: msr      {{dbgbcr9_el1|DBGBCR9_EL1}}, x12           // encoding: [0xac,0x09,0x10,0xd5]
+// CHECK: msr      {{dbgbcr10_el1|DBGBCR10_EL1}}, x12          // encoding: [0xac,0x0a,0x10,0xd5]
+// CHECK: msr      {{dbgbcr11_el1|DBGBCR11_EL1}}, x12          // encoding: [0xac,0x0b,0x10,0xd5]
+// CHECK: msr      {{dbgbcr12_el1|DBGBCR12_EL1}}, x12          // encoding: [0xac,0x0c,0x10,0xd5]
+// CHECK: msr      {{dbgbcr13_el1|DBGBCR13_EL1}}, x12          // encoding: [0xac,0x0d,0x10,0xd5]
+// CHECK: msr      {{dbgbcr14_el1|DBGBCR14_EL1}}, x12          // encoding: [0xac,0x0e,0x10,0xd5]
+// CHECK: msr      {{dbgbcr15_el1|DBGBCR15_EL1}}, x12          // encoding: [0xac,0x0f,0x10,0xd5]
+// CHECK: msr      {{dbgwvr0_el1|DBGWVR0_EL1}}, x12           // encoding: [0xcc,0x00,0x10,0xd5]
+// CHECK: msr      {{dbgwvr1_el1|DBGWVR1_EL1}}, x12           // encoding: [0xcc,0x01,0x10,0xd5]
+// CHECK: msr      {{dbgwvr2_el1|DBGWVR2_EL1}}, x12           // encoding: [0xcc,0x02,0x10,0xd5]
+// CHECK: msr      {{dbgwvr3_el1|DBGWVR3_EL1}}, x12           // encoding: [0xcc,0x03,0x10,0xd5]
+// CHECK: msr      {{dbgwvr4_el1|DBGWVR4_EL1}}, x12           // encoding: [0xcc,0x04,0x10,0xd5]
+// CHECK: msr      {{dbgwvr5_el1|DBGWVR5_EL1}}, x12           // encoding: [0xcc,0x05,0x10,0xd5]
+// CHECK: msr      {{dbgwvr6_el1|DBGWVR6_EL1}}, x12           // encoding: [0xcc,0x06,0x10,0xd5]
+// CHECK: msr      {{dbgwvr7_el1|DBGWVR7_EL1}}, x12           // encoding: [0xcc,0x07,0x10,0xd5]
+// CHECK: msr      {{dbgwvr8_el1|DBGWVR8_EL1}}, x12           // encoding: [0xcc,0x08,0x10,0xd5]
+// CHECK: msr      {{dbgwvr9_el1|DBGWVR9_EL1}}, x12           // encoding: [0xcc,0x09,0x10,0xd5]
+// CHECK: msr      {{dbgwvr10_el1|DBGWVR10_EL1}}, x12          // encoding: [0xcc,0x0a,0x10,0xd5]
+// CHECK: msr      {{dbgwvr11_el1|DBGWVR11_EL1}}, x12          // encoding: [0xcc,0x0b,0x10,0xd5]
+// CHECK: msr      {{dbgwvr12_el1|DBGWVR12_EL1}}, x12          // encoding: [0xcc,0x0c,0x10,0xd5]
+// CHECK: msr      {{dbgwvr13_el1|DBGWVR13_EL1}}, x12          // encoding: [0xcc,0x0d,0x10,0xd5]
+// CHECK: msr      {{dbgwvr14_el1|DBGWVR14_EL1}}, x12          // encoding: [0xcc,0x0e,0x10,0xd5]
+// CHECK: msr      {{dbgwvr15_el1|DBGWVR15_EL1}}, x12          // encoding: [0xcc,0x0f,0x10,0xd5]
+// CHECK: msr      {{dbgwcr0_el1|DBGWCR0_EL1}}, x12           // encoding: [0xec,0x00,0x10,0xd5]
+// CHECK: msr      {{dbgwcr1_el1|DBGWCR1_EL1}}, x12           // encoding: [0xec,0x01,0x10,0xd5]
+// CHECK: msr      {{dbgwcr2_el1|DBGWCR2_EL1}}, x12           // encoding: [0xec,0x02,0x10,0xd5]
+// CHECK: msr      {{dbgwcr3_el1|DBGWCR3_EL1}}, x12           // encoding: [0xec,0x03,0x10,0xd5]
+// CHECK: msr      {{dbgwcr4_el1|DBGWCR4_EL1}}, x12           // encoding: [0xec,0x04,0x10,0xd5]
+// CHECK: msr      {{dbgwcr5_el1|DBGWCR5_EL1}}, x12           // encoding: [0xec,0x05,0x10,0xd5]
+// CHECK: msr      {{dbgwcr6_el1|DBGWCR6_EL1}}, x12           // encoding: [0xec,0x06,0x10,0xd5]
+// CHECK: msr      {{dbgwcr7_el1|DBGWCR7_EL1}}, x12           // encoding: [0xec,0x07,0x10,0xd5]
+// CHECK: msr      {{dbgwcr8_el1|DBGWCR8_EL1}}, x12           // encoding: [0xec,0x08,0x10,0xd5]
+// CHECK: msr      {{dbgwcr9_el1|DBGWCR9_EL1}}, x12           // encoding: [0xec,0x09,0x10,0xd5]
+// CHECK: msr      {{dbgwcr10_el1|DBGWCR10_EL1}}, x12          // encoding: [0xec,0x0a,0x10,0xd5]
+// CHECK: msr      {{dbgwcr11_el1|DBGWCR11_EL1}}, x12          // encoding: [0xec,0x0b,0x10,0xd5]
+// CHECK: msr      {{dbgwcr12_el1|DBGWCR12_EL1}}, x12          // encoding: [0xec,0x0c,0x10,0xd5]
+// CHECK: msr      {{dbgwcr13_el1|DBGWCR13_EL1}}, x12          // encoding: [0xec,0x0d,0x10,0xd5]
+// CHECK: msr      {{dbgwcr14_el1|DBGWCR14_EL1}}, x12          // encoding: [0xec,0x0e,0x10,0xd5]
+// CHECK: msr      {{dbgwcr15_el1|DBGWCR15_EL1}}, x12          // encoding: [0xec,0x0f,0x10,0xd5]
+// CHECK: msr      {{teehbr32_el1|TEEHBR32_EL1}}, x12          // encoding: [0x0c,0x10,0x12,0xd5]
+// CHECK: msr      {{oslar_el1|OSLAR_EL1}}, x12             // encoding: [0x8c,0x10,0x10,0xd5]
+// CHECK: msr      {{osdlr_el1|OSDLR_EL1}}, x12             // encoding: [0x8c,0x13,0x10,0xd5]
+// CHECK: msr      {{dbgprcr_el1|DBGPRCR_EL1}}, x12           // encoding: [0x8c,0x14,0x10,0xd5]
+// CHECK: msr      {{dbgclaimset_el1|DBGCLAIMSET_EL1}}, x12       // encoding: [0xcc,0x78,0x10,0xd5]
+// CHECK: msr      {{dbgclaimclr_el1|DBGCLAIMCLR_EL1}}, x12       // encoding: [0xcc,0x79,0x10,0xd5]
+// CHECK: msr      {{csselr_el1|CSSELR_EL1}}, x12            // encoding: [0x0c,0x00,0x1a,0xd5]
+// CHECK: msr      {{vpidr_el2|VPIDR_EL2}}, x12             // encoding: [0x0c,0x00,0x1c,0xd5]
+// CHECK: msr      {{vmpidr_el2|VMPIDR_EL2}}, x12            // encoding: [0xac,0x00,0x1c,0xd5]
+// CHECK: msr      {{sctlr_el1|SCTLR_EL1}}, x12             // encoding: [0x0c,0x10,0x18,0xd5]
+// CHECK: msr      {{sctlr_el2|SCTLR_EL2}}, x12             // encoding: [0x0c,0x10,0x1c,0xd5]
+// CHECK: msr      {{sctlr_el3|SCTLR_EL3}}, x12             // encoding: [0x0c,0x10,0x1e,0xd5]
+// CHECK: msr      {{actlr_el1|ACTLR_EL1}}, x12             // encoding: [0x2c,0x10,0x18,0xd5]
+// CHECK: msr      {{actlr_el2|ACTLR_EL2}}, x12             // encoding: [0x2c,0x10,0x1c,0xd5]
+// CHECK: msr      {{actlr_el3|ACTLR_EL3}}, x12             // encoding: [0x2c,0x10,0x1e,0xd5]
+// CHECK: msr      {{cpacr_el1|CPACR_EL1}}, x12             // encoding: [0x4c,0x10,0x18,0xd5]
+// CHECK: msr      {{hcr_el2|HCR_EL2}}, x12               // encoding: [0x0c,0x11,0x1c,0xd5]
+// CHECK: msr      {{scr_el3|SCR_EL3}}, x12               // encoding: [0x0c,0x11,0x1e,0xd5]
+// CHECK: msr      {{mdcr_el2|MDCR_EL2}}, x12              // encoding: [0x2c,0x11,0x1c,0xd5]
+// CHECK: msr      {{sder32_el3|SDER32_EL3}}, x12            // encoding: [0x2c,0x11,0x1e,0xd5]
+// CHECK: msr      {{cptr_el2|CPTR_EL2}}, x12              // encoding: [0x4c,0x11,0x1c,0xd5]
+// CHECK: msr      {{cptr_el3|CPTR_EL3}}, x12              // encoding: [0x4c,0x11,0x1e,0xd5]
+// CHECK: msr      {{hstr_el2|HSTR_EL2}}, x12              // encoding: [0x6c,0x11,0x1c,0xd5]
+// CHECK: msr      {{hacr_el2|HACR_EL2}}, x12              // encoding: [0xec,0x11,0x1c,0xd5]
+// CHECK: msr      {{mdcr_el3|MDCR_EL3}}, x12              // encoding: [0x2c,0x13,0x1e,0xd5]
+// CHECK: msr      {{ttbr0_el1|TTBR0_EL1}}, x12             // encoding: [0x0c,0x20,0x18,0xd5]
+// CHECK: msr      {{ttbr0_el2|TTBR0_EL2}}, x12             // encoding: [0x0c,0x20,0x1c,0xd5]
+// CHECK: msr      {{ttbr0_el3|TTBR0_EL3}}, x12             // encoding: [0x0c,0x20,0x1e,0xd5]
+// CHECK: msr      {{ttbr1_el1|TTBR1_EL1}}, x12             // encoding: [0x2c,0x20,0x18,0xd5]
+// CHECK: msr      {{tcr_el1|TCR_EL1}}, x12               // encoding: [0x4c,0x20,0x18,0xd5]
+// CHECK: msr      {{tcr_el2|TCR_EL2}}, x12               // encoding: [0x4c,0x20,0x1c,0xd5]
+// CHECK: msr      {{tcr_el3|TCR_EL3}}, x12               // encoding: [0x4c,0x20,0x1e,0xd5]
+// CHECK: msr      {{vttbr_el2|VTTBR_EL2}}, x12             // encoding: [0x0c,0x21,0x1c,0xd5]
+// CHECK: msr      {{vtcr_el2|VTCR_EL2}}, x12              // encoding: [0x4c,0x21,0x1c,0xd5]
+// CHECK: msr      {{dacr32_el2|DACR32_EL2}}, x12            // encoding: [0x0c,0x30,0x1c,0xd5]
+// CHECK: msr      {{spsr_el1|SPSR_EL1}}, x12              // encoding: [0x0c,0x40,0x18,0xd5]
+// CHECK: msr      {{spsr_el2|SPSR_EL2}}, x12              // encoding: [0x0c,0x40,0x1c,0xd5]
+// CHECK: msr      {{spsr_el3|SPSR_EL3}}, x12              // encoding: [0x0c,0x40,0x1e,0xd5]
+// CHECK: msr      {{elr_el1|ELR_EL1}}, x12               // encoding: [0x2c,0x40,0x18,0xd5]
+// CHECK: msr      {{elr_el2|ELR_EL2}}, x12               // encoding: [0x2c,0x40,0x1c,0xd5]
+// CHECK: msr      {{elr_el3|ELR_EL3}}, x12               // encoding: [0x2c,0x40,0x1e,0xd5]
+// CHECK: msr      {{sp_el0|SP_EL0}}, x12                // encoding: [0x0c,0x41,0x18,0xd5]
+// CHECK: msr      {{sp_el1|SP_EL1}}, x12                // encoding: [0x0c,0x41,0x1c,0xd5]
+// CHECK: msr      {{sp_el2|SP_EL2}}, x12                // encoding: [0x0c,0x41,0x1e,0xd5]
+// CHECK: msr      {{spsel|SPSEL}}, x12                 // encoding: [0x0c,0x42,0x18,0xd5]
+// CHECK: msr      {{nzcv|NZCV}}, x12                  // encoding: [0x0c,0x42,0x1b,0xd5]
+// CHECK: msr      {{daif|DAIF}}, x12                  // encoding: [0x2c,0x42,0x1b,0xd5]
+// CHECK: msr      {{currentel|CURRENTEL}}, x12             // encoding: [0x4c,0x42,0x18,0xd5]
+// CHECK: msr      {{spsr_irq|SPSR_IRQ}}, x12              // encoding: [0x0c,0x43,0x1c,0xd5]
+// CHECK: msr      {{spsr_abt|SPSR_ABT}}, x12              // encoding: [0x2c,0x43,0x1c,0xd5]
+// CHECK: msr      {{spsr_und|SPSR_UND}}, x12              // encoding: [0x4c,0x43,0x1c,0xd5]
+// CHECK: msr      {{spsr_fiq|SPSR_FIQ}}, x12              // encoding: [0x6c,0x43,0x1c,0xd5]
+// CHECK: msr      {{fpcr|FPCR}}, x12                  // encoding: [0x0c,0x44,0x1b,0xd5]
+// CHECK: msr      {{fpsr|FPSR}}, x12                  // encoding: [0x2c,0x44,0x1b,0xd5]
+// CHECK: msr      {{dspsr_el0|DSPSR_EL0}}, x12             // encoding: [0x0c,0x45,0x1b,0xd5]
+// CHECK: msr      {{dlr_el0|DLR_EL0}}, x12               // encoding: [0x2c,0x45,0x1b,0xd5]
+// CHECK: msr      {{ifsr32_el2|IFSR32_EL2}}, x12            // encoding: [0x2c,0x50,0x1c,0xd5]
+// CHECK: msr      {{afsr0_el1|AFSR0_EL1}}, x12             // encoding: [0x0c,0x51,0x18,0xd5]
+// CHECK: msr      {{afsr0_el2|AFSR0_EL2}}, x12             // encoding: [0x0c,0x51,0x1c,0xd5]
+// CHECK: msr      {{afsr0_el3|AFSR0_EL3}}, x12             // encoding: [0x0c,0x51,0x1e,0xd5]
+// CHECK: msr      {{afsr1_el1|AFSR1_EL1}}, x12             // encoding: [0x2c,0x51,0x18,0xd5]
+// CHECK: msr      {{afsr1_el2|AFSR1_EL2}}, x12             // encoding: [0x2c,0x51,0x1c,0xd5]
+// CHECK: msr      {{afsr1_el3|AFSR1_EL3}}, x12             // encoding: [0x2c,0x51,0x1e,0xd5]
+// CHECK: msr      {{esr_el1|ESR_EL1}}, x12               // encoding: [0x0c,0x52,0x18,0xd5]
+// CHECK: msr      {{esr_el2|ESR_EL2}}, x12               // encoding: [0x0c,0x52,0x1c,0xd5]
+// CHECK: msr      {{esr_el3|ESR_EL3}}, x12               // encoding: [0x0c,0x52,0x1e,0xd5]
+// CHECK: msr      {{fpexc32_el2|FPEXC32_EL2}}, x12           // encoding: [0x0c,0x53,0x1c,0xd5]
+// CHECK: msr      {{far_el1|FAR_EL1}}, x12               // encoding: [0x0c,0x60,0x18,0xd5]
+// CHECK: msr      {{far_el2|FAR_EL2}}, x12               // encoding: [0x0c,0x60,0x1c,0xd5]
+// CHECK: msr      {{far_el3|FAR_EL3}}, x12               // encoding: [0x0c,0x60,0x1e,0xd5]
+// CHECK: msr      {{hpfar_el2|HPFAR_EL2}}, x12             // encoding: [0x8c,0x60,0x1c,0xd5]
+// CHECK: msr      {{par_el1|PAR_EL1}}, x12               // encoding: [0x0c,0x74,0x18,0xd5]
+// CHECK: msr      {{pmcr_el0|PMCR_EL0}}, x12              // encoding: [0x0c,0x9c,0x1b,0xd5]
+// CHECK: msr      {{pmcntenset_el0|PMCNTENSET_EL0}}, x12        // encoding: [0x2c,0x9c,0x1b,0xd5]
+// CHECK: msr      {{pmcntenclr_el0|PMCNTENCLR_EL0}}, x12        // encoding: [0x4c,0x9c,0x1b,0xd5]
+// CHECK: msr      {{pmovsclr_el0|PMOVSCLR_EL0}}, x12          // encoding: [0x6c,0x9c,0x1b,0xd5]
+// CHECK: msr      {{pmselr_el0|PMSELR_EL0}}, x12            // encoding: [0xac,0x9c,0x1b,0xd5]
+// CHECK: msr      {{pmccntr_el0|PMCCNTR_EL0}}, x12           // encoding: [0x0c,0x9d,0x1b,0xd5]
+// CHECK: msr      {{pmxevtyper_el0|PMXEVTYPER_EL0}}, x12        // encoding: [0x2c,0x9d,0x1b,0xd5]
+// CHECK: msr      {{pmxevcntr_el0|PMXEVCNTR_EL0}}, x12         // encoding: [0x4c,0x9d,0x1b,0xd5]
+// CHECK: msr      {{pmuserenr_el0|PMUSERENR_EL0}}, x12         // encoding: [0x0c,0x9e,0x1b,0xd5]
+// CHECK: msr      {{pmintenset_el1|PMINTENSET_EL1}}, x12        // encoding: [0x2c,0x9e,0x18,0xd5]
+// CHECK: msr      {{pmintenclr_el1|PMINTENCLR_EL1}}, x12        // encoding: [0x4c,0x9e,0x18,0xd5]
+// CHECK: msr      {{pmovsset_el0|PMOVSSET_EL0}}, x12          // encoding: [0x6c,0x9e,0x1b,0xd5]
+// CHECK: msr      {{mair_el1|MAIR_EL1}}, x12              // encoding: [0x0c,0xa2,0x18,0xd5]
+// CHECK: msr      {{mair_el2|MAIR_EL2}}, x12              // encoding: [0x0c,0xa2,0x1c,0xd5]
+// CHECK: msr      {{mair_el3|MAIR_EL3}}, x12              // encoding: [0x0c,0xa2,0x1e,0xd5]
+// CHECK: msr      {{amair_el1|AMAIR_EL1}}, x12             // encoding: [0x0c,0xa3,0x18,0xd5]
+// CHECK: msr      {{amair_el2|AMAIR_EL2}}, x12             // encoding: [0x0c,0xa3,0x1c,0xd5]
+// CHECK: msr      {{amair_el3|AMAIR_EL3}}, x12             // encoding: [0x0c,0xa3,0x1e,0xd5]
+// CHECK: msr      {{vbar_el1|VBAR_EL1}}, x12              // encoding: [0x0c,0xc0,0x18,0xd5]
+// CHECK: msr      {{vbar_el2|VBAR_EL2}}, x12              // encoding: [0x0c,0xc0,0x1c,0xd5]
+// CHECK: msr      {{vbar_el3|VBAR_EL3}}, x12              // encoding: [0x0c,0xc0,0x1e,0xd5]
+// CHECK: msr      {{rmr_el1|RMR_EL1}}, x12               // encoding: [0x4c,0xc0,0x18,0xd5]
+// CHECK: msr      {{rmr_el2|RMR_EL2}}, x12               // encoding: [0x4c,0xc0,0x1c,0xd5]
+// CHECK: msr      {{rmr_el3|RMR_EL3}}, x12               // encoding: [0x4c,0xc0,0x1e,0xd5]
+// CHECK: msr      {{contextidr_el1|CONTEXTIDR_EL1}}, x12        // encoding: [0x2c,0xd0,0x18,0xd5]
+// CHECK: msr      {{tpidr_el0|TPIDR_EL0}}, x12             // encoding: [0x4c,0xd0,0x1b,0xd5]
+// CHECK: msr      {{tpidr_el2|TPIDR_EL2}}, x12             // encoding: [0x4c,0xd0,0x1c,0xd5]
+// CHECK: msr      {{tpidr_el3|TPIDR_EL3}}, x12             // encoding: [0x4c,0xd0,0x1e,0xd5]
+// CHECK: msr      {{tpidrro_el0|TPIDRRO_EL0}}, x12           // encoding: [0x6c,0xd0,0x1b,0xd5]
+// CHECK: msr      {{tpidr_el1|TPIDR_EL1}}, x12             // encoding: [0x8c,0xd0,0x18,0xd5]
+// CHECK: msr      {{cntfrq_el0|CNTFRQ_EL0}}, x12            // encoding: [0x0c,0xe0,0x1b,0xd5]
+// CHECK: msr      {{cntvoff_el2|CNTVOFF_EL2}}, x12           // encoding: [0x6c,0xe0,0x1c,0xd5]
+// CHECK: msr      {{cntkctl_el1|CNTKCTL_EL1}}, x12           // encoding: [0x0c,0xe1,0x18,0xd5]
+// CHECK: msr      {{cnthctl_el2|CNTHCTL_EL2}}, x12           // encoding: [0x0c,0xe1,0x1c,0xd5]
+// CHECK: msr      {{cntp_tval_el0|CNTP_TVAL_EL0}}, x12         // encoding: [0x0c,0xe2,0x1b,0xd5]
+// CHECK: msr      {{cnthp_tval_el2|CNTHP_TVAL_EL2}}, x12        // encoding: [0x0c,0xe2,0x1c,0xd5]
+// CHECK: msr      {{cntps_tval_el1|CNTPS_TVAL_EL1}}, x12        // encoding: [0x0c,0xe2,0x1f,0xd5]
+// CHECK: msr      {{cntp_ctl_el0|CNTP_CTL_EL0}}, x12          // encoding: [0x2c,0xe2,0x1b,0xd5]
+// CHECK: msr      {{cnthp_ctl_el2|CNTHP_CTL_EL2}}, x12         // encoding: [0x2c,0xe2,0x1c,0xd5]
+// CHECK: msr      {{cntps_ctl_el1|CNTPS_CTL_EL1}}, x12         // encoding: [0x2c,0xe2,0x1f,0xd5]
+// CHECK: msr      {{cntp_cval_el0|CNTP_CVAL_EL0}}, x12         // encoding: [0x4c,0xe2,0x1b,0xd5]
+// CHECK: msr      {{cnthp_cval_el2|CNTHP_CVAL_EL2}}, x12        // encoding: [0x4c,0xe2,0x1c,0xd5]
+// CHECK: msr      {{cntps_cval_el1|CNTPS_CVAL_EL1}}, x12        // encoding: [0x4c,0xe2,0x1f,0xd5]
+// CHECK: msr      {{cntv_tval_el0|CNTV_TVAL_EL0}}, x12         // encoding: [0x0c,0xe3,0x1b,0xd5]
+// CHECK: msr      {{cntv_ctl_el0|CNTV_CTL_EL0}}, x12          // encoding: [0x2c,0xe3,0x1b,0xd5]
+// CHECK: msr      {{cntv_cval_el0|CNTV_CVAL_EL0}}, x12         // encoding: [0x4c,0xe3,0x1b,0xd5]
+// CHECK: msr      {{pmevcntr0_el0|PMEVCNTR0_EL0}}, x12         // encoding: [0x0c,0xe8,0x1b,0xd5]
+// CHECK: msr      {{pmevcntr1_el0|PMEVCNTR1_EL0}}, x12         // encoding: [0x2c,0xe8,0x1b,0xd5]
+// CHECK: msr      {{pmevcntr2_el0|PMEVCNTR2_EL0}}, x12         // encoding: [0x4c,0xe8,0x1b,0xd5]
+// CHECK: msr      {{pmevcntr3_el0|PMEVCNTR3_EL0}}, x12         // encoding: [0x6c,0xe8,0x1b,0xd5]
+// CHECK: msr      {{pmevcntr4_el0|PMEVCNTR4_EL0}}, x12         // encoding: [0x8c,0xe8,0x1b,0xd5]
+// CHECK: msr      {{pmevcntr5_el0|PMEVCNTR5_EL0}}, x12         // encoding: [0xac,0xe8,0x1b,0xd5]
+// CHECK: msr      {{pmevcntr6_el0|PMEVCNTR6_EL0}}, x12         // encoding: [0xcc,0xe8,0x1b,0xd5]
+// CHECK: msr      {{pmevcntr7_el0|PMEVCNTR7_EL0}}, x12         // encoding: [0xec,0xe8,0x1b,0xd5]
+// CHECK: msr      {{pmevcntr8_el0|PMEVCNTR8_EL0}}, x12         // encoding: [0x0c,0xe9,0x1b,0xd5]
+// CHECK: msr      {{pmevcntr9_el0|PMEVCNTR9_EL0}}, x12         // encoding: [0x2c,0xe9,0x1b,0xd5]
+// CHECK: msr      {{pmevcntr10_el0|PMEVCNTR10_EL0}}, x12        // encoding: [0x4c,0xe9,0x1b,0xd5]
+// CHECK: msr      {{pmevcntr11_el0|PMEVCNTR11_EL0}}, x12        // encoding: [0x6c,0xe9,0x1b,0xd5]
+// CHECK: msr      {{pmevcntr12_el0|PMEVCNTR12_EL0}}, x12        // encoding: [0x8c,0xe9,0x1b,0xd5]
+// CHECK: msr      {{pmevcntr13_el0|PMEVCNTR13_EL0}}, x12        // encoding: [0xac,0xe9,0x1b,0xd5]
+// CHECK: msr      {{pmevcntr14_el0|PMEVCNTR14_EL0}}, x12        // encoding: [0xcc,0xe9,0x1b,0xd5]
+// CHECK: msr      {{pmevcntr15_el0|PMEVCNTR15_EL0}}, x12        // encoding: [0xec,0xe9,0x1b,0xd5]
+// CHECK: msr      {{pmevcntr16_el0|PMEVCNTR16_EL0}}, x12        // encoding: [0x0c,0xea,0x1b,0xd5]
+// CHECK: msr      {{pmevcntr17_el0|PMEVCNTR17_EL0}}, x12        // encoding: [0x2c,0xea,0x1b,0xd5]
+// CHECK: msr      {{pmevcntr18_el0|PMEVCNTR18_EL0}}, x12        // encoding: [0x4c,0xea,0x1b,0xd5]
+// CHECK: msr      {{pmevcntr19_el0|PMEVCNTR19_EL0}}, x12        // encoding: [0x6c,0xea,0x1b,0xd5]
+// CHECK: msr      {{pmevcntr20_el0|PMEVCNTR20_EL0}}, x12        // encoding: [0x8c,0xea,0x1b,0xd5]
+// CHECK: msr      {{pmevcntr21_el0|PMEVCNTR21_EL0}}, x12        // encoding: [0xac,0xea,0x1b,0xd5]
+// CHECK: msr      {{pmevcntr22_el0|PMEVCNTR22_EL0}}, x12        // encoding: [0xcc,0xea,0x1b,0xd5]
+// CHECK: msr      {{pmevcntr23_el0|PMEVCNTR23_EL0}}, x12        // encoding: [0xec,0xea,0x1b,0xd5]
+// CHECK: msr      {{pmevcntr24_el0|PMEVCNTR24_EL0}}, x12        // encoding: [0x0c,0xeb,0x1b,0xd5]
+// CHECK: msr      {{pmevcntr25_el0|PMEVCNTR25_EL0}}, x12        // encoding: [0x2c,0xeb,0x1b,0xd5]
+// CHECK: msr      {{pmevcntr26_el0|PMEVCNTR26_EL0}}, x12        // encoding: [0x4c,0xeb,0x1b,0xd5]
+// CHECK: msr      {{pmevcntr27_el0|PMEVCNTR27_EL0}}, x12        // encoding: [0x6c,0xeb,0x1b,0xd5]
+// CHECK: msr      {{pmevcntr28_el0|PMEVCNTR28_EL0}}, x12        // encoding: [0x8c,0xeb,0x1b,0xd5]
+// CHECK: msr      {{pmevcntr29_el0|PMEVCNTR29_EL0}}, x12        // encoding: [0xac,0xeb,0x1b,0xd5]
+// CHECK: msr      {{pmevcntr30_el0|PMEVCNTR30_EL0}}, x12        // encoding: [0xcc,0xeb,0x1b,0xd5]
+// CHECK: msr      {{pmccfiltr_el0|PMCCFILTR_EL0}}, x12         // encoding: [0xec,0xef,0x1b,0xd5]
+// CHECK: msr      {{pmevtyper0_el0|PMEVTYPER0_EL0}}, x12        // encoding: [0x0c,0xec,0x1b,0xd5]
+// CHECK: msr      {{pmevtyper1_el0|PMEVTYPER1_EL0}}, x12        // encoding: [0x2c,0xec,0x1b,0xd5]
+// CHECK: msr      {{pmevtyper2_el0|PMEVTYPER2_EL0}}, x12        // encoding: [0x4c,0xec,0x1b,0xd5]
+// CHECK: msr      {{pmevtyper3_el0|PMEVTYPER3_EL0}}, x12        // encoding: [0x6c,0xec,0x1b,0xd5]
+// CHECK: msr      {{pmevtyper4_el0|PMEVTYPER4_EL0}}, x12        // encoding: [0x8c,0xec,0x1b,0xd5]
+// CHECK: msr      {{pmevtyper5_el0|PMEVTYPER5_EL0}}, x12        // encoding: [0xac,0xec,0x1b,0xd5]
+// CHECK: msr      {{pmevtyper6_el0|PMEVTYPER6_EL0}}, x12        // encoding: [0xcc,0xec,0x1b,0xd5]
+// CHECK: msr      {{pmevtyper7_el0|PMEVTYPER7_EL0}}, x12        // encoding: [0xec,0xec,0x1b,0xd5]
+// CHECK: msr      {{pmevtyper8_el0|PMEVTYPER8_EL0}}, x12        // encoding: [0x0c,0xed,0x1b,0xd5]
+// CHECK: msr      {{pmevtyper9_el0|PMEVTYPER9_EL0}}, x12        // encoding: [0x2c,0xed,0x1b,0xd5]
+// CHECK: msr      {{pmevtyper10_el0|PMEVTYPER10_EL0}}, x12       // encoding: [0x4c,0xed,0x1b,0xd5]
+// CHECK: msr      {{pmevtyper11_el0|PMEVTYPER11_EL0}}, x12       // encoding: [0x6c,0xed,0x1b,0xd5]
+// CHECK: msr      {{pmevtyper12_el0|PMEVTYPER12_EL0}}, x12       // encoding: [0x8c,0xed,0x1b,0xd5]
+// CHECK: msr      {{pmevtyper13_el0|PMEVTYPER13_EL0}}, x12       // encoding: [0xac,0xed,0x1b,0xd5]
+// CHECK: msr      {{pmevtyper14_el0|PMEVTYPER14_EL0}}, x12       // encoding: [0xcc,0xed,0x1b,0xd5]
+// CHECK: msr      {{pmevtyper15_el0|PMEVTYPER15_EL0}}, x12       // encoding: [0xec,0xed,0x1b,0xd5]
+// CHECK: msr      {{pmevtyper16_el0|PMEVTYPER16_EL0}}, x12       // encoding: [0x0c,0xee,0x1b,0xd5]
+// CHECK: msr      {{pmevtyper17_el0|PMEVTYPER17_EL0}}, x12       // encoding: [0x2c,0xee,0x1b,0xd5]
+// CHECK: msr      {{pmevtyper18_el0|PMEVTYPER18_EL0}}, x12       // encoding: [0x4c,0xee,0x1b,0xd5]
+// CHECK: msr      {{pmevtyper19_el0|PMEVTYPER19_EL0}}, x12       // encoding: [0x6c,0xee,0x1b,0xd5]
+// CHECK: msr      {{pmevtyper20_el0|PMEVTYPER20_EL0}}, x12       // encoding: [0x8c,0xee,0x1b,0xd5]
+// CHECK: msr      {{pmevtyper21_el0|PMEVTYPER21_EL0}}, x12       // encoding: [0xac,0xee,0x1b,0xd5]
+// CHECK: msr      {{pmevtyper22_el0|PMEVTYPER22_EL0}}, x12       // encoding: [0xcc,0xee,0x1b,0xd5]
+// CHECK: msr      {{pmevtyper23_el0|PMEVTYPER23_EL0}}, x12       // encoding: [0xec,0xee,0x1b,0xd5]
+// CHECK: msr      {{pmevtyper24_el0|PMEVTYPER24_EL0}}, x12       // encoding: [0x0c,0xef,0x1b,0xd5]
+// CHECK: msr      {{pmevtyper25_el0|PMEVTYPER25_EL0}}, x12       // encoding: [0x2c,0xef,0x1b,0xd5]
+// CHECK: msr      {{pmevtyper26_el0|PMEVTYPER26_EL0}}, x12       // encoding: [0x4c,0xef,0x1b,0xd5]
+// CHECK: msr      {{pmevtyper27_el0|PMEVTYPER27_EL0}}, x12       // encoding: [0x6c,0xef,0x1b,0xd5]
+// CHECK: msr      {{pmevtyper28_el0|PMEVTYPER28_EL0}}, x12       // encoding: [0x8c,0xef,0x1b,0xd5]
+// CHECK: msr      {{pmevtyper29_el0|PMEVTYPER29_EL0}}, x12       // encoding: [0xac,0xef,0x1b,0xd5]
+// CHECK: msr      {{pmevtyper30_el0|PMEVTYPER30_EL0}}, x12       // encoding: [0xcc,0xef,0x1b,0xd5]
 
 	mrs x9, TEECR32_EL1
 	mrs x9, OSDTRRX_EL1
@@ -4497,315 +4681,315 @@ _func:
 	mrs x9, PMEVTYPER28_EL0
 	mrs x9, PMEVTYPER29_EL0
 	mrs x9, PMEVTYPER30_EL0
-// CHECK: mrs      x9, teecr32_el1            // encoding: [0x09,0x00,0x32,0xd5]
-// CHECK: mrs      x9, osdtrrx_el1            // encoding: [0x49,0x00,0x30,0xd5]
-// CHECK: mrs      x9, mdccsr_el0             // encoding: [0x09,0x01,0x33,0xd5]
-// CHECK: mrs      x9, mdccint_el1            // encoding: [0x09,0x02,0x30,0xd5]
-// CHECK: mrs      x9, mdscr_el1              // encoding: [0x49,0x02,0x30,0xd5]
-// CHECK: mrs      x9, osdtrtx_el1            // encoding: [0x49,0x03,0x30,0xd5]
-// CHECK: mrs      x9, dbgdtr_el0             // encoding: [0x09,0x04,0x33,0xd5]
-// CHECK: mrs      x9, dbgdtrrx_el0           // encoding: [0x09,0x05,0x33,0xd5]
-// CHECK: mrs      x9, oseccr_el1             // encoding: [0x49,0x06,0x30,0xd5]
-// CHECK: mrs      x9, dbgvcr32_el2           // encoding: [0x09,0x07,0x34,0xd5]
-// CHECK: mrs      x9, dbgbvr0_el1            // encoding: [0x89,0x00,0x30,0xd5]
-// CHECK: mrs      x9, dbgbvr1_el1            // encoding: [0x89,0x01,0x30,0xd5]
-// CHECK: mrs      x9, dbgbvr2_el1            // encoding: [0x89,0x02,0x30,0xd5]
-// CHECK: mrs      x9, dbgbvr3_el1            // encoding: [0x89,0x03,0x30,0xd5]
-// CHECK: mrs      x9, dbgbvr4_el1            // encoding: [0x89,0x04,0x30,0xd5]
-// CHECK: mrs      x9, dbgbvr5_el1            // encoding: [0x89,0x05,0x30,0xd5]
-// CHECK: mrs      x9, dbgbvr6_el1            // encoding: [0x89,0x06,0x30,0xd5]
-// CHECK: mrs      x9, dbgbvr7_el1            // encoding: [0x89,0x07,0x30,0xd5]
-// CHECK: mrs      x9, dbgbvr8_el1            // encoding: [0x89,0x08,0x30,0xd5]
-// CHECK: mrs      x9, dbgbvr9_el1            // encoding: [0x89,0x09,0x30,0xd5]
-// CHECK: mrs      x9, dbgbvr10_el1           // encoding: [0x89,0x0a,0x30,0xd5]
-// CHECK: mrs      x9, dbgbvr11_el1           // encoding: [0x89,0x0b,0x30,0xd5]
-// CHECK: mrs      x9, dbgbvr12_el1           // encoding: [0x89,0x0c,0x30,0xd5]
-// CHECK: mrs      x9, dbgbvr13_el1           // encoding: [0x89,0x0d,0x30,0xd5]
-// CHECK: mrs      x9, dbgbvr14_el1           // encoding: [0x89,0x0e,0x30,0xd5]
-// CHECK: mrs      x9, dbgbvr15_el1           // encoding: [0x89,0x0f,0x30,0xd5]
-// CHECK: mrs      x9, dbgbcr0_el1            // encoding: [0xa9,0x00,0x30,0xd5]
-// CHECK: mrs      x9, dbgbcr1_el1            // encoding: [0xa9,0x01,0x30,0xd5]
-// CHECK: mrs      x9, dbgbcr2_el1            // encoding: [0xa9,0x02,0x30,0xd5]
-// CHECK: mrs      x9, dbgbcr3_el1            // encoding: [0xa9,0x03,0x30,0xd5]
-// CHECK: mrs      x9, dbgbcr4_el1            // encoding: [0xa9,0x04,0x30,0xd5]
-// CHECK: mrs      x9, dbgbcr5_el1            // encoding: [0xa9,0x05,0x30,0xd5]
-// CHECK: mrs      x9, dbgbcr6_el1            // encoding: [0xa9,0x06,0x30,0xd5]
-// CHECK: mrs      x9, dbgbcr7_el1            // encoding: [0xa9,0x07,0x30,0xd5]
-// CHECK: mrs      x9, dbgbcr8_el1            // encoding: [0xa9,0x08,0x30,0xd5]
-// CHECK: mrs      x9, dbgbcr9_el1            // encoding: [0xa9,0x09,0x30,0xd5]
-// CHECK: mrs      x9, dbgbcr10_el1           // encoding: [0xa9,0x0a,0x30,0xd5]
-// CHECK: mrs      x9, dbgbcr11_el1           // encoding: [0xa9,0x0b,0x30,0xd5]
-// CHECK: mrs      x9, dbgbcr12_el1           // encoding: [0xa9,0x0c,0x30,0xd5]
-// CHECK: mrs      x9, dbgbcr13_el1           // encoding: [0xa9,0x0d,0x30,0xd5]
-// CHECK: mrs      x9, dbgbcr14_el1           // encoding: [0xa9,0x0e,0x30,0xd5]
-// CHECK: mrs      x9, dbgbcr15_el1           // encoding: [0xa9,0x0f,0x30,0xd5]
-// CHECK: mrs      x9, dbgwvr0_el1            // encoding: [0xc9,0x00,0x30,0xd5]
-// CHECK: mrs      x9, dbgwvr1_el1            // encoding: [0xc9,0x01,0x30,0xd5]
-// CHECK: mrs      x9, dbgwvr2_el1            // encoding: [0xc9,0x02,0x30,0xd5]
-// CHECK: mrs      x9, dbgwvr3_el1            // encoding: [0xc9,0x03,0x30,0xd5]
-// CHECK: mrs      x9, dbgwvr4_el1            // encoding: [0xc9,0x04,0x30,0xd5]
-// CHECK: mrs      x9, dbgwvr5_el1            // encoding: [0xc9,0x05,0x30,0xd5]
-// CHECK: mrs      x9, dbgwvr6_el1            // encoding: [0xc9,0x06,0x30,0xd5]
-// CHECK: mrs      x9, dbgwvr7_el1            // encoding: [0xc9,0x07,0x30,0xd5]
-// CHECK: mrs      x9, dbgwvr8_el1            // encoding: [0xc9,0x08,0x30,0xd5]
-// CHECK: mrs      x9, dbgwvr9_el1            // encoding: [0xc9,0x09,0x30,0xd5]
-// CHECK: mrs      x9, dbgwvr10_el1           // encoding: [0xc9,0x0a,0x30,0xd5]
-// CHECK: mrs      x9, dbgwvr11_el1           // encoding: [0xc9,0x0b,0x30,0xd5]
-// CHECK: mrs      x9, dbgwvr12_el1           // encoding: [0xc9,0x0c,0x30,0xd5]
-// CHECK: mrs      x9, dbgwvr13_el1           // encoding: [0xc9,0x0d,0x30,0xd5]
-// CHECK: mrs      x9, dbgwvr14_el1           // encoding: [0xc9,0x0e,0x30,0xd5]
-// CHECK: mrs      x9, dbgwvr15_el1           // encoding: [0xc9,0x0f,0x30,0xd5]
-// CHECK: mrs      x9, dbgwcr0_el1            // encoding: [0xe9,0x00,0x30,0xd5]
-// CHECK: mrs      x9, dbgwcr1_el1            // encoding: [0xe9,0x01,0x30,0xd5]
-// CHECK: mrs      x9, dbgwcr2_el1            // encoding: [0xe9,0x02,0x30,0xd5]
-// CHECK: mrs      x9, dbgwcr3_el1            // encoding: [0xe9,0x03,0x30,0xd5]
-// CHECK: mrs      x9, dbgwcr4_el1            // encoding: [0xe9,0x04,0x30,0xd5]
-// CHECK: mrs      x9, dbgwcr5_el1            // encoding: [0xe9,0x05,0x30,0xd5]
-// CHECK: mrs      x9, dbgwcr6_el1            // encoding: [0xe9,0x06,0x30,0xd5]
-// CHECK: mrs      x9, dbgwcr7_el1            // encoding: [0xe9,0x07,0x30,0xd5]
-// CHECK: mrs      x9, dbgwcr8_el1            // encoding: [0xe9,0x08,0x30,0xd5]
-// CHECK: mrs      x9, dbgwcr9_el1            // encoding: [0xe9,0x09,0x30,0xd5]
-// CHECK: mrs      x9, dbgwcr10_el1           // encoding: [0xe9,0x0a,0x30,0xd5]
-// CHECK: mrs      x9, dbgwcr11_el1           // encoding: [0xe9,0x0b,0x30,0xd5]
-// CHECK: mrs      x9, dbgwcr12_el1           // encoding: [0xe9,0x0c,0x30,0xd5]
-// CHECK: mrs      x9, dbgwcr13_el1           // encoding: [0xe9,0x0d,0x30,0xd5]
-// CHECK: mrs      x9, dbgwcr14_el1           // encoding: [0xe9,0x0e,0x30,0xd5]
-// CHECK: mrs      x9, dbgwcr15_el1           // encoding: [0xe9,0x0f,0x30,0xd5]
-// CHECK: mrs      x9, mdrar_el1              // encoding: [0x09,0x10,0x30,0xd5]
-// CHECK: mrs      x9, teehbr32_el1           // encoding: [0x09,0x10,0x32,0xd5]
-// CHECK: mrs      x9, oslsr_el1              // encoding: [0x89,0x11,0x30,0xd5]
-// CHECK: mrs      x9, osdlr_el1              // encoding: [0x89,0x13,0x30,0xd5]
-// CHECK: mrs      x9, dbgprcr_el1            // encoding: [0x89,0x14,0x30,0xd5]
-// CHECK: mrs      x9, dbgclaimset_el1        // encoding: [0xc9,0x78,0x30,0xd5]
-// CHECK: mrs      x9, dbgclaimclr_el1        // encoding: [0xc9,0x79,0x30,0xd5]
-// CHECK: mrs      x9, dbgauthstatus_el1      // encoding: [0xc9,0x7e,0x30,0xd5]
-// CHECK: mrs      x9, midr_el1               // encoding: [0x09,0x00,0x38,0xd5]
-// CHECK: mrs      x9, ccsidr_el1             // encoding: [0x09,0x00,0x39,0xd5]
-// CHECK: mrs      x9, csselr_el1             // encoding: [0x09,0x00,0x3a,0xd5]
-// CHECK: mrs      x9, vpidr_el2              // encoding: [0x09,0x00,0x3c,0xd5]
-// CHECK: mrs      x9, clidr_el1              // encoding: [0x29,0x00,0x39,0xd5]
-// CHECK: mrs      x9, ctr_el0                // encoding: [0x29,0x00,0x3b,0xd5]
-// CHECK: mrs      x9, mpidr_el1              // encoding: [0xa9,0x00,0x38,0xd5]
-// CHECK: mrs      x9, vmpidr_el2             // encoding: [0xa9,0x00,0x3c,0xd5]
-// CHECK: mrs      x9, revidr_el1             // encoding: [0xc9,0x00,0x38,0xd5]
-// CHECK: mrs      x9, aidr_el1               // encoding: [0xe9,0x00,0x39,0xd5]
-// CHECK: mrs      x9, dczid_el0              // encoding: [0xe9,0x00,0x3b,0xd5]
-// CHECK: mrs      x9, id_pfr0_el1            // encoding: [0x09,0x01,0x38,0xd5]
-// CHECK: mrs      x9, id_pfr1_el1            // encoding: [0x29,0x01,0x38,0xd5]
-// CHECK: mrs      x9, id_dfr0_el1            // encoding: [0x49,0x01,0x38,0xd5]
-// CHECK: mrs      x9, id_afr0_el1            // encoding: [0x69,0x01,0x38,0xd5]
-// CHECK: mrs      x9, id_mmfr0_el1           // encoding: [0x89,0x01,0x38,0xd5]
-// CHECK: mrs      x9, id_mmfr1_el1           // encoding: [0xa9,0x01,0x38,0xd5]
-// CHECK: mrs      x9, id_mmfr2_el1           // encoding: [0xc9,0x01,0x38,0xd5]
-// CHECK: mrs      x9, id_mmfr3_el1           // encoding: [0xe9,0x01,0x38,0xd5]
-// CHECK: mrs      x9, id_isar0_el1           // encoding: [0x09,0x02,0x38,0xd5]
-// CHECK: mrs      x9, id_isar1_el1           // encoding: [0x29,0x02,0x38,0xd5]
-// CHECK: mrs      x9, id_isar2_el1           // encoding: [0x49,0x02,0x38,0xd5]
-// CHECK: mrs      x9, id_isar3_el1           // encoding: [0x69,0x02,0x38,0xd5]
-// CHECK: mrs      x9, id_isar4_el1           // encoding: [0x89,0x02,0x38,0xd5]
-// CHECK: mrs      x9, id_isar5_el1           // encoding: [0xa9,0x02,0x38,0xd5]
-// CHECK: mrs      x9, mvfr0_el1              // encoding: [0x09,0x03,0x38,0xd5]
-// CHECK: mrs      x9, mvfr1_el1              // encoding: [0x29,0x03,0x38,0xd5]
-// CHECK: mrs      x9, mvfr2_el1              // encoding: [0x49,0x03,0x38,0xd5]
-// CHECK: mrs      x9, id_aa64pfr0_el1        // encoding: [0x09,0x04,0x38,0xd5]
-// CHECK: mrs      x9, id_aa64pfr1_el1        // encoding: [0x29,0x04,0x38,0xd5]
-// CHECK: mrs      x9, id_aa64dfr0_el1        // encoding: [0x09,0x05,0x38,0xd5]
-// CHECK: mrs      x9, id_aa64dfr1_el1        // encoding: [0x29,0x05,0x38,0xd5]
-// CHECK: mrs      x9, id_aa64afr0_el1        // encoding: [0x89,0x05,0x38,0xd5]
-// CHECK: mrs      x9, id_aa64afr1_el1        // encoding: [0xa9,0x05,0x38,0xd5]
-// CHECK: mrs      x9, id_aa64isar0_el1       // encoding: [0x09,0x06,0x38,0xd5]
-// CHECK: mrs      x9, id_aa64isar1_el1       // encoding: [0x29,0x06,0x38,0xd5]
-// CHECK: mrs      x9, id_aa64mmfr0_el1       // encoding: [0x09,0x07,0x38,0xd5]
-// CHECK: mrs      x9, id_aa64mmfr1_el1       // encoding: [0x29,0x07,0x38,0xd5]
-// CHECK: mrs      x9, sctlr_el1              // encoding: [0x09,0x10,0x38,0xd5]
-// CHECK: mrs      x9, sctlr_el2              // encoding: [0x09,0x10,0x3c,0xd5]
-// CHECK: mrs      x9, sctlr_el3              // encoding: [0x09,0x10,0x3e,0xd5]
-// CHECK: mrs      x9, actlr_el1              // encoding: [0x29,0x10,0x38,0xd5]
-// CHECK: mrs      x9, actlr_el2              // encoding: [0x29,0x10,0x3c,0xd5]
-// CHECK: mrs      x9, actlr_el3              // encoding: [0x29,0x10,0x3e,0xd5]
-// CHECK: mrs      x9, cpacr_el1              // encoding: [0x49,0x10,0x38,0xd5]
-// CHECK: mrs      x9, hcr_el2                // encoding: [0x09,0x11,0x3c,0xd5]
-// CHECK: mrs      x9, scr_el3                // encoding: [0x09,0x11,0x3e,0xd5]
-// CHECK: mrs      x9, mdcr_el2               // encoding: [0x29,0x11,0x3c,0xd5]
-// CHECK: mrs      x9, sder32_el3             // encoding: [0x29,0x11,0x3e,0xd5]
-// CHECK: mrs      x9, cptr_el2               // encoding: [0x49,0x11,0x3c,0xd5]
-// CHECK: mrs      x9, cptr_el3               // encoding: [0x49,0x11,0x3e,0xd5]
-// CHECK: mrs      x9, hstr_el2               // encoding: [0x69,0x11,0x3c,0xd5]
-// CHECK: mrs      x9, hacr_el2               // encoding: [0xe9,0x11,0x3c,0xd5]
-// CHECK: mrs      x9, mdcr_el3               // encoding: [0x29,0x13,0x3e,0xd5]
-// CHECK: mrs      x9, ttbr0_el1              // encoding: [0x09,0x20,0x38,0xd5]
-// CHECK: mrs      x9, ttbr0_el2              // encoding: [0x09,0x20,0x3c,0xd5]
-// CHECK: mrs      x9, ttbr0_el3              // encoding: [0x09,0x20,0x3e,0xd5]
-// CHECK: mrs      x9, ttbr1_el1              // encoding: [0x29,0x20,0x38,0xd5]
-// CHECK: mrs      x9, tcr_el1                // encoding: [0x49,0x20,0x38,0xd5]
-// CHECK: mrs      x9, tcr_el2                // encoding: [0x49,0x20,0x3c,0xd5]
-// CHECK: mrs      x9, tcr_el3                // encoding: [0x49,0x20,0x3e,0xd5]
-// CHECK: mrs      x9, vttbr_el2              // encoding: [0x09,0x21,0x3c,0xd5]
-// CHECK: mrs      x9, vtcr_el2               // encoding: [0x49,0x21,0x3c,0xd5]
-// CHECK: mrs      x9, dacr32_el2             // encoding: [0x09,0x30,0x3c,0xd5]
-// CHECK: mrs      x9, spsr_el1               // encoding: [0x09,0x40,0x38,0xd5]
-// CHECK: mrs      x9, spsr_el2               // encoding: [0x09,0x40,0x3c,0xd5]
-// CHECK: mrs      x9, spsr_el3               // encoding: [0x09,0x40,0x3e,0xd5]
-// CHECK: mrs      x9, elr_el1                // encoding: [0x29,0x40,0x38,0xd5]
-// CHECK: mrs      x9, elr_el2                // encoding: [0x29,0x40,0x3c,0xd5]
-// CHECK: mrs      x9, elr_el3                // encoding: [0x29,0x40,0x3e,0xd5]
-// CHECK: mrs      x9, sp_el0                 // encoding: [0x09,0x41,0x38,0xd5]
-// CHECK: mrs      x9, sp_el1                 // encoding: [0x09,0x41,0x3c,0xd5]
-// CHECK: mrs      x9, sp_el2                 // encoding: [0x09,0x41,0x3e,0xd5]
-// CHECK: mrs      x9, spsel                  // encoding: [0x09,0x42,0x38,0xd5]
-// CHECK: mrs      x9, nzcv                   // encoding: [0x09,0x42,0x3b,0xd5]
-// CHECK: mrs      x9, daif                   // encoding: [0x29,0x42,0x3b,0xd5]
-// CHECK: mrs      x9, currentel              // encoding: [0x49,0x42,0x38,0xd5]
-// CHECK: mrs      x9, spsr_irq               // encoding: [0x09,0x43,0x3c,0xd5]
-// CHECK: mrs      x9, spsr_abt               // encoding: [0x29,0x43,0x3c,0xd5]
-// CHECK: mrs      x9, spsr_und               // encoding: [0x49,0x43,0x3c,0xd5]
-// CHECK: mrs      x9, spsr_fiq               // encoding: [0x69,0x43,0x3c,0xd5]
-// CHECK: mrs      x9, fpcr                   // encoding: [0x09,0x44,0x3b,0xd5]
-// CHECK: mrs      x9, fpsr                   // encoding: [0x29,0x44,0x3b,0xd5]
-// CHECK: mrs      x9, dspsr_el0              // encoding: [0x09,0x45,0x3b,0xd5]
-// CHECK: mrs      x9, dlr_el0                // encoding: [0x29,0x45,0x3b,0xd5]
-// CHECK: mrs      x9, ifsr32_el2             // encoding: [0x29,0x50,0x3c,0xd5]
-// CHECK: mrs      x9, afsr0_el1              // encoding: [0x09,0x51,0x38,0xd5]
-// CHECK: mrs      x9, afsr0_el2              // encoding: [0x09,0x51,0x3c,0xd5]
-// CHECK: mrs      x9, afsr0_el3              // encoding: [0x09,0x51,0x3e,0xd5]
-// CHECK: mrs      x9, afsr1_el1              // encoding: [0x29,0x51,0x38,0xd5]
-// CHECK: mrs      x9, afsr1_el2              // encoding: [0x29,0x51,0x3c,0xd5]
-// CHECK: mrs      x9, afsr1_el3              // encoding: [0x29,0x51,0x3e,0xd5]
-// CHECK: mrs      x9, esr_el1                // encoding: [0x09,0x52,0x38,0xd5]
-// CHECK: mrs      x9, esr_el2                // encoding: [0x09,0x52,0x3c,0xd5]
-// CHECK: mrs      x9, esr_el3                // encoding: [0x09,0x52,0x3e,0xd5]
-// CHECK: mrs      x9, fpexc32_el2            // encoding: [0x09,0x53,0x3c,0xd5]
-// CHECK: mrs      x9, far_el1                // encoding: [0x09,0x60,0x38,0xd5]
-// CHECK: mrs      x9, far_el2                // encoding: [0x09,0x60,0x3c,0xd5]
-// CHECK: mrs      x9, far_el3                // encoding: [0x09,0x60,0x3e,0xd5]
-// CHECK: mrs      x9, hpfar_el2              // encoding: [0x89,0x60,0x3c,0xd5]
-// CHECK: mrs      x9, par_el1                // encoding: [0x09,0x74,0x38,0xd5]
-// CHECK: mrs      x9, pmcr_el0               // encoding: [0x09,0x9c,0x3b,0xd5]
-// CHECK: mrs      x9, pmcntenset_el0         // encoding: [0x29,0x9c,0x3b,0xd5]
-// CHECK: mrs      x9, pmcntenclr_el0         // encoding: [0x49,0x9c,0x3b,0xd5]
-// CHECK: mrs      x9, pmovsclr_el0           // encoding: [0x69,0x9c,0x3b,0xd5]
-// CHECK: mrs      x9, pmselr_el0             // encoding: [0xa9,0x9c,0x3b,0xd5]
-// CHECK: mrs      x9, pmceid0_el0            // encoding: [0xc9,0x9c,0x3b,0xd5]
-// CHECK: mrs      x9, pmceid1_el0            // encoding: [0xe9,0x9c,0x3b,0xd5]
-// CHECK: mrs      x9, pmccntr_el0            // encoding: [0x09,0x9d,0x3b,0xd5]
-// CHECK: mrs      x9, pmxevtyper_el0         // encoding: [0x29,0x9d,0x3b,0xd5]
-// CHECK: mrs      x9, pmxevcntr_el0          // encoding: [0x49,0x9d,0x3b,0xd5]
-// CHECK: mrs      x9, pmuserenr_el0          // encoding: [0x09,0x9e,0x3b,0xd5]
-// CHECK: mrs      x9, pmintenset_el1         // encoding: [0x29,0x9e,0x38,0xd5]
-// CHECK: mrs      x9, pmintenclr_el1         // encoding: [0x49,0x9e,0x38,0xd5]
-// CHECK: mrs      x9, pmovsset_el0           // encoding: [0x69,0x9e,0x3b,0xd5]
-// CHECK: mrs      x9, mair_el1               // encoding: [0x09,0xa2,0x38,0xd5]
-// CHECK: mrs      x9, mair_el2               // encoding: [0x09,0xa2,0x3c,0xd5]
-// CHECK: mrs      x9, mair_el3               // encoding: [0x09,0xa2,0x3e,0xd5]
-// CHECK: mrs      x9, amair_el1              // encoding: [0x09,0xa3,0x38,0xd5]
-// CHECK: mrs      x9, amair_el2              // encoding: [0x09,0xa3,0x3c,0xd5]
-// CHECK: mrs      x9, amair_el3              // encoding: [0x09,0xa3,0x3e,0xd5]
-// CHECK: mrs      x9, vbar_el1               // encoding: [0x09,0xc0,0x38,0xd5]
-// CHECK: mrs      x9, vbar_el2               // encoding: [0x09,0xc0,0x3c,0xd5]
-// CHECK: mrs      x9, vbar_el3               // encoding: [0x09,0xc0,0x3e,0xd5]
-// CHECK: mrs      x9, rvbar_el1              // encoding: [0x29,0xc0,0x38,0xd5]
-// CHECK: mrs      x9, rvbar_el2              // encoding: [0x29,0xc0,0x3c,0xd5]
-// CHECK: mrs      x9, rvbar_el3              // encoding: [0x29,0xc0,0x3e,0xd5]
-// CHECK: mrs      x9, rmr_el1                // encoding: [0x49,0xc0,0x38,0xd5]
-// CHECK: mrs      x9, rmr_el2                // encoding: [0x49,0xc0,0x3c,0xd5]
-// CHECK: mrs      x9, rmr_el3                // encoding: [0x49,0xc0,0x3e,0xd5]
-// CHECK: mrs      x9, isr_el1                // encoding: [0x09,0xc1,0x38,0xd5]
-// CHECK: mrs      x9, contextidr_el1         // encoding: [0x29,0xd0,0x38,0xd5]
-// CHECK: mrs      x9, tpidr_el0              // encoding: [0x49,0xd0,0x3b,0xd5]
-// CHECK: mrs      x9, tpidr_el2              // encoding: [0x49,0xd0,0x3c,0xd5]
-// CHECK: mrs      x9, tpidr_el3              // encoding: [0x49,0xd0,0x3e,0xd5]
-// CHECK: mrs      x9, tpidrro_el0            // encoding: [0x69,0xd0,0x3b,0xd5]
-// CHECK: mrs      x9, tpidr_el1              // encoding: [0x89,0xd0,0x38,0xd5]
-// CHECK: mrs      x9, cntfrq_el0             // encoding: [0x09,0xe0,0x3b,0xd5]
-// CHECK: mrs      x9, cntpct_el0             // encoding: [0x29,0xe0,0x3b,0xd5]
-// CHECK: mrs      x9, cntvct_el0             // encoding: [0x49,0xe0,0x3b,0xd5]
-// CHECK: mrs      x9, cntvoff_el2            // encoding: [0x69,0xe0,0x3c,0xd5]
-// CHECK: mrs      x9, cntkctl_el1            // encoding: [0x09,0xe1,0x38,0xd5]
-// CHECK: mrs      x9, cnthctl_el2            // encoding: [0x09,0xe1,0x3c,0xd5]
-// CHECK: mrs      x9, cntp_tval_el0          // encoding: [0x09,0xe2,0x3b,0xd5]
-// CHECK: mrs      x9, cnthp_tval_el2         // encoding: [0x09,0xe2,0x3c,0xd5]
-// CHECK: mrs      x9, cntps_tval_el1         // encoding: [0x09,0xe2,0x3f,0xd5]
-// CHECK: mrs      x9, cntp_ctl_el0           // encoding: [0x29,0xe2,0x3b,0xd5]
-// CHECK: mrs      x9, cnthp_ctl_el2          // encoding: [0x29,0xe2,0x3c,0xd5]
-// CHECK: mrs      x9, cntps_ctl_el1          // encoding: [0x29,0xe2,0x3f,0xd5]
-// CHECK: mrs      x9, cntp_cval_el0          // encoding: [0x49,0xe2,0x3b,0xd5]
-// CHECK: mrs      x9, cnthp_cval_el2         // encoding: [0x49,0xe2,0x3c,0xd5]
-// CHECK: mrs      x9, cntps_cval_el1         // encoding: [0x49,0xe2,0x3f,0xd5]
-// CHECK: mrs      x9, cntv_tval_el0          // encoding: [0x09,0xe3,0x3b,0xd5]
-// CHECK: mrs      x9, cntv_ctl_el0           // encoding: [0x29,0xe3,0x3b,0xd5]
-// CHECK: mrs      x9, cntv_cval_el0          // encoding: [0x49,0xe3,0x3b,0xd5]
-// CHECK: mrs      x9, pmevcntr0_el0          // encoding: [0x09,0xe8,0x3b,0xd5]
-// CHECK: mrs      x9, pmevcntr1_el0          // encoding: [0x29,0xe8,0x3b,0xd5]
-// CHECK: mrs      x9, pmevcntr2_el0          // encoding: [0x49,0xe8,0x3b,0xd5]
-// CHECK: mrs      x9, pmevcntr3_el0          // encoding: [0x69,0xe8,0x3b,0xd5]
-// CHECK: mrs      x9, pmevcntr4_el0          // encoding: [0x89,0xe8,0x3b,0xd5]
-// CHECK: mrs      x9, pmevcntr5_el0          // encoding: [0xa9,0xe8,0x3b,0xd5]
-// CHECK: mrs      x9, pmevcntr6_el0          // encoding: [0xc9,0xe8,0x3b,0xd5]
-// CHECK: mrs      x9, pmevcntr7_el0          // encoding: [0xe9,0xe8,0x3b,0xd5]
-// CHECK: mrs      x9, pmevcntr8_el0          // encoding: [0x09,0xe9,0x3b,0xd5]
-// CHECK: mrs      x9, pmevcntr9_el0          // encoding: [0x29,0xe9,0x3b,0xd5]
-// CHECK: mrs      x9, pmevcntr10_el0         // encoding: [0x49,0xe9,0x3b,0xd5]
-// CHECK: mrs      x9, pmevcntr11_el0         // encoding: [0x69,0xe9,0x3b,0xd5]
-// CHECK: mrs      x9, pmevcntr12_el0         // encoding: [0x89,0xe9,0x3b,0xd5]
-// CHECK: mrs      x9, pmevcntr13_el0         // encoding: [0xa9,0xe9,0x3b,0xd5]
-// CHECK: mrs      x9, pmevcntr14_el0         // encoding: [0xc9,0xe9,0x3b,0xd5]
-// CHECK: mrs      x9, pmevcntr15_el0         // encoding: [0xe9,0xe9,0x3b,0xd5]
-// CHECK: mrs      x9, pmevcntr16_el0         // encoding: [0x09,0xea,0x3b,0xd5]
-// CHECK: mrs      x9, pmevcntr17_el0         // encoding: [0x29,0xea,0x3b,0xd5]
-// CHECK: mrs      x9, pmevcntr18_el0         // encoding: [0x49,0xea,0x3b,0xd5]
-// CHECK: mrs      x9, pmevcntr19_el0         // encoding: [0x69,0xea,0x3b,0xd5]
-// CHECK: mrs      x9, pmevcntr20_el0         // encoding: [0x89,0xea,0x3b,0xd5]
-// CHECK: mrs      x9, pmevcntr21_el0         // encoding: [0xa9,0xea,0x3b,0xd5]
-// CHECK: mrs      x9, pmevcntr22_el0         // encoding: [0xc9,0xea,0x3b,0xd5]
-// CHECK: mrs      x9, pmevcntr23_el0         // encoding: [0xe9,0xea,0x3b,0xd5]
-// CHECK: mrs      x9, pmevcntr24_el0         // encoding: [0x09,0xeb,0x3b,0xd5]
-// CHECK: mrs      x9, pmevcntr25_el0         // encoding: [0x29,0xeb,0x3b,0xd5]
-// CHECK: mrs      x9, pmevcntr26_el0         // encoding: [0x49,0xeb,0x3b,0xd5]
-// CHECK: mrs      x9, pmevcntr27_el0         // encoding: [0x69,0xeb,0x3b,0xd5]
-// CHECK: mrs      x9, pmevcntr28_el0         // encoding: [0x89,0xeb,0x3b,0xd5]
-// CHECK: mrs      x9, pmevcntr29_el0         // encoding: [0xa9,0xeb,0x3b,0xd5]
-// CHECK: mrs      x9, pmevcntr30_el0         // encoding: [0xc9,0xeb,0x3b,0xd5]
-// CHECK: mrs      x9, pmccfiltr_el0          // encoding: [0xe9,0xef,0x3b,0xd5]
-// CHECK: mrs      x9, pmevtyper0_el0         // encoding: [0x09,0xec,0x3b,0xd5]
-// CHECK: mrs      x9, pmevtyper1_el0         // encoding: [0x29,0xec,0x3b,0xd5]
-// CHECK: mrs      x9, pmevtyper2_el0         // encoding: [0x49,0xec,0x3b,0xd5]
-// CHECK: mrs      x9, pmevtyper3_el0         // encoding: [0x69,0xec,0x3b,0xd5]
-// CHECK: mrs      x9, pmevtyper4_el0         // encoding: [0x89,0xec,0x3b,0xd5]
-// CHECK: mrs      x9, pmevtyper5_el0         // encoding: [0xa9,0xec,0x3b,0xd5]
-// CHECK: mrs      x9, pmevtyper6_el0         // encoding: [0xc9,0xec,0x3b,0xd5]
-// CHECK: mrs      x9, pmevtyper7_el0         // encoding: [0xe9,0xec,0x3b,0xd5]
-// CHECK: mrs      x9, pmevtyper8_el0         // encoding: [0x09,0xed,0x3b,0xd5]
-// CHECK: mrs      x9, pmevtyper9_el0         // encoding: [0x29,0xed,0x3b,0xd5]
-// CHECK: mrs      x9, pmevtyper10_el0        // encoding: [0x49,0xed,0x3b,0xd5]
-// CHECK: mrs      x9, pmevtyper11_el0        // encoding: [0x69,0xed,0x3b,0xd5]
-// CHECK: mrs      x9, pmevtyper12_el0        // encoding: [0x89,0xed,0x3b,0xd5]
-// CHECK: mrs      x9, pmevtyper13_el0        // encoding: [0xa9,0xed,0x3b,0xd5]
-// CHECK: mrs      x9, pmevtyper14_el0        // encoding: [0xc9,0xed,0x3b,0xd5]
-// CHECK: mrs      x9, pmevtyper15_el0        // encoding: [0xe9,0xed,0x3b,0xd5]
-// CHECK: mrs      x9, pmevtyper16_el0        // encoding: [0x09,0xee,0x3b,0xd5]
-// CHECK: mrs      x9, pmevtyper17_el0        // encoding: [0x29,0xee,0x3b,0xd5]
-// CHECK: mrs      x9, pmevtyper18_el0        // encoding: [0x49,0xee,0x3b,0xd5]
-// CHECK: mrs      x9, pmevtyper19_el0        // encoding: [0x69,0xee,0x3b,0xd5]
-// CHECK: mrs      x9, pmevtyper20_el0        // encoding: [0x89,0xee,0x3b,0xd5]
-// CHECK: mrs      x9, pmevtyper21_el0        // encoding: [0xa9,0xee,0x3b,0xd5]
-// CHECK: mrs      x9, pmevtyper22_el0        // encoding: [0xc9,0xee,0x3b,0xd5]
-// CHECK: mrs      x9, pmevtyper23_el0        // encoding: [0xe9,0xee,0x3b,0xd5]
-// CHECK: mrs      x9, pmevtyper24_el0        // encoding: [0x09,0xef,0x3b,0xd5]
-// CHECK: mrs      x9, pmevtyper25_el0        // encoding: [0x29,0xef,0x3b,0xd5]
-// CHECK: mrs      x9, pmevtyper26_el0        // encoding: [0x49,0xef,0x3b,0xd5]
-// CHECK: mrs      x9, pmevtyper27_el0        // encoding: [0x69,0xef,0x3b,0xd5]
-// CHECK: mrs      x9, pmevtyper28_el0        // encoding: [0x89,0xef,0x3b,0xd5]
-// CHECK: mrs      x9, pmevtyper29_el0        // encoding: [0xa9,0xef,0x3b,0xd5]
-// CHECK: mrs      x9, pmevtyper30_el0        // encoding: [0xc9,0xef,0x3b,0xd5]
+// CHECK: mrs      x9, {{teecr32_el1|TEECR32_EL1}}            // encoding: [0x09,0x00,0x32,0xd5]
+// CHECK: mrs      x9, {{osdtrrx_el1|OSDTRRX_EL1}}            // encoding: [0x49,0x00,0x30,0xd5]
+// CHECK: mrs      x9, {{mdccsr_el0|MDCCSR_EL0}}             // encoding: [0x09,0x01,0x33,0xd5]
+// CHECK: mrs      x9, {{mdccint_el1|MDCCINT_EL1}}            // encoding: [0x09,0x02,0x30,0xd5]
+// CHECK: mrs      x9, {{mdscr_el1|MDSCR_EL1}}              // encoding: [0x49,0x02,0x30,0xd5]
+// CHECK: mrs      x9, {{osdtrtx_el1|OSDTRTX_EL1}}            // encoding: [0x49,0x03,0x30,0xd5]
+// CHECK: mrs      x9, {{dbgdtr_el0|DBGDTR_EL0}}             // encoding: [0x09,0x04,0x33,0xd5]
+// CHECK: mrs      x9, {{dbgdtrrx_el0|DBGDTRRX_EL0}}           // encoding: [0x09,0x05,0x33,0xd5]
+// CHECK: mrs      x9, {{oseccr_el1|OSECCR_EL1}}             // encoding: [0x49,0x06,0x30,0xd5]
+// CHECK: mrs      x9, {{dbgvcr32_el2|DBGVCR32_EL2}}           // encoding: [0x09,0x07,0x34,0xd5]
+// CHECK: mrs      x9, {{dbgbvr0_el1|DBGBVR0_EL1}}            // encoding: [0x89,0x00,0x30,0xd5]
+// CHECK: mrs      x9, {{dbgbvr1_el1|DBGBVR1_EL1}}            // encoding: [0x89,0x01,0x30,0xd5]
+// CHECK: mrs      x9, {{dbgbvr2_el1|DBGBVR2_EL1}}            // encoding: [0x89,0x02,0x30,0xd5]
+// CHECK: mrs      x9, {{dbgbvr3_el1|DBGBVR3_EL1}}            // encoding: [0x89,0x03,0x30,0xd5]
+// CHECK: mrs      x9, {{dbgbvr4_el1|DBGBVR4_EL1}}            // encoding: [0x89,0x04,0x30,0xd5]
+// CHECK: mrs      x9, {{dbgbvr5_el1|DBGBVR5_EL1}}            // encoding: [0x89,0x05,0x30,0xd5]
+// CHECK: mrs      x9, {{dbgbvr6_el1|DBGBVR6_EL1}}            // encoding: [0x89,0x06,0x30,0xd5]
+// CHECK: mrs      x9, {{dbgbvr7_el1|DBGBVR7_EL1}}            // encoding: [0x89,0x07,0x30,0xd5]
+// CHECK: mrs      x9, {{dbgbvr8_el1|DBGBVR8_EL1}}            // encoding: [0x89,0x08,0x30,0xd5]
+// CHECK: mrs      x9, {{dbgbvr9_el1|DBGBVR9_EL1}}            // encoding: [0x89,0x09,0x30,0xd5]
+// CHECK: mrs      x9, {{dbgbvr10_el1|DBGBVR10_EL1}}           // encoding: [0x89,0x0a,0x30,0xd5]
+// CHECK: mrs      x9, {{dbgbvr11_el1|DBGBVR11_EL1}}           // encoding: [0x89,0x0b,0x30,0xd5]
+// CHECK: mrs      x9, {{dbgbvr12_el1|DBGBVR12_EL1}}           // encoding: [0x89,0x0c,0x30,0xd5]
+// CHECK: mrs      x9, {{dbgbvr13_el1|DBGBVR13_EL1}}           // encoding: [0x89,0x0d,0x30,0xd5]
+// CHECK: mrs      x9, {{dbgbvr14_el1|DBGBVR14_EL1}}           // encoding: [0x89,0x0e,0x30,0xd5]
+// CHECK: mrs      x9, {{dbgbvr15_el1|DBGBVR15_EL1}}           // encoding: [0x89,0x0f,0x30,0xd5]
+// CHECK: mrs      x9, {{dbgbcr0_el1|DBGBCR0_EL1}}            // encoding: [0xa9,0x00,0x30,0xd5]
+// CHECK: mrs      x9, {{dbgbcr1_el1|DBGBCR1_EL1}}            // encoding: [0xa9,0x01,0x30,0xd5]
+// CHECK: mrs      x9, {{dbgbcr2_el1|DBGBCR2_EL1}}            // encoding: [0xa9,0x02,0x30,0xd5]
+// CHECK: mrs      x9, {{dbgbcr3_el1|DBGBCR3_EL1}}            // encoding: [0xa9,0x03,0x30,0xd5]
+// CHECK: mrs      x9, {{dbgbcr4_el1|DBGBCR4_EL1}}            // encoding: [0xa9,0x04,0x30,0xd5]
+// CHECK: mrs      x9, {{dbgbcr5_el1|DBGBCR5_EL1}}            // encoding: [0xa9,0x05,0x30,0xd5]
+// CHECK: mrs      x9, {{dbgbcr6_el1|DBGBCR6_EL1}}            // encoding: [0xa9,0x06,0x30,0xd5]
+// CHECK: mrs      x9, {{dbgbcr7_el1|DBGBCR7_EL1}}            // encoding: [0xa9,0x07,0x30,0xd5]
+// CHECK: mrs      x9, {{dbgbcr8_el1|DBGBCR8_EL1}}            // encoding: [0xa9,0x08,0x30,0xd5]
+// CHECK: mrs      x9, {{dbgbcr9_el1|DBGBCR9_EL1}}            // encoding: [0xa9,0x09,0x30,0xd5]
+// CHECK: mrs      x9, {{dbgbcr10_el1|DBGBCR10_EL1}}           // encoding: [0xa9,0x0a,0x30,0xd5]
+// CHECK: mrs      x9, {{dbgbcr11_el1|DBGBCR11_EL1}}           // encoding: [0xa9,0x0b,0x30,0xd5]
+// CHECK: mrs      x9, {{dbgbcr12_el1|DBGBCR12_EL1}}           // encoding: [0xa9,0x0c,0x30,0xd5]
+// CHECK: mrs      x9, {{dbgbcr13_el1|DBGBCR13_EL1}}           // encoding: [0xa9,0x0d,0x30,0xd5]
+// CHECK: mrs      x9, {{dbgbcr14_el1|DBGBCR14_EL1}}           // encoding: [0xa9,0x0e,0x30,0xd5]
+// CHECK: mrs      x9, {{dbgbcr15_el1|DBGBCR15_EL1}}           // encoding: [0xa9,0x0f,0x30,0xd5]
+// CHECK: mrs      x9, {{dbgwvr0_el1|DBGWVR0_EL1}}            // encoding: [0xc9,0x00,0x30,0xd5]
+// CHECK: mrs      x9, {{dbgwvr1_el1|DBGWVR1_EL1}}            // encoding: [0xc9,0x01,0x30,0xd5]
+// CHECK: mrs      x9, {{dbgwvr2_el1|DBGWVR2_EL1}}            // encoding: [0xc9,0x02,0x30,0xd5]
+// CHECK: mrs      x9, {{dbgwvr3_el1|DBGWVR3_EL1}}            // encoding: [0xc9,0x03,0x30,0xd5]
+// CHECK: mrs      x9, {{dbgwvr4_el1|DBGWVR4_EL1}}            // encoding: [0xc9,0x04,0x30,0xd5]
+// CHECK: mrs      x9, {{dbgwvr5_el1|DBGWVR5_EL1}}            // encoding: [0xc9,0x05,0x30,0xd5]
+// CHECK: mrs      x9, {{dbgwvr6_el1|DBGWVR6_EL1}}            // encoding: [0xc9,0x06,0x30,0xd5]
+// CHECK: mrs      x9, {{dbgwvr7_el1|DBGWVR7_EL1}}            // encoding: [0xc9,0x07,0x30,0xd5]
+// CHECK: mrs      x9, {{dbgwvr8_el1|DBGWVR8_EL1}}            // encoding: [0xc9,0x08,0x30,0xd5]
+// CHECK: mrs      x9, {{dbgwvr9_el1|DBGWVR9_EL1}}            // encoding: [0xc9,0x09,0x30,0xd5]
+// CHECK: mrs      x9, {{dbgwvr10_el1|DBGWVR10_EL1}}           // encoding: [0xc9,0x0a,0x30,0xd5]
+// CHECK: mrs      x9, {{dbgwvr11_el1|DBGWVR11_EL1}}           // encoding: [0xc9,0x0b,0x30,0xd5]
+// CHECK: mrs      x9, {{dbgwvr12_el1|DBGWVR12_EL1}}           // encoding: [0xc9,0x0c,0x30,0xd5]
+// CHECK: mrs      x9, {{dbgwvr13_el1|DBGWVR13_EL1}}           // encoding: [0xc9,0x0d,0x30,0xd5]
+// CHECK: mrs      x9, {{dbgwvr14_el1|DBGWVR14_EL1}}           // encoding: [0xc9,0x0e,0x30,0xd5]
+// CHECK: mrs      x9, {{dbgwvr15_el1|DBGWVR15_EL1}}           // encoding: [0xc9,0x0f,0x30,0xd5]
+// CHECK: mrs      x9, {{dbgwcr0_el1|DBGWCR0_EL1}}            // encoding: [0xe9,0x00,0x30,0xd5]
+// CHECK: mrs      x9, {{dbgwcr1_el1|DBGWCR1_EL1}}            // encoding: [0xe9,0x01,0x30,0xd5]
+// CHECK: mrs      x9, {{dbgwcr2_el1|DBGWCR2_EL1}}            // encoding: [0xe9,0x02,0x30,0xd5]
+// CHECK: mrs      x9, {{dbgwcr3_el1|DBGWCR3_EL1}}            // encoding: [0xe9,0x03,0x30,0xd5]
+// CHECK: mrs      x9, {{dbgwcr4_el1|DBGWCR4_EL1}}            // encoding: [0xe9,0x04,0x30,0xd5]
+// CHECK: mrs      x9, {{dbgwcr5_el1|DBGWCR5_EL1}}            // encoding: [0xe9,0x05,0x30,0xd5]
+// CHECK: mrs      x9, {{dbgwcr6_el1|DBGWCR6_EL1}}            // encoding: [0xe9,0x06,0x30,0xd5]
+// CHECK: mrs      x9, {{dbgwcr7_el1|DBGWCR7_EL1}}            // encoding: [0xe9,0x07,0x30,0xd5]
+// CHECK: mrs      x9, {{dbgwcr8_el1|DBGWCR8_EL1}}            // encoding: [0xe9,0x08,0x30,0xd5]
+// CHECK: mrs      x9, {{dbgwcr9_el1|DBGWCR9_EL1}}            // encoding: [0xe9,0x09,0x30,0xd5]
+// CHECK: mrs      x9, {{dbgwcr10_el1|DBGWCR10_EL1}}           // encoding: [0xe9,0x0a,0x30,0xd5]
+// CHECK: mrs      x9, {{dbgwcr11_el1|DBGWCR11_EL1}}           // encoding: [0xe9,0x0b,0x30,0xd5]
+// CHECK: mrs      x9, {{dbgwcr12_el1|DBGWCR12_EL1}}           // encoding: [0xe9,0x0c,0x30,0xd5]
+// CHECK: mrs      x9, {{dbgwcr13_el1|DBGWCR13_EL1}}           // encoding: [0xe9,0x0d,0x30,0xd5]
+// CHECK: mrs      x9, {{dbgwcr14_el1|DBGWCR14_EL1}}           // encoding: [0xe9,0x0e,0x30,0xd5]
+// CHECK: mrs      x9, {{dbgwcr15_el1|DBGWCR15_EL1}}           // encoding: [0xe9,0x0f,0x30,0xd5]
+// CHECK: mrs      x9, {{mdrar_el1|MDRAR_EL1}}              // encoding: [0x09,0x10,0x30,0xd5]
+// CHECK: mrs      x9, {{teehbr32_el1|TEEHBR32_EL1}}           // encoding: [0x09,0x10,0x32,0xd5]
+// CHECK: mrs      x9, {{oslsr_el1|OSLSR_EL1}}              // encoding: [0x89,0x11,0x30,0xd5]
+// CHECK: mrs      x9, {{osdlr_el1|OSDLR_EL1}}              // encoding: [0x89,0x13,0x30,0xd5]
+// CHECK: mrs      x9, {{dbgprcr_el1|DBGPRCR_EL1}}            // encoding: [0x89,0x14,0x30,0xd5]
+// CHECK: mrs      x9, {{dbgclaimset_el1|DBGCLAIMSET_EL1}}        // encoding: [0xc9,0x78,0x30,0xd5]
+// CHECK: mrs      x9, {{dbgclaimclr_el1|DBGCLAIMCLR_EL1}}        // encoding: [0xc9,0x79,0x30,0xd5]
+// CHECK: mrs      x9, {{dbgauthstatus_el1|DBGAUTHSTATUS_EL1}}      // encoding: [0xc9,0x7e,0x30,0xd5]
+// CHECK: mrs      x9, {{midr_el1|MIDR_EL1}}               // encoding: [0x09,0x00,0x38,0xd5]
+// CHECK: mrs      x9, {{ccsidr_el1|CCSIDR_EL1}}             // encoding: [0x09,0x00,0x39,0xd5]
+// CHECK: mrs      x9, {{csselr_el1|CSSELR_EL1}}             // encoding: [0x09,0x00,0x3a,0xd5]
+// CHECK: mrs      x9, {{vpidr_el2|VPIDR_EL2}}              // encoding: [0x09,0x00,0x3c,0xd5]
+// CHECK: mrs      x9, {{clidr_el1|CLIDR_EL1}}              // encoding: [0x29,0x00,0x39,0xd5]
+// CHECK: mrs      x9, {{ctr_el0|CTR_EL0}}                // encoding: [0x29,0x00,0x3b,0xd5]
+// CHECK: mrs      x9, {{mpidr_el1|MPIDR_EL1}}              // encoding: [0xa9,0x00,0x38,0xd5]
+// CHECK: mrs      x9, {{vmpidr_el2|VMPIDR_EL2}}             // encoding: [0xa9,0x00,0x3c,0xd5]
+// CHECK: mrs      x9, {{revidr_el1|REVIDR_EL1}}             // encoding: [0xc9,0x00,0x38,0xd5]
+// CHECK: mrs      x9, {{aidr_el1|AIDR_EL1}}               // encoding: [0xe9,0x00,0x39,0xd5]
+// CHECK: mrs      x9, {{dczid_el0|DCZID_EL0}}              // encoding: [0xe9,0x00,0x3b,0xd5]
+// CHECK: mrs      x9, {{id_pfr0_el1|ID_PFR0_EL1}}            // encoding: [0x09,0x01,0x38,0xd5]
+// CHECK: mrs      x9, {{id_pfr1_el1|ID_PFR1_EL1}}            // encoding: [0x29,0x01,0x38,0xd5]
+// CHECK: mrs      x9, {{id_dfr0_el1|ID_DFR0_EL1}}            // encoding: [0x49,0x01,0x38,0xd5]
+// CHECK: mrs      x9, {{id_afr0_el1|ID_AFR0_EL1}}            // encoding: [0x69,0x01,0x38,0xd5]
+// CHECK: mrs      x9, {{id_mmfr0_el1|ID_MMFR0_EL1}}           // encoding: [0x89,0x01,0x38,0xd5]
+// CHECK: mrs      x9, {{id_mmfr1_el1|ID_MMFR1_EL1}}           // encoding: [0xa9,0x01,0x38,0xd5]
+// CHECK: mrs      x9, {{id_mmfr2_el1|ID_MMFR2_EL1}}           // encoding: [0xc9,0x01,0x38,0xd5]
+// CHECK: mrs      x9, {{id_mmfr3_el1|ID_MMFR3_EL1}}           // encoding: [0xe9,0x01,0x38,0xd5]
+// CHECK: mrs      x9, {{id_isar0_el1|ID_ISAR0_EL1}}           // encoding: [0x09,0x02,0x38,0xd5]
+// CHECK: mrs      x9, {{id_isar1_el1|ID_ISAR1_EL1}}           // encoding: [0x29,0x02,0x38,0xd5]
+// CHECK: mrs      x9, {{id_isar2_el1|ID_ISAR2_EL1}}           // encoding: [0x49,0x02,0x38,0xd5]
+// CHECK: mrs      x9, {{id_isar3_el1|ID_ISAR3_EL1}}           // encoding: [0x69,0x02,0x38,0xd5]
+// CHECK: mrs      x9, {{id_isar4_el1|ID_ISAR4_EL1}}           // encoding: [0x89,0x02,0x38,0xd5]
+// CHECK: mrs      x9, {{id_isar5_el1|ID_ISAR5_EL1}}           // encoding: [0xa9,0x02,0x38,0xd5]
+// CHECK: mrs      x9, {{mvfr0_el1|MVFR0_EL1}}              // encoding: [0x09,0x03,0x38,0xd5]
+// CHECK: mrs      x9, {{mvfr1_el1|MVFR1_EL1}}              // encoding: [0x29,0x03,0x38,0xd5]
+// CHECK: mrs      x9, {{mvfr2_el1|MVFR2_EL1}}              // encoding: [0x49,0x03,0x38,0xd5]
+// CHECK: mrs      x9, {{id_aa64pfr0_el1|ID_AA64PFR0_EL1}}        // encoding: [0x09,0x04,0x38,0xd5]
+// CHECK: mrs      x9, {{id_aa64pfr1_el1|ID_AA64PFR1_EL1}}        // encoding: [0x29,0x04,0x38,0xd5]
+// CHECK: mrs      x9, {{id_aa64dfr0_el1|ID_AA64DFR0_EL1}}        // encoding: [0x09,0x05,0x38,0xd5]
+// CHECK: mrs      x9, {{id_aa64dfr1_el1|ID_AA64DFR1_EL1}}        // encoding: [0x29,0x05,0x38,0xd5]
+// CHECK: mrs      x9, {{id_aa64afr0_el1|ID_AA64AFR0_EL1}}        // encoding: [0x89,0x05,0x38,0xd5]
+// CHECK: mrs      x9, {{id_aa64afr1_el1|ID_AA64AFR1_EL1}}        // encoding: [0xa9,0x05,0x38,0xd5]
+// CHECK: mrs      x9, {{id_aa64isar0_el1|ID_AA64ISAR0_EL1}}       // encoding: [0x09,0x06,0x38,0xd5]
+// CHECK: mrs      x9, {{id_aa64isar1_el1|ID_AA64ISAR1_EL1}}       // encoding: [0x29,0x06,0x38,0xd5]
+// CHECK: mrs      x9, {{id_aa64mmfr0_el1|ID_AA64MMFR0_EL1}}       // encoding: [0x09,0x07,0x38,0xd5]
+// CHECK: mrs      x9, {{id_aa64mmfr1_el1|ID_AA64MMFR1_EL1}}       // encoding: [0x29,0x07,0x38,0xd5]
+// CHECK: mrs      x9, {{sctlr_el1|SCTLR_EL1}}              // encoding: [0x09,0x10,0x38,0xd5]
+// CHECK: mrs      x9, {{sctlr_el2|SCTLR_EL2}}              // encoding: [0x09,0x10,0x3c,0xd5]
+// CHECK: mrs      x9, {{sctlr_el3|SCTLR_EL3}}              // encoding: [0x09,0x10,0x3e,0xd5]
+// CHECK: mrs      x9, {{actlr_el1|ACTLR_EL1}}              // encoding: [0x29,0x10,0x38,0xd5]
+// CHECK: mrs      x9, {{actlr_el2|ACTLR_EL2}}              // encoding: [0x29,0x10,0x3c,0xd5]
+// CHECK: mrs      x9, {{actlr_el3|ACTLR_EL3}}              // encoding: [0x29,0x10,0x3e,0xd5]
+// CHECK: mrs      x9, {{cpacr_el1|CPACR_EL1}}              // encoding: [0x49,0x10,0x38,0xd5]
+// CHECK: mrs      x9, {{hcr_el2|HCR_EL2}}                // encoding: [0x09,0x11,0x3c,0xd5]
+// CHECK: mrs      x9, {{scr_el3|SCR_EL3}}                // encoding: [0x09,0x11,0x3e,0xd5]
+// CHECK: mrs      x9, {{mdcr_el2|MDCR_EL2}}               // encoding: [0x29,0x11,0x3c,0xd5]
+// CHECK: mrs      x9, {{sder32_el3|SDER32_EL3}}             // encoding: [0x29,0x11,0x3e,0xd5]
+// CHECK: mrs      x9, {{cptr_el2|CPTR_EL2}}               // encoding: [0x49,0x11,0x3c,0xd5]
+// CHECK: mrs      x9, {{cptr_el3|CPTR_EL3}}               // encoding: [0x49,0x11,0x3e,0xd5]
+// CHECK: mrs      x9, {{hstr_el2|HSTR_EL2}}               // encoding: [0x69,0x11,0x3c,0xd5]
+// CHECK: mrs      x9, {{hacr_el2|HACR_EL2}}               // encoding: [0xe9,0x11,0x3c,0xd5]
+// CHECK: mrs      x9, {{mdcr_el3|MDCR_EL3}}               // encoding: [0x29,0x13,0x3e,0xd5]
+// CHECK: mrs      x9, {{ttbr0_el1|TTBR0_EL1}}              // encoding: [0x09,0x20,0x38,0xd5]
+// CHECK: mrs      x9, {{ttbr0_el2|TTBR0_EL2}}              // encoding: [0x09,0x20,0x3c,0xd5]
+// CHECK: mrs      x9, {{ttbr0_el3|TTBR0_EL3}}              // encoding: [0x09,0x20,0x3e,0xd5]
+// CHECK: mrs      x9, {{ttbr1_el1|TTBR1_EL1}}              // encoding: [0x29,0x20,0x38,0xd5]
+// CHECK: mrs      x9, {{tcr_el1|TCR_EL1}}                // encoding: [0x49,0x20,0x38,0xd5]
+// CHECK: mrs      x9, {{tcr_el2|TCR_EL2}}                // encoding: [0x49,0x20,0x3c,0xd5]
+// CHECK: mrs      x9, {{tcr_el3|TCR_EL3}}                // encoding: [0x49,0x20,0x3e,0xd5]
+// CHECK: mrs      x9, {{vttbr_el2|VTTBR_EL2}}              // encoding: [0x09,0x21,0x3c,0xd5]
+// CHECK: mrs      x9, {{vtcr_el2|VTCR_EL2}}               // encoding: [0x49,0x21,0x3c,0xd5]
+// CHECK: mrs      x9, {{dacr32_el2|DACR32_EL2}}             // encoding: [0x09,0x30,0x3c,0xd5]
+// CHECK: mrs      x9, {{spsr_el1|SPSR_EL1}}               // encoding: [0x09,0x40,0x38,0xd5]
+// CHECK: mrs      x9, {{spsr_el2|SPSR_EL2}}               // encoding: [0x09,0x40,0x3c,0xd5]
+// CHECK: mrs      x9, {{spsr_el3|SPSR_EL3}}               // encoding: [0x09,0x40,0x3e,0xd5]
+// CHECK: mrs      x9, {{elr_el1|ELR_EL1}}                // encoding: [0x29,0x40,0x38,0xd5]
+// CHECK: mrs      x9, {{elr_el2|ELR_EL2}}                // encoding: [0x29,0x40,0x3c,0xd5]
+// CHECK: mrs      x9, {{elr_el3|ELR_EL3}}                // encoding: [0x29,0x40,0x3e,0xd5]
+// CHECK: mrs      x9, {{sp_el0|SP_EL0}}                 // encoding: [0x09,0x41,0x38,0xd5]
+// CHECK: mrs      x9, {{sp_el1|SP_EL1}}                 // encoding: [0x09,0x41,0x3c,0xd5]
+// CHECK: mrs      x9, {{sp_el2|SP_EL2}}                 // encoding: [0x09,0x41,0x3e,0xd5]
+// CHECK: mrs      x9, {{spsel|SPSEL}}                  // encoding: [0x09,0x42,0x38,0xd5]
+// CHECK: mrs      x9, {{nzcv|NZCV}}                   // encoding: [0x09,0x42,0x3b,0xd5]
+// CHECK: mrs      x9, {{daif|DAIF}}                   // encoding: [0x29,0x42,0x3b,0xd5]
+// CHECK: mrs      x9, {{currentel|CURRENTEL}}              // encoding: [0x49,0x42,0x38,0xd5]
+// CHECK: mrs      x9, {{spsr_irq|SPSR_IRQ}}               // encoding: [0x09,0x43,0x3c,0xd5]
+// CHECK: mrs      x9, {{spsr_abt|SPSR_ABT}}               // encoding: [0x29,0x43,0x3c,0xd5]
+// CHECK: mrs      x9, {{spsr_und|SPSR_UND}}               // encoding: [0x49,0x43,0x3c,0xd5]
+// CHECK: mrs      x9, {{spsr_fiq|SPSR_FIQ}}               // encoding: [0x69,0x43,0x3c,0xd5]
+// CHECK: mrs      x9, {{fpcr|FPCR}}                   // encoding: [0x09,0x44,0x3b,0xd5]
+// CHECK: mrs      x9, {{fpsr|FPSR}}                   // encoding: [0x29,0x44,0x3b,0xd5]
+// CHECK: mrs      x9, {{dspsr_el0|DSPSR_EL0}}              // encoding: [0x09,0x45,0x3b,0xd5]
+// CHECK: mrs      x9, {{dlr_el0|DLR_EL0}}                // encoding: [0x29,0x45,0x3b,0xd5]
+// CHECK: mrs      x9, {{ifsr32_el2|IFSR32_EL2}}             // encoding: [0x29,0x50,0x3c,0xd5]
+// CHECK: mrs      x9, {{afsr0_el1|AFSR0_EL1}}              // encoding: [0x09,0x51,0x38,0xd5]
+// CHECK: mrs      x9, {{afsr0_el2|AFSR0_EL2}}              // encoding: [0x09,0x51,0x3c,0xd5]
+// CHECK: mrs      x9, {{afsr0_el3|AFSR0_EL3}}              // encoding: [0x09,0x51,0x3e,0xd5]
+// CHECK: mrs      x9, {{afsr1_el1|AFSR1_EL1}}              // encoding: [0x29,0x51,0x38,0xd5]
+// CHECK: mrs      x9, {{afsr1_el2|AFSR1_EL2}}              // encoding: [0x29,0x51,0x3c,0xd5]
+// CHECK: mrs      x9, {{afsr1_el3|AFSR1_EL3}}              // encoding: [0x29,0x51,0x3e,0xd5]
+// CHECK: mrs      x9, {{esr_el1|ESR_EL1}}                // encoding: [0x09,0x52,0x38,0xd5]
+// CHECK: mrs      x9, {{esr_el2|ESR_EL2}}                // encoding: [0x09,0x52,0x3c,0xd5]
+// CHECK: mrs      x9, {{esr_el3|ESR_EL3}}                // encoding: [0x09,0x52,0x3e,0xd5]
+// CHECK: mrs      x9, {{fpexc32_el2|FPEXC32_EL2}}            // encoding: [0x09,0x53,0x3c,0xd5]
+// CHECK: mrs      x9, {{far_el1|FAR_EL1}}                // encoding: [0x09,0x60,0x38,0xd5]
+// CHECK: mrs      x9, {{far_el2|FAR_EL2}}                // encoding: [0x09,0x60,0x3c,0xd5]
+// CHECK: mrs      x9, {{far_el3|FAR_EL3}}                // encoding: [0x09,0x60,0x3e,0xd5]
+// CHECK: mrs      x9, {{hpfar_el2|HPFAR_EL2}}              // encoding: [0x89,0x60,0x3c,0xd5]
+// CHECK: mrs      x9, {{par_el1|PAR_EL1}}                // encoding: [0x09,0x74,0x38,0xd5]
+// CHECK: mrs      x9, {{pmcr_el0|PMCR_EL0}}               // encoding: [0x09,0x9c,0x3b,0xd5]
+// CHECK: mrs      x9, {{pmcntenset_el0|PMCNTENSET_EL0}}         // encoding: [0x29,0x9c,0x3b,0xd5]
+// CHECK: mrs      x9, {{pmcntenclr_el0|PMCNTENCLR_EL0}}         // encoding: [0x49,0x9c,0x3b,0xd5]
+// CHECK: mrs      x9, {{pmovsclr_el0|PMOVSCLR_EL0}}           // encoding: [0x69,0x9c,0x3b,0xd5]
+// CHECK: mrs      x9, {{pmselr_el0|PMSELR_EL0}}             // encoding: [0xa9,0x9c,0x3b,0xd5]
+// CHECK: mrs      x9, {{pmceid0_el0|PMCEID0_EL0}}            // encoding: [0xc9,0x9c,0x3b,0xd5]
+// CHECK: mrs      x9, {{pmceid1_el0|PMCEID1_EL0}}            // encoding: [0xe9,0x9c,0x3b,0xd5]
+// CHECK: mrs      x9, {{pmccntr_el0|PMCCNTR_EL0}}            // encoding: [0x09,0x9d,0x3b,0xd5]
+// CHECK: mrs      x9, {{pmxevtyper_el0|PMXEVTYPER_EL0}}         // encoding: [0x29,0x9d,0x3b,0xd5]
+// CHECK: mrs      x9, {{pmxevcntr_el0|PMXEVCNTR_EL0}}          // encoding: [0x49,0x9d,0x3b,0xd5]
+// CHECK: mrs      x9, {{pmuserenr_el0|PMUSERENR_EL0}}          // encoding: [0x09,0x9e,0x3b,0xd5]
+// CHECK: mrs      x9, {{pmintenset_el1|PMINTENSET_EL1}}         // encoding: [0x29,0x9e,0x38,0xd5]
+// CHECK: mrs      x9, {{pmintenclr_el1|PMINTENCLR_EL1}}         // encoding: [0x49,0x9e,0x38,0xd5]
+// CHECK: mrs      x9, {{pmovsset_el0|PMOVSSET_EL0}}           // encoding: [0x69,0x9e,0x3b,0xd5]
+// CHECK: mrs      x9, {{mair_el1|MAIR_EL1}}               // encoding: [0x09,0xa2,0x38,0xd5]
+// CHECK: mrs      x9, {{mair_el2|MAIR_EL2}}               // encoding: [0x09,0xa2,0x3c,0xd5]
+// CHECK: mrs      x9, {{mair_el3|MAIR_EL3}}               // encoding: [0x09,0xa2,0x3e,0xd5]
+// CHECK: mrs      x9, {{amair_el1|AMAIR_EL1}}              // encoding: [0x09,0xa3,0x38,0xd5]
+// CHECK: mrs      x9, {{amair_el2|AMAIR_EL2}}              // encoding: [0x09,0xa3,0x3c,0xd5]
+// CHECK: mrs      x9, {{amair_el3|AMAIR_EL3}}              // encoding: [0x09,0xa3,0x3e,0xd5]
+// CHECK: mrs      x9, {{vbar_el1|VBAR_EL1}}               // encoding: [0x09,0xc0,0x38,0xd5]
+// CHECK: mrs      x9, {{vbar_el2|VBAR_EL2}}               // encoding: [0x09,0xc0,0x3c,0xd5]
+// CHECK: mrs      x9, {{vbar_el3|VBAR_EL3}}               // encoding: [0x09,0xc0,0x3e,0xd5]
+// CHECK: mrs      x9, {{rvbar_el1|RVBAR_EL1}}              // encoding: [0x29,0xc0,0x38,0xd5]
+// CHECK: mrs      x9, {{rvbar_el2|RVBAR_EL2}}              // encoding: [0x29,0xc0,0x3c,0xd5]
+// CHECK: mrs      x9, {{rvbar_el3|RVBAR_EL3}}              // encoding: [0x29,0xc0,0x3e,0xd5]
+// CHECK: mrs      x9, {{rmr_el1|RMR_EL1}}                // encoding: [0x49,0xc0,0x38,0xd5]
+// CHECK: mrs      x9, {{rmr_el2|RMR_EL2}}                // encoding: [0x49,0xc0,0x3c,0xd5]
+// CHECK: mrs      x9, {{rmr_el3|RMR_EL3}}                // encoding: [0x49,0xc0,0x3e,0xd5]
+// CHECK: mrs      x9, {{isr_el1|ISR_EL1}}                // encoding: [0x09,0xc1,0x38,0xd5]
+// CHECK: mrs      x9, {{contextidr_el1|CONTEXTIDR_EL1}}         // encoding: [0x29,0xd0,0x38,0xd5]
+// CHECK: mrs      x9, {{tpidr_el0|TPIDR_EL0}}              // encoding: [0x49,0xd0,0x3b,0xd5]
+// CHECK: mrs      x9, {{tpidr_el2|TPIDR_EL2}}              // encoding: [0x49,0xd0,0x3c,0xd5]
+// CHECK: mrs      x9, {{tpidr_el3|TPIDR_EL3}}              // encoding: [0x49,0xd0,0x3e,0xd5]
+// CHECK: mrs      x9, {{tpidrro_el0|TPIDRRO_EL0}}            // encoding: [0x69,0xd0,0x3b,0xd5]
+// CHECK: mrs      x9, {{tpidr_el1|TPIDR_EL1}}              // encoding: [0x89,0xd0,0x38,0xd5]
+// CHECK: mrs      x9, {{cntfrq_el0|CNTFRQ_EL0}}             // encoding: [0x09,0xe0,0x3b,0xd5]
+// CHECK: mrs      x9, {{cntpct_el0|CNTPCT_EL0}}             // encoding: [0x29,0xe0,0x3b,0xd5]
+// CHECK: mrs      x9, {{cntvct_el0|CNTVCT_EL0}}             // encoding: [0x49,0xe0,0x3b,0xd5]
+// CHECK: mrs      x9, {{cntvoff_el2|CNTVOFF_EL2}}            // encoding: [0x69,0xe0,0x3c,0xd5]
+// CHECK: mrs      x9, {{cntkctl_el1|CNTKCTL_EL1}}            // encoding: [0x09,0xe1,0x38,0xd5]
+// CHECK: mrs      x9, {{cnthctl_el2|CNTHCTL_EL2}}            // encoding: [0x09,0xe1,0x3c,0xd5]
+// CHECK: mrs      x9, {{cntp_tval_el0|CNTP_TVAL_EL0}}          // encoding: [0x09,0xe2,0x3b,0xd5]
+// CHECK: mrs      x9, {{cnthp_tval_el2|CNTHP_TVAL_EL2}}         // encoding: [0x09,0xe2,0x3c,0xd5]
+// CHECK: mrs      x9, {{cntps_tval_el1|CNTPS_TVAL_EL1}}         // encoding: [0x09,0xe2,0x3f,0xd5]
+// CHECK: mrs      x9, {{cntp_ctl_el0|CNTP_CTL_EL0}}           // encoding: [0x29,0xe2,0x3b,0xd5]
+// CHECK: mrs      x9, {{cnthp_ctl_el2|CNTHP_CTL_EL2}}          // encoding: [0x29,0xe2,0x3c,0xd5]
+// CHECK: mrs      x9, {{cntps_ctl_el1|CNTPS_CTL_EL1}}          // encoding: [0x29,0xe2,0x3f,0xd5]
+// CHECK: mrs      x9, {{cntp_cval_el0|CNTP_CVAL_EL0}}          // encoding: [0x49,0xe2,0x3b,0xd5]
+// CHECK: mrs      x9, {{cnthp_cval_el2|CNTHP_CVAL_EL2}}         // encoding: [0x49,0xe2,0x3c,0xd5]
+// CHECK: mrs      x9, {{cntps_cval_el1|CNTPS_CVAL_EL1}}         // encoding: [0x49,0xe2,0x3f,0xd5]
+// CHECK: mrs      x9, {{cntv_tval_el0|CNTV_TVAL_EL0}}          // encoding: [0x09,0xe3,0x3b,0xd5]
+// CHECK: mrs      x9, {{cntv_ctl_el0|CNTV_CTL_EL0}}           // encoding: [0x29,0xe3,0x3b,0xd5]
+// CHECK: mrs      x9, {{cntv_cval_el0|CNTV_CVAL_EL0}}          // encoding: [0x49,0xe3,0x3b,0xd5]
+// CHECK: mrs      x9, {{pmevcntr0_el0|PMEVCNTR0_EL0}}          // encoding: [0x09,0xe8,0x3b,0xd5]
+// CHECK: mrs      x9, {{pmevcntr1_el0|PMEVCNTR1_EL0}}          // encoding: [0x29,0xe8,0x3b,0xd5]
+// CHECK: mrs      x9, {{pmevcntr2_el0|PMEVCNTR2_EL0}}          // encoding: [0x49,0xe8,0x3b,0xd5]
+// CHECK: mrs      x9, {{pmevcntr3_el0|PMEVCNTR3_EL0}}          // encoding: [0x69,0xe8,0x3b,0xd5]
+// CHECK: mrs      x9, {{pmevcntr4_el0|PMEVCNTR4_EL0}}          // encoding: [0x89,0xe8,0x3b,0xd5]
+// CHECK: mrs      x9, {{pmevcntr5_el0|PMEVCNTR5_EL0}}          // encoding: [0xa9,0xe8,0x3b,0xd5]
+// CHECK: mrs      x9, {{pmevcntr6_el0|PMEVCNTR6_EL0}}          // encoding: [0xc9,0xe8,0x3b,0xd5]
+// CHECK: mrs      x9, {{pmevcntr7_el0|PMEVCNTR7_EL0}}          // encoding: [0xe9,0xe8,0x3b,0xd5]
+// CHECK: mrs      x9, {{pmevcntr8_el0|PMEVCNTR8_EL0}}          // encoding: [0x09,0xe9,0x3b,0xd5]
+// CHECK: mrs      x9, {{pmevcntr9_el0|PMEVCNTR9_EL0}}          // encoding: [0x29,0xe9,0x3b,0xd5]
+// CHECK: mrs      x9, {{pmevcntr10_el0|PMEVCNTR10_EL0}}         // encoding: [0x49,0xe9,0x3b,0xd5]
+// CHECK: mrs      x9, {{pmevcntr11_el0|PMEVCNTR11_EL0}}         // encoding: [0x69,0xe9,0x3b,0xd5]
+// CHECK: mrs      x9, {{pmevcntr12_el0|PMEVCNTR12_EL0}}         // encoding: [0x89,0xe9,0x3b,0xd5]
+// CHECK: mrs      x9, {{pmevcntr13_el0|PMEVCNTR13_EL0}}         // encoding: [0xa9,0xe9,0x3b,0xd5]
+// CHECK: mrs      x9, {{pmevcntr14_el0|PMEVCNTR14_EL0}}         // encoding: [0xc9,0xe9,0x3b,0xd5]
+// CHECK: mrs      x9, {{pmevcntr15_el0|PMEVCNTR15_EL0}}         // encoding: [0xe9,0xe9,0x3b,0xd5]
+// CHECK: mrs      x9, {{pmevcntr16_el0|PMEVCNTR16_EL0}}         // encoding: [0x09,0xea,0x3b,0xd5]
+// CHECK: mrs      x9, {{pmevcntr17_el0|PMEVCNTR17_EL0}}         // encoding: [0x29,0xea,0x3b,0xd5]
+// CHECK: mrs      x9, {{pmevcntr18_el0|PMEVCNTR18_EL0}}         // encoding: [0x49,0xea,0x3b,0xd5]
+// CHECK: mrs      x9, {{pmevcntr19_el0|PMEVCNTR19_EL0}}         // encoding: [0x69,0xea,0x3b,0xd5]
+// CHECK: mrs      x9, {{pmevcntr20_el0|PMEVCNTR20_EL0}}         // encoding: [0x89,0xea,0x3b,0xd5]
+// CHECK: mrs      x9, {{pmevcntr21_el0|PMEVCNTR21_EL0}}         // encoding: [0xa9,0xea,0x3b,0xd5]
+// CHECK: mrs      x9, {{pmevcntr22_el0|PMEVCNTR22_EL0}}         // encoding: [0xc9,0xea,0x3b,0xd5]
+// CHECK: mrs      x9, {{pmevcntr23_el0|PMEVCNTR23_EL0}}         // encoding: [0xe9,0xea,0x3b,0xd5]
+// CHECK: mrs      x9, {{pmevcntr24_el0|PMEVCNTR24_EL0}}         // encoding: [0x09,0xeb,0x3b,0xd5]
+// CHECK: mrs      x9, {{pmevcntr25_el0|PMEVCNTR25_EL0}}         // encoding: [0x29,0xeb,0x3b,0xd5]
+// CHECK: mrs      x9, {{pmevcntr26_el0|PMEVCNTR26_EL0}}         // encoding: [0x49,0xeb,0x3b,0xd5]
+// CHECK: mrs      x9, {{pmevcntr27_el0|PMEVCNTR27_EL0}}         // encoding: [0x69,0xeb,0x3b,0xd5]
+// CHECK: mrs      x9, {{pmevcntr28_el0|PMEVCNTR28_EL0}}         // encoding: [0x89,0xeb,0x3b,0xd5]
+// CHECK: mrs      x9, {{pmevcntr29_el0|PMEVCNTR29_EL0}}         // encoding: [0xa9,0xeb,0x3b,0xd5]
+// CHECK: mrs      x9, {{pmevcntr30_el0|PMEVCNTR30_EL0}}         // encoding: [0xc9,0xeb,0x3b,0xd5]
+// CHECK: mrs      x9, {{pmccfiltr_el0|PMCCFILTR_EL0}}          // encoding: [0xe9,0xef,0x3b,0xd5]
+// CHECK: mrs      x9, {{pmevtyper0_el0|PMEVTYPER0_EL0}}         // encoding: [0x09,0xec,0x3b,0xd5]
+// CHECK: mrs      x9, {{pmevtyper1_el0|PMEVTYPER1_EL0}}         // encoding: [0x29,0xec,0x3b,0xd5]
+// CHECK: mrs      x9, {{pmevtyper2_el0|PMEVTYPER2_EL0}}         // encoding: [0x49,0xec,0x3b,0xd5]
+// CHECK: mrs      x9, {{pmevtyper3_el0|PMEVTYPER3_EL0}}         // encoding: [0x69,0xec,0x3b,0xd5]
+// CHECK: mrs      x9, {{pmevtyper4_el0|PMEVTYPER4_EL0}}         // encoding: [0x89,0xec,0x3b,0xd5]
+// CHECK: mrs      x9, {{pmevtyper5_el0|PMEVTYPER5_EL0}}         // encoding: [0xa9,0xec,0x3b,0xd5]
+// CHECK: mrs      x9, {{pmevtyper6_el0|PMEVTYPER6_EL0}}         // encoding: [0xc9,0xec,0x3b,0xd5]
+// CHECK: mrs      x9, {{pmevtyper7_el0|PMEVTYPER7_EL0}}         // encoding: [0xe9,0xec,0x3b,0xd5]
+// CHECK: mrs      x9, {{pmevtyper8_el0|PMEVTYPER8_EL0}}         // encoding: [0x09,0xed,0x3b,0xd5]
+// CHECK: mrs      x9, {{pmevtyper9_el0|PMEVTYPER9_EL0}}         // encoding: [0x29,0xed,0x3b,0xd5]
+// CHECK: mrs      x9, {{pmevtyper10_el0|PMEVTYPER10_EL0}}        // encoding: [0x49,0xed,0x3b,0xd5]
+// CHECK: mrs      x9, {{pmevtyper11_el0|PMEVTYPER11_EL0}}        // encoding: [0x69,0xed,0x3b,0xd5]
+// CHECK: mrs      x9, {{pmevtyper12_el0|PMEVTYPER12_EL0}}        // encoding: [0x89,0xed,0x3b,0xd5]
+// CHECK: mrs      x9, {{pmevtyper13_el0|PMEVTYPER13_EL0}}        // encoding: [0xa9,0xed,0x3b,0xd5]
+// CHECK: mrs      x9, {{pmevtyper14_el0|PMEVTYPER14_EL0}}        // encoding: [0xc9,0xed,0x3b,0xd5]
+// CHECK: mrs      x9, {{pmevtyper15_el0|PMEVTYPER15_EL0}}        // encoding: [0xe9,0xed,0x3b,0xd5]
+// CHECK: mrs      x9, {{pmevtyper16_el0|PMEVTYPER16_EL0}}        // encoding: [0x09,0xee,0x3b,0xd5]
+// CHECK: mrs      x9, {{pmevtyper17_el0|PMEVTYPER17_EL0}}        // encoding: [0x29,0xee,0x3b,0xd5]
+// CHECK: mrs      x9, {{pmevtyper18_el0|PMEVTYPER18_EL0}}        // encoding: [0x49,0xee,0x3b,0xd5]
+// CHECK: mrs      x9, {{pmevtyper19_el0|PMEVTYPER19_EL0}}        // encoding: [0x69,0xee,0x3b,0xd5]
+// CHECK: mrs      x9, {{pmevtyper20_el0|PMEVTYPER20_EL0}}        // encoding: [0x89,0xee,0x3b,0xd5]
+// CHECK: mrs      x9, {{pmevtyper21_el0|PMEVTYPER21_EL0}}        // encoding: [0xa9,0xee,0x3b,0xd5]
+// CHECK: mrs      x9, {{pmevtyper22_el0|PMEVTYPER22_EL0}}        // encoding: [0xc9,0xee,0x3b,0xd5]
+// CHECK: mrs      x9, {{pmevtyper23_el0|PMEVTYPER23_EL0}}        // encoding: [0xe9,0xee,0x3b,0xd5]
+// CHECK: mrs      x9, {{pmevtyper24_el0|PMEVTYPER24_EL0}}        // encoding: [0x09,0xef,0x3b,0xd5]
+// CHECK: mrs      x9, {{pmevtyper25_el0|PMEVTYPER25_EL0}}        // encoding: [0x29,0xef,0x3b,0xd5]
+// CHECK: mrs      x9, {{pmevtyper26_el0|PMEVTYPER26_EL0}}        // encoding: [0x49,0xef,0x3b,0xd5]
+// CHECK: mrs      x9, {{pmevtyper27_el0|PMEVTYPER27_EL0}}        // encoding: [0x69,0xef,0x3b,0xd5]
+// CHECK: mrs      x9, {{pmevtyper28_el0|PMEVTYPER28_EL0}}        // encoding: [0x89,0xef,0x3b,0xd5]
+// CHECK: mrs      x9, {{pmevtyper29_el0|PMEVTYPER29_EL0}}        // encoding: [0xa9,0xef,0x3b,0xd5]
+// CHECK: mrs      x9, {{pmevtyper30_el0|PMEVTYPER30_EL0}}        // encoding: [0xc9,0xef,0x3b,0xd5]
 
         mrs x12, s3_7_c15_c1_5
         mrs x13, s3_2_c11_c15_7
         msr s3_0_c15_c0_0, x12
         msr s3_7_c11_c13_7, x5
-// CHECK: mrs     x12, s3_7_c15_c1_5      // encoding: [0xac,0xf1,0x3f,0xd5]
-// CHECK: mrs     x13, s3_2_c11_c15_7     // encoding: [0xed,0xbf,0x3a,0xd5]
-// CHECK: msr     s3_0_c15_c0_0, x12      // encoding: [0x0c,0xf0,0x18,0xd5]
-// CHECK: msr     s3_7_c11_c13_7, x5      // encoding: [0xe5,0xbd,0x1f,0xd5]
+// CHECK: mrs     x12, {{s3_7_c15_c1_5|S3_7_C15_C1_5}}      // encoding: [0xac,0xf1,0x3f,0xd5]
+// CHECK: mrs     x13, {{s3_2_c11_c15_7|S3_2_C11_C15_7}}     // encoding: [0xed,0xbf,0x3a,0xd5]
+// CHECK: msr     {{s3_0_c15_c0_0|S3_0_C15_C0_0}}, x12      // encoding: [0x0c,0xf0,0x18,0xd5]
+// CHECK: msr     {{s3_7_c11_c13_7|S3_7_C11_C13_7}}, x5      // encoding: [0xe5,0xbd,0x1f,0xd5]
 
 //------------------------------------------------------------------------------
 // Unconditional branch (immediate)
@@ -4814,22 +4998,37 @@ _func:
         tbz x5, #0, somewhere
         tbz xzr, #63, elsewhere
         tbnz x5, #45, nowhere
-// CHECK: tbz     x5, #0, somewhere       // encoding: [0x05'A',A,A,0x36'A']
-// CHECK:                                 //   fixup A - offset: 0, value: somewhere, kind: fixup_a64_tstbr
-// CHECK: tbz     xzr, #63, elsewhere     // encoding: [0x1f'A',A,0xf8'A',0xb6'A']
-// CHECK:                                 //   fixup A - offset: 0, value: elsewhere, kind: fixup_a64_tstbr
-// CHECK: tbnz    x5, #45, nowhere        // encoding: [0x05'A',A,0x68'A',0xb7'A']
-// CHECK:                                 //   fixup A - offset: 0, value: nowhere, kind: fixup_a64_tstbr
+// CHECK-AARCH64: tbz     x5, #0, somewhere       // encoding: [0x05'A',A,A,0x36'A']
+// CHECK-AARCH64:                                 //   fixup A - offset: 0, value: somewhere, kind: fixup_a64_tstbr
+// CHECK-AARCH64: tbz     xzr, #63, elsewhere     // encoding: [0x1f'A',A,0xf8'A',0xb6'A']
+// CHECK-AARCH64:                                 //   fixup A - offset: 0, value: elsewhere, kind: fixup_a64_tstbr
+// CHECK-AARCH64: tbnz    x5, #45, nowhere        // encoding: [0x05'A',A,0x68'A',0xb7'A']
+// CHECK-AARCH64:                                 //   fixup A - offset: 0, value: nowhere, kind: fixup_a64_tstbr
+
+// CHECK-ARM64: tbz    w5, #0, somewhere       // encoding: [0bAAA00101,A,0b00000AAA,0x36]
+// CHECK-ARM64:                                //   fixup A - offset: 0, value: somewhere, kind: fixup_arm64_pcrel_branch14
+// CHECK-ARM64: tbz    xzr, #63, elsewhere     // encoding: [0bAAA11111,A,0b11111AAA,0xb6]
+// CHECK-ARM64:                                //   fixup A - offset: 0, value: elsewhere, kind: fixup_arm64_pcrel_branch14
+// CHECK-ARM64: tbnz   x5, #45, nowhere        // encoding: [0bAAA00101,A,0b01101AAA,0xb7]
+// CHECK-ARM64:                                //   fixup A - offset: 0, value: nowhere, kind: fixup_arm64_pcrel_branch14
+
 
         tbnz w3, #2, there
         tbnz wzr, #31, nowhere
         tbz w5, #12, anywhere
-// CHECK: tbnz    w3, #2, there           // encoding: [0x03'A',A,0x10'A',0x37'A']
-// CHECK:                                 //   fixup A - offset: 0, value: there, kind: fixup_a64_tstbr
-// CHECK: tbnz    wzr, #31, nowhere       // encoding: [0x1f'A',A,0xf8'A',0x37'A']
-// CHECK:                                 //   fixup A - offset: 0, value: nowhere, kind: fixup_a64_tstbr
-// CHECK: tbz     w5, #12, anywhere       // encoding: [0x05'A',A,0x60'A',0x36'A']
-// CHECK:                                 //   fixup A - offset: 0, value: anywhere, kind: fixup_a64_tstbr
+// CHECK-AARCH64: tbnz    w3, #2, there           // encoding: [0x03'A',A,0x10'A',0x37'A']
+// CHECK-AARCH64:                                 //   fixup A - offset: 0, value: there, kind: fixup_a64_tstbr
+// CHECK-AARCH64: tbnz    wzr, #31, nowhere       // encoding: [0x1f'A',A,0xf8'A',0x37'A']
+// CHECK-AARCH64:                                 //   fixup A - offset: 0, value: nowhere, kind: fixup_a64_tstbr
+// CHECK-AARCH64: tbz     w5, #12, anywhere       // encoding: [0x05'A',A,0x60'A',0x36'A']
+// CHECK-AARCH64:                                 //   fixup A - offset: 0, value: anywhere, kind: fixup_a64_tstbr
+
+// CHECK-ARM64: tbnz    w3, #2, there           // encoding: [0bAAA00011,A,0b00010AAA,0x37]
+// CHECK-ARM64:                                 //   fixup A - offset: 0, value: there, kind: fixup_arm64_pcrel_branch14
+// CHECK-ARM64: tbnz    wzr, #31, nowhere       // encoding: [0bAAA11111,A,0b11111AAA,0x37]
+// CHECK-ARM64:                                 //   fixup A - offset: 0, value: nowhere, kind: fixup_arm64_pcrel_branch14
+// CHECK-ARM64: tbz     w5, #12, anywhere       // encoding: [0bAAA00101,A,0b01100AAA,0x36]
+// CHECK-ARM64:                                 //   fixup A - offset: 0, value: anywhere, kind: fixup_arm64_pcrel_branch14
 
 //------------------------------------------------------------------------------
 // Unconditional branch (immediate)
@@ -4837,10 +5036,15 @@ _func:
 
         b somewhere
         bl elsewhere
-// CHECK: b       somewhere               // encoding: [A,A,A,0x14'A']
-// CHECK:                                 //   fixup A - offset: 0, value: somewhere, kind: fixup_a64_uncondbr
-// CHECK: bl      elsewhere               // encoding: [A,A,A,0x94'A']
-// CHECK:                                 //   fixup A - offset: 0, value: elsewhere, kind: fixup_a64_call
+// CHECK-AARCH64: b       somewhere               // encoding: [A,A,A,0x14'A']
+// CHECK-AARCH64:                                 //   fixup A - offset: 0, value: somewhere, kind: fixup_a64_uncondbr
+// CHECK-AARCH64: bl      elsewhere               // encoding: [A,A,A,0x94'A']
+// CHECK-AARCH64:                                 //   fixup A - offset: 0, value: elsewhere, kind: fixup_a64_call
+
+// CHECK-ARM64: b    somewhere               // encoding: [A,A,A,0b000101AA]
+// CHECK-ARM64:                              //   fixup A - offset: 0, value: somewhere, kind: fixup_arm64_pcrel_branch26
+// CHECK-ARM64: bl    elsewhere               // encoding: [A,A,A,0b100101AA]
+// CHECK-ARM64:                               //   fixup A - offset: 0, value: elsewhere, kind: fixup_arm64_pcrel_call26
 
         b #4
         bl #0
diff --git a/test/MC/AArch64/gicv3-regs-diagnostics.s b/test/MC/AArch64/gicv3-regs-diagnostics.s
index bc005b1d53..c884312354 100644
--- a/test/MC/AArch64/gicv3-regs-diagnostics.s
+++ b/test/MC/AArch64/gicv3-regs-diagnostics.s
@@ -1,4 +1,5 @@
 // RUN: not llvm-mc -triple aarch64-none-linux-gnu < %s 2>&1 | FileCheck %s
+// RUN: not llvm-mc -triple arm64-none-linux-gnu < %s 2>&1 | FileCheck %s
 
         // Write-only
         mrs x10, icc_eoir1_el1
diff --git a/test/MC/AArch64/gicv3-regs.s b/test/MC/AArch64/gicv3-regs.s
index f7776514da..470fc4667f 100644
--- a/test/MC/AArch64/gicv3-regs.s
+++ b/test/MC/AArch64/gicv3-regs.s
@@ -1,4 +1,5 @@
  // RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding < %s | FileCheck %s
+ // RUN: llvm-mc -triple arm64-none-linux-gnu -show-encoding < %s | FileCheck %s
 
         mrs x8, icc_iar1_el1
         mrs x26, icc_iar0_el1
@@ -56,62 +57,62 @@
         mrs x8, ich_lr13_el2
         mrs x2, ich_lr14_el2
         mrs x8, ich_lr15_el2
-// CHECK: mrs      x8, icc_iar1_el1           // encoding: [0x08,0xcc,0x38,0xd5]
-// CHECK: mrs      x26, icc_iar0_el1          // encoding: [0x1a,0xc8,0x38,0xd5]
-// CHECK: mrs      x2, icc_hppir1_el1         // encoding: [0x42,0xcc,0x38,0xd5]
-// CHECK: mrs      x17, icc_hppir0_el1        // encoding: [0x51,0xc8,0x38,0xd5]
-// CHECK: mrs      x29, icc_rpr_el1           // encoding: [0x7d,0xcb,0x38,0xd5]
-// CHECK: mrs      x4, ich_vtr_el2            // encoding: [0x24,0xcb,0x3c,0xd5]
-// CHECK: mrs      x24, ich_eisr_el2          // encoding: [0x78,0xcb,0x3c,0xd5]
-// CHECK: mrs      x9, ich_elsr_el2           // encoding: [0xa9,0xcb,0x3c,0xd5]
-// CHECK: mrs      x24, icc_bpr1_el1          // encoding: [0x78,0xcc,0x38,0xd5]
-// CHECK: mrs      x14, icc_bpr0_el1          // encoding: [0x6e,0xc8,0x38,0xd5]
-// CHECK: mrs      x19, icc_pmr_el1           // encoding: [0x13,0x46,0x38,0xd5]
-// CHECK: mrs      x23, icc_ctlr_el1          // encoding: [0x97,0xcc,0x38,0xd5]
-// CHECK: mrs      x20, icc_ctlr_el3          // encoding: [0x94,0xcc,0x3e,0xd5]
-// CHECK: mrs      x28, icc_sre_el1           // encoding: [0xbc,0xcc,0x38,0xd5]
-// CHECK: mrs      x25, icc_sre_el2           // encoding: [0xb9,0xc9,0x3c,0xd5]
-// CHECK: mrs      x8, icc_sre_el3            // encoding: [0xa8,0xcc,0x3e,0xd5]
-// CHECK: mrs      x22, icc_igrpen0_el1       // encoding: [0xd6,0xcc,0x38,0xd5]
-// CHECK: mrs      x5, icc_igrpen1_el1        // encoding: [0xe5,0xcc,0x38,0xd5]
-// CHECK: mrs      x7, icc_igrpen1_el3        // encoding: [0xe7,0xcc,0x3e,0xd5]
-// CHECK: mrs      x22, icc_seien_el1         // encoding: [0x16,0xcd,0x38,0xd5]
-// CHECK: mrs      x4, icc_ap0r0_el1          // encoding: [0x84,0xc8,0x38,0xd5]
-// CHECK: mrs      x11, icc_ap0r1_el1         // encoding: [0xab,0xc8,0x38,0xd5]
-// CHECK: mrs      x27, icc_ap0r2_el1         // encoding: [0xdb,0xc8,0x38,0xd5]
-// CHECK: mrs      x21, icc_ap0r3_el1         // encoding: [0xf5,0xc8,0x38,0xd5]
-// CHECK: mrs      x2, icc_ap1r0_el1          // encoding: [0x02,0xc9,0x38,0xd5]
-// CHECK: mrs      x21, icc_ap1r1_el1         // encoding: [0x35,0xc9,0x38,0xd5]
-// CHECK: mrs      x10, icc_ap1r2_el1         // encoding: [0x4a,0xc9,0x38,0xd5]
-// CHECK: mrs      x27, icc_ap1r3_el1         // encoding: [0x7b,0xc9,0x38,0xd5]
-// CHECK: mrs      x20, ich_ap0r0_el2         // encoding: [0x14,0xc8,0x3c,0xd5]
-// CHECK: mrs      x21, ich_ap0r1_el2         // encoding: [0x35,0xc8,0x3c,0xd5]
-// CHECK: mrs      x5, ich_ap0r2_el2          // encoding: [0x45,0xc8,0x3c,0xd5]
-// CHECK: mrs      x4, ich_ap0r3_el2          // encoding: [0x64,0xc8,0x3c,0xd5]
-// CHECK: mrs      x15, ich_ap1r0_el2         // encoding: [0x0f,0xc9,0x3c,0xd5]
-// CHECK: mrs      x12, ich_ap1r1_el2         // encoding: [0x2c,0xc9,0x3c,0xd5]
-// CHECK: mrs      x27, ich_ap1r2_el2         // encoding: [0x5b,0xc9,0x3c,0xd5]
-// CHECK: mrs      x20, ich_ap1r3_el2         // encoding: [0x74,0xc9,0x3c,0xd5]
-// CHECK: mrs      x10, ich_hcr_el2           // encoding: [0x0a,0xcb,0x3c,0xd5]
-// CHECK: mrs      x27, ich_misr_el2          // encoding: [0x5b,0xcb,0x3c,0xd5]
-// CHECK: mrs      x6, ich_vmcr_el2           // encoding: [0xe6,0xcb,0x3c,0xd5]
-// CHECK: mrs      x19, ich_vseir_el2         // encoding: [0x93,0xc9,0x3c,0xd5]
-// CHECK: mrs      x3, ich_lr0_el2            // encoding: [0x03,0xcc,0x3c,0xd5]
-// CHECK: mrs      x1, ich_lr1_el2            // encoding: [0x21,0xcc,0x3c,0xd5]
-// CHECK: mrs      x22, ich_lr2_el2           // encoding: [0x56,0xcc,0x3c,0xd5]
-// CHECK: mrs      x21, ich_lr3_el2           // encoding: [0x75,0xcc,0x3c,0xd5]
-// CHECK: mrs      x6, ich_lr4_el2            // encoding: [0x86,0xcc,0x3c,0xd5]
-// CHECK: mrs      x10, ich_lr5_el2           // encoding: [0xaa,0xcc,0x3c,0xd5]
-// CHECK: mrs      x11, ich_lr6_el2           // encoding: [0xcb,0xcc,0x3c,0xd5]
-// CHECK: mrs      x12, ich_lr7_el2           // encoding: [0xec,0xcc,0x3c,0xd5]
-// CHECK: mrs      x0, ich_lr8_el2            // encoding: [0x00,0xcd,0x3c,0xd5]
-// CHECK: mrs      x21, ich_lr9_el2           // encoding: [0x35,0xcd,0x3c,0xd5]
-// CHECK: mrs      x13, ich_lr10_el2          // encoding: [0x4d,0xcd,0x3c,0xd5]
-// CHECK: mrs      x26, ich_lr11_el2          // encoding: [0x7a,0xcd,0x3c,0xd5]
-// CHECK: mrs      x1, ich_lr12_el2           // encoding: [0x81,0xcd,0x3c,0xd5]
-// CHECK: mrs      x8, ich_lr13_el2           // encoding: [0xa8,0xcd,0x3c,0xd5]
-// CHECK: mrs      x2, ich_lr14_el2           // encoding: [0xc2,0xcd,0x3c,0xd5]
-// CHECK: mrs      x8, ich_lr15_el2           // encoding: [0xe8,0xcd,0x3c,0xd5]
+// CHECK: mrs      x8, {{icc_iar1_el1|ICC_IAR1_EL1}}           // encoding: [0x08,0xcc,0x38,0xd5]
+// CHECK: mrs      x26, {{icc_iar0_el1|ICC_IAR0_EL1}}          // encoding: [0x1a,0xc8,0x38,0xd5]
+// CHECK: mrs      x2, {{icc_hppir1_el1|ICC_HPPIR1_EL1}}         // encoding: [0x42,0xcc,0x38,0xd5]
+// CHECK: mrs      x17, {{icc_hppir0_el1|ICC_HPPIR0_EL1}}        // encoding: [0x51,0xc8,0x38,0xd5]
+// CHECK: mrs      x29, {{icc_rpr_el1|ICC_RPR_EL1}}           // encoding: [0x7d,0xcb,0x38,0xd5]
+// CHECK: mrs      x4, {{ich_vtr_el2|ICH_VTR_EL2}}            // encoding: [0x24,0xcb,0x3c,0xd5]
+// CHECK: mrs      x24, {{ich_eisr_el2|ICH_EISR_EL2}}          // encoding: [0x78,0xcb,0x3c,0xd5]
+// CHECK: mrs      x9, {{ich_elsr_el2|ICH_ELSR_EL2}}           // encoding: [0xa9,0xcb,0x3c,0xd5]
+// CHECK: mrs      x24, {{icc_bpr1_el1|ICC_BPR1_EL1}}          // encoding: [0x78,0xcc,0x38,0xd5]
+// CHECK: mrs      x14, {{icc_bpr0_el1|ICC_BPR0_EL1}}          // encoding: [0x6e,0xc8,0x38,0xd5]
+// CHECK: mrs      x19, {{icc_pmr_el1|ICC_PMR_EL1}}           // encoding: [0x13,0x46,0x38,0xd5]
+// CHECK: mrs      x23, {{icc_ctlr_el1|ICC_CTLR_EL1}}          // encoding: [0x97,0xcc,0x38,0xd5]
+// CHECK: mrs      x20, {{icc_ctlr_el3|ICC_CTLR_EL3}}          // encoding: [0x94,0xcc,0x3e,0xd5]
+// CHECK: mrs      x28, {{icc_sre_el1|ICC_SRE_EL1}}           // encoding: [0xbc,0xcc,0x38,0xd5]
+// CHECK: mrs      x25, {{icc_sre_el2|ICC_SRE_EL2}}           // encoding: [0xb9,0xc9,0x3c,0xd5]
+// CHECK: mrs      x8, {{icc_sre_el3|ICC_SRE_EL3}}            // encoding: [0xa8,0xcc,0x3e,0xd5]
+// CHECK: mrs      x22, {{icc_igrpen0_el1|ICC_IGRPEN0_EL1}}       // encoding: [0xd6,0xcc,0x38,0xd5]
+// CHECK: mrs      x5, {{icc_igrpen1_el1|ICC_IGRPEN1_EL1}}        // encoding: [0xe5,0xcc,0x38,0xd5]
+// CHECK: mrs      x7, {{icc_igrpen1_el3|ICC_IGRPEN1_EL3}}        // encoding: [0xe7,0xcc,0x3e,0xd5]
+// CHECK: mrs      x22, {{icc_seien_el1|ICC_SEIEN_EL1}}         // encoding: [0x16,0xcd,0x38,0xd5]
+// CHECK: mrs      x4, {{icc_ap0r0_el1|ICC_AP0R0_EL1}}          // encoding: [0x84,0xc8,0x38,0xd5]
+// CHECK: mrs      x11, {{icc_ap0r1_el1|ICC_AP0R1_EL1}}         // encoding: [0xab,0xc8,0x38,0xd5]
+// CHECK: mrs      x27, {{icc_ap0r2_el1|ICC_AP0R2_EL1}}         // encoding: [0xdb,0xc8,0x38,0xd5]
+// CHECK: mrs      x21, {{icc_ap0r3_el1|ICC_AP0R3_EL1}}         // encoding: [0xf5,0xc8,0x38,0xd5]
+// CHECK: mrs      x2, {{icc_ap1r0_el1|ICC_AP1R0_EL1}}          // encoding: [0x02,0xc9,0x38,0xd5]
+// CHECK: mrs      x21, {{icc_ap1r1_el1|ICC_AP1R1_EL1}}         // encoding: [0x35,0xc9,0x38,0xd5]
+// CHECK: mrs      x10, {{icc_ap1r2_el1|ICC_AP1R2_EL1}}         // encoding: [0x4a,0xc9,0x38,0xd5]
+// CHECK: mrs      x27, {{icc_ap1r3_el1|ICC_AP1R3_EL1}}         // encoding: [0x7b,0xc9,0x38,0xd5]
+// CHECK: mrs      x20, {{ich_ap0r0_el2|ICH_AP0R0_EL2}}         // encoding: [0x14,0xc8,0x3c,0xd5]
+// CHECK: mrs      x21, {{ich_ap0r1_el2|ICH_AP0R1_EL2}}         // encoding: [0x35,0xc8,0x3c,0xd5]
+// CHECK: mrs      x5, {{ich_ap0r2_el2|ICH_AP0R2_EL2}}          // encoding: [0x45,0xc8,0x3c,0xd5]
+// CHECK: mrs      x4, {{ich_ap0r3_el2|ICH_AP0R3_EL2}}          // encoding: [0x64,0xc8,0x3c,0xd5]
+// CHECK: mrs      x15, {{ich_ap1r0_el2|ICH_AP1R0_EL2}}         // encoding: [0x0f,0xc9,0x3c,0xd5]
+// CHECK: mrs      x12, {{ich_ap1r1_el2|ICH_AP1R1_EL2}}         // encoding: [0x2c,0xc9,0x3c,0xd5]
+// CHECK: mrs      x27, {{ich_ap1r2_el2|ICH_AP1R2_EL2}}         // encoding: [0x5b,0xc9,0x3c,0xd5]
+// CHECK: mrs      x20, {{ich_ap1r3_el2|ICH_AP1R3_EL2}}         // encoding: [0x74,0xc9,0x3c,0xd5]
+// CHECK: mrs      x10, {{ich_hcr_el2|ICH_HCR_EL2}}           // encoding: [0x0a,0xcb,0x3c,0xd5]
+// CHECK: mrs      x27, {{ich_misr_el2|ICH_MISR_EL2}}          // encoding: [0x5b,0xcb,0x3c,0xd5]
+// CHECK: mrs      x6, {{ich_vmcr_el2|ICH_VMCR_EL2}}           // encoding: [0xe6,0xcb,0x3c,0xd5]
+// CHECK: mrs      x19, {{ich_vseir_el2|ICH_VSEIR_EL2}}         // encoding: [0x93,0xc9,0x3c,0xd5]
+// CHECK: mrs      x3, {{ich_lr0_el2|ICH_LR0_EL2}}            // encoding: [0x03,0xcc,0x3c,0xd5]
+// CHECK: mrs      x1, {{ich_lr1_el2|ICH_LR1_EL2}}            // encoding: [0x21,0xcc,0x3c,0xd5]
+// CHECK: mrs      x22, {{ich_lr2_el2|ICH_LR2_EL2}}           // encoding: [0x56,0xcc,0x3c,0xd5]
+// CHECK: mrs      x21, {{ich_lr3_el2|ICH_LR3_EL2}}           // encoding: [0x75,0xcc,0x3c,0xd5]
+// CHECK: mrs      x6, {{ich_lr4_el2|ICH_LR4_EL2}}            // encoding: [0x86,0xcc,0x3c,0xd5]
+// CHECK: mrs      x10, {{ich_lr5_el2|ICH_LR5_EL2}}           // encoding: [0xaa,0xcc,0x3c,0xd5]
+// CHECK: mrs      x11, {{ich_lr6_el2|ICH_LR6_EL2}}           // encoding: [0xcb,0xcc,0x3c,0xd5]
+// CHECK: mrs      x12, {{ich_lr7_el2|ICH_LR7_EL2}}           // encoding: [0xec,0xcc,0x3c,0xd5]
+// CHECK: mrs      x0, {{ich_lr8_el2|ICH_LR8_EL2}}            // encoding: [0x00,0xcd,0x3c,0xd5]
+// CHECK: mrs      x21, {{ich_lr9_el2|ICH_LR9_EL2}}           // encoding: [0x35,0xcd,0x3c,0xd5]
+// CHECK: mrs      x13, {{ich_lr10_el2|ICH_LR10_EL2}}          // encoding: [0x4d,0xcd,0x3c,0xd5]
+// CHECK: mrs      x26, {{ich_lr11_el2|ICH_LR11_EL2}}          // encoding: [0x7a,0xcd,0x3c,0xd5]
+// CHECK: mrs      x1, {{ich_lr12_el2|ICH_LR12_EL2}}           // encoding: [0x81,0xcd,0x3c,0xd5]
+// CHECK: mrs      x8, {{ich_lr13_el2|ICH_LR13_EL2}}           // encoding: [0xa8,0xcd,0x3c,0xd5]
+// CHECK: mrs      x2, {{ich_lr14_el2|ICH_LR14_EL2}}           // encoding: [0xc2,0xcd,0x3c,0xd5]
+// CHECK: mrs      x8, {{ich_lr15_el2|ICH_LR15_EL2}}           // encoding: [0xe8,0xcd,0x3c,0xd5]
 
         msr icc_eoir1_el1, x27
         msr icc_eoir0_el1, x5
@@ -167,57 +168,57 @@
         msr ich_lr13_el2, x2
         msr ich_lr14_el2, x13
         msr ich_lr15_el2, x27
-// CHECK: msr      icc_eoir1_el1, x27         // encoding: [0x3b,0xcc,0x18,0xd5]
-// CHECK: msr      icc_eoir0_el1, x5          // encoding: [0x25,0xc8,0x18,0xd5]
-// CHECK: msr      icc_dir_el1, x13           // encoding: [0x2d,0xcb,0x18,0xd5]
-// CHECK: msr      icc_sgi1r_el1, x21         // encoding: [0xb5,0xcb,0x18,0xd5]
-// CHECK: msr      icc_asgi1r_el1, x25        // encoding: [0xd9,0xcb,0x18,0xd5]
-// CHECK: msr      icc_sgi0r_el1, x28         // encoding: [0xfc,0xcb,0x18,0xd5]
-// CHECK: msr      icc_bpr1_el1, x7           // encoding: [0x67,0xcc,0x18,0xd5]
-// CHECK: msr      icc_bpr0_el1, x9           // encoding: [0x69,0xc8,0x18,0xd5]
-// CHECK: msr      icc_pmr_el1, x29           // encoding: [0x1d,0x46,0x18,0xd5]
-// CHECK: msr      icc_ctlr_el1, x24          // encoding: [0x98,0xcc,0x18,0xd5]
-// CHECK: msr      icc_ctlr_el3, x0           // encoding: [0x80,0xcc,0x1e,0xd5]
-// CHECK: msr      icc_sre_el1, x2            // encoding: [0xa2,0xcc,0x18,0xd5]
-// CHECK: msr      icc_sre_el2, x5            // encoding: [0xa5,0xc9,0x1c,0xd5]
-// CHECK: msr      icc_sre_el3, x10           // encoding: [0xaa,0xcc,0x1e,0xd5]
-// CHECK: msr      icc_igrpen0_el1, x22       // encoding: [0xd6,0xcc,0x18,0xd5]
-// CHECK: msr      icc_igrpen1_el1, x11       // encoding: [0xeb,0xcc,0x18,0xd5]
-// CHECK: msr      icc_igrpen1_el3, x8        // encoding: [0xe8,0xcc,0x1e,0xd5]
-// CHECK: msr      icc_seien_el1, x4          // encoding: [0x04,0xcd,0x18,0xd5]
-// CHECK: msr      icc_ap0r0_el1, x27         // encoding: [0x9b,0xc8,0x18,0xd5]
-// CHECK: msr      icc_ap0r1_el1, x5          // encoding: [0xa5,0xc8,0x18,0xd5]
-// CHECK: msr      icc_ap0r2_el1, x20         // encoding: [0xd4,0xc8,0x18,0xd5]
-// CHECK: msr      icc_ap0r3_el1, x0          // encoding: [0xe0,0xc8,0x18,0xd5]
-// CHECK: msr      icc_ap1r0_el1, x2          // encoding: [0x02,0xc9,0x18,0xd5]
-// CHECK: msr      icc_ap1r1_el1, x29         // encoding: [0x3d,0xc9,0x18,0xd5]
-// CHECK: msr      icc_ap1r2_el1, x23         // encoding: [0x57,0xc9,0x18,0xd5]
-// CHECK: msr      icc_ap1r3_el1, x11         // encoding: [0x6b,0xc9,0x18,0xd5]
-// CHECK: msr      ich_ap0r0_el2, x2          // encoding: [0x02,0xc8,0x1c,0xd5]
-// CHECK: msr      ich_ap0r1_el2, x27         // encoding: [0x3b,0xc8,0x1c,0xd5]
-// CHECK: msr      ich_ap0r2_el2, x7          // encoding: [0x47,0xc8,0x1c,0xd5]
-// CHECK: msr      ich_ap0r3_el2, x1          // encoding: [0x61,0xc8,0x1c,0xd5]
-// CHECK: msr      ich_ap1r0_el2, x7          // encoding: [0x07,0xc9,0x1c,0xd5]
-// CHECK: msr      ich_ap1r1_el2, x12         // encoding: [0x2c,0xc9,0x1c,0xd5]
-// CHECK: msr      ich_ap1r2_el2, x14         // encoding: [0x4e,0xc9,0x1c,0xd5]
-// CHECK: msr      ich_ap1r3_el2, x13         // encoding: [0x6d,0xc9,0x1c,0xd5]
-// CHECK: msr      ich_hcr_el2, x1            // encoding: [0x01,0xcb,0x1c,0xd5]
-// CHECK: msr      ich_misr_el2, x10          // encoding: [0x4a,0xcb,0x1c,0xd5]
-// CHECK: msr      ich_vmcr_el2, x24          // encoding: [0xf8,0xcb,0x1c,0xd5]
-// CHECK: msr      ich_vseir_el2, x29         // encoding: [0x9d,0xc9,0x1c,0xd5]
-// CHECK: msr      ich_lr0_el2, x26           // encoding: [0x1a,0xcc,0x1c,0xd5]
-// CHECK: msr      ich_lr1_el2, x9            // encoding: [0x29,0xcc,0x1c,0xd5]
-// CHECK: msr      ich_lr2_el2, x18           // encoding: [0x52,0xcc,0x1c,0xd5]
-// CHECK: msr      ich_lr3_el2, x26           // encoding: [0x7a,0xcc,0x1c,0xd5]
-// CHECK: msr      ich_lr4_el2, x22           // encoding: [0x96,0xcc,0x1c,0xd5]
-// CHECK: msr      ich_lr5_el2, x26           // encoding: [0xba,0xcc,0x1c,0xd5]
-// CHECK: msr      ich_lr6_el2, x27           // encoding: [0xdb,0xcc,0x1c,0xd5]
-// CHECK: msr      ich_lr7_el2, x8            // encoding: [0xe8,0xcc,0x1c,0xd5]
-// CHECK: msr      ich_lr8_el2, x17           // encoding: [0x11,0xcd,0x1c,0xd5]
-// CHECK: msr      ich_lr9_el2, x19           // encoding: [0x33,0xcd,0x1c,0xd5]
-// CHECK: msr      ich_lr10_el2, x17          // encoding: [0x51,0xcd,0x1c,0xd5]
-// CHECK: msr      ich_lr11_el2, x5           // encoding: [0x65,0xcd,0x1c,0xd5]
-// CHECK: msr      ich_lr12_el2, x29          // encoding: [0x9d,0xcd,0x1c,0xd5]
-// CHECK: msr      ich_lr13_el2, x2           // encoding: [0xa2,0xcd,0x1c,0xd5]
-// CHECK: msr      ich_lr14_el2, x13          // encoding: [0xcd,0xcd,0x1c,0xd5]
-// CHECK: msr      ich_lr15_el2, x27          // encoding: [0xfb,0xcd,0x1c,0xd5]
+// CHECK: msr      {{icc_eoir1_el1|ICC_EOIR1_EL1}}, x27         // encoding: [0x3b,0xcc,0x18,0xd5]
+// CHECK: msr      {{icc_eoir0_el1|ICC_EOIR0_EL1}}, x5          // encoding: [0x25,0xc8,0x18,0xd5]
+// CHECK: msr      {{icc_dir_el1|ICC_DIR_EL1}}, x13           // encoding: [0x2d,0xcb,0x18,0xd5]
+// CHECK: msr      {{icc_sgi1r_el1|ICC_SGI1R_EL1}}, x21         // encoding: [0xb5,0xcb,0x18,0xd5]
+// CHECK: msr      {{icc_asgi1r_el1|ICC_ASGI1R_EL1}}, x25        // encoding: [0xd9,0xcb,0x18,0xd5]
+// CHECK: msr      {{icc_sgi0r_el1|ICC_SGI0R_EL1}}, x28         // encoding: [0xfc,0xcb,0x18,0xd5]
+// CHECK: msr      {{icc_bpr1_el1|ICC_BPR1_EL1}}, x7           // encoding: [0x67,0xcc,0x18,0xd5]
+// CHECK: msr      {{icc_bpr0_el1|ICC_BPR0_EL1}}, x9           // encoding: [0x69,0xc8,0x18,0xd5]
+// CHECK: msr      {{icc_pmr_el1|ICC_PMR_EL1}}, x29           // encoding: [0x1d,0x46,0x18,0xd5]
+// CHECK: msr      {{icc_ctlr_el1|ICC_CTLR_EL1}}, x24          // encoding: [0x98,0xcc,0x18,0xd5]
+// CHECK: msr      {{icc_ctlr_el3|ICC_CTLR_EL3}}, x0           // encoding: [0x80,0xcc,0x1e,0xd5]
+// CHECK: msr      {{icc_sre_el1|ICC_SRE_EL1}}, x2            // encoding: [0xa2,0xcc,0x18,0xd5]
+// CHECK: msr      {{icc_sre_el2|ICC_SRE_EL2}}, x5            // encoding: [0xa5,0xc9,0x1c,0xd5]
+// CHECK: msr      {{icc_sre_el3|ICC_SRE_EL3}}, x10           // encoding: [0xaa,0xcc,0x1e,0xd5]
+// CHECK: msr      {{icc_igrpen0_el1|ICC_IGRPEN0_EL1}}, x22       // encoding: [0xd6,0xcc,0x18,0xd5]
+// CHECK: msr      {{icc_igrpen1_el1|ICC_IGRPEN1_EL1}}, x11       // encoding: [0xeb,0xcc,0x18,0xd5]
+// CHECK: msr      {{icc_igrpen1_el3|ICC_IGRPEN1_EL3}}, x8        // encoding: [0xe8,0xcc,0x1e,0xd5]
+// CHECK: msr      {{icc_seien_el1|ICC_SEIEN_EL1}}, x4          // encoding: [0x04,0xcd,0x18,0xd5]
+// CHECK: msr      {{icc_ap0r0_el1|ICC_AP0R0_EL1}}, x27         // encoding: [0x9b,0xc8,0x18,0xd5]
+// CHECK: msr      {{icc_ap0r1_el1|ICC_AP0R1_EL1}}, x5          // encoding: [0xa5,0xc8,0x18,0xd5]
+// CHECK: msr      {{icc_ap0r2_el1|ICC_AP0R2_EL1}}, x20         // encoding: [0xd4,0xc8,0x18,0xd5]
+// CHECK: msr      {{icc_ap0r3_el1|ICC_AP0R3_EL1}}, x0          // encoding: [0xe0,0xc8,0x18,0xd5]
+// CHECK: msr      {{icc_ap1r0_el1|ICC_AP1R0_EL1}}, x2          // encoding: [0x02,0xc9,0x18,0xd5]
+// CHECK: msr      {{icc_ap1r1_el1|ICC_AP1R1_EL1}}, x29         // encoding: [0x3d,0xc9,0x18,0xd5]
+// CHECK: msr      {{icc_ap1r2_el1|ICC_AP1R2_EL1}}, x23         // encoding: [0x57,0xc9,0x18,0xd5]
+// CHECK: msr      {{icc_ap1r3_el1|ICC_AP1R3_EL1}}, x11         // encoding: [0x6b,0xc9,0x18,0xd5]
+// CHECK: msr      {{ich_ap0r0_el2|ICH_AP0R0_EL2}}, x2          // encoding: [0x02,0xc8,0x1c,0xd5]
+// CHECK: msr      {{ich_ap0r1_el2|ICH_AP0R1_EL2}}, x27         // encoding: [0x3b,0xc8,0x1c,0xd5]
+// CHECK: msr      {{ich_ap0r2_el2|ICH_AP0R2_EL2}}, x7          // encoding: [0x47,0xc8,0x1c,0xd5]
+// CHECK: msr      {{ich_ap0r3_el2|ICH_AP0R3_EL2}}, x1          // encoding: [0x61,0xc8,0x1c,0xd5]
+// CHECK: msr      {{ich_ap1r0_el2|ICH_AP1R0_EL2}}, x7          // encoding: [0x07,0xc9,0x1c,0xd5]
+// CHECK: msr      {{ich_ap1r1_el2|ICH_AP1R1_EL2}}, x12         // encoding: [0x2c,0xc9,0x1c,0xd5]
+// CHECK: msr      {{ich_ap1r2_el2|ICH_AP1R2_EL2}}, x14         // encoding: [0x4e,0xc9,0x1c,0xd5]
+// CHECK: msr      {{ich_ap1r3_el2|ICH_AP1R3_EL2}}, x13         // encoding: [0x6d,0xc9,0x1c,0xd5]
+// CHECK: msr      {{ich_hcr_el2|ICH_HCR_EL2}}, x1            // encoding: [0x01,0xcb,0x1c,0xd5]
+// CHECK: msr      {{ich_misr_el2|ICH_MISR_EL2}}, x10          // encoding: [0x4a,0xcb,0x1c,0xd5]
+// CHECK: msr      {{ich_vmcr_el2|ICH_VMCR_EL2}}, x24          // encoding: [0xf8,0xcb,0x1c,0xd5]
+// CHECK: msr      {{ich_vseir_el2|ICH_VSEIR_EL2}}, x29         // encoding: [0x9d,0xc9,0x1c,0xd5]
+// CHECK: msr      {{ich_lr0_el2|ICH_LR0_EL2}}, x26           // encoding: [0x1a,0xcc,0x1c,0xd5]
+// CHECK: msr      {{ich_lr1_el2|ICH_LR1_EL2}}, x9            // encoding: [0x29,0xcc,0x1c,0xd5]
+// CHECK: msr      {{ich_lr2_el2|ICH_LR2_EL2}}, x18           // encoding: [0x52,0xcc,0x1c,0xd5]
+// CHECK: msr      {{ich_lr3_el2|ICH_LR3_EL2}}, x26           // encoding: [0x7a,0xcc,0x1c,0xd5]
+// CHECK: msr      {{ich_lr4_el2|ICH_LR4_EL2}}, x22           // encoding: [0x96,0xcc,0x1c,0xd5]
+// CHECK: msr      {{ich_lr5_el2|ICH_LR5_EL2}}, x26           // encoding: [0xba,0xcc,0x1c,0xd5]
+// CHECK: msr      {{ich_lr6_el2|ICH_LR6_EL2}}, x27           // encoding: [0xdb,0xcc,0x1c,0xd5]
+// CHECK: msr      {{ich_lr7_el2|ICH_LR7_EL2}}, x8            // encoding: [0xe8,0xcc,0x1c,0xd5]
+// CHECK: msr      {{ich_lr8_el2|ICH_LR8_EL2}}, x17           // encoding: [0x11,0xcd,0x1c,0xd5]
+// CHECK: msr      {{ich_lr9_el2|ICH_LR9_EL2}}, x19           // encoding: [0x33,0xcd,0x1c,0xd5]
+// CHECK: msr      {{ich_lr10_el2|ICH_LR10_EL2}}, x17          // encoding: [0x51,0xcd,0x1c,0xd5]
+// CHECK: msr      {{ich_lr11_el2|ICH_LR11_EL2}}, x5           // encoding: [0x65,0xcd,0x1c,0xd5]
+// CHECK: msr      {{ich_lr12_el2|ICH_LR12_EL2}}, x29          // encoding: [0x9d,0xcd,0x1c,0xd5]
+// CHECK: msr      {{ich_lr13_el2|ICH_LR13_EL2}}, x2           // encoding: [0xa2,0xcd,0x1c,0xd5]
+// CHECK: msr      {{ich_lr14_el2|ICH_LR14_EL2}}, x13          // encoding: [0xcd,0xcd,0x1c,0xd5]
+// CHECK: msr      {{ich_lr15_el2|ICH_LR15_EL2}}, x27          // encoding: [0xfb,0xcd,0x1c,0xd5]
diff --git a/test/MC/AArch64/neon-compare-instructions.s b/test/MC/AArch64/neon-compare-instructions.s
index d4e3ef5f19..dfc3ae7151 100644
--- a/test/MC/AArch64/neon-compare-instructions.s
+++ b/test/MC/AArch64/neon-compare-instructions.s
@@ -1,4 +1,5 @@
 // RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s
+// RUN: llvm-mc -triple arm64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s
 
 // Check that the assembler can handle the documented syntax for AArch64
 
@@ -255,13 +256,13 @@
          cmeq v9.4s, v7.4s, #0
          cmeq v3.2d, v31.2d, #0
 
-// CHECK: cmeq v0.8b, v15.8b, #0x0    // encoding: [0xe0,0x99,0x20,0x0e]
-// CHECK: cmeq v1.16b, v31.16b, #0x0  // encoding: [0xe1,0x9b,0x20,0x4e]
-// CHECK: cmeq v15.4h, v16.4h, #0x0   // encoding: [0x0f,0x9a,0x60,0x0e]
-// CHECK: cmeq v5.8h, v6.8h, #0x0     // encoding: [0xc5,0x98,0x60,0x4e]
-// CHECK: cmeq v29.2s, v27.2s, #0x0   // encoding: [0x7d,0x9b,0xa0,0x0e]
-// CHECK: cmeq v9.4s, v7.4s, #0x0     // encoding: [0xe9,0x98,0xa0,0x4e]
-// CHECK: cmeq v3.2d, v31.2d, #0x0    // encoding: [0xe3,0x9b,0xe0,0x4e]
+// CHECK: cmeq v0.8b, v15.8b, #{{0x0|0}}    // encoding: [0xe0,0x99,0x20,0x0e]
+// CHECK: cmeq v1.16b, v31.16b, #{{0x0|0}}  // encoding: [0xe1,0x9b,0x20,0x4e]
+// CHECK: cmeq v15.4h, v16.4h, #{{0x0|0}}   // encoding: [0x0f,0x9a,0x60,0x0e]
+// CHECK: cmeq v5.8h, v6.8h, #{{0x0|0}}     // encoding: [0xc5,0x98,0x60,0x4e]
+// CHECK: cmeq v29.2s, v27.2s, #{{0x0|0}}   // encoding: [0x7d,0x9b,0xa0,0x0e]
+// CHECK: cmeq v9.4s, v7.4s, #{{0x0|0}}     // encoding: [0xe9,0x98,0xa0,0x4e]
+// CHECK: cmeq v3.2d, v31.2d, #{{0x0|0}}    // encoding: [0xe3,0x9b,0xe0,0x4e]
 
 //----------------------------------------------------------------------
 // Vector Compare Mask Greater Than or Equal to Zero (Signed Integer)
@@ -274,13 +275,13 @@
          cmge v17.4s, v20.4s, #0
          cmge v3.2d, v31.2d, #0
 
-// CHECK: cmge v0.8b, v15.8b, #0x0    // encoding: [0xe0,0x89,0x20,0x2e]
-// CHECK: cmge v1.16b, v31.16b, #0x0  // encoding: [0xe1,0x8b,0x20,0x6e]
-// CHECK: cmge v15.4h, v16.4h, #0x0   // encoding: [0x0f,0x8a,0x60,0x2e]
-// CHECK: cmge v5.8h, v6.8h, #0x0     // encoding: [0xc5,0x88,0x60,0x6e]
-// CHECK: cmge v29.2s, v27.2s, #0x0   // encoding: [0x7d,0x8b,0xa0,0x2e]
-// CHECK: cmge v17.4s, v20.4s, #0x0   // encoding: [0x91,0x8a,0xa0,0x6e]
-// CHECK: cmge v3.2d, v31.2d, #0x0    // encoding: [0xe3,0x8b,0xe0,0x6e]
+// CHECK: cmge v0.8b, v15.8b, #{{0x0|0}}    // encoding: [0xe0,0x89,0x20,0x2e]
+// CHECK: cmge v1.16b, v31.16b, #{{0x0|0}}  // encoding: [0xe1,0x8b,0x20,0x6e]
+// CHECK: cmge v15.4h, v16.4h, #{{0x0|0}}   // encoding: [0x0f,0x8a,0x60,0x2e]
+// CHECK: cmge v5.8h, v6.8h, #{{0x0|0}}     // encoding: [0xc5,0x88,0x60,0x6e]
+// CHECK: cmge v29.2s, v27.2s, #{{0x0|0}}   // encoding: [0x7d,0x8b,0xa0,0x2e]
+// CHECK: cmge v17.4s, v20.4s, #{{0x0|0}}   // encoding: [0x91,0x8a,0xa0,0x6e]
+// CHECK: cmge v3.2d, v31.2d, #{{0x0|0}}    // encoding: [0xe3,0x8b,0xe0,0x6e]
 
 //----------------------------------------------------------------------
 // Vector Compare Mask Greater Than Zero (Signed Integer)
@@ -294,13 +295,13 @@
          cmgt v9.4s, v7.4s, #0
          cmgt v3.2d, v31.2d, #0
 
-// CHECK: cmgt v0.8b, v15.8b, #0x0    // encoding: [0xe0,0x89,0x20,0x0e]
-// CHECK: cmgt v1.16b, v31.16b, #0x0  // encoding: [0xe1,0x8b,0x20,0x4e]
-// CHECK: cmgt v15.4h, v16.4h, #0x0   // encoding: [0x0f,0x8a,0x60,0x0e]
-// CHECK: cmgt v5.8h, v6.8h, #0x0     // encoding: [0xc5,0x88,0x60,0x4e]
-// CHECK: cmgt v29.2s, v27.2s, #0x0   // encoding: [0x7d,0x8b,0xa0,0x0e]
-// CHECK: cmgt v9.4s, v7.4s, #0x0     // encoding: [0xe9,0x88,0xa0,0x4e]
-// CHECK: cmgt v3.2d, v31.2d, #0x0    // encoding: [0xe3,0x8b,0xe0,0x4e]
+// CHECK: cmgt v0.8b, v15.8b, #{{0x0|0}}    // encoding: [0xe0,0x89,0x20,0x0e]
+// CHECK: cmgt v1.16b, v31.16b, #{{0x0|0}}  // encoding: [0xe1,0x8b,0x20,0x4e]
+// CHECK: cmgt v15.4h, v16.4h, #{{0x0|0}}   // encoding: [0x0f,0x8a,0x60,0x0e]
+// CHECK: cmgt v5.8h, v6.8h, #{{0x0|0}}     // encoding: [0xc5,0x88,0x60,0x4e]
+// CHECK: cmgt v29.2s, v27.2s, #{{0x0|0}}   // encoding: [0x7d,0x8b,0xa0,0x0e]
+// CHECK: cmgt v9.4s, v7.4s, #{{0x0|0}}     // encoding: [0xe9,0x88,0xa0,0x4e]
+// CHECK: cmgt v3.2d, v31.2d, #{{0x0|0}}    // encoding: [0xe3,0x8b,0xe0,0x4e]
 
 //----------------------------------------------------------------------
 // Vector Compare Mask Less Than or Equal To Zero (Signed Integer)
@@ -313,13 +314,13 @@
          cmle v9.4s, v7.4s, #0
          cmle v3.2d, v31.2d, #0
 
-// CHECK: cmle v0.8b, v15.8b, #0x0    // encoding: [0xe0,0x99,0x20,0x2e]
-// CHECK: cmle v1.16b, v31.16b, #0x0  // encoding: [0xe1,0x9b,0x20,0x6e]
-// CHECK: cmle v15.4h, v16.4h, #0x0   // encoding: [0x0f,0x9a,0x60,0x2e]
-// CHECK: cmle v5.8h, v6.8h, #0x0     // encoding: [0xc5,0x98,0x60,0x6e]
-// CHECK: cmle v29.2s, v27.2s, #0x0   // encoding: [0x7d,0x9b,0xa0,0x2e]
-// CHECK: cmle v9.4s, v7.4s, #0x0     // encoding: [0xe9,0x98,0xa0,0x6e]
-// CHECK: cmle v3.2d, v31.2d, #0x0    // encoding: [0xe3,0x9b,0xe0,0x6e]
+// CHECK: cmle v0.8b, v15.8b, #{{0x0|0}}    // encoding: [0xe0,0x99,0x20,0x2e]
+// CHECK: cmle v1.16b, v31.16b, #{{0x0|0}}  // encoding: [0xe1,0x9b,0x20,0x6e]
+// CHECK: cmle v15.4h, v16.4h, #{{0x0|0}}   // encoding: [0x0f,0x9a,0x60,0x2e]
+// CHECK: cmle v5.8h, v6.8h, #{{0x0|0}}     // encoding: [0xc5,0x98,0x60,0x6e]
+// CHECK: cmle v29.2s, v27.2s, #{{0x0|0}}   // encoding: [0x7d,0x9b,0xa0,0x2e]
+// CHECK: cmle v9.4s, v7.4s, #{{0x0|0}}     // encoding: [0xe9,0x98,0xa0,0x6e]
+// CHECK: cmle v3.2d, v31.2d, #{{0x0|0}}    // encoding: [0xe3,0x9b,0xe0,0x6e]
 
 //----------------------------------------------------------------------
 // Vector Compare Mask Less Than Zero (Signed Integer)
@@ -332,13 +333,13 @@
          cmlt v9.4s, v7.4s, #0
          cmlt v3.2d, v31.2d, #0
 
-// CHECK: cmlt v0.8b, v15.8b, #0x0    // encoding: [0xe0,0xa9,0x20,0x0e]
-// CHECK: cmlt v1.16b, v31.16b, #0x0  // encoding: [0xe1,0xab,0x20,0x4e]
-// CHECK: cmlt v15.4h, v16.4h, #0x0   // encoding: [0x0f,0xaa,0x60,0x0e]
-// CHECK: cmlt v5.8h, v6.8h, #0x0     // encoding: [0xc5,0xa8,0x60,0x4e]
-// CHECK: cmlt v29.2s, v27.2s, #0x0   // encoding: [0x7d,0xab,0xa0,0x0e]
-// CHECK: cmlt v9.4s, v7.4s, #0x0     // encoding: [0xe9,0xa8,0xa0,0x4e]
-// CHECK: cmlt v3.2d, v31.2d, #0x0    // encoding: [0xe3,0xab,0xe0,0x4e]
+// CHECK: cmlt v0.8b, v15.8b, #{{0x0|0}}    // encoding: [0xe0,0xa9,0x20,0x0e]
+// CHECK: cmlt v1.16b, v31.16b, #{{0x0|0}}  // encoding: [0xe1,0xab,0x20,0x4e]
+// CHECK: cmlt v15.4h, v16.4h, #{{0x0|0}}   // encoding: [0x0f,0xaa,0x60,0x0e]
+// CHECK: cmlt v5.8h, v6.8h, #{{0x0|0}}     // encoding: [0xc5,0xa8,0x60,0x4e]
+// CHECK: cmlt v29.2s, v27.2s, #{{0x0|0}}   // encoding: [0x7d,0xab,0xa0,0x0e]
+// CHECK: cmlt v9.4s, v7.4s, #{{0x0|0}}     // encoding: [0xe9,0xa8,0xa0,0x4e]
+// CHECK: cmlt v3.2d, v31.2d, #{{0x0|0}}    // encoding: [0xe3,0xab,0xe0,0x4e]
 
 //----------------------------------------------------------------------
 // Vector Compare Mask Equal to Zero (Floating Point)
diff --git a/test/MC/AArch64/neon-scalar-fp-compare.s b/test/MC/AArch64/neon-scalar-fp-compare.s
index b798b34106..054f923322 100644
--- a/test/MC/AArch64/neon-scalar-fp-compare.s
+++ b/test/MC/AArch64/neon-scalar-fp-compare.s
@@ -1,4 +1,5 @@
 // RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s
+// RUN: llvm-mc -triple arm64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s
 
 // Check that the assembler can handle the documented syntax for AArch64
 
diff --git a/test/MC/AArch64/tls-relocs.s b/test/MC/AArch64/tls-relocs.s
index f99cb41fe5..5b2e988759 100644
--- a/test/MC/AArch64/tls-relocs.s
+++ b/test/MC/AArch64/tls-relocs.s
@@ -1,20 +1,33 @@
-// RUN: llvm-mc -triple=aarch64-none-linux-gnu -show-encoding < %s | FileCheck %s
+// RUN: llvm-mc -triple=aarch64-none-linux-gnu -show-encoding < %s | FileCheck %s --check-prefix=CHECK-AARCH64
 // RUN: llvm-mc -triple=aarch64-none-linux-gnu -filetype=obj < %s -o - | \
 // RUN:   llvm-readobj -r -t | FileCheck --check-prefix=CHECK-ELF %s
 
+// RUN: llvm-mc -triple=arm64-none-linux-gnu -show-encoding < %s | FileCheck %s --check-prefix=CHECK-ARM64
+// RUN: llvm-mc -triple=arm64-none-linux-gnu -filetype=obj < %s -o - | \
+// RUN:   llvm-readobj -r -t | FileCheck --check-prefix=CHECK-ELF %s
+
         // TLS local-dynamic forms
         movz x1, #:dtprel_g2:var
         movn x2, #:dtprel_g2:var
         movz x3, #:dtprel_g2:var
         movn x4, #:dtprel_g2:var
-// CHECK: movz    x1, #:dtprel_g2:var     // encoding: [0x01'A',A,0xc0'A',0x92'A']
-// CHECK-NEXT:                                 //   fixup A - offset: 0, value: :dtprel_g2:var, kind: fixup_a64_movw_dtprel_g2
-// CHECK: movn    x2, #:dtprel_g2:var     // encoding: [0x02'A',A,0xc0'A',0x92'A']
-// CHECK-NEXT:                                 //   fixup A - offset: 0, value: :dtprel_g2:var, kind: fixup_a64_movw_dtprel_g2
-// CHECK: movz    x3, #:dtprel_g2:var     // encoding: [0x03'A',A,0xc0'A',0x92'A']
-// CHECK-NEXT:                                 //   fixup A - offset: 0, value: :dtprel_g2:var, kind: fixup_a64_movw_dtprel_g2
-// CHECK: movn    x4, #:dtprel_g2:var     // encoding: [0x04'A',A,0xc0'A',0x92'A']
-// CHECK-NEXT:                                 //   fixup A - offset: 0, value: :dtprel_g2:var, kind: fixup_a64_movw_dtprel_g2
+// CHECK-AARCH64: movz    x1, #:dtprel_g2:var     // encoding: [0x01'A',A,0xc0'A',0x92'A']
+// CHECK-AARCH64-NEXT:                                 //   fixup A - offset: 0, value: :dtprel_g2:var, kind: fixup_a64_movw_dtprel_g2
+// CHECK-AARCH64: movn    x2, #:dtprel_g2:var     // encoding: [0x02'A',A,0xc0'A',0x92'A']
+// CHECK-AARCH64-NEXT:                                 //   fixup A - offset: 0, value: :dtprel_g2:var, kind: fixup_a64_movw_dtprel_g2
+// CHECK-AARCH64: movz    x3, #:dtprel_g2:var     // encoding: [0x03'A',A,0xc0'A',0x92'A']
+// CHECK-AARCH64-NEXT:                                 //   fixup A - offset: 0, value: :dtprel_g2:var, kind: fixup_a64_movw_dtprel_g2
+// CHECK-AARCH64: movn    x4, #:dtprel_g2:var     // encoding: [0x04'A',A,0xc0'A',0x92'A']
+// CHECK-AARCH64-NEXT:                                 //   fixup A - offset: 0, value: :dtprel_g2:var, kind: fixup_a64_movw_dtprel_g2
+
+// CHECK-ARM64: movz    x1, #:dtprel_g2:var     // encoding: [0bAAA00001,A,0b110AAAAA,0x92]
+// CHECK-ARM64:                                 //   fixup A - offset: 0, value: :dtprel_g2:var, kind: fixup_arm64_movw
+// CHECK-ARM64: movn    x2, #:dtprel_g2:var     // encoding: [0bAAA00010,A,0b110AAAAA,0x92]
+// CHECK-ARM64:                                 //   fixup A - offset: 0, value: :dtprel_g2:var, kind: fixup_arm64_movw
+// CHECK-ARM64: movz    x3, #:dtprel_g2:var     // encoding: [0bAAA00011,A,0b110AAAAA,0x92]
+// CHECK-ARM64:                                 //   fixup A - offset: 0, value: :dtprel_g2:var, kind: fixup_arm64_movw
+// CHECK-ARM64: movn    x4, #:dtprel_g2:var     // encoding: [0bAAA00100,A,0b110AAAAA,0x92]
+// CHECK-ARM64:                                 //   fixup A - offset: 0, value: :dtprel_g2:var, kind: fixup_arm64_movw
 
 // CHECK-ELF:      Relocations [
 // CHECK-ELF-NEXT:   Section (2) .rela.text {
@@ -28,14 +41,23 @@
         movn x6, #:dtprel_g1:var
         movz w7, #:dtprel_g1:var
         movn w8, #:dtprel_g1:var
-// CHECK: movz    x5, #:dtprel_g1:var     // encoding: [0x05'A',A,0xa0'A',0x92'A']
-// CHECK-NEXT:                                 //   fixup A - offset: 0, value: :dtprel_g1:var, kind: fixup_a64_movw_dtprel_g1
-// CHECK: movn    x6, #:dtprel_g1:var     // encoding: [0x06'A',A,0xa0'A',0x92'A']
-// CHECK-NEXT:                                 //   fixup A - offset: 0, value: :dtprel_g1:var, kind: fixup_a64_movw_dtprel_g1
-// CHECK: movz    w7, #:dtprel_g1:var     // encoding: [0x07'A',A,0xa0'A',0x12'A']
-// CHECK-NEXT:                                 //   fixup A - offset: 0, value: :dtprel_g1:var, kind: fixup_a64_movw_dtprel_g1
-// CHECK: movn    w8, #:dtprel_g1:var     // encoding: [0x08'A',A,0xa0'A',0x12'A']
-// CHECK-NEXT:                                 //   fixup A - offset: 0, value: :dtprel_g1:var, kind: fixup_a64_movw_dtprel_g1
+// CHECK-AARCH64: movz    x5, #:dtprel_g1:var     // encoding: [0x05'A',A,0xa0'A',0x92'A']
+// CHECK-AARCH64-NEXT:                                 //   fixup A - offset: 0, value: :dtprel_g1:var, kind: fixup_a64_movw_dtprel_g1
+// CHECK-AARCH64: movn    x6, #:dtprel_g1:var     // encoding: [0x06'A',A,0xa0'A',0x92'A']
+// CHECK-AARCH64-NEXT:                                 //   fixup A - offset: 0, value: :dtprel_g1:var, kind: fixup_a64_movw_dtprel_g1
+// CHECK-AARCH64: movz    w7, #:dtprel_g1:var     // encoding: [0x07'A',A,0xa0'A',0x12'A']
+// CHECK-AARCH64-NEXT:                                 //   fixup A - offset: 0, value: :dtprel_g1:var, kind: fixup_a64_movw_dtprel_g1
+// CHECK-AARCH64: movn    w8, #:dtprel_g1:var     // encoding: [0x08'A',A,0xa0'A',0x12'A']
+// CHECK-AARCH64-NEXT:                                 //   fixup A - offset: 0, value: :dtprel_g1:var, kind: fixup_a64_movw_dtprel_g1
+
+// CHECK-ARM64: movz    x5, #:dtprel_g1:var     // encoding: [0bAAA00101,A,0b101AAAAA,0x92]
+// CHECK-ARM64:                                 //   fixup A - offset: 0, value: :dtprel_g1:var, kind: fixup_arm64_movw
+// CHECK-ARM64: movn    x6, #:dtprel_g1:var     // encoding: [0bAAA00110,A,0b101AAAAA,0x92]
+// CHECK-ARM64:                                 //   fixup A - offset: 0, value: :dtprel_g1:var, kind: fixup_arm64_movw
+// CHECK-ARM64: movz    w7, #:dtprel_g1:var     // encoding: [0bAAA00111,A,0b101AAAAA,0x12]
+// CHECK-ARM64:                                 //   fixup A - offset: 0, value: :dtprel_g1:var, kind: fixup_arm64_movw
+// CHECK-ARM64: movn    w8, #:dtprel_g1:var     // encoding: [0bAAA01000,A,0b101AAAAA,0x12]
+// CHECK-ARM64:                                 //   fixup A - offset: 0, value: :dtprel_g1:var, kind: fixup_arm64_movw
 
 // CHECK-ELF-NEXT:     0x10 R_AARCH64_TLSLD_MOVW_DTPREL_G1 [[VARSYM]]
 // CHECK-ELF-NEXT:     0x14 R_AARCH64_TLSLD_MOVW_DTPREL_G1 [[VARSYM]]
@@ -45,10 +67,15 @@
 
         movk x9, #:dtprel_g1_nc:var
         movk w10, #:dtprel_g1_nc:var
-// CHECK: movk    x9, #:dtprel_g1_nc:var  // encoding: [0x09'A',A,0xa0'A',0xf2'A']
-// CHECK-NEXT:                                 //   fixup A - offset: 0, value: :dtprel_g1_nc:var, kind: fixup_a64_movw_dtprel_g1_nc
-// CHECK: movk    w10, #:dtprel_g1_nc:var // encoding: [0x0a'A',A,0xa0'A',0x72'A']
-// CHECK-NEXT:                                 //   fixup A - offset: 0, value: :dtprel_g1_nc:var, kind: fixup_a64_movw_dtprel_g1_nc
+// CHECK-AARCH64: movk    x9, #:dtprel_g1_nc:var  // encoding: [0x09'A',A,0xa0'A',0xf2'A']
+// CHECK-AARCH64-NEXT:                                 //   fixup A - offset: 0, value: :dtprel_g1_nc:var, kind: fixup_a64_movw_dtprel_g1_nc
+// CHECK-AARCH64: movk    w10, #:dtprel_g1_nc:var // encoding: [0x0a'A',A,0xa0'A',0x72'A']
+// CHECK-AARCH64-NEXT:                                 //   fixup A - offset: 0, value: :dtprel_g1_nc:var, kind: fixup_a64_movw_dtprel_g1_nc
+
+// CHECK-ARM64: movk    x9, #:dtprel_g1_nc:var  // encoding: [0bAAA01001,A,0b101AAAAA,0xf2]
+// CHECK-ARM64:                                 //   fixup A - offset: 0, value: :dtprel_g1_nc:var, kind: fixup_arm64_movw
+// CHECK-ARM64: movk    w10, #:dtprel_g1_nc:var // encoding: [0bAAA01010,A,0b101AAAAA,0x72]
+// CHECK-ARM64:                                 //   fixup A - offset: 0, value: :dtprel_g1_nc:var, kind: fixup_arm64_movw
 
 // CHECK-ELF-NEXT:     0x20 R_AARCH64_TLSLD_MOVW_DTPREL_G1_NC [[VARSYM]]
 // CHECK-ELF-NEXT:     0x24 R_AARCH64_TLSLD_MOVW_DTPREL_G1_NC [[VARSYM]]
@@ -58,13 +85,22 @@
         movn x12, #:dtprel_g0:var
         movz w13, #:dtprel_g0:var
         movn w14, #:dtprel_g0:var
-// CHECK: movz    x11, #:dtprel_g0:var    // encoding: [0x0b'A',A,0x80'A',0x92'A']
-// CHECK-NEXT:                                 //   fixup A - offset: 0, value: :dtprel_g0:var, kind: fixup_a64_movw_dtprel_g0
-// CHECK: movn    x12, #:dtprel_g0:var    // encoding: [0x0c'A',A,0x80'A',0x92'A']
-// CHECK-NEXT:                                 //   fixup A - offset: 0, value: :dtprel_g0:var, kind: fixup_a64_movw_dtprel_g0
-// CHECK: movz    w13, #:dtprel_g0:var    // encoding: [0x0d'A',A,0x80'A',0x12'A']
-// CHECK-NEXT:                                 //   fixup A - offset: 0, value: :dtprel_g0:var, kind: fixup_a64_movw_dtprel_g0
-// CHECK: movn    w14, #:dtprel_g0:var    // encoding: [0x0e'A',A,0x80'A',0x12'A']
+// CHECK-AARCH64: movz    x11, #:dtprel_g0:var    // encoding: [0x0b'A',A,0x80'A',0x92'A']
+// CHECK-AARCH64-NEXT:                                 //   fixup A - offset: 0, value: :dtprel_g0:var, kind: fixup_a64_movw_dtprel_g0
+// CHECK-AARCH64: movn    x12, #:dtprel_g0:var    // encoding: [0x0c'A',A,0x80'A',0x92'A']
+// CHECK-AARCH64-NEXT:                                 //   fixup A - offset: 0, value: :dtprel_g0:var, kind: fixup_a64_movw_dtprel_g0
+// CHECK-AARCH64: movz    w13, #:dtprel_g0:var    // encoding: [0x0d'A',A,0x80'A',0x12'A']
+// CHECK-AARCH64-NEXT:                                 //   fixup A - offset: 0, value: :dtprel_g0:var, kind: fixup_a64_movw_dtprel_g0
+// CHECK-AARCH64: movn    w14, #:dtprel_g0:var    // encoding: [0x0e'A',A,0x80'A',0x12'A']
+
+// CHECK-ARM64: movz    x11, #:dtprel_g0:var    // encoding: [0bAAA01011,A,0b100AAAAA,0x92]
+// CHECK-ARM64:                                 //   fixup A - offset: 0, value: :dtprel_g0:var, kind: fixup_arm64_movw
+// CHECK-ARM64: movn    x12, #:dtprel_g0:var    // encoding: [0bAAA01100,A,0b100AAAAA,0x92]
+// CHECK-ARM64:                                 //   fixup A - offset: 0, value: :dtprel_g0:var, kind: fixup_arm64_movw
+// CHECK-ARM64: movz    w13, #:dtprel_g0:var    // encoding: [0bAAA01101,A,0b100AAAAA,0x12]
+// CHECK-ARM64:                                 //   fixup A - offset: 0, value: :dtprel_g0:var, kind: fixup_arm64_movw
+// CHECK-ARM64: movn    w14, #:dtprel_g0:var    // encoding: [0bAAA01110,A,0b100AAAAA,0x12]
+// CHECK-ARM64:                                 //   fixup A - offset: 0, value: :dtprel_g0:var, kind: fixup_arm64_movw
 
 // CHECK-ELF-NEXT:     0x28 R_AARCH64_TLSLD_MOVW_DTPREL_G0 [[VARSYM]]
 // CHECK-ELF-NEXT:     0x2C R_AARCH64_TLSLD_MOVW_DTPREL_G0 [[VARSYM]]
@@ -74,10 +110,15 @@
 
         movk x15, #:dtprel_g0_nc:var
         movk w16, #:dtprel_g0_nc:var
-// CHECK: movk    x15, #:dtprel_g0_nc:var // encoding: [0x0f'A',A,0x80'A',0xf2'A']
-// CHECK-NEXT:                                 //   fixup A - offset: 0, value: :dtprel_g0_nc:var, kind: fixup_a64_movw_dtprel_g0_nc
-// CHECK: movk    w16, #:dtprel_g0_nc:var // encoding: [0x10'A',A,0x80'A',0x72'A']
-// CHECK-NEXT:                                 //   fixup A - offset: 0, value: :dtprel_g0_nc:var, kind: fixup_a64_movw_dtprel_g0_nc
+// CHECK-AARCH64: movk    x15, #:dtprel_g0_nc:var // encoding: [0x0f'A',A,0x80'A',0xf2'A']
+// CHECK-AARCH64-NEXT:                                 //   fixup A - offset: 0, value: :dtprel_g0_nc:var, kind: fixup_a64_movw_dtprel_g0_nc
+// CHECK-AARCH64: movk    w16, #:dtprel_g0_nc:var // encoding: [0x10'A',A,0x80'A',0x72'A']
+// CHECK-AARCH64-NEXT:                                 //   fixup A - offset: 0, value: :dtprel_g0_nc:var, kind: fixup_a64_movw_dtprel_g0_nc
+
+// CHECK-ARM64: movk    x15, #:dtprel_g0_nc:var // encoding: [0bAAA01111,A,0b100AAAAA,0xf2]
+// CHECK-ARM64:                                 //   fixup A - offset: 0, value: :dtprel_g0_nc:var, kind: fixup_arm64_movw
+// CHECK-ARM64: movk    w16, #:dtprel_g0_nc:var // encoding: [0bAAA10000,A,0b100AAAAA,0x72]
+// CHECK-ARM64:                                 //   fixup A - offset: 0, value: :dtprel_g0_nc:var, kind: fixup_arm64_movw
 
 // CHECK-ELF-NEXT:     0x38 R_AARCH64_TLSLD_MOVW_DTPREL_G0_NC [[VARSYM]]
 // CHECK-ELF-NEXT:     0x3C R_AARCH64_TLSLD_MOVW_DTPREL_G0_NC [[VARSYM]]
@@ -85,10 +126,15 @@
 
         add x17, x18, #:dtprel_hi12:var, lsl #12
         add w19, w20, #:dtprel_hi12:var, lsl #12
-// CHECK: add     x17, x18, #:dtprel_hi12:var, lsl #12 // encoding: [0x51'A',0x02'A',0x40'A',0x91'A']
-// CHECK-NEXT:                                 //   fixup A - offset: 0, value: :dtprel_hi12:var, kind: fixup_a64_add_dtprel_hi12
-// CHECK: add     w19, w20, #:dtprel_hi12:var, lsl #12 // encoding: [0x93'A',0x02'A',0x40'A',0x11'A']
-// CHECK-NEXT:                                 //   fixup A - offset: 0, value: :dtprel_hi12:var, kind: fixup_a64_add_dtprel_hi12
+// CHECK-AARCH64: add     x17, x18, #:dtprel_hi12:var, lsl #12 // encoding: [0x51'A',0x02'A',0x40'A',0x91'A']
+// CHECK-AARCH64-NEXT:                                 //   fixup A - offset: 0, value: :dtprel_hi12:var, kind: fixup_a64_add_dtprel_hi12
+// CHECK-AARCH64: add     w19, w20, #:dtprel_hi12:var, lsl #12 // encoding: [0x93'A',0x02'A',0x40'A',0x11'A']
+// CHECK-AARCH64-NEXT:                                 //   fixup A - offset: 0, value: :dtprel_hi12:var, kind: fixup_a64_add_dtprel_hi12
+
+// CHECK-ARM64: add    x17, x18, :dtprel_hi12:var, lsl #12 // encoding: [0x51,0bAAAAAA10,0b00AAAAAA,0x91]
+// CHECK-ARM64:                                            //   fixup A - offset: 0, value: :dtprel_hi12:var, kind: fixup_arm64_add_imm12
+// CHECK-ARM64: add    w19, w20, :dtprel_hi12:var, lsl #12 // encoding: [0x93,0bAAAAAA10,0b00AAAAAA,0x11]
+// CHECK-ARM64:                                            //   fixup A - offset: 0, value: :dtprel_hi12:var, kind: fixup_arm64_add_imm12
 
 // CHECK-ELF-NEXT:     0x40 R_AARCH64_TLSLD_ADD_DTPREL_HI12 [[VARSYM]]
 // CHECK-ELF-NEXT:     0x44 R_AARCH64_TLSLD_ADD_DTPREL_HI12 [[VARSYM]]
@@ -96,10 +142,15 @@
 
         add x21, x22, #:dtprel_lo12:var
         add w23, w24, #:dtprel_lo12:var
-// CHECK: add     x21, x22, #:dtprel_lo12:var // encoding: [0xd5'A',0x02'A',A,0x91'A']
-// CHECK-NEXT:                                 //   fixup A - offset: 0, value: :dtprel_lo12:var, kind: fixup_a64_add_dtprel_lo12
-// CHECK: add     w23, w24, #:dtprel_lo12:var // encoding: [0x17'A',0x03'A',A,0x11'A']
-// CHECK-NEXT:                                 //   fixup A - offset: 0, value: :dtprel_lo12:var, kind: fixup_a64_add_dtprel_lo12
+// CHECK-AARCH64: add     x21, x22, #:dtprel_lo12:var // encoding: [0xd5'A',0x02'A',A,0x91'A']
+// CHECK-AARCH64-NEXT:                                 //   fixup A - offset: 0, value: :dtprel_lo12:var, kind: fixup_a64_add_dtprel_lo12
+// CHECK-AARCH64: add     w23, w24, #:dtprel_lo12:var // encoding: [0x17'A',0x03'A',A,0x11'A']
+// CHECK-AARCH64-NEXT:                                 //   fixup A - offset: 0, value: :dtprel_lo12:var, kind: fixup_a64_add_dtprel_lo12
+
+// CHECK-ARM64: add    x21, x22, :dtprel_lo12:var // encoding: [0xd5,0bAAAAAA10,0b00AAAAAA,0x91]
+// CHECK-ARM64:                                   //   fixup A - offset: 0, value: :dtprel_lo12:var, kind: fixup_arm64_add_imm12
+// CHECK-ARM64: add    w23, w24, :dtprel_lo12:var // encoding: [0x17,0bAAAAAA11,0b00AAAAAA,0x11]
+// CHECK-ARM64:                                   //   fixup A - offset: 0, value: :dtprel_lo12:var, kind: fixup_arm64_add_imm12
 
 // CHECK-ELF-NEXT:     0x48 R_AARCH64_TLSLD_ADD_DTPREL_LO12 [[VARSYM]]
 // CHECK-ELF-NEXT:     0x4C R_AARCH64_TLSLD_ADD_DTPREL_LO12 [[VARSYM]]
@@ -107,10 +158,15 @@
 
         add x25, x26, #:dtprel_lo12_nc:var
         add w27, w28, #:dtprel_lo12_nc:var
-// CHECK: add     x25, x26, #:dtprel_lo12_nc:var // encoding: [0x59'A',0x03'A',A,0x91'A']
-// CHECK-NEXT:                                 //   fixup A - offset: 0, value: :dtprel_lo12_nc:var, kind: fixup_a64_add_dtprel_lo12_nc
-// CHECK: add     w27, w28, #:dtprel_lo12_nc:var // encoding: [0x9b'A',0x03'A',A,0x11'A']
-// CHECK-NEXT:                                 //   fixup A - offset: 0, value: :dtprel_lo12_nc:var, kind: fixup_a64_add_dtprel_lo12_nc
+// CHECK-AARCH64: add     x25, x26, #:dtprel_lo12_nc:var // encoding: [0x59'A',0x03'A',A,0x91'A']
+// CHECK-AARCH64-NEXT:                                 //   fixup A - offset: 0, value: :dtprel_lo12_nc:var, kind: fixup_a64_add_dtprel_lo12_nc
+// CHECK-AARCH64: add     w27, w28, #:dtprel_lo12_nc:var // encoding: [0x9b'A',0x03'A',A,0x11'A']
+// CHECK-AARCH64-NEXT:                                 //   fixup A - offset: 0, value: :dtprel_lo12_nc:var, kind: fixup_a64_add_dtprel_lo12_nc
+
+// CHECK-ARM64: add    x25, x26, :dtprel_lo12_nc:var // encoding: [0x59,0bAAAAAA11,0b00AAAAAA,0x91]
+// CHECK-ARM64:                                      //   fixup A - offset: 0, value: :dtprel_lo12_nc:var, kind: fixup_arm64_add_imm12
+// CHECK-ARM64: add    w27, w28, :dtprel_lo12_nc:var // encoding: [0x9b,0bAAAAAA11,0b00AAAAAA,0x11]
+// CHECK-ARM64:                                      //   fixup A - offset: 0, value: :dtprel_lo12_nc:var, kind: fixup_arm64_add_imm12
 
 // CHECK-ELF-NEXT:     0x50 R_AARCH64_TLSLD_ADD_DTPREL_LO12_NC [[VARSYM]]
 // CHECK-ELF-NEXT:     0x54 R_AARCH64_TLSLD_ADD_DTPREL_LO12_NC [[VARSYM]]
@@ -118,10 +174,15 @@
 
         ldrb w29, [x30, #:dtprel_lo12:var]
         ldrsb x29, [x28, #:dtprel_lo12_nc:var]
-// CHECK: ldrb    w29, [x30, #:dtprel_lo12:var] // encoding: [0xdd'A',0x03'A',0x40'A',0x39'A']
-// CHECK-NEXT:                                 //   fixup A - offset: 0, value: :dtprel_lo12:var, kind: fixup_a64_ldst8_dtprel_lo12
-// CHECK: ldrsb   x29, [x28, #:dtprel_lo12_nc:var] // encoding: [0x9d'A',0x03'A',0x80'A',0x39'A']
-// CHECK-NEXT:                                 //   fixup A - offset: 0, value: :dtprel_lo12_nc:var, kind: fixup_a64_ldst8_dtprel_lo12_nc
+// CHECK-AARCH64: ldrb    w29, [x30, #:dtprel_lo12:var] // encoding: [0xdd'A',0x03'A',0x40'A',0x39'A']
+// CHECK-AARCH64-NEXT:                                 //   fixup A - offset: 0, value: :dtprel_lo12:var, kind: fixup_a64_ldst8_dtprel_lo12
+// CHECK-AARCH64: ldrsb   x29, [x28, #:dtprel_lo12_nc:var] // encoding: [0x9d'A',0x03'A',0x80'A',0x39'A']
+// CHECK-AARCH64-NEXT:                                 //   fixup A - offset: 0, value: :dtprel_lo12_nc:var, kind: fixup_a64_ldst8_dtprel_lo12_nc
+
+// CHECK-ARM64: ldrb    w29, [x30, :dtprel_lo12:var] // encoding: [0xdd,0bAAAAAA11,0b01AAAAAA,0x39]
+// CHECK-ARM64:                                      //   fixup A - offset: 0, value: :dtprel_lo12:var, kind: fixup_arm64_ldst_imm12_scale1
+// CHECK-ARM64: ldrsb    x29, [x28, :dtprel_lo12_nc:var] // encoding: [0x9d,0bAAAAAA11,0b10AAAAAA,0x39]
+// CHECK-ARM64:                                          //   fixup A - offset: 0, value: :dtprel_lo12_nc:var, kind: fixup_arm64_ldst_imm12_scale1
 
 // CHECK-ELF-NEXT:     0x58 R_AARCH64_TLSLD_LDST8_DTPREL_LO12 [[VARSYM]]
 // CHECK-ELF-NEXT:     0x5C R_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC [[VARSYM]]
@@ -129,10 +190,15 @@
 
         strh w27, [x26, #:dtprel_lo12:var]
         ldrsh x25, [x24, #:dtprel_lo12_nc:var]
-// CHECK: strh    w27, [x26, #:dtprel_lo12:var] // encoding: [0x5b'A',0x03'A',A,0x79'A']
-// CHECK-NEXT:                                 //   fixup A - offset: 0, value: :dtprel_lo12:var, kind: fixup_a64_ldst16_dtprel_lo12
-// CHECK: ldrsh   x25, [x24, #:dtprel_lo12_nc:var] // encoding: [0x19'A',0x03'A',0x80'A',0x79'A']
-// CHECK-NEXT:                                 //   fixup A - offset: 0, value: :dtprel_lo12_nc:var, kind: fixup_a64_ldst16_dtprel_lo12_n
+// CHECK-AARCH64: strh    w27, [x26, #:dtprel_lo12:var] // encoding: [0x5b'A',0x03'A',A,0x79'A']
+// CHECK-AARCH64-NEXT:                                 //   fixup A - offset: 0, value: :dtprel_lo12:var, kind: fixup_a64_ldst16_dtprel_lo12
+// CHECK-AARCH64: ldrsh   x25, [x24, #:dtprel_lo12_nc:var] // encoding: [0x19'A',0x03'A',0x80'A',0x79'A']
+// CHECK-AARCH64-NEXT:                                 //   fixup A - offset: 0, value: :dtprel_lo12_nc:var, kind: fixup_a64_ldst16_dtprel_lo12_n
+
+// CHECK-ARM64: strh    w27, [x26, :dtprel_lo12:var] // encoding: [0x5b,0bAAAAAA11,0b00AAAAAA,0x79]
+// CHECK-ARM64:                                      //   fixup A - offset: 0, value: :dtprel_lo12:var, kind: fixup_arm64_ldst_imm12_scale2
+// CHECK-ARM64: ldrsh    x25, [x24, :dtprel_lo12_nc:var] // encoding: [0x19,0bAAAAAA11,0b10AAAAAA,0x79]
+// CHECK-ARM64:                                          //   fixup A - offset: 0, value: :dtprel_lo12_nc:var, kind: fixup_arm64_ldst_imm12_scale2
 
 // CHECK-ELF-NEXT:     0x60 R_AARCH64_TLSLD_LDST16_DTPREL_LO12 [[VARSYM]]
 // CHECK-ELF-NEXT:     0x64 R_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC [[VARSYM]]
@@ -140,10 +206,15 @@
 
         ldr w23, [x22, #:dtprel_lo12:var]
         ldrsw x21, [x20, #:dtprel_lo12_nc:var]
-// CHECK: ldr     w23, [x22, #:dtprel_lo12:var] // encoding: [0xd7'A',0x02'A',0x40'A',0xb9'A']
-// CHECK-NEXT:                                 //   fixup A - offset: 0, value: :dtprel_lo12:var, kind: fixup_a64_ldst32_dtprel_lo12
-// CHECK: ldrsw   x21, [x20, #:dtprel_lo12_nc:var] // encoding: [0x95'A',0x02'A',0x80'A',0xb9'A']
-// CHECK-NEXT:                                 //   fixup A - offset: 0, value: :dtprel_lo12_nc:var, kind: fixup_a64_ldst32_dtprel_lo12_n
+// CHECK-AARCH64: ldr     w23, [x22, #:dtprel_lo12:var] // encoding: [0xd7'A',0x02'A',0x40'A',0xb9'A']
+// CHECK-AARCH64-NEXT:                                 //   fixup A - offset: 0, value: :dtprel_lo12:var, kind: fixup_a64_ldst32_dtprel_lo12
+// CHECK-AARCH64: ldrsw   x21, [x20, #:dtprel_lo12_nc:var] // encoding: [0x95'A',0x02'A',0x80'A',0xb9'A']
+// CHECK-AARCH64-NEXT:                                 //   fixup A - offset: 0, value: :dtprel_lo12_nc:var, kind: fixup_a64_ldst32_dtprel_lo12_n
+
+// CHECK-ARM64: ldr    w23, [x22, :dtprel_lo12:var] // encoding: [0xd7,0bAAAAAA10,0b01AAAAAA,0xb9]
+// CHECK-ARM64:                                     //   fixup A - offset: 0, value: :dtprel_lo12:var, kind: fixup_arm64_ldst_imm12_scale4
+// CHECK-ARM64: ldrsw    x21, [x20, :dtprel_lo12_nc:var] // encoding: [0x95,0bAAAAAA10,0b10AAAAAA,0xb9]
+// CHECK-ARM64:                                          //   fixup A - offset: 0, value: :dtprel_lo12_nc:var, kind: fixup_arm64_ldst_imm12_scale4
 
 // CHECK-ELF-NEXT:     0x68 R_AARCH64_TLSLD_LDST32_DTPREL_LO12 [[VARSYM]]
 // CHECK-ELF-NEXT:     0x6C R_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC [[VARSYM]]
@@ -151,11 +222,15 @@
 
         ldr x19, [x18, #:dtprel_lo12:var]
         str x17, [x16, #:dtprel_lo12_nc:var]
-// CHECK: ldr     x19, [x18, #:dtprel_lo12:var] // encoding: [0x53'A',0x02'A',0x40'A',0xf9'A']
-// CHECK-NEXT:                                 //   fixup A - offset: 0, value: :dtprel_lo12:var, kind: fixup_a64_ldst64_dtprel_lo12
-// CHECK: str     x17, [x16, #:dtprel_lo12_nc:var] // encoding: [0x11'A',0x02'A',A,0xf9'A']
-// CHECK-NEXT:                                 //   fixup A - offset: 0, value: :dtprel_lo12_nc:var, kind: fixup_a64_ldst64_dtprel_lo12_nc
+// CHECK-AARCH64: ldr     x19, [x18, #:dtprel_lo12:var] // encoding: [0x53'A',0x02'A',0x40'A',0xf9'A']
+// CHECK-AARCH64-NEXT:                                 //   fixup A - offset: 0, value: :dtprel_lo12:var, kind: fixup_a64_ldst64_dtprel_lo12
+// CHECK-AARCH64: str     x17, [x16, #:dtprel_lo12_nc:var] // encoding: [0x11'A',0x02'A',A,0xf9'A']
+// CHECK-AARCH64-NEXT:                                 //   fixup A - offset: 0, value: :dtprel_lo12_nc:var, kind: fixup_a64_ldst64_dtprel_lo12_nc
 
+// CHECK-ARM64: ldr    x19, [x18, :dtprel_lo12:var] // encoding: [0x53,0bAAAAAA10,0b01AAAAAA,0xf9]
+// CHECK-ARM64:                                     //   fixup A - offset: 0, value: :dtprel_lo12:var, kind: fixup_arm64_ldst_imm12_scale8
+// CHECK-ARM64: str    x17, [x16, :dtprel_lo12_nc:var] // encoding: [0x11,0bAAAAAA10,0b00AAAAAA,0xf9]
+// CHECK-ARM64:                                        //   fixup A - offset: 0, value: :dtprel_lo12_nc:var, kind: fixup_arm64_ldst_imm12_scale8
 
 // CHECK-ELF-NEXT:     0x70 R_AARCH64_TLSLD_LDST64_DTPREL_LO12 [[VARSYM]]
 // CHECK-ELF-NEXT:     0x74 R_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC [[VARSYM]]
@@ -164,10 +239,15 @@
         // TLS initial-exec forms
         movz x15, #:gottprel_g1:var
         movz w14, #:gottprel_g1:var
-// CHECK: movz    x15, #:gottprel_g1:var  // encoding: [0x0f'A',A,0xa0'A',0x92'A']
-// CHECK-NEXT:                                 //   fixup A - offset: 0, value: :gottprel_g1:var, kind: fixup_a64_movw_gottprel_g1
-// CHECK: movz    w14, #:gottprel_g1:var  // encoding: [0x0e'A',A,0xa0'A',0x12'A']
-// CHECK-NEXT:                                 //   fixup A - offset: 0, value: :gottprel_g1:var, kind: fixup_a64_movw_gottprel_g1
+// CHECK-AARCH64: movz    x15, #:gottprel_g1:var  // encoding: [0x0f'A',A,0xa0'A',0x92'A']
+// CHECK-AARCH64-NEXT:                                 //   fixup A - offset: 0, value: :gottprel_g1:var, kind: fixup_a64_movw_gottprel_g1
+// CHECK-AARCH64: movz    w14, #:gottprel_g1:var  // encoding: [0x0e'A',A,0xa0'A',0x12'A']
+// CHECK-AARCH64-NEXT:                                 //   fixup A - offset: 0, value: :gottprel_g1:var, kind: fixup_a64_movw_gottprel_g1
+
+// CHECK-ARM64: movz    x15, #:gottprel_g1:var  // encoding: [0bAAA01111,A,0b101AAAAA,0x92]
+// CHECK-ARM64:                                 //   fixup A - offset: 0, value: :gottprel_g1:var, kind: fixup_arm64_movw
+// CHECK-ARM64: movz    w14, #:gottprel_g1:var  // encoding: [0bAAA01110,A,0b101AAAAA,0x12]
+// CHECK-ARM64:                                 //   fixup A - offset: 0, value: :gottprel_g1:var, kind: fixup_arm64_movw
 
 // CHECK-ELF-NEXT:     0x78 R_AARCH64_TLSIE_MOVW_GOTTPREL_G1 [[VARSYM]]
 // CHECK-ELF-NEXT:     0x7C R_AARCH64_TLSIE_MOVW_GOTTPREL_G1 [[VARSYM]]
@@ -175,10 +255,15 @@
 
         movk x13, #:gottprel_g0_nc:var
         movk w12, #:gottprel_g0_nc:var
-// CHECK: movk    x13, #:gottprel_g0_nc:var // encoding: [0x0d'A',A,0x80'A',0xf2'A']
-// CHECK-NEXT:                                 //   fixup A - offset: 0, value: :gottprel_g0_nc:var, kind: fixup_a64_movw_gottprel_g0_nc
-// CHECK: movk    w12, #:gottprel_g0_nc:var // encoding: [0x0c'A',A,0x80'A',0x72'A']
-// CHECK-NEXT:                                 //   fixup A - offset: 0, value: :gottprel_g0_nc:var, kind: fixup_a64_movw_gottprel_g0_nc
+// CHECK-AARCH64: movk    x13, #:gottprel_g0_nc:var // encoding: [0x0d'A',A,0x80'A',0xf2'A']
+// CHECK-AARCH64-NEXT:                                 //   fixup A - offset: 0, value: :gottprel_g0_nc:var, kind: fixup_a64_movw_gottprel_g0_nc
+// CHECK-AARCH64: movk    w12, #:gottprel_g0_nc:var // encoding: [0x0c'A',A,0x80'A',0x72'A']
+// CHECK-AARCH64-NEXT:                                 //   fixup A - offset: 0, value: :gottprel_g0_nc:var, kind: fixup_a64_movw_gottprel_g0_nc
+
+// CHECK-ARM64: movk    x13, #:gottprel_g0_nc:var // encoding: [0bAAA01101,A,0b100AAAAA,0xf2]
+// CHECK-ARM64:                                   //   fixup A - offset: 0, value: :gottprel_g0_nc:var, kind: fixup_arm64_movw
+// CHECK-ARM64: movk    w12, #:gottprel_g0_nc:var // encoding: [0bAAA01100,A,0b100AAAAA,0x72]
+// CHECK-ARM64:                                   //   fixup A - offset: 0, value: :gottprel_g0_nc:var, kind: fixup_arm64_movw
 
 // CHECK-ELF-NEXT:     0x80 R_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC [[VARSYM]]
 // CHECK-ELF-NEXT:     0x84 R_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC [[VARSYM]]
@@ -187,12 +272,19 @@
         adrp x11, :gottprel:var
         ldr x10, [x0, #:gottprel_lo12:var]
         ldr x9, :gottprel:var
-// CHECK: adrp    x11, :gottprel:var      // encoding: [0x0b'A',A,A,0x90'A']
-// CHECK-NEXT:                                 //   fixup A - offset: 0, value: :gottprel:var, kind: fixup_a64_adr_gottprel_page
-// CHECK: ldr     x10, [x0, #:gottprel_lo12:var] // encoding: [0x0a'A',A,0x40'A',0xf9'A']
-// CHECK-NEXT:                                 //   fixup A - offset: 0, value: :gottprel_lo12:var, kind: fixup_a64_ld64_gottprel_lo12_nc
-// CHECK: ldr     x9, :gottprel:var       // encoding: [0x09'A',A,A,0x58'A']
-// CHECK-NEXT:                                 //   fixup A - offset: 0, value: :gottprel:var, kind: fixup_a64_ld_gottprel_prel19
+// CHECK-AARCH64: adrp    x11, :gottprel:var      // encoding: [0x0b'A',A,A,0x90'A']
+// CHECK-AARCH64-NEXT:                                 //   fixup A - offset: 0, value: :gottprel:var, kind: fixup_a64_adr_gottprel_page
+// CHECK-AARCH64: ldr     x10, [x0, #:gottprel_lo12:var] // encoding: [0x0a'A',A,0x40'A',0xf9'A']
+// CHECK-AARCH64-NEXT:                                 //   fixup A - offset: 0, value: :gottprel_lo12:var, kind: fixup_a64_ld64_gottprel_lo12_nc
+// CHECK-AARCH64: ldr     x9, :gottprel:var       // encoding: [0x09'A',A,A,0x58'A']
+// CHECK-AARCH64-NEXT:                                 //   fixup A - offset: 0, value: :gottprel:var, kind: fixup_a64_ld_gottprel_prel19
+
+// CHECK-ARM64: adrp    x11, :gottprel:var      // encoding: [0x0b'A',A,A,0x90'A']
+// CHECK-ARM64:                                 //   fixup A - offset: 0, value: :gottprel:var, kind: fixup_arm64_pcrel_adrp_imm21
+// CHECK-ARM64: ldr    x10, [x0, :gottprel_lo12:var] // encoding: [0x0a,0bAAAAAA00,0b01AAAAAA,0xf9]
+// CHECK-ARM64:                                      //   fixup A - offset: 0, value: :gottprel_lo12:var, kind: fixup_arm64_ldst_imm12_scale8
+// CHECK-ARM64: ldr    x9, :gottprel:var       // encoding: [0bAAA01001,A,A,0x58]
+// CHECK-ARM64:                                //   fixup A - offset: 0, value: :gottprel:var, kind: fixup_arm64_ldr_pcrel_imm19
 
 // CHECK-ELF-NEXT:     0x88 R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21 [[VARSYM]]
 // CHECK-ELF-NEXT:     0x8C R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC [[VARSYM]]
@@ -202,10 +294,15 @@
         // TLS local-exec forms
         movz x3, #:tprel_g2:var
         movn x4, #:tprel_g2:var
-// CHECK: movz    x3, #:tprel_g2:var      // encoding: [0x03'A',A,0xc0'A',0x92'A']
-// CHECK-NEXT:                                 //   fixup A - offset: 0, value: :tprel_g2:var, kind: fixup_a64_movw_tprel_g2
-// CHECK: movn    x4, #:tprel_g2:var      // encoding: [0x04'A',A,0xc0'A',0x92'A']
-// CHECK-NEXT:                                 //   fixup A - offset: 0, value: :tprel_g2:var, kind: fixup_a64_movw_tprel_g2
+// CHECK-AARCH64: movz    x3, #:tprel_g2:var      // encoding: [0x03'A',A,0xc0'A',0x92'A']
+// CHECK-AARCH64-NEXT:                                 //   fixup A - offset: 0, value: :tprel_g2:var, kind: fixup_a64_movw_tprel_g2
+// CHECK-AARCH64: movn    x4, #:tprel_g2:var      // encoding: [0x04'A',A,0xc0'A',0x92'A']
+// CHECK-AARCH64-NEXT:                                 //   fixup A - offset: 0, value: :tprel_g2:var, kind: fixup_a64_movw_tprel_g2
+
+// CHECK-ARM64: movz    x3, #:tprel_g2:var      // encoding: [0bAAA00011,A,0b110AAAAA,0x92]
+// CHECK-ARM64:                                 //   fixup A - offset: 0, value: :tprel_g2:var, kind: fixup_arm64_movw
+// CHECK-ARM64: movn    x4, #:tprel_g2:var      // encoding: [0bAAA00100,A,0b110AAAAA,0x92]
+// CHECK-ARM64:                                 //   fixup A - offset: 0, value: :tprel_g2:var, kind: fixup_arm64_movw
 
 // CHECK-ELF-NEXT:     0x94 R_AARCH64_TLSLE_MOVW_TPREL_G2 [[VARSYM]]
 // CHECK-ELF-NEXT:     0x98 R_AARCH64_TLSLE_MOVW_TPREL_G2 [[VARSYM]]
@@ -215,14 +312,23 @@
         movn x6, #:tprel_g1:var
         movz w7, #:tprel_g1:var
         movn w8, #:tprel_g1:var
-// CHECK: movz    x5, #:tprel_g1:var      // encoding: [0x05'A',A,0xa0'A',0x92'A']
-// CHECK-NEXT:                                 //   fixup A - offset: 0, value: :tprel_g1:var, kind: fixup_a64_movw_tprel_g1
-// CHECK: movn    x6, #:tprel_g1:var      // encoding: [0x06'A',A,0xa0'A',0x92'A']
-// CHECK-NEXT:                                 //   fixup A - offset: 0, value: :tprel_g1:var, kind: fixup_a64_movw_tprel_g1
-// CHECK: movz    w7, #:tprel_g1:var      // encoding: [0x07'A',A,0xa0'A',0x12'A']
-// CHECK-NEXT:                                 //   fixup A - offset: 0, value: :tprel_g1:var, kind: fixup_a64_movw_tprel_g1
-// CHECK: movn    w8, #:tprel_g1:var      // encoding: [0x08'A',A,0xa0'A',0x12'A']
-// CHECK-NEXT:                                 //   fixup A - offset: 0, value: :tprel_g1:var, kind: fixup_a64_movw_tprel_g1
+// CHECK-AARCH64: movz    x5, #:tprel_g1:var      // encoding: [0x05'A',A,0xa0'A',0x92'A']
+// CHECK-AARCH64-NEXT:                                 //   fixup A - offset: 0, value: :tprel_g1:var, kind: fixup_a64_movw_tprel_g1
+// CHECK-AARCH64: movn    x6, #:tprel_g1:var      // encoding: [0x06'A',A,0xa0'A',0x92'A']
+// CHECK-AARCH64-NEXT:                                 //   fixup A - offset: 0, value: :tprel_g1:var, kind: fixup_a64_movw_tprel_g1
+// CHECK-AARCH64: movz    w7, #:tprel_g1:var      // encoding: [0x07'A',A,0xa0'A',0x12'A']
+// CHECK-AARCH64-NEXT:                                 //   fixup A - offset: 0, value: :tprel_g1:var, kind: fixup_a64_movw_tprel_g1
+// CHECK-AARCH64: movn    w8, #:tprel_g1:var      // encoding: [0x08'A',A,0xa0'A',0x12'A']
+// CHECK-AARCH64-NEXT:                                 //   fixup A - offset: 0, value: :tprel_g1:var, kind: fixup_a64_movw_tprel_g1
+
+// CHECK-ARM64: movz    x5, #:tprel_g1:var      // encoding: [0bAAA00101,A,0b101AAAAA,0x92]
+// CHECK-ARM64:                                 //   fixup A - offset: 0, value: :tprel_g1:var, kind: fixup_arm64_movw
+// CHECK-ARM64: movn    x6, #:tprel_g1:var      // encoding: [0bAAA00110,A,0b101AAAAA,0x92]
+// CHECK-ARM64:                                 //   fixup A - offset: 0, value: :tprel_g1:var, kind: fixup_arm64_movw
+// CHECK-ARM64: movz    w7, #:tprel_g1:var      // encoding: [0bAAA00111,A,0b101AAAAA,0x12]
+// CHECK-ARM64:                                 //   fixup A - offset: 0, value: :tprel_g1:var, kind: fixup_arm64_movw
+// CHECK-ARM64: movn    w8, #:tprel_g1:var      // encoding: [0bAAA01000,A,0b101AAAAA,0x12]
+// CHECK-ARM64:                                 //   fixup A - offset: 0, value: :tprel_g1:var, kind: fixup_arm64_movw
 
 // CHECK-ELF-NEXT:     0x9C R_AARCH64_TLSLE_MOVW_TPREL_G1 [[VARSYM]]
 // CHECK-ELF-NEXT:     0xA0 R_AARCH64_TLSLE_MOVW_TPREL_G1 [[VARSYM]]
@@ -232,10 +338,15 @@
 
         movk x9, #:tprel_g1_nc:var
         movk w10, #:tprel_g1_nc:var
-// CHECK: movk    x9, #:tprel_g1_nc:var   // encoding: [0x09'A',A,0xa0'A',0xf2'A']
-// CHECK-NEXT:                                 //   fixup A - offset: 0, value: :tprel_g1_nc:var, kind: fixup_a64_movw_tprel_g1_nc
-// CHECK: movk    w10, #:tprel_g1_nc:var  // encoding: [0x0a'A',A,0xa0'A',0x72'A']
-// CHECK-NEXT:                                 //   fixup A - offset: 0, value: :tprel_g1_nc:var, kind: fixup_a64_movw_tprel_g1_nc
+// CHECK-AARCH64: movk    x9, #:tprel_g1_nc:var   // encoding: [0x09'A',A,0xa0'A',0xf2'A']
+// CHECK-AARCH64-NEXT:                                 //   fixup A - offset: 0, value: :tprel_g1_nc:var, kind: fixup_a64_movw_tprel_g1_nc
+// CHECK-AARCH64: movk    w10, #:tprel_g1_nc:var  // encoding: [0x0a'A',A,0xa0'A',0x72'A']
+// CHECK-AARCH64-NEXT:                                 //   fixup A - offset: 0, value: :tprel_g1_nc:var, kind: fixup_a64_movw_tprel_g1_nc
+
+// CHECK-ARM64: movk    x9, #:tprel_g1_nc:var   // encoding: [0bAAA01001,A,0b101AAAAA,0xf2]
+// CHECK-ARM64:                                 //   fixup A - offset: 0, value: :tprel_g1_nc:var, kind: fixup_arm64_movw
+// CHECK-ARM64: movk    w10, #:tprel_g1_nc:var  // encoding: [0bAAA01010,A,0b101AAAAA,0x72]
+// CHECK-ARM64:                                 //   fixup A - offset: 0, value: :tprel_g1_nc:var, kind: fixup_arm64_movw
 
 // CHECK-ELF-NEXT:     0xAC R_AARCH64_TLSLE_MOVW_TPREL_G1_NC [[VARSYM]]
 // CHECK-ELF-NEXT:     0xB0 R_AARCH64_TLSLE_MOVW_TPREL_G1_NC [[VARSYM]]
@@ -245,14 +356,23 @@
         movn x12, #:tprel_g0:var
         movz w13, #:tprel_g0:var
         movn w14, #:tprel_g0:var
-// CHECK: movz    x11, #:tprel_g0:var     // encoding: [0x0b'A',A,0x80'A',0x92'A']
-// CHECK-NEXT:                                 //   fixup A - offset: 0, value: :tprel_g0:var, kind: fixup_a64_movw_tprel_g0
-// CHECK: movn    x12, #:tprel_g0:var     // encoding: [0x0c'A',A,0x80'A',0x92'A']
-// CHECK-NEXT:                                 //   fixup A - offset: 0, value: :tprel_g0:var, kind: fixup_a64_movw_tprel_g0
-// CHECK: movz    w13, #:tprel_g0:var     // encoding: [0x0d'A',A,0x80'A',0x12'A']
-// CHECK-NEXT:                                 //   fixup A - offset: 0, value: :tprel_g0:var, kind: fixup_a64_movw_tprel_g0
-// CHECK: movn    w14, #:tprel_g0:var     // encoding: [0x0e'A',A,0x80'A',0x12'A']
-// CHECK-NEXT:                                 //   fixup A - offset: 0, value: :tprel_g0:var, kind: fixup_a64_movw_tprel_g0
+// CHECK-AARCH64: movz    x11, #:tprel_g0:var     // encoding: [0x0b'A',A,0x80'A',0x92'A']
+// CHECK-AARCH64-NEXT:                                 //   fixup A - offset: 0, value: :tprel_g0:var, kind: fixup_a64_movw_tprel_g0
+// CHECK-AARCH64: movn    x12, #:tprel_g0:var     // encoding: [0x0c'A',A,0x80'A',0x92'A']
+// CHECK-AARCH64-NEXT:                                 //   fixup A - offset: 0, value: :tprel_g0:var, kind: fixup_a64_movw_tprel_g0
+// CHECK-AARCH64: movz    w13, #:tprel_g0:var     // encoding: [0x0d'A',A,0x80'A',0x12'A']
+// CHECK-AARCH64-NEXT:                                 //   fixup A - offset: 0, value: :tprel_g0:var, kind: fixup_a64_movw_tprel_g0
+// CHECK-AARCH64: movn    w14, #:tprel_g0:var     // encoding: [0x0e'A',A,0x80'A',0x12'A']
+// CHECK-AARCH64-NEXT:                                 //   fixup A - offset: 0, value: :tprel_g0:var, kind: fixup_a64_movw_tprel_g0
+
+// CHECK-ARM64: movz    x11, #:tprel_g0:var     // encoding: [0bAAA01011,A,0b100AAAAA,0x92]
+// CHECK-ARM64:                                 //   fixup A - offset: 0, value: :tprel_g0:var, kind: fixup_arm64_movw
+// CHECK-ARM64: movn    x12, #:tprel_g0:var     // encoding: [0bAAA01100,A,0b100AAAAA,0x92]
+// CHECK-ARM64:                                 //   fixup A - offset: 0, value: :tprel_g0:var, kind: fixup_arm64_movw
+// CHECK-ARM64: movz    w13, #:tprel_g0:var     // encoding: [0bAAA01101,A,0b100AAAAA,0x12]
+// CHECK-ARM64:                                 //   fixup A - offset: 0, value: :tprel_g0:var, kind: fixup_arm64_movw
+// CHECK-ARM64: movn    w14, #:tprel_g0:var     // encoding: [0bAAA01110,A,0b100AAAAA,0x12]
+// CHECK-ARM64:                                 //   fixup A - offset: 0, value: :tprel_g0:var, kind: fixup_arm64_movw
 
 // CHECK-ELF-NEXT:     0xB4 R_AARCH64_TLSLE_MOVW_TPREL_G0 [[VARSYM]]
 // CHECK-ELF-NEXT:     0xB8 R_AARCH64_TLSLE_MOVW_TPREL_G0 [[VARSYM]]
@@ -262,10 +382,15 @@
 
         movk x15, #:tprel_g0_nc:var
         movk w16, #:tprel_g0_nc:var
-// CHECK: movk    x15, #:tprel_g0_nc:var  // encoding: [0x0f'A',A,0x80'A',0xf2'A']
-// CHECK-NEXT:                                 //   fixup A - offset: 0, value: :tprel_g0_nc:var, kind: fixup_a64_movw_tprel_g0_nc
-// CHECK: movk    w16, #:tprel_g0_nc:var  // encoding: [0x10'A',A,0x80'A',0x72'A']
-// CHECK-NEXT:                                 //   fixup A - offset: 0, value: :tprel_g0_nc:var, kind: fixup_a64_movw_tprel_g0_nc
+// CHECK-AARCH64: movk    x15, #:tprel_g0_nc:var  // encoding: [0x0f'A',A,0x80'A',0xf2'A']
+// CHECK-AARCH64-NEXT:                                 //   fixup A - offset: 0, value: :tprel_g0_nc:var, kind: fixup_a64_movw_tprel_g0_nc
+// CHECK-AARCH64: movk    w16, #:tprel_g0_nc:var  // encoding: [0x10'A',A,0x80'A',0x72'A']
+// CHECK-AARCH64-NEXT:                                 //   fixup A - offset: 0, value: :tprel_g0_nc:var, kind: fixup_a64_movw_tprel_g0_nc
+
+// CHECK-ARM64: movk    x15, #:tprel_g0_nc:var  // encoding: [0bAAA01111,A,0b100AAAAA,0xf2]
+// CHECK-ARM64:                                 //   fixup A - offset: 0, value: :tprel_g0_nc:var, kind: fixup_arm64_movw
+// CHECK-ARM64: movk    w16, #:tprel_g0_nc:var  // encoding: [0bAAA10000,A,0b100AAAAA,0x72]
+// CHECK-ARM64:                                 //   fixup A - offset: 0, value: :tprel_g0_nc:var, kind: fixup_arm64_movw
 
 // CHECK-ELF-NEXT:     0xC4 R_AARCH64_TLSLE_MOVW_TPREL_G0_NC [[VARSYM]]
 // CHECK-ELF-NEXT:     0xC8 R_AARCH64_TLSLE_MOVW_TPREL_G0_NC [[VARSYM]]
@@ -273,10 +398,15 @@
 
         add x17, x18, #:tprel_hi12:var, lsl #12
         add w19, w20, #:tprel_hi12:var, lsl #12
-// CHECK: add     x17, x18, #:tprel_hi12:var, lsl #12 // encoding: [0x51'A',0x02'A',0x40'A',0x91'A']
-// CHECK-NEXT:                                 //   fixup A - offset: 0, value: :tprel_hi12:var, kind: fixup_a64_add_tprel_hi12
-// CHECK: add     w19, w20, #:tprel_hi12:var, lsl #12 // encoding: [0x93'A',0x02'A',0x40'A',0x11'A']
-// CHECK-NEXT:                                 //   fixup A - offset: 0, value: :tprel_hi12:var, kind: fixup_a64_add_tprel_hi12
+// CHECK-AARCH64: add     x17, x18, #:tprel_hi12:var, lsl #12 // encoding: [0x51'A',0x02'A',0x40'A',0x91'A']
+// CHECK-AARCH64-NEXT:                                 //   fixup A - offset: 0, value: :tprel_hi12:var, kind: fixup_a64_add_tprel_hi12
+// CHECK-AARCH64: add     w19, w20, #:tprel_hi12:var, lsl #12 // encoding: [0x93'A',0x02'A',0x40'A',0x11'A']
+// CHECK-AARCH64-NEXT:                                 //   fixup A - offset: 0, value: :tprel_hi12:var, kind: fixup_a64_add_tprel_hi12
+
+// CHECK-ARM64: add    x17, x18, :tprel_hi12:var, lsl #12 // encoding: [0x51,0bAAAAAA10,0b00AAAAAA,0x91]
+// CHECK-ARM64:                                           //   fixup A - offset: 0, value: :tprel_hi12:var, kind: fixup_arm64_add_imm12
+// CHECK-ARM64: add    w19, w20, :tprel_hi12:var, lsl #12 // encoding: [0x93,0bAAAAAA10,0b00AAAAAA,0x11]
+// CHECK-ARM64:                                           //   fixup A - offset: 0, value: :tprel_hi12:var, kind: fixup_arm64_add_imm12
 
 // CHECK-ELF-NEXT:     0xCC R_AARCH64_TLSLE_ADD_TPREL_HI12 [[VARSYM]]
 // CHECK-ELF-NEXT:     0xD0 R_AARCH64_TLSLE_ADD_TPREL_HI12 [[VARSYM]]
@@ -284,10 +414,15 @@
 
         add x21, x22, #:tprel_lo12:var
         add w23, w24, #:tprel_lo12:var
-// CHECK: add     x21, x22, #:tprel_lo12:var // encoding: [0xd5'A',0x02'A',A,0x91'A']
-// CHECK-NEXT:                                 //   fixup A - offset: 0, value: :tprel_lo12:var, kind: fixup_a64_add_tprel_lo12
-// CHECK: add     w23, w24, #:tprel_lo12:var // encoding: [0x17'A',0x03'A',A,0x11'A']
-// CHECK-NEXT:                                 //   fixup A - offset: 0, value: :tprel_lo12:var, kind: fixup_a64_add_tprel_lo12
+// CHECK-AARCH64: add     x21, x22, #:tprel_lo12:var // encoding: [0xd5'A',0x02'A',A,0x91'A']
+// CHECK-AARCH64-NEXT:                                 //   fixup A - offset: 0, value: :tprel_lo12:var, kind: fixup_a64_add_tprel_lo12
+// CHECK-AARCH64: add     w23, w24, #:tprel_lo12:var // encoding: [0x17'A',0x03'A',A,0x11'A']
+// CHECK-AARCH64-NEXT:                                 //   fixup A - offset: 0, value: :tprel_lo12:var, kind: fixup_a64_add_tprel_lo12
+
+// CHECK-ARM64: add    x21, x22, :tprel_lo12:var // encoding: [0xd5,0bAAAAAA10,0b00AAAAAA,0x91]
+// CHECK-ARM64:                                  //   fixup A - offset: 0, value: :tprel_lo12:var, kind: fixup_arm64_add_imm12
+// CHECK-ARM64: add    w23, w24, :tprel_lo12:var // encoding: [0x17,0bAAAAAA11,0b00AAAAAA,0x11]
+// CHECK-ARM64:                                  //   fixup A - offset: 0, value: :tprel_lo12:var, kind: fixup_arm64_add_imm12
 
 // CHECK-ELF-NEXT:     0xD4 R_AARCH64_TLSLE_ADD_TPREL_LO12 [[VARSYM]]
 // CHECK-ELF-NEXT:     0xD8 R_AARCH64_TLSLE_ADD_TPREL_LO12 [[VARSYM]]
@@ -295,10 +430,15 @@
 
         add x25, x26, #:tprel_lo12_nc:var
         add w27, w28, #:tprel_lo12_nc:var
-// CHECK: add     x25, x26, #:tprel_lo12_nc:var // encoding: [0x59'A',0x03'A',A,0x91'A']
-// CHECK-NEXT:                                 //   fixup A - offset: 0, value: :tprel_lo12_nc:var, kind: fixup_a64_add_tprel_lo12_nc
-// CHECK: add     w27, w28, #:tprel_lo12_nc:var // encoding: [0x9b'A',0x03'A',A,0x11'A']
-// CHECK-NEXT:                                 //   fixup A - offset: 0, value: :tprel_lo12_nc:var, kind: fixup_a64_add_tprel_lo12_nc
+// CHECK-AARCH64: add     x25, x26, #:tprel_lo12_nc:var // encoding: [0x59'A',0x03'A',A,0x91'A']
+// CHECK-AARCH64-NEXT:                                 //   fixup A - offset: 0, value: :tprel_lo12_nc:var, kind: fixup_a64_add_tprel_lo12_nc
+// CHECK-AARCH64: add     w27, w28, #:tprel_lo12_nc:var // encoding: [0x9b'A',0x03'A',A,0x11'A']
+// CHECK-AARCH64-NEXT:                                 //   fixup A - offset: 0, value: :tprel_lo12_nc:var, kind: fixup_a64_add_tprel_lo12_nc
+
+// CHECK-ARM64: add    x25, x26, :tprel_lo12_nc:var // encoding: [0x59,0bAAAAAA11,0b00AAAAAA,0x91]
+// CHECK-ARM64:                                     //   fixup A - offset: 0, value: :tprel_lo12_nc:var, kind: fixup_arm64_add_imm12
+// CHECK-ARM64: add    w27, w28, :tprel_lo12_nc:var // encoding: [0x9b,0bAAAAAA11,0b00AAAAAA,0x11]
+// CHECK-ARM64:                                     //   fixup A - offset: 0, value: :tprel_lo12_nc:var, kind: fixup_arm64_add_imm12
 
 // CHECK-ELF-NEXT:     0xDC R_AARCH64_TLSLE_ADD_TPREL_LO12_NC [[VARSYM]]
 // CHECK-ELF-NEXT:     0xE0 R_AARCH64_TLSLE_ADD_TPREL_LO12_NC [[VARSYM]]
@@ -306,10 +446,15 @@
 
         ldrb w29, [x30, #:tprel_lo12:var]
         ldrsb x29, [x28, #:tprel_lo12_nc:var]
-// CHECK: ldrb    w29, [x30, #:tprel_lo12:var] // encoding: [0xdd'A',0x03'A',0x40'A',0x39'A']
-// CHECK-NEXT:                                 //   fixup A - offset: 0, value: :tprel_lo12:var, kind: fixup_a64_ldst8_tprel_lo12
-// CHECK: ldrsb   x29, [x28, #:tprel_lo12_nc:var] // encoding: [0x9d'A',0x03'A',0x80'A',0x39'A']
-// CHECK-NEXT:                                 //   fixup A - offset: 0, value: :tprel_lo12_nc:var, kind: fixup_a64_ldst8_tprel_lo12_nc
+// CHECK-AARCH64: ldrb    w29, [x30, #:tprel_lo12:var] // encoding: [0xdd'A',0x03'A',0x40'A',0x39'A']
+// CHECK-AARCH64-NEXT:                                 //   fixup A - offset: 0, value: :tprel_lo12:var, kind: fixup_a64_ldst8_tprel_lo12
+// CHECK-AARCH64: ldrsb   x29, [x28, #:tprel_lo12_nc:var] // encoding: [0x9d'A',0x03'A',0x80'A',0x39'A']
+// CHECK-AARCH64-NEXT:                                 //   fixup A - offset: 0, value: :tprel_lo12_nc:var, kind: fixup_a64_ldst8_tprel_lo12_nc
+
+// CHECK-ARM64: ldrb    w29, [x30, :tprel_lo12:var] // encoding: [0xdd,0bAAAAAA11,0b01AAAAAA,0x39]
+// CHECK-ARM64:                                     //   fixup A - offset: 0, value: :tprel_lo12:var, kind: fixup_arm64_ldst_imm12_scale1
+// CHECK-ARM64: ldrsb    x29, [x28, :tprel_lo12_nc:var] // encoding: [0x9d,0bAAAAAA11,0b10AAAAAA,0x39]
+// CHECK-ARM64:                                     //   fixup A - offset: 0, value: :tprel_lo12_nc:var, kind: fixup_arm64_ldst_imm12_scale1
 
 // CHECK-ELF-NEXT:     0xE4 R_AARCH64_TLSLE_LDST8_TPREL_LO12 [[VARSYM]]
 // CHECK-ELF-NEXT:     0xE8 R_AARCH64_TLSLE_LDST8_TPREL_LO12_NC [[VARSYM]]
@@ -317,10 +462,15 @@
 
         strh w27, [x26, #:tprel_lo12:var]
         ldrsh x25, [x24, #:tprel_lo12_nc:var]
-// CHECK: strh    w27, [x26, #:tprel_lo12:var] // encoding: [0x5b'A',0x03'A',A,0x79'A']
-// CHECK-NEXT:                                 //   fixup A - offset: 0, value: :tprel_lo12:var, kind: fixup_a64_ldst16_tprel_lo12
-// CHECK: ldrsh   x25, [x24, #:tprel_lo12_nc:var] // encoding: [0x19'A',0x03'A',0x80'A',0x79'A']
-// CHECK-NEXT:                                 //   fixup A - offset: 0, value: :tprel_lo12_nc:var, kind: fixup_a64_ldst16_tprel_lo12_n
+// CHECK-AARCH64: strh    w27, [x26, #:tprel_lo12:var] // encoding: [0x5b'A',0x03'A',A,0x79'A']
+// CHECK-AARCH64-NEXT:                                 //   fixup A - offset: 0, value: :tprel_lo12:var, kind: fixup_a64_ldst16_tprel_lo12
+// CHECK-AARCH64: ldrsh   x25, [x24, #:tprel_lo12_nc:var] // encoding: [0x19'A',0x03'A',0x80'A',0x79'A']
+// CHECK-AARCH64-NEXT:                                 //   fixup A - offset: 0, value: :tprel_lo12_nc:var, kind: fixup_a64_ldst16_tprel_lo12_n
+
+// CHECK-ARM64: strh    w27, [x26, :tprel_lo12:var] // encoding: [0x5b,0bAAAAAA11,0b00AAAAAA,0x79]
+// CHECK-ARM64:                                     //   fixup A - offset: 0, value: :tprel_lo12:var, kind: fixup_arm64_ldst_imm12_scale2
+// CHECK-ARM64: ldrsh    x25, [x24, :tprel_lo12_nc:var] // encoding: [0x19,0bAAAAAA11,0b10AAAAAA,0x79]
+// CHECK-ARM64:                                         //   fixup A - offset: 0, value: :tprel_lo12_nc:var, kind: fixup_arm64_ldst_imm12_scale2
 
 // CHECK-ELF-NEXT:     0xEC R_AARCH64_TLSLE_LDST16_TPREL_LO12 [[VARSYM]]
 // CHECK-ELF-NEXT:     0xF0 R_AARCH64_TLSLE_LDST16_TPREL_LO12_NC [[VARSYM]]
@@ -328,20 +478,30 @@
 
         ldr w23, [x22, #:tprel_lo12:var]
         ldrsw x21, [x20, #:tprel_lo12_nc:var]
-// CHECK: ldr     w23, [x22, #:tprel_lo12:var] // encoding: [0xd7'A',0x02'A',0x40'A',0xb9'A']
-// CHECK-NEXT:                                 //   fixup A - offset: 0, value: :tprel_lo12:var, kind: fixup_a64_ldst32_tprel_lo12
-// CHECK: ldrsw   x21, [x20, #:tprel_lo12_nc:var] // encoding: [0x95'A',0x02'A',0x80'A',0xb9'A']
-// CHECK-NEXT:                                 //   fixup A - offset: 0, value: :tprel_lo12_nc:var, kind: fixup_a64_ldst32_tprel_lo12_n
+// CHECK-AARCH64: ldr     w23, [x22, #:tprel_lo12:var] // encoding: [0xd7'A',0x02'A',0x40'A',0xb9'A']
+// CHECK-AARCH64-NEXT:                                 //   fixup A - offset: 0, value: :tprel_lo12:var, kind: fixup_a64_ldst32_tprel_lo12
+// CHECK-AARCH64: ldrsw   x21, [x20, #:tprel_lo12_nc:var] // encoding: [0x95'A',0x02'A',0x80'A',0xb9'A']
+// CHECK-AARCH64-NEXT:                                 //   fixup A - offset: 0, value: :tprel_lo12_nc:var, kind: fixup_a64_ldst32_tprel_lo12_n
+
+// CHECK-ARM64: ldr    w23, [x22, :tprel_lo12:var] // encoding: [0xd7,0bAAAAAA10,0b01AAAAAA,0xb9]
+// CHECK-ARM64:                                    //   fixup A - offset: 0, value: :tprel_lo12:var, kind: fixup_arm64_ldst_imm12_scale4
+// CHECK-ARM64: ldrsw    x21, [x20, :tprel_lo12_nc:var] // encoding: [0x95,0bAAAAAA10,0b10AAAAAA,0xb9]
+// CHECK-ARM64:                                         //   fixup A - offset: 0, value: :tprel_lo12_nc:var, kind: fixup_arm64_ldst_imm12_scale4
 
 // CHECK-ELF-NEXT:     0xF4 R_AARCH64_TLSLE_LDST32_TPREL_LO12 [[VARSYM]]
 // CHECK-ELF-NEXT:     0xF8 R_AARCH64_TLSLE_LDST32_TPREL_LO12_NC [[VARSYM]]
 
         ldr x19, [x18, #:tprel_lo12:var]
         str x17, [x16, #:tprel_lo12_nc:var]
-// CHECK: ldr     x19, [x18, #:tprel_lo12:var] // encoding: [0x53'A',0x02'A',0x40'A',0xf9'A']
-// CHECK-NEXT:                                 //   fixup A - offset: 0, value: :tprel_lo12:var, kind: fixup_a64_ldst64_tprel_lo12
-// CHECK: str     x17, [x16, #:tprel_lo12_nc:var] // encoding: [0x11'A',0x02'A',A,0xf9'A']
-// CHECK-NEXT:                                 //   fixup A - offset: 0, value: :tprel_lo12_nc:var, kind: fixup_a64_ldst64_tprel_lo12_nc
+// CHECK-AARCH64: ldr     x19, [x18, #:tprel_lo12:var] // encoding: [0x53'A',0x02'A',0x40'A',0xf9'A']
+// CHECK-AARCH64-NEXT:                                 //   fixup A - offset: 0, value: :tprel_lo12:var, kind: fixup_a64_ldst64_tprel_lo12
+// CHECK-AARCH64: str     x17, [x16, #:tprel_lo12_nc:var] // encoding: [0x11'A',0x02'A',A,0xf9'A']
+// CHECK-AARCH64-NEXT:                                 //   fixup A - offset: 0, value: :tprel_lo12_nc:var, kind: fixup_a64_ldst64_tprel_lo12_nc
+
+// CHECK-ARM64: ldr    x19, [x18, :tprel_lo12:var] // encoding: [0x53,0bAAAAAA10,0b01AAAAAA,0xf9]
+// CHECK-ARM64:                                    //   fixup A - offset: 0, value: :tprel_lo12:var, kind: fixup_arm64_ldst_imm12_scale8
+// CHECK-ARM64: str    x17, [x16, :tprel_lo12_nc:var] // encoding: [0x11,0bAAAAAA10,0b00AAAAAA,0xf9]
+// CHECK-ARM64:                                       //   fixup A - offset: 0, value: :tprel_lo12_nc:var, kind: fixup_arm64_ldst_imm12_scale8
 
 // CHECK-ELF-NEXT:     0xFC  R_AARCH64_TLSLE_LDST64_TPREL_LO12 [[VARSYM]]
 // CHECK-ELF-NEXT:     0x100 R_AARCH64_TLSLE_LDST64_TPREL_LO12_NC [[VARSYM]]
@@ -353,16 +513,25 @@
         .tlsdesccall var
         blr x3
 
-// CHECK: adrp    x8, :tlsdesc:var        // encoding: [0x08'A',A,A,0x90'A']
-// CHECK-NEXT:                                 //   fixup A - offset: 0, value: :tlsdesc:var, kind: fixup_a64_tlsdesc_adr_page
-// CHECK: ldr     x7, [x6, #:tlsdesc_lo12:var] // encoding: [0xc7'A',A,0x40'A',0xf9'A']
-// CHECK-NEXT:                                 //   fixup A - offset: 0, value: :tlsdesc_lo12:var, kind: fixup_a64_tlsdesc_ld64_lo12_nc
-// CHECK: add     x5, x4, #:tlsdesc_lo12:var // encoding: [0x85'A',A,A,0x91'A']
-// CHECK-NEXT:                                 //   fixup A - offset: 0, value: :tlsdesc_lo12:var, kind: fixup_a64_tlsdesc_add_lo12_nc
-// CHECK: .tlsdesccall var                // encoding: []
-// CHECK-NEXT:                                 //   fixup A - offset: 0, value: :tlsdesc:var, kind: fixup_a64_tlsdesc_call
-// CHECK: blr     x3                      // encoding: [0x60,0x00,0x3f,0xd6]
-
+// CHECK-AARCH64: adrp    x8, :tlsdesc:var        // encoding: [0x08'A',A,A,0x90'A']
+// CHECK-AARCH64-NEXT:                                 //   fixup A - offset: 0, value: :tlsdesc:var, kind: fixup_a64_tlsdesc_adr_page
+// CHECK-AARCH64: ldr     x7, [x6, #:tlsdesc_lo12:var] // encoding: [0xc7'A',A,0x40'A',0xf9'A']
+// CHECK-AARCH64-NEXT:                                 //   fixup A - offset: 0, value: :tlsdesc_lo12:var, kind: fixup_a64_tlsdesc_ld64_lo12_nc
+// CHECK-AARCH64: add     x5, x4, #:tlsdesc_lo12:var // encoding: [0x85'A',A,A,0x91'A']
+// CHECK-AARCH64-NEXT:                                 //   fixup A - offset: 0, value: :tlsdesc_lo12:var, kind: fixup_a64_tlsdesc_add_lo12_nc
+// CHECK-AARCH64: .tlsdesccall var                // encoding: []
+// CHECK-AARCH64-NEXT:                                 //   fixup A - offset: 0, value: :tlsdesc:var, kind: fixup_a64_tlsdesc_call
+// CHECK-AARCH64: blr     x3                      // encoding: [0x60,0x00,0x3f,0xd6]
+
+// CHECK-ARM64: adrp    x8, :tlsdesc:var        // encoding: [0x08'A',A,A,0x90'A']
+// CHECK-ARM64:                                 //   fixup A - offset: 0, value: :tlsdesc:var, kind: fixup_arm64_pcrel_adrp_imm21
+// CHECK-ARM64: ldr    x7, [x6, :tlsdesc_lo12:var] // encoding: [0xc7,0bAAAAAA00,0b01AAAAAA,0xf9]
+// CHECK-ARM64:                                    //   fixup A - offset: 0, value: :tlsdesc_lo12:var, kind: fixup_arm64_ldst_imm12_scale8
+// CHECK-ARM64: add    x5, x4, :tlsdesc_lo12:var // encoding: [0x85,0bAAAAAA00,0b00AAAAAA,0x91]
+// CHECK-ARM64:                                  //   fixup A - offset: 0, value: :tlsdesc_lo12:var, kind: fixup_arm64_add_imm12
+// CHECK-ARM64: .tlsdesccall var                // encoding: []
+// CHECK-ARM64:                                 //   fixup A - offset: 0, value: var, kind: fixup_arm64_tlsdesc_call
+// CHECK-ARM64: blr    x3                      // encoding: [0x60,0x00,0x3f,0xd6]
 
 // CHECK-ELF-NEXT:     0x104 R_AARCH64_TLSDESC_ADR_PAGE [[VARSYM]]
 // CHECK-ELF-NEXT:     0x108 R_AARCH64_TLSDESC_LD64_LO12_NC [[VARSYM]]
@@ -374,7 +543,7 @@
 
 // CHECK-ELF:      Symbols [
 // CHECK-ELF:        Symbol {
-// CHECK-ELF:          Name: var (6)
+// CHECK-ELF:          Name: var
 // CHECK-ELF-NEXT:     Value:
 // CHECK-ELF-NEXT:     Size:
 // CHECK-ELF-NEXT:     Binding: Global
diff --git a/test/MC/AArch64/trace-regs-diagnostics.s b/test/MC/AArch64/trace-regs-diagnostics.s
index 41331e7703..04f9d27735 100644
--- a/test/MC/AArch64/trace-regs-diagnostics.s
+++ b/test/MC/AArch64/trace-regs-diagnostics.s
@@ -1,4 +1,5 @@
 // RUN: not llvm-mc -triple aarch64-none-linux-gnu < %s 2>&1 | FileCheck %s
+// RUN: not llvm-mc -triple arm64-none-linux-gnu < %s 2>&1 | FileCheck %s
         // Write-only
         mrs x12, trcoslar
         mrs x10, trclar
diff --git a/test/MC/AArch64/trace-regs.s b/test/MC/AArch64/trace-regs.s
index f9ab4c9ad9..b763e67c91 100644
--- a/test/MC/AArch64/trace-regs.s
+++ b/test/MC/AArch64/trace-regs.s
@@ -1,4 +1,6 @@
 // RUN: llvm-mc -triple=aarch64-none-linux-gnu -show-encoding < %s | FileCheck %s
+// RUN: llvm-mc -triple=arm64-none-linux-gnu -show-encoding < %s | FileCheck %s
+
         mrs x8, trcstatr
         mrs x9, trcidr8
         mrs x11, trcidr9
@@ -207,214 +209,214 @@
         mrs x22, trcitctrl
         mrs x23, trcclaimset
         mrs x14, trcclaimclr
-// CHECK: mrs      x8, trcstatr               // encoding: [0x08,0x03,0x31,0xd5]
-// CHECK: mrs      x9, trcidr8                // encoding: [0xc9,0x00,0x31,0xd5]
-// CHECK: mrs      x11, trcidr9               // encoding: [0xcb,0x01,0x31,0xd5]
-// CHECK: mrs      x25, trcidr10              // encoding: [0xd9,0x02,0x31,0xd5]
-// CHECK: mrs      x7, trcidr11               // encoding: [0xc7,0x03,0x31,0xd5]
-// CHECK: mrs      x7, trcidr12               // encoding: [0xc7,0x04,0x31,0xd5]
-// CHECK: mrs      x6, trcidr13               // encoding: [0xc6,0x05,0x31,0xd5]
-// CHECK: mrs      x27, trcidr0               // encoding: [0xfb,0x08,0x31,0xd5]
-// CHECK: mrs      x29, trcidr1               // encoding: [0xfd,0x09,0x31,0xd5]
-// CHECK: mrs      x4, trcidr2                // encoding: [0xe4,0x0a,0x31,0xd5]
-// CHECK: mrs      x8, trcidr3                // encoding: [0xe8,0x0b,0x31,0xd5]
-// CHECK: mrs      x15, trcidr4               // encoding: [0xef,0x0c,0x31,0xd5]
-// CHECK: mrs      x20, trcidr5               // encoding: [0xf4,0x0d,0x31,0xd5]
-// CHECK: mrs      x6, trcidr6                // encoding: [0xe6,0x0e,0x31,0xd5]
-// CHECK: mrs      x6, trcidr7                // encoding: [0xe6,0x0f,0x31,0xd5]
-// CHECK: mrs      x24, trcoslsr              // encoding: [0x98,0x11,0x31,0xd5]
-// CHECK: mrs      x18, trcpdsr               // encoding: [0x92,0x15,0x31,0xd5]
-// CHECK: mrs      x28, trcdevaff0            // encoding: [0xdc,0x7a,0x31,0xd5]
-// CHECK: mrs      x5, trcdevaff1             // encoding: [0xc5,0x7b,0x31,0xd5]
-// CHECK: mrs      x5, trclsr                 // encoding: [0xc5,0x7d,0x31,0xd5]
-// CHECK: mrs      x11, trcauthstatus         // encoding: [0xcb,0x7e,0x31,0xd5]
-// CHECK: mrs      x13, trcdevarch            // encoding: [0xcd,0x7f,0x31,0xd5]
-// CHECK: mrs      x18, trcdevid              // encoding: [0xf2,0x72,0x31,0xd5]
-// CHECK: mrs      x22, trcdevtype            // encoding: [0xf6,0x73,0x31,0xd5]
-// CHECK: mrs      x14, trcpidr4              // encoding: [0xee,0x74,0x31,0xd5]
-// CHECK: mrs      x5, trcpidr5               // encoding: [0xe5,0x75,0x31,0xd5]
-// CHECK: mrs      x5, trcpidr6               // encoding: [0xe5,0x76,0x31,0xd5]
-// CHECK: mrs      x9, trcpidr7               // encoding: [0xe9,0x77,0x31,0xd5]
-// CHECK: mrs      x15, trcpidr0              // encoding: [0xef,0x78,0x31,0xd5]
-// CHECK: mrs      x6, trcpidr1               // encoding: [0xe6,0x79,0x31,0xd5]
-// CHECK: mrs      x11, trcpidr2              // encoding: [0xeb,0x7a,0x31,0xd5]
-// CHECK: mrs      x20, trcpidr3              // encoding: [0xf4,0x7b,0x31,0xd5]
-// CHECK: mrs      x17, trccidr0              // encoding: [0xf1,0x7c,0x31,0xd5]
-// CHECK: mrs      x2, trccidr1               // encoding: [0xe2,0x7d,0x31,0xd5]
-// CHECK: mrs      x20, trccidr2              // encoding: [0xf4,0x7e,0x31,0xd5]
-// CHECK: mrs      x4, trccidr3               // encoding: [0xe4,0x7f,0x31,0xd5]
-// CHECK: mrs      x11, trcprgctlr            // encoding: [0x0b,0x01,0x31,0xd5]
-// CHECK: mrs      x23, trcprocselr           // encoding: [0x17,0x02,0x31,0xd5]
-// CHECK: mrs      x13, trcconfigr            // encoding: [0x0d,0x04,0x31,0xd5]
-// CHECK: mrs      x23, trcauxctlr            // encoding: [0x17,0x06,0x31,0xd5]
-// CHECK: mrs      x9, trceventctl0r          // encoding: [0x09,0x08,0x31,0xd5]
-// CHECK: mrs      x16, trceventctl1r         // encoding: [0x10,0x09,0x31,0xd5]
-// CHECK: mrs      x4, trcstallctlr           // encoding: [0x04,0x0b,0x31,0xd5]
-// CHECK: mrs      x14, trctsctlr             // encoding: [0x0e,0x0c,0x31,0xd5]
-// CHECK: mrs      x24, trcsyncpr             // encoding: [0x18,0x0d,0x31,0xd5]
-// CHECK: mrs      x28, trcccctlr             // encoding: [0x1c,0x0e,0x31,0xd5]
-// CHECK: mrs      x15, trcbbctlr             // encoding: [0x0f,0x0f,0x31,0xd5]
-// CHECK: mrs      x1, trctraceidr            // encoding: [0x21,0x00,0x31,0xd5]
-// CHECK: mrs      x20, trcqctlr              // encoding: [0x34,0x01,0x31,0xd5]
-// CHECK: mrs      x2, trcvictlr              // encoding: [0x42,0x00,0x31,0xd5]
-// CHECK: mrs      x12, trcviiectlr           // encoding: [0x4c,0x01,0x31,0xd5]
-// CHECK: mrs      x16, trcvissctlr           // encoding: [0x50,0x02,0x31,0xd5]
-// CHECK: mrs      x8, trcvipcssctlr          // encoding: [0x48,0x03,0x31,0xd5]
-// CHECK: mrs      x27, trcvdctlr             // encoding: [0x5b,0x08,0x31,0xd5]
-// CHECK: mrs      x9, trcvdsacctlr           // encoding: [0x49,0x09,0x31,0xd5]
-// CHECK: mrs      x0, trcvdarcctlr           // encoding: [0x40,0x0a,0x31,0xd5]
-// CHECK: mrs      x13, trcseqevr0            // encoding: [0x8d,0x00,0x31,0xd5]
-// CHECK: mrs      x11, trcseqevr1            // encoding: [0x8b,0x01,0x31,0xd5]
-// CHECK: mrs      x26, trcseqevr2            // encoding: [0x9a,0x02,0x31,0xd5]
-// CHECK: mrs      x14, trcseqrstevr          // encoding: [0x8e,0x06,0x31,0xd5]
-// CHECK: mrs      x4, trcseqstr              // encoding: [0x84,0x07,0x31,0xd5]
-// CHECK: mrs      x17, trcextinselr          // encoding: [0x91,0x08,0x31,0xd5]
-// CHECK: mrs      x21, trccntrldvr0          // encoding: [0xb5,0x00,0x31,0xd5]
-// CHECK: mrs      x10, trccntrldvr1          // encoding: [0xaa,0x01,0x31,0xd5]
-// CHECK: mrs      x20, trccntrldvr2          // encoding: [0xb4,0x02,0x31,0xd5]
-// CHECK: mrs      x5, trccntrldvr3           // encoding: [0xa5,0x03,0x31,0xd5]
-// CHECK: mrs      x17, trccntctlr0           // encoding: [0xb1,0x04,0x31,0xd5]
-// CHECK: mrs      x1, trccntctlr1            // encoding: [0xa1,0x05,0x31,0xd5]
-// CHECK: mrs      x17, trccntctlr2           // encoding: [0xb1,0x06,0x31,0xd5]
-// CHECK: mrs      x6, trccntctlr3            // encoding: [0xa6,0x07,0x31,0xd5]
-// CHECK: mrs      x28, trccntvr0             // encoding: [0xbc,0x08,0x31,0xd5]
-// CHECK: mrs      x23, trccntvr1             // encoding: [0xb7,0x09,0x31,0xd5]
-// CHECK: mrs      x9, trccntvr2              // encoding: [0xa9,0x0a,0x31,0xd5]
-// CHECK: mrs      x6, trccntvr3              // encoding: [0xa6,0x0b,0x31,0xd5]
-// CHECK: mrs      x24, trcimspec0            // encoding: [0xf8,0x00,0x31,0xd5]
-// CHECK: mrs      x24, trcimspec1            // encoding: [0xf8,0x01,0x31,0xd5]
-// CHECK: mrs      x15, trcimspec2            // encoding: [0xef,0x02,0x31,0xd5]
-// CHECK: mrs      x10, trcimspec3            // encoding: [0xea,0x03,0x31,0xd5]
-// CHECK: mrs      x29, trcimspec4            // encoding: [0xfd,0x04,0x31,0xd5]
-// CHECK: mrs      x18, trcimspec5            // encoding: [0xf2,0x05,0x31,0xd5]
-// CHECK: mrs      x29, trcimspec6            // encoding: [0xfd,0x06,0x31,0xd5]
-// CHECK: mrs      x2, trcimspec7             // encoding: [0xe2,0x07,0x31,0xd5]
-// CHECK: mrs      x8, trcrsctlr2             // encoding: [0x08,0x12,0x31,0xd5]
-// CHECK: mrs      x0, trcrsctlr3             // encoding: [0x00,0x13,0x31,0xd5]
-// CHECK: mrs      x12, trcrsctlr4            // encoding: [0x0c,0x14,0x31,0xd5]
-// CHECK: mrs      x26, trcrsctlr5            // encoding: [0x1a,0x15,0x31,0xd5]
-// CHECK: mrs      x29, trcrsctlr6            // encoding: [0x1d,0x16,0x31,0xd5]
-// CHECK: mrs      x17, trcrsctlr7            // encoding: [0x11,0x17,0x31,0xd5]
-// CHECK: mrs      x0, trcrsctlr8             // encoding: [0x00,0x18,0x31,0xd5]
-// CHECK: mrs      x1, trcrsctlr9             // encoding: [0x01,0x19,0x31,0xd5]
-// CHECK: mrs      x17, trcrsctlr10           // encoding: [0x11,0x1a,0x31,0xd5]
-// CHECK: mrs      x21, trcrsctlr11           // encoding: [0x15,0x1b,0x31,0xd5]
-// CHECK: mrs      x1, trcrsctlr12            // encoding: [0x01,0x1c,0x31,0xd5]
-// CHECK: mrs      x8, trcrsctlr13            // encoding: [0x08,0x1d,0x31,0xd5]
-// CHECK: mrs      x24, trcrsctlr14           // encoding: [0x18,0x1e,0x31,0xd5]
-// CHECK: mrs      x0, trcrsctlr15            // encoding: [0x00,0x1f,0x31,0xd5]
-// CHECK: mrs      x2, trcrsctlr16            // encoding: [0x22,0x10,0x31,0xd5]
-// CHECK: mrs      x29, trcrsctlr17           // encoding: [0x3d,0x11,0x31,0xd5]
-// CHECK: mrs      x22, trcrsctlr18           // encoding: [0x36,0x12,0x31,0xd5]
-// CHECK: mrs      x6, trcrsctlr19            // encoding: [0x26,0x13,0x31,0xd5]
-// CHECK: mrs      x26, trcrsctlr20           // encoding: [0x3a,0x14,0x31,0xd5]
-// CHECK: mrs      x26, trcrsctlr21           // encoding: [0x3a,0x15,0x31,0xd5]
-// CHECK: mrs      x4, trcrsctlr22            // encoding: [0x24,0x16,0x31,0xd5]
-// CHECK: mrs      x12, trcrsctlr23           // encoding: [0x2c,0x17,0x31,0xd5]
-// CHECK: mrs      x1, trcrsctlr24            // encoding: [0x21,0x18,0x31,0xd5]
-// CHECK: mrs      x0, trcrsctlr25            // encoding: [0x20,0x19,0x31,0xd5]
-// CHECK: mrs      x17, trcrsctlr26           // encoding: [0x31,0x1a,0x31,0xd5]
-// CHECK: mrs      x8, trcrsctlr27            // encoding: [0x28,0x1b,0x31,0xd5]
-// CHECK: mrs      x10, trcrsctlr28           // encoding: [0x2a,0x1c,0x31,0xd5]
-// CHECK: mrs      x25, trcrsctlr29           // encoding: [0x39,0x1d,0x31,0xd5]
-// CHECK: mrs      x12, trcrsctlr30           // encoding: [0x2c,0x1e,0x31,0xd5]
-// CHECK: mrs      x11, trcrsctlr31           // encoding: [0x2b,0x1f,0x31,0xd5]
-// CHECK: mrs      x18, trcssccr0             // encoding: [0x52,0x10,0x31,0xd5]
-// CHECK: mrs      x12, trcssccr1             // encoding: [0x4c,0x11,0x31,0xd5]
-// CHECK: mrs      x3, trcssccr2              // encoding: [0x43,0x12,0x31,0xd5]
-// CHECK: mrs      x2, trcssccr3              // encoding: [0x42,0x13,0x31,0xd5]
-// CHECK: mrs      x21, trcssccr4             // encoding: [0x55,0x14,0x31,0xd5]
-// CHECK: mrs      x10, trcssccr5             // encoding: [0x4a,0x15,0x31,0xd5]
-// CHECK: mrs      x22, trcssccr6             // encoding: [0x56,0x16,0x31,0xd5]
-// CHECK: mrs      x23, trcssccr7             // encoding: [0x57,0x17,0x31,0xd5]
-// CHECK: mrs      x23, trcsscsr0             // encoding: [0x57,0x18,0x31,0xd5]
-// CHECK: mrs      x19, trcsscsr1             // encoding: [0x53,0x19,0x31,0xd5]
-// CHECK: mrs      x25, trcsscsr2             // encoding: [0x59,0x1a,0x31,0xd5]
-// CHECK: mrs      x17, trcsscsr3             // encoding: [0x51,0x1b,0x31,0xd5]
-// CHECK: mrs      x19, trcsscsr4             // encoding: [0x53,0x1c,0x31,0xd5]
-// CHECK: mrs      x11, trcsscsr5             // encoding: [0x4b,0x1d,0x31,0xd5]
-// CHECK: mrs      x5, trcsscsr6              // encoding: [0x45,0x1e,0x31,0xd5]
-// CHECK: mrs      x9, trcsscsr7              // encoding: [0x49,0x1f,0x31,0xd5]
-// CHECK: mrs      x1, trcsspcicr0            // encoding: [0x61,0x10,0x31,0xd5]
-// CHECK: mrs      x12, trcsspcicr1           // encoding: [0x6c,0x11,0x31,0xd5]
-// CHECK: mrs      x21, trcsspcicr2           // encoding: [0x75,0x12,0x31,0xd5]
-// CHECK: mrs      x11, trcsspcicr3           // encoding: [0x6b,0x13,0x31,0xd5]
-// CHECK: mrs      x3, trcsspcicr4            // encoding: [0x63,0x14,0x31,0xd5]
-// CHECK: mrs      x9, trcsspcicr5            // encoding: [0x69,0x15,0x31,0xd5]
-// CHECK: mrs      x5, trcsspcicr6            // encoding: [0x65,0x16,0x31,0xd5]
-// CHECK: mrs      x2, trcsspcicr7            // encoding: [0x62,0x17,0x31,0xd5]
-// CHECK: mrs      x26, trcpdcr               // encoding: [0x9a,0x14,0x31,0xd5]
-// CHECK: mrs      x8, trcacvr0               // encoding: [0x08,0x20,0x31,0xd5]
-// CHECK: mrs      x15, trcacvr1              // encoding: [0x0f,0x22,0x31,0xd5]
-// CHECK: mrs      x19, trcacvr2              // encoding: [0x13,0x24,0x31,0xd5]
-// CHECK: mrs      x8, trcacvr3               // encoding: [0x08,0x26,0x31,0xd5]
-// CHECK: mrs      x28, trcacvr4              // encoding: [0x1c,0x28,0x31,0xd5]
-// CHECK: mrs      x3, trcacvr5               // encoding: [0x03,0x2a,0x31,0xd5]
-// CHECK: mrs      x25, trcacvr6              // encoding: [0x19,0x2c,0x31,0xd5]
-// CHECK: mrs      x24, trcacvr7              // encoding: [0x18,0x2e,0x31,0xd5]
-// CHECK: mrs      x6, trcacvr8               // encoding: [0x26,0x20,0x31,0xd5]
-// CHECK: mrs      x3, trcacvr9               // encoding: [0x23,0x22,0x31,0xd5]
-// CHECK: mrs      x24, trcacvr10             // encoding: [0x38,0x24,0x31,0xd5]
-// CHECK: mrs      x3, trcacvr11              // encoding: [0x23,0x26,0x31,0xd5]
-// CHECK: mrs      x12, trcacvr12             // encoding: [0x2c,0x28,0x31,0xd5]
-// CHECK: mrs      x9, trcacvr13              // encoding: [0x29,0x2a,0x31,0xd5]
-// CHECK: mrs      x14, trcacvr14             // encoding: [0x2e,0x2c,0x31,0xd5]
-// CHECK: mrs      x3, trcacvr15              // encoding: [0x23,0x2e,0x31,0xd5]
-// CHECK: mrs      x21, trcacatr0             // encoding: [0x55,0x20,0x31,0xd5]
-// CHECK: mrs      x26, trcacatr1             // encoding: [0x5a,0x22,0x31,0xd5]
-// CHECK: mrs      x8, trcacatr2              // encoding: [0x48,0x24,0x31,0xd5]
-// CHECK: mrs      x22, trcacatr3             // encoding: [0x56,0x26,0x31,0xd5]
-// CHECK: mrs      x6, trcacatr4              // encoding: [0x46,0x28,0x31,0xd5]
-// CHECK: mrs      x29, trcacatr5             // encoding: [0x5d,0x2a,0x31,0xd5]
-// CHECK: mrs      x5, trcacatr6              // encoding: [0x45,0x2c,0x31,0xd5]
-// CHECK: mrs      x18, trcacatr7             // encoding: [0x52,0x2e,0x31,0xd5]
-// CHECK: mrs      x2, trcacatr8              // encoding: [0x62,0x20,0x31,0xd5]
-// CHECK: mrs      x19, trcacatr9             // encoding: [0x73,0x22,0x31,0xd5]
-// CHECK: mrs      x13, trcacatr10            // encoding: [0x6d,0x24,0x31,0xd5]
-// CHECK: mrs      x25, trcacatr11            // encoding: [0x79,0x26,0x31,0xd5]
-// CHECK: mrs      x18, trcacatr12            // encoding: [0x72,0x28,0x31,0xd5]
-// CHECK: mrs      x29, trcacatr13            // encoding: [0x7d,0x2a,0x31,0xd5]
-// CHECK: mrs      x9, trcacatr14             // encoding: [0x69,0x2c,0x31,0xd5]
-// CHECK: mrs      x18, trcacatr15            // encoding: [0x72,0x2e,0x31,0xd5]
-// CHECK: mrs      x29, trcdvcvr0             // encoding: [0x9d,0x20,0x31,0xd5]
-// CHECK: mrs      x15, trcdvcvr1             // encoding: [0x8f,0x24,0x31,0xd5]
-// CHECK: mrs      x15, trcdvcvr2             // encoding: [0x8f,0x28,0x31,0xd5]
-// CHECK: mrs      x15, trcdvcvr3             // encoding: [0x8f,0x2c,0x31,0xd5]
-// CHECK: mrs      x19, trcdvcvr4             // encoding: [0xb3,0x20,0x31,0xd5]
-// CHECK: mrs      x22, trcdvcvr5             // encoding: [0xb6,0x24,0x31,0xd5]
-// CHECK: mrs      x27, trcdvcvr6             // encoding: [0xbb,0x28,0x31,0xd5]
-// CHECK: mrs      x1, trcdvcvr7              // encoding: [0xa1,0x2c,0x31,0xd5]
-// CHECK: mrs      x29, trcdvcmr0             // encoding: [0xdd,0x20,0x31,0xd5]
-// CHECK: mrs      x9, trcdvcmr1              // encoding: [0xc9,0x24,0x31,0xd5]
-// CHECK: mrs      x1, trcdvcmr2              // encoding: [0xc1,0x28,0x31,0xd5]
-// CHECK: mrs      x2, trcdvcmr3              // encoding: [0xc2,0x2c,0x31,0xd5]
-// CHECK: mrs      x5, trcdvcmr4              // encoding: [0xe5,0x20,0x31,0xd5]
-// CHECK: mrs      x21, trcdvcmr5             // encoding: [0xf5,0x24,0x31,0xd5]
-// CHECK: mrs      x5, trcdvcmr6              // encoding: [0xe5,0x28,0x31,0xd5]
-// CHECK: mrs      x1, trcdvcmr7              // encoding: [0xe1,0x2c,0x31,0xd5]
-// CHECK: mrs      x21, trccidcvr0            // encoding: [0x15,0x30,0x31,0xd5]
-// CHECK: mrs      x24, trccidcvr1            // encoding: [0x18,0x32,0x31,0xd5]
-// CHECK: mrs      x24, trccidcvr2            // encoding: [0x18,0x34,0x31,0xd5]
-// CHECK: mrs      x12, trccidcvr3            // encoding: [0x0c,0x36,0x31,0xd5]
-// CHECK: mrs      x10, trccidcvr4            // encoding: [0x0a,0x38,0x31,0xd5]
-// CHECK: mrs      x9, trccidcvr5             // encoding: [0x09,0x3a,0x31,0xd5]
-// CHECK: mrs      x6, trccidcvr6             // encoding: [0x06,0x3c,0x31,0xd5]
-// CHECK: mrs      x20, trccidcvr7            // encoding: [0x14,0x3e,0x31,0xd5]
-// CHECK: mrs      x20, trcvmidcvr0           // encoding: [0x34,0x30,0x31,0xd5]
-// CHECK: mrs      x20, trcvmidcvr1           // encoding: [0x34,0x32,0x31,0xd5]
-// CHECK: mrs      x26, trcvmidcvr2           // encoding: [0x3a,0x34,0x31,0xd5]
-// CHECK: mrs      x1, trcvmidcvr3            // encoding: [0x21,0x36,0x31,0xd5]
-// CHECK: mrs      x14, trcvmidcvr4           // encoding: [0x2e,0x38,0x31,0xd5]
-// CHECK: mrs      x27, trcvmidcvr5           // encoding: [0x3b,0x3a,0x31,0xd5]
-// CHECK: mrs      x29, trcvmidcvr6           // encoding: [0x3d,0x3c,0x31,0xd5]
-// CHECK: mrs      x17, trcvmidcvr7           // encoding: [0x31,0x3e,0x31,0xd5]
-// CHECK: mrs      x10, trccidcctlr0          // encoding: [0x4a,0x30,0x31,0xd5]
-// CHECK: mrs      x4, trccidcctlr1           // encoding: [0x44,0x31,0x31,0xd5]
-// CHECK: mrs      x9, trcvmidcctlr0          // encoding: [0x49,0x32,0x31,0xd5]
-// CHECK: mrs      x11, trcvmidcctlr1         // encoding: [0x4b,0x33,0x31,0xd5]
-// CHECK: mrs      x22, trcitctrl             // encoding: [0x96,0x70,0x31,0xd5]
-// CHECK: mrs      x23, trcclaimset           // encoding: [0xd7,0x78,0x31,0xd5]
-// CHECK: mrs      x14, trcclaimclr           // encoding: [0xce,0x79,0x31,0xd5]
+// CHECK: mrs      x8, {{trcstatr|TRCSTATR}}               // encoding: [0x08,0x03,0x31,0xd5]
+// CHECK: mrs      x9, {{trcidr8|TRCIDR8}}                // encoding: [0xc9,0x00,0x31,0xd5]
+// CHECK: mrs      x11, {{trcidr9|TRCIDR9}}               // encoding: [0xcb,0x01,0x31,0xd5]
+// CHECK: mrs      x25, {{trcidr10|TRCIDR10}}              // encoding: [0xd9,0x02,0x31,0xd5]
+// CHECK: mrs      x7, {{trcidr11|TRCIDR11}}               // encoding: [0xc7,0x03,0x31,0xd5]
+// CHECK: mrs      x7, {{trcidr12|TRCIDR12}}               // encoding: [0xc7,0x04,0x31,0xd5]
+// CHECK: mrs      x6, {{trcidr13|TRCIDR13}}               // encoding: [0xc6,0x05,0x31,0xd5]
+// CHECK: mrs      x27, {{trcidr0|TRCIDR0}}               // encoding: [0xfb,0x08,0x31,0xd5]
+// CHECK: mrs      x29, {{trcidr1|TRCIDR1}}               // encoding: [0xfd,0x09,0x31,0xd5]
+// CHECK: mrs      x4, {{trcidr2|TRCIDR2}}                // encoding: [0xe4,0x0a,0x31,0xd5]
+// CHECK: mrs      x8, {{trcidr3|TRCIDR3}}                // encoding: [0xe8,0x0b,0x31,0xd5]
+// CHECK: mrs      x15, {{trcidr4|TRCIDR4}}               // encoding: [0xef,0x0c,0x31,0xd5]
+// CHECK: mrs      x20, {{trcidr5|TRCIDR5}}               // encoding: [0xf4,0x0d,0x31,0xd5]
+// CHECK: mrs      x6, {{trcidr6|TRCIDR6}}                // encoding: [0xe6,0x0e,0x31,0xd5]
+// CHECK: mrs      x6, {{trcidr7|TRCIDR7}}                // encoding: [0xe6,0x0f,0x31,0xd5]
+// CHECK: mrs      x24, {{trcoslsr|TRCOSLSR}}              // encoding: [0x98,0x11,0x31,0xd5]
+// CHECK: mrs      x18, {{trcpdsr|TRCPDSR}}               // encoding: [0x92,0x15,0x31,0xd5]
+// CHECK: mrs      x28, {{trcdevaff0|TRCDEVAFF0}}            // encoding: [0xdc,0x7a,0x31,0xd5]
+// CHECK: mrs      x5, {{trcdevaff1|TRCDEVAFF1}}             // encoding: [0xc5,0x7b,0x31,0xd5]
+// CHECK: mrs      x5, {{trclsr|TRCLSR}}                 // encoding: [0xc5,0x7d,0x31,0xd5]
+// CHECK: mrs      x11, {{trcauthstatus|TRCAUTHSTATUS}}         // encoding: [0xcb,0x7e,0x31,0xd5]
+// CHECK: mrs      x13, {{trcdevarch|TRCDEVARCH}}            // encoding: [0xcd,0x7f,0x31,0xd5]
+// CHECK: mrs      x18, {{trcdevid|TRCDEVID}}              // encoding: [0xf2,0x72,0x31,0xd5]
+// CHECK: mrs      x22, {{trcdevtype|TRCDEVTYPE}}            // encoding: [0xf6,0x73,0x31,0xd5]
+// CHECK: mrs      x14, {{trcpidr4|TRCPIDR4}}              // encoding: [0xee,0x74,0x31,0xd5]
+// CHECK: mrs      x5, {{trcpidr5|TRCPIDR5}}               // encoding: [0xe5,0x75,0x31,0xd5]
+// CHECK: mrs      x5, {{trcpidr6|TRCPIDR6}}               // encoding: [0xe5,0x76,0x31,0xd5]
+// CHECK: mrs      x9, {{trcpidr7|TRCPIDR7}}               // encoding: [0xe9,0x77,0x31,0xd5]
+// CHECK: mrs      x15, {{trcpidr0|TRCPIDR0}}              // encoding: [0xef,0x78,0x31,0xd5]
+// CHECK: mrs      x6, {{trcpidr1|TRCPIDR1}}               // encoding: [0xe6,0x79,0x31,0xd5]
+// CHECK: mrs      x11, {{trcpidr2|TRCPIDR2}}              // encoding: [0xeb,0x7a,0x31,0xd5]
+// CHECK: mrs      x20, {{trcpidr3|TRCPIDR3}}              // encoding: [0xf4,0x7b,0x31,0xd5]
+// CHECK: mrs      x17, {{trccidr0|TRCCIDR0}}              // encoding: [0xf1,0x7c,0x31,0xd5]
+// CHECK: mrs      x2, {{trccidr1|TRCCIDR1}}               // encoding: [0xe2,0x7d,0x31,0xd5]
+// CHECK: mrs      x20, {{trccidr2|TRCCIDR2}}              // encoding: [0xf4,0x7e,0x31,0xd5]
+// CHECK: mrs      x4, {{trccidr3|TRCCIDR3}}               // encoding: [0xe4,0x7f,0x31,0xd5]
+// CHECK: mrs      x11, {{trcprgctlr|TRCPRGCTLR}}            // encoding: [0x0b,0x01,0x31,0xd5]
+// CHECK: mrs      x23, {{trcprocselr|TRCPROCSELR}}           // encoding: [0x17,0x02,0x31,0xd5]
+// CHECK: mrs      x13, {{trcconfigr|TRCCONFIGR}}            // encoding: [0x0d,0x04,0x31,0xd5]
+// CHECK: mrs      x23, {{trcauxctlr|TRCAUXCTLR}}            // encoding: [0x17,0x06,0x31,0xd5]
+// CHECK: mrs      x9, {{trceventctl0r|TRCEVENTCTL0R}}          // encoding: [0x09,0x08,0x31,0xd5]
+// CHECK: mrs      x16, {{trceventctl1r|TRCEVENTCTL1R}}         // encoding: [0x10,0x09,0x31,0xd5]
+// CHECK: mrs      x4, {{trcstallctlr|TRCSTALLCTLR}}           // encoding: [0x04,0x0b,0x31,0xd5]
+// CHECK: mrs      x14, {{trctsctlr|TRCTSCTLR}}             // encoding: [0x0e,0x0c,0x31,0xd5]
+// CHECK: mrs      x24, {{trcsyncpr|TRCSYNCPR}}             // encoding: [0x18,0x0d,0x31,0xd5]
+// CHECK: mrs      x28, {{trcccctlr|TRCCCCTLR}}             // encoding: [0x1c,0x0e,0x31,0xd5]
+// CHECK: mrs      x15, {{trcbbctlr|TRCBBCTLR}}             // encoding: [0x0f,0x0f,0x31,0xd5]
+// CHECK: mrs      x1, {{trctraceidr|TRCTRACEIDR}}            // encoding: [0x21,0x00,0x31,0xd5]
+// CHECK: mrs      x20, {{trcqctlr|TRCQCTLR}}              // encoding: [0x34,0x01,0x31,0xd5]
+// CHECK: mrs      x2, {{trcvictlr|TRCVICTLR}}              // encoding: [0x42,0x00,0x31,0xd5]
+// CHECK: mrs      x12, {{trcviiectlr|TRCVIIECTLR}}           // encoding: [0x4c,0x01,0x31,0xd5]
+// CHECK: mrs      x16, {{trcvissctlr|TRCVISSCTLR}}           // encoding: [0x50,0x02,0x31,0xd5]
+// CHECK: mrs      x8, {{trcvipcssctlr|TRCVIPCSSCTLR}}          // encoding: [0x48,0x03,0x31,0xd5]
+// CHECK: mrs      x27, {{trcvdctlr|TRCVDCTLR}}             // encoding: [0x5b,0x08,0x31,0xd5]
+// CHECK: mrs      x9, {{trcvdsacctlr|TRCVDSACCTLR}}           // encoding: [0x49,0x09,0x31,0xd5]
+// CHECK: mrs      x0, {{trcvdarcctlr|TRCVDARCCTLR}}           // encoding: [0x40,0x0a,0x31,0xd5]
+// CHECK: mrs      x13, {{trcseqevr0|TRCSEQEVR0}}            // encoding: [0x8d,0x00,0x31,0xd5]
+// CHECK: mrs      x11, {{trcseqevr1|TRCSEQEVR1}}            // encoding: [0x8b,0x01,0x31,0xd5]
+// CHECK: mrs      x26, {{trcseqevr2|TRCSEQEVR2}}            // encoding: [0x9a,0x02,0x31,0xd5]
+// CHECK: mrs      x14, {{trcseqrstevr|TRCSEQRSTEVR}}          // encoding: [0x8e,0x06,0x31,0xd5]
+// CHECK: mrs      x4, {{trcseqstr|TRCSEQSTR}}              // encoding: [0x84,0x07,0x31,0xd5]
+// CHECK: mrs      x17, {{trcextinselr|TRCEXTINSELR}}          // encoding: [0x91,0x08,0x31,0xd5]
+// CHECK: mrs      x21, {{trccntrldvr0|TRCCNTRLDVR0}}          // encoding: [0xb5,0x00,0x31,0xd5]
+// CHECK: mrs      x10, {{trccntrldvr1|TRCCNTRLDVR1}}          // encoding: [0xaa,0x01,0x31,0xd5]
+// CHECK: mrs      x20, {{trccntrldvr2|TRCCNTRLDVR2}}          // encoding: [0xb4,0x02,0x31,0xd5]
+// CHECK: mrs      x5, {{trccntrldvr3|TRCCNTRLDVR3}}           // encoding: [0xa5,0x03,0x31,0xd5]
+// CHECK: mrs      x17, {{trccntctlr0|TRCCNTCTLR0}}           // encoding: [0xb1,0x04,0x31,0xd5]
+// CHECK: mrs      x1, {{trccntctlr1|TRCCNTCTLR1}}            // encoding: [0xa1,0x05,0x31,0xd5]
+// CHECK: mrs      x17, {{trccntctlr2|TRCCNTCTLR2}}           // encoding: [0xb1,0x06,0x31,0xd5]
+// CHECK: mrs      x6, {{trccntctlr3|TRCCNTCTLR3}}            // encoding: [0xa6,0x07,0x31,0xd5]
+// CHECK: mrs      x28, {{trccntvr0|TRCCNTVR0}}             // encoding: [0xbc,0x08,0x31,0xd5]
+// CHECK: mrs      x23, {{trccntvr1|TRCCNTVR1}}             // encoding: [0xb7,0x09,0x31,0xd5]
+// CHECK: mrs      x9, {{trccntvr2|TRCCNTVR2}}              // encoding: [0xa9,0x0a,0x31,0xd5]
+// CHECK: mrs      x6, {{trccntvr3|TRCCNTVR3}}              // encoding: [0xa6,0x0b,0x31,0xd5]
+// CHECK: mrs      x24, {{trcimspec0|TRCIMSPEC0}}            // encoding: [0xf8,0x00,0x31,0xd5]
+// CHECK: mrs      x24, {{trcimspec1|TRCIMSPEC1}}            // encoding: [0xf8,0x01,0x31,0xd5]
+// CHECK: mrs      x15, {{trcimspec2|TRCIMSPEC2}}            // encoding: [0xef,0x02,0x31,0xd5]
+// CHECK: mrs      x10, {{trcimspec3|TRCIMSPEC3}}            // encoding: [0xea,0x03,0x31,0xd5]
+// CHECK: mrs      x29, {{trcimspec4|TRCIMSPEC4}}            // encoding: [0xfd,0x04,0x31,0xd5]
+// CHECK: mrs      x18, {{trcimspec5|TRCIMSPEC5}}            // encoding: [0xf2,0x05,0x31,0xd5]
+// CHECK: mrs      x29, {{trcimspec6|TRCIMSPEC6}}            // encoding: [0xfd,0x06,0x31,0xd5]
+// CHECK: mrs      x2, {{trcimspec7|TRCIMSPEC7}}             // encoding: [0xe2,0x07,0x31,0xd5]
+// CHECK: mrs      x8, {{trcrsctlr2|TRCRSCTLR2}}             // encoding: [0x08,0x12,0x31,0xd5]
+// CHECK: mrs      x0, {{trcrsctlr3|TRCRSCTLR3}}             // encoding: [0x00,0x13,0x31,0xd5]
+// CHECK: mrs      x12, {{trcrsctlr4|TRCRSCTLR4}}            // encoding: [0x0c,0x14,0x31,0xd5]
+// CHECK: mrs      x26, {{trcrsctlr5|TRCRSCTLR5}}            // encoding: [0x1a,0x15,0x31,0xd5]
+// CHECK: mrs      x29, {{trcrsctlr6|TRCRSCTLR6}}            // encoding: [0x1d,0x16,0x31,0xd5]
+// CHECK: mrs      x17, {{trcrsctlr7|TRCRSCTLR7}}            // encoding: [0x11,0x17,0x31,0xd5]
+// CHECK: mrs      x0, {{trcrsctlr8|TRCRSCTLR8}}             // encoding: [0x00,0x18,0x31,0xd5]
+// CHECK: mrs      x1, {{trcrsctlr9|TRCRSCTLR9}}             // encoding: [0x01,0x19,0x31,0xd5]
+// CHECK: mrs      x17, {{trcrsctlr10|TRCRSCTLR10}}           // encoding: [0x11,0x1a,0x31,0xd5]
+// CHECK: mrs      x21, {{trcrsctlr11|TRCRSCTLR11}}           // encoding: [0x15,0x1b,0x31,0xd5]
+// CHECK: mrs      x1, {{trcrsctlr12|TRCRSCTLR12}}            // encoding: [0x01,0x1c,0x31,0xd5]
+// CHECK: mrs      x8, {{trcrsctlr13|TRCRSCTLR13}}            // encoding: [0x08,0x1d,0x31,0xd5]
+// CHECK: mrs      x24, {{trcrsctlr14|TRCRSCTLR14}}           // encoding: [0x18,0x1e,0x31,0xd5]
+// CHECK: mrs      x0, {{trcrsctlr15|TRCRSCTLR15}}            // encoding: [0x00,0x1f,0x31,0xd5]
+// CHECK: mrs      x2, {{trcrsctlr16|TRCRSCTLR16}}            // encoding: [0x22,0x10,0x31,0xd5]
+// CHECK: mrs      x29, {{trcrsctlr17|TRCRSCTLR17}}           // encoding: [0x3d,0x11,0x31,0xd5]
+// CHECK: mrs      x22, {{trcrsctlr18|TRCRSCTLR18}}           // encoding: [0x36,0x12,0x31,0xd5]
+// CHECK: mrs      x6, {{trcrsctlr19|TRCRSCTLR19}}            // encoding: [0x26,0x13,0x31,0xd5]
+// CHECK: mrs      x26, {{trcrsctlr20|TRCRSCTLR20}}           // encoding: [0x3a,0x14,0x31,0xd5]
+// CHECK: mrs      x26, {{trcrsctlr21|TRCRSCTLR21}}           // encoding: [0x3a,0x15,0x31,0xd5]
+// CHECK: mrs      x4, {{trcrsctlr22|TRCRSCTLR22}}            // encoding: [0x24,0x16,0x31,0xd5]
+// CHECK: mrs      x12, {{trcrsctlr23|TRCRSCTLR23}}           // encoding: [0x2c,0x17,0x31,0xd5]
+// CHECK: mrs      x1, {{trcrsctlr24|TRCRSCTLR24}}            // encoding: [0x21,0x18,0x31,0xd5]
+// CHECK: mrs      x0, {{trcrsctlr25|TRCRSCTLR25}}            // encoding: [0x20,0x19,0x31,0xd5]
+// CHECK: mrs      x17, {{trcrsctlr26|TRCRSCTLR26}}           // encoding: [0x31,0x1a,0x31,0xd5]
+// CHECK: mrs      x8, {{trcrsctlr27|TRCRSCTLR27}}            // encoding: [0x28,0x1b,0x31,0xd5]
+// CHECK: mrs      x10, {{trcrsctlr28|TRCRSCTLR28}}           // encoding: [0x2a,0x1c,0x31,0xd5]
+// CHECK: mrs      x25, {{trcrsctlr29|TRCRSCTLR29}}           // encoding: [0x39,0x1d,0x31,0xd5]
+// CHECK: mrs      x12, {{trcrsctlr30|TRCRSCTLR30}}           // encoding: [0x2c,0x1e,0x31,0xd5]
+// CHECK: mrs      x11, {{trcrsctlr31|TRCRSCTLR31}}           // encoding: [0x2b,0x1f,0x31,0xd5]
+// CHECK: mrs      x18, {{trcssccr0|TRCSSCCR0}}             // encoding: [0x52,0x10,0x31,0xd5]
+// CHECK: mrs      x12, {{trcssccr1|TRCSSCCR1}}             // encoding: [0x4c,0x11,0x31,0xd5]
+// CHECK: mrs      x3, {{trcssccr2|TRCSSCCR2}}              // encoding: [0x43,0x12,0x31,0xd5]
+// CHECK: mrs      x2, {{trcssccr3|TRCSSCCR3}}              // encoding: [0x42,0x13,0x31,0xd5]
+// CHECK: mrs      x21, {{trcssccr4|TRCSSCCR4}}             // encoding: [0x55,0x14,0x31,0xd5]
+// CHECK: mrs      x10, {{trcssccr5|TRCSSCCR5}}             // encoding: [0x4a,0x15,0x31,0xd5]
+// CHECK: mrs      x22, {{trcssccr6|TRCSSCCR6}}             // encoding: [0x56,0x16,0x31,0xd5]
+// CHECK: mrs      x23, {{trcssccr7|TRCSSCCR7}}             // encoding: [0x57,0x17,0x31,0xd5]
+// CHECK: mrs      x23, {{trcsscsr0|TRCSSCSR0}}             // encoding: [0x57,0x18,0x31,0xd5]
+// CHECK: mrs      x19, {{trcsscsr1|TRCSSCSR1}}             // encoding: [0x53,0x19,0x31,0xd5]
+// CHECK: mrs      x25, {{trcsscsr2|TRCSSCSR2}}             // encoding: [0x59,0x1a,0x31,0xd5]
+// CHECK: mrs      x17, {{trcsscsr3|TRCSSCSR3}}             // encoding: [0x51,0x1b,0x31,0xd5]
+// CHECK: mrs      x19, {{trcsscsr4|TRCSSCSR4}}             // encoding: [0x53,0x1c,0x31,0xd5]
+// CHECK: mrs      x11, {{trcsscsr5|TRCSSCSR5}}             // encoding: [0x4b,0x1d,0x31,0xd5]
+// CHECK: mrs      x5, {{trcsscsr6|TRCSSCSR6}}              // encoding: [0x45,0x1e,0x31,0xd5]
+// CHECK: mrs      x9, {{trcsscsr7|TRCSSCSR7}}              // encoding: [0x49,0x1f,0x31,0xd5]
+// CHECK: mrs      x1, {{trcsspcicr0|TRCSSPCICR0}}            // encoding: [0x61,0x10,0x31,0xd5]
+// CHECK: mrs      x12, {{trcsspcicr1|TRCSSPCICR1}}           // encoding: [0x6c,0x11,0x31,0xd5]
+// CHECK: mrs      x21, {{trcsspcicr2|TRCSSPCICR2}}           // encoding: [0x75,0x12,0x31,0xd5]
+// CHECK: mrs      x11, {{trcsspcicr3|TRCSSPCICR3}}           // encoding: [0x6b,0x13,0x31,0xd5]
+// CHECK: mrs      x3, {{trcsspcicr4|TRCSSPCICR4}}            // encoding: [0x63,0x14,0x31,0xd5]
+// CHECK: mrs      x9, {{trcsspcicr5|TRCSSPCICR5}}            // encoding: [0x69,0x15,0x31,0xd5]
+// CHECK: mrs      x5, {{trcsspcicr6|TRCSSPCICR6}}            // encoding: [0x65,0x16,0x31,0xd5]
+// CHECK: mrs      x2, {{trcsspcicr7|TRCSSPCICR7}}            // encoding: [0x62,0x17,0x31,0xd5]
+// CHECK: mrs      x26, {{trcpdcr|TRCPDCR}}               // encoding: [0x9a,0x14,0x31,0xd5]
+// CHECK: mrs      x8, {{trcacvr0|TRCACVR0}}               // encoding: [0x08,0x20,0x31,0xd5]
+// CHECK: mrs      x15, {{trcacvr1|TRCACVR1}}              // encoding: [0x0f,0x22,0x31,0xd5]
+// CHECK: mrs      x19, {{trcacvr2|TRCACVR2}}              // encoding: [0x13,0x24,0x31,0xd5]
+// CHECK: mrs      x8, {{trcacvr3|TRCACVR3}}               // encoding: [0x08,0x26,0x31,0xd5]
+// CHECK: mrs      x28, {{trcacvr4|TRCACVR4}}              // encoding: [0x1c,0x28,0x31,0xd5]
+// CHECK: mrs      x3, {{trcacvr5|TRCACVR5}}               // encoding: [0x03,0x2a,0x31,0xd5]
+// CHECK: mrs      x25, {{trcacvr6|TRCACVR6}}              // encoding: [0x19,0x2c,0x31,0xd5]
+// CHECK: mrs      x24, {{trcacvr7|TRCACVR7}}              // encoding: [0x18,0x2e,0x31,0xd5]
+// CHECK: mrs      x6, {{trcacvr8|TRCACVR8}}               // encoding: [0x26,0x20,0x31,0xd5]
+// CHECK: mrs      x3, {{trcacvr9|TRCACVR9}}               // encoding: [0x23,0x22,0x31,0xd5]
+// CHECK: mrs      x24, {{trcacvr10|TRCACVR10}}             // encoding: [0x38,0x24,0x31,0xd5]
+// CHECK: mrs      x3, {{trcacvr11|TRCACVR11}}              // encoding: [0x23,0x26,0x31,0xd5]
+// CHECK: mrs      x12, {{trcacvr12|TRCACVR12}}             // encoding: [0x2c,0x28,0x31,0xd5]
+// CHECK: mrs      x9, {{trcacvr13|TRCACVR13}}              // encoding: [0x29,0x2a,0x31,0xd5]
+// CHECK: mrs      x14, {{trcacvr14|TRCACVR14}}             // encoding: [0x2e,0x2c,0x31,0xd5]
+// CHECK: mrs      x3, {{trcacvr15|TRCACVR15}}              // encoding: [0x23,0x2e,0x31,0xd5]
+// CHECK: mrs      x21, {{trcacatr0|TRCACATR0}}             // encoding: [0x55,0x20,0x31,0xd5]
+// CHECK: mrs      x26, {{trcacatr1|TRCACATR1}}             // encoding: [0x5a,0x22,0x31,0xd5]
+// CHECK: mrs      x8, {{trcacatr2|TRCACATR2}}              // encoding: [0x48,0x24,0x31,0xd5]
+// CHECK: mrs      x22, {{trcacatr3|TRCACATR3}}             // encoding: [0x56,0x26,0x31,0xd5]
+// CHECK: mrs      x6, {{trcacatr4|TRCACATR4}}              // encoding: [0x46,0x28,0x31,0xd5]
+// CHECK: mrs      x29, {{trcacatr5|TRCACATR5}}             // encoding: [0x5d,0x2a,0x31,0xd5]
+// CHECK: mrs      x5, {{trcacatr6|TRCACATR6}}              // encoding: [0x45,0x2c,0x31,0xd5]
+// CHECK: mrs      x18, {{trcacatr7|TRCACATR7}}             // encoding: [0x52,0x2e,0x31,0xd5]
+// CHECK: mrs      x2, {{trcacatr8|TRCACATR8}}              // encoding: [0x62,0x20,0x31,0xd5]
+// CHECK: mrs      x19, {{trcacatr9|TRCACATR9}}             // encoding: [0x73,0x22,0x31,0xd5]
+// CHECK: mrs      x13, {{trcacatr10|TRCACATR10}}            // encoding: [0x6d,0x24,0x31,0xd5]
+// CHECK: mrs      x25, {{trcacatr11|TRCACATR11}}            // encoding: [0x79,0x26,0x31,0xd5]
+// CHECK: mrs      x18, {{trcacatr12|TRCACATR12}}            // encoding: [0x72,0x28,0x31,0xd5]
+// CHECK: mrs      x29, {{trcacatr13|TRCACATR13}}            // encoding: [0x7d,0x2a,0x31,0xd5]
+// CHECK: mrs      x9, {{trcacatr14|TRCACATR14}}             // encoding: [0x69,0x2c,0x31,0xd5]
+// CHECK: mrs      x18, {{trcacatr15|TRCACATR15}}            // encoding: [0x72,0x2e,0x31,0xd5]
+// CHECK: mrs      x29, {{trcdvcvr0|TRCDVCVR0}}             // encoding: [0x9d,0x20,0x31,0xd5]
+// CHECK: mrs      x15, {{trcdvcvr1|TRCDVCVR1}}             // encoding: [0x8f,0x24,0x31,0xd5]
+// CHECK: mrs      x15, {{trcdvcvr2|TRCDVCVR2}}             // encoding: [0x8f,0x28,0x31,0xd5]
+// CHECK: mrs      x15, {{trcdvcvr3|TRCDVCVR3}}             // encoding: [0x8f,0x2c,0x31,0xd5]
+// CHECK: mrs      x19, {{trcdvcvr4|TRCDVCVR4}}             // encoding: [0xb3,0x20,0x31,0xd5]
+// CHECK: mrs      x22, {{trcdvcvr5|TRCDVCVR5}}             // encoding: [0xb6,0x24,0x31,0xd5]
+// CHECK: mrs      x27, {{trcdvcvr6|TRCDVCVR6}}             // encoding: [0xbb,0x28,0x31,0xd5]
+// CHECK: mrs      x1, {{trcdvcvr7|TRCDVCVR7}}              // encoding: [0xa1,0x2c,0x31,0xd5]
+// CHECK: mrs      x29, {{trcdvcmr0|TRCDVCMR0}}             // encoding: [0xdd,0x20,0x31,0xd5]
+// CHECK: mrs      x9, {{trcdvcmr1|TRCDVCMR1}}              // encoding: [0xc9,0x24,0x31,0xd5]
+// CHECK: mrs      x1, {{trcdvcmr2|TRCDVCMR2}}              // encoding: [0xc1,0x28,0x31,0xd5]
+// CHECK: mrs      x2, {{trcdvcmr3|TRCDVCMR3}}              // encoding: [0xc2,0x2c,0x31,0xd5]
+// CHECK: mrs      x5, {{trcdvcmr4|TRCDVCMR4}}              // encoding: [0xe5,0x20,0x31,0xd5]
+// CHECK: mrs      x21, {{trcdvcmr5|TRCDVCMR5}}             // encoding: [0xf5,0x24,0x31,0xd5]
+// CHECK: mrs      x5, {{trcdvcmr6|TRCDVCMR6}}              // encoding: [0xe5,0x28,0x31,0xd5]
+// CHECK: mrs      x1, {{trcdvcmr7|TRCDVCMR7}}              // encoding: [0xe1,0x2c,0x31,0xd5]
+// CHECK: mrs      x21, {{trccidcvr0|TRCCIDCVR0}}            // encoding: [0x15,0x30,0x31,0xd5]
+// CHECK: mrs      x24, {{trccidcvr1|TRCCIDCVR1}}            // encoding: [0x18,0x32,0x31,0xd5]
+// CHECK: mrs      x24, {{trccidcvr2|TRCCIDCVR2}}            // encoding: [0x18,0x34,0x31,0xd5]
+// CHECK: mrs      x12, {{trccidcvr3|TRCCIDCVR3}}            // encoding: [0x0c,0x36,0x31,0xd5]
+// CHECK: mrs      x10, {{trccidcvr4|TRCCIDCVR4}}            // encoding: [0x0a,0x38,0x31,0xd5]
+// CHECK: mrs      x9, {{trccidcvr5|TRCCIDCVR5}}             // encoding: [0x09,0x3a,0x31,0xd5]
+// CHECK: mrs      x6, {{trccidcvr6|TRCCIDCVR6}}             // encoding: [0x06,0x3c,0x31,0xd5]
+// CHECK: mrs      x20, {{trccidcvr7|TRCCIDCVR7}}            // encoding: [0x14,0x3e,0x31,0xd5]
+// CHECK: mrs      x20, {{trcvmidcvr0|TRCVMIDCVR0}}           // encoding: [0x34,0x30,0x31,0xd5]
+// CHECK: mrs      x20, {{trcvmidcvr1|TRCVMIDCVR1}}           // encoding: [0x34,0x32,0x31,0xd5]
+// CHECK: mrs      x26, {{trcvmidcvr2|TRCVMIDCVR2}}           // encoding: [0x3a,0x34,0x31,0xd5]
+// CHECK: mrs      x1, {{trcvmidcvr3|TRCVMIDCVR3}}            // encoding: [0x21,0x36,0x31,0xd5]
+// CHECK: mrs      x14, {{trcvmidcvr4|TRCVMIDCVR4}}           // encoding: [0x2e,0x38,0x31,0xd5]
+// CHECK: mrs      x27, {{trcvmidcvr5|TRCVMIDCVR5}}           // encoding: [0x3b,0x3a,0x31,0xd5]
+// CHECK: mrs      x29, {{trcvmidcvr6|TRCVMIDCVR6}}           // encoding: [0x3d,0x3c,0x31,0xd5]
+// CHECK: mrs      x17, {{trcvmidcvr7|TRCVMIDCVR7}}           // encoding: [0x31,0x3e,0x31,0xd5]
+// CHECK: mrs      x10, {{trccidcctlr0|TRCCIDCCTLR0}}          // encoding: [0x4a,0x30,0x31,0xd5]
+// CHECK: mrs      x4, {{trccidcctlr1|TRCCIDCCTLR1}}           // encoding: [0x44,0x31,0x31,0xd5]
+// CHECK: mrs      x9, {{trcvmidcctlr0|TRCVMIDCCTLR0}}          // encoding: [0x49,0x32,0x31,0xd5]
+// CHECK: mrs      x11, {{trcvmidcctlr1|TRCVMIDCCTLR1}}         // encoding: [0x4b,0x33,0x31,0xd5]
+// CHECK: mrs      x22, {{trcitctrl|TRCITCTRL}}             // encoding: [0x96,0x70,0x31,0xd5]
+// CHECK: mrs      x23, {{trcclaimset|TRCCLAIMSET}}           // encoding: [0xd7,0x78,0x31,0xd5]
+// CHECK: mrs      x14, {{trcclaimclr|TRCCLAIMCLR}}           // encoding: [0xce,0x79,0x31,0xd5]
 
         msr trcoslar, x28
         msr trclar, x14
@@ -590,177 +592,177 @@
         msr trcitctrl, x1
         msr trcclaimset, x7
         msr trcclaimclr, x29
-// CHECK: msr      trcoslar, x28              // encoding: [0x9c,0x10,0x11,0xd5]
-// CHECK: msr      trclar, x14                // encoding: [0xce,0x7c,0x11,0xd5]
-// CHECK: msr      trcprgctlr, x10            // encoding: [0x0a,0x01,0x11,0xd5]
-// CHECK: msr      trcprocselr, x27           // encoding: [0x1b,0x02,0x11,0xd5]
-// CHECK: msr      trcconfigr, x24            // encoding: [0x18,0x04,0x11,0xd5]
-// CHECK: msr      trcauxctlr, x8             // encoding: [0x08,0x06,0x11,0xd5]
-// CHECK: msr      trceventctl0r, x16         // encoding: [0x10,0x08,0x11,0xd5]
-// CHECK: msr      trceventctl1r, x27         // encoding: [0x1b,0x09,0x11,0xd5]
-// CHECK: msr      trcstallctlr, x26          // encoding: [0x1a,0x0b,0x11,0xd5]
-// CHECK: msr      trctsctlr, x0              // encoding: [0x00,0x0c,0x11,0xd5]
-// CHECK: msr      trcsyncpr, x14             // encoding: [0x0e,0x0d,0x11,0xd5]
-// CHECK: msr      trcccctlr, x8              // encoding: [0x08,0x0e,0x11,0xd5]
-// CHECK: msr      trcbbctlr, x6              // encoding: [0x06,0x0f,0x11,0xd5]
-// CHECK: msr      trctraceidr, x23           // encoding: [0x37,0x00,0x11,0xd5]
-// CHECK: msr      trcqctlr, x5               // encoding: [0x25,0x01,0x11,0xd5]
-// CHECK: msr      trcvictlr, x0              // encoding: [0x40,0x00,0x11,0xd5]
-// CHECK: msr      trcviiectlr, x0            // encoding: [0x40,0x01,0x11,0xd5]
-// CHECK: msr      trcvissctlr, x1            // encoding: [0x41,0x02,0x11,0xd5]
-// CHECK: msr      trcvipcssctlr, x0          // encoding: [0x40,0x03,0x11,0xd5]
-// CHECK: msr      trcvdctlr, x7              // encoding: [0x47,0x08,0x11,0xd5]
-// CHECK: msr      trcvdsacctlr, x18          // encoding: [0x52,0x09,0x11,0xd5]
-// CHECK: msr      trcvdarcctlr, x24          // encoding: [0x58,0x0a,0x11,0xd5]
-// CHECK: msr      trcseqevr0, x28            // encoding: [0x9c,0x00,0x11,0xd5]
-// CHECK: msr      trcseqevr1, x21            // encoding: [0x95,0x01,0x11,0xd5]
-// CHECK: msr      trcseqevr2, x16            // encoding: [0x90,0x02,0x11,0xd5]
-// CHECK: msr      trcseqrstevr, x16          // encoding: [0x90,0x06,0x11,0xd5]
-// CHECK: msr      trcseqstr, x25             // encoding: [0x99,0x07,0x11,0xd5]
-// CHECK: msr      trcextinselr, x29          // encoding: [0x9d,0x08,0x11,0xd5]
-// CHECK: msr      trccntrldvr0, x20          // encoding: [0xb4,0x00,0x11,0xd5]
-// CHECK: msr      trccntrldvr1, x20          // encoding: [0xb4,0x01,0x11,0xd5]
-// CHECK: msr      trccntrldvr2, x22          // encoding: [0xb6,0x02,0x11,0xd5]
-// CHECK: msr      trccntrldvr3, x12          // encoding: [0xac,0x03,0x11,0xd5]
-// CHECK: msr      trccntctlr0, x20           // encoding: [0xb4,0x04,0x11,0xd5]
-// CHECK: msr      trccntctlr1, x4            // encoding: [0xa4,0x05,0x11,0xd5]
-// CHECK: msr      trccntctlr2, x8            // encoding: [0xa8,0x06,0x11,0xd5]
-// CHECK: msr      trccntctlr3, x16           // encoding: [0xb0,0x07,0x11,0xd5]
-// CHECK: msr      trccntvr0, x5              // encoding: [0xa5,0x08,0x11,0xd5]
-// CHECK: msr      trccntvr1, x27             // encoding: [0xbb,0x09,0x11,0xd5]
-// CHECK: msr      trccntvr2, x21             // encoding: [0xb5,0x0a,0x11,0xd5]
-// CHECK: msr      trccntvr3, x8              // encoding: [0xa8,0x0b,0x11,0xd5]
-// CHECK: msr      trcimspec0, x6             // encoding: [0xe6,0x00,0x11,0xd5]
-// CHECK: msr      trcimspec1, x27            // encoding: [0xfb,0x01,0x11,0xd5]
-// CHECK: msr      trcimspec2, x23            // encoding: [0xf7,0x02,0x11,0xd5]
-// CHECK: msr      trcimspec3, x15            // encoding: [0xef,0x03,0x11,0xd5]
-// CHECK: msr      trcimspec4, x13            // encoding: [0xed,0x04,0x11,0xd5]
-// CHECK: msr      trcimspec5, x25            // encoding: [0xf9,0x05,0x11,0xd5]
-// CHECK: msr      trcimspec6, x19            // encoding: [0xf3,0x06,0x11,0xd5]
-// CHECK: msr      trcimspec7, x27            // encoding: [0xfb,0x07,0x11,0xd5]
-// CHECK: msr      trcrsctlr2, x4             // encoding: [0x04,0x12,0x11,0xd5]
-// CHECK: msr      trcrsctlr3, x0             // encoding: [0x00,0x13,0x11,0xd5]
-// CHECK: msr      trcrsctlr4, x21            // encoding: [0x15,0x14,0x11,0xd5]
-// CHECK: msr      trcrsctlr5, x8             // encoding: [0x08,0x15,0x11,0xd5]
-// CHECK: msr      trcrsctlr6, x20            // encoding: [0x14,0x16,0x11,0xd5]
-// CHECK: msr      trcrsctlr7, x11            // encoding: [0x0b,0x17,0x11,0xd5]
-// CHECK: msr      trcrsctlr8, x18            // encoding: [0x12,0x18,0x11,0xd5]
-// CHECK: msr      trcrsctlr9, x24            // encoding: [0x18,0x19,0x11,0xd5]
-// CHECK: msr      trcrsctlr10, x15           // encoding: [0x0f,0x1a,0x11,0xd5]
-// CHECK: msr      trcrsctlr11, x21           // encoding: [0x15,0x1b,0x11,0xd5]
-// CHECK: msr      trcrsctlr12, x4            // encoding: [0x04,0x1c,0x11,0xd5]
-// CHECK: msr      trcrsctlr13, x28           // encoding: [0x1c,0x1d,0x11,0xd5]
-// CHECK: msr      trcrsctlr14, x3            // encoding: [0x03,0x1e,0x11,0xd5]
-// CHECK: msr      trcrsctlr15, x20           // encoding: [0x14,0x1f,0x11,0xd5]
-// CHECK: msr      trcrsctlr16, x12           // encoding: [0x2c,0x10,0x11,0xd5]
-// CHECK: msr      trcrsctlr17, x17           // encoding: [0x31,0x11,0x11,0xd5]
-// CHECK: msr      trcrsctlr18, x10           // encoding: [0x2a,0x12,0x11,0xd5]
-// CHECK: msr      trcrsctlr19, x11           // encoding: [0x2b,0x13,0x11,0xd5]
-// CHECK: msr      trcrsctlr20, x3            // encoding: [0x23,0x14,0x11,0xd5]
-// CHECK: msr      trcrsctlr21, x18           // encoding: [0x32,0x15,0x11,0xd5]
-// CHECK: msr      trcrsctlr22, x26           // encoding: [0x3a,0x16,0x11,0xd5]
-// CHECK: msr      trcrsctlr23, x5            // encoding: [0x25,0x17,0x11,0xd5]
-// CHECK: msr      trcrsctlr24, x25           // encoding: [0x39,0x18,0x11,0xd5]
-// CHECK: msr      trcrsctlr25, x5            // encoding: [0x25,0x19,0x11,0xd5]
-// CHECK: msr      trcrsctlr26, x4            // encoding: [0x24,0x1a,0x11,0xd5]
-// CHECK: msr      trcrsctlr27, x20           // encoding: [0x34,0x1b,0x11,0xd5]
-// CHECK: msr      trcrsctlr28, x5            // encoding: [0x25,0x1c,0x11,0xd5]
-// CHECK: msr      trcrsctlr29, x10           // encoding: [0x2a,0x1d,0x11,0xd5]
-// CHECK: msr      trcrsctlr30, x24           // encoding: [0x38,0x1e,0x11,0xd5]
-// CHECK: msr      trcrsctlr31, x20           // encoding: [0x34,0x1f,0x11,0xd5]
-// CHECK: msr      trcssccr0, x23             // encoding: [0x57,0x10,0x11,0xd5]
-// CHECK: msr      trcssccr1, x27             // encoding: [0x5b,0x11,0x11,0xd5]
-// CHECK: msr      trcssccr2, x27             // encoding: [0x5b,0x12,0x11,0xd5]
-// CHECK: msr      trcssccr3, x6              // encoding: [0x46,0x13,0x11,0xd5]
-// CHECK: msr      trcssccr4, x3              // encoding: [0x43,0x14,0x11,0xd5]
-// CHECK: msr      trcssccr5, x12             // encoding: [0x4c,0x15,0x11,0xd5]
-// CHECK: msr      trcssccr6, x7              // encoding: [0x47,0x16,0x11,0xd5]
-// CHECK: msr      trcssccr7, x6              // encoding: [0x46,0x17,0x11,0xd5]
-// CHECK: msr      trcsscsr0, x20             // encoding: [0x54,0x18,0x11,0xd5]
-// CHECK: msr      trcsscsr1, x17             // encoding: [0x51,0x19,0x11,0xd5]
-// CHECK: msr      trcsscsr2, x11             // encoding: [0x4b,0x1a,0x11,0xd5]
-// CHECK: msr      trcsscsr3, x4              // encoding: [0x44,0x1b,0x11,0xd5]
-// CHECK: msr      trcsscsr4, x14             // encoding: [0x4e,0x1c,0x11,0xd5]
-// CHECK: msr      trcsscsr5, x22             // encoding: [0x56,0x1d,0x11,0xd5]
-// CHECK: msr      trcsscsr6, x3              // encoding: [0x43,0x1e,0x11,0xd5]
-// CHECK: msr      trcsscsr7, x11             // encoding: [0x4b,0x1f,0x11,0xd5]
-// CHECK: msr      trcsspcicr0, x2            // encoding: [0x62,0x10,0x11,0xd5]
-// CHECK: msr      trcsspcicr1, x3            // encoding: [0x63,0x11,0x11,0xd5]
-// CHECK: msr      trcsspcicr2, x5            // encoding: [0x65,0x12,0x11,0xd5]
-// CHECK: msr      trcsspcicr3, x7            // encoding: [0x67,0x13,0x11,0xd5]
-// CHECK: msr      trcsspcicr4, x11           // encoding: [0x6b,0x14,0x11,0xd5]
-// CHECK: msr      trcsspcicr5, x13           // encoding: [0x6d,0x15,0x11,0xd5]
-// CHECK: msr      trcsspcicr6, x17           // encoding: [0x71,0x16,0x11,0xd5]
-// CHECK: msr      trcsspcicr7, x23           // encoding: [0x77,0x17,0x11,0xd5]
-// CHECK: msr      trcpdcr, x3                // encoding: [0x83,0x14,0x11,0xd5]
-// CHECK: msr      trcacvr0, x6               // encoding: [0x06,0x20,0x11,0xd5]
-// CHECK: msr      trcacvr1, x20              // encoding: [0x14,0x22,0x11,0xd5]
-// CHECK: msr      trcacvr2, x25              // encoding: [0x19,0x24,0x11,0xd5]
-// CHECK: msr      trcacvr3, x1               // encoding: [0x01,0x26,0x11,0xd5]
-// CHECK: msr      trcacvr4, x28              // encoding: [0x1c,0x28,0x11,0xd5]
-// CHECK: msr      trcacvr5, x15              // encoding: [0x0f,0x2a,0x11,0xd5]
-// CHECK: msr      trcacvr6, x25              // encoding: [0x19,0x2c,0x11,0xd5]
-// CHECK: msr      trcacvr7, x12              // encoding: [0x0c,0x2e,0x11,0xd5]
-// CHECK: msr      trcacvr8, x5               // encoding: [0x25,0x20,0x11,0xd5]
-// CHECK: msr      trcacvr9, x25              // encoding: [0x39,0x22,0x11,0xd5]
-// CHECK: msr      trcacvr10, x13             // encoding: [0x2d,0x24,0x11,0xd5]
-// CHECK: msr      trcacvr11, x10             // encoding: [0x2a,0x26,0x11,0xd5]
-// CHECK: msr      trcacvr12, x19             // encoding: [0x33,0x28,0x11,0xd5]
-// CHECK: msr      trcacvr13, x10             // encoding: [0x2a,0x2a,0x11,0xd5]
-// CHECK: msr      trcacvr14, x19             // encoding: [0x33,0x2c,0x11,0xd5]
-// CHECK: msr      trcacvr15, x2              // encoding: [0x22,0x2e,0x11,0xd5]
-// CHECK: msr      trcacatr0, x15             // encoding: [0x4f,0x20,0x11,0xd5]
-// CHECK: msr      trcacatr1, x13             // encoding: [0x4d,0x22,0x11,0xd5]
-// CHECK: msr      trcacatr2, x8              // encoding: [0x48,0x24,0x11,0xd5]
-// CHECK: msr      trcacatr3, x1              // encoding: [0x41,0x26,0x11,0xd5]
-// CHECK: msr      trcacatr4, x11             // encoding: [0x4b,0x28,0x11,0xd5]
-// CHECK: msr      trcacatr5, x8              // encoding: [0x48,0x2a,0x11,0xd5]
-// CHECK: msr      trcacatr6, x24             // encoding: [0x58,0x2c,0x11,0xd5]
-// CHECK: msr      trcacatr7, x6              // encoding: [0x46,0x2e,0x11,0xd5]
-// CHECK: msr      trcacatr8, x23             // encoding: [0x77,0x20,0x11,0xd5]
-// CHECK: msr      trcacatr9, x5              // encoding: [0x65,0x22,0x11,0xd5]
-// CHECK: msr      trcacatr10, x11            // encoding: [0x6b,0x24,0x11,0xd5]
-// CHECK: msr      trcacatr11, x11            // encoding: [0x6b,0x26,0x11,0xd5]
-// CHECK: msr      trcacatr12, x3             // encoding: [0x63,0x28,0x11,0xd5]
-// CHECK: msr      trcacatr13, x28            // encoding: [0x7c,0x2a,0x11,0xd5]
-// CHECK: msr      trcacatr14, x25            // encoding: [0x79,0x2c,0x11,0xd5]
-// CHECK: msr      trcacatr15, x4             // encoding: [0x64,0x2e,0x11,0xd5]
-// CHECK: msr      trcdvcvr0, x6              // encoding: [0x86,0x20,0x11,0xd5]
-// CHECK: msr      trcdvcvr1, x3              // encoding: [0x83,0x24,0x11,0xd5]
-// CHECK: msr      trcdvcvr2, x5              // encoding: [0x85,0x28,0x11,0xd5]
-// CHECK: msr      trcdvcvr3, x11             // encoding: [0x8b,0x2c,0x11,0xd5]
-// CHECK: msr      trcdvcvr4, x9              // encoding: [0xa9,0x20,0x11,0xd5]
-// CHECK: msr      trcdvcvr5, x14             // encoding: [0xae,0x24,0x11,0xd5]
-// CHECK: msr      trcdvcvr6, x10             // encoding: [0xaa,0x28,0x11,0xd5]
-// CHECK: msr      trcdvcvr7, x12             // encoding: [0xac,0x2c,0x11,0xd5]
-// CHECK: msr      trcdvcmr0, x8              // encoding: [0xc8,0x20,0x11,0xd5]
-// CHECK: msr      trcdvcmr1, x8              // encoding: [0xc8,0x24,0x11,0xd5]
-// CHECK: msr      trcdvcmr2, x22             // encoding: [0xd6,0x28,0x11,0xd5]
-// CHECK: msr      trcdvcmr3, x22             // encoding: [0xd6,0x2c,0x11,0xd5]
-// CHECK: msr      trcdvcmr4, x5              // encoding: [0xe5,0x20,0x11,0xd5]
-// CHECK: msr      trcdvcmr5, x16             // encoding: [0xf0,0x24,0x11,0xd5]
-// CHECK: msr      trcdvcmr6, x27             // encoding: [0xfb,0x28,0x11,0xd5]
-// CHECK: msr      trcdvcmr7, x21             // encoding: [0xf5,0x2c,0x11,0xd5]
-// CHECK: msr      trccidcvr0, x8             // encoding: [0x08,0x30,0x11,0xd5]
-// CHECK: msr      trccidcvr1, x6             // encoding: [0x06,0x32,0x11,0xd5]
-// CHECK: msr      trccidcvr2, x9             // encoding: [0x09,0x34,0x11,0xd5]
-// CHECK: msr      trccidcvr3, x8             // encoding: [0x08,0x36,0x11,0xd5]
-// CHECK: msr      trccidcvr4, x3             // encoding: [0x03,0x38,0x11,0xd5]
-// CHECK: msr      trccidcvr5, x21            // encoding: [0x15,0x3a,0x11,0xd5]
-// CHECK: msr      trccidcvr6, x12            // encoding: [0x0c,0x3c,0x11,0xd5]
-// CHECK: msr      trccidcvr7, x7             // encoding: [0x07,0x3e,0x11,0xd5]
-// CHECK: msr      trcvmidcvr0, x4            // encoding: [0x24,0x30,0x11,0xd5]
-// CHECK: msr      trcvmidcvr1, x3            // encoding: [0x23,0x32,0x11,0xd5]
-// CHECK: msr      trcvmidcvr2, x9            // encoding: [0x29,0x34,0x11,0xd5]
-// CHECK: msr      trcvmidcvr3, x17           // encoding: [0x31,0x36,0x11,0xd5]
-// CHECK: msr      trcvmidcvr4, x14           // encoding: [0x2e,0x38,0x11,0xd5]
-// CHECK: msr      trcvmidcvr5, x12           // encoding: [0x2c,0x3a,0x11,0xd5]
-// CHECK: msr      trcvmidcvr6, x10           // encoding: [0x2a,0x3c,0x11,0xd5]
-// CHECK: msr      trcvmidcvr7, x3            // encoding: [0x23,0x3e,0x11,0xd5]
-// CHECK: msr      trccidcctlr0, x14          // encoding: [0x4e,0x30,0x11,0xd5]
-// CHECK: msr      trccidcctlr1, x22          // encoding: [0x56,0x31,0x11,0xd5]
-// CHECK: msr      trcvmidcctlr0, x8          // encoding: [0x48,0x32,0x11,0xd5]
-// CHECK: msr      trcvmidcctlr1, x15         // encoding: [0x4f,0x33,0x11,0xd5]
-// CHECK: msr      trcitctrl, x1              // encoding: [0x81,0x70,0x11,0xd5]
-// CHECK: msr      trcclaimset, x7            // encoding: [0xc7,0x78,0x11,0xd5]
-// CHECK: msr      trcclaimclr, x29           // encoding: [0xdd,0x79,0x11,0xd5]
+// CHECK: msr      {{trcoslar|TRCOSLAR}}, x28              // encoding: [0x9c,0x10,0x11,0xd5]
+// CHECK: msr      {{trclar|TRCLAR}}, x14                // encoding: [0xce,0x7c,0x11,0xd5]
+// CHECK: msr      {{trcprgctlr|TRCPRGCTLR}}, x10            // encoding: [0x0a,0x01,0x11,0xd5]
+// CHECK: msr      {{trcprocselr|TRCPROCSELR}}, x27           // encoding: [0x1b,0x02,0x11,0xd5]
+// CHECK: msr      {{trcconfigr|TRCCONFIGR}}, x24            // encoding: [0x18,0x04,0x11,0xd5]
+// CHECK: msr      {{trcauxctlr|TRCAUXCTLR}}, x8             // encoding: [0x08,0x06,0x11,0xd5]
+// CHECK: msr      {{trceventctl0r|TRCEVENTCTL0R}}, x16         // encoding: [0x10,0x08,0x11,0xd5]
+// CHECK: msr      {{trceventctl1r|TRCEVENTCTL1R}}, x27         // encoding: [0x1b,0x09,0x11,0xd5]
+// CHECK: msr      {{trcstallctlr|TRCSTALLCTLR}}, x26          // encoding: [0x1a,0x0b,0x11,0xd5]
+// CHECK: msr      {{trctsctlr|TRCTSCTLR}}, x0              // encoding: [0x00,0x0c,0x11,0xd5]
+// CHECK: msr      {{trcsyncpr|TRCSYNCPR}}, x14             // encoding: [0x0e,0x0d,0x11,0xd5]
+// CHECK: msr      {{trcccctlr|TRCCCCTLR}}, x8              // encoding: [0x08,0x0e,0x11,0xd5]
+// CHECK: msr      {{trcbbctlr|TRCBBCTLR}}, x6              // encoding: [0x06,0x0f,0x11,0xd5]
+// CHECK: msr      {{trctraceidr|TRCTRACEIDR}}, x23           // encoding: [0x37,0x00,0x11,0xd5]
+// CHECK: msr      {{trcqctlr|TRCQCTLR}}, x5               // encoding: [0x25,0x01,0x11,0xd5]
+// CHECK: msr      {{trcvictlr|TRCVICTLR}}, x0              // encoding: [0x40,0x00,0x11,0xd5]
+// CHECK: msr      {{trcviiectlr|TRCVIIECTLR}}, x0            // encoding: [0x40,0x01,0x11,0xd5]
+// CHECK: msr      {{trcvissctlr|TRCVISSCTLR}}, x1            // encoding: [0x41,0x02,0x11,0xd5]
+// CHECK: msr      {{trcvipcssctlr|TRCVIPCSSCTLR}}, x0          // encoding: [0x40,0x03,0x11,0xd5]
+// CHECK: msr      {{trcvdctlr|TRCVDCTLR}}, x7              // encoding: [0x47,0x08,0x11,0xd5]
+// CHECK: msr      {{trcvdsacctlr|TRCVDSACCTLR}}, x18          // encoding: [0x52,0x09,0x11,0xd5]
+// CHECK: msr      {{trcvdarcctlr|TRCVDARCCTLR}}, x24          // encoding: [0x58,0x0a,0x11,0xd5]
+// CHECK: msr      {{trcseqevr0|TRCSEQEVR0}}, x28            // encoding: [0x9c,0x00,0x11,0xd5]
+// CHECK: msr      {{trcseqevr1|TRCSEQEVR1}}, x21            // encoding: [0x95,0x01,0x11,0xd5]
+// CHECK: msr      {{trcseqevr2|TRCSEQEVR2}}, x16            // encoding: [0x90,0x02,0x11,0xd5]
+// CHECK: msr      {{trcseqrstevr|TRCSEQRSTEVR}}, x16          // encoding: [0x90,0x06,0x11,0xd5]
+// CHECK: msr      {{trcseqstr|TRCSEQSTR}}, x25             // encoding: [0x99,0x07,0x11,0xd5]
+// CHECK: msr      {{trcextinselr|TRCEXTINSELR}}, x29          // encoding: [0x9d,0x08,0x11,0xd5]
+// CHECK: msr      {{trccntrldvr0|TRCCNTRLDVR0}}, x20          // encoding: [0xb4,0x00,0x11,0xd5]
+// CHECK: msr      {{trccntrldvr1|TRCCNTRLDVR1}}, x20          // encoding: [0xb4,0x01,0x11,0xd5]
+// CHECK: msr      {{trccntrldvr2|TRCCNTRLDVR2}}, x22          // encoding: [0xb6,0x02,0x11,0xd5]
+// CHECK: msr      {{trccntrldvr3|TRCCNTRLDVR3}}, x12          // encoding: [0xac,0x03,0x11,0xd5]
+// CHECK: msr      {{trccntctlr0|TRCCNTCTLR0}}, x20           // encoding: [0xb4,0x04,0x11,0xd5]
+// CHECK: msr      {{trccntctlr1|TRCCNTCTLR1}}, x4            // encoding: [0xa4,0x05,0x11,0xd5]
+// CHECK: msr      {{trccntctlr2|TRCCNTCTLR2}}, x8            // encoding: [0xa8,0x06,0x11,0xd5]
+// CHECK: msr      {{trccntctlr3|TRCCNTCTLR3}}, x16           // encoding: [0xb0,0x07,0x11,0xd5]
+// CHECK: msr      {{trccntvr0|TRCCNTVR0}}, x5              // encoding: [0xa5,0x08,0x11,0xd5]
+// CHECK: msr      {{trccntvr1|TRCCNTVR1}}, x27             // encoding: [0xbb,0x09,0x11,0xd5]
+// CHECK: msr      {{trccntvr2|TRCCNTVR2}}, x21             // encoding: [0xb5,0x0a,0x11,0xd5]
+// CHECK: msr      {{trccntvr3|TRCCNTVR3}}, x8              // encoding: [0xa8,0x0b,0x11,0xd5]
+// CHECK: msr      {{trcimspec0|TRCIMSPEC0}}, x6             // encoding: [0xe6,0x00,0x11,0xd5]
+// CHECK: msr      {{trcimspec1|TRCIMSPEC1}}, x27            // encoding: [0xfb,0x01,0x11,0xd5]
+// CHECK: msr      {{trcimspec2|TRCIMSPEC2}}, x23            // encoding: [0xf7,0x02,0x11,0xd5]
+// CHECK: msr      {{trcimspec3|TRCIMSPEC3}}, x15            // encoding: [0xef,0x03,0x11,0xd5]
+// CHECK: msr      {{trcimspec4|TRCIMSPEC4}}, x13            // encoding: [0xed,0x04,0x11,0xd5]
+// CHECK: msr      {{trcimspec5|TRCIMSPEC5}}, x25            // encoding: [0xf9,0x05,0x11,0xd5]
+// CHECK: msr      {{trcimspec6|TRCIMSPEC6}}, x19            // encoding: [0xf3,0x06,0x11,0xd5]
+// CHECK: msr      {{trcimspec7|TRCIMSPEC7}}, x27            // encoding: [0xfb,0x07,0x11,0xd5]
+// CHECK: msr      {{trcrsctlr2|TRCRSCTLR2}}, x4             // encoding: [0x04,0x12,0x11,0xd5]
+// CHECK: msr      {{trcrsctlr3|TRCRSCTLR3}}, x0             // encoding: [0x00,0x13,0x11,0xd5]
+// CHECK: msr      {{trcrsctlr4|TRCRSCTLR4}}, x21            // encoding: [0x15,0x14,0x11,0xd5]
+// CHECK: msr      {{trcrsctlr5|TRCRSCTLR5}}, x8             // encoding: [0x08,0x15,0x11,0xd5]
+// CHECK: msr      {{trcrsctlr6|TRCRSCTLR6}}, x20            // encoding: [0x14,0x16,0x11,0xd5]
+// CHECK: msr      {{trcrsctlr7|TRCRSCTLR7}}, x11            // encoding: [0x0b,0x17,0x11,0xd5]
+// CHECK: msr      {{trcrsctlr8|TRCRSCTLR8}}, x18            // encoding: [0x12,0x18,0x11,0xd5]
+// CHECK: msr      {{trcrsctlr9|TRCRSCTLR9}}, x24            // encoding: [0x18,0x19,0x11,0xd5]
+// CHECK: msr      {{trcrsctlr10|TRCRSCTLR10}}, x15           // encoding: [0x0f,0x1a,0x11,0xd5]
+// CHECK: msr      {{trcrsctlr11|TRCRSCTLR11}}, x21           // encoding: [0x15,0x1b,0x11,0xd5]
+// CHECK: msr      {{trcrsctlr12|TRCRSCTLR12}}, x4            // encoding: [0x04,0x1c,0x11,0xd5]
+// CHECK: msr      {{trcrsctlr13|TRCRSCTLR13}}, x28           // encoding: [0x1c,0x1d,0x11,0xd5]
+// CHECK: msr      {{trcrsctlr14|TRCRSCTLR14}}, x3            // encoding: [0x03,0x1e,0x11,0xd5]
+// CHECK: msr      {{trcrsctlr15|TRCRSCTLR15}}, x20           // encoding: [0x14,0x1f,0x11,0xd5]
+// CHECK: msr      {{trcrsctlr16|TRCRSCTLR16}}, x12           // encoding: [0x2c,0x10,0x11,0xd5]
+// CHECK: msr      {{trcrsctlr17|TRCRSCTLR17}}, x17           // encoding: [0x31,0x11,0x11,0xd5]
+// CHECK: msr      {{trcrsctlr18|TRCRSCTLR18}}, x10           // encoding: [0x2a,0x12,0x11,0xd5]
+// CHECK: msr      {{trcrsctlr19|TRCRSCTLR19}}, x11           // encoding: [0x2b,0x13,0x11,0xd5]
+// CHECK: msr      {{trcrsctlr20|TRCRSCTLR20}}, x3            // encoding: [0x23,0x14,0x11,0xd5]
+// CHECK: msr      {{trcrsctlr21|TRCRSCTLR21}}, x18           // encoding: [0x32,0x15,0x11,0xd5]
+// CHECK: msr      {{trcrsctlr22|TRCRSCTLR22}}, x26           // encoding: [0x3a,0x16,0x11,0xd5]
+// CHECK: msr      {{trcrsctlr23|TRCRSCTLR23}}, x5            // encoding: [0x25,0x17,0x11,0xd5]
+// CHECK: msr      {{trcrsctlr24|TRCRSCTLR24}}, x25           // encoding: [0x39,0x18,0x11,0xd5]
+// CHECK: msr      {{trcrsctlr25|TRCRSCTLR25}}, x5            // encoding: [0x25,0x19,0x11,0xd5]
+// CHECK: msr      {{trcrsctlr26|TRCRSCTLR26}}, x4            // encoding: [0x24,0x1a,0x11,0xd5]
+// CHECK: msr      {{trcrsctlr27|TRCRSCTLR27}}, x20           // encoding: [0x34,0x1b,0x11,0xd5]
+// CHECK: msr      {{trcrsctlr28|TRCRSCTLR28}}, x5            // encoding: [0x25,0x1c,0x11,0xd5]
+// CHECK: msr      {{trcrsctlr29|TRCRSCTLR29}}, x10           // encoding: [0x2a,0x1d,0x11,0xd5]
+// CHECK: msr      {{trcrsctlr30|TRCRSCTLR30}}, x24           // encoding: [0x38,0x1e,0x11,0xd5]
+// CHECK: msr      {{trcrsctlr31|TRCRSCTLR31}}, x20           // encoding: [0x34,0x1f,0x11,0xd5]
+// CHECK: msr      {{trcssccr0|TRCSSCCR0}}, x23             // encoding: [0x57,0x10,0x11,0xd5]
+// CHECK: msr      {{trcssccr1|TRCSSCCR1}}, x27             // encoding: [0x5b,0x11,0x11,0xd5]
+// CHECK: msr      {{trcssccr2|TRCSSCCR2}}, x27             // encoding: [0x5b,0x12,0x11,0xd5]
+// CHECK: msr      {{trcssccr3|TRCSSCCR3}}, x6              // encoding: [0x46,0x13,0x11,0xd5]
+// CHECK: msr      {{trcssccr4|TRCSSCCR4}}, x3              // encoding: [0x43,0x14,0x11,0xd5]
+// CHECK: msr      {{trcssccr5|TRCSSCCR5}}, x12             // encoding: [0x4c,0x15,0x11,0xd5]
+// CHECK: msr      {{trcssccr6|TRCSSCCR6}}, x7              // encoding: [0x47,0x16,0x11,0xd5]
+// CHECK: msr      {{trcssccr7|TRCSSCCR7}}, x6              // encoding: [0x46,0x17,0x11,0xd5]
+// CHECK: msr      {{trcsscsr0|TRCSSCSR0}}, x20             // encoding: [0x54,0x18,0x11,0xd5]
+// CHECK: msr      {{trcsscsr1|TRCSSCSR1}}, x17             // encoding: [0x51,0x19,0x11,0xd5]
+// CHECK: msr      {{trcsscsr2|TRCSSCSR2}}, x11             // encoding: [0x4b,0x1a,0x11,0xd5]
+// CHECK: msr      {{trcsscsr3|TRCSSCSR3}}, x4              // encoding: [0x44,0x1b,0x11,0xd5]
+// CHECK: msr      {{trcsscsr4|TRCSSCSR4}}, x14             // encoding: [0x4e,0x1c,0x11,0xd5]
+// CHECK: msr      {{trcsscsr5|TRCSSCSR5}}, x22             // encoding: [0x56,0x1d,0x11,0xd5]
+// CHECK: msr      {{trcsscsr6|TRCSSCSR6}}, x3              // encoding: [0x43,0x1e,0x11,0xd5]
+// CHECK: msr      {{trcsscsr7|TRCSSCSR7}}, x11             // encoding: [0x4b,0x1f,0x11,0xd5]
+// CHECK: msr      {{trcsspcicr0|TRCSSPCICR0}}, x2            // encoding: [0x62,0x10,0x11,0xd5]
+// CHECK: msr      {{trcsspcicr1|TRCSSPCICR1}}, x3            // encoding: [0x63,0x11,0x11,0xd5]
+// CHECK: msr      {{trcsspcicr2|TRCSSPCICR2}}, x5            // encoding: [0x65,0x12,0x11,0xd5]
+// CHECK: msr      {{trcsspcicr3|TRCSSPCICR3}}, x7            // encoding: [0x67,0x13,0x11,0xd5]
+// CHECK: msr      {{trcsspcicr4|TRCSSPCICR4}}, x11           // encoding: [0x6b,0x14,0x11,0xd5]
+// CHECK: msr      {{trcsspcicr5|TRCSSPCICR5}}, x13           // encoding: [0x6d,0x15,0x11,0xd5]
+// CHECK: msr      {{trcsspcicr6|TRCSSPCICR6}}, x17           // encoding: [0x71,0x16,0x11,0xd5]
+// CHECK: msr      {{trcsspcicr7|TRCSSPCICR7}}, x23           // encoding: [0x77,0x17,0x11,0xd5]
+// CHECK: msr      {{trcpdcr|TRCPDCR}}, x3                // encoding: [0x83,0x14,0x11,0xd5]
+// CHECK: msr      {{trcacvr0|TRCACVR0}}, x6               // encoding: [0x06,0x20,0x11,0xd5]
+// CHECK: msr      {{trcacvr1|TRCACVR1}}, x20              // encoding: [0x14,0x22,0x11,0xd5]
+// CHECK: msr      {{trcacvr2|TRCACVR2}}, x25              // encoding: [0x19,0x24,0x11,0xd5]
+// CHECK: msr      {{trcacvr3|TRCACVR3}}, x1               // encoding: [0x01,0x26,0x11,0xd5]
+// CHECK: msr      {{trcacvr4|TRCACVR4}}, x28              // encoding: [0x1c,0x28,0x11,0xd5]
+// CHECK: msr      {{trcacvr5|TRCACVR5}}, x15              // encoding: [0x0f,0x2a,0x11,0xd5]
+// CHECK: msr      {{trcacvr6|TRCACVR6}}, x25              // encoding: [0x19,0x2c,0x11,0xd5]
+// CHECK: msr      {{trcacvr7|TRCACVR7}}, x12              // encoding: [0x0c,0x2e,0x11,0xd5]
+// CHECK: msr      {{trcacvr8|TRCACVR8}}, x5               // encoding: [0x25,0x20,0x11,0xd5]
+// CHECK: msr      {{trcacvr9|TRCACVR9}}, x25              // encoding: [0x39,0x22,0x11,0xd5]
+// CHECK: msr      {{trcacvr10|TRCACVR10}}, x13             // encoding: [0x2d,0x24,0x11,0xd5]
+// CHECK: msr      {{trcacvr11|TRCACVR11}}, x10             // encoding: [0x2a,0x26,0x11,0xd5]
+// CHECK: msr      {{trcacvr12|TRCACVR12}}, x19             // encoding: [0x33,0x28,0x11,0xd5]
+// CHECK: msr      {{trcacvr13|TRCACVR13}}, x10             // encoding: [0x2a,0x2a,0x11,0xd5]
+// CHECK: msr      {{trcacvr14|TRCACVR14}}, x19             // encoding: [0x33,0x2c,0x11,0xd5]
+// CHECK: msr      {{trcacvr15|TRCACVR15}}, x2              // encoding: [0x22,0x2e,0x11,0xd5]
+// CHECK: msr      {{trcacatr0|TRCACATR0}}, x15             // encoding: [0x4f,0x20,0x11,0xd5]
+// CHECK: msr      {{trcacatr1|TRCACATR1}}, x13             // encoding: [0x4d,0x22,0x11,0xd5]
+// CHECK: msr      {{trcacatr2|TRCACATR2}}, x8              // encoding: [0x48,0x24,0x11,0xd5]
+// CHECK: msr      {{trcacatr3|TRCACATR3}}, x1              // encoding: [0x41,0x26,0x11,0xd5]
+// CHECK: msr      {{trcacatr4|TRCACATR4}}, x11             // encoding: [0x4b,0x28,0x11,0xd5]
+// CHECK: msr      {{trcacatr5|TRCACATR5}}, x8              // encoding: [0x48,0x2a,0x11,0xd5]
+// CHECK: msr      {{trcacatr6|TRCACATR6}}, x24             // encoding: [0x58,0x2c,0x11,0xd5]
+// CHECK: msr      {{trcacatr7|TRCACATR7}}, x6              // encoding: [0x46,0x2e,0x11,0xd5]
+// CHECK: msr      {{trcacatr8|TRCACATR8}}, x23             // encoding: [0x77,0x20,0x11,0xd5]
+// CHECK: msr      {{trcacatr9|TRCACATR9}}, x5              // encoding: [0x65,0x22,0x11,0xd5]
+// CHECK: msr      {{trcacatr10|TRCACATR10}}, x11            // encoding: [0x6b,0x24,0x11,0xd5]
+// CHECK: msr      {{trcacatr11|TRCACATR11}}, x11            // encoding: [0x6b,0x26,0x11,0xd5]
+// CHECK: msr      {{trcacatr12|TRCACATR12}}, x3             // encoding: [0x63,0x28,0x11,0xd5]
+// CHECK: msr      {{trcacatr13|TRCACATR13}}, x28            // encoding: [0x7c,0x2a,0x11,0xd5]
+// CHECK: msr      {{trcacatr14|TRCACATR14}}, x25            // encoding: [0x79,0x2c,0x11,0xd5]
+// CHECK: msr      {{trcacatr15|TRCACATR15}}, x4             // encoding: [0x64,0x2e,0x11,0xd5]
+// CHECK: msr      {{trcdvcvr0|TRCDVCVR0}}, x6              // encoding: [0x86,0x20,0x11,0xd5]
+// CHECK: msr      {{trcdvcvr1|TRCDVCVR1}}, x3              // encoding: [0x83,0x24,0x11,0xd5]
+// CHECK: msr      {{trcdvcvr2|TRCDVCVR2}}, x5              // encoding: [0x85,0x28,0x11,0xd5]
+// CHECK: msr      {{trcdvcvr3|TRCDVCVR3}}, x11             // encoding: [0x8b,0x2c,0x11,0xd5]
+// CHECK: msr      {{trcdvcvr4|TRCDVCVR4}}, x9              // encoding: [0xa9,0x20,0x11,0xd5]
+// CHECK: msr      {{trcdvcvr5|TRCDVCVR5}}, x14             // encoding: [0xae,0x24,0x11,0xd5]
+// CHECK: msr      {{trcdvcvr6|TRCDVCVR6}}, x10             // encoding: [0xaa,0x28,0x11,0xd5]
+// CHECK: msr      {{trcdvcvr7|TRCDVCVR7}}, x12             // encoding: [0xac,0x2c,0x11,0xd5]
+// CHECK: msr      {{trcdvcmr0|TRCDVCMR0}}, x8              // encoding: [0xc8,0x20,0x11,0xd5]
+// CHECK: msr      {{trcdvcmr1|TRCDVCMR1}}, x8              // encoding: [0xc8,0x24,0x11,0xd5]
+// CHECK: msr      {{trcdvcmr2|TRCDVCMR2}}, x22             // encoding: [0xd6,0x28,0x11,0xd5]
+// CHECK: msr      {{trcdvcmr3|TRCDVCMR3}}, x22             // encoding: [0xd6,0x2c,0x11,0xd5]
+// CHECK: msr      {{trcdvcmr4|TRCDVCMR4}}, x5              // encoding: [0xe5,0x20,0x11,0xd5]
+// CHECK: msr      {{trcdvcmr5|TRCDVCMR5}}, x16             // encoding: [0xf0,0x24,0x11,0xd5]
+// CHECK: msr      {{trcdvcmr6|TRCDVCMR6}}, x27             // encoding: [0xfb,0x28,0x11,0xd5]
+// CHECK: msr      {{trcdvcmr7|TRCDVCMR7}}, x21             // encoding: [0xf5,0x2c,0x11,0xd5]
+// CHECK: msr      {{trccidcvr0|TRCCIDCVR0}}, x8             // encoding: [0x08,0x30,0x11,0xd5]
+// CHECK: msr      {{trccidcvr1|TRCCIDCVR1}}, x6             // encoding: [0x06,0x32,0x11,0xd5]
+// CHECK: msr      {{trccidcvr2|TRCCIDCVR2}}, x9             // encoding: [0x09,0x34,0x11,0xd5]
+// CHECK: msr      {{trccidcvr3|TRCCIDCVR3}}, x8             // encoding: [0x08,0x36,0x11,0xd5]
+// CHECK: msr      {{trccidcvr4|TRCCIDCVR4}}, x3             // encoding: [0x03,0x38,0x11,0xd5]
+// CHECK: msr      {{trccidcvr5|TRCCIDCVR5}}, x21            // encoding: [0x15,0x3a,0x11,0xd5]
+// CHECK: msr      {{trccidcvr6|TRCCIDCVR6}}, x12            // encoding: [0x0c,0x3c,0x11,0xd5]
+// CHECK: msr      {{trccidcvr7|TRCCIDCVR7}}, x7             // encoding: [0x07,0x3e,0x11,0xd5]
+// CHECK: msr      {{trcvmidcvr0|TRCVMIDCVR0}}, x4            // encoding: [0x24,0x30,0x11,0xd5]
+// CHECK: msr      {{trcvmidcvr1|TRCVMIDCVR1}}, x3            // encoding: [0x23,0x32,0x11,0xd5]
+// CHECK: msr      {{trcvmidcvr2|TRCVMIDCVR2}}, x9            // encoding: [0x29,0x34,0x11,0xd5]
+// CHECK: msr      {{trcvmidcvr3|TRCVMIDCVR3}}, x17           // encoding: [0x31,0x36,0x11,0xd5]
+// CHECK: msr      {{trcvmidcvr4|TRCVMIDCVR4}}, x14           // encoding: [0x2e,0x38,0x11,0xd5]
+// CHECK: msr      {{trcvmidcvr5|TRCVMIDCVR5}}, x12           // encoding: [0x2c,0x3a,0x11,0xd5]
+// CHECK: msr      {{trcvmidcvr6|TRCVMIDCVR6}}, x10           // encoding: [0x2a,0x3c,0x11,0xd5]
+// CHECK: msr      {{trcvmidcvr7|TRCVMIDCVR7}}, x3            // encoding: [0x23,0x3e,0x11,0xd5]
+// CHECK: msr      {{trccidcctlr0|TRCCIDCCTLR0}}, x14          // encoding: [0x4e,0x30,0x11,0xd5]
+// CHECK: msr      {{trccidcctlr1|TRCCIDCCTLR1}}, x22          // encoding: [0x56,0x31,0x11,0xd5]
+// CHECK: msr      {{trcvmidcctlr0|TRCVMIDCCTLR0}}, x8          // encoding: [0x48,0x32,0x11,0xd5]
+// CHECK: msr      {{trcvmidcctlr1|TRCVMIDCCTLR1}}, x15         // encoding: [0x4f,0x33,0x11,0xd5]
+// CHECK: msr      {{trcitctrl|TRCITCTRL}}, x1              // encoding: [0x81,0x70,0x11,0xd5]
+// CHECK: msr      {{trcclaimset|TRCCLAIMSET}}, x7            // encoding: [0xc7,0x78,0x11,0xd5]
+// CHECK: msr      {{trcclaimclr|TRCCLAIMCLR}}, x29           // encoding: [0xdd,0x79,0x11,0xd5]
diff --git a/test/MC/ARM/coff-function-type-info.ll b/test/MC/ARM/coff-function-type-info.ll
new file mode 100644
index 0000000000..a9f7c186b6
--- /dev/null
+++ b/test/MC/ARM/coff-function-type-info.ll
@@ -0,0 +1,45 @@
+; RUN: llc -mtriple thumbv7-windows-itanium -filetype asm -o - %s \
+; RUN:    | FileCheck %s -check-prefix CHECK-ASM
+
+; RUN: llc -mtriple thumbv7-windows-itanium -filetype obj -o - %s \
+; RUN:    | llvm-readobj -t | FileCheck %s -check-prefix CHECK-OBJECT
+
+define arm_aapcs_vfpcc void @external() {
+entry:
+  ret void
+}
+
+; CHECK-ASM: .def external
+; CHECK-ASM:   .scl 2
+; CHECK-ASM:   .type 32
+; CHECK-ASM: .endef
+; CHECK-ASM: .globl external
+
+define internal arm_aapcs_vfpcc void @internal() {
+entry:
+  ret void
+}
+
+; CHECK-ASM: .def internal
+; CHECK-ASM:    .scl 3
+; CHECK-ASM:    .type 32
+; CHECK-ASM: .endef
+; CHECK-ASM-NOT: .globl internal
+
+; CHECK-OBJECT: Symbol {
+; CHECK-OBJECT:   Name: external
+; CHECK-OBJECT:   Section: .text
+; CHECK-OBJECT:   BaseType: Null
+; CHECK-OBJECT:   ComplexType: Function
+; CHECK-OBJECT:   StorageClass: External
+; CHECK-OBJECT:   AuxSymbolCount: 0
+; CHECK-OBJECT: }
+; CHECK-OBJECT: Symbol {
+; CHECK-OBJECT:   Name: internal
+; CHECK-OBJECT:   Section: .text
+; CHECK-OBJECT:   BaseType: Null
+; CHECK-OBJECT:   ComplexType: Function
+; CHECK-OBJECT:   StorageClass: Static
+; CHECK-OBJECT:   AuxSymbolCount: 0
+; CHECK-OBJECT: }
+
diff --git a/test/MC/ARM/symbol-variants.s b/test/MC/ARM/symbol-variants.s
index e1036a33e3..a10fe5029e 100644
--- a/test/MC/ARM/symbol-variants.s
+++ b/test/MC/ARM/symbol-variants.s
@@ -2,6 +2,7 @@
 @ RUN: llvm-mc < %s -triple thumbv7-none-linux-gnueabi -filetype=obj  | llvm-objdump -triple thumbv7-none-linux-gnueabi -r - | FileCheck %s --check-prefix=CHECK --check-prefix=THUMB
 
 @ CHECK-LABEL: RELOCATION RECORDS FOR [.rel.text]
+.Lsym:
 
 @ empty
 .word f00
@@ -83,3 +84,8 @@ bl f05(plt)
 @ CHECK: 60 R_ARM_TLS_GOTDESC f24
 @ CHECK: 64 R_ARM_TLS_GOTDESC f25
 
+@ got_prel
+.word	f26(GOT_PREL) + (. - .Lsym)
+	ldr r3, =f27(GOT_PREL)
+@ CHECK: 68 R_ARM_GOT_PREL f26
+@ CHECK: 70 R_ARM_GOT_PREL f27
diff --git a/test/MC/ARM/thumb_set.s b/test/MC/ARM/thumb_set.s
index 650e1e5f40..ac4bd32889 100644
--- a/test/MC/ARM/thumb_set.s
+++ b/test/MC/ARM/thumb_set.s
@@ -14,6 +14,9 @@ arm_func:
 
 	.thumb_set alias_arm_func, arm_func
 
+        alias_arm_func2 = alias_arm_func
+        alias_arm_func3 = alias_arm_func2
+
 @ ASM: .thumb_set alias_arm_func, arm_func
 
 	.thumb
@@ -65,6 +68,18 @@ beta:
 @ CHECK: }
 
 @ CHECK: Symbol {
+@ CHECK:   Name: alias_arm_func2
+@ CHECK:   Value: 0x1
+@ CHECK:   Type: Function
+@ CHECK: }
+
+@ CHECK: Symbol {
+@ CHECK:   Name: alias_arm_func3
+@ CHECK:   Value: 0x1
+@ CHECK:   Type: Function
+@ CHECK: }
+
+@ CHECK: Symbol {
 @ CHECK:   Name: alias_defined_data
 @ CHECK:   Value: 0x5
 @ CHECK:   Type: Function
diff --git a/test/MC/ARM64/advsimd.s b/test/MC/ARM64/advsimd.s
index bd1924e4cd..bf8f3efb06 100644
--- a/test/MC/ARM64/advsimd.s
+++ b/test/MC/ARM64/advsimd.s
@@ -608,11 +608,11 @@ foo:
 ; CHECK: cmgt.8b	v0, v0, #0              ; encoding: [0x00,0x88,0x20,0x0e]
 ; CHECK: cmle.8b	v0, v0, #0              ; encoding: [0x00,0x98,0x20,0x2e]
 ; CHECK: cmlt.8b	v0, v0, #0              ; encoding: [0x00,0xa8,0x20,0x0e]
-; CHECK: fcmeq.2s	v0, v0, #0      ; encoding: [0x00,0xd8,0xa0,0x0e]
-; CHECK: fcmge.2s	v0, v0, #0      ; encoding: [0x00,0xc8,0xa0,0x2e]
-; CHECK: fcmgt.2s	v0, v0, #0      ; encoding: [0x00,0xc8,0xa0,0x0e]
-; CHECK: fcmle.2s	v0, v0, #0      ; encoding: [0x00,0xd8,0xa0,0x2e]
-; CHECK: fcmlt.2s	v0, v0, #0      ; encoding: [0x00,0xe8,0xa0,0x0e]
+; CHECK: fcmeq.2s	v0, v0, #0.0      ; encoding: [0x00,0xd8,0xa0,0x0e]
+; CHECK: fcmge.2s	v0, v0, #0.0      ; encoding: [0x00,0xc8,0xa0,0x2e]
+; CHECK: fcmgt.2s	v0, v0, #0.0      ; encoding: [0x00,0xc8,0xa0,0x0e]
+; CHECK: fcmle.2s	v0, v0, #0.0      ; encoding: [0x00,0xd8,0xa0,0x2e]
+; CHECK: fcmlt.2s	v0, v0, #0.0      ; encoding: [0x00,0xe8,0xa0,0x0e]
 ; CHECK: cmlt.8b	v8, v14, #0             ; encoding: [0xc8,0xa9,0x20,0x0e]
 ; CHECK: cmlt.16b	v8, v14, #0     ; encoding: [0xc8,0xa9,0x20,0x4e]
 ; CHECK: cmlt.4h	v8, v14, #0             ; encoding: [0xc8,0xa9,0x60,0x0e]
@@ -780,19 +780,19 @@ foo:
   bic.2s  v0, #1, lsl #16
   bic.2s  v0, #1, lsl #24
 
-; CHECK: bic.2s v0, #1               ; encoding: [0x20,0x14,0x00,0x2f]
-; CHECK: bic.2s v0, #1               ; encoding: [0x20,0x14,0x00,0x2f]
-; CHECK: bic.2s v0, #1, lsl #8       ; encoding: [0x20,0x34,0x00,0x2f]
-; CHECK: bic.2s v0, #1, lsl #16      ; encoding: [0x20,0x54,0x00,0x2f]
-; CHECK: bic.2s v0, #1, lsl #24      ; encoding: [0x20,0x74,0x00,0x2f]
+; CHECK: bic.2s v0, #0x1               ; encoding: [0x20,0x14,0x00,0x2f]
+; CHECK: bic.2s v0, #0x1               ; encoding: [0x20,0x14,0x00,0x2f]
+; CHECK: bic.2s v0, #0x1, lsl #8       ; encoding: [0x20,0x34,0x00,0x2f]
+; CHECK: bic.2s v0, #0x1, lsl #16      ; encoding: [0x20,0x54,0x00,0x2f]
+; CHECK: bic.2s v0, #0x1, lsl #24      ; encoding: [0x20,0x74,0x00,0x2f]
 
   bic.4h  v0, #1
   bic.4h  v0, #1, lsl #0
   bic.4h  v0, #1, lsl #8
 
-; CHECK: bic.4h v0, #1               ; encoding: [0x20,0x94,0x00,0x2f]
-; CHECK: bic.4h v0, #1               ; encoding: [0x20,0x94,0x00,0x2f]
-; CHECK: bic.4h v0, #1, lsl #8       ; encoding: [0x20,0xb4,0x00,0x2f]
+; CHECK: bic.4h v0, #0x1               ; encoding: [0x20,0x94,0x00,0x2f]
+; CHECK: bic.4h v0, #0x1               ; encoding: [0x20,0x94,0x00,0x2f]
+; CHECK: bic.4h v0, #0x1, lsl #8       ; encoding: [0x20,0xb4,0x00,0x2f]
 
   bic.4s  v0, #1
   bic.4s  v0, #1, lsl #0
@@ -800,29 +800,29 @@ foo:
   bic.4s  v0, #1, lsl #16
   bic.4s  v0, #1, lsl #24
 
-; CHECK: bic.4s v0, #1               ; encoding: [0x20,0x14,0x00,0x6f]
-; CHECK: bic.4s v0, #1               ; encoding: [0x20,0x14,0x00,0x6f]
-; CHECK: bic.4s v0, #1, lsl #8       ; encoding: [0x20,0x34,0x00,0x6f]
-; CHECK: bic.4s v0, #1, lsl #16      ; encoding: [0x20,0x54,0x00,0x6f]
-; CHECK: bic.4s v0, #1, lsl #24      ; encoding: [0x20,0x74,0x00,0x6f]
+; CHECK: bic.4s v0, #0x1               ; encoding: [0x20,0x14,0x00,0x6f]
+; CHECK: bic.4s v0, #0x1               ; encoding: [0x20,0x14,0x00,0x6f]
+; CHECK: bic.4s v0, #0x1, lsl #8       ; encoding: [0x20,0x34,0x00,0x6f]
+; CHECK: bic.4s v0, #0x1, lsl #16      ; encoding: [0x20,0x54,0x00,0x6f]
+; CHECK: bic.4s v0, #0x1, lsl #24      ; encoding: [0x20,0x74,0x00,0x6f]
 
   bic.8h  v0, #1
   bic.8h  v0, #1, lsl #0
   bic.8h  v0, #1, lsl #8
 
-; CHECK: bic.8h v0, #1               ; encoding: [0x20,0x94,0x00,0x6f]
-; CHECK: bic.8h v0, #1               ; encoding: [0x20,0x94,0x00,0x6f]
-; CHECK: bic.8h v0, #1, lsl #8       ; encoding: [0x20,0xb4,0x00,0x6f]
+; CHECK: bic.8h v0, #0x1               ; encoding: [0x20,0x94,0x00,0x6f]
+; CHECK: bic.8h v0, #0x1               ; encoding: [0x20,0x94,0x00,0x6f]
+; CHECK: bic.8h v0, #0x1, lsl #8       ; encoding: [0x20,0xb4,0x00,0x6f]
 
   fmov.2d v0, #1.250000e-01
 
-; CHECK: fmov.2d v0, #1.250000e-01             ; encoding: [0x00,0xf4,0x02,0x6f]
+; CHECK: fmov.2d v0, #0.12500000             ; encoding: [0x00,0xf4,0x02,0x6f]
 
   fmov.2s v0, #1.250000e-01
   fmov.4s v0, #1.250000e-01
 
-; CHECK: fmov.2s v0, #1.250000e-01             ; encoding: [0x00,0xf4,0x02,0x0f]
-; CHECK: fmov.4s v0, #1.250000e-01             ; encoding: [0x00,0xf4,0x02,0x4f]
+; CHECK: fmov.2s v0, #0.12500000             ; encoding: [0x00,0xf4,0x02,0x0f]
+; CHECK: fmov.4s v0, #0.12500000             ; encoding: [0x00,0xf4,0x02,0x4f]
 
   orr.2s  v0, #1
   orr.2s  v0, #1, lsl #0
@@ -830,19 +830,19 @@ foo:
   orr.2s  v0, #1, lsl #16
   orr.2s  v0, #1, lsl #24
 
-; CHECK: orr.2s v0, #1               ; encoding: [0x20,0x14,0x00,0x0f]
-; CHECK: orr.2s v0, #1               ; encoding: [0x20,0x14,0x00,0x0f]
-; CHECK: orr.2s v0, #1, lsl #8       ; encoding: [0x20,0x34,0x00,0x0f]
-; CHECK: orr.2s v0, #1, lsl #16      ; encoding: [0x20,0x54,0x00,0x0f]
-; CHECK: orr.2s v0, #1, lsl #24      ; encoding: [0x20,0x74,0x00,0x0f]
+; CHECK: orr.2s v0, #0x1               ; encoding: [0x20,0x14,0x00,0x0f]
+; CHECK: orr.2s v0, #0x1               ; encoding: [0x20,0x14,0x00,0x0f]
+; CHECK: orr.2s v0, #0x1, lsl #8       ; encoding: [0x20,0x34,0x00,0x0f]
+; CHECK: orr.2s v0, #0x1, lsl #16      ; encoding: [0x20,0x54,0x00,0x0f]
+; CHECK: orr.2s v0, #0x1, lsl #24      ; encoding: [0x20,0x74,0x00,0x0f]
 
   orr.4h  v0, #1
   orr.4h  v0, #1, lsl #0
   orr.4h  v0, #1, lsl #8
 
-; CHECK: orr.4h v0, #1               ; encoding: [0x20,0x94,0x00,0x0f]
-; CHECK: orr.4h v0, #1               ; encoding: [0x20,0x94,0x00,0x0f]
-; CHECK: orr.4h v0, #1, lsl #8       ; encoding: [0x20,0xb4,0x00,0x0f]
+; CHECK: orr.4h v0, #0x1               ; encoding: [0x20,0x94,0x00,0x0f]
+; CHECK: orr.4h v0, #0x1               ; encoding: [0x20,0x94,0x00,0x0f]
+; CHECK: orr.4h v0, #0x1, lsl #8       ; encoding: [0x20,0xb4,0x00,0x0f]
 
   orr.4s  v0, #1
   orr.4s  v0, #1, lsl #0
@@ -850,19 +850,19 @@ foo:
   orr.4s  v0, #1, lsl #16
   orr.4s  v0, #1, lsl #24
 
-; CHECK: orr.4s v0, #1               ; encoding: [0x20,0x14,0x00,0x4f]
-; CHECK: orr.4s v0, #1               ; encoding: [0x20,0x14,0x00,0x4f]
-; CHECK: orr.4s v0, #1, lsl #8       ; encoding: [0x20,0x34,0x00,0x4f]
-; CHECK: orr.4s v0, #1, lsl #16      ; encoding: [0x20,0x54,0x00,0x4f]
-; CHECK: orr.4s v0, #1, lsl #24      ; encoding: [0x20,0x74,0x00,0x4f]
+; CHECK: orr.4s v0, #0x1               ; encoding: [0x20,0x14,0x00,0x4f]
+; CHECK: orr.4s v0, #0x1               ; encoding: [0x20,0x14,0x00,0x4f]
+; CHECK: orr.4s v0, #0x1, lsl #8       ; encoding: [0x20,0x34,0x00,0x4f]
+; CHECK: orr.4s v0, #0x1, lsl #16      ; encoding: [0x20,0x54,0x00,0x4f]
+; CHECK: orr.4s v0, #0x1, lsl #24      ; encoding: [0x20,0x74,0x00,0x4f]
 
   orr.8h  v0, #1
   orr.8h  v0, #1, lsl #0
   orr.8h  v0, #1, lsl #8
 
-; CHECK: orr.8h v0, #1               ; encoding: [0x20,0x94,0x00,0x4f]
-; CHECK: orr.8h v0, #1               ; encoding: [0x20,0x94,0x00,0x4f]
-; CHECK: orr.8h v0, #1, lsl #8       ; encoding: [0x20,0xb4,0x00,0x4f]
+; CHECK: orr.8h v0, #0x1               ; encoding: [0x20,0x94,0x00,0x4f]
+; CHECK: orr.8h v0, #0x1               ; encoding: [0x20,0x94,0x00,0x4f]
+; CHECK: orr.8h v0, #0x1, lsl #8       ; encoding: [0x20,0xb4,0x00,0x4f]
 
   movi     d0, #0x000000000000ff
   movi.2d  v0, #0x000000000000ff
@@ -876,11 +876,11 @@ foo:
   movi.2s v0, #1, lsl #16
   movi.2s v0, #1, lsl #24
 
-; CHECK: movi.2s v0, #1              ; encoding: [0x20,0x04,0x00,0x0f]
-; CHECK: movi.2s v0, #1              ; encoding: [0x20,0x04,0x00,0x0f]
-; CHECK: movi.2s v0, #1, lsl #8      ; encoding: [0x20,0x24,0x00,0x0f]
-; CHECK: movi.2s v0, #1, lsl #16     ; encoding: [0x20,0x44,0x00,0x0f]
-; CHECK: movi.2s v0, #1, lsl #24     ; encoding: [0x20,0x64,0x00,0x0f]
+; CHECK: movi.2s v0, #0x1              ; encoding: [0x20,0x04,0x00,0x0f]
+; CHECK: movi.2s v0, #0x1              ; encoding: [0x20,0x04,0x00,0x0f]
+; CHECK: movi.2s v0, #0x1, lsl #8      ; encoding: [0x20,0x24,0x00,0x0f]
+; CHECK: movi.2s v0, #0x1, lsl #16     ; encoding: [0x20,0x44,0x00,0x0f]
+; CHECK: movi.2s v0, #0x1, lsl #24     ; encoding: [0x20,0x64,0x00,0x0f]
 
   movi.4s v0, #1
   movi.4s v0, #1, lsl #0
@@ -888,43 +888,43 @@ foo:
   movi.4s v0, #1, lsl #16
   movi.4s v0, #1, lsl #24
 
-; CHECK: movi.4s v0, #1              ; encoding: [0x20,0x04,0x00,0x4f]
-; CHECK: movi.4s v0, #1              ; encoding: [0x20,0x04,0x00,0x4f]
-; CHECK: movi.4s v0, #1, lsl #8      ; encoding: [0x20,0x24,0x00,0x4f]
-; CHECK: movi.4s v0, #1, lsl #16     ; encoding: [0x20,0x44,0x00,0x4f]
-; CHECK: movi.4s v0, #1, lsl #24     ; encoding: [0x20,0x64,0x00,0x4f]
+; CHECK: movi.4s v0, #0x1              ; encoding: [0x20,0x04,0x00,0x4f]
+; CHECK: movi.4s v0, #0x1              ; encoding: [0x20,0x04,0x00,0x4f]
+; CHECK: movi.4s v0, #0x1, lsl #8      ; encoding: [0x20,0x24,0x00,0x4f]
+; CHECK: movi.4s v0, #0x1, lsl #16     ; encoding: [0x20,0x44,0x00,0x4f]
+; CHECK: movi.4s v0, #0x1, lsl #24     ; encoding: [0x20,0x64,0x00,0x4f]
 
   movi.4h v0, #1
   movi.4h v0, #1, lsl #0
   movi.4h v0, #1, lsl #8
 
-; CHECK: movi.4h v0, #1              ; encoding: [0x20,0x84,0x00,0x0f]
-; CHECK: movi.4h v0, #1              ; encoding: [0x20,0x84,0x00,0x0f]
-; CHECK: movi.4h v0, #1, lsl #8      ; encoding: [0x20,0xa4,0x00,0x0f]
+; CHECK: movi.4h v0, #0x1              ; encoding: [0x20,0x84,0x00,0x0f]
+; CHECK: movi.4h v0, #0x1              ; encoding: [0x20,0x84,0x00,0x0f]
+; CHECK: movi.4h v0, #0x1, lsl #8      ; encoding: [0x20,0xa4,0x00,0x0f]
 
   movi.8h v0, #1
   movi.8h v0, #1, lsl #0
   movi.8h v0, #1, lsl #8
 
-; CHECK: movi.8h v0, #1              ; encoding: [0x20,0x84,0x00,0x4f]
-; CHECK: movi.8h v0, #1              ; encoding: [0x20,0x84,0x00,0x4f]
-; CHECK: movi.8h v0, #1, lsl #8      ; encoding: [0x20,0xa4,0x00,0x4f]
+; CHECK: movi.8h v0, #0x1              ; encoding: [0x20,0x84,0x00,0x4f]
+; CHECK: movi.8h v0, #0x1              ; encoding: [0x20,0x84,0x00,0x4f]
+; CHECK: movi.8h v0, #0x1, lsl #8      ; encoding: [0x20,0xa4,0x00,0x4f]
 
   movi.2s v0, #1, msl #8
   movi.2s v0, #1, msl #16
   movi.4s v0, #1, msl #8
   movi.4s v0, #1, msl #16
 
-; CHECK: movi.2s v0, #1, msl #8      ; encoding: [0x20,0xc4,0x00,0x0f]
-; CHECK: movi.2s v0, #1, msl #16     ; encoding: [0x20,0xd4,0x00,0x0f]
-; CHECK: movi.4s v0, #1, msl #8      ; encoding: [0x20,0xc4,0x00,0x4f]
-; CHECK: movi.4s v0, #1, msl #16     ; encoding: [0x20,0xd4,0x00,0x4f]
+; CHECK: movi.2s v0, #0x1, msl #8      ; encoding: [0x20,0xc4,0x00,0x0f]
+; CHECK: movi.2s v0, #0x1, msl #16     ; encoding: [0x20,0xd4,0x00,0x0f]
+; CHECK: movi.4s v0, #0x1, msl #8      ; encoding: [0x20,0xc4,0x00,0x4f]
+; CHECK: movi.4s v0, #0x1, msl #16     ; encoding: [0x20,0xd4,0x00,0x4f]
 
   movi.8b  v0, #1
   movi.16b v0, #1
 
-; CHECK: movi.8b  v0, #1             ; encoding: [0x20,0xe4,0x00,0x0f]
-; CHECK: movi.16b v0, #1             ; encoding: [0x20,0xe4,0x00,0x4f]
+; CHECK: movi.8b  v0, #0x1             ; encoding: [0x20,0xe4,0x00,0x0f]
+; CHECK: movi.16b v0, #0x1             ; encoding: [0x20,0xe4,0x00,0x4f]
 
   mvni.2s v0, #1
   mvni.2s v0, #1, lsl #0
@@ -932,11 +932,11 @@ foo:
   mvni.2s v0, #1, lsl #16
   mvni.2s v0, #1, lsl #24
 
-; CHECK: mvni.2s v0, #1              ; encoding: [0x20,0x04,0x00,0x2f]
-; CHECK: mvni.2s v0, #1              ; encoding: [0x20,0x04,0x00,0x2f]
-; CHECK: mvni.2s v0, #1, lsl #8      ; encoding: [0x20,0x24,0x00,0x2f]
-; CHECK: mvni.2s v0, #1, lsl #16     ; encoding: [0x20,0x44,0x00,0x2f]
-; CHECK: mvni.2s v0, #1, lsl #24     ; encoding: [0x20,0x64,0x00,0x2f]
+; CHECK: mvni.2s v0, #0x1              ; encoding: [0x20,0x04,0x00,0x2f]
+; CHECK: mvni.2s v0, #0x1              ; encoding: [0x20,0x04,0x00,0x2f]
+; CHECK: mvni.2s v0, #0x1, lsl #8      ; encoding: [0x20,0x24,0x00,0x2f]
+; CHECK: mvni.2s v0, #0x1, lsl #16     ; encoding: [0x20,0x44,0x00,0x2f]
+; CHECK: mvni.2s v0, #0x1, lsl #24     ; encoding: [0x20,0x64,0x00,0x2f]
 
   mvni.4s v0, #1
   mvni.4s v0, #1, lsl #0
@@ -944,37 +944,37 @@ foo:
   mvni.4s v0, #1, lsl #16
   mvni.4s v0, #1, lsl #24
 
-; CHECK: mvni.4s v0, #1              ; encoding: [0x20,0x04,0x00,0x6f]
-; CHECK: mvni.4s v0, #1              ; encoding: [0x20,0x04,0x00,0x6f]
-; CHECK: mvni.4s v0, #1, lsl #8      ; encoding: [0x20,0x24,0x00,0x6f]
-; CHECK: mvni.4s v0, #1, lsl #16     ; encoding: [0x20,0x44,0x00,0x6f]
-; CHECK: mvni.4s v0, #1, lsl #24     ; encoding: [0x20,0x64,0x00,0x6f]
+; CHECK: mvni.4s v0, #0x1              ; encoding: [0x20,0x04,0x00,0x6f]
+; CHECK: mvni.4s v0, #0x1              ; encoding: [0x20,0x04,0x00,0x6f]
+; CHECK: mvni.4s v0, #0x1, lsl #8      ; encoding: [0x20,0x24,0x00,0x6f]
+; CHECK: mvni.4s v0, #0x1, lsl #16     ; encoding: [0x20,0x44,0x00,0x6f]
+; CHECK: mvni.4s v0, #0x1, lsl #24     ; encoding: [0x20,0x64,0x00,0x6f]
 
   mvni.4h v0, #1
   mvni.4h v0, #1, lsl #0
   mvni.4h v0, #1, lsl #8
 
-; CHECK: mvni.4h v0, #1              ; encoding: [0x20,0x84,0x00,0x2f]
-; CHECK: mvni.4h v0, #1              ; encoding: [0x20,0x84,0x00,0x2f]
-; CHECK: mvni.4h v0, #1, lsl #8      ; encoding: [0x20,0xa4,0x00,0x2f]
+; CHECK: mvni.4h v0, #0x1              ; encoding: [0x20,0x84,0x00,0x2f]
+; CHECK: mvni.4h v0, #0x1              ; encoding: [0x20,0x84,0x00,0x2f]
+; CHECK: mvni.4h v0, #0x1, lsl #8      ; encoding: [0x20,0xa4,0x00,0x2f]
 
   mvni.8h v0, #1
   mvni.8h v0, #1, lsl #0
   mvni.8h v0, #1, lsl #8
 
-; CHECK: mvni.8h v0, #1              ; encoding: [0x20,0x84,0x00,0x6f]
-; CHECK: mvni.8h v0, #1              ; encoding: [0x20,0x84,0x00,0x6f]
-; CHECK: mvni.8h v0, #1, lsl #8      ; encoding: [0x20,0xa4,0x00,0x6f]
+; CHECK: mvni.8h v0, #0x1              ; encoding: [0x20,0x84,0x00,0x6f]
+; CHECK: mvni.8h v0, #0x1              ; encoding: [0x20,0x84,0x00,0x6f]
+; CHECK: mvni.8h v0, #0x1, lsl #8      ; encoding: [0x20,0xa4,0x00,0x6f]
 
   mvni.2s v0, #1, msl #8
   mvni.2s v0, #1, msl #16
   mvni.4s v0, #1, msl #8
   mvni.4s v0, #1, msl #16
 
-; CHECK: mvni.2s v0, #1, msl #8      ; encoding: [0x20,0xc4,0x00,0x2f]
-; CHECK: mvni.2s v0, #1, msl #16     ; encoding: [0x20,0xd4,0x00,0x2f]
-; CHECK: mvni.4s v0, #1, msl #8      ; encoding: [0x20,0xc4,0x00,0x6f]
-; CHECK: mvni.4s v0, #1, msl #16     ; encoding: [0x20,0xd4,0x00,0x6f]
+; CHECK: mvni.2s v0, #0x1, msl #8      ; encoding: [0x20,0xc4,0x00,0x2f]
+; CHECK: mvni.2s v0, #0x1, msl #16     ; encoding: [0x20,0xd4,0x00,0x2f]
+; CHECK: mvni.4s v0, #0x1, msl #8      ; encoding: [0x20,0xc4,0x00,0x6f]
+; CHECK: mvni.4s v0, #0x1, msl #16     ; encoding: [0x20,0xd4,0x00,0x6f]
 
 ;===-------------------------------------------------------------------------===
 ; AdvSIMD scalar x index
diff --git a/test/MC/ARM64/aliases.s b/test/MC/ARM64/aliases.s
index a1d1e8349b..18c32240d2 100644
--- a/test/MC/ARM64/aliases.s
+++ b/test/MC/ARM64/aliases.s
@@ -67,7 +67,7 @@ foo:
   cmn x4, x5, uxtx #1
 
 ; CHECK: cmn	w1, #3                  ; encoding: [0x3f,0x0c,0x00,0x31]
-; CHECK: cmn	x2, #4194304            ; encoding: [0x5f,0x00,0x50,0xb1]
+; CHECK: cmn	x2, #1024, lsl #12      ; encoding: [0x5f,0x00,0x50,0xb1]
 ; CHECK: cmn	w4, w5                  ; encoding: [0x9f,0x00,0x05,0x2b]
 ; CHECK: cmn	x6, x7                  ; encoding: [0xdf,0x00,0x07,0xab]
 ; CHECK: cmn	w8, w9, asr #3          ; encoding: [0x1f,0x0d,0x89,0x2b]
@@ -92,7 +92,7 @@ foo:
   cmp w9, w8, uxtw
   cmp wsp, w9, lsl #0
 
-; CHECK: cmp	w1, #4194304            ; encoding: [0x3f,0x00,0x50,0x71]
+; CHECK: cmp	w1, #1024, lsl #12      ; encoding: [0x3f,0x00,0x50,0x71]
 ; CHECK: cmp	x2, #1024               ; encoding: [0x5f,0x00,0x10,0xf1]
 ; CHECK: cmp	w4, w5                  ; encoding: [0x9f,0x00,0x05,0x6b]
 ; CHECK: cmp	x6, x7                  ; encoding: [0xdf,0x00,0x07,0xeb]
@@ -134,8 +134,8 @@ foo:
   mov x0, #281470681743360
   mov x0, #18446744073709486080
 
-; CHECK: movz	x0, #65535, lsl #32
-; CHECK: movn	x0, #65535
+; CHECK: movz	x0, #0xffff, lsl #32
+; CHECK: movn	x0, #0xffff
 
   mov w0, #0xffffffff
   mov w0, #0xffffff00
@@ -143,9 +143,9 @@ foo:
   mov wzr, #0xffffff00
 
 ; CHECK: movn   w0, #0
-; CHECK: movn   w0, #255
+; CHECK: movn   w0, #0xff
 ; CHECK: movn   wzr, #0
-; CHECK: movn   wzr, #255
+; CHECK: movn   wzr, #0xff
 
 ;-----------------------------------------------------------------------------
 ; MVN aliases
@@ -249,8 +249,8 @@ foo:
 ; CHECK: sxtb x1, w2
 ; CHECK: sxth x1, w2
 ; CHECK: sxtw x1, w2
-; CHECK: ubfx x1, x2, #0, #8
-; CHECK: ubfx x1, x2, #0, #16
+; CHECK: uxtb w1, w2
+; CHECK: uxth w1, w2
 ; CHECK: ubfx x1, x2, #0, #32
 
 ;-----------------------------------------------------------------------------
@@ -746,8 +746,8 @@ foo:
   movi v2.2D, #0x000000000000ff
 
 ; CHECK: movi.16b	v4, #0              ; encoding: [0x04,0xe4,0x00,0x4f]
-; CHECK: movi.16b	v4, #1              ; encoding: [0x24,0xe4,0x00,0x4f]
-; CHECK: movi.8b	v4, #2               ; encoding: [0x44,0xe4,0x00,0x0f]
-; CHECK: movi.8b	v4, #3               ; encoding: [0x64,0xe4,0x00,0x0f]
+; CHECK: movi.16b	v4, #0x1              ; encoding: [0x24,0xe4,0x00,0x4f]
+; CHECK: movi.8b	v4, #0x2               ; encoding: [0x44,0xe4,0x00,0x0f]
+; CHECK: movi.8b	v4, #0x3               ; encoding: [0x64,0xe4,0x00,0x0f]
 ; CHECK: movi.2d	v1, #0x000000000000ff ; encoding: [0x21,0xe4,0x00,0x6f]
 ; CHECK: movi.2d	v2, #0x000000000000ff ; encoding: [0x22,0xe4,0x00,0x6f]
diff --git a/test/MC/ARM64/arithmetic-encoding.s b/test/MC/ARM64/arithmetic-encoding.s
index 2193feb3f6..7a30e998cb 100644
--- a/test/MC/ARM64/arithmetic-encoding.s
+++ b/test/MC/ARM64/arithmetic-encoding.s
@@ -47,11 +47,11 @@ foo:
   add x3, x4, #0, lsl #12
   add sp, sp, #32
 
-; CHECK: add w3, w4, #4194304        ; encoding: [0x83,0x00,0x50,0x11]
-; CHECK: add w3, w4, #4194304        ; encoding: [0x83,0x00,0x50,0x11]
+; CHECK: add w3, w4, #1024, lsl #12  ; encoding: [0x83,0x00,0x50,0x11]
+; CHECK: add w3, w4, #1024, lsl #12  ; encoding: [0x83,0x00,0x50,0x11]
 ; CHECK: add w3, w4, #0, lsl #12     ; encoding: [0x83,0x00,0x40,0x11]
-; CHECK: add x3, x4, #4194304        ; encoding: [0x83,0x00,0x50,0x91]
-; CHECK: add x3, x4, #4194304        ; encoding: [0x83,0x00,0x50,0x91]
+; CHECK: add x3, x4, #1024, lsl #12  ; encoding: [0x83,0x00,0x50,0x91]
+; CHECK: add x3, x4, #1024, lsl #12  ; encoding: [0x83,0x00,0x50,0x91]
 ; CHECK: add x3, x4, #0, lsl #12     ; encoding: [0x83,0x00,0x40,0x91]
 ; CHECK: add sp, sp, #32             ; encoding: [0xff,0x83,0x00,0x91]
 
@@ -64,10 +64,10 @@ foo:
 
 ; CHECK: adds w3, w4, #1024          ; encoding: [0x83,0x00,0x10,0x31]
 ; CHECK: adds w3, w4, #1024          ; encoding: [0x83,0x00,0x10,0x31]
-; CHECK: adds w3, w4, #4194304       ; encoding: [0x83,0x00,0x50,0x31]
+; CHECK: adds w3, w4, #1024, lsl #12 ; encoding: [0x83,0x00,0x50,0x31]
 ; CHECK: adds x3, x4, #1024          ; encoding: [0x83,0x00,0x10,0xb1]
 ; CHECK: adds x3, x4, #1024          ; encoding: [0x83,0x00,0x10,0xb1]
-; CHECK: adds x3, x4, #4194304       ; encoding: [0x83,0x00,0x50,0xb1]
+; CHECK: adds x3, x4, #1024, lsl #12 ; encoding: [0x83,0x00,0x50,0xb1]
 
   sub w3, w4, #1024
   sub w3, w4, #1024, lsl #0
@@ -79,10 +79,10 @@ foo:
 
 ; CHECK: sub w3, w4, #1024           ; encoding: [0x83,0x00,0x10,0x51]
 ; CHECK: sub w3, w4, #1024           ; encoding: [0x83,0x00,0x10,0x51]
-; CHECK: sub w3, w4, #4194304        ; encoding: [0x83,0x00,0x50,0x51]
+; CHECK: sub w3, w4, #1024, lsl #12  ; encoding: [0x83,0x00,0x50,0x51]
 ; CHECK: sub x3, x4, #1024           ; encoding: [0x83,0x00,0x10,0xd1]
 ; CHECK: sub x3, x4, #1024           ; encoding: [0x83,0x00,0x10,0xd1]
-; CHECK: sub x3, x4, #4194304        ; encoding: [0x83,0x00,0x50,0xd1]
+; CHECK: sub x3, x4, #1024, lsl #12  ; encoding: [0x83,0x00,0x50,0xd1]
 ; CHECK: sub sp, sp, #32             ; encoding: [0xff,0x83,0x00,0xd1]
 
   subs w3, w4, #1024
@@ -94,10 +94,10 @@ foo:
 
 ; CHECK: subs w3, w4, #1024          ; encoding: [0x83,0x00,0x10,0x71]
 ; CHECK: subs w3, w4, #1024          ; encoding: [0x83,0x00,0x10,0x71]
-; CHECK: subs w3, w4, #4194304       ; encoding: [0x83,0x00,0x50,0x71]
+; CHECK: subs w3, w4, #1024, lsl #12 ; encoding: [0x83,0x00,0x50,0x71]
 ; CHECK: subs x3, x4, #1024          ; encoding: [0x83,0x00,0x10,0xf1]
 ; CHECK: subs x3, x4, #1024          ; encoding: [0x83,0x00,0x10,0xf1]
-; CHECK: subs x3, x4, #4194304       ; encoding: [0x83,0x00,0x50,0xf1]
+; CHECK: subs x3, x4, #1024, lsl #12 ; encoding: [0x83,0x00,0x50,0xf1]
 
 ;==---------------------------------------------------------------------------==
 ; Add/Subtract register with (optional) shift
@@ -510,30 +510,30 @@ foo:
   movz w0, #1, lsl #16
   movz x0, #1, lsl #16
 
-; CHECK: movz w0, #1                 ; encoding: [0x20,0x00,0x80,0x52]
-; CHECK: movz x0, #1                 ; encoding: [0x20,0x00,0x80,0xd2]
-; CHECK: movz w0, #1, lsl #16        ; encoding: [0x20,0x00,0xa0,0x52]
-; CHECK: movz x0, #1, lsl #16        ; encoding: [0x20,0x00,0xa0,0xd2]
+; CHECK: movz w0, #0x1                 ; encoding: [0x20,0x00,0x80,0x52]
+; CHECK: movz x0, #0x1                 ; encoding: [0x20,0x00,0x80,0xd2]
+; CHECK: movz w0, #0x1, lsl #16        ; encoding: [0x20,0x00,0xa0,0x52]
+; CHECK: movz x0, #0x1, lsl #16        ; encoding: [0x20,0x00,0xa0,0xd2]
 
   movn w0, #2
   movn x0, #2
   movn w0, #2, lsl #16
   movn x0, #2, lsl #16
 
-; CHECK: movn w0, #2                 ; encoding: [0x40,0x00,0x80,0x12]
-; CHECK: movn x0, #2                 ; encoding: [0x40,0x00,0x80,0x92]
-; CHECK: movn w0, #2, lsl #16        ; encoding: [0x40,0x00,0xa0,0x12]
-; CHECK: movn x0, #2, lsl #16        ; encoding: [0x40,0x00,0xa0,0x92]
+; CHECK: movn w0, #0x2                 ; encoding: [0x40,0x00,0x80,0x12]
+; CHECK: movn x0, #0x2                 ; encoding: [0x40,0x00,0x80,0x92]
+; CHECK: movn w0, #0x2, lsl #16        ; encoding: [0x40,0x00,0xa0,0x12]
+; CHECK: movn x0, #0x2, lsl #16        ; encoding: [0x40,0x00,0xa0,0x92]
 
   movk w0, #1
   movk x0, #1
   movk w0, #1, lsl #16
   movk x0, #1, lsl #16
 
-; CHECK: movk w0, #1                 ; encoding: [0x20,0x00,0x80,0x72]
-; CHECK: movk x0, #1                 ; encoding: [0x20,0x00,0x80,0xf2]
-; CHECK: movk w0, #1, lsl #16        ; encoding: [0x20,0x00,0xa0,0x72]
-; CHECK: movk x0, #1, lsl #16        ; encoding: [0x20,0x00,0xa0,0xf2]
+; CHECK: movk w0, #0x1                 ; encoding: [0x20,0x00,0x80,0x72]
+; CHECK: movk x0, #0x1                 ; encoding: [0x20,0x00,0x80,0xf2]
+; CHECK: movk w0, #0x1, lsl #16        ; encoding: [0x20,0x00,0xa0,0x72]
+; CHECK: movk x0, #0x1, lsl #16        ; encoding: [0x20,0x00,0xa0,0xf2]
 
 ;==---------------------------------------------------------------------------==
 ; Conditionally set flags instructions
@@ -602,10 +602,10 @@ foo:
 
 ; CHECK: csel	w16, w7, w27, eq        ; encoding: [0xf0,0x00,0x9b,0x1a]
 ; CHECK: csel	w15, w6, w26, ne        ; encoding: [0xcf,0x10,0x9a,0x1a]
-; CHECK: csel	w14, w5, w25, cs        ; encoding: [0xae,0x20,0x99,0x1a]
-; CHECK: csel	w13, w4, w24, cs        ; encoding: [0x8d,0x20,0x98,0x1a]
-; CHECK: csel	w12, w3, w23, cc        ; encoding: [0x6c,0x30,0x97,0x1a]
-; CHECK: csel	w11, w2, w22, cc        ; encoding: [0x4b,0x30,0x96,0x1a]
+; CHECK: csel	w14, w5, w25, hs        ; encoding: [0xae,0x20,0x99,0x1a]
+; CHECK: csel	w13, w4, w24, hs        ; encoding: [0x8d,0x20,0x98,0x1a]
+; CHECK: csel	w12, w3, w23, lo        ; encoding: [0x6c,0x30,0x97,0x1a]
+; CHECK: csel	w11, w2, w22, lo        ; encoding: [0x4b,0x30,0x96,0x1a]
 ; CHECK: csel	w10, w1, w21, mi        ; encoding: [0x2a,0x40,0x95,0x1a]
 ; CHECK: csel	x9, x9, x1, pl          ; encoding: [0x29,0x51,0x81,0x9a]
 ; CHECK: csel	x8, x8, x2, vs          ; encoding: [0x08,0x61,0x82,0x9a]
diff --git a/test/MC/ARM64/branch-encoding.s b/test/MC/ARM64/branch-encoding.s
index 8f8751c2cc..ba8fb3d901 100644
--- a/test/MC/ARM64/branch-encoding.s
+++ b/test/MC/ARM64/branch-encoding.s
@@ -36,10 +36,10 @@ foo:
 ; CHECK: b.ne L1   ; encoding: [0bAAA00001,A,A,0x54]
 ; CHECK: fixup A - offset: 0, value: L1, kind: fixup_arm64_pcrel_branch19
   b.cs  L1
-; CHECK: b.cs L1   ; encoding: [0bAAA00010,A,A,0x54]
+; CHECK: b.hs L1   ; encoding: [0bAAA00010,A,A,0x54]
 ; CHECK: fixup A - offset: 0, value: L1, kind: fixup_arm64_pcrel_branch19
   b.cc  L1
-; CHECK: b.cc L1   ; encoding: [0bAAA00011,A,A,0x54]
+; CHECK: b.lo L1   ; encoding: [0bAAA00011,A,A,0x54]
 ; CHECK: fixup A - offset: 0, value: L1, kind: fixup_arm64_pcrel_branch19
   b.mi  L1
 ; CHECK: b.mi L1   ; encoding: [0bAAA00100,A,A,0x54]
@@ -80,7 +80,7 @@ L1:
   b.lt #28
 ; CHECK: b.lt #28
   b.cc #1048572
-; CHECK: b.cc	#1048572                ; encoding: [0xe3,0xff,0x7f,0x54]
+; CHECK: b.lo	#1048572                ; encoding: [0xe3,0xff,0x7f,0x54]
   b #134217724
 ; CHECK: b	#134217724              ; encoding: [0xff,0xff,0xff,0x15]
   b #-134217728
diff --git a/test/MC/ARM64/condbr-without-dots.s b/test/MC/ARM64/condbr-without-dots.s
new file mode 100644
index 0000000000..2a9f7a7cf7
--- /dev/null
+++ b/test/MC/ARM64/condbr-without-dots.s
@@ -0,0 +1,37 @@
+// RUN: llvm-mc -triple arm64-apple-ios -o - %s | FileCheck %s
+        
+        beq lbl
+        bne lbl
+        bcs lbl
+        bhs lbl
+        blo lbl
+        bcc lbl
+        bmi lbl
+        bpl lbl
+        bvs lbl
+        bvc lbl
+        bhi lbl
+        bls lbl
+        bge lbl
+        blt lbl
+        bgt lbl
+        ble lbl
+        bal lbl
+
+// CHECK: b.eq lbl
+// CHECK: b.ne lbl
+// CHECK: b.hs lbl
+// CHECK: b.hs lbl
+// CHECK: b.lo lbl
+// CHECK: b.lo lbl
+// CHECK: b.mi lbl
+// CHECK: b.pl lbl
+// CHECK: b.vs lbl
+// CHECK: b.vc lbl
+// CHECK: b.hi lbl
+// CHECK: b.ls lbl
+// CHECK: b.ge lbl
+// CHECK: b.lt lbl
+// CHECK: b.gt lbl
+// CHECK: b.le lbl
+// CHECK: b.al lbl
diff --git a/test/MC/ARM64/elf-relocs.s b/test/MC/ARM64/elf-relocs.s
index 7eec085f17..eb22cc2f23 100644
--- a/test/MC/ARM64/elf-relocs.s
+++ b/test/MC/ARM64/elf-relocs.s
@@ -88,9 +88,9 @@ trickQuestion:
 // CHECK: adrp x3, trickQuestion
 // CHECK-OBJ: 5c R_AARCH64_ADR_PREL_PG_HI21 trickQuestion
 
-   ldrb w2, [x3, #:lo12:sym]
+   ldrb w2, [x3, :lo12:sym]
    ldrsb w5, [x7, #:lo12:sym]
-   ldrsb x11, [x13, #:lo12:sym]
+   ldrsb x11, [x13, :lo12:sym]
    ldr b17, [x19, #:lo12:sym]
 // CHECK: ldrb w2, [x3, :lo12:sym]
 // CHECK: ldrsb w5, [x7, :lo12:sym]
@@ -103,7 +103,7 @@ trickQuestion:
 
    ldrb w23, [x29, #:dtprel_lo12_nc:sym]
    ldrsb w23, [x19, #:dtprel_lo12:sym]
-   ldrsb x17, [x13, #:dtprel_lo12_nc:sym]
+   ldrsb x17, [x13, :dtprel_lo12_nc:sym]
    ldr b11, [x7, #:dtprel_lo12:sym]
 // CHECK: ldrb w23, [x29, :dtprel_lo12_nc:sym]
 // CHECK: ldrsb w23, [x19, :dtprel_lo12:sym]
@@ -114,9 +114,9 @@ trickQuestion:
 // CHECK-OBJ: R_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC sym
 // CHECK-OBJ: R_AARCH64_TLSLD_LDST8_DTPREL_LO12 sym
 
-   ldrb w1, [x2, #:tprel_lo12:sym]
+   ldrb w1, [x2, :tprel_lo12:sym]
    ldrsb w3, [x4, #:tprel_lo12_nc:sym]
-   ldrsb x5, [x6, #:tprel_lo12:sym]
+   ldrsb x5, [x6, :tprel_lo12:sym]
    ldr b7, [x8, #:tprel_lo12_nc:sym]
 // CHECK: ldrb w1, [x2, :tprel_lo12:sym]
 // CHECK: ldrsb w3, [x4, :tprel_lo12_nc:sym]
@@ -128,9 +128,9 @@ trickQuestion:
 // CHECK-OBJ: R_AARCH64_TLSLE_LDST8_TPREL_LO12_NC sym
 
    ldrh w2, [x3, #:lo12:sym]
-   ldrsh w5, [x7, #:lo12:sym]
+   ldrsh w5, [x7, :lo12:sym]
    ldrsh x11, [x13, #:lo12:sym]
-   ldr h17, [x19, #:lo12:sym]
+   ldr h17, [x19, :lo12:sym]
 // CHECK: ldrh w2, [x3, :lo12:sym]
 // CHECK: ldrsh w5, [x7, :lo12:sym]
 // CHECK: ldrsh x11, [x13, :lo12:sym]
@@ -141,8 +141,8 @@ trickQuestion:
 // CHECK-OBJ: R_AARCH64_LDST16_ABS_LO12_NC sym
 
    ldrh w23, [x29, #:dtprel_lo12_nc:sym]
-   ldrsh w23, [x19, #:dtprel_lo12:sym]
-   ldrsh x17, [x13, #:dtprel_lo12_nc:sym]
+   ldrsh w23, [x19, :dtprel_lo12:sym]
+   ldrsh x17, [x13, :dtprel_lo12_nc:sym]
    ldr h11, [x7, #:dtprel_lo12:sym]
 // CHECK: ldrh w23, [x29, :dtprel_lo12_nc:sym]
 // CHECK: ldrsh w23, [x19, :dtprel_lo12:sym]
@@ -153,9 +153,9 @@ trickQuestion:
 // CHECK-OBJ: R_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC sym
 // CHECK-OBJ: R_AARCH64_TLSLD_LDST16_DTPREL_LO12 sym
 
-   ldrh w1, [x2, #:tprel_lo12:sym]
+   ldrh w1, [x2, :tprel_lo12:sym]
    ldrsh w3, [x4, #:tprel_lo12_nc:sym]
-   ldrsh x5, [x6, #:tprel_lo12:sym]
+   ldrsh x5, [x6, :tprel_lo12:sym]
    ldr h7, [x8, #:tprel_lo12_nc:sym]
 // CHECK: ldrh w1, [x2, :tprel_lo12:sym]
 // CHECK: ldrsh w3, [x4, :tprel_lo12_nc:sym]
@@ -168,7 +168,7 @@ trickQuestion:
 
    ldr w1, [x2, #:lo12:sym]
    ldrsw x3, [x4, #:lo12:sym]
-   ldr s4, [x5, #:lo12:sym]
+   ldr s4, [x5, :lo12:sym]
 // CHECK: ldr w1, [x2, :lo12:sym]
 // CHECK: ldrsw x3, [x4, :lo12:sym]
 // CHECK: ldr s4, [x5, :lo12:sym]
@@ -176,7 +176,7 @@ trickQuestion:
 // CHECK-OBJ: R_AARCH64_LDST32_ABS_LO12_NC sym
 // CHECK-OBJ: R_AARCH64_LDST32_ABS_LO12_NC sym
 
-   ldr w1, [x2, #:dtprel_lo12:sym]
+   ldr w1, [x2, :dtprel_lo12:sym]
    ldrsw x3, [x4, #:dtprel_lo12_nc:sym]
    ldr s4, [x5, #:dtprel_lo12_nc:sym]
 // CHECK: ldr w1, [x2, :dtprel_lo12:sym]
@@ -188,8 +188,8 @@ trickQuestion:
 
 
    ldr w1, [x2, #:tprel_lo12:sym]
-   ldrsw x3, [x4, #:tprel_lo12_nc:sym]
-   ldr s4, [x5, #:tprel_lo12_nc:sym]
+   ldrsw x3, [x4, :tprel_lo12_nc:sym]
+   ldr s4, [x5, :tprel_lo12_nc:sym]
 // CHECK: ldr w1, [x2, :tprel_lo12:sym]
 // CHECK: ldrsw x3, [x4, :tprel_lo12_nc:sym]
 // CHECK: ldr s4, [x5, :tprel_lo12_nc:sym]
@@ -197,7 +197,7 @@ trickQuestion:
 // CHECK-OBJ: R_AARCH64_TLSLE_LDST32_TPREL_LO12_NC sym
 // CHECK-OBJ: R_AARCH64_TLSLE_LDST32_TPREL_LO12_NC sym
 
-   ldr x28, [x27, #:lo12:sym]
+   ldr x28, [x27, :lo12:sym]
    ldr d26, [x25, #:lo12:sym]
 // CHECK: ldr x28, [x27, :lo12:sym]
 // CHECK: ldr d26, [x25, :lo12:sym]
@@ -205,13 +205,13 @@ trickQuestion:
 // CHECK-OBJ: R_AARCH64_LDST64_ABS_LO12_NC sym
 
    ldr x24, [x23, #:got_lo12:sym]
-   ldr d22, [x21, #:got_lo12:sym]
+   ldr d22, [x21, :got_lo12:sym]
 // CHECK: ldr x24, [x23, :got_lo12:sym]
 // CHECK: ldr d22, [x21, :got_lo12:sym]
 // CHECK-OBJ: R_AARCH64_LD64_GOT_LO12_NC sym
 // CHECK-OBJ: R_AARCH64_LD64_GOT_LO12_NC sym
 
-   ldr x24, [x23, #:dtprel_lo12_nc:sym]
+   ldr x24, [x23, :dtprel_lo12_nc:sym]
    ldr d22, [x21, #:dtprel_lo12:sym]
 // CHECK: ldr x24, [x23, :dtprel_lo12_nc:sym]
 // CHECK: ldr d22, [x21, :dtprel_lo12:sym]
@@ -219,13 +219,13 @@ trickQuestion:
 // CHECK-OBJ: R_AARCH64_TLSLD_LDST64_DTPREL_LO12 sym
 
    ldr x24, [x23, #:tprel_lo12:sym]
-   ldr d22, [x21, #:tprel_lo12_nc:sym]
+   ldr d22, [x21, :tprel_lo12_nc:sym]
 // CHECK: ldr x24, [x23, :tprel_lo12:sym]
 // CHECK: ldr d22, [x21, :tprel_lo12_nc:sym]
 // CHECK-OBJ: R_AARCH64_TLSLE_LDST64_TPREL_LO12 sym
 // CHECK-OBJ: R_AARCH64_TLSLE_LDST64_TPREL_LO12_NC sym
 
-   ldr x24, [x23, #:gottprel_lo12:sym]
+   ldr x24, [x23, :gottprel_lo12:sym]
    ldr d22, [x21, #:gottprel_lo12:sym]
 // CHECK: ldr x24, [x23, :gottprel_lo12:sym]
 // CHECK: ldr d22, [x21, :gottprel_lo12:sym]
@@ -233,7 +233,7 @@ trickQuestion:
 // CHECK-OBJ: R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC sym
 
    ldr x24, [x23, #:tlsdesc_lo12:sym]
-   ldr d22, [x21, #:tlsdesc_lo12:sym]
+   ldr d22, [x21, :tlsdesc_lo12:sym]
 // CHECK: ldr x24, [x23, :tlsdesc_lo12:sym]
 // CHECK: ldr d22, [x21, :tlsdesc_lo12:sym]
 // CHECK-OBJ: R_AARCH64_TLSDESC_LD64_LO12_NC sym
diff --git a/test/MC/ARM64/fp-encoding.s b/test/MC/ARM64/fp-encoding.s
index 08a7b6f027..684d9883e3 100644
--- a/test/MC/ARM64/fp-encoding.s
+++ b/test/MC/ARM64/fp-encoding.s
@@ -333,13 +333,13 @@ foo:
   fmov s2, #0.0
   fmov d2, #0.0
 
-; CHECK: fmov s1, #1.250000e-01      ; encoding: [0x01,0x10,0x28,0x1e]
-; CHECK: fmov s1, #1.250000e-01      ; encoding: [0x01,0x10,0x28,0x1e]
-; CHECK: fmov d1, #1.250000e-01      ; encoding: [0x01,0x10,0x68,0x1e]
-; CHECK: fmov d1, #1.250000e-01      ; encoding: [0x01,0x10,0x68,0x1e]
-; CHECK: fmov d1, #-4.843750e-01     ; encoding: [0x01,0xf0,0x7b,0x1e]
-; CHECK: fmov d1, #4.843750e-01      ; encoding: [0x01,0xf0,0x6b,0x1e]
-; CHECK: fmov d3, #3.000000e+00      ; encoding: [0x03,0x10,0x61,0x1e]
+; CHECK: fmov s1, #0.12500000      ; encoding: [0x01,0x10,0x28,0x1e]
+; CHECK: fmov s1, #0.12500000      ; encoding: [0x01,0x10,0x28,0x1e]
+; CHECK: fmov d1, #0.12500000      ; encoding: [0x01,0x10,0x68,0x1e]
+; CHECK: fmov d1, #0.12500000      ; encoding: [0x01,0x10,0x68,0x1e]
+; CHECK: fmov d1, #-0.48437500     ; encoding: [0x01,0xf0,0x7b,0x1e]
+; CHECK: fmov d1, #0.48437500      ; encoding: [0x01,0xf0,0x6b,0x1e]
+; CHECK: fmov d3, #3.00000000      ; encoding: [0x03,0x10,0x61,0x1e]
 ; CHECK: fmov s2, wzr                ; encoding: [0xe2,0x03,0x27,0x1e]
 ; CHECK: fmov d2, xzr                ; encoding: [0xe2,0x03,0x67,0x9e]
 
diff --git a/test/MC/ARM64/optional-hash.s b/test/MC/ARM64/optional-hash.s
index c67c124c31..71e2fda217 100644
--- a/test/MC/ARM64/optional-hash.s
+++ b/test/MC/ARM64/optional-hash.s
@@ -5,7 +5,7 @@
     add sp, sp, 32
 
 ; Optional shift
-; CHECK: adds x3, x4, #4194304       ; encoding: [0x83,0x00,0x50,0xb1]
+; CHECK: adds x3, x4, #1024, lsl #12 ; encoding: [0x83,0x00,0x50,0xb1]
 adds x3, x4, 1024, lsl 12
 
 ; Optional extend
@@ -13,7 +13,7 @@ adds x3, x4, 1024, lsl 12
 add sp, x2, x3, uxtx 0
 
 ; FP immediates
-; CHECK: fmov s1, #1.250000e-01      ; encoding: [0x01,0x10,0x28,0x1e]
+; CHECK: fmov s1, #0.12500000      ; encoding: [0x01,0x10,0x28,0x1e]
 fmov s1, 0.125
 
 ; Barrier operand
diff --git a/test/MC/ARM64/spsel-sysreg.s b/test/MC/ARM64/spsel-sysreg.s
index e6ff4bf51a..fe556593af 100644
--- a/test/MC/ARM64/spsel-sysreg.s
+++ b/test/MC/ARM64/spsel-sysreg.s
@@ -19,6 +19,6 @@ mrs x0, ESR_EL1
 msr DAIFSet, x0
 msr ESR_EL1, #0
 mrs x0, DAIFSet
+// CHECK-ERRORS: error: expected writable system register or pstate
 // CHECK-ERRORS: error: invalid operand for instruction
-// CHECK-ERRORS: error: invalid operand for instruction
-// CHECK-ERRORS: error: invalid operand for instruction
+// CHECK-ERRORS: error: expected readable system register
diff --git a/test/MC/ARM64/tls-relocs.s b/test/MC/ARM64/tls-relocs.s
index 28c8ad9ef2..681f616d90 100644
--- a/test/MC/ARM64/tls-relocs.s
+++ b/test/MC/ARM64/tls-relocs.s
@@ -313,7 +313,7 @@
 
 // CHECK-ELF:      Symbols [
 // CHECK-ELF:        Symbol {
-// CHECK-ELF:          Name: var (6)
+// CHECK-ELF:          Name: var
 // CHECK-ELF-NEXT:     Value:
 // CHECK-ELF-NEXT:     Size:
 // CHECK-ELF-NEXT:     Binding: Global
diff --git a/test/MC/Disassembler/ARM64/advsimd.txt b/test/MC/Disassembler/ARM64/advsimd.txt
index f9bfc8859c..745ff893aa 100644
--- a/test/MC/Disassembler/ARM64/advsimd.txt
+++ b/test/MC/Disassembler/ARM64/advsimd.txt
@@ -535,18 +535,18 @@
 0x20 0x54 0x00 0x2f
 0x20 0x74 0x00 0x2f
 
-# CHECK: bic.2s v0, #1
-# CHECK: bic.2s v0, #1, lsl #8
-# CHECK: bic.2s v0, #1, lsl #16
-# CHECK: bic.2s v0, #1, lsl #24
+# CHECK: bic.2s v0, #0x1
+# CHECK: bic.2s v0, #0x1, lsl #8
+# CHECK: bic.2s v0, #0x1, lsl #16
+# CHECK: bic.2s v0, #0x1, lsl #24
 
 0x20 0x94 0x00 0x2f
 0x20 0x94 0x00 0x2f
 0x20 0xb4 0x00 0x2f
 
-# CHECK: bic.4h v0, #1
-# CHECK: bic.4h v0, #1
-# FIXME: bic.4h v0, #1, lsl #8
+# CHECK: bic.4h v0, #0x1
+# CHECK: bic.4h v0, #0x1
+# FIXME: bic.4h v0, #0x1, lsl #8
 #    'bic.4h' should be selected over "fcvtnu.2s v0, v1, #0"
 
 0x20 0x14 0x00 0x6f
@@ -554,43 +554,43 @@
 0x20 0x54 0x00 0x6f
 0x20 0x74 0x00 0x6f
 
-# CHECK: bic.4s v0, #1
-# CHECK: bic.4s v0, #1, lsl #8
-# CHECK: bic.4s v0, #1, lsl #16
-# CHECK: bic.4s v0, #1, lsl #24
+# CHECK: bic.4s v0, #0x1
+# CHECK: bic.4s v0, #0x1, lsl #8
+# CHECK: bic.4s v0, #0x1, lsl #16
+# CHECK: bic.4s v0, #0x1, lsl #24
 
 0x20 0x94 0x00 0x6f
 0x20 0xb4 0x00 0x6f
 
-# CHECK: bic.8h v0, #1
-# FIXME: bic.8h v0, #1, lsl #8
+# CHECK: bic.8h v0, #0x1
+# FIXME: bic.8h v0, #0x1, lsl #8
 #    "bic.8h" should be selected over "fcvtnu.4s v0, v1, #0"
 
 0x00 0xf4 0x02 0x6f
 
-# CHECK: fmov.2d v0, #1.250000e-01
+# CHECK: fmov.2d v0, #0.12500000
 
 0x00 0xf4 0x02 0x0f
 0x00 0xf4 0x02 0x4f
 
-# CHECK: fmov.2s v0, #1.250000e-01
-# CHECK: fmov.4s v0, #1.250000e-01
+# CHECK: fmov.2s v0, #0.12500000
+# CHECK: fmov.4s v0, #0.12500000
 
 0x20 0x14 0x00 0x0f
 0x20 0x34 0x00 0x0f
 0x20 0x54 0x00 0x0f
 0x20 0x74 0x00 0x0f
 
-# CHECK: orr.2s v0, #1
-# CHECK: orr.2s v0, #1, lsl #8
-# CHECK: orr.2s v0, #1, lsl #16
-# CHECK: orr.2s v0, #1, lsl #24
+# CHECK: orr.2s v0, #0x1
+# CHECK: orr.2s v0, #0x1, lsl #8
+# CHECK: orr.2s v0, #0x1, lsl #16
+# CHECK: orr.2s v0, #0x1, lsl #24
 
 0x20 0x94 0x00 0x0f
 0x20 0xb4 0x00 0x0f
 
-# CHECK: orr.4h v0, #1
-# FIXME: orr.4h v0, #1, lsl #8
+# CHECK: orr.4h v0, #0x1
+# FIXME: orr.4h v0, #0x1, lsl #8
 #    'orr.4h' should be selected over "fcvtns.2s v0, v1, #0"
 
 0x20 0x14 0x00 0x4f
@@ -598,17 +598,16 @@
 0x20 0x54 0x00 0x4f
 0x20 0x74 0x00 0x4f
 
-# CHECK: orr.4s v0, #1
-# CHECK: orr.4s v0, #1, lsl #8
-# CHECK: orr.4s v0, #1, lsl #16
-# CHECK: orr.4s v0, #1, lsl #24
+# CHECK: orr.4s v0, #0x1
+# CHECK: orr.4s v0, #0x1, lsl #8
+# CHECK: orr.4s v0, #0x1, lsl #16
+# CHECK: orr.4s v0, #0x1, lsl #24
 
 0x20 0x94 0x00 0x4f
 0x20 0xb4 0x00 0x4f
 
-# CHECK: orr.8h v0, #1
-# FIXME: orr.8h v0, #1, lsl #8
-#    "orr.8h" should be selected over "fcvtns.4s v0, v1, #0"
+# CHECK: orr.8h v0, #0x1
+# CHECK: orr.8h v0, #0x1, lsl #8
 
 0x21 0x70 0x40 0x0c
 0x42 0xa0 0x40 0x4c
@@ -1445,82 +1444,82 @@
 
 # CHECK: movi     d0, #0x000000000000ff
 # CHECK: movi.2d  v0, #0x000000000000ff
-# CHECK: movi.8b  v0, #1
-# CHECK: movi.16b v0, #1
+# CHECK: movi.8b  v0, #0x1
+# CHECK: movi.16b v0, #0x1
 
 0x20 0x04 0x00 0x0f
 0x20 0x24 0x00 0x0f
 0x20 0x44 0x00 0x0f
 0x20 0x64 0x00 0x0f
 
-# CHECK: movi.2s v0, #1
-# CHECK: movi.2s v0, #1, lsl #8
-# CHECK: movi.2s v0, #1, lsl #16
-# CHECK: movi.2s v0, #1, lsl #24
+# CHECK: movi.2s v0, #0x1
+# CHECK: movi.2s v0, #0x1, lsl #8
+# CHECK: movi.2s v0, #0x1, lsl #16
+# CHECK: movi.2s v0, #0x1, lsl #24
 
 0x20 0x04 0x00 0x4f
 0x20 0x24 0x00 0x4f
 0x20 0x44 0x00 0x4f
 0x20 0x64 0x00 0x4f
 
-# CHECK: movi.4s v0, #1
-# CHECK: movi.4s v0, #1, lsl #8
-# CHECK: movi.4s v0, #1, lsl #16
-# CHECK: movi.4s v0, #1, lsl #24
+# CHECK: movi.4s v0, #0x1
+# CHECK: movi.4s v0, #0x1, lsl #8
+# CHECK: movi.4s v0, #0x1, lsl #16
+# CHECK: movi.4s v0, #0x1, lsl #24
 
 0x20 0x84 0x00 0x0f
 0x20 0xa4 0x00 0x0f
 
-# CHECK: movi.4h v0, #1
-# CHECK: movi.4h v0, #1, lsl #8
+# CHECK: movi.4h v0, #0x1
+# CHECK: movi.4h v0, #0x1, lsl #8
 
 0x20 0x84 0x00 0x4f
 0x20 0xa4 0x00 0x4f
 
-# CHECK: movi.8h v0, #1
-# CHECK: movi.8h v0, #1, lsl #8
+# CHECK: movi.8h v0, #0x1
+# CHECK: movi.8h v0, #0x1, lsl #8
 
 0x20 0x04 0x00 0x2f
 0x20 0x24 0x00 0x2f
 0x20 0x44 0x00 0x2f
 0x20 0x64 0x00 0x2f
 
-# CHECK: mvni.2s v0, #1
-# CHECK: mvni.2s v0, #1, lsl #8
-# CHECK: mvni.2s v0, #1, lsl #16
-# CHECK: mvni.2s v0, #1, lsl #24
+# CHECK: mvni.2s v0, #0x1
+# CHECK: mvni.2s v0, #0x1, lsl #8
+# CHECK: mvni.2s v0, #0x1, lsl #16
+# CHECK: mvni.2s v0, #0x1, lsl #24
 
 0x20 0x04 0x00 0x6f
 0x20 0x24 0x00 0x6f
 0x20 0x44 0x00 0x6f
 0x20 0x64 0x00 0x6f
 
-# CHECK: mvni.4s v0, #1
-# CHECK: mvni.4s v0, #1, lsl #8
-# CHECK: mvni.4s v0, #1, lsl #16
-# CHECK: mvni.4s v0, #1, lsl #24
+# CHECK: mvni.4s v0, #0x1
+# CHECK: mvni.4s v0, #0x1, lsl #8
+# CHECK: mvni.4s v0, #0x1, lsl #16
+# CHECK: mvni.4s v0, #0x1, lsl #24
 
 0x20 0x84 0x00 0x2f
 0x20 0xa4 0x00 0x2f
 
-# CHECK: mvni.4h v0, #1
-# CHECK: mvni.4h v0, #1, lsl #8
+# CHECK: mvni.4h v0, #0x1
+# CHECK: mvni.4h v0, #0x1, lsl #8
 
 0x20 0x84 0x00 0x6f
 0x20 0xa4 0x00 0x6f
 
-# CHECK: mvni.8h v0, #1
-# CHECK: mvni.8h v0, #1, lsl #8
+# CHECK: mvni.8h v0, #0x1
+# CHECK: mvni.8h v0, #0x1, lsl #8
 
 0x20 0xc4 0x00 0x2f
 0x20 0xd4 0x00 0x2f
 0x20 0xc4 0x00 0x6f
 0x20 0xd4 0x00 0x6f
 
-# CHECK: mvni.2s v0, #1, msl #8
-# CHECK: mvni.2s v0, #1, msl #16
-# CHECK: mvni.4s v0, #1, msl #8
-# CHECK: mvni.4s v0, #1, msl #16
+# CHECK: mvni.2s v0, #0x1, msl #8
+# CHECK: mvni.2s v0, #0x1, msl #16
+# CHECK: mvni.4s v0, #0x1, msl #8
+# CHECK: mvni.4s v0, #0x1, msl #16
 
 0x00 0x88 0x21 0x2e
 0x00 0x98 0x21 0x2e
diff --git a/test/MC/Disassembler/ARM64/arithmetic.txt b/test/MC/Disassembler/ARM64/arithmetic.txt
index d68f43bd33..ffd97702f3 100644
--- a/test/MC/Disassembler/ARM64/arithmetic.txt
+++ b/test/MC/Disassembler/ARM64/arithmetic.txt
@@ -40,8 +40,8 @@
 0x83 0x00 0x40 0x91
 0xff 0x83 0x00 0x91
 
-# CHECK: add w3, w4, #4194304
-# CHECK: add x3, x4, #4194304
+# CHECK: add w3, w4, #1024, lsl #12
+# CHECK: add x3, x4, #1024, lsl #12
 # CHECK: add x3, x4, #0, lsl #12
 # CHECK: add sp, sp, #32
 
@@ -52,9 +52,9 @@
 0xff 0x83 0x00 0xb1
 
 # CHECK: adds w3, w4, #1024
-# CHECK: adds w3, w4, #4194304
+# CHECK: adds w3, w4, #1024, lsl #12
 # CHECK: adds x3, x4, #1024
-# CHECK: adds x3, x4, #4194304
+# CHECK: adds x3, x4, #1024, lsl #12
 # CHECK: cmn  sp, #32
 
 0x83 0x00 0x10 0x51
@@ -64,9 +64,9 @@
 0xff 0x83 0x00 0xd1
 
 # CHECK: sub w3, w4, #1024
-# CHECK: sub w3, w4, #4194304
+# CHECK: sub w3, w4, #1024, lsl #12
 # CHECK: sub x3, x4, #1024
-# CHECK: sub x3, x4, #4194304
+# CHECK: sub x3, x4, #1024, lsl #12
 # CHECK: sub sp, sp, #32
 
 0x83 0x00 0x10 0x71
@@ -76,9 +76,9 @@
 0xff 0x83 0x00 0xf1
 
 # CHECK: subs w3, w4, #1024
-# CHECK: subs w3, w4, #4194304
+# CHECK: subs w3, w4, #1024, lsl #12
 # CHECK: subs x3, x4, #1024
-# CHECK: subs x3, x4, #4194304
+# CHECK: subs x3, x4, #1024, lsl #12
 # CHECK: cmp  sp, #32
 
 #==---------------------------------------------------------------------------==
@@ -368,21 +368,21 @@
 #==---------------------------------------------------------------------------==
 
   0x41 0x28 0xc3 0x1a
-# CHECK: asrv w1, w2, w3
+# CHECK: asr w1, w2, w3
   0x41 0x28 0xc3 0x9a
-# CHECK: asrv x1, x2, x3
+# CHECK: asr x1, x2, x3
   0x41 0x20 0xc3 0x1a
-# CHECK: lslv w1, w2, w3
+# CHECK: lsl w1, w2, w3
   0x41 0x20 0xc3 0x9a
-# CHECK: lslv x1, x2, x3
+# CHECK: lsl x1, x2, x3
   0x41 0x24 0xc3 0x1a
-# CHECK: lsrv w1, w2, w3
+# CHECK: lsr w1, w2, w3
   0x41 0x24 0xc3 0x9a
-# CHECK: lsrv x1, x2, x3
+# CHECK: lsr x1, x2, x3
   0x41 0x2c 0xc3 0x1a
-# CHECK: rorv w1, w2, w3
+# CHECK: ror w1, w2, w3
   0x41 0x2c 0xc3 0x9a
-# CHECK: rorv x1, x2, x3
+# CHECK: ror x1, x2, x3
 
 #==---------------------------------------------------------------------------==
 # One operand instructions
@@ -452,30 +452,30 @@
 0x20 0x00 0xa0 0x52
 0x20 0x00 0xa0 0xd2
 
-# CHECK: movz w0, #1
-# CHECK: movz x0, #1
-# CHECK: movz w0, #1, lsl #16
-# CHECK: movz x0, #1, lsl #16
+# CHECK: movz w0, #0x1
+# CHECK: movz x0, #0x1
+# CHECK: movz w0, #0x1, lsl #16
+# CHECK: movz x0, #0x1, lsl #16
 
 0x40 0x00 0x80 0x12
 0x40 0x00 0x80 0x92
 0x40 0x00 0xa0 0x12
 0x40 0x00 0xa0 0x92
 
-# CHECK: movn w0, #2
-# CHECK: movn x0, #2
-# CHECK: movn w0, #2, lsl #16
-# CHECK: movn x0, #2, lsl #16
+# CHECK: movn w0, #0x2
+# CHECK: movn x0, #0x2
+# CHECK: movn w0, #0x2, lsl #16
+# CHECK: movn x0, #0x2, lsl #16
 
 0x20 0x00 0x80 0x72
 0x20 0x00 0x80 0xf2
 0x20 0x00 0xa0 0x72
 0x20 0x00 0xa0 0xf2
 
-# CHECK: movk w0, #1
-# CHECK: movk x0, #1
-# CHECK: movk w0, #1, lsl #16
-# CHECK: movk x0, #1, lsl #16
+# CHECK: movk w0, #0x1
+# CHECK: movk x0, #0x1
+# CHECK: movk w0, #0x1, lsl #16
+# CHECK: movk x0, #0x1, lsl #16
 
 #==---------------------------------------------------------------------------==
 # Conditionally set flags instructions
diff --git a/test/MC/Disassembler/ARM64/branch.txt b/test/MC/Disassembler/ARM64/branch.txt
index c5b254b736..6af1ad886a 100644
--- a/test/MC/Disassembler/ARM64/branch.txt
+++ b/test/MC/Disassembler/ARM64/branch.txt
@@ -24,21 +24,21 @@
 #-----------------------------------------------------------------------------
 
   0x20 0x00 0x20 0xd4
-# CHECK: brk   #1
+# CHECK: brk   #0x1
   0x41 0x00 0xa0 0xd4
-# CHECK: dcps1 #2
+# CHECK: dcps1 #0x2
   0x62 0x00 0xa0 0xd4
-# CHECK: dcps2 #3
+# CHECK: dcps2 #0x3
   0x83 0x00 0xa0 0xd4
-# CHECK: dcps3 #4
+# CHECK: dcps3 #0x4
   0xa0 0x00 0x40 0xd4
-# CHECK: hlt   #5
+# CHECK: hlt   #0x5
   0xc2 0x00 0x00 0xd4
-# CHECK: hvc   #6
+# CHECK: hvc   #0x6
   0xe3 0x00 0x00 0xd4
-# CHECK: smc   #7
+# CHECK: smc   #0x7
   0x01 0x01 0x00 0xd4
-# CHECK: svc   #8
+# CHECK: svc   #0x8
 
 #-----------------------------------------------------------------------------
 # PC-relative branches (both positive and negative displacement)
diff --git a/test/MC/Disassembler/ARM64/scalar-fp.txt b/test/MC/Disassembler/ARM64/scalar-fp.txt
index 1f76dee64d..f139700164 100644
--- a/test/MC/Disassembler/ARM64/scalar-fp.txt
+++ b/test/MC/Disassembler/ARM64/scalar-fp.txt
@@ -184,10 +184,10 @@
 0x01 0xf0 0x7b 0x1e
 0x01 0xf0 0x6b 0x1e
 
-# CHECK: fmov s1, #1.250000e-01
-# CHECK: fmov d1, #1.250000e-01
-# CHECK: fmov d1, #-4.843750e-01
-# CHECK: fmov d1, #4.843750e-01
+# CHECK: fmov s1, #0.12500000
+# CHECK: fmov d1, #0.12500000
+# CHECK: fmov d1, #-0.48437500
+# CHECK: fmov d1, #0.48437500
 
 0x41 0x40 0x20 0x1e
 0x41 0x40 0x60 0x1e
diff --git a/test/MC/ELF/comdat.s b/test/MC/ELF/comdat.s
index 05d08e1481..68b0f328f9 100644
--- a/test/MC/ELF/comdat.s
+++ b/test/MC/ELF/comdat.s
@@ -49,7 +49,7 @@
 // Test that g1 and g2 are local, but g3 is an undefined global.
 
 // CHECK:        Symbol {
-// CHECK:          Name: g1 (1)
+// CHECK:          Name: g1
 // CHECK-NEXT:     Value: 0x0
 // CHECK-NEXT:     Size: 0
 // CHECK-NEXT:     Binding: Local
@@ -58,7 +58,7 @@
 // CHECK-NEXT:     Section: .foo (0x7)
 // CHECK-NEXT:   }
 // CHECK-NEXT:   Symbol {
-// CHECK-NEXT:     Name: g2 (4)
+// CHECK-NEXT:     Name: g2
 // CHECK-NEXT:     Value: 0x0
 // CHECK-NEXT:     Size: 0
 // CHECK-NEXT:     Binding: Local
@@ -68,7 +68,7 @@
 // CHECK-NEXT:   }
 
 // CHECK:        Symbol {
-// CHECK:          Name: g3 (7)
+// CHECK:          Name: g3
 // CHECK-NEXT:     Value: 0x0
 // CHECK-NEXT:     Size: 0
 // CHECK-NEXT:     Binding: Global
diff --git a/test/MC/ELF/common.s b/test/MC/ELF/common.s
index 9cff927ba5..bd96564a5c 100644
--- a/test/MC/ELF/common.s
+++ b/test/MC/ELF/common.s
@@ -9,7 +9,7 @@
 	.comm	common1,1,1
 
 // CHECK:        Symbol {
-// CHECK:          Name: common1 (1)
+// CHECK:          Name: common1
 // CHECK-NEXT:     Value: 0x0
 // CHECK-NEXT:     Size: 1
 // CHECK-NEXT:     Binding: Local
@@ -25,7 +25,7 @@
 	.comm	common2,1,1
 
 // CHECK:        Symbol {
-// CHECK:          Name: common2 (9)
+// CHECK:          Name: common2
 // CHECK-NEXT:     Value: 0x1
 // CHECK-NEXT:     Size: 1
 // CHECK-NEXT:     Binding: Local
@@ -39,7 +39,7 @@
         .comm	common6,8,16
 
 // CHECK:        Symbol {
-// CHECK:          Name: common6 (17)
+// CHECK:          Name: common6
 // CHECK-NEXT:     Value: 0x10
 // CHECK-NEXT:     Size: 8
 // CHECK-NEXT:     Binding: Local
@@ -54,7 +54,7 @@
 	.comm	common3,4,4
 
 // CHECK:        Symbol {
-// CHECK:          Name: common3 (25)
+// CHECK:          Name: common3
 // CHECK-NEXT:     Value: 0x4
 // CHECK-NEXT:     Size: 4
 // CHECK-NEXT:     Binding: Global
@@ -76,7 +76,7 @@ foo:
 	.comm	common4,40,16
 
 // CHECK:        Symbol {
-// CHECK:          Name: common4 (37)
+// CHECK:          Name: common4
 // CHECK-NEXT:     Value: 0x10
 // CHECK-NEXT:     Size: 40
 // CHECK-NEXT:     Binding: Global
@@ -89,7 +89,7 @@ foo:
         .comm	common5,4,4
 
 // CHECK:        Symbol {
-// CHECK:          Name: common5 (45)
+// CHECK:          Name: common5
 // CHECK-NEXT:     Value: 0x4
 // CHECK-NEXT:     Size: 4
 // CHECK-NEXT:     Binding: Global
diff --git a/test/MC/ELF/file-double.s b/test/MC/ELF/file-double.s
index f9b91edd6f..b5da8c5a85 100644
--- a/test/MC/ELF/file-double.s
+++ b/test/MC/ELF/file-double.s
@@ -11,7 +11,7 @@ foo.c:
 bar.c:
 
 // CHECK:        Symbol {
-// CHECK:          Name: foo.c (1)
+// CHECK:          Name: foo.c
 // CHECK-NEXT:     Value: 0x0
 // CHECK-NEXT:     Size: 0
 // CHECK-NEXT:     Binding: Local
@@ -19,7 +19,7 @@ bar.c:
 // CHECK-NEXT:     Other: 0
 // CHECK-NEXT:     Section: Absolute (0xFFF1)
 // CHECK-NEXT:   }
-// CHECK:          Name: bar.c (7)
+// CHECK:          Name: bar.c
 // CHECK-NEXT:     Value: 0x0
 // CHECK-NEXT:     Size: 0
 // CHECK-NEXT:     Binding: Local
@@ -28,7 +28,7 @@ bar.c:
 // CHECK-NEXT:     Section: Absolute (0xFFF1)
 // CHECK-NEXT:   }
 // CHECK:        Symbol {
-// CHECK:        Name: bar.c (7)
+// CHECK:        Name: bar.c
 // CHECK-NEXT:     Value: 0x0
 // CHECK-NEXT:     Size: 0
 // CHECK-NEXT:     Binding: Global
@@ -37,7 +37,7 @@ bar.c:
 // CHECK-NEXT:     Section: .text (0x1)
 // CHECK-NEXT:   }
 // CHECK:        Symbol {
-// CHECK:        Name: foo.c (1)
+// CHECK:        Name: foo.c
 // CHECK-NEXT:     Value: 0x0
 // CHECK-NEXT:     Size: 0
 // CHECK-NEXT:     Binding: Global
diff --git a/test/MC/ELF/lcomm.s b/test/MC/ELF/lcomm.s
index 430b79b54b..7d8ac3fcaf 100644
--- a/test/MC/ELF/lcomm.s
+++ b/test/MC/ELF/lcomm.s
@@ -4,7 +4,7 @@
 .lcomm B, 32 << 20
 
 // CHECK:        Symbol {
-// CHECK:          Name: A (1)
+// CHECK:          Name: A
 // CHECK-NEXT:     Value: 0x0
 // CHECK-NEXT:     Size: 5
 // CHECK-NEXT:     Binding: Local
@@ -13,7 +13,7 @@
 // CHECK-NEXT:     Section: .bss (0x3)
 // CHECK-NEXT:   }
 // CHECK:        Symbol {
-// CHECK:          Name: B (3)
+// CHECK:          Name: B
 // CHECK-NEXT:     Value: 0x5
 // CHECK-NEXT:     Size: 33554432
 // CHECK-NEXT:     Binding: Local
diff --git a/test/MC/ELF/many-sections-2.s b/test/MC/ELF/many-sections-2.s
index d1f9d008f5..88a4822c38 100644
--- a/test/MC/ELF/many-sections-2.s
+++ b/test/MC/ELF/many-sections-2.s
@@ -12,7 +12,7 @@
 
 
 // Test that both a and b show up in the correct section.
-// SYMBOLS:         Name: a (1)
+// SYMBOLS:         Name: a
 // SYMBOLS-NEXT:    Value: 0x0
 // SYMBOLS-NEXT:    Size: 0
 // SYMBOLS-NEXT:    Binding: Local (0x0)
@@ -21,7 +21,7 @@
 // SYMBOLS-NEXT:    Section: last (0xFF00)
 // SYMBOLS-NEXT:  }
 // SYMBOLS-NEXT:  Symbol {
-// SYMBOLS-NEXT:    Name: b (3)
+// SYMBOLS-NEXT:    Name: b
 // SYMBOLS-NEXT:    Value: 0x1
 // SYMBOLS-NEXT:    Size: 0
 // SYMBOLS-NEXT:    Binding: Local (0x0)
@@ -32,7 +32,7 @@
 
 
 // Test that this file has one section too many.
-// SYMBOLS:         Name: last (0)
+// SYMBOLS:         Name: last
 // SYMBOLS-NEXT:    Value: 0x0
 // SYMBOLS-NEXT:    Size: 0
 // SYMBOLS-NEXT:    Binding: Local (0x0)
diff --git a/test/MC/ELF/offset.s b/test/MC/ELF/offset.s
index a412619143..f448332994 100644
--- a/test/MC/ELF/offset.s
+++ b/test/MC/ELF/offset.s
@@ -71,3 +71,62 @@ sym_f = sym_a + (1 - 1)
 // CHECK-NEXT:    Other: 0
 // CHECK-NEXT:    Section: .data
 // CHECK-NEXT:  }
+
+
+        .globl test2_a
+        .globl test2_b
+        .globl test2_c
+        .globl test2_d
+        .globl test2_e
+test2_a:
+    .long 0
+test2_b = test2_a
+test2_c:
+    .long 0
+test2_d = test2_c
+test2_e = test2_d - test2_b
+// CHECK:      Symbol {
+// CHECK:        Name: test2_a
+// CHECK-NEXT:   Value: 0x5
+// CHECK-NEXT:   Size: 0
+// CHECK-NEXT:   Binding: Global
+// CHECK-NEXT:   Type: None
+// CHECK-NEXT:   Other: 0
+// CHECK-NEXT:   Section: .data
+// CHECK-NEXT: }
+// CHECK-NEXT: Symbol {
+// CHECK-NEXT:   Name: test2_b
+// CHECK-NEXT:   Value: 0x5
+// CHECK-NEXT:   Size: 0
+// CHECK-NEXT:   Binding: Global
+// CHECK-NEXT:   Type: None
+// CHECK-NEXT:   Other: 0
+// CHECK-NEXT:   Section: .data
+// CHECK-NEXT: }
+// CHECK-NEXT: Symbol {
+// CHECK-NEXT:   Name: test2_c
+// CHECK-NEXT:   Value: 0x9
+// CHECK-NEXT:   Size: 0
+// CHECK-NEXT:   Binding: Global
+// CHECK-NEXT:   Type: None
+// CHECK-NEXT:   Other: 0
+// CHECK-NEXT:   Section: .data
+// CHECK-NEXT: }
+// CHECK-NEXT: Symbol {
+// CHECK-NEXT:   Name: test2_d
+// CHECK-NEXT:   Value: 0x9
+// CHECK-NEXT:   Size: 0
+// CHECK-NEXT:   Binding: Global
+// CHECK-NEXT:   Type: None
+// CHECK-NEXT:   Other: 0
+// CHECK-NEXT:   Section: .data
+// CHECK-NEXT: }
+// CHECK-NEXT: Symbol {
+// CHECK-NEXT:   Name: test2_e
+// CHECK-NEXT:   Value: 0x4
+// CHECK-NEXT:   Size: 0
+// CHECK-NEXT:   Binding: Global
+// CHECK-NEXT:   Type: None
+// CHECK-NEXT:   Other: 0
+// CHECK-NEXT:   Section: Absolute
+// CHECK-NEXT: }
diff --git a/test/MC/ELF/pic-diff.s b/test/MC/ELF/pic-diff.s
index 30c92780f1..5f0b1459ba 100644
--- a/test/MC/ELF/pic-diff.s
+++ b/test/MC/ELF/pic-diff.s
@@ -7,7 +7,7 @@
 // CHECK-NEXT: ]
 
 // CHECK:        Symbol {
-// CHECK:          Name: baz (5)
+// CHECK:          Name: baz
 // CHECK-NEXT:     Value: 0x0
 // CHECK-NEXT:     Size: 0
 // CHECK-NEXT:     Binding: Global
diff --git a/test/MC/ELF/pr9292.s b/test/MC/ELF/pr9292.s
index a433650bc6..1e01194c70 100644
--- a/test/MC/ELF/pr9292.s
+++ b/test/MC/ELF/pr9292.s
@@ -8,7 +8,7 @@ mov %eax,bar
 
 
 // CHECK:        Symbol {
-// CHECK:          Name: bar (5)
+// CHECK:          Name: bar
 // CHECK-NEXT:     Value: 0x0
 // CHECK-NEXT:     Size: 0
 // CHECK-NEXT:     Binding: Global
@@ -17,7 +17,7 @@ mov %eax,bar
 // CHECK-NEXT:     Section: Undefined (0x0)
 // CHECK-NEXT:   }
 // CHECK-NEXT:   Symbol {
-// CHECK-NEXT:     Name: foo (1)
+// CHECK-NEXT:     Name: foo
 // CHECK-NEXT:     Value: 0x0
 // CHECK-NEXT:     Size: 0
 // CHECK-NEXT:     Binding: Global
diff --git a/test/MC/ELF/set.s b/test/MC/ELF/set.s
index 80e7e5380a..b4f77f5a09 100644
--- a/test/MC/ELF/set.s
+++ b/test/MC/ELF/set.s
@@ -5,7 +5,7 @@
 .set kernbase,0xffffffff80000000
 
 // CHECK:        Symbol {
-// CHECK:          Name: kernbase (1)
+// CHECK:          Name: kernbase
 // CHECK-NEXT:     Value: 0xFFFFFFFF80000000
 // CHECK-NEXT:     Size: 0
 // CHECK-NEXT:     Binding: Local
@@ -26,7 +26,7 @@
 
 // Test that there is an undefined reference to bar
 // CHECK:        Symbol {
-// CHECK:          Name: bar (10)
+// CHECK:          Name: bar
 // CHECK-NEXT:     Value: 0x0
 // CHECK-NEXT:     Size: 0
 // CHECK-NEXT:     Binding: Global
diff --git a/test/MC/ELF/strtab-suffix-opt.s b/test/MC/ELF/strtab-suffix-opt.s
new file mode 100644
index 0000000000..eb5da8a015
--- /dev/null
+++ b/test/MC/ELF/strtab-suffix-opt.s
@@ -0,0 +1,21 @@
+// RUN: llvm-mc -filetype=obj -triple i686-pc-linux-gnu %s -o - | llvm-readobj -symbols | FileCheck %s
+
+	.text
+	.globl	foobar
+	.align	16, 0x90
+	.type	foobar,@function
+foobar:
+	pushl	%ebp
+	movl	%esp, %ebp
+	subl	$8, %esp
+	calll	foo
+	calll	bar
+	addl	$8, %esp
+	popl	%ebp
+	retl
+.Ltmp3:
+	.size	foobar, .Ltmp3-foobar
+
+// CHECK:     Name: foobar (1)
+// CHECK:     Name: bar (4)
+// CHECK:     Name: foo (8)
diff --git a/test/MC/ELF/symref.s b/test/MC/ELF/symver.s
index 737683bd40..6e5825f243 100644
--- a/test/MC/ELF/symref.s
+++ b/test/MC/ELF/symver.s
@@ -32,111 +32,111 @@ global1:
 // CHECK-NEXT: ]
 
 // CHECK:        Symbol {
-// CHECK:          Name: bar1@zed (19)
+// CHECK:          Name: bar1@zed
 // CHECK-NEXT:     Value: 0x0
 // CHECK-NEXT:     Size: 0
 // CHECK-NEXT:     Binding: Local
 // CHECK-NEXT:     Type: None
 // CHECK-NEXT:     Other: 0
-// CHECK-NEXT:     Section: .text (0x1)
+// CHECK-NEXT:     Section: .text
 // CHECK-NEXT:   }
 // CHECK-NEXT:   Symbol {
-// CHECK-NEXT:     Name: bar3@@zed (37)
+// CHECK-NEXT:     Name: bar3@@zed
 // CHECK-NEXT:     Value: 0x0
 // CHECK-NEXT:     Size: 0
 // CHECK-NEXT:     Binding: Local
 // CHECK-NEXT:     Type: None
 // CHECK-NEXT:     Other: 0
-// CHECK-NEXT:     Section: .text (0x1)
+// CHECK-NEXT:     Section: .text
 // CHECK-NEXT:   }
 // CHECK-NEXT:   Symbol {
-// CHECK-NEXT:     Name: bar5@@zed (47)
+// CHECK-NEXT:     Name: bar5@@zed
 // CHECK-NEXT:     Value: 0x0
 // CHECK-NEXT:     Size: 0
 // CHECK-NEXT:     Binding: Local
 // CHECK-NEXT:     Type: None
 // CHECK-NEXT:     Other: 0
-// CHECK-NEXT:     Section: .text (0x1)
+// CHECK-NEXT:     Section: .text
 // CHECK-NEXT:   }
 // CHECK-NEXT:   Symbol {
-// CHECK-NEXT:     Name: defined1 (1)
+// CHECK-NEXT:     Name: defined1
 // CHECK-NEXT:     Value: 0x0
 // CHECK-NEXT:     Size: 0
 // CHECK-NEXT:     Binding: Local
 // CHECK-NEXT:     Type: None
 // CHECK-NEXT:     Other: 0
-// CHECK-NEXT:     Section: .text (0x1)
+// CHECK-NEXT:     Section: .text
 // CHECK-NEXT:   }
 // CHECK-NEXT:   Symbol {
-// CHECK-NEXT:     Name: defined2 (10)
+// CHECK-NEXT:     Name: defined2
 // CHECK-NEXT:     Value: 0x0
 // CHECK-NEXT:     Size: 0
 // CHECK-NEXT:     Binding: Local
 // CHECK-NEXT:     Type: None
 // CHECK-NEXT:     Other: 0
-// CHECK-NEXT:     Section: .text (0x1)
+// CHECK-NEXT:     Section: .text
 // CHECK-NEXT:   }
 // CHECK-NEXT:   Symbol {
-// CHECK-NEXT:     Name: .text (0)
+// CHECK-NEXT:     Name: .text
 // CHECK-NEXT:     Value: 0x0
 // CHECK-NEXT:     Size: 0
 // CHECK-NEXT:     Binding: Local
 // CHECK-NEXT:     Type: Section
 // CHECK-NEXT:     Other: 0
-// CHECK-NEXT:     Section: .text (0x1)
+// CHECK-NEXT:     Section: .text
 // CHECK-NEXT:   }
 // CHECK-NEXT:   Symbol {
-// CHECK-NEXT:     Name: .data (0)
+// CHECK-NEXT:     Name: .data
 // CHECK-NEXT:     Value: 0x0
 // CHECK-NEXT:     Size: 0
 // CHECK-NEXT:     Binding: Local
 // CHECK-NEXT:     Type: Section
 // CHECK-NEXT:     Other: 0
-// CHECK-NEXT:     Section: .data (0x3)
+// CHECK-NEXT:     Section: .data
 // CHECK-NEXT:   }
 // CHECK-NEXT:   Symbol {
-// CHECK-NEXT:     Name: .bss (0)
+// CHECK-NEXT:     Name: .bss
 // CHECK-NEXT:     Value: 0x0
 // CHECK-NEXT:     Size: 0
 // CHECK-NEXT:     Binding: Local
 // CHECK-NEXT:     Type: Section
 // CHECK-NEXT:     Other: 0
-// CHECK-NEXT:     Section: .bss (0x4)
+// CHECK-NEXT:     Section: .bss
 // CHECK-NEXT:   }
 // CHECK-NEXT:   Symbol {
-// CHECK-NEXT:     Name: g1@@zed (74)
+// CHECK-NEXT:     Name: g1@@zed
 // CHECK-NEXT:     Value: 0x14
 // CHECK-NEXT:     Size: 0
 // CHECK-NEXT:     Binding: Global
 // CHECK-NEXT:     Type: None
 // CHECK-NEXT:     Other: 0
-// CHECK-NEXT:     Section: .text (0x1)
+// CHECK-NEXT:     Section: .text
 // CHECK-NEXT:   }
 // CHECK-NEXT:   Symbol {
-// CHECK-NEXT:     Name: global1 (66)
+// CHECK-NEXT:     Name: global1
 // CHECK-NEXT:     Value: 0x14
 // CHECK-NEXT:     Size: 0
 // CHECK-NEXT:     Binding: Global
 // CHECK-NEXT:     Type: None
 // CHECK-NEXT:     Other: 0
-// CHECK-NEXT:     Section: .text (0x1)
+// CHECK-NEXT:     Section: .text
 // CHECK-NEXT:   }
 // CHECK-NEXT:   Symbol {
-// CHECK-NEXT:     Name: bar2@zed (28)
+// CHECK-NEXT:     Name: bar2@zed
 // CHECK-NEXT:     Value: 0x0
 // CHECK-NEXT:     Size: 0
 // CHECK-NEXT:     Binding: Global
 // CHECK-NEXT:     Type: None
 // CHECK-NEXT:     Other: 0
-// CHECK-NEXT:     Section: Undefined (0x0)
+// CHECK-NEXT:     Section: Undefined
 // CHECK-NEXT:   }
 // CHECK-NEXT:   Symbol {
-// CHECK-NEXT:     Name: bar6@zed (57)
+// CHECK-NEXT:     Name: bar6@zed
 // CHECK-NEXT:     Value: 0x0
 // CHECK-NEXT:     Size: 0
 // CHECK-NEXT:     Binding: Global
 // CHECK-NEXT:     Type: None
 // CHECK-NEXT:     Other: 0
-// CHECK-NEXT:     Section: Undefined (0x0)
+// CHECK-NEXT:     Section: Undefined
 // CHECK-NEXT:   }
 // CHECK-NEXT: ]
diff --git a/test/MC/ELF/tls-i386.s b/test/MC/ELF/tls-i386.s
index 88e96ff667..5ee36681e2 100644
--- a/test/MC/ELF/tls-i386.s
+++ b/test/MC/ELF/tls-i386.s
@@ -18,7 +18,7 @@
         .long   fooE@INDNTPOFF
 
 // CHECK:        Symbol {
-// CHECK:          Name: foo1 (1)
+// CHECK:          Name: foo1
 // CHECK-NEXT:     Value: 0x0
 // CHECK-NEXT:     Size: 0
 // CHECK-NEXT:     Binding: Global
@@ -27,7 +27,7 @@
 // CHECK-NEXT:     Section: Undefined (0x0)
 // CHECK-NEXT:   }
 // CHECK-NEXT:   Symbol {
-// CHECK-NEXT:     Name: foo2 (6)
+// CHECK-NEXT:     Name: foo2
 // CHECK-NEXT:     Value: 0x0
 // CHECK-NEXT:     Size: 0
 // CHECK-NEXT:     Binding: Global
@@ -36,7 +36,7 @@
 // CHECK-NEXT:     Section: Undefined (0x0)
 // CHECK-NEXT:   }
 // CHECK-NEXT:   Symbol {
-// CHECK-NEXT:     Name: foo3 (11)
+// CHECK-NEXT:     Name: foo3
 // CHECK-NEXT:     Value: 0x0
 // CHECK-NEXT:     Size: 0
 // CHECK-NEXT:     Binding: Global
@@ -45,7 +45,7 @@
 // CHECK-NEXT:     Section: Undefined (0x0)
 // CHECK-NEXT:   }
 // CHECK-NEXT:   Symbol {
-// CHECK-NEXT:     Name: foo4 (16)
+// CHECK-NEXT:     Name: foo4
 // CHECK-NEXT:     Value: 0x0
 // CHECK-NEXT:     Size: 0
 // CHECK-NEXT:     Binding: Global
@@ -54,7 +54,7 @@
 // CHECK-NEXT:     Section: Undefined (0x0)
 // CHECK-NEXT:   }
 // CHECK-NEXT:   Symbol {
-// CHECK-NEXT:     Name: foo5 (21)
+// CHECK-NEXT:     Name: foo5
 // CHECK-NEXT:     Value: 0x0
 // CHECK-NEXT:     Size: 0
 // CHECK-NEXT:     Binding: Global
@@ -63,7 +63,7 @@
 // CHECK-NEXT:     Section: Undefined (0x0)
 // CHECK-NEXT:   }
 // CHECK-NEXT:   Symbol {
-// CHECK-NEXT:     Name: foo6 (26)
+// CHECK-NEXT:     Name: foo6
 // CHECK-NEXT:     Value: 0x0
 // CHECK-NEXT:     Size: 0
 // CHECK-NEXT:     Binding: Global
@@ -72,7 +72,7 @@
 // CHECK-NEXT:     Section: Undefined (0x0)
 // CHECK-NEXT:   }
 // CHECK-NEXT:   Symbol {
-// CHECK-NEXT:     Name: foo7 (31)
+// CHECK-NEXT:     Name: foo7
 // CHECK-NEXT:     Value: 0x0
 // CHECK-NEXT:     Size: 0
 // CHECK-NEXT:     Binding: Global
@@ -81,7 +81,7 @@
 // CHECK-NEXT:     Section: Undefined (0x0)
 // CHECK-NEXT:   }
 // CHECK-NEXT:   Symbol {
-// CHECK-NEXT:     Name: foo8 (36)
+// CHECK-NEXT:     Name: foo8
 // CHECK-NEXT:     Value: 0x0
 // CHECK-NEXT:     Size: 0
 // CHECK-NEXT:     Binding: Global
@@ -90,7 +90,7 @@
 // CHECK-NEXT:     Section: Undefined (0x0)
 // CHECK-NEXT:   }
 // CHECK-NEXT:   Symbol {
-// CHECK-NEXT:     Name: foo9 (41)
+// CHECK-NEXT:     Name: foo9
 // CHECK-NEXT:     Value: 0x0
 // CHECK-NEXT:     Size: 0
 // CHECK-NEXT:     Binding: Global
@@ -99,7 +99,7 @@
 // CHECK-NEXT:     Section: Undefined (0x0)
 // CHECK-NEXT:   }
 // CHECK-NEXT:   Symbol {
-// CHECK-NEXT:     Name: fooA (46)
+// CHECK-NEXT:     Name: fooA
 // CHECK-NEXT:     Value: 0x0
 // CHECK-NEXT:     Size: 0
 // CHECK-NEXT:     Binding: Global
@@ -108,7 +108,7 @@
 // CHECK-NEXT:     Section: Undefined (0x0)
 // CHECK-NEXT:   }
 // CHECK-NEXT:   Symbol {
-// CHECK-NEXT:     Name: fooB (51)
+// CHECK-NEXT:     Name: fooB
 // CHECK-NEXT:     Value: 0x0
 // CHECK-NEXT:     Size: 0
 // CHECK-NEXT:     Binding: Global
@@ -117,7 +117,7 @@
 // CHECK-NEXT:     Section: Undefined (0x0)
 // CHECK-NEXT:   }
 // CHECK-NEXT:   Symbol {
-// CHECK-NEXT:     Name: fooC (56)
+// CHECK-NEXT:     Name: fooC
 // CHECK-NEXT:     Value: 0x0
 // CHECK-NEXT:     Size: 0
 // CHECK-NEXT:     Binding: Global
@@ -126,7 +126,7 @@
 // CHECK-NEXT:     Section: Undefined (0x0)
 // CHECK-NEXT:   }
 // CHECK-NEXT:   Symbol {
-// CHECK-NEXT:     Name: fooD (61)
+// CHECK-NEXT:     Name: fooD
 // CHECK-NEXT:     Value: 0x0
 // CHECK-NEXT:     Size: 0
 // CHECK-NEXT:     Binding: Global
@@ -135,7 +135,7 @@
 // CHECK-NEXT:     Section: Undefined (0x0)
 // CHECK-NEXT:   }
 // CHECK-NEXT:   Symbol {
-// CHECK-NEXT:     Name: fooE (66)
+// CHECK-NEXT:     Name: fooE
 // CHECK-NEXT:     Value: 0x0
 // CHECK-NEXT:     Size: 0
 // CHECK-NEXT:     Binding: Global
diff --git a/test/MC/ELF/tls.s b/test/MC/ELF/tls.s
index 6d4b703ace..79865cd17b 100644
--- a/test/MC/ELF/tls.s
+++ b/test/MC/ELF/tls.s
@@ -13,7 +13,7 @@ foobar:
 	.long	43
 
 // CHECK:        Symbol {
-// CHECK:          Name: foobar (31)
+// CHECK:          Name: foobar
 // CHECK-NEXT:     Value: 0x0
 // CHECK-NEXT:     Size: 0
 // CHECK-NEXT:     Binding: Local
@@ -23,7 +23,7 @@ foobar:
 // CHECK-NEXT:   }
 
 // CHECK:        Symbol {
-// CHECK:          Name: foo1 (1)
+// CHECK:          Name: foo1
 // CHECK-NEXT:     Value: 0x0
 // CHECK-NEXT:     Size: 0
 // CHECK-NEXT:     Binding: Global
@@ -32,7 +32,7 @@ foobar:
 // CHECK-NEXT:     Section: Undefined (0x0)
 // CHECK-NEXT:   }
 // CHECK-NEXT:   Symbol {
-// CHECK-NEXT:     Name: foo2 (6)
+// CHECK-NEXT:     Name: foo2
 // CHECK-NEXT:     Value: 0x0
 // CHECK-NEXT:     Size: 0
 // CHECK-NEXT:     Binding: Global
@@ -41,7 +41,7 @@ foobar:
 // CHECK-NEXT:     Section: Undefined (0x0)
 // CHECK-NEXT:   }
 // CHECK-NEXT:   Symbol {
-// CHECK-NEXT:     Name: foo3 (11)
+// CHECK-NEXT:     Name: foo3
 // CHECK-NEXT:     Value: 0x0
 // CHECK-NEXT:     Size: 0
 // CHECK-NEXT:     Binding: Global
@@ -50,7 +50,7 @@ foobar:
 // CHECK-NEXT:     Section: Undefined (0x0)
 // CHECK-NEXT:   }
 // CHECK-NEXT:   Symbol {
-// CHECK-NEXT:     Name: foo4 (16)
+// CHECK-NEXT:     Name: foo4
 // CHECK-NEXT:     Value: 0x0
 // CHECK-NEXT:     Size: 0
 // CHECK-NEXT:     Binding: Global
@@ -59,7 +59,7 @@ foobar:
 // CHECK-NEXT:     Section: Undefined (0x0)
 // CHECK-NEXT:   }
 // CHECK-NEXT:   Symbol {
-// CHECK-NEXT:     Name: foo5 (21)
+// CHECK-NEXT:     Name: foo5
 // CHECK-NEXT:     Value: 0x0
 // CHECK-NEXT:     Size: 0
 // CHECK-NEXT:     Binding: Global
@@ -68,7 +68,7 @@ foobar:
 // CHECK-NEXT:     Section: Undefined (0x0)
 // CHECK-NEXT:   }
 // CHECK-NEXT:   Symbol {
-// CHECK-NEXT:     Name: foo6 (26)
+// CHECK-NEXT:     Name: foo6
 // CHECK-NEXT:     Value: 0x0
 // CHECK-NEXT:     Size: 0
 // CHECK-NEXT:     Binding: Global
diff --git a/test/MC/ELF/type.s b/test/MC/ELF/type.s
index 638d828699..c82d3006cf 100644
--- a/test/MC/ELF/type.s
+++ b/test/MC/ELF/type.s
@@ -176,7 +176,7 @@ alias12:
 // CHECK-NEXT:     Section: .text (0x1)
 // CHECK-NEXT:   }
 // CHECK-NEXT:  Symbol {
-// CHECK-NEXT:    Name: sym1 (54)
+// CHECK-NEXT:    Name: sym1
 // CHECK-NEXT:    Value: 0x0
 // CHECK-NEXT:    Size: 0
 // CHECK-NEXT:    Binding: Global (0x1)
@@ -185,7 +185,7 @@ alias12:
 // CHECK-NEXT:    Section: .text (0x1)
 // CHECK-NEXT:  }
 // CHECK-NEXT:  Symbol {
-// CHECK-NEXT:    Name: sym10 (162)
+// CHECK-NEXT:    Name: sym10
 // CHECK-NEXT:    Value: 0x0
 // CHECK-NEXT:    Size: 0
 // CHECK-NEXT:    Binding: Global (0x1)
@@ -194,7 +194,7 @@ alias12:
 // CHECK-NEXT:    Section: .text (0x1)
 // CHECK-NEXT:  }
 // CHECK-NEXT:  Symbol {
-// CHECK-NEXT:    Name: sym11 (176)
+// CHECK-NEXT:    Name: sym11
 // CHECK-NEXT:    Value: 0x0
 // CHECK-NEXT:    Size: 0
 // CHECK-NEXT:    Binding: Global (0x1)
@@ -203,7 +203,7 @@ alias12:
 // CHECK-NEXT:    Section: .text (0x1)
 // CHECK-NEXT:  }
 // CHECK-NEXT:  Symbol {
-// CHECK-NEXT:    Name: sym12 (190)
+// CHECK-NEXT:    Name: sym12
 // CHECK-NEXT:    Value: 0x0
 // CHECK-NEXT:    Size: 0
 // CHECK-NEXT:    Binding: Global (0x1)
@@ -212,7 +212,7 @@ alias12:
 // CHECK-NEXT:    Section: .text (0x1)
 // CHECK-NEXT:  }
 // CHECK-NEXT:  Symbol {
-// CHECK-NEXT:    Name: sym2 (66)
+// CHECK-NEXT:    Name: sym2
 // CHECK-NEXT:    Value: 0x0
 // CHECK-NEXT:    Size: 0
 // CHECK-NEXT:    Binding: Global (0x1)
@@ -221,7 +221,7 @@ alias12:
 // CHECK-NEXT:    Section: .text (0x1)
 // CHECK-NEXT:  }
 // CHECK-NEXT:  Symbol {
-// CHECK-NEXT:    Name: sym3 (78)
+// CHECK-NEXT:    Name: sym3
 // CHECK-NEXT:    Value: 0x0
 // CHECK-NEXT:    Size: 0
 // CHECK-NEXT:    Binding: Global (0x1)
@@ -230,7 +230,7 @@ alias12:
 // CHECK-NEXT:    Section: .text (0x1)
 // CHECK-NEXT:  }
 // CHECK-NEXT:  Symbol {
-// CHECK-NEXT:    Name: sym4 (90)
+// CHECK-NEXT:    Name: sym4
 // CHECK-NEXT:    Value: 0x0
 // CHECK-NEXT:    Size: 0
 // CHECK-NEXT:    Binding: Global (0x1)
@@ -239,7 +239,7 @@ alias12:
 // CHECK-NEXT:    Section: .text (0x1)
 // CHECK-NEXT:  }
 // CHECK-NEXT:  Symbol {
-// CHECK-NEXT:    Name: sym5 (102)
+// CHECK-NEXT:    Name: sym5
 // CHECK-NEXT:    Value: 0x0
 // CHECK-NEXT:    Size: 0
 // CHECK-NEXT:    Binding: Global (0x1)
@@ -248,7 +248,7 @@ alias12:
 // CHECK-NEXT:    Section: .text (0x1)
 // CHECK-NEXT:  }
 // CHECK-NEXT:  Symbol {
-// CHECK-NEXT:    Name: sym6 (114)
+// CHECK-NEXT:    Name: sym6
 // CHECK-NEXT:    Value: 0x0
 // CHECK-NEXT:    Size: 0
 // CHECK-NEXT:    Binding: Global (0x1)
@@ -257,7 +257,7 @@ alias12:
 // CHECK-NEXT:    Section: .text (0x1)
 // CHECK-NEXT:  }
 // CHECK-NEXT:  Symbol {
-// CHECK-NEXT:    Name: sym7 (126)
+// CHECK-NEXT:    Name: sym7
 // CHECK-NEXT:    Value: 0x0
 // CHECK-NEXT:    Size: 0
 // CHECK-NEXT:    Binding: Global (0x1)
@@ -266,7 +266,7 @@ alias12:
 // CHECK-NEXT:    Section: .text (0x1)
 // CHECK-NEXT:  }
 // CHECK-NEXT:  Symbol {
-// CHECK-NEXT:    Name: sym8 (138)
+// CHECK-NEXT:    Name: sym8
 // CHECK-NEXT:    Value: 0x0
 // CHECK-NEXT:    Size: 0
 // CHECK-NEXT:    Binding: Global (0x1)
@@ -275,7 +275,7 @@ alias12:
 // CHECK-NEXT:    Section: .text (0x1)
 // CHECK-NEXT:  }
 // CHECK-NEXT:  Symbol {
-// CHECK-NEXT:    Name: sym9 (150)
+// CHECK-NEXT:    Name: sym9
 // CHECK-NEXT:    Value: 0x0
 // CHECK-NEXT:    Size: 0
 // CHECK-NEXT:    Binding: Global (0x1)
diff --git a/test/MC/ELF/weakref.s b/test/MC/ELF/weakref.s
index cf2228d8f7..2288264bd6 100644
--- a/test/MC/ELF/weakref.s
+++ b/test/MC/ELF/weakref.s
@@ -80,7 +80,7 @@ bar15:
 // CHECK-NEXT:     Section: Undefined (0x0)
 // CHECK-NEXT:   }
 // CHECK-NEXT:   Symbol {
-// CHECK-NEXT:     Name: bar6 (21)
+// CHECK-NEXT:     Name: bar6
 // CHECK-NEXT:     Value: 0x18
 // CHECK-NEXT:     Size: 0
 // CHECK-NEXT:     Binding: Local
@@ -89,7 +89,7 @@ bar15:
 // CHECK-NEXT:     Section: .text (0x1)
 // CHECK-NEXT:   }
 // CHECK-NEXT:   Symbol {
-// CHECK-NEXT:     Name: bar7 (26)
+// CHECK-NEXT:     Name: bar7
 // CHECK-NEXT:     Value: 0x18
 // CHECK-NEXT:     Size: 0
 // CHECK-NEXT:     Binding: Local
@@ -98,7 +98,7 @@ bar15:
 // CHECK-NEXT:     Section: .text (0x1)
 // CHECK-NEXT:   }
 // CHECK-NEXT:   Symbol {
-// CHECK-NEXT:     Name: bar8 (31)
+// CHECK-NEXT:     Name: bar8
 // CHECK-NEXT:     Value: 0x1C
 // CHECK-NEXT:     Size: 0
 // CHECK-NEXT:     Binding: Local
@@ -107,7 +107,7 @@ bar15:
 // CHECK-NEXT:     Section: .text (0x1)
 // CHECK-NEXT:   }
 // CHECK-NEXT:   Symbol {
-// CHECK-NEXT:     Name: bar9 (36)
+// CHECK-NEXT:     Name: bar9
 // CHECK-NEXT:     Value: 0x20
 // CHECK-NEXT:     Size: 0
 // CHECK-NEXT:     Binding: Local
@@ -116,7 +116,7 @@ bar15:
 // CHECK-NEXT:     Section: .text (0x1)
 // CHECK-NEXT:   }
 // CHECK-NEXT:   Symbol {
-// CHECK-NEXT:     Name: .text (0)
+// CHECK-NEXT:     Name: .text
 // CHECK-NEXT:     Value: 0x0
 // CHECK-NEXT:     Size: 0
 // CHECK-NEXT:     Binding: Local
@@ -125,7 +125,7 @@ bar15:
 // CHECK-NEXT:     Section: .text (0x1)
 // CHECK-NEXT:   }
 // CHECK-NEXT:   Symbol {
-// CHECK-NEXT:     Name: .data (0)
+// CHECK-NEXT:     Name: .data
 // CHECK-NEXT:     Value: 0x0
 // CHECK-NEXT:     Size: 0
 // CHECK-NEXT:     Binding: Local
@@ -134,7 +134,7 @@ bar15:
 // CHECK-NEXT:     Section: .data (0x3)
 // CHECK-NEXT:   }
 // CHECK-NEXT:   Symbol {
-// CHECK-NEXT:     Name: .bss (0)
+// CHECK-NEXT:     Name: .bss
 // CHECK-NEXT:     Value: 0x0
 // CHECK-NEXT:     Size: 0
 // CHECK-NEXT:     Binding: Local
@@ -143,7 +143,7 @@ bar15:
 // CHECK-NEXT:     Section: .bss (0x4)
 // CHECK-NEXT:   }
 // CHECK-NEXT:   Symbol {
-// CHECK-NEXT:     Name: bar10 (41)
+// CHECK-NEXT:     Name: bar10
 // CHECK-NEXT:     Value: 0x28
 // CHECK-NEXT:     Size: 0
 // CHECK-NEXT:     Binding: Global
@@ -152,7 +152,7 @@ bar15:
 // CHECK-NEXT:     Section: .text (0x1)
 // CHECK-NEXT:   }
 // CHECK-NEXT:   Symbol {
-// CHECK-NEXT:     Name: bar11 (47)
+// CHECK-NEXT:     Name: bar11
 // CHECK-NEXT:     Value: 0x30
 // CHECK-NEXT:     Size: 0
 // CHECK-NEXT:     Binding: Global
@@ -161,7 +161,7 @@ bar15:
 // CHECK-NEXT:     Section: .text (0x1)
 // CHECK-NEXT:   }
 // CHECK-NEXT:   Symbol {
-// CHECK-NEXT:     Name: bar12 (53)
+// CHECK-NEXT:     Name: bar12
 // CHECK-NEXT:     Value: 0x30
 // CHECK-NEXT:     Size: 0
 // CHECK-NEXT:     Binding: Global
@@ -170,7 +170,7 @@ bar15:
 // CHECK-NEXT:     Section: .text (0x1)
 // CHECK-NEXT:   }
 // CHECK-NEXT:   Symbol {
-// CHECK-NEXT:     Name: bar13 (59)
+// CHECK-NEXT:     Name: bar13
 // CHECK-NEXT:     Value: 0x34
 // CHECK-NEXT:     Size: 0
 // CHECK-NEXT:     Binding: Global
@@ -179,7 +179,7 @@ bar15:
 // CHECK-NEXT:     Section: .text (0x1)
 // CHECK-NEXT:   }
 // CHECK-NEXT:   Symbol {
-// CHECK-NEXT:     Name: bar14 (65)
+// CHECK-NEXT:     Name: bar14
 // CHECK-NEXT:     Value: 0x38
 // CHECK-NEXT:     Size: 0
 // CHECK-NEXT:     Binding: Global
@@ -188,7 +188,7 @@ bar15:
 // CHECK-NEXT:     Section: .text (0x1)
 // CHECK-NEXT:   }
 // CHECK-NEXT:   Symbol {
-// CHECK-NEXT:     Name: bar15 (71)
+// CHECK-NEXT:     Name: bar15
 // CHECK-NEXT:     Value: 0x40
 // CHECK-NEXT:     Size: 0
 // CHECK-NEXT:     Binding: Global
@@ -197,7 +197,7 @@ bar15:
 // CHECK-NEXT:     Section: .text (0x1)
 // CHECK-NEXT:   }
 // CHECK-NEXT:   Symbol {
-// CHECK-NEXT:     Name: bar2 (1)
+// CHECK-NEXT:     Name: bar2
 // CHECK-NEXT:     Value: 0x0
 // CHECK-NEXT:     Size: 0
 // CHECK-NEXT:     Binding: Global
@@ -206,7 +206,7 @@ bar15:
 // CHECK-NEXT:     Section: Undefined (0x0)
 // CHECK-NEXT:   }
 // CHECK-NEXT:   Symbol {
-// CHECK-NEXT:     Name: bar3 (6)
+// CHECK-NEXT:     Name: bar3
 // CHECK-NEXT:     Value: 0x0
 // CHECK-NEXT:     Size: 0
 // CHECK-NEXT:     Binding: Weak
@@ -215,7 +215,7 @@ bar15:
 // CHECK-NEXT:     Section: Undefined (0x0)
 // CHECK-NEXT:   }
 // CHECK-NEXT:   Symbol {
-// CHECK-NEXT:     Name: bar4 (11)
+// CHECK-NEXT:     Name: bar4
 // CHECK-NEXT:     Value: 0x0
 // CHECK-NEXT:     Size: 0
 // CHECK-NEXT:     Binding: Global
@@ -224,7 +224,7 @@ bar15:
 // CHECK-NEXT:     Section: Undefined (0x0)
 // CHECK-NEXT:   }
 // CHECK-NEXT:   Symbol {
-// CHECK-NEXT:     Name: bar5 (16)
+// CHECK-NEXT:     Name: bar5
 // CHECK-NEXT:     Value: 0x0
 // CHECK-NEXT:     Size: 0
 // CHECK-NEXT:     Binding: Global
diff --git a/test/MC/Mips/cpload-bad.s b/test/MC/Mips/cpload-bad.s
new file mode 100644
index 0000000000..7d186f66f7
--- /dev/null
+++ b/test/MC/Mips/cpload-bad.s
@@ -0,0 +1,15 @@
+# RUN: not llvm-mc %s -arch=mips -mcpu=mips32r2 2>%t1
+# RUN: FileCheck %s < %t1 -check-prefix=ASM
+
+        .text
+        .option pic2
+        .set reorder
+        .cpload $25
+# ASM: :[[@LINE-1]]:9: warning: .cpload in reorder section
+        .set noreorder
+        .cpload $32
+# ASM: :[[@LINE-1]]:17: error: invalid register
+        .cpload $foo
+# ASM: :[[@LINE-1]]:17: error: expected register containing function address
+        .cpload bar
+# ASM: :[[@LINE-1]]:17: error: expected register containing function address
diff --git a/test/MC/Mips/cpload.s b/test/MC/Mips/cpload.s
new file mode 100644
index 0000000000..bc5e79787b
--- /dev/null
+++ b/test/MC/Mips/cpload.s
@@ -0,0 +1,33 @@
+# RUN: llvm-mc %s -arch=mips -mcpu=mips32r2 | FileCheck %s -check-prefix=ASM
+#
+# RUN: llvm-mc %s -arch=mips -mcpu=mips32r2 -filetype=obj -o -| \
+# RUN: llvm-objdump -d -r -arch=mips - | \
+# RUN: FileCheck %s -check-prefix=OBJ
+
+# RUN: llvm-mc %s -arch=mips64 -mcpu=mips64r2 -filetype=obj -o -| \
+# RUN: llvm-objdump -d -r -arch=mips - | \
+# RUN: FileCheck %s -check-prefix=OBJ64
+
+# ASM:    .text
+# ASM:    .option pic2
+# ASM:    .set noreorder
+# ASM:    .cpload $25
+# ASM:    .set reorder
+
+# OBJ:    .text
+# OBJ:    lui $gp, 0
+# OBJ: R_MIPS_HI16 _gp_disp
+# OBJ:    addiu $gp, $gp, 0
+# OBJ: R_MIPS_LO16 _gp_disp
+# OBJ:    addu $gp, $gp, $25
+
+# OBJ64: .text
+# OBJ64-NOT: lui $gp, 0
+# OBJ64-NOT: addiu $gp, $gp, 0
+# OBJ64-NOT: addu $gp, $gp, $25
+
+        .text
+        .option pic2
+        .set noreorder
+        .cpload $25
+        .set reorder
diff --git a/test/MC/Mips/elf-N64.s b/test/MC/Mips/elf-N64.s
index 3c01803d2a..bf6ebd7309 100644
--- a/test/MC/Mips/elf-N64.s
+++ b/test/MC/Mips/elf-N64.s
@@ -1,4 +1,5 @@
 // RUN: llvm-mc -filetype=obj -triple=mips64el-pc-linux -mcpu=mips64  %s -o - | llvm-readobj -r | FileCheck %s
+// RUN: llvm-mc -filetype=obj -triple=mips64-pc-linux -mcpu=mips64  %s -o - | llvm-readobj -r | FileCheck %s
 
 // Check for N64 relocation production.
 // Check that the appropriate relocations were created.
diff --git a/test/MC/Mips/elf-gprel-32-64.s b/test/MC/Mips/elf-gprel-32-64.s
index ae75197a4f..2f5ac6652a 100644
--- a/test/MC/Mips/elf-gprel-32-64.s
+++ b/test/MC/Mips/elf-gprel-32-64.s
@@ -1,6 +1,9 @@
 // RUN: llvm-mc -filetype=obj -triple=mips64el-pc-linux -mcpu=mips64 %s -o - \
 // RUN: | llvm-readobj -r \
 // RUN: | FileCheck %s
+// RUN: llvm-mc -filetype=obj -triple=mips64-pc-linux -mcpu=mips64 %s -o - \
+// RUN: | llvm-readobj -r \
+// RUN: | FileCheck %s
 
 // Check that the appropriate relocations were created.
 
diff --git a/test/MC/Mips/mips1/valid.s b/test/MC/Mips/mips1/valid.s
index fca3c5eb9e..33968f9fe9 100644
--- a/test/MC/Mips/mips1/valid.s
+++ b/test/MC/Mips/mips1/valid.s
@@ -67,18 +67,21 @@
 	sh	$t6,-6704($t7)
 	sll   $a3,18               # CHECK: sll $7, $7, 18         # encoding: [0x00,0x07,0x3c,0x80]
 	sll   $a3,$zero,18         # CHECK: sll $7, $zero, 18      # encoding: [0x00,0x00,0x3c,0x80]
+	sll   $a3,$zero,$t1        # CHECK: sllv $7, $zero, $9     # encoding: [0x01,0x20,0x38,0x04]
 	sllv  $a3,$t1              # CHECK: sllv $7, $7, $9        # encoding: [0x01,0x27,0x38,0x04]
 	sllv  $a3,$zero,$t1        # CHECK: sllv $7, $zero, $9     # encoding: [0x01,0x20,0x38,0x04]
-	slt	$s7,$t3,$k1
-	slti	$s1,$t2,9489
-	sltiu	$t9,$t9,-15531
-	sltu	$s4,$s5,$t3
+	slt   $s7,$11,$k1          # CHECK: slt $23, $11, $27      # encoding: [0x01,0x7b,0xb8,0x2a]
+	slti  $s1,$10,9489         # CHECK: slti $17, $10, 9489    # encoding: [0x29,0x51,0x25,0x11]
+	sltiu $t9,$t9,-15531       # CHECK: sltiu $25, $25, -15531 # encoding: [0x2f,0x39,0xc3,0x55]
+	sltu  $s4,$s5,$11          # CHECK: sltu  $20, $21, $11    # encoding: [0x02,0xab,0xa0,0x2b]
+	sltu  $t8,$t9,-15531       # CHECK: sltiu $24, $25, -15531 # encoding: [0x2f,0x38,0xc3,0x55]
 	sra   $s1,15               # CHECK: sra $17, $17, 15       # encoding: [0x00,0x11,0x8b,0xc3]
 	sra   $s1,$s7,15           # CHECK: sra $17, $23, 15       # encoding: [0x00,0x17,0x8b,0xc3]
 	srav  $s1,$sp              # CHECK: srav $17, $17, $sp     # encoding: [0x03,0xb1,0x88,0x07]
 	srav  $s1,$s7,$sp          # CHECK: srav $17, $23, $sp     # encoding: [0x03,0xb7,0x88,0x07]
 	srl   $2,7                 # CHECK: srl $2, $2, 7          # encoding: [0x00,0x02,0x11,0xc2]
 	srl   $2,$2,7              # CHECK: srl $2, $2, 7          # encoding: [0x00,0x02,0x11,0xc2]
+	srl   $t9,$s4,$a0          # CHECK: srlv $25, $20, $4      # encoding: [0x00,0x94,0xc8,0x06]
 	srlv  $t9,$a0              # CHECK: srlv $25, $25, $4      # encoding: [0x00,0x99,0xc8,0x06]
 	srlv  $t9,$s4,$a0          # CHECK: srlv $25, $20, $4      # encoding: [0x00,0x94,0xc8,0x06]
 	ssnop                      # CHECK: ssnop                  # encoding: [0x00,0x00,0x00,0x40]
diff --git a/test/MC/Mips/mips2/valid.s b/test/MC/Mips/mips2/valid.s
index 954ecfe474..7772a001a3 100644
--- a/test/MC/Mips/mips2/valid.s
+++ b/test/MC/Mips/mips2/valid.s
@@ -79,12 +79,14 @@
 	sh	$t6,-6704($t7)
 	sll   $a3,18               # CHECK: sll $7, $7, 18         # encoding: [0x00,0x07,0x3c,0x80]
 	sll   $a3,$zero,18         # CHECK: sll $7, $zero, 18      # encoding: [0x00,0x00,0x3c,0x80]
+	sll   $a3,$zero,$t1        # CHECK: sllv $7, $zero, $9     # encoding: [0x01,0x20,0x38,0x04]
 	sllv  $a3,$t1              # CHECK: sllv $7, $7, $9        # encoding: [0x01,0x27,0x38,0x04]
 	sllv  $a3,$zero,$t1        # CHECK: sllv $7, $zero, $9     # encoding: [0x01,0x20,0x38,0x04]
-	slt	$s7,$t3,$k1
-	slti	$s1,$t2,9489
-	sltiu	$t9,$t9,-15531
-	sltu	$s4,$s5,$t3
+	slt   $s7,$11,$k1          # CHECK: slt $23, $11, $27      # encoding: [0x01,0x7b,0xb8,0x2a]
+	slti  $s1,$10,9489         # CHECK: slti $17, $10, 9489    # encoding: [0x29,0x51,0x25,0x11]
+	sltiu $t9,$t9,-15531       # CHECK: sltiu $25, $25, -15531 # encoding: [0x2f,0x39,0xc3,0x55]
+	sltu  $s4,$s5,$11          # CHECK: sltu  $20, $21, $11    # encoding: [0x02,0xab,0xa0,0x2b]
+	sltu  $t8,$t9,-15531       # CHECK: sltiu $24, $25, -15531 # encoding: [0x2f,0x38,0xc3,0x55]
 	sqrt.d	$f17,$f22
 	sqrt.s	$f0,$f1
 	sra   $s1,15               # CHECK: sra $17, $17, 15       # encoding: [0x00,0x11,0x8b,0xc3]
@@ -93,6 +95,7 @@
 	srav  $s1,$s7,$sp          # CHECK: srav $17, $23, $sp     # encoding: [0x03,0xb7,0x88,0x07]
 	srl   $2,7                 # CHECK: srl $2, $2, 7          # encoding: [0x00,0x02,0x11,0xc2]
 	srl   $2,$2,7              # CHECK: srl $2, $2, 7          # encoding: [0x00,0x02,0x11,0xc2]
+	srl   $t9,$s4,$a0          # CHECK: srlv $25, $20, $4      # encoding: [0x00,0x94,0xc8,0x06]
 	srlv  $t9,$a0              # CHECK: srlv $25, $25, $4      # encoding: [0x00,0x99,0xc8,0x06]
 	srlv  $t9,$s4,$a0          # CHECK: srlv $25, $20, $4      # encoding: [0x00,0x94,0xc8,0x06]
 	ssnop                      # CHECK: ssnop                  # encoding: [0x00,0x00,0x00,0x40]
diff --git a/test/MC/Mips/mips3/valid.s b/test/MC/Mips/mips3/valid.s
index 4232474e12..ba37441ee6 100644
--- a/test/MC/Mips/mips3/valid.s
+++ b/test/MC/Mips/mips3/valid.s
@@ -47,6 +47,7 @@
 	dmultu	$a1,$a2
 	dsll   $zero,18             # CHECK: dsll $zero, $zero, 18       # encoding: [0x00,0x00,0x04,0xb8]
 	dsll   $zero,$s4,18         # CHECK: dsll $zero, $20, 18         # encoding: [0x00,0x14,0x04,0xb8]
+	dsll   $zero,$s4,$t4        # CHECK: dsllv $zero, $20, $12       # encoding: [0x01,0x94,0x00,0x14]
 	dsll32 $zero,18             # CHECK: dsll32 $zero, $zero, 18     # encoding: [0x00,0x00,0x04,0xbc]
 	dsll32 $zero,$zero,18       # CHECK: dsll32 $zero, $zero, 18     # encoding: [0x00,0x00,0x04,0xbc]
 	dsllv  $zero,$t4            # CHECK: dsllv $zero, $zero, $12     # encoding: [0x01,0x80,0x00,0x14]
@@ -59,6 +60,7 @@
 	dsrav  $gp,$s2,$s3          # CHECK: dsrav $gp, $18, $19         # encoding: [0x02,0x72,0xe0,0x17]
 	dsrl   $s3,23               # CHECK: dsrl $19, $19, 23           # encoding: [0x00,0x13,0x9d,0xfa]
 	dsrl   $s3,$6,23            # CHECK: dsrl $19, $6, 23            # encoding: [0x00,0x06,0x9d,0xfa]
+	dsrl   $s3,$6,$s4           # CHECK: dsrlv $19, $6, $20          # encoding: [0x02,0x86,0x98,0x16]
 	dsrl32 $s3,23               # CHECK: dsrl32 $19, $19, 23         # encoding: [0x00,0x13,0x9d,0xfe]
 	dsrl32 $s3,$6,23            # CHECK: dsrl32 $19, $6, 23          # encoding: [0x00,0x06,0x9d,0xfe]
 	dsrlv  $s3,$s4              # CHECK: dsrlv $19, $19, $20         # encoding: [0x02,0x93,0x98,0x16]
@@ -130,12 +132,14 @@
 	sh	$t6,-6704($t7)
 	sll   $a3,18               # CHECK: sll $7, $7, 18         # encoding: [0x00,0x07,0x3c,0x80]
 	sll   $a3,$zero,18         # CHECK: sll $7, $zero, 18      # encoding: [0x00,0x00,0x3c,0x80]
+	sll   $a3,$zero,$9         # CHECK: sllv $7, $zero, $9     # encoding: [0x01,0x20,0x38,0x04]
 	sllv  $a3,$9               # CHECK: sllv $7, $7, $9        # encoding: [0x01,0x27,0x38,0x04]
 	sllv  $a3,$zero,$9         # CHECK: sllv $7, $zero, $9     # encoding: [0x01,0x20,0x38,0x04]
-	slt	$s7,$t3,$k1
-	slti	$s1,$t2,9489
-	sltiu	$t9,$t9,-15531
-	sltu	$s4,$s5,$t3
+	slt   $s7,$11,$k1          # CHECK: slt $23, $11, $27      # encoding: [0x01,0x7b,0xb8,0x2a]
+	slti  $s1,$10,9489         # CHECK: slti $17, $10, 9489    # encoding: [0x29,0x51,0x25,0x11]
+	sltiu $t9,$t9,-15531       # CHECK: sltiu $25, $25, -15531 # encoding: [0x2f,0x39,0xc3,0x55]
+	sltu  $s4,$s5,$11          # CHECK: sltu  $20, $21, $11    # encoding: [0x02,0xab,0xa0,0x2b]
+	sltu  $t8,$t9,-15531       # CHECK: sltiu $24, $25, -15531 # encoding: [0x2f,0x38,0xc3,0x55]
 	sqrt.d	$f17,$f22
 	sqrt.s	$f0,$f1
 	sra   $s1,15               # CHECK: sra $17, $17, 15       # encoding: [0x00,0x11,0x8b,0xc3]
@@ -144,6 +148,7 @@
 	srav  $s1,$s7,$sp          # CHECK: srav $17, $23, $sp     # encoding: [0x03,0xb7,0x88,0x07]
 	srl   $2,7                 # CHECK: srl $2, $2, 7          # encoding: [0x00,0x02,0x11,0xc2]
 	srl   $2,$2,7              # CHECK: srl $2, $2, 7          # encoding: [0x00,0x02,0x11,0xc2]
+	srl   $t9,$s4,$a0          # CHECK: srlv $25, $20, $4      # encoding: [0x00,0x94,0xc8,0x06]
 	srlv  $t9,$a0              # CHECK: srlv $25, $25, $4      # encoding: [0x00,0x99,0xc8,0x06]
 	srlv  $t9,$s4,$a0          # CHECK: srlv $25, $20, $4      # encoding: [0x00,0x94,0xc8,0x06]
 	ssnop                      # CHECK: ssnop                  # encoding: [0x00,0x00,0x00,0x40]
diff --git a/test/MC/Mips/mips32/valid.s b/test/MC/Mips/mips32/valid.s
index 3eaeb8548a..e13edc1d7e 100644
--- a/test/MC/Mips/mips32/valid.s
+++ b/test/MC/Mips/mips32/valid.s
@@ -103,12 +103,14 @@
 	sh	$t6,-6704($t7)
 	sll   $a3,18               # CHECK: sll $7, $7, 18         # encoding: [0x00,0x07,0x3c,0x80]
 	sll   $a3,$zero,18         # CHECK: sll $7, $zero, 18      # encoding: [0x00,0x00,0x3c,0x80]
+	sll   $a3,$zero,$t1        # CHECK: sllv $7, $zero, $9     # encoding: [0x01,0x20,0x38,0x04]
 	sllv  $a3,$t1              # CHECK: sllv $7, $7, $9        # encoding: [0x01,0x27,0x38,0x04]
 	sllv  $a3,$zero,$t1        # CHECK: sllv $7, $zero, $9     # encoding: [0x01,0x20,0x38,0x04]
-	slt	$s7,$t3,$k1
-	slti	$s1,$t2,9489
-	sltiu	$t9,$t9,-15531
-	sltu	$s4,$s5,$t3
+	slt   $s7,$11,$k1          # CHECK: slt $23, $11, $27      # encoding: [0x01,0x7b,0xb8,0x2a]
+	slti  $s1,$10,9489         # CHECK: slti $17, $10, 9489    # encoding: [0x29,0x51,0x25,0x11]
+	sltiu $t9,$t9,-15531       # CHECK: sltiu $25, $25, -15531 # encoding: [0x2f,0x39,0xc3,0x55]
+	sltu  $s4,$s5,$11          # CHECK: sltu  $20, $21, $11    # encoding: [0x02,0xab,0xa0,0x2b]
+	sltu  $t8,$t9,-15531       # CHECK: sltiu $24, $25, -15531 # encoding: [0x2f,0x38,0xc3,0x55]
 	sqrt.d	$f17,$f22
 	sqrt.s	$f0,$f1
 	sra   $s1,15               # CHECK: sra $17, $17, 15       # encoding: [0x00,0x11,0x8b,0xc3]
@@ -117,6 +119,7 @@
 	srav  $s1,$s7,$sp          # CHECK: srav $17, $23, $sp     # encoding: [0x03,0xb7,0x88,0x07]
 	srl   $2,7                 # CHECK: srl $2, $2, 7          # encoding: [0x00,0x02,0x11,0xc2]
 	srl   $2,$2,7              # CHECK: srl $2, $2, 7          # encoding: [0x00,0x02,0x11,0xc2]
+	srl   $t9,$s4,$a0          # CHECK: srlv $25, $20, $4      # encoding: [0x00,0x94,0xc8,0x06]
 	srlv  $t9,$a0              # CHECK: srlv $25, $25, $4      # encoding: [0x00,0x99,0xc8,0x06]
 	srlv  $t9,$s4,$a0          # CHECK: srlv $25, $20, $4      # encoding: [0x00,0x94,0xc8,0x06]
 	ssnop                      # CHECK: ssnop                  # encoding: [0x00,0x00,0x00,0x40]
diff --git a/test/MC/Mips/mips32r2/valid.s b/test/MC/Mips/mips32r2/valid.s
index 078d9f5436..b30485c881 100644
--- a/test/MC/Mips/mips32r2/valid.s
+++ b/test/MC/Mips/mips32r2/valid.s
@@ -129,12 +129,14 @@
 	sh	$t6,-6704($t7)
 	sll   $a3,18               # CHECK: sll $7, $7, 18         # encoding: [0x00,0x07,0x3c,0x80]
 	sll   $a3,$zero,18         # CHECK: sll $7, $zero, 18      # encoding: [0x00,0x00,0x3c,0x80]
+	sll   $a3,$zero,$t1        # CHECK: sllv $7, $zero, $9     # encoding: [0x01,0x20,0x38,0x04]
 	sllv  $a3,$t1              # CHECK: sllv $7, $7, $9        # encoding: [0x01,0x27,0x38,0x04]
 	sllv  $a3,$zero,$t1        # CHECK: sllv $7, $zero, $9     # encoding: [0x01,0x20,0x38,0x04]
-	slt	$s7,$t3,$k1
-	slti	$s1,$t2,9489
-	sltiu	$t9,$t9,-15531
-	sltu	$s4,$s5,$t3
+	slt   $s7,$11,$k1          # CHECK: slt $23, $11, $27      # encoding: [0x01,0x7b,0xb8,0x2a]
+	slti  $s1,$10,9489         # CHECK: slti $17, $10, 9489    # encoding: [0x29,0x51,0x25,0x11]
+	sltiu $t9,$t9,-15531       # CHECK: sltiu $25, $25, -15531 # encoding: [0x2f,0x39,0xc3,0x55]
+	sltu  $s4,$s5,$11          # CHECK: sltu  $20, $21, $11    # encoding: [0x02,0xab,0xa0,0x2b]
+	sltu  $t8,$t9,-15531       # CHECK: sltiu $24, $25, -15531 # encoding: [0x2f,0x38,0xc3,0x55]
 	sqrt.d	$f17,$f22
 	sqrt.s	$f0,$f1
 	sra   $s1,15               # CHECK: sra $17, $17, 15       # encoding: [0x00,0x11,0x8b,0xc3]
@@ -143,6 +145,7 @@
 	srav  $s1,$s7,$sp          # CHECK: srav $17, $23, $sp     # encoding: [0x03,0xb7,0x88,0x07]
 	srl   $2,7                 # CHECK: srl $2, $2, 7          # encoding: [0x00,0x02,0x11,0xc2]
 	srl   $2,$2,7              # CHECK: srl $2, $2, 7          # encoding: [0x00,0x02,0x11,0xc2]
+	srl   $t9,$s4,$a0          # CHECK: srlv $25, $20, $4      # encoding: [0x00,0x94,0xc8,0x06]
 	srlv  $t9,$a0              # CHECK: srlv $25, $25, $4      # encoding: [0x00,0x99,0xc8,0x06]
 	srlv  $t9,$s4,$a0          # CHECK: srlv $25, $20, $4      # encoding: [0x00,0x94,0xc8,0x06]
 	ssnop                      # CHECK: ssnop                  # encoding: [0x00,0x00,0x00,0x40]
diff --git a/test/MC/Mips/mips4/valid.s b/test/MC/Mips/mips4/valid.s
index e13506ecdd..2b002b9179 100644
--- a/test/MC/Mips/mips4/valid.s
+++ b/test/MC/Mips/mips4/valid.s
@@ -46,6 +46,7 @@
 	dmultu	$a1,$a2
 	dsll  $zero,18             # CHECK: dsll $zero, $zero, 18       # encoding: [0x00,0x00,0x04,0xb8]
 	dsll  $zero,$s4,18         # CHECK: dsll $zero, $20, 18         # encoding: [0x00,0x14,0x04,0xb8]
+	dsll  $zero,$s4,$t4        # CHECK: dsllv $zero, $20, $12       # encoding: [0x01,0x94,0x00,0x14]
 	dsll32 $zero,18            # CHECK: dsll32 $zero, $zero, 18     # encoding: [0x00,0x00,0x04,0xbc]
 	dsll32 $zero,$zero,18      # CHECK: dsll32 $zero, $zero, 18     # encoding: [0x00,0x00,0x04,0xbc]
 	dsllv $zero,$t4            # CHECK: dsllv $zero, $zero, $12     # encoding: [0x01,0x80,0x00,0x14]
@@ -58,6 +59,7 @@
 	dsrav $gp,$s2,$s3          # CHECK: dsrav $gp, $18, $19         # encoding: [0x02,0x72,0xe0,0x17]
 	dsrl  $s3,23               # CHECK: dsrl $19, $19, 23           # encoding: [0x00,0x13,0x9d,0xfa]
 	dsrl  $s3,$6,23            # CHECK: dsrl $19, $6, 23            # encoding: [0x00,0x06,0x9d,0xfa]
+	dsrl  $s3,$6,$s4           # CHECK: dsrlv $19, $6, $20          # encoding: [0x02,0x86,0x98,0x16]
 	dsrl32  $s3,23             # CHECK: dsrl32 $19, $19, 23         # encoding: [0x00,0x13,0x9d,0xfe]
 	dsrl32  $s3,$6,23          # CHECK: dsrl32 $19, $6, 23          # encoding: [0x00,0x06,0x9d,0xfe]
 	dsrlv $s3,$s4              # CHECK: dsrlv $19, $19, $20         # encoding: [0x02,0x93,0x98,0x16]
@@ -146,12 +148,14 @@
 	sh	$t6,-6704($t7)
 	sll   $a3,18               # CHECK: sll $7, $7, 18         # encoding: [0x00,0x07,0x3c,0x80]
 	sll   $a3,$zero,18         # CHECK: sll $7, $zero, 18      # encoding: [0x00,0x00,0x3c,0x80]
+	sll   $a3,$zero,$9         # CHECK: sllv $7, $zero, $9     # encoding: [0x01,0x20,0x38,0x04]
 	sllv  $a3,$9               # CHECK: sllv $7, $7, $9        # encoding: [0x01,0x27,0x38,0x04]
 	sllv  $a3,$zero,$9         # CHECK: sllv $7, $zero, $9     # encoding: [0x01,0x20,0x38,0x04]
-	slt	$s7,$t3,$k1
-	slti	$s1,$t2,9489
-	sltiu	$t9,$t9,-15531
-	sltu	$s4,$s5,$t3
+	slt   $s7,$11,$k1          # CHECK: slt $23, $11, $27      # encoding: [0x01,0x7b,0xb8,0x2a]
+	slti  $s1,$10,9489         # CHECK: slti $17, $10, 9489    # encoding: [0x29,0x51,0x25,0x11]
+	sltiu $t9,$t9,-15531       # CHECK: sltiu $25, $25, -15531 # encoding: [0x2f,0x39,0xc3,0x55]
+	sltu  $s4,$s5,$11          # CHECK: sltu  $20, $21, $11    # encoding: [0x02,0xab,0xa0,0x2b]
+	sltu  $t8,$t9,-15531       # CHECK: sltiu $24, $25, -15531 # encoding: [0x2f,0x38,0xc3,0x55]
 	sqrt.d	$f17,$f22
 	sqrt.s	$f0,$f1
 	sra   $s1,15               # CHECK: sra $17, $17, 15       # encoding: [0x00,0x11,0x8b,0xc3]
@@ -160,6 +164,7 @@
 	srav  $s1,$s7,$sp          # CHECK: srav $17, $23, $sp     # encoding: [0x03,0xb7,0x88,0x07]
 	srl   $2,7                 # CHECK: srl $2, $2, 7          # encoding: [0x00,0x02,0x11,0xc2]
 	srl   $2,$2,7              # CHECK: srl $2, $2, 7          # encoding: [0x00,0x02,0x11,0xc2]
+	srl   $t9,$s4,$a0          # CHECK: srlv $25, $20, $4      # encoding: [0x00,0x94,0xc8,0x06]
 	srlv  $t9,$a0              # CHECK: srlv $25, $25, $4      # encoding: [0x00,0x99,0xc8,0x06]
 	srlv  $t9,$s4,$a0          # CHECK: srlv $25, $20, $4      # encoding: [0x00,0x94,0xc8,0x06]
 	ssnop                      # CHECK: ssnop                  # encoding: [0x00,0x00,0x00,0x40]
diff --git a/test/MC/Mips/mips5/valid.s b/test/MC/Mips/mips5/valid.s
index 2a0f98d949..a65514b769 100644
--- a/test/MC/Mips/mips5/valid.s
+++ b/test/MC/Mips/mips5/valid.s
@@ -47,6 +47,7 @@
 	dmultu	$a1,$a2
 	dsll  $zero,18             # CHECK: dsll $zero, $zero, 18       # encoding: [0x00,0x00,0x04,0xb8]
 	dsll  $zero,$s4,18         # CHECK: dsll $zero, $20, 18         # encoding: [0x00,0x14,0x04,0xb8]
+	dsll  $zero,$s4,$t4        # CHECK: dsllv $zero, $20, $12       # encoding: [0x01,0x94,0x00,0x14]
 	dsll32 $zero,18            # CHECK: dsll32 $zero, $zero, 18     # encoding: [0x00,0x00,0x04,0xbc]
 	dsll32 $zero,$zero,18      # CHECK: dsll32 $zero, $zero, 18     # encoding: [0x00,0x00,0x04,0xbc]
 	dsllv $zero,$t4            # CHECK: dsllv $zero, $zero, $12     # encoding: [0x01,0x80,0x00,0x14]
@@ -59,6 +60,7 @@
 	dsrav $gp,$s2,$s3          # CHECK: dsrav $gp, $18, $19         # encoding: [0x02,0x72,0xe0,0x17]
 	dsrl  $s3,23               # CHECK: dsrl $19, $19, 23           # encoding: [0x00,0x13,0x9d,0xfa]
 	dsrl  $s3,$6,23            # CHECK: dsrl $19, $6, 23            # encoding: [0x00,0x06,0x9d,0xfa]
+	dsrl  $s3,$6,$s4           # CHECK: dsrlv $19, $6, $20          # encoding: [0x02,0x86,0x98,0x16]
 	dsrl32  $s3,23             # CHECK: dsrl32 $19, $19, 23         # encoding: [0x00,0x13,0x9d,0xfe]
 	dsrl32  $s3,$6,23          # CHECK: dsrl32 $19, $6, 23          # encoding: [0x00,0x06,0x9d,0xfe]
 	dsrlv $s3,$s4              # CHECK: dsrlv $19, $19, $20         # encoding: [0x02,0x93,0x98,0x16]
@@ -146,12 +148,14 @@
 	sh	$t6,-6704($t7)
 	sll   $a3,18               # CHECK: sll $7, $7, 18         # encoding: [0x00,0x07,0x3c,0x80]
 	sll   $a3,$zero,18         # CHECK: sll $7, $zero, 18      # encoding: [0x00,0x00,0x3c,0x80]
+	sll   $a3,$zero,$9         # CHECK: sllv $7, $zero, $9     # encoding: [0x01,0x20,0x38,0x04]
 	sllv  $a3,$9               # CHECK: sllv $7, $7, $9        # encoding: [0x01,0x27,0x38,0x04]
 	sllv  $a3,$zero,$9         # CHECK: sllv $7, $zero, $9     # encoding: [0x01,0x20,0x38,0x04]
-	slt	$s7,$t3,$k1
-	slti	$s1,$t2,9489
-	sltiu	$t9,$t9,-15531
-	sltu	$s4,$s5,$t3
+	slt   $s7,$11,$k1          # CHECK: slt $23, $11, $27      # encoding: [0x01,0x7b,0xb8,0x2a]
+	slti  $s1,$10,9489         # CHECK: slti $17, $10, 9489    # encoding: [0x29,0x51,0x25,0x11]
+	sltiu $t9,$t9,-15531       # CHECK: sltiu $25, $25, -15531 # encoding: [0x2f,0x39,0xc3,0x55]
+	sltu  $s4,$s5,$11          # CHECK: sltu  $20, $21, $11    # encoding: [0x02,0xab,0xa0,0x2b]
+	sltu  $t8,$t9,-15531       # CHECK: sltiu $24, $25, -15531 # encoding: [0x2f,0x38,0xc3,0x55]
 	sqrt.d	$f17,$f22
 	sqrt.s	$f0,$f1
 	sra   $s1,15               # CHECK: sra $17, $17, 15       # encoding: [0x00,0x11,0x8b,0xc3]
@@ -160,6 +164,7 @@
 	srav  $s1,$s7,$sp          # CHECK: srav $17, $23, $sp     # encoding: [0x03,0xb7,0x88,0x07]
 	srl   $2,7                 # CHECK: srl $2, $2, 7          # encoding: [0x00,0x02,0x11,0xc2]
 	srl   $2,$2,7              # CHECK: srl $2, $2, 7          # encoding: [0x00,0x02,0x11,0xc2]
+	srl   $t9,$s4,$a0          # CHECK: srlv $25, $20, $4      # encoding: [0x00,0x94,0xc8,0x06]
 	srlv  $t9,$a0              # CHECK: srlv $25, $25, $4      # encoding: [0x00,0x99,0xc8,0x06]
 	srlv  $t9,$s4,$a0          # CHECK: srlv $25, $20, $4      # encoding: [0x00,0x94,0xc8,0x06]
 	ssnop                      # CHECK: ssnop                  # encoding: [0x00,0x00,0x00,0x40]
diff --git a/test/MC/Mips/mips64/valid.s b/test/MC/Mips/mips64/valid.s
index 6446d18304..04c2f5b6f9 100644
--- a/test/MC/Mips/mips64/valid.s
+++ b/test/MC/Mips/mips64/valid.s
@@ -51,6 +51,7 @@
 	dmultu	$a1,$a2
 	dsll  $zero,18             # CHECK: dsll $zero, $zero, 18       # encoding: [0x00,0x00,0x04,0xb8]
 	dsll  $zero,$s4,18         # CHECK: dsll $zero, $20, 18         # encoding: [0x00,0x14,0x04,0xb8]
+	dsll  $zero,$s4,$t4        # CHECK: dsllv $zero, $20, $12       # encoding: [0x01,0x94,0x00,0x14]
 	dsll32 $zero,18            # CHECK: dsll32 $zero, $zero, 18     # encoding: [0x00,0x00,0x04,0xbc]
 	dsll32 $zero,$zero,18      # CHECK: dsll32 $zero, $zero, 18     # encoding: [0x00,0x00,0x04,0xbc]
 	dsllv $zero,$t4            # CHECK: dsllv $zero, $zero, $12     # encoding: [0x01,0x80,0x00,0x14]
@@ -63,6 +64,7 @@
 	dsrav $gp,$s2,$s3          # CHECK: dsrav $gp, $18, $19         # encoding: [0x02,0x72,0xe0,0x17]
 	dsrl  $s3,23               # CHECK: dsrl $19, $19, 23           # encoding: [0x00,0x13,0x9d,0xfa]
 	dsrl  $s3,$6,23            # CHECK: dsrl $19, $6, 23            # encoding: [0x00,0x06,0x9d,0xfa]
+	dsrl  $s3,$6,$s4           # CHECK: dsrlv $19, $6, $20          # encoding: [0x02,0x86,0x98,0x16]
 	dsrl32  $s3,23             # CHECK: dsrl32 $19, $19, 23         # encoding: [0x00,0x13,0x9d,0xfe]
 	dsrl32  $s3,$6,23          # CHECK: dsrl32 $19, $6, 23          # encoding: [0x00,0x06,0x9d,0xfe]
 	dsrlv $s3,$s4              # CHECK: dsrlv $19, $19, $20         # encoding: [0x02,0x93,0x98,0x16]
@@ -159,12 +161,14 @@
 	sh	$t6,-6704($t7)
 	sll   $a3,18               # CHECK: sll $7, $7, 18         # encoding: [0x00,0x07,0x3c,0x80]
 	sll   $a3,$zero,18         # CHECK: sll $7, $zero, 18      # encoding: [0x00,0x00,0x3c,0x80]
+	sll   $a3,$zero,$9         # CHECK: sllv $7, $zero, $9     # encoding: [0x01,0x20,0x38,0x04]
 	sllv  $a3,$9               # CHECK: sllv $7, $7, $9        # encoding: [0x01,0x27,0x38,0x04]
 	sllv  $a3,$zero,$9         # CHECK: sllv $7, $zero, $9     # encoding: [0x01,0x20,0x38,0x04]
-	slt	$s7,$t3,$k1
-	slti	$s1,$t2,9489
-	sltiu	$t9,$t9,-15531
-	sltu	$s4,$s5,$t3
+	slt   $s7,$11,$k1          # CHECK: slt $23, $11, $27      # encoding: [0x01,0x7b,0xb8,0x2a]
+	slti  $s1,$10,9489         # CHECK: slti $17, $10, 9489    # encoding: [0x29,0x51,0x25,0x11]
+	sltiu $t9,$t9,-15531       # CHECK: sltiu $25, $25, -15531 # encoding: [0x2f,0x39,0xc3,0x55]
+	sltu  $s4,$s5,$11          # CHECK: sltu  $20, $21, $11    # encoding: [0x02,0xab,0xa0,0x2b]
+	sltu  $t8,$t9,-15531       # CHECK: sltiu $24, $25, -15531 # encoding: [0x2f,0x38,0xc3,0x55]
 	sqrt.d	$f17,$f22
 	sqrt.s	$f0,$f1
 	sra   $s1,15               # CHECK: sra $17, $17, 15       # encoding: [0x00,0x11,0x8b,0xc3]
@@ -173,6 +177,7 @@
 	srav  $s1,$s7,$sp          # CHECK: srav $17, $23, $sp     # encoding: [0x03,0xb7,0x88,0x07]
 	srl   $2,7                 # CHECK: srl $2, $2, 7          # encoding: [0x00,0x02,0x11,0xc2]
 	srl   $2,$2,7              # CHECK: srl $2, $2, 7          # encoding: [0x00,0x02,0x11,0xc2]
+	srl   $t9,$s4,$a0          # CHECK: srlv $25, $20, $4      # encoding: [0x00,0x94,0xc8,0x06]
 	srlv  $t9,$a0              # CHECK: srlv $25, $25, $4      # encoding: [0x00,0x99,0xc8,0x06]
 	srlv  $t9,$s4,$a0          # CHECK: srlv $25, $20, $4      # encoding: [0x00,0x94,0xc8,0x06]
 	ssnop                      # CHECK: ssnop                  # encoding: [0x00,0x00,0x00,0x40]
diff --git a/test/MC/Mips/mips64r2/valid.s b/test/MC/Mips/mips64r2/valid.s
index 97aa9aad72..99f19f68a4 100644
--- a/test/MC/Mips/mips64r2/valid.s
+++ b/test/MC/Mips/mips64r2/valid.s
@@ -60,6 +60,7 @@
 	dshd	$v0,$sp
 	dsll  $zero,18             # CHECK: dsll $zero, $zero, 18       # encoding: [0x00,0x00,0x04,0xb8]
 	dsll  $zero,$s4,18         # CHECK: dsll $zero, $20, 18         # encoding: [0x00,0x14,0x04,0xb8]
+	dsll  $zero,$s4,$t4        # CHECK: dsllv $zero, $20, $12       # encoding: [0x01,0x94,0x00,0x14]
 	dsll32 $zero,18            # CHECK: dsll32 $zero, $zero, 18     # encoding: [0x00,0x00,0x04,0xbc]
 	dsll32 $zero,$zero,18      # CHECK: dsll32 $zero, $zero, 18     # encoding: [0x00,0x00,0x04,0xbc]
 	dsllv $zero,$t4            # CHECK: dsllv $zero, $zero, $12     # encoding: [0x01,0x80,0x00,0x14]
@@ -72,6 +73,7 @@
 	dsrav $gp,$s2,$s3          # CHECK: dsrav $gp, $18, $19         # encoding: [0x02,0x72,0xe0,0x17]
 	dsrl  $s3,23               # CHECK: dsrl $19, $19, 23           # encoding: [0x00,0x13,0x9d,0xfa]
 	dsrl  $s3,$6,23            # CHECK: dsrl $19, $6, 23            # encoding: [0x00,0x06,0x9d,0xfa]
+	dsrl  $s3,$6,$s4           # CHECK: dsrlv $19, $6, $20          # encoding: [0x02,0x86,0x98,0x16]
 	dsrl32  $s3,23             # CHECK: dsrl32 $19, $19, 23         # encoding: [0x00,0x13,0x9d,0xfe]
 	dsrl32  $s3,$6,23          # CHECK: dsrl32 $19, $6, 23          # encoding: [0x00,0x06,0x9d,0xfe]
 	dsrlv $s3,$s4              # CHECK: dsrlv $19, $19, $20         # encoding: [0x02,0x93,0x98,0x16]
@@ -183,12 +185,14 @@
 	sh	$t6,-6704($t7)
 	sll   $a3,18               # CHECK: sll $7, $7, 18         # encoding: [0x00,0x07,0x3c,0x80]
 	sll   $a3,$zero,18         # CHECK: sll $7, $zero, 18      # encoding: [0x00,0x00,0x3c,0x80]
+	sll   $a3,$zero,$9         # CHECK: sllv $7, $zero, $9     # encoding: [0x01,0x20,0x38,0x04]
 	sllv  $a3,$9               # CHECK: sllv $7, $7, $9        # encoding: [0x01,0x27,0x38,0x04]
 	sllv  $a3,$zero,$9         # CHECK: sllv $7, $zero, $9     # encoding: [0x01,0x20,0x38,0x04]
-	slt	$s7,$t3,$k1
-	slti	$s1,$t2,9489
-	sltiu	$t9,$t9,-15531
-	sltu	$s4,$s5,$t3
+	slt   $s7,$11,$k1          # CHECK: slt $23, $11, $27      # encoding: [0x01,0x7b,0xb8,0x2a]
+	slti  $s1,$10,9489         # CHECK: slti $17, $10, 9489    # encoding: [0x29,0x51,0x25,0x11]
+	sltiu $t9,$t9,-15531       # CHECK: sltiu $25, $25, -15531 # encoding: [0x2f,0x39,0xc3,0x55]
+	sltu  $s4,$s5,$11          # CHECK: sltu  $20, $21, $11    # encoding: [0x02,0xab,0xa0,0x2b]
+	sltu  $t8,$t9,-15531       # CHECK: sltiu $24, $25, -15531 # encoding: [0x2f,0x38,0xc3,0x55]
 	sqrt.d	$f17,$f22
 	sqrt.s	$f0,$f1
 	sra   $s1,15               # CHECK: sra $17, $17, 15       # encoding: [0x00,0x11,0x8b,0xc3]
@@ -197,6 +201,7 @@
 	srav  $s1,$s7,$sp          # CHECK: srav $17, $23, $sp     # encoding: [0x03,0xb7,0x88,0x07]
 	srl   $2,7                 # CHECK: srl $2, $2, 7          # encoding: [0x00,0x02,0x11,0xc2]
 	srl   $2,$2,7              # CHECK: srl $2, $2, 7          # encoding: [0x00,0x02,0x11,0xc2]
+	srl   $t9,$s4,$a0          # CHECK: srlv $25, $20, $4      # encoding: [0x00,0x94,0xc8,0x06]
 	srlv  $t9,$a0              # CHECK: srlv $25, $25, $4      # encoding: [0x00,0x99,0xc8,0x06]
 	srlv  $t9,$s4,$a0          # CHECK: srlv $25, $20, $4      # encoding: [0x00,0x94,0xc8,0x06]
 	ssnop                      # CHECK: ssnop                  # encoding: [0x00,0x00,0x00,0x40]
diff --git a/test/Transforms/InstCombine/vec_demanded_elts.ll b/test/Transforms/InstCombine/vec_demanded_elts.ll
index a3e978141a..41d2b292ee 100644
--- a/test/Transforms/InstCombine/vec_demanded_elts.ll
+++ b/test/Transforms/InstCombine/vec_demanded_elts.ll
@@ -318,7 +318,7 @@ define <4 x float> @test_vpermilvar_ps(<4 x float> %v) {
 declare <8 x float> @llvm.x86.avx.vpermilvar.ps.256(<8 x float>, <8 x i32>)
 define <8 x float> @test_vpermilvar_ps_256(<8 x float> %v) {
 ; CHECK-LABEL: @test_vpermilvar_ps_256(
-; CHECK: shufflevector <8 x float> %v, <8 x float> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
+; CHECK: shufflevector <8 x float> %v, <8 x float> undef, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4>
   %a = tail call <8 x float> @llvm.x86.avx.vpermilvar.ps.256(<8 x float> %v, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>)
   ret <8 x float> %a
 }
@@ -327,15 +327,43 @@ declare <2 x double> @llvm.x86.avx.vpermilvar.pd(<2 x double>, <2 x i32>)
 define <2 x double> @test_vpermilvar_pd(<2 x double> %v) {
 ; CHECK-LABEL: @test_vpermilvar_pd(
 ; CHECK: shufflevector <2 x double> %v, <2 x double> undef, <2 x i32> <i32 1, i32 0>
-  %a = tail call <2 x double> @llvm.x86.avx.vpermilvar.pd(<2 x double> %v, <2 x i32> <i32 1, i32 0>)
+  %a = tail call <2 x double> @llvm.x86.avx.vpermilvar.pd(<2 x double> %v, <2 x i32> <i32 2, i32 0>)
   ret <2 x double> %a
 }
 
 declare <4 x double> @llvm.x86.avx.vpermilvar.pd.256(<4 x double>, <4 x i32>)
 define <4 x double> @test_vpermilvar_pd_256(<4 x double> %v) {
 ; CHECK-LABEL: @test_vpermilvar_pd_256(
-; CHECK: shufflevector <4 x double> %v, <4 x double> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
-  %a = tail call <4 x double> @llvm.x86.avx.vpermilvar.pd.256(<4 x double> %v, <4 x i32> <i32 3, i32 2, i32 1, i32 0>)
+; CHECK: shufflevector <4 x double> %v, <4 x double> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
+  %a = tail call <4 x double> @llvm.x86.avx.vpermilvar.pd.256(<4 x double> %v, <4 x i32> <i32 3, i32 1, i32 2, i32 0>)
+  ret <4 x double> %a
+}
+
+define <4 x float> @test_vpermilvar_ps_zero(<4 x float> %v) {
+; CHECK-LABEL: @test_vpermilvar_ps_zero(
+; CHECK: shufflevector <4 x float> %v, <4 x float> undef, <4 x i32> zeroinitializer
+  %a = tail call <4 x float> @llvm.x86.avx.vpermilvar.ps(<4 x float> %v, <4 x i32> zeroinitializer)
+  ret <4 x float> %a
+}
+
+define <8 x float> @test_vpermilvar_ps_256_zero(<8 x float> %v) {
+; CHECK-LABEL: @test_vpermilvar_ps_256_zero(
+; CHECK: shufflevector <8 x float> %v, <8 x float> undef, <8 x i32> <i32 0, i32 0, i32 0, i32 0, i32 4, i32 4, i32 4, i32 4>
+  %a = tail call <8 x float> @llvm.x86.avx.vpermilvar.ps.256(<8 x float> %v, <8 x i32> zeroinitializer)
+  ret <8 x float> %a
+}
+
+define <2 x double> @test_vpermilvar_pd_zero(<2 x double> %v) {
+; CHECK-LABEL: @test_vpermilvar_pd_zero(
+; CHECK: shufflevector <2 x double> %v, <2 x double> undef, <2 x i32> zeroinitializer
+  %a = tail call <2 x double> @llvm.x86.avx.vpermilvar.pd(<2 x double> %v, <2 x i32> zeroinitializer)
+  ret <2 x double> %a
+}
+
+define <4 x double> @test_vpermilvar_pd_256_zero(<4 x double> %v) {
+; CHECK-LABEL: @test_vpermilvar_pd_256_zero(
+; CHECK: shufflevector <4 x double> %v, <4 x double> undef, <4 x i32> <i32 0, i32 0, i32 2, i32 2>
+  %a = tail call <4 x double> @llvm.x86.avx.vpermilvar.pd.256(<4 x double> %v, <4 x i32> zeroinitializer)
   ret <4 x double> %a
 }
 
diff --git a/test/Transforms/LoopStrengthReduce/ARM64/lit.local.cfg b/test/Transforms/LoopStrengthReduce/ARM64/lit.local.cfg
index f8162f04c5..a49957999f 100644
--- a/test/Transforms/LoopStrengthReduce/ARM64/lit.local.cfg
+++ b/test/Transforms/LoopStrengthReduce/ARM64/lit.local.cfg
@@ -1,4 +1,4 @@
-config.suffixes = ['.ll' '.c']
+config.suffixes = ['.ll']
 
 targets = set(config.root.targets_to_build.split())
 if not 'ARM64' in targets:
diff --git a/test/Transforms/LoopStrengthReduce/ARM64/req-regs.c b/test/Transforms/LoopStrengthReduce/ARM64/req-regs.c
deleted file mode 100644
index 0c3c1dd503..0000000000
--- a/test/Transforms/LoopStrengthReduce/ARM64/req-regs.c
+++ /dev/null
@@ -1,36 +0,0 @@
-// RUN: clang %s -O3 -target arm64-apple-ios -o - -S -mllvm -debug-only=loop-reduce 2>&1| FileCheck %s
-// REQUIRES: asserts
-
-// LSR used to fail here due to a bug in the ReqRegs test.  To complicate
-// things, this could only be reproduced with clang because the uses would
-// come out in different order when invoked through llc.
-
-// CHECK: The chosen solution requires
-// CHECK-NOT: No Satisfactory Solution
-
-typedef unsigned long iter_t;
-void use_int(int result);
-
-struct _state {
- int N;
- int M;
- int K;
- double* data;
-};
-void
-do_integer_add(iter_t iterations, void* cookie)
-{
-    struct _state *pState = (struct _state*)cookie;
-    register int i;
-    register int a = pState->N + 57;
-
-    while (iterations-- > 0) {
-        for (i = 1; i < 1001; ++i) {
-          a=a+a+i; a=a+a+i; a=a+a+i; a=a+a+i;
-          a=a+a+i; a=a+a+i; a=a+a+i; a=a+a+i;
-          a=a+a+i; a=a+a+i;
-
-        }
-    }
-    use_int(a);
-}
diff --git a/test/Transforms/LoopUnroll/loop-remarks.ll b/test/Transforms/LoopUnroll/loop-remarks.ll
new file mode 100644
index 0000000000..ff3ac17836
--- /dev/null
+++ b/test/Transforms/LoopUnroll/loop-remarks.ll
@@ -0,0 +1,25 @@
+; RUN: opt < %s -S -loop-unroll -pass-remarks=loop-unroll -unroll-count=16 2>&1 | FileCheck -check-prefix=COMPLETE-UNROLL %s
+; RUN: opt < %s -S -loop-unroll -pass-remarks=loop-unroll -unroll-count=4 2>&1 | FileCheck -check-prefix=PARTIAL-UNROLL %s
+
+; COMPLETE-UNROLL: remark: {{.*}}: completely unrolled loop with 16 iterations
+; PARTIAL-UNROLL: remark: {{.*}}: unrolled loop by a factor of 4
+
+define i32 @sum() {
+entry:
+  br label %for.body
+
+for.body:                                         ; preds = %for.body, %entry
+  %s.06 = phi i32 [ 0, %entry ], [ %add1, %for.body ]
+  %i.05 = phi i32 [ 0, %entry ], [ %inc, %for.body ]
+  %add = add nsw i32 %i.05, 4
+  %call = tail call i32 @baz(i32 %add) #2
+  %add1 = add nsw i32 %call, %s.06
+  %inc = add nsw i32 %i.05, 1
+  %exitcond = icmp eq i32 %inc, 16
+  br i1 %exitcond, label %for.end, label %for.body
+
+for.end:                                          ; preds = %for.body
+  ret i32 %add1
+}
+
+declare i32 @baz(i32)
diff --git a/test/Transforms/LoopVectorize/X86/vect.omp.force.ll b/test/Transforms/LoopVectorize/X86/vect.omp.force.ll
new file mode 100644
index 0000000000..84ffb2721e
--- /dev/null
+++ b/test/Transforms/LoopVectorize/X86/vect.omp.force.ll
@@ -0,0 +1,93 @@
+; RUN: opt < %s  -loop-vectorize -mtriple=x86_64-apple-macosx10.8.0 -mcpu=corei7-avx -debug-only=loop-vectorize -stats -S 2>&1 | FileCheck %s
+; REQUIRES: asserts
+
+; CHECK: LV: Loop hints: force=enabled
+; CHECK: LV: Loop hints: force=?
+; No more loops in the module
+; CHECK-NOT: LV: Loop hints: force=
+; CHECK: 2 loop-vectorize               - Number of loops analyzed for vectorization
+; CHECK: 1 loop-vectorize               - Number of loops vectorized
+
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
+target triple = "x86_64-apple-macosx10.8.0"
+
+;
+; The source code for the test:
+;
+; #include <math.h>
+; void foo(float* restrict A, float * restrict B, int size)
+; {
+;   for (int i = 0; i < size; ++i) A[i] = sinf(B[i]);
+; }
+;
+
+;
+; This loop will be vectorized, although the scalar cost is lower than any of vector costs, but vectorization is explicitly forced in metadata.
+;
+
+define void @vectorized(float* noalias nocapture %A, float* noalias nocapture %B, i32 %size) {
+entry:
+  %cmp6 = icmp sgt i32 %size, 0
+  br i1 %cmp6, label %for.body.preheader, label %for.end
+
+for.body.preheader:
+  br label %for.body
+
+for.body:
+  %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %for.body.preheader ]
+  %arrayidx = getelementptr inbounds float* %B, i64 %indvars.iv
+  %0 = load float* %arrayidx, align 4, !llvm.mem.parallel_loop_access !1
+  %call = tail call float @llvm.sin.f32(float %0)
+  %arrayidx2 = getelementptr inbounds float* %A, i64 %indvars.iv
+  store float %call, float* %arrayidx2, align 4, !llvm.mem.parallel_loop_access !1
+  %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
+  %lftr.wideiv = trunc i64 %indvars.iv.next to i32
+  %exitcond = icmp eq i32 %lftr.wideiv, %size
+  br i1 %exitcond, label %for.end.loopexit, label %for.body, !llvm.loop !1
+
+for.end.loopexit:
+  br label %for.end
+
+for.end:
+  ret void
+}
+
+!1 = metadata !{metadata !1, metadata !2}
+!2 = metadata !{metadata !"llvm.vectorizer.enable", i1 true}
+
+;
+; This method will not be vectorized, as scalar cost is lower than any of vector costs.
+;
+
+define void @not_vectorized(float* noalias nocapture %A, float* noalias nocapture %B, i32 %size) {
+entry:
+  %cmp6 = icmp sgt i32 %size, 0
+  br i1 %cmp6, label %for.body.preheader, label %for.end
+
+for.body.preheader:
+  br label %for.body
+
+for.body:
+  %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %for.body.preheader ]
+  %arrayidx = getelementptr inbounds float* %B, i64 %indvars.iv
+  %0 = load float* %arrayidx, align 4, !llvm.mem.parallel_loop_access !3
+  %call = tail call float @llvm.sin.f32(float %0)
+  %arrayidx2 = getelementptr inbounds float* %A, i64 %indvars.iv
+  store float %call, float* %arrayidx2, align 4, !llvm.mem.parallel_loop_access !3
+  %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
+  %lftr.wideiv = trunc i64 %indvars.iv.next to i32
+  %exitcond = icmp eq i32 %lftr.wideiv, %size
+  br i1 %exitcond, label %for.end.loopexit, label %for.body, !llvm.loop !3
+
+for.end.loopexit:
+  br label %for.end
+
+for.end:
+  ret void
+}
+
+declare float @llvm.sin.f32(float) nounwind readnone
+
+; Dummy metadata
+!3 = metadata !{metadata !3}
+
diff --git a/test/Transforms/LoopVectorize/X86/vect.omp.force.small-tc.ll b/test/Transforms/LoopVectorize/X86/vect.omp.force.small-tc.ll
new file mode 100644
index 0000000000..1b979e5871
--- /dev/null
+++ b/test/Transforms/LoopVectorize/X86/vect.omp.force.small-tc.ll
@@ -0,0 +1,73 @@
+; RUN: opt < %s -loop-vectorize -mtriple=x86_64-apple-macosx10.8.0 -mcpu=corei7-avx -debug-only=loop-vectorize -stats -S -vectorizer-min-trip-count=21 2>&1 | FileCheck %s
+; REQUIRES: asserts
+
+; CHECK: LV: Loop hints: force=enabled
+; CHECK: LV: Loop hints: force=?
+; No more loops in the module
+; CHECK-NOT: LV: Loop hints: force=
+; CHECK: 2 loop-vectorize               - Number of loops analyzed for vectorization
+; CHECK: 1 loop-vectorize               - Number of loops vectorized
+
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
+target triple = "x86_64-apple-macosx10.8.0"
+
+;
+; The source code for the test:
+;
+; void foo(float* restrict A, float* restrict B)
+; {
+;     for (int i = 0; i < 20; ++i) A[i] += B[i];
+; }
+;
+
+;
+; This loop will be vectorized, although the trip count is below the threshold, but vectorization is explicitly forced in metadata.
+;
+define void @vectorized(float* noalias nocapture %A, float* noalias nocapture readonly %B) {
+entry:
+  br label %for.body
+
+for.body:
+  %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
+  %arrayidx = getelementptr inbounds float* %B, i64 %indvars.iv
+  %0 = load float* %arrayidx, align 4, !llvm.mem.parallel_loop_access !1
+  %arrayidx2 = getelementptr inbounds float* %A, i64 %indvars.iv
+  %1 = load float* %arrayidx2, align 4, !llvm.mem.parallel_loop_access !1
+  %add = fadd fast float %0, %1
+  store float %add, float* %arrayidx2, align 4, !llvm.mem.parallel_loop_access !1
+  %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
+  %exitcond = icmp eq i64 %indvars.iv.next, 20
+  br i1 %exitcond, label %for.end, label %for.body, !llvm.loop !1
+
+for.end:
+  ret void
+}
+
+!1 = metadata !{metadata !1, metadata !2}
+!2 = metadata !{metadata !"llvm.vectorizer.enable", i1 true}
+
+;
+; This loop will not be vectorized as the trip count is below the threshold.
+;
+define void @not_vectorized(float* noalias nocapture %A, float* noalias nocapture readonly %B) {
+entry:
+  br label %for.body
+
+for.body:
+  %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
+  %arrayidx = getelementptr inbounds float* %B, i64 %indvars.iv
+  %0 = load float* %arrayidx, align 4, !llvm.mem.parallel_loop_access !3
+  %arrayidx2 = getelementptr inbounds float* %A, i64 %indvars.iv
+  %1 = load float* %arrayidx2, align 4, !llvm.mem.parallel_loop_access !3
+  %add = fadd fast float %0, %1
+  store float %add, float* %arrayidx2, align 4, !llvm.mem.parallel_loop_access !3
+  %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
+  %exitcond = icmp eq i64 %indvars.iv.next, 20
+  br i1 %exitcond, label %for.end, label %for.body, !llvm.loop !3
+
+for.end:
+  ret void
+}
+
+!3 = metadata !{metadata !3}
+
diff --git a/test/Transforms/LoopVectorize/X86/vectorization-remarks.ll b/test/Transforms/LoopVectorize/X86/vectorization-remarks.ll
new file mode 100644
index 0000000000..685d034f21
--- /dev/null
+++ b/test/Transforms/LoopVectorize/X86/vectorization-remarks.ll
@@ -0,0 +1,67 @@
+; RUN: opt < %s -loop-vectorize -mtriple=x86_64-unknown-linux -S -pass-remarks='loop-vectorize' 2>&1 | FileCheck -check-prefix=VECTORIZED %s
+; RUN: opt < %s -loop-vectorize -force-vector-width=1 -force-vector-unroll=4 -mtriple=x86_64-unknown-linux -S -pass-remarks='.*vectorize.*' 2>&1 | FileCheck -check-prefix=UNROLLED %s
+
+; VECTORIZED: remark: {{.*}}.c:17:8: vectorized loop (vectorization factor: 4, unrolling interleave factor: 1)
+; UNROLLED: remark: {{.*}}.c:17:8: unrolled with interleaving factor 4 (vectorization not beneficial)
+
+target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
+
+define i32 @foo(i32 %n) #0 {
+entry:
+  %diff = alloca i32, align 4
+  %cb = alloca [16 x i8], align 16
+  %cc = alloca [16 x i8], align 16
+  store i32 0, i32* %diff, align 4, !dbg !10, !tbaa !11
+  br label %for.body, !dbg !15
+
+for.body:                                         ; preds = %for.body, %entry
+  %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
+  %add8 = phi i32 [ 0, %entry ], [ %add, %for.body ], !dbg !19
+  %arrayidx = getelementptr inbounds [16 x i8]* %cb, i64 0, i64 %indvars.iv, !dbg !19
+  %0 = load i8* %arrayidx, align 1, !dbg !19, !tbaa !21
+  %conv = sext i8 %0 to i32, !dbg !19
+  %arrayidx2 = getelementptr inbounds [16 x i8]* %cc, i64 0, i64 %indvars.iv, !dbg !19
+  %1 = load i8* %arrayidx2, align 1, !dbg !19, !tbaa !21
+  %conv3 = sext i8 %1 to i32, !dbg !19
+  %sub = sub i32 %conv, %conv3, !dbg !19
+  %add = add nsw i32 %sub, %add8, !dbg !19
+  %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1, !dbg !15
+  %exitcond = icmp eq i64 %indvars.iv.next, 16, !dbg !15
+  br i1 %exitcond, label %for.end, label %for.body, !dbg !15
+
+for.end:                                          ; preds = %for.body
+  store i32 %add, i32* %diff, align 4, !dbg !19, !tbaa !11
+  call void @ibar(i32* %diff) #2, !dbg !22
+  ret i32 0, !dbg !23
+}
+
+declare void @ibar(i32*) #1
+
+!llvm.dbg.cu = !{!0}
+!llvm.module.flags = !{!7, !8}
+!llvm.ident = !{!9}
+
+!0 = metadata !{i32 786449, metadata !1, i32 12, metadata !"clang version 3.5.0 ", i1 true, metadata !"", i32 0, metadata !2, metadata !2, metadata !3, metadata !2, metadata !2, metadata !"", i32 2} ; [ DW_TAG_compile_unit ] [./vectorization-remarks.c] [DW_LANG_C99]
+!1 = metadata !{metadata !"vectorization-remarks.c", metadata !"."}
+!2 = metadata !{}
+!3 = metadata !{metadata !4}
+!4 = metadata !{i32 786478, metadata !1, metadata !5, metadata !"foo", metadata !"foo", metadata !"", i32 5, metadata !6, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 true, i32 (i32)* @foo, null, null, metadata !2, i32 6} ; [ DW_TAG_subprogram ] [line 5] [def] [scope 6] [foo]
+!5 = metadata !{i32 786473, metadata !1}          ; [ DW_TAG_file_type ] [./vectorization-remarks.c]
+!6 = metadata !{i32 786453, i32 0, null, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !2, i32 0, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!7 = metadata !{i32 2, metadata !"Dwarf Version", i32 4}
+!8 = metadata !{i32 1, metadata !"Debug Info Version", i32 1}
+!9 = metadata !{metadata !"clang version 3.5.0 "}
+!10 = metadata !{i32 8, i32 3, metadata !4, null} ; [ DW_TAG_imported_declaration ]
+!11 = metadata !{metadata !12, metadata !12, i64 0}
+!12 = metadata !{metadata !"int", metadata !13, i64 0}
+!13 = metadata !{metadata !"omnipotent char", metadata !14, i64 0}
+!14 = metadata !{metadata !"Simple C/C++ TBAA"}
+!15 = metadata !{i32 17, i32 8, metadata !16, null}
+!16 = metadata !{i32 786443, metadata !1, metadata !17, i32 17, i32 8, i32 2, i32 3} ; [ DW_TAG_lexical_block ] [./vectorization-remarks.c]
+!17 = metadata !{i32 786443, metadata !1, metadata !18, i32 17, i32 8, i32 1, i32 2} ; [ DW_TAG_lexical_block ] [./vectorization-remarks.c]
+!18 = metadata !{i32 786443, metadata !1, metadata !4, i32 17, i32 3, i32 0, i32 0} ; [ DW_TAG_lexical_block ] [./vectorization-remarks.c]
+!19 = metadata !{i32 18, i32 5, metadata !20, null}
+!20 = metadata !{i32 786443, metadata !1, metadata !18, i32 17, i32 27, i32 0, i32 1} ; [ DW_TAG_lexical_block ] [./vectorization-remarks.c]
+!21 = metadata !{metadata !13, metadata !13, i64 0}
+!22 = metadata !{i32 20, i32 3, metadata !4, null}
+!23 = metadata !{i32 21, i32 3, metadata !4, null}
diff --git a/test/Transforms/SLPVectorizer/X86/continue_vectorizing.ll b/test/Transforms/SLPVectorizer/X86/continue_vectorizing.ll
new file mode 100644
index 0000000000..ed225743a6
--- /dev/null
+++ b/test/Transforms/SLPVectorizer/X86/continue_vectorizing.ll
@@ -0,0 +1,31 @@
+; RUN: opt < %s -basicaa -slp-vectorizer -S -mtriple=x86_64-apple-macosx10.8.0 -mcpu=corei7-avx | FileCheck %s
+
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
+target triple = "x86_64-apple-macosx10.8.0"
+
+; We will keep trying to vectorize the basic block even we already find vectorized store.
+; CHECK: test1
+; CHECK: store <2 x double>
+; CHECK: ret
+define void @test1(double* %a, double* %b, double* %c, double* %d) {
+entry:
+  %i0 = load double* %a, align 8
+  %i1 = load double* %b, align 8
+  %mul = fmul double %i0, %i1
+  %arrayidx3 = getelementptr inbounds double* %a, i64 1
+  %i3 = load double* %arrayidx3, align 8
+  %arrayidx4 = getelementptr inbounds double* %b, i64 1
+  %i4 = load double* %arrayidx4, align 8
+  %mul5 = fmul double %i3, %i4
+  store double %mul, double* %c, align 8
+  %arrayidx5 = getelementptr inbounds double* %c, i64 1
+  store double %mul5, double* %arrayidx5, align 8
+  %0 = bitcast double* %a to <4 x i32>*
+  %1 = load <4 x i32>* %0, align 8
+  %2 = bitcast double* %b to <4 x i32>*
+  %3 = load <4 x i32>* %2, align 8
+  %4 = mul <4 x i32> %1, %3
+  %5 = bitcast double* %d to <4 x i32>*
+  store <4 x i32> %4, <4 x i32>* %5, align 8
+  ret void
+}
diff --git a/tools/llc/llc.cpp b/tools/llc/llc.cpp
index 6dc5a32263..6ddda20441 100644
--- a/tools/llc/llc.cpp
+++ b/tools/llc/llc.cpp
@@ -28,6 +28,7 @@
 #include "llvm/PassManager.h"
 #include "llvm/Support/CommandLine.h"
 #include "llvm/Support/Debug.h"
+#include "llvm/Support/FileSystem.h"
 #include "llvm/Support/FormattedStream.h"
 #include "llvm/Support/Host.h"
 #include "llvm/Support/ManagedStatic.h"
diff --git a/tools/lli/lli.cpp b/tools/lli/lli.cpp
index f1413f302a..4cde10579c 100644
--- a/tools/lli/lli.cpp
+++ b/tools/lli/lli.cpp
@@ -534,7 +534,7 @@ int main(int argc, char **argv, char * const *envp) {
       Err.print(argv[0], errs());
       return 1;
     }
-    EE->addObjectFile(Obj.get());
+    EE->addObjectFile(std::unique_ptr<object::ObjectFile>(Obj.get()));
   }
 
   for (unsigned i = 0, e = ExtraArchives.size(); i != e; ++i) {
diff --git a/tools/llvm-as/llvm-as.cpp b/tools/llvm-as/llvm-as.cpp
index 70c95080e9..007241c506 100644
--- a/tools/llvm-as/llvm-as.cpp
+++ b/tools/llvm-as/llvm-as.cpp
@@ -21,6 +21,7 @@
 #include "llvm/IR/Module.h"
 #include "llvm/IR/Verifier.h"
 #include "llvm/Support/CommandLine.h"
+#include "llvm/Support/FileSystem.h"
 #include "llvm/Support/ManagedStatic.h"
 #include "llvm/Support/PrettyStackTrace.h"
 #include "llvm/Support/Signals.h"
diff --git a/tools/llvm-dis/llvm-dis.cpp b/tools/llvm-dis/llvm-dis.cpp
index 2c9322ea56..0df7328ffc 100644
--- a/tools/llvm-dis/llvm-dis.cpp
+++ b/tools/llvm-dis/llvm-dis.cpp
@@ -25,6 +25,7 @@
 #include "llvm/IR/Type.h"
 #include "llvm/Support/CommandLine.h"
 #include "llvm/Support/DataStream.h"
+#include "llvm/Support/FileSystem.h"
 #include "llvm/Support/FormattedStream.h"
 #include "llvm/Support/ManagedStatic.h"
 #include "llvm/Support/MemoryBuffer.h"
diff --git a/tools/llvm-extract/llvm-extract.cpp b/tools/llvm-extract/llvm-extract.cpp
index 4131177bd4..769f82a057 100644
--- a/tools/llvm-extract/llvm-extract.cpp
+++ b/tools/llvm-extract/llvm-extract.cpp
@@ -22,6 +22,7 @@
 #include "llvm/IRReader/IRReader.h"
 #include "llvm/PassManager.h"
 #include "llvm/Support/CommandLine.h"
+#include "llvm/Support/FileSystem.h"
 #include "llvm/Support/ManagedStatic.h"
 #include "llvm/Support/PrettyStackTrace.h"
 #include "llvm/Support/Regex.h"
diff --git a/tools/llvm-link/llvm-link.cpp b/tools/llvm-link/llvm-link.cpp
index a756a1c33a..ed8c06e798 100644
--- a/tools/llvm-link/llvm-link.cpp
+++ b/tools/llvm-link/llvm-link.cpp
@@ -19,6 +19,7 @@
 #include "llvm/IR/Verifier.h"
 #include "llvm/IRReader/IRReader.h"
 #include "llvm/Support/CommandLine.h"
+#include "llvm/Support/FileSystem.h"
 #include "llvm/Support/ManagedStatic.h"
 #include "llvm/Support/Path.h"
 #include "llvm/Support/PrettyStackTrace.h"
diff --git a/tools/llvm-lto/llvm-lto.cpp b/tools/llvm-lto/llvm-lto.cpp
index 678e4db08f..8c2d1cdfbb 100644
--- a/tools/llvm-lto/llvm-lto.cpp
+++ b/tools/llvm-lto/llvm-lto.cpp
@@ -17,6 +17,7 @@
 #include "llvm/LTO/LTOCodeGenerator.h"
 #include "llvm/LTO/LTOModule.h"
 #include "llvm/Support/CommandLine.h"
+#include "llvm/Support/FileSystem.h"
 #include "llvm/Support/ManagedStatic.h"
 #include "llvm/Support/PrettyStackTrace.h"
 #include "llvm/Support/Signals.h"
diff --git a/tools/llvm-profdata/llvm-profdata.cpp b/tools/llvm-profdata/llvm-profdata.cpp
index 17710f64ae..fdde32ac6b 100644
--- a/tools/llvm-profdata/llvm-profdata.cpp
+++ b/tools/llvm-profdata/llvm-profdata.cpp
@@ -15,6 +15,7 @@
 #include "llvm/ProfileData/InstrProfReader.h"
 #include "llvm/ProfileData/InstrProfWriter.h"
 #include "llvm/Support/CommandLine.h"
+#include "llvm/Support/FileSystem.h"
 #include "llvm/Support/Format.h"
 #include "llvm/Support/ManagedStatic.h"
 #include "llvm/Support/MemoryBuffer.h"
diff --git a/tools/llvm-stress/llvm-stress.cpp b/tools/llvm-stress/llvm-stress.cpp
index b7bcae7b73..23d3b636b1 100644
--- a/tools/llvm-stress/llvm-stress.cpp
+++ b/tools/llvm-stress/llvm-stress.cpp
@@ -22,6 +22,7 @@
 #include "llvm/IR/Verifier.h"
 #include "llvm/PassManager.h"
 #include "llvm/Support/Debug.h"
+#include "llvm/Support/FileSystem.h"
 #include "llvm/Support/ManagedStatic.h"
 #include "llvm/Support/PluginLoader.h"
 #include "llvm/Support/PrettyStackTrace.h"
diff --git a/tools/opt/opt.cpp b/tools/opt/opt.cpp
index 9b3ce9bdbe..6f0fbf66b7 100644
--- a/tools/opt/opt.cpp
+++ b/tools/opt/opt.cpp
@@ -35,6 +35,7 @@
 #include "llvm/MC/SubtargetFeature.h"
 #include "llvm/PassManager.h"
 #include "llvm/Support/Debug.h"
+#include "llvm/Support/FileSystem.h"
 #include "llvm/Support/ManagedStatic.h"
 #include "llvm/Support/PluginLoader.h"
 #include "llvm/Support/PrettyStackTrace.h"
diff --git a/tools/yaml2obj/yaml2elf.cpp b/tools/yaml2obj/yaml2elf.cpp
index acbac9c605..c78e1dbe77 100644
--- a/tools/yaml2obj/yaml2elf.cpp
+++ b/tools/yaml2obj/yaml2elf.cpp
@@ -30,10 +30,8 @@ using namespace llvm;
 // This class has a deliberately small interface, since a lot of
 // implementation variation is possible.
 //
-// TODO: Use an ordered container with a suffix-based comparison in order
-// to deduplicate suffixes. std::map<> with a custom comparator is likely
-// to be the simplest implementation, but a suffix trie could be more
-// suitable for the job.
+// TODO: Use the StringTable builder from lib/Object instead, since it
+// will deduplicate suffixes.
 namespace {
 class StringTableBuilder {
   /// \brief Indices of strings currently present in `Buf`.
diff --git a/unittests/ADT/PointerUnionTest.cpp b/unittests/ADT/PointerUnionTest.cpp
index 7eb718112d..3bfb79cee4 100644
--- a/unittests/ADT/PointerUnionTest.cpp
+++ b/unittests/ADT/PointerUnionTest.cpp
@@ -13,22 +13,24 @@ using namespace llvm;
 
 namespace {
 
-typedef PointerUnion<int*, float*> PU;
+typedef PointerUnion<int *, float *> PU;
 
-// Test fixture
-class PointerUnionTest : public testing::Test {
-};
+struct PointerUnionTest : public testing::Test {
+  float f;
+  int i;
 
-float f = 3.14f;
-int i = 42;
+  PU a, b, c, n;
 
-const PU a(&f);
-const PU b(&i);
-const PU n;
+  PointerUnionTest() : f(3.14f), i(42), a(&f), b(&i), c(&i), n() {}
+};
 
 TEST_F(PointerUnionTest, Comparison) {
+  EXPECT_TRUE(a == a);
+  EXPECT_FALSE(a != a);
   EXPECT_TRUE(a != b);
   EXPECT_FALSE(a == b);
+  EXPECT_TRUE(b == c);
+  EXPECT_FALSE(b != c);
   EXPECT_TRUE(b != n);
   EXPECT_FALSE(b == n);
 }
@@ -44,21 +46,27 @@ TEST_F(PointerUnionTest, Null) {
   EXPECT_TRUE((bool)a);
   EXPECT_TRUE((bool)b);
   EXPECT_FALSE(n);
+
+  EXPECT_NE(n, b);
+  EXPECT_EQ(b, c);
+  b = nullptr;
+  EXPECT_EQ(n, b);
+  EXPECT_NE(b, c);
 }
 
 TEST_F(PointerUnionTest, Is) {
-  EXPECT_FALSE(a.is<int*>());
-  EXPECT_TRUE(a.is<float*>());
-  EXPECT_TRUE(b.is<int*>());
-  EXPECT_FALSE(b.is<float*>());
-  EXPECT_TRUE(n.is<int*>());
-  EXPECT_FALSE(n.is<float*>());
+  EXPECT_FALSE(a.is<int *>());
+  EXPECT_TRUE(a.is<float *>());
+  EXPECT_TRUE(b.is<int *>());
+  EXPECT_FALSE(b.is<float *>());
+  EXPECT_TRUE(n.is<int *>());
+  EXPECT_FALSE(n.is<float *>());
 }
 
 TEST_F(PointerUnionTest, Get) {
-  EXPECT_EQ(a.get<float*>(), &f);
-  EXPECT_EQ(b.get<int*>(), &i);
-  EXPECT_EQ(n.get<int*>(), (int*)0);
+  EXPECT_EQ(a.get<float *>(), &f);
+  EXPECT_EQ(b.get<int *>(), &i);
+  EXPECT_EQ(n.get<int *>(), (int *)0);
 }
 
 } // end anonymous namespace
diff --git a/unittests/ADT/SmallVectorTest.cpp b/unittests/ADT/SmallVectorTest.cpp
index 90c7982699..58f55914ba 100644
--- a/unittests/ADT/SmallVectorTest.cpp
+++ b/unittests/ADT/SmallVectorTest.cpp
@@ -29,27 +29,43 @@ private:
   static int numDestructorCalls;
   static int numAssignmentCalls;
 
+  bool constructed;
   int value;
 
 public:
-  Constructable() : value(0) {
+  Constructable() : constructed(true), value(0) {
     ++numConstructorCalls;
   }
 
-  Constructable(int val) : value(val) {
+  Constructable(int val) : constructed(true), value(val) {
     ++numConstructorCalls;
   }
 
-  Constructable(const Constructable & src) {
+  Constructable(const Constructable & src) : constructed(true) {
+    value = src.value;
+    ++numConstructorCalls;
+  }
+
+  Constructable(Constructable && src) : constructed(true) {
     value = src.value;
     ++numConstructorCalls;
   }
 
   ~Constructable() {
+    EXPECT_TRUE(constructed);
     ++numDestructorCalls;
+    constructed = false;
   }
 
   Constructable & operator=(const Constructable & src) {
+    EXPECT_TRUE(constructed);
+    value = src.value;
+    ++numAssignmentCalls;
+    return *this;
+  }
+
+  Constructable & operator=(Constructable && src) {
+    EXPECT_TRUE(constructed);
     value = src.value;
     ++numAssignmentCalls;
     return *this;
@@ -338,6 +354,36 @@ TYPED_TEST(SmallVectorTest, AssignTest) {
   this->assertValuesInOrder(this->theVector, 2u, 77, 77);
 }
 
+// Move-assign test
+TYPED_TEST(SmallVectorTest, MoveAssignTest) {
+  SCOPED_TRACE("MoveAssignTest");
+
+  // Set up our vector with a single element, but enough capacity for 4.
+  this->theVector.reserve(4);
+  this->theVector.push_back(Constructable(1));
+  
+  // Set up the other vector with 2 elements.
+  this->otherVector.push_back(Constructable(2));
+  this->otherVector.push_back(Constructable(3));
+
+  // Move-assign from the other vector.
+  this->theVector = std::move(this->otherVector);
+
+  // Make sure we have the right result.
+  this->assertValuesInOrder(this->theVector, 2u, 2, 3);
+
+  // Make sure the # of constructor/destructor calls line up. There
+  // are two live objects after clearing the other vector.
+  this->otherVector.clear();
+  EXPECT_EQ(Constructable::getNumConstructorCalls()-2, 
+            Constructable::getNumDestructorCalls());
+
+  // There shouldn't be any live objects any more.
+  this->theVector.clear();
+  EXPECT_EQ(Constructable::getNumConstructorCalls(), 
+            Constructable::getNumDestructorCalls());
+}
+
 // Erase a single element
 TYPED_TEST(SmallVectorTest, EraseTest) {
   SCOPED_TRACE("EraseTest");
@@ -455,13 +501,12 @@ TYPED_TEST(SmallVectorTest, DirectVectorTest) {
   this->theVector.reserve(4);
   EXPECT_LE(4u, this->theVector.capacity());
   EXPECT_EQ(0, Constructable::getNumConstructorCalls());
-  this->theVector.end()[0] = 1;
-  this->theVector.end()[1] = 2;
-  this->theVector.end()[2] = 3;
-  this->theVector.end()[3] = 4;
-  this->theVector.set_size(4);
+  this->theVector.push_back(1);
+  this->theVector.push_back(2);
+  this->theVector.push_back(3);
+  this->theVector.push_back(4);
   EXPECT_EQ(4u, this->theVector.size());
-  EXPECT_EQ(4, Constructable::getNumConstructorCalls());
+  EXPECT_EQ(8, Constructable::getNumConstructorCalls());
   EXPECT_EQ(1, this->theVector[0].getValue());
   EXPECT_EQ(2, this->theVector[1].getValue());
   EXPECT_EQ(3, this->theVector[2].getValue());
diff --git a/unittests/Analysis/LazyCallGraphTest.cpp b/unittests/Analysis/LazyCallGraphTest.cpp
index 92b9841879..ea68fa77c0 100644
--- a/unittests/Analysis/LazyCallGraphTest.cpp
+++ b/unittests/Analysis/LazyCallGraphTest.cpp
@@ -41,17 +41,17 @@ std::unique_ptr<Module> parseAssembly(const char *Assembly) {
 
 // IR forming a call graph with a diamond of triangle-shaped SCCs:
 //
-//         d1
-//        /  \
-//       d3--d2
-//      /     \
-//     b1     c1
-//   /  \    /  \
-//  b3--b2  c3--c2
-//       \  /
-//        a1
-//       /  \
-//      a3--a2
+//         d1       |
+//        /  \      |
+//       d3--d2     |
+//      /     \     |
+//     b1     c1    |
+//   /  \    /  \   |
+//  b3--b2  c3--c2  |
+//       \  /       |
+//        a1        |
+//       /  \       |
+//      a3--a2      |
 //
 // All call edges go up between SCCs, and clockwise around the SCC.
 static const char DiamondOfTriangles[] =
@@ -290,7 +290,17 @@ TEST(LazyCallGraphTest, BasicGraphMutation) {
   CG.insertEdge(C, C.getFunction());
   EXPECT_EQ(2, std::distance(C.begin(), C.end()));
   EXPECT_EQ(&B, &*C.begin());
-  EXPECT_EQ(&C, &*(C.begin() + 1));
+  EXPECT_EQ(&C, &*std::next(C.begin()));
+
+  CG.removeEdge(C, B.getFunction());
+  EXPECT_EQ(1, std::distance(C.begin(), C.end()));
+  EXPECT_EQ(&C, &*C.begin());
+
+  CG.removeEdge(C, C.getFunction());
+  EXPECT_EQ(0, std::distance(C.begin(), C.end()));
+
+  CG.removeEdge(B, C.getFunction());
+  EXPECT_EQ(0, std::distance(B.begin(), B.end()));
 }
 
 TEST(LazyCallGraphTest, MultiArmSCC) {
@@ -376,6 +386,52 @@ TEST(LazyCallGraphTest, InterSCCEdgeRemoval) {
   EXPECT_EQ(BC.parent_end(), BC.parent_begin());
 }
 
+TEST(LazyCallGraphTest, IntraSCCEdgeInsertion) {
+  std::unique_ptr<Module> M1 = parseAssembly(
+      "define void @a() {\n"
+      "entry:\n"
+      "  call void @b()\n"
+      "  ret void\n"
+      "}\n"
+      "define void @b() {\n"
+      "entry:\n"
+      "  call void @c()\n"
+      "  ret void\n"
+      "}\n"
+      "define void @c() {\n"
+      "entry:\n"
+      "  call void @a()\n"
+      "  ret void\n"
+      "}\n");
+  LazyCallGraph CG1(*M1);
+
+  // Force the graph to be fully expanded.
+  auto SCCI = CG1.postorder_scc_begin();
+  LazyCallGraph::SCC &SCC = *SCCI++;
+  EXPECT_EQ(CG1.postorder_scc_end(), SCCI);
+
+  LazyCallGraph::Node &A = *CG1.lookup(lookupFunction(*M1, "a"));
+  LazyCallGraph::Node &B = *CG1.lookup(lookupFunction(*M1, "b"));
+  LazyCallGraph::Node &C = *CG1.lookup(lookupFunction(*M1, "c"));
+  EXPECT_EQ(&SCC, CG1.lookupSCC(A));
+  EXPECT_EQ(&SCC, CG1.lookupSCC(B));
+  EXPECT_EQ(&SCC, CG1.lookupSCC(C));
+
+  // Insert an edge from 'a' to 'c'. Nothing changes about the SCCs.
+  SCC.insertIntraSCCEdge(A, C);
+  EXPECT_EQ(2, std::distance(A.begin(), A.end()));
+  EXPECT_EQ(&SCC, CG1.lookupSCC(A));
+  EXPECT_EQ(&SCC, CG1.lookupSCC(B));
+  EXPECT_EQ(&SCC, CG1.lookupSCC(C));
+
+  // Insert a self edge from 'a' back to 'a'.
+  SCC.insertIntraSCCEdge(A, A);
+  EXPECT_EQ(3, std::distance(A.begin(), A.end()));
+  EXPECT_EQ(&SCC, CG1.lookupSCC(A));
+  EXPECT_EQ(&SCC, CG1.lookupSCC(B));
+  EXPECT_EQ(&SCC, CG1.lookupSCC(C));
+}
+
 TEST(LazyCallGraphTest, IntraSCCEdgeRemoval) {
   // A nice fully connected (including self-edges) SCC.
   std::unique_ptr<Module> M1 = parseAssembly(
diff --git a/unittests/CMakeLists.txt b/unittests/CMakeLists.txt
index 9e2f60c7b8..bbab2a12b5 100644
--- a/unittests/CMakeLists.txt
+++ b/unittests/CMakeLists.txt
@@ -19,6 +19,7 @@ add_subdirectory(DebugInfo)
 add_subdirectory(ExecutionEngine)
 add_subdirectory(IR)
 add_subdirectory(LineEditor)
+add_subdirectory(Linker)
 add_subdirectory(MC)
 add_subdirectory(Object)
 add_subdirectory(Option)
diff --git a/unittests/LineEditor/LineEditor.cpp b/unittests/LineEditor/LineEditor.cpp
index cb115bd7de..26053c0ede 100644
--- a/unittests/LineEditor/LineEditor.cpp
+++ b/unittests/LineEditor/LineEditor.cpp
@@ -8,6 +8,7 @@
 //===----------------------------------------------------------------------===//
 
 #include "llvm/LineEditor/LineEditor.h"
+#include "llvm/Support/FileSystem.h"
 #include "llvm/Support/Path.h"
 #include "gtest/gtest.h"
 
diff --git a/unittests/Linker/LinkModulesTest.cpp b/unittests/Linker/LinkModulesTest.cpp
index 7b40b9f672..1d5db3641d 100644
--- a/unittests/Linker/LinkModulesTest.cpp
+++ b/unittests/Linker/LinkModulesTest.cpp
@@ -22,11 +22,9 @@ namespace {
 class LinkModuleTest : public testing::Test {
 protected:
   virtual void SetUp() {
-    LLVMContext &Ctx = getGlobalContext();
     M.reset(new Module("MyModule", Ctx));
-    FunctionType *FTy = FunctionType::get(Type::getInt8PtrTy(Ctx),
-                                          Type::getInt32Ty(Ctx),
-                                          false /*=isVarArg*/);
+    FunctionType *FTy = FunctionType::get(
+        Type::getInt8PtrTy(Ctx), Type::getInt32Ty(Ctx), false /*=isVarArg*/);
     F = Function::Create(FTy, Function::ExternalLinkage, "ba_func", M.get());
     F->setCallingConv(CallingConv::C);
 
@@ -38,12 +36,10 @@ protected:
     ArrayType *AT = ArrayType::get(Type::getInt8PtrTy(Ctx), 3);
 
     GV = new GlobalVariable(*M.get(), AT, false /*=isConstant*/,
-                            GlobalValue::InternalLinkage,
-                            0, "switch.bas");
-
+                            GlobalValue::InternalLinkage, 0, "switch.bas");
 
     // Global Initializer
-    std::vector<Constant*> Init;
+    std::vector<Constant *> Init;
     Constant *SwitchCase1BA = BlockAddress::get(SwitchCase1BB);
     Init.push_back(SwitchCase1BA);
 
@@ -51,17 +47,16 @@ protected:
     Init.push_back(SwitchCase2BA);
 
     ConstantInt *One = ConstantInt::get(Type::getInt32Ty(Ctx), 1);
-    Constant *OnePtr = ConstantExpr::getCast(Instruction::IntToPtr,
-                                             One, Type::getInt8PtrTy(Ctx));
+    Constant *OnePtr = ConstantExpr::getCast(Instruction::IntToPtr, One,
+                                             Type::getInt8PtrTy(Ctx));
     Init.push_back(OnePtr);
 
     GV->setInitializer(ConstantArray::get(AT, Init));
   }
 
-  virtual void TearDown() {
-    M.reset();
-  }
+  virtual void TearDown() { M.reset(); }
 
+  LLVMContext Ctx;
   std::unique_ptr<Module> M;
   Function *F;
   GlobalVariable *GV;
@@ -72,10 +67,9 @@ protected:
 };
 
 TEST_F(LinkModuleTest, BlockAddress) {
-  LLVMContext &Ctx = getGlobalContext();
   IRBuilder<> Builder(EntryBB);
 
-  std::vector<Value*> GEPIndices;
+  std::vector<Value *> GEPIndices;
   GEPIndices.push_back(ConstantInt::get(Type::getInt32Ty(Ctx), 0));
   GEPIndices.push_back(F->arg_begin());
 
@@ -93,7 +87,7 @@ TEST_F(LinkModuleTest, BlockAddress) {
   Builder.SetInsertPoint(ExitBB);
   Builder.CreateRet(ConstantPointerNull::get(Type::getInt8PtrTy(Ctx)));
 
-  Module *LinkedModule = new Module("MyModuleLinked", getGlobalContext());
+  Module *LinkedModule = new Module("MyModuleLinked", Ctx);
   Linker::LinkModules(LinkedModule, M.get(), Linker::PreserveSource, 0);
 
   // Delete the original module.
@@ -117,7 +111,7 @@ TEST_F(LinkModuleTest, BlockAddress) {
             LinkedModule->getFunction("ba_func"));
   EXPECT_EQ(cast<BlockAddress>(Elem)->getBasicBlock()->getParent(),
             LinkedModule->getFunction("ba_func"));
-  
+
   Elem = Init->getOperand(1);
   ASSERT_TRUE(isa<BlockAddress>(Elem));
   EXPECT_EQ(cast<BlockAddress>(Elem)->getFunction(),
@@ -129,11 +123,9 @@ TEST_F(LinkModuleTest, BlockAddress) {
 }
 
 TEST_F(LinkModuleTest, EmptyModule) {
-  LLVMContext &Ctx = getGlobalContext();
   Module *InternalM = new Module("InternalModule", Ctx);
-  FunctionType *FTy = FunctionType::get(Type::getVoidTy(Ctx),
-                                        Type::getInt8PtrTy(Ctx),
-                                        false /*=isVarArgs*/);
+  FunctionType *FTy = FunctionType::get(
+      Type::getVoidTy(Ctx), Type::getInt8PtrTy(Ctx), false /*=isVarArgs*/);
 
   F = Function::Create(FTy, Function::InternalLinkage, "bar", InternalM);
   F->setCallingConv(CallingConv::C);
@@ -145,12 +137,11 @@ TEST_F(LinkModuleTest, EmptyModule) {
   StructType *STy = StructType::create(Ctx, PointerType::get(FTy, 0));
 
   GlobalVariable *GV =
-    new GlobalVariable(*InternalM, STy, false /*=isConstant*/,
-                       GlobalValue::InternalLinkage, 0, "g");
+      new GlobalVariable(*InternalM, STy, false /*=isConstant*/,
+                         GlobalValue::InternalLinkage, 0, "g");
 
   GV->setInitializer(ConstantStruct::get(STy, F));
 
-
   Module *EmptyM = new Module("EmptyModule1", Ctx);
   Linker::LinkModules(EmptyM, InternalM, Linker::PreserveSource, 0);
 
diff --git a/unittests/Object/CMakeLists.txt b/unittests/Object/CMakeLists.txt
index 6dd66ce75b..580a894362 100644
--- a/unittests/Object/CMakeLists.txt
+++ b/unittests/Object/CMakeLists.txt
@@ -4,5 +4,6 @@ set(LLVM_LINK_COMPONENTS
   )
 
 add_llvm_unittest(ObjectTests
+  StringTableBuilderTest.cpp
   YAMLTest.cpp
   )
diff --git a/unittests/Object/StringTableBuilderTest.cpp b/unittests/Object/StringTableBuilderTest.cpp
new file mode 100644
index 0000000000..130eb4a3d7
--- /dev/null
+++ b/unittests/Object/StringTableBuilderTest.cpp
@@ -0,0 +1,40 @@
+//===----------- StringTableBuilderTest.cpp -------------------------------===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+
+#include "gtest/gtest.h"
+#include "llvm/Object/StringTableBuilder.h"
+#include <string>
+
+using namespace llvm;
+
+namespace {
+
+TEST(StringTableBuilderTest, Basic) {
+  StringTableBuilder B;
+
+  B.add("foo");
+  B.add("bar");
+  B.add("foobar");
+
+  B.finalize();
+
+  std::string Expected;
+  Expected += '\x00';
+  Expected += "foobar";
+  Expected += '\x00';
+  Expected += "foo";
+  Expected += '\x00';
+
+  EXPECT_EQ(Expected, B.data());
+  EXPECT_EQ(1U, B.getOffset("foobar"));
+  EXPECT_EQ(4U, B.getOffset("bar"));
+  EXPECT_EQ(8U, B.getOffset("foo"));
+}
+
+}
diff --git a/unittests/Support/BlockFrequencyTest.cpp b/unittests/Support/BlockFrequencyTest.cpp
index c318451504..f6e3537de9 100644
--- a/unittests/Support/BlockFrequencyTest.cpp
+++ b/unittests/Support/BlockFrequencyTest.cpp
@@ -15,9 +15,8 @@ TEST(BlockFrequencyTest, OneToZero) {
   EXPECT_EQ(Freq.getFrequency(), 0u);
 
   Freq = BlockFrequency(1);
-  uint32_t Remainder = Freq.scale(Prob);
+  Freq *= Prob;
   EXPECT_EQ(Freq.getFrequency(), 0u);
-  EXPECT_EQ(Remainder, UINT32_MAX - 1);
 }
 
 TEST(BlockFrequencyTest, OneToOne) {
@@ -27,9 +26,8 @@ TEST(BlockFrequencyTest, OneToOne) {
   EXPECT_EQ(Freq.getFrequency(), 1u);
 
   Freq = BlockFrequency(1);
-  uint32_t Remainder = Freq.scale(Prob);
+  Freq *= Prob;
   EXPECT_EQ(Freq.getFrequency(), 1u);
-  EXPECT_EQ(Remainder, 0u);
 }
 
 TEST(BlockFrequencyTest, ThreeToOne) {
@@ -39,9 +37,8 @@ TEST(BlockFrequencyTest, ThreeToOne) {
   EXPECT_EQ(Freq.getFrequency(), 1u);
 
   Freq = BlockFrequency(3);
-  uint32_t Remainder = Freq.scale(Prob);
+  Freq *= Prob;
   EXPECT_EQ(Freq.getFrequency(), 1u);
-  EXPECT_EQ(Remainder, 0u);
 }
 
 TEST(BlockFrequencyTest, MaxToHalfMax) {
@@ -51,9 +48,8 @@ TEST(BlockFrequencyTest, MaxToHalfMax) {
   EXPECT_EQ(Freq.getFrequency(), 9223372034707292159ULL);
 
   Freq = BlockFrequency(UINT64_MAX);
-  uint32_t Remainder = Freq.scale(Prob);
+  Freq *= Prob;
   EXPECT_EQ(Freq.getFrequency(), 9223372034707292159ULL);
-  EXPECT_EQ(Remainder, 0u);
 }
 
 TEST(BlockFrequencyTest, BigToBig) {
@@ -65,9 +61,8 @@ TEST(BlockFrequencyTest, BigToBig) {
   EXPECT_EQ(Freq.getFrequency(), Big);
 
   Freq = BlockFrequency(Big);
-  uint32_t Remainder = Freq.scale(Prob);
+  Freq *= Prob;
   EXPECT_EQ(Freq.getFrequency(), Big);
-  EXPECT_EQ(Remainder, 0u);
 }
 
 TEST(BlockFrequencyTest, MaxToMax) {
@@ -80,109 +75,8 @@ TEST(BlockFrequencyTest, MaxToMax) {
   // value, we do not signal saturation if the result equals said value, but
   // saturating does not occur.
   Freq = BlockFrequency(UINT64_MAX);
-  uint32_t Remainder = Freq.scale(Prob);
+  Freq *= Prob;
   EXPECT_EQ(Freq.getFrequency(), UINT64_MAX);
-  EXPECT_EQ(Remainder, 0u);
-}
-
-TEST(BlockFrequencyTest, ScaleResultRemainderTest) {
-  struct {
-    uint64_t Freq;
-    uint32_t Prob[2];
-    uint64_t ExpectedFreq;
-    uint32_t ExpectedRemainder;
-  } Tests[80] = {
-    // Data for scaling that results in <= 64 bit division.
-    { 0x1423e2a50ULL, { 0x64819521, 0x7765dd13 }, 0x10f418889ULL, 0x92b9d25 },
-    { 0x35ef14ceULL, { 0x28ade3c7, 0x304532ae }, 0x2d73c33aULL, 0x2c0fd0b6 },
-    { 0xd03dbfbe24ULL, { 0x790079, 0xe419f3 }, 0x6e776fc1fdULL, 0x4a06dd },
-    { 0x21d67410bULL, { 0x302a9dc2, 0x3ddb4442 }, 0x1a5948fd6ULL, 0x265d1c2a },
-    { 0x8664aeadULL, { 0x3d523513, 0x403523b1 }, 0x805a04cfULL, 0x324c27b8 },
-    { 0x201db0cf4ULL, { 0x35112a7b, 0x79fc0c74 }, 0xdf8b07f6ULL, 0x490c1dc4 },
-    { 0x13f1e4430aULL, { 0x21c92bf, 0x21e63aae }, 0x13e0cba15ULL, 0x1df47c30 },
-    { 0x16c83229ULL, { 0x3793f66f, 0x53180dea }, 0xf3ce7b6ULL, 0x1d0c1b6b },
-    { 0xc62415be8ULL, { 0x9cc4a63, 0x4327ae9b }, 0x1ce8b71caULL, 0x3f2c696a },
-    { 0x6fac5e434ULL, { 0xe5f9170, 0x1115e10b }, 0x5df23dd4cULL, 0x4dafc7c },
-    { 0x1929375f2ULL, { 0x3a851375, 0x76c08456 }, 0xc662b082ULL, 0x343589ee },
-    { 0x243c89db6ULL, { 0x354ebfc0, 0x450ef197 }, 0x1bf8c1661ULL, 0x4948e49 },
-    { 0x310e9b31aULL, { 0x1b1b8acf, 0x2d3629f0 }, 0x1d69c93f9ULL, 0x73e3b96 },
-    { 0xa1fae921dULL, { 0xa7a098c, 0x10469f44 }, 0x684413d6cULL, 0x86a882c },
-    { 0xc1582d957ULL, { 0x498e061, 0x59856bc }, 0x9edc5f4e7ULL, 0x29b0653 },
-    { 0x57cfee75ULL, { 0x1d061dc3, 0x7c8bfc17 }, 0x1476a220ULL, 0x2383d33f },
-    { 0x139220080ULL, { 0x294a6c71, 0x2a2b07c9 }, 0x1329e1c76ULL, 0x7aa5da },
-    { 0x1665d353cULL, { 0x7080db5, 0xde0d75c }, 0xb590d9fbULL, 0x7ba8c38 },
-    { 0xe8f14541ULL, { 0x5188e8b2, 0x736527ef }, 0xa4971be5ULL, 0x6b612167 },
-    { 0x2f4775f29ULL, { 0x254ef0fe, 0x435fcf50 }, 0x1a2e449c1ULL, 0x28bbf5e },
-    { 0x27b85d8d7ULL, { 0x304c8220, 0x5de678f2 }, 0x146e3bef9ULL, 0x4b27097e },
-    { 0x1d362e36bULL, { 0x36c85b12, 0x37a66f55 }, 0x1cc19b8e6ULL, 0x688e828 },
-    { 0x155fd48c7ULL, { 0xf5894d, 0x1256108 }, 0x11e383602ULL, 0x111f0cb },
-    { 0xb5db2d15ULL, { 0x39bb26c5, 0x5bdcda3e }, 0x72499259ULL, 0x59c4939b },
-    { 0x153990298ULL, { 0x48921c09, 0x706eb817 }, 0xdb3268e8ULL, 0x66bb8a80 },
-    { 0x28a7c3ed7ULL, { 0x1f776fd7, 0x349f7a70 }, 0x184f73ae1ULL, 0x28910321 },
-    { 0x724dbeabULL, { 0x1bd149f5, 0x253a085e }, 0x5569c0b3ULL, 0xff8e2ed },
-    { 0xd8f0c513ULL, { 0x18c8cc4c, 0x1b72bad0 }, 0xc3e30643ULL, 0xd85e134 },
-    { 0x17ce3dcbULL, { 0x1e4c6260, 0x233b359e }, 0x1478f4afULL, 0x49ea31e },
-    { 0x1ce036ce0ULL, { 0x29e3c8af, 0x5318dd4a }, 0xe8e76196ULL, 0x11d5b9c4 },
-    { 0x1473ae2aULL, { 0x29b897ba, 0x2be29378 }, 0x13718185ULL, 0x6f93b2c },
-    { 0x1dd41aa68ULL, { 0x3d0a4441, 0x5a0e8f12 }, 0x1437b6bbfULL, 0x54b09ffa },
-    { 0x1b49e4a53ULL, { 0x3430c1fe, 0x5a204aed }, 0xfcd6852fULL, 0x15ad6ed7 },
-    { 0x217941b19ULL, { 0x12ced2bd, 0x21b68310 }, 0x12aca65b1ULL, 0x1b2a9565 },
-    { 0xac6a4dc8ULL, { 0x3ed68da8, 0x6fdca34c }, 0x60da926dULL, 0x22ff53e4 },
-    { 0x1c503a4e7ULL, { 0xfcbbd32, 0x11e48d17 }, 0x18fec7d38ULL, 0xa8aa816 },
-    { 0x1c885855ULL, { 0x213e919d, 0x25941897 }, 0x193de743ULL, 0x4ea09c },
-    { 0x29b9c168eULL, { 0x2b644aea, 0x45725ee7 }, 0x1a122e5d5ULL, 0xbee1099 },
-    { 0x806a33f2ULL, { 0x30a80a23, 0x5063733a }, 0x4db9a264ULL, 0x1eaed76e },
-    { 0x282afc96bULL, { 0x143ae554, 0x1a9863ff }, 0x1e8de5204ULL, 0x158d9020 },
-    // Data for scaling that results in > 64 bit division.
-    { 0x23ca5f2f672ca41cULL, { 0xecbc641, 0x111373f7 }, 0x1f0301e5e8295ab5ULL, 0xf627f79 },
-    { 0x5e4f2468142265e3ULL, { 0x1ddf5837, 0x32189233 }, 0x383ca7ba9fdd2c8cULL, 0x1c8f33e1 },
-    { 0x277a1a6f6b266bf6ULL, { 0x415d81a8, 0x61eb5e1e }, 0x1a5a3e1d41b30c0fULL, 0x29cde3ae },
-    { 0x1bdbb49a237035cbULL, { 0xea5bf17, 0x1d25ffb3 }, 0xdffc51c53d44b93ULL, 0x5170574 },
-    { 0x2bce6d29b64fb8ULL, { 0x3bfd5631, 0x7525c9bb }, 0x166ebedda7ac57ULL, 0x3026dfab },
-    { 0x3a02116103df5013ULL, { 0x2ee18a83, 0x3299aea8 }, 0x35be8922ab1e2a84ULL, 0x298d9919 },
-    { 0x7b5762390799b18cULL, { 0x12f8e5b9, 0x2563bcd4 }, 0x3e960077aca01209ULL, 0x93afeb8 },
-    { 0x69cfd72537021579ULL, { 0x4c35f468, 0x6a40feee }, 0x4be4cb3848be98a3ULL, 0x4ff96b9e },
-    { 0x49dfdf835120f1c1ULL, { 0x8cb3759, 0x559eb891 }, 0x79663f7120edadeULL, 0x51b1fb5b },
-    { 0x74b5be5c27676381ULL, { 0x47e4c5e0, 0x7c7b19ff }, 0x4367d2dff36a1028ULL, 0x7a7b5608 },
-    { 0x4f50f97075e7f431ULL, { 0x9a50a17, 0x11cd1185 }, 0x2af952b34c032df4ULL, 0xfddc6a3 },
-    { 0x2f8b0d712e393be4ULL, { 0x1487e386, 0x15aa356e }, 0x2d0df36478a776aaULL, 0x14e2564c },
-    { 0x224c1c75999d3deULL, { 0x3b2df0ea, 0x4523b100 }, 0x1d5b481d145f08aULL, 0x15145eec },
-    { 0x2bcbcea22a399a76ULL, { 0x28b58212, 0x48dd013e }, 0x187814d084c47cabULL, 0x3a38ebe2 },
-    { 0x1dbfca91257cb2d1ULL, { 0x1a8c04d9, 0x5e92502c }, 0x859cf7d00f77545ULL, 0x7431f4d },
-    { 0x7f20039b57cda935ULL, { 0xeccf651, 0x323f476e }, 0x25720cd976461a77ULL, 0x202817a3 },
-    { 0x40512c6a586aa087ULL, { 0x113b0423, 0x398c9eab }, 0x1341c03de8696a7eULL, 0x1e27284b },
-    { 0x63d802693f050a11ULL, { 0xf50cdd6, 0xfce2a44 }, 0x60c0177bb5e46846ULL, 0xf7ad89e },
-    { 0x2d956b422838de77ULL, { 0xb2d345b, 0x1321e557 }, 0x1aa0ed16b6aa5319ULL, 0xfe1a5ce },
-    { 0x5a1cdf0c1657bc91ULL, { 0x1d77bb0c, 0x1f991ff1 }, 0x54097ee94ff87560ULL, 0x11c4a26c },
-    { 0x3801b26d7e00176bULL, { 0xeed25da, 0x1a819d8b }, 0x1f89e96a3a639526ULL, 0xcd51e7c },
-    { 0x37655e74338e1e45ULL, { 0x300e170a, 0x5a1595fe }, 0x1d8cfb55fddc0441ULL, 0x3df05434 },
-    { 0x7b38703f2a84e6ULL, { 0x66d9053, 0xc79b6b9 }, 0x3f7d4c91774094ULL, 0x26d939e },
-    { 0x2245063c0acb3215ULL, { 0x30ce2f5b, 0x610e7271 }, 0x113b916468389235ULL, 0x1b588512 },
-    { 0x6bc195877b7b8a7eULL, { 0x392004aa, 0x4a24e60c }, 0x530594fb17db6ba5ULL, 0x35c0a5f0 },
-    { 0x40a3fde23c7b43dbULL, { 0x4e712195, 0x6553e56e }, 0x320a799bc76a466aULL, 0x5e23a5eb },
-    { 0x1d3dfc2866fbccbaULL, { 0x5075b517, 0x5fc42245 }, 0x18917f0061595bc3ULL, 0x3fcf4527 },
-    { 0x19aeb14045a61121ULL, { 0x1bf6edec, 0x707e2f4b }, 0x6626672a070bcc7ULL, 0x3607801f },
-    { 0x44ff90486c531e9fULL, { 0x66598a, 0x8a90dc }, 0x32f6f2b0525199b0ULL, 0x5ab576 },
-    { 0x3f3e7121092c5bcbULL, { 0x1c754df7, 0x5951a1b9 }, 0x14267f50b7ef375dULL, 0x221220a8 },
-    { 0x60e2dafb7e50a67eULL, { 0x4d96c66e, 0x65bd878d }, 0x49e31715ac393f8bULL, 0x4e97b195 },
-    { 0x656286667e0e6e29ULL, { 0x9d971a2, 0xacda23b }, 0x5c6ee315ead6cb4fULL, 0x516f5bd },
-    { 0x1114e0974255d507ULL, { 0x1c693, 0x2d6ff }, 0xaae42e4b35f6e60ULL, 0x8b65 },
-    { 0x508c8baf3a70ff5aULL, { 0x3b26b779, 0x6ad78745 }, 0x2c98387636c4b365ULL, 0x11dc6a51 },
-    { 0x5b47bc666bf1f9cfULL, { 0x10a87ed6, 0x187d358a }, 0x3e1767155848368bULL, 0xfb871c },
-    { 0x50954e3744460395ULL, { 0x7a42263, 0xcdaa048 }, 0x2fe739f0aee1fee1ULL, 0xb8add57 },
-    { 0x20020b406550dd8fULL, { 0x3318539, 0x42eead0 }, 0x186f326325fa346bULL, 0x10d3ae7 },
-    { 0x5bcb0b872439ffd5ULL, { 0x6f61fb2, 0x9af7344 }, 0x41fa1e3bec3c1b30ULL, 0x4fee45a },
-    { 0x7a670f365db87a53ULL, { 0x417e102, 0x3bb54c67 }, 0x8642a558304fd9eULL, 0x3b65f514 },
-    { 0x1ef0db1e7bab1cd0ULL, { 0x2b60cf38, 0x4188f78f }, 0x147ae0d6226b2ee6ULL, 0x336b6106 }
-  };
-
-  for (unsigned i = 0; i < 80; i++) {
-    BlockFrequency Freq(Tests[i].Freq);
-    uint32_t Remainder = Freq.scale(BranchProbability(Tests[i].Prob[0],
-                                                      Tests[i].Prob[1]));
-    EXPECT_EQ(Tests[i].ExpectedFreq, Freq.getFrequency());
-    EXPECT_EQ(Tests[i].ExpectedRemainder, Remainder);
-  }
 }
 
 TEST(BlockFrequency, Divide) {
@@ -208,35 +102,6 @@ TEST(BlockFrequencyTest, Saturate) {
   EXPECT_EQ(33506781356485509ULL, Freq.getFrequency());
 }
 
-TEST(BlockFrequencyTest, ProbabilityCompare) {
-  BranchProbability A(4, 5);
-  BranchProbability B(4U << 29, 5U << 29);
-  BranchProbability C(3, 4);
-
-  EXPECT_TRUE(A == B);
-  EXPECT_FALSE(A != B);
-  EXPECT_FALSE(A < B);
-  EXPECT_FALSE(A > B);
-  EXPECT_TRUE(A <= B);
-  EXPECT_TRUE(A >= B);
-
-  EXPECT_FALSE(B == C);
-  EXPECT_TRUE(B != C);
-  EXPECT_FALSE(B < C);
-  EXPECT_TRUE(B > C);
-  EXPECT_FALSE(B <= C);
-  EXPECT_TRUE(B >= C);
-
-  BranchProbability BigZero(0, UINT32_MAX);
-  BranchProbability BigOne(UINT32_MAX, UINT32_MAX);
-  EXPECT_FALSE(BigZero == BigOne);
-  EXPECT_TRUE(BigZero != BigOne);
-  EXPECT_TRUE(BigZero < BigOne);
-  EXPECT_FALSE(BigZero > BigOne);
-  EXPECT_TRUE(BigZero <= BigOne);
-  EXPECT_FALSE(BigZero >= BigOne);
-}
-
 TEST(BlockFrequencyTest, SaturatingRightShift) {
   BlockFrequency Freq(0x10080ULL);
   Freq >>= 2;
diff --git a/unittests/Support/BranchProbabilityTest.cpp b/unittests/Support/BranchProbabilityTest.cpp
new file mode 100644
index 0000000000..bbd4d4eba1
--- /dev/null
+++ b/unittests/Support/BranchProbabilityTest.cpp
@@ -0,0 +1,282 @@
+//===- unittest/Support/BranchProbabilityTest.cpp - BranchProbability tests -=//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+
+#include "llvm/Support/BranchProbability.h"
+#include "llvm/Support/raw_ostream.h"
+#include "gtest/gtest.h"
+
+using namespace llvm;
+
+namespace llvm {
+void PrintTo(const BranchProbability &P, ::std::ostream *os) {
+  *os << P.getNumerator() << "/" << P.getDenominator();
+}
+}
+namespace {
+
+typedef BranchProbability BP;
+TEST(BranchProbabilityTest, Accessors) {
+  EXPECT_EQ(1u, BP(1, 7).getNumerator());
+  EXPECT_EQ(7u, BP(1, 7).getDenominator());
+  EXPECT_EQ(0u, BP::getZero().getNumerator());
+  EXPECT_EQ(1u, BP::getZero().getDenominator());
+  EXPECT_EQ(1u, BP::getOne().getNumerator());
+  EXPECT_EQ(1u, BP::getOne().getDenominator());
+}
+
+TEST(BranchProbabilityTest, Operators) {
+  EXPECT_TRUE(BP(1, 7) < BP(2, 7));
+  EXPECT_TRUE(BP(1, 7) < BP(1, 4));
+  EXPECT_TRUE(BP(5, 7) < BP(3, 4));
+  EXPECT_FALSE(BP(1, 7) < BP(1, 7));
+  EXPECT_FALSE(BP(1, 7) < BP(2, 14));
+  EXPECT_FALSE(BP(4, 7) < BP(1, 2));
+  EXPECT_FALSE(BP(4, 7) < BP(3, 7));
+
+  EXPECT_FALSE(BP(1, 7) > BP(2, 7));
+  EXPECT_FALSE(BP(1, 7) > BP(1, 4));
+  EXPECT_FALSE(BP(5, 7) > BP(3, 4));
+  EXPECT_FALSE(BP(1, 7) > BP(1, 7));
+  EXPECT_FALSE(BP(1, 7) > BP(2, 14));
+  EXPECT_TRUE(BP(4, 7) > BP(1, 2));
+  EXPECT_TRUE(BP(4, 7) > BP(3, 7));
+
+  EXPECT_TRUE(BP(1, 7) <= BP(2, 7));
+  EXPECT_TRUE(BP(1, 7) <= BP(1, 4));
+  EXPECT_TRUE(BP(5, 7) <= BP(3, 4));
+  EXPECT_TRUE(BP(1, 7) <= BP(1, 7));
+  EXPECT_TRUE(BP(1, 7) <= BP(2, 14));
+  EXPECT_FALSE(BP(4, 7) <= BP(1, 2));
+  EXPECT_FALSE(BP(4, 7) <= BP(3, 7));
+
+  EXPECT_FALSE(BP(1, 7) >= BP(2, 7));
+  EXPECT_FALSE(BP(1, 7) >= BP(1, 4));
+  EXPECT_FALSE(BP(5, 7) >= BP(3, 4));
+  EXPECT_TRUE(BP(1, 7) >= BP(1, 7));
+  EXPECT_TRUE(BP(1, 7) >= BP(2, 14));
+  EXPECT_TRUE(BP(4, 7) >= BP(1, 2));
+  EXPECT_TRUE(BP(4, 7) >= BP(3, 7));
+
+  EXPECT_FALSE(BP(1, 7) == BP(2, 7));
+  EXPECT_FALSE(BP(1, 7) == BP(1, 4));
+  EXPECT_FALSE(BP(5, 7) == BP(3, 4));
+  EXPECT_TRUE(BP(1, 7) == BP(1, 7));
+  EXPECT_TRUE(BP(1, 7) == BP(2, 14));
+  EXPECT_FALSE(BP(4, 7) == BP(1, 2));
+  EXPECT_FALSE(BP(4, 7) == BP(3, 7));
+
+  EXPECT_TRUE(BP(1, 7) != BP(2, 7));
+  EXPECT_TRUE(BP(1, 7) != BP(1, 4));
+  EXPECT_TRUE(BP(5, 7) != BP(3, 4));
+  EXPECT_FALSE(BP(1, 7) != BP(1, 7));
+  EXPECT_FALSE(BP(1, 7) != BP(2, 14));
+  EXPECT_TRUE(BP(4, 7) != BP(1, 2));
+  EXPECT_TRUE(BP(4, 7) != BP(3, 7));
+}
+
+TEST(BranchProbabilityTest, MoreOperators) {
+  BP A(4, 5);
+  BP B(4U << 29, 5U << 29);
+  BP C(3, 4);
+
+  EXPECT_TRUE(A == B);
+  EXPECT_FALSE(A != B);
+  EXPECT_FALSE(A < B);
+  EXPECT_FALSE(A > B);
+  EXPECT_TRUE(A <= B);
+  EXPECT_TRUE(A >= B);
+
+  EXPECT_FALSE(B == C);
+  EXPECT_TRUE(B != C);
+  EXPECT_FALSE(B < C);
+  EXPECT_TRUE(B > C);
+  EXPECT_FALSE(B <= C);
+  EXPECT_TRUE(B >= C);
+
+  BP BigZero(0, UINT32_MAX);
+  BP BigOne(UINT32_MAX, UINT32_MAX);
+  EXPECT_FALSE(BigZero == BigOne);
+  EXPECT_TRUE(BigZero != BigOne);
+  EXPECT_TRUE(BigZero < BigOne);
+  EXPECT_FALSE(BigZero > BigOne);
+  EXPECT_TRUE(BigZero <= BigOne);
+  EXPECT_FALSE(BigZero >= BigOne);
+}
+
+TEST(BranchProbabilityTest, getCompl) {
+  EXPECT_EQ(BP(5, 7), BP(2, 7).getCompl());
+  EXPECT_EQ(BP(2, 7), BP(5, 7).getCompl());
+  EXPECT_EQ(BP::getZero(), BP(7, 7).getCompl());
+  EXPECT_EQ(BP::getOne(), BP(0, 7).getCompl());
+}
+
+TEST(BranchProbabilityTest, scale) {
+  // Multiply by 1.0.
+  EXPECT_EQ(UINT64_MAX, BP(1, 1).scale(UINT64_MAX));
+  EXPECT_EQ(UINT64_MAX, BP(7, 7).scale(UINT64_MAX));
+  EXPECT_EQ(UINT32_MAX, BP(1, 1).scale(UINT32_MAX));
+  EXPECT_EQ(UINT32_MAX, BP(7, 7).scale(UINT32_MAX));
+  EXPECT_EQ(0u, BP(1, 1).scale(0));
+  EXPECT_EQ(0u, BP(7, 7).scale(0));
+
+  // Multiply by 0.0.
+  EXPECT_EQ(0u, BP(0, 1).scale(UINT64_MAX));
+  EXPECT_EQ(0u, BP(0, 1).scale(UINT64_MAX));
+  EXPECT_EQ(0u, BP(0, 1).scale(0));
+
+  auto Two63 = UINT64_C(1) << 63;
+  auto Two31 = UINT64_C(1) << 31;
+
+  // Multiply by 0.5.
+  EXPECT_EQ(Two63 - 1, BP(1, 2).scale(UINT64_MAX));
+
+  // Big fractions.
+  EXPECT_EQ(1u, BP(Two31, UINT32_MAX).scale(2));
+  EXPECT_EQ(Two31, BP(Two31, UINT32_MAX).scale(Two31 * 2));
+  EXPECT_EQ(Two63 + Two31, BP(Two31, UINT32_MAX).scale(UINT64_MAX));
+
+  // High precision.
+  EXPECT_EQ(UINT64_C(9223372047592194055),
+            BP(Two31 + 1, UINT32_MAX - 2).scale(UINT64_MAX));
+}
+
+TEST(BranchProbabilityTest, scaleByInverse) {
+  // Divide by 1.0.
+  EXPECT_EQ(UINT64_MAX, BP(1, 1).scaleByInverse(UINT64_MAX));
+  EXPECT_EQ(UINT64_MAX, BP(7, 7).scaleByInverse(UINT64_MAX));
+  EXPECT_EQ(UINT32_MAX, BP(1, 1).scaleByInverse(UINT32_MAX));
+  EXPECT_EQ(UINT32_MAX, BP(7, 7).scaleByInverse(UINT32_MAX));
+  EXPECT_EQ(0u, BP(1, 1).scaleByInverse(0));
+  EXPECT_EQ(0u, BP(7, 7).scaleByInverse(0));
+
+  // Divide by something very small.
+  EXPECT_EQ(UINT64_MAX, BP(1, UINT32_MAX).scaleByInverse(UINT64_MAX));
+  EXPECT_EQ(uint64_t(UINT32_MAX) * UINT32_MAX,
+            BP(1, UINT32_MAX).scaleByInverse(UINT32_MAX));
+  EXPECT_EQ(UINT32_MAX, BP(1, UINT32_MAX).scaleByInverse(1));
+
+  auto Two63 = UINT64_C(1) << 63;
+  auto Two31 = UINT64_C(1) << 31;
+
+  // Divide by 0.5.
+  EXPECT_EQ(UINT64_MAX - 1, BP(1, 2).scaleByInverse(Two63 - 1));
+  EXPECT_EQ(UINT64_MAX, BP(1, 2).scaleByInverse(Two63));
+
+  // Big fractions.
+  EXPECT_EQ(1u, BP(Two31, UINT32_MAX).scaleByInverse(1));
+  EXPECT_EQ(2u, BP(Two31 - 1, UINT32_MAX).scaleByInverse(1));
+  EXPECT_EQ(Two31 * 2 - 1, BP(Two31, UINT32_MAX).scaleByInverse(Two31));
+  EXPECT_EQ(Two31 * 2 + 1, BP(Two31 - 1, UINT32_MAX).scaleByInverse(Two31));
+  EXPECT_EQ(UINT64_MAX, BP(Two31, UINT32_MAX).scaleByInverse(Two63 + Two31));
+
+  // High precision.  The exact answers to these are close to the successors of
+  // the floor.  If we were rounding, these would round up.
+  EXPECT_EQ(UINT64_C(18446744065119617030),
+            BP(Two31 + 2, UINT32_MAX - 2)
+                .scaleByInverse(UINT64_C(9223372047592194055)));
+  EXPECT_EQ(UINT64_C(18446744065119617026),
+            BP(Two31 + 1, UINT32_MAX).scaleByInverse(Two63 + Two31));
+}
+
+TEST(BranchProbabilityTest, scaleBruteForce) {
+  struct {
+    uint64_t Num;
+    uint32_t Prob[2];
+    uint64_t Result;
+  } Tests[] = {
+    // Data for scaling that results in <= 64 bit division.
+    { 0x1423e2a50ULL, { 0x64819521, 0x7765dd13 }, 0x10f418889ULL },
+    { 0x35ef14ceULL, { 0x28ade3c7, 0x304532ae }, 0x2d73c33aULL },
+    { 0xd03dbfbe24ULL, { 0x790079, 0xe419f3 }, 0x6e776fc1fdULL },
+    { 0x21d67410bULL, { 0x302a9dc2, 0x3ddb4442 }, 0x1a5948fd6ULL },
+    { 0x8664aeadULL, { 0x3d523513, 0x403523b1 }, 0x805a04cfULL },
+    { 0x201db0cf4ULL, { 0x35112a7b, 0x79fc0c74 }, 0xdf8b07f6ULL },
+    { 0x13f1e4430aULL, { 0x21c92bf, 0x21e63aae }, 0x13e0cba15ULL },
+    { 0x16c83229ULL, { 0x3793f66f, 0x53180dea }, 0xf3ce7b6ULL },
+    { 0xc62415be8ULL, { 0x9cc4a63, 0x4327ae9b }, 0x1ce8b71caULL },
+    { 0x6fac5e434ULL, { 0xe5f9170, 0x1115e10b }, 0x5df23dd4cULL },
+    { 0x1929375f2ULL, { 0x3a851375, 0x76c08456 }, 0xc662b082ULL },
+    { 0x243c89db6ULL, { 0x354ebfc0, 0x450ef197 }, 0x1bf8c1661ULL },
+    { 0x310e9b31aULL, { 0x1b1b8acf, 0x2d3629f0 }, 0x1d69c93f9ULL },
+    { 0xa1fae921dULL, { 0xa7a098c, 0x10469f44 }, 0x684413d6cULL },
+    { 0xc1582d957ULL, { 0x498e061, 0x59856bc }, 0x9edc5f4e7ULL },
+    { 0x57cfee75ULL, { 0x1d061dc3, 0x7c8bfc17 }, 0x1476a220ULL },
+    { 0x139220080ULL, { 0x294a6c71, 0x2a2b07c9 }, 0x1329e1c76ULL },
+    { 0x1665d353cULL, { 0x7080db5, 0xde0d75c }, 0xb590d9fbULL },
+    { 0xe8f14541ULL, { 0x5188e8b2, 0x736527ef }, 0xa4971be5ULL },
+    { 0x2f4775f29ULL, { 0x254ef0fe, 0x435fcf50 }, 0x1a2e449c1ULL },
+    { 0x27b85d8d7ULL, { 0x304c8220, 0x5de678f2 }, 0x146e3bef9ULL },
+    { 0x1d362e36bULL, { 0x36c85b12, 0x37a66f55 }, 0x1cc19b8e6ULL },
+    { 0x155fd48c7ULL, { 0xf5894d, 0x1256108 }, 0x11e383602ULL },
+    { 0xb5db2d15ULL, { 0x39bb26c5, 0x5bdcda3e }, 0x72499259ULL },
+    { 0x153990298ULL, { 0x48921c09, 0x706eb817 }, 0xdb3268e8ULL },
+    { 0x28a7c3ed7ULL, { 0x1f776fd7, 0x349f7a70 }, 0x184f73ae1ULL },
+    { 0x724dbeabULL, { 0x1bd149f5, 0x253a085e }, 0x5569c0b3ULL },
+    { 0xd8f0c513ULL, { 0x18c8cc4c, 0x1b72bad0 }, 0xc3e30643ULL },
+    { 0x17ce3dcbULL, { 0x1e4c6260, 0x233b359e }, 0x1478f4afULL },
+    { 0x1ce036ce0ULL, { 0x29e3c8af, 0x5318dd4a }, 0xe8e76196ULL },
+    { 0x1473ae2aULL, { 0x29b897ba, 0x2be29378 }, 0x13718185ULL },
+    { 0x1dd41aa68ULL, { 0x3d0a4441, 0x5a0e8f12 }, 0x1437b6bbfULL },
+    { 0x1b49e4a53ULL, { 0x3430c1fe, 0x5a204aed }, 0xfcd6852fULL },
+    { 0x217941b19ULL, { 0x12ced2bd, 0x21b68310 }, 0x12aca65b1ULL },
+    { 0xac6a4dc8ULL, { 0x3ed68da8, 0x6fdca34c }, 0x60da926dULL },
+    { 0x1c503a4e7ULL, { 0xfcbbd32, 0x11e48d17 }, 0x18fec7d38ULL },
+    { 0x1c885855ULL, { 0x213e919d, 0x25941897 }, 0x193de743ULL },
+    { 0x29b9c168eULL, { 0x2b644aea, 0x45725ee7 }, 0x1a122e5d5ULL },
+    { 0x806a33f2ULL, { 0x30a80a23, 0x5063733a }, 0x4db9a264ULL },
+    { 0x282afc96bULL, { 0x143ae554, 0x1a9863ff }, 0x1e8de5204ULL },
+    // Data for scaling that results in > 64 bit division.
+    { 0x23ca5f2f672ca41cULL, { 0xecbc641, 0x111373f7 }, 0x1f0301e5e8295ab5ULL },
+    { 0x5e4f2468142265e3ULL, { 0x1ddf5837, 0x32189233 }, 0x383ca7ba9fdd2c8cULL },
+    { 0x277a1a6f6b266bf6ULL, { 0x415d81a8, 0x61eb5e1e }, 0x1a5a3e1d41b30c0fULL },
+    { 0x1bdbb49a237035cbULL, { 0xea5bf17, 0x1d25ffb3 }, 0xdffc51c53d44b93ULL },
+    { 0x2bce6d29b64fb8ULL, { 0x3bfd5631, 0x7525c9bb }, 0x166ebedda7ac57ULL },
+    { 0x3a02116103df5013ULL, { 0x2ee18a83, 0x3299aea8 }, 0x35be8922ab1e2a84ULL },
+    { 0x7b5762390799b18cULL, { 0x12f8e5b9, 0x2563bcd4 }, 0x3e960077aca01209ULL },
+    { 0x69cfd72537021579ULL, { 0x4c35f468, 0x6a40feee }, 0x4be4cb3848be98a3ULL },
+    { 0x49dfdf835120f1c1ULL, { 0x8cb3759, 0x559eb891 }, 0x79663f7120edadeULL },
+    { 0x74b5be5c27676381ULL, { 0x47e4c5e0, 0x7c7b19ff }, 0x4367d2dff36a1028ULL },
+    { 0x4f50f97075e7f431ULL, { 0x9a50a17, 0x11cd1185 }, 0x2af952b34c032df4ULL },
+    { 0x2f8b0d712e393be4ULL, { 0x1487e386, 0x15aa356e }, 0x2d0df36478a776aaULL },
+    { 0x224c1c75999d3deULL, { 0x3b2df0ea, 0x4523b100 }, 0x1d5b481d145f08aULL },
+    { 0x2bcbcea22a399a76ULL, { 0x28b58212, 0x48dd013e }, 0x187814d084c47cabULL },
+    { 0x1dbfca91257cb2d1ULL, { 0x1a8c04d9, 0x5e92502c }, 0x859cf7d00f77545ULL },
+    { 0x7f20039b57cda935ULL, { 0xeccf651, 0x323f476e }, 0x25720cd976461a77ULL },
+    { 0x40512c6a586aa087ULL, { 0x113b0423, 0x398c9eab }, 0x1341c03de8696a7eULL },
+    { 0x63d802693f050a11ULL, { 0xf50cdd6, 0xfce2a44 }, 0x60c0177bb5e46846ULL },
+    { 0x2d956b422838de77ULL, { 0xb2d345b, 0x1321e557 }, 0x1aa0ed16b6aa5319ULL },
+    { 0x5a1cdf0c1657bc91ULL, { 0x1d77bb0c, 0x1f991ff1 }, 0x54097ee94ff87560ULL },
+    { 0x3801b26d7e00176bULL, { 0xeed25da, 0x1a819d8b }, 0x1f89e96a3a639526ULL },
+    { 0x37655e74338e1e45ULL, { 0x300e170a, 0x5a1595fe }, 0x1d8cfb55fddc0441ULL },
+    { 0x7b38703f2a84e6ULL, { 0x66d9053, 0xc79b6b9 }, 0x3f7d4c91774094ULL },
+    { 0x2245063c0acb3215ULL, { 0x30ce2f5b, 0x610e7271 }, 0x113b916468389235ULL },
+    { 0x6bc195877b7b8a7eULL, { 0x392004aa, 0x4a24e60c }, 0x530594fb17db6ba5ULL },
+    { 0x40a3fde23c7b43dbULL, { 0x4e712195, 0x6553e56e }, 0x320a799bc76a466aULL },
+    { 0x1d3dfc2866fbccbaULL, { 0x5075b517, 0x5fc42245 }, 0x18917f0061595bc3ULL },
+    { 0x19aeb14045a61121ULL, { 0x1bf6edec, 0x707e2f4b }, 0x6626672a070bcc7ULL },
+    { 0x44ff90486c531e9fULL, { 0x66598a, 0x8a90dc }, 0x32f6f2b0525199b0ULL },
+    { 0x3f3e7121092c5bcbULL, { 0x1c754df7, 0x5951a1b9 }, 0x14267f50b7ef375dULL },
+    { 0x60e2dafb7e50a67eULL, { 0x4d96c66e, 0x65bd878d }, 0x49e31715ac393f8bULL },
+    { 0x656286667e0e6e29ULL, { 0x9d971a2, 0xacda23b }, 0x5c6ee315ead6cb4fULL },
+    { 0x1114e0974255d507ULL, { 0x1c693, 0x2d6ff }, 0xaae42e4b35f6e60ULL },
+    { 0x508c8baf3a70ff5aULL, { 0x3b26b779, 0x6ad78745 }, 0x2c98387636c4b365ULL },
+    { 0x5b47bc666bf1f9cfULL, { 0x10a87ed6, 0x187d358a }, 0x3e1767155848368bULL },
+    { 0x50954e3744460395ULL, { 0x7a42263, 0xcdaa048 }, 0x2fe739f0aee1fee1ULL },
+    { 0x20020b406550dd8fULL, { 0x3318539, 0x42eead0 }, 0x186f326325fa346bULL },
+    { 0x5bcb0b872439ffd5ULL, { 0x6f61fb2, 0x9af7344 }, 0x41fa1e3bec3c1b30ULL },
+    { 0x7a670f365db87a53ULL, { 0x417e102, 0x3bb54c67 }, 0x8642a558304fd9eULL },
+    { 0x1ef0db1e7bab1cd0ULL, { 0x2b60cf38, 0x4188f78f }, 0x147ae0d6226b2ee6ULL }
+  };
+
+  for (const auto &T : Tests) {
+    EXPECT_EQ(T.Result, BP(T.Prob[0], T.Prob[1]).scale(T.Num));
+  }
+}
+
+}
diff --git a/unittests/Support/CMakeLists.txt b/unittests/Support/CMakeLists.txt
index 44f80ac222..0ea9310333 100644
--- a/unittests/Support/CMakeLists.txt
+++ b/unittests/Support/CMakeLists.txt
@@ -7,6 +7,7 @@ add_llvm_unittest(SupportTests
   AllocatorTest.cpp
   ArrayRecyclerTest.cpp
   BlockFrequencyTest.cpp
+  BranchProbabilityTest.cpp
   Casting.cpp
   CommandLineTest.cpp
   CompressionTest.cpp
diff --git a/utils/FileUpdate/FileUpdate.cpp b/utils/FileUpdate/FileUpdate.cpp
index 5ccf3f32a0..1bf1248f65 100644
--- a/utils/FileUpdate/FileUpdate.cpp
+++ b/utils/FileUpdate/FileUpdate.cpp
@@ -14,6 +14,7 @@
 //===----------------------------------------------------------------------===//
 
 #include "llvm/Support/CommandLine.h"
+#include "llvm/Support/FileSystem.h"
 #include "llvm/Support/MemoryBuffer.h"
 #include "llvm/Support/PrettyStackTrace.h"
 #include "llvm/Support/Signals.h"
diff --git a/utils/TableGen/AsmWriterEmitter.cpp b/utils/TableGen/AsmWriterEmitter.cpp
index 666d0a1b89..8e83df2009 100644
--- a/utils/TableGen/AsmWriterEmitter.cpp
+++ b/utils/TableGen/AsmWriterEmitter.cpp
@@ -15,6 +15,7 @@
 #include "AsmWriterInst.h"
 #include "CodeGenTarget.h"
 #include "SequenceToOffsetTable.h"
+#include "llvm/ADT/SmallString.h"
 #include "llvm/ADT/StringExtras.h"
 #include "llvm/ADT/Twine.h"
 #include "llvm/Support/Debug.h"
diff --git a/utils/TableGen/InstrInfoEmitter.cpp b/utils/TableGen/InstrInfoEmitter.cpp
index afc05b6009..76f05cea3f 100644
--- a/utils/TableGen/InstrInfoEmitter.cpp
+++ b/utils/TableGen/InstrInfoEmitter.cpp
@@ -523,20 +523,20 @@ void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num,
   // Emit the implicit uses and defs lists...
   std::vector<Record*> UseList = Inst.TheDef->getValueAsListOfDefs("Uses");
   if (UseList.empty())
-    OS << "NULL, ";
+    OS << "nullptr, ";
   else
     OS << "ImplicitList" << EmittedLists[UseList] << ", ";
 
   std::vector<Record*> DefList = Inst.TheDef->getValueAsListOfDefs("Defs");
   if (DefList.empty())
-    OS << "NULL, ";
+    OS << "nullptr, ";
   else
     OS << "ImplicitList" << EmittedLists[DefList] << ", ";
 
   // Emit the operand info.
   std::vector<std::string> OperandInfo = GetOperandInfo(Inst);
   if (OperandInfo.empty())
-    OS << "0";
+    OS << "nullptr";
   else
     OS << "OperandInfo" << OpInfo.find(OperandInfo)->second;
 
@@ -548,10 +548,10 @@ void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num,
   else if (!Inst.DeprecatedReason.empty())
     // Emit the Subtarget feature.
     OS << "," << Target.getInstNamespace() << "::" << Inst.DeprecatedReason
-       << ",0";
+       << ",nullptr";
   else
     // Instruction isn't deprecated.
-    OS << ",0,0";
+    OS << ",0,nullptr";
 
   OS << " },  // Inst #" << Num << " = " << Inst.TheDef->getName() << "\n";
 }
diff --git a/utils/TableGen/RegisterInfoEmitter.cpp b/utils/TableGen/RegisterInfoEmitter.cpp
index bc252a9bde..573c37f4ee 100644
--- a/utils/TableGen/RegisterInfoEmitter.cpp
+++ b/utils/TableGen/RegisterInfoEmitter.cpp
@@ -225,7 +225,7 @@ EmitRegUnitPressure(raw_ostream &OS, const CodeGenRegBank &RegBank,
   for (unsigned i = 0; i < NumSets; ++i ) {
     OS << "    \"" << RegBank.getRegSetAt(i).Name << "\",\n";
   }
-  OS << "    0 };\n"
+  OS << "    nullptr };\n"
      << "  return PressureNameTable[Idx];\n"
      << "}\n\n";
 
@@ -1068,7 +1068,7 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
   // Now that all of the structs have been emitted, emit the instances.
   if (!RegisterClasses.empty()) {
     OS << "\nstatic const TargetRegisterClass *const "
-       << "NullRegClasses[] = { NULL };\n\n";
+       << "NullRegClasses[] = { nullptr };\n\n";
 
     // Emit register class bit mask tables. The first bit mask emitted for a
     // register class, RC, is the set of sub-classes, including RC itself.
@@ -1135,7 +1135,7 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
          << RC.getName() << "Superclasses[] = {\n";
       for (unsigned i = 0; i != Supers.size(); ++i)
         OS << "  &" << Supers[i]->getQualifiedName() << "RegClass,\n";
-      OS << "  NULL\n};\n\n";
+      OS << "  nullptr\n};\n\n";
     }
 
     // Emit methods.
@@ -1189,7 +1189,7 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
       else
         OS << RC.getName() << "Superclasses,\n    ";
       if (RC.AltOrderSelect.empty())
-        OS << "0\n";
+        OS << "nullptr\n";
       else
         OS << RC.getName() << "GetRawAllocationOrder\n";
       OS << "  };\n\n";
@@ -1258,7 +1258,7 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
        << "  if (!Idx) return RC;\n  --Idx;\n"
        << "  assert(Idx < " << SubRegIndices.size() << " && \"Bad subreg\");\n"
        << "  unsigned TV = Table[RC->getID()][Idx];\n"
-       << "  return TV ? getRegClass(TV - 1) : 0;\n}\n\n";
+       << "  return TV ? getRegClass(TV - 1) : nullptr;\n}\n\n";
   }
 
   EmitRegUnitPressure(OS, RegBank, ClassName);
diff --git a/utils/TableGen/SubtargetEmitter.cpp b/utils/TableGen/SubtargetEmitter.cpp
index 39130bde06..846a485959 100644
--- a/utils/TableGen/SubtargetEmitter.cpp
+++ b/utils/TableGen/SubtargetEmitter.cpp
@@ -578,7 +578,7 @@ EmitItineraries(raw_ostream &OS,
     OS << "\n";
     OS << "static const llvm::InstrItinerary ";
     if (ItinList.empty()) {
-      OS << '*' << Name << " = 0;\n";
+      OS << '*' << Name << " = nullptr;\n";
       continue;
     }