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author | Tim Northover <tnorthover@apple.com> | 2014-04-30 16:13:34 +0000 |
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committer | Tim Northover <tnorthover@apple.com> | 2014-04-30 16:13:34 +0000 |
commit | b1c1b8a78dce82d3740316ddf94029696ba68674 (patch) | |
tree | 1b831b7fe06a60cc0cb339f88447b561781e5f49 | |
parent | 83286f081d7245a35841c9abec3672f467fd662f (diff) | |
download | llvm_35a-b1c1b8a78dce82d3740316ddf94029696ba68674.tar.gz |
ARM64: print fp immediates without using scientific notation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207669 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r-- | lib/Target/ARM64/InstPrinter/ARM64InstPrinter.cpp | 10 | ||||
-rw-r--r-- | test/CodeGen/ARM64/fast-isel-materialize.ll | 4 | ||||
-rw-r--r-- | test/CodeGen/ARM64/vector-imm.ll | 6 | ||||
-rw-r--r-- | test/CodeGen/ARM64/vector-insertion.ll | 2 | ||||
-rw-r--r-- | test/MC/ARM64/advsimd.s | 6 | ||||
-rw-r--r-- | test/MC/ARM64/fp-encoding.s | 14 | ||||
-rw-r--r-- | test/MC/ARM64/optional-hash.s | 2 | ||||
-rw-r--r-- | test/MC/Disassembler/ARM64/advsimd.txt | 6 | ||||
-rw-r--r-- | test/MC/Disassembler/ARM64/scalar-fp.txt | 8 |
9 files changed, 28 insertions, 30 deletions
diff --git a/lib/Target/ARM64/InstPrinter/ARM64InstPrinter.cpp b/lib/Target/ARM64/InstPrinter/ARM64InstPrinter.cpp index 266b5f294b..65d5eae2d2 100644 --- a/lib/Target/ARM64/InstPrinter/ARM64InstPrinter.cpp +++ b/lib/Target/ARM64/InstPrinter/ARM64InstPrinter.cpp @@ -1221,12 +1221,10 @@ void ARM64InstPrinter::printMemoryRegOffset(const MCInst *MI, unsigned OpNum, void ARM64InstPrinter::printFPImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O) { const MCOperand &MO = MI->getOperand(OpNum); - O << '#'; - if (MO.isFPImm()) - // FIXME: Should this ever happen? - O << MO.getFPImm(); - else - O << ARM64_AM::getFPImmFloat(MO.getImm()); + float FPImm = MO.isFPImm() ? MO.getFPImm() : ARM64_AM::getFPImmFloat(MO.getImm()); + + // 8 decimal places are enough to perfectly represent permitted floats. + O << format("#%.8f", FPImm); } static unsigned getNextVectorRegister(unsigned Reg, unsigned Stride = 1) { diff --git a/test/CodeGen/ARM64/fast-isel-materialize.ll b/test/CodeGen/ARM64/fast-isel-materialize.ll index fa2daf73db..ffac131f0c 100644 --- a/test/CodeGen/ARM64/fast-isel-materialize.ll +++ b/test/CodeGen/ARM64/fast-isel-materialize.ll @@ -3,14 +3,14 @@ ; Materialize using fmov define void @float_(float* %value) { ; CHECK: @float_ -; CHECK: fmov s0, #1.250000e+00 +; CHECK: fmov s0, #1.25000000 store float 1.250000e+00, float* %value, align 4 ret void } define void @double_(double* %value) { ; CHECK: @double_ -; CHECK: fmov d0, #1.250000e+00 +; CHECK: fmov d0, #1.25000000 store double 1.250000e+00, double* %value, align 8 ret void } diff --git a/test/CodeGen/ARM64/vector-imm.ll b/test/CodeGen/ARM64/vector-imm.ll index 2a9450f4e2..a84f804c8c 100644 --- a/test/CodeGen/ARM64/vector-imm.ll +++ b/test/CodeGen/ARM64/vector-imm.ll @@ -42,7 +42,7 @@ define <16 x i8> @v_bicimmQ(<16 x i8>* %A) nounwind { define <2 x double> @foo(<2 x double> %bar) nounwind { ; CHECK: foo -; CHECK: fmov.2d v1, #1.000000e+00 +; CHECK: fmov.2d v1, #1.0000000 %add = fadd <2 x double> %bar, <double 1.0, double 1.0> ret <2 x double> %add } @@ -122,13 +122,13 @@ ret <2 x i64> <i64 71777214294589695, i64 71777214294589695> define <4 x i32> @movi_4s_imm_t11() nounwind readnone ssp { entry: ; CHECK-LABEL: movi_4s_imm_t11: -; CHECK: fmov.4s v0, #-3.281250e-01 +; CHECK: fmov.4s v0, #-0.32812500 ret <4 x i32> <i32 3198681088, i32 3198681088, i32 3198681088, i32 3198681088> } define <2 x i64> @movi_2d_imm_t12() nounwind readnone ssp { entry: ; CHECK-LABEL: movi_2d_imm_t12: -; CHECK: fmov.2d v0, #-1.718750e-01 +; CHECK: fmov.2d v0, #-0.17187500 ret <2 x i64> <i64 13818732506632945664, i64 13818732506632945664> } diff --git a/test/CodeGen/ARM64/vector-insertion.ll b/test/CodeGen/ARM64/vector-insertion.ll index b9f3fc131e..0926bcfde9 100644 --- a/test/CodeGen/ARM64/vector-insertion.ll +++ b/test/CodeGen/ARM64/vector-insertion.ll @@ -25,7 +25,7 @@ entry: ret void ; CHECK-LABEL: test1f - ; CHECK: fmov s[[TEMP:[0-9]+]], #1.000000e+00 + ; CHECK: fmov s[[TEMP:[0-9]+]], #1.0000000 ; CHECK: dup.4s v[[TEMP2:[0-9]+]], v[[TEMP]][0] ; CHECK: ins.s v[[TEMP2]][0], v0[0] ; CHECK: str q[[TEMP2]], [x0] diff --git a/test/MC/ARM64/advsimd.s b/test/MC/ARM64/advsimd.s index 107d945478..bf8f3efb06 100644 --- a/test/MC/ARM64/advsimd.s +++ b/test/MC/ARM64/advsimd.s @@ -816,13 +816,13 @@ foo: fmov.2d v0, #1.250000e-01 -; CHECK: fmov.2d v0, #1.250000e-01 ; encoding: [0x00,0xf4,0x02,0x6f] +; CHECK: fmov.2d v0, #0.12500000 ; encoding: [0x00,0xf4,0x02,0x6f] fmov.2s v0, #1.250000e-01 fmov.4s v0, #1.250000e-01 -; CHECK: fmov.2s v0, #1.250000e-01 ; encoding: [0x00,0xf4,0x02,0x0f] -; CHECK: fmov.4s v0, #1.250000e-01 ; encoding: [0x00,0xf4,0x02,0x4f] +; CHECK: fmov.2s v0, #0.12500000 ; encoding: [0x00,0xf4,0x02,0x0f] +; CHECK: fmov.4s v0, #0.12500000 ; encoding: [0x00,0xf4,0x02,0x4f] orr.2s v0, #1 orr.2s v0, #1, lsl #0 diff --git a/test/MC/ARM64/fp-encoding.s b/test/MC/ARM64/fp-encoding.s index 08a7b6f027..684d9883e3 100644 --- a/test/MC/ARM64/fp-encoding.s +++ b/test/MC/ARM64/fp-encoding.s @@ -333,13 +333,13 @@ foo: fmov s2, #0.0 fmov d2, #0.0 -; CHECK: fmov s1, #1.250000e-01 ; encoding: [0x01,0x10,0x28,0x1e] -; CHECK: fmov s1, #1.250000e-01 ; encoding: [0x01,0x10,0x28,0x1e] -; CHECK: fmov d1, #1.250000e-01 ; encoding: [0x01,0x10,0x68,0x1e] -; CHECK: fmov d1, #1.250000e-01 ; encoding: [0x01,0x10,0x68,0x1e] -; CHECK: fmov d1, #-4.843750e-01 ; encoding: [0x01,0xf0,0x7b,0x1e] -; CHECK: fmov d1, #4.843750e-01 ; encoding: [0x01,0xf0,0x6b,0x1e] -; CHECK: fmov d3, #3.000000e+00 ; encoding: [0x03,0x10,0x61,0x1e] +; CHECK: fmov s1, #0.12500000 ; encoding: [0x01,0x10,0x28,0x1e] +; CHECK: fmov s1, #0.12500000 ; encoding: [0x01,0x10,0x28,0x1e] +; CHECK: fmov d1, #0.12500000 ; encoding: [0x01,0x10,0x68,0x1e] +; CHECK: fmov d1, #0.12500000 ; encoding: [0x01,0x10,0x68,0x1e] +; CHECK: fmov d1, #-0.48437500 ; encoding: [0x01,0xf0,0x7b,0x1e] +; CHECK: fmov d1, #0.48437500 ; encoding: [0x01,0xf0,0x6b,0x1e] +; CHECK: fmov d3, #3.00000000 ; encoding: [0x03,0x10,0x61,0x1e] ; CHECK: fmov s2, wzr ; encoding: [0xe2,0x03,0x27,0x1e] ; CHECK: fmov d2, xzr ; encoding: [0xe2,0x03,0x67,0x9e] diff --git a/test/MC/ARM64/optional-hash.s b/test/MC/ARM64/optional-hash.s index f7c5e21832..71e2fda217 100644 --- a/test/MC/ARM64/optional-hash.s +++ b/test/MC/ARM64/optional-hash.s @@ -13,7 +13,7 @@ adds x3, x4, 1024, lsl 12 add sp, x2, x3, uxtx 0 ; FP immediates -; CHECK: fmov s1, #1.250000e-01 ; encoding: [0x01,0x10,0x28,0x1e] +; CHECK: fmov s1, #0.12500000 ; encoding: [0x01,0x10,0x28,0x1e] fmov s1, 0.125 ; Barrier operand diff --git a/test/MC/Disassembler/ARM64/advsimd.txt b/test/MC/Disassembler/ARM64/advsimd.txt index 36aae17a5e..745ff893aa 100644 --- a/test/MC/Disassembler/ARM64/advsimd.txt +++ b/test/MC/Disassembler/ARM64/advsimd.txt @@ -568,13 +568,13 @@ 0x00 0xf4 0x02 0x6f -# CHECK: fmov.2d v0, #1.250000e-01 +# CHECK: fmov.2d v0, #0.12500000 0x00 0xf4 0x02 0x0f 0x00 0xf4 0x02 0x4f -# CHECK: fmov.2s v0, #1.250000e-01 -# CHECK: fmov.4s v0, #1.250000e-01 +# CHECK: fmov.2s v0, #0.12500000 +# CHECK: fmov.4s v0, #0.12500000 0x20 0x14 0x00 0x0f 0x20 0x34 0x00 0x0f diff --git a/test/MC/Disassembler/ARM64/scalar-fp.txt b/test/MC/Disassembler/ARM64/scalar-fp.txt index 1f76dee64d..f139700164 100644 --- a/test/MC/Disassembler/ARM64/scalar-fp.txt +++ b/test/MC/Disassembler/ARM64/scalar-fp.txt @@ -184,10 +184,10 @@ 0x01 0xf0 0x7b 0x1e 0x01 0xf0 0x6b 0x1e -# CHECK: fmov s1, #1.250000e-01 -# CHECK: fmov d1, #1.250000e-01 -# CHECK: fmov d1, #-4.843750e-01 -# CHECK: fmov d1, #4.843750e-01 +# CHECK: fmov s1, #0.12500000 +# CHECK: fmov d1, #0.12500000 +# CHECK: fmov d1, #-0.48437500 +# CHECK: fmov d1, #0.48437500 0x41 0x40 0x20 0x1e 0x41 0x40 0x60 0x1e |