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| author | Caio Oliveira <caio.oliveira@intel.com> | 2024-02-17 20:58:59 -0800 |
|---|---|---|
| committer | Marge Bot <emma+marge@anholt.net> | 2024-02-28 05:45:38 +0000 |
| commit | 625338389ecb03a16b1f83ee987f26ce7ec46597 (patch) | |
| tree | 95d5cc178eb4f06d1bb6ca7fd22bbf979f6f8723 | |
| parent | 4e16c565f41a3e516f58d0d2a4db2cc998340ca1 (diff) | |
| download | mesa3d-625338389ecb03a16b1f83ee987f26ce7ec46597.tar.gz | |
intel/brw: Update comments for FK macro
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27691>
| -rw-r--r-- | src/intel/compiler/brw_inst.h | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/src/intel/compiler/brw_inst.h b/src/intel/compiler/brw_inst.h index 46a25931aaf..6b51756a33d 100644 --- a/src/intel/compiler/brw_inst.h +++ b/src/intel/compiler/brw_inst.h @@ -281,7 +281,7 @@ brw_inst_##name(const struct intel_device_info *devinfo, const brw_inst *inst)\ /* Macro for fields that become a constant in Gfx12+ not actually represented * in the instruction. */ -#define FK(name, hi4, lo4, const12) \ +#define FK(name, hi9, lo9, const12) \ static inline void \ brw_inst_set_##name(const struct intel_device_info *devinfo, \ brw_inst *inst, uint64_t v) \ @@ -289,7 +289,7 @@ brw_inst_set_##name(const struct intel_device_info *devinfo, \ if (devinfo->ver >= 12) \ assert(v == (const12)); \ else \ - brw_inst_set_bits(inst, hi4, lo4, v); \ + brw_inst_set_bits(inst, hi9, lo9, v); \ } \ static inline uint64_t \ brw_inst_##name(const struct intel_device_info *devinfo, \ @@ -298,7 +298,7 @@ brw_inst_##name(const struct intel_device_info *devinfo, \ if (devinfo->ver >= 12) \ return (const12); \ else \ - return brw_inst_bits(inst, hi4, lo4); \ + return brw_inst_bits(inst, hi9, lo9); \ } FV20(src1_vstride, /* 9+ */ 120, 117, /* 12+ */ 119, 116, /* 20+ */ 118, 116) @@ -382,7 +382,7 @@ FF(nib_control, F(no_dd_check, /* 9+ */ 10, 10, /* 12+ */ -1, -1) F(no_dd_clear, /* 9+ */ 9, 9, /* 12+ */ -1, -1) F20(swsb, /* 9+ */ -1, -1, /* 12+ */ 15, 8, /* 20+ */ 17, 8) -FK(access_mode, /* 4+ */ 8, 8, /* 12+ */ BRW_ALIGN_1) +FK(access_mode, /* 9+ */ 8, 8, /* 12+ */ BRW_ALIGN_1) /* Bit 7 is Reserved (for future Opcode expansion) */ F(hw_opcode, /* 9+ */ 6, 0, /* 12+ */ 6, 0) @@ -432,7 +432,7 @@ F20(3src_qtr_control, /* 9+ */ 13, 12, /* 12+ */ 21, 20, /* 20+ */ 25, 2 F(3src_no_dd_check, /* 9+ */ 10, 10, /* 12+ */ -1, -1) F(3src_no_dd_clear, /* 9+ */ 9, 9, /* 12+ */ -1, -1) F(3src_mask_control, /* 9+ */ 34, 34, /* 12+ */ 31, 31) -FK(3src_access_mode, /* 4+ */ 8, 8, /* 12+ */ BRW_ALIGN_1) +FK(3src_access_mode, /* 9+ */ 8, 8, /* 12+ */ BRW_ALIGN_1) F(3src_swsb, /* 9+ */ -1, -1, /* 12+ */ 15, 8) /* Bit 7 is Reserved (for future Opcode expansion) */ F(3src_hw_opcode, /* 9+ */ 6, 0, /* 12+ */ 6, 0) |