intel/brw: Remove Gfx8- code from builder

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27691>

1 files changed, 4 insertions, 58 deletions

diff --git a/src/intel/compiler/brw_fs_builder.h b/src/intel/compiler/brw_fs_builder.h
index c6bca167e47..897eee51f22 100644
--- a/src/intel/compiler/brw_fs_builder.h
+++ b/src/intel/compiler/brw_fs_builder.h
@@ -280,20 +280,7 @@ namespace brw {
       instruction *
       emit(enum opcode opcode, const dst_reg &dst, const src_reg &src0) const
       {
-         switch (opcode) {
-         case SHADER_OPCODE_RCP:
-         case SHADER_OPCODE_RSQ:
-         case SHADER_OPCODE_SQRT:
-         case SHADER_OPCODE_EXP2:
-         case SHADER_OPCODE_LOG2:
-         case SHADER_OPCODE_SIN:
-         case SHADER_OPCODE_COS:
-            return emit(instruction(opcode, dispatch_width(), dst,
-                                    fix_math_operand(src0)));
-
-         default:
-            return emit(instruction(opcode, dispatch_width(), dst, src0));
-         }
+         return emit(instruction(opcode, dispatch_width(), dst, src0));
       }
 
       /**
@@ -303,19 +290,8 @@ namespace brw {
       emit(enum opcode opcode, const dst_reg &dst, const src_reg &src0,
            const src_reg &src1) const
       {
-         switch (opcode) {
-         case SHADER_OPCODE_POW:
-         case SHADER_OPCODE_INT_QUOTIENT:
-         case SHADER_OPCODE_INT_REMAINDER:
-            return emit(instruction(opcode, dispatch_width(), dst,
-                                    fix_math_operand(src0),
-                                    fix_math_operand(src1)));
-
-         default:
-            return emit(instruction(opcode, dispatch_width(), dst,
-                                    src0, src1));
-
-         }
+         return emit(instruction(opcode, dispatch_width(), dst,
+                                 src0, src1));
       }
 
       /**
@@ -755,7 +731,7 @@ namespace brw {
       LRP(const dst_reg &dst, const src_reg &x, const src_reg &y,
           const src_reg &a) const
       {
-         if (shader->devinfo->ver >= 6 && shader->devinfo->ver <= 10) {
+         if (shader->devinfo->ver <= 10) {
             /* The LRP instruction actually does op1 * op0 + op2 * (1 - op0), so
              * we need to reorder the operands.
              */
@@ -881,36 +857,6 @@ namespace brw {
          return expanded;
       }
 
-      /**
-       * Workaround for source register modes not supported by the math
-       * instruction.
-       */
-      src_reg
-      fix_math_operand(const src_reg &src) const
-      {
-         /* Can't do hstride == 0 args on gfx6 math, so expand it out. We
-          * might be able to do better by doing execsize = 1 math and then
-          * expanding that result out, but we would need to be careful with
-          * masking.
-          *
-          * Gfx6 hardware ignores source modifiers (negate and abs) on math
-          * instructions, so we also move to a temp to set those up.
-          *
-          * Gfx7 relaxes most of the above restrictions, but still can't use IMM
-          * operands to math
-          */
-         if ((shader->devinfo->ver == 6 &&
-              (src.file == IMM || src.file == UNIFORM ||
-               src.abs || src.negate)) ||
-             (shader->devinfo->ver == 7 && src.file == IMM)) {
-            const dst_reg tmp = vgrf(src.type);
-            MOV(tmp, src);
-            return tmp;
-         } else {
-            return src;
-         }
-      }
-
       bblock_t *block;
       exec_node *cursor;