intel/brw: Remove runtime_check_aads_emit

It was used for Gfx4 payload.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27691>

10 files changed, 13 insertions, 22 deletions

diff --git a/src/intel/compiler/brw_compile_gs.cpp b/src/intel/compiler/brw_compile_gs.cpp
index 5ec51e376c9..becafac6858 100644
--- a/src/intel/compiler/brw_compile_gs.cpp
+++ b/src/intel/compiler/brw_compile_gs.cpp
@@ -251,7 +251,7 @@ brw_compile_gs(const struct brw_compiler *compiler,
          v.payload().num_regs / reg_unit(compiler->devinfo);
 
       fs_generator g(compiler, &params->base,
-                     &prog_data->base.base, false, MESA_SHADER_GEOMETRY);
+                     &prog_data->base.base, MESA_SHADER_GEOMETRY);
       if (unlikely(debug_enabled)) {
          const char *label =
             nir->info.label ? nir->info.label : "unnamed";
diff --git a/src/intel/compiler/brw_compile_tcs.cpp b/src/intel/compiler/brw_compile_tcs.cpp
index 83ef3ff20cf..c0f294608c8 100644
--- a/src/intel/compiler/brw_compile_tcs.cpp
+++ b/src/intel/compiler/brw_compile_tcs.cpp
@@ -145,7 +145,7 @@ brw_compile_tcs(const struct brw_compiler *compiler,
    prog_data->base.base.dispatch_grf_start_reg = v.payload().num_regs / reg_unit(devinfo);
 
    fs_generator g(compiler, &params->base,
-                  &prog_data->base.base, false, MESA_SHADER_TESS_CTRL);
+                  &prog_data->base.base, MESA_SHADER_TESS_CTRL);
    if (unlikely(debug_enabled)) {
       g.enable_debug(ralloc_asprintf(params->base.mem_ctx,
                                      "%s tessellation control shader %s",
diff --git a/src/intel/compiler/brw_compile_vs.cpp b/src/intel/compiler/brw_compile_vs.cpp
index ecc07765f95..221a96b830d 100644
--- a/src/intel/compiler/brw_compile_vs.cpp
+++ b/src/intel/compiler/brw_compile_vs.cpp
@@ -112,7 +112,7 @@ brw_compile_vs(const struct brw_compiler *compiler,
       v.payload().num_regs / reg_unit(compiler->devinfo);
 
    fs_generator g(compiler, &params->base,
-                  &prog_data->base.base, v.runtime_check_aads_emit,
+                  &prog_data->base.base,
                   MESA_SHADER_VERTEX);
    if (unlikely(debug_enabled)) {
       const char *debug_name =
diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp
index d07f1d18359..0eb8513e552 100644
--- a/src/intel/compiler/brw_fs.cpp
+++ b/src/intel/compiler/brw_fs.cpp
@@ -2908,8 +2908,7 @@ fs_visitor::run_fs(bool allow_spilling, bool do_rep_send)
 
    assert(stage == MESA_SHADER_FRAGMENT);
 
-   payload_ = new fs_thread_payload(*this, source_depth_to_render_target,
-                                    runtime_check_aads_emit);
+   payload_ = new fs_thread_payload(*this, source_depth_to_render_target);
 
    if (do_rep_send) {
       assert(dispatch_width == 16);
@@ -3687,7 +3686,7 @@ brw_compile_fs(const struct brw_compiler *compiler,
       simd8_cfg = NULL;
 
    fs_generator g(compiler, &params->base, &prog_data->base,
-                  v8 && v8->runtime_check_aads_emit, MESA_SHADER_FRAGMENT);
+                  MESA_SHADER_FRAGMENT);
 
    if (unlikely(debug_enabled)) {
       g.enable_debug(ralloc_asprintf(params->base.mem_ctx,
@@ -3932,13 +3931,12 @@ brw_compile_cs(const struct brw_compiler *compiler,
    }
 
    assert(selected_simd < 3);
-   fs_visitor *selected = v[selected_simd].get();
 
    if (!nir->info.workgroup_size_variable)
       prog_data->prog_mask = 1 << selected_simd;
 
    fs_generator g(compiler, &params->base, &prog_data->base,
-                  selected->runtime_check_aads_emit, MESA_SHADER_COMPUTE);
+                  MESA_SHADER_COMPUTE);
    if (unlikely(debug_enabled)) {
       char *name = ralloc_asprintf(params->base.mem_ctx,
                                    "%s compute shader %s",
@@ -4116,7 +4114,7 @@ brw_compile_bs(const struct brw_compiler *compiler,
    prog_data->num_resume_shaders = num_resume_shaders;
 
    fs_generator g(compiler, &params->base, &prog_data->base,
-                  false, shader->info.stage);
+                  shader->info.stage);
    if (unlikely(debug_enabled)) {
       char *name = ralloc_asprintf(params->base.mem_ctx,
                                    "%s %s shader %s",
diff --git a/src/intel/compiler/brw_fs.h b/src/intel/compiler/brw_fs.h
index 69da8669596..9e246cfdcca 100644
--- a/src/intel/compiler/brw_fs.h
+++ b/src/intel/compiler/brw_fs.h
@@ -128,8 +128,7 @@ struct gs_thread_payload : public thread_payload {
 
 struct fs_thread_payload : public thread_payload {
    fs_thread_payload(const fs_visitor &v,
-                     bool &source_depth_to_render_target,
-                     bool &runtime_check_aads_emit);
+                     bool &source_depth_to_render_target);
 
    uint8_t subspan_coord_reg[2];
    uint8_t source_depth_reg[2];
@@ -371,7 +370,6 @@ public:
    }
 
    bool source_depth_to_render_target;
-   bool runtime_check_aads_emit;
 
    fs_reg pixel_x;
    fs_reg pixel_y;
@@ -426,7 +424,6 @@ public:
    fs_generator(const struct brw_compiler *compiler,
                 const struct brw_compile_params *params,
                 struct brw_stage_prog_data *prog_data,
-                bool runtime_check_aads_emit,
                 gl_shader_stage stage);
    ~fs_generator();
 
@@ -488,7 +485,6 @@ private:
    unsigned dispatch_width; /**< 8, 16 or 32 */
 
    exec_list discard_halt_patches;
-   bool runtime_check_aads_emit;
    bool debug_flag;
    const char *shader_name;
    gl_shader_stage stage;
diff --git a/src/intel/compiler/brw_fs_generator.cpp b/src/intel/compiler/brw_fs_generator.cpp
index 6a7026c3622..f228b8f85a0 100644
--- a/src/intel/compiler/brw_fs_generator.cpp
+++ b/src/intel/compiler/brw_fs_generator.cpp
@@ -129,13 +129,12 @@ brw_reg_from_fs_reg(const struct intel_device_info *devinfo, fs_inst *inst,
 fs_generator::fs_generator(const struct brw_compiler *compiler,
                            const struct brw_compile_params *params,
                            struct brw_stage_prog_data *prog_data,
-                           bool runtime_check_aads_emit,
                            gl_shader_stage stage)
 
    : compiler(compiler), params(params),
      devinfo(compiler->devinfo),
      prog_data(prog_data), dispatch_width(0),
-     runtime_check_aads_emit(runtime_check_aads_emit), debug_flag(false),
+     debug_flag(false),
      shader_name(NULL), stage(stage), mem_ctx(params->mem_ctx)
 {
    p = rzalloc(mem_ctx, struct brw_codegen);
diff --git a/src/intel/compiler/brw_fs_thread_payload.cpp b/src/intel/compiler/brw_fs_thread_payload.cpp
index 1a52c420d0d..085d55e6da1 100644
--- a/src/intel/compiler/brw_fs_thread_payload.cpp
+++ b/src/intel/compiler/brw_fs_thread_payload.cpp
@@ -303,8 +303,7 @@ setup_fs_payload_gfx9(fs_thread_payload &payload,
 }
 
 fs_thread_payload::fs_thread_payload(const fs_visitor &v,
-                                     bool &source_depth_to_render_target,
-                                     bool &runtime_check_aads_emit)
+                                     bool &source_depth_to_render_target)
   : subspan_coord_reg(),
     source_depth_reg(),
     source_w_reg(),
diff --git a/src/intel/compiler/brw_fs_visitor.cpp b/src/intel/compiler/brw_fs_visitor.cpp
index 5bcf51c9be3..cade905f73b 100644
--- a/src/intel/compiler/brw_fs_visitor.cpp
+++ b/src/intel/compiler/brw_fs_visitor.cpp
@@ -1059,7 +1059,6 @@ fs_visitor::init()
 
    this->payload_ = NULL;
    this->source_depth_to_render_target = false;
-   this->runtime_check_aads_emit = false;
    this->first_non_payload_grf = 0;
 
    this->uniforms = 0;
diff --git a/src/intel/compiler/brw_mesh.cpp b/src/intel/compiler/brw_mesh.cpp
index 66a02b2275e..ca8aa9a759c 100644
--- a/src/intel/compiler/brw_mesh.cpp
+++ b/src/intel/compiler/brw_mesh.cpp
@@ -359,7 +359,7 @@ brw_compile_task(const struct brw_compiler *compiler,
    }
 
    fs_generator g(compiler, &params->base, &prog_data->base.base,
-                  false, MESA_SHADER_TASK);
+                  MESA_SHADER_TASK);
    if (unlikely(debug_enabled)) {
       g.enable_debug(ralloc_asprintf(params->base.mem_ctx,
                                      "%s task shader %s",
@@ -1590,7 +1590,7 @@ brw_compile_mesh(const struct brw_compiler *compiler,
    }
 
    fs_generator g(compiler, &params->base, &prog_data->base.base,
-                  false, MESA_SHADER_MESH);
+                  MESA_SHADER_MESH);
    if (unlikely(debug_enabled)) {
       g.enable_debug(ralloc_asprintf(params->base.mem_ctx,
                                      "%s mesh shader %s",
diff --git a/src/intel/compiler/brw_shader.cpp b/src/intel/compiler/brw_shader.cpp
index dd52ce41fc7..6999e3152af 100644
--- a/src/intel/compiler/brw_shader.cpp
+++ b/src/intel/compiler/brw_shader.cpp
@@ -1268,7 +1268,7 @@ brw_compile_tes(const struct brw_compiler *compiler,
    prog_data->base.dispatch_mode = INTEL_DISPATCH_MODE_SIMD8;
 
    fs_generator g(compiler, &params->base,
-                  &prog_data->base.base, false, MESA_SHADER_TESS_EVAL);
+                  &prog_data->base.base, MESA_SHADER_TESS_EVAL);
    if (unlikely(debug_enabled)) {
       g.enable_debug(ralloc_asprintf(params->base.mem_ctx,
                                      "%s tessellation evaluation shader %s",