aboutsummaryrefslogtreecommitdiff
path: root/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c
diff options
context:
space:
mode:
Diffstat (limited to 'drivers/phy/rockchip/phy-rockchip-snps-pcie3.c')
-rw-r--r--drivers/phy/rockchip/phy-rockchip-snps-pcie3.c230
1 files changed, 176 insertions, 54 deletions
diff --git a/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c b/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c
index 66c75f98e6..a4392daf4c 100644
--- a/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c
+++ b/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c
@@ -16,9 +16,27 @@
#include <dm/device_compat.h>
#include <dm/lists.h>
-#define GRF_PCIE30PHY_CON1 0x4
-#define GRF_PCIE30PHY_CON6 0x18
-#define GRF_PCIE30PHY_CON9 0x24
+/* Register for RK3568 */
+#define GRF_PCIE30PHY_CON1 0x4
+#define GRF_PCIE30PHY_CON6 0x18
+#define GRF_PCIE30PHY_CON9 0x24
+#define GRF_PCIE30PHY_DA_OCM (BIT(15) | BIT(31))
+#define GRF_PCIE30PHY_STATUS0 0x80
+#define GRF_PCIE30PHY_WR_EN (0xf << 16)
+#define SRAM_INIT_DONE(reg) (reg & BIT(14))
+
+#define RK3568_BIFURCATION_LANE_0_1 BIT(0)
+
+/* Register for RK3588 */
+#define PHP_GRF_PCIESEL_CON 0x100
+#define RK3588_PCIE3PHY_GRF_CMN_CON0 0x0
+#define RK3588_PCIE3PHY_GRF_PHY0_STATUS1 0x904
+#define RK3588_PCIE3PHY_GRF_PHY1_STATUS1 0xa04
+#define RK3588_SRAM_INIT_DONE(reg) (reg & BIT(0))
+
+#define RK3588_BIFURCATION_LANE_0_1 BIT(0)
+#define RK3588_BIFURCATION_LANE_2_3 BIT(1)
+#define RK3588_LANE_AGGREGATION BIT(2)
/**
* struct rockchip_p3phy_priv - RK DW PCIe PHY state
@@ -26,51 +44,144 @@
* @mmio: The base address of PHY internal registers
* @phy_grf: The regmap for controlling pipe signal
* @p30phy: The reset signal for PHY
- * @ref_clk_m: The reference clock of M for PHY
- * @ref_clk_n: The reference clock of N for PHY
- * @pclk: The clock for accessing PHY blocks
+ * @clks: The clocks for PHY
+ * @num_lanes: The number of lane to controller mappings
+ * @lanes: The lane to controller mapping
*/
struct rockchip_p3phy_priv {
void __iomem *mmio;
struct regmap *phy_grf;
+ struct regmap *pipe_grf;
struct reset_ctl p30phy;
- struct clk ref_clk_m;
- struct clk ref_clk_n;
- struct clk pclk;
+ struct clk_bulk clks;
+ int num_lanes;
+ u32 lanes[4];
};
-static int rochchip_p3phy_init(struct phy *phy)
+struct rockchip_p3phy_ops {
+ int (*phy_init)(struct phy *phy);
+};
+
+static int rockchip_p3phy_rk3568_init(struct phy *phy)
{
struct rockchip_p3phy_priv *priv = dev_get_priv(phy->dev);
+ bool bifurcation = false;
int ret;
+ u32 reg;
- ret = clk_enable(&priv->ref_clk_m);
- if (ret < 0 && ret != -ENOSYS)
- return ret;
+ /* Deassert PCIe PMA output clamp mode */
+ regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON9, GRF_PCIE30PHY_DA_OCM);
- ret = clk_enable(&priv->ref_clk_n);
- if (ret < 0 && ret != -ENOSYS)
- goto err_ref;
+ for (int i = 0; i < priv->num_lanes; i++) {
+ if (priv->lanes[i] > 1)
+ bifurcation = true;
+ }
- ret = clk_enable(&priv->pclk);
- if (ret < 0 && ret != -ENOSYS)
- goto err_pclk;
+ /* Set bifurcation if needed, and it doesn't care RC/EP */
+ if (bifurcation) {
+ regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON6,
+ GRF_PCIE30PHY_WR_EN | RK3568_BIFURCATION_LANE_0_1);
+ regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON1,
+ GRF_PCIE30PHY_DA_OCM);
+ } else {
+ regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON6,
+ GRF_PCIE30PHY_WR_EN & ~RK3568_BIFURCATION_LANE_0_1);
+ }
- reset_assert(&priv->p30phy);
+ reset_deassert(&priv->p30phy);
udelay(1);
+ ret = regmap_read_poll_timeout(priv->phy_grf,
+ GRF_PCIE30PHY_STATUS0,
+ reg, SRAM_INIT_DONE(reg),
+ 0, 500);
+ if (ret)
+ dev_err(phy->dev, "lock failed 0x%x\n", reg);
+
+ return ret;
+}
+
+static const struct rockchip_p3phy_ops rk3568_ops = {
+ .phy_init = rockchip_p3phy_rk3568_init,
+};
+
+static int rockchip_p3phy_rk3588_init(struct phy *phy)
+{
+ struct rockchip_p3phy_priv *priv = dev_get_priv(phy->dev);
+ u32 reg = 0;
+ u8 mode = 0;
+ int ret;
+
/* Deassert PCIe PMA output clamp mode */
- regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON9,
- (0x1 << 15) | (0x1 << 31));
+ regmap_write(priv->phy_grf, RK3588_PCIE3PHY_GRF_CMN_CON0,
+ BIT(8) | BIT(24));
+
+ /* Set bifurcation if needed */
+ for (int i = 0; i < priv->num_lanes; i++) {
+ if (!priv->lanes[i])
+ mode |= (BIT(i) << 3);
+
+ if (priv->lanes[i] > 1)
+ mode |= (BIT(i) >> 1);
+ }
+
+ if (!mode) {
+ reg = RK3588_LANE_AGGREGATION;
+ } else {
+ if (mode & (BIT(0) | BIT(1)))
+ reg |= RK3588_BIFURCATION_LANE_0_1;
+
+ if (mode & (BIT(2) | BIT(3)))
+ reg |= RK3588_BIFURCATION_LANE_2_3;
+ }
+
+ regmap_write(priv->phy_grf, RK3588_PCIE3PHY_GRF_CMN_CON0,
+ (0x7 << 16) | reg);
+
+ /* Set pcie1ln_sel in PHP_GRF_PCIESEL_CON */
+ reg = (mode & (BIT(6) | BIT(7))) >> 6;
+ if (reg)
+ regmap_write(priv->pipe_grf, PHP_GRF_PCIESEL_CON,
+ (reg << 16) | reg);
reset_deassert(&priv->p30phy);
udelay(1);
- return 0;
-err_pclk:
- clk_disable(&priv->ref_clk_n);
-err_ref:
- clk_disable(&priv->ref_clk_m);
+ ret = regmap_read_poll_timeout(priv->phy_grf,
+ RK3588_PCIE3PHY_GRF_PHY0_STATUS1,
+ reg, RK3588_SRAM_INIT_DONE(reg),
+ 0, 500);
+ ret |= regmap_read_poll_timeout(priv->phy_grf,
+ RK3588_PCIE3PHY_GRF_PHY1_STATUS1,
+ reg, RK3588_SRAM_INIT_DONE(reg),
+ 0, 500);
+ if (ret)
+ dev_err(phy->dev, "lock failed 0x%x\n", reg);
+
+ return ret;
+}
+
+static const struct rockchip_p3phy_ops rk3588_ops = {
+ .phy_init = rockchip_p3phy_rk3588_init,
+};
+
+static int rochchip_p3phy_init(struct phy *phy)
+{
+ struct rockchip_p3phy_ops *ops =
+ (struct rockchip_p3phy_ops *)dev_get_driver_data(phy->dev);
+ struct rockchip_p3phy_priv *priv = dev_get_priv(phy->dev);
+ int ret;
+
+ ret = clk_enable_bulk(&priv->clks);
+ if (ret)
+ return ret;
+
+ reset_assert(&priv->p30phy);
+ udelay(1);
+
+ ret = ops->phy_init(phy);
+ if (ret)
+ clk_disable_bulk(&priv->clks);
return ret;
}
@@ -79,9 +190,7 @@ static int rochchip_p3phy_exit(struct phy *phy)
{
struct rockchip_p3phy_priv *priv = dev_get_priv(phy->dev);
- clk_disable(&priv->ref_clk_m);
- clk_disable(&priv->ref_clk_n);
- clk_disable(&priv->pclk);
+ clk_disable_bulk(&priv->clks);
reset_assert(&priv->p30phy);
return 0;
@@ -90,48 +199,54 @@ static int rochchip_p3phy_exit(struct phy *phy)
static int rockchip_p3phy_probe(struct udevice *dev)
{
struct rockchip_p3phy_priv *priv = dev_get_priv(dev);
- struct udevice *syscon;
int ret;
priv->mmio = dev_read_addr_ptr(dev);
if (!priv->mmio)
return -EINVAL;
- ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev,
- "rockchip,phy-grf", &syscon);
- if (ret) {
- pr_err("unable to find syscon device for rockchip,phy-grf\n");
- return ret;
- }
-
- priv->phy_grf = syscon_get_regmap(syscon);
+ priv->phy_grf = syscon_regmap_lookup_by_phandle(dev, "rockchip,phy-grf");
if (IS_ERR(priv->phy_grf)) {
dev_err(dev, "failed to find rockchip,phy_grf regmap\n");
return PTR_ERR(priv->phy_grf);
}
- ret = reset_get_by_name(dev, "phy", &priv->p30phy);
- if (ret) {
- dev_err(dev, "no phy reset control specified\n");
- return ret;
+ if (device_is_compatible(dev, "rockchip,rk3588-pcie3-phy")) {
+ priv->pipe_grf =
+ syscon_regmap_lookup_by_phandle(dev, "rockchip,pipe-grf");
+ if (IS_ERR(priv->pipe_grf)) {
+ dev_err(dev, "failed to find rockchip,pipe_grf regmap\n");
+ return PTR_ERR(priv->pipe_grf);
+ }
}
- ret = clk_get_by_name(dev, "refclk_m", &priv->ref_clk_m);
- if (ret) {
- dev_err(dev, "failed to find ref clock M\n");
- return PTR_ERR(&priv->ref_clk_m);
+ ret = dev_read_size(dev, "data-lanes");
+ if (ret > 0) {
+ priv->num_lanes = ret / sizeof(u32);
+ if (priv->num_lanes < 2 ||
+ priv->num_lanes > ARRAY_SIZE(priv->lanes)) {
+ dev_err(dev, "unsupported data-lanes property size\n");
+ return -EINVAL;
+ }
+
+ ret = dev_read_u32_array(dev, "data-lanes", priv->lanes,
+ priv->num_lanes);
+ if (ret) {
+ dev_err(dev, "failed to read data-lanes property\n");
+ return ret;
+ }
}
- ret = clk_get_by_name(dev, "refclk_n", &priv->ref_clk_n);
+ ret = reset_get_by_name(dev, "phy", &priv->p30phy);
if (ret) {
- dev_err(dev, "failed to find ref clock N\n");
- return PTR_ERR(&priv->ref_clk_n);
+ dev_err(dev, "no phy reset control specified\n");
+ return ret;
}
- ret = clk_get_by_name(dev, "pclk", &priv->pclk);
+ ret = clk_get_bulk(dev, &priv->clks);
if (ret) {
- dev_err(dev, "failed to find pclk\n");
- return PTR_ERR(&priv->pclk);
+ dev_err(dev, "failed to get clocks\n");
+ return ret;
}
return 0;
@@ -143,7 +258,14 @@ static struct phy_ops rochchip_p3phy_ops = {
};
static const struct udevice_id rockchip_p3phy_of_match[] = {
- { .compatible = "rockchip,rk3568-pcie3-phy" },
+ {
+ .compatible = "rockchip,rk3568-pcie3-phy",
+ .data = (ulong)&rk3568_ops,
+ },
+ {
+ .compatible = "rockchip,rk3588-pcie3-phy",
+ .data = (ulong)&rk3588_ops,
+ },
{ },
};
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-11 01:42:24 +0000