diff options
Diffstat (limited to 'cachegrind/cg-x86.c')
| -rw-r--r-- | cachegrind/cg-x86.c | 57 |
1 files changed, 22 insertions, 35 deletions
diff --git a/cachegrind/cg-x86.c b/cachegrind/cg-x86.c index f9fa15ba7..be5eb82ec 100644 --- a/cachegrind/cg-x86.c +++ b/cachegrind/cg-x86.c @@ -42,12 +42,10 @@ static void micro_ops_warn(Int actual_size, Int used_size, Int line_size) { - VG_(message)(Vg_DebugMsg, - "warning: Pentium 4 with %d KB micro-op instruction trace cache", - actual_size); - VG_(message)(Vg_DebugMsg, - " Simulating a %d KB I-cache with %d B lines", - used_size, line_size); + VG_DMSG("warning: Pentium 4 with %d KB micro-op instruction trace cache", + actual_size); + VG_DMSG(" Simulating a %d KB I-cache with %d B lines", + used_size, line_size); } /* Intel method is truly wretched. We have to do an insane indexing into an @@ -67,9 +65,7 @@ Int Intel_cache_info(Int level, cache_t* I1c, cache_t* D1c, cache_t* L2c) Bool L2_found = False; if (level < 2) { - VG_(message)(Vg_DebugMsg, - "warning: CPUID level < 2 for Intel processor (%d)", - level); + VG_DMSG("warning: CPUID level < 2 for Intel processor (%d)", level); return -1; } @@ -85,9 +81,8 @@ Int Intel_cache_info(Int level, cache_t* I1c, cache_t* D1c, cache_t* L2c) info[0] = 0x0; /* reset AL */ if (0 != trials) { - VG_(message)(Vg_DebugMsg, - "warning: non-zero CPUID trials for Intel processor (%d)", - trials); + VG_DMSG("warning: non-zero CPUID trials for Intel processor (%d)", + trials); return -1; } @@ -124,8 +119,7 @@ Int Intel_cache_info(Int level, cache_t* I1c, cache_t* D1c, cache_t* L2c) case 0x22: case 0x23: case 0x25: case 0x29: case 0x46: case 0x47: case 0x4a: case 0x4b: case 0x4c: case 0x4d: - VG_(message)(Vg_DebugMsg, - "warning: L3 cache detected but ignored"); + VG_DMSG("warning: L3 cache detected but ignored"); break; /* These are sectored, whatever that means */ @@ -148,8 +142,7 @@ Int Intel_cache_info(Int level, cache_t* I1c, cache_t* D1c, cache_t* L2c) case 0x49: if ((family == 15) && (model == 6)) /* On Xeon MP (family F, model 6), this is for L3 */ - VG_(message)(Vg_DebugMsg, - "warning: L3 cache detected but ignored"); + VG_DMSG("warning: L3 cache detected but ignored"); else *L2c = (cache_t) { 4096, 16, 64 }; L2_found = True; break; @@ -200,19 +193,17 @@ Int Intel_cache_info(Int level, cache_t* I1c, cache_t* D1c, cache_t* L2c) /* Ignore prefetch information */ case 0xf0: case 0xf1: - break; + break; default: - VG_(message)(Vg_DebugMsg, - "warning: Unknown Intel cache config value " - "(0x%x), ignoring", info[i]); - break; + VG_DMSG("warning: Unknown Intel cache config value (0x%x), ignoring", + info[i]); + break; } } if (!L2_found) - VG_(message)(Vg_DebugMsg, - "warning: L2 cache not installed, ignore L2 results."); + VG_DMSG("warning: L2 cache not installed, ignore L2 results."); return 0; } @@ -251,9 +242,8 @@ Int AMD_cache_info(cache_t* I1c, cache_t* D1c, cache_t* L2c) VG_(cpuid)(0x80000000, &ext_level, &dummy, &dummy, &dummy); if (0 == (ext_level & 0x80000000) || ext_level < 0x80000006) { - VG_(message)(Vg_UserMsg, - "warning: ext_level < 0x80000006 for AMD processor (0x%x)", - ext_level); + VG_DMSG("warning: ext_level < 0x80000006 for AMD processor (0x%x)", + ext_level); return -1; } @@ -264,8 +254,7 @@ Int AMD_cache_info(cache_t* I1c, cache_t* D1c, cache_t* L2c) /* Check for Duron bug */ if (model == 0x630) { - VG_(message)(Vg_UserMsg, - "Buggy Duron stepping A0. Assuming L2 size=65536 bytes"); + VG_DMSG("warning: Buggy Duron stepping A0. Assuming L2 size=65536 bytes"); L2i = (64 << 16) | (L2i & 0xffff); } @@ -291,7 +280,7 @@ Int get_caches_from_CPUID(cache_t* I1c, cache_t* D1c, cache_t* L2c) Char vendor_id[13]; if (!VG_(has_cpuid)()) { - VG_(message)(Vg_DebugMsg, "CPUID instruction not supported"); + VG_DMSG("CPUID instruction not supported"); return -1; } @@ -300,7 +289,7 @@ Int get_caches_from_CPUID(cache_t* I1c, cache_t* D1c, cache_t* L2c) vendor_id[12] = '\0'; if (0 == level) { - VG_(message)(Vg_DebugMsg, "CPUID level is 0, early Pentium?"); + VG_DMSG("CPUID level is 0, early Pentium?"); return -1; } @@ -325,8 +314,7 @@ Int get_caches_from_CPUID(cache_t* I1c, cache_t* D1c, cache_t* L2c) ret = 0; } else { - VG_(message)(Vg_DebugMsg, "CPU vendor ID not recognised (%s)", - vendor_id); + VG_DMSG("CPU vendor ID not recognised (%s)", vendor_id); return -1; } @@ -354,9 +342,8 @@ void VG_(configure_caches)(cache_t* I1c, cache_t* D1c, cache_t* L2c, // Warn if CPUID failed and config not completely specified from cmd line. if (res != 0 && !all_caches_clo_defined) { - VG_(message)(Vg_DebugMsg, - "Warning: Couldn't auto-detect cache config, using one " - "or more defaults "); + VG_DMSG("Warning: Couldn't auto-detect cache config, using one " + "or more defaults "); } } |