Require an immediate (0.0) for compare-with-zero instructions.

This matches conventions elsewhere in the API, and allows for immediate
synthesis. Immediate synthesis is not included in this patch.

Change-Id: If4bdc9cfd9d4bb83a9c015ef363291c1ff08a64a

3 files changed, 84 insertions, 24 deletions

diff --git a/src/aarch64/assembler-aarch64.h b/src/aarch64/assembler-aarch64.h
index 929bc17a..95287d85 100644
--- a/src/aarch64/assembler-aarch64.h
+++ b/src/aarch64/assembler-aarch64.h
@@ -4093,7 +4093,8 @@ class Assembler : public vixl::internal::AssemblerBase {
   // Floating-point compare vector with zero.
   void fcmeq(const PRegisterWithLaneSize& pd,
              const PRegisterZ& pg,
-             const ZRegister& zn);
+             const ZRegister& zn,
+             double zero);
 
   // Floating-point compare vectors.
   void fcmeq(const PRegisterWithLaneSize& pd,
@@ -4104,7 +4105,8 @@ class Assembler : public vixl::internal::AssemblerBase {
   // Floating-point compare vector with zero.
   void fcmge(const PRegisterWithLaneSize& pd,
              const PRegisterZ& pg,
-             const ZRegister& zn);
+             const ZRegister& zn,
+             double zero);
 
   // Floating-point compare vectors.
   void fcmge(const PRegisterWithLaneSize& pd,
@@ -4115,7 +4117,8 @@ class Assembler : public vixl::internal::AssemblerBase {
   // Floating-point compare vector with zero.
   void fcmgt(const PRegisterWithLaneSize& pd,
              const PRegisterZ& pg,
-             const ZRegister& zn);
+             const ZRegister& zn,
+             double zero);
 
   // Floating-point compare vectors.
   void fcmgt(const PRegisterWithLaneSize& pd,
@@ -4140,17 +4143,20 @@ class Assembler : public vixl::internal::AssemblerBase {
   // Floating-point compare vector with zero.
   void fcmle(const PRegisterWithLaneSize& pd,
              const PRegisterZ& pg,
-             const ZRegister& zn);
+             const ZRegister& zn,
+             double zero);
 
   // Floating-point compare vector with zero.
   void fcmlt(const PRegisterWithLaneSize& pd,
              const PRegisterZ& pg,
-             const ZRegister& zn);
+             const ZRegister& zn,
+             double zero);
 
   // Floating-point compare vector with zero.
   void fcmne(const PRegisterWithLaneSize& pd,
              const PRegisterZ& pg,
-             const ZRegister& zn);
+             const ZRegister& zn,
+             double zero);
 
   // Floating-point compare vectors.
   void fcmne(const PRegisterWithLaneSize& pd,
diff --git a/src/aarch64/assembler-sve-aarch64.cc b/src/aarch64/assembler-sve-aarch64.cc
index de8358fe..a09691af 100644
--- a/src/aarch64/assembler-sve-aarch64.cc
+++ b/src/aarch64/assembler-sve-aarch64.cc
@@ -1165,7 +1165,8 @@ void Assembler::fcmuo(const PRegisterWithLaneSize& pd,
 
 void Assembler::fcmeq(const PRegisterWithLaneSize& pd,
                       const PRegisterZ& pg,
-                      const ZRegister& zn) {
+                      const ZRegister& zn,
+                      double zero) {
   // FCMEQ <Pd>.<T>, <Pg>/Z, <Zn>.<T>, #0.0
   //  0110 0101 ..01 0010 001. .... ...0 ....
   //  size<23:22> | eq<17> = 1 | lt<16> = 0 | Pg<12:10> | Zn<9:5> | ne<4> = 0 |
@@ -1173,13 +1174,16 @@ void Assembler::fcmeq(const PRegisterWithLaneSize& pd,
 
   VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
   VIXL_ASSERT(zn.GetLaneSizeInBytes() != kBRegSizeInBytes);
+  VIXL_ASSERT(zero == 0.0);
+  USE(zero);
 
   Emit(FCMEQ_p_p_z0 | SVESize(zn) | Pd(pd) | Rx<12, 10>(pg) | Rn(zn));
 }
 
 void Assembler::fcmge(const PRegisterWithLaneSize& pd,
                       const PRegisterZ& pg,
-                      const ZRegister& zn) {
+                      const ZRegister& zn,
+                      double zero) {
   // FCMGE <Pd>.<T>, <Pg>/Z, <Zn>.<T>, #0.0
   //  0110 0101 ..01 0000 001. .... ...0 ....
   //  size<23:22> | eq<17> = 0 | lt<16> = 0 | Pg<12:10> | Zn<9:5> | ne<4> = 0 |
@@ -1187,13 +1191,16 @@ void Assembler::fcmge(const PRegisterWithLaneSize& pd,
 
   VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
   VIXL_ASSERT(zn.GetLaneSizeInBytes() != kBRegSizeInBytes);
+  VIXL_ASSERT(zero == 0.0);
+  USE(zero);
 
   Emit(FCMGE_p_p_z0 | SVESize(zn) | Pd(pd) | Rx<12, 10>(pg) | Rn(zn));
 }
 
 void Assembler::fcmgt(const PRegisterWithLaneSize& pd,
                       const PRegisterZ& pg,
-                      const ZRegister& zn) {
+                      const ZRegister& zn,
+                      double zero) {
   // FCMGT <Pd>.<T>, <Pg>/Z, <Zn>.<T>, #0.0
   //  0110 0101 ..01 0000 001. .... ...1 ....
   //  size<23:22> | eq<17> = 0 | lt<16> = 0 | Pg<12:10> | Zn<9:5> | ne<4> = 1 |
@@ -1201,13 +1208,16 @@ void Assembler::fcmgt(const PRegisterWithLaneSize& pd,
 
   VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
   VIXL_ASSERT(zn.GetLaneSizeInBytes() != kBRegSizeInBytes);
+  VIXL_ASSERT(zero == 0.0);
+  USE(zero);
 
   Emit(FCMGT_p_p_z0 | SVESize(zn) | Pd(pd) | Rx<12, 10>(pg) | Rn(zn));
 }
 
 void Assembler::fcmle(const PRegisterWithLaneSize& pd,
                       const PRegisterZ& pg,
-                      const ZRegister& zn) {
+                      const ZRegister& zn,
+                      double zero) {
   // FCMLE <Pd>.<T>, <Pg>/Z, <Zn>.<T>, #0.0
   //  0110 0101 ..01 0001 001. .... ...1 ....
   //  size<23:22> | eq<17> = 0 | lt<16> = 1 | Pg<12:10> | Zn<9:5> | ne<4> = 1 |
@@ -1215,13 +1225,16 @@ void Assembler::fcmle(const PRegisterWithLaneSize& pd,
 
   VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
   VIXL_ASSERT(zn.GetLaneSizeInBytes() != kBRegSizeInBytes);
+  VIXL_ASSERT(zero == 0.0);
+  USE(zero);
 
   Emit(FCMLE_p_p_z0 | SVESize(zn) | Pd(pd) | Rx<12, 10>(pg) | Rn(zn));
 }
 
 void Assembler::fcmlt(const PRegisterWithLaneSize& pd,
                       const PRegisterZ& pg,
-                      const ZRegister& zn) {
+                      const ZRegister& zn,
+                      double zero) {
   // FCMLT <Pd>.<T>, <Pg>/Z, <Zn>.<T>, #0.0
   //  0110 0101 ..01 0001 001. .... ...0 ....
   //  size<23:22> | eq<17> = 0 | lt<16> = 1 | Pg<12:10> | Zn<9:5> | ne<4> = 0 |
@@ -1229,13 +1242,16 @@ void Assembler::fcmlt(const PRegisterWithLaneSize& pd,
 
   VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
   VIXL_ASSERT(zn.GetLaneSizeInBytes() != kBRegSizeInBytes);
+  VIXL_ASSERT(zero == 0.0);
+  USE(zero);
 
   Emit(FCMLT_p_p_z0 | SVESize(zn) | Pd(pd) | Rx<12, 10>(pg) | Rn(zn));
 }
 
 void Assembler::fcmne(const PRegisterWithLaneSize& pd,
                       const PRegisterZ& pg,
-                      const ZRegister& zn) {
+                      const ZRegister& zn,
+                      double zero) {
   // FCMNE <Pd>.<T>, <Pg>/Z, <Zn>.<T>, #0.0
   //  0110 0101 ..01 0011 001. .... ...0 ....
   //  size<23:22> | eq<17> = 1 | lt<16> = 1 | Pg<12:10> | Zn<9:5> | ne<4> = 0 |
@@ -1243,6 +1259,8 @@ void Assembler::fcmne(const PRegisterWithLaneSize& pd,
 
   VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
   VIXL_ASSERT(zn.GetLaneSizeInBytes() != kBRegSizeInBytes);
+  VIXL_ASSERT(zero == 0.0);
+  USE(zero);
 
   Emit(FCMNE_p_p_z0 | SVESize(zn) | Pd(pd) | Rx<12, 10>(pg) | Rn(zn));
 }
diff --git a/src/aarch64/macro-assembler-aarch64.h b/src/aarch64/macro-assembler-aarch64.h
index 06b6f484..20681ee9 100644
--- a/src/aarch64/macro-assembler-aarch64.h
+++ b/src/aarch64/macro-assembler-aarch64.h
@@ -4184,10 +4184,16 @@ class MacroAssembler : public Assembler, public MacroAssemblerInterface {
              int rot);
   void Fcmeq(const PRegisterWithLaneSize& pd,
              const PRegisterZ& pg,
-             const ZRegister& zn) {
+             const ZRegister& zn,
+             double zero) {
     VIXL_ASSERT(allow_macro_instructions_);
     SingleEmissionCheckScope guard(this);
-    fcmeq(pd, pg, zn);
+    if (zero == 0.0) {
+      fcmeq(pd, pg, zn, zero);
+    } else {
+      // TODO: Synthesise other immediates.
+      VIXL_UNIMPLEMENTED();
+    }
   }
   void Fcmeq(const PRegisterWithLaneSize& pd,
              const PRegisterZ& pg,
@@ -4199,10 +4205,16 @@ class MacroAssembler : public Assembler, public MacroAssemblerInterface {
   }
   void Fcmge(const PRegisterWithLaneSize& pd,
              const PRegisterZ& pg,
-             const ZRegister& zn) {
+             const ZRegister& zn,
+             double zero) {
     VIXL_ASSERT(allow_macro_instructions_);
     SingleEmissionCheckScope guard(this);
-    fcmge(pd, pg, zn);
+    if (zero == 0.0) {
+      fcmge(pd, pg, zn, zero);
+    } else {
+      // TODO: Synthesise other immediates.
+      VIXL_UNIMPLEMENTED();
+    }
   }
   void Fcmge(const PRegisterWithLaneSize& pd,
              const PRegisterZ& pg,
@@ -4214,10 +4226,16 @@ class MacroAssembler : public Assembler, public MacroAssemblerInterface {
   }
   void Fcmgt(const PRegisterWithLaneSize& pd,
              const PRegisterZ& pg,
-             const ZRegister& zn) {
+             const ZRegister& zn,
+             double zero) {
     VIXL_ASSERT(allow_macro_instructions_);
     SingleEmissionCheckScope guard(this);
-    fcmgt(pd, pg, zn);
+    if (zero == 0.0) {
+      fcmgt(pd, pg, zn, zero);
+    } else {
+      // TODO: Synthesise other immediates.
+      VIXL_UNIMPLEMENTED();
+    }
   }
   void Fcmgt(const PRegisterWithLaneSize& pd,
              const PRegisterZ& pg,
@@ -4247,10 +4265,16 @@ class MacroAssembler : public Assembler, public MacroAssemblerInterface {
   }
   void Fcmle(const PRegisterWithLaneSize& pd,
              const PRegisterZ& pg,
-             const ZRegister& zn) {
+             const ZRegister& zn,
+             double zero) {
     VIXL_ASSERT(allow_macro_instructions_);
     SingleEmissionCheckScope guard(this);
-    fcmle(pd, pg, zn);
+    if (zero == 0.0) {
+      fcmle(pd, pg, zn, zero);
+    } else {
+      // TODO: Synthesise other immediates.
+      VIXL_UNIMPLEMENTED();
+    }
   }
   void Fcmle(const PRegisterWithLaneSize& pd,
              const PRegisterZ& pg,
@@ -4262,10 +4286,16 @@ class MacroAssembler : public Assembler, public MacroAssemblerInterface {
   }
   void Fcmlt(const PRegisterWithLaneSize& pd,
              const PRegisterZ& pg,
-             const ZRegister& zn) {
+             const ZRegister& zn,
+             double zero) {
     VIXL_ASSERT(allow_macro_instructions_);
     SingleEmissionCheckScope guard(this);
-    fcmlt(pd, pg, zn);
+    if (zero == 0.0) {
+      fcmlt(pd, pg, zn, zero);
+    } else {
+      // TODO: Synthesise other immediates.
+      VIXL_UNIMPLEMENTED();
+    }
   }
   void Fcmlt(const PRegisterWithLaneSize& pd,
              const PRegisterZ& pg,
@@ -4277,10 +4307,16 @@ class MacroAssembler : public Assembler, public MacroAssemblerInterface {
   }
   void Fcmne(const PRegisterWithLaneSize& pd,
              const PRegisterZ& pg,
-             const ZRegister& zn) {
+             const ZRegister& zn,
+             double zero) {
     VIXL_ASSERT(allow_macro_instructions_);
     SingleEmissionCheckScope guard(this);
-    fcmne(pd, pg, zn);
+    if (zero == 0.0) {
+      fcmne(pd, pg, zn, zero);
+    } else {
+      // TODO: Synthesise other immediates.
+      VIXL_UNIMPLEMENTED();
+    }
   }
   void Fcmne(const PRegisterWithLaneSize& pd,
              const PRegisterZ& pg,