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| author | Caesar Wang <wxt@rock-chips.com> | 2015-11-06 19:38:14 +0800 |
|---|---|---|
| committer | Caesar Wang <wxt@rock-chips.com> | 2016-01-29 12:46:08 +0800 |
| commit | 40ec189879b8d1d8d68fdd4b28fa97ed2f97b2f6 (patch) | |
| tree | f5cb2a695409ea18960d4a9dc96ee6003340c0a9 | |
| parent | cd86d624c845bb02eab95b1eb327bcc2199ee524 (diff) | |
| download | v4.1-40ec189879b8d1d8d68fdd4b28fa97ed2f97b2f6.tar.gz | |
UPSTREAM: ASoC: rockchip: i2s: change bclk and lrck according to sample rates
This patch sets the dividers autonomously.
when i2s works on master mode, and sample rates changed. We need to change
bclk and lrck at the same time for cpu internal side.
As the input source clock to the module is MCLK_I2S,
and by the divider of the module, the clock generator generates
SCLK and LRCK to transmitter and receiver.
Bug: 25923642
Patchset: I2S block needed to adjust it's divider settings for these
different frequencies.
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
(cherry picked from git.kernel.org torvalds/linux.git master
commit 2458c37779ddb91b4109949d86f5a5e193ba415b)
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Change-Id: I91073f0a2252d965cd425c7240db3a024dc055ab
| -rw-r--r-- | sound/soc/rockchip/rockchip_i2s.c | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/sound/soc/rockchip/rockchip_i2s.c b/sound/soc/rockchip/rockchip_i2s.c index 0c894a814d7..e34b88e74a3 100644 --- a/sound/soc/rockchip/rockchip_i2s.c +++ b/sound/soc/rockchip/rockchip_i2s.c @@ -42,6 +42,7 @@ struct rk_i2s_dev { */ bool tx_start; bool rx_start; + bool is_master_mode; }; static int i2s_runtime_suspend(struct device *dev) @@ -186,9 +187,11 @@ static int rockchip_i2s_set_fmt(struct snd_soc_dai *cpu_dai, case SND_SOC_DAIFMT_CBS_CFS: /* Set source clock in Master mode */ val = I2S_CKR_MSS_MASTER; + i2s->is_master_mode = true; break; case SND_SOC_DAIFMT_CBM_CFM: val = I2S_CKR_MSS_SLAVE; + i2s->is_master_mode = false; break; default: return -EINVAL; @@ -239,6 +242,26 @@ static int rockchip_i2s_hw_params(struct snd_pcm_substream *substream, { struct rk_i2s_dev *i2s = to_info(dai); unsigned int val = 0; + unsigned int mclk_rate, bclk_rate, div_bclk, div_lrck; + + if (i2s->is_master_mode) { + mclk_rate = clk_get_rate(i2s->mclk); + bclk_rate = 2 * 32 * params_rate(params); + if (bclk_rate && mclk_rate % bclk_rate) + return -EINVAL; + + div_bclk = mclk_rate / bclk_rate; + div_lrck = bclk_rate / params_rate(params); + regmap_update_bits(i2s->regmap, I2S_CKR, + I2S_CKR_MDIV_MASK, + I2S_CKR_MDIV(div_bclk)); + + regmap_update_bits(i2s->regmap, I2S_CKR, + I2S_CKR_TSD_MASK | + I2S_CKR_RSD_MASK, + I2S_CKR_TSD(div_lrck) | + I2S_CKR_RSD(div_lrck)); + } switch (params_format(params)) { case SNDRV_PCM_FORMAT_S8: |