diff options
| author | zhengxing <zhengxing@rock-chips.com> | 2015-12-28 17:03:53 +0800 |
|---|---|---|
| committer | Leo Wang <leozwang@google.com> | 2016-01-27 06:11:18 +0000 |
| commit | b46d51e236dec1491ca5e2797b493021114e484f (patch) | |
| tree | 94f9db1021da65a6654ce70c82873ea9971b7906 | |
| parent | 656a5945a47f1dd80199f0e89a883cb922f5f731 (diff) | |
| download | v4.1-b46d51e236dec1491ca5e2797b493021114e484f.tar.gz | |
FROMLIST: clk: rockchip: rk3036: fix and add node id for emac clock
Due to referred old version TRM, there is incorrect emac clock node,
we should fix it. The SEL_21_9 is the parent of SEL_21_4.
In the emac driver, we need to refer HCLK_MAC, and because There are
only 3PLLs (APLL/GPLL/DPLL) on the rk3036, most clock are under the
GPLL, and it is unable to provide the accurate rate for mac_ref which
need to 50MHz probability, we should let it under the APLL and are
able to set the freq which integer multiples of 50MHz, so we add these
emac node for reference.
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Bug: 25923642
Patchset: rk3036 kylin bring up with emac.
(Note: remove the merged hclk content)
(am from https://patchwork.kernel.org/patch/7925141/)
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Change-Id: Ieae3dc5fde9162520957c163b36a95207d8bd7e9
| -rw-r--r-- | drivers/clk/rockchip/clk-rk3036.c | 7 | ||||
| -rw-r--r-- | include/dt-bindings/clock/rk3036-cru.h | 1 |
2 files changed, 6 insertions, 2 deletions
diff --git a/drivers/clk/rockchip/clk-rk3036.c b/drivers/clk/rockchip/clk-rk3036.c index 78010104e99..ecb190b7c34 100644 --- a/drivers/clk/rockchip/clk-rk3036.c +++ b/drivers/clk/rockchip/clk-rk3036.c @@ -328,8 +328,11 @@ static struct rockchip_clk_branch rk3036_clk_branches[] __initdata = { RK2928_CLKSEL_CON(16), 0, 2, MFLAGS, 2, 5, DFLAGS, RK2928_CLKGATE_CON(10), 5, GFLAGS), - COMPOSITE_NOGATE(0, "mac_pll_src", mux_pll_src_3plls_p, 0, - RK2928_CLKSEL_CON(21), 0, 2, MFLAGS, 9, 5, DFLAGS), + MUX(SCLK_MACPLL, "mac_pll_pre", mux_pll_src_3plls_p, 0, + RK2928_CLKSEL_CON(21), 0, 2, MFLAGS), + DIV(0, "mac_pll_src", "mac_pll_pre", 0, + RK2928_CLKSEL_CON(21), 9, 5, DFLAGS), + MUX(SCLK_MACREF, "mac_clk_ref", mux_mac_p, CLK_SET_RATE_PARENT, RK2928_CLKSEL_CON(21), 3, 1, MFLAGS), diff --git a/include/dt-bindings/clock/rk3036-cru.h b/include/dt-bindings/clock/rk3036-cru.h index 33965911569..e02f4c02db4 100644 --- a/include/dt-bindings/clock/rk3036-cru.h +++ b/include/dt-bindings/clock/rk3036-cru.h @@ -54,6 +54,7 @@ #define SCLK_PVTM_VIDEO 125 #define SCLK_MAC 151 #define SCLK_MACREF 152 +#define SCLK_MACPLL 153 #define SCLK_SFC 160 /* aclk gates */ |