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| author | Govindraj Raja <Govindraj.Raja@imgtec.com> | 2015-12-17 15:39:45 -0800 |
|---|---|---|
| committer | Chris Dearman <chris.dearman@imgtec.com> | 2015-12-17 15:39:45 -0800 |
| commit | 56b41d6420b3b05e332bd653fbf1681517d8d8de (patch) | |
| tree | 792c35a90407b449d37455ffe3b7dcdefe712db3 | |
| parent | 40f08c818482c54d69e04649c850cd4b6bce0e82 (diff) | |
| download | v4.1-56b41d6420b3b05e332bd653fbf1681517d8d8de.tar.gz | |
pistachio: suspend: calibrate ethernet clock in suspend.
The stmm ethernet driver supports wake-on-lan(wol).
In order to support wol we need to ensure that the
ethernet clocks are correct in the suspend path while
the sys-pll is scaled.
Testing-steps:
--------------
Target: ethtool -s eth0 wol g
Host: wakeonlan -i <ip_addr> <mac_addr>
Target: echo mem > /sys/power/state
Host: wakeonlan -i <ip_addr> <mac_addr>
Change-Id: I8a0c5d8c9c58f9a3e706b808bde9622fffa3e2b3
Signed-off-by: Govindraj Raja <Govindraj.Raja@imgtec.com>
| -rw-r--r-- | arch/mips/pistachio/suspend.S | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/arch/mips/pistachio/suspend.S b/arch/mips/pistachio/suspend.S index 3e41f67026d..22b005609a9 100644 --- a/arch/mips/pistachio/suspend.S +++ b/arch/mips/pistachio/suspend.S @@ -52,6 +52,10 @@ #define IR_DIV1_32K_DIV_VAL 0x00000057 #define IR_DIV1_DIV1_32K_SCALED_DIV_VAL 0x00000018 +#define CR_TOP_ENETPHYCLKOUT_CTRL 0xB8144230 +#define ENET_PHYCLKOUT_50M_DIV_VAL 0x00000006 +#define ENET_PHYCLKOUT_50M_SCALED_DIV_VAL 0x00000001 + .text FEXPORT(pistachio_sram_suspend) LEAF(pistachio_sram_suspend) @@ -125,6 +129,12 @@ ir_adj: PTR_LI t1, IR_DIV1_DIV1_32K_SCALED_DIV_VAL PTR_S t1, (t0) + /* to support wake-on-lan */ +enet_adj: + PTR_LI t0, CR_TOP_ENETPHYCLKOUT_CTRL + PTR_LI t1, ENET_PHYCLKOUT_50M_SCALED_DIV_VAL + PTR_S t1, (t0) + pll_lock_loop1: PTR_LI t0, CR_SYS_PLL_STATUS PTR_L t1, (t0) @@ -167,6 +177,11 @@ ir_setup: PTR_LI t1, IR_DIV1_32K_DIV_VAL PTR_S t1, (t0) +enet_setup: + PTR_LI t0, CR_TOP_ENETPHYCLKOUT_CTRL + PTR_LI t1, ENET_PHYCLKOUT_50M_DIV_VAL + PTR_S t1, (t0) + pll_lock_loop: PTR_LI t0, CR_SYS_PLL_STATUS PTR_L t1, (t0) |