diff options
Diffstat (limited to 'drivers/staging/sep54/dx_env.h')
| -rw-r--r-- | drivers/staging/sep54/dx_env.h | 230 |
1 files changed, 230 insertions, 0 deletions
diff --git a/drivers/staging/sep54/dx_env.h b/drivers/staging/sep54/dx_env.h new file mode 100644 index 00000000000..299e3c7c285 --- /dev/null +++ b/drivers/staging/sep54/dx_env.h @@ -0,0 +1,230 @@ +/******************************************************************* +* (c) Copyright 2011-2012 Discretix Technologies Ltd. * +* This software is protected by copyright, international * +* treaties and patents, and distributed under multiple licenses. * +* Any use of this Software as part of the Discretix CryptoCell or * +* Packet Engine products requires a commercial license. * +* Copies of this Software that are distributed with the Discretix * +* CryptoCell or Packet Engine product drivers, may be used in * +* accordance with a commercial license, or at the user's option, * +* used and redistributed under the terms and conditions of the GNU * +* General Public License ("GPL") version 2, as published by the * +* Free Software Foundation. * +* This program is distributed in the hope that it will be useful, * +* but WITHOUT ANY LIABILITY AND WARRANTY; without even the implied * +* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. * +* See the GNU General Public License version 2 for more details. * +* You should have received a copy of the GNU General Public * +* License version 2 along with this Software; if not, please write * +* to the Free Software Foundation, Inc., 59 Temple Place - Suite * +* 330, Boston, MA 02111-1307, USA. * +* Any copy or reproduction of this Software, as permitted under * +* the GNU General Public License version 2, must include this * +* Copyright Notice as well as any other notices provided under * +* the said license. * +********************************************************************/ +#ifndef __DX_ENV_H__ +#define __DX_ENV_H__ + +/*--------------------------------------*/ +/* BLOCK: ENV_REGS */ +/*--------------------------------------*/ +#define DX_ENV_CC_GPI_REG_OFFSET 0x18UL +#define DX_ENV_CC_GPI_VALUE_BIT_SHIFT 0x0UL +#define DX_ENV_CC_GPI_VALUE_BIT_SIZE 0x20UL +#define DX_ENV_CC_GPO_REG_OFFSET 0x1cUL +#define DX_ENV_CC_GPO_VALUE_BIT_SHIFT 0x0UL +#define DX_ENV_CC_GPO_VALUE_BIT_SIZE 0x20UL +#define DX_ENV_PKA_DEBUG_MODE_REG_OFFSET 0x24UL +#define DX_ENV_PKA_DEBUG_MODE_VALUE_BIT_SHIFT 0x0UL +#define DX_ENV_PKA_DEBUG_MODE_VALUE_BIT_SIZE 0x1UL +#define DX_ENV_SCAN_MODE_REG_OFFSET 0x30UL +#define DX_ENV_SCAN_MODE_VALUE_BIT_SHIFT 0x0UL +#define DX_ENV_SCAN_MODE_VALUE_BIT_SIZE 0x1UL +#define DX_ENV_CC_ALLOW_SCAN_REG_OFFSET 0x34UL +#define DX_ENV_CC_ALLOW_SCAN_VALUE_BIT_SHIFT 0x0UL +#define DX_ENV_CC_ALLOW_SCAN_VALUE_BIT_SIZE 0x1UL +#define DX_ENV_HOST_CC_EXT_INT_REG_OFFSET 0x38UL +#define DX_ENV_HOST_CC_EXT_INT_VALUE_BIT_SHIFT 0x0UL +#define DX_ENV_HOST_CC_EXT_INT_VALUE_BIT_SIZE 0x1UL +#define DX_ENV_CC_SW_MONITOR_ADDR_REG_OFFSET 0x60UL +#define DX_ENV_CC_SW_MONITOR_ADDR_VALUE_BIT_SHIFT 0x0UL +#define DX_ENV_CC_SW_MONITOR_ADDR_VALUE_BIT_SIZE 0x20UL +#define DX_ENV_CC_HOST_INT_REG_OFFSET 0x0A0UL +#define DX_ENV_CC_HOST_INT_VALUE_BIT_SHIFT 0x0UL +#define DX_ENV_CC_HOST_INT_VALUE_BIT_SIZE 0x1UL +#define DX_ENV_CC_RST_N_REG_OFFSET 0x0A8UL +#define DX_ENV_CC_RST_N_VALUE_BIT_SHIFT 0x0UL +#define DX_ENV_CC_RST_N_VALUE_BIT_SIZE 0x1UL +#define DX_ENV_RST_OVERRIDE_REG_OFFSET 0x0ACUL +#define DX_ENV_RST_OVERRIDE_VALUE_BIT_SHIFT 0x0UL +#define DX_ENV_RST_OVERRIDE_VALUE_BIT_SIZE 0x1UL +#define DX_ENV_CC_HOST_EXT_ACK_REG_OFFSET 0x0B0UL +#define DX_ENV_CC_HOST_EXT_ACK_VALUE_BIT_SHIFT 0x0UL +#define DX_ENV_CC_HOST_EXT_ACK_VALUE_BIT_SIZE 0x1UL +#define DX_ENV_CC_POR_N_ADDR_REG_OFFSET 0x0E0UL +#define DX_ENV_CC_POR_N_ADDR_VALUE_BIT_SHIFT 0x0UL +#define DX_ENV_CC_POR_N_ADDR_VALUE_BIT_SIZE 0x1UL +#define DX_ENV_CC_WARM_BOOT_REG_OFFSET 0x0E4UL +#define DX_ENV_CC_WARM_BOOT_VALUE_BIT_SHIFT 0x0UL +#define DX_ENV_CC_WARM_BOOT_VALUE_BIT_SIZE 0x1UL +#define DX_ENV_CC_COLD_BOOT_REG_OFFSET 0x0E8UL +#define DX_ENV_CC_COLD_BOOT_CC_COLD_BOOT_FULL_BIT_SHIFT 0x0UL +#define DX_ENV_CC_COLD_BOOT_CC_COLD_BOOT_FULL_BIT_SIZE 0x1UL +#define DX_ENV_CC_COLD_BOOT_CC_COLD_BOOT_SEMI_BIT_SHIFT 0x1UL +#define DX_ENV_CC_COLD_BOOT_CC_COLD_BOOT_SEMI_BIT_SIZE 0x1UL +#define DX_ENV_CC_BM_LOWER_BOUND_ADDR_REG_OFFSET 0x0F0UL +#define DX_ENV_CC_BM_LOWER_BOUND_ADDR_VALUE_BIT_SHIFT 0x0UL +#define DX_ENV_CC_BM_LOWER_BOUND_ADDR_VALUE_BIT_SIZE 0x14UL +#define DX_ENV_CC_BM_UPPER_BOUND_ADDR_REG_OFFSET 0x0F4UL +#define DX_ENV_CC_BM_UPPER_BOUND_ADDR_VALUE_BIT_SHIFT 0x0UL +#define DX_ENV_CC_BM_UPPER_BOUND_ADDR_VALUE_BIT_SIZE 0x14UL +#define DX_ENV_CC_BM_ENB_ADDR_REG_OFFSET 0x0F8UL +#define DX_ENV_CC_BM_ENB_ADDR_VALUE_BIT_SHIFT 0x0UL +#define DX_ENV_CC_BM_ENB_ADDR_VALUE_BIT_SIZE 0x1UL +#define DX_ENV_CC_COLD_RST_REG_OFFSET 0x0FCUL +#define DX_ENV_CC_COLD_RST_VALUE_BIT_SHIFT 0x0UL +#define DX_ENV_CC_COLD_RST_VALUE_BIT_SIZE 0x1UL +#define DX_ENV_CC_BM_ERR_ACK_ADDR_REG_OFFSET 0x100UL +#define DX_ENV_CC_BM_ERR_ACK_ADDR_VALUE_BIT_SHIFT 0x0UL +#define DX_ENV_CC_BM_ERR_ACK_ADDR_VALUE_BIT_SIZE 0x1UL +#define DX_ENV_BM_CC_ERR_ADDR_REG_OFFSET 0x104UL +#define DX_ENV_BM_CC_ERR_ADDR_VALUE_BIT_SHIFT 0x0UL +#define DX_ENV_BM_CC_ERR_ADDR_VALUE_BIT_SIZE 0x1UL +#define DX_ENV_DUMMY_ADDR_REG_OFFSET 0x108UL +#define DX_ENV_DUMMY_ADDR_VALUE_BIT_SHIFT 0x0UL +#define DX_ENV_DUMMY_ADDR_VALUE_BIT_SIZE 0x20UL +#define DX_ENV_CLK_STATUS_REG_OFFSET 0x10CUL +#define DX_ENV_CLK_STATUS_AES_CLK_STATUS_BIT_SHIFT 0x0UL +#define DX_ENV_CLK_STATUS_AES_CLK_STATUS_BIT_SIZE 0x1UL +#define DX_ENV_CLK_STATUS_DES_CLK_STATUS_BIT_SHIFT 0x1UL +#define DX_ENV_CLK_STATUS_DES_CLK_STATUS_BIT_SIZE 0x1UL +#define DX_ENV_CLK_STATUS_HASH_CLK_STATUS_BIT_SHIFT 0x2UL +#define DX_ENV_CLK_STATUS_HASH_CLK_STATUS_BIT_SIZE 0x1UL +#define DX_ENV_CLK_STATUS_PKA_CLK_STATUS_BIT_SHIFT 0x3UL +#define DX_ENV_CLK_STATUS_PKA_CLK_STATUS_BIT_SIZE 0x1UL +#define DX_ENV_CLK_STATUS_RC4_CLK_STATUS_BIT_SHIFT 0x4UL +#define DX_ENV_CLK_STATUS_RC4_CLK_STATUS_BIT_SIZE 0x1UL +#define DX_ENV_CLK_STATUS_AHB_CLK_STATUS_BIT_SHIFT 0x5UL +#define DX_ENV_CLK_STATUS_AHB_CLK_STATUS_BIT_SIZE 0x1UL +#define DX_ENV_CLK_STATUS_RNG_CLK_STATUS_BIT_SHIFT 0x6UL +#define DX_ENV_CLK_STATUS_RNG_CLK_STATUS_BIT_SIZE 0x1UL +#define DX_ENV_CLK_STATUS_C2_CLK_STATUS_BIT_SHIFT 0x7UL +#define DX_ENV_CLK_STATUS_C2_CLK_STATUS_BIT_SIZE 0x1UL +#define DX_ENV_CLK_STATUS_SEP_CLK_STATUS_BIT_SHIFT 0x8UL +#define DX_ENV_CLK_STATUS_SEP_CLK_STATUS_BIT_SIZE 0x1UL +#define DX_ENV_CLK_STATUS_COMM_CLK_STATUS_BIT_SHIFT 0x9UL +#define DX_ENV_CLK_STATUS_COMM_CLK_STATUS_BIT_SIZE 0x1UL +#define DX_ENV_COUNTER_CLR_REG_OFFSET 0x118UL +#define DX_ENV_COUNTER_CLR_VALUE_BIT_SHIFT 0x0UL +#define DX_ENV_COUNTER_CLR_VALUE_BIT_SIZE 0x1UL +#define DX_ENV_COUNTER_RD_REG_OFFSET 0x11CUL +#define DX_ENV_COUNTER_RD_VALUE_BIT_SHIFT 0x0UL +#define DX_ENV_COUNTER_RD_VALUE_BIT_SIZE 0x20UL +#define DX_ENV_CC_SECOND_BM_LOWER_BOUND_ADDR_REG_OFFSET 0x120UL +#define DX_ENV_CC_SECOND_BM_LOWER_BOUND_ADDR_VALUE_BIT_SHIFT 0x0UL +#define DX_ENV_CC_SECOND_BM_LOWER_BOUND_ADDR_VALUE_BIT_SIZE 0x14UL +#define DX_ENV_CC_SECOND_BM_UPPER_BOUND_ADDR_REG_OFFSET 0x124UL +#define DX_ENV_CC_SECOND_BM_UPPER_BOUND_ADDR_VALUE_BIT_SHIFT 0x0UL +#define DX_ENV_CC_SECOND_BM_UPPER_BOUND_ADDR_VALUE_BIT_SIZE 0x14UL +#define DX_ENV_CC_SECOND_BM_ENB_ADDR_REG_OFFSET 0x128UL +#define DX_ENV_CC_SECOND_BM_ENB_ADDR_VALUE_BIT_SHIFT 0x0UL +#define DX_ENV_CC_SECOND_BM_ENB_ADDR_VALUE_BIT_SIZE 0x1UL +#define DX_ENV_CC_SECOND_BM_ERR_ACK_ADDR_REG_OFFSET 0x12CUL +#define DX_ENV_CC_SECOND_BM_ERR_ACK_ADDR_VALUE_BIT_SHIFT 0x0UL +#define DX_ENV_CC_SECOND_BM_ERR_ACK_ADDR_VALUE_BIT_SIZE 0x1UL +#define DX_ENV_SECOND_BM_CC_ERR_ADDR_REG_OFFSET 0x130UL +#define DX_ENV_SECOND_BM_CC_ERR_ADDR_VALUE_BIT_SHIFT 0x0UL +#define DX_ENV_SECOND_BM_CC_ERR_ADDR_VALUE_BIT_SIZE 0x1UL +#define DX_ENV_RNG_DEBUG_ENABLE_REG_OFFSET 0x430UL +#define DX_ENV_RNG_DEBUG_ENABLE_VALUE_BIT_SHIFT 0x0UL +#define DX_ENV_RNG_DEBUG_ENABLE_VALUE_BIT_SIZE 0x1UL +#define DX_ENV_CC_WARM_BOOT_FINISHED_REG_OFFSET 0x434UL +#define DX_ENV_CC_WARM_BOOT_FINISHED_VALUE_BIT_SHIFT 0x0UL +#define DX_ENV_CC_WARM_BOOT_FINISHED_VALUE_BIT_SIZE 0x1UL +#define DX_ENV_CC_LCS_REG_OFFSET 0x43CUL +#define DX_ENV_CC_LCS_VALUE_BIT_SHIFT 0x0UL +#define DX_ENV_CC_LCS_VALUE_BIT_SIZE 0x8UL +#define DX_ENV_CC_IS_CM_DM_SECURE_RMA_REG_OFFSET 0x440UL +#define DX_ENV_CC_IS_CM_DM_SECURE_RMA_IS_CM_BIT_SHIFT 0x0UL +#define DX_ENV_CC_IS_CM_DM_SECURE_RMA_IS_CM_BIT_SIZE 0x1UL +#define DX_ENV_CC_IS_CM_DM_SECURE_RMA_IS_DM_BIT_SHIFT 0x1UL +#define DX_ENV_CC_IS_CM_DM_SECURE_RMA_IS_DM_BIT_SIZE 0x1UL +#define DX_ENV_CC_IS_CM_DM_SECURE_RMA_IS_SECURE_BIT_SHIFT 0x2UL +#define DX_ENV_CC_IS_CM_DM_SECURE_RMA_IS_SECURE_BIT_SIZE 0x1UL +#define DX_ENV_CC_IS_CM_DM_SECURE_RMA_IS_RMA_BIT_SHIFT 0x3UL +#define DX_ENV_CC_IS_CM_DM_SECURE_RMA_IS_RMA_BIT_SIZE 0x1UL +#define DX_ENV_DCU_EN_REG_OFFSET 0x444UL +#define DX_ENV_DCU_EN_VALUE_BIT_SHIFT 0x0UL +#define DX_ENV_DCU_EN_VALUE_BIT_SIZE 0x20UL +#define DX_ENV_CC_LCS_IS_VALID_REG_OFFSET 0x448UL +#define DX_ENV_CC_LCS_IS_VALID_VALUE_BIT_SHIFT 0x0UL +#define DX_ENV_CC_LCS_IS_VALID_VALUE_BIT_SIZE 0x1UL +#define DX_ENV_CRYPTOKEY_0_REG_OFFSET 0x450UL +#define DX_ENV_CRYPTOKEY_0_VALUE_BIT_SHIFT 0x0UL +#define DX_ENV_CRYPTOKEY_0_VALUE_BIT_SIZE 0x20UL +#define DX_ENV_CRYPTOKEY_1_REG_OFFSET 0x454UL +#define DX_ENV_CRYPTOKEY_1_VALUE_BIT_SHIFT 0x0UL +#define DX_ENV_CRYPTOKEY_1_VALUE_BIT_SIZE 0x20UL +#define DX_ENV_CRYPTOKEY_2_REG_OFFSET 0x458UL +#define DX_ENV_CRYPTOKEY_2_VALUE_BIT_SHIFT 0x0UL +#define DX_ENV_CRYPTOKEY_2_VALUE_BIT_SIZE 0x20UL +#define DX_ENV_CRYPTOKEY_3_REG_OFFSET 0x45CUL +#define DX_ENV_CRYPTOKEY_3_VALUE_BIT_SHIFT 0x0UL +#define DX_ENV_CRYPTOKEY_3_VALUE_BIT_SIZE 0x20UL +#define DX_ENV_CRYPTOKEY_4_REG_OFFSET 0x460UL +#define DX_ENV_CRYPTOKEY_4_VALUE_BIT_SHIFT 0x0UL +#define DX_ENV_CRYPTOKEY_4_VALUE_BIT_SIZE 0x20UL +#define DX_ENV_CRYPTOKEY_5_REG_OFFSET 0x464UL +#define DX_ENV_CRYPTOKEY_5_VALUE_BIT_SHIFT 0x0UL +#define DX_ENV_CRYPTOKEY_5_VALUE_BIT_SIZE 0x20UL +#define DX_ENV_CRYPTOKEY_6_REG_OFFSET 0x468UL +#define DX_ENV_CRYPTOKEY_6_VALUE_BIT_SHIFT 0x0UL +#define DX_ENV_CRYPTOKEY_6_VALUE_BIT_SIZE 0x20UL +#define DX_ENV_CRYPTOKEY_7_REG_OFFSET 0x46CUL +#define DX_ENV_CRYPTOKEY_7_VALUE_BIT_SHIFT 0x0UL +#define DX_ENV_CRYPTOKEY_7_VALUE_BIT_SIZE 0x20UL +#define DX_ENV_POWER_DOWN_REG_OFFSET 0x478UL +#define DX_ENV_POWER_DOWN_VALUE_BIT_SHIFT 0x0UL +#define DX_ENV_POWER_DOWN_VALUE_BIT_SIZE 0x20UL +#define DX_ENV_POWER_DOWN_EN_REG_OFFSET 0x47CUL +#define DX_ENV_POWER_DOWN_EN_VALUE_BIT_SHIFT 0x0UL +#define DX_ENV_POWER_DOWN_EN_VALUE_BIT_SIZE 0x1UL +#define DX_ENV_OTF_SECURE_BOOT_DONE_REG_OFFSET 0x480UL +#define DX_ENV_OTF_SECURE_BOOT_DONE_VALUE_BIT_SHIFT 0x0UL +#define DX_ENV_OTF_SECURE_BOOT_DONE_VALUE_BIT_SIZE 0x1UL +#define DX_ENV_DCU_H_EN_REG_OFFSET 0x484UL +#define DX_ENV_DCU_H_EN_VALUE_BIT_SHIFT 0x0UL +#define DX_ENV_DCU_H_EN_VALUE_BIT_SIZE 0x20UL +#define DX_ENV_VERSION_REG_OFFSET 0x488UL +#define DX_ENV_VERSION_VALUE_BIT_SHIFT 0x0UL +#define DX_ENV_VERSION_VALUE_BIT_SIZE 0x20UL +#define DX_ENV_FUSE_AIB_1K_OFFSET_REG_OFFSET 0x48CUL +#define DX_ENV_FUSE_AIB_1K_OFFSET_VALUE_BIT_SHIFT 0x0UL +#define DX_ENV_FUSE_AIB_1K_OFFSET_VALUE_BIT_SIZE 0x2UL +/* --------------------------------------*/ +/* BLOCK: ENV_CC_MEMORIES */ +/* --------------------------------------*/ +#define DX_ENV_FUSE_READY_REG_OFFSET 0x414UL +#define DX_ENV_FUSE_READY_VALUE_BIT_SHIFT 0x0UL +#define DX_ENV_FUSE_READY_VALUE_BIT_SIZE 0x1UL +#define DX_ENV_ROM_BANK_REG_OFFSET 0x420UL +#define DX_ENV_ROM_BANK_VALUE_BIT_SHIFT 0x0UL +#define DX_ENV_ROM_BANK_VALUE_BIT_SIZE 0x2UL +#define DX_ENV_PERF_RAM_MASTER_REG_OFFSET 0x500UL +#define DX_ENV_PERF_RAM_MASTER_VALUE_BIT_SHIFT 0x0UL +#define DX_ENV_PERF_RAM_MASTER_VALUE_BIT_SIZE 0x1UL +#define DX_ENV_PERF_RAM_ADDR_HIGH4_REG_OFFSET 0x504UL +#define DX_ENV_PERF_RAM_ADDR_HIGH4_VALUE_BIT_SHIFT 0x0UL +#define DX_ENV_PERF_RAM_ADDR_HIGH4_VALUE_BIT_SIZE 0x2UL +#define DX_ENV_FUSES_RAM_REG_OFFSET 0x800UL +#define DX_ENV_FUSES_RAM_VALUE_BIT_SHIFT 0x0UL +#define DX_ENV_FUSES_RAM_VALUE_BIT_SIZE 0x20UL +/* --------------------------------------*/ +/* BLOCK: ENV_PERF_RAM_BASE */ +/* --------------------------------------*/ +#define DX_ENV_PERF_RAM_BASE_REG_OFFSET 0x0UL +#define DX_ENV_PERF_RAM_BASE_VALUE_BIT_SHIFT 0x0UL +#define DX_ENV_PERF_RAM_BASE_VALUE_BIT_SIZE 0x20UL + +#endif /*__DX_ENV_H__*/ |