apq8016: db410c: dt: enable spi on low speed expansion pins

BUG=25474162

Change-Id: I5f9226b548bdc08f701ed7a8acfe1349a5901889
Signed-off-by: Sourabh Banerjee <sbanerje@codeaurora.org>

3 files changed, 40 insertions, 73 deletions

diff --git a/arch/arm/boot/dts/qcom/apq8016-sbc.dtsi b/arch/arm/boot/dts/qcom/apq8016-sbc.dtsi
index 8202585b8c3..75a1ad08225 100644
--- a/arch/arm/boot/dts/qcom/apq8016-sbc.dtsi
+++ b/arch/arm/boot/dts/qcom/apq8016-sbc.dtsi
@@ -74,9 +74,9 @@
 		};
 	};
 
-    spi_0 { /* BLSP1 QUP3 */
-		status = "disabled";
-    };
+	spi_0 { /* SPI High Speed expansion */
+		status = "ok";
+	};
 
 	i2c@78b8000 { /* BLSP1 QUP4 */
 		/* DSI_TO_HDMI I2C configuration */
@@ -96,31 +96,8 @@
 		};
 	};
 
-	i2c@78b9000 { /* BLSP1 QUP5 */
-		synaptics@20 {
-			compatible = "synaptics,rmi4";
-			reg = <0x20>;
-			interrupt-parent = <&msm_gpio>;
-			interrupts = <13 0x2008>;
-			vdd-supply = <&vph_pwr_vreg>;
-			vcc_i2c-supply = <&vph_pwr_vreg>;
-			/* pins used by touchscreen */
-			pinctrl-names = "pmx_ts_active","pmx_ts_suspend","pmx_ts_suspend";
-			pinctrl-0 = <&ts_int_active &ts_reset_active>;
-			pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>;
-			pinctrl-2 = <&ts_release>;
-			synaptics,display-coords = <0 0 1079 1919>;
-			synaptics,panel-coords = <0 0 1079 2084>;
-			synaptics,irq-gpio = <&msm_gpio 13 0x2008>;
-			synaptics,reset-gpio = <&msm_gpio 12 0x0>;
-			synaptics,i2c-pull-up;
-			synaptics,power-down;
-			synaptics,disable-gpios;
-			/* Underlying clocks used by secure touch */
-			clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>,
-			 <&clock_gcc clk_gcc_blsp1_qup5_i2c_apps_clk>;
-			clock-names = "iface_clk", "core_clk";
-		};
+	spi_1 { /* SPI Low Speed Expansion */
+		status = "ok";
 	};
 
 	i2c@78ba000 { /* BLSP1 QUP6 */
diff --git a/arch/arm/boot/dts/qcom/msm8916.dtsi b/arch/arm/boot/dts/qcom/msm8916.dtsi
index fe798da031e..86d83100006 100644
--- a/arch/arm/boot/dts/qcom/msm8916.dtsi
+++ b/arch/arm/boot/dts/qcom/msm8916.dtsi
@@ -46,9 +46,9 @@
 		smd36 = &smdtty_loopback;
 
 		spi0 = &spi_0; /* SPI0 controller device */
+		spi1 = &spi_1; /* SPI0 controller device */
 		i2c0 = &i2c_0; /* I2C0 controller device */
-		i2c5 = &i2c_5; /* I2C5 controller device */
-		i2c6 = &i2c_6; /* I2C6 NFC qup6 device */
+		i2c6 = &i2c_6; /* I2C6 controller device */
 		i2c4 = &i2c_4; /* I2C4 controller device */
 	};
 
@@ -1396,28 +1396,42 @@
                 qcom,bam-consumer-pipe-index = <8>;
                 qcom,bam-producer-pipe-index = <9>;
                 qcom,master-id = <86>;
+                spidev@0 {
+                        compatible = "spidev";
+                        reg = <0>;
+                        spi-max-frequency = <50000000>;
+                };
+        };
 
-		lattice,spi-usb@0 {
-			compatible = "lattice,ice40-spi-usb";
+	spi_1: spi@78b9000 { /* BLSP1 QUP5 */
+		compatible = "qcom,spi-qup-v2";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg-names = "spi_physical", "spi_bam_physical";
+		reg = <0x78b9000 0x600>,
+		      <0x7884000 0x23000>;
+		interrupt-names = "spi_irq", "spi_bam_irq";
+                interrupts = <0 99 0>, <0 238 0>;
+                spi-max-frequency = <50000000>;
+                pinctrl-names = "spi_default", "spi_sleep";
+                pinctrl-0 = <&spi2_default &spi2_cs2_active>;
+                pinctrl-1 = <&spi2_sleep &spi2_cs2_sleep>;
+                clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>,
+                         <&clock_gcc clk_gcc_blsp1_qup5_spi_apps_clk>;
+                clock-names = "iface_clk", "core_clk";
+                qcom,infinite-mode = <0>;
+                qcom,use-bam;
+                qcom,use-pinctrl;
+                qcom,ver-reg-exists;
+                qcom,bam-consumer-pipe-index = <12>;
+                qcom,bam-producer-pipe-index = <13>;
+                qcom,master-id = <86>;
+		spidev@0 {
+			compatible = "spidev";
 			reg = <0>;
 			spi-max-frequency = <50000000>;
-			spi-cpol = <1>;
-			spi-cpha = <1>;
-			core-vcc-supply = <&pm8916_l2>;
-			spi-vcc-supply = <&pm8916_l5>;
-			qcom,pm-qos-latency = <2>;
-			lattice,reset-gpio = <&msm_gpio 3 0>;
-			lattice,config-done-gpio = <&msm_gpio 1 0>;
-			lattice,vcc-en-gpio = <&msm_gpio 114 0>;
-			lattice,clk-en-gpio = <&msm_gpio 0 0>;
-
-			clocks = <&clock_rpm clk_bb_clk2_pin>;
-			clock-names = "xo";
-			pinctrl-names = "default", "sleep";
-			pinctrl-0 = <&ice40_default>;
-			pinctrl-1 = <&ice40_sleep>;
 		};
-        };
+	};
 
 	dma_blsp1: qcom,sps-dma@7884000 { /* BLSP1 */
 		#dma-cells = <4>;
@@ -1451,30 +1465,6 @@
 		qcom,master-id = <86>;
 	};
 
-	i2c_5: i2c@78b9000 { /* BLSP1 QUP5 */
-		compatible = "qcom,i2c-msm-v2";
-		#address-cells = <1>;
-		#size-cells = <0>;
-		reg-names = "qup_phys_addr";
-		reg = <0x78b9000 0x600>;
-		interrupt-names = "qup_irq";
-		interrupts = <0 99 0>;
-		clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>,
-			 <&clock_gcc clk_gcc_blsp1_qup5_i2c_apps_clk>;
-		clock-names = "iface_clk", "core_clk";
-		qcom,clk-freq-out = <100000>;
-		qcom,clk-freq-in  = <19200000>;
-		pinctrl-names = "i2c_active", "i2c_sleep";
-		pinctrl-0 = <&i2c_5_active>;
-		pinctrl-1 = <&i2c_5_sleep>;
-		qcom,noise-rjct-scl = <0>;
-		qcom,noise-rjct-sda = <0>;
-		dmas = <&dma_blsp1 12 64 0x20000020 0x20>,
-			<&dma_blsp1 13 32 0x20000020 0x20>;
-		dma-names = "tx", "rx";
-		qcom,master-id = <86>;
-	};
-
 	i2c_6: i2c@78ba000 { /* BLSP1 QUP6 */
 		compatible = "qcom,i2c-msm-v2";
 		#address-cells=<1>;
diff --git a/arch/arm/configs/msm8916-perf_defconfig b/arch/arm/configs/msm8916-perf_defconfig
index 3d5706a6c2d..71c1e4e7e8f 100644
--- a/arch/arm/configs/msm8916-perf_defconfig
+++ b/arch/arm/configs/msm8916-perf_defconfig
@@ -306,7 +306,7 @@ CONFIG_HAS_DMA=y
 CONFIG_QCOM_SPS_DMA=y
 CONFIG_SPI=y
 CONFIG_SPI_QUP=y
-CONFIG_SPI_SPIDEV=m
+CONFIG_SPI_SPIDEV=y
 CONFIG_SPMI=y
 CONFIG_SPMI_MSM_PMIC_ARB=y
 CONFIG_MSM_QPNP_INT=y