ARM: dts: msm: Add support for new PVS tables for MSM8939

Add new speed bin tables based on the speedbin and
version for MSM8939.

CRs-Fixed: 780871
Change-Id: If0ea2a96ae9af1bf6b8897bb42701ecbee5eed9d
Signed-off-by: Hanumath Prasad <hpprasad@codeaurora.org>
Signed-off-by: Sridhar Gujje <sgujje@codeaurora.org>

3 files changed, 144 insertions, 14 deletions

diff --git a/Documentation/devicetree/bindings/arm/msm/clock-cpu-8939.txt b/Documentation/devicetree/bindings/arm/msm/clock-cpu-8939.txt
new file mode 100644
index 00000000000..a3ec2385eba
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/msm/clock-cpu-8939.txt
@@ -0,0 +1,73 @@
+Qualcomm MSM8939 CPU clock tree
+
+clock-cpu-8939 is a device that represents the MSM8939 or MSM8952 CPU
+subsystem clock tree. It lists the various power supplies that need to be
+scaled when the clocks are scaled and also other HW specific parameters like
+fmax tables, avs settings table, etc.
+
+Required properties:
+- compatible:		Must be one of "qcom,clock-cpu-8939" or
+			"qcom,cpu-clock-8952"
+- reg:			Pairs of physical base addresses and region sizes of
+			memory mapped registers.
+- reg-names:		Names of the bases for the above registers. Expected
+			bases are:
+			"apcs-c0-rcg-base", "apcs-c1-rcg-base",
+			"apcs-cci-rcg-base", "efuse", "efuse1", "efuse2"
+- vdd-c0-supply:	The regulator powering the little cluster
+- vdd-c1-supply:	The regulator powering the big cluster
+- vdd-cci-supply:	The regulator powering the CCI cluster
+- qcom,speedX-bin-vY-ZZZ:
+			A table of CPU frequency (Hz) to voltage (corner)
+			mapping that represents the max frequency possible
+			for each supported voltage level for a CPU. 'X' is
+			the speed bin into which the device falls into - a
+			bin will have unique frequency-voltage relationships.
+			'Y' is the characterization version, implying that
+			characterization (deciding what speed bin a device
+			falls into) methods and/or encoding may change. The
+			values 'X' and 'Y' are read from efuse registers, and
+			the right table is picked from multiple possible tables.
+			'ZZZ' can be c1, c0 or cci depending on whether the table
+			is for the big cluster, little cluster or cci.
+Example:
+	clock_cpu: qcom,cpu-clock-8939@f9015000 {
+		compatible = "qcom,cpu-clock-8939";
+		reg = <0xf9015000 0x1000>,
+		      <0xf9016000 0x1000>,
+		      <0xf9011000 0x1000>,
+		      <0xf900d000 0x1000>,
+		      <0xf900f000 0x1000>,
+		      <0xf9112000 0x1000>;
+		reg-names = "apcs-c0-rcg-base", "apcs-c1-rcg-base",
+			     "apcs-cci-rcg-base", "efuse", "efuse1",
+				"efuse2";
+                vdd-c0-supply = <&apc_vreg_corner>;
+		vdd-c1-supply = <&apc_vreg_corner>;
+		vdd-cci-supply = <&apc_vreg_corner>;
+		qcom,speed0-bin-v0-c0 =
+			<         0 0>,
+			< 384000000 1>,
+			< 787200000 2>,
+			<1286400000 3>;
+		qcom,speed0-bin-v0-c1 =
+			<         0 0>,
+			< 384000000 1>,
+			< 787200000 2>,
+			<1785600000 3>;
+		qcom,speed0-bin-v0-cci =
+			<         0 0>,
+			< 150000000 1>,
+			< 300000000 2>,
+			< 600000000 3>;
+		clocks = <&clock_gcc clk_gpll0_ao>,
+			<&clock_gcc clk_a53ss_c0_pll>,
+			<&clock_gcc clk_gpll0_ao>,
+			<&clock_gcc clk_a53ss_c1_pll>,
+			<&clock_gcc clk_gpll0_ao>,
+			<&clock_gcc clk_a53ss_cci_pll>;
+			clock-names = "clk-c0-4", "clk-c0-5",
+			"clk-c1-4", "clk-c1-5",
+			"clk-cci-4", "clk-cci-5";
+		#clock-cells = <1>;
+};
diff --git a/arch/arm/boot/dts/qcom/msm8939.dtsi b/arch/arm/boot/dts/qcom/msm8939.dtsi
index 4d327e49194..4a4ac72d212 100644
--- a/arch/arm/boot/dts/qcom/msm8939.dtsi
+++ b/arch/arm/boot/dts/qcom/msm8939.dtsi
@@ -46,9 +46,12 @@
 		reg = <0x0b111050 0x8>,
 			<0xb011050 0x8>,
 			<0xb1d1050 0x8>,
-			<0x5800c 0X8>;
+			<0x5800c 0x8>,
+			<0x58000 0x8>,
+			<0x58004 0x8>;
 		reg-names = "apcs-c0-rcg-base", "apcs-c1-rcg-base",
-				"apcs-cci-rcg-base", "efuse";
+				"apcs-cci-rcg-base", "efuse", "efuse1",
+				"efuse2";
 		vdd-c0-supply = <&apc_vreg_corner>;
 		vdd-c1-supply = <&apc_vreg_corner>;
 		vdd-cci-supply = <&apc_vreg_corner>;
@@ -67,7 +70,7 @@
 			<  500000000 9>,
 			<  800000000 12>,
 			<  998400000 17>,
-			< 1113600000 22>;
+			< 1113600000 24>;
 
 		qcom,speed0-bin-v0-c1 =
 			<          0 0>,
@@ -90,7 +93,7 @@
 			<  500000000 9>,
 			<  800000000 12>,
 			<  998400000 17>,
-			< 1113600000 22>;
+			< 1113600000 24>;
 
 		qcom,speed2-bin-v0-c1 =
 			<          0 0>,
@@ -99,7 +102,8 @@
 			<  960000000 12>,
 			< 1113600000 14>,
 			< 1344000000 17>,
-			< 1497600000 19>;
+			< 1459200000 20>,
+			< 1497600000 21>;
 
 		qcom,speed2-bin-v0-cci =
 			<          0 0>,
@@ -108,13 +112,37 @@
 			<  400000000 15>,
 			<  600000000 17>;
 
+		qcom,speed2-bin-v2-c0 =
+			<          0 0>,
+			<  250000000 3>,
+			<  500000000 9>,
+			<  800000000 12>,
+			<  998400000 17>,
+			< 1113600000 24>;
+
+		qcom,speed2-bin-v2-c1 =
+			<          0 0>,
+			<  400000000 3>,
+			<  800000000 9>,
+			<  960000000 12>,
+			< 1113600000 14>,
+			< 1344000000 17>,
+			< 1459200000 20>;
+
+		qcom,speed2-bin-v2-cci =
+			<          0 0>,
+			<  200000000 3>,
+			<  300000000 11>,
+			<  400000000 15>,
+			<  600000000 17>;
+
 		qcom,speed4-bin-v0-c0 =
 			<          0 0>,
 			<  250000000 3>,
 			<  500000000 9>,
 			<  800000000 12>,
 			<  998400000 17>,
-			< 1113600000 22>;
+			< 1113600000 24>;
 
 		qcom,speed4-bin-v0-c1 =
 			<          0 0>,
@@ -123,8 +151,9 @@
 			<  960000000 12>,
 			< 1113600000 14>,
 			< 1344000000 17>,
-			< 1497600000 19>,
-			< 1651200000 24>;
+			< 1459200000 20>,
+			< 1497600000 21>,
+			< 1651200000 26>;
 
 		qcom,speed4-bin-v0-cci =
 			<          0 0>,
@@ -139,7 +168,7 @@
 			<  500000000 9>,
 			<  800000000 12>,
 			<  998400000 17>,
-			< 1113600000 22>;
+			< 1113600000 24>;
 
 		qcom,speed5-bin-v0-c1 =
 			<          0 0>,
@@ -148,8 +177,9 @@
 			<  960000000 12>,
 			< 1113600000 14>,
 			< 1344000000 17>,
-			< 1497600000 19>,
-			< 1651200000 24>;
+			< 1459200000 20>,
+			< 1497600000 21>,
+			< 1651200000 26>;
 
 		qcom,speed5-bin-v0-cci =
 			<          0 0>,
@@ -157,6 +187,32 @@
 			<  300000000 11>,
 			<  400000000 15>,
 			<  600000000 17>;
+
+		qcom,speed5-bin-v6-c0 =
+			<          0 0>,
+			<  250000000 3>,
+			<  500000000 9>,
+			<  800000000 12>,
+			<  998400000 17>,
+			< 1113600000 24>;
+
+		qcom,speed5-bin-v6-c1 =
+			<          0 0>,
+			<  400000000 3>,
+			<  800000000 9>,
+			<  960000000 12>,
+			< 1113600000 14>,
+			< 1344000000 17>,
+			< 1459200000 20>,
+			< 1497600000 21>,
+			< 1651200000 26>;
+
+		qcom,speed5-bin-v6-cci =
+			<          0 0>,
+			<  200000000 3>,
+			<  300000000 11>,
+			<  400000000 15>,
+			<  600000000 17>;
 		#clock-cells = <1>;
 	};
 
@@ -211,8 +267,8 @@
 			<  960000  2636 >,
 			<  1113600 5346 >,
 			<  1344000 6079 >,
+			<  1459200 6079 >,
 			<  1497600 6079 >,
-			<  1612800 6079 >,
 			<  1651200 6079 >;
 		cpu-to-dev-map-4 =
 			<  200000 1525 >,
@@ -256,8 +312,8 @@
 			<  960000  297600 >,
 			< 1113600  297000 >,
 			< 1344000  595200 >,
+			< 1459200  595200 >,
 			< 1497600  595200 >,
-			< 1612800  595200 >,
 			< 1651200  595200 >;
 		cpu-to-dev-map-4 =
 			<  200000 200000 >,
@@ -295,8 +351,8 @@
                          <  960000 >,
 			 < 1113600 >,
 			 < 1344000 >,
+			 < 1459200 >,
 			 < 1497600 >,
-			 < 1612800 >,
 			 < 1651200 >;
 		qcom,cpufreq-table-4 =
 			 <  200000 >,
diff --git a/drivers/clk/qcom/clock-gcc-8936.c b/drivers/clk/qcom/clock-gcc-8936.c
index 6fc6b63ba2d..08671b444d9 100644
--- a/drivers/clk/qcom/clock-gcc-8936.c
+++ b/drivers/clk/qcom/clock-gcc-8936.c
@@ -534,6 +534,7 @@ static struct pll_freq_tbl apcs_c1_pll_freq[] = {
 	F_APCS_PLL(1344000000, 70, 0x0, 0x1, 0x0, 0x0, 0x0),
 	F_APCS_PLL(1363200000, 71, 0x0, 0x1, 0x0, 0x0, 0x0),
 	F_APCS_PLL(1420800000, 74, 0x0, 0x1, 0x0, 0x0, 0x0),
+	F_APCS_PLL(1459200000, 76, 0x0, 0x1, 0x0, 0x0, 0x0),
 	F_APCS_PLL(1497600000, 78, 0x0, 0x1, 0x0, 0x0, 0x0),
 	F_APCS_PLL(1536000000, 80, 0x0, 0x1, 0x0, 0x0, 0x0),
 	F_APCS_PLL(1574400000, 82, 0x0, 0x1, 0x0, 0x0, 0x0),