diff options
author | Bin Gao <bin.gao@intel.com> | 2013-03-30 00:11:07 -0700 |
---|---|---|
committer | Patrick Tjin <pattjin@google.com> | 2014-07-21 20:22:40 -0700 |
commit | 8a13ab75e9709abcf6fb1ec105111f922abdae75 (patch) | |
tree | fdacd83a9a8e60e3fad6c512259db4852bb45eca | |
parent | 1a86f0aeb6fc921c58dfdf97bc7fa23c58ff65f3 (diff) | |
download | bootstub-8a13ab75e9709abcf6fb1ec105111f922abdae75.tar.gz |
bootstub: add VLV2 SoC detection
BZ: 96845
Add ValleyView2 SoC (i.e. Baytrail platorm) detection for bootstub.
This is needed for further VLV2 related feature enabling, e.g. BIOS style
e820 read, etc.
Change-Id: Id590de166acb01a81cc11290bf1efdd27ba82a32
Signed-off-by: Bin Gao <bin.gao@intel.com>
Reviewed-on: http://android.intel.com:8080/99215
Reviewed-by: cactus <cactus@intel.com>
Reviewed-by: Renganathan, Prabu <prabu.renganathan@intel.com>
Reviewed-by: Anagani, Chandra Sekhar <chandra.sekhar.anagani@intel.com>
Reviewed-by: Ernst, Eric <eric.ernst@intel.com>
Reviewed-by: Imberton, Guilhem <guilhem.imberton@intel.com>
Tested-by: Ng, Cheon-woei <cheon-woei.ng@intel.com>
Reviewed-by: buildbot <buildbot@intel.com>
Tested-by: buildbot <buildbot@intel.com>
-rw-r--r-- | bootstub.c | 7 | ||||
-rw-r--r-- | bootstub.h | 4 |
2 files changed, 9 insertions, 2 deletions
@@ -159,10 +159,13 @@ int mrst_identify_cpu(void) u32 regs[4]; cpuid(1, ®s[CR_EAX], ®s[CR_EBX], ®s[CR_ECX], ®s[CR_EDX]); - if ((regs[CR_EAX] & PENWELL_FAMILY) == PENWELL_FAMILY) + + if ((regs[CR_EAX] & CPUID_MASK) == PENWELL_FAMILY) return MRST_CPU_CHIP_PENWELL; - else if ((regs[CR_EAX] & CLOVERVIEW_FAMILY) == CLOVERVIEW_FAMILY) + else if ((regs[CR_EAX] & CPUID_MASK) == CLOVERVIEW_FAMILY) return MRST_CPU_CHIP_CLOVERVIEW; + else if ((regs[CR_EAX] & CPUID_MASK) == VALLEYVIEW2_FAMILY) + return MRST_CPU_CHIP_VALLEYVIEW2; return MRST_CPU_CHIP_LINCROFT; } @@ -4,11 +4,15 @@ #ifndef _BOOT_STUB_HEAD #define _BOOT_STUB_HEAD +#define CPUID_MASK 0xffff0 #define PENWELL_FAMILY 0x20670 #define CLOVERVIEW_FAMILY 0x30650 +#define VALLEYVIEW2_FAMILY 0x30670 + #define MRST_CPU_CHIP_LINCROFT 1 #define MRST_CPU_CHIP_PENWELL 2 #define MRST_CPU_CHIP_CLOVERVIEW 3 +#define MRST_CPU_CHIP_VALLEYVIEW2 4 #define CMDLINE_OFFSET 0x1100000 #define BZIMAGE_SIZE_OFFSET (CMDLINE_OFFSET + CMDLINE_SIZE) |