diff options
| author | Christopher Ferris <cferris@google.com> | 2013-12-16 17:02:34 +0000 |
|---|---|---|
| committer | Gerrit Code Review <noreply-gerritcodereview@google.com> | 2013-12-16 17:02:34 +0000 |
| commit | ca38ed098b05a79d20e852348f27d7c40a53f801 (patch) | |
| tree | 4cab3dfb379e8abfbdf35b6cd8e97d162a161c53 | |
| parent | 88aabcda910c60b5ff0c9b0609b15e308ac4108d (diff) | |
| parent | c86aa056539523ec4aadd2bc9480807859448d3e (diff) | |
| download | msm8960-ca38ed098b05a79d20e852348f27d7c40a53f801.tar.gz | |
Merge "Add missing kernel files."android-l-preview_r2l-previewidea133-weekly-release
| -rw-r--r-- | kernel-headers/linux/mfd/timpani-audio.h | 4599 | ||||
| -rw-r--r-- | kernel-headers/linux/videodev2.h | 2294 | ||||
| -rw-r--r-- | original-kernel-headers/linux/timpani-audio.h | 5016 | ||||
| -rw-r--r-- | original-kernel-headers/linux/videodev2.h | 2688 |
4 files changed, 14597 insertions, 0 deletions
diff --git a/kernel-headers/linux/mfd/timpani-audio.h b/kernel-headers/linux/mfd/timpani-audio.h new file mode 100644 index 0000000..8206be2 --- /dev/null +++ b/kernel-headers/linux/mfd/timpani-audio.h @@ -0,0 +1,4599 @@ +/**************************************************************************** + **************************************************************************** + *** + *** This header was automatically generated from a Linux kernel header + *** of the same name, to make information necessary for userspace to + *** call into the kernel available to libc. It contains only constants, + *** structures, and macros generated from the original header, and thus, + *** contains no copyrightable information. + *** + *** To edit the content of this header, modify the corresponding + *** source file (e.g. under external/kernel-headers/original/) then + *** run bionic/libc/kernel/tools/update_all.py + *** + *** Any manual change here will be lost the next time this script will + *** be run. You've been warned! + *** + **************************************************************************** + ****************************************************************************/ +#ifndef __LINUX_MFD_TIMPANI_AUDIO_H +#define __LINUX_MFD_TIMPANI_AUDIO_H +#define TIMPANI_A_MREF (0x3) +#define TIMPANI_MREF_RWC "RW" +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_MREF_POR 0xe2 +#define TIMPANI_MREF_S 0 +#define TIMPANI_MREF_M 0xFF +#define TIMPANI_MREF_MREF_BG_EN_S 7 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_MREF_MREF_BG_EN_M 0x80 +#define TIMPANI_MREF_MREF_BG_EN_ENABLE 0x0 +#define TIMPANI_MREF_MREF_BG_EN_DISABLE 0x1 +#define TIMPANI_MREF_MREF_BG_REF_CUR_EN_S 6 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_MREF_MREF_BG_REF_CUR_EN_M 0x40 +#define TIMPANI_MREF_MREF_BG_REF_CUR_EN_ENABLE_NORMAL_OP 0x0 +#define TIMPANI_MREF_MREF_BG_REF_CUR_EN_DISABLE 0x1 +#define TIMPANI_MREF_MREF_200K_MODE_EN_S 5 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_MREF_MREF_200K_MODE_EN_M 0x20 +#define TIMPANI_MREF_MREF_200K_MODE_EN_ENABLE 0x0 +#define TIMPANI_MREF_MREF_200K_MODE_EN_DISABLE 0x1 +#define TIMPANI_MREF_MREF_PRE_CHARGE_EN_S 4 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_MREF_MREF_PRE_CHARGE_EN_M 0x10 +#define TIMPANI_MREF_MREF_PRE_CHARGE_EN_DISABLE 0x0 +#define TIMPANI_MREF_MREF_PRE_CHARGE_EN_ENABLE 0x1 +#define TIMPANI_MREF_MREF_100UA_CUR_CONN_S 3 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_MREF_MREF_100UA_CUR_CONN_M 0x8 +#define TIMPANI_MREF_MREF_100UA_CUR_CONN_ON_CHIP_RESISTOR_NORMAL_OP 0x0 +#define TIMPANI_MREF_MREF_100UA_CUR_CONN_ATEST 0x1 +#define TIMPANI_MREF_MREF_PTAT_CURRENT_S 2 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_MREF_MREF_PTAT_CURRENT_M 0x4 +#define TIMPANI_MREF_MREF_PTAT_CURRENT_V_10UA_PTAT_NORMAL_OP 0x0 +#define TIMPANI_MREF_MREF_PTAT_CURRENT_V_5UA_PTAT_BIAS_CURRENT 0x1 +#define TIMPANI_MREF_MREF_400K_MODE_EN_S 1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_MREF_MREF_400K_MODE_EN_M 0x2 +#define TIMPANI_MREF_MREF_400K_MODE_EN_ENABLE 0x0 +#define TIMPANI_MREF_MREF_400K_MODE_EN_DISABLE 0x1 +#define TIMPANI_MREF_RESERVED_S 0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_MREF_RESERVED_M 0x1 +#define TIMPANI_A_CDAC_IDAC_REF_CUR (0x4) +#define TIMPANI_CDAC_IDAC_REF_CUR_RWC "RW" +#define TIMPANI_CDAC_IDAC_REF_CUR_POR 0x8c +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDAC_IDAC_REF_CUR_S 0 +#define TIMPANI_CDAC_IDAC_REF_CUR_M 0xFF +#define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_REF_BUFF_CUR_S 5 +#define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_REF_BUFF_CUR_M 0xE0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_REF_BUFF_CUR_V_4UA 0x0 +#define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_REF_BUFF_CUR_V_6UA 0x1 +#define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_REF_BUFF_CUR_V_8UA 0x2 +#define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_REF_BUFF_CUR_V_9UA 0x3 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_REF_BUFF_CUR_V_10UA_NORMAL_OP 0x4 +#define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_REF_BUFF_CUR_V_11UA 0x5 +#define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_REF_BUFF_CUR_V_13UA 0x6 +#define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_REF_BUFF_CUR_V_15UA 0x7 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_BIAS_CUR_S 2 +#define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_BIAS_CUR_M 0x1C +#define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_BIAS_CUR_V_8_5UA 0x0 +#define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_BIAS_CUR_V_9_0UA 0x1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_BIAS_CUR_V_9_5UA 0x2 +#define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_BIAS_CUR_V_10_0UA_NORMAL_OP 0x3 +#define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_BIAS_CUR_V_10_5UA 0x4 +#define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_BIAS_CUR_V_11_0UA 0x5 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_BIAS_CUR_V_11_5UA 0x6 +#define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_BIAS_CUR_V_12_0UA 0x7 +#define TIMPANI_CDAC_IDAC_REF_CUR_IDAC_REF_CUR_S 0 +#define TIMPANI_CDAC_IDAC_REF_CUR_IDAC_REF_CUR_M 0x3 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDAC_IDAC_REF_CUR_IDAC_REF_CUR_V_2UA 0x0 +#define TIMPANI_CDAC_IDAC_REF_CUR_IDAC_REF_CUR_V_3UA 0x1 +#define TIMPANI_CDAC_IDAC_REF_CUR_IDAC_REF_CUR_V_5UA_NORMAL_OP 0x2 +#define TIMPANI_CDAC_IDAC_REF_CUR_IDAC_REF_CUR_V_8UA 0x3 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_A_TXADC12_REF_CURR (0x5) +#define TIMPANI_TXADC12_REF_CURR_RWC "RW" +#define TIMPANI_TXADC12_REF_CURR_POR 0xa0 +#define TIMPANI_TXADC12_REF_CURR_S 0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_TXADC12_REF_CURR_M 0xFF +#define TIMPANI_TXADC12_REF_CURR_TXADC1_REF_BUFF_CUR_S 6 +#define TIMPANI_TXADC12_REF_CURR_TXADC1_REF_BUFF_CUR_M 0xC0 +#define TIMPANI_TXADC12_REF_CURR_TXADC1_REF_BUFF_CUR_V_50UA 0x0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_TXADC12_REF_CURR_TXADC1_REF_BUFF_CUR_V_45UA 0x1 +#define TIMPANI_TXADC12_REF_CURR_TXADC1_REF_BUFF_CUR_V_40UA_NORMAL_OP 0x2 +#define TIMPANI_TXADC12_REF_CURR_TXADC1_REF_BUFF_CUR_V_35UA 0x3 +#define TIMPANI_TXADC12_REF_CURR_TXADC2_REF_BUFF_CUR_S 4 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_TXADC12_REF_CURR_TXADC2_REF_BUFF_CUR_M 0x30 +#define TIMPANI_TXADC12_REF_CURR_TXADC2_REF_BUFF_CUR_V_50UA 0x0 +#define TIMPANI_TXADC12_REF_CURR_TXADC2_REF_BUFF_CUR_V_45UA 0x1 +#define TIMPANI_TXADC12_REF_CURR_TXADC2_REF_BUFF_CUR_V_40UA_NORMAL_OP 0x2 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_TXADC12_REF_CURR_TXADC2_REF_BUFF_CUR_V_35UA 0x3 +#define TIMPANI_TXADC12_REF_CURR_RESERVED_S 0 +#define TIMPANI_TXADC12_REF_CURR_RESERVED_M 0xF +#define TIMPANI_A_TXADC3_EN (0x9) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_TXADC3_EN_RWC "RW" +#define TIMPANI_TXADC3_EN_POR 0 +#define TIMPANI_TXADC3_EN_S 0 +#define TIMPANI_TXADC3_EN_M 0xFF +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_TXADC3_EN_TXADC3_REF_EN_S 7 +#define TIMPANI_TXADC3_EN_TXADC3_REF_EN_M 0x80 +#define TIMPANI_TXADC3_EN_TXADC3_REF_EN_DISABLE 0x0 +#define TIMPANI_TXADC3_EN_TXADC3_REF_EN_ENABLE 0x1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_TXADC3_EN_TXADC3_DAC_REF_CUR_COMPENSATION_EN_S 6 +#define TIMPANI_TXADC3_EN_TXADC3_DAC_REF_CUR_COMPENSATION_EN_M 0x40 +#define TIMPANI_TXADC3_EN_TXADC3_DAC_REF_CUR_COMPENSATION_EN_DISABLE 0x0 +#define TIMPANI_TXADC3_EN_TXADC3_DAC_REF_CUR_COMPENSATION_EN_ENABLE 0x1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_TXADC3_EN_TXADC3_OTA1_EN_S 5 +#define TIMPANI_TXADC3_EN_TXADC3_OTA1_EN_M 0x20 +#define TIMPANI_TXADC3_EN_TXADC3_OTA1_EN_DISABLE 0x0 +#define TIMPANI_TXADC3_EN_TXADC3_OTA1_EN_ENABLE 0x1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_TXADC3_EN_TXADC3_OTA2_EN_S 4 +#define TIMPANI_TXADC3_EN_TXADC3_OTA2_EN_M 0x10 +#define TIMPANI_TXADC3_EN_TXADC3_OTA2_EN_DISABLE 0x0 +#define TIMPANI_TXADC3_EN_TXADC3_OTA2_EN_ENABLE 0x1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_TXADC3_EN_TXADC3_COMP_EN_S 3 +#define TIMPANI_TXADC3_EN_TXADC3_COMP_EN_M 0x8 +#define TIMPANI_TXADC3_EN_TXADC3_COMP_EN_DISABLE 0x0 +#define TIMPANI_TXADC3_EN_TXADC3_COMP_EN_ENABLE 0x1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_TXADC3_EN_TXADC3_DEM_EN_S 2 +#define TIMPANI_TXADC3_EN_TXADC3_DEM_EN_M 0x4 +#define TIMPANI_TXADC3_EN_TXADC3_DEM_EN_DISABLE 0x0 +#define TIMPANI_TXADC3_EN_TXADC3_DEM_EN_ENABLE 0x1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_TXADC3_EN_TXADC3_DEM_ERROR_DET_EN_S 1 +#define TIMPANI_TXADC3_EN_TXADC3_DEM_ERROR_DET_EN_M 0x2 +#define TIMPANI_TXADC3_EN_TXADC3_DEM_ERROR_DET_EN_DISABLE 0x0 +#define TIMPANI_TXADC3_EN_TXADC3_DEM_ERROR_DET_EN_ENABLE 0x1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_TXADC3_EN_RESERVED_S 0 +#define TIMPANI_TXADC3_EN_RESERVED_M 0x1 +#define TIMPANI_A_TXADC4_EN (0xA) +#define TIMPANI_TXADC4_EN_RWC "RW" +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_TXADC4_EN_POR 0 +#define TIMPANI_TXADC4_EN_S 0 +#define TIMPANI_TXADC4_EN_M 0xFF +#define TIMPANI_TXADC4_EN_TXADC4_REF_EN_S 7 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_TXADC4_EN_TXADC4_REF_EN_M 0x80 +#define TIMPANI_TXADC4_EN_TXADC4_REF_EN_DISABLE 0x0 +#define TIMPANI_TXADC4_EN_TXADC4_REF_EN_ENABLE 0x1 +#define TIMPANI_TXADC4_EN_TXADC4_DAC_REF_CUR_COMPENSATION_EN_S 6 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_TXADC4_EN_TXADC4_DAC_REF_CUR_COMPENSATION_EN_M 0x40 +#define TIMPANI_TXADC4_EN_TXADC4_DAC_REF_CUR_COMPENSATION_EN_DISABLE 0x0 +#define TIMPANI_TXADC4_EN_TXADC4_DAC_REF_CUR_COMPENSATION_EN_ENABLE 0x1 +#define TIMPANI_TXADC4_EN_TXADC4_OTA1_EN_S 5 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_TXADC4_EN_TXADC4_OTA1_EN_M 0x20 +#define TIMPANI_TXADC4_EN_TXADC4_OTA1_EN_DISABLE 0x0 +#define TIMPANI_TXADC4_EN_TXADC4_OTA1_EN_ENABLE 0x1 +#define TIMPANI_TXADC4_EN_TXADC4_OTA2_EN_S 4 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_TXADC4_EN_TXADC4_OTA2_EN_M 0x10 +#define TIMPANI_TXADC4_EN_TXADC4_OTA2_EN_DISABLE 0x0 +#define TIMPANI_TXADC4_EN_TXADC4_OTA2_EN_ENABLE 0x1 +#define TIMPANI_TXADC4_EN_TXADC4_COMP_EN_S 3 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_TXADC4_EN_TXADC4_COMP_EN_M 0x8 +#define TIMPANI_TXADC4_EN_TXADC4_COMP_EN_DISABLE 0x0 +#define TIMPANI_TXADC4_EN_TXADC4_COMP_EN_ENABLE 0x1 +#define TIMPANI_TXADC4_EN_TXADC4_DEM_EN_S 2 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_TXADC4_EN_TXADC4_DEM_EN_M 0x4 +#define TIMPANI_TXADC4_EN_TXADC4_DEM_EN_DISABLE 0x0 +#define TIMPANI_TXADC4_EN_TXADC4_DEM_EN_ENABLE 0x1 +#define TIMPANI_TXADC4_EN_TXADC4_DEM_ERROR_DET_EN_S 1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_TXADC4_EN_TXADC4_DEM_ERROR_DET_EN_M 0x2 +#define TIMPANI_TXADC4_EN_TXADC4_DEM_ERROR_DET_EN_DISABLE 0x0 +#define TIMPANI_TXADC4_EN_TXADC4_DEM_ERROR_DET_EN_ENABLE 0x1 +#define TIMPANI_TXADC4_EN_RESERVED_S 0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_TXADC4_EN_RESERVED_M 0x1 +#define TIMPANI_A_CODEC_TXADC_STATUS_REGISTER_1 (0xB) +#define TIMPANI_CODEC_TXADC_STATUS_REGISTER_1_RWC "R" +#define TIMPANI_CODEC_TXADC_STATUS_REGISTER_1_POR 0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CODEC_TXADC_STATUS_REGISTER_1_S 0 +#define TIMPANI_CODEC_TXADC_STATUS_REGISTER_1_M 0xFF +#define TIMPANI_CODEC_TXADC_STATUS_REGISTER_1_TXADC1_DEM_ERROR_S 7 +#define TIMPANI_CODEC_TXADC_STATUS_REGISTER_1_TXADC1_DEM_ERROR_M 0x80 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CODEC_TXADC_STATUS_REGISTER_1_TXADC2_DEM_ERROR_S 6 +#define TIMPANI_CODEC_TXADC_STATUS_REGISTER_1_TXADC2_DEM_ERROR_M 0x40 +#define TIMPANI_CODEC_TXADC_STATUS_REGISTER_1_TXADC3_DEM_ERROR_S 5 +#define TIMPANI_CODEC_TXADC_STATUS_REGISTER_1_TXADC3_DEM_ERROR_M 0x20 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CODEC_TXADC_STATUS_REGISTER_1_TXADC4_DEM_ERROR_S 4 +#define TIMPANI_CODEC_TXADC_STATUS_REGISTER_1_TXADC4_DEM_ERROR_M 0x10 +#define TIMPANI_CODEC_TXADC_STATUS_REGISTER_1_RESERVED_S 0 +#define TIMPANI_CODEC_TXADC_STATUS_REGISTER_1_RESERVED_M 0xF +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_A_TXFE1 (0xD) +#define TIMPANI_TXFE1_RWC "RW" +#define TIMPANI_TXFE1_POR 0 +#define TIMPANI_TXFE1_S 0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_TXFE1_M 0xFF +#define TIMPANI_TXFE1_TXFE1_EN_S 7 +#define TIMPANI_TXFE1_TXFE1_EN_M 0x80 +#define TIMPANI_TXFE1_TXFE1_EN_DISABLE 0x0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_TXFE1_TXFE1_EN_ENABLE 0x1 +#define TIMPANI_TXFE1_TXFE1_GAIN_S 5 +#define TIMPANI_TXFE1_TXFE1_GAIN_M 0x60 +#define TIMPANI_TXFE1_TXFE1_GAIN_V_0DB 0x0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_TXFE1_TXFE1_GAIN_V_4_5DB 0x1 +#define TIMPANI_TXFE1_TXFE1_GAIN_V_24DB_1 0x2 +#define TIMPANI_TXFE1_TXFE1_GAIN_V_24DB_2 0x3 +#define TIMPANI_TXFE1_TXFE1_IN_MIC1_CONN_S 4 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_TXFE1_TXFE1_IN_MIC1_CONN_M 0x10 +#define TIMPANI_TXFE1_TXFE1_IN_MIC1_CONN_NO_CONNECT 0x0 +#define TIMPANI_TXFE1_TXFE1_IN_MIC1_CONN_CONNECT 0x1 +#define TIMPANI_TXFE1_TXFE1_IN_MIC2_CONN_S 3 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_TXFE1_TXFE1_IN_MIC2_CONN_M 0x8 +#define TIMPANI_TXFE1_TXFE1_IN_MIC2_CONN_NO_CONNECT 0x0 +#define TIMPANI_TXFE1_TXFE1_IN_MIC2_CONN_CONNECT 0x1 +#define TIMPANI_TXFE1_TXFE1_IN_LINE_I_L_CONN_S 2 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_TXFE1_TXFE1_IN_LINE_I_L_CONN_M 0x4 +#define TIMPANI_TXFE1_TXFE1_IN_LINE_I_L_CONN_NO_CONNECT 0x0 +#define TIMPANI_TXFE1_TXFE1_IN_LINE_I_L_CONN_CONNECT 0x1 +#define TIMPANI_TXFE1_TXFE1_IN_LINE_I_R_CONN_S 1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_TXFE1_TXFE1_IN_LINE_I_R_CONN_M 0x2 +#define TIMPANI_TXFE1_TXFE1_IN_LINE_I_R_CONN_NO_CONNECT 0x0 +#define TIMPANI_TXFE1_TXFE1_IN_LINE_I_R_CONN_CONNECT 0x1 +#define TIMPANI_TXFE1_TXFE1_IN_AUXI_CONN_S 0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_TXFE1_TXFE1_IN_AUXI_CONN_M 0x1 +#define TIMPANI_TXFE1_TXFE1_IN_AUXI_CONN_NO_CONNECT 0x0 +#define TIMPANI_TXFE1_TXFE1_IN_AUXI_CONN_CONNECT 0x1 +#define TIMPANI_A_TXFE2 (0xE) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_TXFE2_RWC "RW" +#define TIMPANI_TXFE2_POR 0 +#define TIMPANI_TXFE2_S 0 +#define TIMPANI_TXFE2_M 0xFF +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_TXFE2_TXFE2_EN_S 7 +#define TIMPANI_TXFE2_TXFE2_EN_M 0x80 +#define TIMPANI_TXFE2_TXFE2_EN_DISABLE 0x0 +#define TIMPANI_TXFE2_TXFE2_EN_ENABLE 0x1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_TXFE2_TXFE2_GAIN_S 5 +#define TIMPANI_TXFE2_TXFE2_GAIN_M 0x60 +#define TIMPANI_TXFE2_TXFE2_GAIN_V_0DB 0x0 +#define TIMPANI_TXFE2_TXFE2_GAIN_V_4_5DB 0x1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_TXFE2_TXFE2_GAIN_V_24DB_1 0x2 +#define TIMPANI_TXFE2_TXFE2_GAIN_V_24DB_2 0x3 +#define TIMPANI_TXFE2_TXFE2_IN_MIC1_CONN_S 4 +#define TIMPANI_TXFE2_TXFE2_IN_MIC1_CONN_M 0x10 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_TXFE2_TXFE2_IN_MIC1_CONN_NO_CONNECT 0x0 +#define TIMPANI_TXFE2_TXFE2_IN_MIC1_CONN_CONNECT 0x1 +#define TIMPANI_TXFE2_TXFE2_IN_MIC2_CONN_S 3 +#define TIMPANI_TXFE2_TXFE2_IN_MIC2_CONN_M 0x8 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_TXFE2_TXFE2_IN_MIC2_CONN_NO_CONNECT 0x0 +#define TIMPANI_TXFE2_TXFE2_IN_MIC2_CONN_CONNECT 0x1 +#define TIMPANI_TXFE2_TXFE2_IN_LINE_I_L_CONN_S 2 +#define TIMPANI_TXFE2_TXFE2_IN_LINE_I_L_CONN_M 0x4 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_TXFE2_TXFE2_IN_LINE_I_L_CONN_NO_CONNECT 0x0 +#define TIMPANI_TXFE2_TXFE2_IN_LINE_I_L_CONN_CONNECT 0x1 +#define TIMPANI_TXFE2_TXFE2_IN_LINE_I_R_CONN_S 1 +#define TIMPANI_TXFE2_TXFE2_IN_LINE_I_R_CONN_M 0x2 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_TXFE2_TXFE2_IN_LINE_I_R_CONN_NO_CONNECT 0x0 +#define TIMPANI_TXFE2_TXFE2_IN_LINE_I_R_CONN_CONNECT 0x1 +#define TIMPANI_TXFE2_TXFE2_IN_AUXI_CONN_S 0 +#define TIMPANI_TXFE2_TXFE2_IN_AUXI_CONN_M 0x1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_TXFE2_TXFE2_IN_AUXI_CONN_NO_CONNECT 0x0 +#define TIMPANI_TXFE2_TXFE2_IN_AUXI_CONN_CONNECT 0x1 +#define TIMPANI_A_TXFE12_ATEST (0xF) +#define TIMPANI_TXFE12_ATEST_RWC "RW" +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_TXFE12_ATEST_POR 0 +#define TIMPANI_TXFE12_ATEST_S 0 +#define TIMPANI_TXFE12_ATEST_M 0xFF +#define TIMPANI_TXFE12_ATEST_TXFE1_OUT_SHORT_TO_VICM_EN_S 7 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_TXFE12_ATEST_TXFE1_OUT_SHORT_TO_VICM_EN_M 0x80 +#define TIMPANI_TXFE12_ATEST_TXFE1_OUT_SHORT_TO_VICM_EN_DISABLE 0x0 +#define TIMPANI_TXFE12_ATEST_TXFE1_OUT_SHORT_TO_VICM_EN_ENABLE 0x1 +#define TIMPANI_TXFE12_ATEST_TXFE1_BYPASS_EN_S 6 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_TXFE12_ATEST_TXFE1_BYPASS_EN_M 0x40 +#define TIMPANI_TXFE12_ATEST_TXFE1_BYPASS_EN_DISABLE 0x0 +#define TIMPANI_TXFE12_ATEST_TXFE1_BYPASS_EN_ENABLE 0x1 +#define TIMPANI_TXFE12_ATEST_TXFE1_CMOUT_ATEST_CONN_S 5 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_TXFE12_ATEST_TXFE1_CMOUT_ATEST_CONN_M 0x20 +#define TIMPANI_TXFE12_ATEST_TXFE1_CMOUT_ATEST_CONN_NO_CONNECT 0x0 +#define TIMPANI_TXFE12_ATEST_TXFE1_CMOUT_ATEST_CONN_CONNECT 0x1 +#define TIMPANI_TXFE12_ATEST_TXFE1_OUT_ATEST_CONN_S 4 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_TXFE12_ATEST_TXFE1_OUT_ATEST_CONN_M 0x10 +#define TIMPANI_TXFE12_ATEST_TXFE1_OUT_ATEST_CONN_NO_CONNECT 0x0 +#define TIMPANI_TXFE12_ATEST_TXFE1_OUT_ATEST_CONN_CONNECT 0x1 +#define TIMPANI_TXFE12_ATEST_TXFE2_OUT_SHORT_TO_VICM_EN_S 3 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_TXFE12_ATEST_TXFE2_OUT_SHORT_TO_VICM_EN_M 0x8 +#define TIMPANI_TXFE12_ATEST_TXFE2_OUT_SHORT_TO_VICM_EN_DISABLE 0x0 +#define TIMPANI_TXFE12_ATEST_TXFE2_OUT_SHORT_TO_VICM_EN_ENABLE 0x1 +#define TIMPANI_TXFE12_ATEST_TXFE2_BYPASS_EN_S 2 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_TXFE12_ATEST_TXFE2_BYPASS_EN_M 0x4 +#define TIMPANI_TXFE12_ATEST_TXFE2_BYPASS_EN_DISABLE 0x0 +#define TIMPANI_TXFE12_ATEST_TXFE2_BYPASS_EN_ENABLE 0x1 +#define TIMPANI_TXFE12_ATEST_TXFE2_CMOUT_ATEST_CONN_S 1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_TXFE12_ATEST_TXFE2_CMOUT_ATEST_CONN_M 0x2 +#define TIMPANI_TXFE12_ATEST_TXFE2_CMOUT_ATEST_CONN_NO_CONNECT 0x0 +#define TIMPANI_TXFE12_ATEST_TXFE2_CMOUT_ATEST_CONN_CONNECT 0x1 +#define TIMPANI_TXFE12_ATEST_TXFE2_OUT_ATEST_CONN_S 0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_TXFE12_ATEST_TXFE2_OUT_ATEST_CONN_M 0x1 +#define TIMPANI_TXFE12_ATEST_TXFE2_OUT_ATEST_CONN_NO_CONNECT 0x0 +#define TIMPANI_TXFE12_ATEST_TXFE2_OUT_ATEST_CONN_CONNECT 0x1 +#define TIMPANI_A_TXFE_CLT (0x10) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_TXFE_CLT_RWC "RW" +#define TIMPANI_TXFE_CLT_POR 0x68 +#define TIMPANI_TXFE_CLT_S 0 +#define TIMPANI_TXFE_CLT_M 0xFF +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_TXFE_CLT_TXFE_OUT_CM_VOLT_S 5 +#define TIMPANI_TXFE_CLT_TXFE_OUT_CM_VOLT_M 0xE0 +#define TIMPANI_TXFE_CLT_TXFE_OUT_CM_VOLT_V_1_125V 0x0 +#define TIMPANI_TXFE_CLT_TXFE_OUT_CM_VOLT_V_1_100V 0x1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_TXFE_CLT_TXFE_OUT_CM_VOLT_V_1_075V 0x2 +#define TIMPANI_TXFE_CLT_TXFE_OUT_CM_VOLT_V_1_050V_NORMAL_OP 0x3 +#define TIMPANI_TXFE_CLT_TXFE_OUT_CM_VOLT_V_1_025V 0x4 +#define TIMPANI_TXFE_CLT_TXFE_OUT_CM_VOLT_V_1_000V 0x5 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_TXFE_CLT_TXFE_OUT_CM_VOLT_V_0_975V 0x6 +#define TIMPANI_TXFE_CLT_TXFE_OUT_CM_VOLT_V_0_950V 0x7 +#define TIMPANI_TXFE_CLT_TXFE_BIAS_CUR_S 3 +#define TIMPANI_TXFE_CLT_TXFE_BIAS_CUR_M 0x18 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_TXFE_CLT_TXFE_BIAS_CUR_V_3UA 0x0 +#define TIMPANI_TXFE_CLT_TXFE_BIAS_CUR_V_4UA_NORMAL_OP 0x1 +#define TIMPANI_TXFE_CLT_TXFE_BIAS_CUR_V_6UA 0x2 +#define TIMPANI_TXFE_CLT_TXFE_BIAS_CUR_V_8UA 0x3 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_TXFE_CLT_RESERVED_S 0 +#define TIMPANI_TXFE_CLT_RESERVED_M 0x7 +#define TIMPANI_A_TXADC1_EN (0x11) +#define TIMPANI_TXADC1_EN_RWC "RW" +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_TXADC1_EN_POR 0 +#define TIMPANI_TXADC1_EN_S 0 +#define TIMPANI_TXADC1_EN_M 0xFF +#define TIMPANI_TXADC1_EN_TXADC1_REF_EN_S 7 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_TXADC1_EN_TXADC1_REF_EN_M 0x80 +#define TIMPANI_TXADC1_EN_TXADC1_REF_EN_DISABLE 0x0 +#define TIMPANI_TXADC1_EN_TXADC1_REF_EN_ENABLE 0x1 +#define TIMPANI_TXADC1_EN_TXADC1_DAC_REF_CUR_COMPENSATION_EN_S 6 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_TXADC1_EN_TXADC1_DAC_REF_CUR_COMPENSATION_EN_M 0x40 +#define TIMPANI_TXADC1_EN_TXADC1_DAC_REF_CUR_COMPENSATION_EN_DISABLE 0x0 +#define TIMPANI_TXADC1_EN_TXADC1_DAC_REF_CUR_COMPENSATION_EN_ENABLE 0x1 +#define TIMPANI_TXADC1_EN_TXADC1_OTA1_EN_S 5 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_TXADC1_EN_TXADC1_OTA1_EN_M 0x20 +#define TIMPANI_TXADC1_EN_TXADC1_OTA1_EN_DISABLE 0x0 +#define TIMPANI_TXADC1_EN_TXADC1_OTA1_EN_ENABLE 0x1 +#define TIMPANI_TXADC1_EN_TXADC1_OTA2_EN_S 4 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_TXADC1_EN_TXADC1_OTA2_EN_M 0x10 +#define TIMPANI_TXADC1_EN_TXADC1_OTA2_EN_DISABLE 0x0 +#define TIMPANI_TXADC1_EN_TXADC1_OTA2_EN_ENABLE 0x1 +#define TIMPANI_TXADC1_EN_TXADC1_COMP_EN_S 3 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_TXADC1_EN_TXADC1_COMP_EN_M 0x8 +#define TIMPANI_TXADC1_EN_TXADC1_COMP_EN_DISABLE 0x0 +#define TIMPANI_TXADC1_EN_TXADC1_COMP_EN_ENABLE 0x1 +#define TIMPANI_TXADC1_EN_TXADC1_DEM_EN_S 2 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_TXADC1_EN_TXADC1_DEM_EN_M 0x4 +#define TIMPANI_TXADC1_EN_TXADC1_DEM_EN_DISABLE 0x0 +#define TIMPANI_TXADC1_EN_TXADC1_DEM_EN_ENABLE 0x1 +#define TIMPANI_TXADC1_EN_TXADC1_DEM_ERROR_DET_EN_S 1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_TXADC1_EN_TXADC1_DEM_ERROR_DET_EN_M 0x2 +#define TIMPANI_TXADC1_EN_TXADC1_DEM_ERROR_DET_EN_DISABLE 0x0 +#define TIMPANI_TXADC1_EN_TXADC1_DEM_ERROR_DET_EN_ENABLE 0x1 +#define TIMPANI_TXADC1_EN_RESERVED_S 0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_TXADC1_EN_RESERVED_M 0x1 +#define TIMPANI_A_TXADC2_EN (0x12) +#define TIMPANI_TXADC2_EN_RWC "RW" +#define TIMPANI_TXADC2_EN_POR 0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_TXADC2_EN_S 0 +#define TIMPANI_TXADC2_EN_M 0xFF +#define TIMPANI_TXADC2_EN_TXADC2_REF_EN_S 7 +#define TIMPANI_TXADC2_EN_TXADC2_REF_EN_M 0x80 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_TXADC2_EN_TXADC2_REF_EN_DISABLE 0x0 +#define TIMPANI_TXADC2_EN_TXADC2_REF_EN_ENABLE 0x1 +#define TIMPANI_TXADC2_EN_TXADC2_DAC_REF_CUR_COMPENSATION_EN_S 6 +#define TIMPANI_TXADC2_EN_TXADC2_DAC_REF_CUR_COMPENSATION_EN_M 0x40 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_TXADC2_EN_TXADC2_DAC_REF_CUR_COMPENSATION_EN_DISABLE 0x0 +#define TIMPANI_TXADC2_EN_TXADC2_DAC_REF_CUR_COMPENSATION_EN_ENABLE 0x1 +#define TIMPANI_TXADC2_EN_TXADC2_OTA1_EN_S 5 +#define TIMPANI_TXADC2_EN_TXADC2_OTA1_EN_M 0x20 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_TXADC2_EN_TXADC2_OTA1_EN_DISABLE 0x0 +#define TIMPANI_TXADC2_EN_TXADC2_OTA1_EN_ENABLE 0x1 +#define TIMPANI_TXADC2_EN_TXADC2_OTA2_EN_S 4 +#define TIMPANI_TXADC2_EN_TXADC2_OTA2_EN_M 0x10 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_TXADC2_EN_TXADC2_OTA2_EN_DISABLE 0x0 +#define TIMPANI_TXADC2_EN_TXADC2_OTA2_EN_ENABLE 0x1 +#define TIMPANI_TXADC2_EN_TXADC2_COMP_EN_S 3 +#define TIMPANI_TXADC2_EN_TXADC2_COMP_EN_M 0x8 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_TXADC2_EN_TXADC2_COMP_EN_DISABLE 0x0 +#define TIMPANI_TXADC2_EN_TXADC2_COMP_EN_ENABLE 0x1 +#define TIMPANI_TXADC2_EN_TXADC2_DEM_EN_S 2 +#define TIMPANI_TXADC2_EN_TXADC2_DEM_EN_M 0x4 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_TXADC2_EN_TXADC2_DEM_EN_DISABLE 0x0 +#define TIMPANI_TXADC2_EN_TXADC2_DEM_EN_ENABLE 0x1 +#define TIMPANI_TXADC2_EN_TXADC2_DEM_ERROR_DET_EN_S 1 +#define TIMPANI_TXADC2_EN_TXADC2_DEM_ERROR_DET_EN_M 0x2 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_TXADC2_EN_TXADC2_DEM_ERROR_DET_EN_DISABLE 0x0 +#define TIMPANI_TXADC2_EN_TXADC2_DEM_ERROR_DET_EN_ENABLE 0x1 +#define TIMPANI_TXADC2_EN_RESERVED_S 0 +#define TIMPANI_TXADC2_EN_RESERVED_M 0x1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_A_TXADC_CTL (0x13) +#define TIMPANI_TXADC_CTL_RWC "RW" +#define TIMPANI_TXADC_CTL_POR 0x58 +#define TIMPANI_TXADC_CTL_S 0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_TXADC_CTL_M 0xFF +#define TIMPANI_TXADC_CTL_TXADC_DAC_REF_DDA_AMP_BIAS_CUR_S 6 +#define TIMPANI_TXADC_CTL_TXADC_DAC_REF_DDA_AMP_BIAS_CUR_M 0xC0 +#define TIMPANI_TXADC_CTL_TXADC_DAC_REF_DDA_AMP_BIAS_CUR_V_5UA 0x0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_TXADC_CTL_TXADC_DAC_REF_DDA_AMP_BIAS_CUR_V_10UA_NORMAL_OP 0x1 +#define TIMPANI_TXADC_CTL_TXADC_DAC_REF_DDA_AMP_BIAS_CUR_V_15UA 0x2 +#define TIMPANI_TXADC_CTL_TXADC_DAC_REF_DDA_AMP_BIAS_CUR_V_20UA 0x3 +#define TIMPANI_TXADC_CTL_TXADC_DAC_REF_SRC_FOLLOWER_BIAS_CUR_S 4 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_TXADC_CTL_TXADC_DAC_REF_SRC_FOLLOWER_BIAS_CUR_M 0x30 +#define TIMPANI_TXADC_CTL_TXADC_DAC_REF_SRC_FOLLOWER_BIAS_CUR_V_40UA 0x0 +#define TIMPANI_TXADC_CTL_TXADC_DAC_REF_SRC_FOLLOWER_BIAS_CUR_V_80UA 0x1 +#define TIMPANI_TXADC_CTL_TXADC_DAC_REF_SRC_FOLLOWER_BIAS_CUR_V_120UA 0x2 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_TXADC_CTL_TXADC_DAC_REF_SRC_FOLLOWER_BIAS_CUR_V_160UA 0x3 +#define TIMPANI_TXADC_CTL_TXADC_DAC_REF_VOLT_S 2 +#define TIMPANI_TXADC_CTL_TXADC_DAC_REF_VOLT_M 0xC +#define TIMPANI_TXADC_CTL_TXADC_DAC_REF_VOLT_V_1_8V 0x0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_TXADC_CTL_TXADC_DAC_REF_VOLT_V_1_7V 0x1 +#define TIMPANI_TXADC_CTL_TXADC_DAC_REF_VOLT_V_1_6V_NORMAL_OP 0x2 +#define TIMPANI_TXADC_CTL_TXADC_DAC_REF_VOLT_V_1_5V 0x3 +#define TIMPANI_TXADC_CTL_TXADC_VREFMID_BIAS_CUR_S 0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_TXADC_CTL_TXADC_VREFMID_BIAS_CUR_M 0x3 +#define TIMPANI_TXADC_CTL_TXADC_VREFMID_BIAS_CUR_V_20UA_NORMAL_OP 0x0 +#define TIMPANI_TXADC_CTL_TXADC_VREFMID_BIAS_CUR_V_40UA 0x1 +#define TIMPANI_TXADC_CTL_TXADC_VREFMID_BIAS_CUR_V_80UA 0x2 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_TXADC_CTL_TXADC_VREFMID_BIAS_CUR_V_160UA 0x3 +#define TIMPANI_A_TXADC_CTL2 (0x14) +#define TIMPANI_TXADC_CTL2_RWC "RW" +#define TIMPANI_TXADC_CTL2_POR 0x64 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_TXADC_CTL2_S 0 +#define TIMPANI_TXADC_CTL2_M 0xFF +#define TIMPANI_TXADC_CTL2_TXADC_COMP_THRESH_VOLT_S 6 +#define TIMPANI_TXADC_CTL2_TXADC_COMP_THRESH_VOLT_M 0xC0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_TXADC_CTL2_TXADC_COMP_THRESH_VOLT_V_333MV 0x0 +#define TIMPANI_TXADC_CTL2_TXADC_COMP_THRESH_VOLT_V_356MV_NORMAL_OP 0x1 +#define TIMPANI_TXADC_CTL2_TXADC_COMP_THRESH_VOLT_V_378MV 0x2 +#define TIMPANI_TXADC_CTL2_TXADC_COMP_THRESH_VOLT_V_400MV 0x3 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_TXADC_CTL2_TXADC_VICM_REF_BUFF_BIAS_CUR_S 4 +#define TIMPANI_TXADC_CTL2_TXADC_VICM_REF_BUFF_BIAS_CUR_M 0x30 +#define TIMPANI_TXADC_CTL2_TXADC_VICM_REF_BUFF_BIAS_CUR_V_50UA 0x0 +#define TIMPANI_TXADC_CTL2_TXADC_VICM_REF_BUFF_BIAS_CUR_V_100UA 0x1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_TXADC_CTL2_TXADC_VICM_REF_BUFF_BIAS_CUR_V_200UA_NORMAL_OP 0x2 +#define TIMPANI_TXADC_CTL2_TXADC_VICM_REF_BUFF_BIAS_CUR_V_400UA 0x3 +#define TIMPANI_TXADC_CTL2_TXADC_VICM_REF_BUFF_OUT_VOLT_S 2 +#define TIMPANI_TXADC_CTL2_TXADC_VICM_REF_BUFF_OUT_VOLT_M 0xC +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_TXADC_CTL2_TXADC_VICM_REF_BUFF_OUT_VOLT_V_1_1V 0x0 +#define TIMPANI_TXADC_CTL2_TXADC_VICM_REF_BUFF_OUT_VOLT_V_1_15V_NORMAL_OP 0x1 +#define TIMPANI_TXADC_CTL2_TXADC_VICM_REF_BUFF_OUT_VOLT_V_1_2V 0x2 +#define TIMPANI_TXADC_CTL2_TXADC_VICM_REF_BUFF_OUT_VOLT_V_1_25V 0x3 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_TXADC_CTL2_TXADC_VOCM_BUFFER_BIAS_CUR_S 1 +#define TIMPANI_TXADC_CTL2_TXADC_VOCM_BUFFER_BIAS_CUR_M 0x2 +#define TIMPANI_TXADC_CTL2_TXADC_VOCM_BUFFER_BIAS_CUR_V_50UA_NORMAL_OP 0x0 +#define TIMPANI_TXADC_CTL2_TXADC_VOCM_BUFFER_BIAS_CUR_V_100UA 0x1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_TXADC_CTL2_TXADC_DIG_OUT_EN_S 0 +#define TIMPANI_TXADC_CTL2_TXADC_DIG_OUT_EN_M 0x1 +#define TIMPANI_TXADC_CTL2_TXADC_DIG_OUT_EN_DISABLE 0x0 +#define TIMPANI_TXADC_CTL2_TXADC_DIG_OUT_EN_ENABLE_NORMAL_OP 0x1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_A_TXADC_CTL3 (0x15) +#define TIMPANI_TXADC_CTL3_RWC "RW" +#define TIMPANI_TXADC_CTL3_POR 0x64 +#define TIMPANI_TXADC_CTL3_S 0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_TXADC_CTL3_M 0xFF +#define TIMPANI_TXADC_CTL3_TXADC_VOCM_REF_BUFF_VOLT_S 6 +#define TIMPANI_TXADC_CTL3_TXADC_VOCM_REF_BUFF_VOLT_M 0xC0 +#define TIMPANI_TXADC_CTL3_TXADC_VOCM_REF_BUFF_VOLT_V_0_85V 0x0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_TXADC_CTL3_TXADC_VOCM_REF_BUFF_VOLT_V_0_90V_NORMAL_OP 0x1 +#define TIMPANI_TXADC_CTL3_TXADC_VOCM_REF_BUFF_VOLT_V_0_95V 0x2 +#define TIMPANI_TXADC_CTL3_TXADC_VOCM_REF_BUFF_VOLT_V_1_00V 0x3 +#define TIMPANI_TXADC_CTL3_TXADC_OTA1_BIAS_CUR_S 4 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_TXADC_CTL3_TXADC_OTA1_BIAS_CUR_M 0x30 +#define TIMPANI_TXADC_CTL3_TXADC_OTA1_BIAS_CUR_V_10UA 0x0 +#define TIMPANI_TXADC_CTL3_TXADC_OTA1_BIAS_CUR_V_15UA 0x1 +#define TIMPANI_TXADC_CTL3_TXADC_OTA1_BIAS_CUR_V_20UA_NORMAL_OP 0x2 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_TXADC_CTL3_TXADC_OTA1_BIAS_CUR_V_25UA 0x3 +#define TIMPANI_TXADC_CTL3_TXADC_OTA2_BIAS_CUR_S 2 +#define TIMPANI_TXADC_CTL3_TXADC_OTA2_BIAS_CUR_M 0xC +#define TIMPANI_TXADC_CTL3_TXADC_OTA2_BIAS_CUR_V_5UA 0x0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_TXADC_CTL3_TXADC_OTA2_BIAS_CUR_V_10UA_NORMAL_OP 0x1 +#define TIMPANI_TXADC_CTL3_TXADC_OTA2_BIAS_CUR_V_15UA 0x2 +#define TIMPANI_TXADC_CTL3_TXADC_OTA2_BIAS_CUR_V_20UA 0x3 +#define TIMPANI_TXADC_CTL3_TXADC_COMP_BIAS_CUR_S 1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_TXADC_CTL3_TXADC_COMP_BIAS_CUR_M 0x2 +#define TIMPANI_TXADC_CTL3_TXADC_COMP_BIAS_CUR_V_5UA_NORMAL_OP 0x0 +#define TIMPANI_TXADC_CTL3_TXADC_COMP_BIAS_CUR_V_10UA 0x1 +#define TIMPANI_TXADC_CTL3_RESERVED_S 0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_TXADC_CTL3_RESERVED_M 0x1 +#define TIMPANI_A_TXADC_CHOP_CTL (0x16) +#define TIMPANI_TXADC_CHOP_CTL_RWC "RW" +#define TIMPANI_TXADC_CHOP_CTL_POR 0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_TXADC_CHOP_CTL_S 0 +#define TIMPANI_TXADC_CHOP_CTL_M 0xFF +#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_EN_S 7 +#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_EN_M 0x80 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_EN_DISABLE 0x0 +#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_EN_ENABLE 0x1 +#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_DIV_RATIO_S 4 +#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_DIV_RATIO_M 0x70 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_DIV_RATIO_V_2_NORMAL_OP 0x0 +#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_DIV_RATIO_V_4 0x1 +#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_DIV_RATIO_V_8 0x2 +#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_DIV_RATIO_V_16 0x3 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_DIV_RATIO_V_32 0x4 +#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_DIV_RATIO_V_64 0x5 +#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_DIV_RATIO_V_128 0x6 +#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_DIV_RATIO_V_256 0x7 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_STATE_RESET_S 3 +#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_STATE_RESET_M 0x8 +#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_STATE_RESET_NORMAL_OP 0x0 +#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_STATE_RESET_RESET_CHOP 0x1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_CLK_PHASE_SEL_S 2 +#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_CLK_PHASE_SEL_M 0x4 +#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_CLK_PHASE_SEL_FALLING_EDGE_CK1 0x0 +#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_CLK_PHASE_SEL_FALLING_EDGE_CK2 0x1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_TXADC_CHOP_CTL_RESERVED_S 0 +#define TIMPANI_TXADC_CHOP_CTL_RESERVED_M 0x3 +#define TIMPANI_A_TXFE3 (0x18) +#define TIMPANI_TXFE3_RWC "RW" +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_TXFE3_POR 0 +#define TIMPANI_TXFE3_S 0 +#define TIMPANI_TXFE3_M 0xFF +#define TIMPANI_TXFE3_TXFE3_EN_S 7 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_TXFE3_TXFE3_EN_M 0x80 +#define TIMPANI_TXFE3_TXFE3_EN_DISABLE 0x0 +#define TIMPANI_TXFE3_TXFE3_EN_ENABLE 0x1 +#define TIMPANI_TXFE3_TXFE3_GAIN_S 5 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_TXFE3_TXFE3_GAIN_M 0x60 +#define TIMPANI_TXFE3_TXFE3_GAIN_V_0DB 0x0 +#define TIMPANI_TXFE3_TXFE3_GAIN_V_4_5DB 0x1 +#define TIMPANI_TXFE3_TXFE3_GAIN_V_24DB_1 0x2 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_TXFE3_TXFE3_GAIN_V_24DB_2 0x3 +#define TIMPANI_TXFE3_RESERVED_1_S 2 +#define TIMPANI_TXFE3_RESERVED_1_M 0x1C +#define TIMPANI_TXFE3_TXFE3_IN_CONN_S 1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_TXFE3_TXFE3_IN_CONN_M 0x2 +#define TIMPANI_TXFE3_TXFE3_IN_CONN_NO_CONNECT 0x0 +#define TIMPANI_TXFE3_TXFE3_IN_CONN_LINE_IN_L 0x1 +#define TIMPANI_TXFE3_RESERVED_2_S 0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_TXFE3_RESERVED_2_M 0x1 +#define TIMPANI_A_TXFE4 (0x19) +#define TIMPANI_TXFE4_RWC "RW" +#define TIMPANI_TXFE4_POR 0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_TXFE4_S 0 +#define TIMPANI_TXFE4_M 0xFF +#define TIMPANI_TXFE4_TXFE4_EN_S 7 +#define TIMPANI_TXFE4_TXFE4_EN_M 0x80 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_TXFE4_TXFE4_EN_DISABLE 0x0 +#define TIMPANI_TXFE4_TXFE4_EN_ENABLE 0x1 +#define TIMPANI_TXFE4_TXFE4_GAIN_S 5 +#define TIMPANI_TXFE4_TXFE4_GAIN_M 0x60 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_TXFE4_TXFE4_GAIN_V_0DB 0x0 +#define TIMPANI_TXFE4_TXFE4_GAIN_V_4_5DB 0x1 +#define TIMPANI_TXFE4_TXFE4_GAIN_V_24DB_1 0x2 +#define TIMPANI_TXFE4_TXFE4_GAIN_V_24DB_2 0x3 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_TXFE4_RESERVED_1_S 2 +#define TIMPANI_TXFE4_RESERVED_1_M 0x1C +#define TIMPANI_TXFE4_TXFE4_IN_CONN_S 1 +#define TIMPANI_TXFE4_TXFE4_IN_CONN_M 0x2 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_TXFE4_TXFE4_IN_CONN_NO_CONNECT 0x0 +#define TIMPANI_TXFE4_TXFE4_IN_CONN_LINE_IN_R 0x1 +#define TIMPANI_TXFE4_RESERVED_2_S 0 +#define TIMPANI_TXFE4_RESERVED_2_M 0x1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_A_TXFE3_ATEST (0x1A) +#define TIMPANI_TXFE3_ATEST_RWC "RW" +#define TIMPANI_TXFE3_ATEST_POR 0 +#define TIMPANI_TXFE3_ATEST_S 0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_TXFE3_ATEST_M 0xFF +#define TIMPANI_TXFE3_ATEST_TXFE3_OUT_SHORT_TO_VICM_EN_S 7 +#define TIMPANI_TXFE3_ATEST_TXFE3_OUT_SHORT_TO_VICM_EN_M 0x80 +#define TIMPANI_TXFE3_ATEST_TXFE3_OUT_SHORT_TO_VICM_EN_DISABLE 0x0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_TXFE3_ATEST_TXFE3_OUT_SHORT_TO_VICM_EN_ENABLE 0x1 +#define TIMPANI_TXFE3_ATEST_TXFE3_BYPASS_EN_S 6 +#define TIMPANI_TXFE3_ATEST_TXFE3_BYPASS_EN_M 0x40 +#define TIMPANI_TXFE3_ATEST_TXFE3_BYPASS_EN_DISABLE 0x0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_TXFE3_ATEST_TXFE3_BYPASS_EN_ENABLE 0x1 +#define TIMPANI_TXFE3_ATEST_TXFE3_CMOUT_ATEST_CONN_S 5 +#define TIMPANI_TXFE3_ATEST_TXFE3_CMOUT_ATEST_CONN_M 0x20 +#define TIMPANI_TXFE3_ATEST_TXFE3_CMOUT_ATEST_CONN_NO_CONNECT 0x0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_TXFE3_ATEST_TXFE3_CMOUT_ATEST_CONN_CONNECT 0x1 +#define TIMPANI_TXFE3_ATEST_TXFE3_OUT_ATEST_CONN_S 4 +#define TIMPANI_TXFE3_ATEST_TXFE3_OUT_ATEST_CONN_M 0x10 +#define TIMPANI_TXFE3_ATEST_TXFE3_OUT_ATEST_CONN_NO_CONNECT 0x0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_TXFE3_ATEST_TXFE3_OUT_ATEST_CONN_CONNECT 0x1 +#define TIMPANI_TXFE3_ATEST_TXFE4_OUT_SHORT_TO_VICM_EN_S 3 +#define TIMPANI_TXFE3_ATEST_TXFE4_OUT_SHORT_TO_VICM_EN_M 0x8 +#define TIMPANI_TXFE3_ATEST_TXFE4_OUT_SHORT_TO_VICM_EN_DISABLE 0x0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_TXFE3_ATEST_TXFE4_OUT_SHORT_TO_VICM_EN_ENABLE 0x1 +#define TIMPANI_TXFE3_ATEST_TXFE4_BYPASS_EN_S 2 +#define TIMPANI_TXFE3_ATEST_TXFE4_BYPASS_EN_M 0x4 +#define TIMPANI_TXFE3_ATEST_TXFE4_BYPASS_EN_DISABLE 0x0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_TXFE3_ATEST_TXFE4_BYPASS_EN_ENABLE 0x1 +#define TIMPANI_TXFE3_ATEST_TXFE4_CMOUT_ATEST_CONN_S 1 +#define TIMPANI_TXFE3_ATEST_TXFE4_CMOUT_ATEST_CONN_M 0x2 +#define TIMPANI_TXFE3_ATEST_TXFE4_CMOUT_ATEST_CONN_NO_CONNECT 0x0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_TXFE3_ATEST_TXFE4_CMOUT_ATEST_CONN_CONNECT 0x1 +#define TIMPANI_TXFE3_ATEST_TXFE4_OUT_ATEST_CONN_S 0 +#define TIMPANI_TXFE3_ATEST_TXFE4_OUT_ATEST_CONN_M 0x1 +#define TIMPANI_TXFE3_ATEST_TXFE4_OUT_ATEST_CONN_NO_CONNECT 0x0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_TXFE3_ATEST_TXFE4_OUT_ATEST_CONN_CONNECT 0x1 +#define TIMPANI_A_TXFE_DIFF_SE (0x1B) +#define TIMPANI_TXFE_DIFF_SE_RWC "RW" +#define TIMPANI_TXFE_DIFF_SE_POR 0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_TXFE_DIFF_SE_S 0 +#define TIMPANI_TXFE_DIFF_SE_M 0xFF +#define TIMPANI_TXFE_DIFF_SE_RESERVED_S 4 +#define TIMPANI_TXFE_DIFF_SE_RESERVED_M 0xF0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_TXFE_DIFF_SE_TXADC1_IN_MODE_S 3 +#define TIMPANI_TXFE_DIFF_SE_TXADC1_IN_MODE_M 0x8 +#define TIMPANI_TXFE_DIFF_SE_TXADC1_IN_MODE_DIFF 0x0 +#define TIMPANI_TXFE_DIFF_SE_TXADC1_IN_MODE_SINGLE_ENDED 0x1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_TXFE_DIFF_SE_TXADC2_IN_MODE_S 2 +#define TIMPANI_TXFE_DIFF_SE_TXADC2_IN_MODE_M 0x4 +#define TIMPANI_TXFE_DIFF_SE_TXADC2_IN_MODE_DIFF 0x0 +#define TIMPANI_TXFE_DIFF_SE_TXADC2_IN_MODE_SINGLE_ENDED 0x1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_TXFE_DIFF_SE_TXADC3_IN_MODE_S 1 +#define TIMPANI_TXFE_DIFF_SE_TXADC3_IN_MODE_M 0x2 +#define TIMPANI_TXFE_DIFF_SE_TXADC3_IN_MODE_DIFF 0x0 +#define TIMPANI_TXFE_DIFF_SE_TXADC3_IN_MODE_SINGLE_ENDED 0x1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_TXFE_DIFF_SE_TXADC4_IN_MODE_S 0 +#define TIMPANI_TXFE_DIFF_SE_TXADC4_IN_MODE_M 0x1 +#define TIMPANI_TXFE_DIFF_SE_TXADC4_IN_MODE_DIFF 0x0 +#define TIMPANI_TXFE_DIFF_SE_TXADC4_IN_MODE_SINGLE_ENDED 0x1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_A_CDAC_RX_CLK_CTL (0x20) +#define TIMPANI_CDAC_RX_CLK_CTL_RWC "RW" +#define TIMPANI_CDAC_RX_CLK_CTL_POR 0x98 +#define TIMPANI_CDAC_RX_CLK_CTL_S 0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDAC_RX_CLK_CTL_M 0xFF +#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_RESET_PULSE_GEN_EN_S 7 +#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_RESET_PULSE_GEN_EN_M 0x80 +#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_RESET_PULSE_GEN_EN_DISABLE 0x0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_RESET_PULSE_GEN_EN_ENABLE_NORMAL_OP 0x1 +#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_CTRL_EN_S 6 +#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_CTRL_EN_M 0x40 +#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_CTRL_EN_DISABLE_NORMAL_OP 0x0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_CTRL_EN_ENABLE 0x1 +#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_S 2 +#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_M 0x3C +#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_V_6NS 0x0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_V_8_4NS 0x1 +#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_V_10_8NS 0x2 +#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_V_13_2NS 0x3 +#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_V_15_6NS 0x4 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_V_18NS 0x5 +#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_V_20_4NS_NORMAL_OP 0x6 +#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_V_22_8NS 0x7 +#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_V_25_2NS 0x8 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_V_27_6NS 0x9 +#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_V_30NS 0xA +#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_V_32_4NS 0xB +#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_V_34_8NS 0xC +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_V_37_2NS 0xD +#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_V_39_6NS 0xE +#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_V_42NS 0xF +#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_FF_RESET_S 1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_FF_RESET_M 0x2 +#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_FF_RESET_ENABLE 0x1 +#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_FF_RESET_DISABLE 0x0 +#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_RESET_PULSE_GEN_ATEST_CONN_S 0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_RESET_PULSE_GEN_ATEST_CONN_M 0x1 +#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_RESET_PULSE_GEN_ATEST_CONN_NO_CONNECT 0x0 +#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_RESET_PULSE_GEN_ATEST_CONN_CONNECT 0x1 +#define TIMPANI_A_CDAC_BUFF_CTL (0x21) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDAC_BUFF_CTL_RWC "RW" +#define TIMPANI_CDAC_BUFF_CTL_POR 0x60 +#define TIMPANI_CDAC_BUFF_CTL_S 0 +#define TIMPANI_CDAC_BUFF_CTL_M 0xFF +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDAC_BUFF_CTL_CDAC_DM_BUFF_CUR_S 5 +#define TIMPANI_CDAC_BUFF_CTL_CDAC_DM_BUFF_CUR_M 0xE0 +#define TIMPANI_CDAC_BUFF_CTL_CDAC_DM_BUFF_CUR_V_40UA 0x0 +#define TIMPANI_CDAC_BUFF_CTL_CDAC_DM_BUFF_CUR_V_60UA_NORMAL_OP 0x1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDAC_BUFF_CTL_CDAC_DM_BUFF_CUR_V_80UA 0x2 +#define TIMPANI_CDAC_BUFF_CTL_CDAC_DM_BUFF_CUR_V_100UA 0x3 +#define TIMPANI_CDAC_BUFF_CTL_CDAC_DM_BUFF_CUR_V_120UA 0x4 +#define TIMPANI_CDAC_BUFF_CTL_CDAC_DM_BUFF_CUR_V_140UA 0x5 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDAC_BUFF_CTL_CDAC_DM_BUFF_CUR_V_160UA 0x6 +#define TIMPANI_CDAC_BUFF_CTL_CDAC_DM_BUFF_CUR_V_180UA 0x7 +#define TIMPANI_CDAC_BUFF_CTL_CDAC_CM_BUFF_CUR_S 3 +#define TIMPANI_CDAC_BUFF_CTL_CDAC_CM_BUFF_CUR_M 0x18 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDAC_BUFF_CTL_CDAC_CM_BUFF_CUR_V_20UA 0x0 +#define TIMPANI_CDAC_BUFF_CTL_CDAC_CM_BUFF_CUR_V_30UA_NORMAL_OP 0x1 +#define TIMPANI_CDAC_BUFF_CTL_CDAC_CM_BUFF_CUR_V_40UA 0x2 +#define TIMPANI_CDAC_BUFF_CTL_CDAC_CM_BUFF_CUR_V_50UA 0x3 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDAC_BUFF_CTL_CDAC_REF_BUFF_OTA_BIAS_CUR_S 1 +#define TIMPANI_CDAC_BUFF_CTL_CDAC_REF_BUFF_OTA_BIAS_CUR_M 0x6 +#define TIMPANI_CDAC_BUFF_CTL_CDAC_REF_BUFF_OTA_BIAS_CUR_V_5UA_5UA 0x0 +#define TIMPANI_CDAC_BUFF_CTL_CDAC_REF_BUFF_OTA_BIAS_CUR_V_5UA_10UA 0x1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDAC_BUFF_CTL_CDAC_REF_BUFF_OTA_BIAS_CUR_V_10UA_5UA 0x2 +#define TIMPANI_CDAC_BUFF_CTL_CDAC_REF_BUFF_OTA_BIAS_CUR_V_10UA_10UA 0x3 +#define TIMPANI_CDAC_BUFF_CTL_CDAC_VCOM_SOURCE_S 0 +#define TIMPANI_CDAC_BUFF_CTL_CDAC_VCOM_SOURCE_M 0x1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDAC_BUFF_CTL_CDAC_VCOM_SOURCE_CURRENT_TO_VCOM_NORMAL_OP 0x0 +#define TIMPANI_CDAC_BUFF_CTL_CDAC_VCOM_SOURCE_MASTER_BIAS_TO_VCOM 0x1 +#define TIMPANI_A_CDAC_REF_CTL1 (0x22) +#define TIMPANI_CDAC_REF_CTL1_RWC "RW" +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDAC_REF_CTL1_POR 0xe1 +#define TIMPANI_CDAC_REF_CTL1_S 0 +#define TIMPANI_CDAC_REF_CTL1_M 0xFF +#define TIMPANI_CDAC_REF_CTL1_CDAC_DACH_VOLT_S 5 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDAC_REF_CTL1_CDAC_DACH_VOLT_M 0xE0 +#define TIMPANI_CDAC_REF_CTL1_CDAC_DACH_VOLT_V_1_8V 0x0 +#define TIMPANI_CDAC_REF_CTL1_CDAC_DACH_VOLT_V_1_825V 0x1 +#define TIMPANI_CDAC_REF_CTL1_CDAC_DACH_VOLT_V_1_85V 0x2 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDAC_REF_CTL1_CDAC_DACH_VOLT_V_1_9V 0x3 +#define TIMPANI_CDAC_REF_CTL1_CDAC_DACH_VOLT_V_1_925V 0x4 +#define TIMPANI_CDAC_REF_CTL1_CDAC_DACH_VOLT_V_1_95V_NORMAL_OP 0x5 +#define TIMPANI_CDAC_REF_CTL1_CDAC_DACH_VOLT_V_1_975 0x6 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDAC_REF_CTL1_CDAC_DACH_VOLT_V_2_0V 0x7 +#define TIMPANI_CDAC_REF_CTL1_CDAC_DACL_VOLT_S 2 +#define TIMPANI_CDAC_REF_CTL1_CDAC_DACL_VOLT_M 0x1C +#define TIMPANI_CDAC_REF_CTL1_CDAC_DACL_VOLT_V_0_1V 0x0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDAC_REF_CTL1_CDAC_DACL_VOLT_V_0_125V 0x1 +#define TIMPANI_CDAC_REF_CTL1_CDAC_DACL_VOLT_V_0_15V_NORMAL_OP 0x2 +#define TIMPANI_CDAC_REF_CTL1_CDAC_DACL_VOLT_V_0_175V 0x3 +#define TIMPANI_CDAC_REF_CTL1_CDAC_DACL_VOLT_V_0_2V 0x4 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDAC_REF_CTL1_CDAC_DACL_VOLT_V_0_25V 0x5 +#define TIMPANI_CDAC_REF_CTL1_CDAC_DACL_VOLT_V_0_275V 0x6 +#define TIMPANI_CDAC_REF_CTL1_CDAC_DACL_VOLT_V_0_3V 0x7 +#define TIMPANI_CDAC_REF_CTL1_CDAC_CM_VOLT_S 0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDAC_REF_CTL1_CDAC_CM_VOLT_M 0x3 +#define TIMPANI_CDAC_REF_CTL1_CDAC_CM_VOLT_V_1_025V 0x0 +#define TIMPANI_CDAC_REF_CTL1_CDAC_CM_VOLT_V_1_05V_NORMAL_OP 0x1 +#define TIMPANI_CDAC_REF_CTL1_CDAC_CM_VOLT_V_1_075V 0x2 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDAC_REF_CTL1_CDAC_CM_VOLT_V_1_1V 0x3 +#define TIMPANI_A_IDAC_DWA_FIR_CTL (0x23) +#define TIMPANI_IDAC_DWA_FIR_CTL_RWC "RW" +#define TIMPANI_IDAC_DWA_FIR_CTL_POR 0x28 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_IDAC_DWA_FIR_CTL_S 0 +#define TIMPANI_IDAC_DWA_FIR_CTL_M 0xFF +#define TIMPANI_IDAC_DWA_FIR_CTL_IDAC_CLK_NON_OL_TIME_S 7 +#define TIMPANI_IDAC_DWA_FIR_CTL_IDAC_CLK_NON_OL_TIME_M 0x80 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_IDAC_DWA_FIR_CTL_IDAC_CLK_NON_OL_TIME_NORMAL_OP 0x0 +#define TIMPANI_IDAC_DWA_FIR_CTL_IDAC_CLK_NON_OL_TIME_V_150PSEC_REDUCTION 0x1 +#define TIMPANI_IDAC_DWA_FIR_CTL_IDAC_FIR_S 4 +#define TIMPANI_IDAC_DWA_FIR_CTL_IDAC_FIR_M 0x70 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_IDAC_DWA_FIR_CTL_IDAC_FIR_FIR0 0x0 +#define TIMPANI_IDAC_DWA_FIR_CTL_IDAC_FIR_FIR1 0x1 +#define TIMPANI_IDAC_DWA_FIR_CTL_IDAC_FIR_FIR2 0x2 +#define TIMPANI_IDAC_DWA_FIR_CTL_IDAC_FIR_FIR3 0x3 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_IDAC_DWA_FIR_CTL_IDAC_FIR_FIR4 0x4 +#define TIMPANI_IDAC_DWA_FIR_CTL_IDAC_EN_SOURCE_S 3 +#define TIMPANI_IDAC_DWA_FIR_CTL_IDAC_EN_SOURCE_M 0x8 +#define TIMPANI_IDAC_DWA_FIR_CTL_IDAC_EN_SOURCE_INTERNAL_NORMAL_OP 0x1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_IDAC_DWA_FIR_CTL_IDAC_EN_SOURCE_EXTERNAL 0x0 +#define TIMPANI_IDAC_DWA_FIR_CTL_RESERVED_S 0 +#define TIMPANI_IDAC_DWA_FIR_CTL_RESERVED_M 0x7 +#define TIMPANI_A_CDAC_REF_CTL2 (0x24) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDAC_REF_CTL2_RWC "RW" +#define TIMPANI_CDAC_REF_CTL2_POR 0xc +#define TIMPANI_CDAC_REF_CTL2_S 0 +#define TIMPANI_CDAC_REF_CTL2_M 0xFF +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDAC_REF_CTL2_RESERVED_1_S 7 +#define TIMPANI_CDAC_REF_CTL2_RESERVED_1_M 0x80 +#define TIMPANI_CDAC_REF_CTL2_CDAC_L_EN_S 6 +#define TIMPANI_CDAC_REF_CTL2_CDAC_L_EN_M 0x40 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDAC_REF_CTL2_CDAC_L_EN_DISABLE 0x0 +#define TIMPANI_CDAC_REF_CTL2_CDAC_L_EN_ENABLE 0x1 +#define TIMPANI_CDAC_REF_CTL2_CDAC_R_EN_S 5 +#define TIMPANI_CDAC_REF_CTL2_CDAC_R_EN_M 0x20 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDAC_REF_CTL2_CDAC_R_EN_DISABLE 0x0 +#define TIMPANI_CDAC_REF_CTL2_CDAC_R_EN_ENABLE 0x1 +#define TIMPANI_CDAC_REF_CTL2_RESERVED_2_S 4 +#define TIMPANI_CDAC_REF_CTL2_RESERVED_2_M 0x10 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDAC_REF_CTL2_CDAC_DWA_RX_FILTER_TIMING_S 2 +#define TIMPANI_CDAC_REF_CTL2_CDAC_DWA_RX_FILTER_TIMING_M 0xC +#define TIMPANI_CDAC_REF_CTL2_CDAC_DWA_RX_FILTER_TIMING_CLK_SYNC_CK11DBAR 0x1 +#define TIMPANI_CDAC_REF_CTL2_CDAC_DWA_RX_FILTER_TIMING_CLK_SYNC_CK21 0x3 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDAC_REF_CTL2_CDAC_OSR_S 0 +#define TIMPANI_CDAC_REF_CTL2_CDAC_OSR_M 0x3 +#define TIMPANI_CDAC_REF_CTL2_CDAC_OSR_V_256 0x0 +#define TIMPANI_CDAC_REF_CTL2_CDAC_OSR_V_128 0x1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDAC_REF_CTL2_CDAC_OSR_V_64 0x3 +#define TIMPANI_A_CDAC_CTL1 (0x25) +#define TIMPANI_CDAC_CTL1_RWC "RW" +#define TIMPANI_CDAC_CTL1_POR 0xb +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDAC_CTL1_S 0 +#define TIMPANI_CDAC_CTL1_M 0xFF +#define TIMPANI_CDAC_CTL1_RESERVED_S 6 +#define TIMPANI_CDAC_CTL1_RESERVED_M 0xC0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDAC_CTL1_CDAC_L_OUT_SHORT_EN_S 5 +#define TIMPANI_CDAC_CTL1_CDAC_L_OUT_SHORT_EN_M 0x20 +#define TIMPANI_CDAC_CTL1_CDAC_L_OUT_SHORT_EN_DISABLE 0x0 +#define TIMPANI_CDAC_CTL1_CDAC_L_OUT_SHORT_EN_ENABLE 0x1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDAC_CTL1_CDAC_R_OUT_SHORT_EN_S 4 +#define TIMPANI_CDAC_CTL1_CDAC_R_OUT_SHORT_EN_M 0x10 +#define TIMPANI_CDAC_CTL1_CDAC_R_OUT_SHORT_EN_DISABLE 0x0 +#define TIMPANI_CDAC_CTL1_CDAC_R_OUT_SHORT_EN_ENABLE 0x1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDAC_CTL1_CDAC_REF_RESISTOR_VOLT_S 2 +#define TIMPANI_CDAC_CTL1_CDAC_REF_RESISTOR_VOLT_M 0xC +#define TIMPANI_CDAC_CTL1_CDAC_REF_RESISTOR_VOLT_V_1_0V 0x0 +#define TIMPANI_CDAC_CTL1_CDAC_REF_RESISTOR_VOLT_V_1_025V 0x1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDAC_CTL1_CDAC_REF_RESISTOR_VOLT_V_1_05V_NORMAL_OP 0x2 +#define TIMPANI_CDAC_CTL1_CDAC_REF_RESISTOR_VOLT_V_1_0752V 0x3 +#define TIMPANI_CDAC_CTL1_CDAC_SAMP_CAP_RESET_EN_S 1 +#define TIMPANI_CDAC_CTL1_CDAC_SAMP_CAP_RESET_EN_M 0x2 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDAC_CTL1_CDAC_SAMP_CAP_RESET_EN_DISABLE 0x0 +#define TIMPANI_CDAC_CTL1_CDAC_SAMP_CAP_RESET_EN_ENABLE_NORMAL_OP 0x1 +#define TIMPANI_CDAC_CTL1_CDAC_RESET_SOURCE_S 0 +#define TIMPANI_CDAC_CTL1_CDAC_RESET_SOURCE_M 0x1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDAC_CTL1_CDAC_RESET_SOURCE_INTERNAL_NORMAL_OP 0x1 +#define TIMPANI_CDAC_CTL1_CDAC_RESET_SOURCE_EXTERNAL_REGISTER_RESET 0x0 +#define TIMPANI_A_CDAC_CTL2 (0x26) +#define TIMPANI_CDAC_CTL2_RWC "RW" +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDAC_CTL2_POR 0xd0 +#define TIMPANI_CDAC_CTL2_S 0 +#define TIMPANI_CDAC_CTL2_M 0xFF +#define TIMPANI_CDAC_CTL2_CDAC_OTA_BIAS_S 5 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDAC_CTL2_CDAC_OTA_BIAS_M 0xE0 +#define TIMPANI_CDAC_CTL2_CDAC_OTA_BIAS_V_10UA 0x0 +#define TIMPANI_CDAC_CTL2_CDAC_OTA_BIAS_V_8_75UA 0x1 +#define TIMPANI_CDAC_CTL2_CDAC_OTA_BIAS_V_7_5UA 0x2 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDAC_CTL2_CDAC_OTA_BIAS_V_6_25UA 0x3 +#define TIMPANI_CDAC_CTL2_CDAC_OTA_BIAS_V_5UA 0x4 +#define TIMPANI_CDAC_CTL2_CDAC_OTA_BIAS_V_3_75UA 0x5 +#define TIMPANI_CDAC_CTL2_CDAC_OTA_BIAS_V_2_5UA_NORMAL_OP 0x6 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDAC_CTL2_CDAC_OTA_BIAS_V_1_25UA 0x7 +#define TIMPANI_CDAC_CTL2_CDAC_REF_BUFF_OTA_BIAS_S 2 +#define TIMPANI_CDAC_CTL2_CDAC_REF_BUFF_OTA_BIAS_M 0x1C +#define TIMPANI_CDAC_CTL2_CDAC_REF_BUFF_OTA_BIAS_V_10UA 0x0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDAC_CTL2_CDAC_REF_BUFF_OTA_BIAS_V_8_75UA 0x1 +#define TIMPANI_CDAC_CTL2_CDAC_REF_BUFF_OTA_BIAS_V_7_5UA 0x2 +#define TIMPANI_CDAC_CTL2_CDAC_REF_BUFF_OTA_BIAS_V_6_25UA 0x3 +#define TIMPANI_CDAC_CTL2_CDAC_REF_BUFF_OTA_BIAS_V_5UA_NORMAL_OP 0x4 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDAC_CTL2_CDAC_REF_BUFF_OTA_BIAS_V_3_75UA 0x5 +#define TIMPANI_CDAC_CTL2_CDAC_REF_BUFF_OTA_BIAS_V_2_5UA 0x6 +#define TIMPANI_CDAC_CTL2_CDAC_REF_BUFF_OTA_BIAS_V_1_25UA 0x7 +#define TIMPANI_CDAC_CTL2_CDAC_RESET_PULSE_GEN_UPDATE_RATE_S 0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDAC_CTL2_CDAC_RESET_PULSE_GEN_UPDATE_RATE_M 0x3 +#define TIMPANI_CDAC_CTL2_CDAC_RESET_PULSE_GEN_UPDATE_RATE_FS 0x0 +#define TIMPANI_CDAC_CTL2_CDAC_RESET_PULSE_GEN_UPDATE_RATE_FS_BY_8 0x1 +#define TIMPANI_CDAC_CTL2_CDAC_RESET_PULSE_GEN_UPDATE_RATE_FS_BY_16 0x2 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_A_IDAC_L_CTL (0x28) +#define TIMPANI_IDAC_L_CTL_RWC "RW" +#define TIMPANI_IDAC_L_CTL_POR 0xe +#define TIMPANI_IDAC_L_CTL_S 0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_IDAC_L_CTL_M 0xFF +#define TIMPANI_IDAC_L_CTL_IDAC_L_EN_S 7 +#define TIMPANI_IDAC_L_CTL_IDAC_L_EN_M 0x80 +#define TIMPANI_IDAC_L_CTL_IDAC_L_EN_DISABLE 0x0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_IDAC_L_CTL_IDAC_L_EN_ENABLE 0x1 +#define TIMPANI_IDAC_L_CTL_IDAC_L_REF_SEL_S 5 +#define TIMPANI_IDAC_L_CTL_IDAC_L_REF_SEL_M 0x60 +#define TIMPANI_IDAC_L_CTL_IDAC_L_REF_SEL_GROUND 0x0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_IDAC_L_CTL_IDAC_L_REF_SEL_IBIAS_X_R_REF 0x1 +#define TIMPANI_IDAC_L_CTL_IDAC_L_REF_SEL_BG_VOLTAGE_NORMAL_OP 0x2 +#define TIMPANI_IDAC_L_CTL_IDAC_L_REF_SEL_VDD_BY_2 0x3 +#define TIMPANI_IDAC_L_CTL_IDAC_L_GAIN_S 3 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_IDAC_L_CTL_IDAC_L_GAIN_M 0x18 +#define TIMPANI_IDAC_L_CTL_IDAC_L_GAIN_NEG_1_5DB 0x0 +#define TIMPANI_IDAC_L_CTL_IDAC_L_GAIN_V_0_0DB_NORMAL_OP 0x1 +#define TIMPANI_IDAC_L_CTL_IDAC_L_GAIN_POS_1_5DB 0x2 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_IDAC_L_CTL_IDAC_L_GAIN_POS_3_0DB 0x3 +#define TIMPANI_IDAC_L_CTL_IDAC_L_LOW_RESISTANCE_S 2 +#define TIMPANI_IDAC_L_CTL_IDAC_L_LOW_RESISTANCE_M 0x4 +#define TIMPANI_IDAC_L_CTL_IDAC_L_LOW_RESISTANCE_V_30K 0x0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_IDAC_L_CTL_IDAC_L_LOW_RESISTANCE_V_10K_NORMAL_OP 0x1 +#define TIMPANI_IDAC_L_CTL_IDAC_L_SYNC_EN_S 1 +#define TIMPANI_IDAC_L_CTL_IDAC_L_SYNC_EN_M 0x2 +#define TIMPANI_IDAC_L_CTL_IDAC_L_SYNC_EN_ASYNCHRONOUSLY 0x0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_IDAC_L_CTL_IDAC_L_SYNC_EN_ENABLE_NORMAL_OP 0x1 +#define TIMPANI_IDAC_L_CTL_IDAC_L_REPLICA_BIAS_S 0 +#define TIMPANI_IDAC_L_CTL_IDAC_L_REPLICA_BIAS_M 0x1 +#define TIMPANI_IDAC_L_CTL_IDAC_L_REPLICA_BIAS_REPLICA_BIAS_NORMAL_OP 0x0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_IDAC_L_CTL_IDAC_L_REPLICA_BIAS_SERVO_LOOP_BIAS 0x1 +#define TIMPANI_A_IDAC_R_CTL (0x29) +#define TIMPANI_IDAC_R_CTL_RWC "RW" +#define TIMPANI_IDAC_R_CTL_POR 0xe +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_IDAC_R_CTL_S 0 +#define TIMPANI_IDAC_R_CTL_M 0xFF +#define TIMPANI_IDAC_R_CTL_IDAC_R_EN_S 7 +#define TIMPANI_IDAC_R_CTL_IDAC_R_EN_M 0x80 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_IDAC_R_CTL_IDAC_R_EN_DISABLED 0x0 +#define TIMPANI_IDAC_R_CTL_IDAC_R_EN_ENABLED 0x1 +#define TIMPANI_IDAC_R_CTL_IDAC_R_REF_SEL_S 5 +#define TIMPANI_IDAC_R_CTL_IDAC_R_REF_SEL_M 0x60 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_IDAC_R_CTL_IDAC_R_REF_SEL_GROUND 0x0 +#define TIMPANI_IDAC_R_CTL_IDAC_R_REF_SEL_IBIAS_X_R_REF 0x1 +#define TIMPANI_IDAC_R_CTL_IDAC_R_REF_SEL_BG_VOLTAGE_NORMAL_OP 0x2 +#define TIMPANI_IDAC_R_CTL_IDAC_R_REF_SEL_VDD_BY_2 0x3 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_IDAC_R_CTL_IDAC_R_GAIN_S 3 +#define TIMPANI_IDAC_R_CTL_IDAC_R_GAIN_M 0x18 +#define TIMPANI_IDAC_R_CTL_IDAC_R_GAIN_NEG_1_5DB 0x0 +#define TIMPANI_IDAC_R_CTL_IDAC_R_GAIN_V_0_0DB_NORMAL_OP 0x1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_IDAC_R_CTL_IDAC_R_GAIN_POS_1_5DB 0x2 +#define TIMPANI_IDAC_R_CTL_IDAC_R_GAIN_POS_3_0DB 0x3 +#define TIMPANI_IDAC_R_CTL_IDAC_R_LOW_RESISTANCE_S 2 +#define TIMPANI_IDAC_R_CTL_IDAC_R_LOW_RESISTANCE_M 0x4 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_IDAC_R_CTL_IDAC_R_LOW_RESISTANCE_V_30K 0x0 +#define TIMPANI_IDAC_R_CTL_IDAC_R_LOW_RESISTANCE_V_10K_NORMAL_OP 0x1 +#define TIMPANI_IDAC_R_CTL_IDAC_R_SYNC_EN_S 1 +#define TIMPANI_IDAC_R_CTL_IDAC_R_SYNC_EN_M 0x2 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_IDAC_R_CTL_IDAC_R_SYNC_EN_ASYNCHRONOUSLY 0x0 +#define TIMPANI_IDAC_R_CTL_IDAC_R_SYNC_EN_ENABLE_NORMAL_OP 0x1 +#define TIMPANI_IDAC_R_CTL_IDAC_R_REPLICA_BIAS_S 0 +#define TIMPANI_IDAC_R_CTL_IDAC_R_REPLICA_BIAS_M 0x1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_IDAC_R_CTL_IDAC_R_REPLICA_BIAS_REPLICA_BIAS_NORMAL_OP 0x0 +#define TIMPANI_IDAC_R_CTL_IDAC_R_REPLICA_BIAS_SERVO_LOOP_BIAS 0x1 +#define TIMPANI_A_PA_MASTER_BIAS (0x2D) +#define TIMPANI_PA_MASTER_BIAS_RWC "RW" +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_MASTER_BIAS_POR 0x6f +#define TIMPANI_PA_MASTER_BIAS_S 0 +#define TIMPANI_PA_MASTER_BIAS_M 0xFF +#define TIMPANI_PA_MASTER_BIAS_LINE_MASTER_BIAS_CUR_S 5 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_MASTER_BIAS_LINE_MASTER_BIAS_CUR_M 0xE0 +#define TIMPANI_PA_MASTER_BIAS_LINE_MASTER_BIAS_CUR_V_17_5UA 0x0 +#define TIMPANI_PA_MASTER_BIAS_LINE_MASTER_BIAS_CUR_V_15_0UA 0x1 +#define TIMPANI_PA_MASTER_BIAS_LINE_MASTER_BIAS_CUR_V_12_5UA 0x2 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_MASTER_BIAS_LINE_MASTER_BIAS_CUR_V_10_0UA 0x3 +#define TIMPANI_PA_MASTER_BIAS_LINE_MASTER_BIAS_CUR_V_7_5UA 0x4 +#define TIMPANI_PA_MASTER_BIAS_LINE_MASTER_BIAS_CUR_V_5_0UA 0x5 +#define TIMPANI_PA_MASTER_BIAS_LINE_MASTER_BIAS_CUR_V_2_5UA 0x6 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_MASTER_BIAS_LINE_MASTER_BIAS_CUR_V_0_0UA 0x7 +#define TIMPANI_PA_MASTER_BIAS_HPH_MASTER_BIAS_CUR_S 2 +#define TIMPANI_PA_MASTER_BIAS_HPH_MASTER_BIAS_CUR_M 0x1C +#define TIMPANI_PA_MASTER_BIAS_HPH_MASTER_BIAS_CUR_V_17_5UA 0x0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_MASTER_BIAS_HPH_MASTER_BIAS_CUR_V_15_0UA 0x1 +#define TIMPANI_PA_MASTER_BIAS_HPH_MASTER_BIAS_CUR_V_12_5UA 0x2 +#define TIMPANI_PA_MASTER_BIAS_HPH_MASTER_BIAS_CUR_V_10_0UA 0x3 +#define TIMPANI_PA_MASTER_BIAS_HPH_MASTER_BIAS_CUR_V_7_5UA 0x4 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_MASTER_BIAS_HPH_MASTER_BIAS_CUR_V_5_0UA 0x5 +#define TIMPANI_PA_MASTER_BIAS_HPH_MASTER_BIAS_CUR_V_2_5UA 0x6 +#define TIMPANI_PA_MASTER_BIAS_HPH_MASTER_BIAS_CUR_V_0_0UA 0x7 +#define TIMPANI_PA_MASTER_BIAS_CLASSD_REF_BUF_MASTER_BIAS_CUR_S 0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_MASTER_BIAS_CLASSD_REF_BUF_MASTER_BIAS_CUR_M 0x3 +#define TIMPANI_PA_MASTER_BIAS_CLASSD_REF_BUF_MASTER_BIAS_CUR_V_6_25UA 0x0 +#define TIMPANI_PA_MASTER_BIAS_CLASSD_REF_BUF_MASTER_BIAS_CUR_V_5_0UA 0x1 +#define TIMPANI_PA_MASTER_BIAS_CLASSD_REF_BUF_MASTER_BIAS_CUR_V_3_75UA 0x2 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_MASTER_BIAS_CLASSD_REF_BUF_MASTER_BIAS_CUR_V_2_5UA 0x3 +#define TIMPANI_A_PA_CLASSD_BIAS (0x2E) +#define TIMPANI_PA_CLASSD_BIAS_RWC "RW" +#define TIMPANI_PA_CLASSD_BIAS_POR 0x55 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_CLASSD_BIAS_S 0 +#define TIMPANI_PA_CLASSD_BIAS_M 0xFF +#define TIMPANI_PA_CLASSD_BIAS_CLASSD_COMP_BIAS_CUR_S 6 +#define TIMPANI_PA_CLASSD_BIAS_CLASSD_COMP_BIAS_CUR_M 0xC0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_CLASSD_BIAS_CLASSD_COMP_BIAS_CUR_V_6_25UA 0x0 +#define TIMPANI_PA_CLASSD_BIAS_CLASSD_COMP_BIAS_CUR_V_5_0UA 0x1 +#define TIMPANI_PA_CLASSD_BIAS_CLASSD_COMP_BIAS_CUR_V_3_75UA 0x2 +#define TIMPANI_PA_CLASSD_BIAS_CLASSD_COMP_BIAS_CUR_V_2_5UA 0x3 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_CLASSD_BIAS_CLASSD_OTA1_BIAS_CUR_S 4 +#define TIMPANI_PA_CLASSD_BIAS_CLASSD_OTA1_BIAS_CUR_M 0x30 +#define TIMPANI_PA_CLASSD_BIAS_CLASSD_OTA1_BIAS_CUR_V_6_25UA 0x0 +#define TIMPANI_PA_CLASSD_BIAS_CLASSD_OTA1_BIAS_CUR_V_5_0U 0x1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_CLASSD_BIAS_CLASSD_OTA1_BIAS_CUR_V_3_75UA 0x2 +#define TIMPANI_PA_CLASSD_BIAS_CLASSD_OTA1_BIAS_CUR_V_2_5UA 0x3 +#define TIMPANI_PA_CLASSD_BIAS_CLASSD_OTA2_BIAS_CUR_S 2 +#define TIMPANI_PA_CLASSD_BIAS_CLASSD_OTA2_BIAS_CUR_M 0xC +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_CLASSD_BIAS_CLASSD_OTA2_BIAS_CUR_V_6_25UA 0x0 +#define TIMPANI_PA_CLASSD_BIAS_CLASSD_OTA2_BIAS_CUR_V_5_0UA 0x1 +#define TIMPANI_PA_CLASSD_BIAS_CLASSD_OTA2_BIAS_CUR_V_3_75UA 0x2 +#define TIMPANI_PA_CLASSD_BIAS_CLASSD_OTA2_BIAS_CUR_V_2_5UA 0x3 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_CLASSD_BIAS_CLASSD_OCP_BIAS_CUR_S 0 +#define TIMPANI_PA_CLASSD_BIAS_CLASSD_OCP_BIAS_CUR_M 0x3 +#define TIMPANI_PA_CLASSD_BIAS_CLASSD_OCP_BIAS_CUR_V_6_25UA 0x0 +#define TIMPANI_PA_CLASSD_BIAS_CLASSD_OCP_BIAS_CUR_V_5_0UA 0x1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_CLASSD_BIAS_CLASSD_OCP_BIAS_CUR_V_3_75UA 0x2 +#define TIMPANI_PA_CLASSD_BIAS_CLASSD_OCP_BIAS_CUR_V_2_5UA 0x3 +#define TIMPANI_A_AUXPGA_CUR (0x2F) +#define TIMPANI_AUXPGA_CUR_RWC "RW" +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_AUXPGA_CUR_POR 0x44 +#define TIMPANI_AUXPGA_CUR_S 0 +#define TIMPANI_AUXPGA_CUR_M 0xFF +#define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_S 4 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_M 0xF0 +#define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_V_0UA 0x0 +#define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_V_0_3125UA 0x1 +#define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_V_0_625UA 0x2 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_V_0_9375UA 0x3 +#define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_V_1_25UA 0x4 +#define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_V_1_5625UA 0x5 +#define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_V_1_875UA 0x6 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_V_2_1875UA 0x7 +#define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_V_2_5UA 0x8 +#define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_V_2_8125UA 0x9 +#define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_V_3_125UA 0xA +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_V_3_4375UA 0xB +#define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_V_3_75UA 0xC +#define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_V_4_0625UA 0xD +#define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_V_4_375UA 0xE +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_V_4_6875UA 0xF +#define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_S 0 +#define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_M 0xF +#define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_V_0UA 0x0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_V_0_3125UA 0x1 +#define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_V_0_625UA 0x2 +#define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_V_0_9375UA 0x3 +#define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_V_1_25UA 0x4 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_V_1_5625UA 0x5 +#define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_V_1_875UA 0x6 +#define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_V_2_1875UA 0x7 +#define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_V_2_5UA 0x8 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_V_2_8125UA 0x9 +#define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_V_3_125UA 0xA +#define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_V_3_4375UA 0xB +#define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_V_3_75UA 0xC +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_V_4_0625UA 0xD +#define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_V_4_375UA 0xE +#define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_V_4_6875UA 0xF +#define TIMPANI_A_AUXPGA_CM (0x30) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_AUXPGA_CM_RWC "RW" +#define TIMPANI_AUXPGA_CM_POR 0x92 +#define TIMPANI_AUXPGA_CM_S 0 +#define TIMPANI_AUXPGA_CM_M 0xFF +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_AUXPGA_CM_AUXPGA_R_CM_DIFF_PAIR_TAIL_CUR_S 5 +#define TIMPANI_AUXPGA_CM_AUXPGA_R_CM_DIFF_PAIR_TAIL_CUR_M 0xE0 +#define TIMPANI_AUXPGA_CM_AUXPGA_R_CM_DIFF_PAIR_TAIL_CUR_V_7_5UA 0x0 +#define TIMPANI_AUXPGA_CM_AUXPGA_R_CM_DIFF_PAIR_TAIL_CUR_V_7_925UA 0x1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_AUXPGA_CM_AUXPGA_R_CM_DIFF_PAIR_TAIL_CUR_V_8_75UA 0x2 +#define TIMPANI_AUXPGA_CM_AUXPGA_R_CM_DIFF_PAIR_TAIL_CUR_V_9_375UA 0x3 +#define TIMPANI_AUXPGA_CM_AUXPGA_R_CM_DIFF_PAIR_TAIL_CUR_V_10UA 0x4 +#define TIMPANI_AUXPGA_CM_AUXPGA_R_CM_DIFF_PAIR_TAIL_CUR_V_10_625UA 0x5 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_AUXPGA_CM_AUXPGA_R_CM_DIFF_PAIR_TAIL_CUR_V_11_25UA 0x6 +#define TIMPANI_AUXPGA_CM_AUXPGA_R_CM_DIFF_PAIR_TAIL_CUR_V_11_875UA 0x7 +#define TIMPANI_AUXPGA_CM_AUXPGA_L_CM_DIFF_PAIR_TAIL_CUR_S 2 +#define TIMPANI_AUXPGA_CM_AUXPGA_L_CM_DIFF_PAIR_TAIL_CUR_M 0x1C +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_AUXPGA_CM_AUXPGA_L_CM_DIFF_PAIR_TAIL_CUR_V_7_5UA 0x0 +#define TIMPANI_AUXPGA_CM_AUXPGA_L_CM_DIFF_PAIR_TAIL_CUR_V_7_925UA 0x1 +#define TIMPANI_AUXPGA_CM_AUXPGA_L_CM_DIFF_PAIR_TAIL_CUR_V_8_75UA 0x2 +#define TIMPANI_AUXPGA_CM_AUXPGA_L_CM_DIFF_PAIR_TAIL_CUR_V_9_375UA 0x3 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_AUXPGA_CM_AUXPGA_L_CM_DIFF_PAIR_TAIL_CUR_V_10UA 0x4 +#define TIMPANI_AUXPGA_CM_AUXPGA_L_CM_DIFF_PAIR_TAIL_CUR_V_10_625UA 0x5 +#define TIMPANI_AUXPGA_CM_AUXPGA_L_CM_DIFF_PAIR_TAIL_CUR_V_11_25UA 0x6 +#define TIMPANI_AUXPGA_CM_AUXPGA_L_CM_DIFF_PAIR_TAIL_CUR_V_11_875UA 0x7 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_AUXPGA_CM_AUXPGA_R2R_CM_S 1 +#define TIMPANI_AUXPGA_CM_AUXPGA_R2R_CM_M 0x2 +#define TIMPANI_AUXPGA_CM_AUXPGA_R2R_CM_VCMI_TO_R2R_CM 0x1 +#define TIMPANI_AUXPGA_CM_AUXPGA_R2R_CM_R2R_CM_FLOATING 0x0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_AUXPGA_CM_AUXPGA_VCM_REF_GEN_S 0 +#define TIMPANI_AUXPGA_CM_AUXPGA_VCM_REF_GEN_M 0x1 +#define TIMPANI_AUXPGA_CM_AUXPGA_VCM_REF_GEN_GEN_VCM_LOCALLY 0x1 +#define TIMPANI_AUXPGA_CM_AUXPGA_VCM_REF_GEN_BG_VCM 0x0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_A_PA_HPH_EARPA_MSTB_EN (0x31) +#define TIMPANI_PA_HPH_EARPA_MSTB_EN_RWC "RW" +#define TIMPANI_PA_HPH_EARPA_MSTB_EN_POR 0x4 +#define TIMPANI_PA_HPH_EARPA_MSTB_EN_S 0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_HPH_EARPA_MSTB_EN_M 0xFF +#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_L_EN_S 7 +#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_L_EN_M 0x80 +#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_L_EN_ENABLE 0x1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_L_EN_DISABLE 0x0 +#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_L_BIAS_EN_S 6 +#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_L_BIAS_EN_M 0x40 +#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_L_BIAS_EN_ENABLE 0x1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_L_BIAS_EN_DISABLE 0x0 +#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_R_EN_S 5 +#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_R_EN_M 0x20 +#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_R_EN_ENABLE 0x1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_R_EN_DISABLE 0x0 +#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_R_BIAS_EN_S 4 +#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_R_BIAS_EN_M 0x10 +#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_R_BIAS_EN_ENABLE 0x1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_R_BIAS_EN_DISABLE 0x0 +#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_VCM_BUFFER_EN_S 3 +#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_VCM_BUFFER_EN_M 0x8 +#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_VCM_BUFFER_EN_ENABLE 0x1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_VCM_BUFFER_EN_DISABLE 0x0 +#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_CAPLESS_MODE_S 2 +#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_CAPLESS_MODE_M 0x4 +#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_CAPLESS_MODE_CAPLESS 0x1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_CAPLESS_MODE_LEGACY 0x0 +#define TIMPANI_PA_HPH_EARPA_MSTB_EN_EARPA_EN_S 1 +#define TIMPANI_PA_HPH_EARPA_MSTB_EN_EARPA_EN_M 0x2 +#define TIMPANI_PA_HPH_EARPA_MSTB_EN_EARPA_EN_ENABLE 0x1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_HPH_EARPA_MSTB_EN_EARPA_EN_DISABLE 0x0 +#define TIMPANI_PA_HPH_EARPA_MSTB_EN_PA_MASTER_BIAS_EN_S 0 +#define TIMPANI_PA_HPH_EARPA_MSTB_EN_PA_MASTER_BIAS_EN_M 0x1 +#define TIMPANI_PA_HPH_EARPA_MSTB_EN_PA_MASTER_BIAS_EN_ENABLE 0x1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_HPH_EARPA_MSTB_EN_PA_MASTER_BIAS_EN_DISABLE 0x0 +#define TIMPANI_A_PA_LINE_AUXO_EN (0x32) +#define TIMPANI_PA_LINE_AUXO_EN_RWC "RW" +#define TIMPANI_PA_LINE_AUXO_EN_POR 0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_LINE_AUXO_EN_S 0 +#define TIMPANI_PA_LINE_AUXO_EN_M 0xFF +#define TIMPANI_PA_LINE_AUXO_EN_LINE_L_EN_S 7 +#define TIMPANI_PA_LINE_AUXO_EN_LINE_L_EN_M 0x80 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_LINE_AUXO_EN_LINE_L_EN_ENABLE 0x1 +#define TIMPANI_PA_LINE_AUXO_EN_LINE_L_EN_DISABLE 0x0 +#define TIMPANI_PA_LINE_AUXO_EN_LINE_L_BIAS_EN_S 6 +#define TIMPANI_PA_LINE_AUXO_EN_LINE_L_BIAS_EN_M 0x40 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_LINE_AUXO_EN_LINE_L_BIAS_EN_ENABLE 0x1 +#define TIMPANI_PA_LINE_AUXO_EN_LINE_L_BIAS_EN_DISABLE 0x0 +#define TIMPANI_PA_LINE_AUXO_EN_LINE_R_EN_S 5 +#define TIMPANI_PA_LINE_AUXO_EN_LINE_R_EN_M 0x20 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_LINE_AUXO_EN_LINE_R_EN_ENABLE 0x1 +#define TIMPANI_PA_LINE_AUXO_EN_LINE_R_EN_DISABLE 0x0 +#define TIMPANI_PA_LINE_AUXO_EN_LINE_R_BIAS_EN_S 4 +#define TIMPANI_PA_LINE_AUXO_EN_LINE_R_BIAS_EN_M 0x10 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_LINE_AUXO_EN_LINE_R_BIAS_EN_ENABLE 0x1 +#define TIMPANI_PA_LINE_AUXO_EN_LINE_R_BIAS_EN_DISABLE 0x0 +#define TIMPANI_PA_LINE_AUXO_EN_LINE_VCM_BUFFER_EN_S 3 +#define TIMPANI_PA_LINE_AUXO_EN_LINE_VCM_BUFFER_EN_M 0x8 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_LINE_AUXO_EN_LINE_VCM_BUFFER_EN_ENABLE 0x1 +#define TIMPANI_PA_LINE_AUXO_EN_LINE_VCM_BUFFER_EN_DISABLE 0x0 +#define TIMPANI_PA_LINE_AUXO_EN_AUXOUT_EN_S 2 +#define TIMPANI_PA_LINE_AUXO_EN_AUXOUT_EN_M 0x4 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_LINE_AUXO_EN_AUXOUT_EN_ENABLE 0x1 +#define TIMPANI_PA_LINE_AUXO_EN_AUXOUT_EN_DISABLE 0x0 +#define TIMPANI_PA_LINE_AUXO_EN_AUXOUT_BIAS_EN_S 1 +#define TIMPANI_PA_LINE_AUXO_EN_AUXOUT_BIAS_EN_M 0x2 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_LINE_AUXO_EN_AUXOUT_BIAS_EN_ENABLE 0x1 +#define TIMPANI_PA_LINE_AUXO_EN_AUXOUT_BIAS_EN_DISABLE 0x0 +#define TIMPANI_PA_LINE_AUXO_EN_AUXOUT_VCM_BUFFER_EN_S 0 +#define TIMPANI_PA_LINE_AUXO_EN_AUXOUT_VCM_BUFFER_EN_M 0x1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_LINE_AUXO_EN_AUXOUT_VCM_BUFFER_EN_ENABLE 0x1 +#define TIMPANI_PA_LINE_AUXO_EN_AUXOUT_VCM_BUFFER_EN_DISABLE 0x0 +#define TIMPANI_A_PA_CLASSD_AUXPGA_EN (0x33) +#define TIMPANI_PA_CLASSD_AUXPGA_EN_RWC "RW" +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_CLASSD_AUXPGA_EN_POR 0 +#define TIMPANI_PA_CLASSD_AUXPGA_EN_S 0 +#define TIMPANI_PA_CLASSD_AUXPGA_EN_M 0xFF +#define TIMPANI_PA_CLASSD_AUXPGA_EN_AUXPGA_L_MUTE_S 7 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_CLASSD_AUXPGA_EN_AUXPGA_L_MUTE_M 0x80 +#define TIMPANI_PA_CLASSD_AUXPGA_EN_AUXPGA_L_MUTE_MUTE 0x1 +#define TIMPANI_PA_CLASSD_AUXPGA_EN_AUXPGA_L_MUTE_UNMUTE 0x0 +#define TIMPANI_PA_CLASSD_AUXPGA_EN_AUXPGA_R_MUTE_S 6 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_CLASSD_AUXPGA_EN_AUXPGA_R_MUTE_M 0x40 +#define TIMPANI_PA_CLASSD_AUXPGA_EN_AUXPGA_R_MUTE_MUTE 0x1 +#define TIMPANI_PA_CLASSD_AUXPGA_EN_AUXPGA_R_MUTE_UNMUTE 0x0 +#define TIMPANI_PA_CLASSD_AUXPGA_EN_AUXPGA_L_EN_S 5 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_CLASSD_AUXPGA_EN_AUXPGA_L_EN_M 0x20 +#define TIMPANI_PA_CLASSD_AUXPGA_EN_AUXPGA_L_EN_DISABLE 0x0 +#define TIMPANI_PA_CLASSD_AUXPGA_EN_AUXPGA_L_EN_ENABLE 0x1 +#define TIMPANI_PA_CLASSD_AUXPGA_EN_AUXPGA_R_EN_S 4 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_CLASSD_AUXPGA_EN_AUXPGA_R_EN_M 0x10 +#define TIMPANI_PA_CLASSD_AUXPGA_EN_AUXPGA_R_EN_DISABLE 0x0 +#define TIMPANI_PA_CLASSD_AUXPGA_EN_AUXPGA_R_EN_ENABLE 0x1 +#define TIMPANI_PA_CLASSD_AUXPGA_EN_CLASSD_L_REF_EN_S 3 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_CLASSD_AUXPGA_EN_CLASSD_L_REF_EN_M 0x8 +#define TIMPANI_PA_CLASSD_AUXPGA_EN_CLASSD_L_REF_EN_DISABLE 0x0 +#define TIMPANI_PA_CLASSD_AUXPGA_EN_CLASSD_L_REF_EN_ENABLE 0x1 +#define TIMPANI_PA_CLASSD_AUXPGA_EN_CLASSD_L_EN_S 2 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_CLASSD_AUXPGA_EN_CLASSD_L_EN_M 0x4 +#define TIMPANI_PA_CLASSD_AUXPGA_EN_CLASSD_L_EN_DISABLE 0x0 +#define TIMPANI_PA_CLASSD_AUXPGA_EN_CLASSD_L_EN_ENABLE 0x1 +#define TIMPANI_PA_CLASSD_AUXPGA_EN_CLASSD_R_REF_EN_S 1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_CLASSD_AUXPGA_EN_CLASSD_R_REF_EN_M 0x2 +#define TIMPANI_PA_CLASSD_AUXPGA_EN_CLASSD_R_REF_EN_DISABLE 0x0 +#define TIMPANI_PA_CLASSD_AUXPGA_EN_CLASSD_R_REF_EN_ENABLE 0x1 +#define TIMPANI_PA_CLASSD_AUXPGA_EN_CLASSD_R_EN_S 0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_CLASSD_AUXPGA_EN_CLASSD_R_EN_M 0x1 +#define TIMPANI_PA_CLASSD_AUXPGA_EN_CLASSD_R_EN_DISABLE 0x0 +#define TIMPANI_PA_CLASSD_AUXPGA_EN_CLASSD_R_EN_ENABLE 0x1 +#define TIMPANI_A_PA_LINE_L_GAIN (0x34) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_LINE_L_GAIN_RWC "RW" +#define TIMPANI_PA_LINE_L_GAIN_POR 0xac +#define TIMPANI_PA_LINE_L_GAIN_S 0 +#define TIMPANI_PA_LINE_L_GAIN_M 0xFF +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_S 2 +#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_M 0xFC +#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_POS_1_5 0x0 +#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_POS_0_0 0x1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_1_5 0x2 +#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_3_0 0x3 +#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_4_5 0x4 +#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_6_0 0x5 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_7_5 0x6 +#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_9_0 0x7 +#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_10_5 0x8 +#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_12_0 0x9 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_13_5 0xA +#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_15_0 0xB +#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_16_5 0xC +#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_18_0 0xD +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_19_5 0xE +#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_21_0 0xF +#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_22_5 0x10 +#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_24_0 0x11 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_25_5 0x12 +#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_27_0 0x13 +#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_28_5 0x14 +#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_30_0 0x15 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_31_5 0x16 +#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_33_0 0x17 +#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_34_5 0x18 +#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_36_0 0x19 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_37_5 0x1A +#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_39_0 0x1B +#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_40_5 0x1C +#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_42_0 0x1D +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_43_5 0x1E +#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_45_0 0x1F +#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_46_5 0x20 +#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_48_0 0x21 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_49_5 0x22 +#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_51_0 0x23 +#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_52_5 0x24 +#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_54_0 0x25 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_55_5 0x26 +#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_57_0 0x27 +#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_58_5 0x28 +#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_60_0 0x29 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_61_5 0x2A +#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_63_0 0x2B +#define TIMPANI_PA_LINE_L_GAIN_RESERVED_S 0 +#define TIMPANI_PA_LINE_L_GAIN_RESERVED_M 0x3 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_A_PA_LINE_R_GAIN (0x35) +#define TIMPANI_PA_LINE_R_GAIN_RWC "RW" +#define TIMPANI_PA_LINE_R_GAIN_POR 0xac +#define TIMPANI_PA_LINE_R_GAIN_S 0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_LINE_R_GAIN_M 0xFF +#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_S 2 +#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_M 0xFC +#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_POS_1_5 0x0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_POS_0_0 0x1 +#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_1_5 0x2 +#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_3_0 0x3 +#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_4_5 0x4 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_6_0 0x5 +#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_7_5 0x6 +#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_9_0 0x7 +#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_10_5 0x8 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_12_0 0x9 +#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_13_5 0xA +#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_15_0 0xB +#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_16_5 0xC +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_18_0 0xD +#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_19_5 0xE +#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_21_0 0xF +#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_22_5 0x10 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_24_0 0x11 +#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_25_5 0x12 +#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_27_0 0x13 +#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_28_5 0x14 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_30_0 0x15 +#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_31_5 0x16 +#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_33_0 0x17 +#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_34_5 0x18 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_36_0 0x19 +#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_37_5 0x1A +#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_39_0 0x1B +#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_40_5 0x1C +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_42_0 0x1D +#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_43_5 0x1E +#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_45_0 0x1F +#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_46_5 0x20 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_48_0 0x21 +#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_49_5 0x22 +#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_51_0 0x23 +#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_52_5 0x24 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_54_0 0x25 +#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_55_5 0x26 +#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_57_0 0x27 +#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_58_5 0x28 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_60_0 0x29 +#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_61_5 0x2A +#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_63_0 0x2B +#define TIMPANI_PA_LINE_R_GAIN_RESERVED_S 0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_LINE_R_GAIN_RESERVED_M 0x3 +#define TIMPANI_A_PA_HPH_L_GAIN (0x36) +#define TIMPANI_PA_HPH_L_GAIN_RWC "RW" +#define TIMPANI_PA_HPH_L_GAIN_POR 0xae +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_HPH_L_GAIN_S 0 +#define TIMPANI_PA_HPH_L_GAIN_M 0xFF +#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_S 2 +#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_M 0xFC +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_POS_1_5 0x0 +#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_POS_0_0 0x1 +#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_1_5 0x2 +#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_3_0 0x3 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_4_5 0x4 +#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_6_0 0x5 +#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_7_5 0x6 +#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_9_0 0x7 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_10_5 0x8 +#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_12_0 0x9 +#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_13_5 0xA +#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_15_0 0xB +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_16_5 0xC +#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_18_0 0xD +#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_19_5 0xE +#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_21_0 0xF +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_22_5 0x10 +#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_24_0 0x11 +#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_25_5 0x12 +#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_27_0 0x13 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_28_5 0x14 +#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_30_0 0x15 +#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_31_5 0x16 +#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_33_0 0x17 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_34_5 0x18 +#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_36_0 0x19 +#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_37_5 0x1A +#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_39_0 0x1B +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_40_5 0x1C +#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_42_0 0x1D +#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_43_5 0x1E +#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_45_0 0x1F +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_46_5 0x20 +#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_48_0 0x21 +#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_49_5 0x22 +#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_51_0 0x23 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_52_5 0x24 +#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_54_0 0x25 +#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_55_5 0x26 +#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_57_0 0x27 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_58_5 0x28 +#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_60_0 0x29 +#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_61_5 0x2A +#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_63_0 0x2B +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_HPH_L_GAIN_HPH_L_MUTE_S 1 +#define TIMPANI_PA_HPH_L_GAIN_HPH_L_MUTE_M 0x2 +#define TIMPANI_PA_HPH_L_GAIN_HPH_L_MUTE_MUTE 0x1 +#define TIMPANI_PA_HPH_L_GAIN_HPH_L_MUTE_UNMUTE 0x0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_HPH_L_GAIN_RESERVED_S 0 +#define TIMPANI_PA_HPH_L_GAIN_RESERVED_M 0x1 +#define TIMPANI_A_PA_HPH_R_GAIN (0x37) +#define TIMPANI_PA_HPH_R_GAIN_RWC "RW" +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_HPH_R_GAIN_POR 0xae +#define TIMPANI_PA_HPH_R_GAIN_S 0 +#define TIMPANI_PA_HPH_R_GAIN_M 0xFF +#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_S 2 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_M 0xFC +#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_POS_1_5 0x0 +#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_POS_0_0 0x1 +#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_1_5 0x2 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_3_0 0x3 +#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_4_5 0x4 +#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_6_0 0x5 +#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_7_5 0x6 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_9_0 0x7 +#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_10_5 0x8 +#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_12_0 0x9 +#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_13_5 0xA +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_15_0 0xB +#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_16_5 0xC +#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_18_0 0xD +#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_19_5 0xE +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_21_0 0xF +#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_22_5 0x10 +#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_24_0 0x11 +#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_25_5 0x12 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_27_0 0x13 +#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_28_5 0x14 +#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_30_0 0x15 +#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_31_5 0x16 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_33_0 0x17 +#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_34_5 0x18 +#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_36_0 0x19 +#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_37_5 0x1A +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_39_0 0x1B +#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_40_5 0x1C +#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_42_0 0x1D +#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_43_5 0x1E +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_45_0 0x1F +#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_46_5 0x20 +#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_48_0 0x21 +#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_49_5 0x22 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_51_0 0x23 +#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_52_5 0x24 +#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_54_0 0x25 +#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_55_5 0x26 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_57_0 0x27 +#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_58_5 0x28 +#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_60_0 0x29 +#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_61_5 0x2A +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_63_0 0x2B +#define TIMPANI_PA_HPH_R_GAIN_HPH_R_MUTE_S 1 +#define TIMPANI_PA_HPH_R_GAIN_HPH_R_MUTE_M 0x2 +#define TIMPANI_PA_HPH_R_GAIN_HPH_R_MUTE_MUTE 0x1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_HPH_R_GAIN_HPH_R_MUTE_UNMUTE 0x0 +#define TIMPANI_PA_HPH_R_GAIN_RESERVED_S 0 +#define TIMPANI_PA_HPH_R_GAIN_RESERVED_M 0x1 +#define TIMPANI_A_AUXPGA_LR_GAIN (0x38) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_AUXPGA_LR_GAIN_RWC "RW" +#define TIMPANI_AUXPGA_LR_GAIN_POR 0xaa +#define TIMPANI_AUXPGA_LR_GAIN_S 0 +#define TIMPANI_AUXPGA_LR_GAIN_M 0xFF +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_S 4 +#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_M 0xF0 +#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_NEG_30DB 0x0 +#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_NEG_27DB 0x1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_NEG_24DB 0x2 +#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_NEG_21DB 0x3 +#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_NEG_18DB 0x4 +#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_NEG_15DB 0x5 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_NEG_12DB 0x6 +#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_NEG_9_0DB 0x7 +#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_NEG_6_0DB 0x8 +#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_NEG_3_0DB 0x9 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_POS_0_0DB 0xA +#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_POS_3_0DB 0xB +#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_POS_6_0DB 0xC +#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_POS_9_0DB 0xD +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_POS_12_0DB_1 0xE +#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_POS_12_0DB_2 0xF +#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_S 0 +#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_M 0xF +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_NEG_30DB 0x0 +#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_NEG_27DB 0x1 +#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_NEG_24DB 0x2 +#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_NEG_21DB 0x3 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_NEG_18DB 0x4 +#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_NEG_15DB 0x5 +#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_NEG_12DB 0x6 +#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_NEG_9_0DB 0x7 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_NEG_6_0DB 0x8 +#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_NEG_3_0DB 0x9 +#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_POS_0_0DB 0xA +#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_POS_3_0DB 0xB +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_POS_6_0DB 0xC +#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_POS_9_0DB 0xD +#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_POS_12_0DB_1 0xE +#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_POS_12_0DB_2 0xF +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_A_PA_AUXO_EARPA_CONN (0x39) +#define TIMPANI_PA_AUXO_EARPA_CONN_RWC "RW" +#define TIMPANI_PA_AUXO_EARPA_CONN_POR 0 +#define TIMPANI_PA_AUXO_EARPA_CONN_S 0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_AUXO_EARPA_CONN_M 0xFF +#define TIMPANI_PA_AUXO_EARPA_CONN_AUXOUT_AUXPGA_L_CONN_S 7 +#define TIMPANI_PA_AUXO_EARPA_CONN_AUXOUT_AUXPGA_L_CONN_M 0x80 +#define TIMPANI_PA_AUXO_EARPA_CONN_AUXOUT_AUXPGA_L_CONN_NO_CONNECT 0x0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_AUXO_EARPA_CONN_AUXOUT_AUXPGA_L_CONN_CONNECT 0x1 +#define TIMPANI_PA_AUXO_EARPA_CONN_AUXOUT_IDAC_L_CONN_S 6 +#define TIMPANI_PA_AUXO_EARPA_CONN_AUXOUT_IDAC_L_CONN_M 0x40 +#define TIMPANI_PA_AUXO_EARPA_CONN_AUXOUT_IDAC_L_CONN_NO_CONNECT 0x0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_AUXO_EARPA_CONN_AUXOUT_IDAC_L_CONN_CONNECT 0x1 +#define TIMPANI_PA_AUXO_EARPA_CONN_AUXOUT_CDAC_L_CONN_S 5 +#define TIMPANI_PA_AUXO_EARPA_CONN_AUXOUT_CDAC_L_CONN_M 0x20 +#define TIMPANI_PA_AUXO_EARPA_CONN_AUXOUT_CDAC_L_CONN_NO_CONNECT 0x0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_AUXO_EARPA_CONN_AUXOUT_CDAC_L_CONN_CONNECT 0x1 +#define TIMPANI_PA_AUXO_EARPA_CONN_RESERVED_S 4 +#define TIMPANI_PA_AUXO_EARPA_CONN_RESERVED_M 0x10 +#define TIMPANI_PA_AUXO_EARPA_CONN_EARPA_GAIN_S 3 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_AUXO_EARPA_CONN_EARPA_GAIN_M 0x8 +#define TIMPANI_PA_AUXO_EARPA_CONN_EARPA_GAIN_V_3_52DB 0x1 +#define TIMPANI_PA_AUXO_EARPA_CONN_EARPA_GAIN_V_2_02DB 0x0 +#define TIMPANI_PA_AUXO_EARPA_CONN_EARPA_AUXPGA_L_CONN_S 2 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_AUXO_EARPA_CONN_EARPA_AUXPGA_L_CONN_M 0x4 +#define TIMPANI_PA_AUXO_EARPA_CONN_EARPA_AUXPGA_L_CONN_NO_CONNECT 0x0 +#define TIMPANI_PA_AUXO_EARPA_CONN_EARPA_AUXPGA_L_CONN_CONNECT 0x1 +#define TIMPANI_PA_AUXO_EARPA_CONN_EARPA_IDAC_L_CONN_S 1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_AUXO_EARPA_CONN_EARPA_IDAC_L_CONN_M 0x2 +#define TIMPANI_PA_AUXO_EARPA_CONN_EARPA_IDAC_L_CONN_NO_CONNECT 0x0 +#define TIMPANI_PA_AUXO_EARPA_CONN_EARPA_IDAC_L_CONN_CONNECT 0x1 +#define TIMPANI_PA_AUXO_EARPA_CONN_EARPA_CDAC_L_CONN_S 0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_AUXO_EARPA_CONN_EARPA_CDAC_L_CONN_M 0x1 +#define TIMPANI_PA_AUXO_EARPA_CONN_EARPA_CDAC_L_CONN_NO_CONNECT 0x0 +#define TIMPANI_PA_AUXO_EARPA_CONN_EARPA_CDAC_L_CONN_CONNECT 0x1 +#define TIMPANI_A_PA_LINE_ST_CONN (0x3A) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_LINE_ST_CONN_RWC "RW" +#define TIMPANI_PA_LINE_ST_CONN_POR 0 +#define TIMPANI_PA_LINE_ST_CONN_S 0 +#define TIMPANI_PA_LINE_ST_CONN_M 0xFF +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_LINE_ST_CONN_LINE_L_AUXPGA_L_CONN_S 7 +#define TIMPANI_PA_LINE_ST_CONN_LINE_L_AUXPGA_L_CONN_M 0x80 +#define TIMPANI_PA_LINE_ST_CONN_LINE_L_AUXPGA_L_CONN_NO_CONNECT 0x0 +#define TIMPANI_PA_LINE_ST_CONN_LINE_L_AUXPGA_L_CONN_CONNECT 0x1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_LINE_ST_CONN_LINE_L_IDAC_L_CONN_S 6 +#define TIMPANI_PA_LINE_ST_CONN_LINE_L_IDAC_L_CONN_M 0x40 +#define TIMPANI_PA_LINE_ST_CONN_LINE_L_IDAC_L_CONN_NO_CONNECT 0x0 +#define TIMPANI_PA_LINE_ST_CONN_LINE_L_IDAC_L_CONN_CONNECT 0x1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_LINE_ST_CONN_LINE_L_CDAC_L_CONN_S 5 +#define TIMPANI_PA_LINE_ST_CONN_LINE_L_CDAC_L_CONN_M 0x20 +#define TIMPANI_PA_LINE_ST_CONN_LINE_L_CDAC_L_CONN_NO_CONNECT 0x0 +#define TIMPANI_PA_LINE_ST_CONN_LINE_L_CDAC_L_CONN_CONNECT 0x1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_LINE_ST_CONN_LINE_R_AUXPGA_R_CONN_S 4 +#define TIMPANI_PA_LINE_ST_CONN_LINE_R_AUXPGA_R_CONN_M 0x10 +#define TIMPANI_PA_LINE_ST_CONN_LINE_R_AUXPGA_R_CONN_NO_CONNECT 0x0 +#define TIMPANI_PA_LINE_ST_CONN_LINE_R_AUXPGA_R_CONN_CONNECT 0x1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_LINE_ST_CONN_LINE_R_IDAC_R_CONN_S 3 +#define TIMPANI_PA_LINE_ST_CONN_LINE_R_IDAC_R_CONN_M 0x8 +#define TIMPANI_PA_LINE_ST_CONN_LINE_R_IDAC_R_CONN_NO_CONNECT 0x0 +#define TIMPANI_PA_LINE_ST_CONN_LINE_R_IDAC_R_CONN_CONNECT 0x1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_LINE_ST_CONN_LINE_R_CDAC_R_CONN_S 2 +#define TIMPANI_PA_LINE_ST_CONN_LINE_R_CDAC_R_CONN_M 0x4 +#define TIMPANI_PA_LINE_ST_CONN_LINE_R_CDAC_R_CONN_NO_CONNECT 0x0 +#define TIMPANI_PA_LINE_ST_CONN_LINE_R_CDAC_R_CONN_CONNECT 0x1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_LINE_ST_CONN_AUXPGA_L_VCM_ADD_CURR_S 0 +#define TIMPANI_PA_LINE_ST_CONN_AUXPGA_L_VCM_ADD_CURR_M 0x3 +#define TIMPANI_PA_LINE_ST_CONN_AUXPGA_L_VCM_ADD_CURR_NONE 0x0 +#define TIMPANI_PA_LINE_ST_CONN_AUXPGA_L_VCM_ADD_CURR_V_1_25UA 0x1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_LINE_ST_CONN_AUXPGA_L_VCM_ADD_CURR_V_2_5UA 0x2 +#define TIMPANI_PA_LINE_ST_CONN_AUXPGA_L_VCM_ADD_CURR_V_3_75UA 0x3 +#define TIMPANI_A_PA_LINE_MONO_CONN (0x3B) +#define TIMPANI_PA_LINE_MONO_CONN_RWC "RW" +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_LINE_MONO_CONN_POR 0 +#define TIMPANI_PA_LINE_MONO_CONN_S 0 +#define TIMPANI_PA_LINE_MONO_CONN_M 0xFF +#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_AUXPGA_L_CONN_S 7 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_AUXPGA_L_CONN_M 0x80 +#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_AUXPGA_L_CONN_NO_CONNECT 0x0 +#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_AUXPGA_L_CONN_CONNECT 0x1 +#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_IDAC_L_CONN_S 6 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_IDAC_L_CONN_M 0x40 +#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_IDAC_L_CONN_NO_CONNECT 0x0 +#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_IDAC_L_CONN_CONNECT 0x1 +#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_CDAC_L_CONN_S 5 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_CDAC_L_CONN_M 0x20 +#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_CDAC_L_CONN_NO_CONNECT 0x0 +#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_CDAC_L_CONN_CONNECT 0x1 +#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_AUXPGA_L_INV_CONN_S 4 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_AUXPGA_L_INV_CONN_M 0x10 +#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_AUXPGA_L_INV_CONN_NO_CONNECT 0x0 +#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_AUXPGA_L_INV_CONN_CONNECT 0x1 +#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_IDAC_L_INV_CONN_S 3 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_IDAC_L_INV_CONN_M 0x8 +#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_IDAC_L_INV_CONN_NO_CONNECT 0x0 +#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_IDAC_L_INV_CONN_CONNECT 0x1 +#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_CDAC_L_INV_CONN_S 2 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_CDAC_L_INV_CONN_M 0x4 +#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_CDAC_L_INV_CONN_NO_CONNECT 0x0 +#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_CDAC_L_INV_CONN_CONNECT 0x1 +#define TIMPANI_PA_LINE_MONO_CONN_AUXPGA_R_VCM_ADD_CURR_S 0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_LINE_MONO_CONN_AUXPGA_R_VCM_ADD_CURR_M 0x3 +#define TIMPANI_PA_LINE_MONO_CONN_AUXPGA_R_VCM_ADD_CURR_NONE 0x0 +#define TIMPANI_PA_LINE_MONO_CONN_AUXPGA_R_VCM_ADD_CURR_V_1_25UA 0x1 +#define TIMPANI_PA_LINE_MONO_CONN_AUXPGA_R_VCM_ADD_CURR_V_2_5UA 0x2 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_LINE_MONO_CONN_AUXPGA_R_VCM_ADD_CURR_V_3_75UA 0x3 +#define TIMPANI_A_PA_HPH_ST_CONN (0x3C) +#define TIMPANI_PA_HPH_ST_CONN_RWC "RW" +#define TIMPANI_PA_HPH_ST_CONN_POR 0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_HPH_ST_CONN_S 0 +#define TIMPANI_PA_HPH_ST_CONN_M 0xFF +#define TIMPANI_PA_HPH_ST_CONN_HPH_L_AUXPGA_L_CONN_S 7 +#define TIMPANI_PA_HPH_ST_CONN_HPH_L_AUXPGA_L_CONN_M 0x80 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_HPH_ST_CONN_HPH_L_AUXPGA_L_CONN_NO_CONNECT 0x0 +#define TIMPANI_PA_HPH_ST_CONN_HPH_L_AUXPGA_L_CONN_CONNECT 0x1 +#define TIMPANI_PA_HPH_ST_CONN_HPH_L_IDAC_L_CONN_S 6 +#define TIMPANI_PA_HPH_ST_CONN_HPH_L_IDAC_L_CONN_M 0x40 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_HPH_ST_CONN_HPH_L_IDAC_L_CONN_NO_CONNECT 0x0 +#define TIMPANI_PA_HPH_ST_CONN_HPH_L_IDAC_L_CONN_CONNECT 0x1 +#define TIMPANI_PA_HPH_ST_CONN_HPH_L_CDAC_L_CONN_S 5 +#define TIMPANI_PA_HPH_ST_CONN_HPH_L_CDAC_L_CONN_M 0x20 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_HPH_ST_CONN_HPH_L_CDAC_L_CONN_NO_CONNECT 0x0 +#define TIMPANI_PA_HPH_ST_CONN_HPH_L_CDAC_L_CONN_CONNECT 0x1 +#define TIMPANI_PA_HPH_ST_CONN_HPH_R_AUXPGA_R_CONN_S 4 +#define TIMPANI_PA_HPH_ST_CONN_HPH_R_AUXPGA_R_CONN_M 0x10 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_HPH_ST_CONN_HPH_R_AUXPGA_R_CONN_NO_CONNECT 0x0 +#define TIMPANI_PA_HPH_ST_CONN_HPH_R_AUXPGA_R_CONN_CONNECT 0x1 +#define TIMPANI_PA_HPH_ST_CONN_HPH_R_IDAC_R_CONN_S 3 +#define TIMPANI_PA_HPH_ST_CONN_HPH_R_IDAC_R_CONN_M 0x8 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_HPH_ST_CONN_HPH_R_IDAC_R_CONN_NO_CONNECT 0x0 +#define TIMPANI_PA_HPH_ST_CONN_HPH_R_IDAC_R_CONN_CONNECT 0x1 +#define TIMPANI_PA_HPH_ST_CONN_HPH_R_CDAC_R_CONN_S 2 +#define TIMPANI_PA_HPH_ST_CONN_HPH_R_CDAC_R_CONN_M 0x4 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_HPH_ST_CONN_HPH_R_CDAC_R_CONN_NO_CONNECT 0x0 +#define TIMPANI_PA_HPH_ST_CONN_HPH_R_CDAC_R_CONN_CONNECT 0x1 +#define TIMPANI_PA_HPH_ST_CONN_HPH_L_RAMP_GEN_EN_S 1 +#define TIMPANI_PA_HPH_ST_CONN_HPH_L_RAMP_GEN_EN_M 0x2 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_HPH_ST_CONN_HPH_L_RAMP_GEN_EN_DISABLE 0x1 +#define TIMPANI_PA_HPH_ST_CONN_HPH_L_RAMP_GEN_EN_ENABLE 0x0 +#define TIMPANI_PA_HPH_ST_CONN_HPH_R_RAMP_GEN_EN_S 0 +#define TIMPANI_PA_HPH_ST_CONN_HPH_R_RAMP_GEN_EN_M 0x1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_HPH_ST_CONN_HPH_R_RAMP_GEN_EN_DISABLE 0x1 +#define TIMPANI_PA_HPH_ST_CONN_HPH_R_RAMP_GEN_EN_ENABLE 0x0 +#define TIMPANI_A_PA_HPH_MONO_CONN (0x3D) +#define TIMPANI_PA_HPH_MONO_CONN_RWC "RW" +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_HPH_MONO_CONN_POR 0 +#define TIMPANI_PA_HPH_MONO_CONN_S 0 +#define TIMPANI_PA_HPH_MONO_CONN_M 0xFF +#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_AUXPGA_L_CONN_S 7 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_AUXPGA_L_CONN_M 0x80 +#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_AUXPGA_L_CONN_NO_CONNECT 0x0 +#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_AUXPGA_L_CONN_CONNECT 0x1 +#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_IDAC_L_CONN_S 6 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_IDAC_L_CONN_M 0x40 +#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_IDAC_L_CONN_NO_CONNECT 0x0 +#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_IDAC_L_CONN_CONNECT 0x1 +#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_CDAC_L_CONN_S 5 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_CDAC_L_CONN_M 0x20 +#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_CDAC_L_CONN_NO_CONNECT 0x0 +#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_CDAC_L_CONN_CONNECT 0x1 +#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_AUXPGA_L_INV_CONN_S 4 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_AUXPGA_L_INV_CONN_M 0x10 +#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_AUXPGA_L_INV_CONN_NO_CONNECT 0x0 +#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_AUXPGA_L_INV_CONN_CONNECT 0x1 +#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_IDAC_L_INV_CONN_S 3 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_IDAC_L_INV_CONN_M 0x8 +#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_IDAC_L_INV_CONN_NO_CONNECT 0x0 +#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_IDAC_L_INV_CONN_CONNECT 0x1 +#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_CDAC_L_INV_CONN_S 2 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_CDAC_L_INV_CONN_M 0x4 +#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_CDAC_L_INV_CONN_NO_CONNECT 0x0 +#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_CDAC_L_INV_CONN_CONNECT 0x1 +#define TIMPANI_PA_HPH_MONO_CONN_RESERVED_S 0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_HPH_MONO_CONN_RESERVED_M 0x3 +#define TIMPANI_A_PA_CLASSD_CONN (0x3E) +#define TIMPANI_PA_CLASSD_CONN_RWC "RW" +#define TIMPANI_PA_CLASSD_CONN_POR 0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_CLASSD_CONN_S 0 +#define TIMPANI_PA_CLASSD_CONN_M 0xFF +#define TIMPANI_PA_CLASSD_CONN_CLASSD_CDAC_CONN_S 7 +#define TIMPANI_PA_CLASSD_CONN_CLASSD_CDAC_CONN_M 0x80 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_CLASSD_CONN_CLASSD_CDAC_CONN_NO_CONNECT 0x0 +#define TIMPANI_PA_CLASSD_CONN_CLASSD_CDAC_CONN_CONNECT 0x1 +#define TIMPANI_PA_CLASSD_CONN_CLASSD_IDAC_CONN_S 6 +#define TIMPANI_PA_CLASSD_CONN_CLASSD_IDAC_CONN_M 0x40 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_CLASSD_CONN_CLASSD_IDAC_CONN_NO_CONNECT 0x0 +#define TIMPANI_PA_CLASSD_CONN_CLASSD_IDAC_CONN_CONNECT 0x1 +#define TIMPANI_PA_CLASSD_CONN_CLASSD_AUXPGA_CONN_S 5 +#define TIMPANI_PA_CLASSD_CONN_CLASSD_AUXPGA_CONN_M 0x20 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_CLASSD_CONN_CLASSD_AUXPGA_CONN_NO_CONNECT 0x0 +#define TIMPANI_PA_CLASSD_CONN_CLASSD_AUXPGA_CONN_CONNECT 0x1 +#define TIMPANI_PA_CLASSD_CONN_CLASSD_PA_MODE_S 4 +#define TIMPANI_PA_CLASSD_CONN_CLASSD_PA_MODE_M 0x10 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_CLASSD_CONN_CLASSD_PA_MODE_MONO_DIFF 0x1 +#define TIMPANI_PA_CLASSD_CONN_CLASSD_PA_MODE_STEREO 0x0 +#define TIMPANI_PA_CLASSD_CONN_RESERVED_S 0 +#define TIMPANI_PA_CLASSD_CONN_RESERVED_M 0xF +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_A_PA_CNP_CTL (0x3F) +#define TIMPANI_PA_CNP_CTL_RWC "RW" +#define TIMPANI_PA_CNP_CTL_POR 0x07 +#define TIMPANI_PA_CNP_CTL_S 0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_CNP_CTL_M 0xFF +#define TIMPANI_PA_CNP_CTL_CNP_RAMP_GEN_CURRENT_S 6 +#define TIMPANI_PA_CNP_CTL_CNP_RAMP_GEN_CURRENT_M 0xC0 +#define TIMPANI_PA_CNP_CTL_CNP_RAMP_GEN_CURRENT_V_1_75_NA 0x0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_CNP_CTL_CNP_RAMP_GEN_CURRENT_V_3_5_NA_NORMAL_OP 0x1 +#define TIMPANI_PA_CNP_CTL_CNP_RAMP_GEN_CURRENT_V_5_25_NA 0x2 +#define TIMPANI_PA_CNP_CTL_CNP_RAMP_GEN_CURRENT_V_10_NA 0x3 +#define TIMPANI_PA_CNP_CTL_RESERVED_S 4 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_CNP_CTL_RESERVED_M 0x30 +#define TIMPANI_PA_CNP_CTL_CLASSD_SUPPLY_DUMP_CIRCUIT_EN_S 3 +#define TIMPANI_PA_CNP_CTL_CLASSD_SUPPLY_DUMP_CIRCUIT_EN_M 0x8 +#define TIMPANI_PA_CNP_CTL_CLASSD_SUPPLY_DUMP_CIRCUIT_EN_DISABLE 0x0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_CNP_CTL_CLASSD_SUPPLY_DUMP_CIRCUIT_EN_ENABLE 0x1 +#define TIMPANI_PA_CNP_CTL_CLASSD_SUPPLY_DUMP_THRESH_S 0 +#define TIMPANI_PA_CNP_CTL_CLASSD_SUPPLY_DUMP_THRESH_M 0x7 +#define TIMPANI_PA_CNP_CTL_CLASSD_SUPPLY_DUMP_THRESH_V_2_220_V 0x0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_CNP_CTL_CLASSD_SUPPLY_DUMP_THRESH_V_2_243_V 0x1 +#define TIMPANI_PA_CNP_CTL_CLASSD_SUPPLY_DUMP_THRESH_V_2_266_V 0x2 +#define TIMPANI_PA_CNP_CTL_CLASSD_SUPPLY_DUMP_THRESH_V_2_290_V 0x3 +#define TIMPANI_PA_CNP_CTL_CLASSD_SUPPLY_DUMP_THRESH_V_2_341_V 0x4 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_CNP_CTL_CLASSD_SUPPLY_DUMP_THRESH_V_2_339_V 0x5 +#define TIMPANI_PA_CNP_CTL_CLASSD_SUPPLY_DUMP_THRESH_V_2_365_V 0x6 +#define TIMPANI_PA_CNP_CTL_CLASSD_SUPPLY_DUMP_THRESH_V_2_391_V 0x7 +#define TIMPANI_A_PA_CLASSD_L_CTL (0x40) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_CLASSD_L_CTL_RWC "RW" +#define TIMPANI_PA_CLASSD_L_CTL_POR 0x08 +#define TIMPANI_PA_CLASSD_L_CTL_S 0 +#define TIMPANI_PA_CLASSD_L_CTL_M 0xFF +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_CLASSD_L_CTL_RESERVED_S 6 +#define TIMPANI_PA_CLASSD_L_CTL_RESERVED_M 0xC0 +#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_LOGIC_RESET_S 5 +#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_LOGIC_RESET_M 0x20 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_LOGIC_RESET_NORMAL_OP 0x0 +#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_LOGIC_RESET_RESET_PA_LOGIC 0x1 +#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_INT_RESET_S 4 +#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_INT_RESET_M 0x10 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_INT_RESET_NORMAL_OP 0x0 +#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_INT_RESET_DISCHARGE_CAPS 0x1 +#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_REF_SEL_S 2 +#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_REF_SEL_M 0xC +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_REF_SEL_GND 0x0 +#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_REF_SEL_IBIAS_X_R_REF 0x1 +#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_REF_SEL_BG_VOLTAGE 0x2 +#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_REF_SEL_VDD_BY_2 0x3 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_PA_FORCE_1_S 1 +#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_PA_FORCE_1_M 0x2 +#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_PA_FORCE_1_NORMAL_OP 0x0 +#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_PA_FORCE_1_PA_OUT_TO_VDD 0x1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_PA_FORCE_0_S 0 +#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_PA_FORCE_0_M 0x1 +#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_PA_FORCE_0_NORMAL_OP 0x0 +#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_PA_FORCE_0_PA_OUT_TO_GND 0x1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_A_PA_CLASSD_R_CTL (0x41) +#define TIMPANI_PA_CLASSD_R_CTL_RWC "RW" +#define TIMPANI_PA_CLASSD_R_CTL_POR 0x08 +#define TIMPANI_PA_CLASSD_R_CTL_S 0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_CLASSD_R_CTL_M 0xFF +#define TIMPANI_PA_CLASSD_R_CTL_RESERVED_S 6 +#define TIMPANI_PA_CLASSD_R_CTL_RESERVED_M 0xC0 +#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_LOGIC_RESET_S 5 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_LOGIC_RESET_M 0x20 +#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_LOGIC_RESET_NORMAL_OP 0x0 +#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_LOGIC_RESET_RESET_PA_LOGIC 0x1 +#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_INT_RESET_S 4 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_INT_RESET_M 0x10 +#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_INT_RESET_NORMAL_OP 0x0 +#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_INT_RESET_DISCHARGE_CAPS 0x1 +#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_REF_SEL_S 2 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_REF_SEL_M 0xC +#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_REF_SEL_GND 0x0 +#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_REF_SEL_IBIAS_X_R_REF 0x1 +#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_REF_SEL_BG_VOLTAGE 0x2 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_REF_SEL_VDD_BY_2 0x3 +#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_PA_FORCE_1_S 1 +#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_PA_FORCE_1_M 0x2 +#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_PA_FORCE_1_NORMAL_OP 0x0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_PA_FORCE_1_PA_OUT_TO_VDD 0x1 +#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_PA_FORCE_0_S 0 +#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_PA_FORCE_0_M 0x1 +#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_PA_FORCE_0_NORMAL_OP 0x0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_PA_FORCE_0_PA_OUT_TO_GND 0x1 +#define TIMPANI_A_PA_CLASSD_INT2_CTL (0x42) +#define TIMPANI_PA_CLASSD_INT2_CTL_RWC "RW" +#define TIMPANI_PA_CLASSD_INT2_CTL_POR 0xb0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_CLASSD_INT2_CTL_S 0 +#define TIMPANI_PA_CLASSD_INT2_CTL_M 0xFF +#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_L_INT2_CFB_S 6 +#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_L_INT2_CFB_M 0xC0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_L_INT2_CFB_V_5_0PF 0x0 +#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_L_INT2_CFB_V_7_5PF 0x1 +#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_L_INT2_CFB_V_10PF 0x2 +#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_L_INT2_CFB_V_15PF 0x3 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_L_INT2_RIN_S 4 +#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_L_INT2_RIN_M 0x30 +#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_L_INT2_RIN_V_100K 0x0 +#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_L_INT2_RIN_V_150K 0x1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_L_INT2_RIN_V_175K 0x2 +#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_L_INT2_RIN_V_200K 0x3 +#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_R_INT2_CFB_S 2 +#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_R_INT2_CFB_M 0xC +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_R_INT2_CFB_V_5_0PF 0x0 +#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_R_INT2_CFB_V_7_5PF 0x1 +#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_R_INT2_CFB_V_10PF 0x2 +#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_R_INT2_CFB_V_15PF 0x3 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_R_INT2_RIN_S 0 +#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_R_INT2_RIN_M 0x3 +#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_R_INT2_RIN_V_100K 0x0 +#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_R_INT2_RIN_V_150K 0x1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_R_INT2_RIN_V_175K 0x2 +#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_R_INT2_RIN_V_200K 0x3 +#define TIMPANI_A_PA_HPH_L_OCP_CLK_CTL (0x43) +#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_RWC "RW" +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_POR 0xf2 +#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_S 0 +#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_M 0xFF +#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CARRIER_DIV_2_EN_S 7 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CARRIER_DIV_2_EN_M 0x80 +#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CARRIER_DIV_2_EN_ENABLE 0x1 +#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CARRIER_DIV_2_EN_DISABLE 0x0 +#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CARRIER_PROG_DIV_EN_S 6 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CARRIER_PROG_DIV_EN_M 0x40 +#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CARRIER_PROG_DIV_EN_ENABLE 0x1 +#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CARRIER_PROG_DIV_EN_DISABLE 0x0 +#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CARRIER_PROG_DIV_RATIO_S 4 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CARRIER_PROG_DIV_RATIO_M 0x30 +#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CARRIER_PROG_DIV_RATIO_DIV2 0x0 +#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CARRIER_PROG_DIV_RATIO_DIV4 0x1 +#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CARRIER_PROG_DIV_RATIO_DIV6 0x2 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CARRIER_PROG_DIV_RATIO_DIV8 0x3 +#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CLK_SEL_LEFT_S 3 +#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CLK_SEL_LEFT_M 0x8 +#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CLK_SEL_LEFT_CLK_FROM_CH_2 0x1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CLK_SEL_LEFT_CLK_FROM_CH_1 0x0 +#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_TIMER_DIV_2_EN_S 2 +#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_TIMER_DIV_2_EN_M 0x4 +#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_TIMER_DIV_2_EN_ENABLE 0x1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_TIMER_DIV_2_EN_DISABLE 0x0 +#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_TIMER_DIV_RATIO_S 0 +#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_TIMER_DIV_RATIO_M 0x3 +#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_TIMER_DIV_RATIO_DIV_BY_4 0x0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_TIMER_DIV_RATIO_DIV_BY_8 0x1 +#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_TIMER_DIV_RATIO_DIV_BY_12 0x2 +#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_TIMER_DIV_RATIO_DIV_BY_16 0x3 +#define TIMPANI_A_PA_CLASSD_L_SW_CTL (0x44) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_CLASSD_L_SW_CTL_RWC "RW" +#define TIMPANI_PA_CLASSD_L_SW_CTL_POR 0x37 +#define TIMPANI_PA_CLASSD_L_SW_CTL_S 0 +#define TIMPANI_PA_CLASSD_L_SW_CTL_M 0xFF +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_BREAK_BEFORE_MAKE_DELAY_S 6 +#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_BREAK_BEFORE_MAKE_DELAY_M 0xC0 +#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_BREAK_BEFORE_MAKE_DELAY_V_1 0x0 +#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_BREAK_BEFORE_MAKE_DELAY_V_2 0x1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_BREAK_BEFORE_MAKE_DELAY_V_3 0x2 +#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_BREAK_BEFORE_MAKE_DELAY_V_4 0x3 +#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_OUT_DRIVE_STREN_S 4 +#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_OUT_DRIVE_STREN_M 0x30 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_OUT_DRIVE_STREN_V_3_OF_6_UNITS 0x0 +#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_OUT_DRIVE_STREN_V_4_OF_6_UNITS 0x1 +#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_OUT_DRIVE_STREN_V_5_OF_6_UNITS 0x2 +#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_OUT_DRIVE_STREN_V_6_OF_6_UNITS 0x3 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_CLASSD_L_SW_CTL_RESERVED_S 3 +#define TIMPANI_PA_CLASSD_L_SW_CTL_RESERVED_M 0x8 +#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_CDAC_BYPASS_CAP_EN_S 2 +#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_CDAC_BYPASS_CAP_EN_M 0x4 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_CDAC_BYPASS_CAP_EN_DISABLE 0x0 +#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_CDAC_BYPASS_CAP_EN_ENABLE 0x1 +#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_CDAC_NON_OVERLAP_EN_S 1 +#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_CDAC_NON_OVERLAP_EN_M 0x2 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_CDAC_NON_OVERLAP_EN_DISABLE 0x0 +#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_CDAC_NON_OVERLAP_EN_ENABLE 0x1 +#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_CDAC_SWITCH_MODE_S 0 +#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_CDAC_SWITCH_MODE_M 0x1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_CDAC_SWITCH_MODE_POWER_GROUND 0x0 +#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_CDAC_SWITCH_MODE_RST_MIDPOINT 0x1 +#define TIMPANI_A_PA_CLASSD_L_OCP1 (0x45) +#define TIMPANI_PA_CLASSD_L_OCP1_RWC "RW" +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_CLASSD_L_OCP1_POR 0xff +#define TIMPANI_PA_CLASSD_L_OCP1_S 0 +#define TIMPANI_PA_CLASSD_L_OCP1_M 0xFF +#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_EN_S 7 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_EN_M 0x80 +#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_EN_DISABLE 0x0 +#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_EN_ENABLE 0x1 +#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_LOCK_S 6 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_LOCK_M 0x40 +#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_LOCK_NEVER_LOCKS 0x0 +#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_LOCK_LOCKS 0x1 +#define TIMPANI_PA_CLASSD_L_OCP1_OCP_CUR_THRESH_S 4 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_CLASSD_L_OCP1_OCP_CUR_THRESH_M 0x30 +#define TIMPANI_PA_CLASSD_L_OCP1_OCP_CUR_THRESH_V_100MA_83_3MA_66_7MA_50MA 0x0 +#define TIMPANI_PA_CLASSD_L_OCP1_OCP_CUR_THRESH_V_133MA_111MA_88_7MA_66_7MA 0x1 +#define TIMPANI_PA_CLASSD_L_OCP1_OCP_CUR_THRESH_V_166MA_138MA_111MA_83_3MA 0x2 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_CLASSD_L_OCP1_OCP_CUR_THRESH_V_200MA_166MA_133MA_100MA 0x3 +#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_NUM_CONN_ATTEMPTS_S 0 +#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_NUM_CONN_ATTEMPTS_M 0xF +#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_NUM_CONN_ATTEMPTS_V_1 0x1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_NUM_CONN_ATTEMPTS_V_2 0x2 +#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_NUM_CONN_ATTEMPTS_V_3 0x3 +#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_NUM_CONN_ATTEMPTS_V_4 0x4 +#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_NUM_CONN_ATTEMPTS_V_5 0x5 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_NUM_CONN_ATTEMPTS_V_6 0x6 +#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_NUM_CONN_ATTEMPTS_V_7 0x7 +#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_NUM_CONN_ATTEMPTS_V_8 0x8 +#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_NUM_CONN_ATTEMPTS_V_9 0x9 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_NUM_CONN_ATTEMPTS_V_10 0xA +#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_NUM_CONN_ATTEMPTS_V_11 0xB +#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_NUM_CONN_ATTEMPTS_V_12 0xC +#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_NUM_CONN_ATTEMPTS_V_13 0xD +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_NUM_CONN_ATTEMPTS_V_14 0xE +#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_NUM_CONN_ATTEMPTS_V_15 0xF +#define TIMPANI_A_PA_CLASSD_L_OCP2 (0x46) +#define TIMPANI_PA_CLASSD_L_OCP2_RWC "RW" +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_CLASSD_L_OCP2_POR 0x77 +#define TIMPANI_PA_CLASSD_L_OCP2_S 0 +#define TIMPANI_PA_CLASSD_L_OCP2_M 0xFF +#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_S 4 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_M 0xF0 +#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_V_255 0x0 +#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_V_511 0x1 +#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_V_767 0x2 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_V_1023 0x3 +#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_V_1279 0x4 +#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_V_1535 0x5 +#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_V_1791 0x6 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_V_2047 0x7 +#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_V_2303 0x8 +#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_V_2559 0x9 +#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_V_2815 0xA +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_V_3071 0xB +#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_V_3327 0xC +#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_V_3583 0xD +#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_V_3839 0xE +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_V_4095 0xF +#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_S 0 +#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_M 0xF +#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_V_255 0x0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_V_511 0x1 +#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_V_767 0x2 +#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_V_1023 0x3 +#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_V_1279 0x4 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_V_1535 0x5 +#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_V_1791 0x6 +#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_V_2047 0x7 +#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_V_2303 0x8 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_V_2559 0x9 +#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_V_2815 0xA +#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_V_3071 0xB +#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_V_3327 0xC +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_V_3583 0xD +#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_V_3839 0xE +#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_V_4095 0xF +#define TIMPANI_A_PA_HPH_R_OCP_CLK_CTL (0x47) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_RWC "RW" +#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_POR 0xf2 +#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_S 0 +#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_M 0xFF +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CARRIER_DIV_2_EN_S 7 +#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CARRIER_DIV_2_EN_M 0x80 +#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CARRIER_DIV_2_EN_ENABLE 0x1 +#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CARRIER_DIV_2_EN_DISABLE 0x0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CARRIER_PROG_DIV_EN_S 6 +#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CARRIER_PROG_DIV_EN_M 0x40 +#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CARRIER_PROG_DIV_EN_ENABLE 0x1 +#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CARRIER_PROG_DIV_EN_DISABLE 0x0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CARRIER_PROG_DIV_RATIO_S 4 +#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CARRIER_PROG_DIV_RATIO_M 0x30 +#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CARRIER_PROG_DIV_RATIO_DIV2 0x0 +#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CARRIER_PROG_DIV_RATIO_DIV4 0x1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CARRIER_PROG_DIV_RATIO_DIV6 0x2 +#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CARRIER_PROG_DIV_RATIO_DIV8 0x3 +#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CLK_SEL_RIGHT_S 3 +#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CLK_SEL_RIGHT_M 0x8 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CLK_SEL_RIGHT_CLK_FROM_CH_2 0x1 +#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CLK_SEL_RIGHT_CLK_FROM_CH_1 0x0 +#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_TIMER_DIV_2_EN_S 2 +#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_TIMER_DIV_2_EN_M 0x4 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_TIMER_DIV_2_EN_ENABLE 0x1 +#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_TIMER_DIV_2_EN_DISABLE 0x0 +#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_TIMER_DIV_RATIO_S 0 +#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_TIMER_DIV_RATIO_M 0x3 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_TIMER_DIV_RATIO_DIV_BY_4 0x0 +#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_TIMER_DIV_RATIO_DIV_BY_8 0x1 +#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_TIMER_DIV_RATIO_DIV_BY_12 0x2 +#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_TIMER_DIV_RATIO_DIV_BY_16 0x3 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_A_PA_CLASSD_R_SW_CTL (0x48) +#define TIMPANI_PA_CLASSD_R_SW_CTL_RWC "RW" +#define TIMPANI_PA_CLASSD_R_SW_CTL_POR 0x37 +#define TIMPANI_PA_CLASSD_R_SW_CTL_S 0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_CLASSD_R_SW_CTL_M 0xFF +#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_BREAK_BEFORE_MAKE_DELAY_S 6 +#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_BREAK_BEFORE_MAKE_DELAY_M 0xC0 +#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_BREAK_BEFORE_MAKE_DELAY_V_1 0x0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_BREAK_BEFORE_MAKE_DELAY_V_2 0x1 +#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_BREAK_BEFORE_MAKE_DELAY_V_3 0x2 +#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_BREAK_BEFORE_MAKE_DELAY_V_4 0x3 +#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_OUT_DRIVE_STREN_S 4 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_OUT_DRIVE_STREN_M 0x30 +#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_OUT_DRIVE_STREN_V_3_OF_6_UNITS 0x0 +#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_OUT_DRIVE_STREN_V_4_OF_6_UNITS 0x1 +#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_OUT_DRIVE_STREN_V_5_OF_6_UNITS 0x2 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_OUT_DRIVE_STREN_V_6_OF_6_UNITS 0x3 +#define TIMPANI_PA_CLASSD_R_SW_CTL_RESERVED_S 3 +#define TIMPANI_PA_CLASSD_R_SW_CTL_RESERVED_M 0x8 +#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_CDAC_BYPASS_CAP_EN_S 2 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_CDAC_BYPASS_CAP_EN_M 0x4 +#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_CDAC_BYPASS_CAP_EN_DISABLE 0x0 +#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_CDAC_BYPASS_CAP_EN_ENABLE 0x1 +#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_CDAC_NON_OVERLAP_EN_S 1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_CDAC_NON_OVERLAP_EN_M 0x2 +#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_CDAC_NON_OVERLAP_EN_DISABLE 0x0 +#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_CDAC_NON_OVERLAP_EN_ENABLE 0x1 +#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_CDAC_SWITCH_MODE_S 0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_CDAC_SWITCH_MODE_M 0x1 +#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_CDAC_SWITCH_MODE_POWER_GROUND 0x0 +#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_CDAC_SWITCH_MODE_RST_MIDPOINT 0x1 +#define TIMPANI_A_PA_CLASSD_R_OCP1 (0x49) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_CLASSD_R_OCP1_RWC "RW" +#define TIMPANI_PA_CLASSD_R_OCP1_POR 0xff +#define TIMPANI_PA_CLASSD_R_OCP1_S 0 +#define TIMPANI_PA_CLASSD_R_OCP1_M 0xFF +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_EN_S 7 +#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_EN_M 0x80 +#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_EN_DISABLE 0x0 +#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_EN_ENABLE 0x1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_LOCK_S 6 +#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_LOCK_M 0x40 +#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_LOCK_NEVER_LOCKS 0x0 +#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_LOCK_LOCKS 0x1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_CLASSD_R_OCP1_OCP_CUR_THRESH_S 4 +#define TIMPANI_PA_CLASSD_R_OCP1_OCP_CUR_THRESH_M 0x30 +#define TIMPANI_PA_CLASSD_R_OCP1_OCP_CUR_THRESH_V_100MA_83_3MA_66_7MA_50MA 0x0 +#define TIMPANI_PA_CLASSD_R_OCP1_OCP_CUR_THRESH_V_133MA_111MA_88_7MA_66_7MA 0x1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_CLASSD_R_OCP1_OCP_CUR_THRESH_V_166MA_138MA_111MA_83_3MA 0x2 +#define TIMPANI_PA_CLASSD_R_OCP1_OCP_CUR_THRESH_V_200MA_166MA_133MA_100MA 0x3 +#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_NUM_CONN_ATTEMPTS_S 0 +#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_NUM_CONN_ATTEMPTS_M 0xF +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_NUM_CONN_ATTEMPTS_V_1 0x1 +#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_NUM_CONN_ATTEMPTS_V_2 0x2 +#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_NUM_CONN_ATTEMPTS_V_3 0x3 +#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_NUM_CONN_ATTEMPTS_V_4 0x4 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_NUM_CONN_ATTEMPTS_V_5 0x5 +#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_NUM_CONN_ATTEMPTS_V_6 0x6 +#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_NUM_CONN_ATTEMPTS_V_7 0x7 +#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_NUM_CONN_ATTEMPTS_V_8 0x8 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_NUM_CONN_ATTEMPTS_V_9 0x9 +#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_NUM_CONN_ATTEMPTS_V_10 0xA +#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_NUM_CONN_ATTEMPTS_V_11 0xB +#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_NUM_CONN_ATTEMPTS_V_12 0xC +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_NUM_CONN_ATTEMPTS_V_13 0xD +#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_NUM_CONN_ATTEMPTS_V_14 0xE +#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_NUM_CONN_ATTEMPTS_V_15 0xF +#define TIMPANI_A_PA_CLASSD_R_OCP2 (0x4A) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_CLASSD_R_OCP2_RWC "RW" +#define TIMPANI_PA_CLASSD_R_OCP2_POR 0x77 +#define TIMPANI_PA_CLASSD_R_OCP2_S 0 +#define TIMPANI_PA_CLASSD_R_OCP2_M 0xFF +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_S 4 +#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_M 0xF0 +#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_V_255 0x0 +#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_V_511 0x1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_V_767 0x2 +#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_V_1023 0x3 +#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_V_1279 0x4 +#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_V_1535 0x5 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_V_1791 0x6 +#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_V_2047 0x7 +#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_V_2303 0x8 +#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_V_2559 0x9 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_V_2815 0xA +#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_V_3071 0xB +#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_V_3327 0xC +#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_V_3583 0xD +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_V_3839 0xE +#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_V_4095 0xF +#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_S 0 +#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_M 0xF +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_V_255 0x0 +#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_V_511 0x1 +#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_V_767 0x2 +#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_V_1023 0x3 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_V_1279 0x4 +#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_V_1535 0x5 +#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_V_1791 0x6 +#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_V_2047 0x7 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_V_2303 0x8 +#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_V_2559 0x9 +#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_V_2815 0xA +#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_V_3071 0xB +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_V_3327 0xC +#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_V_3583 0xD +#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_V_3839 0xE +#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_V_4095 0xF +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_A_PA_HPH_CTL1 (0x4B) +#define TIMPANI_PA_HPH_CTL1_RWC "RW" +#define TIMPANI_PA_HPH_CTL1_POR 0x44 +#define TIMPANI_PA_HPH_CTL1_S 0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_HPH_CTL1_M 0xFF +#define TIMPANI_PA_HPH_CTL1_HPH_GM3_BIAS_S 4 +#define TIMPANI_PA_HPH_CTL1_HPH_GM3_BIAS_M 0xF0 +#define TIMPANI_PA_HPH_CTL1_HPH_GM3_BIAS_V_400PER 0x1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_HPH_CTL1_HPH_GM3_BIAS_V_200PER 0x2 +#define TIMPANI_PA_HPH_CTL1_HPH_GM3_BIAS_V_133PER 0x3 +#define TIMPANI_PA_HPH_CTL1_HPH_GM3_BIAS_V_100PER 0x4 +#define TIMPANI_PA_HPH_CTL1_HPH_GM3_BIAS_V_66PER 0x6 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_HPH_CTL1_HPH_GM3_BIAS_V_50PER 0x8 +#define TIMPANI_PA_HPH_CTL1_HPH_GM3_BIAS_V_33PER 0xC +#define TIMPANI_PA_HPH_CTL1_HPH_SHORT_CIRCUIT_DET_EN_S 3 +#define TIMPANI_PA_HPH_CTL1_HPH_SHORT_CIRCUIT_DET_EN_M 0x8 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_HPH_CTL1_HPH_SHORT_CIRCUIT_DET_EN_DISABLE 0x0 +#define TIMPANI_PA_HPH_CTL1_HPH_SHORT_CIRCUIT_DET_EN_ENABLE 0x1 +#define TIMPANI_PA_HPH_CTL1_HPH_SHORT_CIRCUIT_CUR_LIMIT_S 0 +#define TIMPANI_PA_HPH_CTL1_HPH_SHORT_CIRCUIT_CUR_LIMIT_M 0x7 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_HPH_CTL1_HPH_SHORT_CIRCUIT_CUR_LIMIT_V_300MA 0x0 +#define TIMPANI_PA_HPH_CTL1_HPH_SHORT_CIRCUIT_CUR_LIMIT_V_350MA 0x2 +#define TIMPANI_PA_HPH_CTL1_HPH_SHORT_CIRCUIT_CUR_LIMIT_V_365MA 0x3 +#define TIMPANI_PA_HPH_CTL1_HPH_SHORT_CIRCUIT_CUR_LIMIT_V_150MA 0x4 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_HPH_CTL1_HPH_SHORT_CIRCUIT_CUR_LIMIT_V_190MA 0x6 +#define TIMPANI_PA_HPH_CTL1_HPH_SHORT_CIRCUIT_CUR_LIMIT_V_220MA 0x7 +#define TIMPANI_A_PA_HPH_CTL2 (0x4C) +#define TIMPANI_PA_HPH_CTL2_RWC "RW" +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_HPH_CTL2_POR 0xC8 +#define TIMPANI_PA_HPH_CTL2_S 0 +#define TIMPANI_PA_HPH_CTL2_M 0xFF +#define TIMPANI_PA_HPH_CTL2_HPH_SW_VNEG_CTL_S 7 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_HPH_CTL2_HPH_SW_VNEG_CTL_M 0x80 +#define TIMPANI_PA_HPH_CTL2_HPH_SW_VNEG_CTL_VNEG 0x1 +#define TIMPANI_PA_HPH_CTL2_HPH_SW_VNEG_CTL_VSS 0x0 +#define TIMPANI_PA_HPH_CTL2_HPH_VNEG_PS_GAIN_S 6 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_HPH_CTL2_HPH_VNEG_PS_GAIN_M 0x40 +#define TIMPANI_PA_HPH_CTL2_HPH_VNEG_PS_GAIN_V_1_5 0x1 +#define TIMPANI_PA_HPH_CTL2_HPH_VNEG_PS_GAIN_V_2_5 0x0 +#define TIMPANI_PA_HPH_CTL2_HPH_PS_FILTER_EN_S 5 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_HPH_CTL2_HPH_PS_FILTER_EN_M 0x20 +#define TIMPANI_PA_HPH_CTL2_HPH_PS_FILTER_EN_ENABLE 0x1 +#define TIMPANI_PA_HPH_CTL2_HPH_PS_FILTER_EN_DISABLE 0x0 +#define TIMPANI_PA_HPH_CTL2_HPH_OCP_EN_S 4 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_HPH_CTL2_HPH_OCP_EN_M 0x10 +#define TIMPANI_PA_HPH_CTL2_HPH_OCP_EN_ENABLE 0x1 +#define TIMPANI_PA_HPH_CTL2_HPH_OCP_EN_DISABLE 0x0 +#define TIMPANI_PA_HPH_CTL2_HPH_VREF_SEL_S 2 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_HPH_CTL2_HPH_VREF_SEL_M 0xC +#define TIMPANI_PA_HPH_CTL2_HPH_VREF_SEL_GROUND 0x0 +#define TIMPANI_PA_HPH_CTL2_HPH_VREF_SEL_IBIAS_ON_RESISTOR 0x1 +#define TIMPANI_PA_HPH_CTL2_HPH_VREF_SEL_BG 0x2 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_HPH_CTL2_HPH_VREF_SEL_AVDD_BY_2 0x3 +#define TIMPANI_PA_HPH_CTL2_HPH_OUT_SHUNT_EN_S 1 +#define TIMPANI_PA_HPH_CTL2_HPH_OUT_SHUNT_EN_M 0x2 +#define TIMPANI_PA_HPH_CTL2_HPH_OUT_SHUNT_EN_DISABLE 0x0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_HPH_CTL2_HPH_OUT_SHUNT_EN_ENABLE 0x1 +#define TIMPANI_PA_HPH_CTL2_RESERVED_S 0 +#define TIMPANI_PA_HPH_CTL2_RESERVED_M 0x1 +#define TIMPANI_A_PA_LINE_AUXO_CTL (0x4D) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_LINE_AUXO_CTL_RWC "RW" +#define TIMPANI_PA_LINE_AUXO_CTL_POR 0x2 +#define TIMPANI_PA_LINE_AUXO_CTL_S 0 +#define TIMPANI_PA_LINE_AUXO_CTL_M 0xFF +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_AUXO_RAMPGEN_CNT_S 6 +#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_AUXO_RAMPGEN_CNT_M 0xC0 +#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_AUXO_RAMPGEN_CNT_V_1_75NA 0x0 +#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_AUXO_RAMPGEN_CNT_V_3_5NA 0x1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_AUXO_RAMPGEN_CNT_V_5_25NA 0x2 +#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_AUXO_RAMPGEN_CNT_V_10NA 0x3 +#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_L_BIAS_CUR_S 4 +#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_L_BIAS_CUR_M 0x30 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_L_BIAS_CUR_V_60UA 0x0 +#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_L_BIAS_CUR_V_30UA_1 0x1 +#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_L_BIAS_CUR_V_30UA_2 0x2 +#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_L_BIAS_CUR_V_15UA 0x3 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_R_BIAS_CUR_S 2 +#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_R_BIAS_CUR_M 0xC +#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_R_BIAS_CUR_V_60UA 0x0 +#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_R_BIAS_CUR_V_30UA_1 0x1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_R_BIAS_CUR_V_30UA_2 0x2 +#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_R_BIAS_CUR_V_15UA 0x3 +#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_AUXO_CM_REF_SEL_S 0 +#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_AUXO_CM_REF_SEL_M 0x3 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_AUXO_CM_REF_SEL_VSSA 0x0 +#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_AUXO_CM_REF_SEL_BG 0x2 +#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_AUXO_CM_REF_SEL_VDDA_BY_2 0x3 +#define TIMPANI_A_PA_AUXO_EARPA_CTL (0x4E) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_AUXO_EARPA_CTL_RWC "RW" +#define TIMPANI_PA_AUXO_EARPA_CTL_POR 0xe +#define TIMPANI_PA_AUXO_EARPA_CTL_S 0 +#define TIMPANI_PA_AUXO_EARPA_CTL_M 0xFF +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_AUXO_EARPA_CTL_RESERVED_S 6 +#define TIMPANI_PA_AUXO_EARPA_CTL_RESERVED_M 0xC0 +#define TIMPANI_PA_AUXO_EARPA_CTL_AUXO_BIAS_CUR_S 4 +#define TIMPANI_PA_AUXO_EARPA_CTL_AUXO_BIAS_CUR_M 0x30 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_AUXO_EARPA_CTL_AUXO_BIAS_CUR_V_60UA 0x0 +#define TIMPANI_PA_AUXO_EARPA_CTL_AUXO_BIAS_CUR_V_30UA 0x1 +#define TIMPANI_PA_AUXO_EARPA_CTL_AUXO_BIAS_CUR_V_30UA_SAME_AS_01 0x2 +#define TIMPANI_PA_AUXO_EARPA_CTL_AUXO_BIAS_CUR_V_15UA 0x3 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_AUXO_EARPA_CTL_AUXO_GAIN_S 3 +#define TIMPANI_PA_AUXO_EARPA_CTL_AUXO_GAIN_M 0x8 +#define TIMPANI_PA_AUXO_EARPA_CTL_AUXO_GAIN_NEG_4_5DB 0x1 +#define TIMPANI_PA_AUXO_EARPA_CTL_AUXO_GAIN_NEG_3_0DB 0x0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_AUXO_EARPA_CTL_EARPA_MASTER_BIAS_CUR_S 1 +#define TIMPANI_PA_AUXO_EARPA_CTL_EARPA_MASTER_BIAS_CUR_M 0x6 +#define TIMPANI_PA_AUXO_EARPA_CTL_EARPA_MASTER_BIAS_CUR_V_12_5UA 0x0 +#define TIMPANI_PA_AUXO_EARPA_CTL_EARPA_MASTER_BIAS_CUR_V_10_0UA 0x1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_AUXO_EARPA_CTL_EARPA_MASTER_BIAS_CUR_V_7_5UA 0x2 +#define TIMPANI_PA_AUXO_EARPA_CTL_EARPA_MASTER_BIAS_CUR_V_5_0UA 0x3 +#define TIMPANI_PA_AUXO_EARPA_CTL_EARPA_VCM_SOURCE_S 0 +#define TIMPANI_PA_AUXO_EARPA_CTL_EARPA_VCM_SOURCE_M 0x1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_AUXO_EARPA_CTL_EARPA_VCM_SOURCE_BG 0x1 +#define TIMPANI_PA_AUXO_EARPA_CTL_EARPA_VCM_SOURCE_LOCAL_VCM 0x0 +#define TIMPANI_A_PA_EARO_CTL (0x4F) +#define TIMPANI_PA_EARO_CTL_RWC "RW" +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_EARO_CTL_POR 0x0 +#define TIMPANI_PA_EARO_CTL_S 0 +#define TIMPANI_PA_EARO_CTL_M 0xFF +#define TIMPANI_PA_EARO_CTL_EARPA_STARTUP_S 7 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_EARO_CTL_EARPA_STARTUP_M 0x80 +#define TIMPANI_PA_EARO_CTL_EARPA_STARTUP_NORMAL_OP 0x0 +#define TIMPANI_PA_EARO_CTL_EARPA_STARTUP_CONNECT_INPUTS_TO_GROUND 0x1 +#define TIMPANI_PA_EARO_CTL_EARPA_BYPASS_INPUT_CM_S 6 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_EARO_CTL_EARPA_BYPASS_INPUT_CM_M 0x40 +#define TIMPANI_PA_EARO_CTL_EARPA_BYPASS_INPUT_CM_NO_BYPASS 0x0 +#define TIMPANI_PA_EARO_CTL_EARPA_BYPASS_INPUT_CM_BYPASS 0x1 +#define TIMPANI_PA_EARO_CTL_EARPA_NMOS_BIAS_CUR_S 3 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_EARO_CTL_EARPA_NMOS_BIAS_CUR_M 0x38 +#define TIMPANI_PA_EARO_CTL_EARPA_NMOS_BIAS_CUR_V_213UA 0x0 +#define TIMPANI_PA_EARO_CTL_EARPA_NMOS_BIAS_CUR_V_280UA 0x1 +#define TIMPANI_PA_EARO_CTL_EARPA_NMOS_BIAS_CUR_V_408UA_1 0x2 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_EARO_CTL_EARPA_NMOS_BIAS_CUR_V_780UA_1 0x3 +#define TIMPANI_PA_EARO_CTL_EARPA_NMOS_BIAS_CUR_V_408UA_2 0x4 +#define TIMPANI_PA_EARO_CTL_EARPA_NMOS_BIAS_CUR_V_530UA 0x5 +#define TIMPANI_PA_EARO_CTL_EARPA_NMOS_BIAS_CUR_V_780UA_2 0x6 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_EARO_CTL_EARPA_NMOS_BIAS_CUR_V_1480UA 0x7 +#define TIMPANI_PA_EARO_CTL_EARPA_PMOS_BIAS_CUR_S 0 +#define TIMPANI_PA_EARO_CTL_EARPA_PMOS_BIAS_CUR_M 0x7 +#define TIMPANI_PA_EARO_CTL_EARPA_PMOS_BIAS_CUR_V_213UA 0x0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_EARO_CTL_EARPA_PMOS_BIAS_CUR_V_280UA 0x1 +#define TIMPANI_PA_EARO_CTL_EARPA_PMOS_BIAS_CUR_V_408UA_1 0x2 +#define TIMPANI_PA_EARO_CTL_EARPA_PMOS_BIAS_CUR_V_780UA_1 0x3 +#define TIMPANI_PA_EARO_CTL_EARPA_PMOS_BIAS_CUR_V_408UA_2 0x4 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_EARO_CTL_EARPA_PMOS_BIAS_CUR_V_530UA 0x5 +#define TIMPANI_PA_EARO_CTL_EARPA_PMOS_BIAS_CUR_V_780UA_2 0x6 +#define TIMPANI_PA_EARO_CTL_EARPA_PMOS_BIAS_CUR_V_1480UA 0x7 +#define TIMPANI_A_PA_MASTER_BIAS_CUR (0x50) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_MASTER_BIAS_CUR_RWC "RW" +#define TIMPANI_PA_MASTER_BIAS_CUR_POR 0xea +#define TIMPANI_PA_MASTER_BIAS_CUR_S 0 +#define TIMPANI_PA_MASTER_BIAS_CUR_M 0xFF +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_MASTER_BIAS_CUR_RAMPGEN_MASTER_BIAS_CUR_S 7 +#define TIMPANI_PA_MASTER_BIAS_CUR_RAMPGEN_MASTER_BIAS_CUR_M 0x80 +#define TIMPANI_PA_MASTER_BIAS_CUR_RAMPGEN_MASTER_BIAS_CUR_V_2_5UA 0x1 +#define TIMPANI_PA_MASTER_BIAS_CUR_RAMPGEN_MASTER_BIAS_CUR_V_5UA 0x0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_MASTER_BIAS_CUR_AUXPGA_BIAS_CUR_S 5 +#define TIMPANI_PA_MASTER_BIAS_CUR_AUXPGA_BIAS_CUR_M 0x60 +#define TIMPANI_PA_MASTER_BIAS_CUR_AUXPGA_BIAS_CUR_V_10UA 0x0 +#define TIMPANI_PA_MASTER_BIAS_CUR_AUXPGA_BIAS_CUR_V_7_5UA 0x1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_MASTER_BIAS_CUR_AUXPGA_BIAS_CUR_V_5_0UA 0x2 +#define TIMPANI_PA_MASTER_BIAS_CUR_AUXPGA_BIAS_CUR_V_2_5UA 0x3 +#define TIMPANI_PA_MASTER_BIAS_CUR_HPH_VCM_BUFF_BIAS_CURR_S 3 +#define TIMPANI_PA_MASTER_BIAS_CUR_HPH_VCM_BUFF_BIAS_CURR_M 0x18 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_MASTER_BIAS_CUR_HPH_VCM_BUFF_BIAS_CURR_V_6_25UA 0x0 +#define TIMPANI_PA_MASTER_BIAS_CUR_HPH_VCM_BUFF_BIAS_CURR_V_5_0UA 0x1 +#define TIMPANI_PA_MASTER_BIAS_CUR_HPH_VCM_BUFF_BIAS_CURR_V_3_75UA 0x2 +#define TIMPANI_PA_MASTER_BIAS_CUR_HPH_VCM_BUFF_BIAS_CURR_V_2_5UA 0x3 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_MASTER_BIAS_CUR_LINE_VCM_BUFF_BIAS_CURR_S 1 +#define TIMPANI_PA_MASTER_BIAS_CUR_LINE_VCM_BUFF_BIAS_CURR_M 0x6 +#define TIMPANI_PA_MASTER_BIAS_CUR_LINE_VCM_BUFF_BIAS_CURR_V_6_25UA 0x0 +#define TIMPANI_PA_MASTER_BIAS_CUR_LINE_VCM_BUFF_BIAS_CURR_V_5_0UA 0x1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_MASTER_BIAS_CUR_LINE_VCM_BUFF_BIAS_CURR_V_3_75UA 0x2 +#define TIMPANI_PA_MASTER_BIAS_CUR_LINE_VCM_BUFF_BIAS_CURR_V_2_5UA 0x3 +#define TIMPANI_PA_MASTER_BIAS_CUR_RESERVED_S 0 +#define TIMPANI_PA_MASTER_BIAS_CUR_RESERVED_M 0x1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_A_PA_CLASSD_SC_STATUS (0x51) +#define TIMPANI_PA_CLASSD_SC_STATUS_RWC "R" +#define TIMPANI_PA_CLASSD_SC_STATUS_POR 0 +#define TIMPANI_PA_CLASSD_SC_STATUS_S 0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_CLASSD_SC_STATUS_M 0xFF +#define TIMPANI_PA_CLASSD_SC_STATUS_CLASSD_L_SC_DET_S 7 +#define TIMPANI_PA_CLASSD_SC_STATUS_CLASSD_L_SC_DET_M 0x80 +#define TIMPANI_PA_CLASSD_SC_STATUS_CLASSD_L_SC_DET_NORMAL_OP 0x0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_CLASSD_SC_STATUS_CLASSD_L_SC_DET_SC_DET 0x1 +#define TIMPANI_PA_CLASSD_SC_STATUS_CLASSD_L_PWR_STAGE_HI_Z_S 6 +#define TIMPANI_PA_CLASSD_SC_STATUS_CLASSD_L_PWR_STAGE_HI_Z_M 0x40 +#define TIMPANI_PA_CLASSD_SC_STATUS_CLASSD_L_PWR_STAGE_HI_Z_NORMAL_OP 0x0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_CLASSD_SC_STATUS_CLASSD_L_PWR_STAGE_HI_Z_POWER_STAGE_OFF 0x1 +#define TIMPANI_PA_CLASSD_SC_STATUS_RESERVED_1_S 4 +#define TIMPANI_PA_CLASSD_SC_STATUS_RESERVED_1_M 0x30 +#define TIMPANI_PA_CLASSD_SC_STATUS_CLASSD_R_SC_DET_S 3 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_CLASSD_SC_STATUS_CLASSD_R_SC_DET_M 0x8 +#define TIMPANI_PA_CLASSD_SC_STATUS_CLASSD_R_SC_DET_NORMAL_OP 0x0 +#define TIMPANI_PA_CLASSD_SC_STATUS_CLASSD_R_SC_DET_SC_DET 0x1 +#define TIMPANI_PA_CLASSD_SC_STATUS_CLASSD_R_PWR_STAGE_HI_Z_S 2 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_CLASSD_SC_STATUS_CLASSD_R_PWR_STAGE_HI_Z_M 0x4 +#define TIMPANI_PA_CLASSD_SC_STATUS_CLASSD_R_PWR_STAGE_HI_Z_NORMAL_OP 0x0 +#define TIMPANI_PA_CLASSD_SC_STATUS_CLASSD_R_PWR_STAGE_HI_Z_POWER_STAGE_OFF 0x1 +#define TIMPANI_PA_CLASSD_SC_STATUS_RESERVED_2_S 1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_CLASSD_SC_STATUS_RESERVED_2_M 0x2 +#define TIMPANI_PA_CLASSD_SC_STATUS_RESERVED_S 0 +#define TIMPANI_PA_CLASSD_SC_STATUS_RESERVED_M 0x1 +#define TIMPANI_A_PA_HPH_SC_STATUS (0x52) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_HPH_SC_STATUS_RWC "R" +#define TIMPANI_PA_HPH_SC_STATUS_POR 0 +#define TIMPANI_PA_HPH_SC_STATUS_S 0 +#define TIMPANI_PA_HPH_SC_STATUS_M 0xFF +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_HPH_SC_STATUS_HPH_L_SC_DET_S 7 +#define TIMPANI_PA_HPH_SC_STATUS_HPH_L_SC_DET_M 0x80 +#define TIMPANI_PA_HPH_SC_STATUS_HPH_L_SC_DET_NORMAL_OP 0x0 +#define TIMPANI_PA_HPH_SC_STATUS_HPH_L_SC_DET_SC_DET 0x1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_HPH_SC_STATUS_RESERVED_1_S 4 +#define TIMPANI_PA_HPH_SC_STATUS_RESERVED_1_M 0x70 +#define TIMPANI_PA_HPH_SC_STATUS_HPH_R_SC_DET_S 3 +#define TIMPANI_PA_HPH_SC_STATUS_HPH_R_SC_DET_M 0x8 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_HPH_SC_STATUS_HPH_R_SC_DET_NORMAL_OP 0x0 +#define TIMPANI_PA_HPH_SC_STATUS_HPH_R_SC_DET_SC_DET 0x1 +#define TIMPANI_PA_HPH_SC_STATUS_RESERVED_2_S 2 +#define TIMPANI_PA_HPH_SC_STATUS_RESERVED_2_M 0x4 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_PA_HPH_SC_STATUS_RESERVED_S 0 +#define TIMPANI_PA_HPH_SC_STATUS_RESERVED_M 0x3 +#define TIMPANI_A_ATEST_EN (0x53) +#define TIMPANI_ATEST_EN_RWC "RW" +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_ATEST_EN_POR 0 +#define TIMPANI_ATEST_EN_S 0 +#define TIMPANI_ATEST_EN_M 0xFF +#define TIMPANI_ATEST_EN_ATEST_EN_S 7 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_ATEST_EN_ATEST_EN_M 0x80 +#define TIMPANI_ATEST_EN_ATEST_EN_DISABLE 0x0 +#define TIMPANI_ATEST_EN_ATEST_EN_ENABLE 0x1 +#define TIMPANI_ATEST_EN_RESERVED_S 0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_ATEST_EN_RESERVED_M 0x7F +#define TIMPANI_A_ATEST_TSHKADC (0x54) +#define TIMPANI_ATEST_TSHKADC_RWC "RW" +#define TIMPANI_ATEST_TSHKADC_POR 0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_ATEST_TSHKADC_S 0 +#define TIMPANI_ATEST_TSHKADC_M 0xFF +#define TIMPANI_ATEST_TSHKADC_RESERVED_S 4 +#define TIMPANI_ATEST_TSHKADC_RESERVED_M 0xF0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_ATEST_TSHKADC_ATEST_TSADC_AN_CONN_S 2 +#define TIMPANI_ATEST_TSHKADC_ATEST_TSADC_AN_CONN_M 0xC +#define TIMPANI_ATEST_TSHKADC_ATEST_TSADC_AN_CONN_NO_CONNECT 0x0 +#define TIMPANI_ATEST_TSHKADC_ATEST_TSADC_AN_CONN_MUX1 0x1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_ATEST_TSHKADC_ATEST_TSADC_AN_CONN_MUX2 0x2 +#define TIMPANI_ATEST_TSHKADC_ATEST_TSADC_AN_CONN_MUX3 0x3 +#define TIMPANI_ATEST_TSHKADC_ATEST_TSADC_DIG_CONN_S 0 +#define TIMPANI_ATEST_TSHKADC_ATEST_TSADC_DIG_CONN_M 0x3 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_ATEST_TSHKADC_ATEST_TSADC_DIG_CONN_NO_CONNECT 0x0 +#define TIMPANI_ATEST_TSHKADC_ATEST_TSADC_DIG_CONN_MUX1 0x1 +#define TIMPANI_ATEST_TSHKADC_ATEST_TSADC_DIG_CONN_MUX2 0x2 +#define TIMPANI_ATEST_TSHKADC_ATEST_TSADC_DIG_CONN_MUX3 0x3 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_A_ATEST_TXADC13 (0x55) +#define TIMPANI_ATEST_TXADC13_RWC "RW" +#define TIMPANI_ATEST_TXADC13_POR 0 +#define TIMPANI_ATEST_TXADC13_S 0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_ATEST_TXADC13_M 0xFF +#define TIMPANI_ATEST_TXADC13_RESERVED_S 7 +#define TIMPANI_ATEST_TXADC13_RESERVED_M 0x80 +#define TIMPANI_ATEST_TXADC13_ATEST_SEL_L_S 6 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_ATEST_TXADC13_ATEST_SEL_L_M 0x40 +#define TIMPANI_ATEST_TXADC13_ATEST_SEL_L_TXADC1 0x0 +#define TIMPANI_ATEST_TXADC13_ATEST_SEL_L_TXADC3 0x1 +#define TIMPANI_ATEST_TXADC13_ATEST1_TXADC13_CONN_S 3 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_ATEST_TXADC13_ATEST1_TXADC13_CONN_M 0x38 +#define TIMPANI_ATEST_TXADC13_ATEST1_TXADC13_CONN_NO_CONNECT 0x0 +#define TIMPANI_ATEST_TXADC13_ATEST1_TXADC13_CONN_ICMP1_TO_ATEST1 0x1 +#define TIMPANI_ATEST_TXADC13_ATEST1_TXADC13_CONN_IOTA2_TO_ATEST1 0x2 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_ATEST_TXADC13_ATEST1_TXADC13_CONN_IOTA1_TO_ATEST1 0x3 +#define TIMPANI_ATEST_TXADC13_ATEST1_TXADC13_CONN_VICM_TO_ATEST1 0x4 +#define TIMPANI_ATEST_TXADC13_ATEST1_TXADC13_CONN_VTH_P_TO_ATEST1 0x5 +#define TIMPANI_ATEST_TXADC13_ATEST1_TXADC13_CONN_VREFP_TO_ATEST1 0x6 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_ATEST_TXADC13_ATEST2_TXADC13_CONN_S 0 +#define TIMPANI_ATEST_TXADC13_ATEST2_TXADC13_CONN_M 0x7 +#define TIMPANI_ATEST_TXADC13_ATEST2_TXADC13_CONN_NO_CONNECT 0x0 +#define TIMPANI_ATEST_TXADC13_ATEST2_TXADC13_CONN_IDACREF_TO_ATEST2 0x1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_ATEST_TXADC13_ATEST2_TXADC13_CONN_IB_10U_TO_ATEST2 0x2 +#define TIMPANI_ATEST_TXADC13_ATEST2_TXADC13_CONN_VREFMID_TO_ATEST2 0x3 +#define TIMPANI_ATEST_TXADC13_ATEST2_TXADC13_CONN_VOCM_TO_ATEST2 0x4 +#define TIMPANI_ATEST_TXADC13_ATEST2_TXADC13_CONN_VTH_N_TO_ATEST2 0x5 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_ATEST_TXADC13_ATEST2_TXADC13_CONN_VREFN_TO_ATEST2 0x6 +#define TIMPANI_A_ATEST_TXADC24 (0x56) +#define TIMPANI_ATEST_TXADC24_RWC "RW" +#define TIMPANI_ATEST_TXADC24_POR 0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_ATEST_TXADC24_S 0 +#define TIMPANI_ATEST_TXADC24_M 0xFF +#define TIMPANI_ATEST_TXADC24_RESERVED_S 7 +#define TIMPANI_ATEST_TXADC24_RESERVED_M 0x80 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_ATEST_TXADC24_ATEST_SEL_R_S 6 +#define TIMPANI_ATEST_TXADC24_ATEST_SEL_R_M 0x40 +#define TIMPANI_ATEST_TXADC24_ATEST_SEL_R_TXADC1 0x0 +#define TIMPANI_ATEST_TXADC24_ATEST_SEL_R_TXADC3 0x1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_ATEST_TXADC24_ATEST1_TXADC24_CONN_S 3 +#define TIMPANI_ATEST_TXADC24_ATEST1_TXADC24_CONN_M 0x38 +#define TIMPANI_ATEST_TXADC24_ATEST1_TXADC24_CONN_NO_CONNECT 0x0 +#define TIMPANI_ATEST_TXADC24_ATEST1_TXADC24_CONN_ICMP1_TO_ATEST1 0x1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_ATEST_TXADC24_ATEST1_TXADC24_CONN_IOTA2_TO_ATEST1 0x2 +#define TIMPANI_ATEST_TXADC24_ATEST1_TXADC24_CONN_IOTA1_TO_ATEST1 0x3 +#define TIMPANI_ATEST_TXADC24_ATEST1_TXADC24_CONN_VICM_TO_ATEST1 0x4 +#define TIMPANI_ATEST_TXADC24_ATEST1_TXADC24_CONN_VTH_P_TO_ATEST1 0x5 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_ATEST_TXADC24_ATEST1_TXADC24_CONN_VREFP_TO_ATEST1 0x6 +#define TIMPANI_ATEST_TXADC24_ATEST2_TXADC24_CONN_S 0 +#define TIMPANI_ATEST_TXADC24_ATEST2_TXADC24_CONN_M 0x7 +#define TIMPANI_ATEST_TXADC24_ATEST2_TXADC24_CONN_NO_CONNECT 0x0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_ATEST_TXADC24_ATEST2_TXADC24_CONN_IDACREF_TO_ATEST2 0x1 +#define TIMPANI_ATEST_TXADC24_ATEST2_TXADC24_CONN_IB_10U_TO_ATEST2 0x2 +#define TIMPANI_ATEST_TXADC24_ATEST2_TXADC24_CONN_VREFMID_TO_ATEST2 0x3 +#define TIMPANI_ATEST_TXADC24_ATEST2_TXADC24_CONN_VOCM_TO_ATEST2 0x4 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_ATEST_TXADC24_ATEST2_TXADC24_CONN_VTH_N_TO_ATEST2 0x5 +#define TIMPANI_ATEST_TXADC24_ATEST2_TXADC24_CONN_VREFN_TO_ATEST2 0x6 +#define TIMPANI_A_ATEST_AUXPGA (0x57) +#define TIMPANI_ATEST_AUXPGA_RWC "RW" +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_ATEST_AUXPGA_POR 0 +#define TIMPANI_ATEST_AUXPGA_S 0 +#define TIMPANI_ATEST_AUXPGA_M 0xFF +#define TIMPANI_ATEST_AUXPGA_ATEST1_AUXPGA_INT_VCM_CONN_S 7 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_ATEST_AUXPGA_ATEST1_AUXPGA_INT_VCM_CONN_M 0x80 +#define TIMPANI_ATEST_AUXPGA_ATEST1_AUXPGA_INT_VCM_CONN_NO_CONNECT 0x0 +#define TIMPANI_ATEST_AUXPGA_ATEST1_AUXPGA_INT_VCM_CONN_CONNECT 0x1 +#define TIMPANI_ATEST_AUXPGA_ATEST_AUXPGA_VCMI_VDD_CONN_S 6 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_ATEST_AUXPGA_ATEST_AUXPGA_VCMI_VDD_CONN_M 0x40 +#define TIMPANI_ATEST_AUXPGA_ATEST_AUXPGA_VCMI_VDD_CONN_NO_CONNECT 0x0 +#define TIMPANI_ATEST_AUXPGA_ATEST_AUXPGA_VCMI_VDD_CONN_CONNECT 0x1 +#define TIMPANI_ATEST_AUXPGA_ATEST_AUXPGA_VCMO_R_L_CONN_S 5 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_ATEST_AUXPGA_ATEST_AUXPGA_VCMO_R_L_CONN_M 0x20 +#define TIMPANI_ATEST_AUXPGA_ATEST_AUXPGA_VCMO_R_L_CONN_NO_CONNECT 0x0 +#define TIMPANI_ATEST_AUXPGA_ATEST_AUXPGA_VCMO_R_L_CONN_CONNECT 0x1 +#define TIMPANI_ATEST_AUXPGA_ATEST_AUXPGA_R_CONN_S 4 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_ATEST_AUXPGA_ATEST_AUXPGA_R_CONN_M 0x10 +#define TIMPANI_ATEST_AUXPGA_ATEST_AUXPGA_R_CONN_NO_CONNECT 0x0 +#define TIMPANI_ATEST_AUXPGA_ATEST_AUXPGA_R_CONN_CONNECT 0x1 +#define TIMPANI_ATEST_AUXPGA_ATEST_AUXPGA_L_CONN_S 3 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_ATEST_AUXPGA_ATEST_AUXPGA_L_CONN_M 0x8 +#define TIMPANI_ATEST_AUXPGA_ATEST_AUXPGA_L_CONN_NO_CONNECT 0x0 +#define TIMPANI_ATEST_AUXPGA_ATEST_AUXPGA_L_CONN_CONNECT 0x1 +#define TIMPANI_ATEST_AUXPGA_RESERVED_S 0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_ATEST_AUXPGA_RESERVED_M 0x7 +#define TIMPANI_A_ATEST_CDAC (0x58) +#define TIMPANI_ATEST_CDAC_RWC "RW" +#define TIMPANI_ATEST_CDAC_POR 0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_ATEST_CDAC_S 0 +#define TIMPANI_ATEST_CDAC_M 0xFF +#define TIMPANI_ATEST_CDAC_ATEST_CDAC_DWA_IN_CONN_S 7 +#define TIMPANI_ATEST_CDAC_ATEST_CDAC_DWA_IN_CONN_M 0x80 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_ATEST_CDAC_ATEST_CDAC_DWA_IN_CONN_NO_CONNECT 0x0 +#define TIMPANI_ATEST_CDAC_ATEST_CDAC_DWA_IN_CONN_CONNECT 0x1 +#define TIMPANI_ATEST_CDAC_ATEST_CDAC_DWA_OUT_CONN_S 6 +#define TIMPANI_ATEST_CDAC_ATEST_CDAC_DWA_OUT_CONN_M 0x40 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_ATEST_CDAC_ATEST_CDAC_DWA_OUT_CONN_NO_CONNECT 0x0 +#define TIMPANI_ATEST_CDAC_ATEST_CDAC_DWA_OUT_CONN_CONNECT 0x1 +#define TIMPANI_ATEST_CDAC_ATEST_FILTER_L_OUT_CONN_S 5 +#define TIMPANI_ATEST_CDAC_ATEST_FILTER_L_OUT_CONN_M 0x20 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_ATEST_CDAC_ATEST_FILTER_L_OUT_CONN_NO_CONNECT 0x0 +#define TIMPANI_ATEST_CDAC_ATEST_FILTER_L_OUT_CONN_CONNECT 0x1 +#define TIMPANI_ATEST_CDAC_ATEST_FILTER_R_OUT_CONN_S 4 +#define TIMPANI_ATEST_CDAC_ATEST_FILTER_R_OUT_CONN_M 0x10 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_ATEST_CDAC_ATEST_FILTER_R_OUT_CONN_NO_CONNECT 0x0 +#define TIMPANI_ATEST_CDAC_ATEST_FILTER_R_OUT_CONN_CONNECT 0x1 +#define TIMPANI_ATEST_CDAC_ATEST_CDAC_L_CONN_S 2 +#define TIMPANI_ATEST_CDAC_ATEST_CDAC_L_CONN_M 0xC +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_ATEST_CDAC_ATEST_CDAC_L_CONN_NO_CONNECT 0x0 +#define TIMPANI_ATEST_CDAC_ATEST_CDAC_L_CONN_TEST1 0x1 +#define TIMPANI_ATEST_CDAC_ATEST_CDAC_L_CONN_TEST2 0x2 +#define TIMPANI_ATEST_CDAC_ATEST_CDAC_L_CONN_TEST3 0x3 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_ATEST_CDAC_ATEST_CDAC_R_CONN_S 0 +#define TIMPANI_ATEST_CDAC_ATEST_CDAC_R_CONN_M 0x3 +#define TIMPANI_ATEST_CDAC_ATEST_CDAC_R_CONN_NO_CONNECT 0x0 +#define TIMPANI_ATEST_CDAC_ATEST_CDAC_R_CONN_TEST1 0x1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_ATEST_CDAC_ATEST_CDAC_R_CONN_TEST2 0x2 +#define TIMPANI_ATEST_CDAC_ATEST_CDAC_R_CONN_TEST3 0x3 +#define TIMPANI_A_ATEST_IDAC (0x59) +#define TIMPANI_ATEST_IDAC_RWC "RW" +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_ATEST_IDAC_POR 0 +#define TIMPANI_ATEST_IDAC_S 0 +#define TIMPANI_ATEST_IDAC_M 0xFF +#define TIMPANI_ATEST_IDAC_ATEST1_LR_CONN_S 7 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_ATEST_IDAC_ATEST1_LR_CONN_M 0x80 +#define TIMPANI_ATEST_IDAC_ATEST1_LR_CONN_RIGHT 0x1 +#define TIMPANI_ATEST_IDAC_ATEST1_LR_CONN_LEFT 0x0 +#define TIMPANI_ATEST_IDAC_ATEST1_CONN_S 4 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_ATEST_IDAC_ATEST1_CONN_M 0x70 +#define TIMPANI_ATEST_IDAC_ATEST1_CONN_IDAC_NEG_OUT 0x7 +#define TIMPANI_ATEST_IDAC_ATEST1_CONN_CT_FILTER_POS_OUT 0x6 +#define TIMPANI_ATEST_IDAC_ATEST1_CONN_CT_FILTER_IBIAS 0x5 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_ATEST_IDAC_ATEST1_CONN_NO_CONNECT_1 0x4 +#define TIMPANI_ATEST_IDAC_ATEST1_CONN_NO_CONNECT_2 0x3 +#define TIMPANI_ATEST_IDAC_ATEST1_CONN_NO_CONNECT_3 0x2 +#define TIMPANI_ATEST_IDAC_ATEST1_CONN_NO_CONNECT_4 0x1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_ATEST_IDAC_ATEST1_CONN_NO_CONNECT_5 0x0 +#define TIMPANI_ATEST_IDAC_ATEST2_LR_CONN_S 3 +#define TIMPANI_ATEST_IDAC_ATEST2_LR_CONN_M 0x8 +#define TIMPANI_ATEST_IDAC_ATEST2_LR_CONN_RIGHT 0x1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_ATEST_IDAC_ATEST2_LR_CONN_LEFT 0x0 +#define TIMPANI_ATEST_IDAC_ATEST2_CONN_S 0 +#define TIMPANI_ATEST_IDAC_ATEST2_CONN_M 0x7 +#define TIMPANI_ATEST_IDAC_ATEST2_CONN_IDAC_POS_OUT 0x7 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_ATEST_IDAC_ATEST2_CONN_CT_FILTER_NEG_OUT 0x6 +#define TIMPANI_ATEST_IDAC_ATEST2_CONN_IDAC_IBIAS 0x5 +#define TIMPANI_ATEST_IDAC_ATEST2_CONN_NO_CONNECT_1 0x4 +#define TIMPANI_ATEST_IDAC_ATEST2_CONN_NO_CONNECT_2 0x3 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_ATEST_IDAC_ATEST2_CONN_NO_CONNECT_3 0x2 +#define TIMPANI_ATEST_IDAC_ATEST2_CONN_NO_CONNECT_4 0x1 +#define TIMPANI_ATEST_IDAC_ATEST2_CONN_NO_CONNECT_5 0x0 +#define TIMPANI_A_ATEST_PA1 (0x5A) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_ATEST_PA1_RWC "RW" +#define TIMPANI_ATEST_PA1_POR 0 +#define TIMPANI_ATEST_PA1_S 0 +#define TIMPANI_ATEST_PA1_M 0xFF +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_ATEST_PA1_ATEST_EARPA_FSV_NP_CONN_S 7 +#define TIMPANI_ATEST_PA1_ATEST_EARPA_FSV_NP_CONN_M 0x80 +#define TIMPANI_ATEST_PA1_ATEST_EARPA_FSV_NP_CONN_NO_CONNECT 0x0 +#define TIMPANI_ATEST_PA1_ATEST_EARPA_FSV_NP_CONN_EN 0x1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_ATEST_PA1_ATEST_EARPA_NCASC_NMIRR_CONN_S 6 +#define TIMPANI_ATEST_PA1_ATEST_EARPA_NCASC_NMIRR_CONN_M 0x40 +#define TIMPANI_ATEST_PA1_ATEST_EARPA_NCASC_NMIRR_CONN_NO_CONNECT 0x0 +#define TIMPANI_ATEST_PA1_ATEST_EARPA_NCASC_NMIRR_CONN_EN 0x1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_ATEST_PA1_ATEST_EARPA_NMIRR_PCASC_CONN_S 5 +#define TIMPANI_ATEST_PA1_ATEST_EARPA_NMIRR_PCASC_CONN_M 0x20 +#define TIMPANI_ATEST_PA1_ATEST_EARPA_NMIRR_PCASC_CONN_NO_CONNECT 0x0 +#define TIMPANI_ATEST_PA1_ATEST_EARPA_NMIRR_PCASC_CONN_EN 0x1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_ATEST_PA1_ATEST_EARPA_VCM_PTAIL1_CONN_S 4 +#define TIMPANI_ATEST_PA1_ATEST_EARPA_VCM_PTAIL1_CONN_M 0x10 +#define TIMPANI_ATEST_PA1_ATEST_EARPA_VCM_PTAIL1_CONN_NO_CONNECT 0x0 +#define TIMPANI_ATEST_PA1_ATEST_EARPA_VCM_PTAIL1_CONN_EN 0x1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_ATEST_PA1_ATEST_EARPA_IBTEST_VSS2P2_CONN_S 3 +#define TIMPANI_ATEST_PA1_ATEST_EARPA_IBTEST_VSS2P2_CONN_M 0x8 +#define TIMPANI_ATEST_PA1_ATEST_EARPA_IBTEST_VSS2P2_CONN_NO_CONNECT 0x0 +#define TIMPANI_ATEST_PA1_ATEST_EARPA_IBTEST_VSS2P2_CONN_EN 0x1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_ATEST_PA1_ATEST_EARPA_ITEST1_ITEST2_CONN_S 2 +#define TIMPANI_ATEST_PA1_ATEST_EARPA_ITEST1_ITEST2_CONN_M 0x4 +#define TIMPANI_ATEST_PA1_ATEST_EARPA_ITEST1_ITEST2_CONN_NO_CONNECT 0x0 +#define TIMPANI_ATEST_PA1_ATEST_EARPA_ITEST1_ITEST2_CONN_EN 0x1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_ATEST_PA1_ATEST_CLASSD_CLK_GATING_S 1 +#define TIMPANI_ATEST_PA1_ATEST_CLASSD_CLK_GATING_M 0x2 +#define TIMPANI_ATEST_PA1_ATEST_CLASSD_CLK_GATING_PASS 0x0 +#define TIMPANI_ATEST_PA1_ATEST_CLASSD_CLK_GATING_GATE 0x1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_ATEST_PA1_ATEST2_HPH_VCM_CONN_S 0 +#define TIMPANI_ATEST_PA1_ATEST2_HPH_VCM_CONN_M 0x1 +#define TIMPANI_ATEST_PA1_ATEST2_HPH_VCM_CONN_NO_CONNECT 0x0 +#define TIMPANI_ATEST_PA1_ATEST2_HPH_VCM_CONN_CONNECT 0x1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_A_ATEST_CLASSD (0x5B) +#define TIMPANI_ATEST_CLASSD_RWC "RW" +#define TIMPANI_ATEST_CLASSD_POR 0 +#define TIMPANI_ATEST_CLASSD_S 0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_ATEST_CLASSD_M 0xFF +#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_S 4 +#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_M 0xF0 +#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_NO_CONNECT_1 0x0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_L_SC_OCP 0x1 +#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_L_CDAC_CLK 0x2 +#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_L_POS_CDAC 0x3 +#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_L_BREAK_BEFORE_MAKE_OUT_CP 0x4 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_L_COMP_OUT 0x5 +#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_L_INT2_POS_OUT 0x6 +#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_L_INT1_POS_OUT 0x7 +#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_NO_CONNECT_2 0x8 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_R_SC_OCP_SIGNAL 0x9 +#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_R_CDAC_CLK 0xA +#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_R_POS_CDAC 0xB +#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_R_BREAK_BEFORE_MAKE_OUT_CP 0xC +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_R_COMP_OUT 0xD +#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_R_INT2_POS_OUT 0xE +#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_R_INT1_POS_OUT 0xF +#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_S 0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_M 0xF +#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_NO_CONNECT_1 0x0 +#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_L_HI_Z_OCP 0x1 +#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_L_OCP_CLOCK 0x2 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_L_NEG_CDAC 0x3 +#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_L_BREAK_BEFORE_MAKE_OUT_CN 0x4 +#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_L_CM_BUFF_OUT 0x5 +#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_L_INT2_NEG_OUT 0x6 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_L_INT1_NEG_OUT 0x7 +#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_NO_CONNECT_2 0x8 +#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_R_HI_Z_OCP 0x9 +#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_R_OCP_CLOCK 0xA +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_R_NEGATIVE_CDAC 0xB +#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_R_BREAK_BEFORE_MAKE_OUT_CN 0xC +#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_R_CM_BUFF_OUT 0xD +#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_R_INTR2_NEG_OUT 0xE +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_R_INT1_NEG_OUT 0xF +#define TIMPANI_A_ATEST_LINEO_AUXO (0x5C) +#define TIMPANI_ATEST_LINEO_AUXO_RWC "RW" +#define TIMPANI_ATEST_LINEO_AUXO_POR 0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_ATEST_LINEO_AUXO_S 0 +#define TIMPANI_ATEST_LINEO_AUXO_M 0xFF +#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_AUXO_EN_S 7 +#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_AUXO_EN_M 0x80 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_AUXO_EN_DISABLE 0x0 +#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_AUXO_EN_ENABLE 0x1 +#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_AUXO_VCM_CONN_S 6 +#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_AUXO_VCM_CONN_M 0x40 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_AUXO_VCM_CONN_NO_CONNECT 0x0 +#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_AUXO_VCM_CONN_CONNECT 0x1 +#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_L_NREFIN_STG1OP_CONN_S 5 +#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_L_NREFIN_STG1OP_CONN_M 0x20 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_L_NREFIN_STG1OP_CONN_NO_CONNECT 0x0 +#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_L_NREFIN_STG1OP_CONN_EN 0x1 +#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_L_NMOS_PMOS_CONN_S 4 +#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_L_NMOS_PMOS_CONN_M 0x10 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_L_NMOS_PMOS_CONN_NO_CONNECT 0x0 +#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_L_NMOS_PMOS_CONN_EN 01 +#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_R_NREFIN_STG1OP_CONN_S 3 +#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_R_NREFIN_STG1OP_CONN_M 0x8 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_R_NREFIN_STG1OP_CONN_NO_CONNECT 0x0 +#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_R_NREFIN_STG1OP_CONN_EN 01 +#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_R_NMOS_PMOS_CONN_S 2 +#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_R_NMOS_PMOS_CONN_M 0x4 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_R_NMOS_PMOS_CONN_DISABLE 0x0 +#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_R_NMOS_PMOS_CONN_EN 0x1 +#define TIMPANI_ATEST_LINEO_AUXO_ATEST_AUXO_NREFIN_STG1OP_CONN_S 1 +#define TIMPANI_ATEST_LINEO_AUXO_ATEST_AUXO_NREFIN_STG1OP_CONN_M 0x2 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_ATEST_LINEO_AUXO_ATEST_AUXO_NREFIN_STG1OP_CONN_DISABLE 0x0 +#define TIMPANI_ATEST_LINEO_AUXO_ATEST_AUXO_NREFIN_STG1OP_CONN_EN 0x1 +#define TIMPANI_ATEST_LINEO_AUXO_ATEST_AUXO_NMOS_PMOS_CONN_S 0 +#define TIMPANI_ATEST_LINEO_AUXO_ATEST_AUXO_NMOS_PMOS_CONN_M 0x1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_ATEST_LINEO_AUXO_ATEST_AUXO_NMOS_PMOS_CONN_DISABLE 0x0 +#define TIMPANI_ATEST_LINEO_AUXO_ATEST_AUXO_NMOS_PMOS_CONN_EN 0x1 +#define TIMPANI_A_CDC_RESET_CTL (0x80) +#define TIMPANI_CDC_RESET_CTL_RWC "RW" +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_RESET_CTL_POR 0 +#define TIMPANI_CDC_RESET_CTL_S 0 +#define TIMPANI_CDC_RESET_CTL_M 0x7F +#define TIMPANI_CDC_RESET_CTL_ARB_SOFT_RESET_S 6 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_RESET_CTL_ARB_SOFT_RESET_M 0x40 +#define TIMPANI_CDC_RESET_CTL_TX2_SOFT_RESET_R_S 5 +#define TIMPANI_CDC_RESET_CTL_TX2_SOFT_RESET_R_M 0x20 +#define TIMPANI_CDC_RESET_CTL_TX2_SOFT_RESET_L_S 4 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_RESET_CTL_TX2_SOFT_RESET_L_M 0x10 +#define TIMPANI_CDC_RESET_CTL_RX2_SOFT_RESET_S 3 +#define TIMPANI_CDC_RESET_CTL_RX2_SOFT_RESET_M 0x8 +#define TIMPANI_CDC_RESET_CTL_TX1_SOFT_RESET_R_S 2 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_RESET_CTL_TX1_SOFT_RESET_R_M 0x4 +#define TIMPANI_CDC_RESET_CTL_RX1_SOFT_RESET_S 1 +#define TIMPANI_CDC_RESET_CTL_RX1_SOFT_RESET_M 0x2 +#define TIMPANI_CDC_RESET_CTL_TX1_SOFT_RESET_L_S 0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_RESET_CTL_TX1_SOFT_RESET_L_M 0x1 +#define TIMPANI_A_CDC_RX1_CTL (0x81) +#define TIMPANI_CDC_RX1_CTL_RWC "RW" +#define TIMPANI_CDC_RX1_CTL_POR 0xc +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_RX1_CTL_S 0 +#define TIMPANI_CDC_RX1_CTL_M 0x3F +#define TIMPANI_CDC_RX1_CTL_SIDETONE_EN1_R_S 5 +#define TIMPANI_CDC_RX1_CTL_SIDETONE_EN1_R_M 0x20 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_RX1_CTL_SIDETONE_EN1_L_S 4 +#define TIMPANI_CDC_RX1_CTL_SIDETONE_EN1_L_M 0x10 +#define TIMPANI_CDC_RX1_CTL_RX1_RATE_S 2 +#define TIMPANI_CDC_RX1_CTL_RX1_RATE_M 0xC +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_RX1_CTL_RX1_RATE_OSR_256 0x3 +#define TIMPANI_CDC_RX1_CTL_RX1_RATE_OSR_128 0x1 +#define TIMPANI_CDC_RX1_CTL_RX1_RATE_OSR_64 0x0 +#define TIMPANI_CDC_RX1_CTL_RX1_I2S_RATE_S 1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_RX1_CTL_RX1_I2S_RATE_M 0x2 +#define TIMPANI_CDC_RX1_CTL_RX1_I2S_RATE_BR_32 0x1 +#define TIMPANI_CDC_RX1_CTL_RX1_I2S_RATE_BR_64 0x0 +#define TIMPANI_CDC_RX1_CTL_RX1_I2S_MODE_S 0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_RX1_CTL_RX1_I2S_MODE_M 0x1 +#define TIMPANI_CDC_RX1_CTL_RX1_I2S_MODE_MASTER 0x1 +#define TIMPANI_CDC_RX1_CTL_RX1_I2S_MODE_SLAVE 0x0 +#define TIMPANI_A_CDC_TX_I2S_CTL (0x82) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_TX_I2S_CTL_RWC "RW" +#define TIMPANI_CDC_TX_I2S_CTL_POR 0xc +#define TIMPANI_CDC_TX_I2S_CTL_S 0 +#define TIMPANI_CDC_TX_I2S_CTL_M 0x3F +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_TX_I2S_CTL_TX2_I2S_SD_OE_S 5 +#define TIMPANI_CDC_TX_I2S_CTL_TX2_I2S_SD_OE_M 0x20 +#define TIMPANI_CDC_TX_I2S_CTL_TX1_I2S_SD_OE_S 4 +#define TIMPANI_CDC_TX_I2S_CTL_TX1_I2S_SD_OE_M 0x10 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_TX_I2S_CTL_TX_RATE_S 2 +#define TIMPANI_CDC_TX_I2S_CTL_TX_RATE_M 0xC +#define TIMPANI_CDC_TX_I2S_CTL_TX_RATE_OSR_256 0x3 +#define TIMPANI_CDC_TX_I2S_CTL_TX_RATE_OSR_128 0x1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_TX_I2S_CTL_TX_RATE_OSR_64 0x0 +#define TIMPANI_CDC_TX_I2S_CTL_TX_I2S_RATE_S 1 +#define TIMPANI_CDC_TX_I2S_CTL_TX_I2S_RATE_M 0x2 +#define TIMPANI_CDC_TX_I2S_CTL_TX_I2S_RATE_BR_32 0x1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_TX_I2S_CTL_TX_I2S_RATE_BR_64 0x0 +#define TIMPANI_CDC_TX_I2S_CTL_TX_I2S_MODE_S 0 +#define TIMPANI_CDC_TX_I2S_CTL_TX_I2S_MODE_M 0x1 +#define TIMPANI_CDC_TX_I2S_CTL_TX_I2S_MODE_MASTER 0x1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_TX_I2S_CTL_TX_I2S_MODE_SLAVE 0x0 +#define TIMPANI_A_CDC_CH_CTL (0x83) +#define TIMPANI_CDC_CH_CTL_RWC "RW" +#define TIMPANI_CDC_CH_CTL_POR 0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_CH_CTL_S 0 +#define TIMPANI_CDC_CH_CTL_M 0xFF +#define TIMPANI_CDC_CH_CTL_TX2_EN_R_S 7 +#define TIMPANI_CDC_CH_CTL_TX2_EN_R_M 0x80 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_CH_CTL_TX2_EN_L_S 6 +#define TIMPANI_CDC_CH_CTL_TX2_EN_L_M 0x40 +#define TIMPANI_CDC_CH_CTL_RX2_EN_R_S 5 +#define TIMPANI_CDC_CH_CTL_RX2_EN_R_M 0x20 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_CH_CTL_RX2_EN_L_S 4 +#define TIMPANI_CDC_CH_CTL_RX2_EN_L_M 0x10 +#define TIMPANI_CDC_CH_CTL_TX1_EN_R_S 3 +#define TIMPANI_CDC_CH_CTL_TX1_EN_R_M 0x8 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_CH_CTL_TX1_EN_L_S 2 +#define TIMPANI_CDC_CH_CTL_TX1_EN_L_M 0x4 +#define TIMPANI_CDC_CH_CTL_RX1_EN_R_S 1 +#define TIMPANI_CDC_CH_CTL_RX1_EN_R_M 0x2 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_CH_CTL_RX1_EN_L_S 0 +#define TIMPANI_CDC_CH_CTL_RX1_EN_L_M 0x1 +#define TIMPANI_A_CDC_RX1LG (0x84) +#define TIMPANI_CDC_RX1LG_RWC "RW" +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_RX1LG_POR 0xac +#define TIMPANI_CDC_RX1LG_S 0 +#define TIMPANI_CDC_RX1LG_M 0xFF +#define TIMPANI_CDC_RX1LG_GAIN_S 0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_RX1LG_GAIN_M 0xFF +#define TIMPANI_A_CDC_RX1RG (0x85) +#define TIMPANI_CDC_RX1RG_RWC "RW" +#define TIMPANI_CDC_RX1RG_POR 0xac +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_RX1RG_S 0 +#define TIMPANI_CDC_RX1RG_M 0xFF +#define TIMPANI_CDC_RX1RG_GAIN_S 0 +#define TIMPANI_CDC_RX1RG_GAIN_M 0xFF +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_A_CDC_TX1LG (0x86) +#define TIMPANI_CDC_TX1LG_RWC "RW" +#define TIMPANI_CDC_TX1LG_POR 0xac +#define TIMPANI_CDC_TX1LG_S 0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_TX1LG_M 0xFF +#define TIMPANI_CDC_TX1LG_GAIN_S 0 +#define TIMPANI_CDC_TX1LG_GAIN_M 0xFF +#define TIMPANI_A_CDC_TX1RG (0x87) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_TX1RG_RWC "RW" +#define TIMPANI_CDC_TX1RG_POR 0xac +#define TIMPANI_CDC_TX1RG_S 0 +#define TIMPANI_CDC_TX1RG_M 0xFF +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_TX1RG_GAIN_S 0 +#define TIMPANI_CDC_TX1RG_GAIN_M 0xFF +#define TIMPANI_A_CDC_RX_PGA_TIMER (0x88) +#define TIMPANI_CDC_RX_PGA_TIMER_RWC "RW" +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_RX_PGA_TIMER_POR 0xff +#define TIMPANI_CDC_RX_PGA_TIMER_S 0 +#define TIMPANI_CDC_RX_PGA_TIMER_M 0xFF +#define TIMPANI_CDC_RX_PGA_TIMER_TIMER_VAL_S 0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_RX_PGA_TIMER_TIMER_VAL_M 0xFF +#define TIMPANI_A_CDC_TX_PGA_TIMER (0x89) +#define TIMPANI_CDC_TX_PGA_TIMER_RWC "RW" +#define TIMPANI_CDC_TX_PGA_TIMER_POR 0xff +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_TX_PGA_TIMER_S 0 +#define TIMPANI_CDC_TX_PGA_TIMER_M 0xFF +#define TIMPANI_CDC_TX_PGA_TIMER_TIMER_VAL_S 0 +#define TIMPANI_CDC_TX_PGA_TIMER_TIMER_VAL_M 0xFF +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_A_CDC_GCTL1 (0x8A) +#define TIMPANI_CDC_GCTL1_RWC "RW" +#define TIMPANI_CDC_GCTL1_POR 0x33 +#define TIMPANI_CDC_GCTL1_S 0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_GCTL1_M 0xFF +#define TIMPANI_CDC_GCTL1_TX1_PGA_UPDATE_R_S 7 +#define TIMPANI_CDC_GCTL1_TX1_PGA_UPDATE_R_M 0x80 +#define TIMPANI_CDC_GCTL1_TX1_PGA_UPDATE_L_S 6 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_GCTL1_TX1_PGA_UPDATE_L_M 0x40 +#define TIMPANI_CDC_GCTL1_TX1_PGA_MUTE_EN_R_S 5 +#define TIMPANI_CDC_GCTL1_TX1_PGA_MUTE_EN_R_M 0x20 +#define TIMPANI_CDC_GCTL1_TX1_PGA_MUTE_EN_L_S 4 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_GCTL1_TX1_PGA_MUTE_EN_L_M 0x10 +#define TIMPANI_CDC_GCTL1_RX1_PGA_UPDATE_R_S 3 +#define TIMPANI_CDC_GCTL1_RX1_PGA_UPDATE_R_M 0x8 +#define TIMPANI_CDC_GCTL1_RX1_PGA_UPDATE_L_S 2 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_GCTL1_RX1_PGA_UPDATE_L_M 0x4 +#define TIMPANI_CDC_GCTL1_RX1_PGA_MUTE_EN_R_S 1 +#define TIMPANI_CDC_GCTL1_RX1_PGA_MUTE_EN_R_M 0x2 +#define TIMPANI_CDC_GCTL1_RX1_PGA_MUTE_EN_L_S 0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_GCTL1_RX1_PGA_MUTE_EN_L_M 0x1 +#define TIMPANI_A_CDC_TX1L_STG (0x8B) +#define TIMPANI_CDC_TX1L_STG_RWC "RW" +#define TIMPANI_CDC_TX1L_STG_POR 0xac +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_TX1L_STG_S 0 +#define TIMPANI_CDC_TX1L_STG_M 0xFF +#define TIMPANI_CDC_TX1L_STG_GAIN_S 0 +#define TIMPANI_CDC_TX1L_STG_GAIN_M 0xFF +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_A_CDC_ST_CTL (0x8C) +#define TIMPANI_CDC_ST_CTL_RWC "RW" +#define TIMPANI_CDC_ST_CTL_POR 0x55 +#define TIMPANI_CDC_ST_CTL_S 0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_ST_CTL_M 0xFF +#define TIMPANI_CDC_ST_CTL_TX2_R_SIDETONE_UPDATE_S 7 +#define TIMPANI_CDC_ST_CTL_TX2_R_SIDETONE_UPDATE_M 0x80 +#define TIMPANI_CDC_ST_CTL_TX2_R_SIDETONE_MUTE_EN_S 6 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_ST_CTL_TX2_R_SIDETONE_MUTE_EN_M 0x40 +#define TIMPANI_CDC_ST_CTL_TX2_L_SIDETONE_UPDATE_S 5 +#define TIMPANI_CDC_ST_CTL_TX2_L_SIDETONE_UPDATE_M 0x20 +#define TIMPANI_CDC_ST_CTL_TX2_L_SIDETONE_MUTE_EN_S 4 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_ST_CTL_TX2_L_SIDETONE_MUTE_EN_M 0x10 +#define TIMPANI_CDC_ST_CTL_TX1_R_SIDETONE_UPDATE_S 3 +#define TIMPANI_CDC_ST_CTL_TX1_R_SIDETONE_UPDATE_M 0x8 +#define TIMPANI_CDC_ST_CTL_TX1_R_SIDETONE_MUTE_EN_S 2 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_ST_CTL_TX1_R_SIDETONE_MUTE_EN_M 0x4 +#define TIMPANI_CDC_ST_CTL_TX1_L_SIDETONE_UPDATE_S 1 +#define TIMPANI_CDC_ST_CTL_TX1_L_SIDETONE_UPDATE_M 0x2 +#define TIMPANI_CDC_ST_CTL_TX1_L_SIDETONE_MUTE_EN_S 0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_ST_CTL_TX1_L_SIDETONE_MUTE_EN_M 0x1 +#define TIMPANI_A_CDC_RX1L_DCOFFSET (0x8D) +#define TIMPANI_CDC_RX1L_DCOFFSET_RWC "RW" +#define TIMPANI_CDC_RX1L_DCOFFSET_POR 0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_RX1L_DCOFFSET_S 0 +#define TIMPANI_CDC_RX1L_DCOFFSET_M 0xFF +#define TIMPANI_CDC_RX1L_DCOFFSET_OFFSET_S 0 +#define TIMPANI_CDC_RX1L_DCOFFSET_OFFSET_M 0xFF +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_A_CDC_RX1R_DCOFFSET (0x8E) +#define TIMPANI_CDC_RX1R_DCOFFSET_RWC "RW" +#define TIMPANI_CDC_RX1R_DCOFFSET_POR 0 +#define TIMPANI_CDC_RX1R_DCOFFSET_S 0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_RX1R_DCOFFSET_M 0xFF +#define TIMPANI_CDC_RX1R_DCOFFSET_OFFSET_S 0 +#define TIMPANI_CDC_RX1R_DCOFFSET_OFFSET_M 0xFF +#define TIMPANI_A_CDC_BYPASS_CTL1 (0x8F) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_BYPASS_CTL1_RWC "RW" +#define TIMPANI_CDC_BYPASS_CTL1_POR 0x2 +#define TIMPANI_CDC_BYPASS_CTL1_S 0 +#define TIMPANI_CDC_BYPASS_CTL1_M 0xF +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_BYPASS_CTL1_DITHER_BP_S 3 +#define TIMPANI_CDC_BYPASS_CTL1_DITHER_BP_M 0x8 +#define TIMPANI_CDC_BYPASS_CTL1_DITHER_SHAPE_SEL_S 2 +#define TIMPANI_CDC_BYPASS_CTL1_DITHER_SHAPE_SEL_M 0x4 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_BYPASS_CTL1_DITHER_DLY_SEL_S 1 +#define TIMPANI_CDC_BYPASS_CTL1_DITHER_DLY_SEL_M 0x2 +#define TIMPANI_CDC_BYPASS_CTL1_RX1_HPF_BP_S 0 +#define TIMPANI_CDC_BYPASS_CTL1_RX1_HPF_BP_M 0x1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_A_CDC_PDM_CONFIG (0x90) +#define TIMPANI_CDC_PDM_CONFIG_RWC "RW" +#define TIMPANI_CDC_PDM_CONFIG_POR 0 +#define TIMPANI_CDC_PDM_CONFIG_S 0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_PDM_CONFIG_M 0xF +#define TIMPANI_CDC_PDM_CONFIG_PDM_SEL_S 0 +#define TIMPANI_CDC_PDM_CONFIG_PDM_SEL_M 0xF +#define TIMPANI_A_CDC_TESTMODE1 (0x91) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_TESTMODE1_RWC "RW" +#define TIMPANI_CDC_TESTMODE1_POR 0 +#define TIMPANI_CDC_TESTMODE1_S 0 +#define TIMPANI_CDC_TESTMODE1_M 0x3F +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_TESTMODE1_COMP_I2C_TEST_EN_S 5 +#define TIMPANI_CDC_TESTMODE1_COMP_I2C_TEST_EN_M 0x20 +#define TIMPANI_CDC_TESTMODE1_RX1_TEST_EN_R_S 4 +#define TIMPANI_CDC_TESTMODE1_RX1_TEST_EN_R_M 0x10 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_TESTMODE1_RX1_TEST_EN_L_S 3 +#define TIMPANI_CDC_TESTMODE1_RX1_TEST_EN_L_M 0x8 +#define TIMPANI_CDC_TESTMODE1_TX1_TEST_EN_R_S 2 +#define TIMPANI_CDC_TESTMODE1_TX1_TEST_EN_R_M 0x4 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_TESTMODE1_TX1_TEST_EN_L_S 1 +#define TIMPANI_CDC_TESTMODE1_TX1_TEST_EN_L_M 0x2 +#define TIMPANI_CDC_TESTMODE1_A_LOOPBACK_EN1_S 0 +#define TIMPANI_CDC_TESTMODE1_A_LOOPBACK_EN1_M 0x1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_A_CDC_DMIC_CLK_CTL (0x92) +#define TIMPANI_CDC_DMIC_CLK_CTL_RWC "RW" +#define TIMPANI_CDC_DMIC_CLK_CTL_POR 0 +#define TIMPANI_CDC_DMIC_CLK_CTL_S 0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_DMIC_CLK_CTL_M 0x3F +#define TIMPANI_CDC_DMIC_CLK_CTL_DMIC_MCLK_DIV_SEL_S 3 +#define TIMPANI_CDC_DMIC_CLK_CTL_DMIC_MCLK_DIV_SEL_M 0x38 +#define TIMPANI_CDC_DMIC_CLK_CTL_DMIC_MCLK_DIV_SEL_DIV_6 0x4 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_DMIC_CLK_CTL_DMIC_MCLK_DIV_SEL_DIV_4 0x3 +#define TIMPANI_CDC_DMIC_CLK_CTL_DMIC_MCLK_DIV_SEL_DIV_3 0x2 +#define TIMPANI_CDC_DMIC_CLK_CTL_DMIC_MCLK_DIV_SEL_DIV_2 0x1 +#define TIMPANI_CDC_DMIC_CLK_CTL_DMIC_MCLK_DIV_SEL_DIV_1 0x0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_DMIC_CLK_CTL_DMIC_MCLK_SEL_S 1 +#define TIMPANI_CDC_DMIC_CLK_CTL_DMIC_MCLK_SEL_M 0x6 +#define TIMPANI_CDC_DMIC_CLK_CTL_DMIC_MCLK_SEL_RX_MCLK2 0x2 +#define TIMPANI_CDC_DMIC_CLK_CTL_DMIC_MCLK_SEL_RX_MCLK1 0x1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_DMIC_CLK_CTL_DMIC_MCLK_SEL_TX_MCLK 0x0 +#define TIMPANI_CDC_DMIC_CLK_CTL_DMIC_CLK_EN_S 0 +#define TIMPANI_CDC_DMIC_CLK_CTL_DMIC_CLK_EN_M 0x1 +#define TIMPANI_A_CDC_ADC12_CLK_CTL (0x93) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_ADC12_CLK_CTL_RWC "RW" +#define TIMPANI_CDC_ADC12_CLK_CTL_POR 0 +#define TIMPANI_CDC_ADC12_CLK_CTL_S 0 +#define TIMPANI_CDC_ADC12_CLK_CTL_M 0xFF +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_SEL_S 6 +#define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_SEL_M 0xC0 +#define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_SEL_RX_MCLK2 0x2 +#define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_SEL_RX_MCLK1 0x1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_SEL_TX_MCLK 0x0 +#define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_DIV_SEL_R_S 3 +#define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_DIV_SEL_R_M 0x38 +#define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_DIV_SEL_R_DIV_6 0x4 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_DIV_SEL_R_DIV_4 0x3 +#define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_DIV_SEL_R_DIV_3 0x2 +#define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_DIV_SEL_R_DIV_2 0x1 +#define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_DIV_SEL_R_DIV_1 0x0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_DIV_SEL_L_S 0 +#define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_DIV_SEL_L_M 0x7 +#define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_DIV_SEL_L_DIV_6 0x4 +#define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_DIV_SEL_L_DIV_4 0x3 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_DIV_SEL_L_DIV_3 0x2 +#define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_DIV_SEL_L_DIV_2 0x1 +#define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_DIV_SEL_L_DIV_1 0x0 +#define TIMPANI_A_CDC_TX1_CTL (0x94) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_TX1_CTL_RWC "RW" +#define TIMPANI_CDC_TX1_CTL_POR 0x1b +#define TIMPANI_CDC_TX1_CTL_S 0 +#define TIMPANI_CDC_TX1_CTL_M 0x3F +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_TX1_CTL_TX1_DMIC_SEL_R_S 5 +#define TIMPANI_CDC_TX1_CTL_TX1_DMIC_SEL_R_M 0x20 +#define TIMPANI_CDC_TX1_CTL_TX1_RATE_R_S 3 +#define TIMPANI_CDC_TX1_CTL_TX1_RATE_R_M 0x18 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_TX1_CTL_TX1_RATE_R_OSR_256 0x3 +#define TIMPANI_CDC_TX1_CTL_TX1_RATE_R_OSR_128 0x1 +#define TIMPANI_CDC_TX1_CTL_TX1_RATE_R_OSR_64 0x0 +#define TIMPANI_CDC_TX1_CTL_TX1_DMIC_SEL_L_S 2 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_TX1_CTL_TX1_DMIC_SEL_L_M 0x4 +#define TIMPANI_CDC_TX1_CTL_TX1_RATE_L_S 0 +#define TIMPANI_CDC_TX1_CTL_TX1_RATE_L_M 0x3 +#define TIMPANI_CDC_TX1_CTL_TX1_RATE_L_OSR_256 0x3 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_TX1_CTL_TX1_RATE_L_OSR_128 0x1 +#define TIMPANI_CDC_TX1_CTL_TX1_RATE_L_OSR_64 0x0 +#define TIMPANI_A_CDC_ADC34_CLK_CTL (0x95) +#define TIMPANI_CDC_ADC34_CLK_CTL_RWC "RW" +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_ADC34_CLK_CTL_POR 0 +#define TIMPANI_CDC_ADC34_CLK_CTL_S 0 +#define TIMPANI_CDC_ADC34_CLK_CTL_M 0xFF +#define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_SEL_S 6 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_SEL_M 0xC0 +#define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_SEL_RX_MCLK2 0x2 +#define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_SEL_RX_MCLK1 0x1 +#define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_SEL_TX_MCLK 0x0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_DIV_SEL_R_S 3 +#define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_DIV_SEL_R_M 0x38 +#define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_DIV_SEL_R_DIV_6 0x4 +#define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_DIV_SEL_R_DIV_4 0x3 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_DIV_SEL_R_DIV_3 0x2 +#define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_DIV_SEL_R_DIV_2 0x1 +#define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_DIV_SEL_R_DIV_1 0x0 +#define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_DIV_SEL_L_S 0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_DIV_SEL_L_M 0x7 +#define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_DIV_SEL_L_DIV_6 0x4 +#define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_DIV_SEL_L_DIV_4 0x3 +#define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_DIV_SEL_L_DIV_3 0x2 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_DIV_SEL_L_DIV_2 0x1 +#define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_DIV_SEL_L_DIV_1 0x0 +#define TIMPANI_A_CDC_TX2_CTL (0x96) +#define TIMPANI_CDC_TX2_CTL_RWC "RW" +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_TX2_CTL_POR 0x1b +#define TIMPANI_CDC_TX2_CTL_S 0 +#define TIMPANI_CDC_TX2_CTL_M 0x3F +#define TIMPANI_CDC_TX2_CTL_TX2_DMIC_SEL_R_S 5 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_TX2_CTL_TX2_DMIC_SEL_R_M 0x20 +#define TIMPANI_CDC_TX2_CTL_TX2_RATE_R_S 3 +#define TIMPANI_CDC_TX2_CTL_TX2_RATE_R_M 0x18 +#define TIMPANI_CDC_TX2_CTL_TX2_RATE_R_OSR_256 0x3 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_TX2_CTL_TX2_RATE_R_OSR_128 0x1 +#define TIMPANI_CDC_TX2_CTL_TX2_RATE_R_OSR_64 0x0 +#define TIMPANI_CDC_TX2_CTL_TX2_DMIC_SEL_L_S 2 +#define TIMPANI_CDC_TX2_CTL_TX2_DMIC_SEL_L_M 0x4 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_TX2_CTL_TX2_RATE_L_S 0 +#define TIMPANI_CDC_TX2_CTL_TX2_RATE_L_M 0x3 +#define TIMPANI_CDC_TX2_CTL_TX2_RATE_L_OSR_256 0x3 +#define TIMPANI_CDC_TX2_CTL_TX2_RATE_L_OSR_128 0x1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_TX2_CTL_TX2_RATE_L_OSR_64 0x0 +#define TIMPANI_A_CDC_RX1_CLK_CTL (0x97) +#define TIMPANI_CDC_RX1_CLK_CTL_RWC "RW" +#define TIMPANI_CDC_RX1_CLK_CTL_POR 0x1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_RX1_CLK_CTL_S 0 +#define TIMPANI_CDC_RX1_CLK_CTL_M 0x1F +#define TIMPANI_CDC_RX1_CLK_CTL_RX1_MCLK_DIV_SEL_S 2 +#define TIMPANI_CDC_RX1_CLK_CTL_RX1_MCLK_DIV_SEL_M 0x1C +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_RX1_CLK_CTL_RX1_MCLK_DIV_SEL_DIV_6 0x4 +#define TIMPANI_CDC_RX1_CLK_CTL_RX1_MCLK_DIV_SEL_DIV_4 0x3 +#define TIMPANI_CDC_RX1_CLK_CTL_RX1_MCLK_DIV_SEL_DIV_3 0x2 +#define TIMPANI_CDC_RX1_CLK_CTL_RX1_MCLK_DIV_SEL_DIV_2 0x1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_RX1_CLK_CTL_RX1_MCLK_DIV_SEL_DIV_1 0x0 +#define TIMPANI_CDC_RX1_CLK_CTL_RX1_MCLK_SEL_S 0 +#define TIMPANI_CDC_RX1_CLK_CTL_RX1_MCLK_SEL_M 0x3 +#define TIMPANI_CDC_RX1_CLK_CTL_RX1_MCLK_SEL_RX_MCLK2 0x2 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_RX1_CLK_CTL_RX1_MCLK_SEL_RX_MCLK1 0x1 +#define TIMPANI_CDC_RX1_CLK_CTL_RX1_MCLK_SEL_TX_MCLK 0x0 +#define TIMPANI_A_CDC_RX2_CLK_CTL (0x98) +#define TIMPANI_CDC_RX2_CLK_CTL_RWC "RW" +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_RX2_CLK_CTL_POR 0x2 +#define TIMPANI_CDC_RX2_CLK_CTL_S 0 +#define TIMPANI_CDC_RX2_CLK_CTL_M 0x1F +#define TIMPANI_CDC_RX2_CLK_CTL_RX2_MCLK_DIV_SEL_S 2 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_RX2_CLK_CTL_RX2_MCLK_DIV_SEL_M 0x1C +#define TIMPANI_CDC_RX2_CLK_CTL_RX2_MCLK_DIV_SEL_DIV_6 0x4 +#define TIMPANI_CDC_RX2_CLK_CTL_RX2_MCLK_DIV_SEL_DIV_4 0x3 +#define TIMPANI_CDC_RX2_CLK_CTL_RX2_MCLK_DIV_SEL_DIV_3 0x2 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_RX2_CLK_CTL_RX2_MCLK_DIV_SEL_DIV_2 0x1 +#define TIMPANI_CDC_RX2_CLK_CTL_RX2_MCLK_DIV_SEL_DIV_1 0x0 +#define TIMPANI_CDC_RX2_CLK_CTL_RX2_MCLK_SEL_S 0 +#define TIMPANI_CDC_RX2_CLK_CTL_RX2_MCLK_SEL_M 0x3 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_RX2_CLK_CTL_RX2_MCLK_SEL_RX_MCLK2 0x2 +#define TIMPANI_CDC_RX2_CLK_CTL_RX2_MCLK_SEL_RX_MCLK1 0x1 +#define TIMPANI_CDC_RX2_CLK_CTL_RX2_MCLK_SEL_TX_MCLK 0x0 +#define TIMPANI_A_CDC_DEC_ADC_SEL (0x99) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_DEC_ADC_SEL_RWC "RW" +#define TIMPANI_CDC_DEC_ADC_SEL_POR 0 +#define TIMPANI_CDC_DEC_ADC_SEL_S 0 +#define TIMPANI_CDC_DEC_ADC_SEL_M 0xFF +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_DEC_ADC_SEL_TX2_ADC_SEL_R_S 6 +#define TIMPANI_CDC_DEC_ADC_SEL_TX2_ADC_SEL_R_M 0xC0 +#define TIMPANI_CDC_DEC_ADC_SEL_TX2_ADC_SEL_R_ADC4 0x3 +#define TIMPANI_CDC_DEC_ADC_SEL_TX2_ADC_SEL_R_ADC3 0x2 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_DEC_ADC_SEL_TX2_ADC_SEL_R_ADC2 0x1 +#define TIMPANI_CDC_DEC_ADC_SEL_TX2_ADC_SEL_R_ADC1 0x0 +#define TIMPANI_CDC_DEC_ADC_SEL_TX2_ADC_SEL_L_S 4 +#define TIMPANI_CDC_DEC_ADC_SEL_TX2_ADC_SEL_L_M 0x30 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_DEC_ADC_SEL_TX2_ADC_SEL_L_ADC4 0x3 +#define TIMPANI_CDC_DEC_ADC_SEL_TX2_ADC_SEL_L_ADC3 0x2 +#define TIMPANI_CDC_DEC_ADC_SEL_TX2_ADC_SEL_L_ADC2 0x1 +#define TIMPANI_CDC_DEC_ADC_SEL_TX2_ADC_SEL_L_ADC1 0x0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_DEC_ADC_SEL_TX1_ADC_SEL_R_S 2 +#define TIMPANI_CDC_DEC_ADC_SEL_TX1_ADC_SEL_R_M 0xC +#define TIMPANI_CDC_DEC_ADC_SEL_TX1_ADC_SEL_R_ADC4 0x3 +#define TIMPANI_CDC_DEC_ADC_SEL_TX1_ADC_SEL_R_ADC3 0x2 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_DEC_ADC_SEL_TX1_ADC_SEL_R_ADC2 0x1 +#define TIMPANI_CDC_DEC_ADC_SEL_TX1_ADC_SEL_R_ADC1 0x0 +#define TIMPANI_CDC_DEC_ADC_SEL_TX1_ADC_SEL_L_S 0 +#define TIMPANI_CDC_DEC_ADC_SEL_TX1_ADC_SEL_L_M 0x3 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_DEC_ADC_SEL_TX1_ADC_SEL_L_ADC4 0x3 +#define TIMPANI_CDC_DEC_ADC_SEL_TX1_ADC_SEL_L_ADC3 0x2 +#define TIMPANI_CDC_DEC_ADC_SEL_TX1_ADC_SEL_L_ADC2 0x1 +#define TIMPANI_CDC_DEC_ADC_SEL_TX1_ADC_SEL_L_ADC1 0x0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_A_CDC_ANC_INPUT_MUX (0x9A) +#define TIMPANI_CDC_ANC_INPUT_MUX_RWC "RW" +#define TIMPANI_CDC_ANC_INPUT_MUX_POR 0 +#define TIMPANI_CDC_ANC_INPUT_MUX_S 0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_ANC_INPUT_MUX_M 0xFF +#define TIMPANI_CDC_ANC_INPUT_MUX_ANC2_ADC_SEL_S 6 +#define TIMPANI_CDC_ANC_INPUT_MUX_ANC2_ADC_SEL_M 0xC0 +#define TIMPANI_CDC_ANC_INPUT_MUX_ANC2_ADC_SEL_A_CDC_TX2DOR 0x3 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_ANC_INPUT_MUX_ANC2_ADC_SEL_A_CDC_TX2DOL 0x2 +#define TIMPANI_CDC_ANC_INPUT_MUX_ANC2_ADC_SEL_A_CDC_TX1DOR 0x1 +#define TIMPANI_CDC_ANC_INPUT_MUX_ANC2_ADC_SEL_A_CDC_TX1DOL 0x0 +#define TIMPANI_CDC_ANC_INPUT_MUX_ANC2_DMIC_SEL_S 4 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_ANC_INPUT_MUX_ANC2_DMIC_SEL_M 0x30 +#define TIMPANI_CDC_ANC_INPUT_MUX_ANC2_DMIC_SEL_MIC2_DIN_R 0x3 +#define TIMPANI_CDC_ANC_INPUT_MUX_ANC2_DMIC_SEL_MIC2_DIN_L 0x2 +#define TIMPANI_CDC_ANC_INPUT_MUX_ANC2_DMIC_SEL_MIC1_DIN_R 0x1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_ANC_INPUT_MUX_ANC2_DMIC_SEL_MIC1_DIN_L 0x0 +#define TIMPANI_CDC_ANC_INPUT_MUX_ANC1_ADC_SEL_S 2 +#define TIMPANI_CDC_ANC_INPUT_MUX_ANC1_ADC_SEL_M 0xC +#define TIMPANI_CDC_ANC_INPUT_MUX_ANC1_ADC_SEL_A_CDC_TX2DOR 0x3 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_ANC_INPUT_MUX_ANC1_ADC_SEL_A_CDC_TX2DOL 0x2 +#define TIMPANI_CDC_ANC_INPUT_MUX_ANC1_ADC_SEL_A_CDC_TX1DOR 0x1 +#define TIMPANI_CDC_ANC_INPUT_MUX_ANC1_ADC_SEL_A_CDC_TX1DOL 0x0 +#define TIMPANI_CDC_ANC_INPUT_MUX_ANC1_DMIC_SEL_S 0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_ANC_INPUT_MUX_ANC1_DMIC_SEL_M 0x3 +#define TIMPANI_CDC_ANC_INPUT_MUX_ANC1_DMIC_SEL_MIC2_DIN_R 0x3 +#define TIMPANI_CDC_ANC_INPUT_MUX_ANC1_DMIC_SEL_MIC2_DIN_L 0x2 +#define TIMPANI_CDC_ANC_INPUT_MUX_ANC1_DMIC_SEL_MIC1_DIN_R 0x1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_ANC_INPUT_MUX_ANC1_DMIC_SEL_MIC1_DIN_L 0x0 +#define TIMPANI_A_CDC_ANC_RX_CLK_NS_SEL (0x9B) +#define TIMPANI_CDC_ANC_RX_CLK_NS_SEL_RWC "RW" +#define TIMPANI_CDC_ANC_RX_CLK_NS_SEL_POR 0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_ANC_RX_CLK_NS_SEL_S 0 +#define TIMPANI_CDC_ANC_RX_CLK_NS_SEL_M 0x1 +#define TIMPANI_CDC_ANC_RX_CLK_NS_SEL_ANC_RX_CLK_NS_SEL_S 0 +#define TIMPANI_CDC_ANC_RX_CLK_NS_SEL_ANC_RX_CLK_NS_SEL_M 0x1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_A_CDC_ANC_FB_TUNE_SEL (0x9C) +#define TIMPANI_CDC_ANC_FB_TUNE_SEL_RWC "RW" +#define TIMPANI_CDC_ANC_FB_TUNE_SEL_POR 0 +#define TIMPANI_CDC_ANC_FB_TUNE_SEL_S 0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_ANC_FB_TUNE_SEL_M 0x3 +#define TIMPANI_CDC_ANC_FB_TUNE_SEL_ANC2_FB_ADC_SEL_S 1 +#define TIMPANI_CDC_ANC_FB_TUNE_SEL_ANC2_FB_ADC_SEL_M 0x2 +#define TIMPANI_CDC_ANC_FB_TUNE_SEL_ANC2_FB_ADC_SEL_FB_TUNE_EN 0x1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_ANC_FB_TUNE_SEL_ANC2_FB_ADC_SEL_FB_TUNE_DIS 0x0 +#define TIMPANI_CDC_ANC_FB_TUNE_SEL_ANC1_FB_ADC_SEL_S 0 +#define TIMPANI_CDC_ANC_FB_TUNE_SEL_ANC1_FB_ADC_SEL_M 0x1 +#define TIMPANI_CDC_ANC_FB_TUNE_SEL_ANC1_FB_ADC_SEL_FB_TUNE_EN 0x1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_ANC_FB_TUNE_SEL_ANC1_FB_ADC_SEL_FB_TUNE_DIS 0x0 +#define TIMPANI_A_CLK_DIV_SYNC_CTL (0x9E) +#define TIMPANI_CLK_DIV_SYNC_CTL_RWC "RW" +#define TIMPANI_CLK_DIV_SYNC_CTL_POR 0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CLK_DIV_SYNC_CTL_S 0 +#define TIMPANI_CLK_DIV_SYNC_CTL_M 0x3 +#define TIMPANI_CLK_DIV_SYNC_CTL_GLBL_DIV_SYNC_S 1 +#define TIMPANI_CLK_DIV_SYNC_CTL_GLBL_DIV_SYNC_M 0x2 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CLK_DIV_SYNC_CTL_TX_DIV_SYNC_S 0 +#define TIMPANI_CLK_DIV_SYNC_CTL_TX_DIV_SYNC_M 0x1 +#define TIMPANI_A_CDC_ADC_CLK_EN (0x9F) +#define TIMPANI_CDC_ADC_CLK_EN_RWC "RW" +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_ADC_CLK_EN_POR 0 +#define TIMPANI_CDC_ADC_CLK_EN_S 0 +#define TIMPANI_CDC_ADC_CLK_EN_M 0xF +#define TIMPANI_CDC_ADC_CLK_EN_A_TX2_R_EN_S 3 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_ADC_CLK_EN_A_TX2_R_EN_M 0x8 +#define TIMPANI_CDC_ADC_CLK_EN_A_TX2_L_EN_S 2 +#define TIMPANI_CDC_ADC_CLK_EN_A_TX2_L_EN_M 0x4 +#define TIMPANI_CDC_ADC_CLK_EN_A_TX1_R_EN_S 1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_ADC_CLK_EN_A_TX1_R_EN_M 0x2 +#define TIMPANI_CDC_ADC_CLK_EN_A_TX1_L_EN_S 0 +#define TIMPANI_CDC_ADC_CLK_EN_A_TX1_L_EN_M 0x1 +#define TIMPANI_A_CDC_ST_MIXING (0xA0) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_ST_MIXING_RWC "RW" +#define TIMPANI_CDC_ST_MIXING_POR 0 +#define TIMPANI_CDC_ST_MIXING_S 0 +#define TIMPANI_CDC_ST_MIXING_M 0xF +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_ST_MIXING_TX2_R_S 3 +#define TIMPANI_CDC_ST_MIXING_TX2_R_M 0x8 +#define TIMPANI_CDC_ST_MIXING_TX2_L_S 2 +#define TIMPANI_CDC_ST_MIXING_TX2_L_M 0x4 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_ST_MIXING_TX1_R_S 1 +#define TIMPANI_CDC_ST_MIXING_TX1_R_M 0x2 +#define TIMPANI_CDC_ST_MIXING_TX1_L_S 0 +#define TIMPANI_CDC_ST_MIXING_TX1_L_M 0x1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_A_CDC_RX2_CTL (0xA1) +#define TIMPANI_CDC_RX2_CTL_RWC "RW" +#define TIMPANI_CDC_RX2_CTL_POR 0xc +#define TIMPANI_CDC_RX2_CTL_S 0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_RX2_CTL_M 0x3F +#define TIMPANI_CDC_RX2_CTL_SIDETONE_EN2_R_S 5 +#define TIMPANI_CDC_RX2_CTL_SIDETONE_EN2_R_M 0x20 +#define TIMPANI_CDC_RX2_CTL_SIDETONE_EN2_L_S 4 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_RX2_CTL_SIDETONE_EN2_L_M 0x10 +#define TIMPANI_CDC_RX2_CTL_RX2_RATE_S 2 +#define TIMPANI_CDC_RX2_CTL_RX2_RATE_M 0xC +#define TIMPANI_CDC_RX2_CTL_RX2_RATE_OSR_256 0x3 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_RX2_CTL_RX2_RATE_OSR_128 0x1 +#define TIMPANI_CDC_RX2_CTL_RX2_RATE_OSR_64 0x0 +#define TIMPANI_CDC_RX2_CTL_RX2_I2S_RATE_S 1 +#define TIMPANI_CDC_RX2_CTL_RX2_I2S_RATE_M 0x2 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_RX2_CTL_RX2_I2S_RATE_BR_32 0x1 +#define TIMPANI_CDC_RX2_CTL_RX2_I2S_RATE_BR_64 0x0 +#define TIMPANI_CDC_RX2_CTL_RX2_I2S_MODE_S 0 +#define TIMPANI_CDC_RX2_CTL_RX2_I2S_MODE_M 0x1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_RX2_CTL_RX2_I2S_MODE_MASTER 0x1 +#define TIMPANI_CDC_RX2_CTL_RX2_I2S_MODE_SLAVE 0x0 +#define TIMPANI_A_CDC_ARB_CLK_EN (0xA2) +#define TIMPANI_CDC_ARB_CLK_EN_RWC "RW" +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_ARB_CLK_EN_POR 0 +#define TIMPANI_CDC_ARB_CLK_EN_S 0 +#define TIMPANI_CDC_ARB_CLK_EN_M 0x1 +#define TIMPANI_CDC_ARB_CLK_EN_ARB_CLK_EN_S 0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_ARB_CLK_EN_ARB_CLK_EN_M 0x1 +#define TIMPANI_A_CDC_I2S_CTL2 (0xA3) +#define TIMPANI_CDC_I2S_CTL2_RWC "RW" +#define TIMPANI_CDC_I2S_CTL2_POR 0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_I2S_CTL2_S 0 +#define TIMPANI_CDC_I2S_CTL2_M 0x3F +#define TIMPANI_CDC_I2S_CTL2_TX_I2S_CLK_SEL_S 3 +#define TIMPANI_CDC_I2S_CTL2_TX_I2S_CLK_SEL_M 0x38 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_I2S_CTL2_TX_I2S_CLK_SEL_CLK_DMIC 0x4 +#define TIMPANI_CDC_I2S_CTL2_TX_I2S_CLK_SEL_CLK_TX2_R 0x3 +#define TIMPANI_CDC_I2S_CTL2_TX_I2S_CLK_SEL_CLK_TX2_L 0x2 +#define TIMPANI_CDC_I2S_CTL2_TX_I2S_CLK_SEL_CLK_TX1_R 0x1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_I2S_CTL2_TX_I2S_CLK_SEL_CLK_TX1_L 0x0 +#define TIMPANI_CDC_I2S_CTL2_RX2_I2SCLK_EN_S 2 +#define TIMPANI_CDC_I2S_CTL2_RX2_I2SCLK_EN_M 0x4 +#define TIMPANI_CDC_I2S_CTL2_RX1_I2SCLK_EN_S 1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_I2S_CTL2_RX1_I2SCLK_EN_M 0x2 +#define TIMPANI_CDC_I2S_CTL2_TX_I2SCLK_EN_S 0 +#define TIMPANI_CDC_I2S_CTL2_TX_I2SCLK_EN_M 0x1 +#define TIMPANI_A_CDC_RX2LG (0xA4) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_RX2LG_RWC "RW" +#define TIMPANI_CDC_RX2LG_POR 0xac +#define TIMPANI_CDC_RX2LG_S 0 +#define TIMPANI_CDC_RX2LG_M 0xFF +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_RX2LG_GAIN_S 0 +#define TIMPANI_CDC_RX2LG_GAIN_M 0xFF +#define TIMPANI_A_CDC_RX2RG (0xA5) +#define TIMPANI_CDC_RX2RG_RWC "RW" +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_RX2RG_POR 0xac +#define TIMPANI_CDC_RX2RG_S 0 +#define TIMPANI_CDC_RX2RG_M 0xFF +#define TIMPANI_CDC_RX2RG_GAIN_S 0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_RX2RG_GAIN_M 0xFF +#define TIMPANI_A_CDC_TX2LG (0xA6) +#define TIMPANI_CDC_TX2LG_RWC "RW" +#define TIMPANI_CDC_TX2LG_POR 0xac +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_TX2LG_S 0 +#define TIMPANI_CDC_TX2LG_M 0xFF +#define TIMPANI_CDC_TX2LG_GAIN_S 0 +#define TIMPANI_CDC_TX2LG_GAIN_M 0xFF +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_A_CDC_TX2RG (0xA7) +#define TIMPANI_CDC_TX2RG_RWC "RW" +#define TIMPANI_CDC_TX2RG_POR 0xac +#define TIMPANI_CDC_TX2RG_S 0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_TX2RG_M 0xFF +#define TIMPANI_CDC_TX2RG_GAIN_S 0 +#define TIMPANI_CDC_TX2RG_GAIN_M 0xFF +#define TIMPANI_A_CDC_DMIC_MUX (0xA8) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_DMIC_MUX_RWC "RW" +#define TIMPANI_CDC_DMIC_MUX_POR 0 +#define TIMPANI_CDC_DMIC_MUX_S 0 +#define TIMPANI_CDC_DMIC_MUX_M 0xFF +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_DMIC_MUX_TX2_DMIC_MUX_SEL_R_S 6 +#define TIMPANI_CDC_DMIC_MUX_TX2_DMIC_MUX_SEL_R_M 0xC0 +#define TIMPANI_CDC_DMIC_MUX_TX2_DMIC_MUX_SEL_R_MIC2_DIN_R 0x3 +#define TIMPANI_CDC_DMIC_MUX_TX2_DMIC_MUX_SEL_R_MIC2_DIN_L 0x2 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_DMIC_MUX_TX2_DMIC_MUX_SEL_R_MIC1_DIN_R 0x1 +#define TIMPANI_CDC_DMIC_MUX_TX2_DMIC_MUX_SEL_R_MIC1_DIN_L 0x0 +#define TIMPANI_CDC_DMIC_MUX_TX2_DMIC_MUX_SEL_L_S 4 +#define TIMPANI_CDC_DMIC_MUX_TX2_DMIC_MUX_SEL_L_M 0x30 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_DMIC_MUX_TX2_DMIC_MUX_SEL_L_MIC2_DIN_R 0x3 +#define TIMPANI_CDC_DMIC_MUX_TX2_DMIC_MUX_SEL_L_MIC2_DIN_L 0x2 +#define TIMPANI_CDC_DMIC_MUX_TX2_DMIC_MUX_SEL_L_MIC1_DIN_R 0x1 +#define TIMPANI_CDC_DMIC_MUX_TX2_DMIC_MUX_SEL_L_MIC1_DIN_L 0x0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_DMIC_MUX_TX1_DMIC_MUX_SEL_R_S 2 +#define TIMPANI_CDC_DMIC_MUX_TX1_DMIC_MUX_SEL_R_M 0xC +#define TIMPANI_CDC_DMIC_MUX_TX1_DMIC_MUX_SEL_R_MIC2_DIN_R 0x3 +#define TIMPANI_CDC_DMIC_MUX_TX1_DMIC_MUX_SEL_R_MIC2_DIN_L 0x2 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_DMIC_MUX_TX1_DMIC_MUX_SEL_R_MIC1_DIN_R 0x1 +#define TIMPANI_CDC_DMIC_MUX_TX1_DMIC_MUX_SEL_R_MIC1_DIN_L 0x0 +#define TIMPANI_CDC_DMIC_MUX_TX1_DMIC_MUX_SEL_L_S 0 +#define TIMPANI_CDC_DMIC_MUX_TX1_DMIC_MUX_SEL_L_M 0x3 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_DMIC_MUX_TX1_DMIC_MUX_SEL_L_MIC2_DIN_R 0x3 +#define TIMPANI_CDC_DMIC_MUX_TX1_DMIC_MUX_SEL_L_MIC2_DIN_L 0x2 +#define TIMPANI_CDC_DMIC_MUX_TX1_DMIC_MUX_SEL_L_MIC1_DIN_R 0x1 +#define TIMPANI_CDC_DMIC_MUX_TX1_DMIC_MUX_SEL_L_MIC1_DIN_L 0x0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_A_CDC_ARB_CLK_CTL (0xA9) +#define TIMPANI_CDC_ARB_CLK_CTL_RWC "RW" +#define TIMPANI_CDC_ARB_CLK_CTL_POR 0 +#define TIMPANI_CDC_ARB_CLK_CTL_S 0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_ARB_CLK_CTL_M 0x3 +#define TIMPANI_CDC_ARB_CLK_CTL_ARB_CLK_SEL_S 0 +#define TIMPANI_CDC_ARB_CLK_CTL_ARB_CLK_SEL_M 0x3 +#define TIMPANI_CDC_ARB_CLK_CTL_ARB_CLK_SEL_TX_MCLK 0x0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_ARB_CLK_CTL_ARB_CLK_SEL_RX_MCLK1 0x1 +#define TIMPANI_CDC_ARB_CLK_CTL_ARB_CLK_SEL_RX_MCLK2 0x2 +#define TIMPANI_CDC_ARB_CLK_CTL_ARB_CLK_SEL_TCXO 0x3 +#define TIMPANI_A_CDC_GCTL2 (0xAA) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_GCTL2_RWC "RW" +#define TIMPANI_CDC_GCTL2_POR 0x33 +#define TIMPANI_CDC_GCTL2_S 0 +#define TIMPANI_CDC_GCTL2_M 0xFF +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_GCTL2_TX2_PGA_UPDATE_R_S 7 +#define TIMPANI_CDC_GCTL2_TX2_PGA_UPDATE_R_M 0x80 +#define TIMPANI_CDC_GCTL2_TX2_PGA_UPDATE_L_S 6 +#define TIMPANI_CDC_GCTL2_TX2_PGA_UPDATE_L_M 0x40 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_GCTL2_TX2_PGA_MUTE_EN_R_S 5 +#define TIMPANI_CDC_GCTL2_TX2_PGA_MUTE_EN_R_M 0x20 +#define TIMPANI_CDC_GCTL2_TX2_PGA_MUTE_EN_L_S 4 +#define TIMPANI_CDC_GCTL2_TX2_PGA_MUTE_EN_L_M 0x10 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_GCTL2_RX2_PGA_UPDATE_R_S 3 +#define TIMPANI_CDC_GCTL2_RX2_PGA_UPDATE_R_M 0x8 +#define TIMPANI_CDC_GCTL2_RX2_PGA_UPDATE_L_S 2 +#define TIMPANI_CDC_GCTL2_RX2_PGA_UPDATE_L_M 0x4 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_GCTL2_RX2_PGA_MUTE_EN_R_S 1 +#define TIMPANI_CDC_GCTL2_RX2_PGA_MUTE_EN_R_M 0x2 +#define TIMPANI_CDC_GCTL2_RX2_PGA_MUTE_EN_L_S 0 +#define TIMPANI_CDC_GCTL2_RX2_PGA_MUTE_EN_L_M 0x1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_A_CDC_BYPASS_CTL2 (0xAB) +#define TIMPANI_CDC_BYPASS_CTL2_RWC "RW" +#define TIMPANI_CDC_BYPASS_CTL2_POR 0x2D +#define TIMPANI_CDC_BYPASS_CTL2_S 0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_BYPASS_CTL2_M 0x3F +#define TIMPANI_CDC_BYPASS_CTL2_TX1_DMIC_GAIN_BP_R_S 5 +#define TIMPANI_CDC_BYPASS_CTL2_TX1_DMIC_GAIN_BP_R_M 0x20 +#define TIMPANI_CDC_BYPASS_CTL2_TX1_ADC_GAIN_BP_R_S 4 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_BYPASS_CTL2_TX1_ADC_GAIN_BP_R_M 0x10 +#define TIMPANI_CDC_BYPASS_CTL2_TX1_HPF_BP_R_S 3 +#define TIMPANI_CDC_BYPASS_CTL2_TX1_HPF_BP_R_M 0x8 +#define TIMPANI_CDC_BYPASS_CTL2_TX1_DMIC_GAIN_BP_L_S 2 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_BYPASS_CTL2_TX1_DMIC_GAIN_BP_L_M 0x4 +#define TIMPANI_CDC_BYPASS_CTL2_TX1_ADC_GAIN_BP_L_S 1 +#define TIMPANI_CDC_BYPASS_CTL2_TX1_ADC_GAIN_BP_L_M 0x2 +#define TIMPANI_CDC_BYPASS_CTL2_TX1_HPF_BP_L_S 0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_BYPASS_CTL2_TX1_HPF_BP_L_M 0x1 +#define TIMPANI_A_CDC_BYPASS_CTL3 (0xAC) +#define TIMPANI_CDC_BYPASS_CTL3_RWC "RW" +#define TIMPANI_CDC_BYPASS_CTL3_POR 0x2D +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_BYPASS_CTL3_S 0 +#define TIMPANI_CDC_BYPASS_CTL3_M 0x3F +#define TIMPANI_CDC_BYPASS_CTL3_TX2_DMIC_GAIN_BP_R_S 5 +#define TIMPANI_CDC_BYPASS_CTL3_TX2_DMIC_GAIN_BP_R_M 0x20 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_BYPASS_CTL3_TX2_ADC_GAIN_BP_R_S 4 +#define TIMPANI_CDC_BYPASS_CTL3_TX2_ADC_GAIN_BP_R_M 0x10 +#define TIMPANI_CDC_BYPASS_CTL3_TX2_HPF_BP_R_S 3 +#define TIMPANI_CDC_BYPASS_CTL3_TX2_HPF_BP_R_M 0x8 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_BYPASS_CTL3_TX2_DMIC_GAIN_BP_L_S 2 +#define TIMPANI_CDC_BYPASS_CTL3_TX2_DMIC_GAIN_BP_L_M 0x4 +#define TIMPANI_CDC_BYPASS_CTL3_TX2_ADC_GAIN_BP_L_S 1 +#define TIMPANI_CDC_BYPASS_CTL3_TX2_ADC_GAIN_BP_L_M 0x2 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_BYPASS_CTL3_TX2_HPF_BP_L_S 0 +#define TIMPANI_CDC_BYPASS_CTL3_TX2_HPF_BP_L_M 0x1 +#define TIMPANI_A_CDC_BYPASS_CTL4 (0xAD) +#define TIMPANI_CDC_BYPASS_CTL4_RWC "RW" +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_BYPASS_CTL4_POR 0x2 +#define TIMPANI_CDC_BYPASS_CTL4_S 0 +#define TIMPANI_CDC_BYPASS_CTL4_M 0xF +#define TIMPANI_CDC_BYPASS_CTL4_DITHER_BP_S 3 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_BYPASS_CTL4_DITHER_BP_M 0x8 +#define TIMPANI_CDC_BYPASS_CTL4_DITHER_SHAPE_SEL_S 2 +#define TIMPANI_CDC_BYPASS_CTL4_DITHER_SHAPE_SEL_M 0x4 +#define TIMPANI_CDC_BYPASS_CTL4_DITHER_DLY_SEL_S 1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_BYPASS_CTL4_DITHER_DLY_SEL_M 0x2 +#define TIMPANI_CDC_BYPASS_CTL4_RX2_HPF_BP_S 0 +#define TIMPANI_CDC_BYPASS_CTL4_RX2_HPF_BP_M 0x1 +#define TIMPANI_A_CDC_RX2L_DCOFFSET (0xAE) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_RX2L_DCOFFSET_RWC "RW" +#define TIMPANI_CDC_RX2L_DCOFFSET_POR 0 +#define TIMPANI_CDC_RX2L_DCOFFSET_S 0 +#define TIMPANI_CDC_RX2L_DCOFFSET_M 0xFF +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_RX2L_DCOFFSET_OFFSET_S 0 +#define TIMPANI_CDC_RX2L_DCOFFSET_OFFSET_M 0xFF +#define TIMPANI_A_CDC_RX2R_DCOFFSET (0xAF) +#define TIMPANI_CDC_RX2R_DCOFFSET_RWC "RW" +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_RX2R_DCOFFSET_POR 0 +#define TIMPANI_CDC_RX2R_DCOFFSET_S 0 +#define TIMPANI_CDC_RX2R_DCOFFSET_M 0xFF +#define TIMPANI_CDC_RX2R_DCOFFSET_OFFSET_S 0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_RX2R_DCOFFSET_OFFSET_M 0xFF +#define TIMPANI_A_CDC_RX_MIX_CTL (0xB0) +#define TIMPANI_CDC_RX_MIX_CTL_RWC "RW" +#define TIMPANI_CDC_RX_MIX_CTL_POR 0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_RX_MIX_CTL_S 0 +#define TIMPANI_CDC_RX_MIX_CTL_M 0x3 +#define TIMPANI_CDC_RX_MIX_CTL_RX2TO1_EN_S 1 +#define TIMPANI_CDC_RX_MIX_CTL_RX2TO1_EN_M 0x2 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_RX_MIX_CTL_RX1TO2_EN_S 0 +#define TIMPANI_CDC_RX_MIX_CTL_RX1TO2_EN_M 0x1 +#define TIMPANI_A_CDC_SPARE_CTL (0xB1) +#define TIMPANI_CDC_SPARE_CTL_RWC "RW" +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_SPARE_CTL_POR 0 +#define TIMPANI_CDC_SPARE_CTL_S 0 +#define TIMPANI_CDC_SPARE_CTL_M 0xFF +#define TIMPANI_CDC_SPARE_CTL_CDC_SPARE_S 0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_SPARE_CTL_CDC_SPARE_M 0xFF +#define TIMPANI_A_CDC_TESTMODE2 (0xB2) +#define TIMPANI_CDC_TESTMODE2_RWC "RW" +#define TIMPANI_CDC_TESTMODE2_POR 0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_TESTMODE2_S 0 +#define TIMPANI_CDC_TESTMODE2_M 0x1F +#define TIMPANI_CDC_TESTMODE2_RX2_TEST_EN_R_S 4 +#define TIMPANI_CDC_TESTMODE2_RX2_TEST_EN_R_M 0x10 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_TESTMODE2_RX2_TEST_EN_L_S 3 +#define TIMPANI_CDC_TESTMODE2_RX2_TEST_EN_L_M 0x8 +#define TIMPANI_CDC_TESTMODE2_TX2_TEST_EN_R_S 2 +#define TIMPANI_CDC_TESTMODE2_TX2_TEST_EN_R_M 0x4 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_TESTMODE2_TX2_TEST_EN_L_S 1 +#define TIMPANI_CDC_TESTMODE2_TX2_TEST_EN_L_M 0x2 +#define TIMPANI_CDC_TESTMODE2_A_LOOPBACK_EN2_S 0 +#define TIMPANI_CDC_TESTMODE2_A_LOOPBACK_EN2_M 0x1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_A_CDC_PDM_OE (0xB3) +#define TIMPANI_CDC_PDM_OE_RWC "RW" +#define TIMPANI_CDC_PDM_OE_POR 0 +#define TIMPANI_CDC_PDM_OE_S 0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_PDM_OE_M 0x3F +#define TIMPANI_CDC_PDM_OE_PDM_23_20_OE_S 5 +#define TIMPANI_CDC_PDM_OE_PDM_23_20_OE_M 0x20 +#define TIMPANI_CDC_PDM_OE_PDM_19_16_OE_S 4 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_PDM_OE_PDM_19_16_OE_M 0x10 +#define TIMPANI_CDC_PDM_OE_PDM_15_12_OE_S 3 +#define TIMPANI_CDC_PDM_OE_PDM_15_12_OE_M 0x8 +#define TIMPANI_CDC_PDM_OE_PDM_11_8_OE_S 2 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_PDM_OE_PDM_11_8_OE_M 0x4 +#define TIMPANI_CDC_PDM_OE_PDM_7_4_OE_S 1 +#define TIMPANI_CDC_PDM_OE_PDM_7_4_OE_M 0x2 +#define TIMPANI_CDC_PDM_OE_PDM_3_0_OE_S 0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_PDM_OE_PDM_3_0_OE_M 0x1 +#define TIMPANI_A_CDC_TX1R_STG (0xB4) +#define TIMPANI_CDC_TX1R_STG_RWC "RW" +#define TIMPANI_CDC_TX1R_STG_POR 0xac +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_TX1R_STG_S 0 +#define TIMPANI_CDC_TX1R_STG_M 0xFF +#define TIMPANI_CDC_TX1R_STG_GAIN_S 0 +#define TIMPANI_CDC_TX1R_STG_GAIN_M 0xFF +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_A_CDC_TX2L_STG (0xB5) +#define TIMPANI_CDC_TX2L_STG_RWC "RW" +#define TIMPANI_CDC_TX2L_STG_POR 0xac +#define TIMPANI_CDC_TX2L_STG_S 0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_TX2L_STG_M 0xFF +#define TIMPANI_CDC_TX2L_STG_GAIN_S 0 +#define TIMPANI_CDC_TX2L_STG_GAIN_M 0xFF +#define TIMPANI_A_CDC_TX2R_STG (0xB6) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_TX2R_STG_RWC "RW" +#define TIMPANI_CDC_TX2R_STG_POR 0xac +#define TIMPANI_CDC_TX2R_STG_S 0 +#define TIMPANI_CDC_TX2R_STG_M 0xFF +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_TX2R_STG_GAIN_S 0 +#define TIMPANI_CDC_TX2R_STG_GAIN_M 0xFF +#define TIMPANI_A_CDC_ARB_BYPASS_CTL (0xB7) +#define TIMPANI_CDC_ARB_BYPASS_CTL_RWC "RW" +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_ARB_BYPASS_CTL_POR 0 +#define TIMPANI_CDC_ARB_BYPASS_CTL_S 0 +#define TIMPANI_CDC_ARB_BYPASS_CTL_M 0x1 +#define TIMPANI_CDC_ARB_BYPASS_CTL_ARB_BYPASS_EN_S 0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_ARB_BYPASS_CTL_ARB_BYPASS_EN_M 0x1 +#define TIMPANI_CDC_ARB_BYPASS_CTL_ARB_BYPASS_EN_BYPASS 0x1 +#define TIMPANI_CDC_ARB_BYPASS_CTL_ARB_BYPASS_EN_NO_BYPASS 0x0 +#define TIMPANI_A_CDC_ANC1_CTL1 (0xC0) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_ANC1_CTL1_RWC "RW" +#define TIMPANI_CDC_ANC1_CTL1_POR 0 +#define TIMPANI_CDC_ANC1_CTL1_S 0 +#define TIMPANI_CDC_ANC1_CTL1_M 0x3F +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_ANC1_CTL1_ANC1_FF_OUT_DIS_S 5 +#define TIMPANI_CDC_ANC1_CTL1_ANC1_FF_OUT_DIS_M 0x20 +#define TIMPANI_CDC_ANC1_CTL1_ANC1_FF_OUT_DIS_FF_OUT_DIS 0x1 +#define TIMPANI_CDC_ANC1_CTL1_ANC1_FF_OUT_DIS_FF_OUT_EN 0x0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_ANC1_CTL1_ANC1_ADC_DMIC_SEL_S 4 +#define TIMPANI_CDC_ANC1_CTL1_ANC1_ADC_DMIC_SEL_M 0x10 +#define TIMPANI_CDC_ANC1_CTL1_ANC1_ADC_DMIC_SEL_DMIC 0x1 +#define TIMPANI_CDC_ANC1_CTL1_ANC1_ADC_DMIC_SEL_ADC 0x0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_ANC1_CTL1_ANC1_LR_EN_S 3 +#define TIMPANI_CDC_ANC1_CTL1_ANC1_LR_EN_M 0x8 +#define TIMPANI_CDC_ANC1_CTL1_ANC1_LR_EN_LR_MIX_EN 0x1 +#define TIMPANI_CDC_ANC1_CTL1_ANC1_LR_EN_LR_MIX_DIS 0x0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_ANC1_CTL1_ANC1_FB_EN_S 2 +#define TIMPANI_CDC_ANC1_CTL1_ANC1_FB_EN_M 0x4 +#define TIMPANI_CDC_ANC1_CTL1_ANC1_FB_EN_FB_MIX_EN 0x1 +#define TIMPANI_CDC_ANC1_CTL1_ANC1_FB_EN_FB_MIX_DIS 0x0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_ANC1_CTL1_ANC1_EN_S 1 +#define TIMPANI_CDC_ANC1_CTL1_ANC1_EN_M 0x2 +#define TIMPANI_CDC_ANC1_CTL1_ANC1_EN_ANC_EN 0x1 +#define TIMPANI_CDC_ANC1_CTL1_ANC1_EN_ANC_DIS 0x0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_ANC1_CTL1_ANC1_SOFT_RESET_S 0 +#define TIMPANI_CDC_ANC1_CTL1_ANC1_SOFT_RESET_M 0x1 +#define TIMPANI_CDC_ANC1_CTL1_ANC1_SOFT_RESET_ANC_RESET 0x1 +#define TIMPANI_CDC_ANC1_CTL1_ANC1_SOFT_RESET_ANC_ACTIVE 0x0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_A_CDC_ANC1_CTL2 (0xC1) +#define TIMPANI_CDC_ANC1_CTL2_RWC "RW" +#define TIMPANI_CDC_ANC1_CTL2_POR 0 +#define TIMPANI_CDC_ANC1_CTL2_S 0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_ANC1_CTL2_M 0x1F +#define TIMPANI_CDC_ANC1_CTL2_ANC1_FREQ_SEL_S 0 +#define TIMPANI_CDC_ANC1_CTL2_ANC1_FREQ_SEL_M 0x1F +#define TIMPANI_A_CDC_ANC1_FF_FB_SHIFT (0xC2) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_ANC1_FF_FB_SHIFT_RWC "RW" +#define TIMPANI_CDC_ANC1_FF_FB_SHIFT_POR 0 +#define TIMPANI_CDC_ANC1_FF_FB_SHIFT_S 0 +#define TIMPANI_CDC_ANC1_FF_FB_SHIFT_M 0xFF +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_ANC1_FF_FB_SHIFT_ANC1_FB_LPF_SHIFT_S 4 +#define TIMPANI_CDC_ANC1_FF_FB_SHIFT_ANC1_FB_LPF_SHIFT_M 0xF0 +#define TIMPANI_CDC_ANC1_FF_FB_SHIFT_ANC1_FF_LPF_SHIFT_S 0 +#define TIMPANI_CDC_ANC1_FF_FB_SHIFT_ANC1_FF_LPF_SHIFT_M 0xF +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_A_CDC_ANC1_RX_NS (0xC3) +#define TIMPANI_CDC_ANC1_RX_NS_RWC "RW" +#define TIMPANI_CDC_ANC1_RX_NS_POR 0x1 +#define TIMPANI_CDC_ANC1_RX_NS_S 0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_ANC1_RX_NS_M 0x7 +#define TIMPANI_CDC_ANC1_RX_NS_ANC1_DITHER_BP_S 2 +#define TIMPANI_CDC_ANC1_RX_NS_ANC1_DITHER_BP_M 0x4 +#define TIMPANI_CDC_ANC1_RX_NS_ANC1_DITHER_SHAPE_SEL_S 1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_ANC1_RX_NS_ANC1_DITHER_SHAPE_SEL_M 0x2 +#define TIMPANI_CDC_ANC1_RX_NS_ANC1_DITHER_DLY_SEL_S 0 +#define TIMPANI_CDC_ANC1_RX_NS_ANC1_DITHER_DLY_SEL_M 0x1 +#define TIMPANI_A_CDC_ANC1_SPARE (0xC4) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_ANC1_SPARE_RWC "RW" +#define TIMPANI_CDC_ANC1_SPARE_POR 0 +#define TIMPANI_CDC_ANC1_SPARE_S 0 +#define TIMPANI_CDC_ANC1_SPARE_M 0xFF +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_ANC1_SPARE_ANC1_SPARE_S 0 +#define TIMPANI_CDC_ANC1_SPARE_ANC1_SPARE_M 0xFF +#define TIMPANI_A_CDC_ANC1_IIR_COEFF_PTR (0xC5) +#define TIMPANI_CDC_ANC1_IIR_COEFF_PTR_RWC "RW" +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_ANC1_IIR_COEFF_PTR_POR 0 +#define TIMPANI_CDC_ANC1_IIR_COEFF_PTR_S 0 +#define TIMPANI_CDC_ANC1_IIR_COEFF_PTR_M 0x1F +#define TIMPANI_CDC_ANC1_IIR_COEFF_PTR_ANC1_IIR_COEFF_PTR_S 0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_ANC1_IIR_COEFF_PTR_ANC1_IIR_COEFF_PTR_M 0x1F +#define TIMPANI_A_CDC_ANC1_IIR_COEFF_MSB (0xC6) +#define TIMPANI_CDC_ANC1_IIR_COEFF_MSB_RWC "RW" +#define TIMPANI_CDC_ANC1_IIR_COEFF_MSB_POR 0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_ANC1_IIR_COEFF_MSB_S 0 +#define TIMPANI_CDC_ANC1_IIR_COEFF_MSB_M 0x1 +#define TIMPANI_CDC_ANC1_IIR_COEFF_MSB_ANC1_IIR_COEFF_MSB_S 0 +#define TIMPANI_CDC_ANC1_IIR_COEFF_MSB_ANC1_IIR_COEFF_MSB_M 0x1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_A_CDC_ANC1_IIR_COEFF_LSB (0xC7) +#define TIMPANI_CDC_ANC1_IIR_COEFF_LSB_RWC "RW" +#define TIMPANI_CDC_ANC1_IIR_COEFF_LSB_POR 0 +#define TIMPANI_CDC_ANC1_IIR_COEFF_LSB_S 0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_ANC1_IIR_COEFF_LSB_M 0xFF +#define TIMPANI_CDC_ANC1_IIR_COEFF_LSB_ANC1_IIR_COEFF_LSB_S 0 +#define TIMPANI_CDC_ANC1_IIR_COEFF_LSB_ANC1_IIR_COEFF_LSB_M 0xFF +#define TIMPANI_A_CDC_ANC1_IIR_COEFF_CTL (0xC8) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_ANC1_IIR_COEFF_CTL_RWC "RW" +#define TIMPANI_CDC_ANC1_IIR_COEFF_CTL_POR 0 +#define TIMPANI_CDC_ANC1_IIR_COEFF_CTL_S 0 +#define TIMPANI_CDC_ANC1_IIR_COEFF_CTL_M 0x3 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_ANC1_IIR_COEFF_CTL_ANC1_IIR_COEFF_ADAPTIVE_S 1 +#define TIMPANI_CDC_ANC1_IIR_COEFF_CTL_ANC1_IIR_COEFF_ADAPTIVE_M 0x2 +#define TIMPANI_CDC_ANC1_IIR_COEFF_CTL_ANC1_IIR_COEFF_ADAPTIVE_ADAPTIVE 0x1 +#define TIMPANI_CDC_ANC1_IIR_COEFF_CTL_ANC1_IIR_COEFF_ADAPTIVE_NON_ADAPTIVE 0x0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_ANC1_IIR_COEFF_CTL_ANC1_IIR_COEFF_EN_S 0 +#define TIMPANI_CDC_ANC1_IIR_COEFF_CTL_ANC1_IIR_COEFF_EN_M 0x1 +#define TIMPANI_CDC_ANC1_IIR_COEFF_CTL_ANC1_IIR_COEFF_EN_UPDATE 0x1 +#define TIMPANI_CDC_ANC1_IIR_COEFF_CTL_ANC1_IIR_COEFF_EN_NO_UPDATE 0x0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_A_CDC_ANC1_LPF_COEFF_PTR (0xC9) +#define TIMPANI_CDC_ANC1_LPF_COEFF_PTR_RWC "RW" +#define TIMPANI_CDC_ANC1_LPF_COEFF_PTR_POR 0 +#define TIMPANI_CDC_ANC1_LPF_COEFF_PTR_S 0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_ANC1_LPF_COEFF_PTR_M 0xF +#define TIMPANI_CDC_ANC1_LPF_COEFF_PTR_ANC1_LPF_COEFF_PTR_S 0 +#define TIMPANI_CDC_ANC1_LPF_COEFF_PTR_ANC1_LPF_COEFF_PTR_M 0xF +#define TIMPANI_A_CDC_ANC1_LPF_COEFF_MSB (0xCA) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_ANC1_LPF_COEFF_MSB_RWC "RW" +#define TIMPANI_CDC_ANC1_LPF_COEFF_MSB_POR 0 +#define TIMPANI_CDC_ANC1_LPF_COEFF_MSB_S 0 +#define TIMPANI_CDC_ANC1_LPF_COEFF_MSB_M 0xF +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_ANC1_LPF_COEFF_MSB_ANC1_LPF_COEFF_MSB_S 0 +#define TIMPANI_CDC_ANC1_LPF_COEFF_MSB_ANC1_LPF_COEFF_MSB_M 0xF +#define TIMPANI_A_CDC_ANC1_LPF_COEFF_LSB (0xCB) +#define TIMPANI_CDC_ANC1_LPF_COEFF_LSB_RWC "RW" +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_ANC1_LPF_COEFF_LSB_POR 0 +#define TIMPANI_CDC_ANC1_LPF_COEFF_LSB_S 0 +#define TIMPANI_CDC_ANC1_LPF_COEFF_LSB_M 0xFF +#define TIMPANI_CDC_ANC1_LPF_COEFF_LSB_ANC1_LPF_COEFF_LSB_S 0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_ANC1_LPF_COEFF_LSB_ANC1_LPF_COEFF_LSB_M 0xFF +#define TIMPANI_A_CDC_ANC1_SCALE_PTR (0xCC) +#define TIMPANI_CDC_ANC1_SCALE_PTR_RWC "RW" +#define TIMPANI_CDC_ANC1_SCALE_PTR_POR 0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_ANC1_SCALE_PTR_S 0 +#define TIMPANI_CDC_ANC1_SCALE_PTR_M 0x7 +#define TIMPANI_CDC_ANC1_SCALE_PTR_ANC1_SCALE_PTR_S 0 +#define TIMPANI_CDC_ANC1_SCALE_PTR_ANC1_SCALE_PTR_M 0x7 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_A_CDC_ANC1_SCALE (0xCD) +#define TIMPANI_CDC_ANC1_SCALE_RWC "RW" +#define TIMPANI_CDC_ANC1_SCALE_POR 0 +#define TIMPANI_CDC_ANC1_SCALE_S 0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_ANC1_SCALE_M 0xFF +#define TIMPANI_CDC_ANC1_SCALE_ANC1_SCALE_S 0 +#define TIMPANI_CDC_ANC1_SCALE_ANC1_SCALE_M 0xFF +#define TIMPANI_A_CDC_ANC1_DEBUG (0xCE) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_ANC1_DEBUG_RWC "RW" +#define TIMPANI_CDC_ANC1_DEBUG_POR 0 +#define TIMPANI_CDC_ANC1_DEBUG_S 0 +#define TIMPANI_CDC_ANC1_DEBUG_M 0xF +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_ANC1_DEBUG_ANC1_DEBUG_SEL_S 0 +#define TIMPANI_CDC_ANC1_DEBUG_ANC1_DEBUG_SEL_M 0xF +#define TIMPANI_A_CDC_ANC2_CTL1 (0xD0) +#define TIMPANI_CDC_ANC2_CTL1_RWC "RW" +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_ANC2_CTL1_POR 0 +#define TIMPANI_CDC_ANC2_CTL1_S 0 +#define TIMPANI_CDC_ANC2_CTL1_M 0x3F +#define TIMPANI_CDC_ANC2_CTL1_ANC2_FF_OUT_DIS_S 5 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_ANC2_CTL1_ANC2_FF_OUT_DIS_M 0x20 +#define TIMPANI_CDC_ANC2_CTL1_ANC2_FF_OUT_DIS_FF_OUT_DIS 0x1 +#define TIMPANI_CDC_ANC2_CTL1_ANC2_FF_OUT_DIS_FF_OUT_EN 0x0 +#define TIMPANI_CDC_ANC2_CTL1_ANC2_ADC_DMIC_SEL_S 4 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_ANC2_CTL1_ANC2_ADC_DMIC_SEL_M 0x10 +#define TIMPANI_CDC_ANC2_CTL1_ANC2_ADC_DMIC_SEL_DMIC 0x1 +#define TIMPANI_CDC_ANC2_CTL1_ANC2_ADC_DMIC_SEL_ADC 0x0 +#define TIMPANI_CDC_ANC2_CTL1_ANC2_LR_EN_S 3 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_ANC2_CTL1_ANC2_LR_EN_M 0x8 +#define TIMPANI_CDC_ANC2_CTL1_ANC2_LR_EN_LR_MIX_EN 0x1 +#define TIMPANI_CDC_ANC2_CTL1_ANC2_LR_EN_LR_MIX_DIS 0x0 +#define TIMPANI_CDC_ANC2_CTL1_ANC2_FB_EN_S 2 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_ANC2_CTL1_ANC2_FB_EN_M 0x4 +#define TIMPANI_CDC_ANC2_CTL1_ANC2_FB_EN_FB_MIX_EN 0x1 +#define TIMPANI_CDC_ANC2_CTL1_ANC2_FB_EN_FB_MIX_DIS 0x0 +#define TIMPANI_CDC_ANC2_CTL1_ANC2_EN_S 1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_ANC2_CTL1_ANC2_EN_M 0x2 +#define TIMPANI_CDC_ANC2_CTL1_ANC2_EN_ANC_EN 0x1 +#define TIMPANI_CDC_ANC2_CTL1_ANC2_EN_ANC_DIS 0x0 +#define TIMPANI_CDC_ANC2_CTL1_ANC2_SOFT_RESET_S 0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_ANC2_CTL1_ANC2_SOFT_RESET_M 0x1 +#define TIMPANI_CDC_ANC2_CTL1_ANC2_SOFT_RESET_ANC_RESET 0x1 +#define TIMPANI_CDC_ANC2_CTL1_ANC2_SOFT_RESET_ANC_ACTIVE 0x0 +#define TIMPANI_A_CDC_ANC2_CTL2 (0xD1) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_ANC2_CTL2_RWC "RW" +#define TIMPANI_CDC_ANC2_CTL2_POR 0 +#define TIMPANI_CDC_ANC2_CTL2_S 0 +#define TIMPANI_CDC_ANC2_CTL2_M 0x1F +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_ANC2_CTL2_ANC2_FREQ_SEL_S 0 +#define TIMPANI_CDC_ANC2_CTL2_ANC2_FREQ_SEL_M 0x1F +#define TIMPANI_A_CDC_ANC2_FF_FB_SHIFT (0xD2) +#define TIMPANI_CDC_ANC2_FF_FB_SHIFT_RWC "RW" +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_ANC2_FF_FB_SHIFT_POR 0 +#define TIMPANI_CDC_ANC2_FF_FB_SHIFT_S 0 +#define TIMPANI_CDC_ANC2_FF_FB_SHIFT_M 0xFF +#define TIMPANI_CDC_ANC2_FF_FB_SHIFT_ANC2_FB_LPF_SHIFT_S 4 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_ANC2_FF_FB_SHIFT_ANC2_FB_LPF_SHIFT_M 0xF0 +#define TIMPANI_CDC_ANC2_FF_FB_SHIFT_ANC2_FF_LPF_SHIFT_S 0 +#define TIMPANI_CDC_ANC2_FF_FB_SHIFT_ANC2_FF_LPF_SHIFT_M 0xF +#define TIMPANI_A_CDC_ANC2_RX_NS (0xD3) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_ANC2_RX_NS_RWC "RW" +#define TIMPANI_CDC_ANC2_RX_NS_POR 0x1 +#define TIMPANI_CDC_ANC2_RX_NS_S 0 +#define TIMPANI_CDC_ANC2_RX_NS_M 0x7 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_ANC2_RX_NS_ANC2_DITHER_BP_S 2 +#define TIMPANI_CDC_ANC2_RX_NS_ANC2_DITHER_BP_M 0x4 +#define TIMPANI_CDC_ANC2_RX_NS_ANC2_DITHER_SHAPE_SEL_S 1 +#define TIMPANI_CDC_ANC2_RX_NS_ANC2_DITHER_SHAPE_SEL_M 0x2 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_ANC2_RX_NS_ANC2_DITHER_DLY_SEL_S 0 +#define TIMPANI_CDC_ANC2_RX_NS_ANC2_DITHER_DLY_SEL_M 0x1 +#define TIMPANI_A_CDC_ANC2_SPARE (0xD4) +#define TIMPANI_CDC_ANC2_SPARE_RWC "RW" +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_ANC2_SPARE_POR 0 +#define TIMPANI_CDC_ANC2_SPARE_S 0 +#define TIMPANI_CDC_ANC2_SPARE_M 0xFF +#define TIMPANI_CDC_ANC2_SPARE_ANC2_SPARE_S 0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_ANC2_SPARE_ANC2_SPARE_M 0xFF +#define TIMPANI_A_CDC_ANC2_IIR_COEFF_PTR (0xD5) +#define TIMPANI_CDC_ANC2_IIR_COEFF_PTR_RWC "RW" +#define TIMPANI_CDC_ANC2_IIR_COEFF_PTR_POR 0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_ANC2_IIR_COEFF_PTR_S 0 +#define TIMPANI_CDC_ANC2_IIR_COEFF_PTR_M 0x1F +#define TIMPANI_CDC_ANC2_IIR_COEFF_PTR_ANC2_IIR_COEFF_PTR_S 0 +#define TIMPANI_CDC_ANC2_IIR_COEFF_PTR_ANC2_IIR_COEFF_PTR_M 0x1F +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_A_CDC_ANC2_IIR_COEFF_MSB (0xD6) +#define TIMPANI_CDC_ANC2_IIR_COEFF_MSB_RWC "RW" +#define TIMPANI_CDC_ANC2_IIR_COEFF_MSB_POR 0 +#define TIMPANI_CDC_ANC2_IIR_COEFF_MSB_S 0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_ANC2_IIR_COEFF_MSB_M 0x1 +#define TIMPANI_CDC_ANC2_IIR_COEFF_MSB_ANC2_IIR_COEFF_MSB_S 0 +#define TIMPANI_CDC_ANC2_IIR_COEFF_MSB_ANC2_IIR_COEFF_MSB_M 0x1 +#define TIMPANI_A_CDC_ANC2_IIR_COEFF_LSB (0xD7) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_ANC2_IIR_COEFF_LSB_RWC "RW" +#define TIMPANI_CDC_ANC2_IIR_COEFF_LSB_POR 0 +#define TIMPANI_CDC_ANC2_IIR_COEFF_LSB_S 0 +#define TIMPANI_CDC_ANC2_IIR_COEFF_LSB_M 0xFF +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_ANC2_IIR_COEFF_LSB_ANC2_IIR_COEFF_LSB_S 0 +#define TIMPANI_CDC_ANC2_IIR_COEFF_LSB_ANC2_IIR_COEFF_LSB_M 0xFF +#define TIMPANI_A_CDC_ANC2_IIR_COEFF_CTL (0xD8) +#define TIMPANI_CDC_ANC2_IIR_COEFF_CTL_RWC "RW" +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_ANC2_IIR_COEFF_CTL_POR 0 +#define TIMPANI_CDC_ANC2_IIR_COEFF_CTL_S 0 +#define TIMPANI_CDC_ANC2_IIR_COEFF_CTL_M 0x3 +#define TIMPANI_CDC_ANC2_IIR_COEFF_CTL_ANC2_IIR_COEFF_ADAPTIVE_S 1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_ANC2_IIR_COEFF_CTL_ANC2_IIR_COEFF_ADAPTIVE_M 0x2 +#define TIMPANI_CDC_ANC2_IIR_COEFF_CTL_ANC2_IIR_COEFF_ADAPTIVE_ADAPTIVE 0x1 +#define TIMPANI_CDC_ANC2_IIR_COEFF_CTL_ANC2_IIR_COEFF_ADAPTIVE_NON_ADAPTIVE 0x0 +#define TIMPANI_CDC_ANC2_IIR_COEFF_CTL_ANC2_IIR_COEFF_EN_S 0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_ANC2_IIR_COEFF_CTL_ANC2_IIR_COEFF_EN_M 0x1 +#define TIMPANI_CDC_ANC2_IIR_COEFF_CTL_ANC2_IIR_COEFF_EN_UPDATE 0x1 +#define TIMPANI_CDC_ANC2_IIR_COEFF_CTL_ANC2_IIR_COEFF_EN_NO_UPDATE 0x0 +#define TIMPANI_A_CDC_ANC2_LPF_COEFF_PTR (0xD9) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_ANC2_LPF_COEFF_PTR_RWC "RW" +#define TIMPANI_CDC_ANC2_LPF_COEFF_PTR_POR 0 +#define TIMPANI_CDC_ANC2_LPF_COEFF_PTR_S 0 +#define TIMPANI_CDC_ANC2_LPF_COEFF_PTR_M 0xF +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_ANC2_LPF_COEFF_PTR_ANC2_LPF_COEFF_PTR_S 0 +#define TIMPANI_CDC_ANC2_LPF_COEFF_PTR_ANC2_LPF_COEFF_PTR_M 0xF +#define TIMPANI_A_CDC_ANC2_LPF_COEFF_MSB (0xDA) +#define TIMPANI_CDC_ANC2_LPF_COEFF_MSB_RWC "RW" +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_ANC2_LPF_COEFF_MSB_POR 0 +#define TIMPANI_CDC_ANC2_LPF_COEFF_MSB_S 0 +#define TIMPANI_CDC_ANC2_LPF_COEFF_MSB_M 0xF +#define TIMPANI_CDC_ANC2_LPF_COEFF_MSB_ANC2_LPF_COEFF_MSB_S 0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_ANC2_LPF_COEFF_MSB_ANC2_LPF_COEFF_MSB_M 0xF +#define TIMPANI_A_CDC_ANC2_LPF_COEFF_LSB (0xDB) +#define TIMPANI_CDC_ANC2_LPF_COEFF_LSB_RWC "RW" +#define TIMPANI_CDC_ANC2_LPF_COEFF_LSB_POR 0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_ANC2_LPF_COEFF_LSB_S 0 +#define TIMPANI_CDC_ANC2_LPF_COEFF_LSB_M 0xFF +#define TIMPANI_CDC_ANC2_LPF_COEFF_LSB_ANC2_LPF_COEFF_LSB_S 0 +#define TIMPANI_CDC_ANC2_LPF_COEFF_LSB_ANC2_LPF_COEFF_LSB_M 0xFF +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_A_CDC_ANC2_SCALE_PTR (0xDC) +#define TIMPANI_CDC_ANC2_SCALE_PTR_RWC "RW" +#define TIMPANI_CDC_ANC2_SCALE_PTR_POR 0 +#define TIMPANI_CDC_ANC2_SCALE_PTR_S 0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_ANC2_SCALE_PTR_M 0x7 +#define TIMPANI_CDC_ANC2_SCALE_PTR_ANC2_SCALE_PTR_S 0 +#define TIMPANI_CDC_ANC2_SCALE_PTR_ANC2_SCALE_PTR_M 0x7 +#define TIMPANI_A_CDC_ANC2_SCALE (0xDD) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_ANC2_SCALE_RWC "RW" +#define TIMPANI_CDC_ANC2_SCALE_POR 0 +#define TIMPANI_CDC_ANC2_SCALE_S 0 +#define TIMPANI_CDC_ANC2_SCALE_M 0xFF +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_ANC2_SCALE_ANC2_SCALE_S 0 +#define TIMPANI_CDC_ANC2_SCALE_ANC2_SCALE_M 0xFF +#define TIMPANI_A_CDC_ANC2_DEBUG (0xDE) +#define TIMPANI_CDC_ANC2_DEBUG_RWC "RW" +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_ANC2_DEBUG_POR 0 +#define TIMPANI_CDC_ANC2_DEBUG_S 0 +#define TIMPANI_CDC_ANC2_DEBUG_M 0xF +#define TIMPANI_CDC_ANC2_DEBUG_ANC2_DEBUG_SEL_S 0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_ANC2_DEBUG_ANC2_DEBUG_SEL_M 0xF +#define TIMPANI_A_CDC_LINE_L_AVOL (0xE0) +#define TIMPANI_CDC_LINE_L_AVOL_RWC "RW" +#define TIMPANI_CDC_LINE_L_AVOL_POR 0xac +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_LINE_L_AVOL_S 0 +#define TIMPANI_CDC_LINE_L_AVOL_M 0xFF +#define TIMPANI_CDC_LINE_L_AVOL_USER_GAIN_S 2 +#define TIMPANI_CDC_LINE_L_AVOL_USER_GAIN_M 0xFC +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_LINE_L_AVOL_DUMMY_S 0 +#define TIMPANI_CDC_LINE_L_AVOL_DUMMY_M 0x3 +#define TIMPANI_A_CDC_LINE_R_AVOL (0xE1) +#define TIMPANI_CDC_LINE_R_AVOL_RWC "RW" +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_LINE_R_AVOL_POR 0xac +#define TIMPANI_CDC_LINE_R_AVOL_S 0 +#define TIMPANI_CDC_LINE_R_AVOL_M 0xFF +#define TIMPANI_CDC_LINE_R_AVOL_USER_GAIN_S 2 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_LINE_R_AVOL_USER_GAIN_M 0xFC +#define TIMPANI_CDC_LINE_R_AVOL_DUMMY_S 0 +#define TIMPANI_CDC_LINE_R_AVOL_DUMMY_M 0x3 +#define TIMPANI_A_CDC_HPH_L_AVOL (0xE2) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_HPH_L_AVOL_RWC "RW" +#define TIMPANI_CDC_HPH_L_AVOL_POR 0xae +#define TIMPANI_CDC_HPH_L_AVOL_S 0 +#define TIMPANI_CDC_HPH_L_AVOL_M 0xFF +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_HPH_L_AVOL_USER_GAIN_S 2 +#define TIMPANI_CDC_HPH_L_AVOL_USER_GAIN_M 0xFC +#define TIMPANI_CDC_HPH_L_AVOL_MUTE_S 1 +#define TIMPANI_CDC_HPH_L_AVOL_MUTE_M 0x2 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_HPH_L_AVOL_MUTE_MUTE 0x1 +#define TIMPANI_CDC_HPH_L_AVOL_MUTE_UNMUTE 0x0 +#define TIMPANI_CDC_HPH_L_AVOL_DUMMY_S 0 +#define TIMPANI_CDC_HPH_L_AVOL_DUMMY_M 0x1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_A_CDC_HPH_R_AVOL (0xE3) +#define TIMPANI_CDC_HPH_R_AVOL_RWC "RW" +#define TIMPANI_CDC_HPH_R_AVOL_POR 0xae +#define TIMPANI_CDC_HPH_R_AVOL_S 0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_HPH_R_AVOL_M 0xFF +#define TIMPANI_CDC_HPH_R_AVOL_USER_GAIN_S 2 +#define TIMPANI_CDC_HPH_R_AVOL_USER_GAIN_M 0xFC +#define TIMPANI_CDC_HPH_R_AVOL_MUTE_S 1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_HPH_R_AVOL_MUTE_M 0x2 +#define TIMPANI_CDC_HPH_R_AVOL_MUTE_MUTE 0x1 +#define TIMPANI_CDC_HPH_R_AVOL_MUTE_UNMUTE 0x0 +#define TIMPANI_CDC_HPH_R_AVOL_DUMMY_S 0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_HPH_R_AVOL_DUMMY_M 0x1 +#define TIMPANI_A_CDC_COMP_CTL1 (0xE4) +#define TIMPANI_CDC_COMP_CTL1_RWC "RW" +#define TIMPANI_CDC_COMP_CTL1_POR 0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_COMP_CTL1_S 0 +#define TIMPANI_CDC_COMP_CTL1_M 0xFF +#define TIMPANI_CDC_COMP_CTL1_LO_CLK_EN_S 7 +#define TIMPANI_CDC_COMP_CTL1_LO_CLK_EN_M 0x80 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_COMP_CTL1_HPH_CLK_EN_S 6 +#define TIMPANI_CDC_COMP_CTL1_HPH_CLK_EN_M 0x40 +#define TIMPANI_CDC_COMP_CTL1_LO_SOFT_RESET_S 5 +#define TIMPANI_CDC_COMP_CTL1_LO_SOFT_RESET_M 0x20 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_COMP_CTL1_HPH_SOFT_RESET_S 4 +#define TIMPANI_CDC_COMP_CTL1_HPH_SOFT_RESET_M 0x10 +#define TIMPANI_CDC_COMP_CTL1_LO_R_EN_S 3 +#define TIMPANI_CDC_COMP_CTL1_LO_R_EN_M 0x8 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_COMP_CTL1_LO_L_EN_S 2 +#define TIMPANI_CDC_COMP_CTL1_LO_L_EN_M 0x4 +#define TIMPANI_CDC_COMP_CTL1_HPH_R_EN_S 1 +#define TIMPANI_CDC_COMP_CTL1_HPH_R_EN_M 0x2 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_COMP_CTL1_HPH_L_EN_S 0 +#define TIMPANI_CDC_COMP_CTL1_HPH_L_EN_M 0x1 +#define TIMPANI_A_CDC_COMP_CTL2 (0xE5) +#define TIMPANI_CDC_COMP_CTL2_RWC "RW" +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_COMP_CTL2_POR 0xe +#define TIMPANI_CDC_COMP_CTL2_S 0 +#define TIMPANI_CDC_COMP_CTL2_M 0xF +#define TIMPANI_CDC_COMP_CTL2_LINEOUT_IN_MUX_S 2 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_COMP_CTL2_LINEOUT_IN_MUX_M 0xC +#define TIMPANI_CDC_COMP_CTL2_HPH_IN_MUX_S 0 +#define TIMPANI_CDC_COMP_CTL2_HPH_IN_MUX_M 0x3 +#define TIMPANI_A_CDC_COMP_PEAK_METER (0xE6) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_COMP_PEAK_METER_RWC "RW" +#define TIMPANI_CDC_COMP_PEAK_METER_POR 0x9 +#define TIMPANI_CDC_COMP_PEAK_METER_S 0 +#define TIMPANI_CDC_COMP_PEAK_METER_M 0xF +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_COMP_PEAK_METER_TIME_OUT_S 0 +#define TIMPANI_CDC_COMP_PEAK_METER_TIME_OUT_M 0xF +#define TIMPANI_A_CDC_COMP_LEVEL_METER_CTL1 (0xE7) +#define TIMPANI_CDC_COMP_LEVEL_METER_CTL1_RWC "RW" +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_COMP_LEVEL_METER_CTL1_POR 0x7 +#define TIMPANI_CDC_COMP_LEVEL_METER_CTL1_S 0 +#define TIMPANI_CDC_COMP_LEVEL_METER_CTL1_M 0xF +#define TIMPANI_CDC_COMP_LEVEL_METER_CTL1_DIV_FACTOR_S 0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_COMP_LEVEL_METER_CTL1_DIV_FACTOR_M 0xF +#define TIMPANI_A_CDC_COMP_LEVEL_METER_CTL2 (0xE8) +#define TIMPANI_CDC_COMP_LEVEL_METER_CTL2_RWC "RW" +#define TIMPANI_CDC_COMP_LEVEL_METER_CTL2_POR 0x28 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_COMP_LEVEL_METER_CTL2_S 0 +#define TIMPANI_CDC_COMP_LEVEL_METER_CTL2_M 0xFF +#define TIMPANI_CDC_COMP_LEVEL_METER_CTL2_RESAMPLE_RATE_S 0 +#define TIMPANI_CDC_COMP_LEVEL_METER_CTL2_RESAMPLE_RATE_M 0xFF +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_A_CDC_COMP_ZONE_SELECT (0xE9) +#define TIMPANI_CDC_COMP_ZONE_SELECT_RWC "RW" +#define TIMPANI_CDC_COMP_ZONE_SELECT_POR 0x3b +#define TIMPANI_CDC_COMP_ZONE_SELECT_S 0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_COMP_ZONE_SELECT_M 0x7F +#define TIMPANI_CDC_COMP_ZONE_SELECT_ENTRY_S 3 +#define TIMPANI_CDC_COMP_ZONE_SELECT_ENTRY_M 0x78 +#define TIMPANI_CDC_COMP_ZONE_SELECT_SHIFT_S 0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_COMP_ZONE_SELECT_SHIFT_M 0x7 +#define TIMPANI_A_CDC_COMP_ZC_MSB (0xEA) +#define TIMPANI_CDC_COMP_ZC_MSB_RWC "RW" +#define TIMPANI_CDC_COMP_ZC_MSB_POR 0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_COMP_ZC_MSB_S 0 +#define TIMPANI_CDC_COMP_ZC_MSB_M 0x7 +#define TIMPANI_CDC_COMP_ZC_MSB_DET_WINDOW_S 0 +#define TIMPANI_CDC_COMP_ZC_MSB_DET_WINDOW_M 0x7 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_A_CDC_COMP_ZC_LSB (0xEB) +#define TIMPANI_CDC_COMP_ZC_LSB_RWC "RW" +#define TIMPANI_CDC_COMP_ZC_LSB_POR 0x1f +#define TIMPANI_CDC_COMP_ZC_LSB_S 0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_COMP_ZC_LSB_M 0xFF +#define TIMPANI_CDC_COMP_ZC_LSB_DET_WINDOW_S 0 +#define TIMPANI_CDC_COMP_ZC_LSB_DET_WINDOW_M 0xFF +#define TIMPANI_A_CDC_COMP_SHUT_DOWN (0xEC) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_COMP_SHUT_DOWN_RWC "RW" +#define TIMPANI_CDC_COMP_SHUT_DOWN_POR 0x1b +#define TIMPANI_CDC_COMP_SHUT_DOWN_S 0 +#define TIMPANI_CDC_COMP_SHUT_DOWN_M 0x3F +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_COMP_SHUT_DOWN_HPH_TIMEOUT_S 3 +#define TIMPANI_CDC_COMP_SHUT_DOWN_HPH_TIMEOUT_M 0x38 +#define TIMPANI_CDC_COMP_SHUT_DOWN_LO_TIMEOUT_S 0 +#define TIMPANI_CDC_COMP_SHUT_DOWN_LO_TIMEOUT_M 0x7 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_A_CDC_COMP_SHUT_DOWN_STATUS (0xED) +#define TIMPANI_CDC_COMP_SHUT_DOWN_STATUS_RWC "RW" +#define TIMPANI_CDC_COMP_SHUT_DOWN_STATUS_POR 0 +#define TIMPANI_CDC_COMP_SHUT_DOWN_STATUS_S 0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_COMP_SHUT_DOWN_STATUS_M 0xF +#define TIMPANI_CDC_COMP_SHUT_DOWN_STATUS_LO_R_S 3 +#define TIMPANI_CDC_COMP_SHUT_DOWN_STATUS_LO_R_M 0x8 +#define TIMPANI_CDC_COMP_SHUT_DOWN_STATUS_LO_L_S 2 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_COMP_SHUT_DOWN_STATUS_LO_L_M 0x4 +#define TIMPANI_CDC_COMP_SHUT_DOWN_STATUS_HPH_R_S 1 +#define TIMPANI_CDC_COMP_SHUT_DOWN_STATUS_HPH_R_M 0x2 +#define TIMPANI_CDC_COMP_SHUT_DOWN_STATUS_HPH_L_S 0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_COMP_SHUT_DOWN_STATUS_HPH_L_M 0x1 +#define TIMPANI_A_CDC_COMP_HALT (0xEE) +#define TIMPANI_CDC_COMP_HALT_RWC "RW" +#define TIMPANI_CDC_COMP_HALT_POR 0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TIMPANI_CDC_COMP_HALT_S 0 +#define TIMPANI_CDC_COMP_HALT_M 0x1 +#define TIMPANI_CDC_COMP_HALT_COMPANDER_HALT_S 0 +#define TIMPANI_CDC_COMP_HALT_COMPANDER_HALT_M 0x1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#endif diff --git a/kernel-headers/linux/videodev2.h b/kernel-headers/linux/videodev2.h new file mode 100644 index 0000000..ce5a286 --- /dev/null +++ b/kernel-headers/linux/videodev2.h @@ -0,0 +1,2294 @@ +/**************************************************************************** + **************************************************************************** + *** + *** This header was automatically generated from a Linux kernel header + *** of the same name, to make information necessary for userspace to + *** call into the kernel available to libc. It contains only constants, + *** structures, and macros generated from the original header, and thus, + *** contains no copyrightable information. + *** + *** To edit the content of this header, modify the corresponding + *** source file (e.g. under external/kernel-headers/original/) then + *** run bionic/libc/kernel/tools/update_all.py + *** + *** Any manual change here will be lost the next time this script will + *** be run. You've been warned! + *** + **************************************************************************** + ****************************************************************************/ +#ifndef __LINUX_VIDEODEV2_H +#define __LINUX_VIDEODEV2_H +#include <sys/time.h> +#include <linux/compiler.h> +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#include <linux/ioctl.h> +#include <linux/types.h> +#define VIDEO_MAX_FRAME 32 +#define VIDEO_MAX_PLANES 8 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VID_TYPE_CAPTURE 1 +#define VID_TYPE_TUNER 2 +#define VID_TYPE_TELETEXT 4 +#define VID_TYPE_OVERLAY 8 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VID_TYPE_CHROMAKEY 16 +#define VID_TYPE_CLIPPING 32 +#define VID_TYPE_FRAMERAM 64 +#define VID_TYPE_SCALES 128 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VID_TYPE_MONOCHROME 256 +#define VID_TYPE_SUBCAPTURE 512 +#define VID_TYPE_MPEG_DECODER 1024 +#define VID_TYPE_MPEG_ENCODER 2048 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VID_TYPE_MJPEG_DECODER 4096 +#define VID_TYPE_MJPEG_ENCODER 8192 +#define v4l2_fourcc(a, b, c, d) ((__u32)(a) | ((__u32)(b) << 8) | ((__u32)(c) << 16) | ((__u32)(d) << 24)) +enum v4l2_field { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_FIELD_ANY = 0, + V4L2_FIELD_NONE = 1, + V4L2_FIELD_TOP = 2, + V4L2_FIELD_BOTTOM = 3, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_FIELD_INTERLACED = 4, + V4L2_FIELD_SEQ_TB = 5, + V4L2_FIELD_SEQ_BT = 6, + V4L2_FIELD_ALTERNATE = 7, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_FIELD_INTERLACED_TB = 8, + V4L2_FIELD_INTERLACED_BT = 9, +}; +#define V4L2_FIELD_HAS_TOP(field) ((field) == V4L2_FIELD_TOP || (field) == V4L2_FIELD_INTERLACED || (field) == V4L2_FIELD_INTERLACED_TB || (field) == V4L2_FIELD_INTERLACED_BT || (field) == V4L2_FIELD_SEQ_TB || (field) == V4L2_FIELD_SEQ_BT) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_FIELD_HAS_BOTTOM(field) ((field) == V4L2_FIELD_BOTTOM || (field) == V4L2_FIELD_INTERLACED || (field) == V4L2_FIELD_INTERLACED_TB || (field) == V4L2_FIELD_INTERLACED_BT || (field) == V4L2_FIELD_SEQ_TB || (field) == V4L2_FIELD_SEQ_BT) +#define V4L2_FIELD_HAS_BOTH(field) ((field) == V4L2_FIELD_INTERLACED || (field) == V4L2_FIELD_INTERLACED_TB || (field) == V4L2_FIELD_INTERLACED_BT || (field) == V4L2_FIELD_SEQ_TB || (field) == V4L2_FIELD_SEQ_BT) +enum v4l2_buf_type { + V4L2_BUF_TYPE_VIDEO_CAPTURE = 1, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_BUF_TYPE_VIDEO_OUTPUT = 2, + V4L2_BUF_TYPE_VIDEO_OVERLAY = 3, + V4L2_BUF_TYPE_VBI_CAPTURE = 4, + V4L2_BUF_TYPE_VBI_OUTPUT = 5, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_BUF_TYPE_SLICED_VBI_CAPTURE = 6, + V4L2_BUF_TYPE_SLICED_VBI_OUTPUT = 7, + V4L2_BUF_TYPE_VIDEO_OUTPUT_OVERLAY = 8, + V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE = 9, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE = 10, + V4L2_BUF_TYPE_PRIVATE = 0x80, +}; +#define V4L2_TYPE_IS_MULTIPLANAR(type) ((type) == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE || (type) == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_TYPE_IS_OUTPUT(type) ((type) == V4L2_BUF_TYPE_VIDEO_OUTPUT || (type) == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE || (type) == V4L2_BUF_TYPE_VIDEO_OVERLAY || (type) == V4L2_BUF_TYPE_VIDEO_OUTPUT_OVERLAY || (type) == V4L2_BUF_TYPE_VBI_OUTPUT || (type) == V4L2_BUF_TYPE_SLICED_VBI_OUTPUT) +enum v4l2_tuner_type { + V4L2_TUNER_RADIO = 1, + V4L2_TUNER_ANALOG_TV = 2, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_TUNER_DIGITAL_TV = 3, +}; +enum v4l2_memory { + V4L2_MEMORY_MMAP = 1, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MEMORY_USERPTR = 2, + V4L2_MEMORY_OVERLAY = 3, +}; +enum v4l2_colorspace { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_COLORSPACE_SMPTE170M = 1, + V4L2_COLORSPACE_SMPTE240M = 2, + V4L2_COLORSPACE_REC709 = 3, + V4L2_COLORSPACE_BT878 = 4, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_COLORSPACE_470_SYSTEM_M = 5, + V4L2_COLORSPACE_470_SYSTEM_BG = 6, + V4L2_COLORSPACE_JPEG = 7, + V4L2_COLORSPACE_SRGB = 8, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +enum v4l2_priority { + V4L2_PRIORITY_UNSET = 0, + V4L2_PRIORITY_BACKGROUND = 1, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_PRIORITY_INTERACTIVE = 2, + V4L2_PRIORITY_RECORD = 3, + V4L2_PRIORITY_DEFAULT = V4L2_PRIORITY_INTERACTIVE, +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct v4l2_rect { + __s32 left; + __s32 top; + __s32 width; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __s32 height; +}; +struct v4l2_fract { + __u32 numerator; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u32 denominator; +}; +struct v4l2_capability { + __u8 driver[16]; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u8 card[32]; + __u8 bus_info[32]; + __u32 version; + __u32 capabilities; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u32 device_caps; + __u32 reserved[3]; +}; +#define V4L2_CAP_VIDEO_CAPTURE 0x00000001 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CAP_VIDEO_OUTPUT 0x00000002 +#define V4L2_CAP_VIDEO_OVERLAY 0x00000004 +#define V4L2_CAP_VBI_CAPTURE 0x00000010 +#define V4L2_CAP_VBI_OUTPUT 0x00000020 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CAP_SLICED_VBI_CAPTURE 0x00000040 +#define V4L2_CAP_SLICED_VBI_OUTPUT 0x00000080 +#define V4L2_CAP_RDS_CAPTURE 0x00000100 +#define V4L2_CAP_VIDEO_OUTPUT_OVERLAY 0x00000200 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CAP_HW_FREQ_SEEK 0x00000400 +#define V4L2_CAP_RDS_OUTPUT 0x00000800 +#define V4L2_CAP_VIDEO_CAPTURE_MPLANE 0x00001000 +#define V4L2_CAP_VIDEO_OUTPUT_MPLANE 0x00002000 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CAP_TUNER 0x00010000 +#define V4L2_CAP_AUDIO 0x00020000 +#define V4L2_CAP_RADIO 0x00040000 +#define V4L2_CAP_MODULATOR 0x00080000 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CAP_READWRITE 0x01000000 +#define V4L2_CAP_ASYNCIO 0x02000000 +#define V4L2_CAP_STREAMING 0x04000000 +#define V4L2_CAP_DEVICE_CAPS 0x80000000 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct v4l2_pix_format { + __u32 width; + __u32 height; + __u32 pixelformat; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + enum v4l2_field field; + __u32 bytesperline; + __u32 sizeimage; + enum v4l2_colorspace colorspace; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u32 priv; +}; +#define V4L2_PIX_FMT_RGB332 v4l2_fourcc('R', 'G', 'B', '1') +#define V4L2_PIX_FMT_RGB444 v4l2_fourcc('R', '4', '4', '4') +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_PIX_FMT_RGB555 v4l2_fourcc('R', 'G', 'B', 'O') +#define V4L2_PIX_FMT_RGB565 v4l2_fourcc('R', 'G', 'B', 'P') +#define V4L2_PIX_FMT_RGB555X v4l2_fourcc('R', 'G', 'B', 'Q') +#define V4L2_PIX_FMT_RGB565X v4l2_fourcc('R', 'G', 'B', 'R') +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_PIX_FMT_BGR666 v4l2_fourcc('B', 'G', 'R', 'H') +#define V4L2_PIX_FMT_BGR24 v4l2_fourcc('B', 'G', 'R', '3') +#define V4L2_PIX_FMT_RGB24 v4l2_fourcc('R', 'G', 'B', '3') +#define V4L2_PIX_FMT_BGR32 v4l2_fourcc('B', 'G', 'R', '4') +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_PIX_FMT_RGB32 v4l2_fourcc('R', 'G', 'B', '4') +#define V4L2_PIX_FMT_GREY v4l2_fourcc('G', 'R', 'E', 'Y') +#define V4L2_PIX_FMT_Y4 v4l2_fourcc('Y', '0', '4', ' ') +#define V4L2_PIX_FMT_Y6 v4l2_fourcc('Y', '0', '6', ' ') +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_PIX_FMT_Y10 v4l2_fourcc('Y', '1', '0', ' ') +#define V4L2_PIX_FMT_Y12 v4l2_fourcc('Y', '1', '2', ' ') +#define V4L2_PIX_FMT_Y16 v4l2_fourcc('Y', '1', '6', ' ') +#define V4L2_PIX_FMT_Y10BPACK v4l2_fourcc('Y', '1', '0', 'B') +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_PIX_FMT_PAL8 v4l2_fourcc('P', 'A', 'L', '8') +#define V4L2_PIX_FMT_YVU410 v4l2_fourcc('Y', 'V', 'U', '9') +#define V4L2_PIX_FMT_YVU420 v4l2_fourcc('Y', 'V', '1', '2') +#define V4L2_PIX_FMT_YUYV v4l2_fourcc('Y', 'U', 'Y', 'V') +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_PIX_FMT_YYUV v4l2_fourcc('Y', 'Y', 'U', 'V') +#define V4L2_PIX_FMT_YVYU v4l2_fourcc('Y', 'V', 'Y', 'U') +#define V4L2_PIX_FMT_UYVY v4l2_fourcc('U', 'Y', 'V', 'Y') +#define V4L2_PIX_FMT_VYUY v4l2_fourcc('V', 'Y', 'U', 'Y') +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_PIX_FMT_YUV422P v4l2_fourcc('4', '2', '2', 'P') +#define V4L2_PIX_FMT_YUV411P v4l2_fourcc('4', '1', '1', 'P') +#define V4L2_PIX_FMT_Y41P v4l2_fourcc('Y', '4', '1', 'P') +#define V4L2_PIX_FMT_YUV444 v4l2_fourcc('Y', '4', '4', '4') +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_PIX_FMT_YUV555 v4l2_fourcc('Y', 'U', 'V', 'O') +#define V4L2_PIX_FMT_YUV565 v4l2_fourcc('Y', 'U', 'V', 'P') +#define V4L2_PIX_FMT_YUV32 v4l2_fourcc('Y', 'U', 'V', '4') +#define V4L2_PIX_FMT_YUV410 v4l2_fourcc('Y', 'U', 'V', '9') +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_PIX_FMT_YUV420 v4l2_fourcc('Y', 'U', '1', '2') +#define V4L2_PIX_FMT_HI240 v4l2_fourcc('H', 'I', '2', '4') +#define V4L2_PIX_FMT_HM12 v4l2_fourcc('H', 'M', '1', '2') +#define V4L2_PIX_FMT_M420 v4l2_fourcc('M', '4', '2', '0') +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_PIX_FMT_NV12 v4l2_fourcc('N', 'V', '1', '2') +#define V4L2_PIX_FMT_NV21 v4l2_fourcc('N', 'V', '2', '1') +#define V4L2_PIX_FMT_NV16 v4l2_fourcc('N', 'V', '1', '6') +#define V4L2_PIX_FMT_NV61 v4l2_fourcc('N', 'V', '6', '1') +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_PIX_FMT_NV24 v4l2_fourcc('N', 'V', '2', '4') +#define V4L2_PIX_FMT_NV42 v4l2_fourcc('N', 'V', '4', '2') +#define V4L2_PIX_FMT_NV12M v4l2_fourcc('N', 'M', '1', '2') +#define V4L2_PIX_FMT_NV12MT v4l2_fourcc('T', 'M', '1', '2') +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_PIX_FMT_YUV420M v4l2_fourcc('Y', 'M', '1', '2') +#define V4L2_PIX_FMT_SBGGR8 v4l2_fourcc('B', 'A', '8', '1') +#define V4L2_PIX_FMT_SGBRG8 v4l2_fourcc('G', 'B', 'R', 'G') +#define V4L2_PIX_FMT_SGRBG8 v4l2_fourcc('G', 'R', 'B', 'G') +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_PIX_FMT_SRGGB8 v4l2_fourcc('R', 'G', 'G', 'B') +#define V4L2_PIX_FMT_SBGGR10 v4l2_fourcc('B', 'G', '1', '0') +#define V4L2_PIX_FMT_SGBRG10 v4l2_fourcc('G', 'B', '1', '0') +#define V4L2_PIX_FMT_SGRBG10 v4l2_fourcc('B', 'A', '1', '0') +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_PIX_FMT_SRGGB10 v4l2_fourcc('R', 'G', '1', '0') +#define V4L2_PIX_FMT_SBGGR12 v4l2_fourcc('B', 'G', '1', '2') +#define V4L2_PIX_FMT_SGBRG12 v4l2_fourcc('G', 'B', '1', '2') +#define V4L2_PIX_FMT_SGRBG12 v4l2_fourcc('B', 'A', '1', '2') +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_PIX_FMT_SRGGB12 v4l2_fourcc('R', 'G', '1', '2') +#define V4L2_PIX_FMT_SGRBG10DPCM8 v4l2_fourcc('B', 'D', '1', '0') +#define V4L2_PIX_FMT_SBGGR16 v4l2_fourcc('B', 'Y', 'R', '2') +#define V4L2_PIX_FMT_MJPEG v4l2_fourcc('M', 'J', 'P', 'G') +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_PIX_FMT_JPEG v4l2_fourcc('J', 'P', 'E', 'G') +#define V4L2_PIX_FMT_DV v4l2_fourcc('d', 'v', 's', 'd') +#define V4L2_PIX_FMT_MPEG v4l2_fourcc('M', 'P', 'E', 'G') +#define V4L2_PIX_FMT_H264 v4l2_fourcc('H', '2', '6', '4') +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_PIX_FMT_H264_NO_SC v4l2_fourcc('A', 'V', 'C', '1') +#define V4L2_PIX_FMT_H263 v4l2_fourcc('H', '2', '6', '3') +#define V4L2_PIX_FMT_MPEG1 v4l2_fourcc('M', 'P', 'G', '1') +#define V4L2_PIX_FMT_MPEG2 v4l2_fourcc('M', 'P', 'G', '2') +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_PIX_FMT_MPEG4 v4l2_fourcc('M', 'P', 'G', '4') +#define V4L2_PIX_FMT_XVID v4l2_fourcc('X', 'V', 'I', 'D') +#define V4L2_PIX_FMT_VC1_ANNEX_G v4l2_fourcc('V', 'C', '1', 'G') +#define V4L2_PIX_FMT_VC1_ANNEX_L v4l2_fourcc('V', 'C', '1', 'L') +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_PIX_FMT_DIVX_311 v4l2_fourcc('D', 'I', 'V', '3') +#define V4L2_PIX_FMT_DIVX v4l2_fourcc('D', 'I', 'V', 'X') +#define V4L2_PIX_FMT_VP8 v4l2_fourcc('V', 'P', '8', '0') +#define V4L2_PIX_FMT_HEVC v4l2_fourcc('H', 'E', 'V', 'C') +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_PIX_FMT_CPIA1 v4l2_fourcc('C', 'P', 'I', 'A') +#define V4L2_PIX_FMT_WNVA v4l2_fourcc('W', 'N', 'V', 'A') +#define V4L2_PIX_FMT_SN9C10X v4l2_fourcc('S', '9', '1', '0') +#define V4L2_PIX_FMT_SN9C20X_I420 v4l2_fourcc('S', '9', '2', '0') +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_PIX_FMT_PWC1 v4l2_fourcc('P', 'W', 'C', '1') +#define V4L2_PIX_FMT_PWC2 v4l2_fourcc('P', 'W', 'C', '2') +#define V4L2_PIX_FMT_ET61X251 v4l2_fourcc('E', '6', '2', '5') +#define V4L2_PIX_FMT_SPCA501 v4l2_fourcc('S', '5', '0', '1') +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_PIX_FMT_SPCA505 v4l2_fourcc('S', '5', '0', '5') +#define V4L2_PIX_FMT_SPCA508 v4l2_fourcc('S', '5', '0', '8') +#define V4L2_PIX_FMT_SPCA561 v4l2_fourcc('S', '5', '6', '1') +#define V4L2_PIX_FMT_PAC207 v4l2_fourcc('P', '2', '0', '7') +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_PIX_FMT_MR97310A v4l2_fourcc('M', '3', '1', '0') +#define V4L2_PIX_FMT_JL2005BCD v4l2_fourcc('J', 'L', '2', '0') +#define V4L2_PIX_FMT_SN9C2028 v4l2_fourcc('S', 'O', 'N', 'X') +#define V4L2_PIX_FMT_SQ905C v4l2_fourcc('9', '0', '5', 'C') +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_PIX_FMT_PJPG v4l2_fourcc('P', 'J', 'P', 'G') +#define V4L2_PIX_FMT_OV511 v4l2_fourcc('O', '5', '1', '1') +#define V4L2_PIX_FMT_OV518 v4l2_fourcc('O', '5', '1', '8') +#define V4L2_PIX_FMT_STV0680 v4l2_fourcc('S', '6', '8', '0') +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_PIX_FMT_TM6000 v4l2_fourcc('T', 'M', '6', '0') +#define V4L2_PIX_FMT_CIT_YYVYUY v4l2_fourcc('C', 'I', 'T', 'V') +#define V4L2_PIX_FMT_KONICA420 v4l2_fourcc('K', 'O', 'N', 'I') +#define V4L2_PIX_FMT_JPGL v4l2_fourcc('J', 'P', 'G', 'L') +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_PIX_FMT_SE401 v4l2_fourcc('S', '4', '0', '1') +#define V4L2_PIX_FMT_STATS_COMB v4l2_fourcc('S', 'T', 'C', 'M') +#define V4L2_PIX_FMT_STATS_AE v4l2_fourcc('S', 'T', 'A', 'E') +#define V4L2_PIX_FMT_STATS_AF v4l2_fourcc('S', 'T', 'A', 'F') +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_PIX_FMT_STATS_AWB v4l2_fourcc('S', 'T', 'W', 'B') +#define V4L2_PIX_FMT_STATS_IHST v4l2_fourcc('I', 'H', 'S', 'T') +#define V4L2_PIX_FMT_STATS_CS v4l2_fourcc('S', 'T', 'C', 'S') +#define V4L2_PIX_FMT_STATS_RS v4l2_fourcc('S', 'T', 'R', 'S') +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_PIX_FMT_STATS_BG v4l2_fourcc('S', 'T', 'B', 'G') +#define V4L2_PIX_FMT_STATS_BF v4l2_fourcc('S', 'T', 'B', 'F') +#define V4L2_PIX_FMT_STATS_BHST v4l2_fourcc('B', 'H', 'S', 'T') +struct v4l2_fmtdesc { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u32 index; + enum v4l2_buf_type type; + __u32 flags; + __u8 description[32]; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u32 pixelformat; + __u32 reserved[4]; +}; +#define V4L2_FMT_FLAG_COMPRESSED 0x0001 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_FMT_FLAG_EMULATED 0x0002 +enum v4l2_frmsizetypes { + V4L2_FRMSIZE_TYPE_DISCRETE = 1, + V4L2_FRMSIZE_TYPE_CONTINUOUS = 2, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_FRMSIZE_TYPE_STEPWISE = 3, +}; +struct v4l2_frmsize_discrete { + __u32 width; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u32 height; +}; +struct v4l2_frmsize_stepwise { + __u32 min_width; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u32 max_width; + __u32 step_width; + __u32 min_height; + __u32 max_height; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u32 step_height; +}; +struct v4l2_frmsizeenum { + __u32 index; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u32 pixel_format; + __u32 type; + union { + struct v4l2_frmsize_discrete discrete; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + struct v4l2_frmsize_stepwise stepwise; + }; + __u32 reserved[2]; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +enum v4l2_frmivaltypes { + V4L2_FRMIVAL_TYPE_DISCRETE = 1, + V4L2_FRMIVAL_TYPE_CONTINUOUS = 2, + V4L2_FRMIVAL_TYPE_STEPWISE = 3, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +struct v4l2_frmival_stepwise { + struct v4l2_fract min; + struct v4l2_fract max; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + struct v4l2_fract step; +}; +struct v4l2_frmivalenum { + __u32 index; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u32 pixel_format; + __u32 width; + __u32 height; + __u32 type; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + union { + struct v4l2_fract discrete; + struct v4l2_frmival_stepwise stepwise; + }; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u32 reserved[2]; +}; +struct v4l2_timecode { + __u32 type; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u32 flags; + __u8 frames; + __u8 seconds; + __u8 minutes; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u8 hours; + __u8 userbits[4]; +}; +#define V4L2_TC_TYPE_24FPS 1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_TC_TYPE_25FPS 2 +#define V4L2_TC_TYPE_30FPS 3 +#define V4L2_TC_TYPE_50FPS 4 +#define V4L2_TC_TYPE_60FPS 5 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_TC_FLAG_DROPFRAME 0x0001 +#define V4L2_TC_FLAG_COLORFRAME 0x0002 +#define V4L2_TC_USERBITS_field 0x000C +#define V4L2_TC_USERBITS_USERDEFINED 0x0000 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_TC_USERBITS_8BITCHARS 0x0008 +struct v4l2_jpegcompression { + int quality; + int APPn; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + int APP_len; + char APP_data[60]; + int COM_len; + char COM_data[60]; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u32 jpeg_markers; +#define V4L2_JPEG_MARKER_DHT (1<<3) +#define V4L2_JPEG_MARKER_DQT (1<<4) +#define V4L2_JPEG_MARKER_DRI (1<<5) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_JPEG_MARKER_COM (1<<6) +#define V4L2_JPEG_MARKER_APP (1<<7) +}; +struct v4l2_requestbuffers { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u32 count; + enum v4l2_buf_type type; + enum v4l2_memory memory; + __u32 reserved[2]; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +struct v4l2_plane { + __u32 bytesused; + __u32 length; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + union { + __u32 mem_offset; + unsigned long userptr; + } m; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u32 data_offset; + __u32 reserved[11]; +}; +struct v4l2_buffer { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u32 index; + enum v4l2_buf_type type; + __u32 bytesused; + __u32 flags; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + enum v4l2_field field; + struct timeval timestamp; + struct v4l2_timecode timecode; + __u32 sequence; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + enum v4l2_memory memory; + union { + __u32 offset; + unsigned long userptr; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + struct v4l2_plane *planes; + } m; + __u32 length; + __u32 input; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u32 reserved; +}; +#define V4L2_BUF_FLAG_MAPPED 0x0001 +#define V4L2_BUF_FLAG_QUEUED 0x0002 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_BUF_FLAG_DONE 0x0004 +#define V4L2_BUF_FLAG_KEYFRAME 0x0008 +#define V4L2_BUF_FLAG_PFRAME 0x0010 +#define V4L2_BUF_FLAG_BFRAME 0x0020 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_BUF_FLAG_ERROR 0x0040 +#define V4L2_BUF_FLAG_TIMECODE 0x0100 +#define V4L2_BUF_FLAG_INPUT 0x0200 +#define V4L2_BUF_FLAG_PREPARED 0x0400 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_BUF_FLAG_NO_CACHE_INVALIDATE 0x0800 +#define V4L2_BUF_FLAG_NO_CACHE_CLEAN 0x1000 +#define V4L2_BUF_FLAG_EOS 0x2000 +#define V4L2_QCOM_BUF_FLAG_CODECCONFIG 0x4000 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_QCOM_BUF_FLAG_EOSEQ 0x8000 +#define V4L2_QCOM_BUF_TIMESTAMP_INVALID 0x10000 +#define V4L2_QCOM_BUF_FLAG_IDRFRAME 0x20000 +#define V4L2_QCOM_BUF_FLAG_DECODEONLY 0x40000 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_QCOM_BUF_DATA_CORRUPT 0x80000 +#define V4L2_QCOM_BUF_DROP_FRAME 0x100000 +#define V4L2_QCOM_BUF_INPUT_UNSUPPORTED 0x200000 +#define V4L2_QCOM_BUF_FLAG_READONLY 0x400000 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct v4l2_framebuffer { + __u32 capability; + __u32 flags; + void *base; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + struct v4l2_pix_format fmt; +}; +#define V4L2_FBUF_CAP_EXTERNOVERLAY 0x0001 +#define V4L2_FBUF_CAP_CHROMAKEY 0x0002 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_FBUF_CAP_LIST_CLIPPING 0x0004 +#define V4L2_FBUF_CAP_BITMAP_CLIPPING 0x0008 +#define V4L2_FBUF_CAP_LOCAL_ALPHA 0x0010 +#define V4L2_FBUF_CAP_GLOBAL_ALPHA 0x0020 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_FBUF_CAP_LOCAL_INV_ALPHA 0x0040 +#define V4L2_FBUF_CAP_SRC_CHROMAKEY 0x0080 +#define V4L2_FBUF_FLAG_PRIMARY 0x0001 +#define V4L2_FBUF_FLAG_OVERLAY 0x0002 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_FBUF_FLAG_CHROMAKEY 0x0004 +#define V4L2_FBUF_FLAG_LOCAL_ALPHA 0x0008 +#define V4L2_FBUF_FLAG_GLOBAL_ALPHA 0x0010 +#define V4L2_FBUF_FLAG_LOCAL_INV_ALPHA 0x0020 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_FBUF_FLAG_SRC_CHROMAKEY 0x0040 +struct v4l2_clip { + struct v4l2_rect c; + struct v4l2_clip __user *next; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +struct v4l2_window { + struct v4l2_rect w; + enum v4l2_field field; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u32 chromakey; + struct v4l2_clip __user *clips; + __u32 clipcount; + void __user *bitmap; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u8 global_alpha; +}; +struct v4l2_captureparm { + __u32 capability; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u32 capturemode; + struct v4l2_fract timeperframe; + __u32 extendedmode; + __u32 readbuffers; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u32 reserved[4]; +}; +#define V4L2_MODE_HIGHQUALITY 0x0001 +#define V4L2_CAP_TIMEPERFRAME 0x1000 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CAP_QCOM_FRAMESKIP 0x2000 +struct v4l2_qcom_frameskip { + __u64 maxframeinterval; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct v4l2_outputparm { + __u32 capability; + __u32 outputmode; + struct v4l2_fract timeperframe; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u32 extendedmode; + __u32 writebuffers; + __u32 reserved[4]; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct v4l2_cropcap { + enum v4l2_buf_type type; + struct v4l2_rect bounds; + struct v4l2_rect defrect; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + struct v4l2_fract pixelaspect; +}; +struct v4l2_crop { + enum v4l2_buf_type type; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + struct v4l2_rect c; +}; +#define V4L2_SEL_FLAG_GE 0x00000001 +#define V4L2_SEL_FLAG_LE 0x00000002 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_SEL_TGT_CROP_ACTIVE 0x0000 +#define V4L2_SEL_TGT_CROP_DEFAULT 0x0001 +#define V4L2_SEL_TGT_CROP_BOUNDS 0x0002 +#define V4L2_SEL_TGT_COMPOSE_ACTIVE 0x0100 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_SEL_TGT_COMPOSE_DEFAULT 0x0101 +#define V4L2_SEL_TGT_COMPOSE_BOUNDS 0x0102 +#define V4L2_SEL_TGT_COMPOSE_PADDED 0x0103 +struct v4l2_selection { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u32 type; + __u32 target; + __u32 flags; + struct v4l2_rect r; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u32 reserved[9]; +}; +typedef __u64 v4l2_std_id; +#define V4L2_STD_PAL_B ((v4l2_std_id)0x00000001) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_STD_PAL_B1 ((v4l2_std_id)0x00000002) +#define V4L2_STD_PAL_G ((v4l2_std_id)0x00000004) +#define V4L2_STD_PAL_H ((v4l2_std_id)0x00000008) +#define V4L2_STD_PAL_I ((v4l2_std_id)0x00000010) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_STD_PAL_D ((v4l2_std_id)0x00000020) +#define V4L2_STD_PAL_D1 ((v4l2_std_id)0x00000040) +#define V4L2_STD_PAL_K ((v4l2_std_id)0x00000080) +#define V4L2_STD_PAL_M ((v4l2_std_id)0x00000100) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_STD_PAL_N ((v4l2_std_id)0x00000200) +#define V4L2_STD_PAL_Nc ((v4l2_std_id)0x00000400) +#define V4L2_STD_PAL_60 ((v4l2_std_id)0x00000800) +#define V4L2_STD_NTSC_M ((v4l2_std_id)0x00001000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_STD_NTSC_M_JP ((v4l2_std_id)0x00002000) +#define V4L2_STD_NTSC_443 ((v4l2_std_id)0x00004000) +#define V4L2_STD_NTSC_M_KR ((v4l2_std_id)0x00008000) +#define V4L2_STD_SECAM_B ((v4l2_std_id)0x00010000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_STD_SECAM_D ((v4l2_std_id)0x00020000) +#define V4L2_STD_SECAM_G ((v4l2_std_id)0x00040000) +#define V4L2_STD_SECAM_H ((v4l2_std_id)0x00080000) +#define V4L2_STD_SECAM_K ((v4l2_std_id)0x00100000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_STD_SECAM_K1 ((v4l2_std_id)0x00200000) +#define V4L2_STD_SECAM_L ((v4l2_std_id)0x00400000) +#define V4L2_STD_SECAM_LC ((v4l2_std_id)0x00800000) +#define V4L2_STD_ATSC_8_VSB ((v4l2_std_id)0x01000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_STD_ATSC_16_VSB ((v4l2_std_id)0x02000000) +#define V4L2_STD_NTSC (V4L2_STD_NTSC_M | V4L2_STD_NTSC_M_JP | V4L2_STD_NTSC_M_KR) +#define V4L2_STD_SECAM_DK (V4L2_STD_SECAM_D | V4L2_STD_SECAM_K | V4L2_STD_SECAM_K1) +#define V4L2_STD_SECAM (V4L2_STD_SECAM_B | V4L2_STD_SECAM_G | V4L2_STD_SECAM_H | V4L2_STD_SECAM_DK | V4L2_STD_SECAM_L | V4L2_STD_SECAM_LC) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_STD_PAL_BG (V4L2_STD_PAL_B | V4L2_STD_PAL_B1 | V4L2_STD_PAL_G) +#define V4L2_STD_PAL_DK (V4L2_STD_PAL_D | V4L2_STD_PAL_D1 | V4L2_STD_PAL_K) +#define V4L2_STD_PAL (V4L2_STD_PAL_BG | V4L2_STD_PAL_DK | V4L2_STD_PAL_H | V4L2_STD_PAL_I) +#define V4L2_STD_B (V4L2_STD_PAL_B | V4L2_STD_PAL_B1 | V4L2_STD_SECAM_B) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_STD_G (V4L2_STD_PAL_G | V4L2_STD_SECAM_G) +#define V4L2_STD_H (V4L2_STD_PAL_H | V4L2_STD_SECAM_H) +#define V4L2_STD_L (V4L2_STD_SECAM_L | V4L2_STD_SECAM_LC) +#define V4L2_STD_GH (V4L2_STD_G | V4L2_STD_H) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_STD_DK (V4L2_STD_PAL_DK | V4L2_STD_SECAM_DK) +#define V4L2_STD_BG (V4L2_STD_B | V4L2_STD_G) +#define V4L2_STD_MN (V4L2_STD_PAL_M | V4L2_STD_PAL_N | V4L2_STD_PAL_Nc | V4L2_STD_NTSC) +#define V4L2_STD_MTS (V4L2_STD_NTSC_M | V4L2_STD_PAL_M | V4L2_STD_PAL_N | V4L2_STD_PAL_Nc) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_STD_525_60 (V4L2_STD_PAL_M | V4L2_STD_PAL_60 | V4L2_STD_NTSC | V4L2_STD_NTSC_443) +#define V4L2_STD_625_50 (V4L2_STD_PAL | V4L2_STD_PAL_N | V4L2_STD_PAL_Nc | V4L2_STD_SECAM) +#define V4L2_STD_ATSC (V4L2_STD_ATSC_8_VSB | V4L2_STD_ATSC_16_VSB) +#define V4L2_STD_UNKNOWN 0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_STD_ALL (V4L2_STD_525_60 | V4L2_STD_625_50) +struct v4l2_standard { + __u32 index; + v4l2_std_id id; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u8 name[24]; + struct v4l2_fract frameperiod; + __u32 framelines; + __u32 reserved[4]; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +struct v4l2_dv_preset { + __u32 preset; + __u32 reserved[4]; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +struct v4l2_dv_enum_preset { + __u32 index; + __u32 preset; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u8 name[32]; + __u32 width; + __u32 height; + __u32 reserved[4]; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +#define V4L2_DV_INVALID 0 +#define V4L2_DV_480P59_94 1 +#define V4L2_DV_576P50 2 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_DV_720P24 3 +#define V4L2_DV_720P25 4 +#define V4L2_DV_720P30 5 +#define V4L2_DV_720P50 6 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_DV_720P59_94 7 +#define V4L2_DV_720P60 8 +#define V4L2_DV_1080I29_97 9 +#define V4L2_DV_1080I30 10 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_DV_1080I25 11 +#define V4L2_DV_1080I50 12 +#define V4L2_DV_1080I60 13 +#define V4L2_DV_1080P24 14 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_DV_1080P25 15 +#define V4L2_DV_1080P30 16 +#define V4L2_DV_1080P50 17 +#define V4L2_DV_1080P60 18 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct v4l2_bt_timings { + __u32 width; + __u32 height; + __u32 interlaced; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u32 polarities; + __u64 pixelclock; + __u32 hfrontporch; + __u32 hsync; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u32 hbackporch; + __u32 vfrontporch; + __u32 vsync; + __u32 vbackporch; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u32 il_vfrontporch; + __u32 il_vsync; + __u32 il_vbackporch; + __u32 reserved[16]; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +} __attribute__ ((packed)); +#define V4L2_DV_PROGRESSIVE 0 +#define V4L2_DV_INTERLACED 1 +#define V4L2_DV_VSYNC_POS_POL 0x00000001 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_DV_HSYNC_POS_POL 0x00000002 +struct v4l2_dv_timings { + __u32 type; + union { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + struct v4l2_bt_timings bt; + __u32 reserved[32]; + }; +} __attribute__ ((packed)); +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_DV_BT_656_1120 0 +struct v4l2_input { + __u32 index; + __u8 name[32]; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u32 type; + __u32 audioset; + __u32 tuner; + v4l2_std_id std; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u32 status; + __u32 capabilities; + __u32 reserved[3]; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_INPUT_TYPE_TUNER 1 +#define V4L2_INPUT_TYPE_CAMERA 2 +#define V4L2_IN_ST_NO_POWER 0x00000001 +#define V4L2_IN_ST_NO_SIGNAL 0x00000002 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_IN_ST_NO_COLOR 0x00000004 +#define V4L2_IN_ST_HFLIP 0x00000010 +#define V4L2_IN_ST_VFLIP 0x00000020 +#define V4L2_IN_ST_NO_H_LOCK 0x00000100 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_IN_ST_COLOR_KILL 0x00000200 +#define V4L2_IN_ST_NO_SYNC 0x00010000 +#define V4L2_IN_ST_NO_EQU 0x00020000 +#define V4L2_IN_ST_NO_CARRIER 0x00040000 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_IN_ST_MACROVISION 0x01000000 +#define V4L2_IN_ST_NO_ACCESS 0x02000000 +#define V4L2_IN_ST_VTR 0x04000000 +#define V4L2_IN_CAP_PRESETS 0x00000001 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_IN_CAP_CUSTOM_TIMINGS 0x00000002 +#define V4L2_IN_CAP_STD 0x00000004 +struct v4l2_output { + __u32 index; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u8 name[32]; + __u32 type; + __u32 audioset; + __u32 modulator; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + v4l2_std_id std; + __u32 capabilities; + __u32 reserved[3]; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_OUTPUT_TYPE_MODULATOR 1 +#define V4L2_OUTPUT_TYPE_ANALOG 2 +#define V4L2_OUTPUT_TYPE_ANALOGVGAOVERLAY 3 +#define V4L2_OUT_CAP_PRESETS 0x00000001 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_OUT_CAP_CUSTOM_TIMINGS 0x00000002 +#define V4L2_OUT_CAP_STD 0x00000004 +struct v4l2_control { + __u32 id; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __s32 value; +}; +struct v4l2_ext_control { + __u32 id; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u32 size; + __u32 reserved2[1]; + union { + __s32 value; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __s64 value64; + char *string; + }; +} __attribute__ ((packed)); +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct v4l2_ext_controls { + __u32 ctrl_class; + __u32 count; + __u32 error_idx; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u32 reserved[2]; + struct v4l2_ext_control *controls; +}; +#define V4L2_CTRL_CLASS_USER 0x00980000 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CTRL_CLASS_MPEG 0x00990000 +#define V4L2_CTRL_CLASS_CAMERA 0x009a0000 +#define V4L2_CTRL_CLASS_FM_TX 0x009b0000 +#define V4L2_CTRL_CLASS_FLASH 0x009c0000 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CTRL_CLASS_JPEG 0x009d0000 +#define V4L2_CTRL_ID_MASK (0x0fffffff) +#define V4L2_CTRL_ID2CLASS(id) ((id) & 0x0fff0000UL) +#define V4L2_CTRL_DRIVER_PRIV(id) (((id) & 0xffff) >= 0x1000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +enum v4l2_ctrl_type { + V4L2_CTRL_TYPE_INTEGER = 1, + V4L2_CTRL_TYPE_BOOLEAN = 2, + V4L2_CTRL_TYPE_MENU = 3, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_CTRL_TYPE_BUTTON = 4, + V4L2_CTRL_TYPE_INTEGER64 = 5, + V4L2_CTRL_TYPE_CTRL_CLASS = 6, + V4L2_CTRL_TYPE_STRING = 7, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_CTRL_TYPE_BITMASK = 8, +}; +struct v4l2_queryctrl { + __u32 id; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + enum v4l2_ctrl_type type; + __u8 name[32]; + __s32 minimum; + __s32 maximum; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __s32 step; + __s32 default_value; + __u32 flags; + __u32 reserved[2]; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +struct v4l2_querymenu { + __u32 id; + __u32 index; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u8 name[32]; + __u32 reserved; +}; +#define V4L2_CTRL_FLAG_DISABLED 0x0001 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CTRL_FLAG_GRABBED 0x0002 +#define V4L2_CTRL_FLAG_READ_ONLY 0x0004 +#define V4L2_CTRL_FLAG_UPDATE 0x0008 +#define V4L2_CTRL_FLAG_INACTIVE 0x0010 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CTRL_FLAG_SLIDER 0x0020 +#define V4L2_CTRL_FLAG_WRITE_ONLY 0x0040 +#define V4L2_CTRL_FLAG_VOLATILE 0x0080 +#define V4L2_CTRL_FLAG_NEXT_CTRL 0x80000000 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_MAX_CTRLS 1024 +#define V4L2_CID_BASE (V4L2_CTRL_CLASS_USER | 0x900) +#define V4L2_CID_USER_BASE V4L2_CID_BASE +#define V4L2_CID_PRIVATE_BASE 0x08000000 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_USER_CLASS (V4L2_CTRL_CLASS_USER | 1) +#define V4L2_CID_BRIGHTNESS (V4L2_CID_BASE+0) +#define V4L2_CID_CONTRAST (V4L2_CID_BASE+1) +#define V4L2_CID_SATURATION (V4L2_CID_BASE+2) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_HUE (V4L2_CID_BASE+3) +#define V4L2_CID_AUDIO_VOLUME (V4L2_CID_BASE+5) +#define V4L2_CID_AUDIO_BALANCE (V4L2_CID_BASE+6) +#define V4L2_CID_AUDIO_BASS (V4L2_CID_BASE+7) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_AUDIO_TREBLE (V4L2_CID_BASE+8) +#define V4L2_CID_AUDIO_MUTE (V4L2_CID_BASE+9) +#define V4L2_CID_AUDIO_LOUDNESS (V4L2_CID_BASE+10) +#define V4L2_CID_BLACK_LEVEL (V4L2_CID_BASE+11) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_AUTO_WHITE_BALANCE (V4L2_CID_BASE+12) +#define V4L2_CID_DO_WHITE_BALANCE (V4L2_CID_BASE+13) +#define V4L2_CID_RED_BALANCE (V4L2_CID_BASE+14) +#define V4L2_CID_BLUE_BALANCE (V4L2_CID_BASE+15) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_GAMMA (V4L2_CID_BASE+16) +#define V4L2_CID_WHITENESS (V4L2_CID_GAMMA) +#define V4L2_CID_EXPOSURE (V4L2_CID_BASE+17) +#define V4L2_CID_AUTOGAIN (V4L2_CID_BASE+18) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_GAIN (V4L2_CID_BASE+19) +#define V4L2_CID_HFLIP (V4L2_CID_BASE+20) +#define V4L2_CID_VFLIP (V4L2_CID_BASE+21) +#define V4L2_CID_HCENTER (V4L2_CID_BASE+22) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_VCENTER (V4L2_CID_BASE+23) +#define V4L2_CID_POWER_LINE_FREQUENCY (V4L2_CID_BASE+24) +enum v4l2_power_line_frequency { + V4L2_CID_POWER_LINE_FREQUENCY_DISABLED = 0, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_CID_POWER_LINE_FREQUENCY_50HZ = 1, + V4L2_CID_POWER_LINE_FREQUENCY_60HZ = 2, + V4L2_CID_POWER_LINE_FREQUENCY_AUTO = 3, +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_HUE_AUTO (V4L2_CID_BASE+25) +#define V4L2_CID_WHITE_BALANCE_TEMPERATURE (V4L2_CID_BASE+26) +#define V4L2_CID_SHARPNESS (V4L2_CID_BASE+27) +#define V4L2_CID_BACKLIGHT_COMPENSATION (V4L2_CID_BASE+28) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_CHROMA_AGC (V4L2_CID_BASE+29) +#define V4L2_CID_COLOR_KILLER (V4L2_CID_BASE+30) +#define V4L2_CID_COLORFX (V4L2_CID_BASE+31) +enum v4l2_colorfx { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_COLORFX_NONE = 0, + V4L2_COLORFX_BW = 1, + V4L2_COLORFX_SEPIA = 2, + V4L2_COLORFX_NEGATIVE = 3, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_COLORFX_EMBOSS = 4, + V4L2_COLORFX_SKETCH = 5, + V4L2_COLORFX_SKY_BLUE = 6, + V4L2_COLORFX_GRASS_GREEN = 7, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_COLORFX_SKIN_WHITEN = 8, + V4L2_COLORFX_VIVID = 9, +}; +#define V4L2_CID_AUTOBRIGHTNESS (V4L2_CID_BASE+32) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_BAND_STOP_FILTER (V4L2_CID_BASE+33) +#define V4L2_CID_ROTATE (V4L2_CID_BASE+34) +#define V4L2_CID_BG_COLOR (V4L2_CID_BASE+35) +#define V4L2_CID_CHROMA_GAIN (V4L2_CID_BASE+36) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_ILLUMINATORS_1 (V4L2_CID_BASE+37) +#define V4L2_CID_ILLUMINATORS_2 (V4L2_CID_BASE+38) +#define V4L2_CID_MIN_BUFFERS_FOR_CAPTURE (V4L2_CID_BASE+39) +#define V4L2_CID_MIN_BUFFERS_FOR_OUTPUT (V4L2_CID_BASE+40) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_ALPHA_COMPONENT (V4L2_CID_BASE+41) +#define V4L2_CID_LASTP1 (V4L2_CID_BASE+42) +#define V4L2_CID_SPECIAL_EFFECT (V4L2_CID_BASE+43) +#define V4L2_CID_MPEG_BASE (V4L2_CTRL_CLASS_MPEG | 0x900) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_MPEG_CLASS (V4L2_CTRL_CLASS_MPEG | 1) +#define V4L2_CID_MPEG_STREAM_TYPE (V4L2_CID_MPEG_BASE+0) +enum v4l2_mpeg_stream_type { + V4L2_MPEG_STREAM_TYPE_MPEG2_PS = 0, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_STREAM_TYPE_MPEG2_TS = 1, + V4L2_MPEG_STREAM_TYPE_MPEG1_SS = 2, + V4L2_MPEG_STREAM_TYPE_MPEG2_DVD = 3, + V4L2_MPEG_STREAM_TYPE_MPEG1_VCD = 4, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_STREAM_TYPE_MPEG2_SVCD = 5, +}; +#define V4L2_CID_MPEG_STREAM_PID_PMT (V4L2_CID_MPEG_BASE+1) +#define V4L2_CID_MPEG_STREAM_PID_AUDIO (V4L2_CID_MPEG_BASE+2) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_MPEG_STREAM_PID_VIDEO (V4L2_CID_MPEG_BASE+3) +#define V4L2_CID_MPEG_STREAM_PID_PCR (V4L2_CID_MPEG_BASE+4) +#define V4L2_CID_MPEG_STREAM_PES_ID_AUDIO (V4L2_CID_MPEG_BASE+5) +#define V4L2_CID_MPEG_STREAM_PES_ID_VIDEO (V4L2_CID_MPEG_BASE+6) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_MPEG_STREAM_VBI_FMT (V4L2_CID_MPEG_BASE+7) +enum v4l2_mpeg_stream_vbi_fmt { + V4L2_MPEG_STREAM_VBI_FMT_NONE = 0, + V4L2_MPEG_STREAM_VBI_FMT_IVTV = 1, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +#define V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ (V4L2_CID_MPEG_BASE+100) +enum v4l2_mpeg_audio_sampling_freq { + V4L2_MPEG_AUDIO_SAMPLING_FREQ_44100 = 0, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000 = 1, + V4L2_MPEG_AUDIO_SAMPLING_FREQ_32000 = 2, +}; +#define V4L2_CID_MPEG_AUDIO_ENCODING (V4L2_CID_MPEG_BASE+101) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +enum v4l2_mpeg_audio_encoding { + V4L2_MPEG_AUDIO_ENCODING_LAYER_1 = 0, + V4L2_MPEG_AUDIO_ENCODING_LAYER_2 = 1, + V4L2_MPEG_AUDIO_ENCODING_LAYER_3 = 2, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_AUDIO_ENCODING_AAC = 3, + V4L2_MPEG_AUDIO_ENCODING_AC3 = 4, +}; +#define V4L2_CID_MPEG_AUDIO_L1_BITRATE (V4L2_CID_MPEG_BASE+102) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +enum v4l2_mpeg_audio_l1_bitrate { + V4L2_MPEG_AUDIO_L1_BITRATE_32K = 0, + V4L2_MPEG_AUDIO_L1_BITRATE_64K = 1, + V4L2_MPEG_AUDIO_L1_BITRATE_96K = 2, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_AUDIO_L1_BITRATE_128K = 3, + V4L2_MPEG_AUDIO_L1_BITRATE_160K = 4, + V4L2_MPEG_AUDIO_L1_BITRATE_192K = 5, + V4L2_MPEG_AUDIO_L1_BITRATE_224K = 6, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_AUDIO_L1_BITRATE_256K = 7, + V4L2_MPEG_AUDIO_L1_BITRATE_288K = 8, + V4L2_MPEG_AUDIO_L1_BITRATE_320K = 9, + V4L2_MPEG_AUDIO_L1_BITRATE_352K = 10, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_AUDIO_L1_BITRATE_384K = 11, + V4L2_MPEG_AUDIO_L1_BITRATE_416K = 12, + V4L2_MPEG_AUDIO_L1_BITRATE_448K = 13, +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_MPEG_AUDIO_L2_BITRATE (V4L2_CID_MPEG_BASE+103) +enum v4l2_mpeg_audio_l2_bitrate { + V4L2_MPEG_AUDIO_L2_BITRATE_32K = 0, + V4L2_MPEG_AUDIO_L2_BITRATE_48K = 1, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_AUDIO_L2_BITRATE_56K = 2, + V4L2_MPEG_AUDIO_L2_BITRATE_64K = 3, + V4L2_MPEG_AUDIO_L2_BITRATE_80K = 4, + V4L2_MPEG_AUDIO_L2_BITRATE_96K = 5, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_AUDIO_L2_BITRATE_112K = 6, + V4L2_MPEG_AUDIO_L2_BITRATE_128K = 7, + V4L2_MPEG_AUDIO_L2_BITRATE_160K = 8, + V4L2_MPEG_AUDIO_L2_BITRATE_192K = 9, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_AUDIO_L2_BITRATE_224K = 10, + V4L2_MPEG_AUDIO_L2_BITRATE_256K = 11, + V4L2_MPEG_AUDIO_L2_BITRATE_320K = 12, + V4L2_MPEG_AUDIO_L2_BITRATE_384K = 13, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +#define V4L2_CID_MPEG_AUDIO_L3_BITRATE (V4L2_CID_MPEG_BASE+104) +enum v4l2_mpeg_audio_l3_bitrate { + V4L2_MPEG_AUDIO_L3_BITRATE_32K = 0, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_AUDIO_L3_BITRATE_40K = 1, + V4L2_MPEG_AUDIO_L3_BITRATE_48K = 2, + V4L2_MPEG_AUDIO_L3_BITRATE_56K = 3, + V4L2_MPEG_AUDIO_L3_BITRATE_64K = 4, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_AUDIO_L3_BITRATE_80K = 5, + V4L2_MPEG_AUDIO_L3_BITRATE_96K = 6, + V4L2_MPEG_AUDIO_L3_BITRATE_112K = 7, + V4L2_MPEG_AUDIO_L3_BITRATE_128K = 8, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_AUDIO_L3_BITRATE_160K = 9, + V4L2_MPEG_AUDIO_L3_BITRATE_192K = 10, + V4L2_MPEG_AUDIO_L3_BITRATE_224K = 11, + V4L2_MPEG_AUDIO_L3_BITRATE_256K = 12, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_AUDIO_L3_BITRATE_320K = 13, +}; +#define V4L2_CID_MPEG_AUDIO_MODE (V4L2_CID_MPEG_BASE+105) +enum v4l2_mpeg_audio_mode { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_AUDIO_MODE_STEREO = 0, + V4L2_MPEG_AUDIO_MODE_JOINT_STEREO = 1, + V4L2_MPEG_AUDIO_MODE_DUAL = 2, + V4L2_MPEG_AUDIO_MODE_MONO = 3, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +#define V4L2_CID_MPEG_AUDIO_MODE_EXTENSION (V4L2_CID_MPEG_BASE+106) +enum v4l2_mpeg_audio_mode_extension { + V4L2_MPEG_AUDIO_MODE_EXTENSION_BOUND_4 = 0, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_AUDIO_MODE_EXTENSION_BOUND_8 = 1, + V4L2_MPEG_AUDIO_MODE_EXTENSION_BOUND_12 = 2, + V4L2_MPEG_AUDIO_MODE_EXTENSION_BOUND_16 = 3, +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_MPEG_AUDIO_EMPHASIS (V4L2_CID_MPEG_BASE+107) +enum v4l2_mpeg_audio_emphasis { + V4L2_MPEG_AUDIO_EMPHASIS_NONE = 0, + V4L2_MPEG_AUDIO_EMPHASIS_50_DIV_15_uS = 1, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_AUDIO_EMPHASIS_CCITT_J17 = 2, +}; +#define V4L2_CID_MPEG_AUDIO_CRC (V4L2_CID_MPEG_BASE+108) +enum v4l2_mpeg_audio_crc { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_AUDIO_CRC_NONE = 0, + V4L2_MPEG_AUDIO_CRC_CRC16 = 1, +}; +#define V4L2_CID_MPEG_AUDIO_MUTE (V4L2_CID_MPEG_BASE+109) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_MPEG_AUDIO_AAC_BITRATE (V4L2_CID_MPEG_BASE+110) +#define V4L2_CID_MPEG_AUDIO_AC3_BITRATE (V4L2_CID_MPEG_BASE+111) +enum v4l2_mpeg_audio_ac3_bitrate { + V4L2_MPEG_AUDIO_AC3_BITRATE_32K = 0, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_AUDIO_AC3_BITRATE_40K = 1, + V4L2_MPEG_AUDIO_AC3_BITRATE_48K = 2, + V4L2_MPEG_AUDIO_AC3_BITRATE_56K = 3, + V4L2_MPEG_AUDIO_AC3_BITRATE_64K = 4, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_AUDIO_AC3_BITRATE_80K = 5, + V4L2_MPEG_AUDIO_AC3_BITRATE_96K = 6, + V4L2_MPEG_AUDIO_AC3_BITRATE_112K = 7, + V4L2_MPEG_AUDIO_AC3_BITRATE_128K = 8, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_AUDIO_AC3_BITRATE_160K = 9, + V4L2_MPEG_AUDIO_AC3_BITRATE_192K = 10, + V4L2_MPEG_AUDIO_AC3_BITRATE_224K = 11, + V4L2_MPEG_AUDIO_AC3_BITRATE_256K = 12, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_AUDIO_AC3_BITRATE_320K = 13, + V4L2_MPEG_AUDIO_AC3_BITRATE_384K = 14, + V4L2_MPEG_AUDIO_AC3_BITRATE_448K = 15, + V4L2_MPEG_AUDIO_AC3_BITRATE_512K = 16, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_AUDIO_AC3_BITRATE_576K = 17, + V4L2_MPEG_AUDIO_AC3_BITRATE_640K = 18, +}; +#define V4L2_CID_MPEG_AUDIO_DEC_PLAYBACK (V4L2_CID_MPEG_BASE+112) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +enum v4l2_mpeg_audio_dec_playback { + V4L2_MPEG_AUDIO_DEC_PLAYBACK_AUTO = 0, + V4L2_MPEG_AUDIO_DEC_PLAYBACK_STEREO = 1, + V4L2_MPEG_AUDIO_DEC_PLAYBACK_LEFT = 2, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_AUDIO_DEC_PLAYBACK_RIGHT = 3, + V4L2_MPEG_AUDIO_DEC_PLAYBACK_MONO = 4, + V4L2_MPEG_AUDIO_DEC_PLAYBACK_SWAPPED_STEREO = 5, +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_MPEG_AUDIO_DEC_MULTILINGUAL_PLAYBACK (V4L2_CID_MPEG_BASE+113) +#define V4L2_CID_MPEG_VIDEO_ENCODING (V4L2_CID_MPEG_BASE+200) +enum v4l2_mpeg_video_encoding { + V4L2_MPEG_VIDEO_ENCODING_MPEG_1 = 0, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_VIDEO_ENCODING_MPEG_2 = 1, + V4L2_MPEG_VIDEO_ENCODING_MPEG_4_AVC = 2, +}; +#define V4L2_CID_MPEG_VIDEO_ASPECT (V4L2_CID_MPEG_BASE+201) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +enum v4l2_mpeg_video_aspect { + V4L2_MPEG_VIDEO_ASPECT_1x1 = 0, + V4L2_MPEG_VIDEO_ASPECT_4x3 = 1, + V4L2_MPEG_VIDEO_ASPECT_16x9 = 2, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_VIDEO_ASPECT_221x100 = 3, +}; +#define V4L2_CID_MPEG_VIDEO_B_FRAMES (V4L2_CID_MPEG_BASE+202) +#define V4L2_CID_MPEG_VIDEO_GOP_SIZE (V4L2_CID_MPEG_BASE+203) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_MPEG_VIDEO_GOP_CLOSURE (V4L2_CID_MPEG_BASE+204) +#define V4L2_CID_MPEG_VIDEO_PULLDOWN (V4L2_CID_MPEG_BASE+205) +#define V4L2_CID_MPEG_VIDEO_BITRATE_MODE (V4L2_CID_MPEG_BASE+206) +enum v4l2_mpeg_video_bitrate_mode { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_VIDEO_BITRATE_MODE_VBR = 0, + V4L2_MPEG_VIDEO_BITRATE_MODE_CBR = 1, +}; +#define V4L2_CID_MPEG_VIDEO_BITRATE (V4L2_CID_MPEG_BASE+207) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_MPEG_VIDEO_BITRATE_PEAK (V4L2_CID_MPEG_BASE+208) +#define V4L2_CID_MPEG_VIDEO_TEMPORAL_DECIMATION (V4L2_CID_MPEG_BASE+209) +#define V4L2_CID_MPEG_VIDEO_MUTE (V4L2_CID_MPEG_BASE+210) +#define V4L2_CID_MPEG_VIDEO_MUTE_YUV (V4L2_CID_MPEG_BASE+211) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_MPEG_VIDEO_DECODER_SLICE_INTERFACE (V4L2_CID_MPEG_BASE+212) +#define V4L2_CID_MPEG_VIDEO_DECODER_MPEG4_DEBLOCK_FILTER (V4L2_CID_MPEG_BASE+213) +#define V4L2_CID_MPEG_VIDEO_CYCLIC_INTRA_REFRESH_MB (V4L2_CID_MPEG_BASE+214) +#define V4L2_CID_MPEG_VIDEO_FRAME_RC_ENABLE (V4L2_CID_MPEG_BASE+215) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_MPEG_VIDEO_HEADER_MODE (V4L2_CID_MPEG_BASE+216) +enum v4l2_mpeg_video_header_mode { + V4L2_MPEG_VIDEO_HEADER_MODE_SEPARATE = 0, + V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME = 1, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_I_FRAME = 2, +}; +#define V4L2_CID_MPEG_VIDEO_MAX_REF_PIC (V4L2_CID_MPEG_BASE+217) +#define V4L2_CID_MPEG_VIDEO_MB_RC_ENABLE (V4L2_CID_MPEG_BASE+218) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MAX_BYTES (V4L2_CID_MPEG_BASE+219) +#define V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MAX_MB (V4L2_CID_MPEG_BASE+220) +#define V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MODE (V4L2_CID_MPEG_BASE+221) +enum v4l2_mpeg_video_multi_slice_mode { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_VIDEO_MULTI_SLICE_MODE_SINGLE = 0, + V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_MB = 1, + V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_BYTES = 2, + V4L2_MPEG_VIDEO_MULTI_SLICE_GOB = 3, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +#define V4L2_CID_MPEG_VIDEO_VBV_SIZE (V4L2_CID_MPEG_BASE+222) +#define V4L2_CID_MPEG_VIDEO_DEC_PTS (V4L2_CID_MPEG_BASE+223) +#define V4L2_CID_MPEG_VIDEO_DEC_FRAME (V4L2_CID_MPEG_BASE+224) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_MPEG_VIDEO_H263_I_FRAME_QP (V4L2_CID_MPEG_BASE+300) +#define V4L2_CID_MPEG_VIDEO_H263_P_FRAME_QP (V4L2_CID_MPEG_BASE+301) +#define V4L2_CID_MPEG_VIDEO_H263_B_FRAME_QP (V4L2_CID_MPEG_BASE+302) +#define V4L2_CID_MPEG_VIDEO_H263_MIN_QP (V4L2_CID_MPEG_BASE+303) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_MPEG_VIDEO_H263_MAX_QP (V4L2_CID_MPEG_BASE+304) +#define V4L2_CID_MPEG_VIDEO_H264_I_FRAME_QP (V4L2_CID_MPEG_BASE+350) +#define V4L2_CID_MPEG_VIDEO_H264_P_FRAME_QP (V4L2_CID_MPEG_BASE+351) +#define V4L2_CID_MPEG_VIDEO_H264_B_FRAME_QP (V4L2_CID_MPEG_BASE+352) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_MPEG_VIDEO_H264_MIN_QP (V4L2_CID_MPEG_BASE+353) +#define V4L2_CID_MPEG_VIDEO_H264_MAX_QP (V4L2_CID_MPEG_BASE+354) +#define V4L2_CID_MPEG_VIDEO_H264_8X8_TRANSFORM (V4L2_CID_MPEG_BASE+355) +#define V4L2_CID_MPEG_VIDEO_H264_CPB_SIZE (V4L2_CID_MPEG_BASE+356) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_MPEG_VIDEO_H264_ENTROPY_MODE (V4L2_CID_MPEG_BASE+357) +enum v4l2_mpeg_video_h264_entropy_mode { + V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CAVLC = 0, + V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CABAC = 1, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +#define V4L2_CID_MPEG_VIDEO_H264_I_PERIOD (V4L2_CID_MPEG_BASE+358) +#define V4L2_CID_MPEG_VIDEO_H264_LEVEL (V4L2_CID_MPEG_BASE+359) +enum v4l2_mpeg_video_h264_level { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_VIDEO_H264_LEVEL_1_0 = 0, + V4L2_MPEG_VIDEO_H264_LEVEL_1B = 1, + V4L2_MPEG_VIDEO_H264_LEVEL_1_1 = 2, + V4L2_MPEG_VIDEO_H264_LEVEL_1_2 = 3, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_VIDEO_H264_LEVEL_1_3 = 4, + V4L2_MPEG_VIDEO_H264_LEVEL_2_0 = 5, + V4L2_MPEG_VIDEO_H264_LEVEL_2_1 = 6, + V4L2_MPEG_VIDEO_H264_LEVEL_2_2 = 7, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_VIDEO_H264_LEVEL_3_0 = 8, + V4L2_MPEG_VIDEO_H264_LEVEL_3_1 = 9, + V4L2_MPEG_VIDEO_H264_LEVEL_3_2 = 10, + V4L2_MPEG_VIDEO_H264_LEVEL_4_0 = 11, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_VIDEO_H264_LEVEL_4_1 = 12, + V4L2_MPEG_VIDEO_H264_LEVEL_4_2 = 13, + V4L2_MPEG_VIDEO_H264_LEVEL_5_0 = 14, + V4L2_MPEG_VIDEO_H264_LEVEL_5_1 = 15, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +#define V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_ALPHA (V4L2_CID_MPEG_BASE+360) +#define V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_BETA (V4L2_CID_MPEG_BASE+361) +#define V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_MODE (V4L2_CID_MPEG_BASE+362) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +enum v4l2_mpeg_video_h264_loop_filter_mode { + V4L2_MPEG_VIDEO_H264_LOOP_FILTER_MODE_ENABLED = 0, + V4L2_MPEG_VIDEO_H264_LOOP_FILTER_MODE_DISABLED = 1, + V4L2_MPEG_VIDEO_H264_LOOP_FILTER_MODE_DISABLED_AT_SLICE_BOUNDARY = 2, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +#define V4L2_CID_MPEG_VIDEO_H264_PROFILE (V4L2_CID_MPEG_BASE+363) +enum v4l2_mpeg_video_h264_profile { + V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE = 0, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_BASELINE = 1, + V4L2_MPEG_VIDEO_H264_PROFILE_MAIN = 2, + V4L2_MPEG_VIDEO_H264_PROFILE_EXTENDED = 3, + V4L2_MPEG_VIDEO_H264_PROFILE_HIGH = 4, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_10 = 5, + V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_422 = 6, + V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_444_PREDICTIVE = 7, + V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_10_INTRA = 8, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_422_INTRA = 9, + V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_444_INTRA = 10, + V4L2_MPEG_VIDEO_H264_PROFILE_CAVLC_444_INTRA = 11, + V4L2_MPEG_VIDEO_H264_PROFILE_SCALABLE_BASELINE = 12, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_VIDEO_H264_PROFILE_SCALABLE_HIGH = 13, + V4L2_MPEG_VIDEO_H264_PROFILE_SCALABLE_HIGH_INTRA = 14, + V4L2_MPEG_VIDEO_H264_PROFILE_STEREO_HIGH = 15, + V4L2_MPEG_VIDEO_H264_PROFILE_MULTIVIEW_HIGH = 16, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_HIGH = 17, +}; +#define V4L2_CID_MPEG_VIDEO_H264_VUI_EXT_SAR_HEIGHT (V4L2_CID_MPEG_BASE+364) +#define V4L2_CID_MPEG_VIDEO_H264_VUI_EXT_SAR_WIDTH (V4L2_CID_MPEG_BASE+365) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_MPEG_VIDEO_H264_VUI_SAR_ENABLE (V4L2_CID_MPEG_BASE+366) +#define V4L2_CID_MPEG_VIDEO_H264_VUI_SAR_IDC (V4L2_CID_MPEG_BASE+367) +enum v4l2_mpeg_video_h264_vui_sar_idc { + V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_UNSPECIFIED = 0, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_1x1 = 1, + V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_12x11 = 2, + V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_10x11 = 3, + V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_16x11 = 4, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_40x33 = 5, + V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_24x11 = 6, + V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_20x11 = 7, + V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_32x11 = 8, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_80x33 = 9, + V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_18x11 = 10, + V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_15x11 = 11, + V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_64x33 = 12, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_160x99 = 13, + V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_4x3 = 14, + V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_3x2 = 15, + V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_2x1 = 16, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_EXTENDED = 17, +}; +#define V4L2_CID_MPEG_VIDEO_MPEG4_I_FRAME_QP (V4L2_CID_MPEG_BASE+400) +#define V4L2_CID_MPEG_VIDEO_MPEG4_P_FRAME_QP (V4L2_CID_MPEG_BASE+401) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_MPEG_VIDEO_MPEG4_B_FRAME_QP (V4L2_CID_MPEG_BASE+402) +#define V4L2_CID_MPEG_VIDEO_MPEG4_MIN_QP (V4L2_CID_MPEG_BASE+403) +#define V4L2_CID_MPEG_VIDEO_MPEG4_MAX_QP (V4L2_CID_MPEG_BASE+404) +#define V4L2_CID_MPEG_VIDEO_MPEG4_LEVEL (V4L2_CID_MPEG_BASE+405) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +enum v4l2_mpeg_video_mpeg4_level { + V4L2_MPEG_VIDEO_MPEG4_LEVEL_0 = 0, + V4L2_MPEG_VIDEO_MPEG4_LEVEL_0B = 1, + V4L2_MPEG_VIDEO_MPEG4_LEVEL_1 = 2, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_VIDEO_MPEG4_LEVEL_2 = 3, + V4L2_MPEG_VIDEO_MPEG4_LEVEL_3 = 4, + V4L2_MPEG_VIDEO_MPEG4_LEVEL_3B = 5, + V4L2_MPEG_VIDEO_MPEG4_LEVEL_4 = 6, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_VIDEO_MPEG4_LEVEL_5 = 7, +}; +#define V4L2_CID_MPEG_VIDEO_MPEG4_PROFILE (V4L2_CID_MPEG_BASE+406) +enum v4l2_mpeg_video_mpeg4_profile { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_VIDEO_MPEG4_PROFILE_SIMPLE = 0, + V4L2_MPEG_VIDEO_MPEG4_PROFILE_ADVANCED_SIMPLE = 1, + V4L2_MPEG_VIDEO_MPEG4_PROFILE_CORE = 2, + V4L2_MPEG_VIDEO_MPEG4_PROFILE_SIMPLE_SCALABLE = 3, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_VIDEO_MPEG4_PROFILE_ADVANCED_CODING_EFFICIENCY = 4, +}; +#define V4L2_CID_MPEG_VIDEO_MPEG4_QPEL (V4L2_CID_MPEG_BASE+407) +#define V4L2_CID_QCOM_VIDEO_SYNC_FRAME_SEQ_HDR (V4L2_CID_MPEG_BASE+408) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_MPEG_CX2341X_BASE (V4L2_CTRL_CLASS_MPEG | 0x1000) +#define V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER_MODE (V4L2_CID_MPEG_CX2341X_BASE+0) +enum v4l2_mpeg_cx2341x_video_spatial_filter_mode { + V4L2_MPEG_CX2341X_VIDEO_SPATIAL_FILTER_MODE_MANUAL = 0, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_CX2341X_VIDEO_SPATIAL_FILTER_MODE_AUTO = 1, +}; +#define V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER (V4L2_CID_MPEG_CX2341X_BASE+1) +#define V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE (V4L2_CID_MPEG_CX2341X_BASE+2) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +enum v4l2_mpeg_cx2341x_video_luma_spatial_filter_type { + V4L2_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE_OFF = 0, + V4L2_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE_1D_HOR = 1, + V4L2_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE_1D_VERT = 2, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE_2D_HV_SEPARABLE = 3, + V4L2_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE_2D_SYM_NON_SEPARABLE = 4, +}; +#define V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_SPATIAL_FILTER_TYPE (V4L2_CID_MPEG_CX2341X_BASE+3) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +enum v4l2_mpeg_cx2341x_video_chroma_spatial_filter_type { + V4L2_MPEG_CX2341X_VIDEO_CHROMA_SPATIAL_FILTER_TYPE_OFF = 0, + V4L2_MPEG_CX2341X_VIDEO_CHROMA_SPATIAL_FILTER_TYPE_1D_HOR = 1, +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER_MODE (V4L2_CID_MPEG_CX2341X_BASE+4) +enum v4l2_mpeg_cx2341x_video_temporal_filter_mode { + V4L2_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER_MODE_MANUAL = 0, + V4L2_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER_MODE_AUTO = 1, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +#define V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER (V4L2_CID_MPEG_CX2341X_BASE+5) +#define V4L2_CID_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE (V4L2_CID_MPEG_CX2341X_BASE+6) +enum v4l2_mpeg_cx2341x_video_median_filter_type { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE_OFF = 0, + V4L2_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE_HOR = 1, + V4L2_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE_VERT = 2, + V4L2_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE_HOR_VERT = 3, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE_DIAG = 4, +}; +#define V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_BOTTOM (V4L2_CID_MPEG_CX2341X_BASE+7) +#define V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_TOP (V4L2_CID_MPEG_CX2341X_BASE+8) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_BOTTOM (V4L2_CID_MPEG_CX2341X_BASE+9) +#define V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_TOP (V4L2_CID_MPEG_CX2341X_BASE+10) +#define V4L2_CID_MPEG_CX2341X_STREAM_INSERT_NAV_PACKETS (V4L2_CID_MPEG_CX2341X_BASE+11) +#define V4L2_CID_MPEG_MFC51_BASE (V4L2_CTRL_CLASS_MPEG | 0x1100) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_MPEG_MFC51_VIDEO_DECODER_H264_DISPLAY_DELAY (V4L2_CID_MPEG_MFC51_BASE+0) +#define V4L2_CID_MPEG_MFC51_VIDEO_DECODER_H264_DISPLAY_DELAY_ENABLE (V4L2_CID_MPEG_MFC51_BASE+1) +#define V4L2_CID_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE (V4L2_CID_MPEG_MFC51_BASE+2) +enum v4l2_mpeg_mfc51_video_frame_skip_mode { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_DISABLED = 0, + V4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_LEVEL_LIMIT = 1, + V4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT = 2, +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_MPEG_MFC51_VIDEO_FORCE_FRAME_TYPE (V4L2_CID_MPEG_MFC51_BASE+3) +enum v4l2_mpeg_mfc51_video_force_frame_type { + V4L2_MPEG_MFC51_VIDEO_FORCE_FRAME_TYPE_DISABLED = 0, + V4L2_MPEG_MFC51_VIDEO_FORCE_FRAME_TYPE_I_FRAME = 1, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_MFC51_VIDEO_FORCE_FRAME_TYPE_NOT_CODED = 2, +}; +#define V4L2_CID_MPEG_MFC51_VIDEO_PADDING (V4L2_CID_MPEG_MFC51_BASE+4) +#define V4L2_CID_MPEG_MFC51_VIDEO_PADDING_YUV (V4L2_CID_MPEG_MFC51_BASE+5) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_MPEG_MFC51_VIDEO_RC_FIXED_TARGET_BIT (V4L2_CID_MPEG_MFC51_BASE+6) +#define V4L2_CID_MPEG_MFC51_VIDEO_RC_REACTION_COEFF (V4L2_CID_MPEG_MFC51_BASE+7) +#define V4L2_CID_MPEG_MFC51_VIDEO_H264_ADAPTIVE_RC_ACTIVITY (V4L2_CID_MPEG_MFC51_BASE+50) +#define V4L2_CID_MPEG_MFC51_VIDEO_H264_ADAPTIVE_RC_DARK (V4L2_CID_MPEG_MFC51_BASE+51) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_MPEG_MFC51_VIDEO_H264_ADAPTIVE_RC_SMOOTH (V4L2_CID_MPEG_MFC51_BASE+52) +#define V4L2_CID_MPEG_MFC51_VIDEO_H264_ADAPTIVE_RC_STATIC (V4L2_CID_MPEG_MFC51_BASE+53) +#define V4L2_CID_MPEG_MFC51_VIDEO_H264_NUM_REF_PIC_FOR_P (V4L2_CID_MPEG_MFC51_BASE+54) +#define V4L2_CID_MPEG_MSM_VIDC_BASE (V4L2_CTRL_CLASS_MPEG | 0x2000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_MPEG_VIDC_VIDEO_ENABLE_PICTURE_TYPE (V4L2_CID_MPEG_MSM_VIDC_BASE+0) +#define V4L2_CID_MPEG_VIDC_VIDEO_KEEP_ASPECT_RATIO (V4L2_CID_MPEG_MSM_VIDC_BASE+1) +#define V4L2_CID_MPEG_VIDC_VIDEO_POST_LOOP_DEBLOCKER_MODE (V4L2_CID_MPEG_MSM_VIDC_BASE+2) +#define V4L2_CID_MPEG_VIDC_VIDEO_DIVX_FORMAT (V4L2_CID_MPEG_MSM_VIDC_BASE+3) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +enum v4l2_mpeg_vidc_video_divx_format_type { + V4L2_MPEG_VIDC_VIDEO_DIVX_FORMAT_4 = 0, + V4L2_MPEG_VIDC_VIDEO_DIVX_FORMAT_5 = 1, + V4L2_MPEG_VIDC_VIDEO_DIVX_FORMAT_6 = 2, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +#define V4L2_CID_MPEG_VIDC_VIDEO_MB_ERROR_MAP_REPORTING (V4L2_CID_MPEG_MSM_VIDC_BASE+4) +#define V4L2_CID_MPEG_VIDC_VIDEO_CONTINUE_DATA_TRANSFER (V4L2_CID_MPEG_MSM_VIDC_BASE+5) +#define V4L2_CID_MPEG_VIDC_VIDEO_STREAM_FORMAT (V4L2_CID_MPEG_MSM_VIDC_BASE+6) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +enum v4l2_mpeg_vidc_video_stream_format { + V4L2_MPEG_VIDC_VIDEO_NAL_FORMAT_STARTCODES = 0, + V4L2_MPEG_VIDC_VIDEO_NAL_FORMAT_ONE_NAL_PER_BUFFER = 1, + V4L2_MPEG_VIDC_VIDEO_NAL_FORMAT_ONE_BYTE_LENGTH = 2, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_VIDC_VIDEO_NAL_FORMAT_TWO_BYTE_LENGTH = 3, + V4L2_MPEG_VIDC_VIDEO_NAL_FORMAT_FOUR_BYTE_LENGTH = 4, +}; +#define V4L2_CID_MPEG_VIDC_VIDEO_OUTPUT_ORDER (V4L2_CID_MPEG_MSM_VIDC_BASE+7) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +enum v4l2_mpeg_vidc_video_output_order { + V4L2_MPEG_VIDC_VIDEO_OUTPUT_ORDER_DISPLAY = 0, + V4L2_MPEG_VIDC_VIDEO_OUTPUT_ORDER_DECODE = 1, +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_MPEG_VIDC_VIDEO_FRAME_RATE (V4L2_CID_MPEG_MSM_VIDC_BASE+8) +#define V4L2_CID_MPEG_VIDC_VIDEO_IDR_PERIOD (V4L2_CID_MPEG_MSM_VIDC_BASE+9) +#define V4L2_CID_MPEG_VIDC_VIDEO_NUM_P_FRAMES (V4L2_CID_MPEG_MSM_VIDC_BASE+10) +#define V4L2_CID_MPEG_VIDC_VIDEO_NUM_B_FRAMES (V4L2_CID_MPEG_MSM_VIDC_BASE+11) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_MPEG_VIDC_VIDEO_REQUEST_IFRAME (V4L2_CID_MPEG_MSM_VIDC_BASE+12) +#define V4L2_CID_MPEG_VIDC_VIDEO_RATE_CONTROL (V4L2_CID_MPEG_MSM_VIDC_BASE+13) +enum v4l2_mpeg_vidc_video_rate_control { + V4L2_CID_MPEG_VIDC_VIDEO_RATE_CONTROL_OFF = 0, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_CID_MPEG_VIDC_VIDEO_RATE_CONTROL_VBR_VFR = 1, + V4L2_CID_MPEG_VIDC_VIDEO_RATE_CONTROL_VBR_CFR = 2, + V4L2_CID_MPEG_VIDC_VIDEO_RATE_CONTROL_CBR_VFR = 3, + V4L2_CID_MPEG_VIDC_VIDEO_RATE_CONTROL_CBR_CFR = 4, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +#define V4L2_CID_MPEG_VIDC_VIDEO_ROTATION (V4L2_CID_MPEG_MSM_VIDC_BASE+14) +enum v4l2_mpeg_vidc_video_rotation { + V4L2_CID_MPEG_VIDC_VIDEO_ROTATION_NONE = 0, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_CID_MPEG_VIDC_VIDEO_ROTATION_90 = 1, + V4L2_CID_MPEG_VIDC_VIDEO_ROTATION_180 = 2, + V4L2_CID_MPEG_VIDC_VIDEO_ROTATION_270 = 3, +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define MSM_VIDC_BASE V4L2_CID_MPEG_MSM_VIDC_BASE +#define V4L2_CID_MPEG_VIDC_VIDEO_H264_CABAC_MODEL (MSM_VIDC_BASE+15) +enum v4l2_mpeg_vidc_h264_cabac_model { + V4L2_CID_MPEG_VIDC_VIDEO_H264_CABAC_MODEL_0 = 0, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_CID_MPEG_VIDC_VIDEO_H264_CABAC_MODEL_1 = 1, + V4L2_CID_MPEG_VIDC_VIDEO_H264_CABAC_MODEL_2 = 2, +}; +#define V4L2_CID_MPEG_VIDC_VIDEO_INTRA_REFRESH_MODE (MSM_VIDC_BASE+16) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +enum v4l2_mpeg_vidc_video_intra_refresh_mode { + V4L2_CID_MPEG_VIDC_VIDEO_INTRA_REFRESH_NONE = 0, + V4L2_CID_MPEG_VIDC_VIDEO_INTRA_REFRESH_CYCLIC = 1, + V4L2_CID_MPEG_VIDC_VIDEO_INTRA_REFRESH_ADAPTIVE = 2, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_CID_MPEG_VIDC_VIDEO_INTRA_REFRESH_CYCLIC_ADAPTIVE = 3, + V4L2_CID_MPEG_VIDC_VIDEO_INTRA_REFRESH_RANDOM = 4, +}; +#define V4L2_CID_MPEG_VIDC_VIDEO_AIR_MBS (V4L2_CID_MPEG_MSM_VIDC_BASE+17) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_MPEG_VIDC_VIDEO_AIR_REF (V4L2_CID_MPEG_MSM_VIDC_BASE+18) +#define V4L2_CID_MPEG_VIDC_VIDEO_CIR_MBS (V4L2_CID_MPEG_MSM_VIDC_BASE+19) +#define V4L2_CID_MPEG_VIDC_VIDEO_H263_PROFILE (V4L2_CID_MPEG_MSM_VIDC_BASE+20) +enum v4l2_mpeg_vidc_video_h263_profile { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_VIDC_VIDEO_H263_PROFILE_BASELINE = 0, + V4L2_MPEG_VIDC_VIDEO_H263_PROFILE_H320CODING = 1, + V4L2_MPEG_VIDC_VIDEO_H263_PROFILE_BACKWARDCOMPATIBLE = 2, + V4L2_MPEG_VIDC_VIDEO_H263_PROFILE_ISWV2 = 3, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_VIDC_VIDEO_H263_PROFILE_ISWV3 = 4, + V4L2_MPEG_VIDC_VIDEO_H263_PROFILE_HIGHCOMPRESSION = 5, + V4L2_MPEG_VIDC_VIDEO_H263_PROFILE_INTERNET = 6, + V4L2_MPEG_VIDC_VIDEO_H263_PROFILE_INTERLACE = 7, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_VIDC_VIDEO_H263_PROFILE_HIGHLATENCY = 8, +}; +#define V4L2_CID_MPEG_VIDC_VIDEO_H263_LEVEL (V4L2_CID_MPEG_MSM_VIDC_BASE+21) +enum v4l2_mpeg_vidc_video_h263_level { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_VIDC_VIDEO_H263_LEVEL_1_0 = 0, + V4L2_MPEG_VIDC_VIDEO_H263_LEVEL_2_0 = 1, + V4L2_MPEG_VIDC_VIDEO_H263_LEVEL_3_0 = 2, + V4L2_MPEG_VIDC_VIDEO_H263_LEVEL_4_0 = 3, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_VIDC_VIDEO_H263_LEVEL_4_5 = 4, + V4L2_MPEG_VIDC_VIDEO_H263_LEVEL_5_0 = 5, + V4L2_MPEG_VIDC_VIDEO_H263_LEVEL_6_0 = 6, + V4L2_MPEG_VIDC_VIDEO_H263_LEVEL_7_0 = 7, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +#define V4L2_CID_MPEG_VIDC_VIDEO_H264_AU_DELIMITER (V4L2_CID_MPEG_MSM_VIDC_BASE + 22) +enum v4l2_mpeg_vidc_video_h264_au_delimiter { + V4L2_MPEG_VIDC_VIDEO_H264_AU_DELIMITER_DISABLED = 0, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_VIDC_VIDEO_H264_AU_DELIMITER_ENABLED = 1 +}; +#define V4L2_CID_MPEG_VIDC_VIDEO_SYNC_FRAME_DECODE (V4L2_CID_MPEG_MSM_VIDC_BASE + 23) +enum v4l2_mpeg_vidc_video_sync_frame_decode { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_VIDC_VIDEO_SYNC_FRAME_DECODE_DISABLE = 0, + V4L2_MPEG_VIDC_VIDEO_SYNC_FRAME_DECODE_ENABLE = 1 +}; +#define V4L2_CID_MPEG_VIDC_VIDEO_SECURE (V4L2_CID_MPEG_MSM_VIDC_BASE+24) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_MPEG_VIDC_VIDEO_EXTRADATA (V4L2_CID_MPEG_MSM_VIDC_BASE + 25) +enum v4l2_mpeg_vidc_extradata { + V4L2_MPEG_VIDC_EXTRADATA_NONE, + V4L2_MPEG_VIDC_EXTRADATA_MB_QUANTIZATION, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_VIDC_EXTRADATA_INTERLACE_VIDEO, + V4L2_MPEG_VIDC_EXTRADATA_VC1_FRAMEDISP, + V4L2_MPEG_VIDC_EXTRADATA_VC1_SEQDISP, + V4L2_MPEG_VIDC_EXTRADATA_TIMESTAMP, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_VIDC_EXTRADATA_S3D_FRAME_PACKING, + V4L2_MPEG_VIDC_EXTRADATA_FRAME_RATE, + V4L2_MPEG_VIDC_EXTRADATA_PANSCAN_WINDOW, + V4L2_MPEG_VIDC_EXTRADATA_RECOVERY_POINT_SEI, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_VIDC_EXTRADATA_CLOSED_CAPTION_UD, + V4L2_MPEG_VIDC_EXTRADATA_AFD_UD, + V4L2_MPEG_VIDC_EXTRADATA_MULTISLICE_INFO, + V4L2_MPEG_VIDC_EXTRADATA_NUM_CONCEALED_MB, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_VIDC_EXTRADATA_METADATA_FILLER, + V4L2_MPEG_VIDC_INDEX_EXTRADATA_INPUT_CROP, + V4L2_MPEG_VIDC_INDEX_EXTRADATA_DIGITAL_ZOOM, + V4L2_MPEG_VIDC_INDEX_EXTRADATA_ASPECT_RATIO, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_VIDC_EXTRADATA_MPEG2_SEQDISP +}; +#define V4L2_CID_MPEG_VIDC_SET_PERF_LEVEL (V4L2_CID_MPEG_MSM_VIDC_BASE + 26) +enum v4l2_mpeg_vidc_perf_level { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_CID_MPEG_VIDC_PERF_LEVEL_NOMINAL = 0, + V4L2_CID_MPEG_VIDC_PERF_LEVEL_PERFORMANCE = 1, + V4L2_CID_MPEG_VIDC_PERF_LEVEL_TURBO = 2, +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_MPEG_VIDEO_MULTI_SLICE_GOB (V4L2_CID_MPEG_MSM_VIDC_BASE + 27) +#define V4L2_CID_MPEG_VIDEO_MULTI_SLICE_DELIVERY_MODE (V4L2_CID_MPEG_MSM_VIDC_BASE + 28) +#define V4L2_CID_MPEG_VIDC_VIDEO_H264_VUI_TIMING_INFO (V4L2_CID_MPEG_MSM_VIDC_BASE + 29) +enum v4l2_mpeg_vidc_video_h264_vui_timing_info { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_VIDC_VIDEO_H264_VUI_TIMING_INFO_DISABLED = 0, + V4L2_MPEG_VIDC_VIDEO_H264_VUI_TIMING_INFO_ENABLED = 1 +}; +#define V4L2_CID_MPEG_VIDC_VIDEO_ALLOC_MODE_INPUT (V4L2_CID_MPEG_MSM_VIDC_BASE + 30) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_MPEG_VIDC_VIDEO_ALLOC_MODE_OUTPUT (V4L2_CID_MPEG_MSM_VIDC_BASE + 31) +enum v4l2_mpeg_vidc_video_alloc_mode_type { + V4L2_MPEG_VIDC_VIDEO_STATIC = 0, + V4L2_MPEG_VIDC_VIDEO_RING = 1, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_VIDC_VIDEO_DYNAMIC = 2, +}; +#define V4L2_CID_MPEG_VIDC_VIDEO_FRAME_ASSEMBLY (V4L2_CID_MPEG_MSM_VIDC_BASE + 32) +enum v4l2_mpeg_vidc_video_assembly { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_VIDC_FRAME_ASSEMBLY_DISABLE = 0, + V4L2_MPEG_VIDC_FRAME_ASSEMBLY_ENABLE = 1, +}; +#define V4L2_CID_MPEG_VIDC_VIDEO_VP8_PROFILE_LEVEL (V4L2_CID_MPEG_MSM_VIDC_BASE + 33) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +enum v4l2_mpeg_vidc_video_vp8_profile_level { + V4L2_MPEG_VIDC_VIDEO_VP8_UNUSED, + V4L2_MPEG_VIDC_VIDEO_VP8_VERSION_0, + V4L2_MPEG_VIDC_VIDEO_VP8_VERSION_1, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_VIDC_VIDEO_VP8_VERSION_2, + V4L2_MPEG_VIDC_VIDEO_VP8_VERSION_3, +}; +#define V4L2_CID_MPEG_VIDC_VIDEO_H264_VUI_BITSTREAM_RESTRICT (V4L2_CID_MPEG_MSM_VIDC_BASE + 34) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +enum v4l2_mpeg_vidc_video_h264_vui_bitstream_restrict { + V4L2_MPEG_VIDC_VIDEO_H264_VUI_BITSTREAM_RESTRICT_DISABLED = 0, + V4L2_MPEG_VIDC_VIDEO_H264_VUI_BITSTREAM_RESTRICT_ENABLED = 1 +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_MPEG_VIDC_VIDEO_PRESERVE_TEXT_QUALITY (V4L2_CID_MPEG_MSM_VIDC_BASE + 35) +enum v4l2_mpeg_vidc_video_preserve_text_quality { + V4L2_MPEG_VIDC_VIDEO_PRESERVE_TEXT_QUALITY_DISABLED = 0, + V4L2_MPEG_VIDC_VIDEO_PRESERVE_TEXT_QUALITY_ENABLED = 1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +#define V4L2_CID_MPEG_VIDC_VIDEO_REQUEST_SEQ_HEADER (V4L2_CID_MPEG_MSM_VIDC_BASE + 36) +#define V4L2_CID_CAMERA_CLASS_BASE (V4L2_CTRL_CLASS_CAMERA | 0x900) +#define V4L2_CID_CAMERA_CLASS (V4L2_CTRL_CLASS_CAMERA | 1) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_EXPOSURE_AUTO (V4L2_CID_CAMERA_CLASS_BASE+1) +enum v4l2_exposure_auto_type { + V4L2_EXPOSURE_AUTO = 0, + V4L2_EXPOSURE_MANUAL = 1, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_EXPOSURE_SHUTTER_PRIORITY = 2, + V4L2_EXPOSURE_APERTURE_PRIORITY = 3 +}; +#define V4L2_CID_EXPOSURE_ABSOLUTE (V4L2_CID_CAMERA_CLASS_BASE+2) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_EXPOSURE_AUTO_PRIORITY (V4L2_CID_CAMERA_CLASS_BASE+3) +#define V4L2_CID_PAN_RELATIVE (V4L2_CID_CAMERA_CLASS_BASE+4) +#define V4L2_CID_TILT_RELATIVE (V4L2_CID_CAMERA_CLASS_BASE+5) +#define V4L2_CID_PAN_RESET (V4L2_CID_CAMERA_CLASS_BASE+6) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_TILT_RESET (V4L2_CID_CAMERA_CLASS_BASE+7) +#define V4L2_CID_PAN_ABSOLUTE (V4L2_CID_CAMERA_CLASS_BASE+8) +#define V4L2_CID_TILT_ABSOLUTE (V4L2_CID_CAMERA_CLASS_BASE+9) +#define V4L2_CID_FOCUS_ABSOLUTE (V4L2_CID_CAMERA_CLASS_BASE+10) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_FOCUS_RELATIVE (V4L2_CID_CAMERA_CLASS_BASE+11) +#define V4L2_CID_FOCUS_AUTO (V4L2_CID_CAMERA_CLASS_BASE+12) +#define V4L2_CID_ZOOM_ABSOLUTE (V4L2_CID_CAMERA_CLASS_BASE+13) +#define V4L2_CID_ZOOM_RELATIVE (V4L2_CID_CAMERA_CLASS_BASE+14) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_ZOOM_CONTINUOUS (V4L2_CID_CAMERA_CLASS_BASE+15) +#define V4L2_CID_PRIVACY (V4L2_CID_CAMERA_CLASS_BASE+16) +#define V4L2_CID_IRIS_ABSOLUTE (V4L2_CID_CAMERA_CLASS_BASE+17) +#define V4L2_CID_IRIS_RELATIVE (V4L2_CID_CAMERA_CLASS_BASE+18) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_FM_TX_CLASS_BASE (V4L2_CTRL_CLASS_FM_TX | 0x900) +#define V4L2_CID_FM_TX_CLASS (V4L2_CTRL_CLASS_FM_TX | 1) +#define V4L2_CID_RDS_TX_DEVIATION (V4L2_CID_FM_TX_CLASS_BASE + 1) +#define V4L2_CID_RDS_TX_PI (V4L2_CID_FM_TX_CLASS_BASE + 2) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_RDS_TX_PTY (V4L2_CID_FM_TX_CLASS_BASE + 3) +#define V4L2_CID_RDS_TX_PS_NAME (V4L2_CID_FM_TX_CLASS_BASE + 5) +#define V4L2_CID_RDS_TX_RADIO_TEXT (V4L2_CID_FM_TX_CLASS_BASE + 6) +#define V4L2_CID_AUDIO_LIMITER_ENABLED (V4L2_CID_FM_TX_CLASS_BASE + 64) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_AUDIO_LIMITER_RELEASE_TIME (V4L2_CID_FM_TX_CLASS_BASE + 65) +#define V4L2_CID_AUDIO_LIMITER_DEVIATION (V4L2_CID_FM_TX_CLASS_BASE + 66) +#define V4L2_CID_AUDIO_COMPRESSION_ENABLED (V4L2_CID_FM_TX_CLASS_BASE + 80) +#define V4L2_CID_AUDIO_COMPRESSION_GAIN (V4L2_CID_FM_TX_CLASS_BASE + 81) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_AUDIO_COMPRESSION_THRESHOLD (V4L2_CID_FM_TX_CLASS_BASE + 82) +#define V4L2_CID_AUDIO_COMPRESSION_ATTACK_TIME (V4L2_CID_FM_TX_CLASS_BASE + 83) +#define V4L2_CID_AUDIO_COMPRESSION_RELEASE_TIME (V4L2_CID_FM_TX_CLASS_BASE + 84) +#define V4L2_CID_PILOT_TONE_ENABLED (V4L2_CID_FM_TX_CLASS_BASE + 96) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_PILOT_TONE_DEVIATION (V4L2_CID_FM_TX_CLASS_BASE + 97) +#define V4L2_CID_PILOT_TONE_FREQUENCY (V4L2_CID_FM_TX_CLASS_BASE + 98) +#define V4L2_CID_TUNE_PREEMPHASIS (V4L2_CID_FM_TX_CLASS_BASE + 112) +enum v4l2_preemphasis { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_PREEMPHASIS_DISABLED = 0, + V4L2_PREEMPHASIS_50_uS = 1, + V4L2_PREEMPHASIS_75_uS = 2, +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_TUNE_POWER_LEVEL (V4L2_CID_FM_TX_CLASS_BASE + 113) +#define V4L2_CID_TUNE_ANTENNA_CAPACITOR (V4L2_CID_FM_TX_CLASS_BASE + 114) +#define V4L2_CID_FLASH_CLASS_BASE (V4L2_CTRL_CLASS_FLASH | 0x900) +#define V4L2_CID_FLASH_CLASS (V4L2_CTRL_CLASS_FLASH | 1) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_FLASH_LED_MODE (V4L2_CID_FLASH_CLASS_BASE + 1) +enum v4l2_flash_led_mode { + V4L2_FLASH_LED_MODE_NONE, + V4L2_FLASH_LED_MODE_FLASH, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_FLASH_LED_MODE_TORCH, +}; +#define V4L2_CID_FLASH_STROBE_SOURCE (V4L2_CID_FLASH_CLASS_BASE + 2) +enum v4l2_flash_strobe_source { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_FLASH_STROBE_SOURCE_SOFTWARE, + V4L2_FLASH_STROBE_SOURCE_EXTERNAL, +}; +#define V4L2_CID_FLASH_STROBE (V4L2_CID_FLASH_CLASS_BASE + 3) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_FLASH_STROBE_STOP (V4L2_CID_FLASH_CLASS_BASE + 4) +#define V4L2_CID_FLASH_STROBE_STATUS (V4L2_CID_FLASH_CLASS_BASE + 5) +#define V4L2_CID_FLASH_TIMEOUT (V4L2_CID_FLASH_CLASS_BASE + 6) +#define V4L2_CID_FLASH_INTENSITY (V4L2_CID_FLASH_CLASS_BASE + 7) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_FLASH_TORCH_INTENSITY (V4L2_CID_FLASH_CLASS_BASE + 8) +#define V4L2_CID_FLASH_INDICATOR_INTENSITY (V4L2_CID_FLASH_CLASS_BASE + 9) +#define V4L2_CID_FLASH_FAULT (V4L2_CID_FLASH_CLASS_BASE + 10) +#define V4L2_FLASH_FAULT_OVER_VOLTAGE (1 << 0) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_FLASH_FAULT_TIMEOUT (1 << 1) +#define V4L2_FLASH_FAULT_OVER_TEMPERATURE (1 << 2) +#define V4L2_FLASH_FAULT_SHORT_CIRCUIT (1 << 3) +#define V4L2_FLASH_FAULT_OVER_CURRENT (1 << 4) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_FLASH_FAULT_INDICATOR (1 << 5) +#define V4L2_CID_FLASH_CHARGE (V4L2_CID_FLASH_CLASS_BASE + 11) +#define V4L2_CID_FLASH_READY (V4L2_CID_FLASH_CLASS_BASE + 12) +#define V4L2_CID_JPEG_CLASS_BASE (V4L2_CTRL_CLASS_JPEG | 0x900) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_JPEG_CLASS (V4L2_CTRL_CLASS_JPEG | 1) +#define V4L2_CID_JPEG_CHROMA_SUBSAMPLING (V4L2_CID_JPEG_CLASS_BASE + 1) +enum v4l2_jpeg_chroma_subsampling { + V4L2_JPEG_CHROMA_SUBSAMPLING_444 = 0, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_JPEG_CHROMA_SUBSAMPLING_422 = 1, + V4L2_JPEG_CHROMA_SUBSAMPLING_420 = 2, + V4L2_JPEG_CHROMA_SUBSAMPLING_411 = 3, + V4L2_JPEG_CHROMA_SUBSAMPLING_410 = 4, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_JPEG_CHROMA_SUBSAMPLING_GRAY = 5, +}; +#define V4L2_CID_JPEG_RESTART_INTERVAL (V4L2_CID_JPEG_CLASS_BASE + 2) +#define V4L2_CID_JPEG_COMPRESSION_QUALITY (V4L2_CID_JPEG_CLASS_BASE + 3) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_JPEG_ACTIVE_MARKER (V4L2_CID_JPEG_CLASS_BASE + 4) +#define V4L2_JPEG_ACTIVE_MARKER_APP0 (1 << 0) +#define V4L2_JPEG_ACTIVE_MARKER_APP1 (1 << 1) +#define V4L2_JPEG_ACTIVE_MARKER_COM (1 << 16) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_JPEG_ACTIVE_MARKER_DQT (1 << 17) +#define V4L2_JPEG_ACTIVE_MARKER_DHT (1 << 18) +struct v4l2_tuner { + __u32 index; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u8 name[32]; + enum v4l2_tuner_type type; + __u32 capability; + __u32 rangelow; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u32 rangehigh; + __u32 rxsubchans; + __u32 audmode; + __s32 signal; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __s32 afc; + __u32 reserved[4]; +}; +struct v4l2_modulator { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u32 index; + __u8 name[32]; + __u32 capability; + __u32 rangelow; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u32 rangehigh; + __u32 txsubchans; + __u32 reserved[4]; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_TUNER_CAP_LOW 0x0001 +#define V4L2_TUNER_CAP_NORM 0x0002 +#define V4L2_TUNER_CAP_STEREO 0x0010 +#define V4L2_TUNER_CAP_LANG2 0x0020 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_TUNER_CAP_SAP 0x0020 +#define V4L2_TUNER_CAP_LANG1 0x0040 +#define V4L2_TUNER_CAP_RDS 0x0080 +#define V4L2_TUNER_CAP_RDS_BLOCK_IO 0x0100 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_TUNER_CAP_RDS_CONTROLS 0x0200 +#define V4L2_TUNER_SUB_MONO 0x0001 +#define V4L2_TUNER_SUB_STEREO 0x0002 +#define V4L2_TUNER_SUB_LANG2 0x0004 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_TUNER_SUB_SAP 0x0004 +#define V4L2_TUNER_SUB_LANG1 0x0008 +#define V4L2_TUNER_SUB_RDS 0x0010 +#define V4L2_TUNER_MODE_MONO 0x0000 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_TUNER_MODE_STEREO 0x0001 +#define V4L2_TUNER_MODE_LANG2 0x0002 +#define V4L2_TUNER_MODE_SAP 0x0002 +#define V4L2_TUNER_MODE_LANG1 0x0003 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_TUNER_MODE_LANG1_LANG2 0x0004 +struct v4l2_frequency { + __u32 tuner; + enum v4l2_tuner_type type; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u32 frequency; + __u32 reserved[8]; +}; +struct v4l2_hw_freq_seek { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u32 tuner; + enum v4l2_tuner_type type; + __u32 seek_upward; + __u32 wrap_around; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u32 spacing; + __u32 reserved[7]; +}; +struct v4l2_rds_data { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u8 lsb; + __u8 msb; + __u8 block; +} __attribute__ ((packed)); +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_RDS_BLOCK_MSK 0x7 +#define V4L2_RDS_BLOCK_A 0 +#define V4L2_RDS_BLOCK_B 1 +#define V4L2_RDS_BLOCK_C 2 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_RDS_BLOCK_D 3 +#define V4L2_RDS_BLOCK_C_ALT 4 +#define V4L2_RDS_BLOCK_INVALID 7 +#define V4L2_RDS_BLOCK_CORRECTED 0x40 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_RDS_BLOCK_ERROR 0x80 +struct v4l2_audio { + __u32 index; + __u8 name[32]; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u32 capability; + __u32 mode; + __u32 reserved[2]; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_AUDCAP_STEREO 0x00001 +#define V4L2_AUDCAP_AVL 0x00002 +#define V4L2_AUDMODE_AVL 0x00001 +struct v4l2_audioout { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u32 index; + __u8 name[32]; + __u32 capability; + __u32 mode; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u32 reserved[2]; +}; +#define V4L2_ENC_IDX_FRAME_I (0) +#define V4L2_ENC_IDX_FRAME_P (1) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_ENC_IDX_FRAME_B (2) +#define V4L2_ENC_IDX_FRAME_MASK (0xf) +struct v4l2_enc_idx_entry { + __u64 offset; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u64 pts; + __u32 length; + __u32 flags; + __u32 reserved[2]; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +#define V4L2_ENC_IDX_ENTRIES (64) +struct v4l2_enc_idx { + __u32 entries; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u32 entries_cap; + __u32 reserved[4]; + struct v4l2_enc_idx_entry entry[V4L2_ENC_IDX_ENTRIES]; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_ENC_CMD_START (0) +#define V4L2_ENC_CMD_STOP (1) +#define V4L2_ENC_CMD_PAUSE (2) +#define V4L2_ENC_CMD_RESUME (3) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_ENC_QCOM_CMD_FLUSH (4) +#define V4L2_ENC_CMD_STOP_AT_GOP_END (1 << 0) +struct v4l2_encoder_cmd { + __u32 cmd; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u32 flags; + union { + struct { + __u32 data[8]; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + } raw; + }; +}; +#define V4L2_DEC_CMD_START (0) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_DEC_CMD_STOP (1) +#define V4L2_DEC_CMD_PAUSE (2) +#define V4L2_DEC_CMD_RESUME (3) +#define V4L2_DEC_QCOM_CMD_FLUSH (4) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_DEC_CMD_START_MUTE_AUDIO (1 << 0) +#define V4L2_DEC_CMD_PAUSE_TO_BLACK (1 << 0) +#define V4L2_DEC_CMD_STOP_TO_BLACK (1 << 0) +#define V4L2_DEC_CMD_STOP_IMMEDIATELY (1 << 1) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_DEC_QCOM_CMD_FLUSH_OUTPUT (1 << 0) +#define V4L2_DEC_QCOM_CMD_FLUSH_CAPTURE (1 << 1) +#define V4L2_QCOM_CMD_FLUSH_OUTPUT (1 << 0) +#define V4L2_QCOM_CMD_FLUSH_CAPTURE (1 << 1) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_DEC_START_FMT_NONE (0) +#define V4L2_DEC_START_FMT_GOP (1) +struct v4l2_decoder_cmd { + __u32 cmd; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u32 flags; + union { + struct { + __u64 pts; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + } stop; + struct { + __s32 speed; + __u32 format; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + } start; + struct { + __u32 data[16]; + } raw; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + }; +}; +struct v4l2_vbi_format { + __u32 sampling_rate; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u32 offset; + __u32 samples_per_line; + __u32 sample_format; + __s32 start[2]; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u32 count[2]; + __u32 flags; + __u32 reserved[2]; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_VBI_UNSYNC (1 << 0) +#define V4L2_VBI_INTERLACED (1 << 1) +struct v4l2_sliced_vbi_format { + __u16 service_set; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u16 service_lines[2][24]; + __u32 io_size; + __u32 reserved[2]; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_SLICED_TELETEXT_B (0x0001) +#define V4L2_SLICED_VPS (0x0400) +#define V4L2_SLICED_CAPTION_525 (0x1000) +#define V4L2_SLICED_WSS_625 (0x4000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_SLICED_VBI_525 (V4L2_SLICED_CAPTION_525) +#define V4L2_SLICED_VBI_625 (V4L2_SLICED_TELETEXT_B | V4L2_SLICED_VPS | V4L2_SLICED_WSS_625) +struct v4l2_sliced_vbi_cap { + __u16 service_set; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u16 service_lines[2][24]; + enum v4l2_buf_type type; + __u32 reserved[3]; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct v4l2_sliced_vbi_data { + __u32 id; + __u32 field; + __u32 line; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u32 reserved; + __u8 data[48]; +}; +#define V4L2_MPEG_VBI_IVTV_TELETEXT_B (1) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_MPEG_VBI_IVTV_CAPTION_525 (4) +#define V4L2_MPEG_VBI_IVTV_WSS_625 (5) +#define V4L2_MPEG_VBI_IVTV_VPS (7) +struct v4l2_mpeg_vbi_itv0_line { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u8 id; + __u8 data[42]; +} __attribute__ ((packed)); +struct v4l2_mpeg_vbi_itv0 { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __le32 linemask[2]; + struct v4l2_mpeg_vbi_itv0_line line[35]; +} __attribute__ ((packed)); +struct v4l2_mpeg_vbi_ITV0 { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + struct v4l2_mpeg_vbi_itv0_line line[36]; +} __attribute__ ((packed)); +#define V4L2_MPEG_VBI_IVTV_MAGIC0 "itv0" +#define V4L2_MPEG_VBI_IVTV_MAGIC1 "ITV0" +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct v4l2_mpeg_vbi_fmt_ivtv { + __u8 magic[4]; + union { + struct v4l2_mpeg_vbi_itv0 itv0; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + struct v4l2_mpeg_vbi_ITV0 ITV0; + }; +} __attribute__ ((packed)); +struct v4l2_plane_pix_format { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u32 sizeimage; + __u16 bytesperline; + __u16 reserved[7]; +} __attribute__ ((packed)); +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct v4l2_pix_format_mplane { + __u32 width; + __u32 height; + __u32 pixelformat; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + enum v4l2_field field; + enum v4l2_colorspace colorspace; + struct v4l2_plane_pix_format plane_fmt[VIDEO_MAX_PLANES]; + __u8 num_planes; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u8 reserved[11]; +} __attribute__ ((packed)); +struct v4l2_format { + enum v4l2_buf_type type; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + union { + struct v4l2_pix_format pix; + struct v4l2_pix_format_mplane pix_mp; + struct v4l2_window win; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + struct v4l2_vbi_format vbi; + struct v4l2_sliced_vbi_format sliced; + __u8 raw_data[200]; + } fmt; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +struct v4l2_streamparm { + enum v4l2_buf_type type; + union { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + struct v4l2_captureparm capture; + struct v4l2_outputparm output; + __u8 raw_data[200]; + } parm; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +#define V4L2_EVENT_ALL 0 +#define V4L2_EVENT_VSYNC 1 +#define V4L2_EVENT_EOS 2 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_EVENT_CTRL 3 +#define V4L2_EVENT_FRAME_SYNC 4 +#define V4L2_EVENT_PRIVATE_START 0x08000000 +#define V4L2_EVENT_MSM_VIDC_START (V4L2_EVENT_PRIVATE_START + 0x00001000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_EVENT_MSM_VIDC_FLUSH_DONE (V4L2_EVENT_MSM_VIDC_START + 1) +#define V4L2_EVENT_MSM_VIDC_PORT_SETTINGS_CHANGED_SUFFICIENT (V4L2_EVENT_MSM_VIDC_START + 2) +#define V4L2_EVENT_MSM_VIDC_PORT_SETTINGS_CHANGED_INSUFFICIENT (V4L2_EVENT_MSM_VIDC_START + 3) +#define V4L2_EVENT_MSM_VIDC_CLOSE_DONE (V4L2_EVENT_MSM_VIDC_START + 4) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_EVENT_MSM_VIDC_SYS_ERROR (V4L2_EVENT_MSM_VIDC_START + 5) +#define V4L2_EVENT_MSM_VIDC_RELEASE_BUFFER_REFERENCE (V4L2_EVENT_MSM_VIDC_START + 6) +#define V4L2_EVENT_MSM_VIDC_RELEASE_UNQUEUED_BUFFER (V4L2_EVENT_MSM_VIDC_START + 7) +struct v4l2_event_vsync { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u8 field; +} __attribute__ ((packed)); +#define V4L2_EVENT_CTRL_CH_VALUE (1 << 0) +#define V4L2_EVENT_CTRL_CH_FLAGS (1 << 1) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct v4l2_event_ctrl { + __u32 changes; + __u32 type; + union { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __s32 value; + __s64 value64; + }; + __u32 flags; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __s32 minimum; + __s32 maximum; + __s32 step; + __s32 default_value; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +struct v4l2_event_frame_sync { + __u32 frame_sequence; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct v4l2_event { + __u32 type; + union { + struct v4l2_event_vsync vsync; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + struct v4l2_event_ctrl ctrl; + struct v4l2_event_frame_sync frame_sync; + __u8 data[64]; + } u; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u32 pending; + __u32 sequence; + struct timespec timestamp; + __u32 id; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u32 reserved[8]; +}; +#define V4L2_EVENT_SUB_FL_SEND_INITIAL (1 << 0) +#define V4L2_EVENT_SUB_FL_ALLOW_FEEDBACK (1 << 1) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct v4l2_event_subscription { + __u32 type; + __u32 id; + __u32 flags; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u32 reserved[5]; +}; +#define V4L2_CHIP_MATCH_HOST 0 +#define V4L2_CHIP_MATCH_I2C_DRIVER 1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CHIP_MATCH_I2C_ADDR 2 +#define V4L2_CHIP_MATCH_AC97 3 +struct v4l2_dbg_match { + __u32 type; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + union { + __u32 addr; + char name[32]; + }; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +} __attribute__ ((packed)); +struct v4l2_dbg_register { + struct v4l2_dbg_match match; + __u32 size; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u64 reg; + __u64 val; +} __attribute__ ((packed)); +struct v4l2_dbg_chip_ident { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + struct v4l2_dbg_match match; + __u32 ident; + __u32 revision; +} __attribute__ ((packed)); +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct v4l2_create_buffers { + __u32 index; + __u32 count; + enum v4l2_memory memory; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + struct v4l2_format format; + __u32 reserved[8]; +}; +#define VIDIOC_QUERYCAP _IOR('V', 0, struct v4l2_capability) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VIDIOC_RESERVED _IO('V', 1) +#define VIDIOC_ENUM_FMT _IOWR('V', 2, struct v4l2_fmtdesc) +#define VIDIOC_G_FMT _IOWR('V', 4, struct v4l2_format) +#define VIDIOC_S_FMT _IOWR('V', 5, struct v4l2_format) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VIDIOC_REQBUFS _IOWR('V', 8, struct v4l2_requestbuffers) +#define VIDIOC_QUERYBUF _IOWR('V', 9, struct v4l2_buffer) +#define VIDIOC_G_FBUF _IOR('V', 10, struct v4l2_framebuffer) +#define VIDIOC_S_FBUF _IOW('V', 11, struct v4l2_framebuffer) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VIDIOC_OVERLAY _IOW('V', 14, int) +#define VIDIOC_QBUF _IOWR('V', 15, struct v4l2_buffer) +#define VIDIOC_DQBUF _IOWR('V', 17, struct v4l2_buffer) +#define VIDIOC_STREAMON _IOW('V', 18, int) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VIDIOC_STREAMOFF _IOW('V', 19, int) +#define VIDIOC_G_PARM _IOWR('V', 21, struct v4l2_streamparm) +#define VIDIOC_S_PARM _IOWR('V', 22, struct v4l2_streamparm) +#define VIDIOC_G_STD _IOR('V', 23, v4l2_std_id) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VIDIOC_S_STD _IOW('V', 24, v4l2_std_id) +#define VIDIOC_ENUMSTD _IOWR('V', 25, struct v4l2_standard) +#define VIDIOC_ENUMINPUT _IOWR('V', 26, struct v4l2_input) +#define VIDIOC_G_CTRL _IOWR('V', 27, struct v4l2_control) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VIDIOC_S_CTRL _IOWR('V', 28, struct v4l2_control) +#define VIDIOC_G_TUNER _IOWR('V', 29, struct v4l2_tuner) +#define VIDIOC_S_TUNER _IOW('V', 30, struct v4l2_tuner) +#define VIDIOC_G_AUDIO _IOR('V', 33, struct v4l2_audio) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VIDIOC_S_AUDIO _IOW('V', 34, struct v4l2_audio) +#define VIDIOC_QUERYCTRL _IOWR('V', 36, struct v4l2_queryctrl) +#define VIDIOC_QUERYMENU _IOWR('V', 37, struct v4l2_querymenu) +#define VIDIOC_G_INPUT _IOR('V', 38, int) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VIDIOC_S_INPUT _IOWR('V', 39, int) +#define VIDIOC_G_OUTPUT _IOR('V', 46, int) +#define VIDIOC_S_OUTPUT _IOWR('V', 47, int) +#define VIDIOC_ENUMOUTPUT _IOWR('V', 48, struct v4l2_output) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VIDIOC_G_AUDOUT _IOR('V', 49, struct v4l2_audioout) +#define VIDIOC_S_AUDOUT _IOW('V', 50, struct v4l2_audioout) +#define VIDIOC_G_MODULATOR _IOWR('V', 54, struct v4l2_modulator) +#define VIDIOC_S_MODULATOR _IOW('V', 55, struct v4l2_modulator) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VIDIOC_G_FREQUENCY _IOWR('V', 56, struct v4l2_frequency) +#define VIDIOC_S_FREQUENCY _IOW('V', 57, struct v4l2_frequency) +#define VIDIOC_CROPCAP _IOWR('V', 58, struct v4l2_cropcap) +#define VIDIOC_G_CROP _IOWR('V', 59, struct v4l2_crop) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VIDIOC_S_CROP _IOW('V', 60, struct v4l2_crop) +#define VIDIOC_G_JPEGCOMP _IOR('V', 61, struct v4l2_jpegcompression) +#define VIDIOC_S_JPEGCOMP _IOW('V', 62, struct v4l2_jpegcompression) +#define VIDIOC_QUERYSTD _IOR('V', 63, v4l2_std_id) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VIDIOC_TRY_FMT _IOWR('V', 64, struct v4l2_format) +#define VIDIOC_ENUMAUDIO _IOWR('V', 65, struct v4l2_audio) +#define VIDIOC_ENUMAUDOUT _IOWR('V', 66, struct v4l2_audioout) +#define VIDIOC_G_PRIORITY _IOR('V', 67, enum v4l2_priority) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VIDIOC_S_PRIORITY _IOW('V', 68, enum v4l2_priority) +#define VIDIOC_G_SLICED_VBI_CAP _IOWR('V', 69, struct v4l2_sliced_vbi_cap) +#define VIDIOC_LOG_STATUS _IO('V', 70) +#define VIDIOC_G_EXT_CTRLS _IOWR('V', 71, struct v4l2_ext_controls) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VIDIOC_S_EXT_CTRLS _IOWR('V', 72, struct v4l2_ext_controls) +#define VIDIOC_TRY_EXT_CTRLS _IOWR('V', 73, struct v4l2_ext_controls) +#define VIDIOC_ENUM_FRAMESIZES _IOWR('V', 74, struct v4l2_frmsizeenum) +#define VIDIOC_ENUM_FRAMEINTERVALS _IOWR('V', 75, struct v4l2_frmivalenum) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VIDIOC_G_ENC_INDEX _IOR('V', 76, struct v4l2_enc_idx) +#define VIDIOC_ENCODER_CMD _IOWR('V', 77, struct v4l2_encoder_cmd) +#define VIDIOC_TRY_ENCODER_CMD _IOWR('V', 78, struct v4l2_encoder_cmd) +#define VIDIOC_DBG_S_REGISTER _IOW('V', 79, struct v4l2_dbg_register) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VIDIOC_DBG_G_REGISTER _IOWR('V', 80, struct v4l2_dbg_register) +#define VIDIOC_DBG_G_CHIP_IDENT _IOWR('V', 81, struct v4l2_dbg_chip_ident) +#define VIDIOC_S_HW_FREQ_SEEK _IOW('V', 82, struct v4l2_hw_freq_seek) +#define VIDIOC_ENUM_DV_PRESETS _IOWR('V', 83, struct v4l2_dv_enum_preset) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VIDIOC_S_DV_PRESET _IOWR('V', 84, struct v4l2_dv_preset) +#define VIDIOC_G_DV_PRESET _IOWR('V', 85, struct v4l2_dv_preset) +#define VIDIOC_QUERY_DV_PRESET _IOR('V', 86, struct v4l2_dv_preset) +#define VIDIOC_S_DV_TIMINGS _IOWR('V', 87, struct v4l2_dv_timings) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VIDIOC_G_DV_TIMINGS _IOWR('V', 88, struct v4l2_dv_timings) +#define VIDIOC_DQEVENT _IOR('V', 89, struct v4l2_event) +#define VIDIOC_SUBSCRIBE_EVENT _IOW('V', 90, struct v4l2_event_subscription) +#define VIDIOC_UNSUBSCRIBE_EVENT _IOW('V', 91, struct v4l2_event_subscription) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VIDIOC_CREATE_BUFS _IOWR('V', 92, struct v4l2_create_buffers) +#define VIDIOC_PREPARE_BUF _IOWR('V', 93, struct v4l2_buffer) +#define VIDIOC_G_SELECTION _IOWR('V', 94, struct v4l2_selection) +#define VIDIOC_S_SELECTION _IOWR('V', 95, struct v4l2_selection) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VIDIOC_DECODER_CMD _IOWR('V', 96, struct v4l2_decoder_cmd) +#define VIDIOC_TRY_DECODER_CMD _IOWR('V', 97, struct v4l2_decoder_cmd) +#define BASE_VIDIOC_PRIVATE 192 +#endif +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + diff --git a/original-kernel-headers/linux/timpani-audio.h b/original-kernel-headers/linux/timpani-audio.h new file mode 100644 index 0000000..49fd49b --- /dev/null +++ b/original-kernel-headers/linux/timpani-audio.h @@ -0,0 +1,5016 @@ +#ifndef __LINUX_MFD_TIMPANI_AUDIO_H +#define __LINUX_MFD_TIMPANI_AUDIO_H + +/* + * MREF + */ +#define TIMPANI_A_MREF (0x3) +#define TIMPANI_MREF_RWC "RW" +#define TIMPANI_MREF_POR 0xe2 +#define TIMPANI_MREF_S 0 +#define TIMPANI_MREF_M 0xFF + +#define TIMPANI_MREF_MREF_BG_EN_S 7 +#define TIMPANI_MREF_MREF_BG_EN_M 0x80 +#define TIMPANI_MREF_MREF_BG_EN_ENABLE 0x0 +#define TIMPANI_MREF_MREF_BG_EN_DISABLE 0x1 + +#define TIMPANI_MREF_MREF_BG_REF_CUR_EN_S 6 +#define TIMPANI_MREF_MREF_BG_REF_CUR_EN_M 0x40 +#define TIMPANI_MREF_MREF_BG_REF_CUR_EN_ENABLE_NORMAL_OP 0x0 +#define TIMPANI_MREF_MREF_BG_REF_CUR_EN_DISABLE 0x1 + +#define TIMPANI_MREF_MREF_200K_MODE_EN_S 5 +#define TIMPANI_MREF_MREF_200K_MODE_EN_M 0x20 +#define TIMPANI_MREF_MREF_200K_MODE_EN_ENABLE 0x0 +#define TIMPANI_MREF_MREF_200K_MODE_EN_DISABLE 0x1 + +#define TIMPANI_MREF_MREF_PRE_CHARGE_EN_S 4 +#define TIMPANI_MREF_MREF_PRE_CHARGE_EN_M 0x10 +#define TIMPANI_MREF_MREF_PRE_CHARGE_EN_DISABLE 0x0 +#define TIMPANI_MREF_MREF_PRE_CHARGE_EN_ENABLE 0x1 + +#define TIMPANI_MREF_MREF_100UA_CUR_CONN_S 3 +#define TIMPANI_MREF_MREF_100UA_CUR_CONN_M 0x8 +#define TIMPANI_MREF_MREF_100UA_CUR_CONN_ON_CHIP_RESISTOR_NORMAL_OP 0x0 +#define TIMPANI_MREF_MREF_100UA_CUR_CONN_ATEST 0x1 + +#define TIMPANI_MREF_MREF_PTAT_CURRENT_S 2 +#define TIMPANI_MREF_MREF_PTAT_CURRENT_M 0x4 +#define TIMPANI_MREF_MREF_PTAT_CURRENT_V_10UA_PTAT_NORMAL_OP 0x0 +#define TIMPANI_MREF_MREF_PTAT_CURRENT_V_5UA_PTAT_BIAS_CURRENT 0x1 + +#define TIMPANI_MREF_MREF_400K_MODE_EN_S 1 +#define TIMPANI_MREF_MREF_400K_MODE_EN_M 0x2 +#define TIMPANI_MREF_MREF_400K_MODE_EN_ENABLE 0x0 +#define TIMPANI_MREF_MREF_400K_MODE_EN_DISABLE 0x1 + +#define TIMPANI_MREF_RESERVED_S 0 +#define TIMPANI_MREF_RESERVED_M 0x1 + + +/* For CDAC_IDAC_REF_CUR */ +#define TIMPANI_A_CDAC_IDAC_REF_CUR (0x4) +#define TIMPANI_CDAC_IDAC_REF_CUR_RWC "RW" +#define TIMPANI_CDAC_IDAC_REF_CUR_POR 0x8c +#define TIMPANI_CDAC_IDAC_REF_CUR_S 0 +#define TIMPANI_CDAC_IDAC_REF_CUR_M 0xFF + + +#define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_REF_BUFF_CUR_S 5 +#define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_REF_BUFF_CUR_M 0xE0 +#define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_REF_BUFF_CUR_V_4UA 0x0 +#define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_REF_BUFF_CUR_V_6UA 0x1 +#define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_REF_BUFF_CUR_V_8UA 0x2 +#define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_REF_BUFF_CUR_V_9UA 0x3 +#define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_REF_BUFF_CUR_V_10UA_NORMAL_OP 0x4 +#define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_REF_BUFF_CUR_V_11UA 0x5 +#define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_REF_BUFF_CUR_V_13UA 0x6 +#define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_REF_BUFF_CUR_V_15UA 0x7 + +#define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_BIAS_CUR_S 2 +#define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_BIAS_CUR_M 0x1C +#define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_BIAS_CUR_V_8_5UA 0x0 +#define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_BIAS_CUR_V_9_0UA 0x1 +#define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_BIAS_CUR_V_9_5UA 0x2 +#define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_BIAS_CUR_V_10_0UA_NORMAL_OP 0x3 +#define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_BIAS_CUR_V_10_5UA 0x4 +#define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_BIAS_CUR_V_11_0UA 0x5 +#define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_BIAS_CUR_V_11_5UA 0x6 +#define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_BIAS_CUR_V_12_0UA 0x7 + +#define TIMPANI_CDAC_IDAC_REF_CUR_IDAC_REF_CUR_S 0 +#define TIMPANI_CDAC_IDAC_REF_CUR_IDAC_REF_CUR_M 0x3 +#define TIMPANI_CDAC_IDAC_REF_CUR_IDAC_REF_CUR_V_2UA 0x0 +#define TIMPANI_CDAC_IDAC_REF_CUR_IDAC_REF_CUR_V_3UA 0x1 +#define TIMPANI_CDAC_IDAC_REF_CUR_IDAC_REF_CUR_V_5UA_NORMAL_OP 0x2 +#define TIMPANI_CDAC_IDAC_REF_CUR_IDAC_REF_CUR_V_8UA 0x3 + + +/* -- For TXADC12_REF_CURR */ +#define TIMPANI_A_TXADC12_REF_CURR (0x5) +#define TIMPANI_TXADC12_REF_CURR_RWC "RW" +#define TIMPANI_TXADC12_REF_CURR_POR 0xa0 +#define TIMPANI_TXADC12_REF_CURR_S 0 +#define TIMPANI_TXADC12_REF_CURR_M 0xFF + + +#define TIMPANI_TXADC12_REF_CURR_TXADC1_REF_BUFF_CUR_S 6 +#define TIMPANI_TXADC12_REF_CURR_TXADC1_REF_BUFF_CUR_M 0xC0 +#define TIMPANI_TXADC12_REF_CURR_TXADC1_REF_BUFF_CUR_V_50UA 0x0 +#define TIMPANI_TXADC12_REF_CURR_TXADC1_REF_BUFF_CUR_V_45UA 0x1 +#define TIMPANI_TXADC12_REF_CURR_TXADC1_REF_BUFF_CUR_V_40UA_NORMAL_OP 0x2 +#define TIMPANI_TXADC12_REF_CURR_TXADC1_REF_BUFF_CUR_V_35UA 0x3 + +#define TIMPANI_TXADC12_REF_CURR_TXADC2_REF_BUFF_CUR_S 4 +#define TIMPANI_TXADC12_REF_CURR_TXADC2_REF_BUFF_CUR_M 0x30 +#define TIMPANI_TXADC12_REF_CURR_TXADC2_REF_BUFF_CUR_V_50UA 0x0 +#define TIMPANI_TXADC12_REF_CURR_TXADC2_REF_BUFF_CUR_V_45UA 0x1 +#define TIMPANI_TXADC12_REF_CURR_TXADC2_REF_BUFF_CUR_V_40UA_NORMAL_OP 0x2 +#define TIMPANI_TXADC12_REF_CURR_TXADC2_REF_BUFF_CUR_V_35UA 0x3 + +#define TIMPANI_TXADC12_REF_CURR_RESERVED_S 0 +#define TIMPANI_TXADC12_REF_CURR_RESERVED_M 0xF + + +/* -- For TXADC3_EN */ +#define TIMPANI_A_TXADC3_EN (0x9) +#define TIMPANI_TXADC3_EN_RWC "RW" +#define TIMPANI_TXADC3_EN_POR 0 +#define TIMPANI_TXADC3_EN_S 0 +#define TIMPANI_TXADC3_EN_M 0xFF + + +#define TIMPANI_TXADC3_EN_TXADC3_REF_EN_S 7 +#define TIMPANI_TXADC3_EN_TXADC3_REF_EN_M 0x80 +#define TIMPANI_TXADC3_EN_TXADC3_REF_EN_DISABLE 0x0 +#define TIMPANI_TXADC3_EN_TXADC3_REF_EN_ENABLE 0x1 + +#define TIMPANI_TXADC3_EN_TXADC3_DAC_REF_CUR_COMPENSATION_EN_S 6 +#define TIMPANI_TXADC3_EN_TXADC3_DAC_REF_CUR_COMPENSATION_EN_M 0x40 +#define TIMPANI_TXADC3_EN_TXADC3_DAC_REF_CUR_COMPENSATION_EN_DISABLE 0x0 +#define TIMPANI_TXADC3_EN_TXADC3_DAC_REF_CUR_COMPENSATION_EN_ENABLE 0x1 + +#define TIMPANI_TXADC3_EN_TXADC3_OTA1_EN_S 5 +#define TIMPANI_TXADC3_EN_TXADC3_OTA1_EN_M 0x20 +#define TIMPANI_TXADC3_EN_TXADC3_OTA1_EN_DISABLE 0x0 +#define TIMPANI_TXADC3_EN_TXADC3_OTA1_EN_ENABLE 0x1 + +#define TIMPANI_TXADC3_EN_TXADC3_OTA2_EN_S 4 +#define TIMPANI_TXADC3_EN_TXADC3_OTA2_EN_M 0x10 +#define TIMPANI_TXADC3_EN_TXADC3_OTA2_EN_DISABLE 0x0 +#define TIMPANI_TXADC3_EN_TXADC3_OTA2_EN_ENABLE 0x1 + +#define TIMPANI_TXADC3_EN_TXADC3_COMP_EN_S 3 +#define TIMPANI_TXADC3_EN_TXADC3_COMP_EN_M 0x8 +#define TIMPANI_TXADC3_EN_TXADC3_COMP_EN_DISABLE 0x0 +#define TIMPANI_TXADC3_EN_TXADC3_COMP_EN_ENABLE 0x1 + +#define TIMPANI_TXADC3_EN_TXADC3_DEM_EN_S 2 +#define TIMPANI_TXADC3_EN_TXADC3_DEM_EN_M 0x4 +#define TIMPANI_TXADC3_EN_TXADC3_DEM_EN_DISABLE 0x0 +#define TIMPANI_TXADC3_EN_TXADC3_DEM_EN_ENABLE 0x1 + +#define TIMPANI_TXADC3_EN_TXADC3_DEM_ERROR_DET_EN_S 1 +#define TIMPANI_TXADC3_EN_TXADC3_DEM_ERROR_DET_EN_M 0x2 +#define TIMPANI_TXADC3_EN_TXADC3_DEM_ERROR_DET_EN_DISABLE 0x0 +#define TIMPANI_TXADC3_EN_TXADC3_DEM_ERROR_DET_EN_ENABLE 0x1 + +#define TIMPANI_TXADC3_EN_RESERVED_S 0 +#define TIMPANI_TXADC3_EN_RESERVED_M 0x1 + + +/* -- For TXADC4_EN */ +#define TIMPANI_A_TXADC4_EN (0xA) +#define TIMPANI_TXADC4_EN_RWC "RW" +#define TIMPANI_TXADC4_EN_POR 0 +#define TIMPANI_TXADC4_EN_S 0 +#define TIMPANI_TXADC4_EN_M 0xFF + + +#define TIMPANI_TXADC4_EN_TXADC4_REF_EN_S 7 +#define TIMPANI_TXADC4_EN_TXADC4_REF_EN_M 0x80 +#define TIMPANI_TXADC4_EN_TXADC4_REF_EN_DISABLE 0x0 +#define TIMPANI_TXADC4_EN_TXADC4_REF_EN_ENABLE 0x1 + +#define TIMPANI_TXADC4_EN_TXADC4_DAC_REF_CUR_COMPENSATION_EN_S 6 +#define TIMPANI_TXADC4_EN_TXADC4_DAC_REF_CUR_COMPENSATION_EN_M 0x40 +#define TIMPANI_TXADC4_EN_TXADC4_DAC_REF_CUR_COMPENSATION_EN_DISABLE 0x0 +#define TIMPANI_TXADC4_EN_TXADC4_DAC_REF_CUR_COMPENSATION_EN_ENABLE 0x1 + +#define TIMPANI_TXADC4_EN_TXADC4_OTA1_EN_S 5 +#define TIMPANI_TXADC4_EN_TXADC4_OTA1_EN_M 0x20 +#define TIMPANI_TXADC4_EN_TXADC4_OTA1_EN_DISABLE 0x0 +#define TIMPANI_TXADC4_EN_TXADC4_OTA1_EN_ENABLE 0x1 + +#define TIMPANI_TXADC4_EN_TXADC4_OTA2_EN_S 4 +#define TIMPANI_TXADC4_EN_TXADC4_OTA2_EN_M 0x10 +#define TIMPANI_TXADC4_EN_TXADC4_OTA2_EN_DISABLE 0x0 +#define TIMPANI_TXADC4_EN_TXADC4_OTA2_EN_ENABLE 0x1 + +#define TIMPANI_TXADC4_EN_TXADC4_COMP_EN_S 3 +#define TIMPANI_TXADC4_EN_TXADC4_COMP_EN_M 0x8 +#define TIMPANI_TXADC4_EN_TXADC4_COMP_EN_DISABLE 0x0 +#define TIMPANI_TXADC4_EN_TXADC4_COMP_EN_ENABLE 0x1 + +#define TIMPANI_TXADC4_EN_TXADC4_DEM_EN_S 2 +#define TIMPANI_TXADC4_EN_TXADC4_DEM_EN_M 0x4 +#define TIMPANI_TXADC4_EN_TXADC4_DEM_EN_DISABLE 0x0 +#define TIMPANI_TXADC4_EN_TXADC4_DEM_EN_ENABLE 0x1 + +#define TIMPANI_TXADC4_EN_TXADC4_DEM_ERROR_DET_EN_S 1 +#define TIMPANI_TXADC4_EN_TXADC4_DEM_ERROR_DET_EN_M 0x2 +#define TIMPANI_TXADC4_EN_TXADC4_DEM_ERROR_DET_EN_DISABLE 0x0 +#define TIMPANI_TXADC4_EN_TXADC4_DEM_ERROR_DET_EN_ENABLE 0x1 + +#define TIMPANI_TXADC4_EN_RESERVED_S 0 +#define TIMPANI_TXADC4_EN_RESERVED_M 0x1 + + +/* -- For CODEC_TXADC_STATUS_REGISTER_1 */ +#define TIMPANI_A_CODEC_TXADC_STATUS_REGISTER_1 (0xB) +#define TIMPANI_CODEC_TXADC_STATUS_REGISTER_1_RWC "R" +#define TIMPANI_CODEC_TXADC_STATUS_REGISTER_1_POR 0 +#define TIMPANI_CODEC_TXADC_STATUS_REGISTER_1_S 0 +#define TIMPANI_CODEC_TXADC_STATUS_REGISTER_1_M 0xFF + + +#define TIMPANI_CODEC_TXADC_STATUS_REGISTER_1_TXADC1_DEM_ERROR_S 7 +#define TIMPANI_CODEC_TXADC_STATUS_REGISTER_1_TXADC1_DEM_ERROR_M 0x80 + +#define TIMPANI_CODEC_TXADC_STATUS_REGISTER_1_TXADC2_DEM_ERROR_S 6 +#define TIMPANI_CODEC_TXADC_STATUS_REGISTER_1_TXADC2_DEM_ERROR_M 0x40 + +#define TIMPANI_CODEC_TXADC_STATUS_REGISTER_1_TXADC3_DEM_ERROR_S 5 +#define TIMPANI_CODEC_TXADC_STATUS_REGISTER_1_TXADC3_DEM_ERROR_M 0x20 + +#define TIMPANI_CODEC_TXADC_STATUS_REGISTER_1_TXADC4_DEM_ERROR_S 4 +#define TIMPANI_CODEC_TXADC_STATUS_REGISTER_1_TXADC4_DEM_ERROR_M 0x10 + +#define TIMPANI_CODEC_TXADC_STATUS_REGISTER_1_RESERVED_S 0 +#define TIMPANI_CODEC_TXADC_STATUS_REGISTER_1_RESERVED_M 0xF + + +/* -- For TXFE1 */ +#define TIMPANI_A_TXFE1 (0xD) +#define TIMPANI_TXFE1_RWC "RW" +#define TIMPANI_TXFE1_POR 0 +#define TIMPANI_TXFE1_S 0 +#define TIMPANI_TXFE1_M 0xFF + + +#define TIMPANI_TXFE1_TXFE1_EN_S 7 +#define TIMPANI_TXFE1_TXFE1_EN_M 0x80 +#define TIMPANI_TXFE1_TXFE1_EN_DISABLE 0x0 +#define TIMPANI_TXFE1_TXFE1_EN_ENABLE 0x1 + +#define TIMPANI_TXFE1_TXFE1_GAIN_S 5 +#define TIMPANI_TXFE1_TXFE1_GAIN_M 0x60 +#define TIMPANI_TXFE1_TXFE1_GAIN_V_0DB 0x0 +#define TIMPANI_TXFE1_TXFE1_GAIN_V_4_5DB 0x1 +#define TIMPANI_TXFE1_TXFE1_GAIN_V_24DB_1 0x2 +#define TIMPANI_TXFE1_TXFE1_GAIN_V_24DB_2 0x3 + +#define TIMPANI_TXFE1_TXFE1_IN_MIC1_CONN_S 4 +#define TIMPANI_TXFE1_TXFE1_IN_MIC1_CONN_M 0x10 +#define TIMPANI_TXFE1_TXFE1_IN_MIC1_CONN_NO_CONNECT 0x0 +#define TIMPANI_TXFE1_TXFE1_IN_MIC1_CONN_CONNECT 0x1 + +#define TIMPANI_TXFE1_TXFE1_IN_MIC2_CONN_S 3 +#define TIMPANI_TXFE1_TXFE1_IN_MIC2_CONN_M 0x8 +#define TIMPANI_TXFE1_TXFE1_IN_MIC2_CONN_NO_CONNECT 0x0 +#define TIMPANI_TXFE1_TXFE1_IN_MIC2_CONN_CONNECT 0x1 + +#define TIMPANI_TXFE1_TXFE1_IN_LINE_I_L_CONN_S 2 +#define TIMPANI_TXFE1_TXFE1_IN_LINE_I_L_CONN_M 0x4 +#define TIMPANI_TXFE1_TXFE1_IN_LINE_I_L_CONN_NO_CONNECT 0x0 +#define TIMPANI_TXFE1_TXFE1_IN_LINE_I_L_CONN_CONNECT 0x1 + +#define TIMPANI_TXFE1_TXFE1_IN_LINE_I_R_CONN_S 1 +#define TIMPANI_TXFE1_TXFE1_IN_LINE_I_R_CONN_M 0x2 +#define TIMPANI_TXFE1_TXFE1_IN_LINE_I_R_CONN_NO_CONNECT 0x0 +#define TIMPANI_TXFE1_TXFE1_IN_LINE_I_R_CONN_CONNECT 0x1 + +#define TIMPANI_TXFE1_TXFE1_IN_AUXI_CONN_S 0 +#define TIMPANI_TXFE1_TXFE1_IN_AUXI_CONN_M 0x1 +#define TIMPANI_TXFE1_TXFE1_IN_AUXI_CONN_NO_CONNECT 0x0 +#define TIMPANI_TXFE1_TXFE1_IN_AUXI_CONN_CONNECT 0x1 + + +/* -- For TXFE2 */ +#define TIMPANI_A_TXFE2 (0xE) +#define TIMPANI_TXFE2_RWC "RW" +#define TIMPANI_TXFE2_POR 0 +#define TIMPANI_TXFE2_S 0 +#define TIMPANI_TXFE2_M 0xFF + + +#define TIMPANI_TXFE2_TXFE2_EN_S 7 +#define TIMPANI_TXFE2_TXFE2_EN_M 0x80 +#define TIMPANI_TXFE2_TXFE2_EN_DISABLE 0x0 +#define TIMPANI_TXFE2_TXFE2_EN_ENABLE 0x1 + +#define TIMPANI_TXFE2_TXFE2_GAIN_S 5 +#define TIMPANI_TXFE2_TXFE2_GAIN_M 0x60 +#define TIMPANI_TXFE2_TXFE2_GAIN_V_0DB 0x0 +#define TIMPANI_TXFE2_TXFE2_GAIN_V_4_5DB 0x1 +#define TIMPANI_TXFE2_TXFE2_GAIN_V_24DB_1 0x2 +#define TIMPANI_TXFE2_TXFE2_GAIN_V_24DB_2 0x3 + +#define TIMPANI_TXFE2_TXFE2_IN_MIC1_CONN_S 4 +#define TIMPANI_TXFE2_TXFE2_IN_MIC1_CONN_M 0x10 +#define TIMPANI_TXFE2_TXFE2_IN_MIC1_CONN_NO_CONNECT 0x0 +#define TIMPANI_TXFE2_TXFE2_IN_MIC1_CONN_CONNECT 0x1 + +#define TIMPANI_TXFE2_TXFE2_IN_MIC2_CONN_S 3 +#define TIMPANI_TXFE2_TXFE2_IN_MIC2_CONN_M 0x8 +#define TIMPANI_TXFE2_TXFE2_IN_MIC2_CONN_NO_CONNECT 0x0 +#define TIMPANI_TXFE2_TXFE2_IN_MIC2_CONN_CONNECT 0x1 + +#define TIMPANI_TXFE2_TXFE2_IN_LINE_I_L_CONN_S 2 +#define TIMPANI_TXFE2_TXFE2_IN_LINE_I_L_CONN_M 0x4 +#define TIMPANI_TXFE2_TXFE2_IN_LINE_I_L_CONN_NO_CONNECT 0x0 +#define TIMPANI_TXFE2_TXFE2_IN_LINE_I_L_CONN_CONNECT 0x1 + +#define TIMPANI_TXFE2_TXFE2_IN_LINE_I_R_CONN_S 1 +#define TIMPANI_TXFE2_TXFE2_IN_LINE_I_R_CONN_M 0x2 +#define TIMPANI_TXFE2_TXFE2_IN_LINE_I_R_CONN_NO_CONNECT 0x0 +#define TIMPANI_TXFE2_TXFE2_IN_LINE_I_R_CONN_CONNECT 0x1 + +#define TIMPANI_TXFE2_TXFE2_IN_AUXI_CONN_S 0 +#define TIMPANI_TXFE2_TXFE2_IN_AUXI_CONN_M 0x1 +#define TIMPANI_TXFE2_TXFE2_IN_AUXI_CONN_NO_CONNECT 0x0 +#define TIMPANI_TXFE2_TXFE2_IN_AUXI_CONN_CONNECT 0x1 + + +/* -- For TXFE12_ATEST */ +#define TIMPANI_A_TXFE12_ATEST (0xF) +#define TIMPANI_TXFE12_ATEST_RWC "RW" +#define TIMPANI_TXFE12_ATEST_POR 0 +#define TIMPANI_TXFE12_ATEST_S 0 +#define TIMPANI_TXFE12_ATEST_M 0xFF + + +#define TIMPANI_TXFE12_ATEST_TXFE1_OUT_SHORT_TO_VICM_EN_S 7 +#define TIMPANI_TXFE12_ATEST_TXFE1_OUT_SHORT_TO_VICM_EN_M 0x80 +#define TIMPANI_TXFE12_ATEST_TXFE1_OUT_SHORT_TO_VICM_EN_DISABLE 0x0 +#define TIMPANI_TXFE12_ATEST_TXFE1_OUT_SHORT_TO_VICM_EN_ENABLE 0x1 + +#define TIMPANI_TXFE12_ATEST_TXFE1_BYPASS_EN_S 6 +#define TIMPANI_TXFE12_ATEST_TXFE1_BYPASS_EN_M 0x40 +#define TIMPANI_TXFE12_ATEST_TXFE1_BYPASS_EN_DISABLE 0x0 +#define TIMPANI_TXFE12_ATEST_TXFE1_BYPASS_EN_ENABLE 0x1 + +#define TIMPANI_TXFE12_ATEST_TXFE1_CMOUT_ATEST_CONN_S 5 +#define TIMPANI_TXFE12_ATEST_TXFE1_CMOUT_ATEST_CONN_M 0x20 +#define TIMPANI_TXFE12_ATEST_TXFE1_CMOUT_ATEST_CONN_NO_CONNECT 0x0 +#define TIMPANI_TXFE12_ATEST_TXFE1_CMOUT_ATEST_CONN_CONNECT 0x1 + +#define TIMPANI_TXFE12_ATEST_TXFE1_OUT_ATEST_CONN_S 4 +#define TIMPANI_TXFE12_ATEST_TXFE1_OUT_ATEST_CONN_M 0x10 +#define TIMPANI_TXFE12_ATEST_TXFE1_OUT_ATEST_CONN_NO_CONNECT 0x0 +#define TIMPANI_TXFE12_ATEST_TXFE1_OUT_ATEST_CONN_CONNECT 0x1 + +#define TIMPANI_TXFE12_ATEST_TXFE2_OUT_SHORT_TO_VICM_EN_S 3 +#define TIMPANI_TXFE12_ATEST_TXFE2_OUT_SHORT_TO_VICM_EN_M 0x8 +#define TIMPANI_TXFE12_ATEST_TXFE2_OUT_SHORT_TO_VICM_EN_DISABLE 0x0 +#define TIMPANI_TXFE12_ATEST_TXFE2_OUT_SHORT_TO_VICM_EN_ENABLE 0x1 + +#define TIMPANI_TXFE12_ATEST_TXFE2_BYPASS_EN_S 2 +#define TIMPANI_TXFE12_ATEST_TXFE2_BYPASS_EN_M 0x4 +#define TIMPANI_TXFE12_ATEST_TXFE2_BYPASS_EN_DISABLE 0x0 +#define TIMPANI_TXFE12_ATEST_TXFE2_BYPASS_EN_ENABLE 0x1 + +#define TIMPANI_TXFE12_ATEST_TXFE2_CMOUT_ATEST_CONN_S 1 +#define TIMPANI_TXFE12_ATEST_TXFE2_CMOUT_ATEST_CONN_M 0x2 +#define TIMPANI_TXFE12_ATEST_TXFE2_CMOUT_ATEST_CONN_NO_CONNECT 0x0 +#define TIMPANI_TXFE12_ATEST_TXFE2_CMOUT_ATEST_CONN_CONNECT 0x1 + +#define TIMPANI_TXFE12_ATEST_TXFE2_OUT_ATEST_CONN_S 0 +#define TIMPANI_TXFE12_ATEST_TXFE2_OUT_ATEST_CONN_M 0x1 +#define TIMPANI_TXFE12_ATEST_TXFE2_OUT_ATEST_CONN_NO_CONNECT 0x0 +#define TIMPANI_TXFE12_ATEST_TXFE2_OUT_ATEST_CONN_CONNECT 0x1 + + +/* -- For TXFE_CLT */ +#define TIMPANI_A_TXFE_CLT (0x10) +#define TIMPANI_TXFE_CLT_RWC "RW" +#define TIMPANI_TXFE_CLT_POR 0x68 +#define TIMPANI_TXFE_CLT_S 0 +#define TIMPANI_TXFE_CLT_M 0xFF + + +#define TIMPANI_TXFE_CLT_TXFE_OUT_CM_VOLT_S 5 +#define TIMPANI_TXFE_CLT_TXFE_OUT_CM_VOLT_M 0xE0 +#define TIMPANI_TXFE_CLT_TXFE_OUT_CM_VOLT_V_1_125V 0x0 +#define TIMPANI_TXFE_CLT_TXFE_OUT_CM_VOLT_V_1_100V 0x1 +#define TIMPANI_TXFE_CLT_TXFE_OUT_CM_VOLT_V_1_075V 0x2 +#define TIMPANI_TXFE_CLT_TXFE_OUT_CM_VOLT_V_1_050V_NORMAL_OP 0x3 +#define TIMPANI_TXFE_CLT_TXFE_OUT_CM_VOLT_V_1_025V 0x4 +#define TIMPANI_TXFE_CLT_TXFE_OUT_CM_VOLT_V_1_000V 0x5 +#define TIMPANI_TXFE_CLT_TXFE_OUT_CM_VOLT_V_0_975V 0x6 +#define TIMPANI_TXFE_CLT_TXFE_OUT_CM_VOLT_V_0_950V 0x7 + +#define TIMPANI_TXFE_CLT_TXFE_BIAS_CUR_S 3 +#define TIMPANI_TXFE_CLT_TXFE_BIAS_CUR_M 0x18 +#define TIMPANI_TXFE_CLT_TXFE_BIAS_CUR_V_3UA 0x0 +#define TIMPANI_TXFE_CLT_TXFE_BIAS_CUR_V_4UA_NORMAL_OP 0x1 +#define TIMPANI_TXFE_CLT_TXFE_BIAS_CUR_V_6UA 0x2 +#define TIMPANI_TXFE_CLT_TXFE_BIAS_CUR_V_8UA 0x3 + +#define TIMPANI_TXFE_CLT_RESERVED_S 0 +#define TIMPANI_TXFE_CLT_RESERVED_M 0x7 + + +/* -- For TXADC1_EN */ +#define TIMPANI_A_TXADC1_EN (0x11) +#define TIMPANI_TXADC1_EN_RWC "RW" +#define TIMPANI_TXADC1_EN_POR 0 +#define TIMPANI_TXADC1_EN_S 0 +#define TIMPANI_TXADC1_EN_M 0xFF + + +#define TIMPANI_TXADC1_EN_TXADC1_REF_EN_S 7 +#define TIMPANI_TXADC1_EN_TXADC1_REF_EN_M 0x80 +#define TIMPANI_TXADC1_EN_TXADC1_REF_EN_DISABLE 0x0 +#define TIMPANI_TXADC1_EN_TXADC1_REF_EN_ENABLE 0x1 + +#define TIMPANI_TXADC1_EN_TXADC1_DAC_REF_CUR_COMPENSATION_EN_S 6 +#define TIMPANI_TXADC1_EN_TXADC1_DAC_REF_CUR_COMPENSATION_EN_M 0x40 +#define TIMPANI_TXADC1_EN_TXADC1_DAC_REF_CUR_COMPENSATION_EN_DISABLE 0x0 +#define TIMPANI_TXADC1_EN_TXADC1_DAC_REF_CUR_COMPENSATION_EN_ENABLE 0x1 + +#define TIMPANI_TXADC1_EN_TXADC1_OTA1_EN_S 5 +#define TIMPANI_TXADC1_EN_TXADC1_OTA1_EN_M 0x20 +#define TIMPANI_TXADC1_EN_TXADC1_OTA1_EN_DISABLE 0x0 +#define TIMPANI_TXADC1_EN_TXADC1_OTA1_EN_ENABLE 0x1 + +#define TIMPANI_TXADC1_EN_TXADC1_OTA2_EN_S 4 +#define TIMPANI_TXADC1_EN_TXADC1_OTA2_EN_M 0x10 +#define TIMPANI_TXADC1_EN_TXADC1_OTA2_EN_DISABLE 0x0 +#define TIMPANI_TXADC1_EN_TXADC1_OTA2_EN_ENABLE 0x1 + +#define TIMPANI_TXADC1_EN_TXADC1_COMP_EN_S 3 +#define TIMPANI_TXADC1_EN_TXADC1_COMP_EN_M 0x8 +#define TIMPANI_TXADC1_EN_TXADC1_COMP_EN_DISABLE 0x0 +#define TIMPANI_TXADC1_EN_TXADC1_COMP_EN_ENABLE 0x1 + +#define TIMPANI_TXADC1_EN_TXADC1_DEM_EN_S 2 +#define TIMPANI_TXADC1_EN_TXADC1_DEM_EN_M 0x4 +#define TIMPANI_TXADC1_EN_TXADC1_DEM_EN_DISABLE 0x0 +#define TIMPANI_TXADC1_EN_TXADC1_DEM_EN_ENABLE 0x1 + +#define TIMPANI_TXADC1_EN_TXADC1_DEM_ERROR_DET_EN_S 1 +#define TIMPANI_TXADC1_EN_TXADC1_DEM_ERROR_DET_EN_M 0x2 +#define TIMPANI_TXADC1_EN_TXADC1_DEM_ERROR_DET_EN_DISABLE 0x0 +#define TIMPANI_TXADC1_EN_TXADC1_DEM_ERROR_DET_EN_ENABLE 0x1 + +#define TIMPANI_TXADC1_EN_RESERVED_S 0 +#define TIMPANI_TXADC1_EN_RESERVED_M 0x1 + + +/* -- For TXADC2_EN */ +#define TIMPANI_A_TXADC2_EN (0x12) +#define TIMPANI_TXADC2_EN_RWC "RW" +#define TIMPANI_TXADC2_EN_POR 0 +#define TIMPANI_TXADC2_EN_S 0 +#define TIMPANI_TXADC2_EN_M 0xFF + + +#define TIMPANI_TXADC2_EN_TXADC2_REF_EN_S 7 +#define TIMPANI_TXADC2_EN_TXADC2_REF_EN_M 0x80 +#define TIMPANI_TXADC2_EN_TXADC2_REF_EN_DISABLE 0x0 +#define TIMPANI_TXADC2_EN_TXADC2_REF_EN_ENABLE 0x1 + +#define TIMPANI_TXADC2_EN_TXADC2_DAC_REF_CUR_COMPENSATION_EN_S 6 +#define TIMPANI_TXADC2_EN_TXADC2_DAC_REF_CUR_COMPENSATION_EN_M 0x40 +#define TIMPANI_TXADC2_EN_TXADC2_DAC_REF_CUR_COMPENSATION_EN_DISABLE 0x0 +#define TIMPANI_TXADC2_EN_TXADC2_DAC_REF_CUR_COMPENSATION_EN_ENABLE 0x1 + +#define TIMPANI_TXADC2_EN_TXADC2_OTA1_EN_S 5 +#define TIMPANI_TXADC2_EN_TXADC2_OTA1_EN_M 0x20 +#define TIMPANI_TXADC2_EN_TXADC2_OTA1_EN_DISABLE 0x0 +#define TIMPANI_TXADC2_EN_TXADC2_OTA1_EN_ENABLE 0x1 + +#define TIMPANI_TXADC2_EN_TXADC2_OTA2_EN_S 4 +#define TIMPANI_TXADC2_EN_TXADC2_OTA2_EN_M 0x10 +#define TIMPANI_TXADC2_EN_TXADC2_OTA2_EN_DISABLE 0x0 +#define TIMPANI_TXADC2_EN_TXADC2_OTA2_EN_ENABLE 0x1 + +#define TIMPANI_TXADC2_EN_TXADC2_COMP_EN_S 3 +#define TIMPANI_TXADC2_EN_TXADC2_COMP_EN_M 0x8 +#define TIMPANI_TXADC2_EN_TXADC2_COMP_EN_DISABLE 0x0 +#define TIMPANI_TXADC2_EN_TXADC2_COMP_EN_ENABLE 0x1 + +#define TIMPANI_TXADC2_EN_TXADC2_DEM_EN_S 2 +#define TIMPANI_TXADC2_EN_TXADC2_DEM_EN_M 0x4 +#define TIMPANI_TXADC2_EN_TXADC2_DEM_EN_DISABLE 0x0 +#define TIMPANI_TXADC2_EN_TXADC2_DEM_EN_ENABLE 0x1 + +#define TIMPANI_TXADC2_EN_TXADC2_DEM_ERROR_DET_EN_S 1 +#define TIMPANI_TXADC2_EN_TXADC2_DEM_ERROR_DET_EN_M 0x2 +#define TIMPANI_TXADC2_EN_TXADC2_DEM_ERROR_DET_EN_DISABLE 0x0 +#define TIMPANI_TXADC2_EN_TXADC2_DEM_ERROR_DET_EN_ENABLE 0x1 + +#define TIMPANI_TXADC2_EN_RESERVED_S 0 +#define TIMPANI_TXADC2_EN_RESERVED_M 0x1 + + +/* -- For TXADC_CTL */ +#define TIMPANI_A_TXADC_CTL (0x13) +#define TIMPANI_TXADC_CTL_RWC "RW" +#define TIMPANI_TXADC_CTL_POR 0x58 +#define TIMPANI_TXADC_CTL_S 0 +#define TIMPANI_TXADC_CTL_M 0xFF + + +#define TIMPANI_TXADC_CTL_TXADC_DAC_REF_DDA_AMP_BIAS_CUR_S 6 +#define TIMPANI_TXADC_CTL_TXADC_DAC_REF_DDA_AMP_BIAS_CUR_M 0xC0 +#define TIMPANI_TXADC_CTL_TXADC_DAC_REF_DDA_AMP_BIAS_CUR_V_5UA 0x0 +#define TIMPANI_TXADC_CTL_TXADC_DAC_REF_DDA_AMP_BIAS_CUR_V_10UA_NORMAL_OP 0x1 +#define TIMPANI_TXADC_CTL_TXADC_DAC_REF_DDA_AMP_BIAS_CUR_V_15UA 0x2 +#define TIMPANI_TXADC_CTL_TXADC_DAC_REF_DDA_AMP_BIAS_CUR_V_20UA 0x3 + +#define TIMPANI_TXADC_CTL_TXADC_DAC_REF_SRC_FOLLOWER_BIAS_CUR_S 4 +#define TIMPANI_TXADC_CTL_TXADC_DAC_REF_SRC_FOLLOWER_BIAS_CUR_M 0x30 +#define TIMPANI_TXADC_CTL_TXADC_DAC_REF_SRC_FOLLOWER_BIAS_CUR_V_40UA 0x0 +#define TIMPANI_TXADC_CTL_TXADC_DAC_REF_SRC_FOLLOWER_BIAS_CUR_V_80UA 0x1 +#define TIMPANI_TXADC_CTL_TXADC_DAC_REF_SRC_FOLLOWER_BIAS_CUR_V_120UA 0x2 +#define TIMPANI_TXADC_CTL_TXADC_DAC_REF_SRC_FOLLOWER_BIAS_CUR_V_160UA 0x3 + +#define TIMPANI_TXADC_CTL_TXADC_DAC_REF_VOLT_S 2 +#define TIMPANI_TXADC_CTL_TXADC_DAC_REF_VOLT_M 0xC +#define TIMPANI_TXADC_CTL_TXADC_DAC_REF_VOLT_V_1_8V 0x0 +#define TIMPANI_TXADC_CTL_TXADC_DAC_REF_VOLT_V_1_7V 0x1 +#define TIMPANI_TXADC_CTL_TXADC_DAC_REF_VOLT_V_1_6V_NORMAL_OP 0x2 +#define TIMPANI_TXADC_CTL_TXADC_DAC_REF_VOLT_V_1_5V 0x3 + +#define TIMPANI_TXADC_CTL_TXADC_VREFMID_BIAS_CUR_S 0 +#define TIMPANI_TXADC_CTL_TXADC_VREFMID_BIAS_CUR_M 0x3 +#define TIMPANI_TXADC_CTL_TXADC_VREFMID_BIAS_CUR_V_20UA_NORMAL_OP 0x0 +#define TIMPANI_TXADC_CTL_TXADC_VREFMID_BIAS_CUR_V_40UA 0x1 +#define TIMPANI_TXADC_CTL_TXADC_VREFMID_BIAS_CUR_V_80UA 0x2 +#define TIMPANI_TXADC_CTL_TXADC_VREFMID_BIAS_CUR_V_160UA 0x3 + + +/* -- For TXADC_CTL2 */ +#define TIMPANI_A_TXADC_CTL2 (0x14) +#define TIMPANI_TXADC_CTL2_RWC "RW" +#define TIMPANI_TXADC_CTL2_POR 0x64 +#define TIMPANI_TXADC_CTL2_S 0 +#define TIMPANI_TXADC_CTL2_M 0xFF + + +#define TIMPANI_TXADC_CTL2_TXADC_COMP_THRESH_VOLT_S 6 +#define TIMPANI_TXADC_CTL2_TXADC_COMP_THRESH_VOLT_M 0xC0 +#define TIMPANI_TXADC_CTL2_TXADC_COMP_THRESH_VOLT_V_333MV 0x0 +#define TIMPANI_TXADC_CTL2_TXADC_COMP_THRESH_VOLT_V_356MV_NORMAL_OP 0x1 +#define TIMPANI_TXADC_CTL2_TXADC_COMP_THRESH_VOLT_V_378MV 0x2 +#define TIMPANI_TXADC_CTL2_TXADC_COMP_THRESH_VOLT_V_400MV 0x3 + +#define TIMPANI_TXADC_CTL2_TXADC_VICM_REF_BUFF_BIAS_CUR_S 4 +#define TIMPANI_TXADC_CTL2_TXADC_VICM_REF_BUFF_BIAS_CUR_M 0x30 +#define TIMPANI_TXADC_CTL2_TXADC_VICM_REF_BUFF_BIAS_CUR_V_50UA 0x0 +#define TIMPANI_TXADC_CTL2_TXADC_VICM_REF_BUFF_BIAS_CUR_V_100UA 0x1 +#define TIMPANI_TXADC_CTL2_TXADC_VICM_REF_BUFF_BIAS_CUR_V_200UA_NORMAL_OP 0x2 +#define TIMPANI_TXADC_CTL2_TXADC_VICM_REF_BUFF_BIAS_CUR_V_400UA 0x3 + +#define TIMPANI_TXADC_CTL2_TXADC_VICM_REF_BUFF_OUT_VOLT_S 2 +#define TIMPANI_TXADC_CTL2_TXADC_VICM_REF_BUFF_OUT_VOLT_M 0xC +#define TIMPANI_TXADC_CTL2_TXADC_VICM_REF_BUFF_OUT_VOLT_V_1_1V 0x0 +#define TIMPANI_TXADC_CTL2_TXADC_VICM_REF_BUFF_OUT_VOLT_V_1_15V_NORMAL_OP 0x1 +#define TIMPANI_TXADC_CTL2_TXADC_VICM_REF_BUFF_OUT_VOLT_V_1_2V 0x2 +#define TIMPANI_TXADC_CTL2_TXADC_VICM_REF_BUFF_OUT_VOLT_V_1_25V 0x3 + +#define TIMPANI_TXADC_CTL2_TXADC_VOCM_BUFFER_BIAS_CUR_S 1 +#define TIMPANI_TXADC_CTL2_TXADC_VOCM_BUFFER_BIAS_CUR_M 0x2 +#define TIMPANI_TXADC_CTL2_TXADC_VOCM_BUFFER_BIAS_CUR_V_50UA_NORMAL_OP 0x0 +#define TIMPANI_TXADC_CTL2_TXADC_VOCM_BUFFER_BIAS_CUR_V_100UA 0x1 + +#define TIMPANI_TXADC_CTL2_TXADC_DIG_OUT_EN_S 0 +#define TIMPANI_TXADC_CTL2_TXADC_DIG_OUT_EN_M 0x1 +#define TIMPANI_TXADC_CTL2_TXADC_DIG_OUT_EN_DISABLE 0x0 +#define TIMPANI_TXADC_CTL2_TXADC_DIG_OUT_EN_ENABLE_NORMAL_OP 0x1 + + +/* -- For TXADC_CTL3 */ +#define TIMPANI_A_TXADC_CTL3 (0x15) +#define TIMPANI_TXADC_CTL3_RWC "RW" +#define TIMPANI_TXADC_CTL3_POR 0x64 +#define TIMPANI_TXADC_CTL3_S 0 +#define TIMPANI_TXADC_CTL3_M 0xFF + + +#define TIMPANI_TXADC_CTL3_TXADC_VOCM_REF_BUFF_VOLT_S 6 +#define TIMPANI_TXADC_CTL3_TXADC_VOCM_REF_BUFF_VOLT_M 0xC0 +#define TIMPANI_TXADC_CTL3_TXADC_VOCM_REF_BUFF_VOLT_V_0_85V 0x0 +#define TIMPANI_TXADC_CTL3_TXADC_VOCM_REF_BUFF_VOLT_V_0_90V_NORMAL_OP 0x1 +#define TIMPANI_TXADC_CTL3_TXADC_VOCM_REF_BUFF_VOLT_V_0_95V 0x2 +#define TIMPANI_TXADC_CTL3_TXADC_VOCM_REF_BUFF_VOLT_V_1_00V 0x3 + +#define TIMPANI_TXADC_CTL3_TXADC_OTA1_BIAS_CUR_S 4 +#define TIMPANI_TXADC_CTL3_TXADC_OTA1_BIAS_CUR_M 0x30 +#define TIMPANI_TXADC_CTL3_TXADC_OTA1_BIAS_CUR_V_10UA 0x0 +#define TIMPANI_TXADC_CTL3_TXADC_OTA1_BIAS_CUR_V_15UA 0x1 +#define TIMPANI_TXADC_CTL3_TXADC_OTA1_BIAS_CUR_V_20UA_NORMAL_OP 0x2 +#define TIMPANI_TXADC_CTL3_TXADC_OTA1_BIAS_CUR_V_25UA 0x3 + +#define TIMPANI_TXADC_CTL3_TXADC_OTA2_BIAS_CUR_S 2 +#define TIMPANI_TXADC_CTL3_TXADC_OTA2_BIAS_CUR_M 0xC +#define TIMPANI_TXADC_CTL3_TXADC_OTA2_BIAS_CUR_V_5UA 0x0 +#define TIMPANI_TXADC_CTL3_TXADC_OTA2_BIAS_CUR_V_10UA_NORMAL_OP 0x1 +#define TIMPANI_TXADC_CTL3_TXADC_OTA2_BIAS_CUR_V_15UA 0x2 +#define TIMPANI_TXADC_CTL3_TXADC_OTA2_BIAS_CUR_V_20UA 0x3 + +#define TIMPANI_TXADC_CTL3_TXADC_COMP_BIAS_CUR_S 1 +#define TIMPANI_TXADC_CTL3_TXADC_COMP_BIAS_CUR_M 0x2 +#define TIMPANI_TXADC_CTL3_TXADC_COMP_BIAS_CUR_V_5UA_NORMAL_OP 0x0 +#define TIMPANI_TXADC_CTL3_TXADC_COMP_BIAS_CUR_V_10UA 0x1 + +#define TIMPANI_TXADC_CTL3_RESERVED_S 0 +#define TIMPANI_TXADC_CTL3_RESERVED_M 0x1 + + +/* -- For TXADC_CHOP_CTL */ +#define TIMPANI_A_TXADC_CHOP_CTL (0x16) +#define TIMPANI_TXADC_CHOP_CTL_RWC "RW" +#define TIMPANI_TXADC_CHOP_CTL_POR 0 +#define TIMPANI_TXADC_CHOP_CTL_S 0 +#define TIMPANI_TXADC_CHOP_CTL_M 0xFF + + +#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_EN_S 7 +#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_EN_M 0x80 +#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_EN_DISABLE 0x0 +#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_EN_ENABLE 0x1 + +#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_DIV_RATIO_S 4 +#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_DIV_RATIO_M 0x70 +#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_DIV_RATIO_V_2_NORMAL_OP 0x0 +#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_DIV_RATIO_V_4 0x1 +#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_DIV_RATIO_V_8 0x2 +#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_DIV_RATIO_V_16 0x3 +#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_DIV_RATIO_V_32 0x4 +#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_DIV_RATIO_V_64 0x5 +#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_DIV_RATIO_V_128 0x6 +#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_DIV_RATIO_V_256 0x7 + +#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_STATE_RESET_S 3 +#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_STATE_RESET_M 0x8 +#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_STATE_RESET_NORMAL_OP 0x0 +#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_STATE_RESET_RESET_CHOP 0x1 + +#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_CLK_PHASE_SEL_S 2 +#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_CLK_PHASE_SEL_M 0x4 +#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_CLK_PHASE_SEL_FALLING_EDGE_CK1 0x0 +#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_CLK_PHASE_SEL_FALLING_EDGE_CK2 0x1 + +#define TIMPANI_TXADC_CHOP_CTL_RESERVED_S 0 +#define TIMPANI_TXADC_CHOP_CTL_RESERVED_M 0x3 + + +/* -- For TXFE3 */ +#define TIMPANI_A_TXFE3 (0x18) +#define TIMPANI_TXFE3_RWC "RW" +#define TIMPANI_TXFE3_POR 0 +#define TIMPANI_TXFE3_S 0 +#define TIMPANI_TXFE3_M 0xFF + + +#define TIMPANI_TXFE3_TXFE3_EN_S 7 +#define TIMPANI_TXFE3_TXFE3_EN_M 0x80 +#define TIMPANI_TXFE3_TXFE3_EN_DISABLE 0x0 +#define TIMPANI_TXFE3_TXFE3_EN_ENABLE 0x1 + +#define TIMPANI_TXFE3_TXFE3_GAIN_S 5 +#define TIMPANI_TXFE3_TXFE3_GAIN_M 0x60 +#define TIMPANI_TXFE3_TXFE3_GAIN_V_0DB 0x0 +#define TIMPANI_TXFE3_TXFE3_GAIN_V_4_5DB 0x1 +#define TIMPANI_TXFE3_TXFE3_GAIN_V_24DB_1 0x2 +#define TIMPANI_TXFE3_TXFE3_GAIN_V_24DB_2 0x3 + +#define TIMPANI_TXFE3_RESERVED_1_S 2 +#define TIMPANI_TXFE3_RESERVED_1_M 0x1C + +#define TIMPANI_TXFE3_TXFE3_IN_CONN_S 1 +#define TIMPANI_TXFE3_TXFE3_IN_CONN_M 0x2 +#define TIMPANI_TXFE3_TXFE3_IN_CONN_NO_CONNECT 0x0 +#define TIMPANI_TXFE3_TXFE3_IN_CONN_LINE_IN_L 0x1 + +#define TIMPANI_TXFE3_RESERVED_2_S 0 +#define TIMPANI_TXFE3_RESERVED_2_M 0x1 + + +/* -- For TXFE4 */ +#define TIMPANI_A_TXFE4 (0x19) +#define TIMPANI_TXFE4_RWC "RW" +#define TIMPANI_TXFE4_POR 0 +#define TIMPANI_TXFE4_S 0 +#define TIMPANI_TXFE4_M 0xFF + + +#define TIMPANI_TXFE4_TXFE4_EN_S 7 +#define TIMPANI_TXFE4_TXFE4_EN_M 0x80 +#define TIMPANI_TXFE4_TXFE4_EN_DISABLE 0x0 +#define TIMPANI_TXFE4_TXFE4_EN_ENABLE 0x1 + +#define TIMPANI_TXFE4_TXFE4_GAIN_S 5 +#define TIMPANI_TXFE4_TXFE4_GAIN_M 0x60 +#define TIMPANI_TXFE4_TXFE4_GAIN_V_0DB 0x0 +#define TIMPANI_TXFE4_TXFE4_GAIN_V_4_5DB 0x1 +#define TIMPANI_TXFE4_TXFE4_GAIN_V_24DB_1 0x2 +#define TIMPANI_TXFE4_TXFE4_GAIN_V_24DB_2 0x3 + +#define TIMPANI_TXFE4_RESERVED_1_S 2 +#define TIMPANI_TXFE4_RESERVED_1_M 0x1C + +#define TIMPANI_TXFE4_TXFE4_IN_CONN_S 1 +#define TIMPANI_TXFE4_TXFE4_IN_CONN_M 0x2 +#define TIMPANI_TXFE4_TXFE4_IN_CONN_NO_CONNECT 0x0 +#define TIMPANI_TXFE4_TXFE4_IN_CONN_LINE_IN_R 0x1 + +#define TIMPANI_TXFE4_RESERVED_2_S 0 +#define TIMPANI_TXFE4_RESERVED_2_M 0x1 + + +/* -- For TXFE3_ATEST */ +#define TIMPANI_A_TXFE3_ATEST (0x1A) +#define TIMPANI_TXFE3_ATEST_RWC "RW" +#define TIMPANI_TXFE3_ATEST_POR 0 +#define TIMPANI_TXFE3_ATEST_S 0 +#define TIMPANI_TXFE3_ATEST_M 0xFF + + +#define TIMPANI_TXFE3_ATEST_TXFE3_OUT_SHORT_TO_VICM_EN_S 7 +#define TIMPANI_TXFE3_ATEST_TXFE3_OUT_SHORT_TO_VICM_EN_M 0x80 +#define TIMPANI_TXFE3_ATEST_TXFE3_OUT_SHORT_TO_VICM_EN_DISABLE 0x0 +#define TIMPANI_TXFE3_ATEST_TXFE3_OUT_SHORT_TO_VICM_EN_ENABLE 0x1 + +#define TIMPANI_TXFE3_ATEST_TXFE3_BYPASS_EN_S 6 +#define TIMPANI_TXFE3_ATEST_TXFE3_BYPASS_EN_M 0x40 +#define TIMPANI_TXFE3_ATEST_TXFE3_BYPASS_EN_DISABLE 0x0 +#define TIMPANI_TXFE3_ATEST_TXFE3_BYPASS_EN_ENABLE 0x1 + +#define TIMPANI_TXFE3_ATEST_TXFE3_CMOUT_ATEST_CONN_S 5 +#define TIMPANI_TXFE3_ATEST_TXFE3_CMOUT_ATEST_CONN_M 0x20 +#define TIMPANI_TXFE3_ATEST_TXFE3_CMOUT_ATEST_CONN_NO_CONNECT 0x0 +#define TIMPANI_TXFE3_ATEST_TXFE3_CMOUT_ATEST_CONN_CONNECT 0x1 + +#define TIMPANI_TXFE3_ATEST_TXFE3_OUT_ATEST_CONN_S 4 +#define TIMPANI_TXFE3_ATEST_TXFE3_OUT_ATEST_CONN_M 0x10 +#define TIMPANI_TXFE3_ATEST_TXFE3_OUT_ATEST_CONN_NO_CONNECT 0x0 +#define TIMPANI_TXFE3_ATEST_TXFE3_OUT_ATEST_CONN_CONNECT 0x1 + +#define TIMPANI_TXFE3_ATEST_TXFE4_OUT_SHORT_TO_VICM_EN_S 3 +#define TIMPANI_TXFE3_ATEST_TXFE4_OUT_SHORT_TO_VICM_EN_M 0x8 +#define TIMPANI_TXFE3_ATEST_TXFE4_OUT_SHORT_TO_VICM_EN_DISABLE 0x0 +#define TIMPANI_TXFE3_ATEST_TXFE4_OUT_SHORT_TO_VICM_EN_ENABLE 0x1 + +#define TIMPANI_TXFE3_ATEST_TXFE4_BYPASS_EN_S 2 +#define TIMPANI_TXFE3_ATEST_TXFE4_BYPASS_EN_M 0x4 +#define TIMPANI_TXFE3_ATEST_TXFE4_BYPASS_EN_DISABLE 0x0 +#define TIMPANI_TXFE3_ATEST_TXFE4_BYPASS_EN_ENABLE 0x1 + +#define TIMPANI_TXFE3_ATEST_TXFE4_CMOUT_ATEST_CONN_S 1 +#define TIMPANI_TXFE3_ATEST_TXFE4_CMOUT_ATEST_CONN_M 0x2 +#define TIMPANI_TXFE3_ATEST_TXFE4_CMOUT_ATEST_CONN_NO_CONNECT 0x0 +#define TIMPANI_TXFE3_ATEST_TXFE4_CMOUT_ATEST_CONN_CONNECT 0x1 + +#define TIMPANI_TXFE3_ATEST_TXFE4_OUT_ATEST_CONN_S 0 +#define TIMPANI_TXFE3_ATEST_TXFE4_OUT_ATEST_CONN_M 0x1 +#define TIMPANI_TXFE3_ATEST_TXFE4_OUT_ATEST_CONN_NO_CONNECT 0x0 +#define TIMPANI_TXFE3_ATEST_TXFE4_OUT_ATEST_CONN_CONNECT 0x1 + + +/* -- For TXFE_DIFF_SE */ +#define TIMPANI_A_TXFE_DIFF_SE (0x1B) +#define TIMPANI_TXFE_DIFF_SE_RWC "RW" +#define TIMPANI_TXFE_DIFF_SE_POR 0 +#define TIMPANI_TXFE_DIFF_SE_S 0 +#define TIMPANI_TXFE_DIFF_SE_M 0xFF + + +#define TIMPANI_TXFE_DIFF_SE_RESERVED_S 4 +#define TIMPANI_TXFE_DIFF_SE_RESERVED_M 0xF0 + +#define TIMPANI_TXFE_DIFF_SE_TXADC1_IN_MODE_S 3 +#define TIMPANI_TXFE_DIFF_SE_TXADC1_IN_MODE_M 0x8 +#define TIMPANI_TXFE_DIFF_SE_TXADC1_IN_MODE_DIFF 0x0 +#define TIMPANI_TXFE_DIFF_SE_TXADC1_IN_MODE_SINGLE_ENDED 0x1 + +#define TIMPANI_TXFE_DIFF_SE_TXADC2_IN_MODE_S 2 +#define TIMPANI_TXFE_DIFF_SE_TXADC2_IN_MODE_M 0x4 +#define TIMPANI_TXFE_DIFF_SE_TXADC2_IN_MODE_DIFF 0x0 +#define TIMPANI_TXFE_DIFF_SE_TXADC2_IN_MODE_SINGLE_ENDED 0x1 + +#define TIMPANI_TXFE_DIFF_SE_TXADC3_IN_MODE_S 1 +#define TIMPANI_TXFE_DIFF_SE_TXADC3_IN_MODE_M 0x2 +#define TIMPANI_TXFE_DIFF_SE_TXADC3_IN_MODE_DIFF 0x0 +#define TIMPANI_TXFE_DIFF_SE_TXADC3_IN_MODE_SINGLE_ENDED 0x1 + +#define TIMPANI_TXFE_DIFF_SE_TXADC4_IN_MODE_S 0 +#define TIMPANI_TXFE_DIFF_SE_TXADC4_IN_MODE_M 0x1 +#define TIMPANI_TXFE_DIFF_SE_TXADC4_IN_MODE_DIFF 0x0 +#define TIMPANI_TXFE_DIFF_SE_TXADC4_IN_MODE_SINGLE_ENDED 0x1 + + +/* -- For CDAC_RX_CLK_CTL */ +#define TIMPANI_A_CDAC_RX_CLK_CTL (0x20) +#define TIMPANI_CDAC_RX_CLK_CTL_RWC "RW" +#define TIMPANI_CDAC_RX_CLK_CTL_POR 0x98 +#define TIMPANI_CDAC_RX_CLK_CTL_S 0 +#define TIMPANI_CDAC_RX_CLK_CTL_M 0xFF + + +#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_RESET_PULSE_GEN_EN_S 7 +#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_RESET_PULSE_GEN_EN_M 0x80 +#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_RESET_PULSE_GEN_EN_DISABLE 0x0 +#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_RESET_PULSE_GEN_EN_ENABLE_NORMAL_OP 0x1 + +#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_CTRL_EN_S 6 +#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_CTRL_EN_M 0x40 +#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_CTRL_EN_DISABLE_NORMAL_OP 0x0 +#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_CTRL_EN_ENABLE 0x1 + +#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_S 2 +#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_M 0x3C +#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_V_6NS 0x0 +#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_V_8_4NS 0x1 +#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_V_10_8NS 0x2 +#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_V_13_2NS 0x3 +#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_V_15_6NS 0x4 +#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_V_18NS 0x5 +#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_V_20_4NS_NORMAL_OP 0x6 +#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_V_22_8NS 0x7 +#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_V_25_2NS 0x8 +#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_V_27_6NS 0x9 +#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_V_30NS 0xA +#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_V_32_4NS 0xB +#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_V_34_8NS 0xC +#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_V_37_2NS 0xD +#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_V_39_6NS 0xE +#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_V_42NS 0xF + +#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_FF_RESET_S 1 +#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_FF_RESET_M 0x2 +#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_FF_RESET_ENABLE 0x1 +#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_FF_RESET_DISABLE 0x0 + +#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_RESET_PULSE_GEN_ATEST_CONN_S 0 +#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_RESET_PULSE_GEN_ATEST_CONN_M 0x1 +#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_RESET_PULSE_GEN_ATEST_CONN_NO_CONNECT 0x0 +#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_RESET_PULSE_GEN_ATEST_CONN_CONNECT 0x1 + + +/* -- For CDAC_BUFF_CTL */ +#define TIMPANI_A_CDAC_BUFF_CTL (0x21) +#define TIMPANI_CDAC_BUFF_CTL_RWC "RW" +#define TIMPANI_CDAC_BUFF_CTL_POR 0x60 +#define TIMPANI_CDAC_BUFF_CTL_S 0 +#define TIMPANI_CDAC_BUFF_CTL_M 0xFF + + +#define TIMPANI_CDAC_BUFF_CTL_CDAC_DM_BUFF_CUR_S 5 +#define TIMPANI_CDAC_BUFF_CTL_CDAC_DM_BUFF_CUR_M 0xE0 +#define TIMPANI_CDAC_BUFF_CTL_CDAC_DM_BUFF_CUR_V_40UA 0x0 +#define TIMPANI_CDAC_BUFF_CTL_CDAC_DM_BUFF_CUR_V_60UA_NORMAL_OP 0x1 +#define TIMPANI_CDAC_BUFF_CTL_CDAC_DM_BUFF_CUR_V_80UA 0x2 +#define TIMPANI_CDAC_BUFF_CTL_CDAC_DM_BUFF_CUR_V_100UA 0x3 +#define TIMPANI_CDAC_BUFF_CTL_CDAC_DM_BUFF_CUR_V_120UA 0x4 +#define TIMPANI_CDAC_BUFF_CTL_CDAC_DM_BUFF_CUR_V_140UA 0x5 +#define TIMPANI_CDAC_BUFF_CTL_CDAC_DM_BUFF_CUR_V_160UA 0x6 +#define TIMPANI_CDAC_BUFF_CTL_CDAC_DM_BUFF_CUR_V_180UA 0x7 + +#define TIMPANI_CDAC_BUFF_CTL_CDAC_CM_BUFF_CUR_S 3 +#define TIMPANI_CDAC_BUFF_CTL_CDAC_CM_BUFF_CUR_M 0x18 +#define TIMPANI_CDAC_BUFF_CTL_CDAC_CM_BUFF_CUR_V_20UA 0x0 +#define TIMPANI_CDAC_BUFF_CTL_CDAC_CM_BUFF_CUR_V_30UA_NORMAL_OP 0x1 +#define TIMPANI_CDAC_BUFF_CTL_CDAC_CM_BUFF_CUR_V_40UA 0x2 +#define TIMPANI_CDAC_BUFF_CTL_CDAC_CM_BUFF_CUR_V_50UA 0x3 + +#define TIMPANI_CDAC_BUFF_CTL_CDAC_REF_BUFF_OTA_BIAS_CUR_S 1 +#define TIMPANI_CDAC_BUFF_CTL_CDAC_REF_BUFF_OTA_BIAS_CUR_M 0x6 +#define TIMPANI_CDAC_BUFF_CTL_CDAC_REF_BUFF_OTA_BIAS_CUR_V_5UA_5UA 0x0 +#define TIMPANI_CDAC_BUFF_CTL_CDAC_REF_BUFF_OTA_BIAS_CUR_V_5UA_10UA 0x1 +#define TIMPANI_CDAC_BUFF_CTL_CDAC_REF_BUFF_OTA_BIAS_CUR_V_10UA_5UA 0x2 +#define TIMPANI_CDAC_BUFF_CTL_CDAC_REF_BUFF_OTA_BIAS_CUR_V_10UA_10UA 0x3 + +#define TIMPANI_CDAC_BUFF_CTL_CDAC_VCOM_SOURCE_S 0 +#define TIMPANI_CDAC_BUFF_CTL_CDAC_VCOM_SOURCE_M 0x1 +#define TIMPANI_CDAC_BUFF_CTL_CDAC_VCOM_SOURCE_CURRENT_TO_VCOM_NORMAL_OP 0x0 +#define TIMPANI_CDAC_BUFF_CTL_CDAC_VCOM_SOURCE_MASTER_BIAS_TO_VCOM 0x1 + + +/* -- For CDAC_REF_CTL1 */ +#define TIMPANI_A_CDAC_REF_CTL1 (0x22) +#define TIMPANI_CDAC_REF_CTL1_RWC "RW" +#define TIMPANI_CDAC_REF_CTL1_POR 0xe1 +#define TIMPANI_CDAC_REF_CTL1_S 0 +#define TIMPANI_CDAC_REF_CTL1_M 0xFF + + +#define TIMPANI_CDAC_REF_CTL1_CDAC_DACH_VOLT_S 5 +#define TIMPANI_CDAC_REF_CTL1_CDAC_DACH_VOLT_M 0xE0 +#define TIMPANI_CDAC_REF_CTL1_CDAC_DACH_VOLT_V_1_8V 0x0 +#define TIMPANI_CDAC_REF_CTL1_CDAC_DACH_VOLT_V_1_825V 0x1 +#define TIMPANI_CDAC_REF_CTL1_CDAC_DACH_VOLT_V_1_85V 0x2 +#define TIMPANI_CDAC_REF_CTL1_CDAC_DACH_VOLT_V_1_9V 0x3 +#define TIMPANI_CDAC_REF_CTL1_CDAC_DACH_VOLT_V_1_925V 0x4 +#define TIMPANI_CDAC_REF_CTL1_CDAC_DACH_VOLT_V_1_95V_NORMAL_OP 0x5 +#define TIMPANI_CDAC_REF_CTL1_CDAC_DACH_VOLT_V_1_975 0x6 +#define TIMPANI_CDAC_REF_CTL1_CDAC_DACH_VOLT_V_2_0V 0x7 + +#define TIMPANI_CDAC_REF_CTL1_CDAC_DACL_VOLT_S 2 +#define TIMPANI_CDAC_REF_CTL1_CDAC_DACL_VOLT_M 0x1C +#define TIMPANI_CDAC_REF_CTL1_CDAC_DACL_VOLT_V_0_1V 0x0 +#define TIMPANI_CDAC_REF_CTL1_CDAC_DACL_VOLT_V_0_125V 0x1 +#define TIMPANI_CDAC_REF_CTL1_CDAC_DACL_VOLT_V_0_15V_NORMAL_OP 0x2 +#define TIMPANI_CDAC_REF_CTL1_CDAC_DACL_VOLT_V_0_175V 0x3 +#define TIMPANI_CDAC_REF_CTL1_CDAC_DACL_VOLT_V_0_2V 0x4 +#define TIMPANI_CDAC_REF_CTL1_CDAC_DACL_VOLT_V_0_25V 0x5 +#define TIMPANI_CDAC_REF_CTL1_CDAC_DACL_VOLT_V_0_275V 0x6 +#define TIMPANI_CDAC_REF_CTL1_CDAC_DACL_VOLT_V_0_3V 0x7 + +#define TIMPANI_CDAC_REF_CTL1_CDAC_CM_VOLT_S 0 +#define TIMPANI_CDAC_REF_CTL1_CDAC_CM_VOLT_M 0x3 +#define TIMPANI_CDAC_REF_CTL1_CDAC_CM_VOLT_V_1_025V 0x0 +#define TIMPANI_CDAC_REF_CTL1_CDAC_CM_VOLT_V_1_05V_NORMAL_OP 0x1 +#define TIMPANI_CDAC_REF_CTL1_CDAC_CM_VOLT_V_1_075V 0x2 +#define TIMPANI_CDAC_REF_CTL1_CDAC_CM_VOLT_V_1_1V 0x3 + + +/* -- For IDAC_DWA_FIR_CTL */ +#define TIMPANI_A_IDAC_DWA_FIR_CTL (0x23) +#define TIMPANI_IDAC_DWA_FIR_CTL_RWC "RW" +#define TIMPANI_IDAC_DWA_FIR_CTL_POR 0x28 +#define TIMPANI_IDAC_DWA_FIR_CTL_S 0 +#define TIMPANI_IDAC_DWA_FIR_CTL_M 0xFF + + +#define TIMPANI_IDAC_DWA_FIR_CTL_IDAC_CLK_NON_OL_TIME_S 7 +#define TIMPANI_IDAC_DWA_FIR_CTL_IDAC_CLK_NON_OL_TIME_M 0x80 +#define TIMPANI_IDAC_DWA_FIR_CTL_IDAC_CLK_NON_OL_TIME_NORMAL_OP 0x0 +#define TIMPANI_IDAC_DWA_FIR_CTL_IDAC_CLK_NON_OL_TIME_V_150PSEC_REDUCTION 0x1 + +#define TIMPANI_IDAC_DWA_FIR_CTL_IDAC_FIR_S 4 +#define TIMPANI_IDAC_DWA_FIR_CTL_IDAC_FIR_M 0x70 +#define TIMPANI_IDAC_DWA_FIR_CTL_IDAC_FIR_FIR0 0x0 +#define TIMPANI_IDAC_DWA_FIR_CTL_IDAC_FIR_FIR1 0x1 +#define TIMPANI_IDAC_DWA_FIR_CTL_IDAC_FIR_FIR2 0x2 +#define TIMPANI_IDAC_DWA_FIR_CTL_IDAC_FIR_FIR3 0x3 +#define TIMPANI_IDAC_DWA_FIR_CTL_IDAC_FIR_FIR4 0x4 + +#define TIMPANI_IDAC_DWA_FIR_CTL_IDAC_EN_SOURCE_S 3 +#define TIMPANI_IDAC_DWA_FIR_CTL_IDAC_EN_SOURCE_M 0x8 +#define TIMPANI_IDAC_DWA_FIR_CTL_IDAC_EN_SOURCE_INTERNAL_NORMAL_OP 0x1 +#define TIMPANI_IDAC_DWA_FIR_CTL_IDAC_EN_SOURCE_EXTERNAL 0x0 + +#define TIMPANI_IDAC_DWA_FIR_CTL_RESERVED_S 0 +#define TIMPANI_IDAC_DWA_FIR_CTL_RESERVED_M 0x7 + + +/* -- For CDAC_REF_CTL2 */ +#define TIMPANI_A_CDAC_REF_CTL2 (0x24) +#define TIMPANI_CDAC_REF_CTL2_RWC "RW" +#define TIMPANI_CDAC_REF_CTL2_POR 0xc +#define TIMPANI_CDAC_REF_CTL2_S 0 +#define TIMPANI_CDAC_REF_CTL2_M 0xFF + + +#define TIMPANI_CDAC_REF_CTL2_RESERVED_1_S 7 +#define TIMPANI_CDAC_REF_CTL2_RESERVED_1_M 0x80 + +#define TIMPANI_CDAC_REF_CTL2_CDAC_L_EN_S 6 +#define TIMPANI_CDAC_REF_CTL2_CDAC_L_EN_M 0x40 +#define TIMPANI_CDAC_REF_CTL2_CDAC_L_EN_DISABLE 0x0 +#define TIMPANI_CDAC_REF_CTL2_CDAC_L_EN_ENABLE 0x1 + +#define TIMPANI_CDAC_REF_CTL2_CDAC_R_EN_S 5 +#define TIMPANI_CDAC_REF_CTL2_CDAC_R_EN_M 0x20 +#define TIMPANI_CDAC_REF_CTL2_CDAC_R_EN_DISABLE 0x0 +#define TIMPANI_CDAC_REF_CTL2_CDAC_R_EN_ENABLE 0x1 + +#define TIMPANI_CDAC_REF_CTL2_RESERVED_2_S 4 +#define TIMPANI_CDAC_REF_CTL2_RESERVED_2_M 0x10 + +#define TIMPANI_CDAC_REF_CTL2_CDAC_DWA_RX_FILTER_TIMING_S 2 +#define TIMPANI_CDAC_REF_CTL2_CDAC_DWA_RX_FILTER_TIMING_M 0xC +#define TIMPANI_CDAC_REF_CTL2_CDAC_DWA_RX_FILTER_TIMING_CLK_SYNC_CK11DBAR 0x1 +#define TIMPANI_CDAC_REF_CTL2_CDAC_DWA_RX_FILTER_TIMING_CLK_SYNC_CK21 0x3 + +#define TIMPANI_CDAC_REF_CTL2_CDAC_OSR_S 0 +#define TIMPANI_CDAC_REF_CTL2_CDAC_OSR_M 0x3 +#define TIMPANI_CDAC_REF_CTL2_CDAC_OSR_V_256 0x0 +#define TIMPANI_CDAC_REF_CTL2_CDAC_OSR_V_128 0x1 +#define TIMPANI_CDAC_REF_CTL2_CDAC_OSR_V_64 0x3 + + +/* -- For CDAC_CTL1 */ +#define TIMPANI_A_CDAC_CTL1 (0x25) +#define TIMPANI_CDAC_CTL1_RWC "RW" +#define TIMPANI_CDAC_CTL1_POR 0xb +#define TIMPANI_CDAC_CTL1_S 0 +#define TIMPANI_CDAC_CTL1_M 0xFF + + +#define TIMPANI_CDAC_CTL1_RESERVED_S 6 +#define TIMPANI_CDAC_CTL1_RESERVED_M 0xC0 + +#define TIMPANI_CDAC_CTL1_CDAC_L_OUT_SHORT_EN_S 5 +#define TIMPANI_CDAC_CTL1_CDAC_L_OUT_SHORT_EN_M 0x20 +#define TIMPANI_CDAC_CTL1_CDAC_L_OUT_SHORT_EN_DISABLE 0x0 +#define TIMPANI_CDAC_CTL1_CDAC_L_OUT_SHORT_EN_ENABLE 0x1 + +#define TIMPANI_CDAC_CTL1_CDAC_R_OUT_SHORT_EN_S 4 +#define TIMPANI_CDAC_CTL1_CDAC_R_OUT_SHORT_EN_M 0x10 +#define TIMPANI_CDAC_CTL1_CDAC_R_OUT_SHORT_EN_DISABLE 0x0 +#define TIMPANI_CDAC_CTL1_CDAC_R_OUT_SHORT_EN_ENABLE 0x1 + +#define TIMPANI_CDAC_CTL1_CDAC_REF_RESISTOR_VOLT_S 2 +#define TIMPANI_CDAC_CTL1_CDAC_REF_RESISTOR_VOLT_M 0xC +#define TIMPANI_CDAC_CTL1_CDAC_REF_RESISTOR_VOLT_V_1_0V 0x0 +#define TIMPANI_CDAC_CTL1_CDAC_REF_RESISTOR_VOLT_V_1_025V 0x1 +#define TIMPANI_CDAC_CTL1_CDAC_REF_RESISTOR_VOLT_V_1_05V_NORMAL_OP 0x2 +#define TIMPANI_CDAC_CTL1_CDAC_REF_RESISTOR_VOLT_V_1_0752V 0x3 + +#define TIMPANI_CDAC_CTL1_CDAC_SAMP_CAP_RESET_EN_S 1 +#define TIMPANI_CDAC_CTL1_CDAC_SAMP_CAP_RESET_EN_M 0x2 +#define TIMPANI_CDAC_CTL1_CDAC_SAMP_CAP_RESET_EN_DISABLE 0x0 +#define TIMPANI_CDAC_CTL1_CDAC_SAMP_CAP_RESET_EN_ENABLE_NORMAL_OP 0x1 + +#define TIMPANI_CDAC_CTL1_CDAC_RESET_SOURCE_S 0 +#define TIMPANI_CDAC_CTL1_CDAC_RESET_SOURCE_M 0x1 +#define TIMPANI_CDAC_CTL1_CDAC_RESET_SOURCE_INTERNAL_NORMAL_OP 0x1 +#define TIMPANI_CDAC_CTL1_CDAC_RESET_SOURCE_EXTERNAL_REGISTER_RESET 0x0 + + +/* -- For CDAC_CTL2 */ +#define TIMPANI_A_CDAC_CTL2 (0x26) +#define TIMPANI_CDAC_CTL2_RWC "RW" +#define TIMPANI_CDAC_CTL2_POR 0xd0 +#define TIMPANI_CDAC_CTL2_S 0 +#define TIMPANI_CDAC_CTL2_M 0xFF + + +#define TIMPANI_CDAC_CTL2_CDAC_OTA_BIAS_S 5 +#define TIMPANI_CDAC_CTL2_CDAC_OTA_BIAS_M 0xE0 +#define TIMPANI_CDAC_CTL2_CDAC_OTA_BIAS_V_10UA 0x0 +#define TIMPANI_CDAC_CTL2_CDAC_OTA_BIAS_V_8_75UA 0x1 +#define TIMPANI_CDAC_CTL2_CDAC_OTA_BIAS_V_7_5UA 0x2 +#define TIMPANI_CDAC_CTL2_CDAC_OTA_BIAS_V_6_25UA 0x3 +#define TIMPANI_CDAC_CTL2_CDAC_OTA_BIAS_V_5UA 0x4 +#define TIMPANI_CDAC_CTL2_CDAC_OTA_BIAS_V_3_75UA 0x5 +#define TIMPANI_CDAC_CTL2_CDAC_OTA_BIAS_V_2_5UA_NORMAL_OP 0x6 +#define TIMPANI_CDAC_CTL2_CDAC_OTA_BIAS_V_1_25UA 0x7 + +#define TIMPANI_CDAC_CTL2_CDAC_REF_BUFF_OTA_BIAS_S 2 +#define TIMPANI_CDAC_CTL2_CDAC_REF_BUFF_OTA_BIAS_M 0x1C +#define TIMPANI_CDAC_CTL2_CDAC_REF_BUFF_OTA_BIAS_V_10UA 0x0 +#define TIMPANI_CDAC_CTL2_CDAC_REF_BUFF_OTA_BIAS_V_8_75UA 0x1 +#define TIMPANI_CDAC_CTL2_CDAC_REF_BUFF_OTA_BIAS_V_7_5UA 0x2 +#define TIMPANI_CDAC_CTL2_CDAC_REF_BUFF_OTA_BIAS_V_6_25UA 0x3 +#define TIMPANI_CDAC_CTL2_CDAC_REF_BUFF_OTA_BIAS_V_5UA_NORMAL_OP 0x4 +#define TIMPANI_CDAC_CTL2_CDAC_REF_BUFF_OTA_BIAS_V_3_75UA 0x5 +#define TIMPANI_CDAC_CTL2_CDAC_REF_BUFF_OTA_BIAS_V_2_5UA 0x6 +#define TIMPANI_CDAC_CTL2_CDAC_REF_BUFF_OTA_BIAS_V_1_25UA 0x7 + +#define TIMPANI_CDAC_CTL2_CDAC_RESET_PULSE_GEN_UPDATE_RATE_S 0 +#define TIMPANI_CDAC_CTL2_CDAC_RESET_PULSE_GEN_UPDATE_RATE_M 0x3 +#define TIMPANI_CDAC_CTL2_CDAC_RESET_PULSE_GEN_UPDATE_RATE_FS 0x0 +#define TIMPANI_CDAC_CTL2_CDAC_RESET_PULSE_GEN_UPDATE_RATE_FS_BY_8 0x1 +#define TIMPANI_CDAC_CTL2_CDAC_RESET_PULSE_GEN_UPDATE_RATE_FS_BY_16 0x2 + + +/* -- For IDAC_L_CTL */ +#define TIMPANI_A_IDAC_L_CTL (0x28) +#define TIMPANI_IDAC_L_CTL_RWC "RW" +#define TIMPANI_IDAC_L_CTL_POR 0xe +#define TIMPANI_IDAC_L_CTL_S 0 +#define TIMPANI_IDAC_L_CTL_M 0xFF + + +#define TIMPANI_IDAC_L_CTL_IDAC_L_EN_S 7 +#define TIMPANI_IDAC_L_CTL_IDAC_L_EN_M 0x80 +#define TIMPANI_IDAC_L_CTL_IDAC_L_EN_DISABLE 0x0 +#define TIMPANI_IDAC_L_CTL_IDAC_L_EN_ENABLE 0x1 + +#define TIMPANI_IDAC_L_CTL_IDAC_L_REF_SEL_S 5 +#define TIMPANI_IDAC_L_CTL_IDAC_L_REF_SEL_M 0x60 +#define TIMPANI_IDAC_L_CTL_IDAC_L_REF_SEL_GROUND 0x0 +#define TIMPANI_IDAC_L_CTL_IDAC_L_REF_SEL_IBIAS_X_R_REF 0x1 +#define TIMPANI_IDAC_L_CTL_IDAC_L_REF_SEL_BG_VOLTAGE_NORMAL_OP 0x2 +#define TIMPANI_IDAC_L_CTL_IDAC_L_REF_SEL_VDD_BY_2 0x3 + +#define TIMPANI_IDAC_L_CTL_IDAC_L_GAIN_S 3 +#define TIMPANI_IDAC_L_CTL_IDAC_L_GAIN_M 0x18 +#define TIMPANI_IDAC_L_CTL_IDAC_L_GAIN_NEG_1_5DB 0x0 +#define TIMPANI_IDAC_L_CTL_IDAC_L_GAIN_V_0_0DB_NORMAL_OP 0x1 +#define TIMPANI_IDAC_L_CTL_IDAC_L_GAIN_POS_1_5DB 0x2 +#define TIMPANI_IDAC_L_CTL_IDAC_L_GAIN_POS_3_0DB 0x3 + +#define TIMPANI_IDAC_L_CTL_IDAC_L_LOW_RESISTANCE_S 2 +#define TIMPANI_IDAC_L_CTL_IDAC_L_LOW_RESISTANCE_M 0x4 +#define TIMPANI_IDAC_L_CTL_IDAC_L_LOW_RESISTANCE_V_30K 0x0 +#define TIMPANI_IDAC_L_CTL_IDAC_L_LOW_RESISTANCE_V_10K_NORMAL_OP 0x1 + +#define TIMPANI_IDAC_L_CTL_IDAC_L_SYNC_EN_S 1 +#define TIMPANI_IDAC_L_CTL_IDAC_L_SYNC_EN_M 0x2 +#define TIMPANI_IDAC_L_CTL_IDAC_L_SYNC_EN_ASYNCHRONOUSLY 0x0 +#define TIMPANI_IDAC_L_CTL_IDAC_L_SYNC_EN_ENABLE_NORMAL_OP 0x1 + +#define TIMPANI_IDAC_L_CTL_IDAC_L_REPLICA_BIAS_S 0 +#define TIMPANI_IDAC_L_CTL_IDAC_L_REPLICA_BIAS_M 0x1 +#define TIMPANI_IDAC_L_CTL_IDAC_L_REPLICA_BIAS_REPLICA_BIAS_NORMAL_OP 0x0 +#define TIMPANI_IDAC_L_CTL_IDAC_L_REPLICA_BIAS_SERVO_LOOP_BIAS 0x1 + + +/* -- For IDAC_R_CTL */ +#define TIMPANI_A_IDAC_R_CTL (0x29) +#define TIMPANI_IDAC_R_CTL_RWC "RW" +#define TIMPANI_IDAC_R_CTL_POR 0xe +#define TIMPANI_IDAC_R_CTL_S 0 +#define TIMPANI_IDAC_R_CTL_M 0xFF + + +#define TIMPANI_IDAC_R_CTL_IDAC_R_EN_S 7 +#define TIMPANI_IDAC_R_CTL_IDAC_R_EN_M 0x80 +#define TIMPANI_IDAC_R_CTL_IDAC_R_EN_DISABLED 0x0 +#define TIMPANI_IDAC_R_CTL_IDAC_R_EN_ENABLED 0x1 + +#define TIMPANI_IDAC_R_CTL_IDAC_R_REF_SEL_S 5 +#define TIMPANI_IDAC_R_CTL_IDAC_R_REF_SEL_M 0x60 +#define TIMPANI_IDAC_R_CTL_IDAC_R_REF_SEL_GROUND 0x0 +#define TIMPANI_IDAC_R_CTL_IDAC_R_REF_SEL_IBIAS_X_R_REF 0x1 +#define TIMPANI_IDAC_R_CTL_IDAC_R_REF_SEL_BG_VOLTAGE_NORMAL_OP 0x2 +#define TIMPANI_IDAC_R_CTL_IDAC_R_REF_SEL_VDD_BY_2 0x3 + +#define TIMPANI_IDAC_R_CTL_IDAC_R_GAIN_S 3 +#define TIMPANI_IDAC_R_CTL_IDAC_R_GAIN_M 0x18 +#define TIMPANI_IDAC_R_CTL_IDAC_R_GAIN_NEG_1_5DB 0x0 +#define TIMPANI_IDAC_R_CTL_IDAC_R_GAIN_V_0_0DB_NORMAL_OP 0x1 +#define TIMPANI_IDAC_R_CTL_IDAC_R_GAIN_POS_1_5DB 0x2 +#define TIMPANI_IDAC_R_CTL_IDAC_R_GAIN_POS_3_0DB 0x3 + +#define TIMPANI_IDAC_R_CTL_IDAC_R_LOW_RESISTANCE_S 2 +#define TIMPANI_IDAC_R_CTL_IDAC_R_LOW_RESISTANCE_M 0x4 +#define TIMPANI_IDAC_R_CTL_IDAC_R_LOW_RESISTANCE_V_30K 0x0 +#define TIMPANI_IDAC_R_CTL_IDAC_R_LOW_RESISTANCE_V_10K_NORMAL_OP 0x1 + +#define TIMPANI_IDAC_R_CTL_IDAC_R_SYNC_EN_S 1 +#define TIMPANI_IDAC_R_CTL_IDAC_R_SYNC_EN_M 0x2 +#define TIMPANI_IDAC_R_CTL_IDAC_R_SYNC_EN_ASYNCHRONOUSLY 0x0 +#define TIMPANI_IDAC_R_CTL_IDAC_R_SYNC_EN_ENABLE_NORMAL_OP 0x1 + +#define TIMPANI_IDAC_R_CTL_IDAC_R_REPLICA_BIAS_S 0 +#define TIMPANI_IDAC_R_CTL_IDAC_R_REPLICA_BIAS_M 0x1 +#define TIMPANI_IDAC_R_CTL_IDAC_R_REPLICA_BIAS_REPLICA_BIAS_NORMAL_OP 0x0 +#define TIMPANI_IDAC_R_CTL_IDAC_R_REPLICA_BIAS_SERVO_LOOP_BIAS 0x1 + + +/* -- For PA_MASTER_BIAS */ +#define TIMPANI_A_PA_MASTER_BIAS (0x2D) +#define TIMPANI_PA_MASTER_BIAS_RWC "RW" +#define TIMPANI_PA_MASTER_BIAS_POR 0x6f +#define TIMPANI_PA_MASTER_BIAS_S 0 +#define TIMPANI_PA_MASTER_BIAS_M 0xFF + + +#define TIMPANI_PA_MASTER_BIAS_LINE_MASTER_BIAS_CUR_S 5 +#define TIMPANI_PA_MASTER_BIAS_LINE_MASTER_BIAS_CUR_M 0xE0 +#define TIMPANI_PA_MASTER_BIAS_LINE_MASTER_BIAS_CUR_V_17_5UA 0x0 +#define TIMPANI_PA_MASTER_BIAS_LINE_MASTER_BIAS_CUR_V_15_0UA 0x1 +#define TIMPANI_PA_MASTER_BIAS_LINE_MASTER_BIAS_CUR_V_12_5UA 0x2 +#define TIMPANI_PA_MASTER_BIAS_LINE_MASTER_BIAS_CUR_V_10_0UA 0x3 +#define TIMPANI_PA_MASTER_BIAS_LINE_MASTER_BIAS_CUR_V_7_5UA 0x4 +#define TIMPANI_PA_MASTER_BIAS_LINE_MASTER_BIAS_CUR_V_5_0UA 0x5 +#define TIMPANI_PA_MASTER_BIAS_LINE_MASTER_BIAS_CUR_V_2_5UA 0x6 +#define TIMPANI_PA_MASTER_BIAS_LINE_MASTER_BIAS_CUR_V_0_0UA 0x7 + +#define TIMPANI_PA_MASTER_BIAS_HPH_MASTER_BIAS_CUR_S 2 +#define TIMPANI_PA_MASTER_BIAS_HPH_MASTER_BIAS_CUR_M 0x1C +#define TIMPANI_PA_MASTER_BIAS_HPH_MASTER_BIAS_CUR_V_17_5UA 0x0 +#define TIMPANI_PA_MASTER_BIAS_HPH_MASTER_BIAS_CUR_V_15_0UA 0x1 +#define TIMPANI_PA_MASTER_BIAS_HPH_MASTER_BIAS_CUR_V_12_5UA 0x2 +#define TIMPANI_PA_MASTER_BIAS_HPH_MASTER_BIAS_CUR_V_10_0UA 0x3 +#define TIMPANI_PA_MASTER_BIAS_HPH_MASTER_BIAS_CUR_V_7_5UA 0x4 +#define TIMPANI_PA_MASTER_BIAS_HPH_MASTER_BIAS_CUR_V_5_0UA 0x5 +#define TIMPANI_PA_MASTER_BIAS_HPH_MASTER_BIAS_CUR_V_2_5UA 0x6 +#define TIMPANI_PA_MASTER_BIAS_HPH_MASTER_BIAS_CUR_V_0_0UA 0x7 + +#define TIMPANI_PA_MASTER_BIAS_CLASSD_REF_BUF_MASTER_BIAS_CUR_S 0 +#define TIMPANI_PA_MASTER_BIAS_CLASSD_REF_BUF_MASTER_BIAS_CUR_M 0x3 +#define TIMPANI_PA_MASTER_BIAS_CLASSD_REF_BUF_MASTER_BIAS_CUR_V_6_25UA 0x0 +#define TIMPANI_PA_MASTER_BIAS_CLASSD_REF_BUF_MASTER_BIAS_CUR_V_5_0UA 0x1 +#define TIMPANI_PA_MASTER_BIAS_CLASSD_REF_BUF_MASTER_BIAS_CUR_V_3_75UA 0x2 +#define TIMPANI_PA_MASTER_BIAS_CLASSD_REF_BUF_MASTER_BIAS_CUR_V_2_5UA 0x3 + + +/* -- For PA_CLASSD_BIAS */ +#define TIMPANI_A_PA_CLASSD_BIAS (0x2E) +#define TIMPANI_PA_CLASSD_BIAS_RWC "RW" +#define TIMPANI_PA_CLASSD_BIAS_POR 0x55 +#define TIMPANI_PA_CLASSD_BIAS_S 0 +#define TIMPANI_PA_CLASSD_BIAS_M 0xFF + + +#define TIMPANI_PA_CLASSD_BIAS_CLASSD_COMP_BIAS_CUR_S 6 +#define TIMPANI_PA_CLASSD_BIAS_CLASSD_COMP_BIAS_CUR_M 0xC0 +#define TIMPANI_PA_CLASSD_BIAS_CLASSD_COMP_BIAS_CUR_V_6_25UA 0x0 +#define TIMPANI_PA_CLASSD_BIAS_CLASSD_COMP_BIAS_CUR_V_5_0UA 0x1 +#define TIMPANI_PA_CLASSD_BIAS_CLASSD_COMP_BIAS_CUR_V_3_75UA 0x2 +#define TIMPANI_PA_CLASSD_BIAS_CLASSD_COMP_BIAS_CUR_V_2_5UA 0x3 + +#define TIMPANI_PA_CLASSD_BIAS_CLASSD_OTA1_BIAS_CUR_S 4 +#define TIMPANI_PA_CLASSD_BIAS_CLASSD_OTA1_BIAS_CUR_M 0x30 +#define TIMPANI_PA_CLASSD_BIAS_CLASSD_OTA1_BIAS_CUR_V_6_25UA 0x0 +#define TIMPANI_PA_CLASSD_BIAS_CLASSD_OTA1_BIAS_CUR_V_5_0U 0x1 +#define TIMPANI_PA_CLASSD_BIAS_CLASSD_OTA1_BIAS_CUR_V_3_75UA 0x2 +#define TIMPANI_PA_CLASSD_BIAS_CLASSD_OTA1_BIAS_CUR_V_2_5UA 0x3 + +#define TIMPANI_PA_CLASSD_BIAS_CLASSD_OTA2_BIAS_CUR_S 2 +#define TIMPANI_PA_CLASSD_BIAS_CLASSD_OTA2_BIAS_CUR_M 0xC +#define TIMPANI_PA_CLASSD_BIAS_CLASSD_OTA2_BIAS_CUR_V_6_25UA 0x0 +#define TIMPANI_PA_CLASSD_BIAS_CLASSD_OTA2_BIAS_CUR_V_5_0UA 0x1 +#define TIMPANI_PA_CLASSD_BIAS_CLASSD_OTA2_BIAS_CUR_V_3_75UA 0x2 +#define TIMPANI_PA_CLASSD_BIAS_CLASSD_OTA2_BIAS_CUR_V_2_5UA 0x3 + +#define TIMPANI_PA_CLASSD_BIAS_CLASSD_OCP_BIAS_CUR_S 0 +#define TIMPANI_PA_CLASSD_BIAS_CLASSD_OCP_BIAS_CUR_M 0x3 +#define TIMPANI_PA_CLASSD_BIAS_CLASSD_OCP_BIAS_CUR_V_6_25UA 0x0 +#define TIMPANI_PA_CLASSD_BIAS_CLASSD_OCP_BIAS_CUR_V_5_0UA 0x1 +#define TIMPANI_PA_CLASSD_BIAS_CLASSD_OCP_BIAS_CUR_V_3_75UA 0x2 +#define TIMPANI_PA_CLASSD_BIAS_CLASSD_OCP_BIAS_CUR_V_2_5UA 0x3 + + +/* -- For AUXPGA_CUR */ +#define TIMPANI_A_AUXPGA_CUR (0x2F) +#define TIMPANI_AUXPGA_CUR_RWC "RW" +#define TIMPANI_AUXPGA_CUR_POR 0x44 +#define TIMPANI_AUXPGA_CUR_S 0 +#define TIMPANI_AUXPGA_CUR_M 0xFF + + +#define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_S 4 +#define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_M 0xF0 +#define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_V_0UA 0x0 +#define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_V_0_3125UA 0x1 +#define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_V_0_625UA 0x2 +#define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_V_0_9375UA 0x3 +#define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_V_1_25UA 0x4 +#define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_V_1_5625UA 0x5 +#define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_V_1_875UA 0x6 +#define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_V_2_1875UA 0x7 +#define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_V_2_5UA 0x8 +#define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_V_2_8125UA 0x9 +#define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_V_3_125UA 0xA +#define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_V_3_4375UA 0xB +#define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_V_3_75UA 0xC +#define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_V_4_0625UA 0xD +#define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_V_4_375UA 0xE +#define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_V_4_6875UA 0xF + +#define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_S 0 +#define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_M 0xF +#define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_V_0UA 0x0 +#define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_V_0_3125UA 0x1 +#define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_V_0_625UA 0x2 +#define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_V_0_9375UA 0x3 +#define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_V_1_25UA 0x4 +#define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_V_1_5625UA 0x5 +#define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_V_1_875UA 0x6 +#define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_V_2_1875UA 0x7 +#define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_V_2_5UA 0x8 +#define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_V_2_8125UA 0x9 +#define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_V_3_125UA 0xA +#define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_V_3_4375UA 0xB +#define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_V_3_75UA 0xC +#define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_V_4_0625UA 0xD +#define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_V_4_375UA 0xE +#define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_V_4_6875UA 0xF + + +/* -- For AUXPGA_CM */ +#define TIMPANI_A_AUXPGA_CM (0x30) +#define TIMPANI_AUXPGA_CM_RWC "RW" +#define TIMPANI_AUXPGA_CM_POR 0x92 +#define TIMPANI_AUXPGA_CM_S 0 +#define TIMPANI_AUXPGA_CM_M 0xFF + + +#define TIMPANI_AUXPGA_CM_AUXPGA_R_CM_DIFF_PAIR_TAIL_CUR_S 5 +#define TIMPANI_AUXPGA_CM_AUXPGA_R_CM_DIFF_PAIR_TAIL_CUR_M 0xE0 +#define TIMPANI_AUXPGA_CM_AUXPGA_R_CM_DIFF_PAIR_TAIL_CUR_V_7_5UA 0x0 +#define TIMPANI_AUXPGA_CM_AUXPGA_R_CM_DIFF_PAIR_TAIL_CUR_V_7_925UA 0x1 +#define TIMPANI_AUXPGA_CM_AUXPGA_R_CM_DIFF_PAIR_TAIL_CUR_V_8_75UA 0x2 +#define TIMPANI_AUXPGA_CM_AUXPGA_R_CM_DIFF_PAIR_TAIL_CUR_V_9_375UA 0x3 +#define TIMPANI_AUXPGA_CM_AUXPGA_R_CM_DIFF_PAIR_TAIL_CUR_V_10UA 0x4 +#define TIMPANI_AUXPGA_CM_AUXPGA_R_CM_DIFF_PAIR_TAIL_CUR_V_10_625UA 0x5 +#define TIMPANI_AUXPGA_CM_AUXPGA_R_CM_DIFF_PAIR_TAIL_CUR_V_11_25UA 0x6 +#define TIMPANI_AUXPGA_CM_AUXPGA_R_CM_DIFF_PAIR_TAIL_CUR_V_11_875UA 0x7 + +#define TIMPANI_AUXPGA_CM_AUXPGA_L_CM_DIFF_PAIR_TAIL_CUR_S 2 +#define TIMPANI_AUXPGA_CM_AUXPGA_L_CM_DIFF_PAIR_TAIL_CUR_M 0x1C +#define TIMPANI_AUXPGA_CM_AUXPGA_L_CM_DIFF_PAIR_TAIL_CUR_V_7_5UA 0x0 +#define TIMPANI_AUXPGA_CM_AUXPGA_L_CM_DIFF_PAIR_TAIL_CUR_V_7_925UA 0x1 +#define TIMPANI_AUXPGA_CM_AUXPGA_L_CM_DIFF_PAIR_TAIL_CUR_V_8_75UA 0x2 +#define TIMPANI_AUXPGA_CM_AUXPGA_L_CM_DIFF_PAIR_TAIL_CUR_V_9_375UA 0x3 +#define TIMPANI_AUXPGA_CM_AUXPGA_L_CM_DIFF_PAIR_TAIL_CUR_V_10UA 0x4 +#define TIMPANI_AUXPGA_CM_AUXPGA_L_CM_DIFF_PAIR_TAIL_CUR_V_10_625UA 0x5 +#define TIMPANI_AUXPGA_CM_AUXPGA_L_CM_DIFF_PAIR_TAIL_CUR_V_11_25UA 0x6 +#define TIMPANI_AUXPGA_CM_AUXPGA_L_CM_DIFF_PAIR_TAIL_CUR_V_11_875UA 0x7 + +#define TIMPANI_AUXPGA_CM_AUXPGA_R2R_CM_S 1 +#define TIMPANI_AUXPGA_CM_AUXPGA_R2R_CM_M 0x2 +#define TIMPANI_AUXPGA_CM_AUXPGA_R2R_CM_VCMI_TO_R2R_CM 0x1 +#define TIMPANI_AUXPGA_CM_AUXPGA_R2R_CM_R2R_CM_FLOATING 0x0 + +#define TIMPANI_AUXPGA_CM_AUXPGA_VCM_REF_GEN_S 0 +#define TIMPANI_AUXPGA_CM_AUXPGA_VCM_REF_GEN_M 0x1 +#define TIMPANI_AUXPGA_CM_AUXPGA_VCM_REF_GEN_GEN_VCM_LOCALLY 0x1 +#define TIMPANI_AUXPGA_CM_AUXPGA_VCM_REF_GEN_BG_VCM 0x0 + + +/* -- For PA_HPH_EARPA_MSTB_EN */ +#define TIMPANI_A_PA_HPH_EARPA_MSTB_EN (0x31) +#define TIMPANI_PA_HPH_EARPA_MSTB_EN_RWC "RW" +#define TIMPANI_PA_HPH_EARPA_MSTB_EN_POR 0x4 +#define TIMPANI_PA_HPH_EARPA_MSTB_EN_S 0 +#define TIMPANI_PA_HPH_EARPA_MSTB_EN_M 0xFF + + +#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_L_EN_S 7 +#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_L_EN_M 0x80 +#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_L_EN_ENABLE 0x1 +#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_L_EN_DISABLE 0x0 + +#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_L_BIAS_EN_S 6 +#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_L_BIAS_EN_M 0x40 +#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_L_BIAS_EN_ENABLE 0x1 +#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_L_BIAS_EN_DISABLE 0x0 + +#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_R_EN_S 5 +#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_R_EN_M 0x20 +#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_R_EN_ENABLE 0x1 +#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_R_EN_DISABLE 0x0 + +#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_R_BIAS_EN_S 4 +#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_R_BIAS_EN_M 0x10 +#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_R_BIAS_EN_ENABLE 0x1 +#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_R_BIAS_EN_DISABLE 0x0 + +#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_VCM_BUFFER_EN_S 3 +#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_VCM_BUFFER_EN_M 0x8 +#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_VCM_BUFFER_EN_ENABLE 0x1 +#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_VCM_BUFFER_EN_DISABLE 0x0 + +#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_CAPLESS_MODE_S 2 +#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_CAPLESS_MODE_M 0x4 +#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_CAPLESS_MODE_CAPLESS 0x1 +#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_CAPLESS_MODE_LEGACY 0x0 + +#define TIMPANI_PA_HPH_EARPA_MSTB_EN_EARPA_EN_S 1 +#define TIMPANI_PA_HPH_EARPA_MSTB_EN_EARPA_EN_M 0x2 +#define TIMPANI_PA_HPH_EARPA_MSTB_EN_EARPA_EN_ENABLE 0x1 +#define TIMPANI_PA_HPH_EARPA_MSTB_EN_EARPA_EN_DISABLE 0x0 + +#define TIMPANI_PA_HPH_EARPA_MSTB_EN_PA_MASTER_BIAS_EN_S 0 +#define TIMPANI_PA_HPH_EARPA_MSTB_EN_PA_MASTER_BIAS_EN_M 0x1 +#define TIMPANI_PA_HPH_EARPA_MSTB_EN_PA_MASTER_BIAS_EN_ENABLE 0x1 +#define TIMPANI_PA_HPH_EARPA_MSTB_EN_PA_MASTER_BIAS_EN_DISABLE 0x0 + + +/* -- For PA_LINE_AUXO_EN */ +#define TIMPANI_A_PA_LINE_AUXO_EN (0x32) +#define TIMPANI_PA_LINE_AUXO_EN_RWC "RW" +#define TIMPANI_PA_LINE_AUXO_EN_POR 0 +#define TIMPANI_PA_LINE_AUXO_EN_S 0 +#define TIMPANI_PA_LINE_AUXO_EN_M 0xFF + + +#define TIMPANI_PA_LINE_AUXO_EN_LINE_L_EN_S 7 +#define TIMPANI_PA_LINE_AUXO_EN_LINE_L_EN_M 0x80 +#define TIMPANI_PA_LINE_AUXO_EN_LINE_L_EN_ENABLE 0x1 +#define TIMPANI_PA_LINE_AUXO_EN_LINE_L_EN_DISABLE 0x0 + +#define TIMPANI_PA_LINE_AUXO_EN_LINE_L_BIAS_EN_S 6 +#define TIMPANI_PA_LINE_AUXO_EN_LINE_L_BIAS_EN_M 0x40 +#define TIMPANI_PA_LINE_AUXO_EN_LINE_L_BIAS_EN_ENABLE 0x1 +#define TIMPANI_PA_LINE_AUXO_EN_LINE_L_BIAS_EN_DISABLE 0x0 + +#define TIMPANI_PA_LINE_AUXO_EN_LINE_R_EN_S 5 +#define TIMPANI_PA_LINE_AUXO_EN_LINE_R_EN_M 0x20 +#define TIMPANI_PA_LINE_AUXO_EN_LINE_R_EN_ENABLE 0x1 +#define TIMPANI_PA_LINE_AUXO_EN_LINE_R_EN_DISABLE 0x0 + +#define TIMPANI_PA_LINE_AUXO_EN_LINE_R_BIAS_EN_S 4 +#define TIMPANI_PA_LINE_AUXO_EN_LINE_R_BIAS_EN_M 0x10 +#define TIMPANI_PA_LINE_AUXO_EN_LINE_R_BIAS_EN_ENABLE 0x1 +#define TIMPANI_PA_LINE_AUXO_EN_LINE_R_BIAS_EN_DISABLE 0x0 + +#define TIMPANI_PA_LINE_AUXO_EN_LINE_VCM_BUFFER_EN_S 3 +#define TIMPANI_PA_LINE_AUXO_EN_LINE_VCM_BUFFER_EN_M 0x8 +#define TIMPANI_PA_LINE_AUXO_EN_LINE_VCM_BUFFER_EN_ENABLE 0x1 +#define TIMPANI_PA_LINE_AUXO_EN_LINE_VCM_BUFFER_EN_DISABLE 0x0 + +#define TIMPANI_PA_LINE_AUXO_EN_AUXOUT_EN_S 2 +#define TIMPANI_PA_LINE_AUXO_EN_AUXOUT_EN_M 0x4 +#define TIMPANI_PA_LINE_AUXO_EN_AUXOUT_EN_ENABLE 0x1 +#define TIMPANI_PA_LINE_AUXO_EN_AUXOUT_EN_DISABLE 0x0 + +#define TIMPANI_PA_LINE_AUXO_EN_AUXOUT_BIAS_EN_S 1 +#define TIMPANI_PA_LINE_AUXO_EN_AUXOUT_BIAS_EN_M 0x2 +#define TIMPANI_PA_LINE_AUXO_EN_AUXOUT_BIAS_EN_ENABLE 0x1 +#define TIMPANI_PA_LINE_AUXO_EN_AUXOUT_BIAS_EN_DISABLE 0x0 + +#define TIMPANI_PA_LINE_AUXO_EN_AUXOUT_VCM_BUFFER_EN_S 0 +#define TIMPANI_PA_LINE_AUXO_EN_AUXOUT_VCM_BUFFER_EN_M 0x1 +#define TIMPANI_PA_LINE_AUXO_EN_AUXOUT_VCM_BUFFER_EN_ENABLE 0x1 +#define TIMPANI_PA_LINE_AUXO_EN_AUXOUT_VCM_BUFFER_EN_DISABLE 0x0 + + +/* -- For PA_CLASSD_AUXPGA_EN */ +#define TIMPANI_A_PA_CLASSD_AUXPGA_EN (0x33) +#define TIMPANI_PA_CLASSD_AUXPGA_EN_RWC "RW" +#define TIMPANI_PA_CLASSD_AUXPGA_EN_POR 0 +#define TIMPANI_PA_CLASSD_AUXPGA_EN_S 0 +#define TIMPANI_PA_CLASSD_AUXPGA_EN_M 0xFF + + +#define TIMPANI_PA_CLASSD_AUXPGA_EN_AUXPGA_L_MUTE_S 7 +#define TIMPANI_PA_CLASSD_AUXPGA_EN_AUXPGA_L_MUTE_M 0x80 +#define TIMPANI_PA_CLASSD_AUXPGA_EN_AUXPGA_L_MUTE_MUTE 0x1 +#define TIMPANI_PA_CLASSD_AUXPGA_EN_AUXPGA_L_MUTE_UNMUTE 0x0 + +#define TIMPANI_PA_CLASSD_AUXPGA_EN_AUXPGA_R_MUTE_S 6 +#define TIMPANI_PA_CLASSD_AUXPGA_EN_AUXPGA_R_MUTE_M 0x40 +#define TIMPANI_PA_CLASSD_AUXPGA_EN_AUXPGA_R_MUTE_MUTE 0x1 +#define TIMPANI_PA_CLASSD_AUXPGA_EN_AUXPGA_R_MUTE_UNMUTE 0x0 + +#define TIMPANI_PA_CLASSD_AUXPGA_EN_AUXPGA_L_EN_S 5 +#define TIMPANI_PA_CLASSD_AUXPGA_EN_AUXPGA_L_EN_M 0x20 +#define TIMPANI_PA_CLASSD_AUXPGA_EN_AUXPGA_L_EN_DISABLE 0x0 +#define TIMPANI_PA_CLASSD_AUXPGA_EN_AUXPGA_L_EN_ENABLE 0x1 + +#define TIMPANI_PA_CLASSD_AUXPGA_EN_AUXPGA_R_EN_S 4 +#define TIMPANI_PA_CLASSD_AUXPGA_EN_AUXPGA_R_EN_M 0x10 +#define TIMPANI_PA_CLASSD_AUXPGA_EN_AUXPGA_R_EN_DISABLE 0x0 +#define TIMPANI_PA_CLASSD_AUXPGA_EN_AUXPGA_R_EN_ENABLE 0x1 + +#define TIMPANI_PA_CLASSD_AUXPGA_EN_CLASSD_L_REF_EN_S 3 +#define TIMPANI_PA_CLASSD_AUXPGA_EN_CLASSD_L_REF_EN_M 0x8 +#define TIMPANI_PA_CLASSD_AUXPGA_EN_CLASSD_L_REF_EN_DISABLE 0x0 +#define TIMPANI_PA_CLASSD_AUXPGA_EN_CLASSD_L_REF_EN_ENABLE 0x1 + +#define TIMPANI_PA_CLASSD_AUXPGA_EN_CLASSD_L_EN_S 2 +#define TIMPANI_PA_CLASSD_AUXPGA_EN_CLASSD_L_EN_M 0x4 +#define TIMPANI_PA_CLASSD_AUXPGA_EN_CLASSD_L_EN_DISABLE 0x0 +#define TIMPANI_PA_CLASSD_AUXPGA_EN_CLASSD_L_EN_ENABLE 0x1 + +#define TIMPANI_PA_CLASSD_AUXPGA_EN_CLASSD_R_REF_EN_S 1 +#define TIMPANI_PA_CLASSD_AUXPGA_EN_CLASSD_R_REF_EN_M 0x2 +#define TIMPANI_PA_CLASSD_AUXPGA_EN_CLASSD_R_REF_EN_DISABLE 0x0 +#define TIMPANI_PA_CLASSD_AUXPGA_EN_CLASSD_R_REF_EN_ENABLE 0x1 + +#define TIMPANI_PA_CLASSD_AUXPGA_EN_CLASSD_R_EN_S 0 +#define TIMPANI_PA_CLASSD_AUXPGA_EN_CLASSD_R_EN_M 0x1 +#define TIMPANI_PA_CLASSD_AUXPGA_EN_CLASSD_R_EN_DISABLE 0x0 +#define TIMPANI_PA_CLASSD_AUXPGA_EN_CLASSD_R_EN_ENABLE 0x1 + + +/* -- For PA_LINE_L_GAIN */ +#define TIMPANI_A_PA_LINE_L_GAIN (0x34) +#define TIMPANI_PA_LINE_L_GAIN_RWC "RW" +#define TIMPANI_PA_LINE_L_GAIN_POR 0xac +#define TIMPANI_PA_LINE_L_GAIN_S 0 +#define TIMPANI_PA_LINE_L_GAIN_M 0xFF + + +#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_S 2 +#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_M 0xFC +#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_POS_1_5 0x0 +#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_POS_0_0 0x1 +#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_1_5 0x2 +#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_3_0 0x3 +#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_4_5 0x4 +#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_6_0 0x5 +#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_7_5 0x6 +#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_9_0 0x7 +#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_10_5 0x8 +#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_12_0 0x9 +#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_13_5 0xA +#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_15_0 0xB +#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_16_5 0xC +#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_18_0 0xD +#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_19_5 0xE +#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_21_0 0xF +#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_22_5 0x10 +#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_24_0 0x11 +#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_25_5 0x12 +#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_27_0 0x13 +#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_28_5 0x14 +#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_30_0 0x15 +#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_31_5 0x16 +#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_33_0 0x17 +#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_34_5 0x18 +#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_36_0 0x19 +#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_37_5 0x1A +#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_39_0 0x1B +#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_40_5 0x1C +#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_42_0 0x1D +#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_43_5 0x1E +#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_45_0 0x1F +#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_46_5 0x20 +#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_48_0 0x21 +#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_49_5 0x22 +#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_51_0 0x23 +#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_52_5 0x24 +#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_54_0 0x25 +#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_55_5 0x26 +#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_57_0 0x27 +#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_58_5 0x28 +#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_60_0 0x29 +#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_61_5 0x2A +#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_63_0 0x2B + +#define TIMPANI_PA_LINE_L_GAIN_RESERVED_S 0 +#define TIMPANI_PA_LINE_L_GAIN_RESERVED_M 0x3 + + +/* -- For PA_LINE_R_GAIN */ +#define TIMPANI_A_PA_LINE_R_GAIN (0x35) +#define TIMPANI_PA_LINE_R_GAIN_RWC "RW" +#define TIMPANI_PA_LINE_R_GAIN_POR 0xac +#define TIMPANI_PA_LINE_R_GAIN_S 0 +#define TIMPANI_PA_LINE_R_GAIN_M 0xFF + + +#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_S 2 +#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_M 0xFC +#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_POS_1_5 0x0 +#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_POS_0_0 0x1 +#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_1_5 0x2 +#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_3_0 0x3 +#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_4_5 0x4 +#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_6_0 0x5 +#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_7_5 0x6 +#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_9_0 0x7 +#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_10_5 0x8 +#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_12_0 0x9 +#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_13_5 0xA +#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_15_0 0xB +#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_16_5 0xC +#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_18_0 0xD +#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_19_5 0xE +#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_21_0 0xF +#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_22_5 0x10 +#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_24_0 0x11 +#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_25_5 0x12 +#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_27_0 0x13 +#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_28_5 0x14 +#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_30_0 0x15 +#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_31_5 0x16 +#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_33_0 0x17 +#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_34_5 0x18 +#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_36_0 0x19 +#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_37_5 0x1A +#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_39_0 0x1B +#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_40_5 0x1C +#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_42_0 0x1D +#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_43_5 0x1E +#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_45_0 0x1F +#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_46_5 0x20 +#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_48_0 0x21 +#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_49_5 0x22 +#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_51_0 0x23 +#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_52_5 0x24 +#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_54_0 0x25 +#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_55_5 0x26 +#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_57_0 0x27 +#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_58_5 0x28 +#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_60_0 0x29 +#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_61_5 0x2A +#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_63_0 0x2B + +#define TIMPANI_PA_LINE_R_GAIN_RESERVED_S 0 +#define TIMPANI_PA_LINE_R_GAIN_RESERVED_M 0x3 + + +/* -- For PA_HPH_L_GAIN */ +#define TIMPANI_A_PA_HPH_L_GAIN (0x36) +#define TIMPANI_PA_HPH_L_GAIN_RWC "RW" +#define TIMPANI_PA_HPH_L_GAIN_POR 0xae +#define TIMPANI_PA_HPH_L_GAIN_S 0 +#define TIMPANI_PA_HPH_L_GAIN_M 0xFF + + +#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_S 2 +#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_M 0xFC +#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_POS_1_5 0x0 +#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_POS_0_0 0x1 +#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_1_5 0x2 +#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_3_0 0x3 +#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_4_5 0x4 +#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_6_0 0x5 +#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_7_5 0x6 +#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_9_0 0x7 +#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_10_5 0x8 +#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_12_0 0x9 +#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_13_5 0xA +#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_15_0 0xB +#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_16_5 0xC +#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_18_0 0xD +#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_19_5 0xE +#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_21_0 0xF +#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_22_5 0x10 +#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_24_0 0x11 +#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_25_5 0x12 +#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_27_0 0x13 +#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_28_5 0x14 +#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_30_0 0x15 +#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_31_5 0x16 +#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_33_0 0x17 +#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_34_5 0x18 +#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_36_0 0x19 +#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_37_5 0x1A +#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_39_0 0x1B +#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_40_5 0x1C +#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_42_0 0x1D +#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_43_5 0x1E +#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_45_0 0x1F +#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_46_5 0x20 +#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_48_0 0x21 +#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_49_5 0x22 +#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_51_0 0x23 +#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_52_5 0x24 +#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_54_0 0x25 +#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_55_5 0x26 +#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_57_0 0x27 +#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_58_5 0x28 +#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_60_0 0x29 +#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_61_5 0x2A +#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_63_0 0x2B + +#define TIMPANI_PA_HPH_L_GAIN_HPH_L_MUTE_S 1 +#define TIMPANI_PA_HPH_L_GAIN_HPH_L_MUTE_M 0x2 +#define TIMPANI_PA_HPH_L_GAIN_HPH_L_MUTE_MUTE 0x1 +#define TIMPANI_PA_HPH_L_GAIN_HPH_L_MUTE_UNMUTE 0x0 + +#define TIMPANI_PA_HPH_L_GAIN_RESERVED_S 0 +#define TIMPANI_PA_HPH_L_GAIN_RESERVED_M 0x1 + + +/* -- For PA_HPH_R_GAIN */ +#define TIMPANI_A_PA_HPH_R_GAIN (0x37) +#define TIMPANI_PA_HPH_R_GAIN_RWC "RW" +#define TIMPANI_PA_HPH_R_GAIN_POR 0xae +#define TIMPANI_PA_HPH_R_GAIN_S 0 +#define TIMPANI_PA_HPH_R_GAIN_M 0xFF + + +#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_S 2 +#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_M 0xFC +#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_POS_1_5 0x0 +#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_POS_0_0 0x1 +#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_1_5 0x2 +#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_3_0 0x3 +#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_4_5 0x4 +#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_6_0 0x5 +#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_7_5 0x6 +#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_9_0 0x7 +#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_10_5 0x8 +#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_12_0 0x9 +#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_13_5 0xA +#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_15_0 0xB +#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_16_5 0xC +#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_18_0 0xD +#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_19_5 0xE +#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_21_0 0xF +#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_22_5 0x10 +#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_24_0 0x11 +#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_25_5 0x12 +#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_27_0 0x13 +#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_28_5 0x14 +#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_30_0 0x15 +#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_31_5 0x16 +#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_33_0 0x17 +#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_34_5 0x18 +#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_36_0 0x19 +#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_37_5 0x1A +#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_39_0 0x1B +#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_40_5 0x1C +#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_42_0 0x1D +#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_43_5 0x1E +#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_45_0 0x1F +#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_46_5 0x20 +#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_48_0 0x21 +#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_49_5 0x22 +#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_51_0 0x23 +#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_52_5 0x24 +#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_54_0 0x25 +#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_55_5 0x26 +#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_57_0 0x27 +#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_58_5 0x28 +#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_60_0 0x29 +#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_61_5 0x2A +#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_63_0 0x2B + +#define TIMPANI_PA_HPH_R_GAIN_HPH_R_MUTE_S 1 +#define TIMPANI_PA_HPH_R_GAIN_HPH_R_MUTE_M 0x2 +#define TIMPANI_PA_HPH_R_GAIN_HPH_R_MUTE_MUTE 0x1 +#define TIMPANI_PA_HPH_R_GAIN_HPH_R_MUTE_UNMUTE 0x0 + +#define TIMPANI_PA_HPH_R_GAIN_RESERVED_S 0 +#define TIMPANI_PA_HPH_R_GAIN_RESERVED_M 0x1 + + +/* -- For AUXPGA_LR_GAIN */ +#define TIMPANI_A_AUXPGA_LR_GAIN (0x38) +#define TIMPANI_AUXPGA_LR_GAIN_RWC "RW" +#define TIMPANI_AUXPGA_LR_GAIN_POR 0xaa +#define TIMPANI_AUXPGA_LR_GAIN_S 0 +#define TIMPANI_AUXPGA_LR_GAIN_M 0xFF + + +#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_S 4 +#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_M 0xF0 +#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_NEG_30DB 0x0 +#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_NEG_27DB 0x1 +#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_NEG_24DB 0x2 +#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_NEG_21DB 0x3 +#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_NEG_18DB 0x4 +#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_NEG_15DB 0x5 +#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_NEG_12DB 0x6 +#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_NEG_9_0DB 0x7 +#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_NEG_6_0DB 0x8 +#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_NEG_3_0DB 0x9 +#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_POS_0_0DB 0xA +#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_POS_3_0DB 0xB +#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_POS_6_0DB 0xC +#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_POS_9_0DB 0xD +#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_POS_12_0DB_1 0xE +#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_POS_12_0DB_2 0xF + +#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_S 0 +#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_M 0xF +#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_NEG_30DB 0x0 +#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_NEG_27DB 0x1 +#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_NEG_24DB 0x2 +#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_NEG_21DB 0x3 +#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_NEG_18DB 0x4 +#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_NEG_15DB 0x5 +#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_NEG_12DB 0x6 +#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_NEG_9_0DB 0x7 +#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_NEG_6_0DB 0x8 +#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_NEG_3_0DB 0x9 +#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_POS_0_0DB 0xA +#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_POS_3_0DB 0xB +#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_POS_6_0DB 0xC +#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_POS_9_0DB 0xD +#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_POS_12_0DB_1 0xE +#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_POS_12_0DB_2 0xF + + +/* -- For PA_AUXO_EARPA_CONN */ +#define TIMPANI_A_PA_AUXO_EARPA_CONN (0x39) +#define TIMPANI_PA_AUXO_EARPA_CONN_RWC "RW" +#define TIMPANI_PA_AUXO_EARPA_CONN_POR 0 +#define TIMPANI_PA_AUXO_EARPA_CONN_S 0 +#define TIMPANI_PA_AUXO_EARPA_CONN_M 0xFF + + +#define TIMPANI_PA_AUXO_EARPA_CONN_AUXOUT_AUXPGA_L_CONN_S 7 +#define TIMPANI_PA_AUXO_EARPA_CONN_AUXOUT_AUXPGA_L_CONN_M 0x80 +#define TIMPANI_PA_AUXO_EARPA_CONN_AUXOUT_AUXPGA_L_CONN_NO_CONNECT 0x0 +#define TIMPANI_PA_AUXO_EARPA_CONN_AUXOUT_AUXPGA_L_CONN_CONNECT 0x1 + +#define TIMPANI_PA_AUXO_EARPA_CONN_AUXOUT_IDAC_L_CONN_S 6 +#define TIMPANI_PA_AUXO_EARPA_CONN_AUXOUT_IDAC_L_CONN_M 0x40 +#define TIMPANI_PA_AUXO_EARPA_CONN_AUXOUT_IDAC_L_CONN_NO_CONNECT 0x0 +#define TIMPANI_PA_AUXO_EARPA_CONN_AUXOUT_IDAC_L_CONN_CONNECT 0x1 + +#define TIMPANI_PA_AUXO_EARPA_CONN_AUXOUT_CDAC_L_CONN_S 5 +#define TIMPANI_PA_AUXO_EARPA_CONN_AUXOUT_CDAC_L_CONN_M 0x20 +#define TIMPANI_PA_AUXO_EARPA_CONN_AUXOUT_CDAC_L_CONN_NO_CONNECT 0x0 +#define TIMPANI_PA_AUXO_EARPA_CONN_AUXOUT_CDAC_L_CONN_CONNECT 0x1 + +#define TIMPANI_PA_AUXO_EARPA_CONN_RESERVED_S 4 +#define TIMPANI_PA_AUXO_EARPA_CONN_RESERVED_M 0x10 + +#define TIMPANI_PA_AUXO_EARPA_CONN_EARPA_GAIN_S 3 +#define TIMPANI_PA_AUXO_EARPA_CONN_EARPA_GAIN_M 0x8 +#define TIMPANI_PA_AUXO_EARPA_CONN_EARPA_GAIN_V_3_52DB 0x1 +#define TIMPANI_PA_AUXO_EARPA_CONN_EARPA_GAIN_V_2_02DB 0x0 + +#define TIMPANI_PA_AUXO_EARPA_CONN_EARPA_AUXPGA_L_CONN_S 2 +#define TIMPANI_PA_AUXO_EARPA_CONN_EARPA_AUXPGA_L_CONN_M 0x4 +#define TIMPANI_PA_AUXO_EARPA_CONN_EARPA_AUXPGA_L_CONN_NO_CONNECT 0x0 +#define TIMPANI_PA_AUXO_EARPA_CONN_EARPA_AUXPGA_L_CONN_CONNECT 0x1 + +#define TIMPANI_PA_AUXO_EARPA_CONN_EARPA_IDAC_L_CONN_S 1 +#define TIMPANI_PA_AUXO_EARPA_CONN_EARPA_IDAC_L_CONN_M 0x2 +#define TIMPANI_PA_AUXO_EARPA_CONN_EARPA_IDAC_L_CONN_NO_CONNECT 0x0 +#define TIMPANI_PA_AUXO_EARPA_CONN_EARPA_IDAC_L_CONN_CONNECT 0x1 + +#define TIMPANI_PA_AUXO_EARPA_CONN_EARPA_CDAC_L_CONN_S 0 +#define TIMPANI_PA_AUXO_EARPA_CONN_EARPA_CDAC_L_CONN_M 0x1 +#define TIMPANI_PA_AUXO_EARPA_CONN_EARPA_CDAC_L_CONN_NO_CONNECT 0x0 +#define TIMPANI_PA_AUXO_EARPA_CONN_EARPA_CDAC_L_CONN_CONNECT 0x1 + + +/* -- For PA_LINE_ST_CONN */ +#define TIMPANI_A_PA_LINE_ST_CONN (0x3A) +#define TIMPANI_PA_LINE_ST_CONN_RWC "RW" +#define TIMPANI_PA_LINE_ST_CONN_POR 0 +#define TIMPANI_PA_LINE_ST_CONN_S 0 +#define TIMPANI_PA_LINE_ST_CONN_M 0xFF + + +#define TIMPANI_PA_LINE_ST_CONN_LINE_L_AUXPGA_L_CONN_S 7 +#define TIMPANI_PA_LINE_ST_CONN_LINE_L_AUXPGA_L_CONN_M 0x80 +#define TIMPANI_PA_LINE_ST_CONN_LINE_L_AUXPGA_L_CONN_NO_CONNECT 0x0 +#define TIMPANI_PA_LINE_ST_CONN_LINE_L_AUXPGA_L_CONN_CONNECT 0x1 + +#define TIMPANI_PA_LINE_ST_CONN_LINE_L_IDAC_L_CONN_S 6 +#define TIMPANI_PA_LINE_ST_CONN_LINE_L_IDAC_L_CONN_M 0x40 +#define TIMPANI_PA_LINE_ST_CONN_LINE_L_IDAC_L_CONN_NO_CONNECT 0x0 +#define TIMPANI_PA_LINE_ST_CONN_LINE_L_IDAC_L_CONN_CONNECT 0x1 + +#define TIMPANI_PA_LINE_ST_CONN_LINE_L_CDAC_L_CONN_S 5 +#define TIMPANI_PA_LINE_ST_CONN_LINE_L_CDAC_L_CONN_M 0x20 +#define TIMPANI_PA_LINE_ST_CONN_LINE_L_CDAC_L_CONN_NO_CONNECT 0x0 +#define TIMPANI_PA_LINE_ST_CONN_LINE_L_CDAC_L_CONN_CONNECT 0x1 + +#define TIMPANI_PA_LINE_ST_CONN_LINE_R_AUXPGA_R_CONN_S 4 +#define TIMPANI_PA_LINE_ST_CONN_LINE_R_AUXPGA_R_CONN_M 0x10 +#define TIMPANI_PA_LINE_ST_CONN_LINE_R_AUXPGA_R_CONN_NO_CONNECT 0x0 +#define TIMPANI_PA_LINE_ST_CONN_LINE_R_AUXPGA_R_CONN_CONNECT 0x1 + +#define TIMPANI_PA_LINE_ST_CONN_LINE_R_IDAC_R_CONN_S 3 +#define TIMPANI_PA_LINE_ST_CONN_LINE_R_IDAC_R_CONN_M 0x8 +#define TIMPANI_PA_LINE_ST_CONN_LINE_R_IDAC_R_CONN_NO_CONNECT 0x0 +#define TIMPANI_PA_LINE_ST_CONN_LINE_R_IDAC_R_CONN_CONNECT 0x1 + +#define TIMPANI_PA_LINE_ST_CONN_LINE_R_CDAC_R_CONN_S 2 +#define TIMPANI_PA_LINE_ST_CONN_LINE_R_CDAC_R_CONN_M 0x4 +#define TIMPANI_PA_LINE_ST_CONN_LINE_R_CDAC_R_CONN_NO_CONNECT 0x0 +#define TIMPANI_PA_LINE_ST_CONN_LINE_R_CDAC_R_CONN_CONNECT 0x1 + +#define TIMPANI_PA_LINE_ST_CONN_AUXPGA_L_VCM_ADD_CURR_S 0 +#define TIMPANI_PA_LINE_ST_CONN_AUXPGA_L_VCM_ADD_CURR_M 0x3 +#define TIMPANI_PA_LINE_ST_CONN_AUXPGA_L_VCM_ADD_CURR_NONE 0x0 +#define TIMPANI_PA_LINE_ST_CONN_AUXPGA_L_VCM_ADD_CURR_V_1_25UA 0x1 +#define TIMPANI_PA_LINE_ST_CONN_AUXPGA_L_VCM_ADD_CURR_V_2_5UA 0x2 +#define TIMPANI_PA_LINE_ST_CONN_AUXPGA_L_VCM_ADD_CURR_V_3_75UA 0x3 + + +/* -- For PA_LINE_MONO_CONN */ +#define TIMPANI_A_PA_LINE_MONO_CONN (0x3B) +#define TIMPANI_PA_LINE_MONO_CONN_RWC "RW" +#define TIMPANI_PA_LINE_MONO_CONN_POR 0 +#define TIMPANI_PA_LINE_MONO_CONN_S 0 +#define TIMPANI_PA_LINE_MONO_CONN_M 0xFF + + +#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_AUXPGA_L_CONN_S 7 +#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_AUXPGA_L_CONN_M 0x80 +#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_AUXPGA_L_CONN_NO_CONNECT 0x0 +#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_AUXPGA_L_CONN_CONNECT 0x1 + +#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_IDAC_L_CONN_S 6 +#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_IDAC_L_CONN_M 0x40 +#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_IDAC_L_CONN_NO_CONNECT 0x0 +#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_IDAC_L_CONN_CONNECT 0x1 + +#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_CDAC_L_CONN_S 5 +#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_CDAC_L_CONN_M 0x20 +#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_CDAC_L_CONN_NO_CONNECT 0x0 +#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_CDAC_L_CONN_CONNECT 0x1 + +#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_AUXPGA_L_INV_CONN_S 4 +#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_AUXPGA_L_INV_CONN_M 0x10 +#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_AUXPGA_L_INV_CONN_NO_CONNECT 0x0 +#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_AUXPGA_L_INV_CONN_CONNECT 0x1 + +#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_IDAC_L_INV_CONN_S 3 +#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_IDAC_L_INV_CONN_M 0x8 +#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_IDAC_L_INV_CONN_NO_CONNECT 0x0 +#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_IDAC_L_INV_CONN_CONNECT 0x1 + +#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_CDAC_L_INV_CONN_S 2 +#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_CDAC_L_INV_CONN_M 0x4 +#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_CDAC_L_INV_CONN_NO_CONNECT 0x0 +#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_CDAC_L_INV_CONN_CONNECT 0x1 + +#define TIMPANI_PA_LINE_MONO_CONN_AUXPGA_R_VCM_ADD_CURR_S 0 +#define TIMPANI_PA_LINE_MONO_CONN_AUXPGA_R_VCM_ADD_CURR_M 0x3 +#define TIMPANI_PA_LINE_MONO_CONN_AUXPGA_R_VCM_ADD_CURR_NONE 0x0 +#define TIMPANI_PA_LINE_MONO_CONN_AUXPGA_R_VCM_ADD_CURR_V_1_25UA 0x1 +#define TIMPANI_PA_LINE_MONO_CONN_AUXPGA_R_VCM_ADD_CURR_V_2_5UA 0x2 +#define TIMPANI_PA_LINE_MONO_CONN_AUXPGA_R_VCM_ADD_CURR_V_3_75UA 0x3 + + +/* -- For PA_HPH_ST_CONN */ +#define TIMPANI_A_PA_HPH_ST_CONN (0x3C) +#define TIMPANI_PA_HPH_ST_CONN_RWC "RW" +#define TIMPANI_PA_HPH_ST_CONN_POR 0 +#define TIMPANI_PA_HPH_ST_CONN_S 0 +#define TIMPANI_PA_HPH_ST_CONN_M 0xFF + + +#define TIMPANI_PA_HPH_ST_CONN_HPH_L_AUXPGA_L_CONN_S 7 +#define TIMPANI_PA_HPH_ST_CONN_HPH_L_AUXPGA_L_CONN_M 0x80 +#define TIMPANI_PA_HPH_ST_CONN_HPH_L_AUXPGA_L_CONN_NO_CONNECT 0x0 +#define TIMPANI_PA_HPH_ST_CONN_HPH_L_AUXPGA_L_CONN_CONNECT 0x1 + +#define TIMPANI_PA_HPH_ST_CONN_HPH_L_IDAC_L_CONN_S 6 +#define TIMPANI_PA_HPH_ST_CONN_HPH_L_IDAC_L_CONN_M 0x40 +#define TIMPANI_PA_HPH_ST_CONN_HPH_L_IDAC_L_CONN_NO_CONNECT 0x0 +#define TIMPANI_PA_HPH_ST_CONN_HPH_L_IDAC_L_CONN_CONNECT 0x1 + +#define TIMPANI_PA_HPH_ST_CONN_HPH_L_CDAC_L_CONN_S 5 +#define TIMPANI_PA_HPH_ST_CONN_HPH_L_CDAC_L_CONN_M 0x20 +#define TIMPANI_PA_HPH_ST_CONN_HPH_L_CDAC_L_CONN_NO_CONNECT 0x0 +#define TIMPANI_PA_HPH_ST_CONN_HPH_L_CDAC_L_CONN_CONNECT 0x1 + +#define TIMPANI_PA_HPH_ST_CONN_HPH_R_AUXPGA_R_CONN_S 4 +#define TIMPANI_PA_HPH_ST_CONN_HPH_R_AUXPGA_R_CONN_M 0x10 +#define TIMPANI_PA_HPH_ST_CONN_HPH_R_AUXPGA_R_CONN_NO_CONNECT 0x0 +#define TIMPANI_PA_HPH_ST_CONN_HPH_R_AUXPGA_R_CONN_CONNECT 0x1 + +#define TIMPANI_PA_HPH_ST_CONN_HPH_R_IDAC_R_CONN_S 3 +#define TIMPANI_PA_HPH_ST_CONN_HPH_R_IDAC_R_CONN_M 0x8 +#define TIMPANI_PA_HPH_ST_CONN_HPH_R_IDAC_R_CONN_NO_CONNECT 0x0 +#define TIMPANI_PA_HPH_ST_CONN_HPH_R_IDAC_R_CONN_CONNECT 0x1 + +#define TIMPANI_PA_HPH_ST_CONN_HPH_R_CDAC_R_CONN_S 2 +#define TIMPANI_PA_HPH_ST_CONN_HPH_R_CDAC_R_CONN_M 0x4 +#define TIMPANI_PA_HPH_ST_CONN_HPH_R_CDAC_R_CONN_NO_CONNECT 0x0 +#define TIMPANI_PA_HPH_ST_CONN_HPH_R_CDAC_R_CONN_CONNECT 0x1 + +#define TIMPANI_PA_HPH_ST_CONN_HPH_L_RAMP_GEN_EN_S 1 +#define TIMPANI_PA_HPH_ST_CONN_HPH_L_RAMP_GEN_EN_M 0x2 +#define TIMPANI_PA_HPH_ST_CONN_HPH_L_RAMP_GEN_EN_DISABLE 0x1 +#define TIMPANI_PA_HPH_ST_CONN_HPH_L_RAMP_GEN_EN_ENABLE 0x0 + +#define TIMPANI_PA_HPH_ST_CONN_HPH_R_RAMP_GEN_EN_S 0 +#define TIMPANI_PA_HPH_ST_CONN_HPH_R_RAMP_GEN_EN_M 0x1 +#define TIMPANI_PA_HPH_ST_CONN_HPH_R_RAMP_GEN_EN_DISABLE 0x1 +#define TIMPANI_PA_HPH_ST_CONN_HPH_R_RAMP_GEN_EN_ENABLE 0x0 + + +/* -- For PA_HPH_MONO_CONN */ +#define TIMPANI_A_PA_HPH_MONO_CONN (0x3D) +#define TIMPANI_PA_HPH_MONO_CONN_RWC "RW" +#define TIMPANI_PA_HPH_MONO_CONN_POR 0 +#define TIMPANI_PA_HPH_MONO_CONN_S 0 +#define TIMPANI_PA_HPH_MONO_CONN_M 0xFF + + +#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_AUXPGA_L_CONN_S 7 +#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_AUXPGA_L_CONN_M 0x80 +#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_AUXPGA_L_CONN_NO_CONNECT 0x0 +#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_AUXPGA_L_CONN_CONNECT 0x1 + +#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_IDAC_L_CONN_S 6 +#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_IDAC_L_CONN_M 0x40 +#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_IDAC_L_CONN_NO_CONNECT 0x0 +#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_IDAC_L_CONN_CONNECT 0x1 + +#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_CDAC_L_CONN_S 5 +#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_CDAC_L_CONN_M 0x20 +#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_CDAC_L_CONN_NO_CONNECT 0x0 +#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_CDAC_L_CONN_CONNECT 0x1 + +#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_AUXPGA_L_INV_CONN_S 4 +#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_AUXPGA_L_INV_CONN_M 0x10 +#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_AUXPGA_L_INV_CONN_NO_CONNECT 0x0 +#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_AUXPGA_L_INV_CONN_CONNECT 0x1 + +#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_IDAC_L_INV_CONN_S 3 +#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_IDAC_L_INV_CONN_M 0x8 +#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_IDAC_L_INV_CONN_NO_CONNECT 0x0 +#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_IDAC_L_INV_CONN_CONNECT 0x1 + +#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_CDAC_L_INV_CONN_S 2 +#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_CDAC_L_INV_CONN_M 0x4 +#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_CDAC_L_INV_CONN_NO_CONNECT 0x0 +#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_CDAC_L_INV_CONN_CONNECT 0x1 + +#define TIMPANI_PA_HPH_MONO_CONN_RESERVED_S 0 +#define TIMPANI_PA_HPH_MONO_CONN_RESERVED_M 0x3 + + +/* -- For PA_CLASSD_CONN */ +#define TIMPANI_A_PA_CLASSD_CONN (0x3E) +#define TIMPANI_PA_CLASSD_CONN_RWC "RW" +#define TIMPANI_PA_CLASSD_CONN_POR 0 +#define TIMPANI_PA_CLASSD_CONN_S 0 +#define TIMPANI_PA_CLASSD_CONN_M 0xFF + + +#define TIMPANI_PA_CLASSD_CONN_CLASSD_CDAC_CONN_S 7 +#define TIMPANI_PA_CLASSD_CONN_CLASSD_CDAC_CONN_M 0x80 +#define TIMPANI_PA_CLASSD_CONN_CLASSD_CDAC_CONN_NO_CONNECT 0x0 +#define TIMPANI_PA_CLASSD_CONN_CLASSD_CDAC_CONN_CONNECT 0x1 + +#define TIMPANI_PA_CLASSD_CONN_CLASSD_IDAC_CONN_S 6 +#define TIMPANI_PA_CLASSD_CONN_CLASSD_IDAC_CONN_M 0x40 +#define TIMPANI_PA_CLASSD_CONN_CLASSD_IDAC_CONN_NO_CONNECT 0x0 +#define TIMPANI_PA_CLASSD_CONN_CLASSD_IDAC_CONN_CONNECT 0x1 + +#define TIMPANI_PA_CLASSD_CONN_CLASSD_AUXPGA_CONN_S 5 +#define TIMPANI_PA_CLASSD_CONN_CLASSD_AUXPGA_CONN_M 0x20 +#define TIMPANI_PA_CLASSD_CONN_CLASSD_AUXPGA_CONN_NO_CONNECT 0x0 +#define TIMPANI_PA_CLASSD_CONN_CLASSD_AUXPGA_CONN_CONNECT 0x1 + +#define TIMPANI_PA_CLASSD_CONN_CLASSD_PA_MODE_S 4 +#define TIMPANI_PA_CLASSD_CONN_CLASSD_PA_MODE_M 0x10 +#define TIMPANI_PA_CLASSD_CONN_CLASSD_PA_MODE_MONO_DIFF 0x1 +#define TIMPANI_PA_CLASSD_CONN_CLASSD_PA_MODE_STEREO 0x0 + +#define TIMPANI_PA_CLASSD_CONN_RESERVED_S 0 +#define TIMPANI_PA_CLASSD_CONN_RESERVED_M 0xF + + +/* -- For PA_CNP_CTL */ +#define TIMPANI_A_PA_CNP_CTL (0x3F) +#define TIMPANI_PA_CNP_CTL_RWC "RW" +#define TIMPANI_PA_CNP_CTL_POR 0x07 +#define TIMPANI_PA_CNP_CTL_S 0 +#define TIMPANI_PA_CNP_CTL_M 0xFF + + +#define TIMPANI_PA_CNP_CTL_CNP_RAMP_GEN_CURRENT_S 6 +#define TIMPANI_PA_CNP_CTL_CNP_RAMP_GEN_CURRENT_M 0xC0 +#define TIMPANI_PA_CNP_CTL_CNP_RAMP_GEN_CURRENT_V_1_75_NA 0x0 +#define TIMPANI_PA_CNP_CTL_CNP_RAMP_GEN_CURRENT_V_3_5_NA_NORMAL_OP 0x1 +#define TIMPANI_PA_CNP_CTL_CNP_RAMP_GEN_CURRENT_V_5_25_NA 0x2 +#define TIMPANI_PA_CNP_CTL_CNP_RAMP_GEN_CURRENT_V_10_NA 0x3 + +#define TIMPANI_PA_CNP_CTL_RESERVED_S 4 +#define TIMPANI_PA_CNP_CTL_RESERVED_M 0x30 + +#define TIMPANI_PA_CNP_CTL_CLASSD_SUPPLY_DUMP_CIRCUIT_EN_S 3 +#define TIMPANI_PA_CNP_CTL_CLASSD_SUPPLY_DUMP_CIRCUIT_EN_M 0x8 +#define TIMPANI_PA_CNP_CTL_CLASSD_SUPPLY_DUMP_CIRCUIT_EN_DISABLE 0x0 +#define TIMPANI_PA_CNP_CTL_CLASSD_SUPPLY_DUMP_CIRCUIT_EN_ENABLE 0x1 + +#define TIMPANI_PA_CNP_CTL_CLASSD_SUPPLY_DUMP_THRESH_S 0 +#define TIMPANI_PA_CNP_CTL_CLASSD_SUPPLY_DUMP_THRESH_M 0x7 +#define TIMPANI_PA_CNP_CTL_CLASSD_SUPPLY_DUMP_THRESH_V_2_220_V 0x0 +#define TIMPANI_PA_CNP_CTL_CLASSD_SUPPLY_DUMP_THRESH_V_2_243_V 0x1 +#define TIMPANI_PA_CNP_CTL_CLASSD_SUPPLY_DUMP_THRESH_V_2_266_V 0x2 +#define TIMPANI_PA_CNP_CTL_CLASSD_SUPPLY_DUMP_THRESH_V_2_290_V 0x3 +#define TIMPANI_PA_CNP_CTL_CLASSD_SUPPLY_DUMP_THRESH_V_2_341_V 0x4 +#define TIMPANI_PA_CNP_CTL_CLASSD_SUPPLY_DUMP_THRESH_V_2_339_V 0x5 +#define TIMPANI_PA_CNP_CTL_CLASSD_SUPPLY_DUMP_THRESH_V_2_365_V 0x6 +#define TIMPANI_PA_CNP_CTL_CLASSD_SUPPLY_DUMP_THRESH_V_2_391_V 0x7 + + +/* -- For PA_CLASSD_L_CTL */ +#define TIMPANI_A_PA_CLASSD_L_CTL (0x40) +#define TIMPANI_PA_CLASSD_L_CTL_RWC "RW" +#define TIMPANI_PA_CLASSD_L_CTL_POR 0x08 +#define TIMPANI_PA_CLASSD_L_CTL_S 0 +#define TIMPANI_PA_CLASSD_L_CTL_M 0xFF + + +#define TIMPANI_PA_CLASSD_L_CTL_RESERVED_S 6 +#define TIMPANI_PA_CLASSD_L_CTL_RESERVED_M 0xC0 + +#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_LOGIC_RESET_S 5 +#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_LOGIC_RESET_M 0x20 +#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_LOGIC_RESET_NORMAL_OP 0x0 +#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_LOGIC_RESET_RESET_PA_LOGIC 0x1 + +#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_INT_RESET_S 4 +#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_INT_RESET_M 0x10 +#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_INT_RESET_NORMAL_OP 0x0 +#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_INT_RESET_DISCHARGE_CAPS 0x1 + +#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_REF_SEL_S 2 +#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_REF_SEL_M 0xC +#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_REF_SEL_GND 0x0 +#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_REF_SEL_IBIAS_X_R_REF 0x1 +#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_REF_SEL_BG_VOLTAGE 0x2 +#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_REF_SEL_VDD_BY_2 0x3 + +#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_PA_FORCE_1_S 1 +#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_PA_FORCE_1_M 0x2 +#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_PA_FORCE_1_NORMAL_OP 0x0 +#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_PA_FORCE_1_PA_OUT_TO_VDD 0x1 + +#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_PA_FORCE_0_S 0 +#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_PA_FORCE_0_M 0x1 +#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_PA_FORCE_0_NORMAL_OP 0x0 +#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_PA_FORCE_0_PA_OUT_TO_GND 0x1 + + +/* -- For PA_CLASSD_R_CTL */ +#define TIMPANI_A_PA_CLASSD_R_CTL (0x41) +#define TIMPANI_PA_CLASSD_R_CTL_RWC "RW" +#define TIMPANI_PA_CLASSD_R_CTL_POR 0x08 +#define TIMPANI_PA_CLASSD_R_CTL_S 0 +#define TIMPANI_PA_CLASSD_R_CTL_M 0xFF + + +#define TIMPANI_PA_CLASSD_R_CTL_RESERVED_S 6 +#define TIMPANI_PA_CLASSD_R_CTL_RESERVED_M 0xC0 + +#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_LOGIC_RESET_S 5 +#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_LOGIC_RESET_M 0x20 +#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_LOGIC_RESET_NORMAL_OP 0x0 +#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_LOGIC_RESET_RESET_PA_LOGIC 0x1 + +#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_INT_RESET_S 4 +#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_INT_RESET_M 0x10 +#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_INT_RESET_NORMAL_OP 0x0 +#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_INT_RESET_DISCHARGE_CAPS 0x1 + +#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_REF_SEL_S 2 +#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_REF_SEL_M 0xC +#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_REF_SEL_GND 0x0 +#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_REF_SEL_IBIAS_X_R_REF 0x1 +#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_REF_SEL_BG_VOLTAGE 0x2 +#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_REF_SEL_VDD_BY_2 0x3 + +#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_PA_FORCE_1_S 1 +#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_PA_FORCE_1_M 0x2 +#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_PA_FORCE_1_NORMAL_OP 0x0 +#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_PA_FORCE_1_PA_OUT_TO_VDD 0x1 + +#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_PA_FORCE_0_S 0 +#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_PA_FORCE_0_M 0x1 +#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_PA_FORCE_0_NORMAL_OP 0x0 +#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_PA_FORCE_0_PA_OUT_TO_GND 0x1 + + +/* -- For PA_CLASSD_INT2_CTL */ +#define TIMPANI_A_PA_CLASSD_INT2_CTL (0x42) +#define TIMPANI_PA_CLASSD_INT2_CTL_RWC "RW" +#define TIMPANI_PA_CLASSD_INT2_CTL_POR 0xb0 +#define TIMPANI_PA_CLASSD_INT2_CTL_S 0 +#define TIMPANI_PA_CLASSD_INT2_CTL_M 0xFF + + +#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_L_INT2_CFB_S 6 +#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_L_INT2_CFB_M 0xC0 +#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_L_INT2_CFB_V_5_0PF 0x0 +#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_L_INT2_CFB_V_7_5PF 0x1 +#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_L_INT2_CFB_V_10PF 0x2 +#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_L_INT2_CFB_V_15PF 0x3 + +#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_L_INT2_RIN_S 4 +#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_L_INT2_RIN_M 0x30 +#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_L_INT2_RIN_V_100K 0x0 +#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_L_INT2_RIN_V_150K 0x1 +#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_L_INT2_RIN_V_175K 0x2 +#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_L_INT2_RIN_V_200K 0x3 + +#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_R_INT2_CFB_S 2 +#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_R_INT2_CFB_M 0xC +#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_R_INT2_CFB_V_5_0PF 0x0 +#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_R_INT2_CFB_V_7_5PF 0x1 +#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_R_INT2_CFB_V_10PF 0x2 +#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_R_INT2_CFB_V_15PF 0x3 + +#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_R_INT2_RIN_S 0 +#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_R_INT2_RIN_M 0x3 +#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_R_INT2_RIN_V_100K 0x0 +#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_R_INT2_RIN_V_150K 0x1 +#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_R_INT2_RIN_V_175K 0x2 +#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_R_INT2_RIN_V_200K 0x3 + + +/* -- For PA_HPH_L_OCP_CLK_CTL */ +#define TIMPANI_A_PA_HPH_L_OCP_CLK_CTL (0x43) +#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_RWC "RW" +#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_POR 0xf2 +#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_S 0 +#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_M 0xFF + + +#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CARRIER_DIV_2_EN_S 7 +#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CARRIER_DIV_2_EN_M 0x80 +#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CARRIER_DIV_2_EN_ENABLE 0x1 +#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CARRIER_DIV_2_EN_DISABLE 0x0 + +#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CARRIER_PROG_DIV_EN_S 6 +#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CARRIER_PROG_DIV_EN_M 0x40 +#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CARRIER_PROG_DIV_EN_ENABLE 0x1 +#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CARRIER_PROG_DIV_EN_DISABLE 0x0 + +#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CARRIER_PROG_DIV_RATIO_S 4 +#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CARRIER_PROG_DIV_RATIO_M 0x30 +#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CARRIER_PROG_DIV_RATIO_DIV2 0x0 +#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CARRIER_PROG_DIV_RATIO_DIV4 0x1 +#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CARRIER_PROG_DIV_RATIO_DIV6 0x2 +#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CARRIER_PROG_DIV_RATIO_DIV8 0x3 + +#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CLK_SEL_LEFT_S 3 +#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CLK_SEL_LEFT_M 0x8 +#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CLK_SEL_LEFT_CLK_FROM_CH_2 0x1 +#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CLK_SEL_LEFT_CLK_FROM_CH_1 0x0 + +#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_TIMER_DIV_2_EN_S 2 +#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_TIMER_DIV_2_EN_M 0x4 +#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_TIMER_DIV_2_EN_ENABLE 0x1 +#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_TIMER_DIV_2_EN_DISABLE 0x0 + +#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_TIMER_DIV_RATIO_S 0 +#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_TIMER_DIV_RATIO_M 0x3 +#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_TIMER_DIV_RATIO_DIV_BY_4 0x0 +#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_TIMER_DIV_RATIO_DIV_BY_8 0x1 +#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_TIMER_DIV_RATIO_DIV_BY_12 0x2 +#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_TIMER_DIV_RATIO_DIV_BY_16 0x3 + + +/* -- For PA_CLASSD_L_SW_CTL */ +#define TIMPANI_A_PA_CLASSD_L_SW_CTL (0x44) +#define TIMPANI_PA_CLASSD_L_SW_CTL_RWC "RW" +#define TIMPANI_PA_CLASSD_L_SW_CTL_POR 0x37 +#define TIMPANI_PA_CLASSD_L_SW_CTL_S 0 +#define TIMPANI_PA_CLASSD_L_SW_CTL_M 0xFF + + +#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_BREAK_BEFORE_MAKE_DELAY_S 6 +#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_BREAK_BEFORE_MAKE_DELAY_M 0xC0 +#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_BREAK_BEFORE_MAKE_DELAY_V_1 0x0 +#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_BREAK_BEFORE_MAKE_DELAY_V_2 0x1 +#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_BREAK_BEFORE_MAKE_DELAY_V_3 0x2 +#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_BREAK_BEFORE_MAKE_DELAY_V_4 0x3 + +#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_OUT_DRIVE_STREN_S 4 +#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_OUT_DRIVE_STREN_M 0x30 +#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_OUT_DRIVE_STREN_V_3_OF_6_UNITS 0x0 +#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_OUT_DRIVE_STREN_V_4_OF_6_UNITS 0x1 +#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_OUT_DRIVE_STREN_V_5_OF_6_UNITS 0x2 +#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_OUT_DRIVE_STREN_V_6_OF_6_UNITS 0x3 + +#define TIMPANI_PA_CLASSD_L_SW_CTL_RESERVED_S 3 +#define TIMPANI_PA_CLASSD_L_SW_CTL_RESERVED_M 0x8 + +#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_CDAC_BYPASS_CAP_EN_S 2 +#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_CDAC_BYPASS_CAP_EN_M 0x4 +#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_CDAC_BYPASS_CAP_EN_DISABLE 0x0 +#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_CDAC_BYPASS_CAP_EN_ENABLE 0x1 + +#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_CDAC_NON_OVERLAP_EN_S 1 +#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_CDAC_NON_OVERLAP_EN_M 0x2 +#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_CDAC_NON_OVERLAP_EN_DISABLE 0x0 +#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_CDAC_NON_OVERLAP_EN_ENABLE 0x1 + +#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_CDAC_SWITCH_MODE_S 0 +#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_CDAC_SWITCH_MODE_M 0x1 +#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_CDAC_SWITCH_MODE_POWER_GROUND 0x0 +#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_CDAC_SWITCH_MODE_RST_MIDPOINT 0x1 + +/* -- For PA_CLASSD_L_OCP1 */ +#define TIMPANI_A_PA_CLASSD_L_OCP1 (0x45) +#define TIMPANI_PA_CLASSD_L_OCP1_RWC "RW" +#define TIMPANI_PA_CLASSD_L_OCP1_POR 0xff +#define TIMPANI_PA_CLASSD_L_OCP1_S 0 +#define TIMPANI_PA_CLASSD_L_OCP1_M 0xFF + + +#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_EN_S 7 +#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_EN_M 0x80 +#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_EN_DISABLE 0x0 +#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_EN_ENABLE 0x1 + +#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_LOCK_S 6 +#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_LOCK_M 0x40 +#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_LOCK_NEVER_LOCKS 0x0 +#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_LOCK_LOCKS 0x1 + +#define TIMPANI_PA_CLASSD_L_OCP1_OCP_CUR_THRESH_S 4 +#define TIMPANI_PA_CLASSD_L_OCP1_OCP_CUR_THRESH_M 0x30 +#define TIMPANI_PA_CLASSD_L_OCP1_OCP_CUR_THRESH_V_100MA_83_3MA_66_7MA_50MA 0x0 +#define TIMPANI_PA_CLASSD_L_OCP1_OCP_CUR_THRESH_V_133MA_111MA_88_7MA_66_7MA 0x1 +#define TIMPANI_PA_CLASSD_L_OCP1_OCP_CUR_THRESH_V_166MA_138MA_111MA_83_3MA 0x2 +#define TIMPANI_PA_CLASSD_L_OCP1_OCP_CUR_THRESH_V_200MA_166MA_133MA_100MA 0x3 + +#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_NUM_CONN_ATTEMPTS_S 0 +#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_NUM_CONN_ATTEMPTS_M 0xF +#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_NUM_CONN_ATTEMPTS_V_1 0x1 +#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_NUM_CONN_ATTEMPTS_V_2 0x2 +#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_NUM_CONN_ATTEMPTS_V_3 0x3 +#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_NUM_CONN_ATTEMPTS_V_4 0x4 +#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_NUM_CONN_ATTEMPTS_V_5 0x5 +#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_NUM_CONN_ATTEMPTS_V_6 0x6 +#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_NUM_CONN_ATTEMPTS_V_7 0x7 +#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_NUM_CONN_ATTEMPTS_V_8 0x8 +#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_NUM_CONN_ATTEMPTS_V_9 0x9 +#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_NUM_CONN_ATTEMPTS_V_10 0xA +#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_NUM_CONN_ATTEMPTS_V_11 0xB +#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_NUM_CONN_ATTEMPTS_V_12 0xC +#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_NUM_CONN_ATTEMPTS_V_13 0xD +#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_NUM_CONN_ATTEMPTS_V_14 0xE +#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_NUM_CONN_ATTEMPTS_V_15 0xF + +/* -- For PA_CLASSD_L_OCP2 */ +#define TIMPANI_A_PA_CLASSD_L_OCP2 (0x46) +#define TIMPANI_PA_CLASSD_L_OCP2_RWC "RW" +#define TIMPANI_PA_CLASSD_L_OCP2_POR 0x77 +#define TIMPANI_PA_CLASSD_L_OCP2_S 0 +#define TIMPANI_PA_CLASSD_L_OCP2_M 0xFF + + +#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_S 4 +#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_M 0xF0 +#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_V_255 0x0 +#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_V_511 0x1 +#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_V_767 0x2 +#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_V_1023 0x3 +#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_V_1279 0x4 +#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_V_1535 0x5 +#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_V_1791 0x6 +#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_V_2047 0x7 +#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_V_2303 0x8 +#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_V_2559 0x9 +#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_V_2815 0xA +#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_V_3071 0xB +#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_V_3327 0xC +#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_V_3583 0xD +#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_V_3839 0xE +#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_V_4095 0xF + +#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_S 0 +#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_M 0xF +#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_V_255 0x0 +#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_V_511 0x1 +#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_V_767 0x2 +#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_V_1023 0x3 +#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_V_1279 0x4 +#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_V_1535 0x5 +#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_V_1791 0x6 +#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_V_2047 0x7 +#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_V_2303 0x8 +#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_V_2559 0x9 +#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_V_2815 0xA +#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_V_3071 0xB +#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_V_3327 0xC +#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_V_3583 0xD +#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_V_3839 0xE +#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_V_4095 0xF + + +/* -- For PA_HPH_R_OCP_CLK_CTL */ +#define TIMPANI_A_PA_HPH_R_OCP_CLK_CTL (0x47) +#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_RWC "RW" +#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_POR 0xf2 +#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_S 0 +#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_M 0xFF + + +#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CARRIER_DIV_2_EN_S 7 +#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CARRIER_DIV_2_EN_M 0x80 +#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CARRIER_DIV_2_EN_ENABLE 0x1 +#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CARRIER_DIV_2_EN_DISABLE 0x0 + +#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CARRIER_PROG_DIV_EN_S 6 +#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CARRIER_PROG_DIV_EN_M 0x40 +#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CARRIER_PROG_DIV_EN_ENABLE 0x1 +#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CARRIER_PROG_DIV_EN_DISABLE 0x0 + +#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CARRIER_PROG_DIV_RATIO_S 4 +#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CARRIER_PROG_DIV_RATIO_M 0x30 +#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CARRIER_PROG_DIV_RATIO_DIV2 0x0 +#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CARRIER_PROG_DIV_RATIO_DIV4 0x1 +#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CARRIER_PROG_DIV_RATIO_DIV6 0x2 +#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CARRIER_PROG_DIV_RATIO_DIV8 0x3 + +#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CLK_SEL_RIGHT_S 3 +#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CLK_SEL_RIGHT_M 0x8 +#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CLK_SEL_RIGHT_CLK_FROM_CH_2 0x1 +#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CLK_SEL_RIGHT_CLK_FROM_CH_1 0x0 + +#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_TIMER_DIV_2_EN_S 2 +#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_TIMER_DIV_2_EN_M 0x4 +#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_TIMER_DIV_2_EN_ENABLE 0x1 +#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_TIMER_DIV_2_EN_DISABLE 0x0 + +#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_TIMER_DIV_RATIO_S 0 +#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_TIMER_DIV_RATIO_M 0x3 +#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_TIMER_DIV_RATIO_DIV_BY_4 0x0 +#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_TIMER_DIV_RATIO_DIV_BY_8 0x1 +#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_TIMER_DIV_RATIO_DIV_BY_12 0x2 +#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_TIMER_DIV_RATIO_DIV_BY_16 0x3 + + +/* -- For PA_CLASSD_R_SW_CTL */ +#define TIMPANI_A_PA_CLASSD_R_SW_CTL (0x48) +#define TIMPANI_PA_CLASSD_R_SW_CTL_RWC "RW" +#define TIMPANI_PA_CLASSD_R_SW_CTL_POR 0x37 +#define TIMPANI_PA_CLASSD_R_SW_CTL_S 0 +#define TIMPANI_PA_CLASSD_R_SW_CTL_M 0xFF + + +#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_BREAK_BEFORE_MAKE_DELAY_S 6 +#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_BREAK_BEFORE_MAKE_DELAY_M 0xC0 +#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_BREAK_BEFORE_MAKE_DELAY_V_1 0x0 +#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_BREAK_BEFORE_MAKE_DELAY_V_2 0x1 +#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_BREAK_BEFORE_MAKE_DELAY_V_3 0x2 +#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_BREAK_BEFORE_MAKE_DELAY_V_4 0x3 + +#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_OUT_DRIVE_STREN_S 4 +#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_OUT_DRIVE_STREN_M 0x30 +#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_OUT_DRIVE_STREN_V_3_OF_6_UNITS 0x0 +#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_OUT_DRIVE_STREN_V_4_OF_6_UNITS 0x1 +#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_OUT_DRIVE_STREN_V_5_OF_6_UNITS 0x2 +#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_OUT_DRIVE_STREN_V_6_OF_6_UNITS 0x3 + +#define TIMPANI_PA_CLASSD_R_SW_CTL_RESERVED_S 3 +#define TIMPANI_PA_CLASSD_R_SW_CTL_RESERVED_M 0x8 + +#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_CDAC_BYPASS_CAP_EN_S 2 +#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_CDAC_BYPASS_CAP_EN_M 0x4 +#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_CDAC_BYPASS_CAP_EN_DISABLE 0x0 +#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_CDAC_BYPASS_CAP_EN_ENABLE 0x1 + +#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_CDAC_NON_OVERLAP_EN_S 1 +#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_CDAC_NON_OVERLAP_EN_M 0x2 +#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_CDAC_NON_OVERLAP_EN_DISABLE 0x0 +#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_CDAC_NON_OVERLAP_EN_ENABLE 0x1 + +#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_CDAC_SWITCH_MODE_S 0 +#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_CDAC_SWITCH_MODE_M 0x1 +#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_CDAC_SWITCH_MODE_POWER_GROUND 0x0 +#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_CDAC_SWITCH_MODE_RST_MIDPOINT 0x1 + + +/* -- For PA_CLASSD_R_OCP1 */ +#define TIMPANI_A_PA_CLASSD_R_OCP1 (0x49) +#define TIMPANI_PA_CLASSD_R_OCP1_RWC "RW" +#define TIMPANI_PA_CLASSD_R_OCP1_POR 0xff +#define TIMPANI_PA_CLASSD_R_OCP1_S 0 +#define TIMPANI_PA_CLASSD_R_OCP1_M 0xFF + + +#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_EN_S 7 +#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_EN_M 0x80 +#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_EN_DISABLE 0x0 +#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_EN_ENABLE 0x1 + +#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_LOCK_S 6 +#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_LOCK_M 0x40 +#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_LOCK_NEVER_LOCKS 0x0 +#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_LOCK_LOCKS 0x1 + +#define TIMPANI_PA_CLASSD_R_OCP1_OCP_CUR_THRESH_S 4 +#define TIMPANI_PA_CLASSD_R_OCP1_OCP_CUR_THRESH_M 0x30 +#define TIMPANI_PA_CLASSD_R_OCP1_OCP_CUR_THRESH_V_100MA_83_3MA_66_7MA_50MA 0x0 +#define TIMPANI_PA_CLASSD_R_OCP1_OCP_CUR_THRESH_V_133MA_111MA_88_7MA_66_7MA 0x1 +#define TIMPANI_PA_CLASSD_R_OCP1_OCP_CUR_THRESH_V_166MA_138MA_111MA_83_3MA 0x2 +#define TIMPANI_PA_CLASSD_R_OCP1_OCP_CUR_THRESH_V_200MA_166MA_133MA_100MA 0x3 + +#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_NUM_CONN_ATTEMPTS_S 0 +#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_NUM_CONN_ATTEMPTS_M 0xF +#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_NUM_CONN_ATTEMPTS_V_1 0x1 +#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_NUM_CONN_ATTEMPTS_V_2 0x2 +#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_NUM_CONN_ATTEMPTS_V_3 0x3 +#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_NUM_CONN_ATTEMPTS_V_4 0x4 +#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_NUM_CONN_ATTEMPTS_V_5 0x5 +#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_NUM_CONN_ATTEMPTS_V_6 0x6 +#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_NUM_CONN_ATTEMPTS_V_7 0x7 +#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_NUM_CONN_ATTEMPTS_V_8 0x8 +#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_NUM_CONN_ATTEMPTS_V_9 0x9 +#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_NUM_CONN_ATTEMPTS_V_10 0xA +#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_NUM_CONN_ATTEMPTS_V_11 0xB +#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_NUM_CONN_ATTEMPTS_V_12 0xC +#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_NUM_CONN_ATTEMPTS_V_13 0xD +#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_NUM_CONN_ATTEMPTS_V_14 0xE +#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_NUM_CONN_ATTEMPTS_V_15 0xF + + +/* -- For PA_CLASSD_R_OCP2 */ +#define TIMPANI_A_PA_CLASSD_R_OCP2 (0x4A) +#define TIMPANI_PA_CLASSD_R_OCP2_RWC "RW" +#define TIMPANI_PA_CLASSD_R_OCP2_POR 0x77 +#define TIMPANI_PA_CLASSD_R_OCP2_S 0 +#define TIMPANI_PA_CLASSD_R_OCP2_M 0xFF + + +#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_S 4 +#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_M 0xF0 +#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_V_255 0x0 +#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_V_511 0x1 +#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_V_767 0x2 +#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_V_1023 0x3 +#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_V_1279 0x4 +#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_V_1535 0x5 +#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_V_1791 0x6 +#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_V_2047 0x7 +#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_V_2303 0x8 +#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_V_2559 0x9 +#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_V_2815 0xA +#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_V_3071 0xB +#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_V_3327 0xC +#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_V_3583 0xD +#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_V_3839 0xE +#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_V_4095 0xF + +#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_S 0 +#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_M 0xF +#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_V_255 0x0 +#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_V_511 0x1 +#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_V_767 0x2 +#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_V_1023 0x3 +#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_V_1279 0x4 +#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_V_1535 0x5 +#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_V_1791 0x6 +#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_V_2047 0x7 +#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_V_2303 0x8 +#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_V_2559 0x9 +#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_V_2815 0xA +#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_V_3071 0xB +#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_V_3327 0xC +#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_V_3583 0xD +#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_V_3839 0xE +#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_V_4095 0xF + + +/* -- For PA_HPH_CTL1 */ +#define TIMPANI_A_PA_HPH_CTL1 (0x4B) +#define TIMPANI_PA_HPH_CTL1_RWC "RW" +#define TIMPANI_PA_HPH_CTL1_POR 0x44 +#define TIMPANI_PA_HPH_CTL1_S 0 +#define TIMPANI_PA_HPH_CTL1_M 0xFF + + +#define TIMPANI_PA_HPH_CTL1_HPH_GM3_BIAS_S 4 +#define TIMPANI_PA_HPH_CTL1_HPH_GM3_BIAS_M 0xF0 +#define TIMPANI_PA_HPH_CTL1_HPH_GM3_BIAS_V_400PER 0x1 +#define TIMPANI_PA_HPH_CTL1_HPH_GM3_BIAS_V_200PER 0x2 +#define TIMPANI_PA_HPH_CTL1_HPH_GM3_BIAS_V_133PER 0x3 +#define TIMPANI_PA_HPH_CTL1_HPH_GM3_BIAS_V_100PER 0x4 +#define TIMPANI_PA_HPH_CTL1_HPH_GM3_BIAS_V_66PER 0x6 +#define TIMPANI_PA_HPH_CTL1_HPH_GM3_BIAS_V_50PER 0x8 +#define TIMPANI_PA_HPH_CTL1_HPH_GM3_BIAS_V_33PER 0xC + +#define TIMPANI_PA_HPH_CTL1_HPH_SHORT_CIRCUIT_DET_EN_S 3 +#define TIMPANI_PA_HPH_CTL1_HPH_SHORT_CIRCUIT_DET_EN_M 0x8 +#define TIMPANI_PA_HPH_CTL1_HPH_SHORT_CIRCUIT_DET_EN_DISABLE 0x0 +#define TIMPANI_PA_HPH_CTL1_HPH_SHORT_CIRCUIT_DET_EN_ENABLE 0x1 + +#define TIMPANI_PA_HPH_CTL1_HPH_SHORT_CIRCUIT_CUR_LIMIT_S 0 +#define TIMPANI_PA_HPH_CTL1_HPH_SHORT_CIRCUIT_CUR_LIMIT_M 0x7 +#define TIMPANI_PA_HPH_CTL1_HPH_SHORT_CIRCUIT_CUR_LIMIT_V_300MA 0x0 +#define TIMPANI_PA_HPH_CTL1_HPH_SHORT_CIRCUIT_CUR_LIMIT_V_350MA 0x2 +#define TIMPANI_PA_HPH_CTL1_HPH_SHORT_CIRCUIT_CUR_LIMIT_V_365MA 0x3 +#define TIMPANI_PA_HPH_CTL1_HPH_SHORT_CIRCUIT_CUR_LIMIT_V_150MA 0x4 +#define TIMPANI_PA_HPH_CTL1_HPH_SHORT_CIRCUIT_CUR_LIMIT_V_190MA 0x6 +#define TIMPANI_PA_HPH_CTL1_HPH_SHORT_CIRCUIT_CUR_LIMIT_V_220MA 0x7 + + +/* -- For PA_HPH_CTL2 */ +#define TIMPANI_A_PA_HPH_CTL2 (0x4C) +#define TIMPANI_PA_HPH_CTL2_RWC "RW" +#define TIMPANI_PA_HPH_CTL2_POR 0xC8 +#define TIMPANI_PA_HPH_CTL2_S 0 +#define TIMPANI_PA_HPH_CTL2_M 0xFF + + +#define TIMPANI_PA_HPH_CTL2_HPH_SW_VNEG_CTL_S 7 +#define TIMPANI_PA_HPH_CTL2_HPH_SW_VNEG_CTL_M 0x80 +#define TIMPANI_PA_HPH_CTL2_HPH_SW_VNEG_CTL_VNEG 0x1 +#define TIMPANI_PA_HPH_CTL2_HPH_SW_VNEG_CTL_VSS 0x0 + +#define TIMPANI_PA_HPH_CTL2_HPH_VNEG_PS_GAIN_S 6 +#define TIMPANI_PA_HPH_CTL2_HPH_VNEG_PS_GAIN_M 0x40 +#define TIMPANI_PA_HPH_CTL2_HPH_VNEG_PS_GAIN_V_1_5 0x1 +#define TIMPANI_PA_HPH_CTL2_HPH_VNEG_PS_GAIN_V_2_5 0x0 + +#define TIMPANI_PA_HPH_CTL2_HPH_PS_FILTER_EN_S 5 +#define TIMPANI_PA_HPH_CTL2_HPH_PS_FILTER_EN_M 0x20 +#define TIMPANI_PA_HPH_CTL2_HPH_PS_FILTER_EN_ENABLE 0x1 +#define TIMPANI_PA_HPH_CTL2_HPH_PS_FILTER_EN_DISABLE 0x0 + +#define TIMPANI_PA_HPH_CTL2_HPH_OCP_EN_S 4 +#define TIMPANI_PA_HPH_CTL2_HPH_OCP_EN_M 0x10 +#define TIMPANI_PA_HPH_CTL2_HPH_OCP_EN_ENABLE 0x1 +#define TIMPANI_PA_HPH_CTL2_HPH_OCP_EN_DISABLE 0x0 + +#define TIMPANI_PA_HPH_CTL2_HPH_VREF_SEL_S 2 +#define TIMPANI_PA_HPH_CTL2_HPH_VREF_SEL_M 0xC +#define TIMPANI_PA_HPH_CTL2_HPH_VREF_SEL_GROUND 0x0 +#define TIMPANI_PA_HPH_CTL2_HPH_VREF_SEL_IBIAS_ON_RESISTOR 0x1 +#define TIMPANI_PA_HPH_CTL2_HPH_VREF_SEL_BG 0x2 +#define TIMPANI_PA_HPH_CTL2_HPH_VREF_SEL_AVDD_BY_2 0x3 + +#define TIMPANI_PA_HPH_CTL2_HPH_OUT_SHUNT_EN_S 1 +#define TIMPANI_PA_HPH_CTL2_HPH_OUT_SHUNT_EN_M 0x2 +#define TIMPANI_PA_HPH_CTL2_HPH_OUT_SHUNT_EN_DISABLE 0x0 +#define TIMPANI_PA_HPH_CTL2_HPH_OUT_SHUNT_EN_ENABLE 0x1 + +#define TIMPANI_PA_HPH_CTL2_RESERVED_S 0 +#define TIMPANI_PA_HPH_CTL2_RESERVED_M 0x1 + + +/* -- For PA_LINE_AUXO_CTL */ +#define TIMPANI_A_PA_LINE_AUXO_CTL (0x4D) +#define TIMPANI_PA_LINE_AUXO_CTL_RWC "RW" +#define TIMPANI_PA_LINE_AUXO_CTL_POR 0x2 +#define TIMPANI_PA_LINE_AUXO_CTL_S 0 +#define TIMPANI_PA_LINE_AUXO_CTL_M 0xFF + + +#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_AUXO_RAMPGEN_CNT_S 6 +#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_AUXO_RAMPGEN_CNT_M 0xC0 +#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_AUXO_RAMPGEN_CNT_V_1_75NA 0x0 +#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_AUXO_RAMPGEN_CNT_V_3_5NA 0x1 +#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_AUXO_RAMPGEN_CNT_V_5_25NA 0x2 +#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_AUXO_RAMPGEN_CNT_V_10NA 0x3 + +#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_L_BIAS_CUR_S 4 +#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_L_BIAS_CUR_M 0x30 +#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_L_BIAS_CUR_V_60UA 0x0 +#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_L_BIAS_CUR_V_30UA_1 0x1 +#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_L_BIAS_CUR_V_30UA_2 0x2 +#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_L_BIAS_CUR_V_15UA 0x3 + +#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_R_BIAS_CUR_S 2 +#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_R_BIAS_CUR_M 0xC +#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_R_BIAS_CUR_V_60UA 0x0 +#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_R_BIAS_CUR_V_30UA_1 0x1 +#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_R_BIAS_CUR_V_30UA_2 0x2 +#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_R_BIAS_CUR_V_15UA 0x3 + +#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_AUXO_CM_REF_SEL_S 0 +#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_AUXO_CM_REF_SEL_M 0x3 +#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_AUXO_CM_REF_SEL_VSSA 0x0 +#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_AUXO_CM_REF_SEL_BG 0x2 +#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_AUXO_CM_REF_SEL_VDDA_BY_2 0x3 + + +/* -- For PA_AUXO_EARPA_CTL */ +#define TIMPANI_A_PA_AUXO_EARPA_CTL (0x4E) +#define TIMPANI_PA_AUXO_EARPA_CTL_RWC "RW" +#define TIMPANI_PA_AUXO_EARPA_CTL_POR 0xe +#define TIMPANI_PA_AUXO_EARPA_CTL_S 0 +#define TIMPANI_PA_AUXO_EARPA_CTL_M 0xFF + + +#define TIMPANI_PA_AUXO_EARPA_CTL_RESERVED_S 6 +#define TIMPANI_PA_AUXO_EARPA_CTL_RESERVED_M 0xC0 + +#define TIMPANI_PA_AUXO_EARPA_CTL_AUXO_BIAS_CUR_S 4 +#define TIMPANI_PA_AUXO_EARPA_CTL_AUXO_BIAS_CUR_M 0x30 +#define TIMPANI_PA_AUXO_EARPA_CTL_AUXO_BIAS_CUR_V_60UA 0x0 +#define TIMPANI_PA_AUXO_EARPA_CTL_AUXO_BIAS_CUR_V_30UA 0x1 +#define TIMPANI_PA_AUXO_EARPA_CTL_AUXO_BIAS_CUR_V_30UA_SAME_AS_01 0x2 +#define TIMPANI_PA_AUXO_EARPA_CTL_AUXO_BIAS_CUR_V_15UA 0x3 + +#define TIMPANI_PA_AUXO_EARPA_CTL_AUXO_GAIN_S 3 +#define TIMPANI_PA_AUXO_EARPA_CTL_AUXO_GAIN_M 0x8 +#define TIMPANI_PA_AUXO_EARPA_CTL_AUXO_GAIN_NEG_4_5DB 0x1 +#define TIMPANI_PA_AUXO_EARPA_CTL_AUXO_GAIN_NEG_3_0DB 0x0 + +#define TIMPANI_PA_AUXO_EARPA_CTL_EARPA_MASTER_BIAS_CUR_S 1 +#define TIMPANI_PA_AUXO_EARPA_CTL_EARPA_MASTER_BIAS_CUR_M 0x6 +#define TIMPANI_PA_AUXO_EARPA_CTL_EARPA_MASTER_BIAS_CUR_V_12_5UA 0x0 +#define TIMPANI_PA_AUXO_EARPA_CTL_EARPA_MASTER_BIAS_CUR_V_10_0UA 0x1 +#define TIMPANI_PA_AUXO_EARPA_CTL_EARPA_MASTER_BIAS_CUR_V_7_5UA 0x2 +#define TIMPANI_PA_AUXO_EARPA_CTL_EARPA_MASTER_BIAS_CUR_V_5_0UA 0x3 + +#define TIMPANI_PA_AUXO_EARPA_CTL_EARPA_VCM_SOURCE_S 0 +#define TIMPANI_PA_AUXO_EARPA_CTL_EARPA_VCM_SOURCE_M 0x1 +#define TIMPANI_PA_AUXO_EARPA_CTL_EARPA_VCM_SOURCE_BG 0x1 +#define TIMPANI_PA_AUXO_EARPA_CTL_EARPA_VCM_SOURCE_LOCAL_VCM 0x0 + + +/* -- For PA_EARO_CTL */ +#define TIMPANI_A_PA_EARO_CTL (0x4F) +#define TIMPANI_PA_EARO_CTL_RWC "RW" +#define TIMPANI_PA_EARO_CTL_POR 0x0 +#define TIMPANI_PA_EARO_CTL_S 0 +#define TIMPANI_PA_EARO_CTL_M 0xFF + + +#define TIMPANI_PA_EARO_CTL_EARPA_STARTUP_S 7 +#define TIMPANI_PA_EARO_CTL_EARPA_STARTUP_M 0x80 +#define TIMPANI_PA_EARO_CTL_EARPA_STARTUP_NORMAL_OP 0x0 +#define TIMPANI_PA_EARO_CTL_EARPA_STARTUP_CONNECT_INPUTS_TO_GROUND 0x1 + +#define TIMPANI_PA_EARO_CTL_EARPA_BYPASS_INPUT_CM_S 6 +#define TIMPANI_PA_EARO_CTL_EARPA_BYPASS_INPUT_CM_M 0x40 +#define TIMPANI_PA_EARO_CTL_EARPA_BYPASS_INPUT_CM_NO_BYPASS 0x0 +#define TIMPANI_PA_EARO_CTL_EARPA_BYPASS_INPUT_CM_BYPASS 0x1 + +#define TIMPANI_PA_EARO_CTL_EARPA_NMOS_BIAS_CUR_S 3 +#define TIMPANI_PA_EARO_CTL_EARPA_NMOS_BIAS_CUR_M 0x38 +#define TIMPANI_PA_EARO_CTL_EARPA_NMOS_BIAS_CUR_V_213UA 0x0 +#define TIMPANI_PA_EARO_CTL_EARPA_NMOS_BIAS_CUR_V_280UA 0x1 +#define TIMPANI_PA_EARO_CTL_EARPA_NMOS_BIAS_CUR_V_408UA_1 0x2 +#define TIMPANI_PA_EARO_CTL_EARPA_NMOS_BIAS_CUR_V_780UA_1 0x3 +#define TIMPANI_PA_EARO_CTL_EARPA_NMOS_BIAS_CUR_V_408UA_2 0x4 +#define TIMPANI_PA_EARO_CTL_EARPA_NMOS_BIAS_CUR_V_530UA 0x5 +#define TIMPANI_PA_EARO_CTL_EARPA_NMOS_BIAS_CUR_V_780UA_2 0x6 +#define TIMPANI_PA_EARO_CTL_EARPA_NMOS_BIAS_CUR_V_1480UA 0x7 + +#define TIMPANI_PA_EARO_CTL_EARPA_PMOS_BIAS_CUR_S 0 +#define TIMPANI_PA_EARO_CTL_EARPA_PMOS_BIAS_CUR_M 0x7 +#define TIMPANI_PA_EARO_CTL_EARPA_PMOS_BIAS_CUR_V_213UA 0x0 +#define TIMPANI_PA_EARO_CTL_EARPA_PMOS_BIAS_CUR_V_280UA 0x1 +#define TIMPANI_PA_EARO_CTL_EARPA_PMOS_BIAS_CUR_V_408UA_1 0x2 +#define TIMPANI_PA_EARO_CTL_EARPA_PMOS_BIAS_CUR_V_780UA_1 0x3 +#define TIMPANI_PA_EARO_CTL_EARPA_PMOS_BIAS_CUR_V_408UA_2 0x4 +#define TIMPANI_PA_EARO_CTL_EARPA_PMOS_BIAS_CUR_V_530UA 0x5 +#define TIMPANI_PA_EARO_CTL_EARPA_PMOS_BIAS_CUR_V_780UA_2 0x6 +#define TIMPANI_PA_EARO_CTL_EARPA_PMOS_BIAS_CUR_V_1480UA 0x7 + + +/* -- For PA_MASTER_BIAS_CUR */ +#define TIMPANI_A_PA_MASTER_BIAS_CUR (0x50) +#define TIMPANI_PA_MASTER_BIAS_CUR_RWC "RW" +#define TIMPANI_PA_MASTER_BIAS_CUR_POR 0xea +#define TIMPANI_PA_MASTER_BIAS_CUR_S 0 +#define TIMPANI_PA_MASTER_BIAS_CUR_M 0xFF + + +#define TIMPANI_PA_MASTER_BIAS_CUR_RAMPGEN_MASTER_BIAS_CUR_S 7 +#define TIMPANI_PA_MASTER_BIAS_CUR_RAMPGEN_MASTER_BIAS_CUR_M 0x80 +#define TIMPANI_PA_MASTER_BIAS_CUR_RAMPGEN_MASTER_BIAS_CUR_V_2_5UA 0x1 +#define TIMPANI_PA_MASTER_BIAS_CUR_RAMPGEN_MASTER_BIAS_CUR_V_5UA 0x0 + +#define TIMPANI_PA_MASTER_BIAS_CUR_AUXPGA_BIAS_CUR_S 5 +#define TIMPANI_PA_MASTER_BIAS_CUR_AUXPGA_BIAS_CUR_M 0x60 +#define TIMPANI_PA_MASTER_BIAS_CUR_AUXPGA_BIAS_CUR_V_10UA 0x0 +#define TIMPANI_PA_MASTER_BIAS_CUR_AUXPGA_BIAS_CUR_V_7_5UA 0x1 +#define TIMPANI_PA_MASTER_BIAS_CUR_AUXPGA_BIAS_CUR_V_5_0UA 0x2 +#define TIMPANI_PA_MASTER_BIAS_CUR_AUXPGA_BIAS_CUR_V_2_5UA 0x3 + +#define TIMPANI_PA_MASTER_BIAS_CUR_HPH_VCM_BUFF_BIAS_CURR_S 3 +#define TIMPANI_PA_MASTER_BIAS_CUR_HPH_VCM_BUFF_BIAS_CURR_M 0x18 +#define TIMPANI_PA_MASTER_BIAS_CUR_HPH_VCM_BUFF_BIAS_CURR_V_6_25UA 0x0 +#define TIMPANI_PA_MASTER_BIAS_CUR_HPH_VCM_BUFF_BIAS_CURR_V_5_0UA 0x1 +#define TIMPANI_PA_MASTER_BIAS_CUR_HPH_VCM_BUFF_BIAS_CURR_V_3_75UA 0x2 +#define TIMPANI_PA_MASTER_BIAS_CUR_HPH_VCM_BUFF_BIAS_CURR_V_2_5UA 0x3 + +#define TIMPANI_PA_MASTER_BIAS_CUR_LINE_VCM_BUFF_BIAS_CURR_S 1 +#define TIMPANI_PA_MASTER_BIAS_CUR_LINE_VCM_BUFF_BIAS_CURR_M 0x6 +#define TIMPANI_PA_MASTER_BIAS_CUR_LINE_VCM_BUFF_BIAS_CURR_V_6_25UA 0x0 +#define TIMPANI_PA_MASTER_BIAS_CUR_LINE_VCM_BUFF_BIAS_CURR_V_5_0UA 0x1 +#define TIMPANI_PA_MASTER_BIAS_CUR_LINE_VCM_BUFF_BIAS_CURR_V_3_75UA 0x2 +#define TIMPANI_PA_MASTER_BIAS_CUR_LINE_VCM_BUFF_BIAS_CURR_V_2_5UA 0x3 + +#define TIMPANI_PA_MASTER_BIAS_CUR_RESERVED_S 0 +#define TIMPANI_PA_MASTER_BIAS_CUR_RESERVED_M 0x1 + + +/* -- For PA_CLASSD_SC_STATUS */ +#define TIMPANI_A_PA_CLASSD_SC_STATUS (0x51) +#define TIMPANI_PA_CLASSD_SC_STATUS_RWC "R" +#define TIMPANI_PA_CLASSD_SC_STATUS_POR 0 +#define TIMPANI_PA_CLASSD_SC_STATUS_S 0 +#define TIMPANI_PA_CLASSD_SC_STATUS_M 0xFF + + +#define TIMPANI_PA_CLASSD_SC_STATUS_CLASSD_L_SC_DET_S 7 +#define TIMPANI_PA_CLASSD_SC_STATUS_CLASSD_L_SC_DET_M 0x80 +#define TIMPANI_PA_CLASSD_SC_STATUS_CLASSD_L_SC_DET_NORMAL_OP 0x0 +#define TIMPANI_PA_CLASSD_SC_STATUS_CLASSD_L_SC_DET_SC_DET 0x1 + +#define TIMPANI_PA_CLASSD_SC_STATUS_CLASSD_L_PWR_STAGE_HI_Z_S 6 +#define TIMPANI_PA_CLASSD_SC_STATUS_CLASSD_L_PWR_STAGE_HI_Z_M 0x40 +#define TIMPANI_PA_CLASSD_SC_STATUS_CLASSD_L_PWR_STAGE_HI_Z_NORMAL_OP 0x0 +#define TIMPANI_PA_CLASSD_SC_STATUS_CLASSD_L_PWR_STAGE_HI_Z_POWER_STAGE_OFF 0x1 + +#define TIMPANI_PA_CLASSD_SC_STATUS_RESERVED_1_S 4 +#define TIMPANI_PA_CLASSD_SC_STATUS_RESERVED_1_M 0x30 + +#define TIMPANI_PA_CLASSD_SC_STATUS_CLASSD_R_SC_DET_S 3 +#define TIMPANI_PA_CLASSD_SC_STATUS_CLASSD_R_SC_DET_M 0x8 +#define TIMPANI_PA_CLASSD_SC_STATUS_CLASSD_R_SC_DET_NORMAL_OP 0x0 +#define TIMPANI_PA_CLASSD_SC_STATUS_CLASSD_R_SC_DET_SC_DET 0x1 + +#define TIMPANI_PA_CLASSD_SC_STATUS_CLASSD_R_PWR_STAGE_HI_Z_S 2 +#define TIMPANI_PA_CLASSD_SC_STATUS_CLASSD_R_PWR_STAGE_HI_Z_M 0x4 +#define TIMPANI_PA_CLASSD_SC_STATUS_CLASSD_R_PWR_STAGE_HI_Z_NORMAL_OP 0x0 +#define TIMPANI_PA_CLASSD_SC_STATUS_CLASSD_R_PWR_STAGE_HI_Z_POWER_STAGE_OFF 0x1 + +#define TIMPANI_PA_CLASSD_SC_STATUS_RESERVED_2_S 1 +#define TIMPANI_PA_CLASSD_SC_STATUS_RESERVED_2_M 0x2 + +#define TIMPANI_PA_CLASSD_SC_STATUS_RESERVED_S 0 +#define TIMPANI_PA_CLASSD_SC_STATUS_RESERVED_M 0x1 + + +/* -- For PA_HPH_SC_STATUS */ +#define TIMPANI_A_PA_HPH_SC_STATUS (0x52) +#define TIMPANI_PA_HPH_SC_STATUS_RWC "R" +#define TIMPANI_PA_HPH_SC_STATUS_POR 0 +#define TIMPANI_PA_HPH_SC_STATUS_S 0 +#define TIMPANI_PA_HPH_SC_STATUS_M 0xFF + + +#define TIMPANI_PA_HPH_SC_STATUS_HPH_L_SC_DET_S 7 +#define TIMPANI_PA_HPH_SC_STATUS_HPH_L_SC_DET_M 0x80 +#define TIMPANI_PA_HPH_SC_STATUS_HPH_L_SC_DET_NORMAL_OP 0x0 +#define TIMPANI_PA_HPH_SC_STATUS_HPH_L_SC_DET_SC_DET 0x1 + +#define TIMPANI_PA_HPH_SC_STATUS_RESERVED_1_S 4 +#define TIMPANI_PA_HPH_SC_STATUS_RESERVED_1_M 0x70 + +#define TIMPANI_PA_HPH_SC_STATUS_HPH_R_SC_DET_S 3 +#define TIMPANI_PA_HPH_SC_STATUS_HPH_R_SC_DET_M 0x8 +#define TIMPANI_PA_HPH_SC_STATUS_HPH_R_SC_DET_NORMAL_OP 0x0 +#define TIMPANI_PA_HPH_SC_STATUS_HPH_R_SC_DET_SC_DET 0x1 + +#define TIMPANI_PA_HPH_SC_STATUS_RESERVED_2_S 2 +#define TIMPANI_PA_HPH_SC_STATUS_RESERVED_2_M 0x4 + +#define TIMPANI_PA_HPH_SC_STATUS_RESERVED_S 0 +#define TIMPANI_PA_HPH_SC_STATUS_RESERVED_M 0x3 + + +/* -- For ATEST_EN */ +#define TIMPANI_A_ATEST_EN (0x53) +#define TIMPANI_ATEST_EN_RWC "RW" +#define TIMPANI_ATEST_EN_POR 0 +#define TIMPANI_ATEST_EN_S 0 +#define TIMPANI_ATEST_EN_M 0xFF + + +#define TIMPANI_ATEST_EN_ATEST_EN_S 7 +#define TIMPANI_ATEST_EN_ATEST_EN_M 0x80 +#define TIMPANI_ATEST_EN_ATEST_EN_DISABLE 0x0 +#define TIMPANI_ATEST_EN_ATEST_EN_ENABLE 0x1 + +#define TIMPANI_ATEST_EN_RESERVED_S 0 +#define TIMPANI_ATEST_EN_RESERVED_M 0x7F + + +/* -- For ATEST_TSHKADC */ +#define TIMPANI_A_ATEST_TSHKADC (0x54) +#define TIMPANI_ATEST_TSHKADC_RWC "RW" +#define TIMPANI_ATEST_TSHKADC_POR 0 +#define TIMPANI_ATEST_TSHKADC_S 0 +#define TIMPANI_ATEST_TSHKADC_M 0xFF + + +#define TIMPANI_ATEST_TSHKADC_RESERVED_S 4 +#define TIMPANI_ATEST_TSHKADC_RESERVED_M 0xF0 + +#define TIMPANI_ATEST_TSHKADC_ATEST_TSADC_AN_CONN_S 2 +#define TIMPANI_ATEST_TSHKADC_ATEST_TSADC_AN_CONN_M 0xC +#define TIMPANI_ATEST_TSHKADC_ATEST_TSADC_AN_CONN_NO_CONNECT 0x0 +#define TIMPANI_ATEST_TSHKADC_ATEST_TSADC_AN_CONN_MUX1 0x1 +#define TIMPANI_ATEST_TSHKADC_ATEST_TSADC_AN_CONN_MUX2 0x2 +#define TIMPANI_ATEST_TSHKADC_ATEST_TSADC_AN_CONN_MUX3 0x3 + +#define TIMPANI_ATEST_TSHKADC_ATEST_TSADC_DIG_CONN_S 0 +#define TIMPANI_ATEST_TSHKADC_ATEST_TSADC_DIG_CONN_M 0x3 +#define TIMPANI_ATEST_TSHKADC_ATEST_TSADC_DIG_CONN_NO_CONNECT 0x0 +#define TIMPANI_ATEST_TSHKADC_ATEST_TSADC_DIG_CONN_MUX1 0x1 +#define TIMPANI_ATEST_TSHKADC_ATEST_TSADC_DIG_CONN_MUX2 0x2 +#define TIMPANI_ATEST_TSHKADC_ATEST_TSADC_DIG_CONN_MUX3 0x3 + + +/* -- For ATEST_TXADC13 */ +#define TIMPANI_A_ATEST_TXADC13 (0x55) +#define TIMPANI_ATEST_TXADC13_RWC "RW" +#define TIMPANI_ATEST_TXADC13_POR 0 +#define TIMPANI_ATEST_TXADC13_S 0 +#define TIMPANI_ATEST_TXADC13_M 0xFF + + +#define TIMPANI_ATEST_TXADC13_RESERVED_S 7 +#define TIMPANI_ATEST_TXADC13_RESERVED_M 0x80 + +#define TIMPANI_ATEST_TXADC13_ATEST_SEL_L_S 6 +#define TIMPANI_ATEST_TXADC13_ATEST_SEL_L_M 0x40 +#define TIMPANI_ATEST_TXADC13_ATEST_SEL_L_TXADC1 0x0 +#define TIMPANI_ATEST_TXADC13_ATEST_SEL_L_TXADC3 0x1 + +#define TIMPANI_ATEST_TXADC13_ATEST1_TXADC13_CONN_S 3 +#define TIMPANI_ATEST_TXADC13_ATEST1_TXADC13_CONN_M 0x38 +#define TIMPANI_ATEST_TXADC13_ATEST1_TXADC13_CONN_NO_CONNECT 0x0 +#define TIMPANI_ATEST_TXADC13_ATEST1_TXADC13_CONN_ICMP1_TO_ATEST1 0x1 +#define TIMPANI_ATEST_TXADC13_ATEST1_TXADC13_CONN_IOTA2_TO_ATEST1 0x2 +#define TIMPANI_ATEST_TXADC13_ATEST1_TXADC13_CONN_IOTA1_TO_ATEST1 0x3 +#define TIMPANI_ATEST_TXADC13_ATEST1_TXADC13_CONN_VICM_TO_ATEST1 0x4 +#define TIMPANI_ATEST_TXADC13_ATEST1_TXADC13_CONN_VTH_P_TO_ATEST1 0x5 +#define TIMPANI_ATEST_TXADC13_ATEST1_TXADC13_CONN_VREFP_TO_ATEST1 0x6 + +#define TIMPANI_ATEST_TXADC13_ATEST2_TXADC13_CONN_S 0 +#define TIMPANI_ATEST_TXADC13_ATEST2_TXADC13_CONN_M 0x7 +#define TIMPANI_ATEST_TXADC13_ATEST2_TXADC13_CONN_NO_CONNECT 0x0 +#define TIMPANI_ATEST_TXADC13_ATEST2_TXADC13_CONN_IDACREF_TO_ATEST2 0x1 +#define TIMPANI_ATEST_TXADC13_ATEST2_TXADC13_CONN_IB_10U_TO_ATEST2 0x2 +#define TIMPANI_ATEST_TXADC13_ATEST2_TXADC13_CONN_VREFMID_TO_ATEST2 0x3 +#define TIMPANI_ATEST_TXADC13_ATEST2_TXADC13_CONN_VOCM_TO_ATEST2 0x4 +#define TIMPANI_ATEST_TXADC13_ATEST2_TXADC13_CONN_VTH_N_TO_ATEST2 0x5 +#define TIMPANI_ATEST_TXADC13_ATEST2_TXADC13_CONN_VREFN_TO_ATEST2 0x6 + + +/* -- For ATEST_TXADC24 */ +#define TIMPANI_A_ATEST_TXADC24 (0x56) +#define TIMPANI_ATEST_TXADC24_RWC "RW" +#define TIMPANI_ATEST_TXADC24_POR 0 +#define TIMPANI_ATEST_TXADC24_S 0 +#define TIMPANI_ATEST_TXADC24_M 0xFF + + +#define TIMPANI_ATEST_TXADC24_RESERVED_S 7 +#define TIMPANI_ATEST_TXADC24_RESERVED_M 0x80 + +#define TIMPANI_ATEST_TXADC24_ATEST_SEL_R_S 6 +#define TIMPANI_ATEST_TXADC24_ATEST_SEL_R_M 0x40 +#define TIMPANI_ATEST_TXADC24_ATEST_SEL_R_TXADC1 0x0 +#define TIMPANI_ATEST_TXADC24_ATEST_SEL_R_TXADC3 0x1 + +#define TIMPANI_ATEST_TXADC24_ATEST1_TXADC24_CONN_S 3 +#define TIMPANI_ATEST_TXADC24_ATEST1_TXADC24_CONN_M 0x38 +#define TIMPANI_ATEST_TXADC24_ATEST1_TXADC24_CONN_NO_CONNECT 0x0 +#define TIMPANI_ATEST_TXADC24_ATEST1_TXADC24_CONN_ICMP1_TO_ATEST1 0x1 +#define TIMPANI_ATEST_TXADC24_ATEST1_TXADC24_CONN_IOTA2_TO_ATEST1 0x2 +#define TIMPANI_ATEST_TXADC24_ATEST1_TXADC24_CONN_IOTA1_TO_ATEST1 0x3 +#define TIMPANI_ATEST_TXADC24_ATEST1_TXADC24_CONN_VICM_TO_ATEST1 0x4 +#define TIMPANI_ATEST_TXADC24_ATEST1_TXADC24_CONN_VTH_P_TO_ATEST1 0x5 +#define TIMPANI_ATEST_TXADC24_ATEST1_TXADC24_CONN_VREFP_TO_ATEST1 0x6 + +#define TIMPANI_ATEST_TXADC24_ATEST2_TXADC24_CONN_S 0 +#define TIMPANI_ATEST_TXADC24_ATEST2_TXADC24_CONN_M 0x7 +#define TIMPANI_ATEST_TXADC24_ATEST2_TXADC24_CONN_NO_CONNECT 0x0 +#define TIMPANI_ATEST_TXADC24_ATEST2_TXADC24_CONN_IDACREF_TO_ATEST2 0x1 +#define TIMPANI_ATEST_TXADC24_ATEST2_TXADC24_CONN_IB_10U_TO_ATEST2 0x2 +#define TIMPANI_ATEST_TXADC24_ATEST2_TXADC24_CONN_VREFMID_TO_ATEST2 0x3 +#define TIMPANI_ATEST_TXADC24_ATEST2_TXADC24_CONN_VOCM_TO_ATEST2 0x4 +#define TIMPANI_ATEST_TXADC24_ATEST2_TXADC24_CONN_VTH_N_TO_ATEST2 0x5 +#define TIMPANI_ATEST_TXADC24_ATEST2_TXADC24_CONN_VREFN_TO_ATEST2 0x6 + + +/* -- For ATEST_AUXPGA */ +#define TIMPANI_A_ATEST_AUXPGA (0x57) +#define TIMPANI_ATEST_AUXPGA_RWC "RW" +#define TIMPANI_ATEST_AUXPGA_POR 0 +#define TIMPANI_ATEST_AUXPGA_S 0 +#define TIMPANI_ATEST_AUXPGA_M 0xFF + + +#define TIMPANI_ATEST_AUXPGA_ATEST1_AUXPGA_INT_VCM_CONN_S 7 +#define TIMPANI_ATEST_AUXPGA_ATEST1_AUXPGA_INT_VCM_CONN_M 0x80 +#define TIMPANI_ATEST_AUXPGA_ATEST1_AUXPGA_INT_VCM_CONN_NO_CONNECT 0x0 +#define TIMPANI_ATEST_AUXPGA_ATEST1_AUXPGA_INT_VCM_CONN_CONNECT 0x1 + +#define TIMPANI_ATEST_AUXPGA_ATEST_AUXPGA_VCMI_VDD_CONN_S 6 +#define TIMPANI_ATEST_AUXPGA_ATEST_AUXPGA_VCMI_VDD_CONN_M 0x40 +#define TIMPANI_ATEST_AUXPGA_ATEST_AUXPGA_VCMI_VDD_CONN_NO_CONNECT 0x0 +#define TIMPANI_ATEST_AUXPGA_ATEST_AUXPGA_VCMI_VDD_CONN_CONNECT 0x1 + +#define TIMPANI_ATEST_AUXPGA_ATEST_AUXPGA_VCMO_R_L_CONN_S 5 +#define TIMPANI_ATEST_AUXPGA_ATEST_AUXPGA_VCMO_R_L_CONN_M 0x20 +#define TIMPANI_ATEST_AUXPGA_ATEST_AUXPGA_VCMO_R_L_CONN_NO_CONNECT 0x0 +#define TIMPANI_ATEST_AUXPGA_ATEST_AUXPGA_VCMO_R_L_CONN_CONNECT 0x1 + +#define TIMPANI_ATEST_AUXPGA_ATEST_AUXPGA_R_CONN_S 4 +#define TIMPANI_ATEST_AUXPGA_ATEST_AUXPGA_R_CONN_M 0x10 +#define TIMPANI_ATEST_AUXPGA_ATEST_AUXPGA_R_CONN_NO_CONNECT 0x0 +#define TIMPANI_ATEST_AUXPGA_ATEST_AUXPGA_R_CONN_CONNECT 0x1 + +#define TIMPANI_ATEST_AUXPGA_ATEST_AUXPGA_L_CONN_S 3 +#define TIMPANI_ATEST_AUXPGA_ATEST_AUXPGA_L_CONN_M 0x8 +#define TIMPANI_ATEST_AUXPGA_ATEST_AUXPGA_L_CONN_NO_CONNECT 0x0 +#define TIMPANI_ATEST_AUXPGA_ATEST_AUXPGA_L_CONN_CONNECT 0x1 + +#define TIMPANI_ATEST_AUXPGA_RESERVED_S 0 +#define TIMPANI_ATEST_AUXPGA_RESERVED_M 0x7 + + +/* -- For ATEST_CDAC */ +#define TIMPANI_A_ATEST_CDAC (0x58) +#define TIMPANI_ATEST_CDAC_RWC "RW" +#define TIMPANI_ATEST_CDAC_POR 0 +#define TIMPANI_ATEST_CDAC_S 0 +#define TIMPANI_ATEST_CDAC_M 0xFF + + +#define TIMPANI_ATEST_CDAC_ATEST_CDAC_DWA_IN_CONN_S 7 +#define TIMPANI_ATEST_CDAC_ATEST_CDAC_DWA_IN_CONN_M 0x80 +#define TIMPANI_ATEST_CDAC_ATEST_CDAC_DWA_IN_CONN_NO_CONNECT 0x0 +#define TIMPANI_ATEST_CDAC_ATEST_CDAC_DWA_IN_CONN_CONNECT 0x1 + +#define TIMPANI_ATEST_CDAC_ATEST_CDAC_DWA_OUT_CONN_S 6 +#define TIMPANI_ATEST_CDAC_ATEST_CDAC_DWA_OUT_CONN_M 0x40 +#define TIMPANI_ATEST_CDAC_ATEST_CDAC_DWA_OUT_CONN_NO_CONNECT 0x0 +#define TIMPANI_ATEST_CDAC_ATEST_CDAC_DWA_OUT_CONN_CONNECT 0x1 + +#define TIMPANI_ATEST_CDAC_ATEST_FILTER_L_OUT_CONN_S 5 +#define TIMPANI_ATEST_CDAC_ATEST_FILTER_L_OUT_CONN_M 0x20 +#define TIMPANI_ATEST_CDAC_ATEST_FILTER_L_OUT_CONN_NO_CONNECT 0x0 +#define TIMPANI_ATEST_CDAC_ATEST_FILTER_L_OUT_CONN_CONNECT 0x1 + +#define TIMPANI_ATEST_CDAC_ATEST_FILTER_R_OUT_CONN_S 4 +#define TIMPANI_ATEST_CDAC_ATEST_FILTER_R_OUT_CONN_M 0x10 +#define TIMPANI_ATEST_CDAC_ATEST_FILTER_R_OUT_CONN_NO_CONNECT 0x0 +#define TIMPANI_ATEST_CDAC_ATEST_FILTER_R_OUT_CONN_CONNECT 0x1 + +#define TIMPANI_ATEST_CDAC_ATEST_CDAC_L_CONN_S 2 +#define TIMPANI_ATEST_CDAC_ATEST_CDAC_L_CONN_M 0xC +#define TIMPANI_ATEST_CDAC_ATEST_CDAC_L_CONN_NO_CONNECT 0x0 +#define TIMPANI_ATEST_CDAC_ATEST_CDAC_L_CONN_TEST1 0x1 +#define TIMPANI_ATEST_CDAC_ATEST_CDAC_L_CONN_TEST2 0x2 +#define TIMPANI_ATEST_CDAC_ATEST_CDAC_L_CONN_TEST3 0x3 + +#define TIMPANI_ATEST_CDAC_ATEST_CDAC_R_CONN_S 0 +#define TIMPANI_ATEST_CDAC_ATEST_CDAC_R_CONN_M 0x3 +#define TIMPANI_ATEST_CDAC_ATEST_CDAC_R_CONN_NO_CONNECT 0x0 +#define TIMPANI_ATEST_CDAC_ATEST_CDAC_R_CONN_TEST1 0x1 +#define TIMPANI_ATEST_CDAC_ATEST_CDAC_R_CONN_TEST2 0x2 +#define TIMPANI_ATEST_CDAC_ATEST_CDAC_R_CONN_TEST3 0x3 + + +/* -- For ATEST_IDAC */ +#define TIMPANI_A_ATEST_IDAC (0x59) +#define TIMPANI_ATEST_IDAC_RWC "RW" +#define TIMPANI_ATEST_IDAC_POR 0 +#define TIMPANI_ATEST_IDAC_S 0 +#define TIMPANI_ATEST_IDAC_M 0xFF + + +#define TIMPANI_ATEST_IDAC_ATEST1_LR_CONN_S 7 +#define TIMPANI_ATEST_IDAC_ATEST1_LR_CONN_M 0x80 +#define TIMPANI_ATEST_IDAC_ATEST1_LR_CONN_RIGHT 0x1 +#define TIMPANI_ATEST_IDAC_ATEST1_LR_CONN_LEFT 0x0 + +#define TIMPANI_ATEST_IDAC_ATEST1_CONN_S 4 +#define TIMPANI_ATEST_IDAC_ATEST1_CONN_M 0x70 +#define TIMPANI_ATEST_IDAC_ATEST1_CONN_IDAC_NEG_OUT 0x7 +#define TIMPANI_ATEST_IDAC_ATEST1_CONN_CT_FILTER_POS_OUT 0x6 +#define TIMPANI_ATEST_IDAC_ATEST1_CONN_CT_FILTER_IBIAS 0x5 +#define TIMPANI_ATEST_IDAC_ATEST1_CONN_NO_CONNECT_1 0x4 +#define TIMPANI_ATEST_IDAC_ATEST1_CONN_NO_CONNECT_2 0x3 +#define TIMPANI_ATEST_IDAC_ATEST1_CONN_NO_CONNECT_3 0x2 +#define TIMPANI_ATEST_IDAC_ATEST1_CONN_NO_CONNECT_4 0x1 +#define TIMPANI_ATEST_IDAC_ATEST1_CONN_NO_CONNECT_5 0x0 + +#define TIMPANI_ATEST_IDAC_ATEST2_LR_CONN_S 3 +#define TIMPANI_ATEST_IDAC_ATEST2_LR_CONN_M 0x8 +#define TIMPANI_ATEST_IDAC_ATEST2_LR_CONN_RIGHT 0x1 +#define TIMPANI_ATEST_IDAC_ATEST2_LR_CONN_LEFT 0x0 + +#define TIMPANI_ATEST_IDAC_ATEST2_CONN_S 0 +#define TIMPANI_ATEST_IDAC_ATEST2_CONN_M 0x7 +#define TIMPANI_ATEST_IDAC_ATEST2_CONN_IDAC_POS_OUT 0x7 +#define TIMPANI_ATEST_IDAC_ATEST2_CONN_CT_FILTER_NEG_OUT 0x6 +#define TIMPANI_ATEST_IDAC_ATEST2_CONN_IDAC_IBIAS 0x5 +#define TIMPANI_ATEST_IDAC_ATEST2_CONN_NO_CONNECT_1 0x4 +#define TIMPANI_ATEST_IDAC_ATEST2_CONN_NO_CONNECT_2 0x3 +#define TIMPANI_ATEST_IDAC_ATEST2_CONN_NO_CONNECT_3 0x2 +#define TIMPANI_ATEST_IDAC_ATEST2_CONN_NO_CONNECT_4 0x1 +#define TIMPANI_ATEST_IDAC_ATEST2_CONN_NO_CONNECT_5 0x0 + + +/* -- For ATEST_PA1 */ +#define TIMPANI_A_ATEST_PA1 (0x5A) +#define TIMPANI_ATEST_PA1_RWC "RW" +#define TIMPANI_ATEST_PA1_POR 0 +#define TIMPANI_ATEST_PA1_S 0 +#define TIMPANI_ATEST_PA1_M 0xFF + + +#define TIMPANI_ATEST_PA1_ATEST_EARPA_FSV_NP_CONN_S 7 +#define TIMPANI_ATEST_PA1_ATEST_EARPA_FSV_NP_CONN_M 0x80 +#define TIMPANI_ATEST_PA1_ATEST_EARPA_FSV_NP_CONN_NO_CONNECT 0x0 +#define TIMPANI_ATEST_PA1_ATEST_EARPA_FSV_NP_CONN_EN 0x1 + +#define TIMPANI_ATEST_PA1_ATEST_EARPA_NCASC_NMIRR_CONN_S 6 +#define TIMPANI_ATEST_PA1_ATEST_EARPA_NCASC_NMIRR_CONN_M 0x40 +#define TIMPANI_ATEST_PA1_ATEST_EARPA_NCASC_NMIRR_CONN_NO_CONNECT 0x0 +#define TIMPANI_ATEST_PA1_ATEST_EARPA_NCASC_NMIRR_CONN_EN 0x1 + +#define TIMPANI_ATEST_PA1_ATEST_EARPA_NMIRR_PCASC_CONN_S 5 +#define TIMPANI_ATEST_PA1_ATEST_EARPA_NMIRR_PCASC_CONN_M 0x20 +#define TIMPANI_ATEST_PA1_ATEST_EARPA_NMIRR_PCASC_CONN_NO_CONNECT 0x0 +#define TIMPANI_ATEST_PA1_ATEST_EARPA_NMIRR_PCASC_CONN_EN 0x1 + +#define TIMPANI_ATEST_PA1_ATEST_EARPA_VCM_PTAIL1_CONN_S 4 +#define TIMPANI_ATEST_PA1_ATEST_EARPA_VCM_PTAIL1_CONN_M 0x10 +#define TIMPANI_ATEST_PA1_ATEST_EARPA_VCM_PTAIL1_CONN_NO_CONNECT 0x0 +#define TIMPANI_ATEST_PA1_ATEST_EARPA_VCM_PTAIL1_CONN_EN 0x1 + +#define TIMPANI_ATEST_PA1_ATEST_EARPA_IBTEST_VSS2P2_CONN_S 3 +#define TIMPANI_ATEST_PA1_ATEST_EARPA_IBTEST_VSS2P2_CONN_M 0x8 +#define TIMPANI_ATEST_PA1_ATEST_EARPA_IBTEST_VSS2P2_CONN_NO_CONNECT 0x0 +#define TIMPANI_ATEST_PA1_ATEST_EARPA_IBTEST_VSS2P2_CONN_EN 0x1 + +#define TIMPANI_ATEST_PA1_ATEST_EARPA_ITEST1_ITEST2_CONN_S 2 +#define TIMPANI_ATEST_PA1_ATEST_EARPA_ITEST1_ITEST2_CONN_M 0x4 +#define TIMPANI_ATEST_PA1_ATEST_EARPA_ITEST1_ITEST2_CONN_NO_CONNECT 0x0 +#define TIMPANI_ATEST_PA1_ATEST_EARPA_ITEST1_ITEST2_CONN_EN 0x1 + +#define TIMPANI_ATEST_PA1_ATEST_CLASSD_CLK_GATING_S 1 +#define TIMPANI_ATEST_PA1_ATEST_CLASSD_CLK_GATING_M 0x2 +#define TIMPANI_ATEST_PA1_ATEST_CLASSD_CLK_GATING_PASS 0x0 +#define TIMPANI_ATEST_PA1_ATEST_CLASSD_CLK_GATING_GATE 0x1 + +#define TIMPANI_ATEST_PA1_ATEST2_HPH_VCM_CONN_S 0 +#define TIMPANI_ATEST_PA1_ATEST2_HPH_VCM_CONN_M 0x1 +#define TIMPANI_ATEST_PA1_ATEST2_HPH_VCM_CONN_NO_CONNECT 0x0 +#define TIMPANI_ATEST_PA1_ATEST2_HPH_VCM_CONN_CONNECT 0x1 + + +/* -- For ATEST_CLASSD */ +#define TIMPANI_A_ATEST_CLASSD (0x5B) +#define TIMPANI_ATEST_CLASSD_RWC "RW" +#define TIMPANI_ATEST_CLASSD_POR 0 +#define TIMPANI_ATEST_CLASSD_S 0 +#define TIMPANI_ATEST_CLASSD_M 0xFF + + +#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_S 4 +#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_M 0xF0 +#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_NO_CONNECT_1 0x0 +#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_L_SC_OCP 0x1 +#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_L_CDAC_CLK 0x2 +#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_L_POS_CDAC 0x3 +#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_L_BREAK_BEFORE_MAKE_OUT_CP 0x4 +#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_L_COMP_OUT 0x5 +#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_L_INT2_POS_OUT 0x6 +#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_L_INT1_POS_OUT 0x7 +#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_NO_CONNECT_2 0x8 +#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_R_SC_OCP_SIGNAL 0x9 +#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_R_CDAC_CLK 0xA +#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_R_POS_CDAC 0xB +#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_R_BREAK_BEFORE_MAKE_OUT_CP 0xC +#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_R_COMP_OUT 0xD +#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_R_INT2_POS_OUT 0xE +#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_R_INT1_POS_OUT 0xF + +#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_S 0 +#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_M 0xF +#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_NO_CONNECT_1 0x0 +#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_L_HI_Z_OCP 0x1 +#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_L_OCP_CLOCK 0x2 +#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_L_NEG_CDAC 0x3 +#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_L_BREAK_BEFORE_MAKE_OUT_CN 0x4 +#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_L_CM_BUFF_OUT 0x5 +#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_L_INT2_NEG_OUT 0x6 +#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_L_INT1_NEG_OUT 0x7 +#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_NO_CONNECT_2 0x8 +#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_R_HI_Z_OCP 0x9 +#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_R_OCP_CLOCK 0xA +#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_R_NEGATIVE_CDAC 0xB +#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_R_BREAK_BEFORE_MAKE_OUT_CN 0xC +#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_R_CM_BUFF_OUT 0xD +#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_R_INTR2_NEG_OUT 0xE +#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_R_INT1_NEG_OUT 0xF + + +/* -- For ATEST_LINEO_AUXO */ +#define TIMPANI_A_ATEST_LINEO_AUXO (0x5C) +#define TIMPANI_ATEST_LINEO_AUXO_RWC "RW" +#define TIMPANI_ATEST_LINEO_AUXO_POR 0 +#define TIMPANI_ATEST_LINEO_AUXO_S 0 +#define TIMPANI_ATEST_LINEO_AUXO_M 0xFF + + +#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_AUXO_EN_S 7 +#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_AUXO_EN_M 0x80 +#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_AUXO_EN_DISABLE 0x0 +#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_AUXO_EN_ENABLE 0x1 + +#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_AUXO_VCM_CONN_S 6 +#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_AUXO_VCM_CONN_M 0x40 +#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_AUXO_VCM_CONN_NO_CONNECT 0x0 +#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_AUXO_VCM_CONN_CONNECT 0x1 + +#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_L_NREFIN_STG1OP_CONN_S 5 +#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_L_NREFIN_STG1OP_CONN_M 0x20 +#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_L_NREFIN_STG1OP_CONN_NO_CONNECT 0x0 +#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_L_NREFIN_STG1OP_CONN_EN 0x1 + +#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_L_NMOS_PMOS_CONN_S 4 +#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_L_NMOS_PMOS_CONN_M 0x10 +#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_L_NMOS_PMOS_CONN_NO_CONNECT 0x0 +#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_L_NMOS_PMOS_CONN_EN 01 + +#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_R_NREFIN_STG1OP_CONN_S 3 +#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_R_NREFIN_STG1OP_CONN_M 0x8 +#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_R_NREFIN_STG1OP_CONN_NO_CONNECT 0x0 +#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_R_NREFIN_STG1OP_CONN_EN 01 + +#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_R_NMOS_PMOS_CONN_S 2 +#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_R_NMOS_PMOS_CONN_M 0x4 +#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_R_NMOS_PMOS_CONN_DISABLE 0x0 +#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_R_NMOS_PMOS_CONN_EN 0x1 + +#define TIMPANI_ATEST_LINEO_AUXO_ATEST_AUXO_NREFIN_STG1OP_CONN_S 1 +#define TIMPANI_ATEST_LINEO_AUXO_ATEST_AUXO_NREFIN_STG1OP_CONN_M 0x2 +#define TIMPANI_ATEST_LINEO_AUXO_ATEST_AUXO_NREFIN_STG1OP_CONN_DISABLE 0x0 +#define TIMPANI_ATEST_LINEO_AUXO_ATEST_AUXO_NREFIN_STG1OP_CONN_EN 0x1 + +#define TIMPANI_ATEST_LINEO_AUXO_ATEST_AUXO_NMOS_PMOS_CONN_S 0 +#define TIMPANI_ATEST_LINEO_AUXO_ATEST_AUXO_NMOS_PMOS_CONN_M 0x1 +#define TIMPANI_ATEST_LINEO_AUXO_ATEST_AUXO_NMOS_PMOS_CONN_DISABLE 0x0 +#define TIMPANI_ATEST_LINEO_AUXO_ATEST_AUXO_NMOS_PMOS_CONN_EN 0x1 + + +/* -- For CDC_RESET_CTL */ +#define TIMPANI_A_CDC_RESET_CTL (0x80) +#define TIMPANI_CDC_RESET_CTL_RWC "RW" +#define TIMPANI_CDC_RESET_CTL_POR 0 +#define TIMPANI_CDC_RESET_CTL_S 0 +#define TIMPANI_CDC_RESET_CTL_M 0x7F + + +#define TIMPANI_CDC_RESET_CTL_ARB_SOFT_RESET_S 6 +#define TIMPANI_CDC_RESET_CTL_ARB_SOFT_RESET_M 0x40 + +#define TIMPANI_CDC_RESET_CTL_TX2_SOFT_RESET_R_S 5 +#define TIMPANI_CDC_RESET_CTL_TX2_SOFT_RESET_R_M 0x20 + +#define TIMPANI_CDC_RESET_CTL_TX2_SOFT_RESET_L_S 4 +#define TIMPANI_CDC_RESET_CTL_TX2_SOFT_RESET_L_M 0x10 + +#define TIMPANI_CDC_RESET_CTL_RX2_SOFT_RESET_S 3 +#define TIMPANI_CDC_RESET_CTL_RX2_SOFT_RESET_M 0x8 + +#define TIMPANI_CDC_RESET_CTL_TX1_SOFT_RESET_R_S 2 +#define TIMPANI_CDC_RESET_CTL_TX1_SOFT_RESET_R_M 0x4 + +#define TIMPANI_CDC_RESET_CTL_RX1_SOFT_RESET_S 1 +#define TIMPANI_CDC_RESET_CTL_RX1_SOFT_RESET_M 0x2 + +#define TIMPANI_CDC_RESET_CTL_TX1_SOFT_RESET_L_S 0 +#define TIMPANI_CDC_RESET_CTL_TX1_SOFT_RESET_L_M 0x1 + + +/* -- For CDC_RX1_CTL */ +#define TIMPANI_A_CDC_RX1_CTL (0x81) +#define TIMPANI_CDC_RX1_CTL_RWC "RW" +#define TIMPANI_CDC_RX1_CTL_POR 0xc +#define TIMPANI_CDC_RX1_CTL_S 0 +#define TIMPANI_CDC_RX1_CTL_M 0x3F + + +#define TIMPANI_CDC_RX1_CTL_SIDETONE_EN1_R_S 5 +#define TIMPANI_CDC_RX1_CTL_SIDETONE_EN1_R_M 0x20 + +#define TIMPANI_CDC_RX1_CTL_SIDETONE_EN1_L_S 4 +#define TIMPANI_CDC_RX1_CTL_SIDETONE_EN1_L_M 0x10 + +#define TIMPANI_CDC_RX1_CTL_RX1_RATE_S 2 +#define TIMPANI_CDC_RX1_CTL_RX1_RATE_M 0xC +#define TIMPANI_CDC_RX1_CTL_RX1_RATE_OSR_256 0x3 +#define TIMPANI_CDC_RX1_CTL_RX1_RATE_OSR_128 0x1 +#define TIMPANI_CDC_RX1_CTL_RX1_RATE_OSR_64 0x0 + +#define TIMPANI_CDC_RX1_CTL_RX1_I2S_RATE_S 1 +#define TIMPANI_CDC_RX1_CTL_RX1_I2S_RATE_M 0x2 +#define TIMPANI_CDC_RX1_CTL_RX1_I2S_RATE_BR_32 0x1 +#define TIMPANI_CDC_RX1_CTL_RX1_I2S_RATE_BR_64 0x0 + +#define TIMPANI_CDC_RX1_CTL_RX1_I2S_MODE_S 0 +#define TIMPANI_CDC_RX1_CTL_RX1_I2S_MODE_M 0x1 +#define TIMPANI_CDC_RX1_CTL_RX1_I2S_MODE_MASTER 0x1 +#define TIMPANI_CDC_RX1_CTL_RX1_I2S_MODE_SLAVE 0x0 + + +/* -- For CDC_TX_I2S_CTL */ +#define TIMPANI_A_CDC_TX_I2S_CTL (0x82) +#define TIMPANI_CDC_TX_I2S_CTL_RWC "RW" +#define TIMPANI_CDC_TX_I2S_CTL_POR 0xc +#define TIMPANI_CDC_TX_I2S_CTL_S 0 +#define TIMPANI_CDC_TX_I2S_CTL_M 0x3F + + +#define TIMPANI_CDC_TX_I2S_CTL_TX2_I2S_SD_OE_S 5 +#define TIMPANI_CDC_TX_I2S_CTL_TX2_I2S_SD_OE_M 0x20 + +#define TIMPANI_CDC_TX_I2S_CTL_TX1_I2S_SD_OE_S 4 +#define TIMPANI_CDC_TX_I2S_CTL_TX1_I2S_SD_OE_M 0x10 + +#define TIMPANI_CDC_TX_I2S_CTL_TX_RATE_S 2 +#define TIMPANI_CDC_TX_I2S_CTL_TX_RATE_M 0xC +#define TIMPANI_CDC_TX_I2S_CTL_TX_RATE_OSR_256 0x3 +#define TIMPANI_CDC_TX_I2S_CTL_TX_RATE_OSR_128 0x1 +#define TIMPANI_CDC_TX_I2S_CTL_TX_RATE_OSR_64 0x0 + +#define TIMPANI_CDC_TX_I2S_CTL_TX_I2S_RATE_S 1 +#define TIMPANI_CDC_TX_I2S_CTL_TX_I2S_RATE_M 0x2 +#define TIMPANI_CDC_TX_I2S_CTL_TX_I2S_RATE_BR_32 0x1 +#define TIMPANI_CDC_TX_I2S_CTL_TX_I2S_RATE_BR_64 0x0 + +#define TIMPANI_CDC_TX_I2S_CTL_TX_I2S_MODE_S 0 +#define TIMPANI_CDC_TX_I2S_CTL_TX_I2S_MODE_M 0x1 +#define TIMPANI_CDC_TX_I2S_CTL_TX_I2S_MODE_MASTER 0x1 +#define TIMPANI_CDC_TX_I2S_CTL_TX_I2S_MODE_SLAVE 0x0 + + +/* -- For CDC_CH_CTL */ +#define TIMPANI_A_CDC_CH_CTL (0x83) +#define TIMPANI_CDC_CH_CTL_RWC "RW" +#define TIMPANI_CDC_CH_CTL_POR 0 +#define TIMPANI_CDC_CH_CTL_S 0 +#define TIMPANI_CDC_CH_CTL_M 0xFF + + +#define TIMPANI_CDC_CH_CTL_TX2_EN_R_S 7 +#define TIMPANI_CDC_CH_CTL_TX2_EN_R_M 0x80 + +#define TIMPANI_CDC_CH_CTL_TX2_EN_L_S 6 +#define TIMPANI_CDC_CH_CTL_TX2_EN_L_M 0x40 + +#define TIMPANI_CDC_CH_CTL_RX2_EN_R_S 5 +#define TIMPANI_CDC_CH_CTL_RX2_EN_R_M 0x20 + +#define TIMPANI_CDC_CH_CTL_RX2_EN_L_S 4 +#define TIMPANI_CDC_CH_CTL_RX2_EN_L_M 0x10 + +#define TIMPANI_CDC_CH_CTL_TX1_EN_R_S 3 +#define TIMPANI_CDC_CH_CTL_TX1_EN_R_M 0x8 + +#define TIMPANI_CDC_CH_CTL_TX1_EN_L_S 2 +#define TIMPANI_CDC_CH_CTL_TX1_EN_L_M 0x4 + +#define TIMPANI_CDC_CH_CTL_RX1_EN_R_S 1 +#define TIMPANI_CDC_CH_CTL_RX1_EN_R_M 0x2 + +#define TIMPANI_CDC_CH_CTL_RX1_EN_L_S 0 +#define TIMPANI_CDC_CH_CTL_RX1_EN_L_M 0x1 + + +/* -- For CDC_RX1LG */ +#define TIMPANI_A_CDC_RX1LG (0x84) +#define TIMPANI_CDC_RX1LG_RWC "RW" +#define TIMPANI_CDC_RX1LG_POR 0xac +#define TIMPANI_CDC_RX1LG_S 0 +#define TIMPANI_CDC_RX1LG_M 0xFF + + +#define TIMPANI_CDC_RX1LG_GAIN_S 0 +#define TIMPANI_CDC_RX1LG_GAIN_M 0xFF + + +/* -- For CDC_RX1RG */ +#define TIMPANI_A_CDC_RX1RG (0x85) +#define TIMPANI_CDC_RX1RG_RWC "RW" +#define TIMPANI_CDC_RX1RG_POR 0xac +#define TIMPANI_CDC_RX1RG_S 0 +#define TIMPANI_CDC_RX1RG_M 0xFF + + +#define TIMPANI_CDC_RX1RG_GAIN_S 0 +#define TIMPANI_CDC_RX1RG_GAIN_M 0xFF + + +/* -- For CDC_TX1LG */ +#define TIMPANI_A_CDC_TX1LG (0x86) +#define TIMPANI_CDC_TX1LG_RWC "RW" +#define TIMPANI_CDC_TX1LG_POR 0xac +#define TIMPANI_CDC_TX1LG_S 0 +#define TIMPANI_CDC_TX1LG_M 0xFF + + +#define TIMPANI_CDC_TX1LG_GAIN_S 0 +#define TIMPANI_CDC_TX1LG_GAIN_M 0xFF + + +/* -- For CDC_TX1RG */ +#define TIMPANI_A_CDC_TX1RG (0x87) +#define TIMPANI_CDC_TX1RG_RWC "RW" +#define TIMPANI_CDC_TX1RG_POR 0xac +#define TIMPANI_CDC_TX1RG_S 0 +#define TIMPANI_CDC_TX1RG_M 0xFF + + +#define TIMPANI_CDC_TX1RG_GAIN_S 0 +#define TIMPANI_CDC_TX1RG_GAIN_M 0xFF + + +/* -- For CDC_RX_PGA_TIMER */ +#define TIMPANI_A_CDC_RX_PGA_TIMER (0x88) +#define TIMPANI_CDC_RX_PGA_TIMER_RWC "RW" +#define TIMPANI_CDC_RX_PGA_TIMER_POR 0xff +#define TIMPANI_CDC_RX_PGA_TIMER_S 0 +#define TIMPANI_CDC_RX_PGA_TIMER_M 0xFF + + +#define TIMPANI_CDC_RX_PGA_TIMER_TIMER_VAL_S 0 +#define TIMPANI_CDC_RX_PGA_TIMER_TIMER_VAL_M 0xFF + + +/* -- For CDC_TX_PGA_TIMER */ +#define TIMPANI_A_CDC_TX_PGA_TIMER (0x89) +#define TIMPANI_CDC_TX_PGA_TIMER_RWC "RW" +#define TIMPANI_CDC_TX_PGA_TIMER_POR 0xff +#define TIMPANI_CDC_TX_PGA_TIMER_S 0 +#define TIMPANI_CDC_TX_PGA_TIMER_M 0xFF + + +#define TIMPANI_CDC_TX_PGA_TIMER_TIMER_VAL_S 0 +#define TIMPANI_CDC_TX_PGA_TIMER_TIMER_VAL_M 0xFF + + +/* -- For CDC_GCTL1 */ +#define TIMPANI_A_CDC_GCTL1 (0x8A) +#define TIMPANI_CDC_GCTL1_RWC "RW" +#define TIMPANI_CDC_GCTL1_POR 0x33 +#define TIMPANI_CDC_GCTL1_S 0 +#define TIMPANI_CDC_GCTL1_M 0xFF + + +#define TIMPANI_CDC_GCTL1_TX1_PGA_UPDATE_R_S 7 +#define TIMPANI_CDC_GCTL1_TX1_PGA_UPDATE_R_M 0x80 + +#define TIMPANI_CDC_GCTL1_TX1_PGA_UPDATE_L_S 6 +#define TIMPANI_CDC_GCTL1_TX1_PGA_UPDATE_L_M 0x40 + +#define TIMPANI_CDC_GCTL1_TX1_PGA_MUTE_EN_R_S 5 +#define TIMPANI_CDC_GCTL1_TX1_PGA_MUTE_EN_R_M 0x20 + +#define TIMPANI_CDC_GCTL1_TX1_PGA_MUTE_EN_L_S 4 +#define TIMPANI_CDC_GCTL1_TX1_PGA_MUTE_EN_L_M 0x10 + +#define TIMPANI_CDC_GCTL1_RX1_PGA_UPDATE_R_S 3 +#define TIMPANI_CDC_GCTL1_RX1_PGA_UPDATE_R_M 0x8 + +#define TIMPANI_CDC_GCTL1_RX1_PGA_UPDATE_L_S 2 +#define TIMPANI_CDC_GCTL1_RX1_PGA_UPDATE_L_M 0x4 + +#define TIMPANI_CDC_GCTL1_RX1_PGA_MUTE_EN_R_S 1 +#define TIMPANI_CDC_GCTL1_RX1_PGA_MUTE_EN_R_M 0x2 + +#define TIMPANI_CDC_GCTL1_RX1_PGA_MUTE_EN_L_S 0 +#define TIMPANI_CDC_GCTL1_RX1_PGA_MUTE_EN_L_M 0x1 + + +/* -- For CDC_TX1L_STG */ +#define TIMPANI_A_CDC_TX1L_STG (0x8B) +#define TIMPANI_CDC_TX1L_STG_RWC "RW" +#define TIMPANI_CDC_TX1L_STG_POR 0xac +#define TIMPANI_CDC_TX1L_STG_S 0 +#define TIMPANI_CDC_TX1L_STG_M 0xFF + + +#define TIMPANI_CDC_TX1L_STG_GAIN_S 0 +#define TIMPANI_CDC_TX1L_STG_GAIN_M 0xFF + + +/* -- For CDC_ST_CTL */ +#define TIMPANI_A_CDC_ST_CTL (0x8C) +#define TIMPANI_CDC_ST_CTL_RWC "RW" +#define TIMPANI_CDC_ST_CTL_POR 0x55 +#define TIMPANI_CDC_ST_CTL_S 0 +#define TIMPANI_CDC_ST_CTL_M 0xFF + + +#define TIMPANI_CDC_ST_CTL_TX2_R_SIDETONE_UPDATE_S 7 +#define TIMPANI_CDC_ST_CTL_TX2_R_SIDETONE_UPDATE_M 0x80 + +#define TIMPANI_CDC_ST_CTL_TX2_R_SIDETONE_MUTE_EN_S 6 +#define TIMPANI_CDC_ST_CTL_TX2_R_SIDETONE_MUTE_EN_M 0x40 + +#define TIMPANI_CDC_ST_CTL_TX2_L_SIDETONE_UPDATE_S 5 +#define TIMPANI_CDC_ST_CTL_TX2_L_SIDETONE_UPDATE_M 0x20 + +#define TIMPANI_CDC_ST_CTL_TX2_L_SIDETONE_MUTE_EN_S 4 +#define TIMPANI_CDC_ST_CTL_TX2_L_SIDETONE_MUTE_EN_M 0x10 + +#define TIMPANI_CDC_ST_CTL_TX1_R_SIDETONE_UPDATE_S 3 +#define TIMPANI_CDC_ST_CTL_TX1_R_SIDETONE_UPDATE_M 0x8 + +#define TIMPANI_CDC_ST_CTL_TX1_R_SIDETONE_MUTE_EN_S 2 +#define TIMPANI_CDC_ST_CTL_TX1_R_SIDETONE_MUTE_EN_M 0x4 + +#define TIMPANI_CDC_ST_CTL_TX1_L_SIDETONE_UPDATE_S 1 +#define TIMPANI_CDC_ST_CTL_TX1_L_SIDETONE_UPDATE_M 0x2 + +#define TIMPANI_CDC_ST_CTL_TX1_L_SIDETONE_MUTE_EN_S 0 +#define TIMPANI_CDC_ST_CTL_TX1_L_SIDETONE_MUTE_EN_M 0x1 + + +/* -- For CDC_RX1L_DCOFFSET */ +#define TIMPANI_A_CDC_RX1L_DCOFFSET (0x8D) +#define TIMPANI_CDC_RX1L_DCOFFSET_RWC "RW" +#define TIMPANI_CDC_RX1L_DCOFFSET_POR 0 +#define TIMPANI_CDC_RX1L_DCOFFSET_S 0 +#define TIMPANI_CDC_RX1L_DCOFFSET_M 0xFF + + +#define TIMPANI_CDC_RX1L_DCOFFSET_OFFSET_S 0 +#define TIMPANI_CDC_RX1L_DCOFFSET_OFFSET_M 0xFF + + +/* -- For CDC_RX1R_DCOFFSET */ +#define TIMPANI_A_CDC_RX1R_DCOFFSET (0x8E) +#define TIMPANI_CDC_RX1R_DCOFFSET_RWC "RW" +#define TIMPANI_CDC_RX1R_DCOFFSET_POR 0 +#define TIMPANI_CDC_RX1R_DCOFFSET_S 0 +#define TIMPANI_CDC_RX1R_DCOFFSET_M 0xFF + + +#define TIMPANI_CDC_RX1R_DCOFFSET_OFFSET_S 0 +#define TIMPANI_CDC_RX1R_DCOFFSET_OFFSET_M 0xFF + + +/* -- For CDC_BYPASS_CTL1 */ +#define TIMPANI_A_CDC_BYPASS_CTL1 (0x8F) +#define TIMPANI_CDC_BYPASS_CTL1_RWC "RW" +#define TIMPANI_CDC_BYPASS_CTL1_POR 0x2 +#define TIMPANI_CDC_BYPASS_CTL1_S 0 +#define TIMPANI_CDC_BYPASS_CTL1_M 0xF + + +#define TIMPANI_CDC_BYPASS_CTL1_DITHER_BP_S 3 +#define TIMPANI_CDC_BYPASS_CTL1_DITHER_BP_M 0x8 + +#define TIMPANI_CDC_BYPASS_CTL1_DITHER_SHAPE_SEL_S 2 +#define TIMPANI_CDC_BYPASS_CTL1_DITHER_SHAPE_SEL_M 0x4 + +#define TIMPANI_CDC_BYPASS_CTL1_DITHER_DLY_SEL_S 1 +#define TIMPANI_CDC_BYPASS_CTL1_DITHER_DLY_SEL_M 0x2 + +#define TIMPANI_CDC_BYPASS_CTL1_RX1_HPF_BP_S 0 +#define TIMPANI_CDC_BYPASS_CTL1_RX1_HPF_BP_M 0x1 + + +/* -- For CDC_PDM_CONFIG */ +#define TIMPANI_A_CDC_PDM_CONFIG (0x90) +#define TIMPANI_CDC_PDM_CONFIG_RWC "RW" +#define TIMPANI_CDC_PDM_CONFIG_POR 0 +#define TIMPANI_CDC_PDM_CONFIG_S 0 +#define TIMPANI_CDC_PDM_CONFIG_M 0xF + + +#define TIMPANI_CDC_PDM_CONFIG_PDM_SEL_S 0 +#define TIMPANI_CDC_PDM_CONFIG_PDM_SEL_M 0xF + + +/* -- For CDC_TESTMODE1 */ +#define TIMPANI_A_CDC_TESTMODE1 (0x91) +#define TIMPANI_CDC_TESTMODE1_RWC "RW" +#define TIMPANI_CDC_TESTMODE1_POR 0 +#define TIMPANI_CDC_TESTMODE1_S 0 +#define TIMPANI_CDC_TESTMODE1_M 0x3F + + +#define TIMPANI_CDC_TESTMODE1_COMP_I2C_TEST_EN_S 5 +#define TIMPANI_CDC_TESTMODE1_COMP_I2C_TEST_EN_M 0x20 + +#define TIMPANI_CDC_TESTMODE1_RX1_TEST_EN_R_S 4 +#define TIMPANI_CDC_TESTMODE1_RX1_TEST_EN_R_M 0x10 + +#define TIMPANI_CDC_TESTMODE1_RX1_TEST_EN_L_S 3 +#define TIMPANI_CDC_TESTMODE1_RX1_TEST_EN_L_M 0x8 + +#define TIMPANI_CDC_TESTMODE1_TX1_TEST_EN_R_S 2 +#define TIMPANI_CDC_TESTMODE1_TX1_TEST_EN_R_M 0x4 + +#define TIMPANI_CDC_TESTMODE1_TX1_TEST_EN_L_S 1 +#define TIMPANI_CDC_TESTMODE1_TX1_TEST_EN_L_M 0x2 + +#define TIMPANI_CDC_TESTMODE1_A_LOOPBACK_EN1_S 0 +#define TIMPANI_CDC_TESTMODE1_A_LOOPBACK_EN1_M 0x1 + + +/* -- For CDC_DMIC_CLK_CTL */ +#define TIMPANI_A_CDC_DMIC_CLK_CTL (0x92) +#define TIMPANI_CDC_DMIC_CLK_CTL_RWC "RW" +#define TIMPANI_CDC_DMIC_CLK_CTL_POR 0 +#define TIMPANI_CDC_DMIC_CLK_CTL_S 0 +#define TIMPANI_CDC_DMIC_CLK_CTL_M 0x3F + + +#define TIMPANI_CDC_DMIC_CLK_CTL_DMIC_MCLK_DIV_SEL_S 3 +#define TIMPANI_CDC_DMIC_CLK_CTL_DMIC_MCLK_DIV_SEL_M 0x38 +#define TIMPANI_CDC_DMIC_CLK_CTL_DMIC_MCLK_DIV_SEL_DIV_6 0x4 +#define TIMPANI_CDC_DMIC_CLK_CTL_DMIC_MCLK_DIV_SEL_DIV_4 0x3 +#define TIMPANI_CDC_DMIC_CLK_CTL_DMIC_MCLK_DIV_SEL_DIV_3 0x2 +#define TIMPANI_CDC_DMIC_CLK_CTL_DMIC_MCLK_DIV_SEL_DIV_2 0x1 +#define TIMPANI_CDC_DMIC_CLK_CTL_DMIC_MCLK_DIV_SEL_DIV_1 0x0 + +#define TIMPANI_CDC_DMIC_CLK_CTL_DMIC_MCLK_SEL_S 1 +#define TIMPANI_CDC_DMIC_CLK_CTL_DMIC_MCLK_SEL_M 0x6 +#define TIMPANI_CDC_DMIC_CLK_CTL_DMIC_MCLK_SEL_RX_MCLK2 0x2 +#define TIMPANI_CDC_DMIC_CLK_CTL_DMIC_MCLK_SEL_RX_MCLK1 0x1 +#define TIMPANI_CDC_DMIC_CLK_CTL_DMIC_MCLK_SEL_TX_MCLK 0x0 + +#define TIMPANI_CDC_DMIC_CLK_CTL_DMIC_CLK_EN_S 0 +#define TIMPANI_CDC_DMIC_CLK_CTL_DMIC_CLK_EN_M 0x1 + + +/* -- For CDC_ADC12_CLK_CTL */ +#define TIMPANI_A_CDC_ADC12_CLK_CTL (0x93) +#define TIMPANI_CDC_ADC12_CLK_CTL_RWC "RW" +#define TIMPANI_CDC_ADC12_CLK_CTL_POR 0 +#define TIMPANI_CDC_ADC12_CLK_CTL_S 0 +#define TIMPANI_CDC_ADC12_CLK_CTL_M 0xFF + + +#define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_SEL_S 6 +#define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_SEL_M 0xC0 +#define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_SEL_RX_MCLK2 0x2 +#define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_SEL_RX_MCLK1 0x1 +#define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_SEL_TX_MCLK 0x0 + +#define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_DIV_SEL_R_S 3 +#define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_DIV_SEL_R_M 0x38 +#define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_DIV_SEL_R_DIV_6 0x4 +#define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_DIV_SEL_R_DIV_4 0x3 +#define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_DIV_SEL_R_DIV_3 0x2 +#define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_DIV_SEL_R_DIV_2 0x1 +#define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_DIV_SEL_R_DIV_1 0x0 + +#define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_DIV_SEL_L_S 0 +#define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_DIV_SEL_L_M 0x7 +#define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_DIV_SEL_L_DIV_6 0x4 +#define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_DIV_SEL_L_DIV_4 0x3 +#define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_DIV_SEL_L_DIV_3 0x2 +#define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_DIV_SEL_L_DIV_2 0x1 +#define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_DIV_SEL_L_DIV_1 0x0 + + +/* -- For CDC_TX1_CTL */ +#define TIMPANI_A_CDC_TX1_CTL (0x94) +#define TIMPANI_CDC_TX1_CTL_RWC "RW" +#define TIMPANI_CDC_TX1_CTL_POR 0x1b +#define TIMPANI_CDC_TX1_CTL_S 0 +#define TIMPANI_CDC_TX1_CTL_M 0x3F + + +#define TIMPANI_CDC_TX1_CTL_TX1_DMIC_SEL_R_S 5 +#define TIMPANI_CDC_TX1_CTL_TX1_DMIC_SEL_R_M 0x20 + +#define TIMPANI_CDC_TX1_CTL_TX1_RATE_R_S 3 +#define TIMPANI_CDC_TX1_CTL_TX1_RATE_R_M 0x18 +#define TIMPANI_CDC_TX1_CTL_TX1_RATE_R_OSR_256 0x3 +#define TIMPANI_CDC_TX1_CTL_TX1_RATE_R_OSR_128 0x1 +#define TIMPANI_CDC_TX1_CTL_TX1_RATE_R_OSR_64 0x0 + +#define TIMPANI_CDC_TX1_CTL_TX1_DMIC_SEL_L_S 2 +#define TIMPANI_CDC_TX1_CTL_TX1_DMIC_SEL_L_M 0x4 + +#define TIMPANI_CDC_TX1_CTL_TX1_RATE_L_S 0 +#define TIMPANI_CDC_TX1_CTL_TX1_RATE_L_M 0x3 +#define TIMPANI_CDC_TX1_CTL_TX1_RATE_L_OSR_256 0x3 +#define TIMPANI_CDC_TX1_CTL_TX1_RATE_L_OSR_128 0x1 +#define TIMPANI_CDC_TX1_CTL_TX1_RATE_L_OSR_64 0x0 + + +/* -- For CDC_ADC34_CLK_CTL */ +#define TIMPANI_A_CDC_ADC34_CLK_CTL (0x95) +#define TIMPANI_CDC_ADC34_CLK_CTL_RWC "RW" +#define TIMPANI_CDC_ADC34_CLK_CTL_POR 0 +#define TIMPANI_CDC_ADC34_CLK_CTL_S 0 +#define TIMPANI_CDC_ADC34_CLK_CTL_M 0xFF + + +#define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_SEL_S 6 +#define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_SEL_M 0xC0 +#define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_SEL_RX_MCLK2 0x2 +#define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_SEL_RX_MCLK1 0x1 +#define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_SEL_TX_MCLK 0x0 + +#define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_DIV_SEL_R_S 3 +#define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_DIV_SEL_R_M 0x38 +#define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_DIV_SEL_R_DIV_6 0x4 +#define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_DIV_SEL_R_DIV_4 0x3 +#define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_DIV_SEL_R_DIV_3 0x2 +#define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_DIV_SEL_R_DIV_2 0x1 +#define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_DIV_SEL_R_DIV_1 0x0 + +#define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_DIV_SEL_L_S 0 +#define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_DIV_SEL_L_M 0x7 +#define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_DIV_SEL_L_DIV_6 0x4 +#define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_DIV_SEL_L_DIV_4 0x3 +#define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_DIV_SEL_L_DIV_3 0x2 +#define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_DIV_SEL_L_DIV_2 0x1 +#define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_DIV_SEL_L_DIV_1 0x0 + + +/* -- For CDC_TX2_CTL */ +#define TIMPANI_A_CDC_TX2_CTL (0x96) +#define TIMPANI_CDC_TX2_CTL_RWC "RW" +#define TIMPANI_CDC_TX2_CTL_POR 0x1b +#define TIMPANI_CDC_TX2_CTL_S 0 +#define TIMPANI_CDC_TX2_CTL_M 0x3F + + +#define TIMPANI_CDC_TX2_CTL_TX2_DMIC_SEL_R_S 5 +#define TIMPANI_CDC_TX2_CTL_TX2_DMIC_SEL_R_M 0x20 + +#define TIMPANI_CDC_TX2_CTL_TX2_RATE_R_S 3 +#define TIMPANI_CDC_TX2_CTL_TX2_RATE_R_M 0x18 +#define TIMPANI_CDC_TX2_CTL_TX2_RATE_R_OSR_256 0x3 +#define TIMPANI_CDC_TX2_CTL_TX2_RATE_R_OSR_128 0x1 +#define TIMPANI_CDC_TX2_CTL_TX2_RATE_R_OSR_64 0x0 + +#define TIMPANI_CDC_TX2_CTL_TX2_DMIC_SEL_L_S 2 +#define TIMPANI_CDC_TX2_CTL_TX2_DMIC_SEL_L_M 0x4 + +#define TIMPANI_CDC_TX2_CTL_TX2_RATE_L_S 0 +#define TIMPANI_CDC_TX2_CTL_TX2_RATE_L_M 0x3 +#define TIMPANI_CDC_TX2_CTL_TX2_RATE_L_OSR_256 0x3 +#define TIMPANI_CDC_TX2_CTL_TX2_RATE_L_OSR_128 0x1 +#define TIMPANI_CDC_TX2_CTL_TX2_RATE_L_OSR_64 0x0 + + +/* -- For CDC_RX1_CLK_CTL */ +#define TIMPANI_A_CDC_RX1_CLK_CTL (0x97) +#define TIMPANI_CDC_RX1_CLK_CTL_RWC "RW" +#define TIMPANI_CDC_RX1_CLK_CTL_POR 0x1 +#define TIMPANI_CDC_RX1_CLK_CTL_S 0 +#define TIMPANI_CDC_RX1_CLK_CTL_M 0x1F + + +#define TIMPANI_CDC_RX1_CLK_CTL_RX1_MCLK_DIV_SEL_S 2 +#define TIMPANI_CDC_RX1_CLK_CTL_RX1_MCLK_DIV_SEL_M 0x1C +#define TIMPANI_CDC_RX1_CLK_CTL_RX1_MCLK_DIV_SEL_DIV_6 0x4 +#define TIMPANI_CDC_RX1_CLK_CTL_RX1_MCLK_DIV_SEL_DIV_4 0x3 +#define TIMPANI_CDC_RX1_CLK_CTL_RX1_MCLK_DIV_SEL_DIV_3 0x2 +#define TIMPANI_CDC_RX1_CLK_CTL_RX1_MCLK_DIV_SEL_DIV_2 0x1 +#define TIMPANI_CDC_RX1_CLK_CTL_RX1_MCLK_DIV_SEL_DIV_1 0x0 + +#define TIMPANI_CDC_RX1_CLK_CTL_RX1_MCLK_SEL_S 0 +#define TIMPANI_CDC_RX1_CLK_CTL_RX1_MCLK_SEL_M 0x3 +#define TIMPANI_CDC_RX1_CLK_CTL_RX1_MCLK_SEL_RX_MCLK2 0x2 +#define TIMPANI_CDC_RX1_CLK_CTL_RX1_MCLK_SEL_RX_MCLK1 0x1 +#define TIMPANI_CDC_RX1_CLK_CTL_RX1_MCLK_SEL_TX_MCLK 0x0 + + +/* -- For CDC_RX2_CLK_CTL */ +#define TIMPANI_A_CDC_RX2_CLK_CTL (0x98) +#define TIMPANI_CDC_RX2_CLK_CTL_RWC "RW" +#define TIMPANI_CDC_RX2_CLK_CTL_POR 0x2 +#define TIMPANI_CDC_RX2_CLK_CTL_S 0 +#define TIMPANI_CDC_RX2_CLK_CTL_M 0x1F + + +#define TIMPANI_CDC_RX2_CLK_CTL_RX2_MCLK_DIV_SEL_S 2 +#define TIMPANI_CDC_RX2_CLK_CTL_RX2_MCLK_DIV_SEL_M 0x1C +#define TIMPANI_CDC_RX2_CLK_CTL_RX2_MCLK_DIV_SEL_DIV_6 0x4 +#define TIMPANI_CDC_RX2_CLK_CTL_RX2_MCLK_DIV_SEL_DIV_4 0x3 +#define TIMPANI_CDC_RX2_CLK_CTL_RX2_MCLK_DIV_SEL_DIV_3 0x2 +#define TIMPANI_CDC_RX2_CLK_CTL_RX2_MCLK_DIV_SEL_DIV_2 0x1 +#define TIMPANI_CDC_RX2_CLK_CTL_RX2_MCLK_DIV_SEL_DIV_1 0x0 + +#define TIMPANI_CDC_RX2_CLK_CTL_RX2_MCLK_SEL_S 0 +#define TIMPANI_CDC_RX2_CLK_CTL_RX2_MCLK_SEL_M 0x3 +#define TIMPANI_CDC_RX2_CLK_CTL_RX2_MCLK_SEL_RX_MCLK2 0x2 +#define TIMPANI_CDC_RX2_CLK_CTL_RX2_MCLK_SEL_RX_MCLK1 0x1 +#define TIMPANI_CDC_RX2_CLK_CTL_RX2_MCLK_SEL_TX_MCLK 0x0 + + +/* -- For CDC_DEC_ADC_SEL */ +#define TIMPANI_A_CDC_DEC_ADC_SEL (0x99) +#define TIMPANI_CDC_DEC_ADC_SEL_RWC "RW" +#define TIMPANI_CDC_DEC_ADC_SEL_POR 0 +#define TIMPANI_CDC_DEC_ADC_SEL_S 0 +#define TIMPANI_CDC_DEC_ADC_SEL_M 0xFF + + +#define TIMPANI_CDC_DEC_ADC_SEL_TX2_ADC_SEL_R_S 6 +#define TIMPANI_CDC_DEC_ADC_SEL_TX2_ADC_SEL_R_M 0xC0 +#define TIMPANI_CDC_DEC_ADC_SEL_TX2_ADC_SEL_R_ADC4 0x3 +#define TIMPANI_CDC_DEC_ADC_SEL_TX2_ADC_SEL_R_ADC3 0x2 +#define TIMPANI_CDC_DEC_ADC_SEL_TX2_ADC_SEL_R_ADC2 0x1 +#define TIMPANI_CDC_DEC_ADC_SEL_TX2_ADC_SEL_R_ADC1 0x0 + +#define TIMPANI_CDC_DEC_ADC_SEL_TX2_ADC_SEL_L_S 4 +#define TIMPANI_CDC_DEC_ADC_SEL_TX2_ADC_SEL_L_M 0x30 +#define TIMPANI_CDC_DEC_ADC_SEL_TX2_ADC_SEL_L_ADC4 0x3 +#define TIMPANI_CDC_DEC_ADC_SEL_TX2_ADC_SEL_L_ADC3 0x2 +#define TIMPANI_CDC_DEC_ADC_SEL_TX2_ADC_SEL_L_ADC2 0x1 +#define TIMPANI_CDC_DEC_ADC_SEL_TX2_ADC_SEL_L_ADC1 0x0 + +#define TIMPANI_CDC_DEC_ADC_SEL_TX1_ADC_SEL_R_S 2 +#define TIMPANI_CDC_DEC_ADC_SEL_TX1_ADC_SEL_R_M 0xC +#define TIMPANI_CDC_DEC_ADC_SEL_TX1_ADC_SEL_R_ADC4 0x3 +#define TIMPANI_CDC_DEC_ADC_SEL_TX1_ADC_SEL_R_ADC3 0x2 +#define TIMPANI_CDC_DEC_ADC_SEL_TX1_ADC_SEL_R_ADC2 0x1 +#define TIMPANI_CDC_DEC_ADC_SEL_TX1_ADC_SEL_R_ADC1 0x0 + +#define TIMPANI_CDC_DEC_ADC_SEL_TX1_ADC_SEL_L_S 0 +#define TIMPANI_CDC_DEC_ADC_SEL_TX1_ADC_SEL_L_M 0x3 +#define TIMPANI_CDC_DEC_ADC_SEL_TX1_ADC_SEL_L_ADC4 0x3 +#define TIMPANI_CDC_DEC_ADC_SEL_TX1_ADC_SEL_L_ADC3 0x2 +#define TIMPANI_CDC_DEC_ADC_SEL_TX1_ADC_SEL_L_ADC2 0x1 +#define TIMPANI_CDC_DEC_ADC_SEL_TX1_ADC_SEL_L_ADC1 0x0 + + +/* -- For CDC_ANC_INPUT_MUX */ +#define TIMPANI_A_CDC_ANC_INPUT_MUX (0x9A) +#define TIMPANI_CDC_ANC_INPUT_MUX_RWC "RW" +#define TIMPANI_CDC_ANC_INPUT_MUX_POR 0 +#define TIMPANI_CDC_ANC_INPUT_MUX_S 0 +#define TIMPANI_CDC_ANC_INPUT_MUX_M 0xFF + + +#define TIMPANI_CDC_ANC_INPUT_MUX_ANC2_ADC_SEL_S 6 +#define TIMPANI_CDC_ANC_INPUT_MUX_ANC2_ADC_SEL_M 0xC0 +#define TIMPANI_CDC_ANC_INPUT_MUX_ANC2_ADC_SEL_A_CDC_TX2DOR 0x3 +#define TIMPANI_CDC_ANC_INPUT_MUX_ANC2_ADC_SEL_A_CDC_TX2DOL 0x2 +#define TIMPANI_CDC_ANC_INPUT_MUX_ANC2_ADC_SEL_A_CDC_TX1DOR 0x1 +#define TIMPANI_CDC_ANC_INPUT_MUX_ANC2_ADC_SEL_A_CDC_TX1DOL 0x0 + +#define TIMPANI_CDC_ANC_INPUT_MUX_ANC2_DMIC_SEL_S 4 +#define TIMPANI_CDC_ANC_INPUT_MUX_ANC2_DMIC_SEL_M 0x30 +#define TIMPANI_CDC_ANC_INPUT_MUX_ANC2_DMIC_SEL_MIC2_DIN_R 0x3 +#define TIMPANI_CDC_ANC_INPUT_MUX_ANC2_DMIC_SEL_MIC2_DIN_L 0x2 +#define TIMPANI_CDC_ANC_INPUT_MUX_ANC2_DMIC_SEL_MIC1_DIN_R 0x1 +#define TIMPANI_CDC_ANC_INPUT_MUX_ANC2_DMIC_SEL_MIC1_DIN_L 0x0 + +#define TIMPANI_CDC_ANC_INPUT_MUX_ANC1_ADC_SEL_S 2 +#define TIMPANI_CDC_ANC_INPUT_MUX_ANC1_ADC_SEL_M 0xC +#define TIMPANI_CDC_ANC_INPUT_MUX_ANC1_ADC_SEL_A_CDC_TX2DOR 0x3 +#define TIMPANI_CDC_ANC_INPUT_MUX_ANC1_ADC_SEL_A_CDC_TX2DOL 0x2 +#define TIMPANI_CDC_ANC_INPUT_MUX_ANC1_ADC_SEL_A_CDC_TX1DOR 0x1 +#define TIMPANI_CDC_ANC_INPUT_MUX_ANC1_ADC_SEL_A_CDC_TX1DOL 0x0 + +#define TIMPANI_CDC_ANC_INPUT_MUX_ANC1_DMIC_SEL_S 0 +#define TIMPANI_CDC_ANC_INPUT_MUX_ANC1_DMIC_SEL_M 0x3 +#define TIMPANI_CDC_ANC_INPUT_MUX_ANC1_DMIC_SEL_MIC2_DIN_R 0x3 +#define TIMPANI_CDC_ANC_INPUT_MUX_ANC1_DMIC_SEL_MIC2_DIN_L 0x2 +#define TIMPANI_CDC_ANC_INPUT_MUX_ANC1_DMIC_SEL_MIC1_DIN_R 0x1 +#define TIMPANI_CDC_ANC_INPUT_MUX_ANC1_DMIC_SEL_MIC1_DIN_L 0x0 + + +/* -- For CDC_ANC_RX_CLK_NS_SEL */ +#define TIMPANI_A_CDC_ANC_RX_CLK_NS_SEL (0x9B) +#define TIMPANI_CDC_ANC_RX_CLK_NS_SEL_RWC "RW" +#define TIMPANI_CDC_ANC_RX_CLK_NS_SEL_POR 0 +#define TIMPANI_CDC_ANC_RX_CLK_NS_SEL_S 0 +#define TIMPANI_CDC_ANC_RX_CLK_NS_SEL_M 0x1 + + +#define TIMPANI_CDC_ANC_RX_CLK_NS_SEL_ANC_RX_CLK_NS_SEL_S 0 +#define TIMPANI_CDC_ANC_RX_CLK_NS_SEL_ANC_RX_CLK_NS_SEL_M 0x1 + + +/* -- For CDC_ANC_FB_TUNE_SEL */ +#define TIMPANI_A_CDC_ANC_FB_TUNE_SEL (0x9C) +#define TIMPANI_CDC_ANC_FB_TUNE_SEL_RWC "RW" +#define TIMPANI_CDC_ANC_FB_TUNE_SEL_POR 0 +#define TIMPANI_CDC_ANC_FB_TUNE_SEL_S 0 +#define TIMPANI_CDC_ANC_FB_TUNE_SEL_M 0x3 + + +#define TIMPANI_CDC_ANC_FB_TUNE_SEL_ANC2_FB_ADC_SEL_S 1 +#define TIMPANI_CDC_ANC_FB_TUNE_SEL_ANC2_FB_ADC_SEL_M 0x2 +#define TIMPANI_CDC_ANC_FB_TUNE_SEL_ANC2_FB_ADC_SEL_FB_TUNE_EN 0x1 +#define TIMPANI_CDC_ANC_FB_TUNE_SEL_ANC2_FB_ADC_SEL_FB_TUNE_DIS 0x0 + +#define TIMPANI_CDC_ANC_FB_TUNE_SEL_ANC1_FB_ADC_SEL_S 0 +#define TIMPANI_CDC_ANC_FB_TUNE_SEL_ANC1_FB_ADC_SEL_M 0x1 +#define TIMPANI_CDC_ANC_FB_TUNE_SEL_ANC1_FB_ADC_SEL_FB_TUNE_EN 0x1 +#define TIMPANI_CDC_ANC_FB_TUNE_SEL_ANC1_FB_ADC_SEL_FB_TUNE_DIS 0x0 + + +/* -- For CLK_DIV_SYNC_CTL */ +#define TIMPANI_A_CLK_DIV_SYNC_CTL (0x9E) +#define TIMPANI_CLK_DIV_SYNC_CTL_RWC "RW" +#define TIMPANI_CLK_DIV_SYNC_CTL_POR 0 +#define TIMPANI_CLK_DIV_SYNC_CTL_S 0 +#define TIMPANI_CLK_DIV_SYNC_CTL_M 0x3 + + +#define TIMPANI_CLK_DIV_SYNC_CTL_GLBL_DIV_SYNC_S 1 +#define TIMPANI_CLK_DIV_SYNC_CTL_GLBL_DIV_SYNC_M 0x2 + +#define TIMPANI_CLK_DIV_SYNC_CTL_TX_DIV_SYNC_S 0 +#define TIMPANI_CLK_DIV_SYNC_CTL_TX_DIV_SYNC_M 0x1 + + +/* -- For CDC_ADC_CLK_EN */ +#define TIMPANI_A_CDC_ADC_CLK_EN (0x9F) +#define TIMPANI_CDC_ADC_CLK_EN_RWC "RW" +#define TIMPANI_CDC_ADC_CLK_EN_POR 0 +#define TIMPANI_CDC_ADC_CLK_EN_S 0 +#define TIMPANI_CDC_ADC_CLK_EN_M 0xF + + +#define TIMPANI_CDC_ADC_CLK_EN_A_TX2_R_EN_S 3 +#define TIMPANI_CDC_ADC_CLK_EN_A_TX2_R_EN_M 0x8 + +#define TIMPANI_CDC_ADC_CLK_EN_A_TX2_L_EN_S 2 +#define TIMPANI_CDC_ADC_CLK_EN_A_TX2_L_EN_M 0x4 + +#define TIMPANI_CDC_ADC_CLK_EN_A_TX1_R_EN_S 1 +#define TIMPANI_CDC_ADC_CLK_EN_A_TX1_R_EN_M 0x2 + +#define TIMPANI_CDC_ADC_CLK_EN_A_TX1_L_EN_S 0 +#define TIMPANI_CDC_ADC_CLK_EN_A_TX1_L_EN_M 0x1 + + +/* -- For CDC_ST_MIXING */ +#define TIMPANI_A_CDC_ST_MIXING (0xA0) +#define TIMPANI_CDC_ST_MIXING_RWC "RW" +#define TIMPANI_CDC_ST_MIXING_POR 0 +#define TIMPANI_CDC_ST_MIXING_S 0 +#define TIMPANI_CDC_ST_MIXING_M 0xF + + +#define TIMPANI_CDC_ST_MIXING_TX2_R_S 3 +#define TIMPANI_CDC_ST_MIXING_TX2_R_M 0x8 + +#define TIMPANI_CDC_ST_MIXING_TX2_L_S 2 +#define TIMPANI_CDC_ST_MIXING_TX2_L_M 0x4 + +#define TIMPANI_CDC_ST_MIXING_TX1_R_S 1 +#define TIMPANI_CDC_ST_MIXING_TX1_R_M 0x2 + +#define TIMPANI_CDC_ST_MIXING_TX1_L_S 0 +#define TIMPANI_CDC_ST_MIXING_TX1_L_M 0x1 + + +/* -- For CDC_RX2_CTL */ +#define TIMPANI_A_CDC_RX2_CTL (0xA1) +#define TIMPANI_CDC_RX2_CTL_RWC "RW" +#define TIMPANI_CDC_RX2_CTL_POR 0xc +#define TIMPANI_CDC_RX2_CTL_S 0 +#define TIMPANI_CDC_RX2_CTL_M 0x3F + + +#define TIMPANI_CDC_RX2_CTL_SIDETONE_EN2_R_S 5 +#define TIMPANI_CDC_RX2_CTL_SIDETONE_EN2_R_M 0x20 + +#define TIMPANI_CDC_RX2_CTL_SIDETONE_EN2_L_S 4 +#define TIMPANI_CDC_RX2_CTL_SIDETONE_EN2_L_M 0x10 + +#define TIMPANI_CDC_RX2_CTL_RX2_RATE_S 2 +#define TIMPANI_CDC_RX2_CTL_RX2_RATE_M 0xC +#define TIMPANI_CDC_RX2_CTL_RX2_RATE_OSR_256 0x3 +#define TIMPANI_CDC_RX2_CTL_RX2_RATE_OSR_128 0x1 +#define TIMPANI_CDC_RX2_CTL_RX2_RATE_OSR_64 0x0 + +#define TIMPANI_CDC_RX2_CTL_RX2_I2S_RATE_S 1 +#define TIMPANI_CDC_RX2_CTL_RX2_I2S_RATE_M 0x2 +#define TIMPANI_CDC_RX2_CTL_RX2_I2S_RATE_BR_32 0x1 +#define TIMPANI_CDC_RX2_CTL_RX2_I2S_RATE_BR_64 0x0 + +#define TIMPANI_CDC_RX2_CTL_RX2_I2S_MODE_S 0 +#define TIMPANI_CDC_RX2_CTL_RX2_I2S_MODE_M 0x1 +#define TIMPANI_CDC_RX2_CTL_RX2_I2S_MODE_MASTER 0x1 +#define TIMPANI_CDC_RX2_CTL_RX2_I2S_MODE_SLAVE 0x0 + + +/* -- For CDC_ARB_CLK_EN */ +#define TIMPANI_A_CDC_ARB_CLK_EN (0xA2) +#define TIMPANI_CDC_ARB_CLK_EN_RWC "RW" +#define TIMPANI_CDC_ARB_CLK_EN_POR 0 +#define TIMPANI_CDC_ARB_CLK_EN_S 0 +#define TIMPANI_CDC_ARB_CLK_EN_M 0x1 + + +#define TIMPANI_CDC_ARB_CLK_EN_ARB_CLK_EN_S 0 +#define TIMPANI_CDC_ARB_CLK_EN_ARB_CLK_EN_M 0x1 + + +/* -- For CDC_I2S_CTL2 */ +#define TIMPANI_A_CDC_I2S_CTL2 (0xA3) +#define TIMPANI_CDC_I2S_CTL2_RWC "RW" +#define TIMPANI_CDC_I2S_CTL2_POR 0 +#define TIMPANI_CDC_I2S_CTL2_S 0 +#define TIMPANI_CDC_I2S_CTL2_M 0x3F + + +#define TIMPANI_CDC_I2S_CTL2_TX_I2S_CLK_SEL_S 3 +#define TIMPANI_CDC_I2S_CTL2_TX_I2S_CLK_SEL_M 0x38 +#define TIMPANI_CDC_I2S_CTL2_TX_I2S_CLK_SEL_CLK_DMIC 0x4 +#define TIMPANI_CDC_I2S_CTL2_TX_I2S_CLK_SEL_CLK_TX2_R 0x3 +#define TIMPANI_CDC_I2S_CTL2_TX_I2S_CLK_SEL_CLK_TX2_L 0x2 +#define TIMPANI_CDC_I2S_CTL2_TX_I2S_CLK_SEL_CLK_TX1_R 0x1 +#define TIMPANI_CDC_I2S_CTL2_TX_I2S_CLK_SEL_CLK_TX1_L 0x0 + +#define TIMPANI_CDC_I2S_CTL2_RX2_I2SCLK_EN_S 2 +#define TIMPANI_CDC_I2S_CTL2_RX2_I2SCLK_EN_M 0x4 + +#define TIMPANI_CDC_I2S_CTL2_RX1_I2SCLK_EN_S 1 +#define TIMPANI_CDC_I2S_CTL2_RX1_I2SCLK_EN_M 0x2 + +#define TIMPANI_CDC_I2S_CTL2_TX_I2SCLK_EN_S 0 +#define TIMPANI_CDC_I2S_CTL2_TX_I2SCLK_EN_M 0x1 + + +/* -- For CDC_RX2LG */ +#define TIMPANI_A_CDC_RX2LG (0xA4) +#define TIMPANI_CDC_RX2LG_RWC "RW" +#define TIMPANI_CDC_RX2LG_POR 0xac +#define TIMPANI_CDC_RX2LG_S 0 +#define TIMPANI_CDC_RX2LG_M 0xFF + + +#define TIMPANI_CDC_RX2LG_GAIN_S 0 +#define TIMPANI_CDC_RX2LG_GAIN_M 0xFF + + +/* -- For CDC_RX2RG */ +#define TIMPANI_A_CDC_RX2RG (0xA5) +#define TIMPANI_CDC_RX2RG_RWC "RW" +#define TIMPANI_CDC_RX2RG_POR 0xac +#define TIMPANI_CDC_RX2RG_S 0 +#define TIMPANI_CDC_RX2RG_M 0xFF + + +#define TIMPANI_CDC_RX2RG_GAIN_S 0 +#define TIMPANI_CDC_RX2RG_GAIN_M 0xFF + + +/* -- For CDC_TX2LG */ +#define TIMPANI_A_CDC_TX2LG (0xA6) +#define TIMPANI_CDC_TX2LG_RWC "RW" +#define TIMPANI_CDC_TX2LG_POR 0xac +#define TIMPANI_CDC_TX2LG_S 0 +#define TIMPANI_CDC_TX2LG_M 0xFF + + +#define TIMPANI_CDC_TX2LG_GAIN_S 0 +#define TIMPANI_CDC_TX2LG_GAIN_M 0xFF + + +/* -- For CDC_TX2RG */ +#define TIMPANI_A_CDC_TX2RG (0xA7) +#define TIMPANI_CDC_TX2RG_RWC "RW" +#define TIMPANI_CDC_TX2RG_POR 0xac +#define TIMPANI_CDC_TX2RG_S 0 +#define TIMPANI_CDC_TX2RG_M 0xFF + + +#define TIMPANI_CDC_TX2RG_GAIN_S 0 +#define TIMPANI_CDC_TX2RG_GAIN_M 0xFF + + +/* -- For CDC_DMIC_MUX */ +#define TIMPANI_A_CDC_DMIC_MUX (0xA8) +#define TIMPANI_CDC_DMIC_MUX_RWC "RW" +#define TIMPANI_CDC_DMIC_MUX_POR 0 +#define TIMPANI_CDC_DMIC_MUX_S 0 +#define TIMPANI_CDC_DMIC_MUX_M 0xFF + + +#define TIMPANI_CDC_DMIC_MUX_TX2_DMIC_MUX_SEL_R_S 6 +#define TIMPANI_CDC_DMIC_MUX_TX2_DMIC_MUX_SEL_R_M 0xC0 +#define TIMPANI_CDC_DMIC_MUX_TX2_DMIC_MUX_SEL_R_MIC2_DIN_R 0x3 +#define TIMPANI_CDC_DMIC_MUX_TX2_DMIC_MUX_SEL_R_MIC2_DIN_L 0x2 +#define TIMPANI_CDC_DMIC_MUX_TX2_DMIC_MUX_SEL_R_MIC1_DIN_R 0x1 +#define TIMPANI_CDC_DMIC_MUX_TX2_DMIC_MUX_SEL_R_MIC1_DIN_L 0x0 + +#define TIMPANI_CDC_DMIC_MUX_TX2_DMIC_MUX_SEL_L_S 4 +#define TIMPANI_CDC_DMIC_MUX_TX2_DMIC_MUX_SEL_L_M 0x30 +#define TIMPANI_CDC_DMIC_MUX_TX2_DMIC_MUX_SEL_L_MIC2_DIN_R 0x3 +#define TIMPANI_CDC_DMIC_MUX_TX2_DMIC_MUX_SEL_L_MIC2_DIN_L 0x2 +#define TIMPANI_CDC_DMIC_MUX_TX2_DMIC_MUX_SEL_L_MIC1_DIN_R 0x1 +#define TIMPANI_CDC_DMIC_MUX_TX2_DMIC_MUX_SEL_L_MIC1_DIN_L 0x0 + +#define TIMPANI_CDC_DMIC_MUX_TX1_DMIC_MUX_SEL_R_S 2 +#define TIMPANI_CDC_DMIC_MUX_TX1_DMIC_MUX_SEL_R_M 0xC +#define TIMPANI_CDC_DMIC_MUX_TX1_DMIC_MUX_SEL_R_MIC2_DIN_R 0x3 +#define TIMPANI_CDC_DMIC_MUX_TX1_DMIC_MUX_SEL_R_MIC2_DIN_L 0x2 +#define TIMPANI_CDC_DMIC_MUX_TX1_DMIC_MUX_SEL_R_MIC1_DIN_R 0x1 +#define TIMPANI_CDC_DMIC_MUX_TX1_DMIC_MUX_SEL_R_MIC1_DIN_L 0x0 + +#define TIMPANI_CDC_DMIC_MUX_TX1_DMIC_MUX_SEL_L_S 0 +#define TIMPANI_CDC_DMIC_MUX_TX1_DMIC_MUX_SEL_L_M 0x3 +#define TIMPANI_CDC_DMIC_MUX_TX1_DMIC_MUX_SEL_L_MIC2_DIN_R 0x3 +#define TIMPANI_CDC_DMIC_MUX_TX1_DMIC_MUX_SEL_L_MIC2_DIN_L 0x2 +#define TIMPANI_CDC_DMIC_MUX_TX1_DMIC_MUX_SEL_L_MIC1_DIN_R 0x1 +#define TIMPANI_CDC_DMIC_MUX_TX1_DMIC_MUX_SEL_L_MIC1_DIN_L 0x0 + + +/* -- For CDC_ARB_CLK_CTL */ +#define TIMPANI_A_CDC_ARB_CLK_CTL (0xA9) +#define TIMPANI_CDC_ARB_CLK_CTL_RWC "RW" +#define TIMPANI_CDC_ARB_CLK_CTL_POR 0 +#define TIMPANI_CDC_ARB_CLK_CTL_S 0 +#define TIMPANI_CDC_ARB_CLK_CTL_M 0x3 + + +#define TIMPANI_CDC_ARB_CLK_CTL_ARB_CLK_SEL_S 0 +#define TIMPANI_CDC_ARB_CLK_CTL_ARB_CLK_SEL_M 0x3 +#define TIMPANI_CDC_ARB_CLK_CTL_ARB_CLK_SEL_TX_MCLK 0x0 +#define TIMPANI_CDC_ARB_CLK_CTL_ARB_CLK_SEL_RX_MCLK1 0x1 +#define TIMPANI_CDC_ARB_CLK_CTL_ARB_CLK_SEL_RX_MCLK2 0x2 +#define TIMPANI_CDC_ARB_CLK_CTL_ARB_CLK_SEL_TCXO 0x3 + + +/* -- For CDC_GCTL2 */ +#define TIMPANI_A_CDC_GCTL2 (0xAA) +#define TIMPANI_CDC_GCTL2_RWC "RW" +#define TIMPANI_CDC_GCTL2_POR 0x33 +#define TIMPANI_CDC_GCTL2_S 0 +#define TIMPANI_CDC_GCTL2_M 0xFF + + +#define TIMPANI_CDC_GCTL2_TX2_PGA_UPDATE_R_S 7 +#define TIMPANI_CDC_GCTL2_TX2_PGA_UPDATE_R_M 0x80 + +#define TIMPANI_CDC_GCTL2_TX2_PGA_UPDATE_L_S 6 +#define TIMPANI_CDC_GCTL2_TX2_PGA_UPDATE_L_M 0x40 + +#define TIMPANI_CDC_GCTL2_TX2_PGA_MUTE_EN_R_S 5 +#define TIMPANI_CDC_GCTL2_TX2_PGA_MUTE_EN_R_M 0x20 + +#define TIMPANI_CDC_GCTL2_TX2_PGA_MUTE_EN_L_S 4 +#define TIMPANI_CDC_GCTL2_TX2_PGA_MUTE_EN_L_M 0x10 + +#define TIMPANI_CDC_GCTL2_RX2_PGA_UPDATE_R_S 3 +#define TIMPANI_CDC_GCTL2_RX2_PGA_UPDATE_R_M 0x8 + +#define TIMPANI_CDC_GCTL2_RX2_PGA_UPDATE_L_S 2 +#define TIMPANI_CDC_GCTL2_RX2_PGA_UPDATE_L_M 0x4 + +#define TIMPANI_CDC_GCTL2_RX2_PGA_MUTE_EN_R_S 1 +#define TIMPANI_CDC_GCTL2_RX2_PGA_MUTE_EN_R_M 0x2 + +#define TIMPANI_CDC_GCTL2_RX2_PGA_MUTE_EN_L_S 0 +#define TIMPANI_CDC_GCTL2_RX2_PGA_MUTE_EN_L_M 0x1 + + +/* -- For CDC_BYPASS_CTL2 */ +#define TIMPANI_A_CDC_BYPASS_CTL2 (0xAB) +#define TIMPANI_CDC_BYPASS_CTL2_RWC "RW" +#define TIMPANI_CDC_BYPASS_CTL2_POR 0x2D +#define TIMPANI_CDC_BYPASS_CTL2_S 0 +#define TIMPANI_CDC_BYPASS_CTL2_M 0x3F + + +#define TIMPANI_CDC_BYPASS_CTL2_TX1_DMIC_GAIN_BP_R_S 5 +#define TIMPANI_CDC_BYPASS_CTL2_TX1_DMIC_GAIN_BP_R_M 0x20 + +#define TIMPANI_CDC_BYPASS_CTL2_TX1_ADC_GAIN_BP_R_S 4 +#define TIMPANI_CDC_BYPASS_CTL2_TX1_ADC_GAIN_BP_R_M 0x10 + +#define TIMPANI_CDC_BYPASS_CTL2_TX1_HPF_BP_R_S 3 +#define TIMPANI_CDC_BYPASS_CTL2_TX1_HPF_BP_R_M 0x8 + +#define TIMPANI_CDC_BYPASS_CTL2_TX1_DMIC_GAIN_BP_L_S 2 +#define TIMPANI_CDC_BYPASS_CTL2_TX1_DMIC_GAIN_BP_L_M 0x4 + +#define TIMPANI_CDC_BYPASS_CTL2_TX1_ADC_GAIN_BP_L_S 1 +#define TIMPANI_CDC_BYPASS_CTL2_TX1_ADC_GAIN_BP_L_M 0x2 + +#define TIMPANI_CDC_BYPASS_CTL2_TX1_HPF_BP_L_S 0 +#define TIMPANI_CDC_BYPASS_CTL2_TX1_HPF_BP_L_M 0x1 + + +/* -- For CDC_BYPASS_CTL3 */ +#define TIMPANI_A_CDC_BYPASS_CTL3 (0xAC) +#define TIMPANI_CDC_BYPASS_CTL3_RWC "RW" +#define TIMPANI_CDC_BYPASS_CTL3_POR 0x2D +#define TIMPANI_CDC_BYPASS_CTL3_S 0 +#define TIMPANI_CDC_BYPASS_CTL3_M 0x3F + + +#define TIMPANI_CDC_BYPASS_CTL3_TX2_DMIC_GAIN_BP_R_S 5 +#define TIMPANI_CDC_BYPASS_CTL3_TX2_DMIC_GAIN_BP_R_M 0x20 + +#define TIMPANI_CDC_BYPASS_CTL3_TX2_ADC_GAIN_BP_R_S 4 +#define TIMPANI_CDC_BYPASS_CTL3_TX2_ADC_GAIN_BP_R_M 0x10 + +#define TIMPANI_CDC_BYPASS_CTL3_TX2_HPF_BP_R_S 3 +#define TIMPANI_CDC_BYPASS_CTL3_TX2_HPF_BP_R_M 0x8 + +#define TIMPANI_CDC_BYPASS_CTL3_TX2_DMIC_GAIN_BP_L_S 2 +#define TIMPANI_CDC_BYPASS_CTL3_TX2_DMIC_GAIN_BP_L_M 0x4 + +#define TIMPANI_CDC_BYPASS_CTL3_TX2_ADC_GAIN_BP_L_S 1 +#define TIMPANI_CDC_BYPASS_CTL3_TX2_ADC_GAIN_BP_L_M 0x2 + +#define TIMPANI_CDC_BYPASS_CTL3_TX2_HPF_BP_L_S 0 +#define TIMPANI_CDC_BYPASS_CTL3_TX2_HPF_BP_L_M 0x1 + + +/* -- For CDC_BYPASS_CTL4 */ +#define TIMPANI_A_CDC_BYPASS_CTL4 (0xAD) +#define TIMPANI_CDC_BYPASS_CTL4_RWC "RW" +#define TIMPANI_CDC_BYPASS_CTL4_POR 0x2 +#define TIMPANI_CDC_BYPASS_CTL4_S 0 +#define TIMPANI_CDC_BYPASS_CTL4_M 0xF + + +#define TIMPANI_CDC_BYPASS_CTL4_DITHER_BP_S 3 +#define TIMPANI_CDC_BYPASS_CTL4_DITHER_BP_M 0x8 + +#define TIMPANI_CDC_BYPASS_CTL4_DITHER_SHAPE_SEL_S 2 +#define TIMPANI_CDC_BYPASS_CTL4_DITHER_SHAPE_SEL_M 0x4 + +#define TIMPANI_CDC_BYPASS_CTL4_DITHER_DLY_SEL_S 1 +#define TIMPANI_CDC_BYPASS_CTL4_DITHER_DLY_SEL_M 0x2 + +#define TIMPANI_CDC_BYPASS_CTL4_RX2_HPF_BP_S 0 +#define TIMPANI_CDC_BYPASS_CTL4_RX2_HPF_BP_M 0x1 + + +/* -- For CDC_RX2L_DCOFFSET */ +#define TIMPANI_A_CDC_RX2L_DCOFFSET (0xAE) +#define TIMPANI_CDC_RX2L_DCOFFSET_RWC "RW" +#define TIMPANI_CDC_RX2L_DCOFFSET_POR 0 +#define TIMPANI_CDC_RX2L_DCOFFSET_S 0 +#define TIMPANI_CDC_RX2L_DCOFFSET_M 0xFF + + +#define TIMPANI_CDC_RX2L_DCOFFSET_OFFSET_S 0 +#define TIMPANI_CDC_RX2L_DCOFFSET_OFFSET_M 0xFF + + +/* -- For CDC_RX2R_DCOFFSET */ +#define TIMPANI_A_CDC_RX2R_DCOFFSET (0xAF) +#define TIMPANI_CDC_RX2R_DCOFFSET_RWC "RW" +#define TIMPANI_CDC_RX2R_DCOFFSET_POR 0 +#define TIMPANI_CDC_RX2R_DCOFFSET_S 0 +#define TIMPANI_CDC_RX2R_DCOFFSET_M 0xFF + + +#define TIMPANI_CDC_RX2R_DCOFFSET_OFFSET_S 0 +#define TIMPANI_CDC_RX2R_DCOFFSET_OFFSET_M 0xFF + + +/* -- For CDC_RX_MIX_CTL */ +#define TIMPANI_A_CDC_RX_MIX_CTL (0xB0) +#define TIMPANI_CDC_RX_MIX_CTL_RWC "RW" +#define TIMPANI_CDC_RX_MIX_CTL_POR 0 +#define TIMPANI_CDC_RX_MIX_CTL_S 0 +#define TIMPANI_CDC_RX_MIX_CTL_M 0x3 + + +#define TIMPANI_CDC_RX_MIX_CTL_RX2TO1_EN_S 1 +#define TIMPANI_CDC_RX_MIX_CTL_RX2TO1_EN_M 0x2 + +#define TIMPANI_CDC_RX_MIX_CTL_RX1TO2_EN_S 0 +#define TIMPANI_CDC_RX_MIX_CTL_RX1TO2_EN_M 0x1 + + +/* -- For CDC_SPARE_CTL */ +#define TIMPANI_A_CDC_SPARE_CTL (0xB1) +#define TIMPANI_CDC_SPARE_CTL_RWC "RW" +#define TIMPANI_CDC_SPARE_CTL_POR 0 +#define TIMPANI_CDC_SPARE_CTL_S 0 +#define TIMPANI_CDC_SPARE_CTL_M 0xFF + + +#define TIMPANI_CDC_SPARE_CTL_CDC_SPARE_S 0 +#define TIMPANI_CDC_SPARE_CTL_CDC_SPARE_M 0xFF + + +/* -- For CDC_TESTMODE2 */ +#define TIMPANI_A_CDC_TESTMODE2 (0xB2) +#define TIMPANI_CDC_TESTMODE2_RWC "RW" +#define TIMPANI_CDC_TESTMODE2_POR 0 +#define TIMPANI_CDC_TESTMODE2_S 0 +#define TIMPANI_CDC_TESTMODE2_M 0x1F + + +#define TIMPANI_CDC_TESTMODE2_RX2_TEST_EN_R_S 4 +#define TIMPANI_CDC_TESTMODE2_RX2_TEST_EN_R_M 0x10 + +#define TIMPANI_CDC_TESTMODE2_RX2_TEST_EN_L_S 3 +#define TIMPANI_CDC_TESTMODE2_RX2_TEST_EN_L_M 0x8 + +#define TIMPANI_CDC_TESTMODE2_TX2_TEST_EN_R_S 2 +#define TIMPANI_CDC_TESTMODE2_TX2_TEST_EN_R_M 0x4 + +#define TIMPANI_CDC_TESTMODE2_TX2_TEST_EN_L_S 1 +#define TIMPANI_CDC_TESTMODE2_TX2_TEST_EN_L_M 0x2 + +#define TIMPANI_CDC_TESTMODE2_A_LOOPBACK_EN2_S 0 +#define TIMPANI_CDC_TESTMODE2_A_LOOPBACK_EN2_M 0x1 + + +/* -- For CDC_PDM_OE */ +#define TIMPANI_A_CDC_PDM_OE (0xB3) +#define TIMPANI_CDC_PDM_OE_RWC "RW" +#define TIMPANI_CDC_PDM_OE_POR 0 +#define TIMPANI_CDC_PDM_OE_S 0 +#define TIMPANI_CDC_PDM_OE_M 0x3F + + +#define TIMPANI_CDC_PDM_OE_PDM_23_20_OE_S 5 +#define TIMPANI_CDC_PDM_OE_PDM_23_20_OE_M 0x20 + +#define TIMPANI_CDC_PDM_OE_PDM_19_16_OE_S 4 +#define TIMPANI_CDC_PDM_OE_PDM_19_16_OE_M 0x10 + +#define TIMPANI_CDC_PDM_OE_PDM_15_12_OE_S 3 +#define TIMPANI_CDC_PDM_OE_PDM_15_12_OE_M 0x8 + +#define TIMPANI_CDC_PDM_OE_PDM_11_8_OE_S 2 +#define TIMPANI_CDC_PDM_OE_PDM_11_8_OE_M 0x4 + +#define TIMPANI_CDC_PDM_OE_PDM_7_4_OE_S 1 +#define TIMPANI_CDC_PDM_OE_PDM_7_4_OE_M 0x2 + +#define TIMPANI_CDC_PDM_OE_PDM_3_0_OE_S 0 +#define TIMPANI_CDC_PDM_OE_PDM_3_0_OE_M 0x1 + + +/* -- For CDC_TX1R_STG */ +#define TIMPANI_A_CDC_TX1R_STG (0xB4) +#define TIMPANI_CDC_TX1R_STG_RWC "RW" +#define TIMPANI_CDC_TX1R_STG_POR 0xac +#define TIMPANI_CDC_TX1R_STG_S 0 +#define TIMPANI_CDC_TX1R_STG_M 0xFF + + +#define TIMPANI_CDC_TX1R_STG_GAIN_S 0 +#define TIMPANI_CDC_TX1R_STG_GAIN_M 0xFF + + +/* -- For CDC_TX2L_STG */ +#define TIMPANI_A_CDC_TX2L_STG (0xB5) +#define TIMPANI_CDC_TX2L_STG_RWC "RW" +#define TIMPANI_CDC_TX2L_STG_POR 0xac +#define TIMPANI_CDC_TX2L_STG_S 0 +#define TIMPANI_CDC_TX2L_STG_M 0xFF + + +#define TIMPANI_CDC_TX2L_STG_GAIN_S 0 +#define TIMPANI_CDC_TX2L_STG_GAIN_M 0xFF + + +/* -- For CDC_TX2R_STG */ +#define TIMPANI_A_CDC_TX2R_STG (0xB6) +#define TIMPANI_CDC_TX2R_STG_RWC "RW" +#define TIMPANI_CDC_TX2R_STG_POR 0xac +#define TIMPANI_CDC_TX2R_STG_S 0 +#define TIMPANI_CDC_TX2R_STG_M 0xFF + + +#define TIMPANI_CDC_TX2R_STG_GAIN_S 0 +#define TIMPANI_CDC_TX2R_STG_GAIN_M 0xFF + + +/* -- For CDC_ARB_BYPASS_CTL */ +#define TIMPANI_A_CDC_ARB_BYPASS_CTL (0xB7) +#define TIMPANI_CDC_ARB_BYPASS_CTL_RWC "RW" +#define TIMPANI_CDC_ARB_BYPASS_CTL_POR 0 +#define TIMPANI_CDC_ARB_BYPASS_CTL_S 0 +#define TIMPANI_CDC_ARB_BYPASS_CTL_M 0x1 + + +#define TIMPANI_CDC_ARB_BYPASS_CTL_ARB_BYPASS_EN_S 0 +#define TIMPANI_CDC_ARB_BYPASS_CTL_ARB_BYPASS_EN_M 0x1 +#define TIMPANI_CDC_ARB_BYPASS_CTL_ARB_BYPASS_EN_BYPASS 0x1 +#define TIMPANI_CDC_ARB_BYPASS_CTL_ARB_BYPASS_EN_NO_BYPASS 0x0 + + +/* -- For CDC_ANC1_CTL1 */ +#define TIMPANI_A_CDC_ANC1_CTL1 (0xC0) +#define TIMPANI_CDC_ANC1_CTL1_RWC "RW" +#define TIMPANI_CDC_ANC1_CTL1_POR 0 +#define TIMPANI_CDC_ANC1_CTL1_S 0 +#define TIMPANI_CDC_ANC1_CTL1_M 0x3F + + +#define TIMPANI_CDC_ANC1_CTL1_ANC1_FF_OUT_DIS_S 5 +#define TIMPANI_CDC_ANC1_CTL1_ANC1_FF_OUT_DIS_M 0x20 +#define TIMPANI_CDC_ANC1_CTL1_ANC1_FF_OUT_DIS_FF_OUT_DIS 0x1 +#define TIMPANI_CDC_ANC1_CTL1_ANC1_FF_OUT_DIS_FF_OUT_EN 0x0 + +#define TIMPANI_CDC_ANC1_CTL1_ANC1_ADC_DMIC_SEL_S 4 +#define TIMPANI_CDC_ANC1_CTL1_ANC1_ADC_DMIC_SEL_M 0x10 +#define TIMPANI_CDC_ANC1_CTL1_ANC1_ADC_DMIC_SEL_DMIC 0x1 +#define TIMPANI_CDC_ANC1_CTL1_ANC1_ADC_DMIC_SEL_ADC 0x0 + +#define TIMPANI_CDC_ANC1_CTL1_ANC1_LR_EN_S 3 +#define TIMPANI_CDC_ANC1_CTL1_ANC1_LR_EN_M 0x8 +#define TIMPANI_CDC_ANC1_CTL1_ANC1_LR_EN_LR_MIX_EN 0x1 +#define TIMPANI_CDC_ANC1_CTL1_ANC1_LR_EN_LR_MIX_DIS 0x0 + +#define TIMPANI_CDC_ANC1_CTL1_ANC1_FB_EN_S 2 +#define TIMPANI_CDC_ANC1_CTL1_ANC1_FB_EN_M 0x4 +#define TIMPANI_CDC_ANC1_CTL1_ANC1_FB_EN_FB_MIX_EN 0x1 +#define TIMPANI_CDC_ANC1_CTL1_ANC1_FB_EN_FB_MIX_DIS 0x0 + +#define TIMPANI_CDC_ANC1_CTL1_ANC1_EN_S 1 +#define TIMPANI_CDC_ANC1_CTL1_ANC1_EN_M 0x2 +#define TIMPANI_CDC_ANC1_CTL1_ANC1_EN_ANC_EN 0x1 +#define TIMPANI_CDC_ANC1_CTL1_ANC1_EN_ANC_DIS 0x0 + +#define TIMPANI_CDC_ANC1_CTL1_ANC1_SOFT_RESET_S 0 +#define TIMPANI_CDC_ANC1_CTL1_ANC1_SOFT_RESET_M 0x1 +#define TIMPANI_CDC_ANC1_CTL1_ANC1_SOFT_RESET_ANC_RESET 0x1 +#define TIMPANI_CDC_ANC1_CTL1_ANC1_SOFT_RESET_ANC_ACTIVE 0x0 + + +/* -- For CDC_ANC1_CTL2 */ +#define TIMPANI_A_CDC_ANC1_CTL2 (0xC1) +#define TIMPANI_CDC_ANC1_CTL2_RWC "RW" +#define TIMPANI_CDC_ANC1_CTL2_POR 0 +#define TIMPANI_CDC_ANC1_CTL2_S 0 +#define TIMPANI_CDC_ANC1_CTL2_M 0x1F + + +#define TIMPANI_CDC_ANC1_CTL2_ANC1_FREQ_SEL_S 0 +#define TIMPANI_CDC_ANC1_CTL2_ANC1_FREQ_SEL_M 0x1F + + +/* -- For CDC_ANC1_FF_FB_SHIFT */ +#define TIMPANI_A_CDC_ANC1_FF_FB_SHIFT (0xC2) +#define TIMPANI_CDC_ANC1_FF_FB_SHIFT_RWC "RW" +#define TIMPANI_CDC_ANC1_FF_FB_SHIFT_POR 0 +#define TIMPANI_CDC_ANC1_FF_FB_SHIFT_S 0 +#define TIMPANI_CDC_ANC1_FF_FB_SHIFT_M 0xFF + + +#define TIMPANI_CDC_ANC1_FF_FB_SHIFT_ANC1_FB_LPF_SHIFT_S 4 +#define TIMPANI_CDC_ANC1_FF_FB_SHIFT_ANC1_FB_LPF_SHIFT_M 0xF0 + +#define TIMPANI_CDC_ANC1_FF_FB_SHIFT_ANC1_FF_LPF_SHIFT_S 0 +#define TIMPANI_CDC_ANC1_FF_FB_SHIFT_ANC1_FF_LPF_SHIFT_M 0xF + + +/* -- For CDC_ANC1_RX_NS */ +#define TIMPANI_A_CDC_ANC1_RX_NS (0xC3) +#define TIMPANI_CDC_ANC1_RX_NS_RWC "RW" +#define TIMPANI_CDC_ANC1_RX_NS_POR 0x1 +#define TIMPANI_CDC_ANC1_RX_NS_S 0 +#define TIMPANI_CDC_ANC1_RX_NS_M 0x7 + + +#define TIMPANI_CDC_ANC1_RX_NS_ANC1_DITHER_BP_S 2 +#define TIMPANI_CDC_ANC1_RX_NS_ANC1_DITHER_BP_M 0x4 + +#define TIMPANI_CDC_ANC1_RX_NS_ANC1_DITHER_SHAPE_SEL_S 1 +#define TIMPANI_CDC_ANC1_RX_NS_ANC1_DITHER_SHAPE_SEL_M 0x2 + +#define TIMPANI_CDC_ANC1_RX_NS_ANC1_DITHER_DLY_SEL_S 0 +#define TIMPANI_CDC_ANC1_RX_NS_ANC1_DITHER_DLY_SEL_M 0x1 + + +/* -- For CDC_ANC1_SPARE */ +#define TIMPANI_A_CDC_ANC1_SPARE (0xC4) +#define TIMPANI_CDC_ANC1_SPARE_RWC "RW" +#define TIMPANI_CDC_ANC1_SPARE_POR 0 +#define TIMPANI_CDC_ANC1_SPARE_S 0 +#define TIMPANI_CDC_ANC1_SPARE_M 0xFF + + +#define TIMPANI_CDC_ANC1_SPARE_ANC1_SPARE_S 0 +#define TIMPANI_CDC_ANC1_SPARE_ANC1_SPARE_M 0xFF + + +/* -- For CDC_ANC1_IIR_COEFF_PTR */ +#define TIMPANI_A_CDC_ANC1_IIR_COEFF_PTR (0xC5) +#define TIMPANI_CDC_ANC1_IIR_COEFF_PTR_RWC "RW" +#define TIMPANI_CDC_ANC1_IIR_COEFF_PTR_POR 0 +#define TIMPANI_CDC_ANC1_IIR_COEFF_PTR_S 0 +#define TIMPANI_CDC_ANC1_IIR_COEFF_PTR_M 0x1F + + +#define TIMPANI_CDC_ANC1_IIR_COEFF_PTR_ANC1_IIR_COEFF_PTR_S 0 +#define TIMPANI_CDC_ANC1_IIR_COEFF_PTR_ANC1_IIR_COEFF_PTR_M 0x1F + + +/* -- For CDC_ANC1_IIR_COEFF_MSB */ +#define TIMPANI_A_CDC_ANC1_IIR_COEFF_MSB (0xC6) +#define TIMPANI_CDC_ANC1_IIR_COEFF_MSB_RWC "RW" +#define TIMPANI_CDC_ANC1_IIR_COEFF_MSB_POR 0 +#define TIMPANI_CDC_ANC1_IIR_COEFF_MSB_S 0 +#define TIMPANI_CDC_ANC1_IIR_COEFF_MSB_M 0x1 + + +#define TIMPANI_CDC_ANC1_IIR_COEFF_MSB_ANC1_IIR_COEFF_MSB_S 0 +#define TIMPANI_CDC_ANC1_IIR_COEFF_MSB_ANC1_IIR_COEFF_MSB_M 0x1 + + +/* -- For CDC_ANC1_IIR_COEFF_LSB */ +#define TIMPANI_A_CDC_ANC1_IIR_COEFF_LSB (0xC7) +#define TIMPANI_CDC_ANC1_IIR_COEFF_LSB_RWC "RW" +#define TIMPANI_CDC_ANC1_IIR_COEFF_LSB_POR 0 +#define TIMPANI_CDC_ANC1_IIR_COEFF_LSB_S 0 +#define TIMPANI_CDC_ANC1_IIR_COEFF_LSB_M 0xFF + + +#define TIMPANI_CDC_ANC1_IIR_COEFF_LSB_ANC1_IIR_COEFF_LSB_S 0 +#define TIMPANI_CDC_ANC1_IIR_COEFF_LSB_ANC1_IIR_COEFF_LSB_M 0xFF + + +/* -- For CDC_ANC1_IIR_COEFF_CTL */ +#define TIMPANI_A_CDC_ANC1_IIR_COEFF_CTL (0xC8) +#define TIMPANI_CDC_ANC1_IIR_COEFF_CTL_RWC "RW" +#define TIMPANI_CDC_ANC1_IIR_COEFF_CTL_POR 0 +#define TIMPANI_CDC_ANC1_IIR_COEFF_CTL_S 0 +#define TIMPANI_CDC_ANC1_IIR_COEFF_CTL_M 0x3 + + +#define TIMPANI_CDC_ANC1_IIR_COEFF_CTL_ANC1_IIR_COEFF_ADAPTIVE_S 1 +#define TIMPANI_CDC_ANC1_IIR_COEFF_CTL_ANC1_IIR_COEFF_ADAPTIVE_M 0x2 +#define TIMPANI_CDC_ANC1_IIR_COEFF_CTL_ANC1_IIR_COEFF_ADAPTIVE_ADAPTIVE 0x1 +#define TIMPANI_CDC_ANC1_IIR_COEFF_CTL_ANC1_IIR_COEFF_ADAPTIVE_NON_ADAPTIVE 0x0 + +#define TIMPANI_CDC_ANC1_IIR_COEFF_CTL_ANC1_IIR_COEFF_EN_S 0 +#define TIMPANI_CDC_ANC1_IIR_COEFF_CTL_ANC1_IIR_COEFF_EN_M 0x1 +#define TIMPANI_CDC_ANC1_IIR_COEFF_CTL_ANC1_IIR_COEFF_EN_UPDATE 0x1 +#define TIMPANI_CDC_ANC1_IIR_COEFF_CTL_ANC1_IIR_COEFF_EN_NO_UPDATE 0x0 + + +/* -- For CDC_ANC1_LPF_COEFF_PTR */ +#define TIMPANI_A_CDC_ANC1_LPF_COEFF_PTR (0xC9) +#define TIMPANI_CDC_ANC1_LPF_COEFF_PTR_RWC "RW" +#define TIMPANI_CDC_ANC1_LPF_COEFF_PTR_POR 0 +#define TIMPANI_CDC_ANC1_LPF_COEFF_PTR_S 0 +#define TIMPANI_CDC_ANC1_LPF_COEFF_PTR_M 0xF + + +#define TIMPANI_CDC_ANC1_LPF_COEFF_PTR_ANC1_LPF_COEFF_PTR_S 0 +#define TIMPANI_CDC_ANC1_LPF_COEFF_PTR_ANC1_LPF_COEFF_PTR_M 0xF + + +/* -- For CDC_ANC1_LPF_COEFF_MSB */ +#define TIMPANI_A_CDC_ANC1_LPF_COEFF_MSB (0xCA) +#define TIMPANI_CDC_ANC1_LPF_COEFF_MSB_RWC "RW" +#define TIMPANI_CDC_ANC1_LPF_COEFF_MSB_POR 0 +#define TIMPANI_CDC_ANC1_LPF_COEFF_MSB_S 0 +#define TIMPANI_CDC_ANC1_LPF_COEFF_MSB_M 0xF + + +#define TIMPANI_CDC_ANC1_LPF_COEFF_MSB_ANC1_LPF_COEFF_MSB_S 0 +#define TIMPANI_CDC_ANC1_LPF_COEFF_MSB_ANC1_LPF_COEFF_MSB_M 0xF + + +/* -- For CDC_ANC1_LPF_COEFF_LSB */ +#define TIMPANI_A_CDC_ANC1_LPF_COEFF_LSB (0xCB) +#define TIMPANI_CDC_ANC1_LPF_COEFF_LSB_RWC "RW" +#define TIMPANI_CDC_ANC1_LPF_COEFF_LSB_POR 0 +#define TIMPANI_CDC_ANC1_LPF_COEFF_LSB_S 0 +#define TIMPANI_CDC_ANC1_LPF_COEFF_LSB_M 0xFF + + +#define TIMPANI_CDC_ANC1_LPF_COEFF_LSB_ANC1_LPF_COEFF_LSB_S 0 +#define TIMPANI_CDC_ANC1_LPF_COEFF_LSB_ANC1_LPF_COEFF_LSB_M 0xFF + + +/* -- For CDC_ANC1_SCALE_PTR */ +#define TIMPANI_A_CDC_ANC1_SCALE_PTR (0xCC) +#define TIMPANI_CDC_ANC1_SCALE_PTR_RWC "RW" +#define TIMPANI_CDC_ANC1_SCALE_PTR_POR 0 +#define TIMPANI_CDC_ANC1_SCALE_PTR_S 0 +#define TIMPANI_CDC_ANC1_SCALE_PTR_M 0x7 + + +#define TIMPANI_CDC_ANC1_SCALE_PTR_ANC1_SCALE_PTR_S 0 +#define TIMPANI_CDC_ANC1_SCALE_PTR_ANC1_SCALE_PTR_M 0x7 + + +/* -- For CDC_ANC1_SCALE */ +#define TIMPANI_A_CDC_ANC1_SCALE (0xCD) +#define TIMPANI_CDC_ANC1_SCALE_RWC "RW" +#define TIMPANI_CDC_ANC1_SCALE_POR 0 +#define TIMPANI_CDC_ANC1_SCALE_S 0 +#define TIMPANI_CDC_ANC1_SCALE_M 0xFF + + +#define TIMPANI_CDC_ANC1_SCALE_ANC1_SCALE_S 0 +#define TIMPANI_CDC_ANC1_SCALE_ANC1_SCALE_M 0xFF + + +/* -- For CDC_ANC1_DEBUG */ +#define TIMPANI_A_CDC_ANC1_DEBUG (0xCE) +#define TIMPANI_CDC_ANC1_DEBUG_RWC "RW" +#define TIMPANI_CDC_ANC1_DEBUG_POR 0 +#define TIMPANI_CDC_ANC1_DEBUG_S 0 +#define TIMPANI_CDC_ANC1_DEBUG_M 0xF + + +#define TIMPANI_CDC_ANC1_DEBUG_ANC1_DEBUG_SEL_S 0 +#define TIMPANI_CDC_ANC1_DEBUG_ANC1_DEBUG_SEL_M 0xF + + +/* -- For CDC_ANC2_CTL1 */ +#define TIMPANI_A_CDC_ANC2_CTL1 (0xD0) +#define TIMPANI_CDC_ANC2_CTL1_RWC "RW" +#define TIMPANI_CDC_ANC2_CTL1_POR 0 +#define TIMPANI_CDC_ANC2_CTL1_S 0 +#define TIMPANI_CDC_ANC2_CTL1_M 0x3F + + +#define TIMPANI_CDC_ANC2_CTL1_ANC2_FF_OUT_DIS_S 5 +#define TIMPANI_CDC_ANC2_CTL1_ANC2_FF_OUT_DIS_M 0x20 +#define TIMPANI_CDC_ANC2_CTL1_ANC2_FF_OUT_DIS_FF_OUT_DIS 0x1 +#define TIMPANI_CDC_ANC2_CTL1_ANC2_FF_OUT_DIS_FF_OUT_EN 0x0 + +#define TIMPANI_CDC_ANC2_CTL1_ANC2_ADC_DMIC_SEL_S 4 +#define TIMPANI_CDC_ANC2_CTL1_ANC2_ADC_DMIC_SEL_M 0x10 +#define TIMPANI_CDC_ANC2_CTL1_ANC2_ADC_DMIC_SEL_DMIC 0x1 +#define TIMPANI_CDC_ANC2_CTL1_ANC2_ADC_DMIC_SEL_ADC 0x0 + +#define TIMPANI_CDC_ANC2_CTL1_ANC2_LR_EN_S 3 +#define TIMPANI_CDC_ANC2_CTL1_ANC2_LR_EN_M 0x8 +#define TIMPANI_CDC_ANC2_CTL1_ANC2_LR_EN_LR_MIX_EN 0x1 +#define TIMPANI_CDC_ANC2_CTL1_ANC2_LR_EN_LR_MIX_DIS 0x0 + +#define TIMPANI_CDC_ANC2_CTL1_ANC2_FB_EN_S 2 +#define TIMPANI_CDC_ANC2_CTL1_ANC2_FB_EN_M 0x4 +#define TIMPANI_CDC_ANC2_CTL1_ANC2_FB_EN_FB_MIX_EN 0x1 +#define TIMPANI_CDC_ANC2_CTL1_ANC2_FB_EN_FB_MIX_DIS 0x0 + +#define TIMPANI_CDC_ANC2_CTL1_ANC2_EN_S 1 +#define TIMPANI_CDC_ANC2_CTL1_ANC2_EN_M 0x2 +#define TIMPANI_CDC_ANC2_CTL1_ANC2_EN_ANC_EN 0x1 +#define TIMPANI_CDC_ANC2_CTL1_ANC2_EN_ANC_DIS 0x0 + +#define TIMPANI_CDC_ANC2_CTL1_ANC2_SOFT_RESET_S 0 +#define TIMPANI_CDC_ANC2_CTL1_ANC2_SOFT_RESET_M 0x1 +#define TIMPANI_CDC_ANC2_CTL1_ANC2_SOFT_RESET_ANC_RESET 0x1 +#define TIMPANI_CDC_ANC2_CTL1_ANC2_SOFT_RESET_ANC_ACTIVE 0x0 + + +/* -- For CDC_ANC2_CTL2 */ +#define TIMPANI_A_CDC_ANC2_CTL2 (0xD1) +#define TIMPANI_CDC_ANC2_CTL2_RWC "RW" +#define TIMPANI_CDC_ANC2_CTL2_POR 0 +#define TIMPANI_CDC_ANC2_CTL2_S 0 +#define TIMPANI_CDC_ANC2_CTL2_M 0x1F + + +#define TIMPANI_CDC_ANC2_CTL2_ANC2_FREQ_SEL_S 0 +#define TIMPANI_CDC_ANC2_CTL2_ANC2_FREQ_SEL_M 0x1F + + +/* -- For CDC_ANC2_FF_FB_SHIFT */ +#define TIMPANI_A_CDC_ANC2_FF_FB_SHIFT (0xD2) +#define TIMPANI_CDC_ANC2_FF_FB_SHIFT_RWC "RW" +#define TIMPANI_CDC_ANC2_FF_FB_SHIFT_POR 0 +#define TIMPANI_CDC_ANC2_FF_FB_SHIFT_S 0 +#define TIMPANI_CDC_ANC2_FF_FB_SHIFT_M 0xFF + + +#define TIMPANI_CDC_ANC2_FF_FB_SHIFT_ANC2_FB_LPF_SHIFT_S 4 +#define TIMPANI_CDC_ANC2_FF_FB_SHIFT_ANC2_FB_LPF_SHIFT_M 0xF0 + +#define TIMPANI_CDC_ANC2_FF_FB_SHIFT_ANC2_FF_LPF_SHIFT_S 0 +#define TIMPANI_CDC_ANC2_FF_FB_SHIFT_ANC2_FF_LPF_SHIFT_M 0xF + + +/* -- For CDC_ANC2_RX_NS */ +#define TIMPANI_A_CDC_ANC2_RX_NS (0xD3) +#define TIMPANI_CDC_ANC2_RX_NS_RWC "RW" +#define TIMPANI_CDC_ANC2_RX_NS_POR 0x1 +#define TIMPANI_CDC_ANC2_RX_NS_S 0 +#define TIMPANI_CDC_ANC2_RX_NS_M 0x7 + + +#define TIMPANI_CDC_ANC2_RX_NS_ANC2_DITHER_BP_S 2 +#define TIMPANI_CDC_ANC2_RX_NS_ANC2_DITHER_BP_M 0x4 + +#define TIMPANI_CDC_ANC2_RX_NS_ANC2_DITHER_SHAPE_SEL_S 1 +#define TIMPANI_CDC_ANC2_RX_NS_ANC2_DITHER_SHAPE_SEL_M 0x2 + +#define TIMPANI_CDC_ANC2_RX_NS_ANC2_DITHER_DLY_SEL_S 0 +#define TIMPANI_CDC_ANC2_RX_NS_ANC2_DITHER_DLY_SEL_M 0x1 + + +/* -- For CDC_ANC2_SPARE */ +#define TIMPANI_A_CDC_ANC2_SPARE (0xD4) +#define TIMPANI_CDC_ANC2_SPARE_RWC "RW" +#define TIMPANI_CDC_ANC2_SPARE_POR 0 +#define TIMPANI_CDC_ANC2_SPARE_S 0 +#define TIMPANI_CDC_ANC2_SPARE_M 0xFF + + +#define TIMPANI_CDC_ANC2_SPARE_ANC2_SPARE_S 0 +#define TIMPANI_CDC_ANC2_SPARE_ANC2_SPARE_M 0xFF + + +/* -- For CDC_ANC2_IIR_COEFF_PTR */ +#define TIMPANI_A_CDC_ANC2_IIR_COEFF_PTR (0xD5) +#define TIMPANI_CDC_ANC2_IIR_COEFF_PTR_RWC "RW" +#define TIMPANI_CDC_ANC2_IIR_COEFF_PTR_POR 0 +#define TIMPANI_CDC_ANC2_IIR_COEFF_PTR_S 0 +#define TIMPANI_CDC_ANC2_IIR_COEFF_PTR_M 0x1F + + +#define TIMPANI_CDC_ANC2_IIR_COEFF_PTR_ANC2_IIR_COEFF_PTR_S 0 +#define TIMPANI_CDC_ANC2_IIR_COEFF_PTR_ANC2_IIR_COEFF_PTR_M 0x1F + + +/* -- For CDC_ANC2_IIR_COEFF_MSB */ +#define TIMPANI_A_CDC_ANC2_IIR_COEFF_MSB (0xD6) +#define TIMPANI_CDC_ANC2_IIR_COEFF_MSB_RWC "RW" +#define TIMPANI_CDC_ANC2_IIR_COEFF_MSB_POR 0 +#define TIMPANI_CDC_ANC2_IIR_COEFF_MSB_S 0 +#define TIMPANI_CDC_ANC2_IIR_COEFF_MSB_M 0x1 + + +#define TIMPANI_CDC_ANC2_IIR_COEFF_MSB_ANC2_IIR_COEFF_MSB_S 0 +#define TIMPANI_CDC_ANC2_IIR_COEFF_MSB_ANC2_IIR_COEFF_MSB_M 0x1 + + +/* -- For CDC_ANC2_IIR_COEFF_LSB */ +#define TIMPANI_A_CDC_ANC2_IIR_COEFF_LSB (0xD7) +#define TIMPANI_CDC_ANC2_IIR_COEFF_LSB_RWC "RW" +#define TIMPANI_CDC_ANC2_IIR_COEFF_LSB_POR 0 +#define TIMPANI_CDC_ANC2_IIR_COEFF_LSB_S 0 +#define TIMPANI_CDC_ANC2_IIR_COEFF_LSB_M 0xFF + + +#define TIMPANI_CDC_ANC2_IIR_COEFF_LSB_ANC2_IIR_COEFF_LSB_S 0 +#define TIMPANI_CDC_ANC2_IIR_COEFF_LSB_ANC2_IIR_COEFF_LSB_M 0xFF + + +/* -- For CDC_ANC2_IIR_COEFF_CTL */ +#define TIMPANI_A_CDC_ANC2_IIR_COEFF_CTL (0xD8) +#define TIMPANI_CDC_ANC2_IIR_COEFF_CTL_RWC "RW" +#define TIMPANI_CDC_ANC2_IIR_COEFF_CTL_POR 0 +#define TIMPANI_CDC_ANC2_IIR_COEFF_CTL_S 0 +#define TIMPANI_CDC_ANC2_IIR_COEFF_CTL_M 0x3 + + +#define TIMPANI_CDC_ANC2_IIR_COEFF_CTL_ANC2_IIR_COEFF_ADAPTIVE_S 1 +#define TIMPANI_CDC_ANC2_IIR_COEFF_CTL_ANC2_IIR_COEFF_ADAPTIVE_M 0x2 +#define TIMPANI_CDC_ANC2_IIR_COEFF_CTL_ANC2_IIR_COEFF_ADAPTIVE_ADAPTIVE 0x1 +#define TIMPANI_CDC_ANC2_IIR_COEFF_CTL_ANC2_IIR_COEFF_ADAPTIVE_NON_ADAPTIVE 0x0 + +#define TIMPANI_CDC_ANC2_IIR_COEFF_CTL_ANC2_IIR_COEFF_EN_S 0 +#define TIMPANI_CDC_ANC2_IIR_COEFF_CTL_ANC2_IIR_COEFF_EN_M 0x1 +#define TIMPANI_CDC_ANC2_IIR_COEFF_CTL_ANC2_IIR_COEFF_EN_UPDATE 0x1 +#define TIMPANI_CDC_ANC2_IIR_COEFF_CTL_ANC2_IIR_COEFF_EN_NO_UPDATE 0x0 + + +/* -- For CDC_ANC2_LPF_COEFF_PTR */ +#define TIMPANI_A_CDC_ANC2_LPF_COEFF_PTR (0xD9) +#define TIMPANI_CDC_ANC2_LPF_COEFF_PTR_RWC "RW" +#define TIMPANI_CDC_ANC2_LPF_COEFF_PTR_POR 0 +#define TIMPANI_CDC_ANC2_LPF_COEFF_PTR_S 0 +#define TIMPANI_CDC_ANC2_LPF_COEFF_PTR_M 0xF + + +#define TIMPANI_CDC_ANC2_LPF_COEFF_PTR_ANC2_LPF_COEFF_PTR_S 0 +#define TIMPANI_CDC_ANC2_LPF_COEFF_PTR_ANC2_LPF_COEFF_PTR_M 0xF + + +/* -- For CDC_ANC2_LPF_COEFF_MSB */ +#define TIMPANI_A_CDC_ANC2_LPF_COEFF_MSB (0xDA) +#define TIMPANI_CDC_ANC2_LPF_COEFF_MSB_RWC "RW" +#define TIMPANI_CDC_ANC2_LPF_COEFF_MSB_POR 0 +#define TIMPANI_CDC_ANC2_LPF_COEFF_MSB_S 0 +#define TIMPANI_CDC_ANC2_LPF_COEFF_MSB_M 0xF + + +#define TIMPANI_CDC_ANC2_LPF_COEFF_MSB_ANC2_LPF_COEFF_MSB_S 0 +#define TIMPANI_CDC_ANC2_LPF_COEFF_MSB_ANC2_LPF_COEFF_MSB_M 0xF + + +/* -- For CDC_ANC2_LPF_COEFF_LSB */ +#define TIMPANI_A_CDC_ANC2_LPF_COEFF_LSB (0xDB) +#define TIMPANI_CDC_ANC2_LPF_COEFF_LSB_RWC "RW" +#define TIMPANI_CDC_ANC2_LPF_COEFF_LSB_POR 0 +#define TIMPANI_CDC_ANC2_LPF_COEFF_LSB_S 0 +#define TIMPANI_CDC_ANC2_LPF_COEFF_LSB_M 0xFF + + +#define TIMPANI_CDC_ANC2_LPF_COEFF_LSB_ANC2_LPF_COEFF_LSB_S 0 +#define TIMPANI_CDC_ANC2_LPF_COEFF_LSB_ANC2_LPF_COEFF_LSB_M 0xFF + + +/* -- For CDC_ANC2_SCALE_PTR */ +#define TIMPANI_A_CDC_ANC2_SCALE_PTR (0xDC) +#define TIMPANI_CDC_ANC2_SCALE_PTR_RWC "RW" +#define TIMPANI_CDC_ANC2_SCALE_PTR_POR 0 +#define TIMPANI_CDC_ANC2_SCALE_PTR_S 0 +#define TIMPANI_CDC_ANC2_SCALE_PTR_M 0x7 + + +#define TIMPANI_CDC_ANC2_SCALE_PTR_ANC2_SCALE_PTR_S 0 +#define TIMPANI_CDC_ANC2_SCALE_PTR_ANC2_SCALE_PTR_M 0x7 + + +/* -- For CDC_ANC2_SCALE */ +#define TIMPANI_A_CDC_ANC2_SCALE (0xDD) +#define TIMPANI_CDC_ANC2_SCALE_RWC "RW" +#define TIMPANI_CDC_ANC2_SCALE_POR 0 +#define TIMPANI_CDC_ANC2_SCALE_S 0 +#define TIMPANI_CDC_ANC2_SCALE_M 0xFF + + +#define TIMPANI_CDC_ANC2_SCALE_ANC2_SCALE_S 0 +#define TIMPANI_CDC_ANC2_SCALE_ANC2_SCALE_M 0xFF + + +/* -- For CDC_ANC2_DEBUG */ +#define TIMPANI_A_CDC_ANC2_DEBUG (0xDE) +#define TIMPANI_CDC_ANC2_DEBUG_RWC "RW" +#define TIMPANI_CDC_ANC2_DEBUG_POR 0 +#define TIMPANI_CDC_ANC2_DEBUG_S 0 +#define TIMPANI_CDC_ANC2_DEBUG_M 0xF + + +#define TIMPANI_CDC_ANC2_DEBUG_ANC2_DEBUG_SEL_S 0 +#define TIMPANI_CDC_ANC2_DEBUG_ANC2_DEBUG_SEL_M 0xF + + +/* -- For CDC_LINE_L_AVOL */ +#define TIMPANI_A_CDC_LINE_L_AVOL (0xE0) +#define TIMPANI_CDC_LINE_L_AVOL_RWC "RW" +#define TIMPANI_CDC_LINE_L_AVOL_POR 0xac +#define TIMPANI_CDC_LINE_L_AVOL_S 0 +#define TIMPANI_CDC_LINE_L_AVOL_M 0xFF + + +#define TIMPANI_CDC_LINE_L_AVOL_USER_GAIN_S 2 +#define TIMPANI_CDC_LINE_L_AVOL_USER_GAIN_M 0xFC + +#define TIMPANI_CDC_LINE_L_AVOL_DUMMY_S 0 +#define TIMPANI_CDC_LINE_L_AVOL_DUMMY_M 0x3 + + +/* -- For CDC_LINE_R_AVOL */ +#define TIMPANI_A_CDC_LINE_R_AVOL (0xE1) +#define TIMPANI_CDC_LINE_R_AVOL_RWC "RW" +#define TIMPANI_CDC_LINE_R_AVOL_POR 0xac +#define TIMPANI_CDC_LINE_R_AVOL_S 0 +#define TIMPANI_CDC_LINE_R_AVOL_M 0xFF + + +#define TIMPANI_CDC_LINE_R_AVOL_USER_GAIN_S 2 +#define TIMPANI_CDC_LINE_R_AVOL_USER_GAIN_M 0xFC + +#define TIMPANI_CDC_LINE_R_AVOL_DUMMY_S 0 +#define TIMPANI_CDC_LINE_R_AVOL_DUMMY_M 0x3 + + +/* -- For CDC_HPH_L_AVOL */ +#define TIMPANI_A_CDC_HPH_L_AVOL (0xE2) +#define TIMPANI_CDC_HPH_L_AVOL_RWC "RW" +#define TIMPANI_CDC_HPH_L_AVOL_POR 0xae +#define TIMPANI_CDC_HPH_L_AVOL_S 0 +#define TIMPANI_CDC_HPH_L_AVOL_M 0xFF + + +#define TIMPANI_CDC_HPH_L_AVOL_USER_GAIN_S 2 +#define TIMPANI_CDC_HPH_L_AVOL_USER_GAIN_M 0xFC + +#define TIMPANI_CDC_HPH_L_AVOL_MUTE_S 1 +#define TIMPANI_CDC_HPH_L_AVOL_MUTE_M 0x2 +#define TIMPANI_CDC_HPH_L_AVOL_MUTE_MUTE 0x1 +#define TIMPANI_CDC_HPH_L_AVOL_MUTE_UNMUTE 0x0 + +#define TIMPANI_CDC_HPH_L_AVOL_DUMMY_S 0 +#define TIMPANI_CDC_HPH_L_AVOL_DUMMY_M 0x1 + + +/* -- For CDC_HPH_R_AVOL */ +#define TIMPANI_A_CDC_HPH_R_AVOL (0xE3) +#define TIMPANI_CDC_HPH_R_AVOL_RWC "RW" +#define TIMPANI_CDC_HPH_R_AVOL_POR 0xae +#define TIMPANI_CDC_HPH_R_AVOL_S 0 +#define TIMPANI_CDC_HPH_R_AVOL_M 0xFF + + +#define TIMPANI_CDC_HPH_R_AVOL_USER_GAIN_S 2 +#define TIMPANI_CDC_HPH_R_AVOL_USER_GAIN_M 0xFC + +#define TIMPANI_CDC_HPH_R_AVOL_MUTE_S 1 +#define TIMPANI_CDC_HPH_R_AVOL_MUTE_M 0x2 +#define TIMPANI_CDC_HPH_R_AVOL_MUTE_MUTE 0x1 +#define TIMPANI_CDC_HPH_R_AVOL_MUTE_UNMUTE 0x0 + +#define TIMPANI_CDC_HPH_R_AVOL_DUMMY_S 0 +#define TIMPANI_CDC_HPH_R_AVOL_DUMMY_M 0x1 + + +/* -- For CDC_COMP_CTL1 */ +#define TIMPANI_A_CDC_COMP_CTL1 (0xE4) +#define TIMPANI_CDC_COMP_CTL1_RWC "RW" +#define TIMPANI_CDC_COMP_CTL1_POR 0 +#define TIMPANI_CDC_COMP_CTL1_S 0 +#define TIMPANI_CDC_COMP_CTL1_M 0xFF + + +#define TIMPANI_CDC_COMP_CTL1_LO_CLK_EN_S 7 +#define TIMPANI_CDC_COMP_CTL1_LO_CLK_EN_M 0x80 + +#define TIMPANI_CDC_COMP_CTL1_HPH_CLK_EN_S 6 +#define TIMPANI_CDC_COMP_CTL1_HPH_CLK_EN_M 0x40 + +#define TIMPANI_CDC_COMP_CTL1_LO_SOFT_RESET_S 5 +#define TIMPANI_CDC_COMP_CTL1_LO_SOFT_RESET_M 0x20 + +#define TIMPANI_CDC_COMP_CTL1_HPH_SOFT_RESET_S 4 +#define TIMPANI_CDC_COMP_CTL1_HPH_SOFT_RESET_M 0x10 + +#define TIMPANI_CDC_COMP_CTL1_LO_R_EN_S 3 +#define TIMPANI_CDC_COMP_CTL1_LO_R_EN_M 0x8 + +#define TIMPANI_CDC_COMP_CTL1_LO_L_EN_S 2 +#define TIMPANI_CDC_COMP_CTL1_LO_L_EN_M 0x4 + +#define TIMPANI_CDC_COMP_CTL1_HPH_R_EN_S 1 +#define TIMPANI_CDC_COMP_CTL1_HPH_R_EN_M 0x2 + +#define TIMPANI_CDC_COMP_CTL1_HPH_L_EN_S 0 +#define TIMPANI_CDC_COMP_CTL1_HPH_L_EN_M 0x1 + + +/* -- For CDC_COMP_CTL2 */ +#define TIMPANI_A_CDC_COMP_CTL2 (0xE5) +#define TIMPANI_CDC_COMP_CTL2_RWC "RW" +#define TIMPANI_CDC_COMP_CTL2_POR 0xe +#define TIMPANI_CDC_COMP_CTL2_S 0 +#define TIMPANI_CDC_COMP_CTL2_M 0xF + + +#define TIMPANI_CDC_COMP_CTL2_LINEOUT_IN_MUX_S 2 +#define TIMPANI_CDC_COMP_CTL2_LINEOUT_IN_MUX_M 0xC + +#define TIMPANI_CDC_COMP_CTL2_HPH_IN_MUX_S 0 +#define TIMPANI_CDC_COMP_CTL2_HPH_IN_MUX_M 0x3 + + +/* -- For CDC_COMP_PEAK_METER */ +#define TIMPANI_A_CDC_COMP_PEAK_METER (0xE6) +#define TIMPANI_CDC_COMP_PEAK_METER_RWC "RW" +#define TIMPANI_CDC_COMP_PEAK_METER_POR 0x9 +#define TIMPANI_CDC_COMP_PEAK_METER_S 0 +#define TIMPANI_CDC_COMP_PEAK_METER_M 0xF + + +#define TIMPANI_CDC_COMP_PEAK_METER_TIME_OUT_S 0 +#define TIMPANI_CDC_COMP_PEAK_METER_TIME_OUT_M 0xF + + +/* -- For CDC_COMP_LEVEL_METER_CTL1 */ +#define TIMPANI_A_CDC_COMP_LEVEL_METER_CTL1 (0xE7) +#define TIMPANI_CDC_COMP_LEVEL_METER_CTL1_RWC "RW" +#define TIMPANI_CDC_COMP_LEVEL_METER_CTL1_POR 0x7 +#define TIMPANI_CDC_COMP_LEVEL_METER_CTL1_S 0 +#define TIMPANI_CDC_COMP_LEVEL_METER_CTL1_M 0xF + + +#define TIMPANI_CDC_COMP_LEVEL_METER_CTL1_DIV_FACTOR_S 0 +#define TIMPANI_CDC_COMP_LEVEL_METER_CTL1_DIV_FACTOR_M 0xF + + +/* -- For CDC_COMP_LEVEL_METER_CTL2 */ +#define TIMPANI_A_CDC_COMP_LEVEL_METER_CTL2 (0xE8) +#define TIMPANI_CDC_COMP_LEVEL_METER_CTL2_RWC "RW" +#define TIMPANI_CDC_COMP_LEVEL_METER_CTL2_POR 0x28 +#define TIMPANI_CDC_COMP_LEVEL_METER_CTL2_S 0 +#define TIMPANI_CDC_COMP_LEVEL_METER_CTL2_M 0xFF + + +#define TIMPANI_CDC_COMP_LEVEL_METER_CTL2_RESAMPLE_RATE_S 0 +#define TIMPANI_CDC_COMP_LEVEL_METER_CTL2_RESAMPLE_RATE_M 0xFF + + +/* -- For CDC_COMP_ZONE_SELECT */ +#define TIMPANI_A_CDC_COMP_ZONE_SELECT (0xE9) +#define TIMPANI_CDC_COMP_ZONE_SELECT_RWC "RW" +#define TIMPANI_CDC_COMP_ZONE_SELECT_POR 0x3b +#define TIMPANI_CDC_COMP_ZONE_SELECT_S 0 +#define TIMPANI_CDC_COMP_ZONE_SELECT_M 0x7F + + +#define TIMPANI_CDC_COMP_ZONE_SELECT_ENTRY_S 3 +#define TIMPANI_CDC_COMP_ZONE_SELECT_ENTRY_M 0x78 + +#define TIMPANI_CDC_COMP_ZONE_SELECT_SHIFT_S 0 +#define TIMPANI_CDC_COMP_ZONE_SELECT_SHIFT_M 0x7 + + +/* -- For CDC_COMP_ZC_MSB */ +#define TIMPANI_A_CDC_COMP_ZC_MSB (0xEA) +#define TIMPANI_CDC_COMP_ZC_MSB_RWC "RW" +#define TIMPANI_CDC_COMP_ZC_MSB_POR 0 +#define TIMPANI_CDC_COMP_ZC_MSB_S 0 +#define TIMPANI_CDC_COMP_ZC_MSB_M 0x7 + + +#define TIMPANI_CDC_COMP_ZC_MSB_DET_WINDOW_S 0 +#define TIMPANI_CDC_COMP_ZC_MSB_DET_WINDOW_M 0x7 + + +/* -- For CDC_COMP_ZC_LSB */ +#define TIMPANI_A_CDC_COMP_ZC_LSB (0xEB) +#define TIMPANI_CDC_COMP_ZC_LSB_RWC "RW" +#define TIMPANI_CDC_COMP_ZC_LSB_POR 0x1f +#define TIMPANI_CDC_COMP_ZC_LSB_S 0 +#define TIMPANI_CDC_COMP_ZC_LSB_M 0xFF + + +#define TIMPANI_CDC_COMP_ZC_LSB_DET_WINDOW_S 0 +#define TIMPANI_CDC_COMP_ZC_LSB_DET_WINDOW_M 0xFF + + +/* -- For CDC_COMP_SHUT_DOWN */ +#define TIMPANI_A_CDC_COMP_SHUT_DOWN (0xEC) +#define TIMPANI_CDC_COMP_SHUT_DOWN_RWC "RW" +#define TIMPANI_CDC_COMP_SHUT_DOWN_POR 0x1b +#define TIMPANI_CDC_COMP_SHUT_DOWN_S 0 +#define TIMPANI_CDC_COMP_SHUT_DOWN_M 0x3F + + +#define TIMPANI_CDC_COMP_SHUT_DOWN_HPH_TIMEOUT_S 3 +#define TIMPANI_CDC_COMP_SHUT_DOWN_HPH_TIMEOUT_M 0x38 + +#define TIMPANI_CDC_COMP_SHUT_DOWN_LO_TIMEOUT_S 0 +#define TIMPANI_CDC_COMP_SHUT_DOWN_LO_TIMEOUT_M 0x7 + + +/* -- For CDC_COMP_SHUT_DOWN_STATUS */ +#define TIMPANI_A_CDC_COMP_SHUT_DOWN_STATUS (0xED) +#define TIMPANI_CDC_COMP_SHUT_DOWN_STATUS_RWC "RW" +#define TIMPANI_CDC_COMP_SHUT_DOWN_STATUS_POR 0 +#define TIMPANI_CDC_COMP_SHUT_DOWN_STATUS_S 0 +#define TIMPANI_CDC_COMP_SHUT_DOWN_STATUS_M 0xF + + +#define TIMPANI_CDC_COMP_SHUT_DOWN_STATUS_LO_R_S 3 +#define TIMPANI_CDC_COMP_SHUT_DOWN_STATUS_LO_R_M 0x8 + +#define TIMPANI_CDC_COMP_SHUT_DOWN_STATUS_LO_L_S 2 +#define TIMPANI_CDC_COMP_SHUT_DOWN_STATUS_LO_L_M 0x4 + +#define TIMPANI_CDC_COMP_SHUT_DOWN_STATUS_HPH_R_S 1 +#define TIMPANI_CDC_COMP_SHUT_DOWN_STATUS_HPH_R_M 0x2 + +#define TIMPANI_CDC_COMP_SHUT_DOWN_STATUS_HPH_L_S 0 +#define TIMPANI_CDC_COMP_SHUT_DOWN_STATUS_HPH_L_M 0x1 + + +/* -- For CDC_COMP_HALT */ +#define TIMPANI_A_CDC_COMP_HALT (0xEE) +#define TIMPANI_CDC_COMP_HALT_RWC "RW" +#define TIMPANI_CDC_COMP_HALT_POR 0 +#define TIMPANI_CDC_COMP_HALT_S 0 +#define TIMPANI_CDC_COMP_HALT_M 0x1 + + +#define TIMPANI_CDC_COMP_HALT_COMPANDER_HALT_S 0 +#define TIMPANI_CDC_COMP_HALT_COMPANDER_HALT_M 0x1 + + +#endif diff --git a/original-kernel-headers/linux/videodev2.h b/original-kernel-headers/linux/videodev2.h new file mode 100644 index 0000000..e616e10 --- /dev/null +++ b/original-kernel-headers/linux/videodev2.h @@ -0,0 +1,2688 @@ +/* + * Video for Linux Two header file + * + * Copyright (C) 1999-2007 the contributors + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Alternatively you can redistribute this file under the terms of the + * BSD license as stated below: + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. The names of its contributors may not be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Header file for v4l or V4L2 drivers and applications + * with public API. + * All kernel-specific stuff were moved to media/v4l2-dev.h, so + * no #if __KERNEL tests are allowed here + * + * See http://linuxtv.org for more info + * + * Author: Bill Dirks <bill@thedirks.org> + * Justin Schoeman + * Hans Verkuil <hverkuil@xs4all.nl> + * et al. + */ +#ifndef __LINUX_VIDEODEV2_H +#define __LINUX_VIDEODEV2_H + +#ifdef __KERNEL__ +#include <linux/time.h> /* need struct timeval */ +#else +#include <sys/time.h> +#endif +#include <linux/compiler.h> +#include <linux/ioctl.h> +#include <linux/types.h> + +/* + * Common stuff for both V4L1 and V4L2 + * Moved from videodev.h + */ +#define VIDEO_MAX_FRAME 32 +#define VIDEO_MAX_PLANES 8 + +#ifndef __KERNEL__ + +/* These defines are V4L1 specific and should not be used with the V4L2 API! + They will be removed from this header in the future. */ + +#define VID_TYPE_CAPTURE 1 /* Can capture */ +#define VID_TYPE_TUNER 2 /* Can tune */ +#define VID_TYPE_TELETEXT 4 /* Does teletext */ +#define VID_TYPE_OVERLAY 8 /* Overlay onto frame buffer */ +#define VID_TYPE_CHROMAKEY 16 /* Overlay by chromakey */ +#define VID_TYPE_CLIPPING 32 /* Can clip */ +#define VID_TYPE_FRAMERAM 64 /* Uses the frame buffer memory */ +#define VID_TYPE_SCALES 128 /* Scalable */ +#define VID_TYPE_MONOCHROME 256 /* Monochrome only */ +#define VID_TYPE_SUBCAPTURE 512 /* Can capture subareas of the image */ +#define VID_TYPE_MPEG_DECODER 1024 /* Can decode MPEG streams */ +#define VID_TYPE_MPEG_ENCODER 2048 /* Can encode MPEG streams */ +#define VID_TYPE_MJPEG_DECODER 4096 /* Can decode MJPEG streams */ +#define VID_TYPE_MJPEG_ENCODER 8192 /* Can encode MJPEG streams */ +#endif + +/* + * M I S C E L L A N E O U S + */ + +/* Four-character-code (FOURCC) */ +#define v4l2_fourcc(a, b, c, d)\ + ((__u32)(a) | ((__u32)(b) << 8) | ((__u32)(c) << 16) | ((__u32)(d) << 24)) + +/* + * E N U M S + */ +enum v4l2_field { + V4L2_FIELD_ANY = 0, /* driver can choose from none, + top, bottom, interlaced + depending on whatever it thinks + is approximate ... */ + V4L2_FIELD_NONE = 1, /* this device has no fields ... */ + V4L2_FIELD_TOP = 2, /* top field only */ + V4L2_FIELD_BOTTOM = 3, /* bottom field only */ + V4L2_FIELD_INTERLACED = 4, /* both fields interlaced */ + V4L2_FIELD_SEQ_TB = 5, /* both fields sequential into one + buffer, top-bottom order */ + V4L2_FIELD_SEQ_BT = 6, /* same as above + bottom-top order */ + V4L2_FIELD_ALTERNATE = 7, /* both fields alternating into + separate buffers */ + V4L2_FIELD_INTERLACED_TB = 8, /* both fields interlaced, top field + first and the top field is + transmitted first */ + V4L2_FIELD_INTERLACED_BT = 9, /* both fields interlaced, top field + first and the bottom field is + transmitted first */ +}; +#define V4L2_FIELD_HAS_TOP(field) \ + ((field) == V4L2_FIELD_TOP ||\ + (field) == V4L2_FIELD_INTERLACED ||\ + (field) == V4L2_FIELD_INTERLACED_TB ||\ + (field) == V4L2_FIELD_INTERLACED_BT ||\ + (field) == V4L2_FIELD_SEQ_TB ||\ + (field) == V4L2_FIELD_SEQ_BT) +#define V4L2_FIELD_HAS_BOTTOM(field) \ + ((field) == V4L2_FIELD_BOTTOM ||\ + (field) == V4L2_FIELD_INTERLACED ||\ + (field) == V4L2_FIELD_INTERLACED_TB ||\ + (field) == V4L2_FIELD_INTERLACED_BT ||\ + (field) == V4L2_FIELD_SEQ_TB ||\ + (field) == V4L2_FIELD_SEQ_BT) +#define V4L2_FIELD_HAS_BOTH(field) \ + ((field) == V4L2_FIELD_INTERLACED ||\ + (field) == V4L2_FIELD_INTERLACED_TB ||\ + (field) == V4L2_FIELD_INTERLACED_BT ||\ + (field) == V4L2_FIELD_SEQ_TB ||\ + (field) == V4L2_FIELD_SEQ_BT) + +enum v4l2_buf_type { + V4L2_BUF_TYPE_VIDEO_CAPTURE = 1, + V4L2_BUF_TYPE_VIDEO_OUTPUT = 2, + V4L2_BUF_TYPE_VIDEO_OVERLAY = 3, + V4L2_BUF_TYPE_VBI_CAPTURE = 4, + V4L2_BUF_TYPE_VBI_OUTPUT = 5, + V4L2_BUF_TYPE_SLICED_VBI_CAPTURE = 6, + V4L2_BUF_TYPE_SLICED_VBI_OUTPUT = 7, +#if 1 + /* Experimental */ + V4L2_BUF_TYPE_VIDEO_OUTPUT_OVERLAY = 8, +#endif + V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE = 9, + V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE = 10, + V4L2_BUF_TYPE_PRIVATE = 0x80, +}; + +#define V4L2_TYPE_IS_MULTIPLANAR(type) \ + ((type) == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE \ + || (type) == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) + +#define V4L2_TYPE_IS_OUTPUT(type) \ + ((type) == V4L2_BUF_TYPE_VIDEO_OUTPUT \ + || (type) == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE \ + || (type) == V4L2_BUF_TYPE_VIDEO_OVERLAY \ + || (type) == V4L2_BUF_TYPE_VIDEO_OUTPUT_OVERLAY \ + || (type) == V4L2_BUF_TYPE_VBI_OUTPUT \ + || (type) == V4L2_BUF_TYPE_SLICED_VBI_OUTPUT) + +enum v4l2_tuner_type { + V4L2_TUNER_RADIO = 1, + V4L2_TUNER_ANALOG_TV = 2, + V4L2_TUNER_DIGITAL_TV = 3, +}; + +enum v4l2_memory { + V4L2_MEMORY_MMAP = 1, + V4L2_MEMORY_USERPTR = 2, + V4L2_MEMORY_OVERLAY = 3, +}; + +/* see also http://vektor.theorem.ca/graphics/ycbcr/ */ +enum v4l2_colorspace { + /* ITU-R 601 -- broadcast NTSC/PAL */ + V4L2_COLORSPACE_SMPTE170M = 1, + + /* 1125-Line (US) HDTV */ + V4L2_COLORSPACE_SMPTE240M = 2, + + /* HD and modern captures. */ + V4L2_COLORSPACE_REC709 = 3, + + /* broken BT878 extents (601, luma range 16-253 instead of 16-235) */ + V4L2_COLORSPACE_BT878 = 4, + + /* These should be useful. Assume 601 extents. */ + V4L2_COLORSPACE_470_SYSTEM_M = 5, + V4L2_COLORSPACE_470_SYSTEM_BG = 6, + + /* I know there will be cameras that send this. So, this is + * unspecified chromaticities and full 0-255 on each of the + * Y'CbCr components + */ + V4L2_COLORSPACE_JPEG = 7, + + /* For RGB colourspaces, this is probably a good start. */ + V4L2_COLORSPACE_SRGB = 8, +}; + +enum v4l2_priority { + V4L2_PRIORITY_UNSET = 0, /* not initialized */ + V4L2_PRIORITY_BACKGROUND = 1, + V4L2_PRIORITY_INTERACTIVE = 2, + V4L2_PRIORITY_RECORD = 3, + V4L2_PRIORITY_DEFAULT = V4L2_PRIORITY_INTERACTIVE, +}; + +struct v4l2_rect { + __s32 left; + __s32 top; + __s32 width; + __s32 height; +}; + +struct v4l2_fract { + __u32 numerator; + __u32 denominator; +}; + +/** + * struct v4l2_capability - Describes V4L2 device caps returned by VIDIOC_QUERYCAP + * + * @driver: name of the driver module (e.g. "bttv") + * @card: name of the card (e.g. "Hauppauge WinTV") + * @bus_info: name of the bus (e.g. "PCI:" + pci_name(pci_dev) ) + * @version: KERNEL_VERSION + * @capabilities: capabilities of the physical device as a whole + * @device_caps: capabilities accessed via this particular device (node) + * @reserved: reserved fields for future extensions + */ +struct v4l2_capability { + __u8 driver[16]; + __u8 card[32]; + __u8 bus_info[32]; + __u32 version; + __u32 capabilities; + __u32 device_caps; + __u32 reserved[3]; +}; + +/* Values for 'capabilities' field */ +#define V4L2_CAP_VIDEO_CAPTURE 0x00000001 /* Is a video capture device */ +#define V4L2_CAP_VIDEO_OUTPUT 0x00000002 /* Is a video output device */ +#define V4L2_CAP_VIDEO_OVERLAY 0x00000004 /* Can do video overlay */ +#define V4L2_CAP_VBI_CAPTURE 0x00000010 /* Is a raw VBI capture device */ +#define V4L2_CAP_VBI_OUTPUT 0x00000020 /* Is a raw VBI output device */ +#define V4L2_CAP_SLICED_VBI_CAPTURE 0x00000040 /* Is a sliced VBI capture device */ +#define V4L2_CAP_SLICED_VBI_OUTPUT 0x00000080 /* Is a sliced VBI output device */ +#define V4L2_CAP_RDS_CAPTURE 0x00000100 /* RDS data capture */ +#define V4L2_CAP_VIDEO_OUTPUT_OVERLAY 0x00000200 /* Can do video output overlay */ +#define V4L2_CAP_HW_FREQ_SEEK 0x00000400 /* Can do hardware frequency seek */ +#define V4L2_CAP_RDS_OUTPUT 0x00000800 /* Is an RDS encoder */ + +/* Is a video capture device that supports multiplanar formats */ +#define V4L2_CAP_VIDEO_CAPTURE_MPLANE 0x00001000 +/* Is a video output device that supports multiplanar formats */ +#define V4L2_CAP_VIDEO_OUTPUT_MPLANE 0x00002000 + +#define V4L2_CAP_TUNER 0x00010000 /* has a tuner */ +#define V4L2_CAP_AUDIO 0x00020000 /* has audio support */ +#define V4L2_CAP_RADIO 0x00040000 /* is a radio device */ +#define V4L2_CAP_MODULATOR 0x00080000 /* has a modulator */ + +#define V4L2_CAP_READWRITE 0x01000000 /* read/write systemcalls */ +#define V4L2_CAP_ASYNCIO 0x02000000 /* async I/O */ +#define V4L2_CAP_STREAMING 0x04000000 /* streaming I/O ioctls */ + +#define V4L2_CAP_DEVICE_CAPS 0x80000000 /* sets device capabilities field */ + +/* + * V I D E O I M A G E F O R M A T + */ +struct v4l2_pix_format { + __u32 width; + __u32 height; + __u32 pixelformat; + enum v4l2_field field; + __u32 bytesperline; /* for padding, zero if unused */ + __u32 sizeimage; + enum v4l2_colorspace colorspace; + __u32 priv; /* private data, depends on pixelformat */ +}; + +/* Pixel format FOURCC depth Description */ + +/* RGB formats */ +#define V4L2_PIX_FMT_RGB332 v4l2_fourcc('R', 'G', 'B', '1') /* 8 RGB-3-3-2 */ +#define V4L2_PIX_FMT_RGB444 v4l2_fourcc('R', '4', '4', '4') /* 16 xxxxrrrr ggggbbbb */ +#define V4L2_PIX_FMT_RGB555 v4l2_fourcc('R', 'G', 'B', 'O') /* 16 RGB-5-5-5 */ +#define V4L2_PIX_FMT_RGB565 v4l2_fourcc('R', 'G', 'B', 'P') /* 16 RGB-5-6-5 */ +#define V4L2_PIX_FMT_RGB555X v4l2_fourcc('R', 'G', 'B', 'Q') /* 16 RGB-5-5-5 BE */ +#define V4L2_PIX_FMT_RGB565X v4l2_fourcc('R', 'G', 'B', 'R') /* 16 RGB-5-6-5 BE */ +#define V4L2_PIX_FMT_BGR666 v4l2_fourcc('B', 'G', 'R', 'H') /* 18 BGR-6-6-6 */ +#define V4L2_PIX_FMT_BGR24 v4l2_fourcc('B', 'G', 'R', '3') /* 24 BGR-8-8-8 */ +#define V4L2_PIX_FMT_RGB24 v4l2_fourcc('R', 'G', 'B', '3') /* 24 RGB-8-8-8 */ +#define V4L2_PIX_FMT_BGR32 v4l2_fourcc('B', 'G', 'R', '4') /* 32 BGR-8-8-8-8 */ +#define V4L2_PIX_FMT_RGB32 v4l2_fourcc('R', 'G', 'B', '4') /* 32 RGB-8-8-8-8 */ + +/* Grey formats */ +#define V4L2_PIX_FMT_GREY v4l2_fourcc('G', 'R', 'E', 'Y') /* 8 Greyscale */ +#define V4L2_PIX_FMT_Y4 v4l2_fourcc('Y', '0', '4', ' ') /* 4 Greyscale */ +#define V4L2_PIX_FMT_Y6 v4l2_fourcc('Y', '0', '6', ' ') /* 6 Greyscale */ +#define V4L2_PIX_FMT_Y10 v4l2_fourcc('Y', '1', '0', ' ') /* 10 Greyscale */ +#define V4L2_PIX_FMT_Y12 v4l2_fourcc('Y', '1', '2', ' ') /* 12 Greyscale */ +#define V4L2_PIX_FMT_Y16 v4l2_fourcc('Y', '1', '6', ' ') /* 16 Greyscale */ + +/* Grey bit-packed formats */ +#define V4L2_PIX_FMT_Y10BPACK v4l2_fourcc('Y', '1', '0', 'B') /* 10 Greyscale bit-packed */ + +/* Palette formats */ +#define V4L2_PIX_FMT_PAL8 v4l2_fourcc('P', 'A', 'L', '8') /* 8 8-bit palette */ + +/* Luminance+Chrominance formats */ +#define V4L2_PIX_FMT_YVU410 v4l2_fourcc('Y', 'V', 'U', '9') /* 9 YVU 4:1:0 */ +#define V4L2_PIX_FMT_YVU420 v4l2_fourcc('Y', 'V', '1', '2') /* 12 YVU 4:2:0 */ +#define V4L2_PIX_FMT_YUYV v4l2_fourcc('Y', 'U', 'Y', 'V') /* 16 YUV 4:2:2 */ +#define V4L2_PIX_FMT_YYUV v4l2_fourcc('Y', 'Y', 'U', 'V') /* 16 YUV 4:2:2 */ +#define V4L2_PIX_FMT_YVYU v4l2_fourcc('Y', 'V', 'Y', 'U') /* 16 YVU 4:2:2 */ +#define V4L2_PIX_FMT_UYVY v4l2_fourcc('U', 'Y', 'V', 'Y') /* 16 YUV 4:2:2 */ +#define V4L2_PIX_FMT_VYUY v4l2_fourcc('V', 'Y', 'U', 'Y') /* 16 YUV 4:2:2 */ +#define V4L2_PIX_FMT_YUV422P v4l2_fourcc('4', '2', '2', 'P') /* 16 YVU422 planar */ +#define V4L2_PIX_FMT_YUV411P v4l2_fourcc('4', '1', '1', 'P') /* 16 YVU411 planar */ +#define V4L2_PIX_FMT_Y41P v4l2_fourcc('Y', '4', '1', 'P') /* 12 YUV 4:1:1 */ +#define V4L2_PIX_FMT_YUV444 v4l2_fourcc('Y', '4', '4', '4') /* 16 xxxxyyyy uuuuvvvv */ +#define V4L2_PIX_FMT_YUV555 v4l2_fourcc('Y', 'U', 'V', 'O') /* 16 YUV-5-5-5 */ +#define V4L2_PIX_FMT_YUV565 v4l2_fourcc('Y', 'U', 'V', 'P') /* 16 YUV-5-6-5 */ +#define V4L2_PIX_FMT_YUV32 v4l2_fourcc('Y', 'U', 'V', '4') /* 32 YUV-8-8-8-8 */ +#define V4L2_PIX_FMT_YUV410 v4l2_fourcc('Y', 'U', 'V', '9') /* 9 YUV 4:1:0 */ +#define V4L2_PIX_FMT_YUV420 v4l2_fourcc('Y', 'U', '1', '2') /* 12 YUV 4:2:0 */ +#define V4L2_PIX_FMT_HI240 v4l2_fourcc('H', 'I', '2', '4') /* 8 8-bit color */ +#define V4L2_PIX_FMT_HM12 v4l2_fourcc('H', 'M', '1', '2') /* 8 YUV 4:2:0 16x16 macroblocks */ +#define V4L2_PIX_FMT_M420 v4l2_fourcc('M', '4', '2', '0') /* 12 YUV 4:2:0 2 lines y, 1 line uv interleaved */ + +/* two planes -- one Y, one Cr + Cb interleaved */ +#define V4L2_PIX_FMT_NV12 v4l2_fourcc('N', 'V', '1', '2') /* 12 Y/CbCr 4:2:0 */ +#define V4L2_PIX_FMT_NV21 v4l2_fourcc('N', 'V', '2', '1') /* 12 Y/CrCb 4:2:0 */ +#define V4L2_PIX_FMT_NV16 v4l2_fourcc('N', 'V', '1', '6') /* 16 Y/CbCr 4:2:2 */ +#define V4L2_PIX_FMT_NV61 v4l2_fourcc('N', 'V', '6', '1') /* 16 Y/CrCb 4:2:2 */ +#define V4L2_PIX_FMT_NV24 v4l2_fourcc('N', 'V', '2', '4') /* 24 Y/CbCr 4:4:4 */ +#define V4L2_PIX_FMT_NV42 v4l2_fourcc('N', 'V', '4', '2') /* 24 Y/CrCb 4:4:4 */ + +/* two non contiguous planes - one Y, one Cr + Cb interleaved */ +#define V4L2_PIX_FMT_NV12M v4l2_fourcc('N', 'M', '1', '2') /* 12 Y/CbCr 4:2:0 */ +#define V4L2_PIX_FMT_NV12MT v4l2_fourcc('T', 'M', '1', '2') /* 12 Y/CbCr 4:2:0 64x32 macroblocks */ + +/* three non contiguous planes - Y, Cb, Cr */ +#define V4L2_PIX_FMT_YUV420M v4l2_fourcc('Y', 'M', '1', '2') /* 12 YUV420 planar */ + +/* Bayer formats - see http://www.siliconimaging.com/RGB%20Bayer.htm */ +#define V4L2_PIX_FMT_SBGGR8 v4l2_fourcc('B', 'A', '8', '1') /* 8 BGBG.. GRGR.. */ +#define V4L2_PIX_FMT_SGBRG8 v4l2_fourcc('G', 'B', 'R', 'G') /* 8 GBGB.. RGRG.. */ +#define V4L2_PIX_FMT_SGRBG8 v4l2_fourcc('G', 'R', 'B', 'G') /* 8 GRGR.. BGBG.. */ +#define V4L2_PIX_FMT_SRGGB8 v4l2_fourcc('R', 'G', 'G', 'B') /* 8 RGRG.. GBGB.. */ +#define V4L2_PIX_FMT_SBGGR10 v4l2_fourcc('B', 'G', '1', '0') /* 10 BGBG.. GRGR.. */ +#define V4L2_PIX_FMT_SGBRG10 v4l2_fourcc('G', 'B', '1', '0') /* 10 GBGB.. RGRG.. */ +#define V4L2_PIX_FMT_SGRBG10 v4l2_fourcc('B', 'A', '1', '0') /* 10 GRGR.. BGBG.. */ +#define V4L2_PIX_FMT_SRGGB10 v4l2_fourcc('R', 'G', '1', '0') /* 10 RGRG.. GBGB.. */ +#define V4L2_PIX_FMT_SBGGR12 v4l2_fourcc('B', 'G', '1', '2') /* 12 BGBG.. GRGR.. */ +#define V4L2_PIX_FMT_SGBRG12 v4l2_fourcc('G', 'B', '1', '2') /* 12 GBGB.. RGRG.. */ +#define V4L2_PIX_FMT_SGRBG12 v4l2_fourcc('B', 'A', '1', '2') /* 12 GRGR.. BGBG.. */ +#define V4L2_PIX_FMT_SRGGB12 v4l2_fourcc('R', 'G', '1', '2') /* 12 RGRG.. GBGB.. */ + /* 10bit raw bayer DPCM compressed to 8 bits */ +#define V4L2_PIX_FMT_SGRBG10DPCM8 v4l2_fourcc('B', 'D', '1', '0') + /* + * 10bit raw bayer, expanded to 16 bits + * xxxxrrrrrrrrrrxxxxgggggggggg xxxxggggggggggxxxxbbbbbbbbbb... + */ +#define V4L2_PIX_FMT_SBGGR16 v4l2_fourcc('B', 'Y', 'R', '2') /* 16 BGBG.. GRGR.. */ + +/* compressed formats */ +#define V4L2_PIX_FMT_MJPEG v4l2_fourcc('M', 'J', 'P', 'G') /* Motion-JPEG */ +#define V4L2_PIX_FMT_JPEG v4l2_fourcc('J', 'P', 'E', 'G') /* JFIF JPEG */ +#define V4L2_PIX_FMT_DV v4l2_fourcc('d', 'v', 's', 'd') /* 1394 */ +#define V4L2_PIX_FMT_MPEG v4l2_fourcc('M', 'P', 'E', 'G') /* MPEG-1/2/4 Multiplexed */ +#define V4L2_PIX_FMT_H264 v4l2_fourcc('H', '2', '6', '4') /* H264 with start codes */ +#define V4L2_PIX_FMT_H264_NO_SC v4l2_fourcc('A', 'V', 'C', '1') /* H264 without start codes */ +#define V4L2_PIX_FMT_H263 v4l2_fourcc('H', '2', '6', '3') /* H263 */ +#define V4L2_PIX_FMT_MPEG1 v4l2_fourcc('M', 'P', 'G', '1') /* MPEG-1 ES */ +#define V4L2_PIX_FMT_MPEG2 v4l2_fourcc('M', 'P', 'G', '2') /* MPEG-2 ES */ +#define V4L2_PIX_FMT_MPEG4 v4l2_fourcc('M', 'P', 'G', '4') /* MPEG-4 ES */ +#define V4L2_PIX_FMT_XVID v4l2_fourcc('X', 'V', 'I', 'D') /* Xvid */ +#define V4L2_PIX_FMT_VC1_ANNEX_G v4l2_fourcc('V', 'C', '1', 'G') /* SMPTE 421M Annex G compliant stream */ +#define V4L2_PIX_FMT_VC1_ANNEX_L v4l2_fourcc('V', 'C', '1', 'L') /* SMPTE 421M Annex L compliant stream */ +#define V4L2_PIX_FMT_DIVX_311 v4l2_fourcc('D', 'I', 'V', '3') /* DIVX311 */ +#define V4L2_PIX_FMT_DIVX v4l2_fourcc('D', 'I', 'V', 'X') /* DIVX */ +#define V4L2_PIX_FMT_VP8 v4l2_fourcc('V', 'P', '8', '0') /* ON2 VP8 stream */ +#define V4L2_PIX_FMT_HEVC v4l2_fourcc('H', 'E', 'V', 'C') /* for HEVC stream */ + +/* Vendor-specific formats */ +#define V4L2_PIX_FMT_CPIA1 v4l2_fourcc('C', 'P', 'I', 'A') /* cpia1 YUV */ +#define V4L2_PIX_FMT_WNVA v4l2_fourcc('W', 'N', 'V', 'A') /* Winnov hw compress */ +#define V4L2_PIX_FMT_SN9C10X v4l2_fourcc('S', '9', '1', '0') /* SN9C10x compression */ +#define V4L2_PIX_FMT_SN9C20X_I420 v4l2_fourcc('S', '9', '2', '0') /* SN9C20x YUV 4:2:0 */ +#define V4L2_PIX_FMT_PWC1 v4l2_fourcc('P', 'W', 'C', '1') /* pwc older webcam */ +#define V4L2_PIX_FMT_PWC2 v4l2_fourcc('P', 'W', 'C', '2') /* pwc newer webcam */ +#define V4L2_PIX_FMT_ET61X251 v4l2_fourcc('E', '6', '2', '5') /* ET61X251 compression */ +#define V4L2_PIX_FMT_SPCA501 v4l2_fourcc('S', '5', '0', '1') /* YUYV per line */ +#define V4L2_PIX_FMT_SPCA505 v4l2_fourcc('S', '5', '0', '5') /* YYUV per line */ +#define V4L2_PIX_FMT_SPCA508 v4l2_fourcc('S', '5', '0', '8') /* YUVY per line */ +#define V4L2_PIX_FMT_SPCA561 v4l2_fourcc('S', '5', '6', '1') /* compressed GBRG bayer */ +#define V4L2_PIX_FMT_PAC207 v4l2_fourcc('P', '2', '0', '7') /* compressed BGGR bayer */ +#define V4L2_PIX_FMT_MR97310A v4l2_fourcc('M', '3', '1', '0') /* compressed BGGR bayer */ +#define V4L2_PIX_FMT_JL2005BCD v4l2_fourcc('J', 'L', '2', '0') /* compressed RGGB bayer */ +#define V4L2_PIX_FMT_SN9C2028 v4l2_fourcc('S', 'O', 'N', 'X') /* compressed GBRG bayer */ +#define V4L2_PIX_FMT_SQ905C v4l2_fourcc('9', '0', '5', 'C') /* compressed RGGB bayer */ +#define V4L2_PIX_FMT_PJPG v4l2_fourcc('P', 'J', 'P', 'G') /* Pixart 73xx JPEG */ +#define V4L2_PIX_FMT_OV511 v4l2_fourcc('O', '5', '1', '1') /* ov511 JPEG */ +#define V4L2_PIX_FMT_OV518 v4l2_fourcc('O', '5', '1', '8') /* ov518 JPEG */ +#define V4L2_PIX_FMT_STV0680 v4l2_fourcc('S', '6', '8', '0') /* stv0680 bayer */ +#define V4L2_PIX_FMT_TM6000 v4l2_fourcc('T', 'M', '6', '0') /* tm5600/tm60x0 */ +#define V4L2_PIX_FMT_CIT_YYVYUY v4l2_fourcc('C', 'I', 'T', 'V') /* one line of Y then 1 line of VYUY */ +#define V4L2_PIX_FMT_KONICA420 v4l2_fourcc('K', 'O', 'N', 'I') /* YUV420 planar in blocks of 256 pixels */ +#define V4L2_PIX_FMT_JPGL v4l2_fourcc('J', 'P', 'G', 'L') /* JPEG-Lite */ +/* se401 janggu compressed rgb */ +#define V4L2_PIX_FMT_SE401 v4l2_fourcc('S', '4', '0', '1') +/* Composite stats */ +#define V4L2_PIX_FMT_STATS_COMB v4l2_fourcc('S', 'T', 'C', 'M') +/* AEC stats */ +#define V4L2_PIX_FMT_STATS_AE v4l2_fourcc('S', 'T', 'A', 'E') +/* AF stats */ +#define V4L2_PIX_FMT_STATS_AF v4l2_fourcc('S', 'T', 'A', 'F') +/* AWB stats */ +#define V4L2_PIX_FMT_STATS_AWB v4l2_fourcc('S', 'T', 'W', 'B') +/* IHIST stats */ +#define V4L2_PIX_FMT_STATS_IHST v4l2_fourcc('I', 'H', 'S', 'T') +/* Column count stats */ +#define V4L2_PIX_FMT_STATS_CS v4l2_fourcc('S', 'T', 'C', 'S') +/* Row count stats */ +#define V4L2_PIX_FMT_STATS_RS v4l2_fourcc('S', 'T', 'R', 'S') +/* Bayer Grid stats */ +#define V4L2_PIX_FMT_STATS_BG v4l2_fourcc('S', 'T', 'B', 'G') +/* Bayer focus stats */ +#define V4L2_PIX_FMT_STATS_BF v4l2_fourcc('S', 'T', 'B', 'F') +/* Bayer hist stats */ +#define V4L2_PIX_FMT_STATS_BHST v4l2_fourcc('B', 'H', 'S', 'T') + +/* + * F O R M A T E N U M E R A T I O N + */ +struct v4l2_fmtdesc { + __u32 index; /* Format number */ + enum v4l2_buf_type type; /* buffer type */ + __u32 flags; + __u8 description[32]; /* Description string */ + __u32 pixelformat; /* Format fourcc */ + __u32 reserved[4]; +}; + +#define V4L2_FMT_FLAG_COMPRESSED 0x0001 +#define V4L2_FMT_FLAG_EMULATED 0x0002 + +#if 1 + /* Experimental Frame Size and frame rate enumeration */ +/* + * F R A M E S I Z E E N U M E R A T I O N + */ +enum v4l2_frmsizetypes { + V4L2_FRMSIZE_TYPE_DISCRETE = 1, + V4L2_FRMSIZE_TYPE_CONTINUOUS = 2, + V4L2_FRMSIZE_TYPE_STEPWISE = 3, +}; + +struct v4l2_frmsize_discrete { + __u32 width; /* Frame width [pixel] */ + __u32 height; /* Frame height [pixel] */ +}; + +struct v4l2_frmsize_stepwise { + __u32 min_width; /* Minimum frame width [pixel] */ + __u32 max_width; /* Maximum frame width [pixel] */ + __u32 step_width; /* Frame width step size [pixel] */ + __u32 min_height; /* Minimum frame height [pixel] */ + __u32 max_height; /* Maximum frame height [pixel] */ + __u32 step_height; /* Frame height step size [pixel] */ +}; + +struct v4l2_frmsizeenum { + __u32 index; /* Frame size number */ + __u32 pixel_format; /* Pixel format */ + __u32 type; /* Frame size type the device supports. */ + + union { /* Frame size */ + struct v4l2_frmsize_discrete discrete; + struct v4l2_frmsize_stepwise stepwise; + }; + + __u32 reserved[2]; /* Reserved space for future use */ +}; + +/* + * F R A M E R A T E E N U M E R A T I O N + */ +enum v4l2_frmivaltypes { + V4L2_FRMIVAL_TYPE_DISCRETE = 1, + V4L2_FRMIVAL_TYPE_CONTINUOUS = 2, + V4L2_FRMIVAL_TYPE_STEPWISE = 3, +}; + +struct v4l2_frmival_stepwise { + struct v4l2_fract min; /* Minimum frame interval [s] */ + struct v4l2_fract max; /* Maximum frame interval [s] */ + struct v4l2_fract step; /* Frame interval step size [s] */ +}; + +struct v4l2_frmivalenum { + __u32 index; /* Frame format index */ + __u32 pixel_format; /* Pixel format */ + __u32 width; /* Frame width */ + __u32 height; /* Frame height */ + __u32 type; /* Frame interval type the device supports. */ + + union { /* Frame interval */ + struct v4l2_fract discrete; + struct v4l2_frmival_stepwise stepwise; + }; + + __u32 reserved[2]; /* Reserved space for future use */ +}; +#endif + +/* + * T I M E C O D E + */ +struct v4l2_timecode { + __u32 type; + __u32 flags; + __u8 frames; + __u8 seconds; + __u8 minutes; + __u8 hours; + __u8 userbits[4]; +}; + +/* Type */ +#define V4L2_TC_TYPE_24FPS 1 +#define V4L2_TC_TYPE_25FPS 2 +#define V4L2_TC_TYPE_30FPS 3 +#define V4L2_TC_TYPE_50FPS 4 +#define V4L2_TC_TYPE_60FPS 5 + +/* Flags */ +#define V4L2_TC_FLAG_DROPFRAME 0x0001 /* "drop-frame" mode */ +#define V4L2_TC_FLAG_COLORFRAME 0x0002 +#define V4L2_TC_USERBITS_field 0x000C +#define V4L2_TC_USERBITS_USERDEFINED 0x0000 +#define V4L2_TC_USERBITS_8BITCHARS 0x0008 +/* The above is based on SMPTE timecodes */ + +struct v4l2_jpegcompression { + int quality; + + int APPn; /* Number of APP segment to be written, + * must be 0..15 */ + int APP_len; /* Length of data in JPEG APPn segment */ + char APP_data[60]; /* Data in the JPEG APPn segment. */ + + int COM_len; /* Length of data in JPEG COM segment */ + char COM_data[60]; /* Data in JPEG COM segment */ + + __u32 jpeg_markers; /* Which markers should go into the JPEG + * output. Unless you exactly know what + * you do, leave them untouched. + * Inluding less markers will make the + * resulting code smaller, but there will + * be fewer applications which can read it. + * The presence of the APP and COM marker + * is influenced by APP_len and COM_len + * ONLY, not by this property! */ + +#define V4L2_JPEG_MARKER_DHT (1<<3) /* Define Huffman Tables */ +#define V4L2_JPEG_MARKER_DQT (1<<4) /* Define Quantization Tables */ +#define V4L2_JPEG_MARKER_DRI (1<<5) /* Define Restart Interval */ +#define V4L2_JPEG_MARKER_COM (1<<6) /* Comment segment */ +#define V4L2_JPEG_MARKER_APP (1<<7) /* App segment, driver will + * allways use APP0 */ +}; + +/* + * M E M O R Y - M A P P I N G B U F F E R S + */ +struct v4l2_requestbuffers { + __u32 count; + enum v4l2_buf_type type; + enum v4l2_memory memory; + __u32 reserved[2]; +}; + +/** + * struct v4l2_plane - plane info for multi-planar buffers + * @bytesused: number of bytes occupied by data in the plane (payload) + * @length: size of this plane (NOT the payload) in bytes + * @mem_offset: when memory in the associated struct v4l2_buffer is + * V4L2_MEMORY_MMAP, equals the offset from the start of + * the device memory for this plane (or is a "cookie" that + * should be passed to mmap() called on the video node) + * @userptr: when memory is V4L2_MEMORY_USERPTR, a userspace pointer + * pointing to this plane + * @data_offset: offset in the plane to the start of data; usually 0, + * unless there is a header in front of the data + * + * Multi-planar buffers consist of one or more planes, e.g. an YCbCr buffer + * with two planes can have one plane for Y, and another for interleaved CbCr + * components. Each plane can reside in a separate memory buffer, or even in + * a completely separate memory node (e.g. in embedded devices). + */ +struct v4l2_plane { + __u32 bytesused; + __u32 length; + union { + __u32 mem_offset; + unsigned long userptr; + } m; + __u32 data_offset; + __u32 reserved[11]; +}; + +/** + * struct v4l2_buffer - video buffer info + * @index: id number of the buffer + * @type: buffer type (type == *_MPLANE for multiplanar buffers) + * @bytesused: number of bytes occupied by data in the buffer (payload); + * unused (set to 0) for multiplanar buffers + * @flags: buffer informational flags + * @field: field order of the image in the buffer + * @timestamp: frame timestamp + * @timecode: frame timecode + * @sequence: sequence count of this frame + * @memory: the method, in which the actual video data is passed + * @offset: for non-multiplanar buffers with memory == V4L2_MEMORY_MMAP; + * offset from the start of the device memory for this plane, + * (or a "cookie" that should be passed to mmap() as offset) + * @userptr: for non-multiplanar buffers with memory == V4L2_MEMORY_USERPTR; + * a userspace pointer pointing to this buffer + * @planes: for multiplanar buffers; userspace pointer to the array of plane + * info structs for this buffer + * @length: size in bytes of the buffer (NOT its payload) for single-plane + * buffers (when type != *_MPLANE); number of elements in the + * planes array for multi-plane buffers + * @input: input number from which the video data has has been captured + * + * Contains data exchanged by application and driver using one of the Streaming + * I/O methods. + */ +struct v4l2_buffer { + __u32 index; + enum v4l2_buf_type type; + __u32 bytesused; + __u32 flags; + enum v4l2_field field; + struct timeval timestamp; + struct v4l2_timecode timecode; + __u32 sequence; + + /* memory location */ + enum v4l2_memory memory; + union { + __u32 offset; + unsigned long userptr; + struct v4l2_plane *planes; + } m; + __u32 length; + __u32 input; + __u32 reserved; +}; + +/* Flags for 'flags' field */ +#define V4L2_BUF_FLAG_MAPPED 0x0001 /* Buffer is mapped (flag) */ +#define V4L2_BUF_FLAG_QUEUED 0x0002 /* Buffer is queued for processing */ +#define V4L2_BUF_FLAG_DONE 0x0004 /* Buffer is ready */ +#define V4L2_BUF_FLAG_KEYFRAME 0x0008 /* Image is a keyframe (I-frame) */ +#define V4L2_BUF_FLAG_PFRAME 0x0010 /* Image is a P-frame */ +#define V4L2_BUF_FLAG_BFRAME 0x0020 /* Image is a B-frame */ +/* Buffer is ready, but the data contained within is corrupted. */ +#define V4L2_BUF_FLAG_ERROR 0x0040 +#define V4L2_BUF_FLAG_TIMECODE 0x0100 /* timecode field is valid */ +#define V4L2_BUF_FLAG_INPUT 0x0200 /* input field is valid */ +#define V4L2_BUF_FLAG_PREPARED 0x0400 /* Buffer is prepared for queuing */ +/* Cache handling flags */ +#define V4L2_BUF_FLAG_NO_CACHE_INVALIDATE 0x0800 +#define V4L2_BUF_FLAG_NO_CACHE_CLEAN 0x1000 +#define V4L2_BUF_FLAG_EOS 0x2000 +#define V4L2_QCOM_BUF_FLAG_CODECCONFIG 0x4000 +#define V4L2_QCOM_BUF_FLAG_EOSEQ 0x8000 +#define V4L2_QCOM_BUF_TIMESTAMP_INVALID 0x10000 +#define V4L2_QCOM_BUF_FLAG_IDRFRAME 0x20000 /* Image is a IDR-frame */ +#define V4L2_QCOM_BUF_FLAG_DECODEONLY 0x40000 +#define V4L2_QCOM_BUF_DATA_CORRUPT 0x80000 +#define V4L2_QCOM_BUF_DROP_FRAME 0x100000 +#define V4L2_QCOM_BUF_INPUT_UNSUPPORTED 0x200000 +#define V4L2_QCOM_BUF_FLAG_READONLY 0x400000 + +/* + * O V E R L A Y P R E V I E W + */ +struct v4l2_framebuffer { + __u32 capability; + __u32 flags; +/* FIXME: in theory we should pass something like PCI device + memory + * region + offset instead of some physical address */ + void *base; + struct v4l2_pix_format fmt; +}; +/* Flags for the 'capability' field. Read only */ +#define V4L2_FBUF_CAP_EXTERNOVERLAY 0x0001 +#define V4L2_FBUF_CAP_CHROMAKEY 0x0002 +#define V4L2_FBUF_CAP_LIST_CLIPPING 0x0004 +#define V4L2_FBUF_CAP_BITMAP_CLIPPING 0x0008 +#define V4L2_FBUF_CAP_LOCAL_ALPHA 0x0010 +#define V4L2_FBUF_CAP_GLOBAL_ALPHA 0x0020 +#define V4L2_FBUF_CAP_LOCAL_INV_ALPHA 0x0040 +#define V4L2_FBUF_CAP_SRC_CHROMAKEY 0x0080 +/* Flags for the 'flags' field. */ +#define V4L2_FBUF_FLAG_PRIMARY 0x0001 +#define V4L2_FBUF_FLAG_OVERLAY 0x0002 +#define V4L2_FBUF_FLAG_CHROMAKEY 0x0004 +#define V4L2_FBUF_FLAG_LOCAL_ALPHA 0x0008 +#define V4L2_FBUF_FLAG_GLOBAL_ALPHA 0x0010 +#define V4L2_FBUF_FLAG_LOCAL_INV_ALPHA 0x0020 +#define V4L2_FBUF_FLAG_SRC_CHROMAKEY 0x0040 + +struct v4l2_clip { + struct v4l2_rect c; + struct v4l2_clip __user *next; +}; + +struct v4l2_window { + struct v4l2_rect w; + enum v4l2_field field; + __u32 chromakey; + struct v4l2_clip __user *clips; + __u32 clipcount; + void __user *bitmap; + __u8 global_alpha; +}; + +/* + * C A P T U R E P A R A M E T E R S + */ +struct v4l2_captureparm { + __u32 capability; /* Supported modes */ + __u32 capturemode; /* Current mode */ + struct v4l2_fract timeperframe; /* Time per frame in .1us units */ + __u32 extendedmode; /* Driver-specific extensions */ + __u32 readbuffers; /* # of buffers for read */ + __u32 reserved[4]; +}; + +/* Flags for 'capability' and 'capturemode' fields */ +#define V4L2_MODE_HIGHQUALITY 0x0001 /* High quality imaging mode */ +#define V4L2_CAP_TIMEPERFRAME 0x1000 /* timeperframe field is supported */ +#define V4L2_CAP_QCOM_FRAMESKIP 0x2000 /* frame skipping is supported */ + +struct v4l2_qcom_frameskip { + __u64 maxframeinterval; +}; + +struct v4l2_outputparm { + __u32 capability; /* Supported modes */ + __u32 outputmode; /* Current mode */ + struct v4l2_fract timeperframe; /* Time per frame in seconds */ + __u32 extendedmode; /* Driver-specific extensions */ + __u32 writebuffers; /* # of buffers for write */ + __u32 reserved[4]; +}; + +/* + * I N P U T I M A G E C R O P P I N G + */ +struct v4l2_cropcap { + enum v4l2_buf_type type; + struct v4l2_rect bounds; + struct v4l2_rect defrect; + struct v4l2_fract pixelaspect; +}; + +struct v4l2_crop { + enum v4l2_buf_type type; + struct v4l2_rect c; +}; + +/* Hints for adjustments of selection rectangle */ +#define V4L2_SEL_FLAG_GE 0x00000001 +#define V4L2_SEL_FLAG_LE 0x00000002 + +/* Selection targets */ + +/* Current cropping area */ +#define V4L2_SEL_TGT_CROP_ACTIVE 0x0000 +/* Default cropping area */ +#define V4L2_SEL_TGT_CROP_DEFAULT 0x0001 +/* Cropping bounds */ +#define V4L2_SEL_TGT_CROP_BOUNDS 0x0002 +/* Current composing area */ +#define V4L2_SEL_TGT_COMPOSE_ACTIVE 0x0100 +/* Default composing area */ +#define V4L2_SEL_TGT_COMPOSE_DEFAULT 0x0101 +/* Composing bounds */ +#define V4L2_SEL_TGT_COMPOSE_BOUNDS 0x0102 +/* Current composing area plus all padding pixels */ +#define V4L2_SEL_TGT_COMPOSE_PADDED 0x0103 + +/** + * struct v4l2_selection - selection info + * @type: buffer type (do not use *_MPLANE types) + * @target: selection target, used to choose one of possible rectangles + * @flags: constraints flags + * @r: coordinates of selection window + * @reserved: for future use, rounds structure size to 64 bytes, set to zero + * + * Hardware may use multiple helper windows to process a video stream. + * The structure is used to exchange this selection areas between + * an application and a driver. + */ +struct v4l2_selection { + __u32 type; + __u32 target; + __u32 flags; + struct v4l2_rect r; + __u32 reserved[9]; +}; + + +/* + * A N A L O G V I D E O S T A N D A R D + */ + +typedef __u64 v4l2_std_id; + +/* one bit for each */ +#define V4L2_STD_PAL_B ((v4l2_std_id)0x00000001) +#define V4L2_STD_PAL_B1 ((v4l2_std_id)0x00000002) +#define V4L2_STD_PAL_G ((v4l2_std_id)0x00000004) +#define V4L2_STD_PAL_H ((v4l2_std_id)0x00000008) +#define V4L2_STD_PAL_I ((v4l2_std_id)0x00000010) +#define V4L2_STD_PAL_D ((v4l2_std_id)0x00000020) +#define V4L2_STD_PAL_D1 ((v4l2_std_id)0x00000040) +#define V4L2_STD_PAL_K ((v4l2_std_id)0x00000080) + +#define V4L2_STD_PAL_M ((v4l2_std_id)0x00000100) +#define V4L2_STD_PAL_N ((v4l2_std_id)0x00000200) +#define V4L2_STD_PAL_Nc ((v4l2_std_id)0x00000400) +#define V4L2_STD_PAL_60 ((v4l2_std_id)0x00000800) + +#define V4L2_STD_NTSC_M ((v4l2_std_id)0x00001000) /* BTSC */ +#define V4L2_STD_NTSC_M_JP ((v4l2_std_id)0x00002000) /* EIA-J */ +#define V4L2_STD_NTSC_443 ((v4l2_std_id)0x00004000) +#define V4L2_STD_NTSC_M_KR ((v4l2_std_id)0x00008000) /* FM A2 */ + +#define V4L2_STD_SECAM_B ((v4l2_std_id)0x00010000) +#define V4L2_STD_SECAM_D ((v4l2_std_id)0x00020000) +#define V4L2_STD_SECAM_G ((v4l2_std_id)0x00040000) +#define V4L2_STD_SECAM_H ((v4l2_std_id)0x00080000) +#define V4L2_STD_SECAM_K ((v4l2_std_id)0x00100000) +#define V4L2_STD_SECAM_K1 ((v4l2_std_id)0x00200000) +#define V4L2_STD_SECAM_L ((v4l2_std_id)0x00400000) +#define V4L2_STD_SECAM_LC ((v4l2_std_id)0x00800000) + +/* ATSC/HDTV */ +#define V4L2_STD_ATSC_8_VSB ((v4l2_std_id)0x01000000) +#define V4L2_STD_ATSC_16_VSB ((v4l2_std_id)0x02000000) + +/* FIXME: + Although std_id is 64 bits, there is an issue on PPC32 architecture that + makes switch(__u64) to break. So, there's a hack on v4l2-common.c rounding + this value to 32 bits. + As, currently, the max value is for V4L2_STD_ATSC_16_VSB (30 bits wide), + it should work fine. However, if needed to add more than two standards, + v4l2-common.c should be fixed. + */ + +/* + * Some macros to merge video standards in order to make live easier for the + * drivers and V4L2 applications + */ + +/* + * "Common" NTSC/M - It should be noticed that V4L2_STD_NTSC_443 is + * Missing here. + */ +#define V4L2_STD_NTSC (V4L2_STD_NTSC_M |\ + V4L2_STD_NTSC_M_JP |\ + V4L2_STD_NTSC_M_KR) +/* Secam macros */ +#define V4L2_STD_SECAM_DK (V4L2_STD_SECAM_D |\ + V4L2_STD_SECAM_K |\ + V4L2_STD_SECAM_K1) +/* All Secam Standards */ +#define V4L2_STD_SECAM (V4L2_STD_SECAM_B |\ + V4L2_STD_SECAM_G |\ + V4L2_STD_SECAM_H |\ + V4L2_STD_SECAM_DK |\ + V4L2_STD_SECAM_L |\ + V4L2_STD_SECAM_LC) +/* PAL macros */ +#define V4L2_STD_PAL_BG (V4L2_STD_PAL_B |\ + V4L2_STD_PAL_B1 |\ + V4L2_STD_PAL_G) +#define V4L2_STD_PAL_DK (V4L2_STD_PAL_D |\ + V4L2_STD_PAL_D1 |\ + V4L2_STD_PAL_K) +/* + * "Common" PAL - This macro is there to be compatible with the old + * V4L1 concept of "PAL": /BGDKHI. + * Several PAL standards are mising here: /M, /N and /Nc + */ +#define V4L2_STD_PAL (V4L2_STD_PAL_BG |\ + V4L2_STD_PAL_DK |\ + V4L2_STD_PAL_H |\ + V4L2_STD_PAL_I) +/* Chroma "agnostic" standards */ +#define V4L2_STD_B (V4L2_STD_PAL_B |\ + V4L2_STD_PAL_B1 |\ + V4L2_STD_SECAM_B) +#define V4L2_STD_G (V4L2_STD_PAL_G |\ + V4L2_STD_SECAM_G) +#define V4L2_STD_H (V4L2_STD_PAL_H |\ + V4L2_STD_SECAM_H) +#define V4L2_STD_L (V4L2_STD_SECAM_L |\ + V4L2_STD_SECAM_LC) +#define V4L2_STD_GH (V4L2_STD_G |\ + V4L2_STD_H) +#define V4L2_STD_DK (V4L2_STD_PAL_DK |\ + V4L2_STD_SECAM_DK) +#define V4L2_STD_BG (V4L2_STD_B |\ + V4L2_STD_G) +#define V4L2_STD_MN (V4L2_STD_PAL_M |\ + V4L2_STD_PAL_N |\ + V4L2_STD_PAL_Nc |\ + V4L2_STD_NTSC) + +/* Standards where MTS/BTSC stereo could be found */ +#define V4L2_STD_MTS (V4L2_STD_NTSC_M |\ + V4L2_STD_PAL_M |\ + V4L2_STD_PAL_N |\ + V4L2_STD_PAL_Nc) + +/* Standards for Countries with 60Hz Line frequency */ +#define V4L2_STD_525_60 (V4L2_STD_PAL_M |\ + V4L2_STD_PAL_60 |\ + V4L2_STD_NTSC |\ + V4L2_STD_NTSC_443) +/* Standards for Countries with 50Hz Line frequency */ +#define V4L2_STD_625_50 (V4L2_STD_PAL |\ + V4L2_STD_PAL_N |\ + V4L2_STD_PAL_Nc |\ + V4L2_STD_SECAM) + +#define V4L2_STD_ATSC (V4L2_STD_ATSC_8_VSB |\ + V4L2_STD_ATSC_16_VSB) +/* Macros with none and all analog standards */ +#define V4L2_STD_UNKNOWN 0 +#define V4L2_STD_ALL (V4L2_STD_525_60 |\ + V4L2_STD_625_50) + +struct v4l2_standard { + __u32 index; + v4l2_std_id id; + __u8 name[24]; + struct v4l2_fract frameperiod; /* Frames, not fields */ + __u32 framelines; + __u32 reserved[4]; +}; + +/* + * V I D E O T I M I N G S D V P R E S E T + */ +struct v4l2_dv_preset { + __u32 preset; + __u32 reserved[4]; +}; + +/* + * D V P R E S E T S E N U M E R A T I O N + */ +struct v4l2_dv_enum_preset { + __u32 index; + __u32 preset; + __u8 name[32]; /* Name of the preset timing */ + __u32 width; + __u32 height; + __u32 reserved[4]; +}; + +/* + * D V P R E S E T V A L U E S + */ +#define V4L2_DV_INVALID 0 +#define V4L2_DV_480P59_94 1 /* BT.1362 */ +#define V4L2_DV_576P50 2 /* BT.1362 */ +#define V4L2_DV_720P24 3 /* SMPTE 296M */ +#define V4L2_DV_720P25 4 /* SMPTE 296M */ +#define V4L2_DV_720P30 5 /* SMPTE 296M */ +#define V4L2_DV_720P50 6 /* SMPTE 296M */ +#define V4L2_DV_720P59_94 7 /* SMPTE 274M */ +#define V4L2_DV_720P60 8 /* SMPTE 274M/296M */ +#define V4L2_DV_1080I29_97 9 /* BT.1120/ SMPTE 274M */ +#define V4L2_DV_1080I30 10 /* BT.1120/ SMPTE 274M */ +#define V4L2_DV_1080I25 11 /* BT.1120 */ +#define V4L2_DV_1080I50 12 /* SMPTE 296M */ +#define V4L2_DV_1080I60 13 /* SMPTE 296M */ +#define V4L2_DV_1080P24 14 /* SMPTE 296M */ +#define V4L2_DV_1080P25 15 /* SMPTE 296M */ +#define V4L2_DV_1080P30 16 /* SMPTE 296M */ +#define V4L2_DV_1080P50 17 /* BT.1120 */ +#define V4L2_DV_1080P60 18 /* BT.1120 */ + +/* + * D V B T T I M I N G S + */ + +/* BT.656/BT.1120 timing data */ +struct v4l2_bt_timings { + __u32 width; /* width in pixels */ + __u32 height; /* height in lines */ + __u32 interlaced; /* Interlaced or progressive */ + __u32 polarities; /* Positive or negative polarity */ + __u64 pixelclock; /* Pixel clock in HZ. Ex. 74.25MHz->74250000 */ + __u32 hfrontporch; /* Horizpontal front porch in pixels */ + __u32 hsync; /* Horizontal Sync length in pixels */ + __u32 hbackporch; /* Horizontal back porch in pixels */ + __u32 vfrontporch; /* Vertical front porch in pixels */ + __u32 vsync; /* Vertical Sync length in lines */ + __u32 vbackporch; /* Vertical back porch in lines */ + __u32 il_vfrontporch; /* Vertical front porch for bottom field of + * interlaced field formats + */ + __u32 il_vsync; /* Vertical sync length for bottom field of + * interlaced field formats + */ + __u32 il_vbackporch; /* Vertical back porch for bottom field of + * interlaced field formats + */ + __u32 reserved[16]; +} __attribute__ ((packed)); + +/* Interlaced or progressive format */ +#define V4L2_DV_PROGRESSIVE 0 +#define V4L2_DV_INTERLACED 1 + +/* Polarities. If bit is not set, it is assumed to be negative polarity */ +#define V4L2_DV_VSYNC_POS_POL 0x00000001 +#define V4L2_DV_HSYNC_POS_POL 0x00000002 + + +/* DV timings */ +struct v4l2_dv_timings { + __u32 type; + union { + struct v4l2_bt_timings bt; + __u32 reserved[32]; + }; +} __attribute__ ((packed)); + +/* Values for the type field */ +#define V4L2_DV_BT_656_1120 0 /* BT.656/1120 timing type */ + +/* + * V I D E O I N P U T S + */ +struct v4l2_input { + __u32 index; /* Which input */ + __u8 name[32]; /* Label */ + __u32 type; /* Type of input */ + __u32 audioset; /* Associated audios (bitfield) */ + __u32 tuner; /* Associated tuner */ + v4l2_std_id std; + __u32 status; + __u32 capabilities; + __u32 reserved[3]; +}; + +/* Values for the 'type' field */ +#define V4L2_INPUT_TYPE_TUNER 1 +#define V4L2_INPUT_TYPE_CAMERA 2 + +/* field 'status' - general */ +#define V4L2_IN_ST_NO_POWER 0x00000001 /* Attached device is off */ +#define V4L2_IN_ST_NO_SIGNAL 0x00000002 +#define V4L2_IN_ST_NO_COLOR 0x00000004 + +/* field 'status' - sensor orientation */ +/* If sensor is mounted upside down set both bits */ +#define V4L2_IN_ST_HFLIP 0x00000010 /* Frames are flipped horizontally */ +#define V4L2_IN_ST_VFLIP 0x00000020 /* Frames are flipped vertically */ + +/* field 'status' - analog */ +#define V4L2_IN_ST_NO_H_LOCK 0x00000100 /* No horizontal sync lock */ +#define V4L2_IN_ST_COLOR_KILL 0x00000200 /* Color killer is active */ + +/* field 'status' - digital */ +#define V4L2_IN_ST_NO_SYNC 0x00010000 /* No synchronization lock */ +#define V4L2_IN_ST_NO_EQU 0x00020000 /* No equalizer lock */ +#define V4L2_IN_ST_NO_CARRIER 0x00040000 /* Carrier recovery failed */ + +/* field 'status' - VCR and set-top box */ +#define V4L2_IN_ST_MACROVISION 0x01000000 /* Macrovision detected */ +#define V4L2_IN_ST_NO_ACCESS 0x02000000 /* Conditional access denied */ +#define V4L2_IN_ST_VTR 0x04000000 /* VTR time constant */ + +/* capabilities flags */ +#define V4L2_IN_CAP_PRESETS 0x00000001 /* Supports S_DV_PRESET */ +#define V4L2_IN_CAP_CUSTOM_TIMINGS 0x00000002 /* Supports S_DV_TIMINGS */ +#define V4L2_IN_CAP_STD 0x00000004 /* Supports S_STD */ + +/* + * V I D E O O U T P U T S + */ +struct v4l2_output { + __u32 index; /* Which output */ + __u8 name[32]; /* Label */ + __u32 type; /* Type of output */ + __u32 audioset; /* Associated audios (bitfield) */ + __u32 modulator; /* Associated modulator */ + v4l2_std_id std; + __u32 capabilities; + __u32 reserved[3]; +}; +/* Values for the 'type' field */ +#define V4L2_OUTPUT_TYPE_MODULATOR 1 +#define V4L2_OUTPUT_TYPE_ANALOG 2 +#define V4L2_OUTPUT_TYPE_ANALOGVGAOVERLAY 3 + +/* capabilities flags */ +#define V4L2_OUT_CAP_PRESETS 0x00000001 /* Supports S_DV_PRESET */ +#define V4L2_OUT_CAP_CUSTOM_TIMINGS 0x00000002 /* Supports S_DV_TIMINGS */ +#define V4L2_OUT_CAP_STD 0x00000004 /* Supports S_STD */ + +/* + * C O N T R O L S + */ +struct v4l2_control { + __u32 id; + __s32 value; +}; + +struct v4l2_ext_control { + __u32 id; + __u32 size; + __u32 reserved2[1]; + union { + __s32 value; + __s64 value64; + char *string; + }; +} __attribute__ ((packed)); + +struct v4l2_ext_controls { + __u32 ctrl_class; + __u32 count; + __u32 error_idx; + __u32 reserved[2]; + struct v4l2_ext_control *controls; +}; + +/* Values for ctrl_class field */ +#define V4L2_CTRL_CLASS_USER 0x00980000 /* Old-style 'user' controls */ +#define V4L2_CTRL_CLASS_MPEG 0x00990000 /* MPEG-compression controls */ +#define V4L2_CTRL_CLASS_CAMERA 0x009a0000 /* Camera class controls */ +#define V4L2_CTRL_CLASS_FM_TX 0x009b0000 /* FM Modulator control class */ +#define V4L2_CTRL_CLASS_FLASH 0x009c0000 /* Camera flash controls */ +#define V4L2_CTRL_CLASS_JPEG 0x009d0000 /* JPEG-compression controls */ + +#define V4L2_CTRL_ID_MASK (0x0fffffff) +#define V4L2_CTRL_ID2CLASS(id) ((id) & 0x0fff0000UL) +#define V4L2_CTRL_DRIVER_PRIV(id) (((id) & 0xffff) >= 0x1000) + +enum v4l2_ctrl_type { + V4L2_CTRL_TYPE_INTEGER = 1, + V4L2_CTRL_TYPE_BOOLEAN = 2, + V4L2_CTRL_TYPE_MENU = 3, + V4L2_CTRL_TYPE_BUTTON = 4, + V4L2_CTRL_TYPE_INTEGER64 = 5, + V4L2_CTRL_TYPE_CTRL_CLASS = 6, + V4L2_CTRL_TYPE_STRING = 7, + V4L2_CTRL_TYPE_BITMASK = 8, +}; + +/* Used in the VIDIOC_QUERYCTRL ioctl for querying controls */ +struct v4l2_queryctrl { + __u32 id; + enum v4l2_ctrl_type type; + __u8 name[32]; /* Whatever */ + __s32 minimum; /* Note signedness */ + __s32 maximum; + __s32 step; + __s32 default_value; + __u32 flags; + __u32 reserved[2]; +}; + +/* Used in the VIDIOC_QUERYMENU ioctl for querying menu items */ +struct v4l2_querymenu { + __u32 id; + __u32 index; + __u8 name[32]; /* Whatever */ + __u32 reserved; +}; + +/* Control flags */ +#define V4L2_CTRL_FLAG_DISABLED 0x0001 +#define V4L2_CTRL_FLAG_GRABBED 0x0002 +#define V4L2_CTRL_FLAG_READ_ONLY 0x0004 +#define V4L2_CTRL_FLAG_UPDATE 0x0008 +#define V4L2_CTRL_FLAG_INACTIVE 0x0010 +#define V4L2_CTRL_FLAG_SLIDER 0x0020 +#define V4L2_CTRL_FLAG_WRITE_ONLY 0x0040 +#define V4L2_CTRL_FLAG_VOLATILE 0x0080 + +/* Query flag, to be ORed with the control ID */ +#define V4L2_CTRL_FLAG_NEXT_CTRL 0x80000000 + +/* User-class control IDs defined by V4L2 */ +#define V4L2_CID_MAX_CTRLS 1024 +#define V4L2_CID_BASE (V4L2_CTRL_CLASS_USER | 0x900) +#define V4L2_CID_USER_BASE V4L2_CID_BASE +/* IDs reserved for driver specific controls */ +#define V4L2_CID_PRIVATE_BASE 0x08000000 + +#define V4L2_CID_USER_CLASS (V4L2_CTRL_CLASS_USER | 1) +#define V4L2_CID_BRIGHTNESS (V4L2_CID_BASE+0) +#define V4L2_CID_CONTRAST (V4L2_CID_BASE+1) +#define V4L2_CID_SATURATION (V4L2_CID_BASE+2) +#define V4L2_CID_HUE (V4L2_CID_BASE+3) +#define V4L2_CID_AUDIO_VOLUME (V4L2_CID_BASE+5) +#define V4L2_CID_AUDIO_BALANCE (V4L2_CID_BASE+6) +#define V4L2_CID_AUDIO_BASS (V4L2_CID_BASE+7) +#define V4L2_CID_AUDIO_TREBLE (V4L2_CID_BASE+8) +#define V4L2_CID_AUDIO_MUTE (V4L2_CID_BASE+9) +#define V4L2_CID_AUDIO_LOUDNESS (V4L2_CID_BASE+10) +#define V4L2_CID_BLACK_LEVEL (V4L2_CID_BASE+11) /* Deprecated */ +#define V4L2_CID_AUTO_WHITE_BALANCE (V4L2_CID_BASE+12) +#define V4L2_CID_DO_WHITE_BALANCE (V4L2_CID_BASE+13) +#define V4L2_CID_RED_BALANCE (V4L2_CID_BASE+14) +#define V4L2_CID_BLUE_BALANCE (V4L2_CID_BASE+15) +#define V4L2_CID_GAMMA (V4L2_CID_BASE+16) +#define V4L2_CID_WHITENESS (V4L2_CID_GAMMA) /* Deprecated */ +#define V4L2_CID_EXPOSURE (V4L2_CID_BASE+17) +#define V4L2_CID_AUTOGAIN (V4L2_CID_BASE+18) +#define V4L2_CID_GAIN (V4L2_CID_BASE+19) +#define V4L2_CID_HFLIP (V4L2_CID_BASE+20) +#define V4L2_CID_VFLIP (V4L2_CID_BASE+21) + +/* Deprecated; use V4L2_CID_PAN_RESET and V4L2_CID_TILT_RESET */ +#define V4L2_CID_HCENTER (V4L2_CID_BASE+22) +#define V4L2_CID_VCENTER (V4L2_CID_BASE+23) + +#define V4L2_CID_POWER_LINE_FREQUENCY (V4L2_CID_BASE+24) +enum v4l2_power_line_frequency { + V4L2_CID_POWER_LINE_FREQUENCY_DISABLED = 0, + V4L2_CID_POWER_LINE_FREQUENCY_50HZ = 1, + V4L2_CID_POWER_LINE_FREQUENCY_60HZ = 2, + V4L2_CID_POWER_LINE_FREQUENCY_AUTO = 3, +}; +#define V4L2_CID_HUE_AUTO (V4L2_CID_BASE+25) +#define V4L2_CID_WHITE_BALANCE_TEMPERATURE (V4L2_CID_BASE+26) +#define V4L2_CID_SHARPNESS (V4L2_CID_BASE+27) +#define V4L2_CID_BACKLIGHT_COMPENSATION (V4L2_CID_BASE+28) +#define V4L2_CID_CHROMA_AGC (V4L2_CID_BASE+29) +#define V4L2_CID_COLOR_KILLER (V4L2_CID_BASE+30) +#define V4L2_CID_COLORFX (V4L2_CID_BASE+31) +enum v4l2_colorfx { + V4L2_COLORFX_NONE = 0, + V4L2_COLORFX_BW = 1, + V4L2_COLORFX_SEPIA = 2, + V4L2_COLORFX_NEGATIVE = 3, + V4L2_COLORFX_EMBOSS = 4, + V4L2_COLORFX_SKETCH = 5, + V4L2_COLORFX_SKY_BLUE = 6, + V4L2_COLORFX_GRASS_GREEN = 7, + V4L2_COLORFX_SKIN_WHITEN = 8, + V4L2_COLORFX_VIVID = 9, +}; +#define V4L2_CID_AUTOBRIGHTNESS (V4L2_CID_BASE+32) +#define V4L2_CID_BAND_STOP_FILTER (V4L2_CID_BASE+33) + +#define V4L2_CID_ROTATE (V4L2_CID_BASE+34) +#define V4L2_CID_BG_COLOR (V4L2_CID_BASE+35) + +#define V4L2_CID_CHROMA_GAIN (V4L2_CID_BASE+36) + +#define V4L2_CID_ILLUMINATORS_1 (V4L2_CID_BASE+37) +#define V4L2_CID_ILLUMINATORS_2 (V4L2_CID_BASE+38) + +#define V4L2_CID_MIN_BUFFERS_FOR_CAPTURE (V4L2_CID_BASE+39) +#define V4L2_CID_MIN_BUFFERS_FOR_OUTPUT (V4L2_CID_BASE+40) + +#define V4L2_CID_ALPHA_COMPONENT (V4L2_CID_BASE+41) + +/* last CID + 1 */ +#define V4L2_CID_LASTP1 (V4L2_CID_BASE+42) +#define V4L2_CID_SPECIAL_EFFECT (V4L2_CID_BASE+43) +/* Minimum number of buffer neede by the device */ + +/* MPEG-class control IDs defined by V4L2 */ +#define V4L2_CID_MPEG_BASE (V4L2_CTRL_CLASS_MPEG | 0x900) +#define V4L2_CID_MPEG_CLASS (V4L2_CTRL_CLASS_MPEG | 1) + +/* MPEG streams, specific to multiplexed streams */ +#define V4L2_CID_MPEG_STREAM_TYPE (V4L2_CID_MPEG_BASE+0) +enum v4l2_mpeg_stream_type { + V4L2_MPEG_STREAM_TYPE_MPEG2_PS = 0, /* MPEG-2 program stream */ + V4L2_MPEG_STREAM_TYPE_MPEG2_TS = 1, /* MPEG-2 transport stream */ + V4L2_MPEG_STREAM_TYPE_MPEG1_SS = 2, /* MPEG-1 system stream */ + V4L2_MPEG_STREAM_TYPE_MPEG2_DVD = 3, /* MPEG-2 DVD-compatible stream */ + V4L2_MPEG_STREAM_TYPE_MPEG1_VCD = 4, /* MPEG-1 VCD-compatible stream */ + V4L2_MPEG_STREAM_TYPE_MPEG2_SVCD = 5, /* MPEG-2 SVCD-compatible stream */ +}; +#define V4L2_CID_MPEG_STREAM_PID_PMT (V4L2_CID_MPEG_BASE+1) +#define V4L2_CID_MPEG_STREAM_PID_AUDIO (V4L2_CID_MPEG_BASE+2) +#define V4L2_CID_MPEG_STREAM_PID_VIDEO (V4L2_CID_MPEG_BASE+3) +#define V4L2_CID_MPEG_STREAM_PID_PCR (V4L2_CID_MPEG_BASE+4) +#define V4L2_CID_MPEG_STREAM_PES_ID_AUDIO (V4L2_CID_MPEG_BASE+5) +#define V4L2_CID_MPEG_STREAM_PES_ID_VIDEO (V4L2_CID_MPEG_BASE+6) +#define V4L2_CID_MPEG_STREAM_VBI_FMT (V4L2_CID_MPEG_BASE+7) +enum v4l2_mpeg_stream_vbi_fmt { + V4L2_MPEG_STREAM_VBI_FMT_NONE = 0, /* No VBI in the MPEG stream */ + V4L2_MPEG_STREAM_VBI_FMT_IVTV = 1, /* VBI in private packets, IVTV format */ +}; + +/* MPEG audio controls specific to multiplexed streams */ +#define V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ (V4L2_CID_MPEG_BASE+100) +enum v4l2_mpeg_audio_sampling_freq { + V4L2_MPEG_AUDIO_SAMPLING_FREQ_44100 = 0, + V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000 = 1, + V4L2_MPEG_AUDIO_SAMPLING_FREQ_32000 = 2, +}; +#define V4L2_CID_MPEG_AUDIO_ENCODING (V4L2_CID_MPEG_BASE+101) +enum v4l2_mpeg_audio_encoding { + V4L2_MPEG_AUDIO_ENCODING_LAYER_1 = 0, + V4L2_MPEG_AUDIO_ENCODING_LAYER_2 = 1, + V4L2_MPEG_AUDIO_ENCODING_LAYER_3 = 2, + V4L2_MPEG_AUDIO_ENCODING_AAC = 3, + V4L2_MPEG_AUDIO_ENCODING_AC3 = 4, +}; +#define V4L2_CID_MPEG_AUDIO_L1_BITRATE (V4L2_CID_MPEG_BASE+102) +enum v4l2_mpeg_audio_l1_bitrate { + V4L2_MPEG_AUDIO_L1_BITRATE_32K = 0, + V4L2_MPEG_AUDIO_L1_BITRATE_64K = 1, + V4L2_MPEG_AUDIO_L1_BITRATE_96K = 2, + V4L2_MPEG_AUDIO_L1_BITRATE_128K = 3, + V4L2_MPEG_AUDIO_L1_BITRATE_160K = 4, + V4L2_MPEG_AUDIO_L1_BITRATE_192K = 5, + V4L2_MPEG_AUDIO_L1_BITRATE_224K = 6, + V4L2_MPEG_AUDIO_L1_BITRATE_256K = 7, + V4L2_MPEG_AUDIO_L1_BITRATE_288K = 8, + V4L2_MPEG_AUDIO_L1_BITRATE_320K = 9, + V4L2_MPEG_AUDIO_L1_BITRATE_352K = 10, + V4L2_MPEG_AUDIO_L1_BITRATE_384K = 11, + V4L2_MPEG_AUDIO_L1_BITRATE_416K = 12, + V4L2_MPEG_AUDIO_L1_BITRATE_448K = 13, +}; +#define V4L2_CID_MPEG_AUDIO_L2_BITRATE (V4L2_CID_MPEG_BASE+103) +enum v4l2_mpeg_audio_l2_bitrate { + V4L2_MPEG_AUDIO_L2_BITRATE_32K = 0, + V4L2_MPEG_AUDIO_L2_BITRATE_48K = 1, + V4L2_MPEG_AUDIO_L2_BITRATE_56K = 2, + V4L2_MPEG_AUDIO_L2_BITRATE_64K = 3, + V4L2_MPEG_AUDIO_L2_BITRATE_80K = 4, + V4L2_MPEG_AUDIO_L2_BITRATE_96K = 5, + V4L2_MPEG_AUDIO_L2_BITRATE_112K = 6, + V4L2_MPEG_AUDIO_L2_BITRATE_128K = 7, + V4L2_MPEG_AUDIO_L2_BITRATE_160K = 8, + V4L2_MPEG_AUDIO_L2_BITRATE_192K = 9, + V4L2_MPEG_AUDIO_L2_BITRATE_224K = 10, + V4L2_MPEG_AUDIO_L2_BITRATE_256K = 11, + V4L2_MPEG_AUDIO_L2_BITRATE_320K = 12, + V4L2_MPEG_AUDIO_L2_BITRATE_384K = 13, +}; +#define V4L2_CID_MPEG_AUDIO_L3_BITRATE (V4L2_CID_MPEG_BASE+104) +enum v4l2_mpeg_audio_l3_bitrate { + V4L2_MPEG_AUDIO_L3_BITRATE_32K = 0, + V4L2_MPEG_AUDIO_L3_BITRATE_40K = 1, + V4L2_MPEG_AUDIO_L3_BITRATE_48K = 2, + V4L2_MPEG_AUDIO_L3_BITRATE_56K = 3, + V4L2_MPEG_AUDIO_L3_BITRATE_64K = 4, + V4L2_MPEG_AUDIO_L3_BITRATE_80K = 5, + V4L2_MPEG_AUDIO_L3_BITRATE_96K = 6, + V4L2_MPEG_AUDIO_L3_BITRATE_112K = 7, + V4L2_MPEG_AUDIO_L3_BITRATE_128K = 8, + V4L2_MPEG_AUDIO_L3_BITRATE_160K = 9, + V4L2_MPEG_AUDIO_L3_BITRATE_192K = 10, + V4L2_MPEG_AUDIO_L3_BITRATE_224K = 11, + V4L2_MPEG_AUDIO_L3_BITRATE_256K = 12, + V4L2_MPEG_AUDIO_L3_BITRATE_320K = 13, +}; +#define V4L2_CID_MPEG_AUDIO_MODE (V4L2_CID_MPEG_BASE+105) +enum v4l2_mpeg_audio_mode { + V4L2_MPEG_AUDIO_MODE_STEREO = 0, + V4L2_MPEG_AUDIO_MODE_JOINT_STEREO = 1, + V4L2_MPEG_AUDIO_MODE_DUAL = 2, + V4L2_MPEG_AUDIO_MODE_MONO = 3, +}; +#define V4L2_CID_MPEG_AUDIO_MODE_EXTENSION (V4L2_CID_MPEG_BASE+106) +enum v4l2_mpeg_audio_mode_extension { + V4L2_MPEG_AUDIO_MODE_EXTENSION_BOUND_4 = 0, + V4L2_MPEG_AUDIO_MODE_EXTENSION_BOUND_8 = 1, + V4L2_MPEG_AUDIO_MODE_EXTENSION_BOUND_12 = 2, + V4L2_MPEG_AUDIO_MODE_EXTENSION_BOUND_16 = 3, +}; +#define V4L2_CID_MPEG_AUDIO_EMPHASIS (V4L2_CID_MPEG_BASE+107) +enum v4l2_mpeg_audio_emphasis { + V4L2_MPEG_AUDIO_EMPHASIS_NONE = 0, + V4L2_MPEG_AUDIO_EMPHASIS_50_DIV_15_uS = 1, + V4L2_MPEG_AUDIO_EMPHASIS_CCITT_J17 = 2, +}; +#define V4L2_CID_MPEG_AUDIO_CRC (V4L2_CID_MPEG_BASE+108) +enum v4l2_mpeg_audio_crc { + V4L2_MPEG_AUDIO_CRC_NONE = 0, + V4L2_MPEG_AUDIO_CRC_CRC16 = 1, +}; +#define V4L2_CID_MPEG_AUDIO_MUTE (V4L2_CID_MPEG_BASE+109) +#define V4L2_CID_MPEG_AUDIO_AAC_BITRATE (V4L2_CID_MPEG_BASE+110) +#define V4L2_CID_MPEG_AUDIO_AC3_BITRATE (V4L2_CID_MPEG_BASE+111) +enum v4l2_mpeg_audio_ac3_bitrate { + V4L2_MPEG_AUDIO_AC3_BITRATE_32K = 0, + V4L2_MPEG_AUDIO_AC3_BITRATE_40K = 1, + V4L2_MPEG_AUDIO_AC3_BITRATE_48K = 2, + V4L2_MPEG_AUDIO_AC3_BITRATE_56K = 3, + V4L2_MPEG_AUDIO_AC3_BITRATE_64K = 4, + V4L2_MPEG_AUDIO_AC3_BITRATE_80K = 5, + V4L2_MPEG_AUDIO_AC3_BITRATE_96K = 6, + V4L2_MPEG_AUDIO_AC3_BITRATE_112K = 7, + V4L2_MPEG_AUDIO_AC3_BITRATE_128K = 8, + V4L2_MPEG_AUDIO_AC3_BITRATE_160K = 9, + V4L2_MPEG_AUDIO_AC3_BITRATE_192K = 10, + V4L2_MPEG_AUDIO_AC3_BITRATE_224K = 11, + V4L2_MPEG_AUDIO_AC3_BITRATE_256K = 12, + V4L2_MPEG_AUDIO_AC3_BITRATE_320K = 13, + V4L2_MPEG_AUDIO_AC3_BITRATE_384K = 14, + V4L2_MPEG_AUDIO_AC3_BITRATE_448K = 15, + V4L2_MPEG_AUDIO_AC3_BITRATE_512K = 16, + V4L2_MPEG_AUDIO_AC3_BITRATE_576K = 17, + V4L2_MPEG_AUDIO_AC3_BITRATE_640K = 18, +}; +#define V4L2_CID_MPEG_AUDIO_DEC_PLAYBACK (V4L2_CID_MPEG_BASE+112) +enum v4l2_mpeg_audio_dec_playback { + V4L2_MPEG_AUDIO_DEC_PLAYBACK_AUTO = 0, + V4L2_MPEG_AUDIO_DEC_PLAYBACK_STEREO = 1, + V4L2_MPEG_AUDIO_DEC_PLAYBACK_LEFT = 2, + V4L2_MPEG_AUDIO_DEC_PLAYBACK_RIGHT = 3, + V4L2_MPEG_AUDIO_DEC_PLAYBACK_MONO = 4, + V4L2_MPEG_AUDIO_DEC_PLAYBACK_SWAPPED_STEREO = 5, +}; +#define V4L2_CID_MPEG_AUDIO_DEC_MULTILINGUAL_PLAYBACK (V4L2_CID_MPEG_BASE+113) + +/* MPEG video controls specific to multiplexed streams */ +#define V4L2_CID_MPEG_VIDEO_ENCODING (V4L2_CID_MPEG_BASE+200) +enum v4l2_mpeg_video_encoding { + V4L2_MPEG_VIDEO_ENCODING_MPEG_1 = 0, + V4L2_MPEG_VIDEO_ENCODING_MPEG_2 = 1, + V4L2_MPEG_VIDEO_ENCODING_MPEG_4_AVC = 2, +}; +#define V4L2_CID_MPEG_VIDEO_ASPECT (V4L2_CID_MPEG_BASE+201) +enum v4l2_mpeg_video_aspect { + V4L2_MPEG_VIDEO_ASPECT_1x1 = 0, + V4L2_MPEG_VIDEO_ASPECT_4x3 = 1, + V4L2_MPEG_VIDEO_ASPECT_16x9 = 2, + V4L2_MPEG_VIDEO_ASPECT_221x100 = 3, +}; +#define V4L2_CID_MPEG_VIDEO_B_FRAMES (V4L2_CID_MPEG_BASE+202) +#define V4L2_CID_MPEG_VIDEO_GOP_SIZE (V4L2_CID_MPEG_BASE+203) +#define V4L2_CID_MPEG_VIDEO_GOP_CLOSURE (V4L2_CID_MPEG_BASE+204) +#define V4L2_CID_MPEG_VIDEO_PULLDOWN (V4L2_CID_MPEG_BASE+205) +#define V4L2_CID_MPEG_VIDEO_BITRATE_MODE (V4L2_CID_MPEG_BASE+206) +enum v4l2_mpeg_video_bitrate_mode { + V4L2_MPEG_VIDEO_BITRATE_MODE_VBR = 0, + V4L2_MPEG_VIDEO_BITRATE_MODE_CBR = 1, +}; +#define V4L2_CID_MPEG_VIDEO_BITRATE (V4L2_CID_MPEG_BASE+207) +#define V4L2_CID_MPEG_VIDEO_BITRATE_PEAK (V4L2_CID_MPEG_BASE+208) +#define V4L2_CID_MPEG_VIDEO_TEMPORAL_DECIMATION (V4L2_CID_MPEG_BASE+209) +#define V4L2_CID_MPEG_VIDEO_MUTE (V4L2_CID_MPEG_BASE+210) +#define V4L2_CID_MPEG_VIDEO_MUTE_YUV (V4L2_CID_MPEG_BASE+211) +#define V4L2_CID_MPEG_VIDEO_DECODER_SLICE_INTERFACE (V4L2_CID_MPEG_BASE+212) +#define V4L2_CID_MPEG_VIDEO_DECODER_MPEG4_DEBLOCK_FILTER (V4L2_CID_MPEG_BASE+213) +#define V4L2_CID_MPEG_VIDEO_CYCLIC_INTRA_REFRESH_MB (V4L2_CID_MPEG_BASE+214) +#define V4L2_CID_MPEG_VIDEO_FRAME_RC_ENABLE (V4L2_CID_MPEG_BASE+215) +#define V4L2_CID_MPEG_VIDEO_HEADER_MODE (V4L2_CID_MPEG_BASE+216) +enum v4l2_mpeg_video_header_mode { + V4L2_MPEG_VIDEO_HEADER_MODE_SEPARATE = 0, + V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME = 1, + V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_I_FRAME = 2, + +}; +#define V4L2_CID_MPEG_VIDEO_MAX_REF_PIC (V4L2_CID_MPEG_BASE+217) +#define V4L2_CID_MPEG_VIDEO_MB_RC_ENABLE (V4L2_CID_MPEG_BASE+218) +#define V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MAX_BYTES (V4L2_CID_MPEG_BASE+219) +#define V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MAX_MB (V4L2_CID_MPEG_BASE+220) +#define V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MODE (V4L2_CID_MPEG_BASE+221) +enum v4l2_mpeg_video_multi_slice_mode { + V4L2_MPEG_VIDEO_MULTI_SLICE_MODE_SINGLE = 0, + V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_MB = 1, + V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_BYTES = 2, + V4L2_MPEG_VIDEO_MULTI_SLICE_GOB = 3, +}; +#define V4L2_CID_MPEG_VIDEO_VBV_SIZE (V4L2_CID_MPEG_BASE+222) +#define V4L2_CID_MPEG_VIDEO_DEC_PTS (V4L2_CID_MPEG_BASE+223) +#define V4L2_CID_MPEG_VIDEO_DEC_FRAME (V4L2_CID_MPEG_BASE+224) + +#define V4L2_CID_MPEG_VIDEO_H263_I_FRAME_QP (V4L2_CID_MPEG_BASE+300) +#define V4L2_CID_MPEG_VIDEO_H263_P_FRAME_QP (V4L2_CID_MPEG_BASE+301) +#define V4L2_CID_MPEG_VIDEO_H263_B_FRAME_QP (V4L2_CID_MPEG_BASE+302) +#define V4L2_CID_MPEG_VIDEO_H263_MIN_QP (V4L2_CID_MPEG_BASE+303) +#define V4L2_CID_MPEG_VIDEO_H263_MAX_QP (V4L2_CID_MPEG_BASE+304) +#define V4L2_CID_MPEG_VIDEO_H264_I_FRAME_QP (V4L2_CID_MPEG_BASE+350) +#define V4L2_CID_MPEG_VIDEO_H264_P_FRAME_QP (V4L2_CID_MPEG_BASE+351) +#define V4L2_CID_MPEG_VIDEO_H264_B_FRAME_QP (V4L2_CID_MPEG_BASE+352) +#define V4L2_CID_MPEG_VIDEO_H264_MIN_QP (V4L2_CID_MPEG_BASE+353) +#define V4L2_CID_MPEG_VIDEO_H264_MAX_QP (V4L2_CID_MPEG_BASE+354) +#define V4L2_CID_MPEG_VIDEO_H264_8X8_TRANSFORM (V4L2_CID_MPEG_BASE+355) +#define V4L2_CID_MPEG_VIDEO_H264_CPB_SIZE (V4L2_CID_MPEG_BASE+356) +#define V4L2_CID_MPEG_VIDEO_H264_ENTROPY_MODE (V4L2_CID_MPEG_BASE+357) +enum v4l2_mpeg_video_h264_entropy_mode { + V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CAVLC = 0, + V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CABAC = 1, +}; +#define V4L2_CID_MPEG_VIDEO_H264_I_PERIOD (V4L2_CID_MPEG_BASE+358) +#define V4L2_CID_MPEG_VIDEO_H264_LEVEL (V4L2_CID_MPEG_BASE+359) +enum v4l2_mpeg_video_h264_level { + V4L2_MPEG_VIDEO_H264_LEVEL_1_0 = 0, + V4L2_MPEG_VIDEO_H264_LEVEL_1B = 1, + V4L2_MPEG_VIDEO_H264_LEVEL_1_1 = 2, + V4L2_MPEG_VIDEO_H264_LEVEL_1_2 = 3, + V4L2_MPEG_VIDEO_H264_LEVEL_1_3 = 4, + V4L2_MPEG_VIDEO_H264_LEVEL_2_0 = 5, + V4L2_MPEG_VIDEO_H264_LEVEL_2_1 = 6, + V4L2_MPEG_VIDEO_H264_LEVEL_2_2 = 7, + V4L2_MPEG_VIDEO_H264_LEVEL_3_0 = 8, + V4L2_MPEG_VIDEO_H264_LEVEL_3_1 = 9, + V4L2_MPEG_VIDEO_H264_LEVEL_3_2 = 10, + V4L2_MPEG_VIDEO_H264_LEVEL_4_0 = 11, + V4L2_MPEG_VIDEO_H264_LEVEL_4_1 = 12, + V4L2_MPEG_VIDEO_H264_LEVEL_4_2 = 13, + V4L2_MPEG_VIDEO_H264_LEVEL_5_0 = 14, + V4L2_MPEG_VIDEO_H264_LEVEL_5_1 = 15, +}; +#define V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_ALPHA (V4L2_CID_MPEG_BASE+360) +#define V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_BETA (V4L2_CID_MPEG_BASE+361) +#define V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_MODE (V4L2_CID_MPEG_BASE+362) +enum v4l2_mpeg_video_h264_loop_filter_mode { + V4L2_MPEG_VIDEO_H264_LOOP_FILTER_MODE_ENABLED = 0, + V4L2_MPEG_VIDEO_H264_LOOP_FILTER_MODE_DISABLED = 1, + V4L2_MPEG_VIDEO_H264_LOOP_FILTER_MODE_DISABLED_AT_SLICE_BOUNDARY = 2, +}; +#define V4L2_CID_MPEG_VIDEO_H264_PROFILE (V4L2_CID_MPEG_BASE+363) +enum v4l2_mpeg_video_h264_profile { + V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE = 0, + V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_BASELINE = 1, + V4L2_MPEG_VIDEO_H264_PROFILE_MAIN = 2, + V4L2_MPEG_VIDEO_H264_PROFILE_EXTENDED = 3, + V4L2_MPEG_VIDEO_H264_PROFILE_HIGH = 4, + V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_10 = 5, + V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_422 = 6, + V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_444_PREDICTIVE = 7, + V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_10_INTRA = 8, + V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_422_INTRA = 9, + V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_444_INTRA = 10, + V4L2_MPEG_VIDEO_H264_PROFILE_CAVLC_444_INTRA = 11, + V4L2_MPEG_VIDEO_H264_PROFILE_SCALABLE_BASELINE = 12, + V4L2_MPEG_VIDEO_H264_PROFILE_SCALABLE_HIGH = 13, + V4L2_MPEG_VIDEO_H264_PROFILE_SCALABLE_HIGH_INTRA = 14, + V4L2_MPEG_VIDEO_H264_PROFILE_STEREO_HIGH = 15, + V4L2_MPEG_VIDEO_H264_PROFILE_MULTIVIEW_HIGH = 16, + V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_HIGH = 17, +}; +#define V4L2_CID_MPEG_VIDEO_H264_VUI_EXT_SAR_HEIGHT (V4L2_CID_MPEG_BASE+364) +#define V4L2_CID_MPEG_VIDEO_H264_VUI_EXT_SAR_WIDTH (V4L2_CID_MPEG_BASE+365) +#define V4L2_CID_MPEG_VIDEO_H264_VUI_SAR_ENABLE (V4L2_CID_MPEG_BASE+366) +#define V4L2_CID_MPEG_VIDEO_H264_VUI_SAR_IDC (V4L2_CID_MPEG_BASE+367) +enum v4l2_mpeg_video_h264_vui_sar_idc { + V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_UNSPECIFIED = 0, + V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_1x1 = 1, + V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_12x11 = 2, + V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_10x11 = 3, + V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_16x11 = 4, + V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_40x33 = 5, + V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_24x11 = 6, + V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_20x11 = 7, + V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_32x11 = 8, + V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_80x33 = 9, + V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_18x11 = 10, + V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_15x11 = 11, + V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_64x33 = 12, + V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_160x99 = 13, + V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_4x3 = 14, + V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_3x2 = 15, + V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_2x1 = 16, + V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_EXTENDED = 17, +}; +#define V4L2_CID_MPEG_VIDEO_MPEG4_I_FRAME_QP (V4L2_CID_MPEG_BASE+400) +#define V4L2_CID_MPEG_VIDEO_MPEG4_P_FRAME_QP (V4L2_CID_MPEG_BASE+401) +#define V4L2_CID_MPEG_VIDEO_MPEG4_B_FRAME_QP (V4L2_CID_MPEG_BASE+402) +#define V4L2_CID_MPEG_VIDEO_MPEG4_MIN_QP (V4L2_CID_MPEG_BASE+403) +#define V4L2_CID_MPEG_VIDEO_MPEG4_MAX_QP (V4L2_CID_MPEG_BASE+404) +#define V4L2_CID_MPEG_VIDEO_MPEG4_LEVEL (V4L2_CID_MPEG_BASE+405) +enum v4l2_mpeg_video_mpeg4_level { + V4L2_MPEG_VIDEO_MPEG4_LEVEL_0 = 0, + V4L2_MPEG_VIDEO_MPEG4_LEVEL_0B = 1, + V4L2_MPEG_VIDEO_MPEG4_LEVEL_1 = 2, + V4L2_MPEG_VIDEO_MPEG4_LEVEL_2 = 3, + V4L2_MPEG_VIDEO_MPEG4_LEVEL_3 = 4, + V4L2_MPEG_VIDEO_MPEG4_LEVEL_3B = 5, + V4L2_MPEG_VIDEO_MPEG4_LEVEL_4 = 6, + V4L2_MPEG_VIDEO_MPEG4_LEVEL_5 = 7, +}; +#define V4L2_CID_MPEG_VIDEO_MPEG4_PROFILE (V4L2_CID_MPEG_BASE+406) +enum v4l2_mpeg_video_mpeg4_profile { + V4L2_MPEG_VIDEO_MPEG4_PROFILE_SIMPLE = 0, + V4L2_MPEG_VIDEO_MPEG4_PROFILE_ADVANCED_SIMPLE = 1, + V4L2_MPEG_VIDEO_MPEG4_PROFILE_CORE = 2, + V4L2_MPEG_VIDEO_MPEG4_PROFILE_SIMPLE_SCALABLE = 3, + V4L2_MPEG_VIDEO_MPEG4_PROFILE_ADVANCED_CODING_EFFICIENCY = 4, +}; +#define V4L2_CID_MPEG_VIDEO_MPEG4_QPEL (V4L2_CID_MPEG_BASE+407) +#define V4L2_CID_QCOM_VIDEO_SYNC_FRAME_SEQ_HDR (V4L2_CID_MPEG_BASE+408) + +/* MPEG-class control IDs specific to the CX2341x driver as defined by V4L2 */ +#define V4L2_CID_MPEG_CX2341X_BASE (V4L2_CTRL_CLASS_MPEG | 0x1000) +#define V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER_MODE (V4L2_CID_MPEG_CX2341X_BASE+0) +enum v4l2_mpeg_cx2341x_video_spatial_filter_mode { + V4L2_MPEG_CX2341X_VIDEO_SPATIAL_FILTER_MODE_MANUAL = 0, + V4L2_MPEG_CX2341X_VIDEO_SPATIAL_FILTER_MODE_AUTO = 1, +}; +#define V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER (V4L2_CID_MPEG_CX2341X_BASE+1) +#define V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE (V4L2_CID_MPEG_CX2341X_BASE+2) +enum v4l2_mpeg_cx2341x_video_luma_spatial_filter_type { + V4L2_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE_OFF = 0, + V4L2_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE_1D_HOR = 1, + V4L2_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE_1D_VERT = 2, + V4L2_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE_2D_HV_SEPARABLE = 3, + V4L2_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE_2D_SYM_NON_SEPARABLE = 4, +}; +#define V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_SPATIAL_FILTER_TYPE (V4L2_CID_MPEG_CX2341X_BASE+3) +enum v4l2_mpeg_cx2341x_video_chroma_spatial_filter_type { + V4L2_MPEG_CX2341X_VIDEO_CHROMA_SPATIAL_FILTER_TYPE_OFF = 0, + V4L2_MPEG_CX2341X_VIDEO_CHROMA_SPATIAL_FILTER_TYPE_1D_HOR = 1, +}; +#define V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER_MODE (V4L2_CID_MPEG_CX2341X_BASE+4) +enum v4l2_mpeg_cx2341x_video_temporal_filter_mode { + V4L2_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER_MODE_MANUAL = 0, + V4L2_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER_MODE_AUTO = 1, +}; +#define V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER (V4L2_CID_MPEG_CX2341X_BASE+5) +#define V4L2_CID_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE (V4L2_CID_MPEG_CX2341X_BASE+6) +enum v4l2_mpeg_cx2341x_video_median_filter_type { + V4L2_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE_OFF = 0, + V4L2_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE_HOR = 1, + V4L2_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE_VERT = 2, + V4L2_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE_HOR_VERT = 3, + V4L2_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE_DIAG = 4, +}; +#define V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_BOTTOM (V4L2_CID_MPEG_CX2341X_BASE+7) +#define V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_TOP (V4L2_CID_MPEG_CX2341X_BASE+8) +#define V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_BOTTOM (V4L2_CID_MPEG_CX2341X_BASE+9) +#define V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_TOP (V4L2_CID_MPEG_CX2341X_BASE+10) +#define V4L2_CID_MPEG_CX2341X_STREAM_INSERT_NAV_PACKETS (V4L2_CID_MPEG_CX2341X_BASE+11) + +/* MPEG-class control IDs specific to the Samsung MFC 5.1 driver as defined by V4L2 */ +#define V4L2_CID_MPEG_MFC51_BASE (V4L2_CTRL_CLASS_MPEG | 0x1100) + +#define V4L2_CID_MPEG_MFC51_VIDEO_DECODER_H264_DISPLAY_DELAY (V4L2_CID_MPEG_MFC51_BASE+0) +#define V4L2_CID_MPEG_MFC51_VIDEO_DECODER_H264_DISPLAY_DELAY_ENABLE (V4L2_CID_MPEG_MFC51_BASE+1) +#define V4L2_CID_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE (V4L2_CID_MPEG_MFC51_BASE+2) +enum v4l2_mpeg_mfc51_video_frame_skip_mode { + V4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_DISABLED = 0, + V4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_LEVEL_LIMIT = 1, + V4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT = 2, +}; +#define V4L2_CID_MPEG_MFC51_VIDEO_FORCE_FRAME_TYPE (V4L2_CID_MPEG_MFC51_BASE+3) +enum v4l2_mpeg_mfc51_video_force_frame_type { + V4L2_MPEG_MFC51_VIDEO_FORCE_FRAME_TYPE_DISABLED = 0, + V4L2_MPEG_MFC51_VIDEO_FORCE_FRAME_TYPE_I_FRAME = 1, + V4L2_MPEG_MFC51_VIDEO_FORCE_FRAME_TYPE_NOT_CODED = 2, +}; +#define V4L2_CID_MPEG_MFC51_VIDEO_PADDING (V4L2_CID_MPEG_MFC51_BASE+4) +#define V4L2_CID_MPEG_MFC51_VIDEO_PADDING_YUV (V4L2_CID_MPEG_MFC51_BASE+5) +#define V4L2_CID_MPEG_MFC51_VIDEO_RC_FIXED_TARGET_BIT (V4L2_CID_MPEG_MFC51_BASE+6) +#define V4L2_CID_MPEG_MFC51_VIDEO_RC_REACTION_COEFF (V4L2_CID_MPEG_MFC51_BASE+7) +#define V4L2_CID_MPEG_MFC51_VIDEO_H264_ADAPTIVE_RC_ACTIVITY (V4L2_CID_MPEG_MFC51_BASE+50) +#define V4L2_CID_MPEG_MFC51_VIDEO_H264_ADAPTIVE_RC_DARK (V4L2_CID_MPEG_MFC51_BASE+51) +#define V4L2_CID_MPEG_MFC51_VIDEO_H264_ADAPTIVE_RC_SMOOTH (V4L2_CID_MPEG_MFC51_BASE+52) +#define V4L2_CID_MPEG_MFC51_VIDEO_H264_ADAPTIVE_RC_STATIC (V4L2_CID_MPEG_MFC51_BASE+53) +#define V4L2_CID_MPEG_MFC51_VIDEO_H264_NUM_REF_PIC_FOR_P (V4L2_CID_MPEG_MFC51_BASE+54) + +/* MPEG-class control IDs specific to the msm_vidc driver */ +#define V4L2_CID_MPEG_MSM_VIDC_BASE (V4L2_CTRL_CLASS_MPEG | 0x2000) + +#define V4L2_CID_MPEG_VIDC_VIDEO_ENABLE_PICTURE_TYPE \ + (V4L2_CID_MPEG_MSM_VIDC_BASE+0) +#define V4L2_CID_MPEG_VIDC_VIDEO_KEEP_ASPECT_RATIO \ + (V4L2_CID_MPEG_MSM_VIDC_BASE+1) +#define V4L2_CID_MPEG_VIDC_VIDEO_POST_LOOP_DEBLOCKER_MODE \ + (V4L2_CID_MPEG_MSM_VIDC_BASE+2) +#define V4L2_CID_MPEG_VIDC_VIDEO_DIVX_FORMAT \ + (V4L2_CID_MPEG_MSM_VIDC_BASE+3) +enum v4l2_mpeg_vidc_video_divx_format_type { + V4L2_MPEG_VIDC_VIDEO_DIVX_FORMAT_4 = 0, + V4L2_MPEG_VIDC_VIDEO_DIVX_FORMAT_5 = 1, + V4L2_MPEG_VIDC_VIDEO_DIVX_FORMAT_6 = 2, +}; +#define V4L2_CID_MPEG_VIDC_VIDEO_MB_ERROR_MAP_REPORTING \ + (V4L2_CID_MPEG_MSM_VIDC_BASE+4) +#define V4L2_CID_MPEG_VIDC_VIDEO_CONTINUE_DATA_TRANSFER \ + (V4L2_CID_MPEG_MSM_VIDC_BASE+5) + +#define V4L2_CID_MPEG_VIDC_VIDEO_STREAM_FORMAT (V4L2_CID_MPEG_MSM_VIDC_BASE+6) +enum v4l2_mpeg_vidc_video_stream_format { + V4L2_MPEG_VIDC_VIDEO_NAL_FORMAT_STARTCODES = 0, + V4L2_MPEG_VIDC_VIDEO_NAL_FORMAT_ONE_NAL_PER_BUFFER = 1, + V4L2_MPEG_VIDC_VIDEO_NAL_FORMAT_ONE_BYTE_LENGTH = 2, + V4L2_MPEG_VIDC_VIDEO_NAL_FORMAT_TWO_BYTE_LENGTH = 3, + V4L2_MPEG_VIDC_VIDEO_NAL_FORMAT_FOUR_BYTE_LENGTH = 4, +}; + +#define V4L2_CID_MPEG_VIDC_VIDEO_OUTPUT_ORDER (V4L2_CID_MPEG_MSM_VIDC_BASE+7) +enum v4l2_mpeg_vidc_video_output_order { + V4L2_MPEG_VIDC_VIDEO_OUTPUT_ORDER_DISPLAY = 0, + V4L2_MPEG_VIDC_VIDEO_OUTPUT_ORDER_DECODE = 1, +}; + +#define V4L2_CID_MPEG_VIDC_VIDEO_FRAME_RATE (V4L2_CID_MPEG_MSM_VIDC_BASE+8) +#define V4L2_CID_MPEG_VIDC_VIDEO_IDR_PERIOD (V4L2_CID_MPEG_MSM_VIDC_BASE+9) +#define V4L2_CID_MPEG_VIDC_VIDEO_NUM_P_FRAMES (V4L2_CID_MPEG_MSM_VIDC_BASE+10) +#define V4L2_CID_MPEG_VIDC_VIDEO_NUM_B_FRAMES (V4L2_CID_MPEG_MSM_VIDC_BASE+11) +#define V4L2_CID_MPEG_VIDC_VIDEO_REQUEST_IFRAME (V4L2_CID_MPEG_MSM_VIDC_BASE+12) + +#define V4L2_CID_MPEG_VIDC_VIDEO_RATE_CONTROL (V4L2_CID_MPEG_MSM_VIDC_BASE+13) +enum v4l2_mpeg_vidc_video_rate_control { + V4L2_CID_MPEG_VIDC_VIDEO_RATE_CONTROL_OFF = 0, + V4L2_CID_MPEG_VIDC_VIDEO_RATE_CONTROL_VBR_VFR = 1, + V4L2_CID_MPEG_VIDC_VIDEO_RATE_CONTROL_VBR_CFR = 2, + V4L2_CID_MPEG_VIDC_VIDEO_RATE_CONTROL_CBR_VFR = 3, + V4L2_CID_MPEG_VIDC_VIDEO_RATE_CONTROL_CBR_CFR = 4, +}; + +#define V4L2_CID_MPEG_VIDC_VIDEO_ROTATION (V4L2_CID_MPEG_MSM_VIDC_BASE+14) +enum v4l2_mpeg_vidc_video_rotation { + V4L2_CID_MPEG_VIDC_VIDEO_ROTATION_NONE = 0, + V4L2_CID_MPEG_VIDC_VIDEO_ROTATION_90 = 1, + V4L2_CID_MPEG_VIDC_VIDEO_ROTATION_180 = 2, + V4L2_CID_MPEG_VIDC_VIDEO_ROTATION_270 = 3, +}; +#define MSM_VIDC_BASE V4L2_CID_MPEG_MSM_VIDC_BASE +#define V4L2_CID_MPEG_VIDC_VIDEO_H264_CABAC_MODEL (MSM_VIDC_BASE+15) +enum v4l2_mpeg_vidc_h264_cabac_model { + V4L2_CID_MPEG_VIDC_VIDEO_H264_CABAC_MODEL_0 = 0, + V4L2_CID_MPEG_VIDC_VIDEO_H264_CABAC_MODEL_1 = 1, + V4L2_CID_MPEG_VIDC_VIDEO_H264_CABAC_MODEL_2 = 2, +}; + +#define V4L2_CID_MPEG_VIDC_VIDEO_INTRA_REFRESH_MODE (MSM_VIDC_BASE+16) +enum v4l2_mpeg_vidc_video_intra_refresh_mode { + V4L2_CID_MPEG_VIDC_VIDEO_INTRA_REFRESH_NONE = 0, + V4L2_CID_MPEG_VIDC_VIDEO_INTRA_REFRESH_CYCLIC = 1, + V4L2_CID_MPEG_VIDC_VIDEO_INTRA_REFRESH_ADAPTIVE = 2, + V4L2_CID_MPEG_VIDC_VIDEO_INTRA_REFRESH_CYCLIC_ADAPTIVE = 3, + V4L2_CID_MPEG_VIDC_VIDEO_INTRA_REFRESH_RANDOM = 4, +}; +#define V4L2_CID_MPEG_VIDC_VIDEO_AIR_MBS (V4L2_CID_MPEG_MSM_VIDC_BASE+17) +#define V4L2_CID_MPEG_VIDC_VIDEO_AIR_REF (V4L2_CID_MPEG_MSM_VIDC_BASE+18) +#define V4L2_CID_MPEG_VIDC_VIDEO_CIR_MBS (V4L2_CID_MPEG_MSM_VIDC_BASE+19) + +#define V4L2_CID_MPEG_VIDC_VIDEO_H263_PROFILE (V4L2_CID_MPEG_MSM_VIDC_BASE+20) +enum v4l2_mpeg_vidc_video_h263_profile { + V4L2_MPEG_VIDC_VIDEO_H263_PROFILE_BASELINE = 0, + V4L2_MPEG_VIDC_VIDEO_H263_PROFILE_H320CODING = 1, + V4L2_MPEG_VIDC_VIDEO_H263_PROFILE_BACKWARDCOMPATIBLE = 2, + V4L2_MPEG_VIDC_VIDEO_H263_PROFILE_ISWV2 = 3, + V4L2_MPEG_VIDC_VIDEO_H263_PROFILE_ISWV3 = 4, + V4L2_MPEG_VIDC_VIDEO_H263_PROFILE_HIGHCOMPRESSION = 5, + V4L2_MPEG_VIDC_VIDEO_H263_PROFILE_INTERNET = 6, + V4L2_MPEG_VIDC_VIDEO_H263_PROFILE_INTERLACE = 7, + V4L2_MPEG_VIDC_VIDEO_H263_PROFILE_HIGHLATENCY = 8, +}; + +#define V4L2_CID_MPEG_VIDC_VIDEO_H263_LEVEL (V4L2_CID_MPEG_MSM_VIDC_BASE+21) +enum v4l2_mpeg_vidc_video_h263_level { + V4L2_MPEG_VIDC_VIDEO_H263_LEVEL_1_0 = 0, + V4L2_MPEG_VIDC_VIDEO_H263_LEVEL_2_0 = 1, + V4L2_MPEG_VIDC_VIDEO_H263_LEVEL_3_0 = 2, + V4L2_MPEG_VIDC_VIDEO_H263_LEVEL_4_0 = 3, + V4L2_MPEG_VIDC_VIDEO_H263_LEVEL_4_5 = 4, + V4L2_MPEG_VIDC_VIDEO_H263_LEVEL_5_0 = 5, + V4L2_MPEG_VIDC_VIDEO_H263_LEVEL_6_0 = 6, + V4L2_MPEG_VIDC_VIDEO_H263_LEVEL_7_0 = 7, +}; + +#define V4L2_CID_MPEG_VIDC_VIDEO_H264_AU_DELIMITER \ + (V4L2_CID_MPEG_MSM_VIDC_BASE + 22) +enum v4l2_mpeg_vidc_video_h264_au_delimiter { + V4L2_MPEG_VIDC_VIDEO_H264_AU_DELIMITER_DISABLED = 0, + V4L2_MPEG_VIDC_VIDEO_H264_AU_DELIMITER_ENABLED = 1 +}; +#define V4L2_CID_MPEG_VIDC_VIDEO_SYNC_FRAME_DECODE \ + (V4L2_CID_MPEG_MSM_VIDC_BASE + 23) +enum v4l2_mpeg_vidc_video_sync_frame_decode { + V4L2_MPEG_VIDC_VIDEO_SYNC_FRAME_DECODE_DISABLE = 0, + V4L2_MPEG_VIDC_VIDEO_SYNC_FRAME_DECODE_ENABLE = 1 +}; +#define V4L2_CID_MPEG_VIDC_VIDEO_SECURE (V4L2_CID_MPEG_MSM_VIDC_BASE+24) +#define V4L2_CID_MPEG_VIDC_VIDEO_EXTRADATA \ + (V4L2_CID_MPEG_MSM_VIDC_BASE + 25) +enum v4l2_mpeg_vidc_extradata { + V4L2_MPEG_VIDC_EXTRADATA_NONE, + V4L2_MPEG_VIDC_EXTRADATA_MB_QUANTIZATION, + V4L2_MPEG_VIDC_EXTRADATA_INTERLACE_VIDEO, + V4L2_MPEG_VIDC_EXTRADATA_VC1_FRAMEDISP, + V4L2_MPEG_VIDC_EXTRADATA_VC1_SEQDISP, + V4L2_MPEG_VIDC_EXTRADATA_TIMESTAMP, + V4L2_MPEG_VIDC_EXTRADATA_S3D_FRAME_PACKING, + V4L2_MPEG_VIDC_EXTRADATA_FRAME_RATE, + V4L2_MPEG_VIDC_EXTRADATA_PANSCAN_WINDOW, + V4L2_MPEG_VIDC_EXTRADATA_RECOVERY_POINT_SEI, + V4L2_MPEG_VIDC_EXTRADATA_CLOSED_CAPTION_UD, + V4L2_MPEG_VIDC_EXTRADATA_AFD_UD, + V4L2_MPEG_VIDC_EXTRADATA_MULTISLICE_INFO, + V4L2_MPEG_VIDC_EXTRADATA_NUM_CONCEALED_MB, + V4L2_MPEG_VIDC_EXTRADATA_METADATA_FILLER, + V4L2_MPEG_VIDC_INDEX_EXTRADATA_INPUT_CROP, + V4L2_MPEG_VIDC_INDEX_EXTRADATA_DIGITAL_ZOOM, + V4L2_MPEG_VIDC_INDEX_EXTRADATA_ASPECT_RATIO, + V4L2_MPEG_VIDC_EXTRADATA_MPEG2_SEQDISP +}; + +#define V4L2_CID_MPEG_VIDC_SET_PERF_LEVEL (V4L2_CID_MPEG_MSM_VIDC_BASE + 26) +enum v4l2_mpeg_vidc_perf_level { + V4L2_CID_MPEG_VIDC_PERF_LEVEL_NOMINAL = 0, + V4L2_CID_MPEG_VIDC_PERF_LEVEL_PERFORMANCE = 1, + V4L2_CID_MPEG_VIDC_PERF_LEVEL_TURBO = 2, +}; + +#define V4L2_CID_MPEG_VIDEO_MULTI_SLICE_GOB \ + (V4L2_CID_MPEG_MSM_VIDC_BASE + 27) + +#define V4L2_CID_MPEG_VIDEO_MULTI_SLICE_DELIVERY_MODE \ + (V4L2_CID_MPEG_MSM_VIDC_BASE + 28) + +#define V4L2_CID_MPEG_VIDC_VIDEO_H264_VUI_TIMING_INFO \ + (V4L2_CID_MPEG_MSM_VIDC_BASE + 29) +enum v4l2_mpeg_vidc_video_h264_vui_timing_info { + V4L2_MPEG_VIDC_VIDEO_H264_VUI_TIMING_INFO_DISABLED = 0, + V4L2_MPEG_VIDC_VIDEO_H264_VUI_TIMING_INFO_ENABLED = 1 +}; + +#define V4L2_CID_MPEG_VIDC_VIDEO_ALLOC_MODE_INPUT \ + (V4L2_CID_MPEG_MSM_VIDC_BASE + 30) +#define V4L2_CID_MPEG_VIDC_VIDEO_ALLOC_MODE_OUTPUT \ + (V4L2_CID_MPEG_MSM_VIDC_BASE + 31) +enum v4l2_mpeg_vidc_video_alloc_mode_type { + V4L2_MPEG_VIDC_VIDEO_STATIC = 0, + V4L2_MPEG_VIDC_VIDEO_RING = 1, + V4L2_MPEG_VIDC_VIDEO_DYNAMIC = 2, +}; + +#define V4L2_CID_MPEG_VIDC_VIDEO_FRAME_ASSEMBLY \ + (V4L2_CID_MPEG_MSM_VIDC_BASE + 32) +enum v4l2_mpeg_vidc_video_assembly { + V4L2_MPEG_VIDC_FRAME_ASSEMBLY_DISABLE = 0, + V4L2_MPEG_VIDC_FRAME_ASSEMBLY_ENABLE = 1, +}; + +#define V4L2_CID_MPEG_VIDC_VIDEO_VP8_PROFILE_LEVEL \ + (V4L2_CID_MPEG_MSM_VIDC_BASE + 33) +enum v4l2_mpeg_vidc_video_vp8_profile_level { + V4L2_MPEG_VIDC_VIDEO_VP8_UNUSED, + V4L2_MPEG_VIDC_VIDEO_VP8_VERSION_0, + V4L2_MPEG_VIDC_VIDEO_VP8_VERSION_1, + V4L2_MPEG_VIDC_VIDEO_VP8_VERSION_2, + V4L2_MPEG_VIDC_VIDEO_VP8_VERSION_3, +}; + +#define V4L2_CID_MPEG_VIDC_VIDEO_H264_VUI_BITSTREAM_RESTRICT \ + (V4L2_CID_MPEG_MSM_VIDC_BASE + 34) +enum v4l2_mpeg_vidc_video_h264_vui_bitstream_restrict { + V4L2_MPEG_VIDC_VIDEO_H264_VUI_BITSTREAM_RESTRICT_DISABLED = 0, + V4L2_MPEG_VIDC_VIDEO_H264_VUI_BITSTREAM_RESTRICT_ENABLED = 1 +}; + +#define V4L2_CID_MPEG_VIDC_VIDEO_PRESERVE_TEXT_QUALITY \ + (V4L2_CID_MPEG_MSM_VIDC_BASE + 35) +enum v4l2_mpeg_vidc_video_preserve_text_quality { + V4L2_MPEG_VIDC_VIDEO_PRESERVE_TEXT_QUALITY_DISABLED = 0, + V4L2_MPEG_VIDC_VIDEO_PRESERVE_TEXT_QUALITY_ENABLED = 1 +}; + +#define V4L2_CID_MPEG_VIDC_VIDEO_REQUEST_SEQ_HEADER \ + (V4L2_CID_MPEG_MSM_VIDC_BASE + 36) + +/* Camera class control IDs */ +#define V4L2_CID_CAMERA_CLASS_BASE (V4L2_CTRL_CLASS_CAMERA | 0x900) +#define V4L2_CID_CAMERA_CLASS (V4L2_CTRL_CLASS_CAMERA | 1) + +#define V4L2_CID_EXPOSURE_AUTO (V4L2_CID_CAMERA_CLASS_BASE+1) +enum v4l2_exposure_auto_type { + V4L2_EXPOSURE_AUTO = 0, + V4L2_EXPOSURE_MANUAL = 1, + V4L2_EXPOSURE_SHUTTER_PRIORITY = 2, + V4L2_EXPOSURE_APERTURE_PRIORITY = 3 +}; +#define V4L2_CID_EXPOSURE_ABSOLUTE (V4L2_CID_CAMERA_CLASS_BASE+2) +#define V4L2_CID_EXPOSURE_AUTO_PRIORITY (V4L2_CID_CAMERA_CLASS_BASE+3) + +#define V4L2_CID_PAN_RELATIVE (V4L2_CID_CAMERA_CLASS_BASE+4) +#define V4L2_CID_TILT_RELATIVE (V4L2_CID_CAMERA_CLASS_BASE+5) +#define V4L2_CID_PAN_RESET (V4L2_CID_CAMERA_CLASS_BASE+6) +#define V4L2_CID_TILT_RESET (V4L2_CID_CAMERA_CLASS_BASE+7) + +#define V4L2_CID_PAN_ABSOLUTE (V4L2_CID_CAMERA_CLASS_BASE+8) +#define V4L2_CID_TILT_ABSOLUTE (V4L2_CID_CAMERA_CLASS_BASE+9) + +#define V4L2_CID_FOCUS_ABSOLUTE (V4L2_CID_CAMERA_CLASS_BASE+10) +#define V4L2_CID_FOCUS_RELATIVE (V4L2_CID_CAMERA_CLASS_BASE+11) +#define V4L2_CID_FOCUS_AUTO (V4L2_CID_CAMERA_CLASS_BASE+12) + +#define V4L2_CID_ZOOM_ABSOLUTE (V4L2_CID_CAMERA_CLASS_BASE+13) +#define V4L2_CID_ZOOM_RELATIVE (V4L2_CID_CAMERA_CLASS_BASE+14) +#define V4L2_CID_ZOOM_CONTINUOUS (V4L2_CID_CAMERA_CLASS_BASE+15) + +#define V4L2_CID_PRIVACY (V4L2_CID_CAMERA_CLASS_BASE+16) + +#define V4L2_CID_IRIS_ABSOLUTE (V4L2_CID_CAMERA_CLASS_BASE+17) +#define V4L2_CID_IRIS_RELATIVE (V4L2_CID_CAMERA_CLASS_BASE+18) + +/* FM Modulator class control IDs */ +#define V4L2_CID_FM_TX_CLASS_BASE (V4L2_CTRL_CLASS_FM_TX | 0x900) +#define V4L2_CID_FM_TX_CLASS (V4L2_CTRL_CLASS_FM_TX | 1) + +#define V4L2_CID_RDS_TX_DEVIATION (V4L2_CID_FM_TX_CLASS_BASE + 1) +#define V4L2_CID_RDS_TX_PI (V4L2_CID_FM_TX_CLASS_BASE + 2) +#define V4L2_CID_RDS_TX_PTY (V4L2_CID_FM_TX_CLASS_BASE + 3) +#define V4L2_CID_RDS_TX_PS_NAME (V4L2_CID_FM_TX_CLASS_BASE + 5) +#define V4L2_CID_RDS_TX_RADIO_TEXT (V4L2_CID_FM_TX_CLASS_BASE + 6) + +#define V4L2_CID_AUDIO_LIMITER_ENABLED (V4L2_CID_FM_TX_CLASS_BASE + 64) +#define V4L2_CID_AUDIO_LIMITER_RELEASE_TIME (V4L2_CID_FM_TX_CLASS_BASE + 65) +#define V4L2_CID_AUDIO_LIMITER_DEVIATION (V4L2_CID_FM_TX_CLASS_BASE + 66) + +#define V4L2_CID_AUDIO_COMPRESSION_ENABLED (V4L2_CID_FM_TX_CLASS_BASE + 80) +#define V4L2_CID_AUDIO_COMPRESSION_GAIN (V4L2_CID_FM_TX_CLASS_BASE + 81) +#define V4L2_CID_AUDIO_COMPRESSION_THRESHOLD (V4L2_CID_FM_TX_CLASS_BASE + 82) +#define V4L2_CID_AUDIO_COMPRESSION_ATTACK_TIME (V4L2_CID_FM_TX_CLASS_BASE + 83) +#define V4L2_CID_AUDIO_COMPRESSION_RELEASE_TIME (V4L2_CID_FM_TX_CLASS_BASE + 84) + +#define V4L2_CID_PILOT_TONE_ENABLED (V4L2_CID_FM_TX_CLASS_BASE + 96) +#define V4L2_CID_PILOT_TONE_DEVIATION (V4L2_CID_FM_TX_CLASS_BASE + 97) +#define V4L2_CID_PILOT_TONE_FREQUENCY (V4L2_CID_FM_TX_CLASS_BASE + 98) + +#define V4L2_CID_TUNE_PREEMPHASIS (V4L2_CID_FM_TX_CLASS_BASE + 112) +enum v4l2_preemphasis { + V4L2_PREEMPHASIS_DISABLED = 0, + V4L2_PREEMPHASIS_50_uS = 1, + V4L2_PREEMPHASIS_75_uS = 2, +}; +#define V4L2_CID_TUNE_POWER_LEVEL (V4L2_CID_FM_TX_CLASS_BASE + 113) +#define V4L2_CID_TUNE_ANTENNA_CAPACITOR (V4L2_CID_FM_TX_CLASS_BASE + 114) + +/* Flash and privacy (indicator) light controls */ +#define V4L2_CID_FLASH_CLASS_BASE (V4L2_CTRL_CLASS_FLASH | 0x900) +#define V4L2_CID_FLASH_CLASS (V4L2_CTRL_CLASS_FLASH | 1) + +#define V4L2_CID_FLASH_LED_MODE (V4L2_CID_FLASH_CLASS_BASE + 1) +enum v4l2_flash_led_mode { + V4L2_FLASH_LED_MODE_NONE, + V4L2_FLASH_LED_MODE_FLASH, + V4L2_FLASH_LED_MODE_TORCH, +}; + +#define V4L2_CID_FLASH_STROBE_SOURCE (V4L2_CID_FLASH_CLASS_BASE + 2) +enum v4l2_flash_strobe_source { + V4L2_FLASH_STROBE_SOURCE_SOFTWARE, + V4L2_FLASH_STROBE_SOURCE_EXTERNAL, +}; + +#define V4L2_CID_FLASH_STROBE (V4L2_CID_FLASH_CLASS_BASE + 3) +#define V4L2_CID_FLASH_STROBE_STOP (V4L2_CID_FLASH_CLASS_BASE + 4) +#define V4L2_CID_FLASH_STROBE_STATUS (V4L2_CID_FLASH_CLASS_BASE + 5) + +#define V4L2_CID_FLASH_TIMEOUT (V4L2_CID_FLASH_CLASS_BASE + 6) +#define V4L2_CID_FLASH_INTENSITY (V4L2_CID_FLASH_CLASS_BASE + 7) +#define V4L2_CID_FLASH_TORCH_INTENSITY (V4L2_CID_FLASH_CLASS_BASE + 8) +#define V4L2_CID_FLASH_INDICATOR_INTENSITY (V4L2_CID_FLASH_CLASS_BASE + 9) + +#define V4L2_CID_FLASH_FAULT (V4L2_CID_FLASH_CLASS_BASE + 10) +#define V4L2_FLASH_FAULT_OVER_VOLTAGE (1 << 0) +#define V4L2_FLASH_FAULT_TIMEOUT (1 << 1) +#define V4L2_FLASH_FAULT_OVER_TEMPERATURE (1 << 2) +#define V4L2_FLASH_FAULT_SHORT_CIRCUIT (1 << 3) +#define V4L2_FLASH_FAULT_OVER_CURRENT (1 << 4) +#define V4L2_FLASH_FAULT_INDICATOR (1 << 5) + +#define V4L2_CID_FLASH_CHARGE (V4L2_CID_FLASH_CLASS_BASE + 11) +#define V4L2_CID_FLASH_READY (V4L2_CID_FLASH_CLASS_BASE + 12) + +/* JPEG-class control IDs defined by V4L2 */ +#define V4L2_CID_JPEG_CLASS_BASE (V4L2_CTRL_CLASS_JPEG | 0x900) +#define V4L2_CID_JPEG_CLASS (V4L2_CTRL_CLASS_JPEG | 1) + +#define V4L2_CID_JPEG_CHROMA_SUBSAMPLING (V4L2_CID_JPEG_CLASS_BASE + 1) +enum v4l2_jpeg_chroma_subsampling { + V4L2_JPEG_CHROMA_SUBSAMPLING_444 = 0, + V4L2_JPEG_CHROMA_SUBSAMPLING_422 = 1, + V4L2_JPEG_CHROMA_SUBSAMPLING_420 = 2, + V4L2_JPEG_CHROMA_SUBSAMPLING_411 = 3, + V4L2_JPEG_CHROMA_SUBSAMPLING_410 = 4, + V4L2_JPEG_CHROMA_SUBSAMPLING_GRAY = 5, +}; +#define V4L2_CID_JPEG_RESTART_INTERVAL (V4L2_CID_JPEG_CLASS_BASE + 2) +#define V4L2_CID_JPEG_COMPRESSION_QUALITY (V4L2_CID_JPEG_CLASS_BASE + 3) + +#define V4L2_CID_JPEG_ACTIVE_MARKER (V4L2_CID_JPEG_CLASS_BASE + 4) +#define V4L2_JPEG_ACTIVE_MARKER_APP0 (1 << 0) +#define V4L2_JPEG_ACTIVE_MARKER_APP1 (1 << 1) +#define V4L2_JPEG_ACTIVE_MARKER_COM (1 << 16) +#define V4L2_JPEG_ACTIVE_MARKER_DQT (1 << 17) +#define V4L2_JPEG_ACTIVE_MARKER_DHT (1 << 18) + +/* + * T U N I N G + */ +struct v4l2_tuner { + __u32 index; + __u8 name[32]; + enum v4l2_tuner_type type; + __u32 capability; + __u32 rangelow; + __u32 rangehigh; + __u32 rxsubchans; + __u32 audmode; + __s32 signal; + __s32 afc; + __u32 reserved[4]; +}; + +struct v4l2_modulator { + __u32 index; + __u8 name[32]; + __u32 capability; + __u32 rangelow; + __u32 rangehigh; + __u32 txsubchans; + __u32 reserved[4]; +}; + +/* Flags for the 'capability' field */ +#define V4L2_TUNER_CAP_LOW 0x0001 +#define V4L2_TUNER_CAP_NORM 0x0002 +#define V4L2_TUNER_CAP_STEREO 0x0010 +#define V4L2_TUNER_CAP_LANG2 0x0020 +#define V4L2_TUNER_CAP_SAP 0x0020 +#define V4L2_TUNER_CAP_LANG1 0x0040 +#define V4L2_TUNER_CAP_RDS 0x0080 +#define V4L2_TUNER_CAP_RDS_BLOCK_IO 0x0100 +#define V4L2_TUNER_CAP_RDS_CONTROLS 0x0200 + +/* Flags for the 'rxsubchans' field */ +#define V4L2_TUNER_SUB_MONO 0x0001 +#define V4L2_TUNER_SUB_STEREO 0x0002 +#define V4L2_TUNER_SUB_LANG2 0x0004 +#define V4L2_TUNER_SUB_SAP 0x0004 +#define V4L2_TUNER_SUB_LANG1 0x0008 +#define V4L2_TUNER_SUB_RDS 0x0010 + +/* Values for the 'audmode' field */ +#define V4L2_TUNER_MODE_MONO 0x0000 +#define V4L2_TUNER_MODE_STEREO 0x0001 +#define V4L2_TUNER_MODE_LANG2 0x0002 +#define V4L2_TUNER_MODE_SAP 0x0002 +#define V4L2_TUNER_MODE_LANG1 0x0003 +#define V4L2_TUNER_MODE_LANG1_LANG2 0x0004 + +struct v4l2_frequency { + __u32 tuner; + enum v4l2_tuner_type type; + __u32 frequency; + __u32 reserved[8]; +}; + +struct v4l2_hw_freq_seek { + __u32 tuner; + enum v4l2_tuner_type type; + __u32 seek_upward; + __u32 wrap_around; + __u32 spacing; + __u32 reserved[7]; +}; + +/* + * R D S + */ + +struct v4l2_rds_data { + __u8 lsb; + __u8 msb; + __u8 block; +} __attribute__ ((packed)); + +#define V4L2_RDS_BLOCK_MSK 0x7 +#define V4L2_RDS_BLOCK_A 0 +#define V4L2_RDS_BLOCK_B 1 +#define V4L2_RDS_BLOCK_C 2 +#define V4L2_RDS_BLOCK_D 3 +#define V4L2_RDS_BLOCK_C_ALT 4 +#define V4L2_RDS_BLOCK_INVALID 7 + +#define V4L2_RDS_BLOCK_CORRECTED 0x40 +#define V4L2_RDS_BLOCK_ERROR 0x80 + +/* + * A U D I O + */ +struct v4l2_audio { + __u32 index; + __u8 name[32]; + __u32 capability; + __u32 mode; + __u32 reserved[2]; +}; + +/* Flags for the 'capability' field */ +#define V4L2_AUDCAP_STEREO 0x00001 +#define V4L2_AUDCAP_AVL 0x00002 + +/* Flags for the 'mode' field */ +#define V4L2_AUDMODE_AVL 0x00001 + +struct v4l2_audioout { + __u32 index; + __u8 name[32]; + __u32 capability; + __u32 mode; + __u32 reserved[2]; +}; + +/* + * M P E G S E R V I C E S + * + * NOTE: EXPERIMENTAL API + */ +#if 1 +#define V4L2_ENC_IDX_FRAME_I (0) +#define V4L2_ENC_IDX_FRAME_P (1) +#define V4L2_ENC_IDX_FRAME_B (2) +#define V4L2_ENC_IDX_FRAME_MASK (0xf) + +struct v4l2_enc_idx_entry { + __u64 offset; + __u64 pts; + __u32 length; + __u32 flags; + __u32 reserved[2]; +}; + +#define V4L2_ENC_IDX_ENTRIES (64) +struct v4l2_enc_idx { + __u32 entries; + __u32 entries_cap; + __u32 reserved[4]; + struct v4l2_enc_idx_entry entry[V4L2_ENC_IDX_ENTRIES]; +}; + + +#define V4L2_ENC_CMD_START (0) +#define V4L2_ENC_CMD_STOP (1) +#define V4L2_ENC_CMD_PAUSE (2) +#define V4L2_ENC_CMD_RESUME (3) +#define V4L2_ENC_QCOM_CMD_FLUSH (4) + +/* Flags for V4L2_ENC_CMD_STOP */ +#define V4L2_ENC_CMD_STOP_AT_GOP_END (1 << 0) + +struct v4l2_encoder_cmd { + __u32 cmd; + __u32 flags; + union { + struct { + __u32 data[8]; + } raw; + }; +}; + +/* Decoder commands */ +#define V4L2_DEC_CMD_START (0) +#define V4L2_DEC_CMD_STOP (1) +#define V4L2_DEC_CMD_PAUSE (2) +#define V4L2_DEC_CMD_RESUME (3) +#define V4L2_DEC_QCOM_CMD_FLUSH (4) + +/* Flags for V4L2_DEC_CMD_START */ +#define V4L2_DEC_CMD_START_MUTE_AUDIO (1 << 0) + +/* Flags for V4L2_DEC_CMD_PAUSE */ +#define V4L2_DEC_CMD_PAUSE_TO_BLACK (1 << 0) + +/* Flags for V4L2_DEC_CMD_STOP */ +#define V4L2_DEC_CMD_STOP_TO_BLACK (1 << 0) +#define V4L2_DEC_CMD_STOP_IMMEDIATELY (1 << 1) + +/* Flags for V4L2_DEC_QCOM_CMD_FLUSH */ +#define V4L2_DEC_QCOM_CMD_FLUSH_OUTPUT (1 << 0) +#define V4L2_DEC_QCOM_CMD_FLUSH_CAPTURE (1 << 1) + +#define V4L2_QCOM_CMD_FLUSH_OUTPUT (1 << 0) +#define V4L2_QCOM_CMD_FLUSH_CAPTURE (1 << 1) + +/* Play format requirements (returned by the driver): */ + +/* The decoder has no special format requirements */ +#define V4L2_DEC_START_FMT_NONE (0) +/* The decoder requires full GOPs */ +#define V4L2_DEC_START_FMT_GOP (1) + +/* The structure must be zeroed before use by the application + This ensures it can be extended safely in the future. */ +struct v4l2_decoder_cmd { + __u32 cmd; + __u32 flags; + union { + struct { + __u64 pts; + } stop; + + struct { + /* 0 or 1000 specifies normal speed, + 1 specifies forward single stepping, + -1 specifies backward single stepping, + >1: playback at speed/1000 of the normal speed, + <-1: reverse playback at (-speed/1000) of the normal speed. */ + __s32 speed; + __u32 format; + } start; + + struct { + __u32 data[16]; + } raw; + }; +}; +#endif + + +/* + * D A T A S E R V I C E S ( V B I ) + * + * Data services API by Michael Schimek + */ + +/* Raw VBI */ +struct v4l2_vbi_format { + __u32 sampling_rate; /* in 1 Hz */ + __u32 offset; + __u32 samples_per_line; + __u32 sample_format; /* V4L2_PIX_FMT_* */ + __s32 start[2]; + __u32 count[2]; + __u32 flags; /* V4L2_VBI_* */ + __u32 reserved[2]; /* must be zero */ +}; + +/* VBI flags */ +#define V4L2_VBI_UNSYNC (1 << 0) +#define V4L2_VBI_INTERLACED (1 << 1) + +/* Sliced VBI + * + * This implements is a proposal V4L2 API to allow SLICED VBI + * required for some hardware encoders. It should change without + * notice in the definitive implementation. + */ + +struct v4l2_sliced_vbi_format { + __u16 service_set; + /* service_lines[0][...] specifies lines 0-23 (1-23 used) of the first field + service_lines[1][...] specifies lines 0-23 (1-23 used) of the second field + (equals frame lines 313-336 for 625 line video + standards, 263-286 for 525 line standards) */ + __u16 service_lines[2][24]; + __u32 io_size; + __u32 reserved[2]; /* must be zero */ +}; + +/* Teletext World System Teletext + (WST), defined on ITU-R BT.653-2 */ +#define V4L2_SLICED_TELETEXT_B (0x0001) +/* Video Program System, defined on ETS 300 231*/ +#define V4L2_SLICED_VPS (0x0400) +/* Closed Caption, defined on EIA-608 */ +#define V4L2_SLICED_CAPTION_525 (0x1000) +/* Wide Screen System, defined on ITU-R BT1119.1 */ +#define V4L2_SLICED_WSS_625 (0x4000) + +#define V4L2_SLICED_VBI_525 (V4L2_SLICED_CAPTION_525) +#define V4L2_SLICED_VBI_625 (V4L2_SLICED_TELETEXT_B | V4L2_SLICED_VPS | V4L2_SLICED_WSS_625) + +struct v4l2_sliced_vbi_cap { + __u16 service_set; + /* service_lines[0][...] specifies lines 0-23 (1-23 used) of the first field + service_lines[1][...] specifies lines 0-23 (1-23 used) of the second field + (equals frame lines 313-336 for 625 line video + standards, 263-286 for 525 line standards) */ + __u16 service_lines[2][24]; + enum v4l2_buf_type type; + __u32 reserved[3]; /* must be 0 */ +}; + +struct v4l2_sliced_vbi_data { + __u32 id; + __u32 field; /* 0: first field, 1: second field */ + __u32 line; /* 1-23 */ + __u32 reserved; /* must be 0 */ + __u8 data[48]; +}; + +/* + * Sliced VBI data inserted into MPEG Streams + */ + +/* + * V4L2_MPEG_STREAM_VBI_FMT_IVTV: + * + * Structure of payload contained in an MPEG 2 Private Stream 1 PES Packet in an + * MPEG-2 Program Pack that contains V4L2_MPEG_STREAM_VBI_FMT_IVTV Sliced VBI + * data + * + * Note, the MPEG-2 Program Pack and Private Stream 1 PES packet header + * definitions are not included here. See the MPEG-2 specifications for details + * on these headers. + */ + +/* Line type IDs */ +#define V4L2_MPEG_VBI_IVTV_TELETEXT_B (1) +#define V4L2_MPEG_VBI_IVTV_CAPTION_525 (4) +#define V4L2_MPEG_VBI_IVTV_WSS_625 (5) +#define V4L2_MPEG_VBI_IVTV_VPS (7) + +struct v4l2_mpeg_vbi_itv0_line { + __u8 id; /* One of V4L2_MPEG_VBI_IVTV_* above */ + __u8 data[42]; /* Sliced VBI data for the line */ +} __attribute__ ((packed)); + +struct v4l2_mpeg_vbi_itv0 { + __le32 linemask[2]; /* Bitmasks of VBI service lines present */ + struct v4l2_mpeg_vbi_itv0_line line[35]; +} __attribute__ ((packed)); + +struct v4l2_mpeg_vbi_ITV0 { + struct v4l2_mpeg_vbi_itv0_line line[36]; +} __attribute__ ((packed)); + +#define V4L2_MPEG_VBI_IVTV_MAGIC0 "itv0" +#define V4L2_MPEG_VBI_IVTV_MAGIC1 "ITV0" + +struct v4l2_mpeg_vbi_fmt_ivtv { + __u8 magic[4]; + union { + struct v4l2_mpeg_vbi_itv0 itv0; + struct v4l2_mpeg_vbi_ITV0 ITV0; + }; +} __attribute__ ((packed)); + +/* + * A G G R E G A T E S T R U C T U R E S + */ + +/** + * struct v4l2_plane_pix_format - additional, per-plane format definition + * @sizeimage: maximum size in bytes required for data, for which + * this plane will be used + * @bytesperline: distance in bytes between the leftmost pixels in two + * adjacent lines + */ +struct v4l2_plane_pix_format { + __u32 sizeimage; + __u16 bytesperline; + __u16 reserved[7]; +} __attribute__ ((packed)); + +/** + * struct v4l2_pix_format_mplane - multiplanar format definition + * @width: image width in pixels + * @height: image height in pixels + * @pixelformat: little endian four character code (fourcc) + * @field: field order (for interlaced video) + * @colorspace: supplemental to pixelformat + * @plane_fmt: per-plane information + * @num_planes: number of planes for this format + */ +struct v4l2_pix_format_mplane { + __u32 width; + __u32 height; + __u32 pixelformat; + enum v4l2_field field; + enum v4l2_colorspace colorspace; + + struct v4l2_plane_pix_format plane_fmt[VIDEO_MAX_PLANES]; + __u8 num_planes; + __u8 reserved[11]; +} __attribute__ ((packed)); + +/** + * struct v4l2_format - stream data format + * @type: type of the data stream + * @pix: definition of an image format + * @pix_mp: definition of a multiplanar image format + * @win: definition of an overlaid image + * @vbi: raw VBI capture or output parameters + * @sliced: sliced VBI capture or output parameters + * @raw_data: placeholder for future extensions and custom formats + */ +struct v4l2_format { + enum v4l2_buf_type type; + union { + struct v4l2_pix_format pix; /* V4L2_BUF_TYPE_VIDEO_CAPTURE */ + struct v4l2_pix_format_mplane pix_mp; /* V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE */ + struct v4l2_window win; /* V4L2_BUF_TYPE_VIDEO_OVERLAY */ + struct v4l2_vbi_format vbi; /* V4L2_BUF_TYPE_VBI_CAPTURE */ + struct v4l2_sliced_vbi_format sliced; /* V4L2_BUF_TYPE_SLICED_VBI_CAPTURE */ + __u8 raw_data[200]; /* user-defined */ + } fmt; +}; + +/* Stream type-dependent parameters + */ +struct v4l2_streamparm { + enum v4l2_buf_type type; + union { + struct v4l2_captureparm capture; + struct v4l2_outputparm output; + __u8 raw_data[200]; /* user-defined */ + } parm; +}; + +/* + * E V E N T S + */ + +#define V4L2_EVENT_ALL 0 +#define V4L2_EVENT_VSYNC 1 +#define V4L2_EVENT_EOS 2 +#define V4L2_EVENT_CTRL 3 +#define V4L2_EVENT_FRAME_SYNC 4 +#define V4L2_EVENT_PRIVATE_START 0x08000000 + +#define V4L2_EVENT_MSM_VIDC_START (V4L2_EVENT_PRIVATE_START + 0x00001000) +#define V4L2_EVENT_MSM_VIDC_FLUSH_DONE (V4L2_EVENT_MSM_VIDC_START + 1) +#define V4L2_EVENT_MSM_VIDC_PORT_SETTINGS_CHANGED_SUFFICIENT \ + (V4L2_EVENT_MSM_VIDC_START + 2) +#define V4L2_EVENT_MSM_VIDC_PORT_SETTINGS_CHANGED_INSUFFICIENT \ + (V4L2_EVENT_MSM_VIDC_START + 3) +#define V4L2_EVENT_MSM_VIDC_CLOSE_DONE (V4L2_EVENT_MSM_VIDC_START + 4) +#define V4L2_EVENT_MSM_VIDC_SYS_ERROR (V4L2_EVENT_MSM_VIDC_START + 5) +#define V4L2_EVENT_MSM_VIDC_RELEASE_BUFFER_REFERENCE \ + (V4L2_EVENT_MSM_VIDC_START + 6) +#define V4L2_EVENT_MSM_VIDC_RELEASE_UNQUEUED_BUFFER \ + (V4L2_EVENT_MSM_VIDC_START + 7) + +/* Payload for V4L2_EVENT_VSYNC */ +struct v4l2_event_vsync { + /* Can be V4L2_FIELD_ANY, _NONE, _TOP or _BOTTOM */ + __u8 field; +} __attribute__ ((packed)); + +/* Payload for V4L2_EVENT_CTRL */ +#define V4L2_EVENT_CTRL_CH_VALUE (1 << 0) +#define V4L2_EVENT_CTRL_CH_FLAGS (1 << 1) + +struct v4l2_event_ctrl { + __u32 changes; + __u32 type; + union { + __s32 value; + __s64 value64; + }; + __u32 flags; + __s32 minimum; + __s32 maximum; + __s32 step; + __s32 default_value; +}; + +struct v4l2_event_frame_sync { + __u32 frame_sequence; +}; + +struct v4l2_event { + __u32 type; + union { + struct v4l2_event_vsync vsync; + struct v4l2_event_ctrl ctrl; + struct v4l2_event_frame_sync frame_sync; + __u8 data[64]; + } u; + __u32 pending; + __u32 sequence; + struct timespec timestamp; + __u32 id; + __u32 reserved[8]; +}; + +#define V4L2_EVENT_SUB_FL_SEND_INITIAL (1 << 0) +#define V4L2_EVENT_SUB_FL_ALLOW_FEEDBACK (1 << 1) + +struct v4l2_event_subscription { + __u32 type; + __u32 id; + __u32 flags; + __u32 reserved[5]; +}; + +/* + * A D V A N C E D D E B U G G I N G + * + * NOTE: EXPERIMENTAL API, NEVER RELY ON THIS IN APPLICATIONS! + * FOR DEBUGGING, TESTING AND INTERNAL USE ONLY! + */ + +/* VIDIOC_DBG_G_REGISTER and VIDIOC_DBG_S_REGISTER */ + +#define V4L2_CHIP_MATCH_HOST 0 /* Match against chip ID on host (0 for the host) */ +#define V4L2_CHIP_MATCH_I2C_DRIVER 1 /* Match against I2C driver name */ +#define V4L2_CHIP_MATCH_I2C_ADDR 2 /* Match against I2C 7-bit address */ +#define V4L2_CHIP_MATCH_AC97 3 /* Match against anciliary AC97 chip */ + +struct v4l2_dbg_match { + __u32 type; /* Match type */ + union { /* Match this chip, meaning determined by type */ + __u32 addr; + char name[32]; + }; +} __attribute__ ((packed)); + +struct v4l2_dbg_register { + struct v4l2_dbg_match match; + __u32 size; /* register size in bytes */ + __u64 reg; + __u64 val; +} __attribute__ ((packed)); + +/* VIDIOC_DBG_G_CHIP_IDENT */ +struct v4l2_dbg_chip_ident { + struct v4l2_dbg_match match; + __u32 ident; /* chip identifier as specified in <media/v4l2-chip-ident.h> */ + __u32 revision; /* chip revision, chip specific */ +} __attribute__ ((packed)); + +/** + * struct v4l2_create_buffers - VIDIOC_CREATE_BUFS argument + * @index: on return, index of the first created buffer + * @count: entry: number of requested buffers, + * return: number of created buffers + * @memory: buffer memory type + * @format: frame format, for which buffers are requested + * @reserved: future extensions + */ +struct v4l2_create_buffers { + __u32 index; + __u32 count; + enum v4l2_memory memory; + struct v4l2_format format; + __u32 reserved[8]; +}; + +/* + * I O C T L C O D E S F O R V I D E O D E V I C E S + * + */ +#define VIDIOC_QUERYCAP _IOR('V', 0, struct v4l2_capability) +#define VIDIOC_RESERVED _IO('V', 1) +#define VIDIOC_ENUM_FMT _IOWR('V', 2, struct v4l2_fmtdesc) +#define VIDIOC_G_FMT _IOWR('V', 4, struct v4l2_format) +#define VIDIOC_S_FMT _IOWR('V', 5, struct v4l2_format) +#define VIDIOC_REQBUFS _IOWR('V', 8, struct v4l2_requestbuffers) +#define VIDIOC_QUERYBUF _IOWR('V', 9, struct v4l2_buffer) +#define VIDIOC_G_FBUF _IOR('V', 10, struct v4l2_framebuffer) +#define VIDIOC_S_FBUF _IOW('V', 11, struct v4l2_framebuffer) +#define VIDIOC_OVERLAY _IOW('V', 14, int) +#define VIDIOC_QBUF _IOWR('V', 15, struct v4l2_buffer) +#define VIDIOC_DQBUF _IOWR('V', 17, struct v4l2_buffer) +#define VIDIOC_STREAMON _IOW('V', 18, int) +#define VIDIOC_STREAMOFF _IOW('V', 19, int) +#define VIDIOC_G_PARM _IOWR('V', 21, struct v4l2_streamparm) +#define VIDIOC_S_PARM _IOWR('V', 22, struct v4l2_streamparm) +#define VIDIOC_G_STD _IOR('V', 23, v4l2_std_id) +#define VIDIOC_S_STD _IOW('V', 24, v4l2_std_id) +#define VIDIOC_ENUMSTD _IOWR('V', 25, struct v4l2_standard) +#define VIDIOC_ENUMINPUT _IOWR('V', 26, struct v4l2_input) +#define VIDIOC_G_CTRL _IOWR('V', 27, struct v4l2_control) +#define VIDIOC_S_CTRL _IOWR('V', 28, struct v4l2_control) +#define VIDIOC_G_TUNER _IOWR('V', 29, struct v4l2_tuner) +#define VIDIOC_S_TUNER _IOW('V', 30, struct v4l2_tuner) +#define VIDIOC_G_AUDIO _IOR('V', 33, struct v4l2_audio) +#define VIDIOC_S_AUDIO _IOW('V', 34, struct v4l2_audio) +#define VIDIOC_QUERYCTRL _IOWR('V', 36, struct v4l2_queryctrl) +#define VIDIOC_QUERYMENU _IOWR('V', 37, struct v4l2_querymenu) +#define VIDIOC_G_INPUT _IOR('V', 38, int) +#define VIDIOC_S_INPUT _IOWR('V', 39, int) +#define VIDIOC_G_OUTPUT _IOR('V', 46, int) +#define VIDIOC_S_OUTPUT _IOWR('V', 47, int) +#define VIDIOC_ENUMOUTPUT _IOWR('V', 48, struct v4l2_output) +#define VIDIOC_G_AUDOUT _IOR('V', 49, struct v4l2_audioout) +#define VIDIOC_S_AUDOUT _IOW('V', 50, struct v4l2_audioout) +#define VIDIOC_G_MODULATOR _IOWR('V', 54, struct v4l2_modulator) +#define VIDIOC_S_MODULATOR _IOW('V', 55, struct v4l2_modulator) +#define VIDIOC_G_FREQUENCY _IOWR('V', 56, struct v4l2_frequency) +#define VIDIOC_S_FREQUENCY _IOW('V', 57, struct v4l2_frequency) +#define VIDIOC_CROPCAP _IOWR('V', 58, struct v4l2_cropcap) +#define VIDIOC_G_CROP _IOWR('V', 59, struct v4l2_crop) +#define VIDIOC_S_CROP _IOW('V', 60, struct v4l2_crop) +#define VIDIOC_G_JPEGCOMP _IOR('V', 61, struct v4l2_jpegcompression) +#define VIDIOC_S_JPEGCOMP _IOW('V', 62, struct v4l2_jpegcompression) +#define VIDIOC_QUERYSTD _IOR('V', 63, v4l2_std_id) +#define VIDIOC_TRY_FMT _IOWR('V', 64, struct v4l2_format) +#define VIDIOC_ENUMAUDIO _IOWR('V', 65, struct v4l2_audio) +#define VIDIOC_ENUMAUDOUT _IOWR('V', 66, struct v4l2_audioout) +#define VIDIOC_G_PRIORITY _IOR('V', 67, enum v4l2_priority) +#define VIDIOC_S_PRIORITY _IOW('V', 68, enum v4l2_priority) +#define VIDIOC_G_SLICED_VBI_CAP _IOWR('V', 69, struct v4l2_sliced_vbi_cap) +#define VIDIOC_LOG_STATUS _IO('V', 70) +#define VIDIOC_G_EXT_CTRLS _IOWR('V', 71, struct v4l2_ext_controls) +#define VIDIOC_S_EXT_CTRLS _IOWR('V', 72, struct v4l2_ext_controls) +#define VIDIOC_TRY_EXT_CTRLS _IOWR('V', 73, struct v4l2_ext_controls) +#if 1 +#define VIDIOC_ENUM_FRAMESIZES _IOWR('V', 74, struct v4l2_frmsizeenum) +#define VIDIOC_ENUM_FRAMEINTERVALS _IOWR('V', 75, struct v4l2_frmivalenum) +#define VIDIOC_G_ENC_INDEX _IOR('V', 76, struct v4l2_enc_idx) +#define VIDIOC_ENCODER_CMD _IOWR('V', 77, struct v4l2_encoder_cmd) +#define VIDIOC_TRY_ENCODER_CMD _IOWR('V', 78, struct v4l2_encoder_cmd) +#endif + +#if 1 +/* Experimental, meant for debugging, testing and internal use. + Only implemented if CONFIG_VIDEO_ADV_DEBUG is defined. + You must be root to use these ioctls. Never use these in applications! */ +#define VIDIOC_DBG_S_REGISTER _IOW('V', 79, struct v4l2_dbg_register) +#define VIDIOC_DBG_G_REGISTER _IOWR('V', 80, struct v4l2_dbg_register) + +/* Experimental, meant for debugging, testing and internal use. + Never use this ioctl in applications! */ +#define VIDIOC_DBG_G_CHIP_IDENT _IOWR('V', 81, struct v4l2_dbg_chip_ident) +#endif + +#define VIDIOC_S_HW_FREQ_SEEK _IOW('V', 82, struct v4l2_hw_freq_seek) +#define VIDIOC_ENUM_DV_PRESETS _IOWR('V', 83, struct v4l2_dv_enum_preset) +#define VIDIOC_S_DV_PRESET _IOWR('V', 84, struct v4l2_dv_preset) +#define VIDIOC_G_DV_PRESET _IOWR('V', 85, struct v4l2_dv_preset) +#define VIDIOC_QUERY_DV_PRESET _IOR('V', 86, struct v4l2_dv_preset) +#define VIDIOC_S_DV_TIMINGS _IOWR('V', 87, struct v4l2_dv_timings) +#define VIDIOC_G_DV_TIMINGS _IOWR('V', 88, struct v4l2_dv_timings) +#define VIDIOC_DQEVENT _IOR('V', 89, struct v4l2_event) +#define VIDIOC_SUBSCRIBE_EVENT _IOW('V', 90, struct v4l2_event_subscription) +#define VIDIOC_UNSUBSCRIBE_EVENT _IOW('V', 91, struct v4l2_event_subscription) + +/* Experimental, the below two ioctls may change over the next couple of kernel + versions */ +#define VIDIOC_CREATE_BUFS _IOWR('V', 92, struct v4l2_create_buffers) +#define VIDIOC_PREPARE_BUF _IOWR('V', 93, struct v4l2_buffer) + +/* Experimental selection API */ +#define VIDIOC_G_SELECTION _IOWR('V', 94, struct v4l2_selection) +#define VIDIOC_S_SELECTION _IOWR('V', 95, struct v4l2_selection) + +/* Experimental, these two ioctls may change over the next couple of kernel + versions. */ +#define VIDIOC_DECODER_CMD _IOWR('V', 96, struct v4l2_decoder_cmd) +#define VIDIOC_TRY_DECODER_CMD _IOWR('V', 97, struct v4l2_decoder_cmd) + +/* Reminder: when adding new ioctls please add support for them to + drivers/media/video/v4l2-compat-ioctl32.c as well! */ + +#define BASE_VIDIOC_PRIVATE 192 /* 192-255 are private */ + +#endif /* __LINUX_VIDEODEV2_H */ |