diff options
| author | Patrick Tjin <pattjin@google.com> | 2015-03-12 10:00:51 -0700 |
|---|---|---|
| committer | Patrick Tjin <pattjin@google.com> | 2015-03-12 10:00:51 -0700 |
| commit | 4d667bae0175a66dffc4d241a449e706bdee0a85 (patch) | |
| tree | 879f28c3629c9da10f2b23c10701d4a914cca744 | |
| parent | f5dc696274c01f254abddeb22c92b15a46401ad3 (diff) | |
| download | msm8994-4d667bae0175a66dffc4d241a449e706bdee0a85.tar.gz | |
msm8994: update kernel headers
LA.BF64.1.2.1_rb1.10
Change-Id: Ifaeab686491175eb57ba0a2ae94c49c4397e2997
Signed-off-by: Patrick Tjin <pattjin@google.com>
98 files changed, 33764 insertions, 0 deletions
diff --git a/kernel-headers/linux/esoc_ctrl.h b/kernel-headers/linux/esoc_ctrl.h new file mode 100644 index 0000000..239bdfa --- /dev/null +++ b/kernel-headers/linux/esoc_ctrl.h @@ -0,0 +1,82 @@ +/**************************************************************************** + **************************************************************************** + *** + *** This header was automatically generated from a Linux kernel header + *** of the same name, to make information necessary for userspace to + *** call into the kernel available to libc. It contains only constants, + *** structures, and macros generated from the original header, and thus, + *** contains no copyrightable information. + *** + *** To edit the content of this header, modify the corresponding + *** source file (e.g. under external/kernel-headers/original/) then + *** run bionic/libc/kernel/tools/update_all.py + *** + *** Any manual change here will be lost the next time this script will + *** be run. You've been warned! + *** + **************************************************************************** + ****************************************************************************/ +#ifndef _UAPI_ESOC_CTRL_H_ +#define _UAPI_ESOC_CTRL_H_ +#define ESOC_CODE 0xCC +#define ESOC_CMD_EXE _IOW(ESOC_CODE, 1, u32) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define ESOC_WAIT_FOR_REQ _IOR(ESOC_CODE, 2, u32) +#define ESOC_NOTIFY _IOW(ESOC_CODE, 3, u32) +#define ESOC_GET_STATUS _IOR(ESOC_CODE, 4, u32) +#define ESOC_WAIT_FOR_CRASH _IOR(ESOC_CODE, 6, u32) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define ESOC_REG_REQ_ENG _IO(ESOC_CODE, 7) +#define ESOC_REG_CMD_ENG _IO(ESOC_CODE, 8) +#define HSIC "HSIC" +#define HSICPCIe "HSIC+PCIe" +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define PCIe "PCIe" +enum esoc_evt { + ESOC_RUN_STATE = 0x1, + ESOC_UNEXPECTED_RESET, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + ESOC_ERR_FATAL, + ESOC_IN_DEBUG, + ESOC_REQ_ENG_ON, + ESOC_REQ_ENG_OFF, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + ESOC_CMD_ENG_ON, + ESOC_CMD_ENG_OFF, + ESOC_INVALID_STATE, +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +enum esoc_cmd { + ESOC_PWR_ON = 1, + ESOC_PWR_OFF, + ESOC_FORCE_PWR_OFF, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + ESOC_RESET, + ESOC_PREPARE_DEBUG, + ESOC_EXE_DEBUG, + ESOC_EXIT_DEBUG, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +enum esoc_notify { + ESOC_IMG_XFER_DONE = 1, + ESOC_BOOT_DONE, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + ESOC_BOOT_FAIL, + ESOC_IMG_XFER_RETRY, + ESOC_IMG_XFER_FAIL, + ESOC_UPGRADE_AVAILABLE, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + ESOC_DEBUG_DONE, + ESOC_DEBUG_FAIL, + ESOC_PRIMARY_CRASH, + ESOC_PRIMARY_REBOOT, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +enum esoc_req { + ESOC_REQ_IMG = 1, + ESOC_REQ_DEBUG, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + ESOC_REQ_SHUTDOWN, +}; +#endif + diff --git a/kernel-headers/linux/mfd/msm-adie-codec.h b/kernel-headers/linux/mfd/msm-adie-codec.h new file mode 100644 index 0000000..e4bf22b --- /dev/null +++ b/kernel-headers/linux/mfd/msm-adie-codec.h @@ -0,0 +1,110 @@ +/**************************************************************************** + **************************************************************************** + *** + *** This header was automatically generated from a Linux kernel header + *** of the same name, to make information necessary for userspace to + *** call into the kernel available to libc. It contains only constants, + *** structures, and macros generated from the original header, and thus, + *** contains no copyrightable information. + *** + *** To edit the content of this header, modify the corresponding + *** source file (e.g. under external/kernel-headers/original/) then + *** run bionic/libc/kernel/tools/update_all.py + *** + *** Any manual change here will be lost the next time this script will + *** be run. You've been warned! + *** + **************************************************************************** + ****************************************************************************/ +#ifndef __UAPI_MFD_MSM_ADIE_CODEC_H +#define __UAPI_MFD_MSM_ADIE_CODEC_H +#include <linux/types.h> +#define ADIE_CODEC_ACTION_ENTRY 0x1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define ADIE_CODEC_ACTION_DELAY_WAIT 0x2 +#define ADIE_CODEC_ACTION_STAGE_REACHED 0x3 +#define ADIE_CODEC_PATH_OFF 0x0050 +#define ADIE_CODEC_DIGITAL_READY 0x0100 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define ADIE_CODEC_DIGITAL_ANALOG_READY 0x1000 +#define ADIE_CODEC_ANALOG_OFF 0x0750 +#define ADIE_CODEC_DIGITAL_OFF 0x0600 +#define ADIE_CODEC_FLASH_IMAGE 0x0001 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define ADIE_CODEC_RX 0 +#define ADIE_CODEC_TX 1 +#define ADIE_CODEC_LB 3 +#define ADIE_CODEC_MAX 4 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define ADIE_CODEC_PACK_ENTRY(reg, mask, val) ((val)|(mask << 8)|(reg << 16)) +#define ADIE_CODEC_UNPACK_ENTRY(packed, reg, mask, val) do { ((reg) = ((packed >> 16) & (0xff))); ((mask) = ((packed >> 8) & (0xff))); ((val) = ((packed) & (0xff))); } while (0); +struct adie_codec_action_unit { + u32 type; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + u32 action; +}; +struct adie_codec_hwsetting_entry{ + struct adie_codec_action_unit *actions; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + u32 action_sz; + u32 freq_plan; + u32 osr; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct adie_codec_dev_profile { + u32 path_type; + u32 setting_sz; + struct adie_codec_hwsetting_entry *settings; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +struct adie_codec_register { + u8 reg; + u8 mask; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + u8 val; +}; +struct adie_codec_register_image { + struct adie_codec_register *regs; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + u32 img_sz; +}; +struct adie_codec_path; +struct adie_codec_anc_data { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + u32 size; + u32 writes[]; +}; +struct adie_codec_operations { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + int codec_id; + int (*codec_open) (struct adie_codec_dev_profile *profile, + struct adie_codec_path **path_pptr); + int (*codec_close) (struct adie_codec_path *path_ptr); +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + int (*codec_setpath) (struct adie_codec_path *path_ptr, + u32 freq_plan, u32 osr); + int (*codec_proceed_stage) (struct adie_codec_path *path_ptr, + u32 state); +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + u32 (*codec_freq_supported) (struct adie_codec_dev_profile *profile, + u32 requested_freq); + int (*codec_enable_sidetone) (struct adie_codec_path *rx_path_ptr, + u32 enable); +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + int (*codec_enable_anc) (struct adie_codec_path *rx_path_ptr, + u32 enable, struct adie_codec_anc_data *calibration_writes); + int (*codec_set_device_digital_volume) ( + struct adie_codec_path *path_ptr, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + u32 num_channels, + u32 vol_percentage); + int (*codec_set_device_analog_volume) (struct adie_codec_path *path_ptr, + u32 num_channels, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + u32 volume); + int (*codec_set_master_mode) (struct adie_codec_path *path_ptr, + u8 master); +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#endif + diff --git a/kernel-headers/linux/mfd/wcd9xxx/wcd9320_registers.h b/kernel-headers/linux/mfd/wcd9xxx/wcd9320_registers.h new file mode 100644 index 0000000..968be40 --- /dev/null +++ b/kernel-headers/linux/mfd/wcd9xxx/wcd9320_registers.h @@ -0,0 +1,1746 @@ +/**************************************************************************** + **************************************************************************** + *** + *** This header was automatically generated from a Linux kernel header + *** of the same name, to make information necessary for userspace to + *** call into the kernel available to libc. It contains only constants, + *** structures, and macros generated from the original header, and thus, + *** contains no copyrightable information. + *** + *** To edit the content of this header, modify the corresponding + *** source file (e.g. under external/kernel-headers/original/) then + *** run bionic/libc/kernel/tools/update_all.py + *** + *** Any manual change here will be lost the next time this script will + *** be run. You've been warned! + *** + **************************************************************************** + ****************************************************************************/ +#ifndef WCD9320_REGISTERS_H +#define WCD9320_REGISTERS_H +#include <linux/mfd/wcd9xxx/wcd9xxx_registers.h> +#define TAIKO_A_CHIP_CTL WCD9XXX_A_CHIP_CTL +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CHIP_CTL__POR WCD9XXX_A_CHIP_CTL__POR +#define TAIKO_A_CHIP_STATUS WCD9XXX_A_CHIP_STATUS +#define TAIKO_A_CHIP_STATUS__POR WCD9XXX_A_CHIP_STATUS__POR +#define TAIKO_A_CHIP_ID_BYTE_0 WCD9XXX_A_CHIP_ID_BYTE_0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CHIP_ID_BYTE_0__POR WCD9XXX_A_CHIP_ID_BYTE_0__POR +#define TAIKO_A_CHIP_ID_BYTE_1 WCD9XXX_A_CHIP_ID_BYTE_1 +#define TAIKO_A_CHIP_ID_BYTE_1__POR WCD9XXX_A_CHIP_ID_BYTE_1__POR +#define TAIKO_A_CHIP_ID_BYTE_2 WCD9XXX_A_CHIP_ID_BYTE_2 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CHIP_ID_BYTE_2__POR WCD9XXX_A_CHIP_ID_BYTE_2__POR +#define TAIKO_A_CHIP_ID_BYTE_3 WCD9XXX_A_CHIP_ID_BYTE_3 +#define TAIKO_A_CHIP_ID_BYTE_3__POR WCD9XXX_A_CHIP_ID_BYTE_3__POR +#define TAIKO_A_CHIP_VERSION WCD9XXX_A_CHIP_VERSION +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CHIP_VERSION__POR WCD9XXX_A_CHIP_VERSION__POR +#define TAIKO_A_SB_VERSION WCD9XXX_A_SB_VERSION +#define TAIKO_A_SB_VERSION__POR WCD9XXX_A_SB_VERSION__POR +#define TAIKO_A_SLAVE_ID_1 WCD9XXX_A_SLAVE_ID_1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_SLAVE_ID_1__POR WCD9XXX_A_SLAVE_ID_1__POR +#define TAIKO_A_SLAVE_ID_2 WCD9XXX_A_SLAVE_ID_2 +#define TAIKO_A_SLAVE_ID_2__POR WCD9XXX_A_SLAVE_ID_2__POR +#define TAIKO_A_SLAVE_ID_3 WCD9XXX_A_SLAVE_ID_3 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_SLAVE_ID_3__POR WCD9XXX_A_SLAVE_ID_3__POR +#define TAIKO_A_PIN_CTL_OE0 (0x010) +#define TAIKO_A_PIN_CTL_OE0__POR (0x00) +#define TAIKO_A_PIN_CTL_OE1 (0x011) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_PIN_CTL_OE1__POR (0x00) +#define TAIKO_A_PIN_CTL_DATA0 (0x012) +#define TAIKO_A_PIN_CTL_DATA0__POR (0x00) +#define TAIKO_A_PIN_CTL_DATA1 (0x013) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_PIN_CTL_DATA1__POR (0x00) +#define TAIKO_A_HDRIVE_GENERIC (0x018) +#define TAIKO_A_HDRIVE_GENERIC__POR (0x00) +#define TAIKO_A_HDRIVE_OVERRIDE (0x019) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_HDRIVE_OVERRIDE__POR (0x08) +#define TAIKO_A_ANA_CSR_WAIT_STATE (0x020) +#define TAIKO_A_ANA_CSR_WAIT_STATE__POR (0x44) +#define TAIKO_A_PROCESS_MONITOR_CTL0 (0x040) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_PROCESS_MONITOR_CTL0__POR (0x80) +#define TAIKO_A_PROCESS_MONITOR_CTL1 (0x041) +#define TAIKO_A_PROCESS_MONITOR_CTL1__POR (0x00) +#define TAIKO_A_PROCESS_MONITOR_CTL2 (0x042) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_PROCESS_MONITOR_CTL2__POR (0x00) +#define TAIKO_A_PROCESS_MONITOR_CTL3 (0x043) +#define TAIKO_A_PROCESS_MONITOR_CTL3__POR (0x01) +#define TAIKO_A_QFUSE_CTL (0x048) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_QFUSE_CTL__POR (0x00) +#define TAIKO_A_QFUSE_STATUS (0x049) +#define TAIKO_A_QFUSE_STATUS__POR (0x00) +#define TAIKO_A_QFUSE_DATA_OUT0 (0x04A) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_QFUSE_DATA_OUT0__POR (0x00) +#define TAIKO_A_QFUSE_DATA_OUT1 (0x04B) +#define TAIKO_A_QFUSE_DATA_OUT1__POR (0x00) +#define TAIKO_A_QFUSE_DATA_OUT2 (0x04C) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_QFUSE_DATA_OUT2__POR (0x00) +#define TAIKO_A_QFUSE_DATA_OUT3 (0x04D) +#define TAIKO_A_QFUSE_DATA_OUT3__POR (0x00) +#define TAIKO_A_QFUSE_DATA_OUT4 (0x04E) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_QFUSE_DATA_OUT4__POR (0x00) +#define TAIKO_A_QFUSE_DATA_OUT5 (0x04F) +#define TAIKO_A_QFUSE_DATA_OUT5__POR (0x00) +#define TAIKO_A_QFUSE_DATA_OUT6 (0x050) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_QFUSE_DATA_OUT6__POR (0x00) +#define TAIKO_A_QFUSE_DATA_OUT7 (0x051) +#define TAIKO_A_QFUSE_DATA_OUT7__POR (0x00) +#define TAIKO_A_CDC_CTL WCD9XXX_A_CDC_CTL +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_CTL__POR WCD9XXX_A_CDC_CTL__POR +#define TAIKO_A_LEAKAGE_CTL WCD9XXX_A_LEAKAGE_CTL +#define TAIKO_A_LEAKAGE_CTL__POR WCD9XXX_A_LEAKAGE_CTL__POR +#define TAIKO_A_INTR_MODE (0x090) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_INTR_MODE__POR (0x00) +#define TAIKO_A_INTR_MASK0 (0x094) +#define TAIKO_A_INTR_MASK0__POR (0xFF) +#define TAIKO_A_INTR_MASK1 (0x095) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_INTR_MASK1__POR (0xFF) +#define TAIKO_A_INTR_MASK2 (0x096) +#define TAIKO_A_INTR_MASK2__POR (0x3F) +#define TAIKO_A_INTR_MASK3 (0x097) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_INTR_MASK3__POR (0x3F) +#define TAIKO_A_INTR_STATUS0 (0x098) +#define TAIKO_A_INTR_STATUS0__POR (0x00) +#define TAIKO_A_INTR_STATUS1 (0x099) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_INTR_STATUS1__POR (0x00) +#define TAIKO_A_INTR_STATUS2 (0x09A) +#define TAIKO_A_INTR_STATUS2__POR (0x00) +#define TAIKO_A_INTR_STATUS3 (0x09B) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_INTR_STATUS3__POR (0x00) +#define TAIKO_A_INTR_CLEAR0 (0x09C) +#define TAIKO_A_INTR_CLEAR0__POR (0x00) +#define TAIKO_A_INTR_CLEAR1 (0x09D) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_INTR_CLEAR1__POR (0x00) +#define TAIKO_A_INTR_CLEAR2 (0x09E) +#define TAIKO_A_INTR_CLEAR2__POR (0x00) +#define TAIKO_A_INTR_CLEAR3 (0x09F) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_INTR_CLEAR3__POR (0x00) +#define TAIKO_A_INTR_LEVEL0 (0x0A0) +#define TAIKO_A_INTR_LEVEL0__POR (0x01) +#define TAIKO_A_INTR_LEVEL1 (0x0A1) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_INTR_LEVEL1__POR (0x00) +#define TAIKO_A_INTR_LEVEL2 (0x0A2) +#define TAIKO_A_INTR_LEVEL2__POR (0x00) +#define TAIKO_A_INTR_LEVEL3 (0x0A3) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_INTR_LEVEL3__POR (0x00) +#define TAIKO_A_INTR_TEST0 (0x0A4) +#define TAIKO_A_INTR_TEST0__POR (0x00) +#define TAIKO_A_INTR_TEST1 (0x0A5) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_INTR_TEST1__POR (0x00) +#define TAIKO_A_INTR_TEST2 (0x0A6) +#define TAIKO_A_INTR_TEST2__POR (0x00) +#define TAIKO_A_INTR_TEST3 (0x0A7) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_INTR_TEST3__POR (0x00) +#define TAIKO_A_INTR_SET0 (0x0A8) +#define TAIKO_A_INTR_SET0__POR (0x00) +#define TAIKO_A_INTR_SET1 (0x0A9) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_INTR_SET1__POR (0x00) +#define TAIKO_A_INTR_SET2 (0x0AA) +#define TAIKO_A_INTR_SET2__POR (0x00) +#define TAIKO_A_INTR_SET3 (0x0AB) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_INTR_SET3__POR (0x00) +#define TAIKO_A_INTR_DESTN0 (0x0AC) +#define TAIKO_A_INTR_DESTN0__POR (0x00) +#define TAIKO_A_INTR_DESTN1 (0x0AD) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_INTR_DESTN1__POR (0x00) +#define TAIKO_A_INTR_DESTN2 (0x0AE) +#define TAIKO_A_INTR_DESTN2__POR (0x00) +#define TAIKO_A_INTR_DESTN3 (0x0AF) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_INTR_DESTN3__POR (0x00) +#define TAIKO_A_CDC_TX_I2S_SCK_MODE (0x0C0) +#define TAIKO_A_CDC_TX_I2S_SCK_MODE__POR (0x00) +#define TAIKO_A_CDC_TX_I2S_WS_MODE (0x0C1) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_TX_I2S_WS_MODE__POR (0x00) +#define TAIKO_A_CDC_DMIC_DATA0_MODE (0x0C4) +#define TAIKO_A_CDC_DMIC_DATA0_MODE__POR (0x00) +#define TAIKO_A_CDC_DMIC_CLK0_MODE (0x0C5) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_DMIC_CLK0_MODE__POR (0x00) +#define TAIKO_A_CDC_DMIC_DATA1_MODE (0x0C6) +#define TAIKO_A_CDC_DMIC_DATA1_MODE__POR (0x00) +#define TAIKO_A_CDC_DMIC_CLK1_MODE (0x0C7) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_DMIC_CLK1_MODE__POR (0x00) +#define TAIKO_A_CDC_RX_I2S_SCK_MODE (0x0C8) +#define TAIKO_A_CDC_RX_I2S_SCK_MODE__POR (0x00) +#define TAIKO_A_CDC_RX_I2S_WS_MODE (0x0C9) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_RX_I2S_WS_MODE__POR (0x00) +#define TAIKO_A_CDC_DMIC_DATA2_MODE (0x0CA) +#define TAIKO_A_CDC_DMIC_DATA2_MODE__POR (0x00) +#define TAIKO_A_CDC_DMIC_CLK2_MODE (0x0CB) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_DMIC_CLK2_MODE__POR (0x00) +#define TAIKO_A_CDC_INTR1_MODE (0x0CC) +#define TAIKO_A_CDC_INTR1_MODE__POR (0x00) +#define TAIKO_A_CDC_SB_NRZ_SEL_MODE (0x0CD) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_SB_NRZ_SEL_MODE__POR (0x00) +#define TAIKO_A_CDC_INTR2_MODE (0x0CE) +#define TAIKO_A_CDC_INTR2_MODE__POR (0x00) +#define TAIKO_A_CDC_RF_PA_ON_MODE (0x0CF) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_RF_PA_ON_MODE__POR (0x00) +#define TAIKO_A_BIAS_REF_CTL (0x100) +#define TAIKO_A_BIAS_REF_CTL__POR (0x1C) +#define TAIKO_A_BIAS_CENTRAL_BG_CTL (0x101) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_BIAS_CENTRAL_BG_CTL__POR (0x50) +#define TAIKO_A_BIAS_PRECHRG_CTL (0x102) +#define TAIKO_A_BIAS_PRECHRG_CTL__POR (0x07) +#define TAIKO_A_BIAS_CURR_CTL_1 (0x103) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_BIAS_CURR_CTL_1__POR (0x52) +#define TAIKO_A_BIAS_CURR_CTL_2 (0x104) +#define TAIKO_A_BIAS_CURR_CTL_2__POR (0x00) +#define TAIKO_A_BIAS_OSC_BG_CTL (0x105) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_BIAS_OSC_BG_CTL__POR (0x16) +#define TAIKO_A_CLK_BUFF_EN1 (0x108) +#define TAIKO_A_CLK_BUFF_EN1__POR (0x04) +#define TAIKO_A_CLK_BUFF_EN2 (0x109) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CLK_BUFF_EN2__POR (0x02) +#define TAIKO_A_LDO_H_MODE_1 (0x110) +#define TAIKO_A_LDO_H_MODE_1__POR (0x65) +#define TAIKO_A_LDO_H_MODE_2 (0x111) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_LDO_H_MODE_2__POR (0xA8) +#define TAIKO_A_LDO_H_LOOP_CTL (0x112) +#define TAIKO_A_LDO_H_LOOP_CTL__POR (0x6B) +#define TAIKO_A_LDO_H_COMP_1 (0x113) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_LDO_H_COMP_1__POR (0x84) +#define TAIKO_A_LDO_H_COMP_2 (0x114) +#define TAIKO_A_LDO_H_COMP_2__POR (0xE0) +#define TAIKO_A_LDO_H_BIAS_1 (0x115) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_LDO_H_BIAS_1__POR (0x6D) +#define TAIKO_A_LDO_H_BIAS_2 (0x116) +#define TAIKO_A_LDO_H_BIAS_2__POR (0xA5) +#define TAIKO_A_LDO_H_BIAS_3 (0x117) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_LDO_H_BIAS_3__POR (0x60) +#define TAIKO_A_VBAT_CLK (0x118) +#define TAIKO_A_VBAT_CLK__POR (0x03) +#define TAIKO_A_VBAT_LOOP (0x119) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_VBAT_LOOP__POR (0x02) +#define TAIKO_A_VBAT_REF (0x11A) +#define TAIKO_A_VBAT_REF__POR (0x20) +#define TAIKO_A_VBAT_ADC_TEST (0x11B) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_VBAT_ADC_TEST__POR (0x00) +#define TAIKO_A_VBAT_FE (0x11C) +#define TAIKO_A_VBAT_FE__POR (0x48) +#define TAIKO_A_VBAT_BIAS_1 (0x11D) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_VBAT_BIAS_1__POR (0x03) +#define TAIKO_A_VBAT_BIAS_2 (0x11E) +#define TAIKO_A_VBAT_BIAS_2__POR (0x00) +#define TAIKO_A_VBAT_ADC_DATA_MSB (0x11F) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_VBAT_ADC_DATA_MSB__POR (0x00) +#define TAIKO_A_VBAT_ADC_DATA_LSB (0x120) +#define TAIKO_A_VBAT_ADC_DATA_LSB__POR (0x00) +#define TAIKO_A_MICB_CFILT_1_CTL (0x128) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_MICB_CFILT_1_CTL__POR (0x40) +#define TAIKO_A_MICB_CFILT_1_VAL (0x129) +#define TAIKO_A_MICB_CFILT_1_VAL__POR (0x80) +#define TAIKO_A_MICB_CFILT_1_PRECHRG (0x12A) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_MICB_CFILT_1_PRECHRG__POR (0x38) +#define TAIKO_A_MICB_1_CTL (0x12B) +#define TAIKO_A_MICB_1_CTL__POR (0x16) +#define TAIKO_A_MICB_1_INT_RBIAS (0x12C) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_MICB_1_INT_RBIAS__POR (0x24) +#define TAIKO_A_MICB_1_MBHC (0x12D) +#define TAIKO_A_MICB_1_MBHC__POR (0x01) +#define TAIKO_A_MICB_CFILT_2_CTL (0x12E) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_MICB_CFILT_2_CTL__POR (0x40) +#define TAIKO_A_MICB_CFILT_2_VAL (0x12F) +#define TAIKO_A_MICB_CFILT_2_VAL__POR (0x80) +#define TAIKO_A_MICB_CFILT_2_PRECHRG (0x130) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_MICB_CFILT_2_PRECHRG__POR (0x38) +#define TAIKO_A_MICB_2_CTL (0x131) +#define TAIKO_A_MICB_2_CTL__POR (0x16) +#define TAIKO_A_MICB_2_INT_RBIAS (0x132) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_MICB_2_INT_RBIAS__POR (0x24) +#define TAIKO_A_MICB_2_MBHC (0x133) +#define TAIKO_A_MICB_2_MBHC__POR (0x02) +#define TAIKO_A_MICB_CFILT_3_CTL (0x134) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_MICB_CFILT_3_CTL__POR (0x40) +#define TAIKO_A_MICB_CFILT_3_VAL (0x135) +#define TAIKO_A_MICB_CFILT_3_VAL__POR (0x80) +#define TAIKO_A_MICB_CFILT_3_PRECHRG (0x136) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_MICB_CFILT_3_PRECHRG__POR (0x38) +#define TAIKO_A_MICB_3_CTL (0x137) +#define TAIKO_A_MICB_3_CTL__POR (0x16) +#define TAIKO_A_MICB_3_INT_RBIAS (0x138) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_MICB_3_INT_RBIAS__POR (0x24) +#define TAIKO_A_MICB_3_MBHC (0x139) +#define TAIKO_A_MICB_3_MBHC__POR (0x00) +#define TAIKO_A_MICB_4_CTL (0x13D) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_MICB_4_CTL__POR (0x16) +#define TAIKO_A_MICB_4_INT_RBIAS (0x13E) +#define TAIKO_A_MICB_4_INT_RBIAS__POR (0x24) +#define TAIKO_A_MICB_4_MBHC (0x13F) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_MICB_4_MBHC__POR (0x01) +#define TAIKO_A_MBHC_INSERT_DETECT (0x14A) +#define TAIKO_A_MBHC_INSERT_DETECT__POR (0x00) +#define TAIKO_A_MBHC_INSERT_DET_STATUS (0x14B) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_MBHC_INSERT_DET_STATUS__POR (0x00) +#define TAIKO_A_TX_COM_BIAS (0x14C) +#define TAIKO_A_TX_COM_BIAS__POR (0xF0) +#define TAIKO_A_MBHC_SCALING_MUX_1 (0x14E) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_MBHC_SCALING_MUX_1__POR (0x00) +#define TAIKO_A_MBHC_SCALING_MUX_2 (0x14F) +#define TAIKO_A_MBHC_SCALING_MUX_2__POR (0x80) +#define TAIKO_A_MAD_ANA_CTRL (0x150) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_MAD_ANA_CTRL__POR (0xF1) +#define TAIKO_A_TX_SUP_SWITCH_CTRL_1 (0x151) +#define TAIKO_A_TX_SUP_SWITCH_CTRL_1__POR (0x00) +#define TAIKO_A_TX_SUP_SWITCH_CTRL_2 (0x152) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_TX_SUP_SWITCH_CTRL_2__POR (0x80) +#define TAIKO_A_TX_1_2_EN (0x153) +#define TAIKO_A_TX_1_2_EN__POR (0x00) +#define TAIKO_A_TX_1_2_TEST_EN (0x154) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_TX_1_2_TEST_EN__POR (0xCC) +#define TAIKO_A_TX_1_2_ADC_CH1 (0x155) +#define TAIKO_A_TX_1_2_ADC_CH1__POR (0x44) +#define TAIKO_A_TX_1_2_ADC_CH2 (0x156) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_TX_1_2_ADC_CH2__POR (0x44) +#define TAIKO_A_TX_1_2_ATEST_REFCTRL (0x157) +#define TAIKO_A_TX_1_2_ATEST_REFCTRL__POR (0x00) +#define TAIKO_A_TX_1_2_TEST_CTL (0x158) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_TX_1_2_TEST_CTL__POR (0x38) +#define TAIKO_A_TX_1_2_TEST_BLOCK_EN (0x159) +#define TAIKO_A_TX_1_2_TEST_BLOCK_EN__POR (0xFC) +#define TAIKO_A_TX_1_2_TXFE_CLKDIV (0x15A) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_TX_1_2_TXFE_CLKDIV__POR (0x55) +#define TAIKO_A_TX_1_2_SAR_ERR_CH1 (0x15B) +#define TAIKO_A_TX_1_2_SAR_ERR_CH1__POR (0x00) +#define TAIKO_A_TX_1_2_SAR_ERR_CH2 (0x15C) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_TX_1_2_SAR_ERR_CH2__POR (0x00) +#define TAIKO_A_TX_3_4_EN (0x15D) +#define TAIKO_A_TX_3_4_EN__POR (0x00) +#define TAIKO_A_TX_3_4_TEST_EN (0x15E) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_TX_3_4_TEST_EN__POR (0xCC) +#define TAIKO_A_TX_3_4_ADC_CH3 (0x15F) +#define TAIKO_A_TX_3_4_ADC_CH3__POR (0x44) +#define TAIKO_A_TX_3_4_ADC_CH4 (0x160) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_TX_3_4_ADC_CH4__POR (0x44) +#define TAIKO_A_TX_3_4_ATEST_REFCTRL (0x161) +#define TAIKO_A_TX_3_4_ATEST_REFCTRL__POR (0x00) +#define TAIKO_A_TX_3_4_TEST_CTL (0x162) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_TX_3_4_TEST_CTL__POR (0x38) +#define TAIKO_A_TX_3_4_TEST_BLOCK_EN (0x163) +#define TAIKO_A_TX_3_4_TEST_BLOCK_EN__POR (0xFC) +#define TAIKO_A_TX_3_4_TXFE_CKDIV (0x164) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_TX_3_4_TXFE_CKDIV__POR (0x55) +#define TAIKO_A_TX_3_4_SAR_ERR_CH3 (0x165) +#define TAIKO_A_TX_3_4_SAR_ERR_CH3__POR (0x00) +#define TAIKO_A_TX_3_4_SAR_ERR_CH4 (0x166) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_TX_3_4_SAR_ERR_CH4__POR (0x00) +#define TAIKO_A_TX_5_6_EN (0x167) +#define TAIKO_A_TX_5_6_EN__POR (0x11) +#define TAIKO_A_TX_5_6_TEST_EN (0x168) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_TX_5_6_TEST_EN__POR (0xCC) +#define TAIKO_A_TX_5_6_ADC_CH5 (0x169) +#define TAIKO_A_TX_5_6_ADC_CH5__POR (0x44) +#define TAIKO_A_TX_5_6_ADC_CH6 (0x16A) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_TX_5_6_ADC_CH6__POR (0x44) +#define TAIKO_A_TX_5_6_ATEST_REFCTRL (0x16B) +#define TAIKO_A_TX_5_6_ATEST_REFCTRL__POR (0x00) +#define TAIKO_A_TX_5_6_TEST_CTL (0x16C) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_TX_5_6_TEST_CTL__POR (0x38) +#define TAIKO_A_TX_5_6_TEST_BLOCK_EN (0x16D) +#define TAIKO_A_TX_5_6_TEST_BLOCK_EN__POR (0xFC) +#define TAIKO_A_TX_5_6_TXFE_CKDIV (0x16E) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_TX_5_6_TXFE_CKDIV__POR (0x55) +#define TAIKO_A_TX_5_6_SAR_ERR_CH5 (0x16F) +#define TAIKO_A_TX_5_6_SAR_ERR_CH5__POR (0x00) +#define TAIKO_A_TX_5_6_SAR_ERR_CH6 (0x170) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_TX_5_6_SAR_ERR_CH6__POR (0x00) +#define TAIKO_A_TX_7_MBHC_EN (0x171) +#define TAIKO_A_TX_7_MBHC_EN__POR (0x0C) +#define TAIKO_A_TX_7_MBHC_ATEST_REFCTRL (0x172) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_TX_7_MBHC_ATEST_REFCTRL__POR (0x00) +#define TAIKO_A_TX_7_MBHC_ADC (0x173) +#define TAIKO_A_TX_7_MBHC_ADC__POR (0x44) +#define TAIKO_A_TX_7_MBHC_TEST_CTL (0x174) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_TX_7_MBHC_TEST_CTL__POR (0x38) +#define TAIKO_A_TX_7_MBHC_SAR_ERR (0x175) +#define TAIKO_A_TX_7_MBHC_SAR_ERR__POR (0x00) +#define TAIKO_A_TX_7_TXFE_CLKDIV (0x176) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_TX_7_TXFE_CLKDIV__POR (0x0B) +#define TAIKO_A_BUCK_MODE_1 (0x181) +#define TAIKO_A_BUCK_MODE_1__POR (0x21) +#define TAIKO_A_BUCK_MODE_2 (0x182) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_BUCK_MODE_2__POR (0xFF) +#define TAIKO_A_BUCK_MODE_3 (0x183) +#define TAIKO_A_BUCK_MODE_3__POR (0xCC) +#define TAIKO_A_BUCK_MODE_4 (0x184) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_BUCK_MODE_4__POR (0x3A) +#define TAIKO_A_BUCK_MODE_5 (0x185) +#define TAIKO_A_BUCK_MODE_5__POR (0x00) +#define TAIKO_A_BUCK_CTRL_VCL_1 (0x186) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_BUCK_CTRL_VCL_1__POR (0x48) +#define TAIKO_A_BUCK_CTRL_VCL_2 (0x187) +#define TAIKO_A_BUCK_CTRL_VCL_2__POR (0xA3) +#define TAIKO_A_BUCK_CTRL_VCL_3 (0x188) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_BUCK_CTRL_VCL_3__POR (0x82) +#define TAIKO_A_BUCK_CTRL_CCL_1 (0x189) +#define TAIKO_A_BUCK_CTRL_CCL_1__POR (0xAB) +#define TAIKO_A_BUCK_CTRL_CCL_2 (0x18A) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_BUCK_CTRL_CCL_2__POR (0xDC) +#define TAIKO_A_BUCK_CTRL_CCL_3 (0x18B) +#define TAIKO_A_BUCK_CTRL_CCL_3__POR (0x6A) +#define TAIKO_A_BUCK_CTRL_CCL_4 (0x18C) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_BUCK_CTRL_CCL_4__POR (0x58) +#define TAIKO_A_BUCK_CTRL_PWM_DRVR_1 (0x18D) +#define TAIKO_A_BUCK_CTRL_PWM_DRVR_1__POR (0x50) +#define TAIKO_A_BUCK_CTRL_PWM_DRVR_2 (0x18E) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_BUCK_CTRL_PWM_DRVR_2__POR (0x64) +#define TAIKO_A_BUCK_CTRL_PWM_DRVR_3 (0x18F) +#define TAIKO_A_BUCK_CTRL_PWM_DRVR_3__POR (0x77) +#define TAIKO_A_BUCK_TMUX_A_D (0x190) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_BUCK_TMUX_A_D__POR (0x00) +#define TAIKO_A_NCP_BUCKREF (0x191) +#define TAIKO_A_NCP_BUCKREF__POR (0x00) +#define TAIKO_A_NCP_EN (0x192) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_NCP_EN__POR (0xFE) +#define TAIKO_A_NCP_CLK (0x193) +#define TAIKO_A_NCP_CLK__POR (0x94) +#define TAIKO_A_NCP_STATIC (0x194) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_NCP_STATIC__POR (0x28) +#define TAIKO_A_NCP_VTH_LOW (0x195) +#define TAIKO_A_NCP_VTH_LOW__POR (0x88) +#define TAIKO_A_NCP_VTH_HIGH (0x196) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_NCP_VTH_HIGH__POR (0xA0) +#define TAIKO_A_NCP_ATEST (0x197) +#define TAIKO_A_NCP_ATEST__POR (0x00) +#define TAIKO_A_NCP_DTEST (0x198) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_NCP_DTEST__POR (0x00) +#define TAIKO_A_NCP_DLY1 (0x199) +#define TAIKO_A_NCP_DLY1__POR (0x06) +#define TAIKO_A_NCP_DLY2 (0x19A) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_NCP_DLY2__POR (0x06) +#define TAIKO_A_RX_AUX_SW_CTL (0x19B) +#define TAIKO_A_RX_AUX_SW_CTL__POR (0x00) +#define TAIKO_A_RX_PA_AUX_IN_CONN (0x19C) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_RX_PA_AUX_IN_CONN__POR (0x00) +#define TAIKO_A_RX_COM_TIMER_DIV (0x19E) +#define TAIKO_A_RX_COM_TIMER_DIV__POR (0xE8) +#define TAIKO_A_RX_COM_OCP_CTL (0x19F) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_RX_COM_OCP_CTL__POR (0x1F) +#define TAIKO_A_RX_COM_OCP_COUNT (0x1A0) +#define TAIKO_A_RX_COM_OCP_COUNT__POR (0x77) +#define TAIKO_A_RX_COM_DAC_CTL (0x1A1) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_RX_COM_DAC_CTL__POR (0x00) +#define TAIKO_A_RX_COM_BIAS (0x1A2) +#define TAIKO_A_RX_COM_BIAS__POR (0x00) +#define TAIKO_A_RX_HPH_AUTO_CHOP (0x1A4) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_RX_HPH_AUTO_CHOP__POR (0x38) +#define TAIKO_A_RX_HPH_CHOP_CTL (0x1A5) +#define TAIKO_A_RX_HPH_CHOP_CTL__POR (0xB4) +#define TAIKO_A_RX_HPH_BIAS_PA (0x1A6) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_RX_HPH_BIAS_PA__POR (0xAA) +#define TAIKO_A_RX_HPH_BIAS_LDO (0x1A7) +#define TAIKO_A_RX_HPH_BIAS_LDO__POR (0x87) +#define TAIKO_A_RX_HPH_BIAS_CNP (0x1A8) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_RX_HPH_BIAS_CNP__POR (0x8A) +#define TAIKO_A_RX_HPH_BIAS_WG_OCP (0x1A9) +#define TAIKO_A_RX_HPH_BIAS_WG_OCP__POR (0x2A) +#define TAIKO_A_RX_HPH_OCP_CTL (0x1AA) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_RX_HPH_OCP_CTL__POR (0x68) +#define TAIKO_A_RX_HPH_CNP_EN (0x1AB) +#define TAIKO_A_RX_HPH_CNP_EN__POR (0x80) +#define TAIKO_A_RX_HPH_CNP_WG_CTL (0x1AC) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_RX_HPH_CNP_WG_CTL__POR (0xDE) +#define TAIKO_A_RX_HPH_CNP_WG_TIME (0x1AD) +#define TAIKO_A_RX_HPH_CNP_WG_TIME__POR (0x2A) +#define TAIKO_A_RX_HPH_L_GAIN (0x1AE) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_RX_HPH_L_GAIN__POR (0x00) +#define TAIKO_A_RX_HPH_L_TEST (0x1AF) +#define TAIKO_A_RX_HPH_L_TEST__POR (0x00) +#define TAIKO_A_RX_HPH_L_PA_CTL (0x1B0) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_RX_HPH_L_PA_CTL__POR (0x40) +#define TAIKO_A_RX_HPH_L_DAC_CTL (0x1B1) +#define TAIKO_A_RX_HPH_L_DAC_CTL__POR (0x00) +#define TAIKO_A_RX_HPH_L_ATEST (0x1B2) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_RX_HPH_L_ATEST__POR (0x00) +#define TAIKO_A_RX_HPH_L_STATUS (0x1B3) +#define TAIKO_A_RX_HPH_L_STATUS__POR (0x00) +#define TAIKO_A_RX_HPH_R_GAIN (0x1B4) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_RX_HPH_R_GAIN__POR (0x00) +#define TAIKO_A_RX_HPH_R_TEST (0x1B5) +#define TAIKO_A_RX_HPH_R_TEST__POR (0x00) +#define TAIKO_A_RX_HPH_R_PA_CTL (0x1B6) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_RX_HPH_R_PA_CTL__POR (0x40) +#define TAIKO_A_RX_HPH_R_DAC_CTL (0x1B7) +#define TAIKO_A_RX_HPH_R_DAC_CTL__POR (0x00) +#define TAIKO_A_RX_HPH_R_ATEST (0x1B8) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_RX_HPH_R_ATEST__POR (0x00) +#define TAIKO_A_RX_HPH_R_STATUS (0x1B9) +#define TAIKO_A_RX_HPH_R_STATUS__POR (0x00) +#define TAIKO_A_RX_EAR_BIAS_PA (0x1BA) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_RX_EAR_BIAS_PA__POR (0xA6) +#define TAIKO_A_RX_EAR_BIAS_CMBUFF (0x1BB) +#define TAIKO_A_RX_EAR_BIAS_CMBUFF__POR (0xA0) +#define TAIKO_A_RX_EAR_EN (0x1BC) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_RX_EAR_EN__POR (0x00) +#define TAIKO_A_RX_EAR_GAIN (0x1BD) +#define TAIKO_A_RX_EAR_GAIN__POR (0x02) +#define TAIKO_A_RX_EAR_CMBUFF (0x1BE) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_RX_EAR_CMBUFF__POR (0x04) +#define TAIKO_A_RX_EAR_ICTL (0x1BF) +#define TAIKO_A_RX_EAR_ICTL__POR (0x40) +#define TAIKO_A_RX_EAR_CCOMP (0x1C0) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_RX_EAR_CCOMP__POR (0x08) +#define TAIKO_A_RX_EAR_VCM (0x1C1) +#define TAIKO_A_RX_EAR_VCM__POR (0x03) +#define TAIKO_A_RX_EAR_CNP (0x1C2) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_RX_EAR_CNP__POR (0xF2) +#define TAIKO_A_RX_EAR_DAC_CTL_ATEST (0x1C3) +#define TAIKO_A_RX_EAR_DAC_CTL_ATEST__POR (0x00) +#define TAIKO_A_RX_EAR_STATUS (0x1C5) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_RX_EAR_STATUS__POR (0x04) +#define TAIKO_A_RX_LINE_BIAS_PA (0x1C6) +#define TAIKO_A_RX_LINE_BIAS_PA__POR (0xA8) +#define TAIKO_A_RX_BUCK_BIAS1 (0x1C7) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_RX_BUCK_BIAS1__POR (0x42) +#define TAIKO_A_RX_BUCK_BIAS2 (0x1C8) +#define TAIKO_A_RX_BUCK_BIAS2__POR (0x84) +#define TAIKO_A_RX_LINE_COM (0x1C9) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_RX_LINE_COM__POR (0x80) +#define TAIKO_A_RX_LINE_CNP_EN (0x1CA) +#define TAIKO_A_RX_LINE_CNP_EN__POR (0x00) +#define TAIKO_A_RX_LINE_CNP_WG_CTL (0x1CB) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_RX_LINE_CNP_WG_CTL__POR (0x00) +#define TAIKO_A_RX_LINE_CNP_WG_TIME (0x1CC) +#define TAIKO_A_RX_LINE_CNP_WG_TIME__POR (0x04) +#define TAIKO_A_RX_LINE_1_GAIN (0x1CD) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_RX_LINE_1_GAIN__POR (0x00) +#define TAIKO_A_RX_LINE_1_TEST (0x1CE) +#define TAIKO_A_RX_LINE_1_TEST__POR (0x00) +#define TAIKO_A_RX_LINE_1_DAC_CTL (0x1CF) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_RX_LINE_1_DAC_CTL__POR (0x00) +#define TAIKO_A_RX_LINE_1_STATUS (0x1D0) +#define TAIKO_A_RX_LINE_1_STATUS__POR (0x00) +#define TAIKO_A_RX_LINE_2_GAIN (0x1D1) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_RX_LINE_2_GAIN__POR (0x00) +#define TAIKO_A_RX_LINE_2_TEST (0x1D2) +#define TAIKO_A_RX_LINE_2_TEST__POR (0x00) +#define TAIKO_A_RX_LINE_2_DAC_CTL (0x1D3) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_RX_LINE_2_DAC_CTL__POR (0x00) +#define TAIKO_A_RX_LINE_2_STATUS (0x1D4) +#define TAIKO_A_RX_LINE_2_STATUS__POR (0x00) +#define TAIKO_A_RX_LINE_3_GAIN (0x1D5) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_RX_LINE_3_GAIN__POR (0x00) +#define TAIKO_A_RX_LINE_3_TEST (0x1D6) +#define TAIKO_A_RX_LINE_3_TEST__POR (0x00) +#define TAIKO_A_RX_LINE_3_DAC_CTL (0x1D7) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_RX_LINE_3_DAC_CTL__POR (0x00) +#define TAIKO_A_RX_LINE_3_STATUS (0x1D8) +#define TAIKO_A_RX_LINE_3_STATUS__POR (0x00) +#define TAIKO_A_RX_LINE_4_GAIN (0x1D9) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_RX_LINE_4_GAIN__POR (0x00) +#define TAIKO_A_RX_LINE_4_TEST (0x1DA) +#define TAIKO_A_RX_LINE_4_TEST__POR (0x00) +#define TAIKO_A_RX_LINE_4_DAC_CTL (0x1DB) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_RX_LINE_4_DAC_CTL__POR (0x00) +#define TAIKO_A_RX_LINE_4_STATUS (0x1DC) +#define TAIKO_A_RX_LINE_4_STATUS__POR (0x00) +#define TAIKO_A_RX_LINE_CNP_DBG (0x1DD) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_RX_LINE_CNP_DBG__POR (0x00) +#define TAIKO_A_SPKR_DRV_EN (0x1DF) +#define TAIKO_A_SPKR_DRV_EN__POR (0x6F) +#define TAIKO_A_SPKR_DRV_GAIN (0x1E0) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_SPKR_DRV_GAIN__POR (0x00) +#define TAIKO_A_SPKR_DRV_DAC_CTL (0x1E1) +#define TAIKO_A_SPKR_DRV_DAC_CTL__POR (0x04) +#define TAIKO_A_SPKR_DRV_OCP_CTL (0x1E2) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_SPKR_DRV_OCP_CTL__POR (0x98) +#define TAIKO_A_SPKR_DRV_CLIP_DET (0x1E3) +#define TAIKO_A_SPKR_DRV_CLIP_DET__POR (0x48) +#define TAIKO_A_SPKR_DRV_IEC (0x1E4) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_SPKR_DRV_IEC__POR (0x20) +#define TAIKO_A_SPKR_DRV_DBG_DAC (0x1E5) +#define TAIKO_A_SPKR_DRV_DBG_DAC__POR (0x05) +#define TAIKO_A_SPKR_DRV_DBG_PA (0x1E6) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_SPKR_DRV_DBG_PA__POR (0x18) +#define TAIKO_A_SPKR_DRV_DBG_PWRSTG (0x1E7) +#define TAIKO_A_SPKR_DRV_DBG_PWRSTG__POR (0x00) +#define TAIKO_A_SPKR_DRV_BIAS_LDO (0x1E8) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_SPKR_DRV_BIAS_LDO__POR (0x45) +#define TAIKO_A_SPKR_DRV_BIAS_INT (0x1E9) +#define TAIKO_A_SPKR_DRV_BIAS_INT__POR (0xA5) +#define TAIKO_A_SPKR_DRV_BIAS_PA (0x1EA) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_SPKR_DRV_BIAS_PA__POR (0x55) +#define TAIKO_A_SPKR_DRV_STATUS_OCP (0x1EB) +#define TAIKO_A_SPKR_DRV_STATUS_OCP__POR (0x00) +#define TAIKO_A_SPKR_DRV_STATUS_PA (0x1EC) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_SPKR_DRV_STATUS_PA__POR (0x00) +#define TAIKO_A_SPKR_PROT_EN (0x1ED) +#define TAIKO_A_SPKR_PROT_EN__POR (0x00) +#define TAIKO_A_SPKR_PROT_ADC_EN (0x1EE) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_SPKR_PROT_ADC_EN__POR (0x44) +#define TAIKO_A_SPKR_PROT_ISENSE_BIAS (0x1EF) +#define TAIKO_A_SPKR_PROT_ISENSE_BIAS__POR (0x44) +#define TAIKO_A_SPKR_PROT_VSENSE_BIAS (0x1F0) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_SPKR_PROT_VSENSE_BIAS__POR (0x44) +#define TAIKO_A_SPKR_PROT_ADC_ATEST_REFCTRL (0x1F1) +#define TAIKO_A_SPKR_PROT_ADC_ATEST_REFCTRL__POR (0x00) +#define TAIKO_A_SPKR_PROT_ADC_TEST_CTL (0x1F2) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_SPKR_PROT_ADC_TEST_CTL__POR (0x38) +#define TAIKO_A_SPKR_PROT_TEST_BLOCK_EN (0x1F3) +#define TAIKO_A_SPKR_PROT_TEST_BLOCK_EN__POR (0xFC) +#define TAIKO_A_SPKR_PROT_ATEST (0x1F4) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_SPKR_PROT_ATEST__POR (0x00) +#define TAIKO_A_SPKR_PROT_V_SAR_ERR (0x1F5) +#define TAIKO_A_SPKR_PROT_V_SAR_ERR__POR (0x00) +#define TAIKO_A_SPKR_PROT_I_SAR_ERR (0x1F6) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_SPKR_PROT_I_SAR_ERR__POR (0x00) +#define TAIKO_A_SPKR_PROT_LDO_CTRL (0x1F7) +#define TAIKO_A_SPKR_PROT_LDO_CTRL__POR (0x00) +#define TAIKO_A_SPKR_PROT_ISENSE_CTRL (0x1F8) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_SPKR_PROT_ISENSE_CTRL__POR (0x00) +#define TAIKO_A_SPKR_PROT_VSENSE_CTRL (0x1F9) +#define TAIKO_A_SPKR_PROT_VSENSE_CTRL__POR (0x00) +#define TAIKO_A_RC_OSC_FREQ (0x1FA) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_RC_OSC_FREQ__POR (0x46) +#define TAIKO_A_RC_OSC_TEST (0x1FB) +#define TAIKO_A_RC_OSC_TEST__POR (0x0A) +#define TAIKO_A_RC_OSC_STATUS (0x1FC) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_RC_OSC_STATUS__POR (0x18) +#define TAIKO_A_RC_OSC_TUNER (0x1FD) +#define TAIKO_A_RC_OSC_TUNER__POR (0x00) +#define TAIKO_A_MBHC_HPH (0x1FE) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_MBHC_HPH__POR (0x44) +#define TAIKO_A_CDC_ANC1_B1_CTL (0x200) +#define TAIKO_A_CDC_ANC1_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_ANC2_B1_CTL (0x280) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_ANC2_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_ANC1_SHIFT (0x201) +#define TAIKO_A_CDC_ANC1_SHIFT__POR (0x00) +#define TAIKO_A_CDC_ANC2_SHIFT (0x281) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_ANC2_SHIFT__POR (0x00) +#define TAIKO_A_CDC_ANC1_IIR_B1_CTL (0x202) +#define TAIKO_A_CDC_ANC1_IIR_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_ANC2_IIR_B1_CTL (0x282) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_ANC2_IIR_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_ANC1_IIR_B2_CTL (0x203) +#define TAIKO_A_CDC_ANC1_IIR_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_ANC2_IIR_B2_CTL (0x283) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_ANC2_IIR_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_ANC1_IIR_B3_CTL (0x204) +#define TAIKO_A_CDC_ANC1_IIR_B3_CTL__POR (0x00) +#define TAIKO_A_CDC_ANC2_IIR_B3_CTL (0x284) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_ANC2_IIR_B3_CTL__POR (0x00) +#define TAIKO_A_CDC_ANC1_LPF_B1_CTL (0x206) +#define TAIKO_A_CDC_ANC1_LPF_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_ANC2_LPF_B1_CTL (0x286) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_ANC2_LPF_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_ANC1_LPF_B2_CTL (0x207) +#define TAIKO_A_CDC_ANC1_LPF_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_ANC2_LPF_B2_CTL (0x287) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_ANC2_LPF_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_ANC1_SPARE (0x209) +#define TAIKO_A_CDC_ANC1_SPARE__POR (0x00) +#define TAIKO_A_CDC_ANC2_SPARE (0x289) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_ANC2_SPARE__POR (0x00) +#define TAIKO_A_CDC_ANC1_SMLPF_CTL (0x20A) +#define TAIKO_A_CDC_ANC1_SMLPF_CTL__POR (0x00) +#define TAIKO_A_CDC_ANC2_SMLPF_CTL (0x28A) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_ANC2_SMLPF_CTL__POR (0x00) +#define TAIKO_A_CDC_ANC1_DCFLT_CTL (0x20B) +#define TAIKO_A_CDC_ANC1_DCFLT_CTL__POR (0x00) +#define TAIKO_A_CDC_ANC2_DCFLT_CTL (0x28B) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_ANC2_DCFLT_CTL__POR (0x00) +#define TAIKO_A_CDC_ANC1_GAIN_CTL (0x20C) +#define TAIKO_A_CDC_ANC1_GAIN_CTL__POR (0x00) +#define TAIKO_A_CDC_ANC2_GAIN_CTL (0x28C) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_ANC2_GAIN_CTL__POR (0x00) +#define TAIKO_A_CDC_ANC1_B2_CTL (0x20D) +#define TAIKO_A_CDC_ANC1_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_ANC2_B2_CTL (0x28D) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_ANC2_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_TX1_VOL_CTL_TIMER (0x220) +#define TAIKO_A_CDC_TX1_VOL_CTL_TIMER__POR (0x00) +#define TAIKO_A_CDC_TX2_VOL_CTL_TIMER (0x228) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_TX2_VOL_CTL_TIMER__POR (0x00) +#define TAIKO_A_CDC_TX3_VOL_CTL_TIMER (0x230) +#define TAIKO_A_CDC_TX3_VOL_CTL_TIMER__POR (0x00) +#define TAIKO_A_CDC_TX4_VOL_CTL_TIMER (0x238) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_TX4_VOL_CTL_TIMER__POR (0x00) +#define TAIKO_A_CDC_TX5_VOL_CTL_TIMER (0x240) +#define TAIKO_A_CDC_TX5_VOL_CTL_TIMER__POR (0x00) +#define TAIKO_A_CDC_TX6_VOL_CTL_TIMER (0x248) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_TX6_VOL_CTL_TIMER__POR (0x00) +#define TAIKO_A_CDC_TX7_VOL_CTL_TIMER (0x250) +#define TAIKO_A_CDC_TX7_VOL_CTL_TIMER__POR (0x00) +#define TAIKO_A_CDC_TX8_VOL_CTL_TIMER (0x258) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_TX8_VOL_CTL_TIMER__POR (0x00) +#define TAIKO_A_CDC_TX9_VOL_CTL_TIMER (0x260) +#define TAIKO_A_CDC_TX9_VOL_CTL_TIMER__POR (0x00) +#define TAIKO_A_CDC_TX10_VOL_CTL_TIMER (0x268) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_TX10_VOL_CTL_TIMER__POR (0x00) +#define TAIKO_A_CDC_TX1_VOL_CTL_GAIN (0x221) +#define TAIKO_A_CDC_TX1_VOL_CTL_GAIN__POR (0x00) +#define TAIKO_A_CDC_TX2_VOL_CTL_GAIN (0x229) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_TX2_VOL_CTL_GAIN__POR (0x00) +#define TAIKO_A_CDC_TX3_VOL_CTL_GAIN (0x231) +#define TAIKO_A_CDC_TX3_VOL_CTL_GAIN__POR (0x00) +#define TAIKO_A_CDC_TX4_VOL_CTL_GAIN (0x239) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_TX4_VOL_CTL_GAIN__POR (0x00) +#define TAIKO_A_CDC_TX5_VOL_CTL_GAIN (0x241) +#define TAIKO_A_CDC_TX5_VOL_CTL_GAIN__POR (0x00) +#define TAIKO_A_CDC_TX6_VOL_CTL_GAIN (0x249) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_TX6_VOL_CTL_GAIN__POR (0x00) +#define TAIKO_A_CDC_TX7_VOL_CTL_GAIN (0x251) +#define TAIKO_A_CDC_TX7_VOL_CTL_GAIN__POR (0x00) +#define TAIKO_A_CDC_TX8_VOL_CTL_GAIN (0x259) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_TX8_VOL_CTL_GAIN__POR (0x00) +#define TAIKO_A_CDC_TX9_VOL_CTL_GAIN (0x261) +#define TAIKO_A_CDC_TX9_VOL_CTL_GAIN__POR (0x00) +#define TAIKO_A_CDC_TX10_VOL_CTL_GAIN (0x269) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_TX10_VOL_CTL_GAIN__POR (0x00) +#define TAIKO_A_CDC_TX1_VOL_CTL_CFG (0x222) +#define TAIKO_A_CDC_TX1_VOL_CTL_CFG__POR (0x00) +#define TAIKO_A_CDC_TX2_VOL_CTL_CFG (0x22A) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_TX2_VOL_CTL_CFG__POR (0x00) +#define TAIKO_A_CDC_TX3_VOL_CTL_CFG (0x232) +#define TAIKO_A_CDC_TX3_VOL_CTL_CFG__POR (0x00) +#define TAIKO_A_CDC_TX4_VOL_CTL_CFG (0x23A) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_TX4_VOL_CTL_CFG__POR (0x00) +#define TAIKO_A_CDC_TX5_VOL_CTL_CFG (0x242) +#define TAIKO_A_CDC_TX5_VOL_CTL_CFG__POR (0x00) +#define TAIKO_A_CDC_TX6_VOL_CTL_CFG (0x24A) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_TX6_VOL_CTL_CFG__POR (0x00) +#define TAIKO_A_CDC_TX7_VOL_CTL_CFG (0x252) +#define TAIKO_A_CDC_TX7_VOL_CTL_CFG__POR (0x00) +#define TAIKO_A_CDC_TX8_VOL_CTL_CFG (0x25A) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_TX8_VOL_CTL_CFG__POR (0x00) +#define TAIKO_A_CDC_TX9_VOL_CTL_CFG (0x262) +#define TAIKO_A_CDC_TX9_VOL_CTL_CFG__POR (0x00) +#define TAIKO_A_CDC_TX10_VOL_CTL_CFG (0x26A) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_TX10_VOL_CTL_CFG__POR (0x00) +#define TAIKO_A_CDC_TX1_MUX_CTL (0x223) +#define TAIKO_A_CDC_TX1_MUX_CTL__POR (0x08) +#define TAIKO_A_CDC_TX2_MUX_CTL (0x22B) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_TX2_MUX_CTL__POR (0x08) +#define TAIKO_A_CDC_TX3_MUX_CTL (0x233) +#define TAIKO_A_CDC_TX3_MUX_CTL__POR (0x08) +#define TAIKO_A_CDC_TX4_MUX_CTL (0x23B) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_TX4_MUX_CTL__POR (0x08) +#define TAIKO_A_CDC_TX5_MUX_CTL (0x243) +#define TAIKO_A_CDC_TX5_MUX_CTL__POR (0x08) +#define TAIKO_A_CDC_TX6_MUX_CTL (0x24B) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_TX6_MUX_CTL__POR (0x08) +#define TAIKO_A_CDC_TX7_MUX_CTL (0x253) +#define TAIKO_A_CDC_TX7_MUX_CTL__POR (0x08) +#define TAIKO_A_CDC_TX8_MUX_CTL (0x25B) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_TX8_MUX_CTL__POR (0x08) +#define TAIKO_A_CDC_TX9_MUX_CTL (0x263) +#define TAIKO_A_CDC_TX9_MUX_CTL__POR (0x08) +#define TAIKO_A_CDC_TX10_MUX_CTL (0x26B) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_TX10_MUX_CTL__POR (0x08) +#define TAIKO_A_CDC_TX1_CLK_FS_CTL (0x224) +#define TAIKO_A_CDC_TX1_CLK_FS_CTL__POR (0x03) +#define TAIKO_A_CDC_TX2_CLK_FS_CTL (0x22C) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_TX2_CLK_FS_CTL__POR (0x03) +#define TAIKO_A_CDC_TX3_CLK_FS_CTL (0x234) +#define TAIKO_A_CDC_TX3_CLK_FS_CTL__POR (0x03) +#define TAIKO_A_CDC_TX4_CLK_FS_CTL (0x23C) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_TX4_CLK_FS_CTL__POR (0x03) +#define TAIKO_A_CDC_TX5_CLK_FS_CTL (0x244) +#define TAIKO_A_CDC_TX5_CLK_FS_CTL__POR (0x03) +#define TAIKO_A_CDC_TX6_CLK_FS_CTL (0x24C) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_TX6_CLK_FS_CTL__POR (0x03) +#define TAIKO_A_CDC_TX7_CLK_FS_CTL (0x254) +#define TAIKO_A_CDC_TX7_CLK_FS_CTL__POR (0x03) +#define TAIKO_A_CDC_TX8_CLK_FS_CTL (0x25C) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_TX8_CLK_FS_CTL__POR (0x03) +#define TAIKO_A_CDC_TX9_CLK_FS_CTL (0x264) +#define TAIKO_A_CDC_TX9_CLK_FS_CTL__POR (0x03) +#define TAIKO_A_CDC_TX10_CLK_FS_CTL (0x26C) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_TX10_CLK_FS_CTL__POR (0x03) +#define TAIKO_A_CDC_TX1_DMIC_CTL (0x225) +#define TAIKO_A_CDC_TX1_DMIC_CTL__POR (0x00) +#define TAIKO_A_CDC_TX2_DMIC_CTL (0x22D) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_TX2_DMIC_CTL__POR (0x00) +#define TAIKO_A_CDC_TX3_DMIC_CTL (0x235) +#define TAIKO_A_CDC_TX3_DMIC_CTL__POR (0x00) +#define TAIKO_A_CDC_TX4_DMIC_CTL (0x23D) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_TX4_DMIC_CTL__POR (0x00) +#define TAIKO_A_CDC_TX5_DMIC_CTL (0x245) +#define TAIKO_A_CDC_TX5_DMIC_CTL__POR (0x00) +#define TAIKO_A_CDC_TX6_DMIC_CTL (0x24D) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_TX6_DMIC_CTL__POR (0x00) +#define TAIKO_A_CDC_TX7_DMIC_CTL (0x255) +#define TAIKO_A_CDC_TX7_DMIC_CTL__POR (0x00) +#define TAIKO_A_CDC_TX8_DMIC_CTL (0x25D) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_TX8_DMIC_CTL__POR (0x00) +#define TAIKO_A_CDC_TX9_DMIC_CTL (0x265) +#define TAIKO_A_CDC_TX9_DMIC_CTL__POR (0x00) +#define TAIKO_A_CDC_TX10_DMIC_CTL (0x26D) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_TX10_DMIC_CTL__POR (0x00) +#define TAIKO_A_CDC_DEBUG_B1_CTL (0x278) +#define TAIKO_A_CDC_DEBUG_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_DEBUG_B2_CTL (0x279) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_DEBUG_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_DEBUG_B3_CTL (0x27A) +#define TAIKO_A_CDC_DEBUG_B3_CTL__POR (0x00) +#define TAIKO_A_CDC_DEBUG_B4_CTL (0x27B) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_DEBUG_B4_CTL__POR (0x00) +#define TAIKO_A_CDC_DEBUG_B5_CTL (0x27C) +#define TAIKO_A_CDC_DEBUG_B5_CTL__POR (0x00) +#define TAIKO_A_CDC_DEBUG_B6_CTL (0x27D) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_DEBUG_B6_CTL__POR (0x00) +#define TAIKO_A_CDC_DEBUG_B7_CTL (0x27E) +#define TAIKO_A_CDC_DEBUG_B7_CTL__POR (0x00) +#define TAIKO_A_CDC_SRC1_PDA_CFG (0x2A0) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_SRC1_PDA_CFG__POR (0x00) +#define TAIKO_A_CDC_SRC2_PDA_CFG (0x2A8) +#define TAIKO_A_CDC_SRC2_PDA_CFG__POR (0x00) +#define TAIKO_A_CDC_SRC1_FS_CTL (0x2A1) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_SRC1_FS_CTL__POR (0x1B) +#define TAIKO_A_CDC_SRC2_FS_CTL (0x2A9) +#define TAIKO_A_CDC_SRC2_FS_CTL__POR (0x1B) +#define TAIKO_A_CDC_RX1_B1_CTL (0x2B0) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_RX1_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_RX2_B1_CTL (0x2B8) +#define TAIKO_A_CDC_RX2_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_RX3_B1_CTL (0x2C0) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_RX3_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_RX4_B1_CTL (0x2C8) +#define TAIKO_A_CDC_RX4_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_RX5_B1_CTL (0x2D0) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_RX5_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_RX6_B1_CTL (0x2D8) +#define TAIKO_A_CDC_RX6_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_RX7_B1_CTL (0x2E0) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_RX7_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_RX1_B2_CTL (0x2B1) +#define TAIKO_A_CDC_RX1_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_RX2_B2_CTL (0x2B9) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_RX2_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_RX3_B2_CTL (0x2C1) +#define TAIKO_A_CDC_RX3_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_RX4_B2_CTL (0x2C9) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_RX4_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_RX5_B2_CTL (0x2D1) +#define TAIKO_A_CDC_RX5_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_RX6_B2_CTL (0x2D9) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_RX6_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_RX7_B2_CTL (0x2E1) +#define TAIKO_A_CDC_RX7_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_RX1_B3_CTL (0x2B2) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_RX1_B3_CTL__POR (0x00) +#define TAIKO_A_CDC_RX2_B3_CTL (0x2BA) +#define TAIKO_A_CDC_RX2_B3_CTL__POR (0x00) +#define TAIKO_A_CDC_RX3_B3_CTL (0x2C2) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_RX3_B3_CTL__POR (0x00) +#define TAIKO_A_CDC_RX4_B3_CTL (0x2CA) +#define TAIKO_A_CDC_RX4_B3_CTL__POR (0x00) +#define TAIKO_A_CDC_RX5_B3_CTL (0x2D2) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_RX5_B3_CTL__POR (0x00) +#define TAIKO_A_CDC_RX6_B3_CTL (0x2DA) +#define TAIKO_A_CDC_RX6_B3_CTL__POR (0x00) +#define TAIKO_A_CDC_RX7_B3_CTL (0x2E2) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_RX7_B3_CTL__POR (0x00) +#define TAIKO_A_CDC_RX1_B4_CTL (0x2B3) +#define TAIKO_A_CDC_RX1_B4_CTL__POR (0x00) +#define TAIKO_A_CDC_RX2_B4_CTL (0x2BB) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_RX2_B4_CTL__POR (0x00) +#define TAIKO_A_CDC_RX3_B4_CTL (0x2C3) +#define TAIKO_A_CDC_RX3_B4_CTL__POR (0x00) +#define TAIKO_A_CDC_RX4_B4_CTL (0x2CB) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_RX4_B4_CTL__POR (0x00) +#define TAIKO_A_CDC_RX5_B4_CTL (0x2D3) +#define TAIKO_A_CDC_RX5_B4_CTL__POR (0x00) +#define TAIKO_A_CDC_RX6_B4_CTL (0x2DB) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_RX6_B4_CTL__POR (0x00) +#define TAIKO_A_CDC_RX7_B4_CTL (0x2E3) +#define TAIKO_A_CDC_RX7_B4_CTL__POR (0x00) +#define TAIKO_A_CDC_RX1_B5_CTL (0x2B4) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_RX1_B5_CTL__POR (0x78) +#define TAIKO_A_CDC_RX2_B5_CTL (0x2BC) +#define TAIKO_A_CDC_RX2_B5_CTL__POR (0x78) +#define TAIKO_A_CDC_RX3_B5_CTL (0x2C4) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_RX3_B5_CTL__POR (0x78) +#define TAIKO_A_CDC_RX4_B5_CTL (0x2CC) +#define TAIKO_A_CDC_RX4_B5_CTL__POR (0x78) +#define TAIKO_A_CDC_RX5_B5_CTL (0x2D4) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_RX5_B5_CTL__POR (0x78) +#define TAIKO_A_CDC_RX6_B5_CTL (0x2DC) +#define TAIKO_A_CDC_RX6_B5_CTL__POR (0x78) +#define TAIKO_A_CDC_RX7_B5_CTL (0x2E4) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_RX7_B5_CTL__POR (0x78) +#define TAIKO_A_CDC_RX1_B6_CTL (0x2B5) +#define TAIKO_A_CDC_RX1_B6_CTL__POR (0x80) +#define TAIKO_A_CDC_RX2_B6_CTL (0x2BD) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_RX2_B6_CTL__POR (0x80) +#define TAIKO_A_CDC_RX3_B6_CTL (0x2C5) +#define TAIKO_A_CDC_RX3_B6_CTL__POR (0x80) +#define TAIKO_A_CDC_RX4_B6_CTL (0x2CD) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_RX4_B6_CTL__POR (0x80) +#define TAIKO_A_CDC_RX5_B6_CTL (0x2D5) +#define TAIKO_A_CDC_RX5_B6_CTL__POR (0x80) +#define TAIKO_A_CDC_RX6_B6_CTL (0x2DD) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_RX6_B6_CTL__POR (0x80) +#define TAIKO_A_CDC_RX7_B6_CTL (0x2E5) +#define TAIKO_A_CDC_RX7_B6_CTL__POR (0x80) +#define TAIKO_A_CDC_RX1_VOL_CTL_B1_CTL (0x2B6) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_RX1_VOL_CTL_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_RX2_VOL_CTL_B1_CTL (0x2BE) +#define TAIKO_A_CDC_RX2_VOL_CTL_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_RX3_VOL_CTL_B1_CTL (0x2C6) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_RX3_VOL_CTL_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_RX4_VOL_CTL_B1_CTL (0x2CE) +#define TAIKO_A_CDC_RX4_VOL_CTL_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_RX5_VOL_CTL_B1_CTL (0x2D6) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_RX5_VOL_CTL_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_RX6_VOL_CTL_B1_CTL (0x2DE) +#define TAIKO_A_CDC_RX6_VOL_CTL_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_RX7_VOL_CTL_B1_CTL (0x2E6) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_RX7_VOL_CTL_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_RX1_VOL_CTL_B2_CTL (0x2B7) +#define TAIKO_A_CDC_RX1_VOL_CTL_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_RX2_VOL_CTL_B2_CTL (0x2BF) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_RX2_VOL_CTL_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_RX3_VOL_CTL_B2_CTL (0x2C7) +#define TAIKO_A_CDC_RX3_VOL_CTL_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_RX4_VOL_CTL_B2_CTL (0x2CF) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_RX4_VOL_CTL_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_RX5_VOL_CTL_B2_CTL (0x2D7) +#define TAIKO_A_CDC_RX5_VOL_CTL_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_RX6_VOL_CTL_B2_CTL (0x2DF) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_RX6_VOL_CTL_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_RX7_VOL_CTL_B2_CTL (0x2E7) +#define TAIKO_A_CDC_RX7_VOL_CTL_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_VBAT_CFG (0x2E8) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_VBAT_CFG__POR (0x1A) +#define TAIKO_A_CDC_VBAT_ADC_CAL1 (0x2E9) +#define TAIKO_A_CDC_VBAT_ADC_CAL1__POR (0x00) +#define TAIKO_A_CDC_VBAT_ADC_CAL2 (0x2EA) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_VBAT_ADC_CAL2__POR (0x00) +#define TAIKO_A_CDC_VBAT_ADC_CAL3 (0x2EB) +#define TAIKO_A_CDC_VBAT_ADC_CAL3__POR (0x04) +#define TAIKO_A_CDC_VBAT_PK_EST1 (0x2EC) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_VBAT_PK_EST1__POR (0xE0) +#define TAIKO_A_CDC_VBAT_PK_EST2 (0x2ED) +#define TAIKO_A_CDC_VBAT_PK_EST2__POR (0x01) +#define TAIKO_A_CDC_VBAT_PK_EST3 (0x2EE) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_VBAT_PK_EST3__POR (0x40) +#define TAIKO_A_CDC_VBAT_RF_PROC1 (0x2EF) +#define TAIKO_A_CDC_VBAT_RF_PROC1__POR (0x2A) +#define TAIKO_A_CDC_VBAT_RF_PROC2 (0x2F0) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_VBAT_RF_PROC2__POR (0x86) +#define TAIKO_A_CDC_VBAT_TAC1 (0x2F1) +#define TAIKO_A_CDC_VBAT_TAC1__POR (0x70) +#define TAIKO_A_CDC_VBAT_TAC2 (0x2F2) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_VBAT_TAC2__POR (0x18) +#define TAIKO_A_CDC_VBAT_TAC3 (0x2F3) +#define TAIKO_A_CDC_VBAT_TAC3__POR (0x18) +#define TAIKO_A_CDC_VBAT_TAC4 (0x2F4) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_VBAT_TAC4__POR (0x03) +#define TAIKO_A_CDC_VBAT_GAIN_UPD1 (0x2F5) +#define TAIKO_A_CDC_VBAT_GAIN_UPD1__POR (0x01) +#define TAIKO_A_CDC_VBAT_GAIN_UPD2 (0x2F6) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_VBAT_GAIN_UPD2__POR (0x00) +#define TAIKO_A_CDC_VBAT_GAIN_UPD3 (0x2F7) +#define TAIKO_A_CDC_VBAT_GAIN_UPD3__POR (0x64) +#define TAIKO_A_CDC_VBAT_GAIN_UPD4 (0x2F8) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_VBAT_GAIN_UPD4__POR (0x01) +#define TAIKO_A_CDC_VBAT_DEBUG1 (0x2F9) +#define TAIKO_A_CDC_VBAT_DEBUG1__POR (0x00) +#define TAIKO_A_CDC_CLK_ANC_RESET_CTL (0x300) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_CLK_ANC_RESET_CTL__POR (0x00) +#define TAIKO_A_CDC_CLK_RX_RESET_CTL (0x301) +#define TAIKO_A_CDC_CLK_RX_RESET_CTL__POR (0x00) +#define TAIKO_A_CDC_CLK_TX_RESET_B1_CTL (0x302) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_CLK_TX_RESET_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_CLK_TX_RESET_B2_CTL (0x303) +#define TAIKO_A_CDC_CLK_TX_RESET_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_CLK_DMIC_B1_CTL (0x304) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_CLK_DMIC_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_CLK_DMIC_B2_CTL (0x305) +#define TAIKO_A_CDC_CLK_DMIC_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_CLK_RX_I2S_CTL (0x306) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_CLK_RX_I2S_CTL__POR (0x03) +#define TAIKO_A_CDC_CLK_TX_I2S_CTL (0x307) +#define TAIKO_A_CDC_CLK_TX_I2S_CTL__POR (0x03) +#define TAIKO_A_CDC_CLK_OTHR_RESET_B1_CTL (0x308) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_CLK_OTHR_RESET_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_CLK_OTHR_RESET_B2_CTL (0x309) +#define TAIKO_A_CDC_CLK_OTHR_RESET_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_CLK_TX_CLK_EN_B1_CTL (0x30A) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_CLK_TX_CLK_EN_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_CLK_TX_CLK_EN_B2_CTL (0x30B) +#define TAIKO_A_CDC_CLK_TX_CLK_EN_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_CLK_OTHR_CTL (0x30C) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_CLK_OTHR_CTL__POR (0x00) +#define TAIKO_A_CDC_CLK_RDAC_CLK_EN_CTL (0x30D) +#define TAIKO_A_CDC_CLK_RDAC_CLK_EN_CTL__POR (0x00) +#define TAIKO_A_CDC_CLK_ANC_CLK_EN_CTL (0x30E) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_CLK_ANC_CLK_EN_CTL__POR (0x00) +#define TAIKO_A_CDC_CLK_RX_B1_CTL (0x30F) +#define TAIKO_A_CDC_CLK_RX_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_CLK_RX_B2_CTL (0x310) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_CLK_RX_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_CLK_MCLK_CTL (0x311) +#define TAIKO_A_CDC_CLK_MCLK_CTL__POR (0x00) +#define TAIKO_A_CDC_CLK_PDM_CTL (0x312) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_CLK_PDM_CTL__POR (0x00) +#define TAIKO_A_CDC_CLK_SD_CTL (0x313) +#define TAIKO_A_CDC_CLK_SD_CTL__POR (0x00) +#define TAIKO_A_CDC_CLK_POWER_CTL (0x314) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_CLK_POWER_CTL__POR (0x00) +#define TAIKO_A_CDC_CLSH_B1_CTL (0x320) +#define TAIKO_A_CDC_CLSH_B1_CTL__POR (0xE4) +#define TAIKO_A_CDC_CLSH_B2_CTL (0x321) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_CLSH_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_CLSH_B3_CTL (0x322) +#define TAIKO_A_CDC_CLSH_B3_CTL__POR (0x00) +#define TAIKO_A_CDC_CLSH_BUCK_NCP_VARS (0x323) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_CLSH_BUCK_NCP_VARS__POR (0x00) +#define TAIKO_A_CDC_CLSH_IDLE_HPH_THSD (0x324) +#define TAIKO_A_CDC_CLSH_IDLE_HPH_THSD__POR (0x12) +#define TAIKO_A_CDC_CLSH_IDLE_EAR_THSD (0x325) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_CLSH_IDLE_EAR_THSD__POR (0x0C) +#define TAIKO_A_CDC_CLSH_FCLKONLY_HPH_THSD (0x326) +#define TAIKO_A_CDC_CLSH_FCLKONLY_HPH_THSD__POR (0x18) +#define TAIKO_A_CDC_CLSH_FCLKONLY_EAR_THSD (0x327) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_CLSH_FCLKONLY_EAR_THSD__POR (0x23) +#define TAIKO_A_CDC_CLSH_K_ADDR (0x328) +#define TAIKO_A_CDC_CLSH_K_ADDR__POR (0x00) +#define TAIKO_A_CDC_CLSH_K_DATA (0x329) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_CLSH_K_DATA__POR (0xA4) +#define TAIKO_A_CDC_CLSH_I_PA_FACT_HPH_L (0x32A) +#define TAIKO_A_CDC_CLSH_I_PA_FACT_HPH_L__POR (0xD7) +#define TAIKO_A_CDC_CLSH_I_PA_FACT_HPH_U (0x32B) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_CLSH_I_PA_FACT_HPH_U__POR (0x05) +#define TAIKO_A_CDC_CLSH_I_PA_FACT_EAR_L (0x32C) +#define TAIKO_A_CDC_CLSH_I_PA_FACT_EAR_L__POR (0x60) +#define TAIKO_A_CDC_CLSH_I_PA_FACT_EAR_U (0x32D) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_CLSH_I_PA_FACT_EAR_U__POR (0x09) +#define TAIKO_A_CDC_CLSH_V_PA_HD_EAR (0x32E) +#define TAIKO_A_CDC_CLSH_V_PA_HD_EAR__POR (0x00) +#define TAIKO_A_CDC_CLSH_V_PA_HD_HPH (0x32F) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_CLSH_V_PA_HD_HPH__POR (0x00) +#define TAIKO_A_CDC_CLSH_V_PA_MIN_EAR (0x330) +#define TAIKO_A_CDC_CLSH_V_PA_MIN_EAR__POR (0x00) +#define TAIKO_A_CDC_CLSH_V_PA_MIN_HPH (0x331) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_CLSH_V_PA_MIN_HPH__POR (0x00) +#define TAIKO_A_CDC_IIR1_GAIN_B1_CTL (0x340) +#define TAIKO_A_CDC_IIR1_GAIN_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_IIR2_GAIN_B1_CTL (0x350) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_IIR2_GAIN_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_IIR1_GAIN_B2_CTL (0x341) +#define TAIKO_A_CDC_IIR1_GAIN_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_IIR2_GAIN_B2_CTL (0x351) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_IIR2_GAIN_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_IIR1_GAIN_B3_CTL (0x342) +#define TAIKO_A_CDC_IIR1_GAIN_B3_CTL__POR (0x00) +#define TAIKO_A_CDC_IIR2_GAIN_B3_CTL (0x352) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_IIR2_GAIN_B3_CTL__POR (0x00) +#define TAIKO_A_CDC_IIR1_GAIN_B4_CTL (0x343) +#define TAIKO_A_CDC_IIR1_GAIN_B4_CTL__POR (0x00) +#define TAIKO_A_CDC_IIR2_GAIN_B4_CTL (0x353) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_IIR2_GAIN_B4_CTL__POR (0x00) +#define TAIKO_A_CDC_IIR1_GAIN_B5_CTL (0x344) +#define TAIKO_A_CDC_IIR1_GAIN_B5_CTL__POR (0x00) +#define TAIKO_A_CDC_IIR2_GAIN_B5_CTL (0x354) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_IIR2_GAIN_B5_CTL__POR (0x00) +#define TAIKO_A_CDC_IIR1_GAIN_B6_CTL (0x345) +#define TAIKO_A_CDC_IIR1_GAIN_B6_CTL__POR (0x00) +#define TAIKO_A_CDC_IIR2_GAIN_B6_CTL (0x355) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_IIR2_GAIN_B6_CTL__POR (0x00) +#define TAIKO_A_CDC_IIR1_GAIN_B7_CTL (0x346) +#define TAIKO_A_CDC_IIR1_GAIN_B7_CTL__POR (0x00) +#define TAIKO_A_CDC_IIR2_GAIN_B7_CTL (0x356) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_IIR2_GAIN_B7_CTL__POR (0x00) +#define TAIKO_A_CDC_IIR1_GAIN_B8_CTL (0x347) +#define TAIKO_A_CDC_IIR1_GAIN_B8_CTL__POR (0x00) +#define TAIKO_A_CDC_IIR2_GAIN_B8_CTL (0x357) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_IIR2_GAIN_B8_CTL__POR (0x00) +#define TAIKO_A_CDC_IIR1_CTL (0x348) +#define TAIKO_A_CDC_IIR1_CTL__POR (0x40) +#define TAIKO_A_CDC_IIR2_CTL (0x358) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_IIR2_CTL__POR (0x40) +#define TAIKO_A_CDC_IIR1_GAIN_TIMER_CTL (0x349) +#define TAIKO_A_CDC_IIR1_GAIN_TIMER_CTL__POR (0x00) +#define TAIKO_A_CDC_IIR2_GAIN_TIMER_CTL (0x359) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_IIR2_GAIN_TIMER_CTL__POR (0x00) +#define TAIKO_A_CDC_IIR1_COEF_B1_CTL (0x34A) +#define TAIKO_A_CDC_IIR1_COEF_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_IIR2_COEF_B1_CTL (0x35A) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_IIR2_COEF_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_IIR1_COEF_B2_CTL (0x34B) +#define TAIKO_A_CDC_IIR1_COEF_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_IIR2_COEF_B2_CTL (0x35B) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_IIR2_COEF_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_TOP_GAIN_UPDATE (0x360) +#define TAIKO_A_CDC_TOP_GAIN_UPDATE__POR (0x00) +#define TAIKO_A_CDC_COMP0_B1_CTL (0x368) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_COMP0_B1_CTL__POR (0x30) +#define TAIKO_A_CDC_COMP1_B1_CTL (0x370) +#define TAIKO_A_CDC_COMP1_B1_CTL__POR (0x30) +#define TAIKO_A_CDC_COMP2_B1_CTL (0x378) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_COMP2_B1_CTL__POR (0x30) +#define TAIKO_A_CDC_COMP0_B2_CTL (0x369) +#define TAIKO_A_CDC_COMP0_B2_CTL__POR (0xB5) +#define TAIKO_A_CDC_COMP1_B2_CTL (0x371) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_COMP1_B2_CTL__POR (0xB5) +#define TAIKO_A_CDC_COMP2_B2_CTL (0x379) +#define TAIKO_A_CDC_COMP2_B2_CTL__POR (0xB5) +#define TAIKO_A_CDC_COMP0_B3_CTL (0x36A) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_COMP0_B3_CTL__POR (0x28) +#define TAIKO_A_CDC_COMP1_B3_CTL (0x372) +#define TAIKO_A_CDC_COMP1_B3_CTL__POR (0x28) +#define TAIKO_A_CDC_COMP2_B3_CTL (0x37A) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_COMP2_B3_CTL__POR (0x28) +#define TAIKO_A_CDC_COMP0_B4_CTL (0x36B) +#define TAIKO_A_CDC_COMP0_B4_CTL__POR (0x3C) +#define TAIKO_A_CDC_COMP1_B4_CTL (0x373) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_COMP1_B4_CTL__POR (0x3C) +#define TAIKO_A_CDC_COMP2_B4_CTL (0x37B) +#define TAIKO_A_CDC_COMP2_B4_CTL__POR (0x3C) +#define TAIKO_A_CDC_COMP0_B5_CTL (0x36C) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_COMP0_B5_CTL__POR (0x1F) +#define TAIKO_A_CDC_COMP1_B5_CTL (0x374) +#define TAIKO_A_CDC_COMP1_B5_CTL__POR (0x1F) +#define TAIKO_A_CDC_COMP2_B5_CTL (0x37C) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_COMP2_B5_CTL__POR (0x1F) +#define TAIKO_A_CDC_COMP0_B6_CTL (0x36D) +#define TAIKO_A_CDC_COMP0_B6_CTL__POR (0x00) +#define TAIKO_A_CDC_COMP1_B6_CTL (0x375) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_COMP1_B6_CTL__POR (0x00) +#define TAIKO_A_CDC_COMP2_B6_CTL (0x37D) +#define TAIKO_A_CDC_COMP2_B6_CTL__POR (0x00) +#define TAIKO_A_CDC_COMP0_SHUT_DOWN_STATUS (0x36E) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_COMP0_SHUT_DOWN_STATUS__POR (0x03) +#define TAIKO_A_CDC_COMP1_SHUT_DOWN_STATUS (0x376) +#define TAIKO_A_CDC_COMP1_SHUT_DOWN_STATUS__POR (0x03) +#define TAIKO_A_CDC_COMP2_SHUT_DOWN_STATUS (0x37E) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_COMP2_SHUT_DOWN_STATUS__POR (0x03) +#define TAIKO_A_CDC_COMP0_FS_CFG (0x36F) +#define TAIKO_A_CDC_COMP0_FS_CFG__POR (0x03) +#define TAIKO_A_CDC_COMP1_FS_CFG (0x377) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_COMP1_FS_CFG__POR (0x03) +#define TAIKO_A_CDC_COMP2_FS_CFG (0x37F) +#define TAIKO_A_CDC_COMP2_FS_CFG__POR (0x03) +#define TAIKO_A_CDC_CONN_RX1_B1_CTL (0x380) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_CONN_RX1_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_RX1_B2_CTL (0x381) +#define TAIKO_A_CDC_CONN_RX1_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_RX1_B3_CTL (0x382) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_CONN_RX1_B3_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_RX2_B1_CTL (0x383) +#define TAIKO_A_CDC_CONN_RX2_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_RX2_B2_CTL (0x384) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_CONN_RX2_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_RX2_B3_CTL (0x385) +#define TAIKO_A_CDC_CONN_RX2_B3_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_RX3_B1_CTL (0x386) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_CONN_RX3_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_RX3_B2_CTL (0x387) +#define TAIKO_A_CDC_CONN_RX3_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_RX4_B1_CTL (0x388) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_CONN_RX4_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_RX4_B2_CTL (0x389) +#define TAIKO_A_CDC_CONN_RX4_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_RX5_B1_CTL (0x38A) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_CONN_RX5_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_RX5_B2_CTL (0x38B) +#define TAIKO_A_CDC_CONN_RX5_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_RX6_B1_CTL (0x38C) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_CONN_RX6_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_RX6_B2_CTL (0x38D) +#define TAIKO_A_CDC_CONN_RX6_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_RX7_B1_CTL (0x38E) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_CONN_RX7_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_RX7_B2_CTL (0x38F) +#define TAIKO_A_CDC_CONN_RX7_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_RX7_B3_CTL (0x390) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_CONN_RX7_B3_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_ANC_B1_CTL (0x391) +#define TAIKO_A_CDC_CONN_ANC_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_ANC_B2_CTL (0x392) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_CONN_ANC_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_TX_B1_CTL (0x393) +#define TAIKO_A_CDC_CONN_TX_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_TX_B2_CTL (0x394) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_CONN_TX_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_TX_B3_CTL (0x395) +#define TAIKO_A_CDC_CONN_TX_B3_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_TX_B4_CTL (0x396) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_CONN_TX_B4_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_EQ1_B1_CTL (0x397) +#define TAIKO_A_CDC_CONN_EQ1_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_EQ1_B2_CTL (0x398) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_CONN_EQ1_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_EQ1_B3_CTL (0x399) +#define TAIKO_A_CDC_CONN_EQ1_B3_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_EQ1_B4_CTL (0x39A) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_CONN_EQ1_B4_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_EQ2_B1_CTL (0x39B) +#define TAIKO_A_CDC_CONN_EQ2_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_EQ2_B2_CTL (0x39C) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_CONN_EQ2_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_EQ2_B3_CTL (0x39D) +#define TAIKO_A_CDC_CONN_EQ2_B3_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_EQ2_B4_CTL (0x39E) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_CONN_EQ2_B4_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_SRC1_B1_CTL (0x39F) +#define TAIKO_A_CDC_CONN_SRC1_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_SRC1_B2_CTL (0x3A0) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_CONN_SRC1_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_SRC2_B1_CTL (0x3A1) +#define TAIKO_A_CDC_CONN_SRC2_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_SRC2_B2_CTL (0x3A2) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_CONN_SRC2_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_TX_SB_B1_CTL (0x3A3) +#define TAIKO_A_CDC_CONN_TX_SB_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_TX_SB_B2_CTL (0x3A4) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_CONN_TX_SB_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_TX_SB_B3_CTL (0x3A5) +#define TAIKO_A_CDC_CONN_TX_SB_B3_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_TX_SB_B4_CTL (0x3A6) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_CONN_TX_SB_B4_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_TX_SB_B5_CTL (0x3A7) +#define TAIKO_A_CDC_CONN_TX_SB_B5_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_TX_SB_B6_CTL (0x3A8) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_CONN_TX_SB_B6_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_TX_SB_B7_CTL (0x3A9) +#define TAIKO_A_CDC_CONN_TX_SB_B7_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_TX_SB_B8_CTL (0x3AA) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_CONN_TX_SB_B8_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_TX_SB_B9_CTL (0x3AB) +#define TAIKO_A_CDC_CONN_TX_SB_B9_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_TX_SB_B10_CTL (0x3AC) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_CONN_TX_SB_B10_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_TX_SB_B11_CTL (0x3AD) +#define TAIKO_A_CDC_CONN_TX_SB_B11_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_RX_SB_B1_CTL (0x3AE) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_CONN_RX_SB_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_RX_SB_B2_CTL (0x3AF) +#define TAIKO_A_CDC_CONN_RX_SB_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_CLSH_CTL (0x3B0) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_CONN_CLSH_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_MISC (0x3B1) +#define TAIKO_A_CDC_CONN_MISC__POR (0x01) +#define TAIKO_A_CDC_CONN_MAD (0x3B2) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_CONN_MAD__POR (0x01) +#define TAIKO_A_CDC_MBHC_EN_CTL (0x3C0) +#define TAIKO_A_CDC_MBHC_EN_CTL__POR (0x00) +#define TAIKO_A_CDC_MBHC_FIR_B1_CFG (0x3C1) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_MBHC_FIR_B1_CFG__POR (0x00) +#define TAIKO_A_CDC_MBHC_FIR_B2_CFG (0x3C2) +#define TAIKO_A_CDC_MBHC_FIR_B2_CFG__POR (0x06) +#define TAIKO_A_CDC_MBHC_TIMER_B1_CTL (0x3C3) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_MBHC_TIMER_B1_CTL__POR (0x03) +#define TAIKO_A_CDC_MBHC_TIMER_B2_CTL (0x3C4) +#define TAIKO_A_CDC_MBHC_TIMER_B2_CTL__POR (0x09) +#define TAIKO_A_CDC_MBHC_TIMER_B3_CTL (0x3C5) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_MBHC_TIMER_B3_CTL__POR (0x1E) +#define TAIKO_A_CDC_MBHC_TIMER_B4_CTL (0x3C6) +#define TAIKO_A_CDC_MBHC_TIMER_B4_CTL__POR (0x45) +#define TAIKO_A_CDC_MBHC_TIMER_B5_CTL (0x3C7) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_MBHC_TIMER_B5_CTL__POR (0x04) +#define TAIKO_A_CDC_MBHC_TIMER_B6_CTL (0x3C8) +#define TAIKO_A_CDC_MBHC_TIMER_B6_CTL__POR (0x78) +#define TAIKO_A_CDC_MBHC_B1_STATUS (0x3C9) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_MBHC_B1_STATUS__POR (0x00) +#define TAIKO_A_CDC_MBHC_B2_STATUS (0x3CA) +#define TAIKO_A_CDC_MBHC_B2_STATUS__POR (0x00) +#define TAIKO_A_CDC_MBHC_B3_STATUS (0x3CB) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_MBHC_B3_STATUS__POR (0x00) +#define TAIKO_A_CDC_MBHC_B4_STATUS (0x3CC) +#define TAIKO_A_CDC_MBHC_B4_STATUS__POR (0x00) +#define TAIKO_A_CDC_MBHC_B5_STATUS (0x3CD) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_MBHC_B5_STATUS__POR (0x00) +#define TAIKO_A_CDC_MBHC_B1_CTL (0x3CE) +#define TAIKO_A_CDC_MBHC_B1_CTL__POR (0xC0) +#define TAIKO_A_CDC_MBHC_B2_CTL (0x3CF) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_MBHC_B2_CTL__POR (0x5D) +#define TAIKO_A_CDC_MBHC_VOLT_B1_CTL (0x3D0) +#define TAIKO_A_CDC_MBHC_VOLT_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_MBHC_VOLT_B2_CTL (0x3D1) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_MBHC_VOLT_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_MBHC_VOLT_B3_CTL (0x3D2) +#define TAIKO_A_CDC_MBHC_VOLT_B3_CTL__POR (0x00) +#define TAIKO_A_CDC_MBHC_VOLT_B4_CTL (0x3D3) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_MBHC_VOLT_B4_CTL__POR (0x00) +#define TAIKO_A_CDC_MBHC_VOLT_B5_CTL (0x3D4) +#define TAIKO_A_CDC_MBHC_VOLT_B5_CTL__POR (0x00) +#define TAIKO_A_CDC_MBHC_VOLT_B6_CTL (0x3D5) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_MBHC_VOLT_B6_CTL__POR (0x00) +#define TAIKO_A_CDC_MBHC_VOLT_B7_CTL (0x3D6) +#define TAIKO_A_CDC_MBHC_VOLT_B7_CTL__POR (0xFF) +#define TAIKO_A_CDC_MBHC_VOLT_B8_CTL (0x3D7) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_MBHC_VOLT_B8_CTL__POR (0x07) +#define TAIKO_A_CDC_MBHC_VOLT_B9_CTL (0x3D8) +#define TAIKO_A_CDC_MBHC_VOLT_B9_CTL__POR (0xFF) +#define TAIKO_A_CDC_MBHC_VOLT_B10_CTL (0x3D9) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_MBHC_VOLT_B10_CTL__POR (0x7F) +#define TAIKO_A_CDC_MBHC_VOLT_B11_CTL (0x3DA) +#define TAIKO_A_CDC_MBHC_VOLT_B11_CTL__POR (0x00) +#define TAIKO_A_CDC_MBHC_VOLT_B12_CTL (0x3DB) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_MBHC_VOLT_B12_CTL__POR (0x80) +#define TAIKO_A_CDC_MBHC_CLK_CTL (0x3DC) +#define TAIKO_A_CDC_MBHC_CLK_CTL__POR (0x00) +#define TAIKO_A_CDC_MBHC_INT_CTL (0x3DD) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_MBHC_INT_CTL__POR (0x00) +#define TAIKO_A_CDC_MBHC_DEBUG_CTL (0x3DE) +#define TAIKO_A_CDC_MBHC_DEBUG_CTL__POR (0x00) +#define TAIKO_A_CDC_MBHC_SPARE (0x3DF) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_MBHC_SPARE__POR (0x00) +#define TAIKO_A_CDC_MAD_MAIN_CTL_1 (0x3E0) +#define TAIKO_A_CDC_MAD_MAIN_CTL_1__POR (0x00) +#define TAIKO_A_CDC_MAD_MAIN_CTL_2 (0x3E1) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_MAD_MAIN_CTL_2__POR (0x00) +#define TAIKO_A_CDC_MAD_AUDIO_CTL_1 (0x3E2) +#define TAIKO_A_CDC_MAD_AUDIO_CTL_1__POR (0x00) +#define TAIKO_A_CDC_MAD_AUDIO_CTL_2 (0x3E3) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_MAD_AUDIO_CTL_2__POR (0x00) +#define TAIKO_A_CDC_MAD_AUDIO_CTL_3 (0x3E4) +#define TAIKO_A_CDC_MAD_AUDIO_CTL_3__POR (0x00) +#define TAIKO_A_CDC_MAD_AUDIO_CTL_4 (0x3E5) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_MAD_AUDIO_CTL_4__POR (0x00) +#define TAIKO_A_CDC_MAD_AUDIO_CTL_5 (0x3E6) +#define TAIKO_A_CDC_MAD_AUDIO_CTL_5__POR (0x00) +#define TAIKO_A_CDC_MAD_AUDIO_CTL_6 (0x3E7) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_MAD_AUDIO_CTL_6__POR (0x00) +#define TAIKO_A_CDC_MAD_AUDIO_CTL_7 (0x3E8) +#define TAIKO_A_CDC_MAD_AUDIO_CTL_7__POR (0x00) +#define TAIKO_A_CDC_MAD_AUDIO_CTL_8 (0x3E9) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_MAD_AUDIO_CTL_8__POR (0x00) +#define TAIKO_A_CDC_MAD_AUDIO_IIR_CTL_PTR (0x3EA) +#define TAIKO_A_CDC_MAD_AUDIO_IIR_CTL_PTR__POR (0x00) +#define TAIKO_A_CDC_MAD_AUDIO_IIR_CTL_VAL (0x3EB) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_MAD_AUDIO_IIR_CTL_VAL__POR (0x40) +#define TAIKO_A_CDC_MAD_ULTR_CTL_1 (0x3EC) +#define TAIKO_A_CDC_MAD_ULTR_CTL_1__POR (0x00) +#define TAIKO_A_CDC_MAD_ULTR_CTL_2 (0x3ED) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_MAD_ULTR_CTL_2__POR (0x00) +#define TAIKO_A_CDC_MAD_ULTR_CTL_3 (0x3EE) +#define TAIKO_A_CDC_MAD_ULTR_CTL_3__POR (0x00) +#define TAIKO_A_CDC_MAD_ULTR_CTL_4 (0x3EF) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_MAD_ULTR_CTL_4__POR (0x00) +#define TAIKO_A_CDC_MAD_ULTR_CTL_5 (0x3F0) +#define TAIKO_A_CDC_MAD_ULTR_CTL_5__POR (0x00) +#define TAIKO_A_CDC_MAD_ULTR_CTL_6 (0x3F1) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_MAD_ULTR_CTL_6__POR (0x00) +#define TAIKO_A_CDC_MAD_ULTR_CTL_7 (0x3F2) +#define TAIKO_A_CDC_MAD_ULTR_CTL_7__POR (0x00) +#define TAIKO_A_CDC_MAD_BEACON_CTL_1 (0x3F3) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_MAD_BEACON_CTL_1__POR (0x00) +#define TAIKO_A_CDC_MAD_BEACON_CTL_2 (0x3F4) +#define TAIKO_A_CDC_MAD_BEACON_CTL_2__POR (0x00) +#define TAIKO_A_CDC_MAD_BEACON_CTL_3 (0x3F5) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_MAD_BEACON_CTL_3__POR (0x00) +#define TAIKO_A_CDC_MAD_BEACON_CTL_4 (0x3F6) +#define TAIKO_A_CDC_MAD_BEACON_CTL_4__POR (0x00) +#define TAIKO_A_CDC_MAD_BEACON_CTL_5 (0x3F7) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_MAD_BEACON_CTL_5__POR (0x00) +#define TAIKO_A_CDC_MAD_BEACON_CTL_6 (0x3F8) +#define TAIKO_A_CDC_MAD_BEACON_CTL_6__POR (0x00) +#define TAIKO_A_CDC_MAD_BEACON_CTL_7 (0x3F9) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_MAD_BEACON_CTL_7__POR (0x00) +#define TAIKO_A_CDC_MAD_BEACON_CTL_8 (0x3FA) +#define TAIKO_A_CDC_MAD_BEACON_CTL_8__POR (0x00) +#define TAIKO_A_CDC_MAD_BEACON_IIR_CTL_PTR (0x3FB) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_MAD_BEACON_IIR_CTL_PTR__POR (0x00) +#define TAIKO_A_CDC_MAD_BEACON_IIR_CTL_VAL (0x3FC) +#define TAIKO_A_CDC_MAD_BEACON_IIR_CTL_VAL__POR (0x00) +#define TAIKO_A_CDC_TX_1_GAIN (0x153) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_TX_1_GAIN__POR (0x02) +#define TAIKO_A_CDC_TX_2_GAIN (0x155) +#define TAIKO_A_CDC_TX_2_GAIN__POR (0x02) +#define TAIKO_A_CDC_TX_1_2_ADC_IB (0x156) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_TX_1_2_ADC_IB__POR (0x44) +#define TAIKO_A_CDC_TX_3_GAIN (0x15D) +#define TAIKO_A_CDC_TX_3_GAIN__POR (0x02) +#define TAIKO_A_CDC_TX_4_GAIN (0x15F) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_TX_4_GAIN__POR (0x02) +#define TAIKO_A_CDC_TX_3_4_ADC_IB (0x160) +#define TAIKO_A_CDC_TX_3_4_ADC_IB__POR (0x44) +#define TAIKO_A_CDC_TX_5_GAIN (0x167) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_TX_5_GAIN__POR (0x02) +#define TAIKO_A_CDC_TX_6_GAIN (0x169) +#define TAIKO_A_CDC_TX_6_GAIN__POR (0x02) +#define TAIKO_A_CDC_TX_5_6_ADC_IB (0x16A) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_TX_5_6_ADC_IB__POR (0x44) +#define TAIKO_A_CDC_SPKR_CLIPDET_VAL0 (0x270) +#define TAIKO_A_CDC_SPKR_CLIPDET_VAL0__POR (0x00) +#define TAIKO_A_CDC_SPKR_CLIPDET_VAL1 (0x271) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_SPKR_CLIPDET_VAL1__POR (0x00) +#define TAIKO_A_CDC_SPKR_CLIPDET_VAL2 (0x272) +#define TAIKO_A_CDC_SPKR_CLIPDET_VAL2__POR (0x00) +#define TAIKO_A_CDC_SPKR_CLIPDET_VAL3 (0x273) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_SPKR_CLIPDET_VAL3__POR (0x00) +#define TAIKO_A_CDC_SPKR_CLIPDET_VAL4 (0x274) +#define TAIKO_A_CDC_SPKR_CLIPDET_VAL4__POR (0x00) +#define TAIKO_A_CDC_SPKR_CLIPDET_VAL5 (0x275) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_SPKR_CLIPDET_VAL5__POR (0x00) +#define TAIKO_A_CDC_SPKR_CLIPDET_VAL6 (0x276) +#define TAIKO_A_CDC_SPKR_CLIPDET_VAL6__POR (0x00) +#define TAIKO_A_CDC_SPKR_CLIPDET_VAL7 (0x277) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_SPKR_CLIPDET_VAL7__POR (0x00) +#define TAIKO_A_CDC_VBAT_GAIN_UPD_MON (0x2FA) +#define TAIKO_A_CDC_VBAT_GAIN_UPD_MON__POR (0x00) +#define TAIKO_A_CDC_VBAT_GAIN_MON_VAL (0x2FB) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_VBAT_GAIN_MON_VAL__POR (0x00) +#define TAIKO_A_CDC_PA_RAMP_B1_CTL (0x361) +#define TAIKO_A_CDC_PA_RAMP_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_PA_RAMP_B2_CTL (0x362) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_PA_RAMP_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_PA_RAMP_B3_CTL (0x363) +#define TAIKO_A_CDC_PA_RAMP_B3_CTL__POR (0x00) +#define TAIKO_A_CDC_PA_RAMP_B4_CTL (0x364) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_PA_RAMP_B4_CTL__POR (0x00) +#define TAIKO_A_CDC_SPKR_CLIPDET_B1_CTL (0x365) +#define TAIKO_A_CDC_SPKR_CLIPDET_B1_CTL__POR (0x00) +#define TAIKO_SLIM_PGD_PORT_INT_EN0 (0x30) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_SLIM_PGD_PORT_INT_STATUS_RX_0 (0x34) +#define TAIKO_SLIM_PGD_PORT_INT_STATUS_RX_1 (0x35) +#define TAIKO_SLIM_PGD_PORT_INT_STATUS_TX_0 (0x36) +#define TAIKO_SLIM_PGD_PORT_INT_STATUS_TX_1 (0x37) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_SLIM_PGD_PORT_INT_CLR_RX_0 (0x38) +#define TAIKO_SLIM_PGD_PORT_INT_CLR_RX_1 (0x39) +#define TAIKO_SLIM_PGD_PORT_INT_CLR_TX_0 (0x3A) +#define TAIKO_SLIM_PGD_PORT_INT_CLR_TX_1 (0x3B) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_SLIM_PGD_PORT_INT_RX_SOURCE0 (0x60) +#define TAIKO_SLIM_PGD_PORT_INT_TX_SOURCE0 (0x70) +#define TAIKO_PACKED_REG_SIZE sizeof(u32) +#define TAIKO_CODEC_PACK_ENTRY(reg, mask, val) ((val & 0xff)| ((mask & 0xff) << 8)|((reg & 0xffff) << 16)) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_CODEC_UNPACK_ENTRY(packed, reg, mask, val) do { ((reg) = ((packed >> 16) & (0xffff))); ((mask) = ((packed >> 8) & (0xff))); ((val) = ((packed) & (0xff))); } while (0); +#endif + diff --git a/kernel-headers/linux/mfd/wcd9xxx/wcd9xxx_registers.h b/kernel-headers/linux/mfd/wcd9xxx/wcd9xxx_registers.h new file mode 100644 index 0000000..0c3c33d --- /dev/null +++ b/kernel-headers/linux/mfd/wcd9xxx/wcd9xxx_registers.h @@ -0,0 +1,409 @@ +/**************************************************************************** + **************************************************************************** + *** + *** This header was automatically generated from a Linux kernel header + *** of the same name, to make information necessary for userspace to + *** call into the kernel available to libc. It contains only constants, + *** structures, and macros generated from the original header, and thus, + *** contains no copyrightable information. + *** + *** To edit the content of this header, modify the corresponding + *** source file (e.g. under external/kernel-headers/original/) then + *** run bionic/libc/kernel/tools/update_all.py + *** + *** Any manual change here will be lost the next time this script will + *** be run. You've been warned! + *** + **************************************************************************** + ****************************************************************************/ +#ifndef WCD9XXX_CODEC_DIGITAL_H +#define WCD9XXX_CODEC_DIGITAL_H +#define WCD9XXX_A_CHIP_CTL (0x00) +#define WCD9XXX_A_CHIP_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define WCD9XXX_A_CHIP_STATUS (0x01) +#define WCD9XXX_A_CHIP_STATUS__POR (0x00000000) +#define WCD9XXX_A_CHIP_ID_BYTE_0 (0x04) +#define WCD9XXX_A_CHIP_ID_BYTE_0__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define WCD9XXX_A_CHIP_ID_BYTE_1 (0x05) +#define WCD9XXX_A_CHIP_ID_BYTE_1__POR (0x00000000) +#define WCD9XXX_A_CHIP_ID_BYTE_2 (0x06) +#define WCD9XXX_A_CHIP_ID_BYTE_2__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define WCD9XXX_A_CHIP_ID_BYTE_3 (0x07) +#define WCD9XXX_A_CHIP_ID_BYTE_3__POR (0x00000001) +#define WCD9XXX_A_CHIP_VERSION (0x08) +#define WCD9XXX_A_CHIP_VERSION__POR (0x00000020) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define WCD9XXX_A_SB_VERSION (0x09) +#define WCD9XXX_A_SB_VERSION__POR (0x00000010) +#define WCD9XXX_A_SLAVE_ID_1 (0x0C) +#define WCD9XXX_A_SLAVE_ID_1__POR (0x00000077) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define WCD9XXX_A_SLAVE_ID_2 (0x0D) +#define WCD9XXX_A_SLAVE_ID_2__POR (0x00000066) +#define WCD9XXX_A_SLAVE_ID_3 (0x0E) +#define WCD9XXX_A_SLAVE_ID_3__POR (0x00000055) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define WCD9XXX_A_CDC_CTL (0x80) +#define WCD9XXX_A_CDC_CTL__POR (0x00000000) +#define WCD9XXX_A_LEAKAGE_CTL (0x88) +#define WCD9XXX_A_LEAKAGE_CTL__POR (0x00000004) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define WCD9XXX_A_INTR_MODE (0x90) +#define WCD9XXX_A_INTR_MASK0 (0x94) +#define WCD9XXX_A_INTR_STATUS0 (0x98) +#define WCD9XXX_A_INTR_CLEAR0 (0x9C) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define WCD9XXX_A_INTR_LEVEL0 (0xA0) +#define WCD9XXX_A_INTR_LEVEL1 (0xA1) +#define WCD9XXX_A_INTR_LEVEL2 (0xA2) +#define WCD9XXX_A_RX_HPH_CNP_EN (0x1AB) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define WCD9XXX_A_RX_HPH_CNP_EN__POR (0x80) +#define WCD9XXX_A_RX_HPH_CNP_EN (0x1AB) +#define WCD9XXX_A_RX_HPH_CNP_EN__POR (0x80) +#define WCD9XXX_A_BIAS_CENTRAL_BG_CTL (0x101) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define WCD9XXX_A_BIAS_CENTRAL_BG_CTL__POR (0x50) +#define WCD9XXX_A_CLK_BUFF_EN1 (0x108) +#define WCD9XXX_A_CLK_BUFF_EN1__POR (0x04) +#define WCD9XXX_A_CLK_BUFF_EN2 (0x109) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define WCD9XXX_A_CLK_BUFF_EN2__POR (0x02) +#define WCD9XXX_A_RX_COM_BIAS (0x1A2) +#define WCD9XXX_A_RX_COM_BIAS__POR (0x00) +#define WCD9XXX_A_RC_OSC_FREQ (0x1FA) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define WCD9XXX_A_RC_OSC_FREQ__POR (0x46) +#define WCD9XXX_A_BIAS_OSC_BG_CTL (0x105) +#define WCD9XXX_A_BIAS_OSC_BG_CTL__POR (0x16) +#define WCD9XXX_A_RC_OSC_TEST (0x1FB) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define WCD9XXX_A_RC_OSC_TEST__POR (0x0A) +#define WCD9XXX_A_CDC_CLK_MCLK_CTL (0x311) +#define WCD9XXX_A_CDC_CLK_MCLK_CTL__POR (0x00) +#define WCD9XXX_A_CDC_MBHC_EN_CTL (0x3C0) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define WCD9XXX_A_CDC_MBHC_EN_CTL__POR (0x00) +#define WCD9XXX_A_CDC_MBHC_FIR_B1_CFG (0x3C1) +#define WCD9XXX_A_CDC_MBHC_FIR_B1_CFG__POR (0x00) +#define WCD9XXX_A_CDC_MBHC_FIR_B2_CFG (0x3C2) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define WCD9XXX_A_CDC_MBHC_FIR_B2_CFG__POR (0x06) +#define WCD9XXX_A_CDC_MBHC_TIMER_B1_CTL (0x3C3) +#define WCD9XXX_A_CDC_MBHC_TIMER_B1_CTL__POR (0x03) +#define WCD9XXX_A_CDC_MBHC_TIMER_B2_CTL (0x3C4) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define WCD9XXX_A_CDC_MBHC_TIMER_B2_CTL__POR (0x09) +#define WCD9XXX_A_CDC_MBHC_TIMER_B3_CTL (0x3C5) +#define WCD9XXX_A_CDC_MBHC_TIMER_B3_CTL__POR (0x1E) +#define WCD9XXX_A_CDC_MBHC_TIMER_B4_CTL (0x3C6) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define WCD9XXX_A_CDC_MBHC_TIMER_B4_CTL__POR (0x45) +#define WCD9XXX_A_CDC_MBHC_TIMER_B5_CTL (0x3C7) +#define WCD9XXX_A_CDC_MBHC_TIMER_B5_CTL__POR (0x04) +#define WCD9XXX_A_CDC_MBHC_TIMER_B6_CTL (0x3C8) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define WCD9XXX_A_CDC_MBHC_TIMER_B6_CTL__POR (0x78) +#define WCD9XXX_A_CDC_MBHC_B1_STATUS (0x3C9) +#define WCD9XXX_A_CDC_MBHC_B1_STATUS__POR (0x00) +#define WCD9XXX_A_CDC_MBHC_B2_STATUS (0x3CA) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define WCD9XXX_A_CDC_MBHC_B2_STATUS__POR (0x00) +#define WCD9XXX_A_CDC_MBHC_B3_STATUS (0x3CB) +#define WCD9XXX_A_CDC_MBHC_B3_STATUS__POR (0x00) +#define WCD9XXX_A_CDC_MBHC_B4_STATUS (0x3CC) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define WCD9XXX_A_CDC_MBHC_B4_STATUS__POR (0x00) +#define WCD9XXX_A_CDC_MBHC_B5_STATUS (0x3CD) +#define WCD9XXX_A_CDC_MBHC_B5_STATUS__POR (0x00) +#define WCD9XXX_A_CDC_MBHC_B1_CTL (0x3CE) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define WCD9XXX_A_CDC_MBHC_B1_CTL__POR (0xC0) +#define WCD9XXX_A_CDC_MBHC_B2_CTL (0x3CF) +#define WCD9XXX_A_CDC_MBHC_B2_CTL__POR (0x5D) +#define WCD9XXX_A_CDC_MBHC_VOLT_B1_CTL (0x3D0) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define WCD9XXX_A_CDC_MBHC_VOLT_B1_CTL__POR (0x00) +#define WCD9XXX_A_CDC_MBHC_VOLT_B2_CTL (0x3D1) +#define WCD9XXX_A_CDC_MBHC_VOLT_B2_CTL__POR (0x00) +#define WCD9XXX_A_CDC_MBHC_VOLT_B3_CTL (0x3D2) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define WCD9XXX_A_CDC_MBHC_VOLT_B3_CTL__POR (0x00) +#define WCD9XXX_A_CDC_MBHC_VOLT_B4_CTL (0x3D3) +#define WCD9XXX_A_CDC_MBHC_VOLT_B4_CTL__POR (0x00) +#define WCD9XXX_A_CDC_MBHC_VOLT_B5_CTL (0x3D4) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define WCD9XXX_A_CDC_MBHC_VOLT_B5_CTL__POR (0x00) +#define WCD9XXX_A_CDC_MBHC_VOLT_B6_CTL (0x3D5) +#define WCD9XXX_A_CDC_MBHC_VOLT_B6_CTL__POR (0x00) +#define WCD9XXX_A_CDC_MBHC_VOLT_B7_CTL (0x3D6) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define WCD9XXX_A_CDC_MBHC_VOLT_B7_CTL__POR (0xFF) +#define WCD9XXX_A_CDC_MBHC_VOLT_B8_CTL (0x3D7) +#define WCD9XXX_A_CDC_MBHC_VOLT_B8_CTL__POR (0x07) +#define WCD9XXX_A_CDC_MBHC_VOLT_B9_CTL (0x3D8) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define WCD9XXX_A_CDC_MBHC_VOLT_B9_CTL__POR (0xFF) +#define WCD9XXX_A_CDC_MBHC_VOLT_B10_CTL (0x3D9) +#define WCD9XXX_A_CDC_MBHC_VOLT_B10_CTL__POR (0x7F) +#define WCD9XXX_A_CDC_MBHC_VOLT_B11_CTL (0x3DA) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define WCD9XXX_A_CDC_MBHC_VOLT_B11_CTL__POR (0x00) +#define WCD9XXX_A_CDC_MBHC_VOLT_B12_CTL (0x3DB) +#define WCD9XXX_A_CDC_MBHC_VOLT_B12_CTL__POR (0x80) +#define WCD9XXX_A_CDC_MBHC_CLK_CTL (0x3DC) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define WCD9XXX_A_CDC_MBHC_CLK_CTL__POR (0x00) +#define WCD9XXX_A_CDC_MBHC_INT_CTL (0x3DD) +#define WCD9XXX_A_CDC_MBHC_INT_CTL__POR (0x00) +#define WCD9XXX_A_CDC_MBHC_DEBUG_CTL (0x3DE) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define WCD9XXX_A_CDC_MBHC_DEBUG_CTL__POR (0x00) +#define WCD9XXX_A_CDC_MBHC_SPARE (0x3DF) +#define WCD9XXX_A_CDC_MBHC_SPARE__POR (0x00) +#define WCD9XXX_A_MBHC_SCALING_MUX_1 (0x14E) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define WCD9XXX_A_MBHC_SCALING_MUX_1__POR (0x00) +#define WCD9XXX_A_RX_HPH_OCP_CTL (0x1AA) +#define WCD9XXX_A_RX_HPH_OCP_CTL__POR (0x68) +#define WCD9XXX_A_MICB_1_CTL (0x12B) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define WCD9XXX_A_MICB_1_CTL__POR (0x16) +#define WCD9XXX_A_MICB_1_INT_RBIAS (0x12C) +#define WCD9XXX_A_MICB_1_INT_RBIAS__POR (0x24) +#define WCD9XXX_A_MICB_1_MBHC (0x12D) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define WCD9XXX_A_MICB_1_MBHC__POR (0x01) +#define WCD9XXX_A_MICB_CFILT_2_CTL (0x12E) +#define WCD9XXX_A_MICB_CFILT_2_CTL__POR (0x40) +#define WCD9XXX_A_MICB_CFILT_2_VAL (0x12F) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define WCD9XXX_A_MICB_CFILT_2_VAL__POR (0x80) +#define WCD9XXX_A_MICB_CFILT_2_PRECHRG (0x130) +#define WCD9XXX_A_MICB_CFILT_2_PRECHRG__POR (0x38) +#define WCD9XXX_A_MICB_2_CTL (0x131) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define WCD9XXX_A_MICB_2_CTL__POR (0x16) +#define WCD9XXX_A_MICB_2_INT_RBIAS (0x132) +#define WCD9XXX_A_MICB_2_INT_RBIAS__POR (0x24) +#define WCD9XXX_A_MICB_2_MBHC (0x133) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define WCD9XXX_A_MICB_2_MBHC__POR (0x02) +#define WCD9XXX_A_MICB_CFILT_3_CTL (0x134) +#define WCD9XXX_A_MICB_CFILT_3_CTL__POR (0x40) +#define WCD9XXX_A_MICB_CFILT_3_VAL (0x135) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define WCD9XXX_A_MICB_CFILT_3_VAL__POR (0x80) +#define WCD9XXX_A_MICB_CFILT_3_PRECHRG (0x136) +#define WCD9XXX_A_MICB_CFILT_3_PRECHRG__POR (0x38) +#define WCD9XXX_A_MICB_3_CTL (0x137) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define WCD9XXX_A_MICB_3_CTL__POR (0x16) +#define WCD9XXX_A_MICB_3_INT_RBIAS (0x138) +#define WCD9XXX_A_MICB_3_INT_RBIAS__POR (0x24) +#define WCD9XXX_A_MICB_3_MBHC (0x139) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define WCD9XXX_A_MICB_3_MBHC__POR (0x00) +#define WCD9XXX_A_MICB_4_CTL (0x13D) +#define WCD9XXX_A_MICB_4_CTL__POR (0x16) +#define WCD9XXX_A_MICB_4_INT_RBIAS (0x13E) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define WCD9XXX_A_MICB_4_INT_RBIAS__POR (0x24) +#define WCD9XXX_A_MICB_4_MBHC (0x13F) +#define WCD9XXX_A_MICB_4_MBHC__POR (0x01) +#define WCD9XXX_A_MICB_CFILT_1_VAL (0x129) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define WCD9XXX_A_MICB_CFILT_1_VAL__POR (0x80) +#define WCD9XXX_A_RX_HPH_L_STATUS (0x1B3) +#define WCD9XXX_A_RX_HPH_L_STATUS__POR (0x00) +#define WCD9XXX_A_MBHC_HPH (0x1FE) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define WCD9XXX_A_MBHC_HPH__POR (0x44) +#define WCD9XXX_A_RX_HPH_CNP_WG_TIME (0x1AD) +#define WCD9XXX_A_RX_HPH_CNP_WG_TIME__POR (0x2A) +#define WCD9XXX_A_RX_HPH_R_DAC_CTL (0x1B7) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define WCD9XXX_A_RX_HPH_R_DAC_CTL__POR (0x00) +#define WCD9XXX_A_RX_HPH_L_DAC_CTL (0x1B1) +#define WCD9XXX_A_RX_HPH_L_DAC_CTL__POR (0x00) +#define WCD9XXX_A_TX_7_MBHC_EN (0x171) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define WCD9XXX_A_TX_7_MBHC_EN__POR (0x0C) +#define WCD9XXX_A_PIN_CTL_OE0 (0x010) +#define WCD9XXX_A_PIN_CTL_OE0__POR (0x00) +#define WCD9XXX_A_PIN_CTL_OE1 (0x011) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define WCD9XXX_A_PIN_CTL_OE1__POR (0x00) +#define WCD9XXX_A_MICB_CFILT_1_CTL (0x128) +#define WCD9XXX_A_LDO_H_MODE_1 (0x110) +#define WCD9XXX_A_LDO_H_MODE_1__POR (0x65) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define WCD9XXX_A_MICB_CFILT_1_CTL__POR (0x40) +#define WCD9XXX_A_TX_7_MBHC_TEST_CTL (0x174) +#define WCD9XXX_A_TX_7_MBHC_TEST_CTL__POR (0x38) +#define WCD9XXX_A_MBHC_SCALING_MUX_2 (0x14F) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define WCD9XXX_A_MBHC_SCALING_MUX_2__POR (0x80) +#define WCD9XXX_A_TX_COM_BIAS (0x14C) +#define WCD9XXX_A_TX_COM_BIAS__POR (0xF0) +#define WCD9XXX_A_MBHC_INSERT_DETECT (0x14A) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define WCD9XXX_A_MBHC_INSERT_DETECT__POR (0x00) +#define WCD9XXX_A_MBHC_INSERT_DET_STATUS (0x14B) +#define WCD9XXX_A_MBHC_INSERT_DET_STATUS__POR (0x00) +#define WCD9XXX_A_MAD_ANA_CTRL (0x150) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define WCD9XXX_A_MAD_ANA_CTRL__POR (0xF1) +#define WCD9XXX_A_CDC_CLK_OTHR_CTL (0x30C) +#define WCD9XXX_A_CDC_CLK_OTHR_CTL__POR (0x00) +#define WCD9XXX_A_BUCK_MODE_1 (0x181) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define WCD9XXX_A_BUCK_MODE_1__POR (0x21) +#define WCD9XXX_A_BUCK_MODE_2 (0x182) +#define WCD9XXX_A_BUCK_MODE_2__POR (0xFF) +#define WCD9XXX_A_BUCK_MODE_3 (0x183) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define WCD9XXX_A_BUCK_MODE_3__POR (0xCC) +#define WCD9XXX_A_BUCK_MODE_4 (0x184) +#define WCD9XXX_A_BUCK_MODE_4__POR (0x3A) +#define WCD9XXX_A_BUCK_MODE_5 (0x185) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define WCD9XXX_A_BUCK_MODE_5__POR (0x00) +#define WCD9XXX_A_BUCK_CTRL_VCL_1 (0x186) +#define WCD9XXX_A_BUCK_CTRL_VCL_1__POR (0x48) +#define WCD9XXX_A_BUCK_CTRL_VCL_2 (0x187) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define WCD9XXX_A_BUCK_CTRL_VCL_2__POR (0xA3) +#define WCD9XXX_A_BUCK_CTRL_VCL_3 (0x188) +#define WCD9XXX_A_BUCK_CTRL_VCL_3__POR (0x82) +#define WCD9XXX_A_BUCK_CTRL_CCL_1 (0x189) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define WCD9XXX_A_BUCK_CTRL_CCL_1__POR (0xAB) +#define WCD9XXX_A_BUCK_CTRL_CCL_2 (0x18A) +#define WCD9XXX_A_BUCK_CTRL_CCL_2__POR (0xDC) +#define WCD9XXX_A_BUCK_CTRL_CCL_3 (0x18B) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define WCD9XXX_A_BUCK_CTRL_CCL_3__POR (0x6A) +#define WCD9XXX_A_BUCK_CTRL_CCL_4 (0x18C) +#define WCD9XXX_A_BUCK_CTRL_CCL_4__POR (0x58) +#define WCD9XXX_A_BUCK_CTRL_PWM_DRVR_1 (0x18D) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define WCD9XXX_A_BUCK_CTRL_PWM_DRVR_1__POR (0x50) +#define WCD9XXX_A_BUCK_CTRL_PWM_DRVR_2 (0x18E) +#define WCD9XXX_A_BUCK_CTRL_PWM_DRVR_2__POR (0x64) +#define WCD9XXX_A_BUCK_CTRL_PWM_DRVR_3 (0x18F) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define WCD9XXX_A_BUCK_CTRL_PWM_DRVR_3__POR (0x77) +#define WCD9XXX_A_BUCK_TMUX_A_D (0x190) +#define WCD9XXX_A_BUCK_TMUX_A_D__POR (0x00) +#define WCD9XXX_A_NCP_EN (0x192) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define WCD9XXX_A_NCP_EN__POR (0xFE) +#define WCD9XXX_A_NCP_STATIC (0x194) +#define WCD9XXX_A_NCP_STATIC__POR (0x28) +#define WCD9XXX_A_NCP_BUCKREF (0x191) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define WCD9XXX_A_NCP_BUCKREF__POR (0x00) +#define WCD9XXX_A_CDC_CLSH_B1_CTL (0x320) +#define WCD9XXX_A_CDC_CLSH_B1_CTL__POR (0xE4) +#define WCD9XXX_A_CDC_CLSH_B2_CTL (0x321) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define WCD9XXX_A_CDC_CLSH_B2_CTL__POR (0x00) +#define WCD9XXX_A_CDC_CLSH_B3_CTL (0x322) +#define WCD9XXX_A_CDC_CLSH_B3_CTL__POR (0x00) +#define WCD9XXX_A_CDC_CLSH_BUCK_NCP_VARS (0x323) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define WCD9XXX_A_CDC_CLSH_BUCK_NCP_VARS__POR (0x00) +#define WCD9XXX_A_CDC_CLSH_IDLE_HPH_THSD (0x324) +#define WCD9XXX_A_CDC_CLSH_IDLE_HPH_THSD__POR (0x12) +#define WCD9XXX_A_CDC_CLSH_IDLE_EAR_THSD (0x325) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define WCD9XXX_A_CDC_CLSH_IDLE_EAR_THSD__POR (0x0C) +#define WCD9XXX_A_CDC_CLSH_FCLKONLY_HPH_THSD (0x326) +#define WCD9XXX_A_CDC_CLSH_FCLKONLY_HPH_THSD__POR (0x18) +#define WCD9XXX_A_CDC_CLSH_FCLKONLY_EAR_THSD (0x327) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define WCD9XXX_A_CDC_CLSH_FCLKONLY_EAR_THSD__POR (0x23) +#define WCD9XXX_A_CDC_CLSH_K_ADDR (0x328) +#define WCD9XXX_A_CDC_CLSH_K_ADDR__POR (0x00) +#define WCD9XXX_A_CDC_CLSH_K_DATA (0x329) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define WCD9XXX_A_CDC_CLSH_K_DATA__POR (0xA4) +#define WCD9XXX_A_CDC_CLSH_I_PA_FACT_HPH_L (0x32A) +#define WCD9XXX_A_CDC_CLSH_I_PA_FACT_HPH_L__POR (0xD7) +#define WCD9XXX_A_CDC_CLSH_I_PA_FACT_HPH_U (0x32B) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define WCD9XXX_A_CDC_CLSH_I_PA_FACT_HPH_U__POR (0x05) +#define WCD9XXX_A_CDC_CLSH_I_PA_FACT_EAR_L (0x32C) +#define WCD9XXX_A_CDC_CLSH_I_PA_FACT_EAR_L__POR (0x60) +#define WCD9XXX_A_CDC_CLSH_I_PA_FACT_EAR_U (0x32D) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define WCD9XXX_A_CDC_CLSH_I_PA_FACT_EAR_U__POR (0x09) +#define WCD9XXX_A_CDC_CLSH_V_PA_HD_EAR (0x32E) +#define WCD9XXX_A_CDC_CLSH_V_PA_HD_EAR__POR (0x00) +#define WCD9XXX_A_CDC_CLSH_V_PA_HD_HPH (0x32F) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define WCD9XXX_A_CDC_CLSH_V_PA_HD_HPH__POR (0x00) +#define WCD9XXX_A_CDC_CLSH_V_PA_MIN_EAR (0x330) +#define WCD9XXX_A_CDC_CLSH_V_PA_MIN_EAR__POR (0x00) +#define WCD9XXX_A_CDC_CLSH_V_PA_MIN_HPH (0x331) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define WCD9XXX_A_CDC_CLSH_V_PA_MIN_HPH__POR (0x00) +#define WCD9XXX_A_CDC_RX1_B6_CTL (0x2B5) +#define WCD9XXX_A_CDC_RX1_B6_CTL__POR (0x80) +#define WCD9XXX_A_CDC_RX2_B6_CTL (0x2BD) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define WCD9XXX_A_CDC_RX2_B6_CTL__POR (0x80) +#define WCD9XXX_A_RX_HPH_L_GAIN (0x1AE) +#define WCD9XXX_A_RX_HPH_L_GAIN__POR (0x00) +#define WCD9XXX_A_RX_HPH_R_GAIN (0x1B4) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define WCD9XXX_A_RX_HPH_R_GAIN__POR (0x00) +#define WCD9XXX_A_RX_HPH_CHOP_CTL (0x1A5) +#define WCD9XXX_A_RX_HPH_CHOP_CTL__POR (0xB4) +#define WCD9XXX_A_RX_HPH_BIAS_PA (0x1A6) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define WCD9XXX_A_RX_HPH_BIAS_PA__POR (0x7A) +#define WCD9XXX_A_RX_HPH_L_TEST (0x1AF) +#define WCD9XXX_A_RX_HPH_L_TEST__POR (0x00) +#define WCD9XXX_A_RX_HPH_R_TEST (0x1B5) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define WCD9XXX_A_RX_HPH_R_TEST__POR (0x00) +#define WCD9XXX_A_CDC_CLK_RX_B1_CTL (0x30F) +#define WCD9XXX_A_CDC_CLK_RX_B1_CTL__POR (0x00) +#define WCD9XXX_A_NCP_CLK (0x193) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define WCD9XXX_A_NCP_CLK__POR (0x94) +#define WCD9XXX_A_RX_HPH_BIAS_WG_OCP (0x1A9) +#define WCD9XXX_A_RX_HPH_BIAS_WG_OCP__POR (0x2A) +#define WCD9XXX_A_RX_HPH_CNP_WG_CTL (0x1AC) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define WCD9XXX_A_RX_HPH_CNP_WG_CTL__POR (0xDE) +#define WCD9XXX_A_RX_HPH_L_PA_CTL (0x1B0) +#define WCD9XXX_A_RX_HPH_L_PA_CTL__POR (0x42) +#define WCD9XXX_A_RX_HPH_R_PA_CTL (0x1B6) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define WCD9XXX_A_RX_HPH_R_PA_CTL__POR (0x42) +#define WCD9XXX_A_CDC_CONN_RX2_B1_CTL (0x383) +#define WCD9XXX_A_CDC_CONN_RX2_B1_CTL__POR (0x00) +#define WCD9XXX_A_CDC_PA_RAMP_B1_CTL (0x361) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define WCD9XXX_A_CDC_PA_RAMP_B1_CTL__POR (0x00) +#define WCD9XXX_A_CDC_PA_RAMP_B2_CTL (0x362) +#define WCD9XXX_A_CDC_PA_RAMP_B2_CTL__POR (0x00) +#define WCD9XXX_A_CDC_PA_RAMP_B3_CTL (0x363) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define WCD9XXX_A_CDC_PA_RAMP_B3_CTL__POR (0x00) +#define WCD9XXX_A_CDC_PA_RAMP_B4_CTL (0x364) +#define WCD9XXX_A_CDC_PA_RAMP_B4_CTL__POR (0x00) +#define WCD9330_A_LEAKAGE_CTL (0x03C) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define WCD9330_A_LEAKAGE_CTL__POR (0x04) +#define WCD9330_A_CDC_CTL (0x034) +#define WCD9330_A_CDC_CTL__POR (0x00) +#endif +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + diff --git a/kernel-headers/linux/msm_adsp.h b/kernel-headers/linux/msm_adsp.h new file mode 100644 index 0000000..af803d0 --- /dev/null +++ b/kernel-headers/linux/msm_adsp.h @@ -0,0 +1,56 @@ +/**************************************************************************** + **************************************************************************** + *** + *** This header was automatically generated from a Linux kernel header + *** of the same name, to make information necessary for userspace to + *** call into the kernel available to libc. It contains only constants, + *** structures, and macros generated from the original header, and thus, + *** contains no copyrightable information. + *** + *** To edit the content of this header, modify the corresponding + *** source file (e.g. under external/kernel-headers/original/) then + *** run bionic/libc/kernel/tools/update_all.py + *** + *** Any manual change here will be lost the next time this script will + *** be run. You've been warned! + *** + **************************************************************************** + ****************************************************************************/ +#ifndef _UAPI_LINUX_MSM_ADSP_H +#define _UAPI_LINUX_MSM_ADSP_H +#include <linux/types.h> +#include <linux/ioctl.h> +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define ADSP_IOCTL_MAGIC 'q' +struct adsp_command_t { + uint16_t queue; + uint32_t len; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint8_t *data; +}; +struct adsp_event_t { + uint16_t type; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t timeout_ms; + uint16_t msg_id; + uint16_t flags; + uint32_t len; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint8_t *data; +}; +#define ADSP_IOCTL_ENABLE _IOR(ADSP_IOCTL_MAGIC, 1, unsigned) +#define ADSP_IOCTL_DISABLE _IOR(ADSP_IOCTL_MAGIC, 2, unsigned) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define ADSP_IOCTL_DISABLE_ACK _IOR(ADSP_IOCTL_MAGIC, 3, unsigned) +#define ADSP_IOCTL_WRITE_COMMAND _IOR(ADSP_IOCTL_MAGIC, 4, struct adsp_command_t *) +#define ADSP_IOCTL_GET_EVENT _IOWR(ADSP_IOCTL_MAGIC, 5, struct adsp_event_data_t *) +#define ADSP_IOCTL_SET_CLKRATE _IOR(ADSP_IOCTL_MAGIC, 6, unsigned) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define ADSP_IOCTL_DISABLE_EVENT_RSP _IOR(ADSP_IOCTL_MAGIC, 10, unsigned) +#define ADSP_IOCTL_REGISTER_PMEM _IOW(ADSP_IOCTL_MAGIC, 13, unsigned) +#define ADSP_IOCTL_UNREGISTER_PMEM _IOW(ADSP_IOCTL_MAGIC, 14, unsigned) +#define ADSP_IOCTL_ABORT_EVENT_READ _IOW(ADSP_IOCTL_MAGIC, 15, unsigned) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define ADSP_IOCTL_LINK_TASK _IOW(ADSP_IOCTL_MAGIC, 16, unsigned) +#endif + diff --git a/kernel-headers/linux/msm_audio.h b/kernel-headers/linux/msm_audio.h new file mode 100644 index 0000000..9c81dbe --- /dev/null +++ b/kernel-headers/linux/msm_audio.h @@ -0,0 +1,422 @@ +/**************************************************************************** + **************************************************************************** + *** + *** This header was automatically generated from a Linux kernel header + *** of the same name, to make information necessary for userspace to + *** call into the kernel available to libc. It contains only constants, + *** structures, and macros generated from the original header, and thus, + *** contains no copyrightable information. + *** + *** To edit the content of this header, modify the corresponding + *** source file (e.g. under external/kernel-headers/original/) then + *** run bionic/libc/kernel/tools/update_all.py + *** + *** Any manual change here will be lost the next time this script will + *** be run. You've been warned! + *** + **************************************************************************** + ****************************************************************************/ +#ifndef _UAPI_LINUX_MSM_AUDIO_H +#define _UAPI_LINUX_MSM_AUDIO_H +#include <linux/types.h> +#include <linux/ioctl.h> +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define AUDIO_IOCTL_MAGIC 'a' +#define AUDIO_START _IOW(AUDIO_IOCTL_MAGIC, 0, unsigned) +#define AUDIO_STOP _IOW(AUDIO_IOCTL_MAGIC, 1, unsigned) +#define AUDIO_FLUSH _IOW(AUDIO_IOCTL_MAGIC, 2, unsigned) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define AUDIO_GET_CONFIG _IOR(AUDIO_IOCTL_MAGIC, 3, struct msm_audio_config) +#define AUDIO_SET_CONFIG _IOW(AUDIO_IOCTL_MAGIC, 4, struct msm_audio_config) +#define AUDIO_GET_STATS _IOR(AUDIO_IOCTL_MAGIC, 5, struct msm_audio_stats) +#define AUDIO_ENABLE_AUDPP _IOW(AUDIO_IOCTL_MAGIC, 6, unsigned) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define AUDIO_SET_ADRC _IOW(AUDIO_IOCTL_MAGIC, 7, unsigned) +#define AUDIO_SET_EQ _IOW(AUDIO_IOCTL_MAGIC, 8, unsigned) +#define AUDIO_SET_RX_IIR _IOW(AUDIO_IOCTL_MAGIC, 9, unsigned) +#define AUDIO_SET_VOLUME _IOW(AUDIO_IOCTL_MAGIC, 10, unsigned) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define AUDIO_PAUSE _IOW(AUDIO_IOCTL_MAGIC, 11, unsigned) +#define AUDIO_PLAY_DTMF _IOW(AUDIO_IOCTL_MAGIC, 12, unsigned) +#define AUDIO_GET_EVENT _IOR(AUDIO_IOCTL_MAGIC, 13, struct msm_audio_event) +#define AUDIO_ABORT_GET_EVENT _IOW(AUDIO_IOCTL_MAGIC, 14, unsigned) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define AUDIO_REGISTER_PMEM _IOW(AUDIO_IOCTL_MAGIC, 15, unsigned) +#define AUDIO_DEREGISTER_PMEM _IOW(AUDIO_IOCTL_MAGIC, 16, unsigned) +#define AUDIO_ASYNC_WRITE _IOW(AUDIO_IOCTL_MAGIC, 17, struct msm_audio_aio_buf) +#define AUDIO_ASYNC_READ _IOW(AUDIO_IOCTL_MAGIC, 18, struct msm_audio_aio_buf) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define AUDIO_SET_INCALL _IOW(AUDIO_IOCTL_MAGIC, 19, struct msm_voicerec_mode) +#define AUDIO_GET_NUM_SND_DEVICE _IOR(AUDIO_IOCTL_MAGIC, 20, unsigned) +#define AUDIO_GET_SND_DEVICES _IOWR(AUDIO_IOCTL_MAGIC, 21, struct msm_snd_device_list) +#define AUDIO_ENABLE_SND_DEVICE _IOW(AUDIO_IOCTL_MAGIC, 22, unsigned) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define AUDIO_DISABLE_SND_DEVICE _IOW(AUDIO_IOCTL_MAGIC, 23, unsigned) +#define AUDIO_ROUTE_STREAM _IOW(AUDIO_IOCTL_MAGIC, 24, struct msm_audio_route_config) +#define AUDIO_GET_PCM_CONFIG _IOR(AUDIO_IOCTL_MAGIC, 30, unsigned) +#define AUDIO_SET_PCM_CONFIG _IOW(AUDIO_IOCTL_MAGIC, 31, unsigned) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define AUDIO_SWITCH_DEVICE _IOW(AUDIO_IOCTL_MAGIC, 32, unsigned) +#define AUDIO_SET_MUTE _IOW(AUDIO_IOCTL_MAGIC, 33, unsigned) +#define AUDIO_UPDATE_ACDB _IOW(AUDIO_IOCTL_MAGIC, 34, unsigned) +#define AUDIO_START_VOICE _IOW(AUDIO_IOCTL_MAGIC, 35, unsigned) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define AUDIO_STOP_VOICE _IOW(AUDIO_IOCTL_MAGIC, 36, unsigned) +#define AUDIO_REINIT_ACDB _IOW(AUDIO_IOCTL_MAGIC, 39, unsigned) +#define AUDIO_OUTPORT_FLUSH _IOW(AUDIO_IOCTL_MAGIC, 40, unsigned short) +#define AUDIO_SET_ERR_THRESHOLD_VALUE _IOW(AUDIO_IOCTL_MAGIC, 41, unsigned short) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define AUDIO_GET_BITSTREAM_ERROR_INFO _IOR(AUDIO_IOCTL_MAGIC, 42, struct msm_audio_bitstream_error_info) +#define AUDIO_SET_SRS_TRUMEDIA_PARAM _IOW(AUDIO_IOCTL_MAGIC, 43, unsigned) +#define AUDIO_SET_STREAM_CONFIG _IOW(AUDIO_IOCTL_MAGIC, 80, struct msm_audio_stream_config) +#define AUDIO_GET_STREAM_CONFIG _IOR(AUDIO_IOCTL_MAGIC, 81, struct msm_audio_stream_config) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define AUDIO_GET_SESSION_ID _IOR(AUDIO_IOCTL_MAGIC, 82, unsigned short) +#define AUDIO_GET_STREAM_INFO _IOR(AUDIO_IOCTL_MAGIC, 83, struct msm_audio_bitstream_info) +#define AUDIO_SET_PAN _IOW(AUDIO_IOCTL_MAGIC, 84, unsigned) +#define AUDIO_SET_QCONCERT_PLUS _IOW(AUDIO_IOCTL_MAGIC, 85, unsigned) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define AUDIO_SET_MBADRC _IOW(AUDIO_IOCTL_MAGIC, 86, unsigned) +#define AUDIO_SET_VOLUME_PATH _IOW(AUDIO_IOCTL_MAGIC, 87, struct msm_vol_info) +#define AUDIO_SET_MAX_VOL_ALL _IOW(AUDIO_IOCTL_MAGIC, 88, unsigned) +#define AUDIO_ENABLE_AUDPRE _IOW(AUDIO_IOCTL_MAGIC, 89, unsigned) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define AUDIO_SET_AGC _IOW(AUDIO_IOCTL_MAGIC, 90, unsigned) +#define AUDIO_SET_NS _IOW(AUDIO_IOCTL_MAGIC, 91, unsigned) +#define AUDIO_SET_TX_IIR _IOW(AUDIO_IOCTL_MAGIC, 92, unsigned) +#define AUDIO_GET_BUF_CFG _IOW(AUDIO_IOCTL_MAGIC, 93, struct msm_audio_buf_cfg) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define AUDIO_SET_BUF_CFG _IOW(AUDIO_IOCTL_MAGIC, 94, struct msm_audio_buf_cfg) +#define AUDIO_SET_ACDB_BLK _IOW(AUDIO_IOCTL_MAGIC, 95, struct msm_acdb_cmd_device) +#define AUDIO_GET_ACDB_BLK _IOW(AUDIO_IOCTL_MAGIC, 96, struct msm_acdb_cmd_device) +#define AUDIO_REGISTER_ION _IOW(AUDIO_IOCTL_MAGIC, 97, struct msm_audio_ion_info) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define AUDIO_DEREGISTER_ION _IOW(AUDIO_IOCTL_MAGIC, 98, struct msm_audio_ion_info) +#define AUDIO_SET_EFFECTS_CONFIG _IOW(AUDIO_IOCTL_MAGIC, 99, struct msm_hwacc_effects_config) +#define AUDIO_EFFECTS_SET_BUF_LEN _IOW(AUDIO_IOCTL_MAGIC, 100, struct msm_hwacc_buf_cfg) +#define AUDIO_EFFECTS_GET_BUF_AVAIL _IOW(AUDIO_IOCTL_MAGIC, 101, struct msm_hwacc_buf_avail) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define AUDIO_EFFECTS_WRITE _IOW(AUDIO_IOCTL_MAGIC, 102, void *) +#define AUDIO_EFFECTS_READ _IOWR(AUDIO_IOCTL_MAGIC, 103, void *) +#define AUDIO_EFFECTS_SET_PP_PARAMS _IOW(AUDIO_IOCTL_MAGIC, 104, void *) +#define AUDIO_MAX_COMMON_IOCTL_NUM 105 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define HANDSET_MIC 0x01 +#define HANDSET_SPKR 0x02 +#define HEADSET_MIC 0x03 +#define HEADSET_SPKR_MONO 0x04 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define HEADSET_SPKR_STEREO 0x05 +#define SPKR_PHONE_MIC 0x06 +#define SPKR_PHONE_MONO 0x07 +#define SPKR_PHONE_STEREO 0x08 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define BT_SCO_MIC 0x09 +#define BT_SCO_SPKR 0x0A +#define BT_A2DP_SPKR 0x0B +#define TTY_HEADSET_MIC 0x0C +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TTY_HEADSET_SPKR 0x0D +#define DEFAULT_TX 0x0E +#define DEFAULT_RX 0x0F +#define BT_A2DP_TX 0x10 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define HEADSET_MONO_PLUS_SPKR_MONO_RX 0x11 +#define HEADSET_MONO_PLUS_SPKR_STEREO_RX 0x12 +#define HEADSET_STEREO_PLUS_SPKR_MONO_RX 0x13 +#define HEADSET_STEREO_PLUS_SPKR_STEREO_RX 0x14 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define I2S_RX 0x20 +#define I2S_TX 0x21 +#define ADRC_ENABLE 0x0001 +#define EQUALIZER_ENABLE 0x0002 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define IIR_ENABLE 0x0004 +#define QCONCERT_PLUS_ENABLE 0x0008 +#define MBADRC_ENABLE 0x0010 +#define SRS_ENABLE 0x0020 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SRS_DISABLE 0x0040 +#define AGC_ENABLE 0x0001 +#define NS_ENABLE 0x0002 +#define TX_IIR_ENABLE 0x0004 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define FLUENCE_ENABLE 0x0008 +#define VOC_REC_UPLINK 0x00 +#define VOC_REC_DOWNLINK 0x01 +#define VOC_REC_BOTH 0x02 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct msm_audio_config { + uint32_t buffer_size; + uint32_t buffer_count; + uint32_t channel_count; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t sample_rate; + uint32_t type; + uint32_t meta_field; + uint32_t bits; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t unused[3]; +}; +struct msm_audio_stream_config { + uint32_t buffer_size; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t buffer_count; +}; +struct msm_audio_buf_cfg{ + uint32_t meta_info_enable; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t frames_per_buf; +}; +struct msm_audio_stats { + uint32_t byte_count; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t sample_count; + uint32_t unused[2]; +}; +struct msm_audio_ion_info { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + int fd; + void *vaddr; +}; +struct msm_audio_pmem_info { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + int fd; + void *vaddr; +}; +struct msm_audio_aio_buf { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + void *buf_addr; + uint32_t buf_len; + uint32_t data_len; + void *private_data; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned short mfield_sz; +}; +#define SND_IOCTL_MAGIC 's' +#define SND_MUTE_UNMUTED 0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SND_MUTE_MUTED 1 +struct msm_mute_info { + uint32_t mute; + uint32_t path; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +struct msm_vol_info { + uint32_t vol; + uint32_t path; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +struct msm_voicerec_mode { + uint32_t rec_mode; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct msm_snd_device_config { + uint32_t device; + uint32_t ear_mute; + uint32_t mic_mute; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +#define SND_SET_DEVICE _IOW(SND_IOCTL_MAGIC, 2, struct msm_device_config *) +enum cad_device_path_type { + CAD_DEVICE_PATH_RX, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + CAD_DEVICE_PATH_TX, + CAD_DEVICE_PATH_RX_TX, + CAD_DEVICE_PATH_LB, + CAD_DEVICE_PATH_MAX +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +struct cad_devices_type { + uint32_t rx_device; + uint32_t tx_device; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + enum cad_device_path_type pathtype; +}; +struct msm_cad_device_config { + struct cad_devices_type device; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t ear_mute; + uint32_t mic_mute; +}; +#define CAD_SET_DEVICE _IOW(SND_IOCTL_MAGIC, 2, struct msm_cad_device_config *) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SND_METHOD_VOICE 0 +#define SND_METHOD_MIDI 4 +struct msm_snd_volume_config { + uint32_t device; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t method; + uint32_t volume; +}; +#define SND_SET_VOLUME _IOW(SND_IOCTL_MAGIC, 3, struct msm_snd_volume_config *) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct msm_cad_volume_config { + struct cad_devices_type device; + uint32_t method; + uint32_t volume; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +#define CAD_SET_VOLUME _IOW(SND_IOCTL_MAGIC, 3, struct msm_cad_volume_config *) +#define SND_GET_NUM_ENDPOINTS _IOR(SND_IOCTL_MAGIC, 4, unsigned *) +struct msm_snd_endpoint { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + int id; + char name[64]; +}; +#define SND_GET_ENDPOINT _IOWR(SND_IOCTL_MAGIC, 5, struct msm_snd_endpoint *) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SND_AVC_CTL _IOW(SND_IOCTL_MAGIC, 6, unsigned *) +#define SND_AGC_CTL _IOW(SND_IOCTL_MAGIC, 7, unsigned *) +#define CAD_GET_NUM_ENDPOINTS _IOR(SND_IOCTL_MAGIC, 4, unsigned *) +struct msm_cad_endpoint { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + int id; + char name[64]; +}; +#define CAD_GET_ENDPOINT _IOWR(SND_IOCTL_MAGIC, 5, struct msm_cad_endpoint *) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct msm_audio_pcm_config { + uint32_t pcm_feedback; + uint32_t buffer_count; + uint32_t buffer_size; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +#define AUDIO_EVENT_SUSPEND 0 +#define AUDIO_EVENT_RESUME 1 +#define AUDIO_EVENT_WRITE_DONE 2 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define AUDIO_EVENT_READ_DONE 3 +#define AUDIO_EVENT_STREAM_INFO 4 +#define AUDIO_EVENT_BITSTREAM_ERROR_INFO 5 +#define AUDIO_CODEC_TYPE_MP3 0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define AUDIO_CODEC_TYPE_AAC 1 +struct msm_audio_bitstream_info { + uint32_t codec_type; + uint32_t chan_info; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t sample_rate; + uint32_t bit_stream_info; + uint32_t bit_rate; + uint32_t unused[3]; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +struct msm_audio_bitstream_error_info { + uint32_t dec_id; + uint32_t err_msg_indicator; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t err_type; +}; +union msm_audio_event_payload { + struct msm_audio_aio_buf aio_buf; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + struct msm_audio_bitstream_info stream_info; + struct msm_audio_bitstream_error_info error_info; + int reserved; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct msm_audio_event { + int event_type; + int timeout_ms; + union msm_audio_event_payload event_payload; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +#define MSM_SNDDEV_CAP_RX 0x1 +#define MSM_SNDDEV_CAP_TX 0x2 +#define MSM_SNDDEV_CAP_VOICE 0x4 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct msm_snd_device_info { + uint32_t dev_id; + uint32_t dev_cap; + char dev_name[64]; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +struct msm_snd_device_list { + uint32_t num_dev; + struct msm_snd_device_info *list; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +struct msm_dtmf_config { + uint16_t path; + uint16_t dtmf_hi; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint16_t dtmf_low; + uint16_t duration; + uint16_t tx_gain; + uint16_t rx_gain; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint16_t mixing; +}; +#define AUDIO_ROUTE_STREAM_VOICE_RX 0 +#define AUDIO_ROUTE_STREAM_VOICE_TX 1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define AUDIO_ROUTE_STREAM_PLAYBACK 2 +#define AUDIO_ROUTE_STREAM_REC 3 +struct msm_audio_route_config { + uint32_t stream_type; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t stream_id; + uint32_t dev_id; +}; +#define AUDIO_MAX_EQ_BANDS 12 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct msm_audio_eq_band { + uint16_t band_idx; + uint32_t filter_type; + uint32_t center_freq_hz; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t filter_gain; + uint32_t q_factor; +} __attribute__ ((packed)); +struct msm_audio_eq_stream_config { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t enable; + uint32_t num_bands; + struct msm_audio_eq_band eq_bands[AUDIO_MAX_EQ_BANDS]; +} __attribute__ ((packed)); +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct msm_acdb_cmd_device { + uint32_t command_id; + uint32_t device_id; + uint32_t network_id; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t sample_rate_id; + uint32_t interface_id; + uint32_t algorithm_block_id; + uint32_t total_bytes; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t *phys_buf; +}; +struct msm_hwacc_data_config { + __u32 buf_size; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u32 num_buf; + __u32 num_channels; + __u8 channel_map[8]; + __u32 sample_rate; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u32 bits_per_sample; +}; +struct msm_hwacc_buf_cfg { + __u32 input_len; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u32 output_len; +}; +struct msm_hwacc_buf_avail { + __u32 input_num_avail; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u32 output_num_avail; +}; +struct msm_hwacc_effects_config { + struct msm_hwacc_data_config input; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + struct msm_hwacc_data_config output; + struct msm_hwacc_buf_cfg buf_cfg; + __u32 meta_mode_enabled; + __u32 overwrite_topology; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __s32 topology; +}; +#endif + diff --git a/kernel-headers/linux/msm_audio_aac.h b/kernel-headers/linux/msm_audio_aac.h new file mode 100644 index 0000000..d544c75 --- /dev/null +++ b/kernel-headers/linux/msm_audio_aac.h @@ -0,0 +1,82 @@ +/**************************************************************************** + **************************************************************************** + *** + *** This header was automatically generated from a Linux kernel header + *** of the same name, to make information necessary for userspace to + *** call into the kernel available to libc. It contains only constants, + *** structures, and macros generated from the original header, and thus, + *** contains no copyrightable information. + *** + *** To edit the content of this header, modify the corresponding + *** source file (e.g. under external/kernel-headers/original/) then + *** run bionic/libc/kernel/tools/update_all.py + *** + *** Any manual change here will be lost the next time this script will + *** be run. You've been warned! + *** + **************************************************************************** + ****************************************************************************/ +#ifndef _UAPI_MSM_AUDIO_AAC_H +#define _UAPI_MSM_AUDIO_AAC_H +#include <linux/msm_audio.h> +#define AUDIO_SET_AAC_CONFIG _IOW(AUDIO_IOCTL_MAGIC, (AUDIO_MAX_COMMON_IOCTL_NUM+0), struct msm_audio_aac_config) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define AUDIO_GET_AAC_CONFIG _IOR(AUDIO_IOCTL_MAGIC, (AUDIO_MAX_COMMON_IOCTL_NUM+1), struct msm_audio_aac_config) +#define AUDIO_SET_AAC_ENC_CONFIG _IOW(AUDIO_IOCTL_MAGIC, (AUDIO_MAX_COMMON_IOCTL_NUM+3), struct msm_audio_aac_enc_config) +#define AUDIO_GET_AAC_ENC_CONFIG _IOR(AUDIO_IOCTL_MAGIC, (AUDIO_MAX_COMMON_IOCTL_NUM+4), struct msm_audio_aac_enc_config) +#define AUDIO_SET_AAC_MIX_CONFIG _IOR(AUDIO_IOCTL_MAGIC, (AUDIO_MAX_COMMON_IOCTL_NUM+5), uint32_t) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define AUDIO_AAC_FORMAT_ADTS -1 +#define AUDIO_AAC_FORMAT_RAW 0x0000 +#define AUDIO_AAC_FORMAT_PSUEDO_RAW 0x0001 +#define AUDIO_AAC_FORMAT_LOAS 0x0002 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define AUDIO_AAC_FORMAT_ADIF 0x0003 +#define AUDIO_AAC_OBJECT_LC 0x0002 +#define AUDIO_AAC_OBJECT_LTP 0x0004 +#define AUDIO_AAC_OBJECT_ERLC 0x0011 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define AUDIO_AAC_OBJECT_BSAC 0x0016 +#define AUDIO_AAC_SEC_DATA_RES_ON 0x0001 +#define AUDIO_AAC_SEC_DATA_RES_OFF 0x0000 +#define AUDIO_AAC_SCA_DATA_RES_ON 0x0001 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define AUDIO_AAC_SCA_DATA_RES_OFF 0x0000 +#define AUDIO_AAC_SPEC_DATA_RES_ON 0x0001 +#define AUDIO_AAC_SPEC_DATA_RES_OFF 0x0000 +#define AUDIO_AAC_SBR_ON_FLAG_ON 0x0001 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define AUDIO_AAC_SBR_ON_FLAG_OFF 0x0000 +#define AUDIO_AAC_SBR_PS_ON_FLAG_ON 0x0001 +#define AUDIO_AAC_SBR_PS_ON_FLAG_OFF 0x0000 +#define AUDIO_AAC_DUAL_MONO_PL_PR 0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define AUDIO_AAC_DUAL_MONO_SL_SR 1 +#define AUDIO_AAC_DUAL_MONO_SL_PR 2 +#define AUDIO_AAC_DUAL_MONO_PL_SR 3 +struct msm_audio_aac_config { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + signed short format; + unsigned short audio_object; + unsigned short ep_config; + unsigned short aac_section_data_resilience_flag; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned short aac_scalefactor_data_resilience_flag; + unsigned short aac_spectral_data_resilience_flag; + unsigned short sbr_on_flag; + unsigned short sbr_ps_on_flag; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned short dual_mono_mode; + unsigned short channel_configuration; + unsigned short sample_rate; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct msm_audio_aac_enc_config { + uint32_t channels; + uint32_t sample_rate; + uint32_t bit_rate; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t stream_format; +}; +#endif + diff --git a/kernel-headers/linux/msm_audio_acdb.h b/kernel-headers/linux/msm_audio_acdb.h new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/kernel-headers/linux/msm_audio_acdb.h diff --git a/kernel-headers/linux/msm_audio_amrwbplus.h b/kernel-headers/linux/msm_audio_amrwbplus.h new file mode 100644 index 0000000..aedcfa2 --- /dev/null +++ b/kernel-headers/linux/msm_audio_amrwbplus.h @@ -0,0 +1,36 @@ +/**************************************************************************** + **************************************************************************** + *** + *** This header was automatically generated from a Linux kernel header + *** of the same name, to make information necessary for userspace to + *** call into the kernel available to libc. It contains only constants, + *** structures, and macros generated from the original header, and thus, + *** contains no copyrightable information. + *** + *** To edit the content of this header, modify the corresponding + *** source file (e.g. under external/kernel-headers/original/) then + *** run bionic/libc/kernel/tools/update_all.py + *** + *** Any manual change here will be lost the next time this script will + *** be run. You've been warned! + *** + **************************************************************************** + ****************************************************************************/ +#ifndef _UAPI_MSM_AUDIO_AMR_WB_PLUS_H +#define _UAPI_MSM_AUDIO_AMR_WB_PLUS_H +#define AUDIO_GET_AMRWBPLUS_CONFIG_V2 _IOR(AUDIO_IOCTL_MAGIC, (AUDIO_MAX_COMMON_IOCTL_NUM+2), struct msm_audio_amrwbplus_config_v2) +#define AUDIO_SET_AMRWBPLUS_CONFIG_V2 _IOW(AUDIO_IOCTL_MAGIC, (AUDIO_MAX_COMMON_IOCTL_NUM+3), struct msm_audio_amrwbplus_config_v2) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct msm_audio_amrwbplus_config_v2 { + unsigned int size_bytes; + unsigned int version; + unsigned int num_channels; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned int amr_band_mode; + unsigned int amr_dtx_mode; + unsigned int amr_frame_fmt; + unsigned int amr_lsf_idx; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +#endif + diff --git a/kernel-headers/linux/msm_audio_wma.h b/kernel-headers/linux/msm_audio_wma.h new file mode 100644 index 0000000..c1a6ed2 --- /dev/null +++ b/kernel-headers/linux/msm_audio_wma.h @@ -0,0 +1,49 @@ +/**************************************************************************** + **************************************************************************** + *** + *** This header was automatically generated from a Linux kernel header + *** of the same name, to make information necessary for userspace to + *** call into the kernel available to libc. It contains only constants, + *** structures, and macros generated from the original header, and thus, + *** contains no copyrightable information. + *** + *** To edit the content of this header, modify the corresponding + *** source file (e.g. under external/kernel-headers/original/) then + *** run bionic/libc/kernel/tools/update_all.py + *** + *** Any manual change here will be lost the next time this script will + *** be run. You've been warned! + *** + **************************************************************************** + ****************************************************************************/ +#ifndef _UAPI_MSM_AUDIO_WMA_H +#define _UAPI_MSM_AUDIO_WMA_H +#define AUDIO_GET_WMA_CONFIG _IOR(AUDIO_IOCTL_MAGIC, (AUDIO_MAX_COMMON_IOCTL_NUM+0), unsigned) +#define AUDIO_SET_WMA_CONFIG _IOW(AUDIO_IOCTL_MAGIC, (AUDIO_MAX_COMMON_IOCTL_NUM+1), unsigned) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define AUDIO_GET_WMA_CONFIG_V2 _IOR(AUDIO_IOCTL_MAGIC, (AUDIO_MAX_COMMON_IOCTL_NUM+2), struct msm_audio_wma_config_v2) +#define AUDIO_SET_WMA_CONFIG_V2 _IOW(AUDIO_IOCTL_MAGIC, (AUDIO_MAX_COMMON_IOCTL_NUM+3), struct msm_audio_wma_config_v2) +struct msm_audio_wma_config { + unsigned short armdatareqthr; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned short channelsdecoded; + unsigned short wmabytespersec; + unsigned short wmasamplingfreq; + unsigned short wmaencoderopts; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +struct msm_audio_wma_config_v2 { + unsigned short format_tag; + unsigned short numchannels; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t samplingrate; + uint32_t avgbytespersecond; + unsigned short block_align; + unsigned short validbitspersample; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t channelmask; + unsigned short encodeopt; +}; +#endif +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + diff --git a/kernel-headers/linux/msm_audio_wmapro.h b/kernel-headers/linux/msm_audio_wmapro.h new file mode 100644 index 0000000..bcd41f3 --- /dev/null +++ b/kernel-headers/linux/msm_audio_wmapro.h @@ -0,0 +1,41 @@ +/**************************************************************************** + **************************************************************************** + *** + *** This header was automatically generated from a Linux kernel header + *** of the same name, to make information necessary for userspace to + *** call into the kernel available to libc. It contains only constants, + *** structures, and macros generated from the original header, and thus, + *** contains no copyrightable information. + *** + *** To edit the content of this header, modify the corresponding + *** source file (e.g. under external/kernel-headers/original/) then + *** run bionic/libc/kernel/tools/update_all.py + *** + *** Any manual change here will be lost the next time this script will + *** be run. You've been warned! + *** + **************************************************************************** + ****************************************************************************/ +#ifndef _UAPI_MSM_AUDIO_WMAPRO_H +#define _UAPI_MSM_AUDIO_WMAPRO_H +#define AUDIO_GET_WMAPRO_CONFIG _IOR(AUDIO_IOCTL_MAGIC, (AUDIO_MAX_COMMON_IOCTL_NUM+0), struct msm_audio_wmapro_config) +#define AUDIO_SET_WMAPRO_CONFIG _IOW(AUDIO_IOCTL_MAGIC, (AUDIO_MAX_COMMON_IOCTL_NUM+1), struct msm_audio_wmapro_config) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct msm_audio_wmapro_config { + unsigned short armdatareqthr; + uint8_t validbitspersample; + uint8_t numchannels; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned short formattag; + unsigned short samplingrate; + unsigned short avgbytespersecond; + unsigned short asfpacketlength; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned short channelmask; + unsigned short encodeopt; + unsigned short advancedencodeopt; + uint32_t advancedencodeopt2; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +#endif + diff --git a/kernel-headers/linux/msm_ion.h b/kernel-headers/linux/msm_ion.h new file mode 100644 index 0000000..fb5db71 --- /dev/null +++ b/kernel-headers/linux/msm_ion.h @@ -0,0 +1,125 @@ +/**************************************************************************** + **************************************************************************** + *** + *** This header was automatically generated from a Linux kernel header + *** of the same name, to make information necessary for userspace to + *** call into the kernel available to libc. It contains only constants, + *** structures, and macros generated from the original header, and thus, + *** contains no copyrightable information. + *** + *** To edit the content of this header, modify the corresponding + *** source file (e.g. under external/kernel-headers/original/) then + *** run bionic/libc/kernel/tools/update_all.py + *** + *** Any manual change here will be lost the next time this script will + *** be run. You've been warned! + *** + **************************************************************************** + ****************************************************************************/ +#ifndef _UAPI_MSM_ION_H +#define _UAPI_MSM_ION_H +#include "../../../bionic/libc/kernel/uapi/linux/ion.h" +enum msm_ion_heap_types { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + ION_HEAP_TYPE_MSM_START = ION_HEAP_TYPE_CUSTOM + 1, + ION_HEAP_TYPE_SECURE_DMA = ION_HEAP_TYPE_MSM_START, + ION_HEAP_TYPE_REMOVED, +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +enum ion_heap_ids { + INVALID_HEAP_ID = -1, + ION_CP_MM_HEAP_ID = 8, + ION_CP_MFC_HEAP_ID = 12, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + ION_CP_WB_HEAP_ID = 16, + ION_CAMERA_HEAP_ID = 20, + ION_SYSTEM_CONTIG_HEAP_ID = 21, + ION_ADSP_HEAP_ID = 22, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + ION_PIL1_HEAP_ID = 23, + ION_SF_HEAP_ID = 24, + ION_SYSTEM_HEAP_ID = 25, + ION_PIL2_HEAP_ID = 26, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + ION_QSECOM_HEAP_ID = 27, + ION_AUDIO_HEAP_ID = 28, + ION_MM_FIRMWARE_HEAP_ID = 29, + ION_HEAP_ID_RESERVED = 31 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +#define ION_IOMMU_HEAP_ID ION_SYSTEM_HEAP_ID +#define ION_HEAP_TYPE_IOMMU ION_HEAP_TYPE_SYSTEM +enum ion_fixed_position { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + NOT_FIXED, + FIXED_LOW, + FIXED_MIDDLE, + FIXED_HIGH, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +enum cp_mem_usage { + VIDEO_BITSTREAM = 0x1, + VIDEO_PIXEL = 0x2, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + VIDEO_NONPIXEL = 0x3, + DISPLAY_SECURE_CP_USAGE = 0x4, + CAMERA_SECURE_CP_USAGE = 0x5, + MAX_USAGE = 0x6, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + UNKNOWN = 0x7FFFFFFF, +}; +#define ION_FLAG_ALLOW_NON_CONTIG (1 << 24) +#define ION_FLAG_SECURE (1 << ION_HEAP_ID_RESERVED) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define ION_FLAG_FORCE_CONTIGUOUS (1 << 30) +#define ION_FLAG_POOL_FORCE_ALLOC (1 << 16) +#define ION_SECURE ION_FLAG_SECURE +#define ION_FORCE_CONTIGUOUS ION_FLAG_FORCE_CONTIGUOUS +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define ION_HEAP(bit) (1 << (bit)) +#define ION_ADSP_HEAP_NAME "adsp" +#define ION_SYSTEM_HEAP_NAME "system" +#define ION_VMALLOC_HEAP_NAME ION_SYSTEM_HEAP_NAME +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define ION_KMALLOC_HEAP_NAME "kmalloc" +#define ION_AUDIO_HEAP_NAME "audio" +#define ION_SF_HEAP_NAME "sf" +#define ION_MM_HEAP_NAME "mm" +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define ION_CAMERA_HEAP_NAME "camera_preview" +#define ION_IOMMU_HEAP_NAME "iommu" +#define ION_MFC_HEAP_NAME "mfc" +#define ION_WB_HEAP_NAME "wb" +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define ION_MM_FIRMWARE_HEAP_NAME "mm_fw" +#define ION_PIL1_HEAP_NAME "pil_1" +#define ION_PIL2_HEAP_NAME "pil_2" +#define ION_QSECOM_HEAP_NAME "qsecom" +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define ION_SET_CACHED(__cache) (__cache | ION_FLAG_CACHED) +#define ION_SET_UNCACHED(__cache) (__cache & ~ION_FLAG_CACHED) +#define ION_IS_CACHED(__flags) ((__flags) & ION_FLAG_CACHED) +struct ion_flush_data { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + ion_user_handle_t handle; + int fd; + void *vaddr; + unsigned int offset; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned int length; +}; +struct ion_prefetch_data { + int heap_id; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned long len; +}; +#define ION_IOC_MSM_MAGIC 'M' +#define ION_IOC_CLEAN_CACHES _IOWR(ION_IOC_MSM_MAGIC, 0, struct ion_flush_data) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define ION_IOC_INV_CACHES _IOWR(ION_IOC_MSM_MAGIC, 1, struct ion_flush_data) +#define ION_IOC_CLEAN_INV_CACHES _IOWR(ION_IOC_MSM_MAGIC, 2, struct ion_flush_data) +#define ION_IOC_PREFETCH _IOWR(ION_IOC_MSM_MAGIC, 3, struct ion_prefetch_data) +#define ION_IOC_DRAIN _IOWR(ION_IOC_MSM_MAGIC, 4, struct ion_prefetch_data) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#endif + diff --git a/kernel-headers/linux/msm_kgsl.h b/kernel-headers/linux/msm_kgsl.h new file mode 100644 index 0000000..60407eb --- /dev/null +++ b/kernel-headers/linux/msm_kgsl.h @@ -0,0 +1,674 @@ +/**************************************************************************** + **************************************************************************** + *** + *** This header was automatically generated from a Linux kernel header + *** of the same name, to make information necessary for userspace to + *** call into the kernel available to libc. It contains only constants, + *** structures, and macros generated from the original header, and thus, + *** contains no copyrightable information. + *** + *** To edit the content of this header, modify the corresponding + *** source file (e.g. under external/kernel-headers/original/) then + *** run bionic/libc/kernel/tools/update_all.py + *** + *** Any manual change here will be lost the next time this script will + *** be run. You've been warned! + *** + **************************************************************************** + ****************************************************************************/ +#ifndef _UAPI_MSM_KGSL_H +#define _UAPI_MSM_KGSL_H +#define KGSL_VERSION_MAJOR 3 +#define KGSL_VERSION_MINOR 14 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define KGSL_CONTEXT_SAVE_GMEM 0x00000001 +#define KGSL_CONTEXT_NO_GMEM_ALLOC 0x00000002 +#define KGSL_CONTEXT_SUBMIT_IB_LIST 0x00000004 +#define KGSL_CONTEXT_CTX_SWITCH 0x00000008 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define KGSL_CONTEXT_PREAMBLE 0x00000010 +#define KGSL_CONTEXT_TRASH_STATE 0x00000020 +#define KGSL_CONTEXT_PER_CONTEXT_TS 0x00000040 +#define KGSL_CONTEXT_USER_GENERATED_TS 0x00000080 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define KGSL_CONTEXT_END_OF_FRAME 0x00000100 +#define KGSL_CONTEXT_NO_FAULT_TOLERANCE 0x00000200 +#define KGSL_CONTEXT_SYNC 0x00000400 +#define KGSL_CONTEXT_PWR_CONSTRAINT 0x00000800 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define KGSL_CONTEXT_PRIORITY_MASK 0x0000F000 +#define KGSL_CONTEXT_PRIORITY_SHIFT 12 +#define KGSL_CONTEXT_PRIORITY_UNDEF 0 +#define KGSL_CONTEXT_IFH_NOP 0x00010000 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define KGSL_CONTEXT_SECURE 0x00020000 +#define KGSL_CONTEXT_TYPE_MASK 0x01F00000 +#define KGSL_CONTEXT_TYPE_SHIFT 20 +#define KGSL_CONTEXT_TYPE_ANY 0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define KGSL_CONTEXT_TYPE_GL 1 +#define KGSL_CONTEXT_TYPE_CL 2 +#define KGSL_CONTEXT_TYPE_C2D 3 +#define KGSL_CONTEXT_TYPE_RS 4 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define KGSL_CONTEXT_TYPE_UNKNOWN 0x1E +#define KGSL_CONTEXT_INVALID 0xffffffff +#define KGSL_CMDBATCH_MEMLIST 0x00000001 +#define KGSL_CMDBATCH_MARKER 0x00000002 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define KGSL_CMDBATCH_SUBMIT_IB_LIST KGSL_CONTEXT_SUBMIT_IB_LIST +#define KGSL_CMDBATCH_CTX_SWITCH KGSL_CONTEXT_CTX_SWITCH +#define KGSL_CMDBATCH_PROFILING 0x00000010 +#define KGSL_CMDBATCH_END_OF_FRAME KGSL_CONTEXT_END_OF_FRAME +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define KGSL_CMDBATCH_SYNC KGSL_CONTEXT_SYNC +#define KGSL_CMDBATCH_PWR_CONSTRAINT KGSL_CONTEXT_PWR_CONSTRAINT +#define KGSL_MEMFLAGS_GPUREADONLY 0x01000000 +#define KGSL_MEMFLAGS_USE_CPU_MAP 0x10000000 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define KGSL_MEMFLAGS_SECURE 0x00000008 +#define KGSL_CACHEMODE_MASK 0x0C000000 +#define KGSL_CACHEMODE_SHIFT 26 +#define KGSL_CACHEMODE_WRITECOMBINE 0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define KGSL_CACHEMODE_UNCACHED 1 +#define KGSL_CACHEMODE_WRITETHROUGH 2 +#define KGSL_CACHEMODE_WRITEBACK 3 +#define KGSL_MEMTYPE_MASK 0x0000FF00 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define KGSL_MEMTYPE_SHIFT 8 +#define KGSL_MEMTYPE_OBJECTANY 0 +#define KGSL_MEMTYPE_FRAMEBUFFER 1 +#define KGSL_MEMTYPE_RENDERBUFFER 2 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define KGSL_MEMTYPE_ARRAYBUFFER 3 +#define KGSL_MEMTYPE_ELEMENTARRAYBUFFER 4 +#define KGSL_MEMTYPE_VERTEXARRAYBUFFER 5 +#define KGSL_MEMTYPE_TEXTURE 6 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define KGSL_MEMTYPE_SURFACE 7 +#define KGSL_MEMTYPE_EGL_SURFACE 8 +#define KGSL_MEMTYPE_GL 9 +#define KGSL_MEMTYPE_CL 10 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define KGSL_MEMTYPE_CL_BUFFER_MAP 11 +#define KGSL_MEMTYPE_CL_BUFFER_NOMAP 12 +#define KGSL_MEMTYPE_CL_IMAGE_MAP 13 +#define KGSL_MEMTYPE_CL_IMAGE_NOMAP 14 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define KGSL_MEMTYPE_CL_KERNEL_STACK 15 +#define KGSL_MEMTYPE_COMMAND 16 +#define KGSL_MEMTYPE_2D 17 +#define KGSL_MEMTYPE_EGL_IMAGE 18 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define KGSL_MEMTYPE_EGL_SHADOW 19 +#define KGSL_MEMTYPE_MULTISAMPLE 20 +#define KGSL_MEMTYPE_KERNEL 255 +#define KGSL_MEMALIGN_MASK 0x00FF0000 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define KGSL_MEMALIGN_SHIFT 16 +enum kgsl_user_mem_type { + KGSL_USER_MEM_TYPE_PMEM = 0x00000000, + KGSL_USER_MEM_TYPE_ASHMEM = 0x00000001, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + KGSL_USER_MEM_TYPE_ADDR = 0x00000002, + KGSL_USER_MEM_TYPE_ION = 0x00000003, + KGSL_USER_MEM_TYPE_MAX = 0x00000007, +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define KGSL_MEMFLAGS_USERMEM_MASK 0x000000e0 +#define KGSL_MEMFLAGS_USERMEM_SHIFT 5 +#define KGSL_USERMEM_FLAG(x) (((x) + 1) << KGSL_MEMFLAGS_USERMEM_SHIFT) +#define KGSL_MEMFLAGS_NOT_USERMEM 0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define KGSL_MEMFLAGS_USERMEM_PMEM KGSL_USERMEM_FLAG(KGSL_USER_MEM_TYPE_PMEM) +#define KGSL_MEMFLAGS_USERMEM_ASHMEM KGSL_USERMEM_FLAG(KGSL_USER_MEM_TYPE_ASHMEM) +#define KGSL_MEMFLAGS_USERMEM_ADDR KGSL_USERMEM_FLAG(KGSL_USER_MEM_TYPE_ADDR) +#define KGSL_MEMFLAGS_USERMEM_ION KGSL_USERMEM_FLAG(KGSL_USER_MEM_TYPE_ION) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define KGSL_FLAGS_NORMALMODE 0x00000000 +#define KGSL_FLAGS_SAFEMODE 0x00000001 +#define KGSL_FLAGS_INITIALIZED0 0x00000002 +#define KGSL_FLAGS_INITIALIZED 0x00000004 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define KGSL_FLAGS_STARTED 0x00000008 +#define KGSL_FLAGS_ACTIVE 0x00000010 +#define KGSL_FLAGS_RESERVED0 0x00000020 +#define KGSL_FLAGS_RESERVED1 0x00000040 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define KGSL_FLAGS_RESERVED2 0x00000080 +#define KGSL_FLAGS_SOFT_RESET 0x00000100 +#define KGSL_FLAGS_PER_CONTEXT_TIMESTAMPS 0x00000200 +#define KGSL_CLK_SRC 0x00000001 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define KGSL_CLK_CORE 0x00000002 +#define KGSL_CLK_IFACE 0x00000004 +#define KGSL_CLK_MEM 0x00000008 +#define KGSL_CLK_MEM_IFACE 0x00000010 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define KGSL_CLK_AXI 0x00000020 +#define KGSL_SYNCOBJ_SERVER_TIMEOUT 2000 +enum kgsl_ctx_reset_stat { + KGSL_CTX_STAT_NO_ERROR = 0x00000000, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + KGSL_CTX_STAT_GUILTY_CONTEXT_RESET_EXT = 0x00000001, + KGSL_CTX_STAT_INNOCENT_CONTEXT_RESET_EXT = 0x00000002, + KGSL_CTX_STAT_UNKNOWN_CONTEXT_RESET_EXT = 0x00000003 +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define KGSL_CONVERT_TO_MBPS(val) (val*1000*1000U) +enum kgsl_deviceid { + KGSL_DEVICE_3D0 = 0x00000000, + KGSL_DEVICE_2D0 = 0x00000001, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + KGSL_DEVICE_2D1 = 0x00000002, + KGSL_DEVICE_MAX = 0x00000003 +}; +struct kgsl_devinfo { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned int device_id; + unsigned int chip_id; + unsigned int mmu_enabled; + unsigned long gmem_gpubaseaddr; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned int gpu_id; + size_t gmem_sizebytes; +}; +struct kgsl_devmemstore { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + volatile unsigned int soptimestamp; + unsigned int sbz; + volatile unsigned int eoptimestamp; + unsigned int sbz2; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + volatile unsigned int ts_cmp_enable; + unsigned int sbz3; + volatile unsigned int ref_wait_ts; + unsigned int sbz4; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned int current_context; + unsigned int sbz5; +}; +#define KGSL_MEMSTORE_OFFSET(ctxt_id, field) ((ctxt_id)*sizeof(struct kgsl_devmemstore) + offsetof(struct kgsl_devmemstore, field)) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +enum kgsl_timestamp_type { + KGSL_TIMESTAMP_CONSUMED = 0x00000001, + KGSL_TIMESTAMP_RETIRED = 0x00000002, + KGSL_TIMESTAMP_QUEUED = 0x00000003, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +enum kgsl_property_type { + KGSL_PROP_DEVICE_INFO = 0x00000001, + KGSL_PROP_DEVICE_SHADOW = 0x00000002, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + KGSL_PROP_DEVICE_POWER = 0x00000003, + KGSL_PROP_SHMEM = 0x00000004, + KGSL_PROP_SHMEM_APERTURES = 0x00000005, + KGSL_PROP_MMU_ENABLE = 0x00000006, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + KGSL_PROP_INTERRUPT_WAITS = 0x00000007, + KGSL_PROP_VERSION = 0x00000008, + KGSL_PROP_GPU_RESET_STAT = 0x00000009, + KGSL_PROP_PWRCTRL = 0x0000000E, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + KGSL_PROP_PWR_CONSTRAINT = 0x00000012, +}; +struct kgsl_shadowprop { + unsigned long gpuaddr; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + size_t size; + unsigned int flags; +}; +struct kgsl_version { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned int drv_major; + unsigned int drv_minor; + unsigned int dev_major; + unsigned int dev_minor; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +#define KGSL_PERFCOUNTER_GROUP_CP 0x0 +#define KGSL_PERFCOUNTER_GROUP_RBBM 0x1 +#define KGSL_PERFCOUNTER_GROUP_PC 0x2 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define KGSL_PERFCOUNTER_GROUP_VFD 0x3 +#define KGSL_PERFCOUNTER_GROUP_HLSQ 0x4 +#define KGSL_PERFCOUNTER_GROUP_VPC 0x5 +#define KGSL_PERFCOUNTER_GROUP_TSE 0x6 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define KGSL_PERFCOUNTER_GROUP_RAS 0x7 +#define KGSL_PERFCOUNTER_GROUP_UCHE 0x8 +#define KGSL_PERFCOUNTER_GROUP_TP 0x9 +#define KGSL_PERFCOUNTER_GROUP_SP 0xA +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define KGSL_PERFCOUNTER_GROUP_RB 0xB +#define KGSL_PERFCOUNTER_GROUP_PWR 0xC +#define KGSL_PERFCOUNTER_GROUP_VBIF 0xD +#define KGSL_PERFCOUNTER_GROUP_VBIF_PWR 0xE +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define KGSL_PERFCOUNTER_GROUP_MH 0xF +#define KGSL_PERFCOUNTER_GROUP_PA_SU 0x10 +#define KGSL_PERFCOUNTER_GROUP_SQ 0x11 +#define KGSL_PERFCOUNTER_GROUP_SX 0x12 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define KGSL_PERFCOUNTER_GROUP_TCF 0x13 +#define KGSL_PERFCOUNTER_GROUP_TCM 0x14 +#define KGSL_PERFCOUNTER_GROUP_TCR 0x15 +#define KGSL_PERFCOUNTER_GROUP_L2 0x16 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define KGSL_PERFCOUNTER_GROUP_VSC 0x17 +#define KGSL_PERFCOUNTER_GROUP_CCU 0x18 +#define KGSL_PERFCOUNTER_GROUP_ALWAYSON 0x1B +#define KGSL_PERFCOUNTER_GROUP_MAX 0x1C +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define KGSL_PERFCOUNTER_NOT_USED 0xFFFFFFFF +#define KGSL_PERFCOUNTER_BROKEN 0xFFFFFFFE +struct kgsl_ibdesc { + unsigned long gpuaddr; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned long __pad; + size_t sizedwords; + unsigned int ctrl; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct kgsl_cmdbatch_profiling_buffer { + uint64_t wall_clock_s; + uint64_t wall_clock_ns; + uint64_t gpu_ticks_queued; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint64_t gpu_ticks_submitted; + uint64_t gpu_ticks_retired; +}; +#define KGSL_IOC_TYPE 0x09 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct kgsl_device_getproperty { + unsigned int type; + void __user *value; + size_t sizebytes; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +#define IOCTL_KGSL_DEVICE_GETPROPERTY _IOWR(KGSL_IOC_TYPE, 0x2, struct kgsl_device_getproperty) +struct kgsl_device_waittimestamp { + unsigned int timestamp; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned int timeout; +}; +#define IOCTL_KGSL_DEVICE_WAITTIMESTAMP _IOW(KGSL_IOC_TYPE, 0x6, struct kgsl_device_waittimestamp) +struct kgsl_device_waittimestamp_ctxtid { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned int context_id; + unsigned int timestamp; + unsigned int timeout; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define IOCTL_KGSL_DEVICE_WAITTIMESTAMP_CTXTID _IOW(KGSL_IOC_TYPE, 0x7, struct kgsl_device_waittimestamp_ctxtid) +struct kgsl_ringbuffer_issueibcmds { + unsigned int drawctxt_id; + unsigned long ibdesc_addr; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned int numibs; + unsigned int timestamp; + unsigned int flags; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define IOCTL_KGSL_RINGBUFFER_ISSUEIBCMDS _IOWR(KGSL_IOC_TYPE, 0x10, struct kgsl_ringbuffer_issueibcmds) +struct kgsl_cmdstream_readtimestamp { + unsigned int type; + unsigned int timestamp; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +#define IOCTL_KGSL_CMDSTREAM_READTIMESTAMP_OLD _IOR(KGSL_IOC_TYPE, 0x11, struct kgsl_cmdstream_readtimestamp) +#define IOCTL_KGSL_CMDSTREAM_READTIMESTAMP _IOWR(KGSL_IOC_TYPE, 0x11, struct kgsl_cmdstream_readtimestamp) +struct kgsl_cmdstream_freememontimestamp { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned long gpuaddr; + unsigned int type; + unsigned int timestamp; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define IOCTL_KGSL_CMDSTREAM_FREEMEMONTIMESTAMP _IOW(KGSL_IOC_TYPE, 0x12, struct kgsl_cmdstream_freememontimestamp) +#define IOCTL_KGSL_CMDSTREAM_FREEMEMONTIMESTAMP_OLD _IOR(KGSL_IOC_TYPE, 0x12, struct kgsl_cmdstream_freememontimestamp) +struct kgsl_drawctxt_create { + unsigned int flags; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned int drawctxt_id; +}; +#define IOCTL_KGSL_DRAWCTXT_CREATE _IOWR(KGSL_IOC_TYPE, 0x13, struct kgsl_drawctxt_create) +struct kgsl_drawctxt_destroy { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned int drawctxt_id; +}; +#define IOCTL_KGSL_DRAWCTXT_DESTROY _IOW(KGSL_IOC_TYPE, 0x14, struct kgsl_drawctxt_destroy) +struct kgsl_map_user_mem { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + int fd; + unsigned long gpuaddr; + size_t len; + size_t offset; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned long hostptr; + enum kgsl_user_mem_type memtype; + unsigned int flags; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define IOCTL_KGSL_MAP_USER_MEM _IOWR(KGSL_IOC_TYPE, 0x15, struct kgsl_map_user_mem) +struct kgsl_cmdstream_readtimestamp_ctxtid { + unsigned int context_id; + unsigned int type; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned int timestamp; +}; +#define IOCTL_KGSL_CMDSTREAM_READTIMESTAMP_CTXTID _IOWR(KGSL_IOC_TYPE, 0x16, struct kgsl_cmdstream_readtimestamp_ctxtid) +struct kgsl_cmdstream_freememontimestamp_ctxtid { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned int context_id; + unsigned long gpuaddr; + unsigned int type; + unsigned int timestamp; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +#define IOCTL_KGSL_CMDSTREAM_FREEMEMONTIMESTAMP_CTXTID _IOW(KGSL_IOC_TYPE, 0x17, struct kgsl_cmdstream_freememontimestamp_ctxtid) +struct kgsl_sharedmem_from_pmem { + int pmem_fd; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned long gpuaddr; + unsigned int len; + unsigned int offset; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define IOCTL_KGSL_SHAREDMEM_FROM_PMEM _IOWR(KGSL_IOC_TYPE, 0x20, struct kgsl_sharedmem_from_pmem) +struct kgsl_sharedmem_free { + unsigned long gpuaddr; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define IOCTL_KGSL_SHAREDMEM_FREE _IOW(KGSL_IOC_TYPE, 0x21, struct kgsl_sharedmem_free) +struct kgsl_cff_user_event { + unsigned char cff_opcode; + unsigned int op1; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned int op2; + unsigned int op3; + unsigned int op4; + unsigned int op5; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned int __pad[2]; +}; +#define IOCTL_KGSL_CFF_USER_EVENT _IOW(KGSL_IOC_TYPE, 0x31, struct kgsl_cff_user_event) +struct kgsl_gmem_desc { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned int x; + unsigned int y; + unsigned int width; + unsigned int height; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned int pitch; +}; +struct kgsl_buffer_desc { + void *hostptr; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned long gpuaddr; + int size; + unsigned int format; + unsigned int pitch; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned int enabled; +}; +struct kgsl_bind_gmem_shadow { + unsigned int drawctxt_id; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + struct kgsl_gmem_desc gmem_desc; + unsigned int shadow_x; + unsigned int shadow_y; + struct kgsl_buffer_desc shadow_buffer; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned int buffer_id; +}; +#define IOCTL_KGSL_DRAWCTXT_BIND_GMEM_SHADOW _IOW(KGSL_IOC_TYPE, 0x22, struct kgsl_bind_gmem_shadow) +struct kgsl_sharedmem_from_vmalloc { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned long gpuaddr; + unsigned int hostptr; + unsigned int flags; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define IOCTL_KGSL_SHAREDMEM_FROM_VMALLOC _IOWR(KGSL_IOC_TYPE, 0x23, struct kgsl_sharedmem_from_vmalloc) +#define IOCTL_KGSL_SHAREDMEM_FLUSH_CACHE _IOW(KGSL_IOC_TYPE, 0x24, struct kgsl_sharedmem_free) +struct kgsl_drawctxt_set_bin_base_offset { + unsigned int drawctxt_id; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned int offset; +}; +#define IOCTL_KGSL_DRAWCTXT_SET_BIN_BASE_OFFSET _IOW(KGSL_IOC_TYPE, 0x25, struct kgsl_drawctxt_set_bin_base_offset) +enum kgsl_cmdwindow_type { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + KGSL_CMDWINDOW_MIN = 0x00000000, + KGSL_CMDWINDOW_2D = 0x00000000, + KGSL_CMDWINDOW_3D = 0x00000001, + KGSL_CMDWINDOW_MMU = 0x00000002, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + KGSL_CMDWINDOW_ARBITER = 0x000000FF, + KGSL_CMDWINDOW_MAX = 0x000000FF, +}; +struct kgsl_cmdwindow_write { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + enum kgsl_cmdwindow_type target; + unsigned int addr; + unsigned int data; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define IOCTL_KGSL_CMDWINDOW_WRITE _IOW(KGSL_IOC_TYPE, 0x2e, struct kgsl_cmdwindow_write) +struct kgsl_gpumem_alloc { + unsigned long gpuaddr; + size_t size; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned int flags; +}; +#define IOCTL_KGSL_GPUMEM_ALLOC _IOWR(KGSL_IOC_TYPE, 0x2f, struct kgsl_gpumem_alloc) +struct kgsl_cff_syncmem { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned long gpuaddr; + size_t len; + unsigned int __pad[2]; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define IOCTL_KGSL_CFF_SYNCMEM _IOW(KGSL_IOC_TYPE, 0x30, struct kgsl_cff_syncmem) +struct kgsl_timestamp_event { + int type; + unsigned int timestamp; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned int context_id; + void __user *priv; + size_t len; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define IOCTL_KGSL_TIMESTAMP_EVENT_OLD _IOW(KGSL_IOC_TYPE, 0x31, struct kgsl_timestamp_event) +#define KGSL_TIMESTAMP_EVENT_GENLOCK 1 +struct kgsl_timestamp_event_genlock { + int handle; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +#define KGSL_TIMESTAMP_EVENT_FENCE 2 +struct kgsl_timestamp_event_fence { + int fence_fd; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +#define IOCTL_KGSL_SETPROPERTY _IOW(KGSL_IOC_TYPE, 0x32, struct kgsl_device_getproperty) +#define IOCTL_KGSL_TIMESTAMP_EVENT _IOWR(KGSL_IOC_TYPE, 0x33, struct kgsl_timestamp_event) +struct kgsl_gpumem_alloc_id { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned int id; + unsigned int flags; + size_t size; + size_t mmapsize; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned long gpuaddr; + unsigned long __pad[2]; +}; +#define IOCTL_KGSL_GPUMEM_ALLOC_ID _IOWR(KGSL_IOC_TYPE, 0x34, struct kgsl_gpumem_alloc_id) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct kgsl_gpumem_free_id { + unsigned int id; + unsigned int __pad; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define IOCTL_KGSL_GPUMEM_FREE_ID _IOWR(KGSL_IOC_TYPE, 0x35, struct kgsl_gpumem_free_id) +struct kgsl_gpumem_get_info { + unsigned long gpuaddr; + unsigned int id; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned int flags; + size_t size; + size_t mmapsize; + unsigned long useraddr; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned long __pad[4]; +}; +#define IOCTL_KGSL_GPUMEM_GET_INFO _IOWR(KGSL_IOC_TYPE, 0x36, struct kgsl_gpumem_get_info) +struct kgsl_gpumem_sync_cache { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned long gpuaddr; + unsigned int id; + unsigned int op; + size_t offset; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + size_t length; +}; +#define KGSL_GPUMEM_CACHE_CLEAN (1 << 0) +#define KGSL_GPUMEM_CACHE_TO_GPU KGSL_GPUMEM_CACHE_CLEAN +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define KGSL_GPUMEM_CACHE_INV (1 << 1) +#define KGSL_GPUMEM_CACHE_FROM_GPU KGSL_GPUMEM_CACHE_INV +#define KGSL_GPUMEM_CACHE_FLUSH (KGSL_GPUMEM_CACHE_CLEAN | KGSL_GPUMEM_CACHE_INV) +#define KGSL_GPUMEM_CACHE_RANGE (1 << 31U) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define IOCTL_KGSL_GPUMEM_SYNC_CACHE _IOW(KGSL_IOC_TYPE, 0x37, struct kgsl_gpumem_sync_cache) +struct kgsl_perfcounter_get { + unsigned int groupid; + unsigned int countable; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned int offset; + unsigned int offset_hi; + unsigned int __pad; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define IOCTL_KGSL_PERFCOUNTER_GET _IOWR(KGSL_IOC_TYPE, 0x38, struct kgsl_perfcounter_get) +struct kgsl_perfcounter_put { + unsigned int groupid; + unsigned int countable; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned int __pad[2]; +}; +#define IOCTL_KGSL_PERFCOUNTER_PUT _IOW(KGSL_IOC_TYPE, 0x39, struct kgsl_perfcounter_put) +struct kgsl_perfcounter_query { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned int groupid; + unsigned int __user *countables; + unsigned int count; + unsigned int max_counters; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned int __pad[2]; +}; +#define IOCTL_KGSL_PERFCOUNTER_QUERY _IOWR(KGSL_IOC_TYPE, 0x3A, struct kgsl_perfcounter_query) +struct kgsl_perfcounter_read_group { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned int groupid; + unsigned int countable; + unsigned long long value; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct kgsl_perfcounter_read { + struct kgsl_perfcounter_read_group __user *reads; + unsigned int count; + unsigned int __pad[2]; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +#define IOCTL_KGSL_PERFCOUNTER_READ _IOWR(KGSL_IOC_TYPE, 0x3B, struct kgsl_perfcounter_read) +struct kgsl_gpumem_sync_cache_bulk { + unsigned int __user *id_list; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned int count; + unsigned int op; + unsigned int __pad[2]; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define IOCTL_KGSL_GPUMEM_SYNC_CACHE_BULK _IOWR(KGSL_IOC_TYPE, 0x3C, struct kgsl_gpumem_sync_cache_bulk) +struct kgsl_cmd_syncpoint_timestamp { + unsigned int context_id; + unsigned int timestamp; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +#define KGSL_CMD_SYNCPOINT_TYPE_TIMESTAMP 0 +struct kgsl_cmd_syncpoint_fence { + int fd; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +#define KGSL_CMD_SYNCPOINT_TYPE_FENCE 1 +struct kgsl_cmd_syncpoint { + int type; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + void __user *priv; + size_t size; +}; +#define KGSL_IBDESC_MEMLIST 0x1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define KGSL_IBDESC_PROFILING_BUFFER 0x2 +struct kgsl_submit_commands { + unsigned int context_id; + unsigned int flags; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + struct kgsl_ibdesc __user *cmdlist; + unsigned int numcmds; + struct kgsl_cmd_syncpoint __user *synclist; + unsigned int numsyncs; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned int timestamp; + unsigned int __pad[4]; +}; +#define IOCTL_KGSL_SUBMIT_COMMANDS _IOWR(KGSL_IOC_TYPE, 0x3D, struct kgsl_submit_commands) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct kgsl_device_constraint { + unsigned int type; + unsigned int context_id; + void __user *data; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + size_t size; +}; +#define KGSL_CONSTRAINT_NONE 0 +#define KGSL_CONSTRAINT_PWRLEVEL 1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define KGSL_CONSTRAINT_PWR_MIN 0 +#define KGSL_CONSTRAINT_PWR_MAX 1 +struct kgsl_device_constraint_pwrlevel { + unsigned int level; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +struct kgsl_syncsource_create { + unsigned int id; + unsigned int __pad[3]; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +#define IOCTL_KGSL_SYNCSOURCE_CREATE _IOWR(KGSL_IOC_TYPE, 0x40, struct kgsl_syncsource_create) +struct kgsl_syncsource_destroy { + unsigned int id; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned int __pad[3]; +}; +#define IOCTL_KGSL_SYNCSOURCE_DESTROY _IOWR(KGSL_IOC_TYPE, 0x41, struct kgsl_syncsource_destroy) +struct kgsl_syncsource_create_fence { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned int id; + int fence_fd; + unsigned int __pad[4]; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define IOCTL_KGSL_SYNCSOURCE_CREATE_FENCE _IOWR(KGSL_IOC_TYPE, 0x42, struct kgsl_syncsource_create_fence) +struct kgsl_syncsource_signal_fence { + unsigned int id; + int fence_fd; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned int __pad[4]; +}; +#define IOCTL_KGSL_SYNCSOURCE_SIGNAL_FENCE _IOWR(KGSL_IOC_TYPE, 0x43, struct kgsl_syncsource_signal_fence) +#endif +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + diff --git a/kernel-headers/linux/msm_mdp.h b/kernel-headers/linux/msm_mdp.h new file mode 100644 index 0000000..b01dab5 --- /dev/null +++ b/kernel-headers/linux/msm_mdp.h @@ -0,0 +1,1117 @@ +/**************************************************************************** + **************************************************************************** + *** + *** This header was automatically generated from a Linux kernel header + *** of the same name, to make information necessary for userspace to + *** call into the kernel available to libc. It contains only constants, + *** structures, and macros generated from the original header, and thus, + *** contains no copyrightable information. + *** + *** To edit the content of this header, modify the corresponding + *** source file (e.g. under external/kernel-headers/original/) then + *** run bionic/libc/kernel/tools/update_all.py + *** + *** Any manual change here will be lost the next time this script will + *** be run. You've been warned! + *** + **************************************************************************** + ****************************************************************************/ +#ifndef _UAPI_MSM_MDP_H_ +#define _UAPI_MSM_MDP_H_ +#include <linux/types.h> +#include <linux/fb.h> +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define MSMFB_IOCTL_MAGIC 'm' +#define MSMFB_GRP_DISP _IOW(MSMFB_IOCTL_MAGIC, 1, unsigned int) +#define MSMFB_BLIT _IOW(MSMFB_IOCTL_MAGIC, 2, unsigned int) +#define MSMFB_SUSPEND_SW_REFRESHER _IOW(MSMFB_IOCTL_MAGIC, 128, unsigned int) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define MSMFB_RESUME_SW_REFRESHER _IOW(MSMFB_IOCTL_MAGIC, 129, unsigned int) +#define MSMFB_CURSOR _IOW(MSMFB_IOCTL_MAGIC, 130, struct fb_cursor) +#define MSMFB_SET_LUT _IOW(MSMFB_IOCTL_MAGIC, 131, struct fb_cmap) +#define MSMFB_HISTOGRAM _IOWR(MSMFB_IOCTL_MAGIC, 132, struct mdp_histogram_data) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define MSMFB_GET_CCS_MATRIX _IOWR(MSMFB_IOCTL_MAGIC, 133, struct mdp_ccs) +#define MSMFB_SET_CCS_MATRIX _IOW(MSMFB_IOCTL_MAGIC, 134, struct mdp_ccs) +#define MSMFB_OVERLAY_SET _IOWR(MSMFB_IOCTL_MAGIC, 135, struct mdp_overlay) +#define MSMFB_OVERLAY_UNSET _IOW(MSMFB_IOCTL_MAGIC, 136, unsigned int) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define MSMFB_OVERLAY_PLAY _IOW(MSMFB_IOCTL_MAGIC, 137, struct msmfb_overlay_data) +#define MSMFB_OVERLAY_QUEUE MSMFB_OVERLAY_PLAY +#define MSMFB_GET_PAGE_PROTECTION _IOR(MSMFB_IOCTL_MAGIC, 138, struct mdp_page_protection) +#define MSMFB_SET_PAGE_PROTECTION _IOW(MSMFB_IOCTL_MAGIC, 139, struct mdp_page_protection) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define MSMFB_OVERLAY_GET _IOR(MSMFB_IOCTL_MAGIC, 140, struct mdp_overlay) +#define MSMFB_OVERLAY_PLAY_ENABLE _IOW(MSMFB_IOCTL_MAGIC, 141, unsigned int) +#define MSMFB_OVERLAY_BLT _IOWR(MSMFB_IOCTL_MAGIC, 142, struct msmfb_overlay_blt) +#define MSMFB_OVERLAY_BLT_OFFSET _IOW(MSMFB_IOCTL_MAGIC, 143, unsigned int) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define MSMFB_HISTOGRAM_START _IOR(MSMFB_IOCTL_MAGIC, 144, struct mdp_histogram_start_req) +#define MSMFB_HISTOGRAM_STOP _IOR(MSMFB_IOCTL_MAGIC, 145, unsigned int) +#define MSMFB_NOTIFY_UPDATE _IOWR(MSMFB_IOCTL_MAGIC, 146, unsigned int) +#define MSMFB_OVERLAY_3D _IOWR(MSMFB_IOCTL_MAGIC, 147, struct msmfb_overlay_3d) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define MSMFB_MIXER_INFO _IOWR(MSMFB_IOCTL_MAGIC, 148, struct msmfb_mixer_info_req) +#define MSMFB_OVERLAY_PLAY_WAIT _IOWR(MSMFB_IOCTL_MAGIC, 149, struct msmfb_overlay_data) +#define MSMFB_WRITEBACK_INIT _IO(MSMFB_IOCTL_MAGIC, 150) +#define MSMFB_WRITEBACK_START _IO(MSMFB_IOCTL_MAGIC, 151) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define MSMFB_WRITEBACK_STOP _IO(MSMFB_IOCTL_MAGIC, 152) +#define MSMFB_WRITEBACK_QUEUE_BUFFER _IOW(MSMFB_IOCTL_MAGIC, 153, struct msmfb_data) +#define MSMFB_WRITEBACK_DEQUEUE_BUFFER _IOW(MSMFB_IOCTL_MAGIC, 154, struct msmfb_data) +#define MSMFB_WRITEBACK_TERMINATE _IO(MSMFB_IOCTL_MAGIC, 155) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define MSMFB_MDP_PP _IOWR(MSMFB_IOCTL_MAGIC, 156, struct msmfb_mdp_pp) +#define MSMFB_OVERLAY_VSYNC_CTRL _IOW(MSMFB_IOCTL_MAGIC, 160, unsigned int) +#define MSMFB_VSYNC_CTRL _IOW(MSMFB_IOCTL_MAGIC, 161, unsigned int) +#define MSMFB_BUFFER_SYNC _IOW(MSMFB_IOCTL_MAGIC, 162, struct mdp_buf_sync) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define MSMFB_OVERLAY_COMMIT _IO(MSMFB_IOCTL_MAGIC, 163) +#define MSMFB_DISPLAY_COMMIT _IOW(MSMFB_IOCTL_MAGIC, 164, struct mdp_display_commit) +#define MSMFB_METADATA_SET _IOW(MSMFB_IOCTL_MAGIC, 165, struct msmfb_metadata) +#define MSMFB_METADATA_GET _IOW(MSMFB_IOCTL_MAGIC, 166, struct msmfb_metadata) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define MSMFB_WRITEBACK_SET_MIRRORING_HINT _IOW(MSMFB_IOCTL_MAGIC, 167, unsigned int) +#define MSMFB_ASYNC_BLIT _IOW(MSMFB_IOCTL_MAGIC, 168, unsigned int) +#define MSMFB_OVERLAY_PREPARE _IOWR(MSMFB_IOCTL_MAGIC, 169, struct mdp_overlay_list) +#define MSMFB_LPM_ENABLE _IOWR(MSMFB_IOCTL_MAGIC, 170, unsigned int) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define FB_TYPE_3D_PANEL 0x10101010 +#define MDP_IMGTYPE2_START 0x10000 +#define MSMFB_DRIVER_VERSION 0xF9E8D701 +#define MDSS_GET_MAJOR(rev) ((rev) >> 28) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define MDSS_GET_MINOR(rev) (((rev) >> 16) & 0xFFF) +#define MDSS_GET_STEP(rev) ((rev) & 0xFFFF) +#define MDSS_GET_MAJOR_MINOR(rev) ((rev) >> 16) +#define IS_MDSS_MAJOR_MINOR_SAME(rev1, rev2) (MDSS_GET_MAJOR_MINOR((rev1)) == MDSS_GET_MAJOR_MINOR((rev2))) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define MDSS_MDP_REV(major, minor, step) ((((major) & 0x000F) << 28) | (((minor) & 0x0FFF) << 16) | ((step) & 0xFFFF)) +#define MDSS_MDP_HW_REV_100 MDSS_MDP_REV(1, 0, 0) +#define MDSS_MDP_HW_REV_101 MDSS_MDP_REV(1, 1, 0) +#define MDSS_MDP_HW_REV_101_1 MDSS_MDP_REV(1, 1, 1) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define MDSS_MDP_HW_REV_101_2 MDSS_MDP_REV(1, 1, 2) +#define MDSS_MDP_HW_REV_102 MDSS_MDP_REV(1, 2, 0) +#define MDSS_MDP_HW_REV_102_1 MDSS_MDP_REV(1, 2, 1) +#define MDSS_MDP_HW_REV_103 MDSS_MDP_REV(1, 3, 0) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define MDSS_MDP_HW_REV_103_1 MDSS_MDP_REV(1, 3, 1) +#define MDSS_MDP_HW_REV_105 MDSS_MDP_REV(1, 5, 0) +#define MDSS_MDP_HW_REV_106 MDSS_MDP_REV(1, 6, 0) +#define MDSS_MDP_HW_REV_107 MDSS_MDP_REV(1, 7, 0) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define MDSS_MDP_HW_REV_108 MDSS_MDP_REV(1, 8, 0) +#define MDSS_MDP_HW_REV_109 MDSS_MDP_REV(1, 9, 0) +#define MDSS_MDP_HW_REV_110 MDSS_MDP_REV(1, 10, 0) +#define MDSS_MDP_HW_REV_200 MDSS_MDP_REV(2, 0, 0) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +enum { + NOTIFY_UPDATE_START, + NOTIFY_UPDATE_STOP, + NOTIFY_UPDATE_POWER_OFF, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +enum { + NOTIFY_TYPE_NO_UPDATE, + NOTIFY_TYPE_SUSPEND, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + NOTIFY_TYPE_UPDATE, + NOTIFY_TYPE_BL_UPDATE, +}; +enum { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + MDP_RGB_565, + MDP_XRGB_8888, + MDP_Y_CBCR_H2V2, + MDP_Y_CBCR_H2V2_ADRENO, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + MDP_ARGB_8888, + MDP_RGB_888, + MDP_Y_CRCB_H2V2, + MDP_YCRYCB_H2V1, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + MDP_CBYCRY_H2V1, + MDP_Y_CRCB_H2V1, + MDP_Y_CBCR_H2V1, + MDP_Y_CRCB_H1V2, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + MDP_Y_CBCR_H1V2, + MDP_RGBA_8888, + MDP_BGRA_8888, + MDP_RGBX_8888, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + MDP_Y_CRCB_H2V2_TILE, + MDP_Y_CBCR_H2V2_TILE, + MDP_Y_CR_CB_H2V2, + MDP_Y_CR_CB_GH2V2, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + MDP_Y_CB_CR_H2V2, + MDP_Y_CRCB_H1V1, + MDP_Y_CBCR_H1V1, + MDP_YCRCB_H1V1, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + MDP_YCBCR_H1V1, + MDP_BGR_565, + MDP_BGR_888, + MDP_Y_CBCR_H2V2_VENUS, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + MDP_BGRX_8888, + MDP_RGBA_8888_TILE, + MDP_ARGB_8888_TILE, + MDP_ABGR_8888_TILE, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + MDP_BGRA_8888_TILE, + MDP_RGBX_8888_TILE, + MDP_XRGB_8888_TILE, + MDP_XBGR_8888_TILE, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + MDP_BGRX_8888_TILE, + MDP_YCBYCR_H2V1, + MDP_RGB_565_TILE, + MDP_BGR_565_TILE, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + MDP_ARGB_1555, + MDP_RGBA_5551, + MDP_ARGB_4444, + MDP_RGBA_4444, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + MDP_RGB_565_UBWC, + MDP_RGBA_8888_UBWC, + MDP_Y_CBCR_H2V2_UBWC, + MDP_IMGTYPE_LIMIT, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + MDP_RGB_BORDERFILL, + MDP_FB_FORMAT = MDP_IMGTYPE2_START, + MDP_IMGTYPE_LIMIT2 +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +enum { + PMEM_IMG, + FB_IMG, +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +enum { + HSIC_HUE = 0, + HSIC_SAT, + HSIC_INT, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + HSIC_CON, + NUM_HSIC_PARAM, +}; +#define MDSS_MDP_ROT_ONLY 0x80 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define MDSS_MDP_RIGHT_MIXER 0x100 +#define MDSS_MDP_DUAL_PIPE 0x200 +#define MDP_ROT_NOP 0 +#define MDP_FLIP_LR 0x1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define MDP_FLIP_UD 0x2 +#define MDP_ROT_90 0x4 +#define MDP_ROT_180 (MDP_FLIP_UD|MDP_FLIP_LR) +#define MDP_ROT_270 (MDP_ROT_90|MDP_FLIP_UD|MDP_FLIP_LR) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define MDP_DITHER 0x8 +#define MDP_BLUR 0x10 +#define MDP_BLEND_FG_PREMULT 0x20000 +#define MDP_IS_FG 0x40000 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define MDP_SOLID_FILL 0x00000020 +#define MDP_VPU_PIPE 0x00000040 +#define MDP_DEINTERLACE 0x80000000 +#define MDP_SHARPENING 0x40000000 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define MDP_NO_DMA_BARRIER_START 0x20000000 +#define MDP_NO_DMA_BARRIER_END 0x10000000 +#define MDP_NO_BLIT 0x08000000 +#define MDP_BLIT_WITH_DMA_BARRIERS 0x000 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define MDP_BLIT_WITH_NO_DMA_BARRIERS (MDP_NO_DMA_BARRIER_START | MDP_NO_DMA_BARRIER_END) +#define MDP_BLIT_SRC_GEM 0x04000000 +#define MDP_BLIT_DST_GEM 0x02000000 +#define MDP_BLIT_NON_CACHED 0x01000000 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define MDP_OV_PIPE_SHARE 0x00800000 +#define MDP_DEINTERLACE_ODD 0x00400000 +#define MDP_OV_PLAY_NOWAIT 0x00200000 +#define MDP_SOURCE_ROTATED_90 0x00100000 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define MDP_OVERLAY_PP_CFG_EN 0x00080000 +#define MDP_BACKEND_COMPOSITION 0x00040000 +#define MDP_BORDERFILL_SUPPORTED 0x00010000 +#define MDP_SECURE_OVERLAY_SESSION 0x00008000 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define MDP_SECURE_DISPLAY_OVERLAY_SESSION 0x00002000 +#define MDP_OV_PIPE_FORCE_DMA 0x00004000 +#define MDP_MEMORY_ID_TYPE_FB 0x00001000 +#define MDP_BWC_EN 0x00000400 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define MDP_DECIMATION_EN 0x00000800 +#define MDP_SMP_FORCE_ALLOC 0x00200000 +#define MDP_TRANSP_NOP 0xffffffff +#define MDP_ALPHA_NOP 0xff +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define MDP_FB_PAGE_PROTECTION_NONCACHED (0) +#define MDP_FB_PAGE_PROTECTION_WRITECOMBINE (1) +#define MDP_FB_PAGE_PROTECTION_WRITETHROUGHCACHE (2) +#define MDP_FB_PAGE_PROTECTION_WRITEBACKCACHE (3) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define MDP_FB_PAGE_PROTECTION_WRITEBACKWACACHE (4) +#define MDP_FB_PAGE_PROTECTION_INVALID (5) +#define MDP_NUM_FB_PAGE_PROTECTION_VALUES (5) +struct mdp_rect { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t x; + uint32_t y; + uint32_t w; + uint32_t h; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +struct mdp_img { + uint32_t width; + uint32_t height; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t format; + uint32_t offset; + int memory_id; + uint32_t priv; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +#define MDP_CCS_RGB2YUV 0 +#define MDP_CCS_YUV2RGB 1 +#define MDP_CCS_SIZE 9 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define MDP_BV_SIZE 3 +struct mdp_ccs { + int direction; + uint16_t ccs[MDP_CCS_SIZE]; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint16_t bv[MDP_BV_SIZE]; +}; +struct mdp_csc { + int id; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t csc_mv[9]; + uint32_t csc_pre_bv[3]; + uint32_t csc_post_bv[3]; + uint32_t csc_pre_lv[6]; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t csc_post_lv[6]; +}; +#define MDP_BLIT_REQ_VERSION 2 +struct color { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t r; + uint32_t g; + uint32_t b; + uint32_t alpha; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +struct mdp_blit_req { + struct mdp_img src; + struct mdp_img dst; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + struct mdp_rect src_rect; + struct mdp_rect dst_rect; + struct color const_color; + uint32_t alpha; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t transp_mask; + uint32_t flags; + int sharpening_strength; + uint8_t color_space; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t fps; +}; +struct mdp_blit_req_list { + uint32_t count; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + struct mdp_blit_req req[]; +}; +#define MSMFB_DATA_VERSION 2 +struct msmfb_data { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t offset; + int memory_id; + int id; + uint32_t flags; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t priv; + uint32_t iova; +}; +#define MSMFB_NEW_REQUEST -1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct msmfb_overlay_data { + uint32_t id; + struct msmfb_data data; + uint32_t version_key; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + struct msmfb_data plane1_data; + struct msmfb_data plane2_data; + struct msmfb_data dst_data; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct msmfb_img { + uint32_t width; + uint32_t height; + uint32_t format; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +#define MSMFB_WRITEBACK_DEQUEUE_BLOCKING 0x1 +struct msmfb_writeback_data { + struct msmfb_data buf_info; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + struct msmfb_img img; +}; +#define MDP_PP_OPS_ENABLE 0x1 +#define MDP_PP_OPS_READ 0x2 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define MDP_PP_OPS_WRITE 0x4 +#define MDP_PP_OPS_DISABLE 0x8 +#define MDP_PP_IGC_FLAG_ROM0 0x10 +#define MDP_PP_IGC_FLAG_ROM1 0x20 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define MDP_PP_PA_HUE_ENABLE 0x10 +#define MDP_PP_PA_SAT_ENABLE 0x20 +#define MDP_PP_PA_VAL_ENABLE 0x40 +#define MDP_PP_PA_CONT_ENABLE 0x80 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define MDP_PP_PA_SIX_ZONE_ENABLE 0x100 +#define MDP_PP_PA_SKIN_ENABLE 0x200 +#define MDP_PP_PA_SKY_ENABLE 0x400 +#define MDP_PP_PA_FOL_ENABLE 0x800 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define MDP_PP_PA_HUE_MASK 0x1000 +#define MDP_PP_PA_SAT_MASK 0x2000 +#define MDP_PP_PA_VAL_MASK 0x4000 +#define MDP_PP_PA_CONT_MASK 0x8000 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define MDP_PP_PA_SIX_ZONE_HUE_MASK 0x10000 +#define MDP_PP_PA_SIX_ZONE_SAT_MASK 0x20000 +#define MDP_PP_PA_SIX_ZONE_VAL_MASK 0x40000 +#define MDP_PP_PA_MEM_COL_SKIN_MASK 0x80000 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define MDP_PP_PA_MEM_COL_SKY_MASK 0x100000 +#define MDP_PP_PA_MEM_COL_FOL_MASK 0x200000 +#define MDP_PP_PA_MEM_PROTECT_EN 0x400000 +#define MDP_PP_PA_SAT_ZERO_EXP_EN 0x800000 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define MDSS_PP_DSPP_CFG 0x000 +#define MDSS_PP_SSPP_CFG 0x100 +#define MDSS_PP_LM_CFG 0x200 +#define MDSS_PP_WB_CFG 0x300 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define MDSS_PP_ARG_MASK 0x3C00 +#define MDSS_PP_ARG_NUM 4 +#define MDSS_PP_ARG_SHIFT 10 +#define MDSS_PP_LOCATION_MASK 0x0300 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define MDSS_PP_LOGICAL_MASK 0x00FF +#define MDSS_PP_ADD_ARG(var, arg) ((var) | (0x1 << (MDSS_PP_ARG_SHIFT + (arg)))) +#define PP_ARG(x, var) ((var) & (0x1 << (MDSS_PP_ARG_SHIFT + (x)))) +#define PP_LOCAT(var) ((var) & MDSS_PP_LOCATION_MASK) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define PP_BLOCK(var) ((var) & MDSS_PP_LOGICAL_MASK) +struct mdp_qseed_cfg { + uint32_t table_num; + uint32_t ops; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t len; + uint32_t *data; +}; +struct mdp_sharp_cfg { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t flags; + uint32_t strength; + uint32_t edge_thr; + uint32_t smooth_thr; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t noise_thr; +}; +struct mdp_qseed_cfg_data { + uint32_t block; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + struct mdp_qseed_cfg qseed_data; +}; +#define MDP_OVERLAY_PP_CSC_CFG 0x1 +#define MDP_OVERLAY_PP_QSEED_CFG 0x2 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define MDP_OVERLAY_PP_PA_CFG 0x4 +#define MDP_OVERLAY_PP_IGC_CFG 0x8 +#define MDP_OVERLAY_PP_SHARP_CFG 0x10 +#define MDP_OVERLAY_PP_HIST_CFG 0x20 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define MDP_OVERLAY_PP_HIST_LUT_CFG 0x40 +#define MDP_OVERLAY_PP_PA_V2_CFG 0x80 +#define MDP_CSC_FLAG_ENABLE 0x1 +#define MDP_CSC_FLAG_YUV_IN 0x2 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define MDP_CSC_FLAG_YUV_OUT 0x4 +struct mdp_csc_cfg { + uint32_t flags; + uint32_t csc_mv[9]; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t csc_pre_bv[3]; + uint32_t csc_post_bv[3]; + uint32_t csc_pre_lv[6]; + uint32_t csc_post_lv[6]; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +struct mdp_csc_cfg_data { + uint32_t block; + struct mdp_csc_cfg csc_data; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +struct mdp_pa_cfg { + uint32_t flags; + uint32_t hue_adj; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t sat_adj; + uint32_t val_adj; + uint32_t cont_adj; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct mdp_pa_mem_col_cfg { + uint32_t color_adjust_p0; + uint32_t color_adjust_p1; + uint32_t hue_region; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t sat_region; + uint32_t val_region; +}; +#define MDP_SIX_ZONE_LUT_SIZE 384 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct mdp_pa_v2_data { + uint32_t flags; + uint32_t global_hue_adj; + uint32_t global_sat_adj; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t global_val_adj; + uint32_t global_cont_adj; + struct mdp_pa_mem_col_cfg skin_cfg; + struct mdp_pa_mem_col_cfg sky_cfg; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + struct mdp_pa_mem_col_cfg fol_cfg; + uint32_t six_zone_len; + uint32_t six_zone_thresh; + uint32_t *six_zone_curve_p0; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t *six_zone_curve_p1; +}; +struct mdp_igc_lut_data { + uint32_t block; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t len, ops; + uint32_t *c0_c1_data; + uint32_t *c2_data; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct mdp_histogram_cfg { + uint32_t ops; + uint32_t block; + uint8_t frame_cnt; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint8_t bit_mask; + uint16_t num_bins; +}; +struct mdp_hist_lut_data { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t block; + uint32_t ops; + uint32_t len; + uint32_t *data; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +struct mdp_overlay_pp_params { + uint32_t config_ops; + struct mdp_csc_cfg csc_cfg; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + struct mdp_qseed_cfg qseed_cfg[2]; + struct mdp_pa_cfg pa_cfg; + struct mdp_pa_v2_data pa_v2_cfg; + struct mdp_igc_lut_data igc_cfg; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + struct mdp_sharp_cfg sharp_cfg; + struct mdp_histogram_cfg hist_cfg; + struct mdp_hist_lut_data hist_lut_cfg; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +enum mdss_mdp_blend_op { + BLEND_OP_NOT_DEFINED = 0, + BLEND_OP_OPAQUE, + BLEND_OP_PREMULTIPLIED, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + BLEND_OP_COVERAGE, + BLEND_OP_MAX, +}; +#define MAX_PLANES 4 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct mdp_scale_data { + uint8_t enable_pxl_ext; + int init_phase_x[MAX_PLANES]; + int phase_step_x[MAX_PLANES]; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + int init_phase_y[MAX_PLANES]; + int phase_step_y[MAX_PLANES]; + int num_ext_pxls_left[MAX_PLANES]; + int num_ext_pxls_right[MAX_PLANES]; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + int num_ext_pxls_top[MAX_PLANES]; + int num_ext_pxls_btm[MAX_PLANES]; + int left_ftch[MAX_PLANES]; + int left_rpt[MAX_PLANES]; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + int right_ftch[MAX_PLANES]; + int right_rpt[MAX_PLANES]; + int top_rpt[MAX_PLANES]; + int btm_rpt[MAX_PLANES]; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + int top_ftch[MAX_PLANES]; + int btm_ftch[MAX_PLANES]; + uint32_t roi_w[MAX_PLANES]; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +enum mdp_overlay_pipe_type { + PIPE_TYPE_AUTO = 0, + PIPE_TYPE_VIG, + PIPE_TYPE_RGB, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + PIPE_TYPE_DMA, + PIPE_TYPE_CURSOR, + PIPE_TYPE_MAX, +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct mdp_overlay { + struct msmfb_img src; + struct mdp_rect src_rect; + struct mdp_rect dst_rect; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t z_order; + uint32_t is_fg; + uint32_t alpha; + uint32_t blend_op; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t transp_mask; + uint32_t flags; + uint32_t pipe_type; + uint32_t id; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint8_t priority; + uint32_t user_data[6]; + uint32_t bg_color; + uint8_t horz_deci; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint8_t vert_deci; + struct mdp_overlay_pp_params overlay_pp_cfg; + struct mdp_scale_data scale; + uint8_t color_space; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +struct msmfb_overlay_3d { + uint32_t is_3d; + uint32_t width; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t height; +}; +struct msmfb_overlay_blt { + uint32_t enable; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t offset; + uint32_t width; + uint32_t height; + uint32_t bpp; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +struct mdp_histogram { + uint32_t frame_cnt; + uint32_t bin_cnt; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t *r; + uint32_t *g; + uint32_t *b; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define MISR_CRC_BATCH_SIZE 32 +enum { + DISPLAY_MISR_EDP, + DISPLAY_MISR_DSI0, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + DISPLAY_MISR_DSI1, + DISPLAY_MISR_HDMI, + DISPLAY_MISR_LCDC, + DISPLAY_MISR_MDP, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + DISPLAY_MISR_ATV, + DISPLAY_MISR_DSI_CMD, + DISPLAY_MISR_MAX +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +enum { + MISR_OP_NONE, + MISR_OP_SFM, + MISR_OP_MFM, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + MISR_OP_BM, + MISR_OP_MAX +}; +struct mdp_misr { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t block_id; + uint32_t frame_count; + uint32_t crc_op_mode; + uint32_t crc_value[MISR_CRC_BATCH_SIZE]; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +enum { + MDP_BLOCK_RESERVED = 0, + MDP_BLOCK_OVERLAY_0, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + MDP_BLOCK_OVERLAY_1, + MDP_BLOCK_VG_1, + MDP_BLOCK_VG_2, + MDP_BLOCK_RGB_1, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + MDP_BLOCK_RGB_2, + MDP_BLOCK_DMA_P, + MDP_BLOCK_DMA_S, + MDP_BLOCK_DMA_E, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + MDP_BLOCK_OVERLAY_2, + MDP_LOGICAL_BLOCK_DISP_0 = 0x10, + MDP_LOGICAL_BLOCK_DISP_1, + MDP_LOGICAL_BLOCK_DISP_2, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + MDP_BLOCK_MAX, +}; +struct mdp_histogram_start_req { + uint32_t block; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint8_t frame_cnt; + uint8_t bit_mask; + uint16_t num_bins; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct mdp_histogram_data { + uint32_t block; + uint32_t bin_cnt; + uint32_t *c0; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t *c1; + uint32_t *c2; + uint32_t *extra_info; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct mdp_pcc_coeff { + uint32_t c, r, g, b, rr, gg, bb, rg, gb, rb, rgb_0, rgb_1; +}; +struct mdp_pcc_cfg_data { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t block; + uint32_t ops; + struct mdp_pcc_coeff r, g, b; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define MDP_GAMUT_TABLE_NUM 8 +enum { + mdp_lut_igc, + mdp_lut_pgc, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + mdp_lut_hist, + mdp_lut_max, +}; +struct mdp_ar_gc_lut_data { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t x_start; + uint32_t slope; + uint32_t offset; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct mdp_pgc_lut_data { + uint32_t block; + uint32_t flags; + uint8_t num_r_stages; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint8_t num_g_stages; + uint8_t num_b_stages; + struct mdp_ar_gc_lut_data *r_data; + struct mdp_ar_gc_lut_data *g_data; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + struct mdp_ar_gc_lut_data *b_data; +}; +struct mdp_lut_cfg_data { + uint32_t lut_type; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + union { + struct mdp_igc_lut_data igc_lut_data; + struct mdp_pgc_lut_data pgc_lut_data; + struct mdp_hist_lut_data hist_lut_data; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + } data; +}; +struct mdp_bl_scale_data { + uint32_t min_lvl; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t scale; +}; +struct mdp_pa_cfg_data { + uint32_t block; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + struct mdp_pa_cfg pa_data; +}; +struct mdp_pa_v2_cfg_data { + uint32_t block; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + struct mdp_pa_v2_data pa_v2_data; +}; +struct mdp_dither_cfg_data { + uint32_t block; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t flags; + uint32_t g_y_depth; + uint32_t r_cr_depth; + uint32_t b_cb_depth; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +struct mdp_gamut_cfg_data { + uint32_t block; + uint32_t flags; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t gamut_first; + uint32_t tbl_size[MDP_GAMUT_TABLE_NUM]; + uint16_t *r_tbl[MDP_GAMUT_TABLE_NUM]; + uint16_t *g_tbl[MDP_GAMUT_TABLE_NUM]; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint16_t *b_tbl[MDP_GAMUT_TABLE_NUM]; +}; +struct mdp_calib_config_data { + uint32_t ops; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t addr; + uint32_t data; +}; +struct mdp_calib_config_buffer { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t ops; + uint32_t size; + uint32_t *buffer; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct mdp_calib_dcm_state { + uint32_t ops; + uint32_t dcm_state; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct mdp_pp_init_data { + uint32_t init_request; +}; +enum { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + MDP_PP_DISABLE, + MDP_PP_ENABLE, +}; +enum { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + DCM_UNINIT, + DCM_UNBLANK, + DCM_ENTER, + DCM_EXIT, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + DCM_BLANK, + DTM_ENTER, + DTM_EXIT, +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define MDSS_PP_SPLIT_LEFT_ONLY 0x10000000 +#define MDSS_PP_SPLIT_RIGHT_ONLY 0x20000000 +#define MDSS_PP_SPLIT_MASK 0x30000000 +#define MDSS_MAX_BL_BRIGHTNESS 255 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define AD_BL_LIN_LEN 256 +#define AD_BL_ATT_LUT_LEN 33 +#define MDSS_AD_MODE_AUTO_BL 0x0 +#define MDSS_AD_MODE_AUTO_STR 0x1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define MDSS_AD_MODE_TARG_STR 0x3 +#define MDSS_AD_MODE_MAN_STR 0x7 +#define MDSS_AD_MODE_CALIB 0xF +#define MDP_PP_AD_INIT 0x10 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define MDP_PP_AD_CFG 0x20 +struct mdss_ad_init { + uint32_t asym_lut[33]; + uint32_t color_corr_lut[33]; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint8_t i_control[2]; + uint16_t black_lvl; + uint16_t white_lvl; + uint8_t var; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint8_t limit_ampl; + uint8_t i_dither; + uint8_t slope_max; + uint8_t slope_min; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint8_t dither_ctl; + uint8_t format; + uint8_t auto_size; + uint16_t frame_w; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint16_t frame_h; + uint8_t logo_v; + uint8_t logo_h; + uint32_t alpha; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t alpha_base; + uint32_t bl_lin_len; + uint32_t bl_att_len; + uint32_t *bl_lin; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t *bl_lin_inv; + uint32_t *bl_att_lut; +}; +#define MDSS_AD_BL_CTRL_MODE_EN 1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define MDSS_AD_BL_CTRL_MODE_DIS 0 +struct mdss_ad_cfg { + uint32_t mode; + uint32_t al_calib_lut[33]; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint16_t backlight_min; + uint16_t backlight_max; + uint16_t backlight_scale; + uint16_t amb_light_min; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint16_t filter[2]; + uint16_t calib[4]; + uint8_t strength_limit; + uint8_t t_filter_recursion; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint16_t stab_itr; + uint32_t bl_ctrl_mode; +}; +struct mdss_ad_init_cfg { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t ops; + union { + struct mdss_ad_init init; + struct mdss_ad_cfg cfg; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + } params; +}; +struct mdss_ad_input { + uint32_t mode; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + union { + uint32_t amb_light; + uint32_t strength; + uint32_t calib_bl; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + } in; + uint32_t output; +}; +#define MDSS_CALIB_MODE_BL 0x1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct mdss_calib_cfg { + uint32_t ops; + uint32_t calib_mask; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +enum { + mdp_op_pcc_cfg, + mdp_op_csc_cfg, + mdp_op_lut_cfg, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + mdp_op_qseed_cfg, + mdp_bl_scale_cfg, + mdp_op_pa_cfg, + mdp_op_pa_v2_cfg, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + mdp_op_dither_cfg, + mdp_op_gamut_cfg, + mdp_op_calib_cfg, + mdp_op_ad_cfg, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + mdp_op_ad_input, + mdp_op_calib_mode, + mdp_op_calib_buffer, + mdp_op_calib_dcm_state, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + mdp_op_max, + mdp_op_pp_init_cfg, +}; +enum { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + WB_FORMAT_NV12, + WB_FORMAT_RGB_565, + WB_FORMAT_RGB_888, + WB_FORMAT_xRGB_8888, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + WB_FORMAT_ARGB_8888, + WB_FORMAT_BGRA_8888, + WB_FORMAT_BGRX_8888, + WB_FORMAT_ARGB_8888_INPUT_ALPHA +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +struct msmfb_mdp_pp { + uint32_t op; + union { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + struct mdp_pcc_cfg_data pcc_cfg_data; + struct mdp_csc_cfg_data csc_cfg_data; + struct mdp_lut_cfg_data lut_cfg_data; + struct mdp_qseed_cfg_data qseed_cfg_data; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + struct mdp_bl_scale_data bl_scale_data; + struct mdp_pa_cfg_data pa_cfg_data; + struct mdp_pa_v2_cfg_data pa_v2_cfg_data; + struct mdp_dither_cfg_data dither_cfg_data; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + struct mdp_gamut_cfg_data gamut_cfg_data; + struct mdp_calib_config_data calib_cfg; + struct mdss_ad_init_cfg ad_init_cfg; + struct mdss_calib_cfg mdss_calib_cfg; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + struct mdss_ad_input ad_input; + struct mdp_calib_config_buffer calib_buffer; + struct mdp_calib_dcm_state calib_dcm; + struct mdp_pp_init_data init_data; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + } data; +}; +#define FB_METADATA_VIDEO_INFO_CODE_SUPPORT 1 +enum { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + metadata_op_none, + metadata_op_base_blend, + metadata_op_frame_rate, + metadata_op_vic, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + metadata_op_wb_format, + metadata_op_wb_secure, + metadata_op_get_caps, + metadata_op_crc, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + metadata_op_get_ion_fd, + metadata_op_max +}; +struct mdp_blend_cfg { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t is_premultiplied; +}; +struct mdp_mixer_cfg { + uint32_t writeback_format; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t alpha; +}; +struct mdss_hw_caps { + uint32_t mdp_rev; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint8_t rgb_pipes; + uint8_t vig_pipes; + uint8_t dma_pipes; + uint8_t max_smp_cnt; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint8_t smp_per_pipe; + uint32_t features; +}; +struct msmfb_metadata { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t op; + uint32_t flags; + union { + struct mdp_misr misr_request; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + struct mdp_blend_cfg blend_cfg; + struct mdp_mixer_cfg mixer_cfg; + uint32_t panel_frame_rate; + uint32_t video_info_code; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + struct mdss_hw_caps caps; + uint8_t secure_en; + int fbmem_ionfd; + } data; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +#define MDP_MAX_FENCE_FD 32 +#define MDP_BUF_SYNC_FLAG_WAIT 1 +#define MDP_BUF_SYNC_FLAG_RETIRE_FENCE 0x10 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct mdp_buf_sync { + uint32_t flags; + uint32_t acq_fen_fd_cnt; + uint32_t session_id; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + int *acq_fen_fd; + int *rel_fen_fd; + int *retire_fen_fd; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct mdp_async_blit_req_list { + struct mdp_buf_sync sync; + uint32_t count; + struct mdp_blit_req req[]; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +#define MDP_DISPLAY_COMMIT_OVERLAY 1 +struct mdp_display_commit { + uint32_t flags; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t wait_for_finish; + struct fb_var_screeninfo var; + struct mdp_rect l_roi; + struct mdp_rect r_roi; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +struct mdp_overlay_list { + uint32_t num_overlays; + struct mdp_overlay **overlay_list; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t flags; + uint32_t processed_overlays; +}; +struct mdp_page_protection { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t page_protection; +}; +struct mdp_mixer_info { + int pndx; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + int pnum; + int ptype; + int mixer_num; + int z_order; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +#define MAX_PIPE_PER_MIXER 7 +struct msmfb_mixer_info_req { + int mixer_num; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + int cnt; + struct mdp_mixer_info info[MAX_PIPE_PER_MIXER]; +}; +enum { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + DISPLAY_SUBSYSTEM_ID, + ROTATOR_SUBSYSTEM_ID, +}; +enum { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + MDP_IOMMU_DOMAIN_CP, + MDP_IOMMU_DOMAIN_NS, +}; +enum { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + MDP_WRITEBACK_MIRROR_OFF, + MDP_WRITEBACK_MIRROR_ON, + MDP_WRITEBACK_MIRROR_PAUSE, + MDP_WRITEBACK_MIRROR_RESUME, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +enum { + MDP_CSC_ITU_R_601, + MDP_CSC_ITU_R_601_FR, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + MDP_CSC_ITU_R_709, +}; +#endif + diff --git a/kernel-headers/linux/msm_rmnet.h b/kernel-headers/linux/msm_rmnet.h new file mode 100644 index 0000000..0e415f5 --- /dev/null +++ b/kernel-headers/linux/msm_rmnet.h @@ -0,0 +1,155 @@ +/**************************************************************************** + **************************************************************************** + *** + *** This header was automatically generated from a Linux kernel header + *** of the same name, to make information necessary for userspace to + *** call into the kernel available to libc. It contains only constants, + *** structures, and macros generated from the original header, and thus, + *** contains no copyrightable information. + *** + *** To edit the content of this header, modify the corresponding + *** source file (e.g. under external/kernel-headers/original/) then + *** run bionic/libc/kernel/tools/update_all.py + *** + *** Any manual change here will be lost the next time this script will + *** be run. You've been warned! + *** + **************************************************************************** + ****************************************************************************/ +#ifndef _UAPI_MSM_RMNET_H_ +#define _UAPI_MSM_RMNET_H_ +#define RMNET_MODE_NONE (0x00) +#define RMNET_MODE_LLP_ETH (0x01) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define RMNET_MODE_LLP_IP (0x02) +#define RMNET_MODE_QOS (0x04) +#define RMNET_MODE_MASK (RMNET_MODE_LLP_ETH | RMNET_MODE_LLP_IP | RMNET_MODE_QOS) +#define RMNET_IS_MODE_QOS(mode) ((mode & RMNET_MODE_QOS) == RMNET_MODE_QOS) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define RMNET_IS_MODE_IP(mode) ((mode & RMNET_MODE_LLP_IP) == RMNET_MODE_LLP_IP) +enum rmnet_ioctl_cmds_e { + RMNET_IOCTL_SET_LLP_ETHERNET = 0x000089F1, + RMNET_IOCTL_SET_LLP_IP = 0x000089F2, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + RMNET_IOCTL_GET_LLP = 0x000089F3, + RMNET_IOCTL_SET_QOS_ENABLE = 0x000089F4, + RMNET_IOCTL_SET_QOS_DISABLE = 0x000089F5, + RMNET_IOCTL_GET_QOS = 0x000089F6, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + RMNET_IOCTL_GET_OPMODE = 0x000089F7, + RMNET_IOCTL_OPEN = 0x000089F8, + RMNET_IOCTL_CLOSE = 0x000089F9, + RMNET_IOCTL_FLOW_ENABLE = 0x000089FA, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + RMNET_IOCTL_FLOW_DISABLE = 0x000089FB, + RMNET_IOCTL_FLOW_SET_HNDL = 0x000089FC, + RMNET_IOCTL_EXTENDED = 0x000089FD, + RMNET_IOCTL_MAX +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +enum rmnet_ioctl_extended_cmds_e { + RMNET_IOCTL_GET_SUPPORTED_FEATURES = 0x0000, + RMNET_IOCTL_SET_MRU = 0x0001, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + RMNET_IOCTL_GET_MRU = 0x0002, + RMNET_IOCTL_GET_EPID = 0x0003, + RMNET_IOCTL_GET_DRIVER_NAME = 0x0004, + RMNET_IOCTL_ADD_MUX_CHANNEL = 0x0005, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + RMNET_IOCTL_SET_EGRESS_DATA_FORMAT = 0x0006, + RMNET_IOCTL_SET_INGRESS_DATA_FORMAT = 0x0007, + RMNET_IOCTL_SET_AGGREGATION_COUNT = 0x0008, + RMNET_IOCTL_GET_AGGREGATION_COUNT = 0x0009, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + RMNET_IOCTL_SET_AGGREGATION_SIZE = 0x000A, + RMNET_IOCTL_GET_AGGREGATION_SIZE = 0x000B, + RMNET_IOCTL_FLOW_CONTROL = 0x000C, + RMNET_IOCTL_GET_DFLT_CONTROL_CHANNEL = 0x000D, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + RMNET_IOCTL_GET_HWSW_MAP = 0x000E, + RMNET_IOCTL_SET_RX_HEADROOM = 0x000F, + RMNET_IOCTL_GET_EP_PAIR = 0x0010, + RMNET_IOCTL_SET_QOS_VERSION = 0x0011, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + RMNET_IOCTL_GET_QOS_VERSION = 0x0012, + RMNET_IOCTL_GET_SUPPORTED_QOS_MODES = 0x0013, + RMNET_IOCTL_SET_SLEEP_STATE = 0x0014, + RMNET_IOCTL_SET_XLAT_DEV_INFO = 0x0015, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + RMNET_IOCTL_EXTENDED_MAX = 0x0016 +}; +#define RMNET_IOCTL_FEAT_NOTIFY_MUX_CHANNEL (1<<0) +#define RMNET_IOCTL_FEAT_SET_EGRESS_DATA_FORMAT (1<<1) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define RMNET_IOCTL_FEAT_SET_INGRESS_DATA_FORMAT (1<<2) +#define RMNET_IOCTL_FEAT_SET_AGGREGATION_COUNT (1<<3) +#define RMNET_IOCTL_FEAT_GET_AGGREGATION_COUNT (1<<4) +#define RMNET_IOCTL_FEAT_SET_AGGREGATION_SIZE (1<<5) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define RMNET_IOCTL_FEAT_GET_AGGREGATION_SIZE (1<<6) +#define RMNET_IOCTL_FEAT_FLOW_CONTROL (1<<7) +#define RMNET_IOCTL_FEAT_GET_DFLT_CONTROL_CHANNEL (1<<8) +#define RMNET_IOCTL_FEAT_GET_HWSW_MAP (1<<9) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define RMNET_IOCTL_EGRESS_FORMAT_MAP (1<<1) +#define RMNET_IOCTL_EGRESS_FORMAT_AGGREGATION (1<<2) +#define RMNET_IOCTL_EGRESS_FORMAT_MUXING (1<<3) +#define RMNET_IOCTL_EGRESS_FORMAT_CHECKSUM (1<<4) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define RMNET_IOCTL_INGRESS_FORMAT_MAP (1<<1) +#define RMNET_IOCTL_INGRESS_FORMAT_DEAGGREGATION (1<<2) +#define RMNET_IOCTL_INGRESS_FORMAT_DEMUXING (1<<3) +#define RMNET_IOCTL_INGRESS_FORMAT_CHECKSUM (1<<4) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#ifndef IFNAMSIZ +#define IFNAMSIZ 16 +#endif +struct rmnet_ioctl_extended_s { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t extended_ioctl; + union { + uint32_t data; + int8_t if_name[IFNAMSIZ]; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + struct { + uint32_t mux_id; + int8_t vchannel_name[IFNAMSIZ]; + } rmnet_mux_val; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + struct { + uint8_t flow_mode; + uint8_t mux_id; + } flow_control_prop; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + struct { + uint32_t consumer_pipe_num; + uint32_t producer_pipe_num; + } ipa_ep_pair; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + } u; +}; +struct rmnet_ioctl_data_s { + union { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t operation_mode; + uint32_t tcm_handle; + } u; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define RMNET_IOCTL_QOS_MODE_6 (1<<0) +#define RMNET_IOCTL_QOS_MODE_8 (1<<1) +#define QMI_QOS_HDR_S __attribute((__packed__)) qmi_qos_hdr_s +struct QMI_QOS_HDR_S { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned char version; + unsigned char flags; + uint32_t flow_id; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct qmi_qos_hdr8_s { + struct QMI_QOS_HDR_S hdr; + uint8_t reserved[2]; +} __attribute((__packed__)); +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#endif + diff --git a/kernel-headers/linux/msm_rotator.h b/kernel-headers/linux/msm_rotator.h new file mode 100644 index 0000000..a840a8d --- /dev/null +++ b/kernel-headers/linux/msm_rotator.h @@ -0,0 +1,76 @@ +/**************************************************************************** + **************************************************************************** + *** + *** This header was automatically generated from a Linux kernel header + *** of the same name, to make information necessary for userspace to + *** call into the kernel available to libc. It contains only constants, + *** structures, and macros generated from the original header, and thus, + *** contains no copyrightable information. + *** + *** To edit the content of this header, modify the corresponding + *** source file (e.g. under external/kernel-headers/original/) then + *** run bionic/libc/kernel/tools/update_all.py + *** + *** Any manual change here will be lost the next time this script will + *** be run. You've been warned! + *** + **************************************************************************** + ****************************************************************************/ +#ifndef _UAPI__MSM_ROTATOR_H__ +#define _UAPI__MSM_ROTATOR_H__ +#include <linux/types.h> +#include <linux/msm_mdp.h> +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define MSM_ROTATOR_IOCTL_MAGIC 'R' +#define MSM_ROTATOR_IOCTL_START _IOWR(MSM_ROTATOR_IOCTL_MAGIC, 1, struct msm_rotator_img_info) +#define MSM_ROTATOR_IOCTL_ROTATE _IOW(MSM_ROTATOR_IOCTL_MAGIC, 2, struct msm_rotator_data_info) +#define MSM_ROTATOR_IOCTL_FINISH _IOW(MSM_ROTATOR_IOCTL_MAGIC, 3, int) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define ROTATOR_VERSION_01 0xA5B4C301 +enum rotator_clk_type { + ROTATOR_CORE_CLK, + ROTATOR_PCLK, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + ROTATOR_IMEM_CLK +}; +struct msm_rotator_img_info { + unsigned int session_id; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + struct msmfb_img src; + struct msmfb_img dst; + struct mdp_rect src_rect; + unsigned int dst_x; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned int dst_y; + unsigned char rotations; + int enable; + unsigned int downscale_ratio; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned int secure; +}; +struct msm_rotator_data_info { + int session_id; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + struct msmfb_data src; + struct msmfb_data dst; + unsigned int version_key; + struct msmfb_data src_chroma; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + struct msmfb_data dst_chroma; +}; +struct msm_rot_clocks { + const char *clk_name; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + enum rotator_clk_type clk_type; + unsigned int clk_rate; +}; +struct msm_rotator_platform_data { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned int number_of_clocks; + unsigned int hardware_version_number; + struct msm_rot_clocks *rotator_clks; + char rot_iommu_split_domain; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +#endif + diff --git a/kernel-headers/linux/msm_thermal_ioctl.h b/kernel-headers/linux/msm_thermal_ioctl.h new file mode 100644 index 0000000..ec715e0 --- /dev/null +++ b/kernel-headers/linux/msm_thermal_ioctl.h @@ -0,0 +1,76 @@ +/**************************************************************************** + **************************************************************************** + *** + *** This header was automatically generated from a Linux kernel header + *** of the same name, to make information necessary for userspace to + *** call into the kernel available to libc. It contains only constants, + *** structures, and macros generated from the original header, and thus, + *** contains no copyrightable information. + *** + *** To edit the content of this header, modify the corresponding + *** source file (e.g. under external/kernel-headers/original/) then + *** run bionic/libc/kernel/tools/update_all.py + *** + *** Any manual change here will be lost the next time this script will + *** be run. You've been warned! + *** + **************************************************************************** + ****************************************************************************/ +#ifndef _MSM_THERMAL_IOCTL_H +#define _MSM_THERMAL_IOCTL_H +#include <linux/ioctl.h> +#define MSM_THERMAL_IOCTL_NAME "msm_thermal_query" +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define MSM_IOCTL_FREQ_SIZE 16 +struct __attribute__((__packed__)) cpu_freq_arg { + uint32_t cpu_num; + uint32_t freq_req; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +struct __attribute__((__packed__)) clock_plan_arg { + uint32_t cluster_num; + uint32_t freq_table_len; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t set_idx; + unsigned int freq_table[MSM_IOCTL_FREQ_SIZE]; +}; +struct __attribute__((__packed__)) voltage_plan_arg { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t cluster_num; + uint32_t voltage_table_len; + uint32_t set_idx; + uint32_t voltage_table[MSM_IOCTL_FREQ_SIZE]; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +struct __attribute__((__packed__)) msm_thermal_ioctl { + uint32_t size; + union { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + struct cpu_freq_arg cpu_freq; + struct clock_plan_arg clock_freq; + struct voltage_plan_arg voltage; + }; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +enum { + MSM_SET_CPU_MAX_FREQ = 0x00, + MSM_SET_CPU_MIN_FREQ = 0x01, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + MSM_SET_CLUSTER_MAX_FREQ = 0x02, + MSM_SET_CLUSTER_MIN_FREQ = 0x03, + MSM_GET_CLUSTER_FREQ_PLAN = 0x04, + MSM_GET_CLUSTER_VOLTAGE_PLAN = 0x05, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + MSM_CMD_MAX_NR, +}; +#define MSM_THERMAL_MAGIC_NUM 0xCA +#define MSM_THERMAL_SET_CPU_MAX_FREQUENCY _IOW(MSM_THERMAL_MAGIC_NUM, MSM_SET_CPU_MAX_FREQ, struct msm_thermal_ioctl) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define MSM_THERMAL_SET_CPU_MIN_FREQUENCY _IOW(MSM_THERMAL_MAGIC_NUM, MSM_SET_CPU_MIN_FREQ, struct msm_thermal_ioctl) +#define MSM_THERMAL_SET_CLUSTER_MAX_FREQUENCY _IOW(MSM_THERMAL_MAGIC_NUM, MSM_SET_CLUSTER_MAX_FREQ, struct msm_thermal_ioctl) +#define MSM_THERMAL_SET_CLUSTER_MIN_FREQUENCY _IOW(MSM_THERMAL_MAGIC_NUM, MSM_SET_CLUSTER_MIN_FREQ, struct msm_thermal_ioctl) +#define MSM_THERMAL_GET_CLUSTER_FREQUENCY_PLAN _IOR(MSM_THERMAL_MAGIC_NUM, MSM_GET_CLUSTER_FREQ_PLAN, struct msm_thermal_ioctl) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define MSM_THERMAL_GET_CLUSTER_VOLTAGE_PLAN _IOR(MSM_THERMAL_MAGIC_NUM, MSM_GET_CLUSTER_VOLTAGE_PLAN, struct msm_thermal_ioctl) +#endif + diff --git a/kernel-headers/linux/msm_vidc_dec.h b/kernel-headers/linux/msm_vidc_dec.h new file mode 100644 index 0000000..0bf0798 --- /dev/null +++ b/kernel-headers/linux/msm_vidc_dec.h @@ -0,0 +1,571 @@ +/**************************************************************************** + **************************************************************************** + *** + *** This header was automatically generated from a Linux kernel header + *** of the same name, to make information necessary for userspace to + *** call into the kernel available to libc. It contains only constants, + *** structures, and macros generated from the original header, and thus, + *** contains no copyrightable information. + *** + *** To edit the content of this header, modify the corresponding + *** source file (e.g. under external/kernel-headers/original/) then + *** run bionic/libc/kernel/tools/update_all.py + *** + *** Any manual change here will be lost the next time this script will + *** be run. You've been warned! + *** + **************************************************************************** + ****************************************************************************/ +#ifndef _UAPI_MSM_VIDC_DEC_H_ +#define _UAPI_MSM_VIDC_DEC_H_ +#include <linux/types.h> +#include <linux/ioctl.h> +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VDEC_S_BASE 0x40000000 +#define VDEC_S_SUCCESS (VDEC_S_BASE) +#define VDEC_S_EFAIL (VDEC_S_BASE + 1) +#define VDEC_S_EFATAL (VDEC_S_BASE + 2) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VDEC_S_EBADPARAM (VDEC_S_BASE + 3) +#define VDEC_S_EINVALSTATE (VDEC_S_BASE + 4) +#define VDEC_S_ENOSWRES (VDEC_S_BASE + 5) +#define VDEC_S_ENOHWRES (VDEC_S_BASE + 6) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VDEC_S_EINVALCMD (VDEC_S_BASE + 7) +#define VDEC_S_ETIMEOUT (VDEC_S_BASE + 8) +#define VDEC_S_ENOPREREQ (VDEC_S_BASE + 9) +#define VDEC_S_ECMDQFULL (VDEC_S_BASE + 10) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VDEC_S_ENOTSUPP (VDEC_S_BASE + 11) +#define VDEC_S_ENOTIMPL (VDEC_S_BASE + 12) +#define VDEC_S_BUSY (VDEC_S_BASE + 13) +#define VDEC_S_INPUT_BITSTREAM_ERR (VDEC_S_BASE + 14) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VDEC_INTF_VER 1 +#define VDEC_MSG_BASE 0x0000000 +#define VDEC_MSG_INVALID (VDEC_MSG_BASE + 0) +#define VDEC_MSG_RESP_INPUT_BUFFER_DONE (VDEC_MSG_BASE + 1) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VDEC_MSG_RESP_OUTPUT_BUFFER_DONE (VDEC_MSG_BASE + 2) +#define VDEC_MSG_RESP_INPUT_FLUSHED (VDEC_MSG_BASE + 3) +#define VDEC_MSG_RESP_OUTPUT_FLUSHED (VDEC_MSG_BASE + 4) +#define VDEC_MSG_RESP_FLUSH_INPUT_DONE (VDEC_MSG_BASE + 5) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VDEC_MSG_RESP_FLUSH_OUTPUT_DONE (VDEC_MSG_BASE + 6) +#define VDEC_MSG_RESP_START_DONE (VDEC_MSG_BASE + 7) +#define VDEC_MSG_RESP_STOP_DONE (VDEC_MSG_BASE + 8) +#define VDEC_MSG_RESP_PAUSE_DONE (VDEC_MSG_BASE + 9) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VDEC_MSG_RESP_RESUME_DONE (VDEC_MSG_BASE + 10) +#define VDEC_MSG_RESP_RESOURCE_LOADED (VDEC_MSG_BASE + 11) +#define VDEC_EVT_RESOURCES_LOST (VDEC_MSG_BASE + 12) +#define VDEC_MSG_EVT_CONFIG_CHANGED (VDEC_MSG_BASE + 13) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VDEC_MSG_EVT_HW_ERROR (VDEC_MSG_BASE + 14) +#define VDEC_MSG_EVT_INFO_CONFIG_CHANGED (VDEC_MSG_BASE + 15) +#define VDEC_MSG_EVT_INFO_FIELD_DROPPED (VDEC_MSG_BASE + 16) +#define VDEC_MSG_EVT_HW_OVERLOAD (VDEC_MSG_BASE + 17) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VDEC_MSG_EVT_MAX_CLIENTS (VDEC_MSG_BASE + 18) +#define VDEC_MSG_EVT_HW_UNSUPPORTED (VDEC_MSG_BASE + 19) +#define VDEC_BUFFERFLAG_EOS 0x00000001 +#define VDEC_BUFFERFLAG_DECODEONLY 0x00000004 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VDEC_BUFFERFLAG_DATACORRUPT 0x00000008 +#define VDEC_BUFFERFLAG_ENDOFFRAME 0x00000010 +#define VDEC_BUFFERFLAG_SYNCFRAME 0x00000020 +#define VDEC_BUFFERFLAG_EXTRADATA 0x00000040 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VDEC_BUFFERFLAG_CODECCONFIG 0x00000080 +#define VDEC_EXTRADATA_NONE 0x001 +#define VDEC_EXTRADATA_QP 0x004 +#define VDEC_EXTRADATA_MB_ERROR_MAP 0x008 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VDEC_EXTRADATA_SEI 0x010 +#define VDEC_EXTRADATA_VUI 0x020 +#define VDEC_EXTRADATA_VC1 0x040 +#define VDEC_EXTRADATA_EXT_DATA 0x0800 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VDEC_EXTRADATA_USER_DATA 0x1000 +#define VDEC_EXTRADATA_EXT_BUFFER 0x2000 +#define VDEC_CMDBASE 0x800 +#define VDEC_CMD_SET_INTF_VERSION (VDEC_CMDBASE) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VDEC_IOCTL_MAGIC 'v' +struct vdec_ioctl_msg { + void __user *in; + void __user *out; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +#define VDEC_IOCTL_GET_PROFILE_LEVEL_SUPPORTED _IOWR(VDEC_IOCTL_MAGIC, 0, struct vdec_ioctl_msg) +#define VDEC_IOCTL_GET_INTERLACE_FORMAT _IOR(VDEC_IOCTL_MAGIC, 1, struct vdec_ioctl_msg) +#define VDEC_IOCTL_GET_CURRENT_PROFILE_LEVEL _IOWR(VDEC_IOCTL_MAGIC, 2, struct vdec_ioctl_msg) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VDEC_IOCTL_SET_OUTPUT_FORMAT _IOWR(VDEC_IOCTL_MAGIC, 3, struct vdec_ioctl_msg) +#define VDEC_IOCTL_GET_OUTPUT_FORMAT _IOWR(VDEC_IOCTL_MAGIC, 4, struct vdec_ioctl_msg) +#define VDEC_IOCTL_SET_CODEC _IOW(VDEC_IOCTL_MAGIC, 5, struct vdec_ioctl_msg) +#define VDEC_IOCTL_GET_CODEC _IOR(VDEC_IOCTL_MAGIC, 6, struct vdec_ioctl_msg) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VDEC_IOCTL_SET_PICRES _IOW(VDEC_IOCTL_MAGIC, 7, struct vdec_ioctl_msg) +#define VDEC_IOCTL_GET_PICRES _IOR(VDEC_IOCTL_MAGIC, 8, struct vdec_ioctl_msg) +#define VDEC_IOCTL_SET_EXTRADATA _IOW(VDEC_IOCTL_MAGIC, 9, struct vdec_ioctl_msg) +#define VDEC_IOCTL_GET_EXTRADATA _IOR(VDEC_IOCTL_MAGIC, 10, struct vdec_ioctl_msg) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VDEC_IOCTL_SET_SEQUENCE_HEADER _IOW(VDEC_IOCTL_MAGIC, 11, struct vdec_ioctl_msg) +#define VDEC_IOCTL_SET_BUFFER_REQ _IOW(VDEC_IOCTL_MAGIC, 12, struct vdec_ioctl_msg) +#define VDEC_IOCTL_GET_BUFFER_REQ _IOR(VDEC_IOCTL_MAGIC, 13, struct vdec_ioctl_msg) +#define VDEC_IOCTL_ALLOCATE_BUFFER _IOWR(VDEC_IOCTL_MAGIC, 14, struct vdec_ioctl_msg) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VDEC_IOCTL_FREE_BUFFER _IOW(VDEC_IOCTL_MAGIC, 15, struct vdec_ioctl_msg) +#define VDEC_IOCTL_SET_BUFFER _IOW(VDEC_IOCTL_MAGIC, 16, struct vdec_ioctl_msg) +#define VDEC_IOCTL_FILL_OUTPUT_BUFFER _IOW(VDEC_IOCTL_MAGIC, 17, struct vdec_ioctl_msg) +#define VDEC_IOCTL_DECODE_FRAME _IOW(VDEC_IOCTL_MAGIC, 18, struct vdec_ioctl_msg) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VDEC_IOCTL_LOAD_RESOURCES _IO(VDEC_IOCTL_MAGIC, 19) +#define VDEC_IOCTL_CMD_START _IO(VDEC_IOCTL_MAGIC, 20) +#define VDEC_IOCTL_CMD_STOP _IO(VDEC_IOCTL_MAGIC, 21) +#define VDEC_IOCTL_CMD_PAUSE _IO(VDEC_IOCTL_MAGIC, 22) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VDEC_IOCTL_CMD_RESUME _IO(VDEC_IOCTL_MAGIC, 23) +#define VDEC_IOCTL_CMD_FLUSH _IOW(VDEC_IOCTL_MAGIC, 24, struct vdec_ioctl_msg) +#define VDEC_IOCTL_GET_NEXT_MSG _IOR(VDEC_IOCTL_MAGIC, 25, struct vdec_ioctl_msg) +#define VDEC_IOCTL_STOP_NEXT_MSG _IO(VDEC_IOCTL_MAGIC, 26) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VDEC_IOCTL_GET_NUMBER_INSTANCES _IOR(VDEC_IOCTL_MAGIC, 27, struct vdec_ioctl_msg) +#define VDEC_IOCTL_SET_PICTURE_ORDER _IOW(VDEC_IOCTL_MAGIC, 28, struct vdec_ioctl_msg) +#define VDEC_IOCTL_SET_FRAME_RATE _IOW(VDEC_IOCTL_MAGIC, 29, struct vdec_ioctl_msg) +#define VDEC_IOCTL_SET_H264_MV_BUFFER _IOW(VDEC_IOCTL_MAGIC, 30, struct vdec_ioctl_msg) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VDEC_IOCTL_FREE_H264_MV_BUFFER _IOW(VDEC_IOCTL_MAGIC, 31, struct vdec_ioctl_msg) +#define VDEC_IOCTL_GET_MV_BUFFER_SIZE _IOR(VDEC_IOCTL_MAGIC, 32, struct vdec_ioctl_msg) +#define VDEC_IOCTL_SET_IDR_ONLY_DECODING _IO(VDEC_IOCTL_MAGIC, 33) +#define VDEC_IOCTL_SET_CONT_ON_RECONFIG _IO(VDEC_IOCTL_MAGIC, 34) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VDEC_IOCTL_SET_DISABLE_DMX _IOW(VDEC_IOCTL_MAGIC, 35, struct vdec_ioctl_msg) +#define VDEC_IOCTL_GET_DISABLE_DMX _IOR(VDEC_IOCTL_MAGIC, 36, struct vdec_ioctl_msg) +#define VDEC_IOCTL_GET_DISABLE_DMX_SUPPORT _IOR(VDEC_IOCTL_MAGIC, 37, struct vdec_ioctl_msg) +#define VDEC_IOCTL_SET_PERF_CLK _IOR(VDEC_IOCTL_MAGIC, 38, struct vdec_ioctl_msg) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VDEC_IOCTL_SET_META_BUFFERS _IOW(VDEC_IOCTL_MAGIC, 39, struct vdec_ioctl_msg) +#define VDEC_IOCTL_FREE_META_BUFFERS _IO(VDEC_IOCTL_MAGIC, 40) +enum vdec_picture { + PICTURE_TYPE_I, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + PICTURE_TYPE_P, + PICTURE_TYPE_B, + PICTURE_TYPE_BI, + PICTURE_TYPE_SKIP, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + PICTURE_TYPE_IDR, + PICTURE_TYPE_UNKNOWN +}; +enum vdec_buffer { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + VDEC_BUFFER_TYPE_INPUT, + VDEC_BUFFER_TYPE_OUTPUT +}; +struct vdec_allocatorproperty { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + enum vdec_buffer buffer_type; + uint32_t mincount; + uint32_t maxcount; + uint32_t actualcount; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + size_t buffer_size; + uint32_t alignment; + uint32_t buf_poolid; + size_t meta_buffer_size; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +struct vdec_bufferpayload { + void __user *bufferaddr; + size_t buffer_len; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + int pmem_fd; + size_t offset; + size_t mmaped_size; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct vdec_setbuffer_cmd { + enum vdec_buffer buffer_type; + struct vdec_bufferpayload buffer; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct vdec_fillbuffer_cmd { + struct vdec_bufferpayload buffer; + void *client_data; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +enum vdec_bufferflush { + VDEC_FLUSH_TYPE_INPUT, + VDEC_FLUSH_TYPE_OUTPUT, + VDEC_FLUSH_TYPE_ALL +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +enum vdec_codec { + VDEC_CODECTYPE_H264 = 0x1, + VDEC_CODECTYPE_H263 = 0x2, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + VDEC_CODECTYPE_MPEG4 = 0x3, + VDEC_CODECTYPE_DIVX_3 = 0x4, + VDEC_CODECTYPE_DIVX_4 = 0x5, + VDEC_CODECTYPE_DIVX_5 = 0x6, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + VDEC_CODECTYPE_DIVX_6 = 0x7, + VDEC_CODECTYPE_XVID = 0x8, + VDEC_CODECTYPE_MPEG1 = 0x9, + VDEC_CODECTYPE_MPEG2 = 0xa, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + VDEC_CODECTYPE_VC1 = 0xb, + VDEC_CODECTYPE_VC1_RCV = 0xc, + VDEC_CODECTYPE_HEVC = 0xd, + VDEC_CODECTYPE_MVC = 0xe, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +enum vdec_mpeg2_profile { + VDEC_MPEG2ProfileSimple = 0x1, + VDEC_MPEG2ProfileMain = 0x2, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + VDEC_MPEG2Profile422 = 0x4, + VDEC_MPEG2ProfileSNR = 0x8, + VDEC_MPEG2ProfileSpatial = 0x10, + VDEC_MPEG2ProfileHigh = 0x20, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + VDEC_MPEG2ProfileKhronosExtensions = 0x6F000000, + VDEC_MPEG2ProfileVendorStartUnused = 0x7F000000, + VDEC_MPEG2ProfileMax = 0x7FFFFFFF +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +enum vdec_mpeg2_level { + VDEC_MPEG2LevelLL = 0x1, + VDEC_MPEG2LevelML = 0x2, + VDEC_MPEG2LevelH14 = 0x4, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + VDEC_MPEG2LevelHL = 0x8, + VDEC_MPEG2LevelKhronosExtensions = 0x6F000000, + VDEC_MPEG2LevelVendorStartUnused = 0x7F000000, + VDEC_MPEG2LevelMax = 0x7FFFFFFF +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +enum vdec_mpeg4_profile { + VDEC_MPEG4ProfileSimple = 0x01, + VDEC_MPEG4ProfileSimpleScalable = 0x02, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + VDEC_MPEG4ProfileCore = 0x04, + VDEC_MPEG4ProfileMain = 0x08, + VDEC_MPEG4ProfileNbit = 0x10, + VDEC_MPEG4ProfileScalableTexture = 0x20, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + VDEC_MPEG4ProfileSimpleFace = 0x40, + VDEC_MPEG4ProfileSimpleFBA = 0x80, + VDEC_MPEG4ProfileBasicAnimated = 0x100, + VDEC_MPEG4ProfileHybrid = 0x200, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + VDEC_MPEG4ProfileAdvancedRealTime = 0x400, + VDEC_MPEG4ProfileCoreScalable = 0x800, + VDEC_MPEG4ProfileAdvancedCoding = 0x1000, + VDEC_MPEG4ProfileAdvancedCore = 0x2000, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + VDEC_MPEG4ProfileAdvancedScalable = 0x4000, + VDEC_MPEG4ProfileAdvancedSimple = 0x8000, + VDEC_MPEG4ProfileKhronosExtensions = 0x6F000000, + VDEC_MPEG4ProfileVendorStartUnused = 0x7F000000, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + VDEC_MPEG4ProfileMax = 0x7FFFFFFF +}; +enum vdec_mpeg4_level { + VDEC_MPEG4Level0 = 0x01, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + VDEC_MPEG4Level0b = 0x02, + VDEC_MPEG4Level1 = 0x04, + VDEC_MPEG4Level2 = 0x08, + VDEC_MPEG4Level3 = 0x10, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + VDEC_MPEG4Level4 = 0x20, + VDEC_MPEG4Level4a = 0x40, + VDEC_MPEG4Level5 = 0x80, + VDEC_MPEG4LevelKhronosExtensions = 0x6F000000, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + VDEC_MPEG4LevelVendorStartUnused = 0x7F000000, + VDEC_MPEG4LevelMax = 0x7FFFFFFF +}; +enum vdec_avc_profile { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + VDEC_AVCProfileBaseline = 0x01, + VDEC_AVCProfileMain = 0x02, + VDEC_AVCProfileExtended = 0x04, + VDEC_AVCProfileHigh = 0x08, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + VDEC_AVCProfileHigh10 = 0x10, + VDEC_AVCProfileHigh422 = 0x20, + VDEC_AVCProfileHigh444 = 0x40, + VDEC_AVCProfileKhronosExtensions = 0x6F000000, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + VDEC_AVCProfileVendorStartUnused = 0x7F000000, + VDEC_AVCProfileMax = 0x7FFFFFFF +}; +enum vdec_avc_level { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + VDEC_AVCLevel1 = 0x01, + VDEC_AVCLevel1b = 0x02, + VDEC_AVCLevel11 = 0x04, + VDEC_AVCLevel12 = 0x08, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + VDEC_AVCLevel13 = 0x10, + VDEC_AVCLevel2 = 0x20, + VDEC_AVCLevel21 = 0x40, + VDEC_AVCLevel22 = 0x80, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + VDEC_AVCLevel3 = 0x100, + VDEC_AVCLevel31 = 0x200, + VDEC_AVCLevel32 = 0x400, + VDEC_AVCLevel4 = 0x800, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + VDEC_AVCLevel41 = 0x1000, + VDEC_AVCLevel42 = 0x2000, + VDEC_AVCLevel5 = 0x4000, + VDEC_AVCLevel51 = 0x8000, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + VDEC_AVCLevelKhronosExtensions = 0x6F000000, + VDEC_AVCLevelVendorStartUnused = 0x7F000000, + VDEC_AVCLevelMax = 0x7FFFFFFF +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +enum vdec_divx_profile { + VDEC_DIVXProfile_qMobile = 0x01, + VDEC_DIVXProfile_Mobile = 0x02, + VDEC_DIVXProfile_HD = 0x04, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + VDEC_DIVXProfile_Handheld = 0x08, + VDEC_DIVXProfile_Portable = 0x10, + VDEC_DIVXProfile_HomeTheater = 0x20 +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +enum vdec_xvid_profile { + VDEC_XVIDProfile_Simple = 0x1, + VDEC_XVIDProfile_Advanced_Realtime_Simple = 0x2, + VDEC_XVIDProfile_Advanced_Simple = 0x4 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +enum vdec_xvid_level { + VDEC_XVID_LEVEL_S_L0 = 0x1, + VDEC_XVID_LEVEL_S_L1 = 0x2, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + VDEC_XVID_LEVEL_S_L2 = 0x4, + VDEC_XVID_LEVEL_S_L3 = 0x8, + VDEC_XVID_LEVEL_ARTS_L1 = 0x10, + VDEC_XVID_LEVEL_ARTS_L2 = 0x20, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + VDEC_XVID_LEVEL_ARTS_L3 = 0x40, + VDEC_XVID_LEVEL_ARTS_L4 = 0x80, + VDEC_XVID_LEVEL_AS_L0 = 0x100, + VDEC_XVID_LEVEL_AS_L1 = 0x200, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + VDEC_XVID_LEVEL_AS_L2 = 0x400, + VDEC_XVID_LEVEL_AS_L3 = 0x800, + VDEC_XVID_LEVEL_AS_L4 = 0x1000 +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +enum vdec_h263profile { + VDEC_H263ProfileBaseline = 0x01, + VDEC_H263ProfileH320Coding = 0x02, + VDEC_H263ProfileBackwardCompatible = 0x04, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + VDEC_H263ProfileISWV2 = 0x08, + VDEC_H263ProfileISWV3 = 0x10, + VDEC_H263ProfileHighCompression = 0x20, + VDEC_H263ProfileInternet = 0x40, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + VDEC_H263ProfileInterlace = 0x80, + VDEC_H263ProfileHighLatency = 0x100, + VDEC_H263ProfileKhronosExtensions = 0x6F000000, + VDEC_H263ProfileVendorStartUnused = 0x7F000000, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + VDEC_H263ProfileMax = 0x7FFFFFFF +}; +enum vdec_h263level { + VDEC_H263Level10 = 0x01, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + VDEC_H263Level20 = 0x02, + VDEC_H263Level30 = 0x04, + VDEC_H263Level40 = 0x08, + VDEC_H263Level45 = 0x10, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + VDEC_H263Level50 = 0x20, + VDEC_H263Level60 = 0x40, + VDEC_H263Level70 = 0x80, + VDEC_H263LevelKhronosExtensions = 0x6F000000, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + VDEC_H263LevelVendorStartUnused = 0x7F000000, + VDEC_H263LevelMax = 0x7FFFFFFF +}; +enum vdec_wmv_format { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + VDEC_WMVFormatUnused = 0x01, + VDEC_WMVFormat7 = 0x02, + VDEC_WMVFormat8 = 0x04, + VDEC_WMVFormat9 = 0x08, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + VDEC_WMFFormatKhronosExtensions = 0x6F000000, + VDEC_WMFFormatVendorStartUnused = 0x7F000000, + VDEC_WMVFormatMax = 0x7FFFFFFF +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +enum vdec_vc1_profile { + VDEC_VC1ProfileSimple = 0x1, + VDEC_VC1ProfileMain = 0x2, + VDEC_VC1ProfileAdvanced = 0x4 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +enum vdec_vc1_level { + VDEC_VC1_LEVEL_S_Low = 0x1, + VDEC_VC1_LEVEL_S_Medium = 0x2, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + VDEC_VC1_LEVEL_M_Low = 0x4, + VDEC_VC1_LEVEL_M_Medium = 0x8, + VDEC_VC1_LEVEL_M_High = 0x10, + VDEC_VC1_LEVEL_A_L0 = 0x20, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + VDEC_VC1_LEVEL_A_L1 = 0x40, + VDEC_VC1_LEVEL_A_L2 = 0x80, + VDEC_VC1_LEVEL_A_L3 = 0x100, + VDEC_VC1_LEVEL_A_L4 = 0x200 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +struct vdec_profile_level { + uint32_t profiles; + uint32_t levels; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +enum vdec_interlaced_format { + VDEC_InterlaceFrameProgressive = 0x1, + VDEC_InterlaceInterleaveFrameTopFieldFirst = 0x2, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + VDEC_InterlaceInterleaveFrameBottomFieldFirst = 0x4 +}; +enum vdec_output_fromat { + VDEC_YUV_FORMAT_NV12 = 0x1, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + VDEC_YUV_FORMAT_TILE_4x2 = 0x2 +}; +enum vdec_output_order { + VDEC_ORDER_DISPLAY = 0x1, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + VDEC_ORDER_DECODE = 0x2 +}; +struct vdec_picsize { + uint32_t frame_width; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t frame_height; + uint32_t stride; + uint32_t scan_lines; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct vdec_seqheader { + void __user *ptr_seqheader; + size_t seq_header_len; + int pmem_fd; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + size_t pmem_offset; +}; +struct vdec_mberror { + void __user *ptr_errormap; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + size_t err_mapsize; +}; +struct vdec_input_frameinfo { + void __user *bufferaddr; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + size_t offset; + size_t datalen; + uint32_t flags; + int64_t timestamp; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + void *client_data; + int pmem_fd; + size_t pmem_offset; + void __user *desc_addr; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t desc_size; +}; +struct vdec_framesize { + uint32_t left; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t top; + uint32_t right; + uint32_t bottom; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct vdec_aspectratioinfo { + uint32_t aspect_ratio; + uint32_t par_width; + uint32_t par_height; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +struct vdec_sep_metadatainfo { + void __user *metabufaddr; + uint32_t size; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +struct vdec_output_frameinfo { + void __user *bufferaddr; + size_t offset; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + size_t len; + uint32_t flags; + int64_t time_stamp; + enum vdec_picture pic_type; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + void *client_data; + void *input_frame_clientdata; + struct vdec_picsize picsize; + struct vdec_framesize framesize; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + enum vdec_interlaced_format interlaced_format; + struct vdec_aspectratioinfo aspect_ratio_info; + struct vdec_sep_metadatainfo metadata_info; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +union vdec_msgdata { + struct vdec_output_frameinfo output_frame; + void *input_frame_clientdata; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct vdec_msginfo { + uint32_t status_code; + uint32_t msgcode; + union vdec_msgdata msgdata; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + size_t msgdatasize; +}; +struct vdec_framerate { + unsigned long fps_denominator; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned long fps_numerator; +}; +struct vdec_h264_mv{ + size_t size; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + int count; + int pmem_fd; + int offset; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct vdec_mv_buff_size{ + int width; + int height; + int size; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + int alignment; +}; +struct vdec_meta_buffers { + size_t size; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + int count; + int pmem_fd; + int pmem_fd_iommu; + int offset; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +#endif + diff --git a/kernel-headers/linux/msm_vidc_enc.h b/kernel-headers/linux/msm_vidc_enc.h new file mode 100644 index 0000000..f1cf25b --- /dev/null +++ b/kernel-headers/linux/msm_vidc_enc.h @@ -0,0 +1,479 @@ +/**************************************************************************** + **************************************************************************** + *** + *** This header was automatically generated from a Linux kernel header + *** of the same name, to make information necessary for userspace to + *** call into the kernel available to libc. It contains only constants, + *** structures, and macros generated from the original header, and thus, + *** contains no copyrightable information. + *** + *** To edit the content of this header, modify the corresponding + *** source file (e.g. under external/kernel-headers/original/) then + *** run bionic/libc/kernel/tools/update_all.py + *** + *** Any manual change here will be lost the next time this script will + *** be run. You've been warned! + *** + **************************************************************************** + ****************************************************************************/ +#ifndef _UAPI_MSM_VIDC_ENC_H_ +#define _UAPI_MSM_VIDC_ENC_H_ +#include <linux/types.h> +#include <linux/ioctl.h> +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VEN_S_BASE 0x00000000 +#define VEN_S_SUCCESS (VEN_S_BASE) +#define VEN_S_EFAIL (VEN_S_BASE+1) +#define VEN_S_EFATAL (VEN_S_BASE+2) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VEN_S_EBADPARAM (VEN_S_BASE+3) +#define VEN_S_EINVALSTATE (VEN_S_BASE+4) +#define VEN_S_ENOSWRES (VEN_S_BASE+5) +#define VEN_S_ENOHWRES (VEN_S_BASE+6) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VEN_S_EBUFFREQ (VEN_S_BASE+7) +#define VEN_S_EINVALCMD (VEN_S_BASE+8) +#define VEN_S_ETIMEOUT (VEN_S_BASE+9) +#define VEN_S_ENOREATMPT (VEN_S_BASE+10) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VEN_S_ENOPREREQ (VEN_S_BASE+11) +#define VEN_S_ECMDQFULL (VEN_S_BASE+12) +#define VEN_S_ENOTSUPP (VEN_S_BASE+13) +#define VEN_S_ENOTIMPL (VEN_S_BASE+14) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VEN_S_ENOTPMEM (VEN_S_BASE+15) +#define VEN_S_EFLUSHED (VEN_S_BASE+16) +#define VEN_S_EINSUFBUF (VEN_S_BASE+17) +#define VEN_S_ESAMESTATE (VEN_S_BASE+18) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VEN_S_EINVALTRANS (VEN_S_BASE+19) +#define VEN_INTF_VER 1 +#define VEN_MSG_INDICATION 0 +#define VEN_MSG_INPUT_BUFFER_DONE 1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VEN_MSG_OUTPUT_BUFFER_DONE 2 +#define VEN_MSG_NEED_OUTPUT_BUFFER 3 +#define VEN_MSG_FLUSH_INPUT_DONE 4 +#define VEN_MSG_FLUSH_OUPUT_DONE 5 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VEN_MSG_START 6 +#define VEN_MSG_STOP 7 +#define VEN_MSG_PAUSE 8 +#define VEN_MSG_RESUME 9 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VEN_MSG_STOP_READING_MSG 10 +#define VEN_MSG_LTRUSE_FAILED 11 +#define VEN_MSG_HW_OVERLOAD 12 +#define VEN_MSG_MAX_CLIENTS 13 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VEN_BUFFLAG_EOS 0x00000001 +#define VEN_BUFFLAG_ENDOFFRAME 0x00000010 +#define VEN_BUFFLAG_SYNCFRAME 0x00000020 +#define VEN_BUFFLAG_EXTRADATA 0x00000040 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VEN_BUFFLAG_CODECCONFIG 0x00000080 +#define VEN_EXTRADATA_NONE 0x001 +#define VEN_EXTRADATA_QCOMFILLER 0x002 +#define VEN_EXTRADATA_SLICEINFO 0x100 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VEN_EXTRADATA_LTRINFO 0x200 +#define VEN_EXTRADATA_MBINFO 0x400 +#define VEN_FRAME_TYPE_I 1 +#define VEN_FRAME_TYPE_P 2 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VEN_FRAME_TYPE_B 3 +#define VEN_CODEC_MPEG4 1 +#define VEN_CODEC_H264 2 +#define VEN_CODEC_H263 3 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VEN_PROFILE_MPEG4_SP 1 +#define VEN_PROFILE_MPEG4_ASP 2 +#define VEN_PROFILE_H264_BASELINE 3 +#define VEN_PROFILE_H264_MAIN 4 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VEN_PROFILE_H264_HIGH 5 +#define VEN_PROFILE_H263_BASELINE 6 +#define VEN_LEVEL_MPEG4_0 0x1 +#define VEN_LEVEL_MPEG4_1 0x2 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VEN_LEVEL_MPEG4_2 0x3 +#define VEN_LEVEL_MPEG4_3 0x4 +#define VEN_LEVEL_MPEG4_4 0x5 +#define VEN_LEVEL_MPEG4_5 0x6 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VEN_LEVEL_MPEG4_3b 0x7 +#define VEN_LEVEL_MPEG4_6 0x8 +#define VEN_LEVEL_H264_1 0x9 +#define VEN_LEVEL_H264_1b 0xA +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VEN_LEVEL_H264_1p1 0xB +#define VEN_LEVEL_H264_1p2 0xC +#define VEN_LEVEL_H264_1p3 0xD +#define VEN_LEVEL_H264_2 0xE +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VEN_LEVEL_H264_2p1 0xF +#define VEN_LEVEL_H264_2p2 0x10 +#define VEN_LEVEL_H264_3 0x11 +#define VEN_LEVEL_H264_3p1 0x12 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VEN_LEVEL_H264_3p2 0x13 +#define VEN_LEVEL_H264_4 0x14 +#define VEN_LEVEL_H263_10 0x15 +#define VEN_LEVEL_H263_20 0x16 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VEN_LEVEL_H263_30 0x17 +#define VEN_LEVEL_H263_40 0x18 +#define VEN_LEVEL_H263_45 0x19 +#define VEN_LEVEL_H263_50 0x1A +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VEN_LEVEL_H263_60 0x1B +#define VEN_LEVEL_H263_70 0x1C +#define VEN_ENTROPY_MODEL_CAVLC 1 +#define VEN_ENTROPY_MODEL_CABAC 2 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VEN_CABAC_MODEL_0 1 +#define VEN_CABAC_MODEL_1 2 +#define VEN_CABAC_MODEL_2 3 +#define VEN_DB_DISABLE 1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VEN_DB_ALL_BLKG_BNDRY 2 +#define VEN_DB_SKIP_SLICE_BNDRY 3 +#define VEN_MSLICE_OFF 1 +#define VEN_MSLICE_CNT_MB 2 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VEN_MSLICE_CNT_BYTE 3 +#define VEN_MSLICE_GOB 4 +#define VEN_RC_OFF 1 +#define VEN_RC_VBR_VFR 2 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VEN_RC_VBR_CFR 3 +#define VEN_RC_CBR_VFR 4 +#define VEN_RC_CBR_CFR 5 +#define VEN_FLUSH_INPUT 1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VEN_FLUSH_OUTPUT 2 +#define VEN_FLUSH_ALL 3 +#define VEN_INPUTFMT_NV12 1 +#define VEN_INPUTFMT_NV21 2 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VEN_INPUTFMT_NV12_16M2KA 3 +#define VEN_ROTATION_0 1 +#define VEN_ROTATION_90 2 +#define VEN_ROTATION_180 3 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VEN_ROTATION_270 4 +#define VEN_TIMEOUT_INFINITE 0xffffffff +#define VEN_IR_OFF 1 +#define VEN_IR_CYCLIC 2 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VEN_IR_RANDOM 3 +#define VEN_IOCTLBASE_NENC 0x800 +#define VEN_IOCTLBASE_ENC 0x850 +struct venc_ioctl_msg{ +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + void __user *in; + void __user *out; +}; +#define VEN_IOCTL_SET_INTF_VERSION _IOW(VEN_IOCTLBASE_NENC, 0, struct venc_ioctl_msg) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VEN_IOCTL_CMD_READ_NEXT_MSG _IOWR(VEN_IOCTLBASE_NENC, 1, struct venc_ioctl_msg) +#define VEN_IOCTL_CMD_STOP_READ_MSG _IO(VEN_IOCTLBASE_NENC, 2) +#define VEN_IOCTL_SET_INPUT_BUFFER_REQ _IOW(VEN_IOCTLBASE_NENC, 3, struct venc_ioctl_msg) +#define VEN_IOCTL_GET_INPUT_BUFFER_REQ _IOR(VEN_IOCTLBASE_NENC, 4, struct venc_ioctl_msg) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VEN_IOCTL_CMD_ALLOC_INPUT_BUFFER _IOW(VEN_IOCTLBASE_NENC, 5, struct venc_ioctl_msg) +#define VEN_IOCTL_SET_INPUT_BUFFER _IOW(VEN_IOCTLBASE_NENC, 6, struct venc_ioctl_msg) +#define VEN_IOCTL_CMD_FREE_INPUT_BUFFER _IOW(VEN_IOCTLBASE_NENC, 7, struct venc_ioctl_msg) +#define VEN_IOCTL_SET_OUTPUT_BUFFER_REQ _IOW(VEN_IOCTLBASE_NENC, 8, struct venc_ioctl_msg) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VEN_IOCTL_GET_OUTPUT_BUFFER_REQ _IOR(VEN_IOCTLBASE_NENC, 9, struct venc_ioctl_msg) +#define VEN_IOCTL_CMD_ALLOC_OUTPUT_BUFFER _IOW(VEN_IOCTLBASE_NENC, 10, struct venc_ioctl_msg) +#define VEN_IOCTL_SET_OUTPUT_BUFFER _IOW(VEN_IOCTLBASE_NENC, 11, struct venc_ioctl_msg) +#define VEN_IOCTL_CMD_FREE_OUTPUT_BUFFER _IOW(VEN_IOCTLBASE_NENC, 12, struct venc_ioctl_msg) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VEN_IOCTL_CMD_START _IO(VEN_IOCTLBASE_NENC, 13) +#define VEN_IOCTL_CMD_ENCODE_FRAME _IOW(VEN_IOCTLBASE_NENC, 14, struct venc_ioctl_msg) +#define VEN_IOCTL_CMD_FILL_OUTPUT_BUFFER _IOW(VEN_IOCTLBASE_NENC, 15, struct venc_ioctl_msg) +#define VEN_IOCTL_CMD_FLUSH _IOW(VEN_IOCTLBASE_NENC, 16, struct venc_ioctl_msg) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VEN_IOCTL_CMD_PAUSE _IO(VEN_IOCTLBASE_NENC, 17) +#define VEN_IOCTL_CMD_RESUME _IO(VEN_IOCTLBASE_NENC, 18) +#define VEN_IOCTL_CMD_STOP _IO(VEN_IOCTLBASE_NENC, 19) +#define VEN_IOCTL_SET_RECON_BUFFER _IOW(VEN_IOCTLBASE_NENC, 20, struct venc_ioctl_msg) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VEN_IOCTL_FREE_RECON_BUFFER _IOW(VEN_IOCTLBASE_NENC, 21, struct venc_ioctl_msg) +#define VEN_IOCTL_GET_RECON_BUFFER_SIZE _IOW(VEN_IOCTLBASE_NENC, 22, struct venc_ioctl_msg) +#define VEN_IOCTL_SET_BASE_CFG _IOW(VEN_IOCTLBASE_ENC, 1, struct venc_ioctl_msg) +#define VEN_IOCTL_GET_BASE_CFG _IOR(VEN_IOCTLBASE_ENC, 2, struct venc_ioctl_msg) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VEN_IOCTL_SET_LIVE_MODE _IOW(VEN_IOCTLBASE_ENC, 3, struct venc_ioctl_msg) +#define VEN_IOCTL_GET_LIVE_MODE _IOR(VEN_IOCTLBASE_ENC, 4, struct venc_ioctl_msg) +#define VEN_IOCTL_SET_CODEC_PROFILE _IOW(VEN_IOCTLBASE_ENC, 5, struct venc_ioctl_msg) +#define VEN_IOCTL_GET_CODEC_PROFILE _IOR(VEN_IOCTLBASE_ENC, 6, struct venc_ioctl_msg) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VEN_IOCTL_SET_PROFILE_LEVEL _IOW(VEN_IOCTLBASE_ENC, 7, struct venc_ioctl_msg) +#define VEN_IOCTL_GET_PROFILE_LEVEL _IOR(VEN_IOCTLBASE_ENC, 8, struct venc_ioctl_msg) +#define VEN_IOCTL_SET_SHORT_HDR _IOW(VEN_IOCTLBASE_ENC, 9, struct venc_ioctl_msg) +#define VEN_IOCTL_GET_SHORT_HDR _IOR(VEN_IOCTLBASE_ENC, 10, struct venc_ioctl_msg) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VEN_IOCTL_SET_SESSION_QP _IOW(VEN_IOCTLBASE_ENC, 11, struct venc_ioctl_msg) +#define VEN_IOCTL_GET_SESSION_QP _IOR(VEN_IOCTLBASE_ENC, 12, struct venc_ioctl_msg) +#define VEN_IOCTL_SET_INTRA_PERIOD _IOW(VEN_IOCTLBASE_ENC, 13, struct venc_ioctl_msg) +#define VEN_IOCTL_GET_INTRA_PERIOD _IOR(VEN_IOCTLBASE_ENC, 14, struct venc_ioctl_msg) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VEN_IOCTL_CMD_REQUEST_IFRAME _IO(VEN_IOCTLBASE_ENC, 15) +#define VEN_IOCTL_GET_CAPABILITY _IOR(VEN_IOCTLBASE_ENC, 16, struct venc_ioctl_msg) +#define VEN_IOCTL_GET_SEQUENCE_HDR _IOR(VEN_IOCTLBASE_ENC, 17, struct venc_ioctl_msg) +#define VEN_IOCTL_SET_ENTROPY_CFG _IOW(VEN_IOCTLBASE_ENC, 18, struct venc_ioctl_msg) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VEN_IOCTL_GET_ENTROPY_CFG _IOR(VEN_IOCTLBASE_ENC, 19, struct venc_ioctl_msg) +#define VEN_IOCTL_SET_DEBLOCKING_CFG _IOW(VEN_IOCTLBASE_ENC, 20, struct venc_ioctl_msg) +#define VEN_IOCTL_GET_DEBLOCKING_CFG _IOR(VEN_IOCTLBASE_ENC, 21, struct venc_ioctl_msg) +#define VEN_IOCTL_SET_INTRA_REFRESH _IOW(VEN_IOCTLBASE_ENC, 22, struct venc_ioctl_msg) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VEN_IOCTL_GET_INTRA_REFRESH _IOR(VEN_IOCTLBASE_ENC, 23, struct venc_ioctl_msg) +#define VEN_IOCTL_SET_MULTI_SLICE_CFG _IOW(VEN_IOCTLBASE_ENC, 24, struct venc_ioctl_msg) +#define VEN_IOCTL_GET_MULTI_SLICE_CFG _IOR(VEN_IOCTLBASE_ENC, 25, struct venc_ioctl_msg) +#define VEN_IOCTL_SET_RATE_CTRL_CFG _IOW(VEN_IOCTLBASE_ENC, 26, struct venc_ioctl_msg) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VEN_IOCTL_GET_RATE_CTRL_CFG _IOR(VEN_IOCTLBASE_ENC, 27, struct venc_ioctl_msg) +#define VEN_IOCTL_SET_VOP_TIMING_CFG _IOW(VEN_IOCTLBASE_ENC, 28, struct venc_ioctl_msg) +#define VEN_IOCTL_GET_VOP_TIMING_CFG _IOR(VEN_IOCTLBASE_ENC, 29, struct venc_ioctl_msg) +#define VEN_IOCTL_SET_FRAME_RATE _IOW(VEN_IOCTLBASE_ENC, 30, struct venc_ioctl_msg) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VEN_IOCTL_GET_FRAME_RATE _IOR(VEN_IOCTLBASE_ENC, 31, struct venc_ioctl_msg) +#define VEN_IOCTL_SET_TARGET_BITRATE _IOW(VEN_IOCTLBASE_ENC, 32, struct venc_ioctl_msg) +#define VEN_IOCTL_GET_TARGET_BITRATE _IOR(VEN_IOCTLBASE_ENC, 33, struct venc_ioctl_msg) +#define VEN_IOCTL_SET_ROTATION _IOW(VEN_IOCTLBASE_ENC, 34, struct venc_ioctl_msg) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VEN_IOCTL_GET_ROTATION _IOR(VEN_IOCTLBASE_ENC, 35, struct venc_ioctl_msg) +#define VEN_IOCTL_SET_HEC _IOW(VEN_IOCTLBASE_ENC, 36, struct venc_ioctl_msg) +#define VEN_IOCTL_GET_HEC _IOR(VEN_IOCTLBASE_ENC, 37, struct venc_ioctl_msg) +#define VEN_IOCTL_SET_DATA_PARTITION _IOW(VEN_IOCTLBASE_ENC, 38, struct venc_ioctl_msg) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VEN_IOCTL_GET_DATA_PARTITION _IOR(VEN_IOCTLBASE_ENC, 39, struct venc_ioctl_msg) +#define VEN_IOCTL_SET_RVLC _IOW(VEN_IOCTLBASE_ENC, 40, struct venc_ioctl_msg) +#define VEN_IOCTL_GET_RVLC _IOR(VEN_IOCTLBASE_ENC, 41, struct venc_ioctl_msg) +#define VEN_IOCTL_SET_AC_PREDICTION _IOW(VEN_IOCTLBASE_ENC, 42, struct venc_ioctl_msg) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VEN_IOCTL_GET_AC_PREDICTION _IOR(VEN_IOCTLBASE_ENC, 43, struct venc_ioctl_msg) +#define VEN_IOCTL_SET_QP_RANGE _IOW(VEN_IOCTLBASE_ENC, 44, struct venc_ioctl_msg) +#define VEN_IOCTL_GET_QP_RANGE _IOR(VEN_IOCTLBASE_ENC, 45, struct venc_ioctl_msg) +#define VEN_IOCTL_GET_NUMBER_INSTANCES _IOR(VEN_IOCTLBASE_ENC, 46, struct venc_ioctl_msg) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VEN_IOCTL_SET_METABUFFER_MODE _IOW(VEN_IOCTLBASE_ENC, 47, struct venc_ioctl_msg) +#define VEN_IOCTL_SET_EXTRADATA _IOW(VEN_IOCTLBASE_ENC, 48, struct venc_ioctl_msg) +#define VEN_IOCTL_GET_EXTRADATA _IOR(VEN_IOCTLBASE_ENC, 49, struct venc_ioctl_msg) +#define VEN_IOCTL_SET_SLICE_DELIVERY_MODE _IO(VEN_IOCTLBASE_ENC, 50) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VEN_IOCTL_SET_H263_PLUSPTYPE _IOW(VEN_IOCTLBASE_ENC, 51, struct venc_ioctl_msg) +#define VEN_IOCTL_SET_CAPABILITY_LTRCOUNT _IOW(VEN_IOCTLBASE_ENC, 52, struct venc_ioctl_msg) +#define VEN_IOCTL_GET_CAPABILITY_LTRCOUNT _IOR(VEN_IOCTLBASE_ENC, 53, struct venc_ioctl_msg) +#define VEN_IOCTL_SET_LTRMODE _IOW(VEN_IOCTLBASE_ENC, 54, struct venc_ioctl_msg) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VEN_IOCTL_GET_LTRMODE _IOR(VEN_IOCTLBASE_ENC, 55, struct venc_ioctl_msg) +#define VEN_IOCTL_SET_LTRCOUNT _IOW(VEN_IOCTLBASE_ENC, 56, struct venc_ioctl_msg) +#define VEN_IOCTL_GET_LTRCOUNT _IOR(VEN_IOCTLBASE_ENC, 57, struct venc_ioctl_msg) +#define VEN_IOCTL_SET_LTRPERIOD _IOW(VEN_IOCTLBASE_ENC, 58, struct venc_ioctl_msg) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VEN_IOCTL_GET_LTRPERIOD _IOR(VEN_IOCTLBASE_ENC, 59, struct venc_ioctl_msg) +#define VEN_IOCTL_SET_LTRUSE _IOW(VEN_IOCTLBASE_ENC, 60, struct venc_ioctl_msg) +#define VEN_IOCTL_GET_LTRUSE _IOR(VEN_IOCTLBASE_ENC, 61, struct venc_ioctl_msg) +#define VEN_IOCTL_SET_LTRMARK _IOW(VEN_IOCTLBASE_ENC, 62, struct venc_ioctl_msg) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VEN_IOCTL_GET_LTRMARK _IOR(VEN_IOCTLBASE_ENC, 63, struct venc_ioctl_msg) +#define VEN_IOCTL_SET_SPS_PPS_FOR_IDR _IOW(VEN_IOCTLBASE_ENC, 64, struct venc_ioctl_msg) +struct venc_range { + unsigned long max; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned long min; + unsigned long step_size; +}; +struct venc_switch{ +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned char status; +}; +struct venc_allocatorproperty{ + unsigned long mincount; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned long maxcount; + unsigned long actualcount; + unsigned long datasize; + unsigned long suffixsize; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned long alignment; + unsigned long bufpoolid; +}; +struct venc_bufferpayload{ +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned char *pbuffer; + size_t sz; + int fd; + unsigned int offset; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned int maped_size; + unsigned long filled_len; +}; +struct venc_buffer{ +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned char *ptrbuffer; + unsigned long sz; + unsigned long len; + unsigned long offset; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + long long timestamp; + unsigned long flags; + void *clientdata; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct venc_basecfg{ + unsigned long input_width; + unsigned long input_height; + unsigned long dvs_width; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned long dvs_height; + unsigned long codectype; + unsigned long fps_num; + unsigned long fps_den; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned long targetbitrate; + unsigned long inputformat; +}; +struct venc_profile{ +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned long profile; +}; +struct ven_profilelevel{ + unsigned long level; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +struct venc_sessionqp{ + unsigned long iframeqp; + unsigned long pframqp; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +struct venc_qprange{ + unsigned long maxqp; + unsigned long minqp; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +struct venc_plusptype { + unsigned long plusptype_enable; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct venc_intraperiod{ + unsigned long num_pframes; + unsigned long num_bframes; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct venc_seqheader{ + unsigned char *hdrbufptr; + unsigned long bufsize; + unsigned long hdrlen; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +struct venc_capability{ + unsigned long codec_types; + unsigned long maxframe_width; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned long maxframe_height; + unsigned long maxtarget_bitrate; + unsigned long maxframe_rate; + unsigned long input_formats; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned char dvs; +}; +struct venc_entropycfg{ + unsigned longentropysel; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned long cabacmodel; +}; +struct venc_dbcfg{ + unsigned long db_mode; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned long slicealpha_offset; + unsigned long slicebeta_offset; +}; +struct venc_intrarefresh{ +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned long irmode; + unsigned long mbcount; +}; +struct venc_multiclicecfg{ +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned long mslice_mode; + unsigned long mslice_size; +}; +struct venc_bufferflush{ +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned long flush_mode; +}; +struct venc_ratectrlcfg{ + unsigned long rcmode; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +struct venc_voptimingcfg{ + unsigned long voptime_resolution; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct venc_framerate{ + unsigned long fps_denominator; + unsigned long fps_numerator; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct venc_targetbitrate{ + unsigned long target_bitrate; +}; +struct venc_rotation{ +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned long rotation; +}; +struct venc_timeout{ + unsigned long millisec; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +struct venc_headerextension{ + unsigned long header_extension; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct venc_msg{ + unsigned long statuscode; + unsigned long msgcode; + struct venc_buffer buf; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned long msgdata_size; +}; +struct venc_recon_addr{ + unsigned char *pbuffer; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned long buffer_size; + unsigned long pmem_fd; + unsigned long offset; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct venc_recon_buff_size{ + int width; + int height; + int size; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + int alignment; +}; +struct venc_ltrmode { + unsigned long ltr_mode; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +struct venc_ltrcount { + unsigned long ltr_count; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct venc_ltrperiod { + unsigned long ltr_period; +}; +struct venc_ltruse { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned long ltr_id; + unsigned long ltr_frames; +}; +#endif +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + diff --git a/kernel-headers/linux/netlink.h b/kernel-headers/linux/netlink.h new file mode 100644 index 0000000..091aa26 --- /dev/null +++ b/kernel-headers/linux/netlink.h @@ -0,0 +1,171 @@ +/**************************************************************************** + **************************************************************************** + *** + *** This header was automatically generated from a Linux kernel header + *** of the same name, to make information necessary for userspace to + *** call into the kernel available to libc. It contains only constants, + *** structures, and macros generated from the original header, and thus, + *** contains no copyrightable information. + *** + *** To edit the content of this header, modify the corresponding + *** source file (e.g. under external/kernel-headers/original/) then + *** run bionic/libc/kernel/tools/update_all.py + *** + *** Any manual change here will be lost the next time this script will + *** be run. You've been warned! + *** + **************************************************************************** + ****************************************************************************/ +#ifndef _UAPI__LINUX_NETLINK_H +#define _UAPI__LINUX_NETLINK_H +#include <linux/socket.h> +#include <linux/types.h> +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define NETLINK_ROUTE 0 +#define NETLINK_UNUSED 1 +#define NETLINK_USERSOCK 2 +#define NETLINK_FIREWALL 3 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define NETLINK_SOCK_DIAG 4 +#define NETLINK_NFLOG 5 +#define NETLINK_XFRM 6 +#define NETLINK_SELINUX 7 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define NETLINK_ISCSI 8 +#define NETLINK_AUDIT 9 +#define NETLINK_FIB_LOOKUP 10 +#define NETLINK_CONNECTOR 11 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define NETLINK_NETFILTER 12 +#define NETLINK_IP6_FW 13 +#define NETLINK_DNRTMSG 14 +#define NETLINK_KOBJECT_UEVENT 15 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define NETLINK_GENERIC 16 +#define NETLINK_SCSITRANSPORT 18 +#define NETLINK_ECRYPTFS 19 +#define NETLINK_RDMA 20 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define NETLINK_CRYPTO 21 +#define NETLINK_SOCKEV 22 +#define NETLINK_INET_DIAG NETLINK_SOCK_DIAG +#define MAX_LINKS 32 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct sockaddr_nl { + __kernel_sa_family_t nl_family; + unsigned short nl_pad; + __u32 nl_pid; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u32 nl_groups; +}; +struct nlmsghdr { + __u32 nlmsg_len; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u16 nlmsg_type; + __u16 nlmsg_flags; + __u32 nlmsg_seq; + __u32 nlmsg_pid; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +#define NLM_F_REQUEST 1 +#define NLM_F_MULTI 2 +#define NLM_F_ACK 4 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define NLM_F_ECHO 8 +#define NLM_F_DUMP_INTR 16 +#define NLM_F_ROOT 0x100 +#define NLM_F_MATCH 0x200 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define NLM_F_ATOMIC 0x400 +#define NLM_F_DUMP (NLM_F_ROOT|NLM_F_MATCH) +#define NLM_F_REPLACE 0x100 +#define NLM_F_EXCL 0x200 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define NLM_F_CREATE 0x400 +#define NLM_F_APPEND 0x800 +#define NLMSG_ALIGNTO 4U +#define NLMSG_ALIGN(len) ( ((len)+NLMSG_ALIGNTO-1) & ~(NLMSG_ALIGNTO-1) ) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define NLMSG_HDRLEN ((int) NLMSG_ALIGN(sizeof(struct nlmsghdr))) +#define NLMSG_LENGTH(len) ((len) + NLMSG_HDRLEN) +#define NLMSG_SPACE(len) NLMSG_ALIGN(NLMSG_LENGTH(len)) +#define NLMSG_DATA(nlh) ((void*)(((char*)nlh) + NLMSG_LENGTH(0))) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define NLMSG_NEXT(nlh,len) ((len) -= NLMSG_ALIGN((nlh)->nlmsg_len), (struct nlmsghdr*)(((char*)(nlh)) + NLMSG_ALIGN((nlh)->nlmsg_len))) +#define NLMSG_OK(nlh,len) ((len) >= (int)sizeof(struct nlmsghdr) && (nlh)->nlmsg_len >= sizeof(struct nlmsghdr) && (nlh)->nlmsg_len <= (len)) +#define NLMSG_PAYLOAD(nlh,len) ((nlh)->nlmsg_len - NLMSG_SPACE((len))) +#define NLMSG_NOOP 0x1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define NLMSG_ERROR 0x2 +#define NLMSG_DONE 0x3 +#define NLMSG_OVERRUN 0x4 +#define NLMSG_MIN_TYPE 0x10 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct nlmsgerr { + int error; + struct nlmsghdr msg; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define NETLINK_ADD_MEMBERSHIP 1 +#define NETLINK_DROP_MEMBERSHIP 2 +#define NETLINK_PKTINFO 3 +#define NETLINK_BROADCAST_ERROR 4 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define NETLINK_NO_ENOBUFS 5 +#define NETLINK_RX_RING 6 +#define NETLINK_TX_RING 7 +struct nl_pktinfo { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u32 group; +}; +struct nl_mmap_req { + unsigned int nm_block_size; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned int nm_block_nr; + unsigned int nm_frame_size; + unsigned int nm_frame_nr; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct nl_mmap_hdr { + unsigned int nm_status; + unsigned int nm_len; + __u32 nm_group; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u32 nm_pid; + __u32 nm_uid; + __u32 nm_gid; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +enum nl_mmap_status { + NL_MMAP_STATUS_UNUSED, + NL_MMAP_STATUS_RESERVED, + NL_MMAP_STATUS_VALID, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + NL_MMAP_STATUS_COPY, + NL_MMAP_STATUS_SKIP, +}; +#define NL_MMAP_MSG_ALIGNMENT NLMSG_ALIGNTO +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define NL_MMAP_MSG_ALIGN(sz) __ALIGN_KERNEL(sz, NL_MMAP_MSG_ALIGNMENT) +#define NL_MMAP_HDRLEN NL_MMAP_MSG_ALIGN(sizeof(struct nl_mmap_hdr)) +#define NET_MAJOR 36 +enum { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + NETLINK_UNCONNECTED = 0, + NETLINK_CONNECTED, +}; +struct nlattr { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u16 nla_len; + __u16 nla_type; +}; +#define NLA_F_NESTED (1 << 15) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define NLA_F_NET_BYTEORDER (1 << 14) +#define NLA_TYPE_MASK ~(NLA_F_NESTED | NLA_F_NET_BYTEORDER) +#define NLA_ALIGNTO 4 +#define NLA_ALIGN(len) (((len) + NLA_ALIGNTO - 1) & ~(NLA_ALIGNTO - 1)) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define NLA_HDRLEN ((int) NLA_ALIGN(sizeof(struct nlattr))) +#endif + diff --git a/kernel-headers/linux/qseecom.h b/kernel-headers/linux/qseecom.h new file mode 100644 index 0000000..07322dd --- /dev/null +++ b/kernel-headers/linux/qseecom.h @@ -0,0 +1,196 @@ +/**************************************************************************** + **************************************************************************** + *** + *** This header was automatically generated from a Linux kernel header + *** of the same name, to make information necessary for userspace to + *** call into the kernel available to libc. It contains only constants, + *** structures, and macros generated from the original header, and thus, + *** contains no copyrightable information. + *** + *** To edit the content of this header, modify the corresponding + *** source file (e.g. under external/kernel-headers/original/) then + *** run bionic/libc/kernel/tools/update_all.py + *** + *** Any manual change here will be lost the next time this script will + *** be run. You've been warned! + *** + **************************************************************************** + ****************************************************************************/ +#ifndef _UAPI_QSEECOM_H_ +#define _UAPI_QSEECOM_H_ +#include <linux/types.h> +#include <linux/ioctl.h> +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define MAX_ION_FD 4 +#define MAX_APP_NAME_SIZE 32 +#define QSEECOM_HASH_SIZE 32 +struct qseecom_register_listener_req { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t listener_id; + int32_t ifd_data_fd; + void *virt_sb_base; + uint32_t sb_size; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +struct qseecom_send_cmd_req { + void *cmd_req_buf; + unsigned int cmd_req_len; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + void *resp_buf; + unsigned int resp_len; +}; +struct qseecom_ion_fd_info { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + int32_t fd; + uint32_t cmd_buf_offset; +}; +struct qseecom_send_modfd_cmd_req { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + void *cmd_req_buf; + unsigned int cmd_req_len; + void *resp_buf; + unsigned int resp_len; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + struct qseecom_ion_fd_info ifd_data[MAX_ION_FD]; +}; +struct qseecom_send_resp_req { + void *resp_buf; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned int resp_len; +}; +struct qseecom_load_img_req { + uint32_t mdt_len; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t img_len; + int32_t ifd_data_fd; + char img_name[MAX_APP_NAME_SIZE]; + int app_id; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +struct qseecom_set_sb_mem_param_req { + int32_t ifd_data_fd; + void *virt_sb_base; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t sb_len; +}; +struct qseecom_qseos_version_req { + unsigned int qseos_version; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +struct qseecom_qseos_app_load_query { + char app_name[MAX_APP_NAME_SIZE]; + int app_id; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +struct qseecom_send_svc_cmd_req { + uint32_t cmd_id; + void *cmd_req_buf; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned int cmd_req_len; + void *resp_buf; + unsigned int resp_len; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +enum qseecom_key_management_usage_type { + QSEOS_KM_USAGE_DISK_ENCRYPTION = 0x01, + QSEOS_KM_USAGE_FILE_ENCRYPTION = 0x02, + QSEOS_KM_USAGE_ICE_DISK_ENCRYPTION = 0x03, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + QSEOS_KM_USAGE_ICE_FILE_ENCRYPTION = 0x04, + QSEOS_KM_USAGE_MAX +}; +struct qseecom_create_key_req { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned char hash32[QSEECOM_HASH_SIZE]; + enum qseecom_key_management_usage_type usage; +}; +struct qseecom_wipe_key_req { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + enum qseecom_key_management_usage_type usage; + int wipe_key_flag; +}; +struct qseecom_update_key_userinfo_req { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned char current_hash32[QSEECOM_HASH_SIZE]; + unsigned char new_hash32[QSEECOM_HASH_SIZE]; + enum qseecom_key_management_usage_type usage; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SHA256_DIGEST_LENGTH (256/8) +struct qseecom_save_partition_hash_req { + int partition_id; + char digest[SHA256_DIGEST_LENGTH]; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +struct qseecom_is_es_activated_req { + int is_activated; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +enum qseecom_bandwidth_request_mode { + INACTIVE = 0, + LOW, + MEDIUM, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + HIGH, +}; +struct qseecom_send_modfd_listener_resp { + void *resp_buf_ptr; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned int resp_len; + struct qseecom_ion_fd_info ifd_data[MAX_ION_FD]; +}; +struct qseecom_qteec_req { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + void *req_ptr; + uint32_t req_len; + void *resp_ptr; + uint32_t resp_len; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +struct qseecom_qteec_modfd_req { + void *req_ptr; + uint32_t req_len; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + void *resp_ptr; + uint32_t resp_len; + struct qseecom_ion_fd_info ifd_data[MAX_ION_FD]; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct file; +#define QSEECOM_IOC_MAGIC 0x97 +#define QSEECOM_IOCTL_REGISTER_LISTENER_REQ _IOWR(QSEECOM_IOC_MAGIC, 1, struct qseecom_register_listener_req) +#define QSEECOM_IOCTL_UNREGISTER_LISTENER_REQ _IO(QSEECOM_IOC_MAGIC, 2) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define QSEECOM_IOCTL_SEND_CMD_REQ _IOWR(QSEECOM_IOC_MAGIC, 3, struct qseecom_send_cmd_req) +#define QSEECOM_IOCTL_SEND_MODFD_CMD_REQ _IOWR(QSEECOM_IOC_MAGIC, 4, struct qseecom_send_modfd_cmd_req) +#define QSEECOM_IOCTL_RECEIVE_REQ _IO(QSEECOM_IOC_MAGIC, 5) +#define QSEECOM_IOCTL_SEND_RESP_REQ _IO(QSEECOM_IOC_MAGIC, 6) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define QSEECOM_IOCTL_LOAD_APP_REQ _IOWR(QSEECOM_IOC_MAGIC, 7, struct qseecom_load_img_req) +#define QSEECOM_IOCTL_SET_MEM_PARAM_REQ _IOWR(QSEECOM_IOC_MAGIC, 8, struct qseecom_set_sb_mem_param_req) +#define QSEECOM_IOCTL_UNLOAD_APP_REQ _IO(QSEECOM_IOC_MAGIC, 9) +#define QSEECOM_IOCTL_GET_QSEOS_VERSION_REQ _IOWR(QSEECOM_IOC_MAGIC, 10, struct qseecom_qseos_version_req) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define QSEECOM_IOCTL_PERF_ENABLE_REQ _IO(QSEECOM_IOC_MAGIC, 11) +#define QSEECOM_IOCTL_PERF_DISABLE_REQ _IO(QSEECOM_IOC_MAGIC, 12) +#define QSEECOM_IOCTL_LOAD_EXTERNAL_ELF_REQ _IOWR(QSEECOM_IOC_MAGIC, 13, struct qseecom_load_img_req) +#define QSEECOM_IOCTL_UNLOAD_EXTERNAL_ELF_REQ _IO(QSEECOM_IOC_MAGIC, 14) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define QSEECOM_IOCTL_APP_LOADED_QUERY_REQ _IOWR(QSEECOM_IOC_MAGIC, 15, struct qseecom_qseos_app_load_query) +#define QSEECOM_IOCTL_SEND_CMD_SERVICE_REQ _IOWR(QSEECOM_IOC_MAGIC, 16, struct qseecom_send_svc_cmd_req) +#define QSEECOM_IOCTL_CREATE_KEY_REQ _IOWR(QSEECOM_IOC_MAGIC, 17, struct qseecom_create_key_req) +#define QSEECOM_IOCTL_WIPE_KEY_REQ _IOWR(QSEECOM_IOC_MAGIC, 18, struct qseecom_wipe_key_req) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define QSEECOM_IOCTL_SAVE_PARTITION_HASH_REQ _IOWR(QSEECOM_IOC_MAGIC, 19, struct qseecom_save_partition_hash_req) +#define QSEECOM_IOCTL_IS_ES_ACTIVATED_REQ _IOWR(QSEECOM_IOC_MAGIC, 20, struct qseecom_is_es_activated_req) +#define QSEECOM_IOCTL_SEND_MODFD_RESP _IOWR(QSEECOM_IOC_MAGIC, 21, struct qseecom_send_modfd_listener_resp) +#define QSEECOM_IOCTL_SET_BUS_SCALING_REQ _IOWR(QSEECOM_IOC_MAGIC, 23, int) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define QSEECOM_IOCTL_UPDATE_KEY_USER_INFO_REQ _IOWR(QSEECOM_IOC_MAGIC, 24, struct qseecom_update_key_userinfo_req) +#define QSEECOM_QTEEC_IOCTL_OPEN_SESSION_REQ _IOWR(QSEECOM_IOC_MAGIC, 30, struct qseecom_qteec_modfd_req) +#define QSEECOM_QTEEC_IOCTL_CLOSE_SESSION_REQ _IOWR(QSEECOM_IOC_MAGIC, 31, struct qseecom_qteec_req) +#define QSEECOM_QTEEC_IOCTL_INVOKE_MODFD_CMD_REQ _IOWR(QSEECOM_IOC_MAGIC, 32, struct qseecom_qteec_modfd_req) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define QSEECOM_QTEEC_IOCTL_REQUEST_CANCELLATION_REQ _IOWR(QSEECOM_IOC_MAGIC, 33, struct qseecom_qteec_modfd_req) +#endif + diff --git a/kernel-headers/linux/rmnet_data.h b/kernel-headers/linux/rmnet_data.h new file mode 100644 index 0000000..a043690 --- /dev/null +++ b/kernel-headers/linux/rmnet_data.h @@ -0,0 +1,134 @@ +/**************************************************************************** + **************************************************************************** + *** + *** This header was automatically generated from a Linux kernel header + *** of the same name, to make information necessary for userspace to + *** call into the kernel available to libc. It contains only constants, + *** structures, and macros generated from the original header, and thus, + *** contains no copyrightable information. + *** + *** To edit the content of this header, modify the corresponding + *** source file (e.g. under external/kernel-headers/original/) then + *** run bionic/libc/kernel/tools/update_all.py + *** + *** Any manual change here will be lost the next time this script will + *** be run. You've been warned! + *** + **************************************************************************** + ****************************************************************************/ +#ifndef _RMNET_DATA_H_ +#define _RMNET_DATA_H_ +#define RMNET_LOCAL_LOGICAL_ENDPOINT -1 +#define RMNET_EGRESS_FORMAT__RESERVED__ (1<<0) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define RMNET_EGRESS_FORMAT_MAP (1<<1) +#define RMNET_EGRESS_FORMAT_AGGREGATION (1<<2) +#define RMNET_EGRESS_FORMAT_MUXING (1<<3) +#define RMNET_EGRESS_FORMAT_MAP_CKSUMV3 (1<<4) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define RMNET_INGRESS_FIX_ETHERNET (1<<0) +#define RMNET_INGRESS_FORMAT_MAP (1<<1) +#define RMNET_INGRESS_FORMAT_DEAGGREGATION (1<<2) +#define RMNET_INGRESS_FORMAT_DEMUXING (1<<3) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define RMNET_INGRESS_FORMAT_MAP_COMMANDS (1<<4) +#define RMNET_INGRESS_FORMAT_MAP_CKSUMV3 (1<<5) +#define RMNET_NETLINK_PROTO 31 +#define RMNET_MAX_STR_LEN 16 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define RMNET_NL_DATA_MAX_LEN 64 +#define RMNET_NETLINK_MSG_COMMAND 0 +#define RMNET_NETLINK_MSG_RETURNCODE 1 +#define RMNET_NETLINK_MSG_RETURNDATA 2 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct rmnet_nl_msg_s { + uint16_t reserved; + uint16_t message_type; + uint16_t reserved2:14; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint16_t crd:2; + union { + uint16_t arg_length; + uint16_t return_code; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + }; + union { + uint8_t data[RMNET_NL_DATA_MAX_LEN]; + struct { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint8_t dev[RMNET_MAX_STR_LEN]; + uint32_t flags; + uint16_t agg_size; + uint16_t agg_count; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint8_t tail_spacing; + } data_format; + struct { + uint8_t dev[RMNET_MAX_STR_LEN]; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + int32_t ep_id; + uint8_t operating_mode; + uint8_t next_dev[RMNET_MAX_STR_LEN]; + } local_ep_config; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + struct { + uint32_t id; + uint8_t vnd_name[RMNET_MAX_STR_LEN]; + } vnd; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + struct { + uint32_t id; + uint32_t map_flow_id; + uint32_t tc_flow_id; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + } flow_control; + }; +}; +enum rmnet_netlink_message_types_e { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + RMNET_NETLINK_ASSOCIATE_NETWORK_DEVICE, + RMNET_NETLINK_UNASSOCIATE_NETWORK_DEVICE, + RMNET_NETLINK_GET_NETWORK_DEVICE_ASSOCIATED, + RMNET_NETLINK_SET_LINK_EGRESS_DATA_FORMAT, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + RMNET_NETLINK_GET_LINK_EGRESS_DATA_FORMAT, + RMNET_NETLINK_SET_LINK_INGRESS_DATA_FORMAT, + RMNET_NETLINK_GET_LINK_INGRESS_DATA_FORMAT, + RMNET_NETLINK_SET_LOGICAL_EP_CONFIG, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + RMNET_NETLINK_UNSET_LOGICAL_EP_CONFIG, + RMNET_NETLINK_GET_LOGICAL_EP_CONFIG, + RMNET_NETLINK_NEW_VND, + RMNET_NETLINK_NEW_VND_WITH_PREFIX, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + RMNET_NETLINK_GET_VND_NAME, + RMNET_NETLINK_FREE_VND, + RMNET_NETLINK_ADD_VND_TC_FLOW, + RMNET_NETLINK_DEL_VND_TC_FLOW +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +enum rmnet_config_endpoint_modes_e { + RMNET_EPMODE_NONE, + RMNET_EPMODE_VND, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + RMNET_EPMODE_BRIDGE, + RMNET_EPMODE_LENGTH +}; +enum rmnet_config_return_codes_e { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + RMNET_CONFIG_OK, + RMNET_CONFIG_UNKNOWN_MESSAGE, + RMNET_CONFIG_UNKNOWN_ERROR, + RMNET_CONFIG_NOMEM, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + RMNET_CONFIG_DEVICE_IN_USE, + RMNET_CONFIG_INVALID_REQUEST, + RMNET_CONFIG_NO_SUCH_DEVICE, + RMNET_CONFIG_BAD_ARGUMENTS, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + RMNET_CONFIG_BAD_EGRESS_DEVICE, + RMNET_CONFIG_TC_HANDLE_FULL +}; +#endif +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + diff --git a/kernel-headers/linux/sockev.h b/kernel-headers/linux/sockev.h new file mode 100644 index 0000000..2703d67 --- /dev/null +++ b/kernel-headers/linux/sockev.h @@ -0,0 +1,45 @@ +/**************************************************************************** + **************************************************************************** + *** + *** This header was automatically generated from a Linux kernel header + *** of the same name, to make information necessary for userspace to + *** call into the kernel available to libc. It contains only constants, + *** structures, and macros generated from the original header, and thus, + *** contains no copyrightable information. + *** + *** To edit the content of this header, modify the corresponding + *** source file (e.g. under external/kernel-headers/original/) then + *** run bionic/libc/kernel/tools/update_all.py + *** + *** Any manual change here will be lost the next time this script will + *** be run. You've been warned! + *** + **************************************************************************** + ****************************************************************************/ +#ifndef _SOCKEV_H_ +#define _SOCKEV_H_ +#include <linux/types.h> +#include <linux/netlink.h> +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#include <linux/socket.h> +enum sknetlink_groups { + SKNLGRP_UNICAST, + SKNLGRP_SOCKEV, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __SKNLGRP_MAX +}; +#define SOCKEV_STR_MAX 32 +struct sknlsockevmsg { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u8 event[SOCKEV_STR_MAX]; + __u32 pid; + __u16 skfamily; + __u8 skstate; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u8 skprotocol; + __u16 sktype; + __u64 skflags; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#endif + diff --git a/kernel-headers/linux/sockios.h b/kernel-headers/linux/sockios.h new file mode 100644 index 0000000..aa303b9 --- /dev/null +++ b/kernel-headers/linux/sockios.h @@ -0,0 +1,119 @@ +/**************************************************************************** + **************************************************************************** + *** + *** This header was automatically generated from a Linux kernel header + *** of the same name, to make information necessary for userspace to + *** call into the kernel available to libc. It contains only constants, + *** structures, and macros generated from the original header, and thus, + *** contains no copyrightable information. + *** + *** To edit the content of this header, modify the corresponding + *** source file (e.g. under external/kernel-headers/original/) then + *** run bionic/libc/kernel/tools/update_all.py + *** + *** Any manual change here will be lost the next time this script will + *** be run. You've been warned! + *** + **************************************************************************** + ****************************************************************************/ +#ifndef _LINUX_SOCKIOS_H +#define _LINUX_SOCKIOS_H +#include <asm/sockios.h> +#define SIOCINQ FIONREAD +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SIOCOUTQ TIOCOUTQ +#define SIOCADDRT 0x890B +#define SIOCDELRT 0x890C +#define SIOCRTMSG 0x890D +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SIOCGIFNAME 0x8910 +#define SIOCSIFLINK 0x8911 +#define SIOCGIFCONF 0x8912 +#define SIOCGIFFLAGS 0x8913 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SIOCSIFFLAGS 0x8914 +#define SIOCGIFADDR 0x8915 +#define SIOCSIFADDR 0x8916 +#define SIOCGIFDSTADDR 0x8917 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SIOCSIFDSTADDR 0x8918 +#define SIOCGIFBRDADDR 0x8919 +#define SIOCSIFBRDADDR 0x891a +#define SIOCGIFNETMASK 0x891b +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SIOCSIFNETMASK 0x891c +#define SIOCGIFMETRIC 0x891d +#define SIOCSIFMETRIC 0x891e +#define SIOCGIFMEM 0x891f +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SIOCSIFMEM 0x8920 +#define SIOCGIFMTU 0x8921 +#define SIOCSIFMTU 0x8922 +#define SIOCSIFNAME 0x8923 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SIOCSIFHWADDR 0x8924 +#define SIOCGIFENCAP 0x8925 +#define SIOCSIFENCAP 0x8926 +#define SIOCGIFHWADDR 0x8927 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SIOCGIFSLAVE 0x8929 +#define SIOCSIFSLAVE 0x8930 +#define SIOCADDMULTI 0x8931 +#define SIOCDELMULTI 0x8932 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SIOCGIFINDEX 0x8933 +#define SIOGIFINDEX SIOCGIFINDEX +#define SIOCSIFPFLAGS 0x8934 +#define SIOCGIFPFLAGS 0x8935 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SIOCDIFADDR 0x8936 +#define SIOCSIFHWBROADCAST 0x8937 +#define SIOCGIFCOUNT 0x8938 +#define SIOCKILLADDR 0x8939 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SIOCGIFBR 0x8940 +#define SIOCSIFBR 0x8941 +#define SIOCGIFTXQLEN 0x8942 +#define SIOCSIFTXQLEN 0x8943 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SIOCETHTOOL 0x8946 +#define SIOCGMIIPHY 0x8947 +#define SIOCGMIIREG 0x8948 +#define SIOCSMIIREG 0x8949 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SIOCWANDEV 0x894A +#define SIOCOUTQNSD 0x894B +#define SIOCDARP 0x8953 +#define SIOCGARP 0x8954 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SIOCSARP 0x8955 +#define SIOCDRARP 0x8960 +#define SIOCGRARP 0x8961 +#define SIOCSRARP 0x8962 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SIOCGIFMAP 0x8970 +#define SIOCSIFMAP 0x8971 +#define SIOCADDDLCI 0x8980 +#define SIOCDELDLCI 0x8981 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SIOCGIFVLAN 0x8982 +#define SIOCSIFVLAN 0x8983 +#define SIOCBONDENSLAVE 0x8990 +#define SIOCBONDRELEASE 0x8991 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SIOCBONDSETHWADDR 0x8992 +#define SIOCBONDSLAVEINFOQUERY 0x8993 +#define SIOCBONDINFOQUERY 0x8994 +#define SIOCBONDCHANGEACTIVE 0x8995 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SIOCBRADDBR 0x89a0 +#define SIOCBRDELBR 0x89a1 +#define SIOCBRADDIF 0x89a2 +#define SIOCBRDELIF 0x89a3 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SIOCSHWTSTAMP 0x89b0 +#define SIOCDEVPRIVATE 0x89F0 +#define SIOCPROTOPRIVATE 0x89E0 +#endif +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + diff --git a/kernel-headers/linux/sound/lsm_params.h b/kernel-headers/linux/sound/lsm_params.h new file mode 100644 index 0000000..34c6c55 --- /dev/null +++ b/kernel-headers/linux/sound/lsm_params.h @@ -0,0 +1,95 @@ +/**************************************************************************** + **************************************************************************** + *** + *** This header was automatically generated from a Linux kernel header + *** of the same name, to make information necessary for userspace to + *** call into the kernel available to libc. It contains only constants, + *** structures, and macros generated from the original header, and thus, + *** contains no copyrightable information. + *** + *** To edit the content of this header, modify the corresponding + *** source file (e.g. under external/kernel-headers/original/) then + *** run bionic/libc/kernel/tools/update_all.py + *** + *** Any manual change here will be lost the next time this script will + *** be run. You've been warned! + *** + **************************************************************************** + ****************************************************************************/ +#ifndef _UAPI_LSM_PARAMS_H__ +#define _UAPI_LSM_PARAMS_H__ +#include <linux/types.h> +#include <sound/asound.h> +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SNDRV_LSM_VERSION SNDRV_PROTOCOL_VERSION(0, 1, 0) +enum lsm_app_id { + LSM_VOICE_WAKEUP_APP_ID = 1, + LSM_VOICE_WAKEUP_APP_ID_V2 = 2, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +enum lsm_detection_mode { + LSM_MODE_KEYWORD_ONLY_DETECTION = 1, + LSM_MODE_USER_KEYWORD_DETECTION +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +enum lsm_vw_status { + LSM_VOICE_WAKEUP_STATUS_RUNNING = 1, + LSM_VOICE_WAKEUP_STATUS_DETECTED, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + LSM_VOICE_WAKEUP_STATUS_END_SPEECH, + LSM_VOICE_WAKEUP_STATUS_REJECTED +}; +struct snd_lsm_sound_model { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u8 __user *data; + __u32 data_size; + enum lsm_detection_mode detection_mode; + __u16 min_keyw_confidence; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u16 min_user_confidence; + bool detect_failure; +}; +struct snd_lsm_sound_model_v2 { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u8 __user *data; + __u8 *confidence_level; + __u32 data_size; + enum lsm_detection_mode detection_mode; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u8 num_confidence_levels; + bool detect_failure; +}; +struct snd_lsm_session_data { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + enum lsm_app_id app_id; +}; +struct snd_lsm_event_status { + __u16 status; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u16 payload_size; + __u8 payload[0]; +}; +struct snd_lsm_detection_params { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u8 *conf_level; + enum lsm_detection_mode detect_mode; + __u8 num_confidence_levels; + bool detect_failure; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +#define SNDRV_LSM_REG_SND_MODEL _IOW('U', 0x00, struct snd_lsm_sound_model) +#define SNDRV_LSM_DEREG_SND_MODEL _IOW('U', 0x01, int) +#define SNDRV_LSM_EVENT_STATUS _IOW('U', 0x02, struct snd_lsm_event_status) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SNDRV_LSM_ABORT_EVENT _IOW('U', 0x03, int) +#define SNDRV_LSM_START _IOW('U', 0x04, int) +#define SNDRV_LSM_STOP _IOW('U', 0x05, int) +#define SNDRV_LSM_SET_SESSION_DATA _IOW('U', 0x06, struct snd_lsm_session_data) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SNDRV_LSM_REG_SND_MODEL_V2 _IOW('U', 0x07, struct snd_lsm_sound_model_v2) +#define SNDRV_LSM_LAB_CONTROL _IOW('U', 0x08, uint32_t) +#define SNDRV_LSM_STOP_LAB _IO('U', 0x09) +#define SNDRV_LSM_SET_PARAMS _IOW('U', 0x0A, struct snd_lsm_detection_params) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#endif + diff --git a/kernel-headers/linux/v4l2-common.h b/kernel-headers/linux/v4l2-common.h new file mode 100644 index 0000000..5c2b5fc --- /dev/null +++ b/kernel-headers/linux/v4l2-common.h @@ -0,0 +1,46 @@ +/**************************************************************************** + **************************************************************************** + *** + *** This header was automatically generated from a Linux kernel header + *** of the same name, to make information necessary for userspace to + *** call into the kernel available to libc. It contains only constants, + *** structures, and macros generated from the original header, and thus, + *** contains no copyrightable information. + *** + *** To edit the content of this header, modify the corresponding + *** source file (e.g. under external/kernel-headers/original/) then + *** run bionic/libc/kernel/tools/update_all.py + *** + *** Any manual change here will be lost the next time this script will + *** be run. You've been warned! + *** + **************************************************************************** + ****************************************************************************/ +#ifndef __V4L2_COMMON__ +#define __V4L2_COMMON__ +#define V4L2_SEL_TGT_CROP 0x0000 +#define V4L2_SEL_TGT_CROP_DEFAULT 0x0001 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_SEL_TGT_CROP_BOUNDS 0x0002 +#define V4L2_SEL_TGT_COMPOSE 0x0100 +#define V4L2_SEL_TGT_COMPOSE_DEFAULT 0x0101 +#define V4L2_SEL_TGT_COMPOSE_BOUNDS 0x0102 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_SEL_TGT_COMPOSE_PADDED 0x0103 +#define V4L2_SEL_TGT_CROP_ACTIVE V4L2_SEL_TGT_CROP +#define V4L2_SEL_TGT_COMPOSE_ACTIVE V4L2_SEL_TGT_COMPOSE +#define V4L2_SUBDEV_SEL_TGT_CROP_ACTUAL V4L2_SEL_TGT_CROP +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_SUBDEV_SEL_TGT_COMPOSE_ACTUAL V4L2_SEL_TGT_COMPOSE +#define V4L2_SUBDEV_SEL_TGT_CROP_BOUNDS V4L2_SEL_TGT_CROP_BOUNDS +#define V4L2_SUBDEV_SEL_TGT_COMPOSE_BOUNDS V4L2_SEL_TGT_COMPOSE_BOUNDS +#define V4L2_SEL_FLAG_GE (1 << 0) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_SEL_FLAG_LE (1 << 1) +#define V4L2_SEL_FLAG_KEEP_CONFIG (1 << 2) +#define V4L2_SUBDEV_SEL_FLAG_SIZE_GE V4L2_SEL_FLAG_GE +#define V4L2_SUBDEV_SEL_FLAG_SIZE_LE V4L2_SEL_FLAG_LE +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_SUBDEV_SEL_FLAG_KEEP_CONFIG V4L2_SEL_FLAG_KEEP_CONFIG +#endif + diff --git a/kernel-headers/linux/v4l2-controls.h b/kernel-headers/linux/v4l2-controls.h new file mode 100644 index 0000000..46d420e --- /dev/null +++ b/kernel-headers/linux/v4l2-controls.h @@ -0,0 +1,1262 @@ +/**************************************************************************** + **************************************************************************** + *** + *** This header was automatically generated from a Linux kernel header + *** of the same name, to make information necessary for userspace to + *** call into the kernel available to libc. It contains only constants, + *** structures, and macros generated from the original header, and thus, + *** contains no copyrightable information. + *** + *** To edit the content of this header, modify the corresponding + *** source file (e.g. under external/kernel-headers/original/) then + *** run bionic/libc/kernel/tools/update_all.py + *** + *** Any manual change here will be lost the next time this script will + *** be run. You've been warned! + *** + **************************************************************************** + ****************************************************************************/ +#ifndef __LINUX_V4L2_CONTROLS_H +#define __LINUX_V4L2_CONTROLS_H +#define V4L2_CTRL_CLASS_USER 0x00980000 +#define V4L2_CTRL_CLASS_MPEG 0x00990000 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CTRL_CLASS_CAMERA 0x009a0000 +#define V4L2_CTRL_CLASS_FM_TX 0x009b0000 +#define V4L2_CTRL_CLASS_FLASH 0x009c0000 +#define V4L2_CTRL_CLASS_JPEG 0x009d0000 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CTRL_CLASS_IMAGE_SOURCE 0x009e0000 +#define V4L2_CTRL_CLASS_IMAGE_PROC 0x009f0000 +#define V4L2_CTRL_CLASS_DV 0x00a00000 +#define V4L2_CTRL_CLASS_FM_RX 0x00a10000 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_BASE (V4L2_CTRL_CLASS_USER | 0x900) +#define V4L2_CID_USER_BASE V4L2_CID_BASE +#define V4L2_CID_USER_CLASS (V4L2_CTRL_CLASS_USER | 1) +#define V4L2_CID_BRIGHTNESS (V4L2_CID_BASE+0) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_CONTRAST (V4L2_CID_BASE+1) +#define V4L2_CID_SATURATION (V4L2_CID_BASE+2) +#define V4L2_CID_HUE (V4L2_CID_BASE+3) +#define V4L2_CID_AUDIO_VOLUME (V4L2_CID_BASE+5) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_AUDIO_BALANCE (V4L2_CID_BASE+6) +#define V4L2_CID_AUDIO_BASS (V4L2_CID_BASE+7) +#define V4L2_CID_AUDIO_TREBLE (V4L2_CID_BASE+8) +#define V4L2_CID_AUDIO_MUTE (V4L2_CID_BASE+9) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_AUDIO_LOUDNESS (V4L2_CID_BASE+10) +#define V4L2_CID_BLACK_LEVEL (V4L2_CID_BASE+11) +#define V4L2_CID_AUTO_WHITE_BALANCE (V4L2_CID_BASE+12) +#define V4L2_CID_DO_WHITE_BALANCE (V4L2_CID_BASE+13) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_RED_BALANCE (V4L2_CID_BASE+14) +#define V4L2_CID_BLUE_BALANCE (V4L2_CID_BASE+15) +#define V4L2_CID_GAMMA (V4L2_CID_BASE+16) +#define V4L2_CID_WHITENESS (V4L2_CID_GAMMA) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_EXPOSURE (V4L2_CID_BASE+17) +#define V4L2_CID_AUTOGAIN (V4L2_CID_BASE+18) +#define V4L2_CID_GAIN (V4L2_CID_BASE+19) +#define V4L2_CID_HFLIP (V4L2_CID_BASE+20) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_VFLIP (V4L2_CID_BASE+21) +#define V4L2_CID_POWER_LINE_FREQUENCY (V4L2_CID_BASE+24) +enum v4l2_power_line_frequency { + V4L2_CID_POWER_LINE_FREQUENCY_DISABLED = 0, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_CID_POWER_LINE_FREQUENCY_50HZ = 1, + V4L2_CID_POWER_LINE_FREQUENCY_60HZ = 2, + V4L2_CID_POWER_LINE_FREQUENCY_AUTO = 3, +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_HUE_AUTO (V4L2_CID_BASE+25) +#define V4L2_CID_WHITE_BALANCE_TEMPERATURE (V4L2_CID_BASE+26) +#define V4L2_CID_SHARPNESS (V4L2_CID_BASE+27) +#define V4L2_CID_BACKLIGHT_COMPENSATION (V4L2_CID_BASE+28) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_CHROMA_AGC (V4L2_CID_BASE+29) +#define V4L2_CID_COLOR_KILLER (V4L2_CID_BASE+30) +#define V4L2_CID_COLORFX (V4L2_CID_BASE+31) +enum v4l2_colorfx { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_COLORFX_NONE = 0, + V4L2_COLORFX_BW = 1, + V4L2_COLORFX_SEPIA = 2, + V4L2_COLORFX_NEGATIVE = 3, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_COLORFX_EMBOSS = 4, + V4L2_COLORFX_SKETCH = 5, + V4L2_COLORFX_SKY_BLUE = 6, + V4L2_COLORFX_GRASS_GREEN = 7, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_COLORFX_SKIN_WHITEN = 8, + V4L2_COLORFX_VIVID = 9, + V4L2_COLORFX_AQUA = 10, + V4L2_COLORFX_ART_FREEZE = 11, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_COLORFX_SILHOUETTE = 12, + V4L2_COLORFX_SOLARIZATION = 13, + V4L2_COLORFX_ANTIQUE = 14, + V4L2_COLORFX_SET_CBCR = 15, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +#define V4L2_CID_AUTOBRIGHTNESS (V4L2_CID_BASE+32) +#define V4L2_CID_BAND_STOP_FILTER (V4L2_CID_BASE+33) +#define V4L2_CID_ROTATE (V4L2_CID_BASE+34) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_BG_COLOR (V4L2_CID_BASE+35) +#define V4L2_CID_CHROMA_GAIN (V4L2_CID_BASE+36) +#define V4L2_CID_ILLUMINATORS_1 (V4L2_CID_BASE+37) +#define V4L2_CID_ILLUMINATORS_2 (V4L2_CID_BASE+38) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_MIN_BUFFERS_FOR_CAPTURE (V4L2_CID_BASE+39) +#define V4L2_CID_MIN_BUFFERS_FOR_OUTPUT (V4L2_CID_BASE+40) +#define V4L2_CID_ALPHA_COMPONENT (V4L2_CID_BASE+41) +#define V4L2_CID_COLORFX_CBCR (V4L2_CID_BASE+42) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_LASTP1 (V4L2_CID_BASE+43) +#define V4L2_CID_SPECIAL_EFFECT (V4L2_CID_BASE+44) +#define V4L2_CID_USER_MEYE_BASE (V4L2_CID_USER_BASE + 0x1000) +#define V4L2_CID_USER_BTTV_BASE (V4L2_CID_USER_BASE + 0x1010) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_USER_S2255_BASE (V4L2_CID_USER_BASE + 0x1030) +#define V4L2_CID_USER_SI476X_BASE (V4L2_CID_USER_BASE + 0x1040) +#define V4L2_CID_MPEG_BASE (V4L2_CTRL_CLASS_MPEG | 0x900) +#define V4L2_CID_MPEG_CLASS (V4L2_CTRL_CLASS_MPEG | 1) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_MPEG_STREAM_TYPE (V4L2_CID_MPEG_BASE+0) +enum v4l2_mpeg_stream_type { + V4L2_MPEG_STREAM_TYPE_MPEG2_PS = 0, + V4L2_MPEG_STREAM_TYPE_MPEG2_TS = 1, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_STREAM_TYPE_MPEG1_SS = 2, + V4L2_MPEG_STREAM_TYPE_MPEG2_DVD = 3, + V4L2_MPEG_STREAM_TYPE_MPEG1_VCD = 4, + V4L2_MPEG_STREAM_TYPE_MPEG2_SVCD = 5, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +#define V4L2_CID_MPEG_STREAM_PID_PMT (V4L2_CID_MPEG_BASE+1) +#define V4L2_CID_MPEG_STREAM_PID_AUDIO (V4L2_CID_MPEG_BASE+2) +#define V4L2_CID_MPEG_STREAM_PID_VIDEO (V4L2_CID_MPEG_BASE+3) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_MPEG_STREAM_PID_PCR (V4L2_CID_MPEG_BASE+4) +#define V4L2_CID_MPEG_STREAM_PES_ID_AUDIO (V4L2_CID_MPEG_BASE+5) +#define V4L2_CID_MPEG_STREAM_PES_ID_VIDEO (V4L2_CID_MPEG_BASE+6) +#define V4L2_CID_MPEG_STREAM_VBI_FMT (V4L2_CID_MPEG_BASE+7) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +enum v4l2_mpeg_stream_vbi_fmt { + V4L2_MPEG_STREAM_VBI_FMT_NONE = 0, + V4L2_MPEG_STREAM_VBI_FMT_IVTV = 1, +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ (V4L2_CID_MPEG_BASE+100) +enum v4l2_mpeg_audio_sampling_freq { + V4L2_MPEG_AUDIO_SAMPLING_FREQ_44100 = 0, + V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000 = 1, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_AUDIO_SAMPLING_FREQ_32000 = 2, +}; +#define V4L2_CID_MPEG_AUDIO_ENCODING (V4L2_CID_MPEG_BASE+101) +enum v4l2_mpeg_audio_encoding { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_AUDIO_ENCODING_LAYER_1 = 0, + V4L2_MPEG_AUDIO_ENCODING_LAYER_2 = 1, + V4L2_MPEG_AUDIO_ENCODING_LAYER_3 = 2, + V4L2_MPEG_AUDIO_ENCODING_AAC = 3, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_AUDIO_ENCODING_AC3 = 4, +}; +#define V4L2_CID_MPEG_AUDIO_L1_BITRATE (V4L2_CID_MPEG_BASE+102) +enum v4l2_mpeg_audio_l1_bitrate { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_AUDIO_L1_BITRATE_32K = 0, + V4L2_MPEG_AUDIO_L1_BITRATE_64K = 1, + V4L2_MPEG_AUDIO_L1_BITRATE_96K = 2, + V4L2_MPEG_AUDIO_L1_BITRATE_128K = 3, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_AUDIO_L1_BITRATE_160K = 4, + V4L2_MPEG_AUDIO_L1_BITRATE_192K = 5, + V4L2_MPEG_AUDIO_L1_BITRATE_224K = 6, + V4L2_MPEG_AUDIO_L1_BITRATE_256K = 7, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_AUDIO_L1_BITRATE_288K = 8, + V4L2_MPEG_AUDIO_L1_BITRATE_320K = 9, + V4L2_MPEG_AUDIO_L1_BITRATE_352K = 10, + V4L2_MPEG_AUDIO_L1_BITRATE_384K = 11, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_AUDIO_L1_BITRATE_416K = 12, + V4L2_MPEG_AUDIO_L1_BITRATE_448K = 13, +}; +#define V4L2_CID_MPEG_AUDIO_L2_BITRATE (V4L2_CID_MPEG_BASE+103) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +enum v4l2_mpeg_audio_l2_bitrate { + V4L2_MPEG_AUDIO_L2_BITRATE_32K = 0, + V4L2_MPEG_AUDIO_L2_BITRATE_48K = 1, + V4L2_MPEG_AUDIO_L2_BITRATE_56K = 2, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_AUDIO_L2_BITRATE_64K = 3, + V4L2_MPEG_AUDIO_L2_BITRATE_80K = 4, + V4L2_MPEG_AUDIO_L2_BITRATE_96K = 5, + V4L2_MPEG_AUDIO_L2_BITRATE_112K = 6, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_AUDIO_L2_BITRATE_128K = 7, + V4L2_MPEG_AUDIO_L2_BITRATE_160K = 8, + V4L2_MPEG_AUDIO_L2_BITRATE_192K = 9, + V4L2_MPEG_AUDIO_L2_BITRATE_224K = 10, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_AUDIO_L2_BITRATE_256K = 11, + V4L2_MPEG_AUDIO_L2_BITRATE_320K = 12, + V4L2_MPEG_AUDIO_L2_BITRATE_384K = 13, +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_MPEG_AUDIO_L3_BITRATE (V4L2_CID_MPEG_BASE+104) +enum v4l2_mpeg_audio_l3_bitrate { + V4L2_MPEG_AUDIO_L3_BITRATE_32K = 0, + V4L2_MPEG_AUDIO_L3_BITRATE_40K = 1, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_AUDIO_L3_BITRATE_48K = 2, + V4L2_MPEG_AUDIO_L3_BITRATE_56K = 3, + V4L2_MPEG_AUDIO_L3_BITRATE_64K = 4, + V4L2_MPEG_AUDIO_L3_BITRATE_80K = 5, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_AUDIO_L3_BITRATE_96K = 6, + V4L2_MPEG_AUDIO_L3_BITRATE_112K = 7, + V4L2_MPEG_AUDIO_L3_BITRATE_128K = 8, + V4L2_MPEG_AUDIO_L3_BITRATE_160K = 9, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_AUDIO_L3_BITRATE_192K = 10, + V4L2_MPEG_AUDIO_L3_BITRATE_224K = 11, + V4L2_MPEG_AUDIO_L3_BITRATE_256K = 12, + V4L2_MPEG_AUDIO_L3_BITRATE_320K = 13, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +#define V4L2_CID_MPEG_AUDIO_MODE (V4L2_CID_MPEG_BASE+105) +enum v4l2_mpeg_audio_mode { + V4L2_MPEG_AUDIO_MODE_STEREO = 0, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_AUDIO_MODE_JOINT_STEREO = 1, + V4L2_MPEG_AUDIO_MODE_DUAL = 2, + V4L2_MPEG_AUDIO_MODE_MONO = 3, +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_MPEG_AUDIO_MODE_EXTENSION (V4L2_CID_MPEG_BASE+106) +enum v4l2_mpeg_audio_mode_extension { + V4L2_MPEG_AUDIO_MODE_EXTENSION_BOUND_4 = 0, + V4L2_MPEG_AUDIO_MODE_EXTENSION_BOUND_8 = 1, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_AUDIO_MODE_EXTENSION_BOUND_12 = 2, + V4L2_MPEG_AUDIO_MODE_EXTENSION_BOUND_16 = 3, +}; +#define V4L2_CID_MPEG_AUDIO_EMPHASIS (V4L2_CID_MPEG_BASE+107) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +enum v4l2_mpeg_audio_emphasis { + V4L2_MPEG_AUDIO_EMPHASIS_NONE = 0, + V4L2_MPEG_AUDIO_EMPHASIS_50_DIV_15_uS = 1, + V4L2_MPEG_AUDIO_EMPHASIS_CCITT_J17 = 2, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +#define V4L2_CID_MPEG_AUDIO_CRC (V4L2_CID_MPEG_BASE+108) +enum v4l2_mpeg_audio_crc { + V4L2_MPEG_AUDIO_CRC_NONE = 0, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_AUDIO_CRC_CRC16 = 1, +}; +#define V4L2_CID_MPEG_AUDIO_MUTE (V4L2_CID_MPEG_BASE+109) +#define V4L2_CID_MPEG_AUDIO_AAC_BITRATE (V4L2_CID_MPEG_BASE+110) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_MPEG_AUDIO_AC3_BITRATE (V4L2_CID_MPEG_BASE+111) +enum v4l2_mpeg_audio_ac3_bitrate { + V4L2_MPEG_AUDIO_AC3_BITRATE_32K = 0, + V4L2_MPEG_AUDIO_AC3_BITRATE_40K = 1, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_AUDIO_AC3_BITRATE_48K = 2, + V4L2_MPEG_AUDIO_AC3_BITRATE_56K = 3, + V4L2_MPEG_AUDIO_AC3_BITRATE_64K = 4, + V4L2_MPEG_AUDIO_AC3_BITRATE_80K = 5, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_AUDIO_AC3_BITRATE_96K = 6, + V4L2_MPEG_AUDIO_AC3_BITRATE_112K = 7, + V4L2_MPEG_AUDIO_AC3_BITRATE_128K = 8, + V4L2_MPEG_AUDIO_AC3_BITRATE_160K = 9, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_AUDIO_AC3_BITRATE_192K = 10, + V4L2_MPEG_AUDIO_AC3_BITRATE_224K = 11, + V4L2_MPEG_AUDIO_AC3_BITRATE_256K = 12, + V4L2_MPEG_AUDIO_AC3_BITRATE_320K = 13, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_AUDIO_AC3_BITRATE_384K = 14, + V4L2_MPEG_AUDIO_AC3_BITRATE_448K = 15, + V4L2_MPEG_AUDIO_AC3_BITRATE_512K = 16, + V4L2_MPEG_AUDIO_AC3_BITRATE_576K = 17, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_AUDIO_AC3_BITRATE_640K = 18, +}; +#define V4L2_CID_MPEG_AUDIO_DEC_PLAYBACK (V4L2_CID_MPEG_BASE+112) +enum v4l2_mpeg_audio_dec_playback { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_AUDIO_DEC_PLAYBACK_AUTO = 0, + V4L2_MPEG_AUDIO_DEC_PLAYBACK_STEREO = 1, + V4L2_MPEG_AUDIO_DEC_PLAYBACK_LEFT = 2, + V4L2_MPEG_AUDIO_DEC_PLAYBACK_RIGHT = 3, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_AUDIO_DEC_PLAYBACK_MONO = 4, + V4L2_MPEG_AUDIO_DEC_PLAYBACK_SWAPPED_STEREO = 5, +}; +#define V4L2_CID_MPEG_AUDIO_DEC_MULTILINGUAL_PLAYBACK (V4L2_CID_MPEG_BASE+113) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_MPEG_VIDEO_ENCODING (V4L2_CID_MPEG_BASE+200) +enum v4l2_mpeg_video_encoding { + V4L2_MPEG_VIDEO_ENCODING_MPEG_1 = 0, + V4L2_MPEG_VIDEO_ENCODING_MPEG_2 = 1, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_VIDEO_ENCODING_MPEG_4_AVC = 2, +}; +#define V4L2_CID_MPEG_VIDEO_ASPECT (V4L2_CID_MPEG_BASE+201) +enum v4l2_mpeg_video_aspect { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_VIDEO_ASPECT_1x1 = 0, + V4L2_MPEG_VIDEO_ASPECT_4x3 = 1, + V4L2_MPEG_VIDEO_ASPECT_16x9 = 2, + V4L2_MPEG_VIDEO_ASPECT_221x100 = 3, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +#define V4L2_CID_MPEG_VIDEO_B_FRAMES (V4L2_CID_MPEG_BASE+202) +#define V4L2_CID_MPEG_VIDEO_GOP_SIZE (V4L2_CID_MPEG_BASE+203) +#define V4L2_CID_MPEG_VIDEO_GOP_CLOSURE (V4L2_CID_MPEG_BASE+204) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_MPEG_VIDEO_PULLDOWN (V4L2_CID_MPEG_BASE+205) +#define V4L2_CID_MPEG_VIDEO_BITRATE_MODE (V4L2_CID_MPEG_BASE+206) +enum v4l2_mpeg_video_bitrate_mode { + V4L2_MPEG_VIDEO_BITRATE_MODE_VBR = 0, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_VIDEO_BITRATE_MODE_CBR = 1, +}; +#define V4L2_CID_MPEG_VIDEO_BITRATE (V4L2_CID_MPEG_BASE+207) +#define V4L2_CID_MPEG_VIDEO_BITRATE_PEAK (V4L2_CID_MPEG_BASE+208) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_MPEG_VIDEO_TEMPORAL_DECIMATION (V4L2_CID_MPEG_BASE+209) +#define V4L2_CID_MPEG_VIDEO_MUTE (V4L2_CID_MPEG_BASE+210) +#define V4L2_CID_MPEG_VIDEO_MUTE_YUV (V4L2_CID_MPEG_BASE+211) +#define V4L2_CID_MPEG_VIDEO_DECODER_SLICE_INTERFACE (V4L2_CID_MPEG_BASE+212) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_MPEG_VIDEO_DECODER_MPEG4_DEBLOCK_FILTER (V4L2_CID_MPEG_BASE+213) +#define V4L2_CID_MPEG_VIDEO_CYCLIC_INTRA_REFRESH_MB (V4L2_CID_MPEG_BASE+214) +#define V4L2_CID_MPEG_VIDEO_FRAME_RC_ENABLE (V4L2_CID_MPEG_BASE+215) +#define V4L2_CID_MPEG_VIDEO_HEADER_MODE (V4L2_CID_MPEG_BASE+216) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +enum v4l2_mpeg_video_header_mode { + V4L2_MPEG_VIDEO_HEADER_MODE_SEPARATE = 0, + V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME = 1, + V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_I_FRAME = 2, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +#define V4L2_CID_MPEG_VIDEO_MAX_REF_PIC (V4L2_CID_MPEG_BASE+217) +#define V4L2_CID_MPEG_VIDEO_MB_RC_ENABLE (V4L2_CID_MPEG_BASE+218) +#define V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MAX_BYTES (V4L2_CID_MPEG_BASE+219) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MAX_MB (V4L2_CID_MPEG_BASE+220) +#define V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MODE (V4L2_CID_MPEG_BASE+221) +enum v4l2_mpeg_video_multi_slice_mode { + V4L2_MPEG_VIDEO_MULTI_SLICE_MODE_SINGLE = 0, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_MB = 1, + V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_BYTES = 2, + V4L2_MPEG_VIDEO_MULTI_SLICE_GOB = 3, +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_MPEG_VIDEO_VBV_SIZE (V4L2_CID_MPEG_BASE+222) +#define V4L2_CID_MPEG_VIDEO_DEC_PTS (V4L2_CID_MPEG_BASE+223) +#define V4L2_CID_MPEG_VIDEO_DEC_FRAME (V4L2_CID_MPEG_BASE+224) +#define V4L2_CID_MPEG_VIDEO_VBV_DELAY (V4L2_CID_MPEG_BASE+225) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_MPEG_VIDEO_REPEAT_SEQ_HEADER (V4L2_CID_MPEG_BASE+226) +#define V4L2_CID_MPEG_VIDEO_H263_I_FRAME_QP (V4L2_CID_MPEG_BASE+300) +#define V4L2_CID_MPEG_VIDEO_H263_P_FRAME_QP (V4L2_CID_MPEG_BASE+301) +#define V4L2_CID_MPEG_VIDEO_H263_B_FRAME_QP (V4L2_CID_MPEG_BASE+302) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_MPEG_VIDEO_H263_MIN_QP (V4L2_CID_MPEG_BASE+303) +#define V4L2_CID_MPEG_VIDEO_H263_MAX_QP (V4L2_CID_MPEG_BASE+304) +#define V4L2_CID_MPEG_VIDEO_H264_I_FRAME_QP (V4L2_CID_MPEG_BASE+350) +#define V4L2_CID_MPEG_VIDEO_H264_P_FRAME_QP (V4L2_CID_MPEG_BASE+351) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_MPEG_VIDEO_H264_B_FRAME_QP (V4L2_CID_MPEG_BASE+352) +#define V4L2_CID_MPEG_VIDEO_H264_MIN_QP (V4L2_CID_MPEG_BASE+353) +#define V4L2_CID_MPEG_VIDEO_H264_MAX_QP (V4L2_CID_MPEG_BASE+354) +#define V4L2_CID_MPEG_VIDEO_H264_8X8_TRANSFORM (V4L2_CID_MPEG_BASE+355) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_MPEG_VIDEO_H264_CPB_SIZE (V4L2_CID_MPEG_BASE+356) +#define V4L2_CID_MPEG_VIDEO_H264_ENTROPY_MODE (V4L2_CID_MPEG_BASE+357) +enum v4l2_mpeg_video_h264_entropy_mode { + V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CAVLC = 0, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CABAC = 1, +}; +#define V4L2_CID_MPEG_VIDEO_H264_I_PERIOD (V4L2_CID_MPEG_BASE+358) +#define V4L2_CID_MPEG_VIDEO_H264_LEVEL (V4L2_CID_MPEG_BASE+359) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +enum v4l2_mpeg_video_h264_level { + V4L2_MPEG_VIDEO_H264_LEVEL_1_0 = 0, + V4L2_MPEG_VIDEO_H264_LEVEL_1B = 1, + V4L2_MPEG_VIDEO_H264_LEVEL_1_1 = 2, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_VIDEO_H264_LEVEL_1_2 = 3, + V4L2_MPEG_VIDEO_H264_LEVEL_1_3 = 4, + V4L2_MPEG_VIDEO_H264_LEVEL_2_0 = 5, + V4L2_MPEG_VIDEO_H264_LEVEL_2_1 = 6, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_VIDEO_H264_LEVEL_2_2 = 7, + V4L2_MPEG_VIDEO_H264_LEVEL_3_0 = 8, + V4L2_MPEG_VIDEO_H264_LEVEL_3_1 = 9, + V4L2_MPEG_VIDEO_H264_LEVEL_3_2 = 10, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_VIDEO_H264_LEVEL_4_0 = 11, + V4L2_MPEG_VIDEO_H264_LEVEL_4_1 = 12, + V4L2_MPEG_VIDEO_H264_LEVEL_4_2 = 13, + V4L2_MPEG_VIDEO_H264_LEVEL_5_0 = 14, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_VIDEO_H264_LEVEL_5_1 = 15, + V4L2_MPEG_VIDEO_H264_LEVEL_5_2 = 16, +}; +#define V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_ALPHA (V4L2_CID_MPEG_BASE+360) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_BETA (V4L2_CID_MPEG_BASE+361) +#define V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_MODE (V4L2_CID_MPEG_BASE+362) +enum v4l2_mpeg_video_h264_loop_filter_mode { + V4L2_MPEG_VIDEO_H264_LOOP_FILTER_MODE_DISABLED = 0, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_VIDEO_H264_LOOP_FILTER_MODE_ENABLED = 1, + V4L2_MPEG_VIDEO_H264_LOOP_FILTER_MODE_DISABLED_AT_SLICE_BOUNDARY + = 2, +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_MPEG_VIDEO_H264_PROFILE (V4L2_CID_MPEG_BASE+363) +enum v4l2_mpeg_video_h264_profile { + V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE = 0, + V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_BASELINE = 1, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_VIDEO_H264_PROFILE_MAIN = 2, + V4L2_MPEG_VIDEO_H264_PROFILE_EXTENDED = 3, + V4L2_MPEG_VIDEO_H264_PROFILE_HIGH = 4, + V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_10 = 5, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_422 = 6, + V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_444_PREDICTIVE = 7, + V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_10_INTRA = 8, + V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_422_INTRA = 9, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_444_INTRA = 10, + V4L2_MPEG_VIDEO_H264_PROFILE_CAVLC_444_INTRA = 11, + V4L2_MPEG_VIDEO_H264_PROFILE_SCALABLE_BASELINE = 12, + V4L2_MPEG_VIDEO_H264_PROFILE_SCALABLE_HIGH = 13, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_VIDEO_H264_PROFILE_SCALABLE_HIGH_INTRA = 14, + V4L2_MPEG_VIDEO_H264_PROFILE_STEREO_HIGH = 15, + V4L2_MPEG_VIDEO_H264_PROFILE_MULTIVIEW_HIGH = 16, + V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_HIGH = 17, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +#define V4L2_CID_MPEG_VIDEO_H264_VUI_EXT_SAR_HEIGHT (V4L2_CID_MPEG_BASE+364) +#define V4L2_CID_MPEG_VIDEO_H264_VUI_EXT_SAR_WIDTH (V4L2_CID_MPEG_BASE+365) +#define V4L2_CID_MPEG_VIDEO_H264_VUI_SAR_ENABLE (V4L2_CID_MPEG_BASE+366) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_MPEG_VIDEO_H264_VUI_SAR_IDC (V4L2_CID_MPEG_BASE+367) +enum v4l2_mpeg_video_h264_vui_sar_idc { + V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_UNSPECIFIED = 0, + V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_1x1 = 1, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_12x11 = 2, + V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_10x11 = 3, + V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_16x11 = 4, + V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_40x33 = 5, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_24x11 = 6, + V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_20x11 = 7, + V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_32x11 = 8, + V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_80x33 = 9, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_18x11 = 10, + V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_15x11 = 11, + V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_64x33 = 12, + V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_160x99 = 13, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_4x3 = 14, + V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_3x2 = 15, + V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_2x1 = 16, + V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_EXTENDED = 17, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +#define V4L2_CID_MPEG_VIDEO_H264_SEI_FRAME_PACKING (V4L2_CID_MPEG_BASE+368) +#define V4L2_CID_MPEG_VIDEO_H264_SEI_FP_CURRENT_FRAME_0 (V4L2_CID_MPEG_BASE+369) +#define V4L2_CID_MPEG_VIDEO_H264_SEI_FP_ARRANGEMENT_TYPE (V4L2_CID_MPEG_BASE+370) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +enum v4l2_mpeg_video_h264_sei_fp_arrangement_type { + V4L2_MPEG_VIDEO_H264_SEI_FP_ARRANGEMENT_TYPE_CHECKERBOARD = 0, + V4L2_MPEG_VIDEO_H264_SEI_FP_ARRANGEMENT_TYPE_COLUMN = 1, + V4L2_MPEG_VIDEO_H264_SEI_FP_ARRANGEMENT_TYPE_ROW = 2, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_VIDEO_H264_SEI_FP_ARRANGEMENT_TYPE_SIDE_BY_SIDE = 3, + V4L2_MPEG_VIDEO_H264_SEI_FP_ARRANGEMENT_TYPE_TOP_BOTTOM = 4, + V4L2_MPEG_VIDEO_H264_SEI_FP_ARRANGEMENT_TYPE_TEMPORAL = 5, +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_MPEG_VIDEO_H264_FMO (V4L2_CID_MPEG_BASE+371) +#define V4L2_CID_MPEG_VIDEO_H264_FMO_MAP_TYPE (V4L2_CID_MPEG_BASE+372) +enum v4l2_mpeg_video_h264_fmo_map_type { + V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_INTERLEAVED_SLICES = 0, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_SCATTERED_SLICES = 1, + V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_FOREGROUND_WITH_LEFT_OVER = 2, + V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_BOX_OUT = 3, + V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_RASTER_SCAN = 4, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_WIPE_SCAN = 5, + V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_EXPLICIT = 6, +}; +#define V4L2_CID_MPEG_VIDEO_H264_FMO_SLICE_GROUP (V4L2_CID_MPEG_BASE+373) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_MPEG_VIDEO_H264_FMO_CHANGE_DIRECTION (V4L2_CID_MPEG_BASE+374) +enum v4l2_mpeg_video_h264_fmo_change_dir { + V4L2_MPEG_VIDEO_H264_FMO_CHANGE_DIR_RIGHT = 0, + V4L2_MPEG_VIDEO_H264_FMO_CHANGE_DIR_LEFT = 1, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +#define V4L2_CID_MPEG_VIDEO_H264_FMO_CHANGE_RATE (V4L2_CID_MPEG_BASE+375) +#define V4L2_CID_MPEG_VIDEO_H264_FMO_RUN_LENGTH (V4L2_CID_MPEG_BASE+376) +#define V4L2_CID_MPEG_VIDEO_H264_ASO (V4L2_CID_MPEG_BASE+377) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_MPEG_VIDEO_H264_ASO_SLICE_ORDER (V4L2_CID_MPEG_BASE+378) +#define V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING (V4L2_CID_MPEG_BASE+379) +#define V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING_TYPE (V4L2_CID_MPEG_BASE+380) +enum v4l2_mpeg_video_h264_hierarchical_coding_type { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_VIDEO_H264_HIERARCHICAL_CODING_B = 0, + V4L2_MPEG_VIDEO_H264_HIERARCHICAL_CODING_P = 1, +}; +#define V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING_LAYER (V4L2_CID_MPEG_BASE+381) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING_LAYER_QP (V4L2_CID_MPEG_BASE+382) +#define V4L2_CID_MPEG_VIDEO_MPEG4_I_FRAME_QP (V4L2_CID_MPEG_BASE+400) +#define V4L2_CID_MPEG_VIDEO_MPEG4_P_FRAME_QP (V4L2_CID_MPEG_BASE+401) +#define V4L2_CID_MPEG_VIDEO_MPEG4_B_FRAME_QP (V4L2_CID_MPEG_BASE+402) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_MPEG_VIDEO_MPEG4_MIN_QP (V4L2_CID_MPEG_BASE+403) +#define V4L2_CID_MPEG_VIDEO_MPEG4_MAX_QP (V4L2_CID_MPEG_BASE+404) +#define V4L2_CID_MPEG_VIDEO_MPEG4_LEVEL (V4L2_CID_MPEG_BASE+405) +enum v4l2_mpeg_video_mpeg4_level { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_VIDEO_MPEG4_LEVEL_0 = 0, + V4L2_MPEG_VIDEO_MPEG4_LEVEL_0B = 1, + V4L2_MPEG_VIDEO_MPEG4_LEVEL_1 = 2, + V4L2_MPEG_VIDEO_MPEG4_LEVEL_2 = 3, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_VIDEO_MPEG4_LEVEL_3 = 4, + V4L2_MPEG_VIDEO_MPEG4_LEVEL_3B = 5, + V4L2_MPEG_VIDEO_MPEG4_LEVEL_4 = 6, + V4L2_MPEG_VIDEO_MPEG4_LEVEL_5 = 7, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +#define V4L2_CID_MPEG_VIDEO_MPEG4_PROFILE (V4L2_CID_MPEG_BASE+406) +enum v4l2_mpeg_video_mpeg4_profile { + V4L2_MPEG_VIDEO_MPEG4_PROFILE_SIMPLE = 0, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_VIDEO_MPEG4_PROFILE_ADVANCED_SIMPLE = 1, + V4L2_MPEG_VIDEO_MPEG4_PROFILE_CORE = 2, + V4L2_MPEG_VIDEO_MPEG4_PROFILE_SIMPLE_SCALABLE = 3, + V4L2_MPEG_VIDEO_MPEG4_PROFILE_ADVANCED_CODING_EFFICIENCY = 4, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +#define V4L2_CID_MPEG_VIDEO_MPEG4_QPEL (V4L2_CID_MPEG_BASE+407) +#define V4L2_CID_QCOM_VIDEO_SYNC_FRAME_SEQ_HDR (V4L2_CID_MPEG_BASE+408) +#define V4L2_CID_MPEG_CX2341X_BASE (V4L2_CTRL_CLASS_MPEG | 0x1000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER_MODE (V4L2_CID_MPEG_CX2341X_BASE+0) +enum v4l2_mpeg_cx2341x_video_spatial_filter_mode { + V4L2_MPEG_CX2341X_VIDEO_SPATIAL_FILTER_MODE_MANUAL = 0, + V4L2_MPEG_CX2341X_VIDEO_SPATIAL_FILTER_MODE_AUTO = 1, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +#define V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER (V4L2_CID_MPEG_CX2341X_BASE+1) +#define V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE (V4L2_CID_MPEG_CX2341X_BASE+2) +enum v4l2_mpeg_cx2341x_video_luma_spatial_filter_type { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE_OFF = 0, + V4L2_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE_1D_HOR = 1, + V4L2_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE_1D_VERT = 2, + V4L2_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE_2D_HV_SEPARABLE = 3, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE_2D_SYM_NON_SEPARABLE = 4, +}; +#define V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_SPATIAL_FILTER_TYPE (V4L2_CID_MPEG_CX2341X_BASE+3) +enum v4l2_mpeg_cx2341x_video_chroma_spatial_filter_type { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_CX2341X_VIDEO_CHROMA_SPATIAL_FILTER_TYPE_OFF = 0, + V4L2_MPEG_CX2341X_VIDEO_CHROMA_SPATIAL_FILTER_TYPE_1D_HOR = 1, +}; +#define V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER_MODE (V4L2_CID_MPEG_CX2341X_BASE+4) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +enum v4l2_mpeg_cx2341x_video_temporal_filter_mode { + V4L2_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER_MODE_MANUAL = 0, + V4L2_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER_MODE_AUTO = 1, +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER (V4L2_CID_MPEG_CX2341X_BASE+5) +#define V4L2_CID_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE (V4L2_CID_MPEG_CX2341X_BASE+6) +enum v4l2_mpeg_cx2341x_video_median_filter_type { + V4L2_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE_OFF = 0, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE_HOR = 1, + V4L2_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE_VERT = 2, + V4L2_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE_HOR_VERT = 3, + V4L2_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE_DIAG = 4, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +#define V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_BOTTOM (V4L2_CID_MPEG_CX2341X_BASE+7) +#define V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_TOP (V4L2_CID_MPEG_CX2341X_BASE+8) +#define V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_BOTTOM (V4L2_CID_MPEG_CX2341X_BASE+9) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_TOP (V4L2_CID_MPEG_CX2341X_BASE+10) +#define V4L2_CID_MPEG_CX2341X_STREAM_INSERT_NAV_PACKETS (V4L2_CID_MPEG_CX2341X_BASE+11) +#define V4L2_CID_MPEG_MFC51_BASE (V4L2_CTRL_CLASS_MPEG | 0x1100) +#define V4L2_CID_MPEG_MFC51_VIDEO_DECODER_H264_DISPLAY_DELAY (V4L2_CID_MPEG_MFC51_BASE+0) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_MPEG_MFC51_VIDEO_DECODER_H264_DISPLAY_DELAY_ENABLE (V4L2_CID_MPEG_MFC51_BASE+1) +#define V4L2_CID_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE (V4L2_CID_MPEG_MFC51_BASE+2) +enum v4l2_mpeg_mfc51_video_frame_skip_mode { + V4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_DISABLED = 0, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_LEVEL_LIMIT = 1, + V4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT = 2, +}; +#define V4L2_CID_MPEG_MFC51_VIDEO_FORCE_FRAME_TYPE (V4L2_CID_MPEG_MFC51_BASE+3) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +enum v4l2_mpeg_mfc51_video_force_frame_type { + V4L2_MPEG_MFC51_VIDEO_FORCE_FRAME_TYPE_DISABLED = 0, + V4L2_MPEG_MFC51_VIDEO_FORCE_FRAME_TYPE_I_FRAME = 1, + V4L2_MPEG_MFC51_VIDEO_FORCE_FRAME_TYPE_NOT_CODED = 2, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +#define V4L2_CID_MPEG_MFC51_VIDEO_PADDING (V4L2_CID_MPEG_MFC51_BASE+4) +#define V4L2_CID_MPEG_MFC51_VIDEO_PADDING_YUV (V4L2_CID_MPEG_MFC51_BASE+5) +#define V4L2_CID_MPEG_MFC51_VIDEO_RC_FIXED_TARGET_BIT (V4L2_CID_MPEG_MFC51_BASE+6) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_MPEG_MFC51_VIDEO_RC_REACTION_COEFF (V4L2_CID_MPEG_MFC51_BASE+7) +#define V4L2_CID_MPEG_MFC51_VIDEO_H264_ADAPTIVE_RC_ACTIVITY (V4L2_CID_MPEG_MFC51_BASE+50) +#define V4L2_CID_MPEG_MFC51_VIDEO_H264_ADAPTIVE_RC_DARK (V4L2_CID_MPEG_MFC51_BASE+51) +#define V4L2_CID_MPEG_MFC51_VIDEO_H264_ADAPTIVE_RC_SMOOTH (V4L2_CID_MPEG_MFC51_BASE+52) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_MPEG_MFC51_VIDEO_H264_ADAPTIVE_RC_STATIC (V4L2_CID_MPEG_MFC51_BASE+53) +#define V4L2_CID_MPEG_MFC51_VIDEO_H264_NUM_REF_PIC_FOR_P (V4L2_CID_MPEG_MFC51_BASE+54) +#define V4L2_CID_MPEG_MSM_VIDC_BASE (V4L2_CTRL_CLASS_MPEG | 0x2000) +#define V4L2_CID_MPEG_VIDC_VIDEO_ENABLE_PICTURE_TYPE (V4L2_CID_MPEG_MSM_VIDC_BASE+0) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_MPEG_VIDC_VIDEO_KEEP_ASPECT_RATIO (V4L2_CID_MPEG_MSM_VIDC_BASE+1) +#define V4L2_CID_MPEG_VIDC_VIDEO_POST_LOOP_DEBLOCKER_MODE (V4L2_CID_MPEG_MSM_VIDC_BASE+2) +#define V4L2_CID_MPEG_VIDC_VIDEO_DIVX_FORMAT (V4L2_CID_MPEG_MSM_VIDC_BASE+3) +enum v4l2_mpeg_vidc_video_divx_format_type { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_VIDC_VIDEO_DIVX_FORMAT_4 = 0, + V4L2_MPEG_VIDC_VIDEO_DIVX_FORMAT_5 = 1, + V4L2_MPEG_VIDC_VIDEO_DIVX_FORMAT_6 = 2, +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_MPEG_VIDC_VIDEO_MB_ERROR_MAP_REPORTING (V4L2_CID_MPEG_MSM_VIDC_BASE+4) +#define V4L2_CID_MPEG_VIDC_VIDEO_CONTINUE_DATA_TRANSFER (V4L2_CID_MPEG_MSM_VIDC_BASE+5) +#define V4L2_CID_MPEG_VIDC_VIDEO_STREAM_FORMAT (V4L2_CID_MPEG_MSM_VIDC_BASE+6) +enum v4l2_mpeg_vidc_video_stream_format { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_VIDC_VIDEO_NAL_FORMAT_STARTCODES = 0, + V4L2_MPEG_VIDC_VIDEO_NAL_FORMAT_ONE_NAL_PER_BUFFER = 1, + V4L2_MPEG_VIDC_VIDEO_NAL_FORMAT_ONE_BYTE_LENGTH = 2, + V4L2_MPEG_VIDC_VIDEO_NAL_FORMAT_TWO_BYTE_LENGTH = 3, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_VIDC_VIDEO_NAL_FORMAT_FOUR_BYTE_LENGTH = 4, +}; +#define V4L2_CID_MPEG_VIDC_VIDEO_OUTPUT_ORDER (V4L2_CID_MPEG_MSM_VIDC_BASE+7) +enum v4l2_mpeg_vidc_video_output_order { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_VIDC_VIDEO_OUTPUT_ORDER_DISPLAY = 0, + V4L2_MPEG_VIDC_VIDEO_OUTPUT_ORDER_DECODE = 1, +}; +#define V4L2_CID_MPEG_VIDC_VIDEO_FRAME_RATE (V4L2_CID_MPEG_MSM_VIDC_BASE+8) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_MPEG_VIDC_VIDEO_IDR_PERIOD (V4L2_CID_MPEG_MSM_VIDC_BASE+9) +#define V4L2_CID_MPEG_VIDC_VIDEO_NUM_P_FRAMES (V4L2_CID_MPEG_MSM_VIDC_BASE+10) +#define V4L2_CID_MPEG_VIDC_VIDEO_NUM_B_FRAMES (V4L2_CID_MPEG_MSM_VIDC_BASE+11) +#define V4L2_CID_MPEG_VIDC_VIDEO_REQUEST_IFRAME (V4L2_CID_MPEG_MSM_VIDC_BASE+12) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_MPEG_VIDC_VIDEO_RATE_CONTROL (V4L2_CID_MPEG_MSM_VIDC_BASE+13) +enum v4l2_mpeg_vidc_video_rate_control { + V4L2_CID_MPEG_VIDC_VIDEO_RATE_CONTROL_OFF = 0, + V4L2_CID_MPEG_VIDC_VIDEO_RATE_CONTROL_VBR_VFR = 1, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_CID_MPEG_VIDC_VIDEO_RATE_CONTROL_VBR_CFR = 2, + V4L2_CID_MPEG_VIDC_VIDEO_RATE_CONTROL_CBR_VFR = 3, + V4L2_CID_MPEG_VIDC_VIDEO_RATE_CONTROL_CBR_CFR = 4, +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_MPEG_VIDC_VIDEO_ROTATION (V4L2_CID_MPEG_MSM_VIDC_BASE+14) +enum v4l2_mpeg_vidc_video_rotation { + V4L2_CID_MPEG_VIDC_VIDEO_ROTATION_NONE = 0, + V4L2_CID_MPEG_VIDC_VIDEO_ROTATION_90 = 1, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_CID_MPEG_VIDC_VIDEO_ROTATION_180 = 2, + V4L2_CID_MPEG_VIDC_VIDEO_ROTATION_270 = 3, +}; +#define MSM_VIDC_BASE V4L2_CID_MPEG_MSM_VIDC_BASE +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_MPEG_VIDC_VIDEO_H264_CABAC_MODEL (MSM_VIDC_BASE+15) +enum v4l2_mpeg_vidc_h264_cabac_model { + V4L2_CID_MPEG_VIDC_VIDEO_H264_CABAC_MODEL_0 = 0, + V4L2_CID_MPEG_VIDC_VIDEO_H264_CABAC_MODEL_1 = 1, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_CID_MPEG_VIDC_VIDEO_H264_CABAC_MODEL_2 = 2, +}; +#define V4L2_CID_MPEG_VIDC_VIDEO_INTRA_REFRESH_MODE (MSM_VIDC_BASE+16) +enum v4l2_mpeg_vidc_video_intra_refresh_mode { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_CID_MPEG_VIDC_VIDEO_INTRA_REFRESH_NONE = 0, + V4L2_CID_MPEG_VIDC_VIDEO_INTRA_REFRESH_CYCLIC = 1, + V4L2_CID_MPEG_VIDC_VIDEO_INTRA_REFRESH_ADAPTIVE = 2, + V4L2_CID_MPEG_VIDC_VIDEO_INTRA_REFRESH_CYCLIC_ADAPTIVE = 3, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_CID_MPEG_VIDC_VIDEO_INTRA_REFRESH_RANDOM = 4, +}; +#define V4L2_CID_MPEG_VIDC_VIDEO_AIR_MBS (V4L2_CID_MPEG_MSM_VIDC_BASE+17) +#define V4L2_CID_MPEG_VIDC_VIDEO_AIR_REF (V4L2_CID_MPEG_MSM_VIDC_BASE+18) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_MPEG_VIDC_VIDEO_CIR_MBS (V4L2_CID_MPEG_MSM_VIDC_BASE+19) +#define V4L2_CID_MPEG_VIDC_VIDEO_H263_PROFILE (V4L2_CID_MPEG_MSM_VIDC_BASE+20) +enum v4l2_mpeg_vidc_video_h263_profile { + V4L2_MPEG_VIDC_VIDEO_H263_PROFILE_BASELINE = 0, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_VIDC_VIDEO_H263_PROFILE_H320CODING = 1, + V4L2_MPEG_VIDC_VIDEO_H263_PROFILE_BACKWARDCOMPATIBLE = 2, + V4L2_MPEG_VIDC_VIDEO_H263_PROFILE_ISWV2 = 3, + V4L2_MPEG_VIDC_VIDEO_H263_PROFILE_ISWV3 = 4, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_VIDC_VIDEO_H263_PROFILE_HIGHCOMPRESSION = 5, + V4L2_MPEG_VIDC_VIDEO_H263_PROFILE_INTERNET = 6, + V4L2_MPEG_VIDC_VIDEO_H263_PROFILE_INTERLACE = 7, + V4L2_MPEG_VIDC_VIDEO_H263_PROFILE_HIGHLATENCY = 8, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +#define V4L2_CID_MPEG_VIDC_VIDEO_H263_LEVEL (V4L2_CID_MPEG_MSM_VIDC_BASE+21) +enum v4l2_mpeg_vidc_video_h263_level { + V4L2_MPEG_VIDC_VIDEO_H263_LEVEL_1_0 = 0, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_VIDC_VIDEO_H263_LEVEL_2_0 = 1, + V4L2_MPEG_VIDC_VIDEO_H263_LEVEL_3_0 = 2, + V4L2_MPEG_VIDC_VIDEO_H263_LEVEL_4_0 = 3, + V4L2_MPEG_VIDC_VIDEO_H263_LEVEL_4_5 = 4, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_VIDC_VIDEO_H263_LEVEL_5_0 = 5, + V4L2_MPEG_VIDC_VIDEO_H263_LEVEL_6_0 = 6, + V4L2_MPEG_VIDC_VIDEO_H263_LEVEL_7_0 = 7, +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_MPEG_VIDC_VIDEO_H264_AU_DELIMITER (V4L2_CID_MPEG_MSM_VIDC_BASE + 22) +enum v4l2_mpeg_vidc_video_h264_au_delimiter { + V4L2_MPEG_VIDC_VIDEO_H264_AU_DELIMITER_DISABLED = 0, + V4L2_MPEG_VIDC_VIDEO_H264_AU_DELIMITER_ENABLED = 1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +#define V4L2_CID_MPEG_VIDC_VIDEO_SYNC_FRAME_DECODE (V4L2_CID_MPEG_MSM_VIDC_BASE + 23) +enum v4l2_mpeg_vidc_video_sync_frame_decode { + V4L2_MPEG_VIDC_VIDEO_SYNC_FRAME_DECODE_DISABLE = 0, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_VIDC_VIDEO_SYNC_FRAME_DECODE_ENABLE = 1 +}; +#define V4L2_CID_MPEG_VIDC_VIDEO_SECURE (V4L2_CID_MPEG_MSM_VIDC_BASE+24) +#define V4L2_CID_MPEG_VIDC_VIDEO_EXTRADATA (V4L2_CID_MPEG_MSM_VIDC_BASE + 25) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +enum v4l2_mpeg_vidc_extradata { + V4L2_MPEG_VIDC_EXTRADATA_NONE = 0, + V4L2_MPEG_VIDC_EXTRADATA_MB_QUANTIZATION = 1, + V4L2_MPEG_VIDC_EXTRADATA_INTERLACE_VIDEO = 2, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_VIDC_EXTRADATA_VC1_FRAMEDISP = 3, + V4L2_MPEG_VIDC_EXTRADATA_VC1_SEQDISP = 4, + V4L2_MPEG_VIDC_EXTRADATA_TIMESTAMP = 5, + V4L2_MPEG_VIDC_EXTRADATA_S3D_FRAME_PACKING = 6, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_VIDC_EXTRADATA_FRAME_RATE = 7, + V4L2_MPEG_VIDC_EXTRADATA_PANSCAN_WINDOW = 8, + V4L2_MPEG_VIDC_EXTRADATA_RECOVERY_POINT_SEI = 9, + V4L2_MPEG_VIDC_EXTRADATA_MULTISLICE_INFO = 10, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_VIDC_EXTRADATA_NUM_CONCEALED_MB = 11, + V4L2_MPEG_VIDC_EXTRADATA_METADATA_FILLER = 12, + V4L2_MPEG_VIDC_EXTRADATA_INPUT_CROP = 13, + V4L2_MPEG_VIDC_EXTRADATA_DIGITAL_ZOOM = 14, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_VIDC_EXTRADATA_ASPECT_RATIO = 15, + V4L2_MPEG_VIDC_EXTRADATA_MPEG2_SEQDISP = 16, + V4L2_MPEG_VIDC_EXTRADATA_STREAM_USERDATA = 17, + V4L2_MPEG_VIDC_EXTRADATA_FRAME_QP = 18, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_VIDC_EXTRADATA_FRAME_BITS_INFO = 19, + V4L2_MPEG_VIDC_EXTRADATA_LTR = 20, + V4L2_MPEG_VIDC_EXTRADATA_METADATA_MBI = 21, +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_MPEG_VIDC_SET_PERF_LEVEL (V4L2_CID_MPEG_MSM_VIDC_BASE + 26) +enum v4l2_mpeg_vidc_perf_level { + V4L2_CID_MPEG_VIDC_PERF_LEVEL_NOMINAL = 0, + V4L2_CID_MPEG_VIDC_PERF_LEVEL_PERFORMANCE = 1, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_CID_MPEG_VIDC_PERF_LEVEL_TURBO = 2, +}; +#define V4L2_CID_MPEG_VIDEO_MULTI_SLICE_GOB (V4L2_CID_MPEG_MSM_VIDC_BASE + 27) +#define V4L2_CID_MPEG_VIDEO_MULTI_SLICE_DELIVERY_MODE (V4L2_CID_MPEG_MSM_VIDC_BASE + 28) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_MPEG_VIDC_VIDEO_H264_VUI_TIMING_INFO (V4L2_CID_MPEG_MSM_VIDC_BASE + 29) +enum v4l2_mpeg_vidc_video_h264_vui_timing_info { + V4L2_MPEG_VIDC_VIDEO_H264_VUI_TIMING_INFO_DISABLED = 0, + V4L2_MPEG_VIDC_VIDEO_H264_VUI_TIMING_INFO_ENABLED = 1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +#define V4L2_CID_MPEG_VIDC_VIDEO_ALLOC_MODE_INPUT (V4L2_CID_MPEG_MSM_VIDC_BASE + 30) +#define V4L2_CID_MPEG_VIDC_VIDEO_ALLOC_MODE_OUTPUT (V4L2_CID_MPEG_MSM_VIDC_BASE + 31) +enum v4l2_mpeg_vidc_video_alloc_mode_type { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_VIDC_VIDEO_STATIC = 0, + V4L2_MPEG_VIDC_VIDEO_RING = 1, + V4L2_MPEG_VIDC_VIDEO_DYNAMIC = 2, +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_MPEG_VIDC_VIDEO_FRAME_ASSEMBLY (V4L2_CID_MPEG_MSM_VIDC_BASE + 32) +enum v4l2_mpeg_vidc_video_assembly { + V4L2_MPEG_VIDC_FRAME_ASSEMBLY_DISABLE = 0, + V4L2_MPEG_VIDC_FRAME_ASSEMBLY_ENABLE = 1, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +#define V4L2_CID_MPEG_VIDC_VIDEO_VP8_PROFILE_LEVEL (V4L2_CID_MPEG_MSM_VIDC_BASE + 33) +enum v4l2_mpeg_vidc_video_vp8_profile_level { + V4L2_MPEG_VIDC_VIDEO_VP8_UNUSED, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_VIDC_VIDEO_VP8_VERSION_0, + V4L2_MPEG_VIDC_VIDEO_VP8_VERSION_1, + V4L2_MPEG_VIDC_VIDEO_VP8_VERSION_2, + V4L2_MPEG_VIDC_VIDEO_VP8_VERSION_3, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +#define V4L2_CID_MPEG_VIDC_VIDEO_H264_VUI_BITSTREAM_RESTRICT (V4L2_CID_MPEG_MSM_VIDC_BASE + 34) +enum v4l2_mpeg_vidc_video_h264_vui_bitstream_restrict { + V4L2_MPEG_VIDC_VIDEO_H264_VUI_BITSTREAM_RESTRICT_DISABLED = 0, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_VIDC_VIDEO_H264_VUI_BITSTREAM_RESTRICT_ENABLED = 1 +}; +#define V4L2_CID_MPEG_VIDC_VIDEO_PRESERVE_TEXT_QUALITY (V4L2_CID_MPEG_MSM_VIDC_BASE + 35) +enum v4l2_mpeg_vidc_video_preserve_text_quality { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_VIDC_VIDEO_PRESERVE_TEXT_QUALITY_DISABLED = 0, + V4L2_MPEG_VIDC_VIDEO_PRESERVE_TEXT_QUALITY_ENABLED = 1 +}; +#define V4L2_CID_MPEG_VIDC_VIDEO_DEINTERLACE (V4L2_CID_MPEG_MSM_VIDC_BASE + 36) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +enum v4l2_mpeg_vidc_video_deinterlace { + V4L2_CID_MPEG_VIDC_VIDEO_DEINTERLACE_DISABLED = 0, + V4L2_CID_MPEG_VIDC_VIDEO_DEINTERLACE_ENABLED = 1 +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_MPEG_VIDC_VIDEO_MPEG4_TIME_RESOLUTION (V4L2_CID_MPEG_MSM_VIDC_BASE + 37) +#define V4L2_CID_MPEG_VIDC_VIDEO_STREAM_OUTPUT_MODE (V4L2_CID_MPEG_MSM_VIDC_BASE + 38) +enum v4l2_mpeg_vidc_video_decoder_multi_stream { + V4L2_CID_MPEG_VIDC_VIDEO_STREAM_OUTPUT_PRIMARY = 0, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_CID_MPEG_VIDC_VIDEO_STREAM_OUTPUT_SECONDARY = 1, +}; +#define V4L2_CID_MPEG_VIDC_VIDEO_SCS_THRESHOLD (V4L2_CID_MPEG_MSM_VIDC_BASE + 39) +#define V4L2_CID_MPEG_VIDC_VIDEO_MPEG2_LEVEL (V4L2_CID_MPEG_MSM_VIDC_BASE+40) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +enum v4l2_mpeg_vidc_video_mpeg2_level { + V4L2_MPEG_VIDC_VIDEO_MPEG2_LEVEL_0 = 0, + V4L2_MPEG_VIDC_VIDEO_MPEG2_LEVEL_1 = 1, + V4L2_MPEG_VIDC_VIDEO_MPEG2_LEVEL_2 = 2, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_VIDC_VIDEO_MPEG2_LEVEL_3 = 3, +}; +#define V4L2_CID_MPEG_VIDC_VIDEO_MPEG2_PROFILE (V4L2_CID_MPEG_MSM_VIDC_BASE+41) +enum v4l2_mpeg_vidc_video_mpeg2_profile { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_VIDC_VIDEO_MPEG2_PROFILE_SIMPLE = 0, + V4L2_MPEG_VIDC_VIDEO_MPEG2_PROFILE_MAIN = 1, + V4L2_MPEG_VIDC_VIDEO_MPEG2_PROFILE_422 = 2, + V4L2_MPEG_VIDC_VIDEO_MPEG2_PROFILE_SNR_SCALABLE = 3, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_VIDC_VIDEO_MPEG2_PROFILE_SPATIAL_SCALABLE = 4, + V4L2_MPEG_VIDC_VIDEO_MPEG2_PROFILE_HIGH = 5, +}; +#define V4L2_CID_MPEG_VIDC_VIDEO_REQUEST_SEQ_HEADER (V4L2_CID_MPEG_MSM_VIDC_BASE + 42) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_MPEG_VIDC_VIDEO_MVC_BUFFER_LAYOUT (V4L2_CID_MPEG_MSM_VIDC_BASE + 43) +enum v4l2_mpeg_vidc_video_mvc_layout { + V4L2_MPEG_VIDC_VIDEO_MVC_SEQUENTIAL = 0, + V4L2_MPEG_VIDC_VIDEO_MVC_TOP_BOTTOM = 1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +#define V4L2_CID_MPEG_VIDC_VIDEO_VP8_MIN_QP (V4L2_CID_MPEG_MSM_VIDC_BASE + 44) +#define V4L2_CID_MPEG_VIDC_VIDEO_VP8_MAX_QP (V4L2_CID_MPEG_MSM_VIDC_BASE + 45) +#define V4L2_CID_MPEG_VIDC_VIDEO_CONCEAL_COLOR (V4L2_CID_MPEG_MSM_VIDC_BASE + 46) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_MPEG_VIDC_VIDEO_LTRMODE (V4L2_CID_MPEG_MSM_VIDC_BASE + 47) +enum v4l2_mpeg_vidc_video_ltrmode { + V4L2_MPEG_VIDC_VIDEO_LTR_MODE_DISABLE = 0, + V4L2_MPEG_VIDC_VIDEO_LTR_MODE_MANUAL = 1, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_VIDC_VIDEO_LTR_MODE_PERIODIC = 2 +}; +#define V4L2_CID_MPEG_VIDC_VIDEO_LTRCOUNT (V4L2_CID_MPEG_MSM_VIDC_BASE + 48) +#define V4L2_CID_MPEG_VIDC_VIDEO_USELTRFRAME (V4L2_CID_MPEG_MSM_VIDC_BASE + 49) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_MPEG_VIDC_VIDEO_MARKLTRFRAME (V4L2_CID_MPEG_MSM_VIDC_BASE + 50) +#define V4L2_CID_MPEG_VIDC_VIDEO_HIER_P_NUM_LAYERS (V4L2_CID_MPEG_MSM_VIDC_BASE + 51) +#define V4L2_CID_MPEG_VIDC_VIDEO_RATE_CONTROL_TIMESTAMP_MODE (V4L2_CID_MPEG_MSM_VIDC_BASE + 52) +enum v4l2_mpeg_vidc_video_rate_control_timestamp_mode { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_VIDC_VIDEO_RATE_CONTROL_TIMESTAMP_MODE_HONOR = 0, + V4L2_MPEG_VIDC_VIDEO_RATE_CONTROL_TIMESTAMP_MODE_IGNORE = 1, +}; +#define V4L2_CID_MPEG_VIDC_VIDEO_ENABLE_INITIAL_QP (V4L2_CID_MPEG_MSM_VIDC_BASE + 53) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +enum vl42_mpeg_vidc_video_enable_initial_qp { + V4L2_CID_MPEG_VIDC_VIDEO_ENABLE_INITIAL_QP_IFRAME = 0x1, + V4L2_CID_MPEG_VIDC_VIDEO_ENABLE_INITIAL_QP_PFRAME = 0x2, + V4L2_CID_MPEG_VIDC_VIDEO_ENABLE_INITIAL_QP_BFRAME = 0x4, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +#define V4L2_CID_MPEG_VIDC_VIDEO_I_FRAME_QP (V4L2_CID_MPEG_MSM_VIDC_BASE + 54) +#define V4L2_CID_MPEG_VIDC_VIDEO_P_FRAME_QP (V4L2_CID_MPEG_MSM_VIDC_BASE + 55) +#define V4L2_CID_MPEG_VIDC_VIDEO_B_FRAME_QP (V4L2_CID_MPEG_MSM_VIDC_BASE + 56) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_MPEG_VIDC_VIDEO_IFRAME_X_RANGE (V4L2_CID_MPEG_MSM_VIDC_BASE + 57) +#define V4L2_CID_MPEG_VIDC_VIDEO_PFRAME_X_RANGE (V4L2_CID_MPEG_MSM_VIDC_BASE + 58) +#define V4L2_CID_MPEG_VIDC_VIDEO_BFRAME_X_RANGE (V4L2_CID_MPEG_MSM_VIDC_BASE + 59) +#define V4L2_CID_MPEG_VIDC_VIDEO_IFRAME_Y_RANGE (V4L2_CID_MPEG_MSM_VIDC_BASE + 60) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_MPEG_VIDC_VIDEO_PFRAME_Y_RANGE (V4L2_CID_MPEG_MSM_VIDC_BASE + 61) +#define V4L2_CID_MPEG_VIDC_VIDEO_BFRAME_Y_RANGE (V4L2_CID_MPEG_MSM_VIDC_BASE + 62) +#define V4L2_CID_MPEG_VIDC_VIDEO_VPX_ERROR_RESILIENCE (V4L2_CID_MPEG_MSM_VIDC_BASE + 63) +#define V4L2_CID_MPEG_VIDC_VIDEO_BUFFER_SIZE_LIMIT (V4L2_CID_MPEG_MSM_VIDC_BASE + 64) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +enum vl42_mpeg_vidc_video_vpx_error_resilience { + V4L2_MPEG_VIDC_VIDEO_VPX_ERROR_RESILIENCE_DISABLED = 0, + V4L2_MPEG_VIDC_VIDEO_VPX_ERROR_RESILIENCE_ENABLED = 1, +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_MPEG_VIDC_VIDEO_HEVC_PROFILE (V4L2_CID_MPEG_MSM_VIDC_BASE + 65) +enum v4l2_mpeg_video_hevc_profile { + V4L2_MPEG_VIDC_VIDEO_HEVC_PROFILE_MAIN = 0, + V4L2_MPEG_VIDC_VIDEO_HEVC_PROFILE_MAIN10 = 1, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_VIDC_VIDEO_HEVC_PROFILE_MAIN_STILL_PIC = 2, +}; +#define V4L2_CID_MPEG_VIDC_VIDEO_HEVC_TIER_LEVEL (V4L2_CID_MPEG_MSM_VIDC_BASE + 66) +enum v4l2_mpeg_video_hevc_level { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_VIDC_VIDEO_HEVC_LEVEL_MAIN_TIER_LEVEL_1 = 0, + V4L2_MPEG_VIDC_VIDEO_HEVC_LEVEL_HIGH_TIER_LEVEL_1 = 1, + V4L2_MPEG_VIDC_VIDEO_HEVC_LEVEL_MAIN_TIER_LEVEL_2 = 2, + V4L2_MPEG_VIDC_VIDEO_HEVC_LEVEL_HIGH_TIER_LEVEL_2 = 3, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_VIDC_VIDEO_HEVC_LEVEL_MAIN_TIER_LEVEL_2_1 = 4, + V4L2_MPEG_VIDC_VIDEO_HEVC_LEVEL_HIGH_TIER_LEVEL_2_1 = 5, + V4L2_MPEG_VIDC_VIDEO_HEVC_LEVEL_MAIN_TIER_LEVEL_3 = 6, + V4L2_MPEG_VIDC_VIDEO_HEVC_LEVEL_HIGH_TIER_LEVEL_3 = 7, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_VIDC_VIDEO_HEVC_LEVEL_MAIN_TIER_LEVEL_3_1 = 8, + V4L2_MPEG_VIDC_VIDEO_HEVC_LEVEL_HIGH_TIER_LEVEL_3_1 = 9, + V4L2_MPEG_VIDC_VIDEO_HEVC_LEVEL_MAIN_TIER_LEVEL_4 = 10, + V4L2_MPEG_VIDC_VIDEO_HEVC_LEVEL_HIGH_TIER_LEVEL_4 = 11, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_VIDC_VIDEO_HEVC_LEVEL_MAIN_TIER_LEVEL_4_1 = 12, + V4L2_MPEG_VIDC_VIDEO_HEVC_LEVEL_HIGH_TIER_LEVEL_4_1 = 13, + V4L2_MPEG_VIDC_VIDEO_HEVC_LEVEL_MAIN_TIER_LEVEL_5 = 14, + V4L2_MPEG_VIDC_VIDEO_HEVC_LEVEL_HIGH_TIER_LEVEL_5 = 15, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_VIDC_VIDEO_HEVC_LEVEL_MAIN_TIER_LEVEL_5_1 = 16, + V4L2_MPEG_VIDC_VIDEO_HEVC_LEVEL_HIGH_TIER_LEVEL_5_1 = 17, + V4L2_MPEG_VIDC_VIDEO_HEVC_LEVEL_MAIN_TIER_LEVEL_5_2 = 18, + V4L2_MPEG_VIDC_VIDEO_HEVC_LEVEL_HIGH_TIER_LEVEL_5_2 = 19, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_VIDC_VIDEO_HEVC_LEVEL_MAIN_TIER_LEVEL_6 = 20, + V4L2_MPEG_VIDC_VIDEO_HEVC_LEVEL_HIGH_TIER_LEVEL_6 = 21, + V4L2_MPEG_VIDC_VIDEO_HEVC_LEVEL_MAIN_TIER_LEVEL_6_1 = 22, + V4L2_MPEG_VIDC_VIDEO_HEVC_LEVEL_HIGH_TIER_LEVEL_6_1 = 23, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MPEG_VIDC_VIDEO_HEVC_LEVEL_MAIN_TIER_LEVEL_6_2 = 24, + V4L2_MPEG_VIDC_VIDEO_HEVC_LEVEL_HIGH_TIER_LEVEL_6_2 = 25, +}; +#define V4L2_CID_MPEG_VIDC_VIDEO_H264_NAL_SVC (V4L2_CID_MPEG_MSM_VIDC_BASE + 67) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +enum vl42_mpeg_vidc_video_h264_svc_nal { + V4L2_CID_MPEG_VIDC_VIDEO_H264_NAL_SVC_DISABLED = 0, + V4L2_CID_MPEG_VIDC_VIDEO_H264_NAL_SVC_ENABLED = 1, +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_MPEG_VIDC_VIDEO_PERF_MODE (V4L2_CID_MPEG_MSM_VIDC_BASE + 68) +enum v4l2_mpeg_vidc_video_perf_mode { + V4L2_MPEG_VIDC_VIDEO_PERF_MAX_QUALITY = 1, + V4L2_MPEG_VIDC_VIDEO_PERF_POWER_SAVE = 2 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +#define V4L2_CID_MPEG_VIDC_VIDEO_HIER_B_NUM_LAYERS (V4L2_CID_MPEG_MSM_VIDC_BASE + 69) +#define V4L2_CID_MPEG_VIDC_VIDEO_SECURE_SCALING_THRESHOLD (V4L2_CID_MPEG_MSM_VIDC_BASE + 70) +#define V4L2_CID_MPEG_VIDC_VIDEO_NON_SECURE_OUTPUT2 (V4L2_CID_MPEG_MSM_VIDC_BASE + 71) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_MPEG_VIDC_VIDEO_HYBRID_HIERP_MODE (V4L2_CID_MPEG_MSM_VIDC_BASE + 72) +#define V4L2_CID_CAMERA_CLASS_BASE (V4L2_CTRL_CLASS_CAMERA | 0x900) +#define V4L2_CID_CAMERA_CLASS (V4L2_CTRL_CLASS_CAMERA | 1) +#define V4L2_CID_EXPOSURE_AUTO (V4L2_CID_CAMERA_CLASS_BASE+1) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +enum v4l2_exposure_auto_type { + V4L2_EXPOSURE_AUTO = 0, + V4L2_EXPOSURE_MANUAL = 1, + V4L2_EXPOSURE_SHUTTER_PRIORITY = 2, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_EXPOSURE_APERTURE_PRIORITY = 3 +}; +#define V4L2_CID_EXPOSURE_ABSOLUTE (V4L2_CID_CAMERA_CLASS_BASE+2) +#define V4L2_CID_EXPOSURE_AUTO_PRIORITY (V4L2_CID_CAMERA_CLASS_BASE+3) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_PAN_RELATIVE (V4L2_CID_CAMERA_CLASS_BASE+4) +#define V4L2_CID_TILT_RELATIVE (V4L2_CID_CAMERA_CLASS_BASE+5) +#define V4L2_CID_PAN_RESET (V4L2_CID_CAMERA_CLASS_BASE+6) +#define V4L2_CID_TILT_RESET (V4L2_CID_CAMERA_CLASS_BASE+7) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_PAN_ABSOLUTE (V4L2_CID_CAMERA_CLASS_BASE+8) +#define V4L2_CID_TILT_ABSOLUTE (V4L2_CID_CAMERA_CLASS_BASE+9) +#define V4L2_CID_FOCUS_ABSOLUTE (V4L2_CID_CAMERA_CLASS_BASE+10) +#define V4L2_CID_FOCUS_RELATIVE (V4L2_CID_CAMERA_CLASS_BASE+11) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_FOCUS_AUTO (V4L2_CID_CAMERA_CLASS_BASE+12) +#define V4L2_CID_ZOOM_ABSOLUTE (V4L2_CID_CAMERA_CLASS_BASE+13) +#define V4L2_CID_ZOOM_RELATIVE (V4L2_CID_CAMERA_CLASS_BASE+14) +#define V4L2_CID_ZOOM_CONTINUOUS (V4L2_CID_CAMERA_CLASS_BASE+15) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_PRIVACY (V4L2_CID_CAMERA_CLASS_BASE+16) +#define V4L2_CID_IRIS_ABSOLUTE (V4L2_CID_CAMERA_CLASS_BASE+17) +#define V4L2_CID_IRIS_RELATIVE (V4L2_CID_CAMERA_CLASS_BASE+18) +#define V4L2_CID_AUTO_EXPOSURE_BIAS (V4L2_CID_CAMERA_CLASS_BASE+19) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_AUTO_N_PRESET_WHITE_BALANCE (V4L2_CID_CAMERA_CLASS_BASE+20) +enum v4l2_auto_n_preset_white_balance { + V4L2_WHITE_BALANCE_MANUAL = 0, + V4L2_WHITE_BALANCE_AUTO = 1, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_WHITE_BALANCE_INCANDESCENT = 2, + V4L2_WHITE_BALANCE_FLUORESCENT = 3, + V4L2_WHITE_BALANCE_FLUORESCENT_H = 4, + V4L2_WHITE_BALANCE_HORIZON = 5, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_WHITE_BALANCE_DAYLIGHT = 6, + V4L2_WHITE_BALANCE_FLASH = 7, + V4L2_WHITE_BALANCE_CLOUDY = 8, + V4L2_WHITE_BALANCE_SHADE = 9, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +#define V4L2_CID_WIDE_DYNAMIC_RANGE (V4L2_CID_CAMERA_CLASS_BASE+21) +#define V4L2_CID_IMAGE_STABILIZATION (V4L2_CID_CAMERA_CLASS_BASE+22) +#define V4L2_CID_ISO_SENSITIVITY (V4L2_CID_CAMERA_CLASS_BASE+23) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_ISO_SENSITIVITY_AUTO (V4L2_CID_CAMERA_CLASS_BASE+24) +enum v4l2_iso_sensitivity_auto_type { + V4L2_ISO_SENSITIVITY_MANUAL = 0, + V4L2_ISO_SENSITIVITY_AUTO = 1, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +#define V4L2_CID_EXPOSURE_METERING (V4L2_CID_CAMERA_CLASS_BASE+25) +enum v4l2_exposure_metering { + V4L2_EXPOSURE_METERING_AVERAGE = 0, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_EXPOSURE_METERING_CENTER_WEIGHTED = 1, + V4L2_EXPOSURE_METERING_SPOT = 2, + V4L2_EXPOSURE_METERING_MATRIX = 3, +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_SCENE_MODE (V4L2_CID_CAMERA_CLASS_BASE+26) +enum v4l2_scene_mode { + V4L2_SCENE_MODE_NONE = 0, + V4L2_SCENE_MODE_BACKLIGHT = 1, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_SCENE_MODE_BEACH_SNOW = 2, + V4L2_SCENE_MODE_CANDLE_LIGHT = 3, + V4L2_SCENE_MODE_DAWN_DUSK = 4, + V4L2_SCENE_MODE_FALL_COLORS = 5, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_SCENE_MODE_FIREWORKS = 6, + V4L2_SCENE_MODE_LANDSCAPE = 7, + V4L2_SCENE_MODE_NIGHT = 8, + V4L2_SCENE_MODE_PARTY_INDOOR = 9, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_SCENE_MODE_PORTRAIT = 10, + V4L2_SCENE_MODE_SPORTS = 11, + V4L2_SCENE_MODE_SUNSET = 12, + V4L2_SCENE_MODE_TEXT = 13, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +#define V4L2_CID_3A_LOCK (V4L2_CID_CAMERA_CLASS_BASE+27) +#define V4L2_LOCK_EXPOSURE (1 << 0) +#define V4L2_LOCK_WHITE_BALANCE (1 << 1) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_LOCK_FOCUS (1 << 2) +#define V4L2_CID_AUTO_FOCUS_START (V4L2_CID_CAMERA_CLASS_BASE+28) +#define V4L2_CID_AUTO_FOCUS_STOP (V4L2_CID_CAMERA_CLASS_BASE+29) +#define V4L2_CID_AUTO_FOCUS_STATUS (V4L2_CID_CAMERA_CLASS_BASE+30) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_AUTO_FOCUS_STATUS_IDLE (0 << 0) +#define V4L2_AUTO_FOCUS_STATUS_BUSY (1 << 0) +#define V4L2_AUTO_FOCUS_STATUS_REACHED (1 << 1) +#define V4L2_AUTO_FOCUS_STATUS_FAILED (1 << 2) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_AUTO_FOCUS_RANGE (V4L2_CID_CAMERA_CLASS_BASE+31) +enum v4l2_auto_focus_range { + V4L2_AUTO_FOCUS_RANGE_AUTO = 0, + V4L2_AUTO_FOCUS_RANGE_NORMAL = 1, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_AUTO_FOCUS_RANGE_MACRO = 2, + V4L2_AUTO_FOCUS_RANGE_INFINITY = 3, +}; +#define V4L2_CID_FM_TX_CLASS_BASE (V4L2_CTRL_CLASS_FM_TX | 0x900) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_FM_TX_CLASS (V4L2_CTRL_CLASS_FM_TX | 1) +#define V4L2_CID_RDS_TX_DEVIATION (V4L2_CID_FM_TX_CLASS_BASE + 1) +#define V4L2_CID_RDS_TX_PI (V4L2_CID_FM_TX_CLASS_BASE + 2) +#define V4L2_CID_RDS_TX_PTY (V4L2_CID_FM_TX_CLASS_BASE + 3) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_RDS_TX_PS_NAME (V4L2_CID_FM_TX_CLASS_BASE + 5) +#define V4L2_CID_RDS_TX_RADIO_TEXT (V4L2_CID_FM_TX_CLASS_BASE + 6) +#define V4L2_CID_AUDIO_LIMITER_ENABLED (V4L2_CID_FM_TX_CLASS_BASE + 64) +#define V4L2_CID_AUDIO_LIMITER_RELEASE_TIME (V4L2_CID_FM_TX_CLASS_BASE + 65) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_AUDIO_LIMITER_DEVIATION (V4L2_CID_FM_TX_CLASS_BASE + 66) +#define V4L2_CID_AUDIO_COMPRESSION_ENABLED (V4L2_CID_FM_TX_CLASS_BASE + 80) +#define V4L2_CID_AUDIO_COMPRESSION_GAIN (V4L2_CID_FM_TX_CLASS_BASE + 81) +#define V4L2_CID_AUDIO_COMPRESSION_THRESHOLD (V4L2_CID_FM_TX_CLASS_BASE + 82) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_AUDIO_COMPRESSION_ATTACK_TIME (V4L2_CID_FM_TX_CLASS_BASE + 83) +#define V4L2_CID_AUDIO_COMPRESSION_RELEASE_TIME (V4L2_CID_FM_TX_CLASS_BASE + 84) +#define V4L2_CID_PILOT_TONE_ENABLED (V4L2_CID_FM_TX_CLASS_BASE + 96) +#define V4L2_CID_PILOT_TONE_DEVIATION (V4L2_CID_FM_TX_CLASS_BASE + 97) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_PILOT_TONE_FREQUENCY (V4L2_CID_FM_TX_CLASS_BASE + 98) +#define V4L2_CID_TUNE_PREEMPHASIS (V4L2_CID_FM_TX_CLASS_BASE + 112) +enum v4l2_preemphasis { + V4L2_PREEMPHASIS_DISABLED = 0, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_PREEMPHASIS_50_uS = 1, + V4L2_PREEMPHASIS_75_uS = 2, +}; +#define V4L2_CID_TUNE_POWER_LEVEL (V4L2_CID_FM_TX_CLASS_BASE + 113) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_TUNE_ANTENNA_CAPACITOR (V4L2_CID_FM_TX_CLASS_BASE + 114) +#define V4L2_CID_FLASH_CLASS_BASE (V4L2_CTRL_CLASS_FLASH | 0x900) +#define V4L2_CID_FLASH_CLASS (V4L2_CTRL_CLASS_FLASH | 1) +#define V4L2_CID_FLASH_LED_MODE (V4L2_CID_FLASH_CLASS_BASE + 1) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +enum v4l2_flash_led_mode { + V4L2_FLASH_LED_MODE_NONE, + V4L2_FLASH_LED_MODE_FLASH, + V4L2_FLASH_LED_MODE_TORCH, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +#define V4L2_CID_FLASH_STROBE_SOURCE (V4L2_CID_FLASH_CLASS_BASE + 2) +enum v4l2_flash_strobe_source { + V4L2_FLASH_STROBE_SOURCE_SOFTWARE, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_FLASH_STROBE_SOURCE_EXTERNAL, +}; +#define V4L2_CID_FLASH_STROBE (V4L2_CID_FLASH_CLASS_BASE + 3) +#define V4L2_CID_FLASH_STROBE_STOP (V4L2_CID_FLASH_CLASS_BASE + 4) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_FLASH_STROBE_STATUS (V4L2_CID_FLASH_CLASS_BASE + 5) +#define V4L2_CID_FLASH_TIMEOUT (V4L2_CID_FLASH_CLASS_BASE + 6) +#define V4L2_CID_FLASH_INTENSITY (V4L2_CID_FLASH_CLASS_BASE + 7) +#define V4L2_CID_FLASH_TORCH_INTENSITY (V4L2_CID_FLASH_CLASS_BASE + 8) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_FLASH_INDICATOR_INTENSITY (V4L2_CID_FLASH_CLASS_BASE + 9) +#define V4L2_CID_FLASH_FAULT (V4L2_CID_FLASH_CLASS_BASE + 10) +#define V4L2_FLASH_FAULT_OVER_VOLTAGE (1 << 0) +#define V4L2_FLASH_FAULT_TIMEOUT (1 << 1) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_FLASH_FAULT_OVER_TEMPERATURE (1 << 2) +#define V4L2_FLASH_FAULT_SHORT_CIRCUIT (1 << 3) +#define V4L2_FLASH_FAULT_OVER_CURRENT (1 << 4) +#define V4L2_FLASH_FAULT_INDICATOR (1 << 5) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_FLASH_CHARGE (V4L2_CID_FLASH_CLASS_BASE + 11) +#define V4L2_CID_FLASH_READY (V4L2_CID_FLASH_CLASS_BASE + 12) +#define V4L2_CID_JPEG_CLASS_BASE (V4L2_CTRL_CLASS_JPEG | 0x900) +#define V4L2_CID_JPEG_CLASS (V4L2_CTRL_CLASS_JPEG | 1) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_JPEG_CHROMA_SUBSAMPLING (V4L2_CID_JPEG_CLASS_BASE + 1) +enum v4l2_jpeg_chroma_subsampling { + V4L2_JPEG_CHROMA_SUBSAMPLING_444 = 0, + V4L2_JPEG_CHROMA_SUBSAMPLING_422 = 1, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_JPEG_CHROMA_SUBSAMPLING_420 = 2, + V4L2_JPEG_CHROMA_SUBSAMPLING_411 = 3, + V4L2_JPEG_CHROMA_SUBSAMPLING_410 = 4, + V4L2_JPEG_CHROMA_SUBSAMPLING_GRAY = 5, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +#define V4L2_CID_JPEG_RESTART_INTERVAL (V4L2_CID_JPEG_CLASS_BASE + 2) +#define V4L2_CID_JPEG_COMPRESSION_QUALITY (V4L2_CID_JPEG_CLASS_BASE + 3) +#define V4L2_CID_JPEG_ACTIVE_MARKER (V4L2_CID_JPEG_CLASS_BASE + 4) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_JPEG_ACTIVE_MARKER_APP0 (1 << 0) +#define V4L2_JPEG_ACTIVE_MARKER_APP1 (1 << 1) +#define V4L2_JPEG_ACTIVE_MARKER_COM (1 << 16) +#define V4L2_JPEG_ACTIVE_MARKER_DQT (1 << 17) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_JPEG_ACTIVE_MARKER_DHT (1 << 18) +#define V4L2_CID_IMAGE_SOURCE_CLASS_BASE (V4L2_CTRL_CLASS_IMAGE_SOURCE | 0x900) +#define V4L2_CID_IMAGE_SOURCE_CLASS (V4L2_CTRL_CLASS_IMAGE_SOURCE | 1) +#define V4L2_CID_VBLANK (V4L2_CID_IMAGE_SOURCE_CLASS_BASE + 1) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_HBLANK (V4L2_CID_IMAGE_SOURCE_CLASS_BASE + 2) +#define V4L2_CID_ANALOGUE_GAIN (V4L2_CID_IMAGE_SOURCE_CLASS_BASE + 3) +#define V4L2_CID_IMAGE_PROC_CLASS_BASE (V4L2_CTRL_CLASS_IMAGE_PROC | 0x900) +#define V4L2_CID_IMAGE_PROC_CLASS (V4L2_CTRL_CLASS_IMAGE_PROC | 1) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_LINK_FREQ (V4L2_CID_IMAGE_PROC_CLASS_BASE + 1) +#define V4L2_CID_PIXEL_RATE (V4L2_CID_IMAGE_PROC_CLASS_BASE + 2) +#define V4L2_CID_TEST_PATTERN (V4L2_CID_IMAGE_PROC_CLASS_BASE + 3) +#define V4L2_CID_DV_CLASS_BASE (V4L2_CTRL_CLASS_DV | 0x900) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_DV_CLASS (V4L2_CTRL_CLASS_DV | 1) +#define V4L2_CID_DV_TX_HOTPLUG (V4L2_CID_DV_CLASS_BASE + 1) +#define V4L2_CID_DV_TX_RXSENSE (V4L2_CID_DV_CLASS_BASE + 2) +#define V4L2_CID_DV_TX_EDID_PRESENT (V4L2_CID_DV_CLASS_BASE + 3) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_DV_TX_MODE (V4L2_CID_DV_CLASS_BASE + 4) +enum v4l2_dv_tx_mode { + V4L2_DV_TX_MODE_DVI_D = 0, + V4L2_DV_TX_MODE_HDMI = 1, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +#define V4L2_CID_DV_TX_RGB_RANGE (V4L2_CID_DV_CLASS_BASE + 5) +enum v4l2_dv_rgb_range { + V4L2_DV_RGB_RANGE_AUTO = 0, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_DV_RGB_RANGE_LIMITED = 1, + V4L2_DV_RGB_RANGE_FULL = 2, +}; +#define V4L2_CID_DV_RX_POWER_PRESENT (V4L2_CID_DV_CLASS_BASE + 100) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_DV_RX_RGB_RANGE (V4L2_CID_DV_CLASS_BASE + 101) +#define V4L2_CID_FM_RX_CLASS_BASE (V4L2_CTRL_CLASS_FM_RX | 0x900) +#define V4L2_CID_FM_RX_CLASS (V4L2_CTRL_CLASS_FM_RX | 1) +#define V4L2_CID_TUNE_DEEMPHASIS (V4L2_CID_FM_RX_CLASS_BASE + 1) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +enum v4l2_deemphasis { + V4L2_DEEMPHASIS_DISABLED = V4L2_PREEMPHASIS_DISABLED, + V4L2_DEEMPHASIS_50_uS = V4L2_PREEMPHASIS_50_uS, + V4L2_DEEMPHASIS_75_uS = V4L2_PREEMPHASIS_75_uS, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +#define V4L2_CID_RDS_RECEPTION (V4L2_CID_FM_RX_CLASS_BASE + 2) +#endif + diff --git a/kernel-headers/linux/videodev2.h b/kernel-headers/linux/videodev2.h new file mode 100644 index 0000000..8dce06d --- /dev/null +++ b/kernel-headers/linux/videodev2.h @@ -0,0 +1,1484 @@ +/**************************************************************************** + **************************************************************************** + *** + *** This header was automatically generated from a Linux kernel header + *** of the same name, to make information necessary for userspace to + *** call into the kernel available to libc. It contains only constants, + *** structures, and macros generated from the original header, and thus, + *** contains no copyrightable information. + *** + *** To edit the content of this header, modify the corresponding + *** source file (e.g. under external/kernel-headers/original/) then + *** run bionic/libc/kernel/tools/update_all.py + *** + *** Any manual change here will be lost the next time this script will + *** be run. You've been warned! + *** + **************************************************************************** + ****************************************************************************/ +#ifndef _UAPI__LINUX_VIDEODEV2_H +#define _UAPI__LINUX_VIDEODEV2_H +#include <sys/time.h> +#include <linux/compiler.h> +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#include <linux/ioctl.h> +#include <linux/types.h> +#include <linux/v4l2-common.h> +#include <linux/v4l2-controls.h> +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VIDEO_MAX_FRAME 32 +#define VIDEO_MAX_PLANES 8 +#define v4l2_fourcc(a, b, c, d) ((__u32)(a) | ((__u32)(b) << 8) | ((__u32)(c) << 16) | ((__u32)(d) << 24)) +enum v4l2_field { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_FIELD_ANY = 0, + V4L2_FIELD_NONE = 1, + V4L2_FIELD_TOP = 2, + V4L2_FIELD_BOTTOM = 3, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_FIELD_INTERLACED = 4, + V4L2_FIELD_SEQ_TB = 5, + V4L2_FIELD_SEQ_BT = 6, + V4L2_FIELD_ALTERNATE = 7, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_FIELD_INTERLACED_TB = 8, + V4L2_FIELD_INTERLACED_BT = 9, +}; +#define V4L2_FIELD_HAS_TOP(field) ((field) == V4L2_FIELD_TOP || (field) == V4L2_FIELD_INTERLACED || (field) == V4L2_FIELD_INTERLACED_TB || (field) == V4L2_FIELD_INTERLACED_BT || (field) == V4L2_FIELD_SEQ_TB || (field) == V4L2_FIELD_SEQ_BT) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_FIELD_HAS_BOTTOM(field) ((field) == V4L2_FIELD_BOTTOM || (field) == V4L2_FIELD_INTERLACED || (field) == V4L2_FIELD_INTERLACED_TB || (field) == V4L2_FIELD_INTERLACED_BT || (field) == V4L2_FIELD_SEQ_TB || (field) == V4L2_FIELD_SEQ_BT) +#define V4L2_FIELD_HAS_BOTH(field) ((field) == V4L2_FIELD_INTERLACED || (field) == V4L2_FIELD_INTERLACED_TB || (field) == V4L2_FIELD_INTERLACED_BT || (field) == V4L2_FIELD_SEQ_TB || (field) == V4L2_FIELD_SEQ_BT) +enum v4l2_buf_type { + V4L2_BUF_TYPE_VIDEO_CAPTURE = 1, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_BUF_TYPE_VIDEO_OUTPUT = 2, + V4L2_BUF_TYPE_VIDEO_OVERLAY = 3, + V4L2_BUF_TYPE_VBI_CAPTURE = 4, + V4L2_BUF_TYPE_VBI_OUTPUT = 5, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_BUF_TYPE_SLICED_VBI_CAPTURE = 6, + V4L2_BUF_TYPE_SLICED_VBI_OUTPUT = 7, + V4L2_BUF_TYPE_VIDEO_OUTPUT_OVERLAY = 8, + V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE = 9, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE = 10, + V4L2_BUF_TYPE_PRIVATE = 0x80, +}; +#define V4L2_TYPE_IS_MULTIPLANAR(type) ((type) == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE || (type) == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_TYPE_IS_OUTPUT(type) ((type) == V4L2_BUF_TYPE_VIDEO_OUTPUT || (type) == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE || (type) == V4L2_BUF_TYPE_VIDEO_OVERLAY || (type) == V4L2_BUF_TYPE_VIDEO_OUTPUT_OVERLAY || (type) == V4L2_BUF_TYPE_VBI_OUTPUT || (type) == V4L2_BUF_TYPE_SLICED_VBI_OUTPUT) +#define V4L2_TYPE_IS_PRIVATE(type) ((type) == V4L2_BUF_TYPE_PRIVATE) +enum v4l2_tuner_type { + V4L2_TUNER_RADIO = 1, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_TUNER_ANALOG_TV = 2, + V4L2_TUNER_DIGITAL_TV = 3, +}; +enum v4l2_memory { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_MEMORY_MMAP = 1, + V4L2_MEMORY_USERPTR = 2, + V4L2_MEMORY_OVERLAY = 3, + V4L2_MEMORY_DMABUF = 4, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +enum v4l2_colorspace { + V4L2_COLORSPACE_SMPTE170M = 1, + V4L2_COLORSPACE_SMPTE240M = 2, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_COLORSPACE_REC709 = 3, + V4L2_COLORSPACE_BT878 = 4, + V4L2_COLORSPACE_470_SYSTEM_M = 5, + V4L2_COLORSPACE_470_SYSTEM_BG = 6, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_COLORSPACE_JPEG = 7, + V4L2_COLORSPACE_SRGB = 8, +}; +enum v4l2_priority { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_PRIORITY_UNSET = 0, + V4L2_PRIORITY_BACKGROUND = 1, + V4L2_PRIORITY_INTERACTIVE = 2, + V4L2_PRIORITY_RECORD = 3, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_PRIORITY_DEFAULT = V4L2_PRIORITY_INTERACTIVE, +}; +struct v4l2_rect { + __s32 left; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __s32 top; + __s32 width; + __s32 height; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct v4l2_fract { + __u32 numerator; + __u32 denominator; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct v4l2_capability { + __u8 driver[16]; + __u8 card[32]; + __u8 bus_info[32]; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u32 version; + __u32 capabilities; + __u32 device_caps; + __u32 reserved[3]; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +#define V4L2_CAP_VIDEO_CAPTURE 0x00000001 +#define V4L2_CAP_VIDEO_OUTPUT 0x00000002 +#define V4L2_CAP_VIDEO_OVERLAY 0x00000004 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CAP_VBI_CAPTURE 0x00000010 +#define V4L2_CAP_VBI_OUTPUT 0x00000020 +#define V4L2_CAP_SLICED_VBI_CAPTURE 0x00000040 +#define V4L2_CAP_SLICED_VBI_OUTPUT 0x00000080 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CAP_RDS_CAPTURE 0x00000100 +#define V4L2_CAP_VIDEO_OUTPUT_OVERLAY 0x00000200 +#define V4L2_CAP_HW_FREQ_SEEK 0x00000400 +#define V4L2_CAP_RDS_OUTPUT 0x00000800 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CAP_VIDEO_CAPTURE_MPLANE 0x00001000 +#define V4L2_CAP_VIDEO_OUTPUT_MPLANE 0x00002000 +#define V4L2_CAP_VIDEO_M2M_MPLANE 0x00004000 +#define V4L2_CAP_VIDEO_M2M 0x00008000 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CAP_TUNER 0x00010000 +#define V4L2_CAP_AUDIO 0x00020000 +#define V4L2_CAP_RADIO 0x00040000 +#define V4L2_CAP_MODULATOR 0x00080000 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CAP_READWRITE 0x01000000 +#define V4L2_CAP_ASYNCIO 0x02000000 +#define V4L2_CAP_STREAMING 0x04000000 +#define V4L2_CAP_DEVICE_CAPS 0x80000000 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct v4l2_pix_format { + __u32 width; + __u32 height; + __u32 pixelformat; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u32 field; + __u32 bytesperline; + __u32 sizeimage; + __u32 colorspace; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u32 priv; +}; +#define V4L2_PIX_FMT_RGB332 v4l2_fourcc('R', 'G', 'B', '1') +#define V4L2_PIX_FMT_RGB444 v4l2_fourcc('R', '4', '4', '4') +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_PIX_FMT_RGB555 v4l2_fourcc('R', 'G', 'B', 'O') +#define V4L2_PIX_FMT_RGB565 v4l2_fourcc('R', 'G', 'B', 'P') +#define V4L2_PIX_FMT_RGB555X v4l2_fourcc('R', 'G', 'B', 'Q') +#define V4L2_PIX_FMT_RGB565X v4l2_fourcc('R', 'G', 'B', 'R') +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_PIX_FMT_BGR666 v4l2_fourcc('B', 'G', 'R', 'H') +#define V4L2_PIX_FMT_BGR24 v4l2_fourcc('B', 'G', 'R', '3') +#define V4L2_PIX_FMT_RGB24 v4l2_fourcc('R', 'G', 'B', '3') +#define V4L2_PIX_FMT_BGR32 v4l2_fourcc('B', 'G', 'R', '4') +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_PIX_FMT_RGB32 v4l2_fourcc('R', 'G', 'B', '4') +#define V4L2_PIX_FMT_GREY v4l2_fourcc('G', 'R', 'E', 'Y') +#define V4L2_PIX_FMT_Y4 v4l2_fourcc('Y', '0', '4', ' ') +#define V4L2_PIX_FMT_Y6 v4l2_fourcc('Y', '0', '6', ' ') +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_PIX_FMT_Y10 v4l2_fourcc('Y', '1', '0', ' ') +#define V4L2_PIX_FMT_Y12 v4l2_fourcc('Y', '1', '2', ' ') +#define V4L2_PIX_FMT_Y16 v4l2_fourcc('Y', '1', '6', ' ') +#define V4L2_PIX_FMT_Y10BPACK v4l2_fourcc('Y', '1', '0', 'B') +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_PIX_FMT_PAL8 v4l2_fourcc('P', 'A', 'L', '8') +#define V4L2_PIX_FMT_UV8 v4l2_fourcc('U', 'V', '8', ' ') +#define V4L2_PIX_FMT_YVU410 v4l2_fourcc('Y', 'V', 'U', '9') +#define V4L2_PIX_FMT_YVU420 v4l2_fourcc('Y', 'V', '1', '2') +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_PIX_FMT_YUYV v4l2_fourcc('Y', 'U', 'Y', 'V') +#define V4L2_PIX_FMT_YYUV v4l2_fourcc('Y', 'Y', 'U', 'V') +#define V4L2_PIX_FMT_YVYU v4l2_fourcc('Y', 'V', 'Y', 'U') +#define V4L2_PIX_FMT_UYVY v4l2_fourcc('U', 'Y', 'V', 'Y') +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_PIX_FMT_VYUY v4l2_fourcc('V', 'Y', 'U', 'Y') +#define V4L2_PIX_FMT_YUV422P v4l2_fourcc('4', '2', '2', 'P') +#define V4L2_PIX_FMT_YUV411P v4l2_fourcc('4', '1', '1', 'P') +#define V4L2_PIX_FMT_Y41P v4l2_fourcc('Y', '4', '1', 'P') +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_PIX_FMT_YUV444 v4l2_fourcc('Y', '4', '4', '4') +#define V4L2_PIX_FMT_YUV555 v4l2_fourcc('Y', 'U', 'V', 'O') +#define V4L2_PIX_FMT_YUV565 v4l2_fourcc('Y', 'U', 'V', 'P') +#define V4L2_PIX_FMT_YUV32 v4l2_fourcc('Y', 'U', 'V', '4') +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_PIX_FMT_YUV410 v4l2_fourcc('Y', 'U', 'V', '9') +#define V4L2_PIX_FMT_YUV420 v4l2_fourcc('Y', 'U', '1', '2') +#define V4L2_PIX_FMT_HI240 v4l2_fourcc('H', 'I', '2', '4') +#define V4L2_PIX_FMT_HM12 v4l2_fourcc('H', 'M', '1', '2') +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_PIX_FMT_M420 v4l2_fourcc('M', '4', '2', '0') +#define V4L2_PIX_FMT_NV12 v4l2_fourcc('N', 'V', '1', '2') +#define V4L2_PIX_FMT_NV21 v4l2_fourcc('N', 'V', '2', '1') +#define V4L2_PIX_FMT_NV16 v4l2_fourcc('N', 'V', '1', '6') +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_PIX_FMT_NV61 v4l2_fourcc('N', 'V', '6', '1') +#define V4L2_PIX_FMT_NV24 v4l2_fourcc('N', 'V', '2', '4') +#define V4L2_PIX_FMT_NV42 v4l2_fourcc('N', 'V', '4', '2') +#define V4L2_PIX_FMT_NV12M v4l2_fourcc('N', 'M', '1', '2') +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_PIX_FMT_NV21M v4l2_fourcc('N', 'M', '2', '1') +#define V4L2_PIX_FMT_NV12MT v4l2_fourcc('T', 'M', '1', '2') +#define V4L2_PIX_FMT_NV12MT_16X16 v4l2_fourcc('V', 'M', '1', '2') +#define V4L2_PIX_FMT_YUV420M v4l2_fourcc('Y', 'M', '1', '2') +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_PIX_FMT_YVU420M v4l2_fourcc('Y', 'M', '2', '1') +#define V4L2_PIX_FMT_SBGGR8 v4l2_fourcc('B', 'A', '8', '1') +#define V4L2_PIX_FMT_SGBRG8 v4l2_fourcc('G', 'B', 'R', 'G') +#define V4L2_PIX_FMT_SGRBG8 v4l2_fourcc('G', 'R', 'B', 'G') +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_PIX_FMT_SRGGB8 v4l2_fourcc('R', 'G', 'G', 'B') +#define V4L2_PIX_FMT_SBGGR10 v4l2_fourcc('B', 'G', '1', '0') +#define V4L2_PIX_FMT_SGBRG10 v4l2_fourcc('G', 'B', '1', '0') +#define V4L2_PIX_FMT_SGRBG10 v4l2_fourcc('B', 'A', '1', '0') +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_PIX_FMT_SRGGB10 v4l2_fourcc('R', 'G', '1', '0') +#define V4L2_PIX_FMT_SBGGR12 v4l2_fourcc('B', 'G', '1', '2') +#define V4L2_PIX_FMT_SGBRG12 v4l2_fourcc('G', 'B', '1', '2') +#define V4L2_PIX_FMT_SGRBG12 v4l2_fourcc('B', 'A', '1', '2') +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_PIX_FMT_SRGGB12 v4l2_fourcc('R', 'G', '1', '2') +#define V4L2_PIX_FMT_SBGGR10ALAW8 v4l2_fourcc('a', 'B', 'A', '8') +#define V4L2_PIX_FMT_SGBRG10ALAW8 v4l2_fourcc('a', 'G', 'A', '8') +#define V4L2_PIX_FMT_SGRBG10ALAW8 v4l2_fourcc('a', 'g', 'A', '8') +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_PIX_FMT_SRGGB10ALAW8 v4l2_fourcc('a', 'R', 'A', '8') +#define V4L2_PIX_FMT_SBGGR10DPCM8 v4l2_fourcc('b', 'B', 'A', '8') +#define V4L2_PIX_FMT_SGBRG10DPCM8 v4l2_fourcc('b', 'G', 'A', '8') +#define V4L2_PIX_FMT_SGRBG10DPCM8 v4l2_fourcc('B', 'D', '1', '0') +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_PIX_FMT_SRGGB10DPCM8 v4l2_fourcc('b', 'R', 'A', '8') +#define V4L2_PIX_FMT_SBGGR16 v4l2_fourcc('B', 'Y', 'R', '2') +#define V4L2_PIX_FMT_MJPEG v4l2_fourcc('M', 'J', 'P', 'G') +#define V4L2_PIX_FMT_JPEG v4l2_fourcc('J', 'P', 'E', 'G') +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_PIX_FMT_DV v4l2_fourcc('d', 'v', 's', 'd') +#define V4L2_PIX_FMT_MPEG v4l2_fourcc('M', 'P', 'E', 'G') +#define V4L2_PIX_FMT_H264 v4l2_fourcc('H', '2', '6', '4') +#define V4L2_PIX_FMT_H264_NO_SC v4l2_fourcc('A', 'V', 'C', '1') +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_PIX_FMT_H264_MVC v4l2_fourcc('M', '2', '6', '4') +#define V4L2_PIX_FMT_H263 v4l2_fourcc('H', '2', '6', '3') +#define V4L2_PIX_FMT_MPEG1 v4l2_fourcc('M', 'P', 'G', '1') +#define V4L2_PIX_FMT_MPEG2 v4l2_fourcc('M', 'P', 'G', '2') +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_PIX_FMT_MPEG4 v4l2_fourcc('M', 'P', 'G', '4') +#define V4L2_PIX_FMT_XVID v4l2_fourcc('X', 'V', 'I', 'D') +#define V4L2_PIX_FMT_VC1_ANNEX_G v4l2_fourcc('V', 'C', '1', 'G') +#define V4L2_PIX_FMT_VC1_ANNEX_L v4l2_fourcc('V', 'C', '1', 'L') +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_PIX_FMT_DIVX_311 v4l2_fourcc('D', 'I', 'V', '3') +#define V4L2_PIX_FMT_DIVX v4l2_fourcc('D', 'I', 'V', 'X') +#define V4L2_PIX_FMT_VP8 v4l2_fourcc('V', 'P', '8', '0') +#define V4L2_PIX_FMT_HEVC v4l2_fourcc('H', 'E', 'V', 'C') +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_PIX_FMT_HEVC_HYBRID v4l2_fourcc('H', 'V', 'C', 'H') +#define V4L2_PIX_FMT_CPIA1 v4l2_fourcc('C', 'P', 'I', 'A') +#define V4L2_PIX_FMT_WNVA v4l2_fourcc('W', 'N', 'V', 'A') +#define V4L2_PIX_FMT_SN9C10X v4l2_fourcc('S', '9', '1', '0') +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_PIX_FMT_SN9C20X_I420 v4l2_fourcc('S', '9', '2', '0') +#define V4L2_PIX_FMT_PWC1 v4l2_fourcc('P', 'W', 'C', '1') +#define V4L2_PIX_FMT_PWC2 v4l2_fourcc('P', 'W', 'C', '2') +#define V4L2_PIX_FMT_ET61X251 v4l2_fourcc('E', '6', '2', '5') +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_PIX_FMT_SPCA501 v4l2_fourcc('S', '5', '0', '1') +#define V4L2_PIX_FMT_SPCA505 v4l2_fourcc('S', '5', '0', '5') +#define V4L2_PIX_FMT_SPCA508 v4l2_fourcc('S', '5', '0', '8') +#define V4L2_PIX_FMT_SPCA561 v4l2_fourcc('S', '5', '6', '1') +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_PIX_FMT_PAC207 v4l2_fourcc('P', '2', '0', '7') +#define V4L2_PIX_FMT_MR97310A v4l2_fourcc('M', '3', '1', '0') +#define V4L2_PIX_FMT_JL2005BCD v4l2_fourcc('J', 'L', '2', '0') +#define V4L2_PIX_FMT_SN9C2028 v4l2_fourcc('S', 'O', 'N', 'X') +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_PIX_FMT_SQ905C v4l2_fourcc('9', '0', '5', 'C') +#define V4L2_PIX_FMT_PJPG v4l2_fourcc('P', 'J', 'P', 'G') +#define V4L2_PIX_FMT_OV511 v4l2_fourcc('O', '5', '1', '1') +#define V4L2_PIX_FMT_OV518 v4l2_fourcc('O', '5', '1', '8') +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_PIX_FMT_STV0680 v4l2_fourcc('S', '6', '8', '0') +#define V4L2_PIX_FMT_TM6000 v4l2_fourcc('T', 'M', '6', '0') +#define V4L2_PIX_FMT_CIT_YYVYUY v4l2_fourcc('C', 'I', 'T', 'V') +#define V4L2_PIX_FMT_KONICA420 v4l2_fourcc('K', 'O', 'N', 'I') +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_PIX_FMT_JPGL v4l2_fourcc('J', 'P', 'G', 'L') +#define V4L2_PIX_FMT_SE401 v4l2_fourcc('S', '4', '0', '1') +#define V4L2_PIX_FMT_S5C_UYVY_JPG v4l2_fourcc('S', '5', 'C', 'I') +#define V4L2_PIX_FMT_STATS_COMB v4l2_fourcc('S', 'T', 'C', 'M') +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_PIX_FMT_STATS_AE v4l2_fourcc('S', 'T', 'A', 'E') +#define V4L2_PIX_FMT_STATS_AF v4l2_fourcc('S', 'T', 'A', 'F') +#define V4L2_PIX_FMT_STATS_AWB v4l2_fourcc('S', 'T', 'W', 'B') +#define V4L2_PIX_FMT_STATS_IHST v4l2_fourcc('I', 'H', 'S', 'T') +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_PIX_FMT_STATS_CS v4l2_fourcc('S', 'T', 'C', 'S') +#define V4L2_PIX_FMT_STATS_RS v4l2_fourcc('S', 'T', 'R', 'S') +#define V4L2_PIX_FMT_STATS_BG v4l2_fourcc('S', 'T', 'B', 'G') +#define V4L2_PIX_FMT_STATS_BF v4l2_fourcc('S', 'T', 'B', 'F') +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_PIX_FMT_STATS_BHST v4l2_fourcc('B', 'H', 'S', 'T') +struct v4l2_fmtdesc { + __u32 index; + __u32 type; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u32 flags; + __u8 description[32]; + __u32 pixelformat; + __u32 reserved[4]; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +#define V4L2_FMT_FLAG_COMPRESSED 0x0001 +#define V4L2_FMT_FLAG_EMULATED 0x0002 +enum v4l2_frmsizetypes { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_FRMSIZE_TYPE_DISCRETE = 1, + V4L2_FRMSIZE_TYPE_CONTINUOUS = 2, + V4L2_FRMSIZE_TYPE_STEPWISE = 3, +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct v4l2_frmsize_discrete { + __u32 width; + __u32 height; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct v4l2_frmsize_stepwise { + __u32 min_width; + __u32 max_width; + __u32 step_width; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u32 min_height; + __u32 max_height; + __u32 step_height; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct v4l2_frmsizeenum { + __u32 index; + __u32 pixel_format; + __u32 type; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + union { + struct v4l2_frmsize_discrete discrete; + struct v4l2_frmsize_stepwise stepwise; + }; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u32 reserved[2]; +}; +enum v4l2_frmivaltypes { + V4L2_FRMIVAL_TYPE_DISCRETE = 1, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_FRMIVAL_TYPE_CONTINUOUS = 2, + V4L2_FRMIVAL_TYPE_STEPWISE = 3, +}; +struct v4l2_frmival_stepwise { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + struct v4l2_fract min; + struct v4l2_fract max; + struct v4l2_fract step; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct v4l2_frmivalenum { + __u32 index; + __u32 pixel_format; + __u32 width; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u32 height; + __u32 type; + union { + struct v4l2_fract discrete; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + struct v4l2_frmival_stepwise stepwise; + }; + __u32 reserved[2]; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct v4l2_timecode { + __u32 type; + __u32 flags; + __u8 frames; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u8 seconds; + __u8 minutes; + __u8 hours; + __u8 userbits[4]; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +#define V4L2_TC_TYPE_24FPS 1 +#define V4L2_TC_TYPE_25FPS 2 +#define V4L2_TC_TYPE_30FPS 3 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_TC_TYPE_50FPS 4 +#define V4L2_TC_TYPE_60FPS 5 +#define V4L2_TC_FLAG_DROPFRAME 0x0001 +#define V4L2_TC_FLAG_COLORFRAME 0x0002 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_TC_USERBITS_field 0x000C +#define V4L2_TC_USERBITS_USERDEFINED 0x0000 +#define V4L2_TC_USERBITS_8BITCHARS 0x0008 +struct v4l2_jpegcompression { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + int quality; + int APPn; + int APP_len; + char APP_data[60]; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + int COM_len; + char COM_data[60]; + __u32 jpeg_markers; +#define V4L2_JPEG_MARKER_DHT (1<<3) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_JPEG_MARKER_DQT (1<<4) +#define V4L2_JPEG_MARKER_DRI (1<<5) +#define V4L2_JPEG_MARKER_COM (1<<6) +#define V4L2_JPEG_MARKER_APP (1<<7) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +struct v4l2_requestbuffers { + __u32 count; + __u32 type; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u32 memory; + __u32 reserved[2]; +}; +struct v4l2_plane { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u32 bytesused; + __u32 length; + union { + __u32 mem_offset; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned long userptr; + __s32 fd; + } m; + __u32 data_offset; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u32 reserved[11]; +}; +struct v4l2_buffer { + __u32 index; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u32 type; + __u32 bytesused; + __u32 flags; + __u32 field; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + struct timeval timestamp; + struct v4l2_timecode timecode; + __u32 sequence; + __u32 memory; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + union { + __u32 offset; + unsigned long userptr; + struct v4l2_plane *planes; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __s32 fd; + } m; + __u32 length; + __u32 reserved2; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u32 reserved; +}; +#define V4L2_BUF_FLAG_MAPPED 0x0001 +#define V4L2_BUF_FLAG_QUEUED 0x0002 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_BUF_FLAG_DONE 0x0004 +#define V4L2_BUF_FLAG_KEYFRAME 0x0008 +#define V4L2_BUF_FLAG_PFRAME 0x0010 +#define V4L2_BUF_FLAG_BFRAME 0x0020 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_BUF_FLAG_ERROR 0x0040 +#define V4L2_BUF_FLAG_TIMECODE 0x0100 +#define V4L2_BUF_FLAG_PREPARED 0x0400 +#define V4L2_BUF_FLAG_NO_CACHE_INVALIDATE 0x0800 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_BUF_FLAG_NO_CACHE_CLEAN 0x1000 +#define V4L2_BUF_FLAG_TIMESTAMP_MASK 0xe000 +#define V4L2_BUF_FLAG_TIMESTAMP_UNKNOWN 0x0000 +#define V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC 0x2000 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_BUF_FLAG_TIMESTAMP_COPY 0x4000 +#define V4L2_QCOM_BUF_FLAG_CODECCONFIG 0x10000 +#define V4L2_QCOM_BUF_FLAG_EOSEQ 0x20000 +#define V4L2_QCOM_BUF_TIMESTAMP_INVALID 0x40000 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_QCOM_BUF_FLAG_IDRFRAME 0x80000 +#define V4L2_QCOM_BUF_FLAG_DECODEONLY 0x100000 +#define V4L2_QCOM_BUF_DATA_CORRUPT 0x200000 +#define V4L2_QCOM_BUF_DROP_FRAME 0x400000 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_QCOM_BUF_INPUT_UNSUPPORTED 0x800000 +#define V4L2_QCOM_BUF_FLAG_EOS 0x1000000 +#define V4L2_QCOM_BUF_TS_DISCONTINUITY 0x2000000 +#define V4L2_QCOM_BUF_TS_ERROR 0x4000000 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_QCOM_BUF_FLAG_READONLY 0x8000000 +#define V4L2_MSM_VIDC_BUF_START_CODE_NOT_FOUND 0x10000000 +#define V4L2_MSM_BUF_FLAG_YUV_601_709_CLAMP 0x20000000 +#define V4L2_MSM_BUF_FLAG_MBAFF 0x40000000 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct v4l2_exportbuffer { + __u32 type; + __u32 index; + __u32 plane; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u32 flags; + __s32 fd; + __u32 reserved[11]; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct v4l2_framebuffer { + __u32 capability; + __u32 flags; + void *base; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + struct v4l2_pix_format fmt; +}; +#define V4L2_FBUF_CAP_EXTERNOVERLAY 0x0001 +#define V4L2_FBUF_CAP_CHROMAKEY 0x0002 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_FBUF_CAP_LIST_CLIPPING 0x0004 +#define V4L2_FBUF_CAP_BITMAP_CLIPPING 0x0008 +#define V4L2_FBUF_CAP_LOCAL_ALPHA 0x0010 +#define V4L2_FBUF_CAP_GLOBAL_ALPHA 0x0020 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_FBUF_CAP_LOCAL_INV_ALPHA 0x0040 +#define V4L2_FBUF_CAP_SRC_CHROMAKEY 0x0080 +#define V4L2_FBUF_FLAG_PRIMARY 0x0001 +#define V4L2_FBUF_FLAG_OVERLAY 0x0002 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_FBUF_FLAG_CHROMAKEY 0x0004 +#define V4L2_FBUF_FLAG_LOCAL_ALPHA 0x0008 +#define V4L2_FBUF_FLAG_GLOBAL_ALPHA 0x0010 +#define V4L2_FBUF_FLAG_LOCAL_INV_ALPHA 0x0020 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_FBUF_FLAG_SRC_CHROMAKEY 0x0040 +struct v4l2_clip { + struct v4l2_rect c; + struct v4l2_clip __user *next; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +struct v4l2_window { + struct v4l2_rect w; + __u32 field; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u32 chromakey; + struct v4l2_clip __user *clips; + __u32 clipcount; + void __user *bitmap; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u8 global_alpha; +}; +struct v4l2_captureparm { + __u32 capability; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u32 capturemode; + struct v4l2_fract timeperframe; + __u32 extendedmode; + __u32 readbuffers; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u32 reserved[4]; +}; +#define V4L2_MODE_HIGHQUALITY 0x0001 +#define V4L2_CAP_TIMEPERFRAME 0x1000 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CAP_QCOM_FRAMESKIP 0x2000 +struct v4l2_qcom_frameskip { + __u64 maxframeinterval; + __u8 fpsvariance; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +struct v4l2_outputparm { + __u32 capability; + __u32 outputmode; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + struct v4l2_fract timeperframe; + __u32 extendedmode; + __u32 writebuffers; + __u32 reserved[4]; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +struct v4l2_cropcap { + __u32 type; + struct v4l2_rect bounds; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + struct v4l2_rect defrect; + struct v4l2_fract pixelaspect; +}; +struct v4l2_crop { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u32 type; + struct v4l2_rect c; +}; +struct v4l2_selection { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u32 type; + __u32 target; + __u32 flags; + struct v4l2_rect r; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u32 reserved[9]; +}; +typedef __u64 v4l2_std_id; +#define V4L2_STD_PAL_B ((v4l2_std_id)0x00000001) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_STD_PAL_B1 ((v4l2_std_id)0x00000002) +#define V4L2_STD_PAL_G ((v4l2_std_id)0x00000004) +#define V4L2_STD_PAL_H ((v4l2_std_id)0x00000008) +#define V4L2_STD_PAL_I ((v4l2_std_id)0x00000010) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_STD_PAL_D ((v4l2_std_id)0x00000020) +#define V4L2_STD_PAL_D1 ((v4l2_std_id)0x00000040) +#define V4L2_STD_PAL_K ((v4l2_std_id)0x00000080) +#define V4L2_STD_PAL_M ((v4l2_std_id)0x00000100) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_STD_PAL_N ((v4l2_std_id)0x00000200) +#define V4L2_STD_PAL_Nc ((v4l2_std_id)0x00000400) +#define V4L2_STD_PAL_60 ((v4l2_std_id)0x00000800) +#define V4L2_STD_NTSC_M ((v4l2_std_id)0x00001000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_STD_NTSC_M_JP ((v4l2_std_id)0x00002000) +#define V4L2_STD_NTSC_443 ((v4l2_std_id)0x00004000) +#define V4L2_STD_NTSC_M_KR ((v4l2_std_id)0x00008000) +#define V4L2_STD_SECAM_B ((v4l2_std_id)0x00010000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_STD_SECAM_D ((v4l2_std_id)0x00020000) +#define V4L2_STD_SECAM_G ((v4l2_std_id)0x00040000) +#define V4L2_STD_SECAM_H ((v4l2_std_id)0x00080000) +#define V4L2_STD_SECAM_K ((v4l2_std_id)0x00100000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_STD_SECAM_K1 ((v4l2_std_id)0x00200000) +#define V4L2_STD_SECAM_L ((v4l2_std_id)0x00400000) +#define V4L2_STD_SECAM_LC ((v4l2_std_id)0x00800000) +#define V4L2_STD_ATSC_8_VSB ((v4l2_std_id)0x01000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_STD_ATSC_16_VSB ((v4l2_std_id)0x02000000) +#define V4L2_STD_NTSC (V4L2_STD_NTSC_M | V4L2_STD_NTSC_M_JP | V4L2_STD_NTSC_M_KR) +#define V4L2_STD_SECAM_DK (V4L2_STD_SECAM_D | V4L2_STD_SECAM_K | V4L2_STD_SECAM_K1) +#define V4L2_STD_SECAM (V4L2_STD_SECAM_B | V4L2_STD_SECAM_G | V4L2_STD_SECAM_H | V4L2_STD_SECAM_DK | V4L2_STD_SECAM_L | V4L2_STD_SECAM_LC) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_STD_PAL_BG (V4L2_STD_PAL_B | V4L2_STD_PAL_B1 | V4L2_STD_PAL_G) +#define V4L2_STD_PAL_DK (V4L2_STD_PAL_D | V4L2_STD_PAL_D1 | V4L2_STD_PAL_K) +#define V4L2_STD_PAL (V4L2_STD_PAL_BG | V4L2_STD_PAL_DK | V4L2_STD_PAL_H | V4L2_STD_PAL_I) +#define V4L2_STD_B (V4L2_STD_PAL_B | V4L2_STD_PAL_B1 | V4L2_STD_SECAM_B) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_STD_G (V4L2_STD_PAL_G | V4L2_STD_SECAM_G) +#define V4L2_STD_H (V4L2_STD_PAL_H | V4L2_STD_SECAM_H) +#define V4L2_STD_L (V4L2_STD_SECAM_L | V4L2_STD_SECAM_LC) +#define V4L2_STD_GH (V4L2_STD_G | V4L2_STD_H) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_STD_DK (V4L2_STD_PAL_DK | V4L2_STD_SECAM_DK) +#define V4L2_STD_BG (V4L2_STD_B | V4L2_STD_G) +#define V4L2_STD_MN (V4L2_STD_PAL_M | V4L2_STD_PAL_N | V4L2_STD_PAL_Nc | V4L2_STD_NTSC) +#define V4L2_STD_MTS (V4L2_STD_NTSC_M | V4L2_STD_PAL_M | V4L2_STD_PAL_N | V4L2_STD_PAL_Nc) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_STD_525_60 (V4L2_STD_PAL_M | V4L2_STD_PAL_60 | V4L2_STD_NTSC | V4L2_STD_NTSC_443) +#define V4L2_STD_625_50 (V4L2_STD_PAL | V4L2_STD_PAL_N | V4L2_STD_PAL_Nc | V4L2_STD_SECAM) +#define V4L2_STD_ATSC (V4L2_STD_ATSC_8_VSB | V4L2_STD_ATSC_16_VSB) +#define V4L2_STD_UNKNOWN 0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_STD_ALL (V4L2_STD_525_60 | V4L2_STD_625_50) +struct v4l2_standard { + __u32 index; + v4l2_std_id id; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u8 name[24]; + struct v4l2_fract frameperiod; + __u32 framelines; + __u32 reserved[4]; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +struct v4l2_bt_timings { + __u32 width; + __u32 height; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u32 interlaced; + __u32 polarities; + __u64 pixelclock; + __u32 hfrontporch; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u32 hsync; + __u32 hbackporch; + __u32 vfrontporch; + __u32 vsync; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u32 vbackporch; + __u32 il_vfrontporch; + __u32 il_vsync; + __u32 il_vbackporch; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u32 standards; + __u32 flags; + __u32 reserved[14]; +} __attribute__ ((packed)); +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_DV_PROGRESSIVE 0 +#define V4L2_DV_INTERLACED 1 +#define V4L2_DV_VSYNC_POS_POL 0x00000001 +#define V4L2_DV_HSYNC_POS_POL 0x00000002 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_DV_BT_STD_CEA861 (1 << 0) +#define V4L2_DV_BT_STD_DMT (1 << 1) +#define V4L2_DV_BT_STD_CVT (1 << 2) +#define V4L2_DV_BT_STD_GTF (1 << 3) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_DV_FL_REDUCED_BLANKING (1 << 0) +#define V4L2_DV_FL_CAN_REDUCE_FPS (1 << 1) +#define V4L2_DV_FL_REDUCED_FPS (1 << 2) +#define V4L2_DV_FL_HALF_LINE (1 << 3) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct v4l2_dv_timings { + __u32 type; + union { + struct v4l2_bt_timings bt; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u32 reserved[32]; + }; +} __attribute__ ((packed)); +#define V4L2_DV_BT_656_1120 0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct v4l2_enum_dv_timings { + __u32 index; + __u32 reserved[3]; + struct v4l2_dv_timings timings; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +struct v4l2_bt_timings_cap { + __u32 min_width; + __u32 max_width; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u32 min_height; + __u32 max_height; + __u64 min_pixelclock; + __u64 max_pixelclock; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u32 standards; + __u32 capabilities; + __u32 reserved[16]; +} __attribute__ ((packed)); +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_DV_BT_CAP_INTERLACED (1 << 0) +#define V4L2_DV_BT_CAP_PROGRESSIVE (1 << 1) +#define V4L2_DV_BT_CAP_REDUCED_BLANKING (1 << 2) +#define V4L2_DV_BT_CAP_CUSTOM (1 << 3) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct v4l2_dv_timings_cap { + __u32 type; + __u32 reserved[3]; + union { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + struct v4l2_bt_timings_cap bt; + __u32 raw_data[32]; + }; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct v4l2_input { + __u32 index; + __u8 name[32]; + __u32 type; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u32 audioset; + __u32 tuner; + v4l2_std_id std; + __u32 status; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u32 capabilities; + __u32 reserved[3]; +}; +#define V4L2_INPUT_TYPE_TUNER 1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_INPUT_TYPE_CAMERA 2 +#define V4L2_IN_ST_NO_POWER 0x00000001 +#define V4L2_IN_ST_NO_SIGNAL 0x00000002 +#define V4L2_IN_ST_NO_COLOR 0x00000004 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_IN_ST_HFLIP 0x00000010 +#define V4L2_IN_ST_VFLIP 0x00000020 +#define V4L2_IN_ST_NO_H_LOCK 0x00000100 +#define V4L2_IN_ST_COLOR_KILL 0x00000200 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_IN_ST_NO_SYNC 0x00010000 +#define V4L2_IN_ST_NO_EQU 0x00020000 +#define V4L2_IN_ST_NO_CARRIER 0x00040000 +#define V4L2_IN_ST_MACROVISION 0x01000000 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_IN_ST_NO_ACCESS 0x02000000 +#define V4L2_IN_ST_VTR 0x04000000 +#define V4L2_IN_CAP_DV_TIMINGS 0x00000002 +#define V4L2_IN_CAP_CUSTOM_TIMINGS V4L2_IN_CAP_DV_TIMINGS +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_IN_CAP_STD 0x00000004 +struct v4l2_output { + __u32 index; + __u8 name[32]; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u32 type; + __u32 audioset; + __u32 modulator; + v4l2_std_id std; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u32 capabilities; + __u32 reserved[3]; +}; +#define V4L2_OUTPUT_TYPE_MODULATOR 1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_OUTPUT_TYPE_ANALOG 2 +#define V4L2_OUTPUT_TYPE_ANALOGVGAOVERLAY 3 +#define V4L2_OUT_CAP_DV_TIMINGS 0x00000002 +#define V4L2_OUT_CAP_CUSTOM_TIMINGS V4L2_OUT_CAP_DV_TIMINGS +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_OUT_CAP_STD 0x00000004 +struct v4l2_control { + __u32 id; + __s32 value; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +struct v4l2_ext_control { + __u32 id; + __u32 size; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u32 reserved2[1]; + union { + __s32 value; + __s64 value64; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + char *string; + }; +} __attribute__ ((packed)); +struct v4l2_ext_controls { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u32 ctrl_class; + __u32 count; + __u32 error_idx; + __u32 reserved[2]; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + struct v4l2_ext_control *controls; +}; +#define V4L2_CTRL_ID_MASK (0x0fffffff) +#define V4L2_CTRL_ID2CLASS(id) ((id) & 0x0fff0000UL) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CTRL_DRIVER_PRIV(id) (((id) & 0xffff) >= 0x1000) +enum v4l2_ctrl_type { + V4L2_CTRL_TYPE_INTEGER = 1, + V4L2_CTRL_TYPE_BOOLEAN = 2, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_CTRL_TYPE_MENU = 3, + V4L2_CTRL_TYPE_BUTTON = 4, + V4L2_CTRL_TYPE_INTEGER64 = 5, + V4L2_CTRL_TYPE_CTRL_CLASS = 6, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + V4L2_CTRL_TYPE_STRING = 7, + V4L2_CTRL_TYPE_BITMASK = 8, + V4L2_CTRL_TYPE_INTEGER_MENU = 9, +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct v4l2_queryctrl { + __u32 id; + __u32 type; + __u8 name[32]; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __s32 minimum; + __s32 maximum; + __s32 step; + __s32 default_value; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u32 flags; + __u32 reserved[2]; +}; +struct v4l2_querymenu { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u32 id; + __u32 index; + union { + __u8 name[32]; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __s64 value; + }; + __u32 reserved; +} __attribute__ ((packed)); +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CTRL_FLAG_DISABLED 0x0001 +#define V4L2_CTRL_FLAG_GRABBED 0x0002 +#define V4L2_CTRL_FLAG_READ_ONLY 0x0004 +#define V4L2_CTRL_FLAG_UPDATE 0x0008 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CTRL_FLAG_INACTIVE 0x0010 +#define V4L2_CTRL_FLAG_SLIDER 0x0020 +#define V4L2_CTRL_FLAG_WRITE_ONLY 0x0040 +#define V4L2_CTRL_FLAG_VOLATILE 0x0080 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CTRL_FLAG_NEXT_CTRL 0x80000000 +#define V4L2_CID_MAX_CTRLS 1024 +#define V4L2_CID_PRIVATE_BASE 0x08000000 +struct v4l2_tuner { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u32 index; + __u8 name[32]; + __u32 type; + __u32 capability; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u32 rangelow; + __u32 rangehigh; + __u32 rxsubchans; + __u32 audmode; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __s32 signal; + __s32 afc; + __u32 reserved[4]; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct v4l2_modulator { + __u32 index; + __u8 name[32]; + __u32 capability; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u32 rangelow; + __u32 rangehigh; + __u32 txsubchans; + __u32 reserved[4]; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +#define V4L2_TUNER_CAP_LOW 0x0001 +#define V4L2_TUNER_CAP_NORM 0x0002 +#define V4L2_TUNER_CAP_HWSEEK_BOUNDED 0x0004 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_TUNER_CAP_HWSEEK_WRAP 0x0008 +#define V4L2_TUNER_CAP_STEREO 0x0010 +#define V4L2_TUNER_CAP_LANG2 0x0020 +#define V4L2_TUNER_CAP_SAP 0x0020 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_TUNER_CAP_LANG1 0x0040 +#define V4L2_TUNER_CAP_RDS 0x0080 +#define V4L2_TUNER_CAP_RDS_BLOCK_IO 0x0100 +#define V4L2_TUNER_CAP_RDS_CONTROLS 0x0200 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_TUNER_CAP_FREQ_BANDS 0x0400 +#define V4L2_TUNER_CAP_HWSEEK_PROG_LIM 0x0800 +#define V4L2_TUNER_SUB_MONO 0x0001 +#define V4L2_TUNER_SUB_STEREO 0x0002 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_TUNER_SUB_LANG2 0x0004 +#define V4L2_TUNER_SUB_SAP 0x0004 +#define V4L2_TUNER_SUB_LANG1 0x0008 +#define V4L2_TUNER_SUB_RDS 0x0010 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_TUNER_MODE_MONO 0x0000 +#define V4L2_TUNER_MODE_STEREO 0x0001 +#define V4L2_TUNER_MODE_LANG2 0x0002 +#define V4L2_TUNER_MODE_SAP 0x0002 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_TUNER_MODE_LANG1 0x0003 +#define V4L2_TUNER_MODE_LANG1_LANG2 0x0004 +struct v4l2_frequency { + __u32 tuner; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u32 type; + __u32 frequency; + __u32 reserved[8]; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_BAND_MODULATION_VSB (1 << 1) +#define V4L2_BAND_MODULATION_FM (1 << 2) +#define V4L2_BAND_MODULATION_AM (1 << 3) +struct v4l2_frequency_band { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u32 tuner; + __u32 type; + __u32 index; + __u32 capability; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u32 rangelow; + __u32 rangehigh; + __u32 modulation; + __u32 reserved[9]; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +struct v4l2_hw_freq_seek { + __u32 tuner; + __u32 type; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u32 seek_upward; + __u32 wrap_around; + __u32 spacing; + __u32 rangelow; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u32 rangehigh; + __u32 reserved[5]; +}; +struct v4l2_rds_data { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u8 lsb; + __u8 msb; + __u8 block; +} __attribute__ ((packed)); +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_RDS_BLOCK_MSK 0x7 +#define V4L2_RDS_BLOCK_A 0 +#define V4L2_RDS_BLOCK_B 1 +#define V4L2_RDS_BLOCK_C 2 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_RDS_BLOCK_D 3 +#define V4L2_RDS_BLOCK_C_ALT 4 +#define V4L2_RDS_BLOCK_INVALID 7 +#define V4L2_RDS_BLOCK_CORRECTED 0x40 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_RDS_BLOCK_ERROR 0x80 +struct v4l2_audio { + __u32 index; + __u8 name[32]; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u32 capability; + __u32 mode; + __u32 reserved[2]; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_AUDCAP_STEREO 0x00001 +#define V4L2_AUDCAP_AVL 0x00002 +#define V4L2_AUDMODE_AVL 0x00001 +struct v4l2_audioout { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u32 index; + __u8 name[32]; + __u32 capability; + __u32 mode; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u32 reserved[2]; +}; +#define V4L2_ENC_IDX_FRAME_I (0) +#define V4L2_ENC_IDX_FRAME_P (1) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_ENC_IDX_FRAME_B (2) +#define V4L2_ENC_IDX_FRAME_MASK (0xf) +struct v4l2_enc_idx_entry { + __u64 offset; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u64 pts; + __u32 length; + __u32 flags; + __u32 reserved[2]; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +#define V4L2_ENC_IDX_ENTRIES (64) +struct v4l2_enc_idx { + __u32 entries; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u32 entries_cap; + __u32 reserved[4]; + struct v4l2_enc_idx_entry entry[V4L2_ENC_IDX_ENTRIES]; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_ENC_CMD_START (0) +#define V4L2_ENC_CMD_STOP (1) +#define V4L2_ENC_CMD_PAUSE (2) +#define V4L2_ENC_CMD_RESUME (3) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_ENC_QCOM_CMD_FLUSH (4) +#define V4L2_ENC_CMD_STOP_AT_GOP_END (1 << 0) +struct v4l2_encoder_cmd { + __u32 cmd; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u32 flags; + union { + struct { + __u32 data[8]; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + } raw; + }; +}; +#define V4L2_DEC_CMD_START (0) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_DEC_CMD_STOP (1) +#define V4L2_DEC_CMD_PAUSE (2) +#define V4L2_DEC_CMD_RESUME (3) +#define V4L2_DEC_QCOM_CMD_FLUSH (4) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_DEC_CMD_START_MUTE_AUDIO (1 << 0) +#define V4L2_DEC_CMD_PAUSE_TO_BLACK (1 << 0) +#define V4L2_DEC_CMD_STOP_TO_BLACK (1 << 0) +#define V4L2_DEC_CMD_STOP_IMMEDIATELY (1 << 1) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_DEC_QCOM_CMD_FLUSH_OUTPUT (1 << 0) +#define V4L2_DEC_QCOM_CMD_FLUSH_CAPTURE (1 << 1) +#define V4L2_QCOM_CMD_FLUSH_OUTPUT (1 << 0) +#define V4L2_QCOM_CMD_FLUSH_CAPTURE (1 << 1) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_DEC_START_FMT_NONE (0) +#define V4L2_DEC_START_FMT_GOP (1) +struct v4l2_decoder_cmd { + __u32 cmd; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u32 flags; + union { + struct { + __u64 pts; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + } stop; + struct { + __s32 speed; + __u32 format; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + } start; + struct { + __u32 data[16]; + } raw; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + }; +}; +struct v4l2_vbi_format { + __u32 sampling_rate; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u32 offset; + __u32 samples_per_line; + __u32 sample_format; + __s32 start[2]; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u32 count[2]; + __u32 flags; + __u32 reserved[2]; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_VBI_UNSYNC (1 << 0) +#define V4L2_VBI_INTERLACED (1 << 1) +struct v4l2_sliced_vbi_format { + __u16 service_set; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u16 service_lines[2][24]; + __u32 io_size; + __u32 reserved[2]; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_SLICED_TELETEXT_B (0x0001) +#define V4L2_SLICED_VPS (0x0400) +#define V4L2_SLICED_CAPTION_525 (0x1000) +#define V4L2_SLICED_WSS_625 (0x4000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_SLICED_VBI_525 (V4L2_SLICED_CAPTION_525) +#define V4L2_SLICED_VBI_625 (V4L2_SLICED_TELETEXT_B | V4L2_SLICED_VPS | V4L2_SLICED_WSS_625) +struct v4l2_sliced_vbi_cap { + __u16 service_set; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u16 service_lines[2][24]; + __u32 type; + __u32 reserved[3]; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct v4l2_sliced_vbi_data { + __u32 id; + __u32 field; + __u32 line; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u32 reserved; + __u8 data[48]; +}; +#define V4L2_MPEG_VBI_IVTV_TELETEXT_B (1) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_MPEG_VBI_IVTV_CAPTION_525 (4) +#define V4L2_MPEG_VBI_IVTV_WSS_625 (5) +#define V4L2_MPEG_VBI_IVTV_VPS (7) +struct v4l2_mpeg_vbi_itv0_line { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u8 id; + __u8 data[42]; +} __attribute__ ((packed)); +struct v4l2_mpeg_vbi_itv0 { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __le32 linemask[2]; + struct v4l2_mpeg_vbi_itv0_line line[35]; +} __attribute__ ((packed)); +struct v4l2_mpeg_vbi_ITV0 { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + struct v4l2_mpeg_vbi_itv0_line line[36]; +} __attribute__ ((packed)); +#define V4L2_MPEG_VBI_IVTV_MAGIC0 "itv0" +#define V4L2_MPEG_VBI_IVTV_MAGIC1 "ITV0" +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct v4l2_mpeg_vbi_fmt_ivtv { + __u8 magic[4]; + union { + struct v4l2_mpeg_vbi_itv0 itv0; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + struct v4l2_mpeg_vbi_ITV0 ITV0; + }; +} __attribute__ ((packed)); +struct v4l2_plane_pix_format { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u32 sizeimage; + __u16 bytesperline; + __u16 reserved[7]; +} __attribute__ ((packed)); +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct v4l2_pix_format_mplane { + __u32 width; + __u32 height; + __u32 pixelformat; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u32 field; + __u32 colorspace; + struct v4l2_plane_pix_format plane_fmt[VIDEO_MAX_PLANES]; + __u8 num_planes; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u8 reserved[11]; +} __attribute__ ((packed)); +struct v4l2_format { + __u32 type; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + union { + struct v4l2_pix_format pix; + struct v4l2_pix_format_mplane pix_mp; + struct v4l2_window win; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + struct v4l2_vbi_format vbi; + struct v4l2_sliced_vbi_format sliced; + __u8 raw_data[200]; + } fmt; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +struct v4l2_streamparm { + __u32 type; + union { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + struct v4l2_captureparm capture; + struct v4l2_outputparm output; + __u8 raw_data[200]; + } parm; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +#define V4L2_EVENT_ALL 0 +#define V4L2_EVENT_VSYNC 1 +#define V4L2_EVENT_EOS 2 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_EVENT_CTRL 3 +#define V4L2_EVENT_FRAME_SYNC 4 +#define V4L2_EVENT_PRIVATE_START 0x08000000 +#define V4L2_EVENT_MSM_VIDC_START (V4L2_EVENT_PRIVATE_START + 0x00001000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_EVENT_MSM_VIDC_FLUSH_DONE (V4L2_EVENT_MSM_VIDC_START + 1) +#define V4L2_EVENT_MSM_VIDC_PORT_SETTINGS_CHANGED_SUFFICIENT (V4L2_EVENT_MSM_VIDC_START + 2) +#define V4L2_EVENT_MSM_VIDC_PORT_SETTINGS_CHANGED_INSUFFICIENT (V4L2_EVENT_MSM_VIDC_START + 3) +#define V4L2_EVENT_MSM_VIDC_CLOSE_DONE (V4L2_EVENT_MSM_VIDC_START + 4) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_EVENT_MSM_VIDC_SYS_ERROR (V4L2_EVENT_MSM_VIDC_START + 5) +#define V4L2_EVENT_MSM_VIDC_RELEASE_BUFFER_REFERENCE (V4L2_EVENT_MSM_VIDC_START + 6) +#define V4L2_EVENT_MSM_VIDC_RELEASE_UNQUEUED_BUFFER (V4L2_EVENT_MSM_VIDC_START + 7) +#define V4L2_EVENT_MSM_VIDC_HW_OVERLOAD (V4L2_EVENT_MSM_VIDC_START + 8) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_EVENT_MSM_VIDC_MAX_CLIENTS (V4L2_EVENT_MSM_VIDC_START + 9) +#define V4L2_EVENT_MSM_VIDC_HW_UNSUPPORTED (V4L2_EVENT_MSM_VIDC_START + 10) +struct v4l2_event_vsync { + __u8 field; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +} __attribute__ ((packed)); +#define V4L2_EVENT_CTRL_CH_VALUE (1 << 0) +#define V4L2_EVENT_CTRL_CH_FLAGS (1 << 1) +#define V4L2_EVENT_CTRL_CH_RANGE (1 << 2) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct v4l2_event_ctrl { + __u32 changes; + __u32 type; + union { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __s32 value; + __s64 value64; + }; + __u32 flags; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __s32 minimum; + __s32 maximum; + __s32 step; + __s32 default_value; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +struct v4l2_event_frame_sync { + __u32 frame_sequence; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct v4l2_event { + __u32 type; + union { + struct v4l2_event_vsync vsync; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + struct v4l2_event_ctrl ctrl; + struct v4l2_event_frame_sync frame_sync; + __u8 data[64]; + } u; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u32 pending; + __u32 sequence; + struct timespec timestamp; + __u32 id; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u32 reserved[8]; +}; +#define V4L2_EVENT_SUB_FL_SEND_INITIAL (1 << 0) +#define V4L2_EVENT_SUB_FL_ALLOW_FEEDBACK (1 << 1) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct v4l2_event_subscription { + __u32 type; + __u32 id; + __u32 flags; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u32 reserved[5]; +}; +#define V4L2_CHIP_MATCH_BRIDGE 0 +#define V4L2_CHIP_MATCH_HOST V4L2_CHIP_MATCH_BRIDGE +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CHIP_MATCH_I2C_DRIVER 1 +#define V4L2_CHIP_MATCH_I2C_ADDR 2 +#define V4L2_CHIP_MATCH_AC97 3 +#define V4L2_CHIP_MATCH_SUBDEV 4 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct v4l2_dbg_match { + __u32 type; + union { + __u32 addr; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + char name[32]; + }; +} __attribute__ ((packed)); +struct v4l2_dbg_register { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + struct v4l2_dbg_match match; + __u32 size; + __u64 reg; + __u64 val; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +} __attribute__ ((packed)); +struct v4l2_dbg_chip_ident { + struct v4l2_dbg_match match; + __u32 ident; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u32 revision; +} __attribute__ ((packed)); +#define V4L2_CHIP_FL_READABLE (1 << 0) +#define V4L2_CHIP_FL_WRITABLE (1 << 1) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct v4l2_dbg_chip_info { + struct v4l2_dbg_match match; + char name[32]; + __u32 flags; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u32 reserved[32]; +} __attribute__ ((packed)); +struct v4l2_create_buffers { + __u32 index; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u32 count; + __u32 memory; + struct v4l2_format format; + __u32 reserved[8]; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +#define VIDIOC_QUERYCAP _IOR('V', 0, struct v4l2_capability) +#define VIDIOC_RESERVED _IO('V', 1) +#define VIDIOC_ENUM_FMT _IOWR('V', 2, struct v4l2_fmtdesc) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VIDIOC_G_FMT _IOWR('V', 4, struct v4l2_format) +#define VIDIOC_S_FMT _IOWR('V', 5, struct v4l2_format) +#define VIDIOC_REQBUFS _IOWR('V', 8, struct v4l2_requestbuffers) +#define VIDIOC_QUERYBUF _IOWR('V', 9, struct v4l2_buffer) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VIDIOC_G_FBUF _IOR('V', 10, struct v4l2_framebuffer) +#define VIDIOC_S_FBUF _IOW('V', 11, struct v4l2_framebuffer) +#define VIDIOC_OVERLAY _IOW('V', 14, int) +#define VIDIOC_QBUF _IOWR('V', 15, struct v4l2_buffer) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VIDIOC_EXPBUF _IOWR('V', 16, struct v4l2_exportbuffer) +#define VIDIOC_DQBUF _IOWR('V', 17, struct v4l2_buffer) +#define VIDIOC_STREAMON _IOW('V', 18, int) +#define VIDIOC_STREAMOFF _IOW('V', 19, int) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VIDIOC_G_PARM _IOWR('V', 21, struct v4l2_streamparm) +#define VIDIOC_S_PARM _IOWR('V', 22, struct v4l2_streamparm) +#define VIDIOC_G_STD _IOR('V', 23, v4l2_std_id) +#define VIDIOC_S_STD _IOW('V', 24, v4l2_std_id) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VIDIOC_ENUMSTD _IOWR('V', 25, struct v4l2_standard) +#define VIDIOC_ENUMINPUT _IOWR('V', 26, struct v4l2_input) +#define VIDIOC_G_CTRL _IOWR('V', 27, struct v4l2_control) +#define VIDIOC_S_CTRL _IOWR('V', 28, struct v4l2_control) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VIDIOC_G_TUNER _IOWR('V', 29, struct v4l2_tuner) +#define VIDIOC_S_TUNER _IOW('V', 30, struct v4l2_tuner) +#define VIDIOC_G_AUDIO _IOR('V', 33, struct v4l2_audio) +#define VIDIOC_S_AUDIO _IOW('V', 34, struct v4l2_audio) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VIDIOC_QUERYCTRL _IOWR('V', 36, struct v4l2_queryctrl) +#define VIDIOC_QUERYMENU _IOWR('V', 37, struct v4l2_querymenu) +#define VIDIOC_G_INPUT _IOR('V', 38, int) +#define VIDIOC_S_INPUT _IOWR('V', 39, int) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VIDIOC_G_OUTPUT _IOR('V', 46, int) +#define VIDIOC_S_OUTPUT _IOWR('V', 47, int) +#define VIDIOC_ENUMOUTPUT _IOWR('V', 48, struct v4l2_output) +#define VIDIOC_G_AUDOUT _IOR('V', 49, struct v4l2_audioout) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VIDIOC_S_AUDOUT _IOW('V', 50, struct v4l2_audioout) +#define VIDIOC_G_MODULATOR _IOWR('V', 54, struct v4l2_modulator) +#define VIDIOC_S_MODULATOR _IOW('V', 55, struct v4l2_modulator) +#define VIDIOC_G_FREQUENCY _IOWR('V', 56, struct v4l2_frequency) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VIDIOC_S_FREQUENCY _IOW('V', 57, struct v4l2_frequency) +#define VIDIOC_CROPCAP _IOWR('V', 58, struct v4l2_cropcap) +#define VIDIOC_G_CROP _IOWR('V', 59, struct v4l2_crop) +#define VIDIOC_S_CROP _IOW('V', 60, struct v4l2_crop) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VIDIOC_G_JPEGCOMP _IOR('V', 61, struct v4l2_jpegcompression) +#define VIDIOC_S_JPEGCOMP _IOW('V', 62, struct v4l2_jpegcompression) +#define VIDIOC_QUERYSTD _IOR('V', 63, v4l2_std_id) +#define VIDIOC_TRY_FMT _IOWR('V', 64, struct v4l2_format) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VIDIOC_ENUMAUDIO _IOWR('V', 65, struct v4l2_audio) +#define VIDIOC_ENUMAUDOUT _IOWR('V', 66, struct v4l2_audioout) +#define VIDIOC_G_PRIORITY _IOR('V', 67, __u32) +#define VIDIOC_S_PRIORITY _IOW('V', 68, __u32) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VIDIOC_G_SLICED_VBI_CAP _IOWR('V', 69, struct v4l2_sliced_vbi_cap) +#define VIDIOC_LOG_STATUS _IO('V', 70) +#define VIDIOC_G_EXT_CTRLS _IOWR('V', 71, struct v4l2_ext_controls) +#define VIDIOC_S_EXT_CTRLS _IOWR('V', 72, struct v4l2_ext_controls) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VIDIOC_TRY_EXT_CTRLS _IOWR('V', 73, struct v4l2_ext_controls) +#define VIDIOC_ENUM_FRAMESIZES _IOWR('V', 74, struct v4l2_frmsizeenum) +#define VIDIOC_ENUM_FRAMEINTERVALS _IOWR('V', 75, struct v4l2_frmivalenum) +#define VIDIOC_G_ENC_INDEX _IOR('V', 76, struct v4l2_enc_idx) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VIDIOC_ENCODER_CMD _IOWR('V', 77, struct v4l2_encoder_cmd) +#define VIDIOC_TRY_ENCODER_CMD _IOWR('V', 78, struct v4l2_encoder_cmd) +#define VIDIOC_DBG_S_REGISTER _IOW('V', 79, struct v4l2_dbg_register) +#define VIDIOC_DBG_G_REGISTER _IOWR('V', 80, struct v4l2_dbg_register) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VIDIOC_DBG_G_CHIP_IDENT _IOWR('V', 81, struct v4l2_dbg_chip_ident) +#define VIDIOC_S_HW_FREQ_SEEK _IOW('V', 82, struct v4l2_hw_freq_seek) +#define VIDIOC_S_DV_TIMINGS _IOWR('V', 87, struct v4l2_dv_timings) +#define VIDIOC_G_DV_TIMINGS _IOWR('V', 88, struct v4l2_dv_timings) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VIDIOC_DQEVENT _IOR('V', 89, struct v4l2_event) +#define VIDIOC_SUBSCRIBE_EVENT _IOW('V', 90, struct v4l2_event_subscription) +#define VIDIOC_UNSUBSCRIBE_EVENT _IOW('V', 91, struct v4l2_event_subscription) +#define VIDIOC_CREATE_BUFS _IOWR('V', 92, struct v4l2_create_buffers) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VIDIOC_PREPARE_BUF _IOWR('V', 93, struct v4l2_buffer) +#define VIDIOC_G_SELECTION _IOWR('V', 94, struct v4l2_selection) +#define VIDIOC_S_SELECTION _IOWR('V', 95, struct v4l2_selection) +#define VIDIOC_DECODER_CMD _IOWR('V', 96, struct v4l2_decoder_cmd) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VIDIOC_TRY_DECODER_CMD _IOWR('V', 97, struct v4l2_decoder_cmd) +#define VIDIOC_ENUM_DV_TIMINGS _IOWR('V', 98, struct v4l2_enum_dv_timings) +#define VIDIOC_QUERY_DV_TIMINGS _IOR('V', 99, struct v4l2_dv_timings) +#define VIDIOC_DV_TIMINGS_CAP _IOWR('V', 100, struct v4l2_dv_timings_cap) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VIDIOC_ENUM_FREQ_BANDS _IOWR('V', 101, struct v4l2_frequency_band) +#define VIDIOC_DBG_G_CHIP_INFO _IOWR('V', 102, struct v4l2_dbg_chip_info) +#define BASE_VIDIOC_PRIVATE 192 +#endif +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + diff --git a/kernel-headers/media/msm_cam_sensor.h b/kernel-headers/media/msm_cam_sensor.h new file mode 100644 index 0000000..82c2a1e --- /dev/null +++ b/kernel-headers/media/msm_cam_sensor.h @@ -0,0 +1,572 @@ +/**************************************************************************** + **************************************************************************** + *** + *** This header was automatically generated from a Linux kernel header + *** of the same name, to make information necessary for userspace to + *** call into the kernel available to libc. It contains only constants, + *** structures, and macros generated from the original header, and thus, + *** contains no copyrightable information. + *** + *** To edit the content of this header, modify the corresponding + *** source file (e.g. under external/kernel-headers/original/) then + *** run bionic/libc/kernel/tools/update_all.py + *** + *** Any manual change here will be lost the next time this script will + *** be run. You've been warned! + *** + **************************************************************************** + ****************************************************************************/ +#ifndef __LINUX_MSM_CAM_SENSOR_H +#define __LINUX_MSM_CAM_SENSOR_H +#ifdef MSM_CAMERA_BIONIC +#include <sys/types.h> +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#endif +#include <media/msm_camsensor_sdk.h> +#include <linux/types.h> +#include <linux/i2c.h> +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define I2C_SEQ_REG_SETTING_MAX 5 +#define MSM_SENSOR_MCLK_8HZ 8000000 +#define MSM_SENSOR_MCLK_16HZ 16000000 +#define MSM_SENSOR_MCLK_24HZ 24000000 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define MAX_SENSOR_NAME 32 +#define MAX_ACTUATOR_AF_TOTAL_STEPS 1024 +#define MAX_OIS_MOD_NAME_SIZE 32 +#define MAX_OIS_NAME_SIZE 32 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define MAX_OIS_REG_SETTINGS 800 +#define MOVE_NEAR 0 +#define MOVE_FAR 1 +#define MSM_ACTUATOR_MOVE_SIGNED_FAR -1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define MSM_ACTUATOR_MOVE_SIGNED_NEAR 1 +#define MAX_EEPROM_NAME 32 +#define MAX_AF_ITERATIONS 3 +#define MAX_NUMBER_OF_STEPS 47 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +enum flash_type { + LED_FLASH = 1, + STROBE_FLASH, + GPIO_FLASH +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +enum msm_sensor_resolution_t { + MSM_SENSOR_RES_FULL, + MSM_SENSOR_RES_QTR, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + MSM_SENSOR_RES_2, + MSM_SENSOR_RES_3, + MSM_SENSOR_RES_4, + MSM_SENSOR_RES_5, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + MSM_SENSOR_RES_6, + MSM_SENSOR_RES_7, + MSM_SENSOR_INVALID_RES, +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +enum msm_camera_stream_type_t { + MSM_CAMERA_STREAM_PREVIEW, + MSM_CAMERA_STREAM_SNAPSHOT, + MSM_CAMERA_STREAM_VIDEO, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + MSM_CAMERA_STREAM_INVALID, +}; +enum sensor_sub_module_t { + SUB_MODULE_SENSOR, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + SUB_MODULE_CHROMATIX, + SUB_MODULE_ACTUATOR, + SUB_MODULE_EEPROM, + SUB_MODULE_LED_FLASH, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + SUB_MODULE_STROBE_FLASH, + SUB_MODULE_CSID, + SUB_MODULE_CSID_3D, + SUB_MODULE_CSIPHY, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + SUB_MODULE_CSIPHY_3D, + SUB_MODULE_OIS, + SUB_MODULE_MAX, +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +enum { + MSM_CAMERA_EFFECT_MODE_OFF, + MSM_CAMERA_EFFECT_MODE_MONO, + MSM_CAMERA_EFFECT_MODE_NEGATIVE, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + MSM_CAMERA_EFFECT_MODE_SOLARIZE, + MSM_CAMERA_EFFECT_MODE_SEPIA, + MSM_CAMERA_EFFECT_MODE_POSTERIZE, + MSM_CAMERA_EFFECT_MODE_WHITEBOARD, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + MSM_CAMERA_EFFECT_MODE_BLACKBOARD, + MSM_CAMERA_EFFECT_MODE_AQUA, + MSM_CAMERA_EFFECT_MODE_EMBOSS, + MSM_CAMERA_EFFECT_MODE_SKETCH, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + MSM_CAMERA_EFFECT_MODE_NEON, + MSM_CAMERA_EFFECT_MODE_MAX +}; +enum { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + MSM_CAMERA_WB_MODE_AUTO, + MSM_CAMERA_WB_MODE_CUSTOM, + MSM_CAMERA_WB_MODE_INCANDESCENT, + MSM_CAMERA_WB_MODE_FLUORESCENT, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + MSM_CAMERA_WB_MODE_WARM_FLUORESCENT, + MSM_CAMERA_WB_MODE_DAYLIGHT, + MSM_CAMERA_WB_MODE_CLOUDY_DAYLIGHT, + MSM_CAMERA_WB_MODE_TWILIGHT, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + MSM_CAMERA_WB_MODE_SHADE, + MSM_CAMERA_WB_MODE_OFF, + MSM_CAMERA_WB_MODE_MAX +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +enum { + MSM_CAMERA_SCENE_MODE_OFF, + MSM_CAMERA_SCENE_MODE_AUTO, + MSM_CAMERA_SCENE_MODE_LANDSCAPE, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + MSM_CAMERA_SCENE_MODE_SNOW, + MSM_CAMERA_SCENE_MODE_BEACH, + MSM_CAMERA_SCENE_MODE_SUNSET, + MSM_CAMERA_SCENE_MODE_NIGHT, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + MSM_CAMERA_SCENE_MODE_PORTRAIT, + MSM_CAMERA_SCENE_MODE_BACKLIGHT, + MSM_CAMERA_SCENE_MODE_SPORTS, + MSM_CAMERA_SCENE_MODE_ANTISHAKE, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + MSM_CAMERA_SCENE_MODE_FLOWERS, + MSM_CAMERA_SCENE_MODE_CANDLELIGHT, + MSM_CAMERA_SCENE_MODE_FIREWORKS, + MSM_CAMERA_SCENE_MODE_PARTY, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + MSM_CAMERA_SCENE_MODE_NIGHT_PORTRAIT, + MSM_CAMERA_SCENE_MODE_THEATRE, + MSM_CAMERA_SCENE_MODE_ACTION, + MSM_CAMERA_SCENE_MODE_AR, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + MSM_CAMERA_SCENE_MODE_FACE_PRIORITY, + MSM_CAMERA_SCENE_MODE_BARCODE, + MSM_CAMERA_SCENE_MODE_HDR, + MSM_CAMERA_SCENE_MODE_MAX +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +enum csid_cfg_type_t { + CSID_INIT, + CSID_CFG, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + CSID_RELEASE, +}; +enum csiphy_cfg_type_t { + CSIPHY_INIT, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + CSIPHY_CFG, + CSIPHY_RELEASE, +}; +enum camera_vreg_type { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + VREG_TYPE_DEFAULT, + VREG_TYPE_CUSTOM, +}; +enum sensor_af_t { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + SENSOR_AF_FOCUSSED, + SENSOR_AF_NOT_FOCUSSED, +}; +enum cci_i2c_master_t { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + MASTER_0, + MASTER_1, + MASTER_MAX, +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct msm_camera_i2c_array_write_config { + struct msm_camera_i2c_reg_setting conf_array; + uint16_t slave_addr; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct msm_camera_i2c_read_config { + uint16_t slave_addr; + uint16_t reg_addr; + enum msm_camera_i2c_data_type data_type; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint16_t data; +}; +struct msm_camera_csi2_params { + struct msm_camera_csid_params csid_params; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + struct msm_camera_csiphy_params csiphy_params; + uint8_t csi_clk_scale_enable; +}; +struct msm_camera_csi_lane_params { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint16_t csi_lane_assign; + uint16_t csi_lane_mask; +}; +struct csi_lane_params_t { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint16_t csi_lane_assign; + uint8_t csi_lane_mask; + uint8_t csi_if; + int8_t csid_core[2]; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint8_t csi_phy_sel; +}; +struct msm_sensor_info_t { + char sensor_name[MAX_SENSOR_NAME]; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t session_id; + int32_t subdev_id[SUB_MODULE_MAX]; + int32_t subdev_intf[SUB_MODULE_MAX]; + uint8_t is_mount_angle_valid; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t sensor_mount_angle; + int modes_supported; + enum camb_position_t position; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct camera_vreg_t { + const char *reg_name; + int min_voltage; + int max_voltage; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + int op_mode; + uint32_t delay; + const char *custom_vreg_name; + enum camera_vreg_type type; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +struct sensorb_cfg_data { + int cfgtype; + union { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + struct msm_sensor_info_t sensor_info; + struct msm_sensor_init_params sensor_init_params; + void *setting; + } cfg; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +struct csid_cfg_data { + enum csid_cfg_type_t cfgtype; + union { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t csid_version; + struct msm_camera_csid_params *csid_params; + } cfg; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct csiphy_cfg_data { + enum csiphy_cfg_type_t cfgtype; + union { + struct msm_camera_csiphy_params *csiphy_params; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + struct msm_camera_csi_lane_params *csi_lane_params; + } cfg; +}; +enum eeprom_cfg_type_t { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + CFG_EEPROM_GET_INFO, + CFG_EEPROM_GET_CAL_DATA, + CFG_EEPROM_READ_CAL_DATA, + CFG_EEPROM_WRITE_DATA, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + CFG_EEPROM_GET_MM_INFO, +}; +struct eeprom_get_t { + uint32_t num_bytes; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +struct eeprom_read_t { + uint8_t *dbuffer; + uint32_t num_bytes; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +struct eeprom_write_t { + uint8_t *dbuffer; + uint32_t num_bytes; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +struct eeprom_get_cmm_t { + uint32_t cmm_support; + uint32_t cmm_compression; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t cmm_size; +}; +struct msm_eeprom_cfg_data { + enum eeprom_cfg_type_t cfgtype; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint8_t is_supported; + union { + char eeprom_name[MAX_SENSOR_NAME]; + struct eeprom_get_t get_data; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + struct eeprom_read_t read_data; + struct eeprom_write_t write_data; + struct eeprom_get_cmm_t get_cmm_data; + } cfg; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +enum msm_sensor_cfg_type_t { + CFG_SET_SLAVE_INFO, + CFG_SLAVE_READ_I2C, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + CFG_WRITE_I2C_ARRAY, + CFG_SLAVE_WRITE_I2C_ARRAY, + CFG_WRITE_I2C_SEQ_ARRAY, + CFG_POWER_UP, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + CFG_POWER_DOWN, + CFG_SET_STOP_STREAM_SETTING, + CFG_GET_SENSOR_INFO, + CFG_GET_SENSOR_INIT_PARAMS, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + CFG_SET_INIT_SETTING, + CFG_SET_RESOLUTION, + CFG_SET_STOP_STREAM, + CFG_SET_START_STREAM, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + CFG_SET_SATURATION, + CFG_SET_CONTRAST, + CFG_SET_SHARPNESS, + CFG_SET_ISO, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + CFG_SET_EXPOSURE_COMPENSATION, + CFG_SET_ANTIBANDING, + CFG_SET_BESTSHOT_MODE, + CFG_SET_EFFECT, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + CFG_SET_WHITE_BALANCE, + CFG_SET_AUTOFOCUS, + CFG_CANCEL_AUTOFOCUS, + CFG_SET_STREAM_TYPE, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +enum msm_actuator_cfg_type_t { + CFG_GET_ACTUATOR_INFO, + CFG_SET_ACTUATOR_INFO, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + CFG_SET_DEFAULT_FOCUS, + CFG_MOVE_FOCUS, + CFG_SET_POSITION, + CFG_ACTUATOR_POWERDOWN, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + CFG_ACTUATOR_POWERUP, + CFG_ACTUATOR_INIT, +}; +enum msm_ois_cfg_type_t { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + CFG_OIS_INIT, + CFG_OIS_POWERDOWN, + CFG_OIS_POWERUP, + CFG_OIS_CONTROL, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + CFG_OIS_I2C_WRITE_SEQ_TABLE, +}; +enum msm_ois_i2c_operation { + MSM_OIS_WRITE = 0, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + MSM_OIS_POLL, +}; +struct reg_settings_ois_t { + uint16_t reg_addr; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + enum msm_camera_i2c_reg_addr_type addr_type; + uint32_t reg_data; + enum msm_camera_i2c_data_type data_type; + enum msm_ois_i2c_operation i2c_operation; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t delay; +}; +struct msm_ois_params_t { + uint16_t data_size; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint16_t setting_size; + uint32_t i2c_addr; + enum msm_camera_i2c_reg_addr_type i2c_addr_type; + enum msm_camera_i2c_data_type i2c_data_type; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + struct reg_settings_ois_t *settings; +}; +struct msm_ois_set_info_t { + struct msm_ois_params_t ois_params; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +struct msm_actuator_move_params_t { + int8_t dir; + int8_t sign_dir; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + int16_t dest_step_pos; + int32_t num_steps; + uint16_t curr_lens_pos; + struct damping_params_t *ringing_params; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +struct msm_actuator_tuning_params_t { + int16_t initial_code; + uint16_t pwd_step; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint16_t region_size; + uint32_t total_steps; + struct region_params_t *region_params; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct park_lens_data_t { + uint32_t damping_step; + uint32_t damping_delay; + uint32_t hw_params; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t max_step; +}; +struct msm_actuator_params_t { + enum actuator_type act_type; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint8_t reg_tbl_size; + uint16_t data_size; + uint16_t init_setting_size; + uint32_t i2c_addr; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + enum msm_actuator_addr_type i2c_addr_type; + enum msm_actuator_data_type i2c_data_type; + struct msm_actuator_reg_params_t *reg_tbl_params; + struct reg_settings_t *init_settings; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + struct park_lens_data_t park_lens; +}; +struct msm_actuator_set_info_t { + struct msm_actuator_params_t actuator_params; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + struct msm_actuator_tuning_params_t af_tuning_params; +}; +struct msm_actuator_get_info_t { + uint32_t focal_length_num; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t focal_length_den; + uint32_t f_number_num; + uint32_t f_number_den; + uint32_t f_pix_num; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t f_pix_den; + uint32_t total_f_dist_num; + uint32_t total_f_dist_den; + uint32_t hor_view_angle_num; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t hor_view_angle_den; + uint32_t ver_view_angle_num; + uint32_t ver_view_angle_den; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +enum af_camera_name { + ACTUATOR_MAIN_CAM_0, + ACTUATOR_MAIN_CAM_1, + ACTUATOR_MAIN_CAM_2, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + ACTUATOR_MAIN_CAM_3, + ACTUATOR_MAIN_CAM_4, + ACTUATOR_MAIN_CAM_5, + ACTUATOR_WEB_CAM_0, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + ACTUATOR_WEB_CAM_1, + ACTUATOR_WEB_CAM_2, +}; +struct msm_ois_cfg_data { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + int cfgtype; + union { + struct msm_ois_set_info_t set_info; + struct msm_camera_i2c_seq_reg_setting *settings; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + } cfg; +}; +struct msm_actuator_set_position_t { + uint16_t number_of_steps; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint16_t pos[MAX_NUMBER_OF_STEPS]; + uint16_t delay[MAX_NUMBER_OF_STEPS]; +}; +struct msm_actuator_cfg_data { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + int cfgtype; + uint8_t is_af_supported; + union { + struct msm_actuator_move_params_t move; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + struct msm_actuator_set_info_t set_info; + struct msm_actuator_get_info_t get_info; + struct msm_actuator_set_position_t setpos; + enum af_camera_name cam_name; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + } cfg; +}; +enum msm_camera_led_config_t { + MSM_CAMERA_LED_OFF, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + MSM_CAMERA_LED_LOW, + MSM_CAMERA_LED_HIGH, + MSM_CAMERA_LED_INIT, + MSM_CAMERA_LED_RELEASE, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +struct msm_camera_led_cfg_t { + enum msm_camera_led_config_t cfgtype; + int32_t torch_current[MAX_LED_TRIGGERS]; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + int32_t flash_current[MAX_LED_TRIGGERS]; + int32_t flash_duration[MAX_LED_TRIGGERS]; +}; +struct msm_flash_init_info_t { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + enum msm_flash_driver_type flash_driver_type; + struct msm_sensor_power_setting_array *power_setting_array; + struct msm_camera_i2c_reg_setting_array *settings; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct msm_flash_cfg_data_t { + enum msm_flash_cfg_type_t cfg_type; + int32_t flash_current[MAX_LED_TRIGGERS]; + int32_t flash_duration[MAX_LED_TRIGGERS]; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + union { + struct msm_flash_init_info_t *flash_init_info; + struct msm_camera_i2c_reg_setting_array *settings; + } cfg; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +enum msm_sensor_init_cfg_type_t { + CFG_SINIT_PROBE, + CFG_SINIT_PROBE_DONE, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + CFG_SINIT_PROBE_WAIT_DONE, +}; +struct sensor_init_cfg_data { + enum msm_sensor_init_cfg_type_t cfgtype; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + struct msm_sensor_info_t probed_info; + char entity_name[MAX_SENSOR_NAME]; + union { + void *setting; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + } cfg; +}; +#define VIDIOC_MSM_SENSOR_CFG _IOWR('V', BASE_VIDIOC_PRIVATE + 1, struct sensorb_cfg_data) +#define VIDIOC_MSM_SENSOR_RELEASE _IO('V', BASE_VIDIOC_PRIVATE + 2) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VIDIOC_MSM_SENSOR_GET_SUBDEV_ID _IOWR('V', BASE_VIDIOC_PRIVATE + 3, uint32_t) +#define VIDIOC_MSM_CSIPHY_IO_CFG _IOWR('V', BASE_VIDIOC_PRIVATE + 4, struct csiphy_cfg_data) +#define VIDIOC_MSM_CSID_IO_CFG _IOWR('V', BASE_VIDIOC_PRIVATE + 5, struct csid_cfg_data) +#define VIDIOC_MSM_ACTUATOR_CFG _IOWR('V', BASE_VIDIOC_PRIVATE + 6, struct msm_actuator_cfg_data) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VIDIOC_MSM_FLASH_LED_DATA_CFG _IOWR('V', BASE_VIDIOC_PRIVATE + 7, struct msm_camera_led_cfg_t) +#define VIDIOC_MSM_EEPROM_CFG _IOWR('V', BASE_VIDIOC_PRIVATE + 8, struct msm_eeprom_cfg_data) +#define VIDIOC_MSM_SENSOR_GET_AF_STATUS _IOWR('V', BASE_VIDIOC_PRIVATE + 9, uint32_t) +#define VIDIOC_MSM_SENSOR_INIT_CFG _IOWR('V', BASE_VIDIOC_PRIVATE + 10, struct sensor_init_cfg_data) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VIDIOC_MSM_OIS_CFG _IOWR('V', BASE_VIDIOC_PRIVATE + 11, struct msm_ois_cfg_data) +#define VIDIOC_MSM_FLASH_CFG _IOWR('V', BASE_VIDIOC_PRIVATE + 13, struct msm_flash_cfg_data_t) +#endif + diff --git a/kernel-headers/media/msm_camsensor_sdk.h b/kernel-headers/media/msm_camsensor_sdk.h new file mode 100644 index 0000000..2fb2d5b --- /dev/null +++ b/kernel-headers/media/msm_camsensor_sdk.h @@ -0,0 +1,369 @@ +/**************************************************************************** + **************************************************************************** + *** + *** This header was automatically generated from a Linux kernel header + *** of the same name, to make information necessary for userspace to + *** call into the kernel available to libc. It contains only constants, + *** structures, and macros generated from the original header, and thus, + *** contains no copyrightable information. + *** + *** To edit the content of this header, modify the corresponding + *** source file (e.g. under external/kernel-headers/original/) then + *** run bionic/libc/kernel/tools/update_all.py + *** + *** Any manual change here will be lost the next time this script will + *** be run. You've been warned! + *** + **************************************************************************** + ****************************************************************************/ +#ifndef __LINUX_MSM_CAMSENSOR_SDK_H +#define __LINUX_MSM_CAMSENSOR_SDK_H +#include <linux/v4l2-mediabus.h> +#define KVERSION 0x1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define MAX_POWER_CONFIG 12 +#define GPIO_OUT_LOW (0 << 1) +#define GPIO_OUT_HIGH (1 << 1) +#define CSI_EMBED_DATA 0x12 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define CSI_RESERVED_DATA_0 0x13 +#define CSI_YUV422_8 0x1E +#define CSI_RAW8 0x2A +#define CSI_RAW10 0x2B +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define CSI_RAW12 0x2C +#define CSI_DECODE_6BIT 0 +#define CSI_DECODE_8BIT 1 +#define CSI_DECODE_10BIT 2 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define CSI_DECODE_DPCM_10_8_10 5 +#define MAX_CID 16 +#define I2C_SEQ_REG_DATA_MAX 256 +#define MSM_V4L2_PIX_FMT_META v4l2_fourcc('M', 'E', 'T', 'A') +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define MSM_V4L2_PIX_FMT_SBGGR14 v4l2_fourcc('B', 'G', '1', '4') +#define MSM_V4L2_PIX_FMT_SGBRG14 v4l2_fourcc('G', 'B', '1', '4') +#define MSM_V4L2_PIX_FMT_SGRBG14 v4l2_fourcc('B', 'A', '1', '4') +#define MSM_V4L2_PIX_FMT_SRGGB14 v4l2_fourcc('R', 'G', '1', '4') +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define MAX_ACTUATOR_REG_TBL_SIZE 8 +#define MAX_ACTUATOR_REGION 5 +#define NUM_ACTUATOR_DIR 2 +#define MAX_ACTUATOR_SCENARIO 8 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define MAX_ACT_MOD_NAME_SIZE 32 +#define MAX_ACT_NAME_SIZE 32 +#define MAX_ACTUATOR_INIT_SET 120 +#define MAX_I2C_REG_SET 12 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define MAX_NAME_SIZE 32 +#define MAX_LED_TRIGGERS 3 +enum msm_sensor_camera_id_t { + CAMERA_0, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + CAMERA_1, + CAMERA_2, + CAMERA_3, + MAX_CAMERAS, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +enum i2c_freq_mode_t { + I2C_STANDARD_MODE, + I2C_FAST_MODE, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + I2C_CUSTOM_MODE, + I2C_FAST_PLUS_MODE, + I2C_MAX_MODES, +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +enum camb_position_t { + BACK_CAMERA_B, + FRONT_CAMERA_B, + INVALID_CAMERA_B, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +enum msm_sensor_power_seq_type_t { + SENSOR_CLK, + SENSOR_GPIO, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + SENSOR_VREG, + SENSOR_I2C_MUX, + SENSOR_I2C, +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +enum msm_camera_i2c_reg_addr_type { + MSM_CAMERA_I2C_BYTE_ADDR = 1, + MSM_CAMERA_I2C_WORD_ADDR, + MSM_CAMERA_I2C_3B_ADDR, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + MSM_CAMERA_I2C_ADDR_TYPE_MAX, +}; +enum msm_camera_i2c_data_type { + MSM_CAMERA_I2C_BYTE_DATA = 1, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + MSM_CAMERA_I2C_WORD_DATA, + MSM_CAMERA_I2C_DWORD_DATA, + MSM_CAMERA_I2C_SET_BYTE_MASK, + MSM_CAMERA_I2C_UNSET_BYTE_MASK, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + MSM_CAMERA_I2C_SET_WORD_MASK, + MSM_CAMERA_I2C_UNSET_WORD_MASK, + MSM_CAMERA_I2C_SET_BYTE_WRITE_MASK_DATA, + MSM_CAMERA_I2C_DATA_TYPE_MAX, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +enum msm_sensor_power_seq_gpio_t { + SENSOR_GPIO_RESET, + SENSOR_GPIO_STANDBY, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + SENSOR_GPIO_AF_PWDM, + SENSOR_GPIO_VIO, + SENSOR_GPIO_VANA, + SENSOR_GPIO_VDIG, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + SENSOR_GPIO_VAF, + SENSOR_GPIO_FL_EN, + SENSOR_GPIO_FL_NOW, + SENSOR_GPIO_FL_RESET, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + SENSOR_GPIO_CUSTOM1, + SENSOR_GPIO_CUSTOM2, + SENSOR_GPIO_MAX, +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +enum msm_camera_vreg_name_t { + CAM_VDIG, + CAM_VIO, + CAM_VANA, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + CAM_VAF, + CAM_V_CUSTOM1, + CAM_V_CUSTOM2, + CAM_VREG_MAX, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +enum msm_sensor_clk_type_t { + SENSOR_CAM_MCLK, + SENSOR_CAM_CLK, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + SENSOR_CAM_CLK_MAX, +}; +enum camerab_mode_t { + CAMERA_MODE_2D_B = (1<<0), +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + CAMERA_MODE_3D_B = (1<<1), + CAMERA_MODE_INVALID = (1<<2), +}; +enum sensor_stats_type { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + YRGB, + YYYY, +}; +enum msm_actuator_data_type { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + MSM_ACTUATOR_BYTE_DATA = 1, + MSM_ACTUATOR_WORD_DATA, +}; +enum msm_actuator_addr_type { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + MSM_ACTUATOR_BYTE_ADDR = 1, + MSM_ACTUATOR_WORD_ADDR, +}; +enum msm_actuator_write_type { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + MSM_ACTUATOR_WRITE_HW_DAMP, + MSM_ACTUATOR_WRITE_DAC, + MSM_ACTUATOR_WRITE, + MSM_ACTUATOR_WRITE_DIR_REG, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + MSM_ACTUATOR_POLL, + MSM_ACTUATOR_READ_WRITE, +}; +enum msm_actuator_i2c_operation { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + MSM_ACT_WRITE = 0, + MSM_ACT_POLL, +}; +enum actuator_type { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + ACTUATOR_VCM, + ACTUATOR_PIEZO, + ACTUATOR_HVCM, + ACTUATOR_BIVCM, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +enum msm_flash_driver_type { + FLASH_DRIVER_PMIC, + FLASH_DRIVER_I2C, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + FLASH_DRIVER_GPIO, + FLASH_DRIVER_DEFAULT +}; +enum msm_flash_cfg_type_t { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + CFG_FLASH_INIT, + CFG_FLASH_RELEASE, + CFG_FLASH_OFF, + CFG_FLASH_LOW, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + CFG_FLASH_HIGH, +}; +struct msm_sensor_power_setting { + enum msm_sensor_power_seq_type_t seq_type; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint16_t seq_val; + long config_val; + uint16_t delay; + void *data[10]; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +struct msm_sensor_power_setting_array { + struct msm_sensor_power_setting power_setting_a[MAX_POWER_CONFIG]; + struct msm_sensor_power_setting *power_setting; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint16_t size; + struct msm_sensor_power_setting power_down_setting_a[MAX_POWER_CONFIG]; + struct msm_sensor_power_setting *power_down_setting; + uint16_t size_down; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +struct msm_sensor_init_params { + int modes_supported; + enum camb_position_t position; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t sensor_mount_angle; +}; +struct msm_sensor_id_info_t { + uint16_t sensor_id_reg_addr; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint16_t sensor_id; + uint16_t sensor_id_mask; +}; +struct msm_camera_sensor_slave_info { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + char sensor_name[32]; + char eeprom_name[32]; + char actuator_name[32]; + char ois_name[32]; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + char flash_name[32]; + enum msm_sensor_camera_id_t camera_id; + uint16_t slave_addr; + enum i2c_freq_mode_t i2c_freq_mode; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + enum msm_camera_i2c_reg_addr_type addr_type; + struct msm_sensor_id_info_t sensor_id_info; + struct msm_sensor_power_setting_array power_setting_array; + uint8_t is_init_params_valid; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + struct msm_sensor_init_params sensor_init_params; + uint8_t is_flash_supported; +}; +struct msm_camera_i2c_reg_array { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint16_t reg_addr; + uint16_t reg_data; + uint32_t delay; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct msm_camera_i2c_reg_setting { + struct msm_camera_i2c_reg_array *reg_setting; + uint16_t size; + enum msm_camera_i2c_reg_addr_type addr_type; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + enum msm_camera_i2c_data_type data_type; + uint16_t delay; +}; +struct msm_camera_csid_vc_cfg { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint8_t cid; + uint8_t dt; + uint8_t decode_format; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct msm_camera_csid_lut_params { + uint8_t num_cid; + struct msm_camera_csid_vc_cfg vc_cfg_a[MAX_CID]; + struct msm_camera_csid_vc_cfg *vc_cfg[MAX_CID]; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +struct msm_camera_csid_params { + uint8_t lane_cnt; + uint16_t lane_assign; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint8_t phy_sel; + uint32_t csi_clk; + struct msm_camera_csid_lut_params lut_params; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct msm_camera_csiphy_params { + uint8_t lane_cnt; + uint8_t settle_cnt; + uint16_t lane_mask; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint8_t combo_mode; + uint8_t csid_core; + uint32_t csiphy_clk; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct msm_camera_i2c_seq_reg_array { + uint16_t reg_addr; + uint8_t reg_data[I2C_SEQ_REG_DATA_MAX]; + uint16_t reg_data_size; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +struct msm_camera_i2c_seq_reg_setting { + struct msm_camera_i2c_seq_reg_array *reg_setting; + uint16_t size; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + enum msm_camera_i2c_reg_addr_type addr_type; + uint16_t delay; +}; +struct msm_actuator_reg_params_t { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + enum msm_actuator_write_type reg_write_type; + uint32_t hw_mask; + uint16_t reg_addr; + uint16_t hw_shift; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint16_t data_shift; + uint16_t data_type; + uint16_t addr_type; + uint16_t reg_data; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint16_t delay; +}; +struct damping_params_t { + uint32_t damping_step; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t damping_delay; + uint32_t hw_params; +}; +struct region_params_t { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint16_t step_bound[2]; + uint16_t code_per_step; + uint32_t qvalue; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct reg_settings_t { + uint16_t reg_addr; + enum msm_actuator_addr_type addr_type; + uint16_t reg_data; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + enum msm_actuator_data_type data_type; + enum msm_actuator_i2c_operation i2c_operation; + uint32_t delay; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct msm_camera_i2c_reg_setting_array { + struct msm_camera_i2c_reg_array reg_setting_a[MAX_I2C_REG_SET]; + uint16_t size; + enum msm_camera_i2c_reg_addr_type addr_type; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + enum msm_camera_i2c_data_type data_type; + uint16_t delay; +}; +#endif +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + diff --git a/kernel-headers/media/msm_fd.h b/kernel-headers/media/msm_fd.h new file mode 100644 index 0000000..9fb53c1 --- /dev/null +++ b/kernel-headers/media/msm_fd.h @@ -0,0 +1,65 @@ +/**************************************************************************** + **************************************************************************** + *** + *** This header was automatically generated from a Linux kernel header + *** of the same name, to make information necessary for userspace to + *** call into the kernel available to libc. It contains only constants, + *** structures, and macros generated from the original header, and thus, + *** contains no copyrightable information. + *** + *** To edit the content of this header, modify the corresponding + *** source file (e.g. under external/kernel-headers/original/) then + *** run bionic/libc/kernel/tools/update_all.py + *** + *** Any manual change here will be lost the next time this script will + *** be run. You've been warned! + *** + **************************************************************************** + ****************************************************************************/ +#ifndef __UAPI_MSM_FD__ +#define __UAPI_MSM_FD__ +#include <linux/videodev2.h> +struct msm_fd_event { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u32 buf_index; + __u32 frame_id; + __u32 face_cnt; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +enum msm_fd_pose { + MSM_FD_POSE_FRONT, + MSM_FD_POSE_RIGHT_DIAGONAL, + MSM_FD_POSE_RIGHT, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + MSM_FD_POSE_LEFT_DIAGONAL, + MSM_FD_POSE_LEFT, +}; +struct msm_fd_face_data { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u32 pose; + __u32 angle; + __u32 confidence; + __u32 reserved; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + struct v4l2_rect face; +}; +struct msm_fd_result { + __u32 frame_id; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u32 face_cnt; + struct msm_fd_face_data __user *face_data; +}; +#define VIDIOC_MSM_FD_GET_RESULT _IOWR('V', BASE_VIDIOC_PRIVATE, struct msm_fd_result) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define MSM_EVENT_FD (V4L2_EVENT_PRIVATE_START) +#define V4L2_CID_FD_SPEED (V4L2_CID_PRIVATE_BASE) +#define V4L2_CID_FD_FACE_ANGLE (V4L2_CID_PRIVATE_BASE + 1) +#define V4L2_CID_FD_MIN_FACE_SIZE (V4L2_CID_PRIVATE_BASE + 2) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_CID_FD_FACE_DIRECTION (V4L2_CID_PRIVATE_BASE + 3) +#define V4L2_CID_FD_DETECTION_THRESHOLD (V4L2_CID_PRIVATE_BASE + 4) +#define V4L2_CID_FD_WORK_MEMORY_SIZE (V4L2_CID_PRIVATE_BASE + 5) +#define V4L2_CID_FD_WORK_MEMORY_FD (V4L2_CID_PRIVATE_BASE + 6) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#endif + diff --git a/kernel-headers/media/msm_isp.h b/kernel-headers/media/msm_isp.h new file mode 100644 index 0000000..4ed2ce0 --- /dev/null +++ b/kernel-headers/media/msm_isp.h @@ -0,0 +1,412 @@ +/**************************************************************************** + **************************************************************************** + *** + *** This header was automatically generated from a Linux kernel header + *** of the same name, to make information necessary for userspace to + *** call into the kernel available to libc. It contains only constants, + *** structures, and macros generated from the original header, and thus, + *** contains no copyrightable information. + *** + *** To edit the content of this header, modify the corresponding + *** source file (e.g. under external/kernel-headers/original/) then + *** run bionic/libc/kernel/tools/update_all.py + *** + *** Any manual change here will be lost the next time this script will + *** be run. You've been warned! + *** + **************************************************************************** + ****************************************************************************/ +#ifndef __UAPI_MSM_ISP_H__ +#define __UAPI_MSM_ISP_H__ +#define BIT(nr) (1UL << (nr)) +#define MSG_ID_RESET_ACK 0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define MSG_ID_START_ACK 1 +#define MSG_ID_STOP_ACK 2 +#define MSG_ID_UPDATE_ACK 3 +#define MSG_ID_OUTPUT_P 4 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define MSG_ID_OUTPUT_T 5 +#define MSG_ID_OUTPUT_S 6 +#define MSG_ID_OUTPUT_V 7 +#define MSG_ID_SNAPSHOT_DONE 8 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define MSG_ID_STATS_AEC 9 +#define MSG_ID_STATS_AF 10 +#define MSG_ID_STATS_AWB 11 +#define MSG_ID_STATS_RS 12 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define MSG_ID_STATS_CS 13 +#define MSG_ID_STATS_IHIST 14 +#define MSG_ID_STATS_SKIN 15 +#define MSG_ID_EPOCH1 16 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define MSG_ID_EPOCH2 17 +#define MSG_ID_SYNC_TIMER0_DONE 18 +#define MSG_ID_SYNC_TIMER1_DONE 19 +#define MSG_ID_SYNC_TIMER2_DONE 20 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define MSG_ID_ASYNC_TIMER0_DONE 21 +#define MSG_ID_ASYNC_TIMER1_DONE 22 +#define MSG_ID_ASYNC_TIMER2_DONE 23 +#define MSG_ID_ASYNC_TIMER3_DONE 24 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define MSG_ID_AE_OVERFLOW 25 +#define MSG_ID_AF_OVERFLOW 26 +#define MSG_ID_AWB_OVERFLOW 27 +#define MSG_ID_RS_OVERFLOW 28 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define MSG_ID_CS_OVERFLOW 29 +#define MSG_ID_IHIST_OVERFLOW 30 +#define MSG_ID_SKIN_OVERFLOW 31 +#define MSG_ID_AXI_ERROR 32 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define MSG_ID_CAMIF_OVERFLOW 33 +#define MSG_ID_VIOLATION 34 +#define MSG_ID_CAMIF_ERROR 35 +#define MSG_ID_BUS_OVERFLOW 36 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define MSG_ID_SOF_ACK 37 +#define MSG_ID_STOP_REC_ACK 38 +#define MSG_ID_STATS_AWB_AEC 39 +#define MSG_ID_OUTPUT_PRIMARY 40 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define MSG_ID_OUTPUT_SECONDARY 41 +#define MSG_ID_STATS_COMPOSITE 42 +#define MSG_ID_OUTPUT_TERTIARY1 43 +#define MSG_ID_STOP_LS_ACK 44 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define MSG_ID_OUTPUT_TERTIARY2 45 +#define MSG_ID_STATS_BG 46 +#define MSG_ID_STATS_BF 47 +#define MSG_ID_STATS_BHIST 48 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define MSG_ID_RDI0_UPDATE_ACK 49 +#define MSG_ID_RDI1_UPDATE_ACK 50 +#define MSG_ID_RDI2_UPDATE_ACK 51 +#define MSG_ID_PIX0_UPDATE_ACK 52 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define MSG_ID_PREV_STOP_ACK 53 +#define MSG_ID_STATS_BE 54 +#define VFE_CMD_DUMMY_0 0 +#define VFE_CMD_SET_CLK 1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VFE_CMD_RESET 2 +#define VFE_CMD_START 3 +#define VFE_CMD_TEST_GEN_START 4 +#define VFE_CMD_OPERATION_CFG 5 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VFE_CMD_AXI_OUT_CFG 6 +#define VFE_CMD_CAMIF_CFG 7 +#define VFE_CMD_AXI_INPUT_CFG 8 +#define VFE_CMD_BLACK_LEVEL_CFG 9 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VFE_CMD_MESH_ROLL_OFF_CFG 10 +#define VFE_CMD_DEMUX_CFG 11 +#define VFE_CMD_FOV_CFG 12 +#define VFE_CMD_MAIN_SCALER_CFG 13 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VFE_CMD_WB_CFG 14 +#define VFE_CMD_COLOR_COR_CFG 15 +#define VFE_CMD_RGB_G_CFG 16 +#define VFE_CMD_LA_CFG 17 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VFE_CMD_CHROMA_EN_CFG 18 +#define VFE_CMD_CHROMA_SUP_CFG 19 +#define VFE_CMD_MCE_CFG 20 +#define VFE_CMD_SK_ENHAN_CFG 21 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VFE_CMD_ASF_CFG 22 +#define VFE_CMD_S2Y_CFG 23 +#define VFE_CMD_S2CbCr_CFG 24 +#define VFE_CMD_CHROMA_SUBS_CFG 25 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VFE_CMD_OUT_CLAMP_CFG 26 +#define VFE_CMD_FRAME_SKIP_CFG 27 +#define VFE_CMD_DUMMY_1 28 +#define VFE_CMD_DUMMY_2 29 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VFE_CMD_DUMMY_3 30 +#define VFE_CMD_UPDATE 31 +#define VFE_CMD_BL_LVL_UPDATE 32 +#define VFE_CMD_DEMUX_UPDATE 33 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VFE_CMD_FOV_UPDATE 34 +#define VFE_CMD_MAIN_SCALER_UPDATE 35 +#define VFE_CMD_WB_UPDATE 36 +#define VFE_CMD_COLOR_COR_UPDATE 37 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VFE_CMD_RGB_G_UPDATE 38 +#define VFE_CMD_LA_UPDATE 39 +#define VFE_CMD_CHROMA_EN_UPDATE 40 +#define VFE_CMD_CHROMA_SUP_UPDATE 41 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VFE_CMD_MCE_UPDATE 42 +#define VFE_CMD_SK_ENHAN_UPDATE 43 +#define VFE_CMD_S2CbCr_UPDATE 44 +#define VFE_CMD_S2Y_UPDATE 45 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VFE_CMD_ASF_UPDATE 46 +#define VFE_CMD_FRAME_SKIP_UPDATE 47 +#define VFE_CMD_CAMIF_FRAME_UPDATE 48 +#define VFE_CMD_STATS_AF_UPDATE 49 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VFE_CMD_STATS_AE_UPDATE 50 +#define VFE_CMD_STATS_AWB_UPDATE 51 +#define VFE_CMD_STATS_RS_UPDATE 52 +#define VFE_CMD_STATS_CS_UPDATE 53 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VFE_CMD_STATS_SKIN_UPDATE 54 +#define VFE_CMD_STATS_IHIST_UPDATE 55 +#define VFE_CMD_DUMMY_4 56 +#define VFE_CMD_EPOCH1_ACK 57 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VFE_CMD_EPOCH2_ACK 58 +#define VFE_CMD_START_RECORDING 59 +#define VFE_CMD_STOP_RECORDING 60 +#define VFE_CMD_DUMMY_5 61 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VFE_CMD_DUMMY_6 62 +#define VFE_CMD_CAPTURE 63 +#define VFE_CMD_DUMMY_7 64 +#define VFE_CMD_STOP 65 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VFE_CMD_GET_HW_VERSION 66 +#define VFE_CMD_GET_FRAME_SKIP_COUNTS 67 +#define VFE_CMD_OUTPUT1_BUFFER_ENQ 68 +#define VFE_CMD_OUTPUT2_BUFFER_ENQ 69 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VFE_CMD_OUTPUT3_BUFFER_ENQ 70 +#define VFE_CMD_JPEG_OUT_BUF_ENQ 71 +#define VFE_CMD_RAW_OUT_BUF_ENQ 72 +#define VFE_CMD_RAW_IN_BUF_ENQ 73 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VFE_CMD_STATS_AF_ENQ 74 +#define VFE_CMD_STATS_AE_ENQ 75 +#define VFE_CMD_STATS_AWB_ENQ 76 +#define VFE_CMD_STATS_RS_ENQ 77 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VFE_CMD_STATS_CS_ENQ 78 +#define VFE_CMD_STATS_SKIN_ENQ 79 +#define VFE_CMD_STATS_IHIST_ENQ 80 +#define VFE_CMD_DUMMY_8 81 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VFE_CMD_JPEG_ENC_CFG 82 +#define VFE_CMD_DUMMY_9 83 +#define VFE_CMD_STATS_AF_START 84 +#define VFE_CMD_STATS_AF_STOP 85 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VFE_CMD_STATS_AE_START 86 +#define VFE_CMD_STATS_AE_STOP 87 +#define VFE_CMD_STATS_AWB_START 88 +#define VFE_CMD_STATS_AWB_STOP 89 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VFE_CMD_STATS_RS_START 90 +#define VFE_CMD_STATS_RS_STOP 91 +#define VFE_CMD_STATS_CS_START 92 +#define VFE_CMD_STATS_CS_STOP 93 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VFE_CMD_STATS_SKIN_START 94 +#define VFE_CMD_STATS_SKIN_STOP 95 +#define VFE_CMD_STATS_IHIST_START 96 +#define VFE_CMD_STATS_IHIST_STOP 97 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VFE_CMD_DUMMY_10 98 +#define VFE_CMD_SYNC_TIMER_SETTING 99 +#define VFE_CMD_ASYNC_TIMER_SETTING 100 +#define VFE_CMD_LIVESHOT 101 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VFE_CMD_LA_SETUP 102 +#define VFE_CMD_LINEARIZATION_CFG 103 +#define VFE_CMD_DEMOSAICV3 104 +#define VFE_CMD_DEMOSAICV3_ABCC_CFG 105 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VFE_CMD_DEMOSAICV3_DBCC_CFG 106 +#define VFE_CMD_DEMOSAICV3_DBPC_CFG 107 +#define VFE_CMD_DEMOSAICV3_ABF_CFG 108 +#define VFE_CMD_DEMOSAICV3_ABCC_UPDATE 109 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VFE_CMD_DEMOSAICV3_DBCC_UPDATE 110 +#define VFE_CMD_DEMOSAICV3_DBPC_UPDATE 111 +#define VFE_CMD_XBAR_CFG 112 +#define VFE_CMD_MODULE_CFG 113 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VFE_CMD_ZSL 114 +#define VFE_CMD_LINEARIZATION_UPDATE 115 +#define VFE_CMD_DEMOSAICV3_ABF_UPDATE 116 +#define VFE_CMD_CLF_CFG 117 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VFE_CMD_CLF_LUMA_UPDATE 118 +#define VFE_CMD_CLF_CHROMA_UPDATE 119 +#define VFE_CMD_PCA_ROLL_OFF_CFG 120 +#define VFE_CMD_PCA_ROLL_OFF_UPDATE 121 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VFE_CMD_GET_REG_DUMP 122 +#define VFE_CMD_GET_LINEARIZATON_TABLE 123 +#define VFE_CMD_GET_MESH_ROLLOFF_TABLE 124 +#define VFE_CMD_GET_PCA_ROLLOFF_TABLE 125 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VFE_CMD_GET_RGB_G_TABLE 126 +#define VFE_CMD_GET_LA_TABLE 127 +#define VFE_CMD_DEMOSAICV3_UPDATE 128 +#define VFE_CMD_ACTIVE_REGION_CFG 129 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VFE_CMD_COLOR_PROCESSING_CONFIG 130 +#define VFE_CMD_STATS_WB_AEC_CONFIG 131 +#define VFE_CMD_STATS_WB_AEC_UPDATE 132 +#define VFE_CMD_Y_GAMMA_CONFIG 133 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VFE_CMD_SCALE_OUTPUT1_CONFIG 134 +#define VFE_CMD_SCALE_OUTPUT2_CONFIG 135 +#define VFE_CMD_CAPTURE_RAW 136 +#define VFE_CMD_STOP_LIVESHOT 137 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VFE_CMD_RECONFIG_VFE 138 +#define VFE_CMD_STATS_REQBUF 139 +#define VFE_CMD_STATS_ENQUEUEBUF 140 +#define VFE_CMD_STATS_FLUSH_BUFQ 141 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VFE_CMD_STATS_UNREGBUF 142 +#define VFE_CMD_STATS_BG_START 143 +#define VFE_CMD_STATS_BG_STOP 144 +#define VFE_CMD_STATS_BF_START 145 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VFE_CMD_STATS_BF_STOP 146 +#define VFE_CMD_STATS_BHIST_START 147 +#define VFE_CMD_STATS_BHIST_STOP 148 +#define VFE_CMD_RESET_2 149 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VFE_CMD_FOV_ENC_CFG 150 +#define VFE_CMD_FOV_VIEW_CFG 151 +#define VFE_CMD_FOV_ENC_UPDATE 152 +#define VFE_CMD_FOV_VIEW_UPDATE 153 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VFE_CMD_SCALER_ENC_CFG 154 +#define VFE_CMD_SCALER_VIEW_CFG 155 +#define VFE_CMD_SCALER_ENC_UPDATE 156 +#define VFE_CMD_SCALER_VIEW_UPDATE 157 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VFE_CMD_COLORXFORM_ENC_CFG 158 +#define VFE_CMD_COLORXFORM_VIEW_CFG 159 +#define VFE_CMD_COLORXFORM_ENC_UPDATE 160 +#define VFE_CMD_COLORXFORM_VIEW_UPDATE 161 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VFE_CMD_TEST_GEN_CFG 162 +#define VFE_CMD_STATS_BE_START 163 +#define VFE_CMD_STATS_BE_STOP 164 +struct msm_isp_cmd { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + int32_t id; + uint16_t length; + void *value; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VPE_CMD_DUMMY_0 0 +#define VPE_CMD_INIT 1 +#define VPE_CMD_DEINIT 2 +#define VPE_CMD_ENABLE 3 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VPE_CMD_DISABLE 4 +#define VPE_CMD_RESET 5 +#define VPE_CMD_FLUSH 6 +#define VPE_CMD_OPERATION_MODE_CFG 7 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VPE_CMD_INPUT_PLANE_CFG 8 +#define VPE_CMD_OUTPUT_PLANE_CFG 9 +#define VPE_CMD_INPUT_PLANE_UPDATE 10 +#define VPE_CMD_SCALE_CFG_TYPE 11 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VPE_CMD_ZOOM 13 +#define VPE_CMD_MAX 14 +#define MSM_PP_CMD_TYPE_NOT_USED 0 +#define MSM_PP_CMD_TYPE_VPE 1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define MSM_PP_CMD_TYPE_MCTL 2 +#define MCTL_CMD_DUMMY_0 0 +#define MCTL_CMD_GET_FRAME_BUFFER 1 +#define MCTL_CMD_PUT_FRAME_BUFFER 2 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define MCTL_CMD_DIVERT_FRAME_PP_PATH 3 +#define MCTL_PP_EVENT_NOTUSED 0 +#define MCTL_PP_EVENT_CMD_ACK 1 +#define VPE_OPERATION_MODE_CFG_LEN 4 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VPE_INPUT_PLANE_CFG_LEN 24 +#define VPE_OUTPUT_PLANE_CFG_LEN 20 +#define VPE_INPUT_PLANE_UPDATE_LEN 12 +#define VPE_SCALER_CONFIG_LEN 260 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VPE_DIS_OFFSET_CFG_LEN 12 +#define CAPTURE_WIDTH 1280 +#define IMEM_Y_SIZE (CAPTURE_WIDTH*16) +#define IMEM_CBCR_SIZE (CAPTURE_WIDTH*8) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define IMEM_Y_PING_OFFSET 0x2E000000 +#define IMEM_CBCR_PING_OFFSET (IMEM_Y_PING_OFFSET + IMEM_Y_SIZE) +#define IMEM_Y_PONG_OFFSET (IMEM_CBCR_PING_OFFSET + IMEM_CBCR_SIZE) +#define IMEM_CBCR_PONG_OFFSET (IMEM_Y_PONG_OFFSET + IMEM_Y_SIZE) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct msm_vpe_op_mode_cfg { + uint8_t op_mode_cfg[VPE_OPERATION_MODE_CFG_LEN]; +}; +struct msm_vpe_input_plane_cfg { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint8_t input_plane_cfg[VPE_INPUT_PLANE_CFG_LEN]; +}; +struct msm_vpe_output_plane_cfg { + uint8_t output_plane_cfg[VPE_OUTPUT_PLANE_CFG_LEN]; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +struct msm_vpe_input_plane_update_cfg { + uint8_t input_plane_update_cfg[VPE_INPUT_PLANE_UPDATE_LEN]; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct msm_vpe_scaler_cfg { + uint8_t scaler_cfg[VPE_SCALER_CONFIG_LEN]; +}; +struct msm_vpe_flush_frame_buffer { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t src_buf_handle; + uint32_t dest_buf_handle; + int path; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct msm_mctl_pp_frame_buffer { + uint32_t buf_handle; + int path; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct msm_mctl_pp_divert_pp { + int path; + int enable; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct msm_vpe_clock_rate { + uint32_t rate; +}; +#define MSM_MCTL_PP_VPE_FRAME_ACK (1<<0) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define MSM_MCTL_PP_VPE_FRAME_TO_APP (1<<1) +#define VFE_OUTPUTS_MAIN_AND_PREVIEW BIT(0) +#define VFE_OUTPUTS_MAIN_AND_VIDEO BIT(1) +#define VFE_OUTPUTS_MAIN_AND_THUMB BIT(2) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VFE_OUTPUTS_THUMB_AND_MAIN BIT(3) +#define VFE_OUTPUTS_PREVIEW_AND_VIDEO BIT(4) +#define VFE_OUTPUTS_VIDEO_AND_PREVIEW BIT(5) +#define VFE_OUTPUTS_PREVIEW BIT(6) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VFE_OUTPUTS_VIDEO BIT(7) +#define VFE_OUTPUTS_RAW BIT(8) +#define VFE_OUTPUTS_JPEG_AND_THUMB BIT(9) +#define VFE_OUTPUTS_THUMB_AND_JPEG BIT(10) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VFE_OUTPUTS_RDI0 BIT(11) +#define VFE_OUTPUTS_RDI1 BIT(12) +struct msm_frame_info { + uint32_t inst_handle; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t path; +}; +#endif + diff --git a/kernel-headers/media/msm_jpeg.h b/kernel-headers/media/msm_jpeg.h new file mode 100644 index 0000000..8b52149 --- /dev/null +++ b/kernel-headers/media/msm_jpeg.h @@ -0,0 +1,109 @@ +/**************************************************************************** + **************************************************************************** + *** + *** This header was automatically generated from a Linux kernel header + *** of the same name, to make information necessary for userspace to + *** call into the kernel available to libc. It contains only constants, + *** structures, and macros generated from the original header, and thus, + *** contains no copyrightable information. + *** + *** To edit the content of this header, modify the corresponding + *** source file (e.g. under external/kernel-headers/original/) then + *** run bionic/libc/kernel/tools/update_all.py + *** + *** Any manual change here will be lost the next time this script will + *** be run. You've been warned! + *** + **************************************************************************** + ****************************************************************************/ +#ifndef __LINUX_MSM_JPEG_H +#define __LINUX_MSM_JPEG_H +#include <linux/types.h> +#include <linux/ioctl.h> +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define OUTPUT_H2V1 0 +#define OUTPUT_H2V2 1 +#define OUTPUT_BYTE 6 +#define MSM_JPEG_IOCTL_MAGIC 'g' +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define MSM_JPEG_IOCTL_GET_HW_VERSION _IOW(MSM_JPEG_IOCTL_MAGIC, 1, struct msm_jpeg_hw_cmd) +#define MSM_JPEG_IOCTL_RESET _IOW(MSM_JPEG_IOCTL_MAGIC, 2, struct msm_jpeg_ctrl_cmd) +#define MSM_JPEG_IOCTL_STOP _IOW(MSM_JPEG_IOCTL_MAGIC, 3, struct msm_jpeg_hw_cmds) +#define MSM_JPEG_IOCTL_START _IOW(MSM_JPEG_IOCTL_MAGIC, 4, struct msm_jpeg_hw_cmds) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define MSM_JPEG_IOCTL_INPUT_BUF_ENQUEUE _IOW(MSM_JPEG_IOCTL_MAGIC, 5, struct msm_jpeg_buf) +#define MSM_JPEG_IOCTL_INPUT_GET _IOW(MSM_JPEG_IOCTL_MAGIC, 6, struct msm_jpeg_buf) +#define MSM_JPEG_IOCTL_INPUT_GET_UNBLOCK _IOW(MSM_JPEG_IOCTL_MAGIC, 7, int) +#define MSM_JPEG_IOCTL_OUTPUT_BUF_ENQUEUE _IOW(MSM_JPEG_IOCTL_MAGIC, 8, struct msm_jpeg_buf) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define MSM_JPEG_IOCTL_OUTPUT_GET _IOW(MSM_JPEG_IOCTL_MAGIC, 9, struct msm_jpeg_buf) +#define MSM_JPEG_IOCTL_OUTPUT_GET_UNBLOCK _IOW(MSM_JPEG_IOCTL_MAGIC, 10, int) +#define MSM_JPEG_IOCTL_EVT_GET _IOW(MSM_JPEG_IOCTL_MAGIC, 11, struct msm_jpeg_ctrl_cmd) +#define MSM_JPEG_IOCTL_EVT_GET_UNBLOCK _IOW(MSM_JPEG_IOCTL_MAGIC, 12, int) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define MSM_JPEG_IOCTL_HW_CMD _IOW(MSM_JPEG_IOCTL_MAGIC, 13, struct msm_jpeg_hw_cmd) +#define MSM_JPEG_IOCTL_HW_CMDS _IOW(MSM_JPEG_IOCTL_MAGIC, 14, struct msm_jpeg_hw_cmds) +#define MSM_JPEG_IOCTL_TEST_DUMP_REGION _IOW(MSM_JPEG_IOCTL_MAGIC, 15, unsigned long) +#define MSM_JPEG_IOCTL_SET_CLK_RATE _IOW(MSM_JPEG_IOCTL_MAGIC, 16, unsigned int) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define MSM_JPEG_MODE_REALTIME_ENCODE 0 +#define MSM_JPEG_MODE_OFFLINE_ENCODE 1 +#define MSM_JPEG_MODE_REALTIME_ROTATION 2 +#define MSM_JPEG_MODE_OFFLINE_ROTATION 3 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct msm_jpeg_ctrl_cmd { + uint32_t type; + uint32_t len; + void *value; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +#define MSM_JPEG_EVT_RESET 0 +#define MSM_JPEG_EVT_SESSION_DONE 1 +#define MSM_JPEG_EVT_ERR 2 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct msm_jpeg_buf { + uint32_t type; + int fd; + void *vaddr; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t y_off; + uint32_t y_len; + uint32_t framedone_len; + uint32_t cbcr_off; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t cbcr_len; + uint32_t num_of_mcu_rows; + uint32_t offset; + uint32_t pln2_off; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t pln2_len; +}; +#define MSM_JPEG_HW_CMD_TYPE_READ 0 +#define MSM_JPEG_HW_CMD_TYPE_WRITE 1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define MSM_JPEG_HW_CMD_TYPE_WRITE_OR 2 +#define MSM_JPEG_HW_CMD_TYPE_UWAIT 3 +#define MSM_JPEG_HW_CMD_TYPE_MWAIT 4 +#define MSM_JPEG_HW_CMD_TYPE_MDELAY 5 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define MSM_JPEG_HW_CMD_TYPE_UDELAY 6 +struct msm_jpeg_hw_cmd { + uint32_t type:4; + uint32_t n:12; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t offset:16; + uint32_t mask; + union { + uint32_t data; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t *pdata; + }; +}; +struct msm_jpeg_hw_cmds { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t m; + struct msm_jpeg_hw_cmd hw_cmd[1]; +}; +#endif +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + diff --git a/kernel-headers/media/msm_media_info.h b/kernel-headers/media/msm_media_info.h new file mode 100644 index 0000000..83aa7ee --- /dev/null +++ b/kernel-headers/media/msm_media_info.h @@ -0,0 +1,611 @@ +#ifndef __MEDIA_INFO_H__ +#define __MEDIA_INFO_H__ + +#ifndef MSM_MEDIA_ALIGN +#define MSM_MEDIA_ALIGN(__sz, __align) (((__sz) + (__align-1)) & (~(__align-1))) +#endif + +#ifndef MSM_MEDIA_ROUNDUP +#define MSM_MEDIA_ROUNDUP(__sz, __r) (((__sz) + ((__r) - 1)) / (__r)) +#endif + +enum color_fmts { + /* Venus NV12: + * YUV 4:2:0 image with a plane of 8 bit Y samples followed + * by an interleaved U/V plane containing 8 bit 2x2 subsampled + * colour difference samples. + * + * <-------- Y/UV_Stride --------> + * <------- Width -------> + * Y Y Y Y Y Y Y Y Y Y Y Y . . . . ^ ^ + * Y Y Y Y Y Y Y Y Y Y Y Y . . . . | | + * Y Y Y Y Y Y Y Y Y Y Y Y . . . . Height | + * Y Y Y Y Y Y Y Y Y Y Y Y . . . . | Y_Scanlines + * Y Y Y Y Y Y Y Y Y Y Y Y . . . . | | + * Y Y Y Y Y Y Y Y Y Y Y Y . . . . | | + * Y Y Y Y Y Y Y Y Y Y Y Y . . . . | | + * Y Y Y Y Y Y Y Y Y Y Y Y . . . . V | + * . . . . . . . . . . . . . . . . | + * . . . . . . . . . . . . . . . . | + * . . . . . . . . . . . . . . . . | + * . . . . . . . . . . . . . . . . V + * U V U V U V U V U V U V . . . . ^ + * U V U V U V U V U V U V . . . . | + * U V U V U V U V U V U V . . . . | + * U V U V U V U V U V U V . . . . UV_Scanlines + * . . . . . . . . . . . . . . . . | + * . . . . . . . . . . . . . . . . V + * . . . . . . . . . . . . . . . . --> Buffer size alignment + * + * Y_Stride : Width aligned to 128 + * UV_Stride : Width aligned to 128 + * Y_Scanlines: Height aligned to 32 + * UV_Scanlines: Height/2 aligned to 16 + * Extradata: Arbitrary (software-imposed) padding + * Total size = align((Y_Stride * Y_Scanlines + * + UV_Stride * UV_Scanlines + Extradata), 4096) + */ + COLOR_FMT_NV12, + + /* Venus NV21: + * YUV 4:2:0 image with a plane of 8 bit Y samples followed + * by an interleaved V/U plane containing 8 bit 2x2 subsampled + * colour difference samples. + * + * <-------- Y/UV_Stride --------> + * <------- Width -------> + * Y Y Y Y Y Y Y Y Y Y Y Y . . . . ^ ^ + * Y Y Y Y Y Y Y Y Y Y Y Y . . . . | | + * Y Y Y Y Y Y Y Y Y Y Y Y . . . . Height | + * Y Y Y Y Y Y Y Y Y Y Y Y . . . . | Y_Scanlines + * Y Y Y Y Y Y Y Y Y Y Y Y . . . . | | + * Y Y Y Y Y Y Y Y Y Y Y Y . . . . | | + * Y Y Y Y Y Y Y Y Y Y Y Y . . . . | | + * Y Y Y Y Y Y Y Y Y Y Y Y . . . . V | + * . . . . . . . . . . . . . . . . | + * . . . . . . . . . . . . . . . . | + * . . . . . . . . . . . . . . . . | + * . . . . . . . . . . . . . . . . V + * V U V U V U V U V U V U . . . . ^ + * V U V U V U V U V U V U . . . . | + * V U V U V U V U V U V U . . . . | + * V U V U V U V U V U V U . . . . UV_Scanlines + * . . . . . . . . . . . . . . . . | + * . . . . . . . . . . . . . . . . V + * . . . . . . . . . . . . . . . . --> Padding & Buffer size alignment + * + * Y_Stride : Width aligned to 128 + * UV_Stride : Width aligned to 128 + * Y_Scanlines: Height aligned to 32 + * UV_Scanlines: Height/2 aligned to 16 + * Extradata: Arbitrary (software-imposed) padding + * Total size = align((Y_Stride * Y_Scanlines + * + UV_Stride * UV_Scanlines + Extradata), 4096) + */ + COLOR_FMT_NV21, + /* Venus NV12_MVTB: + * Two YUV 4:2:0 images/views one after the other + * in a top-bottom layout, same as NV12 + * with a plane of 8 bit Y samples followed + * by an interleaved U/V plane containing 8 bit 2x2 subsampled + * colour difference samples. + * + * + * <-------- Y/UV_Stride --------> + * <------- Width -------> + * Y Y Y Y Y Y Y Y Y Y Y Y . . . . ^ ^ ^ + * Y Y Y Y Y Y Y Y Y Y Y Y . . . . | | | + * Y Y Y Y Y Y Y Y Y Y Y Y . . . . Height | | + * Y Y Y Y Y Y Y Y Y Y Y Y . . . . | Y_Scanlines | + * Y Y Y Y Y Y Y Y Y Y Y Y . . . . | | | + * Y Y Y Y Y Y Y Y Y Y Y Y . . . . | | | + * Y Y Y Y Y Y Y Y Y Y Y Y . . . . | | | + * Y Y Y Y Y Y Y Y Y Y Y Y . . . . V | | + * . . . . . . . . . . . . . . . . | View_1 + * . . . . . . . . . . . . . . . . | | + * . . . . . . . . . . . . . . . . | | + * . . . . . . . . . . . . . . . . V | + * U V U V U V U V U V U V . . . . ^ | + * U V U V U V U V U V U V . . . . | | + * U V U V U V U V U V U V . . . . | | + * U V U V U V U V U V U V . . . . UV_Scanlines | + * . . . . . . . . . . . . . . . . | | + * . . . . . . . . . . . . . . . . V V + * Y Y Y Y Y Y Y Y Y Y Y Y . . . . ^ ^ ^ + * Y Y Y Y Y Y Y Y Y Y Y Y . . . . | | | + * Y Y Y Y Y Y Y Y Y Y Y Y . . . . Height | | + * Y Y Y Y Y Y Y Y Y Y Y Y . . . . | Y_Scanlines | + * Y Y Y Y Y Y Y Y Y Y Y Y . . . . | | | + * Y Y Y Y Y Y Y Y Y Y Y Y . . . . | | | + * Y Y Y Y Y Y Y Y Y Y Y Y . . . . | | | + * Y Y Y Y Y Y Y Y Y Y Y Y . . . . V | | + * . . . . . . . . . . . . . . . . | View_2 + * . . . . . . . . . . . . . . . . | | + * . . . . . . . . . . . . . . . . | | + * . . . . . . . . . . . . . . . . V | + * U V U V U V U V U V U V . . . . ^ | + * U V U V U V U V U V U V . . . . | | + * U V U V U V U V U V U V . . . . | | + * U V U V U V U V U V U V . . . . UV_Scanlines | + * . . . . . . . . . . . . . . . . | | + * . . . . . . . . . . . . . . . . V V + * . . . . . . . . . . . . . . . . --> Buffer size alignment + * + * Y_Stride : Width aligned to 128 + * UV_Stride : Width aligned to 128 + * Y_Scanlines: Height aligned to 32 + * UV_Scanlines: Height/2 aligned to 16 + * View_1 begin at: 0 (zero) + * View_2 begin at: Y_Stride * Y_Scanlines + UV_Stride * UV_Scanlines + * Extradata: Arbitrary (software-imposed) padding + * Total size = align((2*(Y_Stride * Y_Scanlines) + * + 2*(UV_Stride * UV_Scanlines) + Extradata), 4096) + */ + COLOR_FMT_NV12_MVTB, + /* Venus NV12 UBWC: + * Compressed Macro-tile format for NV12. + * Contains 4 planes in the following order - + * (A) Y_Meta_Plane + * (B) Y_UBWC_Plane + * (C) UV_Meta_Plane + * (D) UV_UBWC_Plane + * + * Y_Meta_Plane consists of meta information to decode compressed + * tile data in Y_UBWC_Plane. + * Y_UBWC_Plane consists of Y data in compressed macro-tile format. + * UBWC decoder block will use the Y_Meta_Plane data together with + * Y_UBWC_Plane data to produce loss-less uncompressed 8 bit Y samples. + * + * UV_Meta_Plane consists of meta information to decode compressed + * tile data in UV_UBWC_Plane. + * UV_UBWC_Plane consists of UV data in compressed macro-tile format. + * UBWC decoder block will use UV_Meta_Plane data together with + * UV_UBWC_Plane data to produce loss-less uncompressed 8 bit 2x2 + * subsampled color difference samples. + * + * Each tile in Y_UBWC_Plane/UV_UBWC_Plane is independently decodable + * and randomly accessible. There is no dependency between tiles. + * + * <----- Y_Meta_Stride ----> + * <-------- Width ------> + * M M M M M M M M M M M M . . ^ ^ + * M M M M M M M M M M M M . . | | + * M M M M M M M M M M M M . . Height | + * M M M M M M M M M M M M . . | Meta_Y_Scanlines + * M M M M M M M M M M M M . . | | + * M M M M M M M M M M M M . . | | + * M M M M M M M M M M M M . . | | + * M M M M M M M M M M M M . . V | + * . . . . . . . . . . . . . . | + * . . . . . . . . . . . . . . | + * . . . . . . . . . . . . . . -------> Buffer size aligned to 4k + * . . . . . . . . . . . . . . V + * <--Compressed tile Y Stride---> + * <------- Width -------> + * Y* Y* Y* Y* Y* Y* Y* Y* . . . . ^ ^ + * Y* Y* Y* Y* Y* Y* Y* Y* . . . . | | + * Y* Y* Y* Y* Y* Y* Y* Y* . . . . Height | + * Y* Y* Y* Y* Y* Y* Y* Y* . . . . | Macro_tile_Y_Scanlines + * Y* Y* Y* Y* Y* Y* Y* Y* . . . . | | + * Y* Y* Y* Y* Y* Y* Y* Y* . . . . | | + * Y* Y* Y* Y* Y* Y* Y* Y* . . . . | | + * Y* Y* Y* Y* Y* Y* Y* Y* . . . . V | + * . . . . . . . . . . . . . . . . | + * . . . . . . . . . . . . . . . . | + * . . . . . . . . . . . . . . . . -------> Buffer size aligned to 4k + * . . . . . . . . . . . . . . . . V + * <----- UV_Meta_Stride ----> + * M M M M M M M M M M M M . . ^ + * M M M M M M M M M M M M . . | + * M M M M M M M M M M M M . . | + * M M M M M M M M M M M M . . M_UV_Scanlines + * . . . . . . . . . . . . . . | + * . . . . . . . . . . . . . . V + * . . . . . . . . . . . . . . -------> Buffer size aligned to 4k + * <--Compressed tile UV Stride---> + * U* V* U* V* U* V* U* V* . . . . ^ + * U* V* U* V* U* V* U* V* . . . . | + * U* V* U* V* U* V* U* V* . . . . | + * U* V* U* V* U* V* U* V* . . . . UV_Scanlines + * . . . . . . . . . . . . . . . . | + * . . . . . . . . . . . . . . . . V + * . . . . . . . . . . . . . . . . -------> Buffer size aligned to 4k + * + * Y_Stride = align(Width, 128) + * UV_Stride = align(Width, 128) + * Y_Scanlines = align(Height, 32) + * UV_Scanlines = align(Height/2, 16) + * Y_UBWC_Plane_size = align(Y_Stride * Y_Scanlines, 4096) + * UV_UBWC_Plane_size = align(UV_Stride * UV_Scanlines, 4096) + * Y_Meta_Stride = align(roundup(Width, Y_TileWidth), 64) + * Y_Meta_Scanlines = align(roundup(Height, Y_TileHeight), 16) + * Y_Meta_Plane_size = align(Y_Meta_Stride * Y_Meta_Scanlines, 4096) + * UV_Meta_Stride = align(roundup(Width, UV_TileWidth), 64) + * UV_Meta_Scanlines = align(roundup(Height, UV_TileHeight), 16) + * UV_Meta_Plane_size = align(UV_Meta_Stride * UV_Meta_Scanlines, 4096) + * Extradata = 8k + * + * Total size = align( Y_UBWC_Plane_size + UV_UBWC_Plane_size + + * Y_Meta_Plane_size + UV_Meta_Plane_size + Extradata, 4096) + */ + COLOR_FMT_NV12_UBWC, + /* Venus NV12 10-bit UBWC: + * Compressed Macro-tile format for NV12. + * Contains 4 planes in the following order - + * (A) Y_Meta_Plane + * (B) Y_UBWC_Plane + * (C) UV_Meta_Plane + * (D) UV_UBWC_Plane + * + * Y_Meta_Plane consists of meta information to decode compressed + * tile data in Y_UBWC_Plane. + * Y_UBWC_Plane consists of Y data in compressed macro-tile format. + * UBWC decoder block will use the Y_Meta_Plane data together with + * Y_UBWC_Plane data to produce loss-less uncompressed 10 bit Y samples. + * + * UV_Meta_Plane consists of meta information to decode compressed + * tile data in UV_UBWC_Plane. + * UV_UBWC_Plane consists of UV data in compressed macro-tile format. + * UBWC decoder block will use UV_Meta_Plane data together with + * UV_UBWC_Plane data to produce loss-less uncompressed 10 bit 2x2 + * subsampled color difference samples. + * + * Each tile in Y_UBWC_Plane/UV_UBWC_Plane is independently decodable + * and randomly accessible. There is no dependency between tiles. + * + * <----- Y_Meta_Stride -----> + * <-------- Width ------> + * M M M M M M M M M M M M . . ^ ^ + * M M M M M M M M M M M M . . | | + * M M M M M M M M M M M M . . Height | + * M M M M M M M M M M M M . . | Meta_Y_Scanlines + * M M M M M M M M M M M M . . | | + * M M M M M M M M M M M M . . | | + * M M M M M M M M M M M M . . | | + * M M M M M M M M M M M M . . V | + * . . . . . . . . . . . . . . | + * . . . . . . . . . . . . . . | + * . . . . . . . . . . . . . . -------> Buffer size aligned to 4k + * . . . . . . . . . . . . . . V + * <--Compressed tile Y Stride---> + * <------- Width -------> + * Y* Y* Y* Y* Y* Y* Y* Y* . . . . ^ ^ + * Y* Y* Y* Y* Y* Y* Y* Y* . . . . | | + * Y* Y* Y* Y* Y* Y* Y* Y* . . . . Height | + * Y* Y* Y* Y* Y* Y* Y* Y* . . . . | Macro_tile_Y_Scanlines + * Y* Y* Y* Y* Y* Y* Y* Y* . . . . | | + * Y* Y* Y* Y* Y* Y* Y* Y* . . . . | | + * Y* Y* Y* Y* Y* Y* Y* Y* . . . . | | + * Y* Y* Y* Y* Y* Y* Y* Y* . . . . V | + * . . . . . . . . . . . . . . . . | + * . . . . . . . . . . . . . . . . | + * . . . . . . . . . . . . . . . . -------> Buffer size aligned to 4k + * . . . . . . . . . . . . . . . . V + * <----- UV_Meta_Stride ----> + * M M M M M M M M M M M M . . ^ + * M M M M M M M M M M M M . . | + * M M M M M M M M M M M M . . | + * M M M M M M M M M M M M . . M_UV_Scanlines + * . . . . . . . . . . . . . . | + * . . . . . . . . . . . . . . V + * . . . . . . . . . . . . . . -------> Buffer size aligned to 4k + * <--Compressed tile UV Stride---> + * U* V* U* V* U* V* U* V* . . . . ^ + * U* V* U* V* U* V* U* V* . . . . | + * U* V* U* V* U* V* U* V* . . . . | + * U* V* U* V* U* V* U* V* . . . . UV_Scanlines + * . . . . . . . . . . . . . . . . | + * . . . . . . . . . . . . . . . . V + * . . . . . . . . . . . . . . . . -------> Buffer size aligned to 4k + * + * + * Y_Stride = align(Width * 4/3, 128) + * UV_Stride = align(Width * 4/3, 128) + * Y_Scanlines = align(Height, 32) + * UV_Scanlines = align(Height/2, 16) + * Y_UBWC_Plane_Size = align(Y_Stride * Y_Scanlines, 4096) + * UV_UBWC_Plane_Size = align(UV_Stride * UV_Scanlines, 4096) + * Y_Meta_Stride = align(roundup(Width, Y_TileWidth), 64) + * Y_Meta_Scanlines = align(roundup(Height, Y_TileHeight), 16) + * Y_Meta_Plane_size = align(Y_Meta_Stride * Y_Meta_Scanlines, 4096) + * UV_Meta_Stride = align(roundup(Width, UV_TileWidth), 64) + * UV_Meta_Scanlines = align(roundup(Height, UV_TileHeight), 16) + * UV_Meta_Plane_size = align(UV_Meta_Stride * UV_Meta_Scanlines, 4096) + * Extradata = 8k + */ + COLOR_FMT_NV12_BPP10_UBWC, +}; + +static inline unsigned int VENUS_EXTRADATA_SIZE(int width, int height) +{ + (void)height; + (void)width; + + /* + * In the future, calculate the size based on the w/h but just + * hardcode it for now since 8K satisfies all current usecases. + */ + return 8 * 1024; +} + +static inline unsigned int VENUS_Y_STRIDE(int color_fmt, int width) +{ + unsigned int alignment, stride = 0; + if (!width) + goto invalid_input; + + switch (color_fmt) { + case COLOR_FMT_NV21: + case COLOR_FMT_NV12: + case COLOR_FMT_NV12_MVTB: + case COLOR_FMT_NV12_UBWC: + alignment = 128; + stride = MSM_MEDIA_ALIGN(width, alignment); + break; + case COLOR_FMT_NV12_BPP10_UBWC: + alignment = 128; + stride = MSM_MEDIA_ALIGN(width * 4/3, alignment); + break; + default: + break; + } +invalid_input: + return stride; +} + +static inline unsigned int VENUS_UV_STRIDE(int color_fmt, int width) +{ + unsigned int alignment, stride = 0; + if (!width) + goto invalid_input; + + switch (color_fmt) { + case COLOR_FMT_NV21: + case COLOR_FMT_NV12: + case COLOR_FMT_NV12_MVTB: + case COLOR_FMT_NV12_UBWC: + alignment = 128; + stride = MSM_MEDIA_ALIGN(width, alignment); + break; + case COLOR_FMT_NV12_BPP10_UBWC: + alignment = 128; + stride = MSM_MEDIA_ALIGN(width * 4/3, alignment); + break; + default: + break; + } +invalid_input: + return stride; +} + +static inline unsigned int VENUS_Y_SCANLINES(int color_fmt, int height) +{ + unsigned int alignment, sclines = 0; + if (!height) + goto invalid_input; + + switch (color_fmt) { + case COLOR_FMT_NV21: + case COLOR_FMT_NV12: + case COLOR_FMT_NV12_MVTB: + case COLOR_FMT_NV12_UBWC: + case COLOR_FMT_NV12_BPP10_UBWC: + alignment = 32; + sclines = MSM_MEDIA_ALIGN(height, alignment); + break; + default: + break; + } +invalid_input: + return sclines; +} + +static inline unsigned int VENUS_UV_SCANLINES(int color_fmt, int height) +{ + unsigned int alignment, sclines = 0; + if (!height) + goto invalid_input; + + switch (color_fmt) { + case COLOR_FMT_NV21: + case COLOR_FMT_NV12: + case COLOR_FMT_NV12_MVTB: + case COLOR_FMT_NV12_UBWC: + case COLOR_FMT_NV12_BPP10_UBWC: + alignment = 16; + sclines = MSM_MEDIA_ALIGN(((height + 1) >> 1), alignment); + break; + default: + break; + } +invalid_input: + return sclines; +} + +static inline unsigned int VENUS_Y_META_STRIDE(int color_fmt, int width) +{ + int y_tile_width = 0, y_meta_stride = 0; + + if (!width) + goto invalid_input; + + switch (color_fmt) { + case COLOR_FMT_NV12_UBWC: + y_tile_width = 32; + break; + case COLOR_FMT_NV12_BPP10_UBWC: + y_tile_width = 48; + break; + default: + goto invalid_input; + } + + y_meta_stride = MSM_MEDIA_ROUNDUP(width, y_tile_width); + y_meta_stride = MSM_MEDIA_ALIGN(y_meta_stride, 64); + +invalid_input: + return y_meta_stride; +} + +static inline unsigned int VENUS_Y_META_SCANLINES(int color_fmt, int height) +{ + int y_tile_height = 0, y_meta_scanlines = 0; + + if (!height) + goto invalid_input; + + switch (color_fmt) { + case COLOR_FMT_NV12_UBWC: + y_tile_height = 8; + break; + case COLOR_FMT_NV12_BPP10_UBWC: + y_tile_height = 4; + break; + default: + goto invalid_input; + } + + y_meta_scanlines = MSM_MEDIA_ROUNDUP(height, y_tile_height); + y_meta_scanlines = MSM_MEDIA_ALIGN(y_meta_scanlines, 16); + +invalid_input: + return y_meta_scanlines; +} + +static inline unsigned int VENUS_UV_META_STRIDE(int color_fmt, int width) +{ + int uv_tile_width = 0, uv_meta_stride = 0; + + if (!width) + goto invalid_input; + + switch (color_fmt) { + case COLOR_FMT_NV12_UBWC: + uv_tile_width = 16; + break; + case COLOR_FMT_NV12_BPP10_UBWC: + uv_tile_width = 24; + break; + default: + goto invalid_input; + } + + uv_meta_stride = MSM_MEDIA_ROUNDUP(width, uv_tile_width); + uv_meta_stride = MSM_MEDIA_ALIGN(uv_meta_stride, 64); + +invalid_input: + return uv_meta_stride; +} + +static inline unsigned int VENUS_UV_META_SCANLINES(int color_fmt, int height) +{ + int uv_tile_height = 0, uv_meta_scanlines = 0; + + if (!height) + goto invalid_input; + + switch (color_fmt) { + case COLOR_FMT_NV12_UBWC: + uv_tile_height = 8; + break; + case COLOR_FMT_NV12_BPP10_UBWC: + uv_tile_height = 4; + break; + default: + goto invalid_input; + } + + uv_meta_scanlines = MSM_MEDIA_ROUNDUP(height, uv_tile_height); + uv_meta_scanlines = MSM_MEDIA_ALIGN(uv_meta_scanlines, 16); + +invalid_input: + return uv_meta_scanlines; +} + +static inline unsigned int VENUS_BUFFER_SIZE( + int color_fmt, int width, int height) +{ + const unsigned int extra_size = VENUS_EXTRADATA_SIZE(width, height); + unsigned int uv_alignment = 0, size = 0; + unsigned int y_plane, uv_plane, y_stride, + uv_stride, y_sclines, uv_sclines; + unsigned int y_ubwc_plane = 0, uv_ubwc_plane = 0; + unsigned int y_meta_stride = 0, y_meta_scanlines = 0; + unsigned int uv_meta_stride = 0, uv_meta_scanlines = 0; + unsigned int y_meta_plane = 0, uv_meta_plane = 0; + + if (!width || !height) + goto invalid_input; + + y_stride = VENUS_Y_STRIDE(color_fmt, width); + uv_stride = VENUS_UV_STRIDE(color_fmt, width); + y_sclines = VENUS_Y_SCANLINES(color_fmt, height); + uv_sclines = VENUS_UV_SCANLINES(color_fmt, height); + switch (color_fmt) { + case COLOR_FMT_NV21: + case COLOR_FMT_NV12: + uv_alignment = 4096; + y_plane = y_stride * y_sclines; + uv_plane = uv_stride * uv_sclines + uv_alignment; + size = y_plane + uv_plane + extra_size; + size = MSM_MEDIA_ALIGN(size, 4096); + break; + case COLOR_FMT_NV12_MVTB: + uv_alignment = 4096; + y_plane = y_stride * y_sclines; + uv_plane = uv_stride * uv_sclines + uv_alignment; + size = y_plane + uv_plane; + size = 2 * size + extra_size; + size = MSM_MEDIA_ALIGN(size, 4096); + break; + case COLOR_FMT_NV12_UBWC: + case COLOR_FMT_NV12_BPP10_UBWC: + y_ubwc_plane = MSM_MEDIA_ALIGN(y_stride * y_sclines, 4096); + uv_ubwc_plane = MSM_MEDIA_ALIGN(uv_stride * uv_sclines, 4096); + y_meta_stride = VENUS_Y_META_STRIDE(color_fmt, width); + y_meta_scanlines = VENUS_Y_META_SCANLINES(color_fmt, height); + y_meta_plane = MSM_MEDIA_ALIGN( + y_meta_stride * y_meta_scanlines, 4096); + uv_meta_stride = VENUS_UV_META_STRIDE(color_fmt, width); + uv_meta_scanlines = VENUS_UV_META_SCANLINES(color_fmt, height); + uv_meta_plane = MSM_MEDIA_ALIGN(uv_meta_stride * + uv_meta_scanlines, 4096); + + size = y_ubwc_plane + uv_ubwc_plane + y_meta_plane + + uv_meta_plane + extra_size; + size = MSM_MEDIA_ALIGN(size, 4096); + break; + default: + break; + } +invalid_input: + return size; +} + +static inline unsigned int VENUS_VIEW2_OFFSET( + int color_fmt, int width, int height) +{ + unsigned int offset = 0; + unsigned int y_plane, uv_plane, y_stride, + uv_stride, y_sclines, uv_sclines; + if (!width || !height) + goto invalid_input; + + y_stride = VENUS_Y_STRIDE(color_fmt, width); + uv_stride = VENUS_UV_STRIDE(color_fmt, width); + y_sclines = VENUS_Y_SCANLINES(color_fmt, height); + uv_sclines = VENUS_UV_SCANLINES(color_fmt, height); + switch (color_fmt) { + case COLOR_FMT_NV12_MVTB: + y_plane = y_stride * y_sclines; + uv_plane = uv_stride * uv_sclines; + offset = y_plane + uv_plane; + break; + default: + break; + } +invalid_input: + return offset; +} + +#endif diff --git a/kernel-headers/media/msm_vidc.h b/kernel-headers/media/msm_vidc.h new file mode 100644 index 0000000..0e053d8 --- /dev/null +++ b/kernel-headers/media/msm_vidc.h @@ -0,0 +1,207 @@ +/**************************************************************************** + **************************************************************************** + *** + *** This header was automatically generated from a Linux kernel header + *** of the same name, to make information necessary for userspace to + *** call into the kernel available to libc. It contains only constants, + *** structures, and macros generated from the original header, and thus, + *** contains no copyrightable information. + *** + *** To edit the content of this header, modify the corresponding + *** source file (e.g. under external/kernel-headers/original/) then + *** run bionic/libc/kernel/tools/update_all.py + *** + *** Any manual change here will be lost the next time this script will + *** be run. You've been warned! + *** + **************************************************************************** + ****************************************************************************/ +#ifndef __MSM_VIDC_H__ +#define __MSM_VIDC_H__ +#include <linux/types.h> +struct msm_vidc_extradata_header { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned int size; + unsigned int:32; + unsigned int:32; + unsigned int type; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned int data_size; + unsigned char data[1]; +}; +struct msm_vidc_interlace_payload { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned int format; +}; +struct msm_vidc_framerate_payload { + unsigned int frame_rate; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +struct msm_vidc_ts_payload { + unsigned int timestamp_lo; + unsigned int timestamp_hi; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +struct msm_vidc_concealmb_payload { + unsigned int num_mbs; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct msm_vidc_recoverysei_payload { + unsigned int flags; +}; +struct msm_vidc_aspect_ratio_payload { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned int size; + unsigned int version; + unsigned int port_index; + unsigned int aspect_width; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned int aspect_height; +}; +struct msm_vidc_mpeg2_seqdisp_payload { + unsigned int video_format; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned int color_descp; + unsigned int color_primaries; + unsigned int transfer_char; + unsigned int matrix_coeffs; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned int disp_width; + unsigned int disp_height; +}; +struct msm_vidc_input_crop_payload { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned int size; + unsigned int version; + unsigned int port_index; + unsigned int left; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned int top; + unsigned int width; + unsigned int height; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct msm_vidc_digital_zoom_payload { + unsigned int size; + unsigned int version; + unsigned int port_index; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned int zoom_width; + unsigned int zoom_height; +}; +struct msm_vidc_extradata_index { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned int type; + union { + struct msm_vidc_input_crop_payload input_crop; + struct msm_vidc_digital_zoom_payload digital_zoom; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + struct msm_vidc_aspect_ratio_payload aspect_ratio; + }; +}; +struct msm_vidc_panscan_window { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned int panscan_height_offset; + unsigned int panscan_width_offset; + unsigned int panscan_window_width; + unsigned int panscan_window_height; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +struct msm_vidc_panscan_window_payload { + unsigned int num_panscan_windows; + struct msm_vidc_panscan_window wnd[1]; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +struct msm_vidc_stream_userdata_payload { + unsigned int type; + unsigned int data[1]; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +struct msm_vidc_frame_qp_payload { + unsigned int frame_qp; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct msm_vidc_frame_bits_info_payload { + unsigned int frame_bits; + unsigned int header_bits; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct msm_vidc_s3d_frame_packing_payload { + unsigned int fpa_id; + unsigned int cancel_flag; + unsigned int fpa_type; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned int quin_cunx_flag; + unsigned int content_interprtation_type; + unsigned int spatial_flipping_flag; + unsigned int frame0_flipped_flag; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned int field_views_flag; + unsigned int current_frame_is_frame0_flag; + unsigned int frame0_self_contained_flag; + unsigned int frame1_self_contained_flag; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned int frame0_graid_pos_x; + unsigned int frame0_graid_pos_y; + unsigned int frame1_graid_pos_x; + unsigned int frame1_graid_pos_y; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned int fpa_reserved_byte; + unsigned int fpa_repetition_period; + unsigned int fpa_extension_flag; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +enum msm_vidc_extradata_type { + MSM_VIDC_EXTRADATA_NONE = 0x00000000, + MSM_VIDC_EXTRADATA_MB_QUANTIZATION = 0x00000001, + MSM_VIDC_EXTRADATA_INTERLACE_VIDEO = 0x00000002, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + MSM_VIDC_EXTRADATA_VC1_FRAMEDISP = 0x00000003, + MSM_VIDC_EXTRADATA_VC1_SEQDISP = 0x00000004, + MSM_VIDC_EXTRADATA_TIMESTAMP = 0x00000005, + MSM_VIDC_EXTRADATA_S3D_FRAME_PACKING = 0x00000006, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + MSM_VIDC_EXTRADATA_FRAME_RATE = 0x00000007, + MSM_VIDC_EXTRADATA_PANSCAN_WINDOW = 0x00000008, + MSM_VIDC_EXTRADATA_RECOVERY_POINT_SEI = 0x00000009, + MSM_VIDC_EXTRADATA_MPEG2_SEQDISP = 0x0000000D, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + MSM_VIDC_EXTRADATA_STREAM_USERDATA = 0x0000000E, + MSM_VIDC_EXTRADATA_FRAME_QP = 0x0000000F, + MSM_VIDC_EXTRADATA_FRAME_BITS_INFO = 0x00000010, + MSM_VIDC_EXTRADATA_INPUT_CROP = 0x0700000E, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + MSM_VIDC_EXTRADATA_DIGITAL_ZOOM = 0x07000010, + MSM_VIDC_EXTRADATA_MULTISLICE_INFO = 0x7F100000, + MSM_VIDC_EXTRADATA_NUM_CONCEALED_MB = 0x7F100001, + MSM_VIDC_EXTRADATA_INDEX = 0x7F100002, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + MSM_VIDC_EXTRADATA_ASPECT_RATIO = 0x7F100003, + MSM_VIDC_EXTRADATA_METADATA_LTR = 0x7F100004, + MSM_VIDC_EXTRADATA_METADATA_FILLER = 0x7FE00002, + MSM_VIDC_EXTRADATA_METADATA_MBI = 0x7F100005, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +enum msm_vidc_interlace_type { + MSM_VIDC_INTERLACE_FRAME_PROGRESSIVE = 0x01, + MSM_VIDC_INTERLACE_INTERLEAVE_FRAME_TOPFIELDFIRST = 0x02, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + MSM_VIDC_INTERLACE_INTERLEAVE_FRAME_BOTTOMFIELDFIRST = 0x04, + MSM_VIDC_INTERLACE_FRAME_TOPFIELDFIRST = 0x08, + MSM_VIDC_INTERLACE_FRAME_BOTTOMFIELDFIRST = 0x10, +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +enum msm_vidc_recovery_sei { + MSM_VIDC_FRAME_RECONSTRUCTION_INCORRECT = 0x0, + MSM_VIDC_FRAME_RECONSTRUCTION_CORRECT = 0x01, + MSM_VIDC_FRAME_RECONSTRUCTION_APPROXIMATELY_CORRECT = 0x02, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +enum msm_vidc_userdata_type { + MSM_VIDC_USERDATA_TYPE_FRAME = 0x1, + MSM_VIDC_USERDATA_TYPE_TOP_FIELD = 0x2, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + MSM_VIDC_USERDATA_TYPE_BOTTOM_FIELD = 0x3, +}; +#endif + diff --git a/kernel-headers/media/msm_vpu.h b/kernel-headers/media/msm_vpu.h new file mode 100644 index 0000000..9892dca --- /dev/null +++ b/kernel-headers/media/msm_vpu.h @@ -0,0 +1,225 @@ +/**************************************************************************** + **************************************************************************** + *** + *** This header was automatically generated from a Linux kernel header + *** of the same name, to make information necessary for userspace to + *** call into the kernel available to libc. It contains only constants, + *** structures, and macros generated from the original header, and thus, + *** contains no copyrightable information. + *** + *** To edit the content of this header, modify the corresponding + *** source file (e.g. under external/kernel-headers/original/) then + *** run bionic/libc/kernel/tools/update_all.py + *** + *** Any manual change here will be lost the next time this script will + *** be run. You've been warned! + *** + **************************************************************************** + ****************************************************************************/ +#ifndef _H_MSM_VPU_H_ +#define _H_MSM_VPU_H_ +#include <linux/videodev2.h> +#define V4L2_BUF_FLAG_CDS_ENABLE 0x10000000 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_PLANE_MEM_OFFSET 0 +enum vpu_colorspace { + VPU_CS_MIN = 0, + VPU_CS_RGB_FULL = 1, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + VPU_CS_RGB_LIMITED = 2, + VPU_CS_REC601_FULL = 3, + VPU_CS_REC601_LIMITED = 4, + VPU_CS_REC709_FULL = 5, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + VPU_CS_REC709_LIMITED = 6, + VPU_CS_SMPTE240_FULL = 7, + VPU_CS_SMPTE240_LIMITED = 8, + VPU_CS_MAX = 9, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +#define VPU_FMT_EXT_FLAG_BT 1 +#define VPU_FMT_EXT_FLAG_TB 2 +#define VPU_FMT_EXT_FLAG_3D 4 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct v4l2_format_vpu_extension { + __u8 flag; + __u8 gap_in_lines; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_PIX_FMT_XRGB2 v4l2_fourcc('X', 'R', 'G', '2') +#define V4L2_PIX_FMT_XBGR2 v4l2_fourcc('X', 'B', 'G', '2') +#define V4L2_PIX_FMT_YUYV10 v4l2_fourcc('Y', 'U', 'Y', 'L') +#define V4L2_PIX_FMT_YUV8 v4l2_fourcc('Y', 'U', 'V', '8') +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_PIX_FMT_YUV10 v4l2_fourcc('Y', 'U', 'V', 'L') +#define V4L2_PIX_FMT_YUYV10BWC v4l2_fourcc('Y', 'B', 'W', 'C') +#define VPU_INPUT_TYPE_HOST 0 +#define VPU_INPUT_TYPE_VCAP 1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VPU_OUTPUT_TYPE_HOST 0 +#define VPU_OUTPUT_TYPE_DISPLAY 1 +#define VPU_PIPE_VCAP0 (1 << 16) +#define VPU_PIPE_VCAP1 (1 << 17) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VPU_PIPE_DISPLAY0 (1 << 18) +#define VPU_PIPE_DISPLAY1 (1 << 19) +#define VPU_PIPE_DISPLAY2 (1 << 20) +#define VPU_PIPE_DISPLAY3 (1 << 21) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VPU_PRIVATE_EVENT_BASE (V4L2_EVENT_PRIVATE_START + 6 * 1000) +enum VPU_PRIVATE_EVENT { + VPU_EVENT_START = VPU_PRIVATE_EVENT_BASE, + VPU_EVENT_FLUSH_DONE = VPU_EVENT_START + 1, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + VPU_EVENT_ACTIVE_REGION_CHANGED = VPU_EVENT_START + 2, + VPU_EVENT_SESSION_TIMESTAMP = VPU_EVENT_START + 3, + VPU_EVENT_SESSION_CREATED = VPU_EVENT_START + 4, + VPU_EVENT_SESSION_FREED = VPU_EVENT_START + 5, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + VPU_EVENT_SESSION_CLIENT_EXITED = VPU_EVENT_START + 6, + VPU_EVENT_HW_ERROR = VPU_EVENT_START + 11, + VPU_EVENT_INVALID_CONFIG = VPU_EVENT_START + 12, + VPU_EVENT_FAILED_SESSION_STREAMING = VPU_EVENT_START + 13, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + VPU_EVENT_END +}; +struct vpu_ctrl_standard { + __u32 enable; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __s32 value; +}; +struct vpu_ctrl_auto_manual { + __u32 enable; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u32 auto_mode; + __s32 value; +}; +struct vpu_ctrl_range_mapping { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u32 enable; + __u32 y_range; + __u32 uv_range; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VPU_ACTIVE_REGION_N_EXCLUSIONS 1 +struct vpu_ctrl_active_region_param { + __u32 enable; + __u32 num_exclusions; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + struct v4l2_rect detection_region; + struct v4l2_rect excluded_regions[VPU_ACTIVE_REGION_N_EXCLUSIONS]; +}; +struct vpu_ctrl_deinterlacing_mode { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u32 field_polarity; + __u32 mvp_mode; +}; +struct vpu_ctrl_hqv { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u32 enable; + __u32 sharpen_strength; + __u32 auto_nr_strength; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct vpu_info_frame_timestamp { + __u32 pts_low; + __u32 pts_high; + __u32 qtime_low; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u32 qtime_high; +}; +struct vpu_control { + __u32 control_id; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + union control_data { + __s32 value; + struct vpu_ctrl_standard standard; + struct vpu_ctrl_auto_manual auto_manual; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + struct vpu_ctrl_range_mapping range_mapping; + struct vpu_ctrl_active_region_param active_region_param; + struct v4l2_rect active_region_result; + struct vpu_ctrl_deinterlacing_mode deinterlacing_mode; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + struct vpu_ctrl_hqv hqv; + struct vpu_info_frame_timestamp timestamp; + __u8 reserved[124]; + } data; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +#define VPU_CTRL_ID_MIN 0 +#define VPU_CTRL_NOISE_REDUCTION 1 +#define VPU_CTRL_IMAGE_ENHANCEMENT 2 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VPU_CTRL_ANAMORPHIC_SCALING 3 +#define VPU_CTRL_DIRECTIONAL_INTERPOLATION 4 +#define VPU_CTRL_BACKGROUND_COLOR 5 +#define VPU_CTRL_RANGE_MAPPING 6 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VPU_CTRL_DEINTERLACING_MODE 7 +#define VPU_CTRL_ACTIVE_REGION_PARAM 8 +#define VPU_CTRL_ACTIVE_REGION_RESULT 9 +#define VPU_CTRL_PRIORITY 10 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VPU_CTRL_CONTENT_PROTECTION 11 +#define VPU_CTRL_DISPLAY_REFRESH_RATE 12 +#define VPU_CTRL_HQV 20 +#define VPU_CTRL_HQV_SHARPEN 21 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VPU_CTRL_HQV_AUTONR 22 +#define VPU_CTRL_ACE 23 +#define VPU_CTRL_ACE_BRIGHTNESS 24 +#define VPU_CTRL_ACE_CONTRAST 25 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VPU_CTRL_2D3D 26 +#define VPU_CTRL_2D3D_DEPTH 27 +#define VPU_CTRL_FRC 28 +#define VPU_CTRL_FRC_MOTION_SMOOTHNESS 29 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VPU_CTRL_FRC_MOTION_CLEAR 30 +#define VPU_INFO_TIMESTAMP 35 +#define VPU_CTRL_TIMESTAMP_INFO_MODE 36 +#define VPU_INFO_STATISTICS 37 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VPU_CTRL_LATENCY 38 +#define VPU_CTRL_LATENCY_MODE 39 +#define VPU_CTRL_ID_MAX 40 +#define VPU_MAX_EXT_DATA_SIZE 720 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct vpu_control_extended { + __u32 type; + __u32 data_len; + void __user *data_ptr; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u32 buf_size; + void __user *buf_ptr; +}; +struct vpu_control_port { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u32 control_id; + __u32 port; + union control_port_data { + __u32 framerate; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + } data; +}; +#define VPU_CTRL_FPS 1000 +#define VPU_ATTACH_TO_SESSION _IOW('V', (BASE_VIDIOC_PRIVATE + 1), int) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VPU_QUERY_SESSIONS _IOR('V', (BASE_VIDIOC_PRIVATE + 0), int) +#define VPU_CREATE_SESSION _IOR('V', (BASE_VIDIOC_PRIVATE + 2), int) +#define VPU_JOIN_SESSION _IOW('V', (BASE_VIDIOC_PRIVATE + 3), int) +#define VPU_CREATE_OUTPUT2 _IO('V', (BASE_VIDIOC_PRIVATE + 5)) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VPU_COMMIT_CONFIGURATION _IO('V', (BASE_VIDIOC_PRIVATE + 10)) +#define VPU_FLUSH_BUFS _IOW('V', (BASE_VIDIOC_PRIVATE + 15), enum v4l2_buf_type) +#define VPU_G_CONTROL _IOWR('V', (BASE_VIDIOC_PRIVATE + 20), struct vpu_control) +#define VPU_S_CONTROL _IOW('V', (BASE_VIDIOC_PRIVATE + 21), struct vpu_control) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VPU_G_CONTROL_EXTENDED _IOWR('V', (BASE_VIDIOC_PRIVATE + 22), struct vpu_control_extended) +#define VPU_S_CONTROL_EXTENDED _IOW('V', (BASE_VIDIOC_PRIVATE + 23), struct vpu_control_extended) +#define VPU_G_CONTROL_PORT _IOWR('V', (BASE_VIDIOC_PRIVATE + 24), struct vpu_control_port) +#define VPU_S_CONTROL_PORT _IOW('V', (BASE_VIDIOC_PRIVATE + 25), struct vpu_control_port) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#endif + diff --git a/kernel-headers/media/msmb_camera.h b/kernel-headers/media/msmb_camera.h new file mode 100644 index 0000000..07fc439 --- /dev/null +++ b/kernel-headers/media/msmb_camera.h @@ -0,0 +1,157 @@ +/**************************************************************************** + **************************************************************************** + *** + *** This header was automatically generated from a Linux kernel header + *** of the same name, to make information necessary for userspace to + *** call into the kernel available to libc. It contains only constants, + *** structures, and macros generated from the original header, and thus, + *** contains no copyrightable information. + *** + *** To edit the content of this header, modify the corresponding + *** source file (e.g. under external/kernel-headers/original/) then + *** run bionic/libc/kernel/tools/update_all.py + *** + *** Any manual change here will be lost the next time this script will + *** be run. You've been warned! + *** + **************************************************************************** + ****************************************************************************/ +#ifndef __LINUX_MSMB_CAMERA_H +#define __LINUX_MSMB_CAMERA_H +#include <linux/videodev2.h> +#include <linux/types.h> +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#include <linux/ioctl.h> +#define MSM_CAM_V4L2_IOCTL_NOTIFY _IOW('V', BASE_VIDIOC_PRIVATE + 30, struct msm_v4l2_event_data) +#define MSM_CAM_V4L2_IOCTL_NOTIFY_META _IOW('V', BASE_VIDIOC_PRIVATE + 31, struct msm_v4l2_event_data) +#define MSM_CAM_V4L2_IOCTL_CMD_ACK _IOW('V', BASE_VIDIOC_PRIVATE + 32, struct msm_v4l2_event_data) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define MSM_CAM_V4L2_IOCTL_NOTIFY_ERROR _IOW('V', BASE_VIDIOC_PRIVATE + 33, struct msm_v4l2_event_data) +#define QCAMERA_DEVICE_GROUP_ID 1 +#define QCAMERA_VNODE_GROUP_ID 2 +#define MSM_CAMERA_NAME "msm_camera" +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define MSM_CONFIGURATION_NAME "msm_config" +#define MSM_CAMERA_SUBDEV_CSIPHY 0 +#define MSM_CAMERA_SUBDEV_CSID 1 +#define MSM_CAMERA_SUBDEV_ISPIF 2 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define MSM_CAMERA_SUBDEV_VFE 3 +#define MSM_CAMERA_SUBDEV_AXI 4 +#define MSM_CAMERA_SUBDEV_VPE 5 +#define MSM_CAMERA_SUBDEV_SENSOR 6 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define MSM_CAMERA_SUBDEV_ACTUATOR 7 +#define MSM_CAMERA_SUBDEV_EEPROM 8 +#define MSM_CAMERA_SUBDEV_CPP 9 +#define MSM_CAMERA_SUBDEV_CCI 10 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define MSM_CAMERA_SUBDEV_LED_FLASH 11 +#define MSM_CAMERA_SUBDEV_STROBE_FLASH 12 +#define MSM_CAMERA_SUBDEV_BUF_MNGR 13 +#define MSM_CAMERA_SUBDEV_SENSOR_INIT 14 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define MSM_CAMERA_SUBDEV_OIS 15 +#define MSM_CAMERA_SUBDEV_FLASH 16 +#define MSM_MAX_CAMERA_SENSORS 5 +#define MSM_CAMERA_MAX_STREAM_BUF 40 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define MSM_CAMERA_FEATURE_BASE 0x00010000 +#define MSM_CAMERA_FEATURE_SHUTDOWN (MSM_CAMERA_FEATURE_BASE + 1) +#define MSM_CAMERA_STATUS_BASE 0x00020000 +#define MSM_CAMERA_STATUS_FAIL (MSM_CAMERA_STATUS_BASE + 1) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define MSM_CAMERA_STATUS_SUCCESS (MSM_CAMERA_STATUS_BASE + 2) +#define MSM_CAMERA_V4L2_EVENT_TYPE (V4L2_EVENT_PRIVATE_START + 0x00002000) +#define MSM_CAMERA_EVENT_MIN 0 +#define MSM_CAMERA_NEW_SESSION (MSM_CAMERA_EVENT_MIN + 1) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define MSM_CAMERA_DEL_SESSION (MSM_CAMERA_EVENT_MIN + 2) +#define MSM_CAMERA_SET_PARM (MSM_CAMERA_EVENT_MIN + 3) +#define MSM_CAMERA_GET_PARM (MSM_CAMERA_EVENT_MIN + 4) +#define MSM_CAMERA_MAPPING_CFG (MSM_CAMERA_EVENT_MIN + 5) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define MSM_CAMERA_MAPPING_SES (MSM_CAMERA_EVENT_MIN + 6) +#define MSM_CAMERA_MSM_NOTIFY (MSM_CAMERA_EVENT_MIN + 7) +#define MSM_CAMERA_EVENT_MAX (MSM_CAMERA_EVENT_MIN + 8) +#define MSM_CAMERA_PRIV_S_CROP (V4L2_CID_PRIVATE_BASE + 1) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define MSM_CAMERA_PRIV_G_CROP (V4L2_CID_PRIVATE_BASE + 2) +#define MSM_CAMERA_PRIV_G_FMT (V4L2_CID_PRIVATE_BASE + 3) +#define MSM_CAMERA_PRIV_S_FMT (V4L2_CID_PRIVATE_BASE + 4) +#define MSM_CAMERA_PRIV_TRY_FMT (V4L2_CID_PRIVATE_BASE + 5) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define MSM_CAMERA_PRIV_METADATA (V4L2_CID_PRIVATE_BASE + 6) +#define MSM_CAMERA_PRIV_QUERY_CAP (V4L2_CID_PRIVATE_BASE + 7) +#define MSM_CAMERA_PRIV_STREAM_ON (V4L2_CID_PRIVATE_BASE + 8) +#define MSM_CAMERA_PRIV_STREAM_OFF (V4L2_CID_PRIVATE_BASE + 9) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define MSM_CAMERA_PRIV_NEW_STREAM (V4L2_CID_PRIVATE_BASE + 10) +#define MSM_CAMERA_PRIV_DEL_STREAM (V4L2_CID_PRIVATE_BASE + 11) +#define MSM_CAMERA_PRIV_SHUTDOWN (V4L2_CID_PRIVATE_BASE + 12) +#define MSM_CAMERA_PRIV_STREAM_INFO_SYNC (V4L2_CID_PRIVATE_BASE + 13) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define MSM_CAMERA_CMD_SUCESS 0x00000001 +#define MSM_CAMERA_BUF_MAP_SUCESS 0x00000002 +#define MSM_CAMERA_ERR_EVT_BASE 0x00010000 +#define MSM_CAMERA_ERR_CMD_FAIL (MSM_CAMERA_ERR_EVT_BASE + 1) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define MSM_CAMERA_ERR_MAPPING (MSM_CAMERA_ERR_EVT_BASE + 2) +struct msm_v4l2_event_data { + unsigned int command; + unsigned int status; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned int session_id; + unsigned int stream_id; + unsigned int map_op; + unsigned int map_buf_idx; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned int notify; + unsigned int arg_value; + unsigned int ret_value; + unsigned int v4l2_event_type; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned int v4l2_event_id; + unsigned int nop5; + unsigned int nop6; + unsigned int nop7; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned int nop8; + unsigned int nop9; +}; +struct msm_v4l2_format_data { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + enum v4l2_buf_type type; + unsigned int width; + unsigned int height; + unsigned int pixelformat; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned char num_planes; + unsigned int plane_sizes[VIDEO_MAX_PLANES]; +}; +#define msm_v4l2_fourcc(a, b, c, d) ((__u32)(a) | ((__u32)(b) << 8) | ((__u32)(c) << 16) | ((__u32)(d) << 24)) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define MSM_V4L2_PIX_FMT_STATS_COMB v4l2_fourcc('S', 'T', 'C', 'M') +#define MSM_V4L2_PIX_FMT_STATS_AE v4l2_fourcc('S', 'T', 'A', 'E') +#define MSM_V4L2_PIX_FMT_STATS_AF v4l2_fourcc('S', 'T', 'A', 'F') +#define MSM_V4L2_PIX_FMT_STATS_AWB v4l2_fourcc('S', 'T', 'W', 'B') +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define MSM_V4L2_PIX_FMT_STATS_IHST v4l2_fourcc('I', 'H', 'S', 'T') +#define MSM_V4L2_PIX_FMT_STATS_CS v4l2_fourcc('S', 'T', 'C', 'S') +#define MSM_V4L2_PIX_FMT_STATS_RS v4l2_fourcc('S', 'T', 'R', 'S') +#define MSM_V4L2_PIX_FMT_STATS_BG v4l2_fourcc('S', 'T', 'B', 'G') +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define MSM_V4L2_PIX_FMT_STATS_BF v4l2_fourcc('S', 'T', 'B', 'F') +#define MSM_V4L2_PIX_FMT_STATS_BHST v4l2_fourcc('B', 'H', 'S', 'T') +enum smmu_attach_mode { + NON_SECURE_MODE, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + SECURE_MODE, + MAX_PROTECTION_MODE, +}; +struct msm_camera_smmu_attach_type { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + enum smmu_attach_mode attach; +}; +#endif + diff --git a/kernel-headers/media/msmb_generic_buf_mgr.h b/kernel-headers/media/msmb_generic_buf_mgr.h new file mode 100644 index 0000000..5b6c6fb --- /dev/null +++ b/kernel-headers/media/msmb_generic_buf_mgr.h @@ -0,0 +1,40 @@ +/**************************************************************************** + **************************************************************************** + *** + *** This header was automatically generated from a Linux kernel header + *** of the same name, to make information necessary for userspace to + *** call into the kernel available to libc. It contains only constants, + *** structures, and macros generated from the original header, and thus, + *** contains no copyrightable information. + *** + *** To edit the content of this header, modify the corresponding + *** source file (e.g. under external/kernel-headers/original/) then + *** run bionic/libc/kernel/tools/update_all.py + *** + *** Any manual change here will be lost the next time this script will + *** be run. You've been warned! + *** + **************************************************************************** + ****************************************************************************/ +#ifndef __UAPI_MEDIA_MSMB_BUF_MNGR_H__ +#define __UAPI_MEDIA_MSMB_BUF_MNGR_H__ +struct msm_buf_mngr_info { + uint32_t session_id; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t stream_id; + uint32_t frame_id; + struct timeval timestamp; + uint32_t index; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t reserved; +}; +struct v4l2_subdev *msm_buf_mngr_get_subdev(void); +#define VIDIOC_MSM_BUF_MNGR_GET_BUF _IOWR('V', BASE_VIDIOC_PRIVATE + 33, struct msm_buf_mngr_info) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VIDIOC_MSM_BUF_MNGR_PUT_BUF _IOWR('V', BASE_VIDIOC_PRIVATE + 34, struct msm_buf_mngr_info) +#define VIDIOC_MSM_BUF_MNGR_BUF_DONE _IOWR('V', BASE_VIDIOC_PRIVATE + 35, struct msm_buf_mngr_info) +#define VIDIOC_MSM_BUF_MNGR_INIT _IOWR('V', BASE_VIDIOC_PRIVATE + 36, struct msm_buf_mngr_info) +#define VIDIOC_MSM_BUF_MNGR_DEINIT _IOWR('V', BASE_VIDIOC_PRIVATE + 37, struct msm_buf_mngr_info) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#endif + diff --git a/kernel-headers/media/msmb_isp.h b/kernel-headers/media/msmb_isp.h new file mode 100644 index 0000000..bc468a1 --- /dev/null +++ b/kernel-headers/media/msmb_isp.h @@ -0,0 +1,641 @@ +/**************************************************************************** + **************************************************************************** + *** + *** This header was automatically generated from a Linux kernel header + *** of the same name, to make information necessary for userspace to + *** call into the kernel available to libc. It contains only constants, + *** structures, and macros generated from the original header, and thus, + *** contains no copyrightable information. + *** + *** To edit the content of this header, modify the corresponding + *** source file (e.g. under external/kernel-headers/original/) then + *** run bionic/libc/kernel/tools/update_all.py + *** + *** Any manual change here will be lost the next time this script will + *** be run. You've been warned! + *** + **************************************************************************** + ****************************************************************************/ +#ifndef __MSMB_ISP__ +#define __MSMB_ISP__ +#include <linux/videodev2.h> +#define MAX_PLANES_PER_STREAM 3 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define MAX_NUM_STREAM 7 +#define ISP_VERSION_47 47 +#define ISP_VERSION_46 46 +#define ISP_VERSION_44 44 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define ISP_VERSION_40 40 +#define ISP_VERSION_32 32 +#define ISP_NATIVE_BUF_BIT (0x10000 << 0) +#define ISP0_BIT (0x10000 << 1) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define ISP1_BIT (0x10000 << 2) +#define ISP_META_CHANNEL_BIT (0x10000 << 3) +#define ISP_SCRATCH_BUF_BIT (0x10000 << 4) +#define ISP_STATS_STREAM_BIT 0x80000000 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct msm_vfe_cfg_cmd_list; +enum ISP_START_PIXEL_PATTERN { + ISP_BAYER_RGRGRG, + ISP_BAYER_GRGRGR, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + ISP_BAYER_BGBGBG, + ISP_BAYER_GBGBGB, + ISP_YUV_YCbYCr, + ISP_YUV_YCrYCb, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + ISP_YUV_CbYCrY, + ISP_YUV_CrYCbY, + ISP_PIX_PATTERN_MAX +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +enum msm_vfe_plane_fmt { + Y_PLANE, + CB_PLANE, + CR_PLANE, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + CRCB_PLANE, + CBCR_PLANE, + VFE_PLANE_FMT_MAX +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +enum msm_vfe_input_src { + VFE_PIX_0, + VFE_RAW_0, + VFE_RAW_1, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + VFE_RAW_2, + VFE_SRC_MAX, +}; +enum msm_vfe_axi_stream_src { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + PIX_ENCODER, + PIX_VIEWFINDER, + PIX_VIDEO, + CAMIF_RAW, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + IDEAL_RAW, + RDI_INTF_0, + RDI_INTF_1, + RDI_INTF_2, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + VFE_AXI_SRC_MAX +}; +enum msm_vfe_frame_skip_pattern { + NO_SKIP, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + EVERY_2FRAME, + EVERY_3FRAME, + EVERY_4FRAME, + EVERY_5FRAME, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + EVERY_6FRAME, + EVERY_7FRAME, + EVERY_8FRAME, + EVERY_16FRAME, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + EVERY_32FRAME, + SKIP_ALL, + SKIP_RANGE, + MAX_SKIP, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +enum msm_isp_stats_type { + MSM_ISP_STATS_AEC, + MSM_ISP_STATS_AF, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + MSM_ISP_STATS_AWB, + MSM_ISP_STATS_RS, + MSM_ISP_STATS_CS, + MSM_ISP_STATS_IHIST, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + MSM_ISP_STATS_SKIN, + MSM_ISP_STATS_BG, + MSM_ISP_STATS_BF, + MSM_ISP_STATS_BE, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + MSM_ISP_STATS_BHIST, + MSM_ISP_STATS_BF_SCALE, + MSM_ISP_STATS_HDR_BE, + MSM_ISP_STATS_HDR_BHIST, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + MSM_ISP_STATS_MAX +}; +struct msm_isp_sw_framskip { + uint32_t stats_type_mask; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t stream_src_mask; + enum msm_vfe_frame_skip_pattern skip_mode; + uint32_t min_frame_id; + uint32_t max_frame_id; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +enum msm_vfe_testgen_color_pattern { + COLOR_BAR_8_COLOR, + UNICOLOR_WHITE, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + UNICOLOR_YELLOW, + UNICOLOR_CYAN, + UNICOLOR_GREEN, + UNICOLOR_MAGENTA, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + UNICOLOR_RED, + UNICOLOR_BLUE, + UNICOLOR_BLACK, + MAX_COLOR, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +enum msm_vfe_camif_input { + CAMIF_DISABLED, + CAMIF_PAD_REG_INPUT, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + CAMIF_MIDDI_INPUT, + CAMIF_MIPI_INPUT, +}; +struct msm_vfe_fetch_engine_cfg { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t input_format; + uint32_t buf_width; + uint32_t buf_height; + uint32_t fetch_width; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t fetch_height; + uint32_t x_offset; + uint32_t y_offset; + uint32_t buf_stride; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +struct msm_vfe_camif_cfg { + uint32_t lines_per_frame; + uint32_t pixels_per_line; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t first_pixel; + uint32_t last_pixel; + uint32_t first_line; + uint32_t last_line; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t epoch_line0; + uint32_t epoch_line1; + enum msm_vfe_camif_input camif_input; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct msm_vfe_testgen_cfg { + uint32_t lines_per_frame; + uint32_t pixels_per_line; + uint32_t v_blank; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t h_blank; + enum ISP_START_PIXEL_PATTERN pixel_bayer_pattern; + uint32_t rotate_period; + enum msm_vfe_testgen_color_pattern color_bar_pattern; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t burst_num_frame; +}; +enum msm_vfe_inputmux { + CAMIF, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + TESTGEN, + EXTERNAL_READ, +}; +enum msm_vfe_stats_composite_group { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + STATS_COMPOSITE_GRP_NONE, + STATS_COMPOSITE_GRP_1, + STATS_COMPOSITE_GRP_2, + STATS_COMPOSITE_GRP_MAX, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +struct msm_vfe_pix_cfg { + struct msm_vfe_camif_cfg camif_cfg; + struct msm_vfe_testgen_cfg testgen_cfg; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + struct msm_vfe_fetch_engine_cfg fetch_engine_cfg; + enum msm_vfe_inputmux input_mux; + enum ISP_START_PIXEL_PATTERN pixel_pattern; + uint32_t input_format; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +struct msm_vfe_rdi_cfg { + uint8_t cid; + uint8_t frame_based; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +struct msm_vfe_input_cfg { + union { + struct msm_vfe_pix_cfg pix_cfg; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + struct msm_vfe_rdi_cfg rdi_cfg; + } d; + enum msm_vfe_input_src input_src; + uint32_t input_pix_clk; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +struct msm_vfe_fetch_eng_start { + uint32_t session_id; + uint32_t stream_id; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t buf_idx; + uint32_t buf_addr; +}; +struct msm_vfe_axi_plane_cfg { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t output_width; + uint32_t output_height; + uint32_t output_stride; + uint32_t output_scan_lines; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t output_plane_format; + uint32_t plane_addr_offset; + uint8_t csid_src; + uint8_t rdi_cid; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +enum msm_stream_memory_input_t { + MEMORY_INPUT_DISABLED, + MEMORY_INPUT_ENABLED +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +struct msm_vfe_axi_stream_request_cmd { + uint32_t session_id; + uint32_t stream_id; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t vt_enable; + uint32_t output_format; + enum msm_vfe_axi_stream_src stream_src; + struct msm_vfe_axi_plane_cfg plane_cfg[MAX_PLANES_PER_STREAM]; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t burst_count; + uint32_t hfr_mode; + uint8_t frame_base; + uint32_t init_frame_drop; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + enum msm_vfe_frame_skip_pattern frame_skip_pattern; + uint8_t buf_divert; + uint32_t axi_stream_handle; + uint32_t controllable_output; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t burst_len; + enum msm_stream_memory_input_t memory_input; +}; +struct msm_vfe_axi_stream_release_cmd { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t stream_handle; +}; +enum msm_vfe_axi_stream_cmd { + STOP_STREAM, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + START_STREAM, + STOP_IMMEDIATELY, +}; +struct msm_vfe_axi_stream_cfg_cmd { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint8_t num_streams; + uint32_t stream_handle[MAX_NUM_STREAM]; + enum msm_vfe_axi_stream_cmd cmd; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +enum msm_vfe_axi_stream_update_type { + ENABLE_STREAM_BUF_DIVERT, + DISABLE_STREAM_BUF_DIVERT, + UPDATE_STREAM_FRAMEDROP_PATTERN, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + UPDATE_STREAM_STATS_FRAMEDROP_PATTERN, + UPDATE_STREAM_AXI_CONFIG, + UPDATE_STREAM_REQUEST_FRAMES, + UPDATE_STREAM_ADD_BUFQ, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + UPDATE_STREAM_REMOVE_BUFQ, + UPDATE_STREAM_SW_FRAME_DROP, +}; +enum msm_vfe_iommu_type { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + IOMMU_ATTACH, + IOMMU_DETACH, +}; +enum msm_vfe_buff_queue_id { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + VFE_BUF_QUEUE_DEFAULT, + VFE_BUF_QUEUE_SHARED, + VFE_BUF_QUEUE_MAX, +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct msm_vfe_axi_stream_cfg_update_info { + uint32_t stream_handle; + uint32_t output_format; + uint32_t user_stream_id; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + enum msm_vfe_frame_skip_pattern skip_pattern; + struct msm_vfe_axi_plane_cfg plane_cfg[MAX_PLANES_PER_STREAM]; + struct msm_isp_sw_framskip sw_skip_info; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct msm_vfe_axi_halt_cmd { + uint32_t stop_camif; + uint32_t overflow_detected; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct msm_vfe_axi_reset_cmd { + uint32_t blocking; + uint32_t frame_id; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct msm_vfe_axi_restart_cmd { + uint32_t enable_camif; +}; +struct msm_vfe_axi_stream_update_cmd { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t num_streams; + enum msm_vfe_axi_stream_update_type update_type; + struct msm_vfe_axi_stream_cfg_update_info + update_info[MSM_ISP_STATS_MAX]; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +struct msm_vfe_smmu_attach_cmd { + uint32_t security_mode; + uint32_t iommu_attach_mode; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +struct msm_vfe_stats_stream_request_cmd { + uint32_t session_id; + uint32_t stream_id; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + enum msm_isp_stats_type stats_type; + uint32_t composite_flag; + uint32_t framedrop_pattern; + uint32_t init_frame_drop; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t irq_subsample_pattern; + uint32_t buffer_offset; + uint32_t stream_handle; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct msm_vfe_stats_stream_release_cmd { + uint32_t stream_handle; +}; +struct msm_vfe_stats_stream_cfg_cmd { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint8_t num_streams; + uint32_t stream_handle[MSM_ISP_STATS_MAX]; + uint8_t enable; + uint32_t stats_burst_len; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +enum msm_vfe_reg_cfg_type { + VFE_WRITE, + VFE_WRITE_MB, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + VFE_READ, + VFE_CFG_MASK, + VFE_WRITE_DMI_16BIT, + VFE_WRITE_DMI_32BIT, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + VFE_WRITE_DMI_64BIT, + VFE_READ_DMI_16BIT, + VFE_READ_DMI_32BIT, + VFE_READ_DMI_64BIT, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + GET_MAX_CLK_RATE, + GET_CLK_RATES, + GET_ISP_ID, + VFE_HW_UPDATE_LOCK, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + VFE_HW_UPDATE_UNLOCK, + SET_WM_UB_SIZE, + SET_UB_POLICY, +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct msm_vfe_cfg_cmd2 { + uint16_t num_cfg; + uint16_t cmd_len; + void __user *cfg_data; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + void __user *cfg_cmd; +}; +struct msm_vfe_cfg_cmd_list { + struct msm_vfe_cfg_cmd2 cfg_cmd; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + struct msm_vfe_cfg_cmd_list *next; + uint32_t next_size; +}; +struct msm_vfe_reg_rw_info { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t reg_offset; + uint32_t cmd_data_offset; + uint32_t len; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct msm_vfe_reg_mask_info { + uint32_t reg_offset; + uint32_t mask; + uint32_t val; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +struct msm_vfe_reg_dmi_info { + uint32_t hi_tbl_offset; + uint32_t lo_tbl_offset; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t len; +}; +struct msm_vfe_reg_cfg_cmd { + union { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + struct msm_vfe_reg_rw_info rw_info; + struct msm_vfe_reg_mask_info mask_info; + struct msm_vfe_reg_dmi_info dmi_info; + } u; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + enum msm_vfe_reg_cfg_type cmd_type; +}; +enum msm_isp_buf_type { + ISP_PRIVATE_BUF, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + ISP_SHARE_BUF, + MAX_ISP_BUF_TYPE, +}; +struct msm_isp_buf_request { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t session_id; + uint32_t stream_id; + uint8_t num_buf; + uint32_t handle; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + enum msm_isp_buf_type buf_type; +}; +struct msm_isp_qbuf_plane { + uint32_t addr; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t offset; + uint32_t length; +}; +struct msm_isp_qbuf_buffer { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + struct msm_isp_qbuf_plane planes[MAX_PLANES_PER_STREAM]; + uint32_t num_planes; +}; +struct msm_isp_qbuf_info { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t handle; + int32_t buf_idx; + struct msm_isp_qbuf_buffer buffer; + uint32_t dirty_buf; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +struct msm_isp_clk_rates { + uint32_t nominal_rate; + uint32_t high_rate; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +struct msm_vfe_axi_src_state { + enum msm_vfe_input_src input_src; + uint32_t src_active; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t src_frame_id; +}; +enum msm_isp_event_idx { + ISP_REG_UPDATE = 0, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + ISP_EPOCH_0 = 1, + ISP_EPOCH_1 = 2, + ISP_START_ACK = 3, + ISP_STOP_ACK = 4, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + ISP_IRQ_VIOLATION = 5, + ISP_WM_BUS_OVERFLOW = 6, + ISP_STATS_OVERFLOW = 7, + ISP_CAMIF_ERROR = 8, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + ISP_BUF_DONE = 9, + ISP_FE_RD_DONE = 10, + ISP_EVENT_MAX = 11 +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define ISP_EVENT_OFFSET 8 +#define ISP_EVENT_BASE (V4L2_EVENT_PRIVATE_START) +#define ISP_BUF_EVENT_BASE (ISP_EVENT_BASE + (1 << ISP_EVENT_OFFSET)) +#define ISP_STATS_EVENT_BASE (ISP_EVENT_BASE + (2 << ISP_EVENT_OFFSET)) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define ISP_CAMIF_EVENT_BASE (ISP_EVENT_BASE + (3 << ISP_EVENT_OFFSET)) +#define ISP_STREAM_EVENT_BASE (ISP_EVENT_BASE + (4 << ISP_EVENT_OFFSET)) +#define ISP_EVENT_REG_UPDATE (ISP_EVENT_BASE + ISP_REG_UPDATE) +#define ISP_EVENT_EPOCH_0 (ISP_EVENT_BASE + ISP_EPOCH_0) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define ISP_EVENT_EPOCH_1 (ISP_EVENT_BASE + ISP_EPOCH_1) +#define ISP_EVENT_START_ACK (ISP_EVENT_BASE + ISP_START_ACK) +#define ISP_EVENT_STOP_ACK (ISP_EVENT_BASE + ISP_STOP_ACK) +#define ISP_EVENT_IRQ_VIOLATION (ISP_EVENT_BASE + ISP_IRQ_VIOLATION) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define ISP_EVENT_WM_BUS_OVERFLOW (ISP_EVENT_BASE + ISP_WM_BUS_OVERFLOW) +#define ISP_EVENT_STATS_OVERFLOW (ISP_EVENT_BASE + ISP_STATS_OVERFLOW) +#define ISP_EVENT_CAMIF_ERROR (ISP_EVENT_BASE + ISP_CAMIF_ERROR) +#define ISP_EVENT_SOF (ISP_CAMIF_EVENT_BASE) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define ISP_EVENT_EOF (ISP_CAMIF_EVENT_BASE + 1) +#define ISP_EVENT_BUF_DONE (ISP_EVENT_BASE + ISP_BUF_DONE) +#define ISP_EVENT_BUF_DIVERT (ISP_BUF_EVENT_BASE) +#define ISP_EVENT_STATS_NOTIFY (ISP_STATS_EVENT_BASE) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define ISP_EVENT_COMP_STATS_NOTIFY (ISP_EVENT_STATS_NOTIFY + MSM_ISP_STATS_MAX) +#define ISP_EVENT_FE_READ_DONE (ISP_EVENT_BASE + ISP_FE_RD_DONE) +#define ISP_EVENT_STREAM_UPDATE_DONE (ISP_STREAM_EVENT_BASE) +struct msm_isp_buf_event { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t session_id; + uint32_t stream_id; + uint32_t handle; + uint32_t output_format; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + int8_t buf_idx; +}; +struct msm_isp_stats_event { + uint32_t stats_mask; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint8_t stats_buf_idxs[MSM_ISP_STATS_MAX]; +}; +struct msm_isp_stream_ack { + uint32_t session_id; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t stream_id; + uint32_t handle; +}; +struct msm_isp_error_info { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t error_mask; +}; +struct msm_isp_event_data { + struct timeval timestamp; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + struct timeval mono_timestamp; + enum msm_vfe_input_src input_intf; + uint32_t frame_id; + union { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + struct msm_isp_stats_event stats; + struct msm_isp_buf_event buf_done; + struct msm_isp_error_info error_info; + } u; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +#define V4L2_PIX_FMT_QBGGR8 v4l2_fourcc('Q', 'B', 'G', '8') +#define V4L2_PIX_FMT_QGBRG8 v4l2_fourcc('Q', 'G', 'B', '8') +#define V4L2_PIX_FMT_QGRBG8 v4l2_fourcc('Q', 'G', 'R', '8') +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_PIX_FMT_QRGGB8 v4l2_fourcc('Q', 'R', 'G', '8') +#define V4L2_PIX_FMT_QBGGR10 v4l2_fourcc('Q', 'B', 'G', '0') +#define V4L2_PIX_FMT_QGBRG10 v4l2_fourcc('Q', 'G', 'B', '0') +#define V4L2_PIX_FMT_QGRBG10 v4l2_fourcc('Q', 'G', 'R', '0') +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_PIX_FMT_QRGGB10 v4l2_fourcc('Q', 'R', 'G', '0') +#define V4L2_PIX_FMT_QBGGR12 v4l2_fourcc('Q', 'B', 'G', '2') +#define V4L2_PIX_FMT_QGBRG12 v4l2_fourcc('Q', 'G', 'B', '2') +#define V4L2_PIX_FMT_QGRBG12 v4l2_fourcc('Q', 'G', 'R', '2') +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_PIX_FMT_QRGGB12 v4l2_fourcc('Q', 'R', 'G', '2') +#define V4L2_PIX_FMT_QBGGR14 v4l2_fourcc('Q', 'B', 'G', '4') +#define V4L2_PIX_FMT_QGBRG14 v4l2_fourcc('Q', 'G', 'B', '4') +#define V4L2_PIX_FMT_QGRBG14 v4l2_fourcc('Q', 'G', 'R', '4') +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_PIX_FMT_QRGGB14 v4l2_fourcc('Q', 'R', 'G', '4') +#define V4L2_PIX_FMT_P16BGGR10 v4l2_fourcc('P', 'B', 'G', '0') +#define V4L2_PIX_FMT_P16GBRG10 v4l2_fourcc('P', 'G', 'B', '0') +#define V4L2_PIX_FMT_P16GRBG10 v4l2_fourcc('P', 'G', 'R', '0') +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_PIX_FMT_P16RGGB10 v4l2_fourcc('P', 'R', 'G', '0') +#define V4L2_PIX_FMT_NV14 v4l2_fourcc('N', 'V', '1', '4') +#define V4L2_PIX_FMT_NV41 v4l2_fourcc('N', 'V', '4', '1') +#define V4L2_PIX_FMT_META v4l2_fourcc('Q', 'M', 'E', 'T') +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define V4L2_PIX_FMT_SBGGR14 v4l2_fourcc('B', 'G', '1', '4') +#define V4L2_PIX_FMT_SGBRG14 v4l2_fourcc('G', 'B', '1', '4') +#define V4L2_PIX_FMT_SGRBG14 v4l2_fourcc('B', 'A', '1', '4') +#define V4L2_PIX_FMT_SRGGB14 v4l2_fourcc('R', 'G', '1', '4') +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VIDIOC_MSM_VFE_REG_CFG _IOWR('V', BASE_VIDIOC_PRIVATE, struct msm_vfe_cfg_cmd2) +#define VIDIOC_MSM_ISP_REQUEST_BUF _IOWR('V', BASE_VIDIOC_PRIVATE+1, struct msm_isp_buf_request) +#define VIDIOC_MSM_ISP_ENQUEUE_BUF _IOWR('V', BASE_VIDIOC_PRIVATE+2, struct msm_isp_qbuf_info) +#define VIDIOC_MSM_ISP_RELEASE_BUF _IOWR('V', BASE_VIDIOC_PRIVATE+3, struct msm_isp_buf_request) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VIDIOC_MSM_ISP_REQUEST_STREAM _IOWR('V', BASE_VIDIOC_PRIVATE+4, struct msm_vfe_axi_stream_request_cmd) +#define VIDIOC_MSM_ISP_CFG_STREAM _IOWR('V', BASE_VIDIOC_PRIVATE+5, struct msm_vfe_axi_stream_cfg_cmd) +#define VIDIOC_MSM_ISP_RELEASE_STREAM _IOWR('V', BASE_VIDIOC_PRIVATE+6, struct msm_vfe_axi_stream_release_cmd) +#define VIDIOC_MSM_ISP_INPUT_CFG _IOWR('V', BASE_VIDIOC_PRIVATE+7, struct msm_vfe_input_cfg) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VIDIOC_MSM_ISP_SET_SRC_STATE _IOWR('V', BASE_VIDIOC_PRIVATE+8, struct msm_vfe_axi_src_state) +#define VIDIOC_MSM_ISP_REQUEST_STATS_STREAM _IOWR('V', BASE_VIDIOC_PRIVATE+9, struct msm_vfe_stats_stream_request_cmd) +#define VIDIOC_MSM_ISP_CFG_STATS_STREAM _IOWR('V', BASE_VIDIOC_PRIVATE+10, struct msm_vfe_stats_stream_cfg_cmd) +#define VIDIOC_MSM_ISP_RELEASE_STATS_STREAM _IOWR('V', BASE_VIDIOC_PRIVATE+11, struct msm_vfe_stats_stream_release_cmd) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VIDIOC_MSM_ISP_REG_UPDATE_CMD _IOWR('V', BASE_VIDIOC_PRIVATE+12, enum msm_vfe_input_src) +#define VIDIOC_MSM_ISP_UPDATE_STREAM _IOWR('V', BASE_VIDIOC_PRIVATE+13, struct msm_vfe_axi_stream_update_cmd) +#define VIDIOC_MSM_VFE_REG_LIST_CFG _IOWR('V', BASE_VIDIOC_PRIVATE+14, struct msm_vfe_cfg_cmd_list) +#define VIDIOC_MSM_ISP_SMMU_ATTACH _IOWR('V', BASE_VIDIOC_PRIVATE+15, struct msm_vfe_smmu_attach_cmd) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VIDIOC_MSM_ISP_UPDATE_STATS_STREAM _IOWR('V', BASE_VIDIOC_PRIVATE+16, struct msm_vfe_axi_stream_update_cmd) +#define VIDIOC_MSM_ISP_AXI_HALT _IOWR('V', BASE_VIDIOC_PRIVATE+17, struct msm_vfe_axi_halt_cmd) +#define VIDIOC_MSM_ISP_AXI_RESET _IOWR('V', BASE_VIDIOC_PRIVATE+18, struct msm_vfe_axi_reset_cmd) +#define VIDIOC_MSM_ISP_AXI_RESTART _IOWR('V', BASE_VIDIOC_PRIVATE+19, struct msm_vfe_axi_restart_cmd) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VIDIOC_MSM_ISP_FETCH_ENG_START _IOWR('V', BASE_VIDIOC_PRIVATE+20, struct msm_vfe_fetch_eng_start) +#endif + diff --git a/kernel-headers/media/msmb_ispif.h b/kernel-headers/media/msmb_ispif.h new file mode 100644 index 0000000..23f916d --- /dev/null +++ b/kernel-headers/media/msmb_ispif.h @@ -0,0 +1,154 @@ +/**************************************************************************** + **************************************************************************** + *** + *** This header was automatically generated from a Linux kernel header + *** of the same name, to make information necessary for userspace to + *** call into the kernel available to libc. It contains only constants, + *** structures, and macros generated from the original header, and thus, + *** contains no copyrightable information. + *** + *** To edit the content of this header, modify the corresponding + *** source file (e.g. under external/kernel-headers/original/) then + *** run bionic/libc/kernel/tools/update_all.py + *** + *** Any manual change here will be lost the next time this script will + *** be run. You've been warned! + *** + **************************************************************************** + ****************************************************************************/ +#ifndef MSM_CAM_ISPIF_H +#define MSM_CAM_ISPIF_H +#define CSID_VERSION_V20 0x02000011 +#define CSID_VERSION_V22 0x02001000 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define CSID_VERSION_V30 0x30000000 +#define CSID_VERSION_V3 0x30000000 +enum msm_ispif_vfe_intf { + VFE0, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + VFE1, + VFE_MAX +}; +#define VFE0_MASK (1 << VFE0) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VFE1_MASK (1 << VFE1) +enum msm_ispif_intftype { + PIX0, + RDI0, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + PIX1, + RDI1, + RDI2, + INTF_MAX +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +#define MAX_PARAM_ENTRIES (INTF_MAX * 2) +#define MAX_CID_CH 8 +#define PIX0_MASK (1 << PIX0) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define PIX1_MASK (1 << PIX1) +#define RDI0_MASK (1 << RDI0) +#define RDI1_MASK (1 << RDI1) +#define RDI2_MASK (1 << RDI2) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +enum msm_ispif_vc { + VC0, + VC1, + VC2, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + VC3, + VC_MAX +}; +enum msm_ispif_cid { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + CID0, + CID1, + CID2, + CID3, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + CID4, + CID5, + CID6, + CID7, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + CID8, + CID9, + CID10, + CID11, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + CID12, + CID13, + CID14, + CID15, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + CID_MAX +}; +enum msm_ispif_csid { + CSID0, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + CSID1, + CSID2, + CSID3, + CSID_MAX +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +struct msm_ispif_params_entry { + enum msm_ispif_vfe_intf vfe_intf; + enum msm_ispif_intftype intftype; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + int num_cids; + enum msm_ispif_cid cids[3]; + enum msm_ispif_csid csid; + int crop_enable; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint16_t crop_start_pixel; + uint16_t crop_end_pixel; +}; +struct msm_ispif_param_data { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t num; + struct msm_ispif_params_entry entries[MAX_PARAM_ENTRIES]; +}; +struct msm_isp_info { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t max_resolution; + uint32_t id; + uint32_t ver; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct msm_ispif_vfe_info { + int num_vfe; + struct msm_isp_info info[VFE_MAX]; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +enum ispif_cfg_type_t { + ISPIF_CLK_ENABLE, + ISPIF_CLK_DISABLE, + ISPIF_INIT, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + ISPIF_CFG, + ISPIF_START_FRAME_BOUNDARY, + ISPIF_RESTART_FRAME_BOUNDARY, + ISPIF_STOP_FRAME_BOUNDARY, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + ISPIF_STOP_IMMEDIATELY, + ISPIF_RELEASE, + ISPIF_ENABLE_REG_DUMP, + ISPIF_SET_VFE_INFO, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +struct ispif_cfg_data { + enum ispif_cfg_type_t cfg_type; + union { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + int reg_dump; + uint32_t csid_version; + struct msm_ispif_vfe_info vfe_info; + struct msm_ispif_param_data params; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + }; +}; +#define VIDIOC_MSM_ISPIF_CFG _IOWR('V', BASE_VIDIOC_PRIVATE, struct ispif_cfg_data) +#endif +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + diff --git a/kernel-headers/media/msmb_pproc.h b/kernel-headers/media/msmb_pproc.h new file mode 100644 index 0000000..7392518 --- /dev/null +++ b/kernel-headers/media/msmb_pproc.h @@ -0,0 +1,326 @@ +/**************************************************************************** + **************************************************************************** + *** + *** This header was automatically generated from a Linux kernel header + *** of the same name, to make information necessary for userspace to + *** call into the kernel available to libc. It contains only constants, + *** structures, and macros generated from the original header, and thus, + *** contains no copyrightable information. + *** + *** To edit the content of this header, modify the corresponding + *** source file (e.g. under external/kernel-headers/original/) then + *** run bionic/libc/kernel/tools/update_all.py + *** + *** Any manual change here will be lost the next time this script will + *** be run. You've been warned! + *** + **************************************************************************** + ****************************************************************************/ +#ifndef __MSMB_PPROC_H +#define __MSMB_PPROC_H +#ifdef MSM_CAMERA_BIONIC +#include <sys/types.h> +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#endif +#include <linux/videodev2.h> +#include <linux/types.h> +#include <media/msmb_generic_buf_mgr.h> +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define MAX_PLANES VIDEO_MAX_PLANES +#define MAX_NUM_CPP_STRIPS 8 +#define MSM_CPP_MAX_NUM_PLANES 3 +#define MSM_CPP_MIN_FRAME_LENGTH 13 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define MSM_CPP_MAX_FRAME_LENGTH 2048 +#define MSM_CPP_MAX_FW_NAME_LEN 32 +#define MAX_FREQ_TBL 10 +enum msm_cpp_frame_type { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + MSM_CPP_OFFLINE_FRAME, + MSM_CPP_REALTIME_FRAME, +}; +enum msm_vpe_frame_type { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + MSM_VPE_OFFLINE_FRAME, + MSM_VPE_REALTIME_FRAME, +}; +struct msm_cpp_frame_strip_info { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t scale_v_en; + uint32_t scale_h_en; + uint32_t upscale_v_en; + uint32_t upscale_h_en; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + int32_t src_start_x; + uint32_t src_end_x; + int32_t src_start_y; + uint32_t src_end_y; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + int32_t extra_src_start_x; + int32_t extra_src_end_x; + int32_t extra_src_start_y; + int32_t extra_src_end_y; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + int32_t extra_initial_vertical_count[2]; + int32_t extra_initial_horizontal_count[2]; + int32_t extra_left_crop; + int32_t extra_top_crop; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + int32_t extra_pad_bottom; + int32_t extra_pad_top; + int32_t extra_pad_right; + int32_t extra_pad_left; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + int32_t extra_upscale_width; + int32_t extra_upscale_height; + uint32_t temporal_pad_bottom; + uint32_t temporal_pad_top; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t temporal_pad_right; + uint32_t temporal_pad_left; + int32_t temporal_src_start_x; + uint32_t temporal_src_end_x; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + int32_t temporal_src_start_y; + uint32_t temporal_src_end_y; + uint32_t pad_bottom; + uint32_t pad_top; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t pad_right; + uint32_t pad_left; + uint32_t v_init_phase; + uint32_t h_init_phase; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t h_phase_step; + uint32_t v_phase_step; + uint32_t spatial_denoise_crop_width_first_pixel; + uint32_t spatial_denoise_crop_width_last_pixel; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t spatial_denoise_crop_height_first_line; + uint32_t spatial_denoise_crop_height_last_line; + uint32_t sharpen_crop_height_first_line; + uint32_t sharpen_crop_height_last_line; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t sharpen_crop_width_first_pixel; + uint32_t sharpen_crop_width_last_pixel; + uint32_t temporal_denoise_crop_width_first_pixel; + uint32_t temporal_denoise_crop_width_last_pixel; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t temporal_denoise_crop_height_first_line; + uint32_t temporal_denoise_crop_height_last_line; + uint32_t prescaler_spatial_denoise_crop_width_first_pixel; + uint32_t prescaler_spatial_denoise_crop_width_last_pixel; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t prescaler_spatial_denoise_crop_height_first_line; + uint32_t prescaler_spatial_denoise_crop_height_last_line; + uint32_t state_crop_width_first_pixel; + uint32_t state_crop_width_last_pixel; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t state_crop_height_first_line; + uint32_t state_crop_height_last_line; + int32_t dst_start_x; + uint32_t dst_end_x; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + int32_t dst_start_y; + uint32_t dst_end_y; + int32_t temporal_dst_start_x; + uint32_t temporal_dst_end_x; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + int32_t temporal_dst_start_y; + uint32_t temporal_dst_end_y; + uint32_t input_bytes_per_pixel; + uint32_t output_bytes_per_pixel; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t temporal_bytes_per_pixel; + uint32_t source_address[2]; + uint32_t extra_source_address[2]; + uint32_t destination_address[2]; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t temporal_source_address[2]; + uint32_t temporal_destination_address[2]; + uint32_t src_stride; + uint32_t dst_stride; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t rotate_270; + uint32_t horizontal_flip; + uint32_t vertical_flip; + uint32_t scale_output_width; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t scale_output_height; + uint32_t spatial_denoise_crop_en; + uint32_t sharpen_crop_en; + uint32_t temporal_denoise_crop_en; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t prescaler_spatial_denoise_crop_en; + uint32_t state_crop_en; + int32_t we_h_init; + int32_t we_v_init; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + int32_t we_h_step; + int32_t we_v_step; +}; +struct msm_cpp_buffer_info_t { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + int32_t fd; + uint32_t index; + uint32_t offset; + uint8_t native_buff; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint8_t processed_divert; + uint32_t identity; +}; +struct msm_cpp_stream_buff_info_t { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t identity; + uint32_t num_buffs; + struct msm_cpp_buffer_info_t *buffer_info; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct msm_cpp_frame_info_t { + int32_t frame_id; + struct timeval timestamp; + uint32_t inst_id; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t identity; + uint32_t client_id; + enum msm_cpp_frame_type frame_type; + uint32_t num_strips; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + struct msm_cpp_frame_strip_info __user *strip_info; + uint32_t msg_len; + uint32_t *cpp_cmd_msg; + int src_fd; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + int dst_fd; + struct timeval in_time, out_time; + void __user *cookie; + int32_t *status; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + int32_t duplicate_output; + uint32_t duplicate_identity; + uint8_t we_disable; + struct msm_cpp_buffer_info_t input_buffer_info; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + struct msm_cpp_buffer_info_t output_buffer_info[2]; + struct msm_cpp_buffer_info_t tnr_scratch_buffer_info[2]; + uint32_t reserved; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct msm_cpp_pop_stream_info_t { + int32_t frame_id; + uint32_t identity; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct cpp_hw_info { + uint32_t cpp_hw_version; + uint32_t cpp_hw_caps; + unsigned long freq_tbl[MAX_FREQ_TBL]; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t freq_tbl_count; +}; +struct msm_vpe_frame_strip_info { + uint32_t src_w; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t src_h; + uint32_t dst_w; + uint32_t dst_h; + uint32_t src_x; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t src_y; + uint32_t phase_step_x; + uint32_t phase_step_y; + uint32_t phase_init_x; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t phase_init_y; +}; +struct msm_vpe_buffer_info_t { + int32_t fd; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t index; + uint32_t offset; + uint8_t native_buff; + uint8_t processed_divert; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +struct msm_vpe_stream_buff_info_t { + uint32_t identity; + uint32_t num_buffs; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + struct msm_vpe_buffer_info_t *buffer_info; +}; +struct msm_vpe_frame_info_t { + int32_t frame_id; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + struct timeval timestamp; + uint32_t inst_id; + uint32_t identity; + uint32_t client_id; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + enum msm_vpe_frame_type frame_type; + struct msm_vpe_frame_strip_info strip_info; + unsigned long src_fd; + unsigned long dst_fd; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + struct ion_handle *src_ion_handle; + struct ion_handle *dest_ion_handle; + unsigned long src_phyaddr; + unsigned long dest_phyaddr; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned long src_chroma_plane_offset; + unsigned long dest_chroma_plane_offset; + struct timeval in_time, out_time; + void *cookie; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + struct msm_vpe_buffer_info_t input_buffer_info; + struct msm_vpe_buffer_info_t output_buffer_info; +}; +struct msm_pproc_queue_buf_info { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + struct msm_buf_mngr_info buff_mgr_info; + uint8_t is_buf_dirty; +}; +struct msm_cpp_clock_settings_t { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned long clock_rate; + uint64_t avg; + uint64_t inst; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VIDIOC_MSM_CPP_CFG _IOWR('V', BASE_VIDIOC_PRIVATE, struct msm_camera_v4l2_ioctl_t) +#define VIDIOC_MSM_CPP_GET_EVENTPAYLOAD _IOWR('V', BASE_VIDIOC_PRIVATE + 1, struct msm_camera_v4l2_ioctl_t) +#define VIDIOC_MSM_CPP_GET_INST_INFO _IOWR('V', BASE_VIDIOC_PRIVATE + 2, struct msm_camera_v4l2_ioctl_t) +#define VIDIOC_MSM_CPP_LOAD_FIRMWARE _IOWR('V', BASE_VIDIOC_PRIVATE + 3, struct msm_camera_v4l2_ioctl_t) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VIDIOC_MSM_CPP_GET_HW_INFO _IOWR('V', BASE_VIDIOC_PRIVATE + 4, struct msm_camera_v4l2_ioctl_t) +#define VIDIOC_MSM_CPP_FLUSH_QUEUE _IOWR('V', BASE_VIDIOC_PRIVATE + 5, struct msm_camera_v4l2_ioctl_t) +#define VIDIOC_MSM_CPP_ENQUEUE_STREAM_BUFF_INFO _IOWR('V', BASE_VIDIOC_PRIVATE + 6, struct msm_camera_v4l2_ioctl_t) +#define VIDIOC_MSM_CPP_DEQUEUE_STREAM_BUFF_INFO _IOWR('V', BASE_VIDIOC_PRIVATE + 7, struct msm_camera_v4l2_ioctl_t) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VIDIOC_MSM_VPE_CFG _IOWR('V', BASE_VIDIOC_PRIVATE + 8, struct msm_camera_v4l2_ioctl_t) +#define VIDIOC_MSM_VPE_TRANSACTION_SETUP _IOWR('V', BASE_VIDIOC_PRIVATE + 9, struct msm_camera_v4l2_ioctl_t) +#define VIDIOC_MSM_VPE_GET_EVENTPAYLOAD _IOWR('V', BASE_VIDIOC_PRIVATE + 10, struct msm_camera_v4l2_ioctl_t) +#define VIDIOC_MSM_VPE_GET_INST_INFO _IOWR('V', BASE_VIDIOC_PRIVATE + 11, struct msm_camera_v4l2_ioctl_t) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VIDIOC_MSM_VPE_ENQUEUE_STREAM_BUFF_INFO _IOWR('V', BASE_VIDIOC_PRIVATE + 12, struct msm_camera_v4l2_ioctl_t) +#define VIDIOC_MSM_VPE_DEQUEUE_STREAM_BUFF_INFO _IOWR('V', BASE_VIDIOC_PRIVATE + 13, struct msm_camera_v4l2_ioctl_t) +#define VIDIOC_MSM_CPP_QUEUE_BUF _IOWR('V', BASE_VIDIOC_PRIVATE + 14, struct msm_camera_v4l2_ioctl_t) +#define VIDIOC_MSM_CPP_APPEND_STREAM_BUFF_INFO _IOWR('V', BASE_VIDIOC_PRIVATE + 15, struct msm_camera_v4l2_ioctl_t) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VIDIOC_MSM_CPP_SET_CLOCK _IOWR('V', BASE_VIDIOC_PRIVATE + 16, struct msm_camera_v4l2_ioctl_t) +#define VIDIOC_MSM_CPP_POP_STREAM_BUFFER _IOWR('V', BASE_VIDIOC_PRIVATE + 17, struct msm_camera_v4l2_ioctl_t) +#define VIDIOC_MSM_CPP_IOMMU_ATTACH _IOWR('V', BASE_VIDIOC_PRIVATE + 18, struct msm_camera_v4l2_ioctl_t) +#define VIDIOC_MSM_CPP_IOMMU_DETACH _IOWR('V', BASE_VIDIOC_PRIVATE + 19, struct msm_camera_v4l2_ioctl_t) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VIDIOC_MSM_CPP_DELETE_STREAM_BUFF _IOWR('V', BASE_VIDIOC_PRIVATE + 20, struct msm_camera_v4l2_ioctl_t) +#define V4L2_EVENT_CPP_FRAME_DONE (V4L2_EVENT_PRIVATE_START + 0) +#define V4L2_EVENT_VPE_FRAME_DONE (V4L2_EVENT_PRIVATE_START + 1) +struct msm_camera_v4l2_ioctl_t { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t id; + size_t len; + int32_t trans_code; + void __user *ioctl_ptr; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +#endif + diff --git a/kernel-headers/sound/asound.h b/kernel-headers/sound/asound.h new file mode 100644 index 0000000..7864893 --- /dev/null +++ b/kernel-headers/sound/asound.h @@ -0,0 +1,992 @@ +/**************************************************************************** + **************************************************************************** + *** + *** This header was automatically generated from a Linux kernel header + *** of the same name, to make information necessary for userspace to + *** call into the kernel available to libc. It contains only constants, + *** structures, and macros generated from the original header, and thus, + *** contains no copyrightable information. + *** + *** To edit the content of this header, modify the corresponding + *** source file (e.g. under external/kernel-headers/original/) then + *** run bionic/libc/kernel/tools/update_all.py + *** + *** Any manual change here will be lost the next time this script will + *** be run. You've been warned! + *** + **************************************************************************** + ****************************************************************************/ +#ifndef _UAPI__SOUND_ASOUND_H +#define _UAPI__SOUND_ASOUND_H +#include <linux/types.h> +#define SNDRV_PROTOCOL_VERSION(major, minor, subminor) (((major)<<16)|((minor)<<8)|(subminor)) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SNDRV_PROTOCOL_MAJOR(version) (((version)>>16)&0xffff) +#define SNDRV_PROTOCOL_MINOR(version) (((version)>>8)&0xff) +#define SNDRV_PROTOCOL_MICRO(version) ((version)&0xff) +#define SNDRV_PROTOCOL_INCOMPATIBLE(kversion, uversion) (SNDRV_PROTOCOL_MAJOR(kversion) != SNDRV_PROTOCOL_MAJOR(uversion) || (SNDRV_PROTOCOL_MAJOR(kversion) == SNDRV_PROTOCOL_MAJOR(uversion) && SNDRV_PROTOCOL_MINOR(kversion) != SNDRV_PROTOCOL_MINOR(uversion))) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct snd_aes_iec958 { + unsigned char status[24]; + unsigned char subcode[147]; + unsigned char pad; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned char dig_subframe[4]; +}; +struct snd_cea_861_aud_if { + unsigned char db1_ct_cc; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned char db2_sf_ss; + unsigned char db3; + unsigned char db4_ca; + unsigned char db5_dminh_lsv; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +#define SNDRV_HWDEP_VERSION SNDRV_PROTOCOL_VERSION(1, 0, 1) +enum { + SNDRV_HWDEP_IFACE_OPL2 = 0, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + SNDRV_HWDEP_IFACE_OPL3, + SNDRV_HWDEP_IFACE_OPL4, + SNDRV_HWDEP_IFACE_SB16CSP, + SNDRV_HWDEP_IFACE_EMU10K1, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + SNDRV_HWDEP_IFACE_YSS225, + SNDRV_HWDEP_IFACE_ICS2115, + SNDRV_HWDEP_IFACE_SSCAPE, + SNDRV_HWDEP_IFACE_VX, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + SNDRV_HWDEP_IFACE_MIXART, + SNDRV_HWDEP_IFACE_USX2Y, + SNDRV_HWDEP_IFACE_EMUX_WAVETABLE, + SNDRV_HWDEP_IFACE_BLUETOOTH, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + SNDRV_HWDEP_IFACE_USX2Y_PCM, + SNDRV_HWDEP_IFACE_PCXHR, + SNDRV_HWDEP_IFACE_SB_RC, + SNDRV_HWDEP_IFACE_HDA, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + SNDRV_HWDEP_IFACE_USB_STREAM, + SNDRV_HWDEP_IFACE_AUDIO_BE, + SNDRV_HWDEP_IFACE_AUDIO_CODEC, + SNDRV_HWDEP_IFACE_LAST = SNDRV_HWDEP_IFACE_AUDIO_CODEC +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +struct snd_hwdep_info { + unsigned int device; + int card; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned char id[64]; + unsigned char name[80]; + int iface; + unsigned char reserved[64]; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +struct snd_hwdep_dsp_status { + unsigned int version; + unsigned char id[32]; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned int num_dsps; + unsigned int dsp_loaded; + unsigned int chip_ready; + unsigned char reserved[16]; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +struct snd_hwdep_dsp_image { + unsigned int index; + unsigned char name[64]; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned char __user *image; + size_t length; + unsigned long driver_data; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SNDRV_HWDEP_IOCTL_PVERSION _IOR ('H', 0x00, int) +#define SNDRV_HWDEP_IOCTL_INFO _IOR ('H', 0x01, struct snd_hwdep_info) +#define SNDRV_HWDEP_IOCTL_DSP_STATUS _IOR('H', 0x02, struct snd_hwdep_dsp_status) +#define SNDRV_HWDEP_IOCTL_DSP_LOAD _IOW('H', 0x03, struct snd_hwdep_dsp_image) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SNDRV_PCM_VERSION SNDRV_PROTOCOL_VERSION(2, 0, 11) +typedef unsigned long snd_pcm_uframes_t; +typedef signed long snd_pcm_sframes_t; +enum { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + SNDRV_PCM_CLASS_GENERIC = 0, + SNDRV_PCM_CLASS_MULTI, + SNDRV_PCM_CLASS_MODEM, + SNDRV_PCM_CLASS_DIGITIZER, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + SNDRV_PCM_CLASS_LAST = SNDRV_PCM_CLASS_DIGITIZER, +}; +enum { + SNDRV_PCM_SUBCLASS_GENERIC_MIX = 0, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + SNDRV_PCM_SUBCLASS_MULTI_MIX, + SNDRV_PCM_SUBCLASS_LAST = SNDRV_PCM_SUBCLASS_MULTI_MIX, +}; +enum { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + SNDRV_PCM_STREAM_PLAYBACK = 0, + SNDRV_PCM_STREAM_CAPTURE, + SNDRV_PCM_STREAM_LAST = SNDRV_PCM_STREAM_CAPTURE, +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +typedef int __bitwise snd_pcm_access_t; +#define SNDRV_PCM_ACCESS_MMAP_INTERLEAVED ((__force snd_pcm_access_t) 0) +#define SNDRV_PCM_ACCESS_MMAP_NONINTERLEAVED ((__force snd_pcm_access_t) 1) +#define SNDRV_PCM_ACCESS_MMAP_COMPLEX ((__force snd_pcm_access_t) 2) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SNDRV_PCM_ACCESS_RW_INTERLEAVED ((__force snd_pcm_access_t) 3) +#define SNDRV_PCM_ACCESS_RW_NONINTERLEAVED ((__force snd_pcm_access_t) 4) +#define SNDRV_PCM_ACCESS_LAST SNDRV_PCM_ACCESS_RW_NONINTERLEAVED +typedef int __bitwise snd_pcm_format_t; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SNDRV_PCM_FORMAT_S8 ((__force snd_pcm_format_t) 0) +#define SNDRV_PCM_FORMAT_U8 ((__force snd_pcm_format_t) 1) +#define SNDRV_PCM_FORMAT_S16_LE ((__force snd_pcm_format_t) 2) +#define SNDRV_PCM_FORMAT_S16_BE ((__force snd_pcm_format_t) 3) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SNDRV_PCM_FORMAT_U16_LE ((__force snd_pcm_format_t) 4) +#define SNDRV_PCM_FORMAT_U16_BE ((__force snd_pcm_format_t) 5) +#define SNDRV_PCM_FORMAT_S24_LE ((__force snd_pcm_format_t) 6) +#define SNDRV_PCM_FORMAT_S24_BE ((__force snd_pcm_format_t) 7) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SNDRV_PCM_FORMAT_U24_LE ((__force snd_pcm_format_t) 8) +#define SNDRV_PCM_FORMAT_U24_BE ((__force snd_pcm_format_t) 9) +#define SNDRV_PCM_FORMAT_S32_LE ((__force snd_pcm_format_t) 10) +#define SNDRV_PCM_FORMAT_S32_BE ((__force snd_pcm_format_t) 11) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SNDRV_PCM_FORMAT_U32_LE ((__force snd_pcm_format_t) 12) +#define SNDRV_PCM_FORMAT_U32_BE ((__force snd_pcm_format_t) 13) +#define SNDRV_PCM_FORMAT_FLOAT_LE ((__force snd_pcm_format_t) 14) +#define SNDRV_PCM_FORMAT_FLOAT_BE ((__force snd_pcm_format_t) 15) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SNDRV_PCM_FORMAT_FLOAT64_LE ((__force snd_pcm_format_t) 16) +#define SNDRV_PCM_FORMAT_FLOAT64_BE ((__force snd_pcm_format_t) 17) +#define SNDRV_PCM_FORMAT_IEC958_SUBFRAME_LE ((__force snd_pcm_format_t) 18) +#define SNDRV_PCM_FORMAT_IEC958_SUBFRAME_BE ((__force snd_pcm_format_t) 19) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SNDRV_PCM_FORMAT_MU_LAW ((__force snd_pcm_format_t) 20) +#define SNDRV_PCM_FORMAT_A_LAW ((__force snd_pcm_format_t) 21) +#define SNDRV_PCM_FORMAT_IMA_ADPCM ((__force snd_pcm_format_t) 22) +#define SNDRV_PCM_FORMAT_MPEG ((__force snd_pcm_format_t) 23) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SNDRV_PCM_FORMAT_GSM ((__force snd_pcm_format_t) 24) +#define SNDRV_PCM_FORMAT_SPECIAL ((__force snd_pcm_format_t) 31) +#define SNDRV_PCM_FORMAT_S24_3LE ((__force snd_pcm_format_t) 32) +#define SNDRV_PCM_FORMAT_S24_3BE ((__force snd_pcm_format_t) 33) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SNDRV_PCM_FORMAT_U24_3LE ((__force snd_pcm_format_t) 34) +#define SNDRV_PCM_FORMAT_U24_3BE ((__force snd_pcm_format_t) 35) +#define SNDRV_PCM_FORMAT_S20_3LE ((__force snd_pcm_format_t) 36) +#define SNDRV_PCM_FORMAT_S20_3BE ((__force snd_pcm_format_t) 37) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SNDRV_PCM_FORMAT_U20_3LE ((__force snd_pcm_format_t) 38) +#define SNDRV_PCM_FORMAT_U20_3BE ((__force snd_pcm_format_t) 39) +#define SNDRV_PCM_FORMAT_S18_3LE ((__force snd_pcm_format_t) 40) +#define SNDRV_PCM_FORMAT_S18_3BE ((__force snd_pcm_format_t) 41) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SNDRV_PCM_FORMAT_U18_3LE ((__force snd_pcm_format_t) 42) +#define SNDRV_PCM_FORMAT_U18_3BE ((__force snd_pcm_format_t) 43) +#define SNDRV_PCM_FORMAT_G723_24 ((__force snd_pcm_format_t) 44) +#define SNDRV_PCM_FORMAT_G723_24_1B ((__force snd_pcm_format_t) 45) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SNDRV_PCM_FORMAT_G723_40 ((__force snd_pcm_format_t) 46) +#define SNDRV_PCM_FORMAT_G723_40_1B ((__force snd_pcm_format_t) 47) +#define SNDRV_PCM_FORMAT_DSD_U8 ((__force snd_pcm_format_t) 48) +#define SNDRV_PCM_FORMAT_DSD_U16_LE ((__force snd_pcm_format_t) 49) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SNDRV_PCM_FORMAT_LAST SNDRV_PCM_FORMAT_DSD_U16_LE +#ifdef SNDRV_LITTLE_ENDIAN +#define SNDRV_PCM_FORMAT_S16 SNDRV_PCM_FORMAT_S16_LE +#define SNDRV_PCM_FORMAT_U16 SNDRV_PCM_FORMAT_U16_LE +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SNDRV_PCM_FORMAT_S24 SNDRV_PCM_FORMAT_S24_LE +#define SNDRV_PCM_FORMAT_U24 SNDRV_PCM_FORMAT_U24_LE +#define SNDRV_PCM_FORMAT_S32 SNDRV_PCM_FORMAT_S32_LE +#define SNDRV_PCM_FORMAT_U32 SNDRV_PCM_FORMAT_U32_LE +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SNDRV_PCM_FORMAT_FLOAT SNDRV_PCM_FORMAT_FLOAT_LE +#define SNDRV_PCM_FORMAT_FLOAT64 SNDRV_PCM_FORMAT_FLOAT64_LE +#define SNDRV_PCM_FORMAT_IEC958_SUBFRAME SNDRV_PCM_FORMAT_IEC958_SUBFRAME_LE +#endif +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#ifdef SNDRV_BIG_ENDIAN +#define SNDRV_PCM_FORMAT_S16 SNDRV_PCM_FORMAT_S16_BE +#define SNDRV_PCM_FORMAT_U16 SNDRV_PCM_FORMAT_U16_BE +#define SNDRV_PCM_FORMAT_S24 SNDRV_PCM_FORMAT_S24_BE +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SNDRV_PCM_FORMAT_U24 SNDRV_PCM_FORMAT_U24_BE +#define SNDRV_PCM_FORMAT_S32 SNDRV_PCM_FORMAT_S32_BE +#define SNDRV_PCM_FORMAT_U32 SNDRV_PCM_FORMAT_U32_BE +#define SNDRV_PCM_FORMAT_FLOAT SNDRV_PCM_FORMAT_FLOAT_BE +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SNDRV_PCM_FORMAT_FLOAT64 SNDRV_PCM_FORMAT_FLOAT64_BE +#define SNDRV_PCM_FORMAT_IEC958_SUBFRAME SNDRV_PCM_FORMAT_IEC958_SUBFRAME_BE +#endif +typedef int __bitwise snd_pcm_subformat_t; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SNDRV_PCM_SUBFORMAT_STD ((__force snd_pcm_subformat_t) 0) +#define SNDRV_PCM_SUBFORMAT_LAST SNDRV_PCM_SUBFORMAT_STD +#define SNDRV_PCM_INFO_MMAP 0x00000001 +#define SNDRV_PCM_INFO_MMAP_VALID 0x00000002 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SNDRV_PCM_INFO_DOUBLE 0x00000004 +#define SNDRV_PCM_INFO_BATCH 0x00000010 +#define SNDRV_PCM_INFO_INTERLEAVED 0x00000100 +#define SNDRV_PCM_INFO_NONINTERLEAVED 0x00000200 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SNDRV_PCM_INFO_COMPLEX 0x00000400 +#define SNDRV_PCM_INFO_BLOCK_TRANSFER 0x00010000 +#define SNDRV_PCM_INFO_OVERRANGE 0x00020000 +#define SNDRV_PCM_INFO_RESUME 0x00040000 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SNDRV_PCM_INFO_PAUSE 0x00080000 +#define SNDRV_PCM_INFO_HALF_DUPLEX 0x00100000 +#define SNDRV_PCM_INFO_JOINT_DUPLEX 0x00200000 +#define SNDRV_PCM_INFO_SYNC_START 0x00400000 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SNDRV_PCM_INFO_NO_PERIOD_WAKEUP 0x00800000 +#define SNDRV_PCM_INFO_HAS_WALL_CLOCK 0x01000000 +#define SNDRV_PCM_INFO_FIFO_IN_FRAMES 0x80000000 +typedef int __bitwise snd_pcm_state_t; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SNDRV_PCM_STATE_OPEN ((__force snd_pcm_state_t) 0) +#define SNDRV_PCM_STATE_SETUP ((__force snd_pcm_state_t) 1) +#define SNDRV_PCM_STATE_PREPARED ((__force snd_pcm_state_t) 2) +#define SNDRV_PCM_STATE_RUNNING ((__force snd_pcm_state_t) 3) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SNDRV_PCM_STATE_XRUN ((__force snd_pcm_state_t) 4) +#define SNDRV_PCM_STATE_DRAINING ((__force snd_pcm_state_t) 5) +#define SNDRV_PCM_STATE_PAUSED ((__force snd_pcm_state_t) 6) +#define SNDRV_PCM_STATE_SUSPENDED ((__force snd_pcm_state_t) 7) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SNDRV_PCM_STATE_DISCONNECTED ((__force snd_pcm_state_t) 8) +#define SNDRV_PCM_STATE_LAST SNDRV_PCM_STATE_DISCONNECTED +enum { + SNDRV_PCM_MMAP_OFFSET_DATA = 0x00000000, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + SNDRV_PCM_MMAP_OFFSET_STATUS = 0x80000000, + SNDRV_PCM_MMAP_OFFSET_CONTROL = 0x81000000, +}; +union snd_pcm_sync_id { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned char id[16]; + unsigned short id16[8]; + unsigned int id32[4]; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct snd_pcm_info { + unsigned int device; + unsigned int subdevice; + int stream; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + int card; + unsigned char id[64]; + unsigned char name[80]; + unsigned char subname[32]; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + int dev_class; + int dev_subclass; + unsigned int subdevices_count; + unsigned int subdevices_avail; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + union snd_pcm_sync_id sync; + unsigned char reserved[64]; +}; +typedef int snd_pcm_hw_param_t; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SNDRV_PCM_HW_PARAM_ACCESS 0 +#define SNDRV_PCM_HW_PARAM_FORMAT 1 +#define SNDRV_PCM_HW_PARAM_SUBFORMAT 2 +#define SNDRV_PCM_HW_PARAM_FIRST_MASK SNDRV_PCM_HW_PARAM_ACCESS +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SNDRV_PCM_HW_PARAM_LAST_MASK SNDRV_PCM_HW_PARAM_SUBFORMAT +#define SNDRV_PCM_HW_PARAM_SAMPLE_BITS 8 +#define SNDRV_PCM_HW_PARAM_FRAME_BITS 9 +#define SNDRV_PCM_HW_PARAM_CHANNELS 10 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SNDRV_PCM_HW_PARAM_RATE 11 +#define SNDRV_PCM_HW_PARAM_PERIOD_TIME 12 +#define SNDRV_PCM_HW_PARAM_PERIOD_SIZE 13 +#define SNDRV_PCM_HW_PARAM_PERIOD_BYTES 14 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SNDRV_PCM_HW_PARAM_PERIODS 15 +#define SNDRV_PCM_HW_PARAM_BUFFER_TIME 16 +#define SNDRV_PCM_HW_PARAM_BUFFER_SIZE 17 +#define SNDRV_PCM_HW_PARAM_BUFFER_BYTES 18 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SNDRV_PCM_HW_PARAM_TICK_TIME 19 +#define SNDRV_PCM_HW_PARAM_FIRST_INTERVAL SNDRV_PCM_HW_PARAM_SAMPLE_BITS +#define SNDRV_PCM_HW_PARAM_LAST_INTERVAL SNDRV_PCM_HW_PARAM_TICK_TIME +#define SNDRV_PCM_HW_PARAMS_NORESAMPLE (1<<0) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SNDRV_PCM_HW_PARAMS_EXPORT_BUFFER (1<<1) +#define SNDRV_PCM_HW_PARAMS_NO_PERIOD_WAKEUP (1<<2) +struct snd_interval { + unsigned int min, max; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned int openmin:1, + openmax:1, + integer:1, + empty:1; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +#define SNDRV_MASK_MAX 256 +struct snd_mask { + __u32 bits[(SNDRV_MASK_MAX+31)/32]; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +struct snd_pcm_hw_params { + unsigned int flags; + struct snd_mask masks[SNDRV_PCM_HW_PARAM_LAST_MASK - +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + SNDRV_PCM_HW_PARAM_FIRST_MASK + 1]; + struct snd_mask mres[5]; + struct snd_interval intervals[SNDRV_PCM_HW_PARAM_LAST_INTERVAL - + SNDRV_PCM_HW_PARAM_FIRST_INTERVAL + 1]; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + struct snd_interval ires[9]; + unsigned int rmask; + unsigned int cmask; + unsigned int info; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned int msbits; + unsigned int rate_num; + unsigned int rate_den; + snd_pcm_uframes_t fifo_size; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned char reserved[64]; +}; +enum { + SNDRV_PCM_TSTAMP_NONE = 0, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + SNDRV_PCM_TSTAMP_ENABLE, + SNDRV_PCM_TSTAMP_LAST = SNDRV_PCM_TSTAMP_ENABLE, +}; +struct snd_pcm_sw_params { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + int tstamp_mode; + unsigned int period_step; + unsigned int sleep_min; + snd_pcm_uframes_t avail_min; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + snd_pcm_uframes_t xfer_align; + snd_pcm_uframes_t start_threshold; + snd_pcm_uframes_t stop_threshold; + snd_pcm_uframes_t silence_threshold; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + snd_pcm_uframes_t silence_size; + snd_pcm_uframes_t boundary; + unsigned char reserved[64]; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct snd_pcm_channel_info { + unsigned int channel; + __kernel_off_t offset; + unsigned int first; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned int step; +}; +struct snd_pcm_status { + snd_pcm_state_t state; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + struct timespec trigger_tstamp; + struct timespec tstamp; + snd_pcm_uframes_t appl_ptr; + snd_pcm_uframes_t hw_ptr; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + snd_pcm_sframes_t delay; + snd_pcm_uframes_t avail; + snd_pcm_uframes_t avail_max; + snd_pcm_uframes_t overrange; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + snd_pcm_state_t suspended_state; + __u32 reserved_alignment; + struct timespec audio_tstamp; + unsigned char reserved[56-sizeof(struct timespec)]; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +struct snd_pcm_mmap_status { + snd_pcm_state_t state; + int pad1; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + snd_pcm_uframes_t hw_ptr; + struct timespec tstamp; + snd_pcm_state_t suspended_state; + struct timespec audio_tstamp; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +struct snd_pcm_mmap_control { + snd_pcm_uframes_t appl_ptr; + snd_pcm_uframes_t avail_min; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +#define SNDRV_PCM_SYNC_PTR_HWSYNC (1<<0) +#define SNDRV_PCM_SYNC_PTR_APPL (1<<1) +#define SNDRV_PCM_SYNC_PTR_AVAIL_MIN (1<<2) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct snd_pcm_sync_ptr { + unsigned int flags; + union { + struct snd_pcm_mmap_status status; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned char reserved[64]; + } s; + union { + struct snd_pcm_mmap_control control; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned char reserved[64]; + } c; +}; +struct snd_xferi { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + snd_pcm_sframes_t result; + void __user *buf; + snd_pcm_uframes_t frames; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct snd_xfern { + snd_pcm_sframes_t result; + void __user * __user *bufs; + snd_pcm_uframes_t frames; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +enum { + SNDRV_PCM_TSTAMP_TYPE_GETTIMEOFDAY = 0, + SNDRV_PCM_TSTAMP_TYPE_MONOTONIC, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + SNDRV_PCM_TSTAMP_TYPE_LAST = SNDRV_PCM_TSTAMP_TYPE_MONOTONIC, +}; +enum { + SNDRV_CHMAP_UNKNOWN = 0, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + SNDRV_CHMAP_NA, + SNDRV_CHMAP_MONO, + SNDRV_CHMAP_FL, + SNDRV_CHMAP_FR, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + SNDRV_CHMAP_RL, + SNDRV_CHMAP_RR, + SNDRV_CHMAP_FC, + SNDRV_CHMAP_LFE, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + SNDRV_CHMAP_SL, + SNDRV_CHMAP_SR, + SNDRV_CHMAP_RC, + SNDRV_CHMAP_FLC, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + SNDRV_CHMAP_FRC, + SNDRV_CHMAP_RLC, + SNDRV_CHMAP_RRC, + SNDRV_CHMAP_FLW, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + SNDRV_CHMAP_FRW, + SNDRV_CHMAP_FLH, + SNDRV_CHMAP_FCH, + SNDRV_CHMAP_FRH, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + SNDRV_CHMAP_TC, + SNDRV_CHMAP_TFL, + SNDRV_CHMAP_TFR, + SNDRV_CHMAP_TFC, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + SNDRV_CHMAP_TRL, + SNDRV_CHMAP_TRR, + SNDRV_CHMAP_TRC, + SNDRV_CHMAP_TFLC, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + SNDRV_CHMAP_TFRC, + SNDRV_CHMAP_TSL, + SNDRV_CHMAP_TSR, + SNDRV_CHMAP_LLFE, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + SNDRV_CHMAP_RLFE, + SNDRV_CHMAP_BC, + SNDRV_CHMAP_BLC, + SNDRV_CHMAP_BRC, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + SNDRV_CHMAP_LAST = SNDRV_CHMAP_BRC, +}; +#define SNDRV_CHMAP_POSITION_MASK 0xffff +#define SNDRV_CHMAP_PHASE_INVERSE (0x01 << 16) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SNDRV_CHMAP_DRIVER_SPEC (0x02 << 16) +#define SNDRV_PCM_IOCTL_PVERSION _IOR('A', 0x00, int) +#define SNDRV_PCM_IOCTL_INFO _IOR('A', 0x01, struct snd_pcm_info) +#define SNDRV_PCM_IOCTL_TSTAMP _IOW('A', 0x02, int) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SNDRV_PCM_IOCTL_TTSTAMP _IOW('A', 0x03, int) +#define SNDRV_PCM_IOCTL_HW_REFINE _IOWR('A', 0x10, struct snd_pcm_hw_params) +#define SNDRV_PCM_IOCTL_HW_PARAMS _IOWR('A', 0x11, struct snd_pcm_hw_params) +#define SNDRV_PCM_IOCTL_HW_FREE _IO('A', 0x12) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SNDRV_PCM_IOCTL_SW_PARAMS _IOWR('A', 0x13, struct snd_pcm_sw_params) +#define SNDRV_PCM_IOCTL_STATUS _IOR('A', 0x20, struct snd_pcm_status) +#define SNDRV_PCM_IOCTL_DELAY _IOR('A', 0x21, snd_pcm_sframes_t) +#define SNDRV_PCM_IOCTL_HWSYNC _IO('A', 0x22) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SNDRV_PCM_IOCTL_SYNC_PTR _IOWR('A', 0x23, struct snd_pcm_sync_ptr) +#define SNDRV_PCM_IOCTL_CHANNEL_INFO _IOR('A', 0x32, struct snd_pcm_channel_info) +#define SNDRV_PCM_IOCTL_PREPARE _IO('A', 0x40) +#define SNDRV_PCM_IOCTL_RESET _IO('A', 0x41) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SNDRV_PCM_IOCTL_START _IO('A', 0x42) +#define SNDRV_PCM_IOCTL_DROP _IO('A', 0x43) +#define SNDRV_PCM_IOCTL_DRAIN _IO('A', 0x44) +#define SNDRV_PCM_IOCTL_PAUSE _IOW('A', 0x45, int) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SNDRV_PCM_IOCTL_REWIND _IOW('A', 0x46, snd_pcm_uframes_t) +#define SNDRV_PCM_IOCTL_RESUME _IO('A', 0x47) +#define SNDRV_PCM_IOCTL_XRUN _IO('A', 0x48) +#define SNDRV_PCM_IOCTL_FORWARD _IOW('A', 0x49, snd_pcm_uframes_t) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SNDRV_PCM_IOCTL_WRITEI_FRAMES _IOW('A', 0x50, struct snd_xferi) +#define SNDRV_PCM_IOCTL_READI_FRAMES _IOR('A', 0x51, struct snd_xferi) +#define SNDRV_PCM_IOCTL_WRITEN_FRAMES _IOW('A', 0x52, struct snd_xfern) +#define SNDRV_PCM_IOCTL_READN_FRAMES _IOR('A', 0x53, struct snd_xfern) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SNDRV_PCM_IOCTL_LINK _IOW('A', 0x60, int) +#define SNDRV_PCM_IOCTL_UNLINK _IO('A', 0x61) +#define SNDRV_RAWMIDI_VERSION SNDRV_PROTOCOL_VERSION(2, 0, 0) +enum { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + SNDRV_RAWMIDI_STREAM_OUTPUT = 0, + SNDRV_RAWMIDI_STREAM_INPUT, + SNDRV_RAWMIDI_STREAM_LAST = SNDRV_RAWMIDI_STREAM_INPUT, +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SNDRV_RAWMIDI_INFO_OUTPUT 0x00000001 +#define SNDRV_RAWMIDI_INFO_INPUT 0x00000002 +#define SNDRV_RAWMIDI_INFO_DUPLEX 0x00000004 +struct snd_rawmidi_info { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned int device; + unsigned int subdevice; + int stream; + int card; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned int flags; + unsigned char id[64]; + unsigned char name[80]; + unsigned char subname[32]; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned int subdevices_count; + unsigned int subdevices_avail; + unsigned char reserved[64]; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct snd_rawmidi_params { + int stream; + size_t buffer_size; + size_t avail_min; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned int no_active_sensing: 1; + unsigned char reserved[16]; +}; +struct snd_rawmidi_status { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + int stream; + struct timespec tstamp; + size_t avail; + size_t xruns; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned char reserved[16]; +}; +#define SNDRV_RAWMIDI_IOCTL_PVERSION _IOR('W', 0x00, int) +#define SNDRV_RAWMIDI_IOCTL_INFO _IOR('W', 0x01, struct snd_rawmidi_info) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SNDRV_RAWMIDI_IOCTL_PARAMS _IOWR('W', 0x10, struct snd_rawmidi_params) +#define SNDRV_RAWMIDI_IOCTL_STATUS _IOWR('W', 0x20, struct snd_rawmidi_status) +#define SNDRV_RAWMIDI_IOCTL_DROP _IOW('W', 0x30, int) +#define SNDRV_RAWMIDI_IOCTL_DRAIN _IOW('W', 0x31, int) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SNDRV_TIMER_VERSION SNDRV_PROTOCOL_VERSION(2, 0, 6) +enum { + SNDRV_TIMER_CLASS_NONE = -1, + SNDRV_TIMER_CLASS_SLAVE = 0, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + SNDRV_TIMER_CLASS_GLOBAL, + SNDRV_TIMER_CLASS_CARD, + SNDRV_TIMER_CLASS_PCM, + SNDRV_TIMER_CLASS_LAST = SNDRV_TIMER_CLASS_PCM, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +enum { + SNDRV_TIMER_SCLASS_NONE = 0, + SNDRV_TIMER_SCLASS_APPLICATION, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + SNDRV_TIMER_SCLASS_SEQUENCER, + SNDRV_TIMER_SCLASS_OSS_SEQUENCER, + SNDRV_TIMER_SCLASS_LAST = SNDRV_TIMER_SCLASS_OSS_SEQUENCER, +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SNDRV_TIMER_GLOBAL_SYSTEM 0 +#define SNDRV_TIMER_GLOBAL_RTC 1 +#define SNDRV_TIMER_GLOBAL_HPET 2 +#define SNDRV_TIMER_GLOBAL_HRTIMER 3 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SNDRV_TIMER_FLG_SLAVE (1<<0) +struct snd_timer_id { + int dev_class; + int dev_sclass; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + int card; + int device; + int subdevice; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct snd_timer_ginfo { + struct snd_timer_id tid; + unsigned int flags; + int card; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned char id[64]; + unsigned char name[80]; + unsigned long reserved0; + unsigned long resolution; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned long resolution_min; + unsigned long resolution_max; + unsigned int clients; + unsigned char reserved[32]; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +struct snd_timer_gparams { + struct snd_timer_id tid; + unsigned long period_num; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned long period_den; + unsigned char reserved[32]; +}; +struct snd_timer_gstatus { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + struct snd_timer_id tid; + unsigned long resolution; + unsigned long resolution_num; + unsigned long resolution_den; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned char reserved[32]; +}; +struct snd_timer_select { + struct snd_timer_id id; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned char reserved[32]; +}; +struct snd_timer_info { + unsigned int flags; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + int card; + unsigned char id[64]; + unsigned char name[80]; + unsigned long reserved0; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned long resolution; + unsigned char reserved[64]; +}; +#define SNDRV_TIMER_PSFLG_AUTO (1<<0) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SNDRV_TIMER_PSFLG_EXCLUSIVE (1<<1) +#define SNDRV_TIMER_PSFLG_EARLY_EVENT (1<<2) +struct snd_timer_params { + unsigned int flags; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned int ticks; + unsigned int queue_size; + unsigned int reserved0; + unsigned int filter; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned char reserved[60]; +}; +struct snd_timer_status { + struct timespec tstamp; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned int resolution; + unsigned int lost; + unsigned int overrun; + unsigned int queue; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned char reserved[64]; +}; +#define SNDRV_TIMER_IOCTL_PVERSION _IOR('T', 0x00, int) +#define SNDRV_TIMER_IOCTL_NEXT_DEVICE _IOWR('T', 0x01, struct snd_timer_id) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SNDRV_TIMER_IOCTL_TREAD _IOW('T', 0x02, int) +#define SNDRV_TIMER_IOCTL_GINFO _IOWR('T', 0x03, struct snd_timer_ginfo) +#define SNDRV_TIMER_IOCTL_GPARAMS _IOW('T', 0x04, struct snd_timer_gparams) +#define SNDRV_TIMER_IOCTL_GSTATUS _IOWR('T', 0x05, struct snd_timer_gstatus) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SNDRV_TIMER_IOCTL_SELECT _IOW('T', 0x10, struct snd_timer_select) +#define SNDRV_TIMER_IOCTL_INFO _IOR('T', 0x11, struct snd_timer_info) +#define SNDRV_TIMER_IOCTL_PARAMS _IOW('T', 0x12, struct snd_timer_params) +#define SNDRV_TIMER_IOCTL_STATUS _IOR('T', 0x14, struct snd_timer_status) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SNDRV_TIMER_IOCTL_START _IO('T', 0xa0) +#define SNDRV_TIMER_IOCTL_STOP _IO('T', 0xa1) +#define SNDRV_TIMER_IOCTL_CONTINUE _IO('T', 0xa2) +#define SNDRV_TIMER_IOCTL_PAUSE _IO('T', 0xa3) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct snd_timer_read { + unsigned int resolution; + unsigned int ticks; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +enum { + SNDRV_TIMER_EVENT_RESOLUTION = 0, + SNDRV_TIMER_EVENT_TICK, + SNDRV_TIMER_EVENT_START, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + SNDRV_TIMER_EVENT_STOP, + SNDRV_TIMER_EVENT_CONTINUE, + SNDRV_TIMER_EVENT_PAUSE, + SNDRV_TIMER_EVENT_EARLY, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + SNDRV_TIMER_EVENT_SUSPEND, + SNDRV_TIMER_EVENT_RESUME, + SNDRV_TIMER_EVENT_MSTART = SNDRV_TIMER_EVENT_START + 10, + SNDRV_TIMER_EVENT_MSTOP = SNDRV_TIMER_EVENT_STOP + 10, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + SNDRV_TIMER_EVENT_MCONTINUE = SNDRV_TIMER_EVENT_CONTINUE + 10, + SNDRV_TIMER_EVENT_MPAUSE = SNDRV_TIMER_EVENT_PAUSE + 10, + SNDRV_TIMER_EVENT_MSUSPEND = SNDRV_TIMER_EVENT_SUSPEND + 10, + SNDRV_TIMER_EVENT_MRESUME = SNDRV_TIMER_EVENT_RESUME + 10, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +struct snd_timer_tread { + int event; + struct timespec tstamp; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned int val; +}; +#define SNDRV_CTL_VERSION SNDRV_PROTOCOL_VERSION(2, 0, 7) +struct snd_ctl_card_info { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + int card; + int pad; + unsigned char id[16]; + unsigned char driver[16]; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned char name[32]; + unsigned char longname[80]; + unsigned char reserved_[16]; + unsigned char mixername[80]; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned char components[128]; +}; +typedef int __bitwise snd_ctl_elem_type_t; +#define SNDRV_CTL_ELEM_TYPE_NONE ((__force snd_ctl_elem_type_t) 0) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SNDRV_CTL_ELEM_TYPE_BOOLEAN ((__force snd_ctl_elem_type_t) 1) +#define SNDRV_CTL_ELEM_TYPE_INTEGER ((__force snd_ctl_elem_type_t) 2) +#define SNDRV_CTL_ELEM_TYPE_ENUMERATED ((__force snd_ctl_elem_type_t) 3) +#define SNDRV_CTL_ELEM_TYPE_BYTES ((__force snd_ctl_elem_type_t) 4) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SNDRV_CTL_ELEM_TYPE_IEC958 ((__force snd_ctl_elem_type_t) 5) +#define SNDRV_CTL_ELEM_TYPE_INTEGER64 ((__force snd_ctl_elem_type_t) 6) +#define SNDRV_CTL_ELEM_TYPE_LAST SNDRV_CTL_ELEM_TYPE_INTEGER64 +typedef int __bitwise snd_ctl_elem_iface_t; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SNDRV_CTL_ELEM_IFACE_CARD ((__force snd_ctl_elem_iface_t) 0) +#define SNDRV_CTL_ELEM_IFACE_HWDEP ((__force snd_ctl_elem_iface_t) 1) +#define SNDRV_CTL_ELEM_IFACE_MIXER ((__force snd_ctl_elem_iface_t) 2) +#define SNDRV_CTL_ELEM_IFACE_PCM ((__force snd_ctl_elem_iface_t) 3) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SNDRV_CTL_ELEM_IFACE_RAWMIDI ((__force snd_ctl_elem_iface_t) 4) +#define SNDRV_CTL_ELEM_IFACE_TIMER ((__force snd_ctl_elem_iface_t) 5) +#define SNDRV_CTL_ELEM_IFACE_SEQUENCER ((__force snd_ctl_elem_iface_t) 6) +#define SNDRV_CTL_ELEM_IFACE_LAST SNDRV_CTL_ELEM_IFACE_SEQUENCER +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SNDRV_CTL_ELEM_ACCESS_READ (1<<0) +#define SNDRV_CTL_ELEM_ACCESS_WRITE (1<<1) +#define SNDRV_CTL_ELEM_ACCESS_READWRITE (SNDRV_CTL_ELEM_ACCESS_READ|SNDRV_CTL_ELEM_ACCESS_WRITE) +#define SNDRV_CTL_ELEM_ACCESS_VOLATILE (1<<2) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SNDRV_CTL_ELEM_ACCESS_TIMESTAMP (1<<3) +#define SNDRV_CTL_ELEM_ACCESS_TLV_READ (1<<4) +#define SNDRV_CTL_ELEM_ACCESS_TLV_WRITE (1<<5) +#define SNDRV_CTL_ELEM_ACCESS_TLV_READWRITE (SNDRV_CTL_ELEM_ACCESS_TLV_READ|SNDRV_CTL_ELEM_ACCESS_TLV_WRITE) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SNDRV_CTL_ELEM_ACCESS_TLV_COMMAND (1<<6) +#define SNDRV_CTL_ELEM_ACCESS_INACTIVE (1<<8) +#define SNDRV_CTL_ELEM_ACCESS_LOCK (1<<9) +#define SNDRV_CTL_ELEM_ACCESS_OWNER (1<<10) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK (1<<28) +#define SNDRV_CTL_ELEM_ACCESS_USER (1<<29) +#define SNDRV_CTL_POWER_D0 0x0000 +#define SNDRV_CTL_POWER_D1 0x0100 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SNDRV_CTL_POWER_D2 0x0200 +#define SNDRV_CTL_POWER_D3 0x0300 +#define SNDRV_CTL_POWER_D3hot (SNDRV_CTL_POWER_D3|0x0000) +#define SNDRV_CTL_POWER_D3cold (SNDRV_CTL_POWER_D3|0x0001) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct snd_ctl_elem_id { + unsigned int numid; + snd_ctl_elem_iface_t iface; + unsigned int device; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned int subdevice; + unsigned char name[44]; + unsigned int index; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct snd_ctl_elem_list { + unsigned int offset; + unsigned int space; + unsigned int used; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned int count; + struct snd_ctl_elem_id __user *pids; + unsigned char reserved[50]; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct snd_ctl_elem_info { + struct snd_ctl_elem_id id; + snd_ctl_elem_type_t type; + unsigned int access; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned int count; + __kernel_pid_t owner; + union { + struct { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + long min; + long max; + long step; + } integer; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + struct { + long long min; + long long max; + long long step; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + } integer64; + struct { + unsigned int items; + unsigned int item; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + char name[64]; + __u64 names_ptr; + unsigned int names_length; + } enumerated; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned char reserved[128]; + } value; + union { + unsigned short d[4]; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned short *d_ptr; + } dimen; + unsigned char reserved[64-4*sizeof(unsigned short)]; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct snd_ctl_elem_value { + struct snd_ctl_elem_id id; + unsigned int indirect: 1; + union { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + union { + long value[128]; + long *value_ptr; + } integer; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + union { + long long value[64]; + long long *value_ptr; + } integer64; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + union { + unsigned int item[128]; + unsigned int *item_ptr; + } enumerated; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + union { + unsigned char data[512]; + unsigned char *data_ptr; + } bytes; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + struct snd_aes_iec958 iec958; + } value; + struct timespec tstamp; + unsigned char reserved[128-sizeof(struct timespec)]; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +struct snd_ctl_tlv { + unsigned int numid; + unsigned int length; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned int tlv[0]; +}; +#define SNDRV_CTL_IOCTL_PVERSION _IOR('U', 0x00, int) +#define SNDRV_CTL_IOCTL_CARD_INFO _IOR('U', 0x01, struct snd_ctl_card_info) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SNDRV_CTL_IOCTL_ELEM_LIST _IOWR('U', 0x10, struct snd_ctl_elem_list) +#define SNDRV_CTL_IOCTL_ELEM_INFO _IOWR('U', 0x11, struct snd_ctl_elem_info) +#define SNDRV_CTL_IOCTL_ELEM_READ _IOWR('U', 0x12, struct snd_ctl_elem_value) +#define SNDRV_CTL_IOCTL_ELEM_WRITE _IOWR('U', 0x13, struct snd_ctl_elem_value) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SNDRV_CTL_IOCTL_ELEM_LOCK _IOW('U', 0x14, struct snd_ctl_elem_id) +#define SNDRV_CTL_IOCTL_ELEM_UNLOCK _IOW('U', 0x15, struct snd_ctl_elem_id) +#define SNDRV_CTL_IOCTL_SUBSCRIBE_EVENTS _IOWR('U', 0x16, int) +#define SNDRV_CTL_IOCTL_ELEM_ADD _IOWR('U', 0x17, struct snd_ctl_elem_info) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SNDRV_CTL_IOCTL_ELEM_REPLACE _IOWR('U', 0x18, struct snd_ctl_elem_info) +#define SNDRV_CTL_IOCTL_ELEM_REMOVE _IOWR('U', 0x19, struct snd_ctl_elem_id) +#define SNDRV_CTL_IOCTL_TLV_READ _IOWR('U', 0x1a, struct snd_ctl_tlv) +#define SNDRV_CTL_IOCTL_TLV_WRITE _IOWR('U', 0x1b, struct snd_ctl_tlv) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SNDRV_CTL_IOCTL_TLV_COMMAND _IOWR('U', 0x1c, struct snd_ctl_tlv) +#define SNDRV_CTL_IOCTL_HWDEP_NEXT_DEVICE _IOWR('U', 0x20, int) +#define SNDRV_CTL_IOCTL_HWDEP_INFO _IOR('U', 0x21, struct snd_hwdep_info) +#define SNDRV_CTL_IOCTL_PCM_NEXT_DEVICE _IOR('U', 0x30, int) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SNDRV_CTL_IOCTL_PCM_INFO _IOWR('U', 0x31, struct snd_pcm_info) +#define SNDRV_CTL_IOCTL_PCM_PREFER_SUBDEVICE _IOW('U', 0x32, int) +#define SNDRV_CTL_IOCTL_RAWMIDI_NEXT_DEVICE _IOWR('U', 0x40, int) +#define SNDRV_CTL_IOCTL_RAWMIDI_INFO _IOWR('U', 0x41, struct snd_rawmidi_info) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SNDRV_CTL_IOCTL_RAWMIDI_PREFER_SUBDEVICE _IOW('U', 0x42, int) +#define SNDRV_CTL_IOCTL_POWER _IOWR('U', 0xd0, int) +#define SNDRV_CTL_IOCTL_POWER_STATE _IOR('U', 0xd1, int) +enum sndrv_ctl_event_type { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + SNDRV_CTL_EVENT_ELEM = 0, + SNDRV_CTL_EVENT_LAST = SNDRV_CTL_EVENT_ELEM, +}; +#define SNDRV_CTL_EVENT_MASK_VALUE (1<<0) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SNDRV_CTL_EVENT_MASK_INFO (1<<1) +#define SNDRV_CTL_EVENT_MASK_ADD (1<<2) +#define SNDRV_CTL_EVENT_MASK_TLV (1<<3) +#define SNDRV_CTL_EVENT_MASK_REMOVE (~0U) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct snd_ctl_event { + int type; + union { + struct { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned int mask; + struct snd_ctl_elem_id id; + } elem; + unsigned char data8[60]; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + } data; +}; +#define SNDRV_CTL_NAME_NONE "" +#define SNDRV_CTL_NAME_PLAYBACK "Playback " +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SNDRV_CTL_NAME_CAPTURE "Capture " +#define SNDRV_CTL_NAME_IEC958_NONE "" +#define SNDRV_CTL_NAME_IEC958_SWITCH "Switch" +#define SNDRV_CTL_NAME_IEC958_VOLUME "Volume" +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SNDRV_CTL_NAME_IEC958_DEFAULT "Default" +#define SNDRV_CTL_NAME_IEC958_MASK "Mask" +#define SNDRV_CTL_NAME_IEC958_CON_MASK "Con Mask" +#define SNDRV_CTL_NAME_IEC958_PRO_MASK "Pro Mask" +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SNDRV_CTL_NAME_IEC958_PCM_STREAM "PCM Stream" +#define SNDRV_CTL_NAME_IEC958(expl,direction,what) "IEC958 " expl SNDRV_CTL_NAME_##direction SNDRV_CTL_NAME_IEC958_##what +#endif + diff --git a/kernel-headers/sound/audio_effects.h b/kernel-headers/sound/audio_effects.h new file mode 100644 index 0000000..9bbd5c5 --- /dev/null +++ b/kernel-headers/sound/audio_effects.h @@ -0,0 +1,294 @@ +/**************************************************************************** + **************************************************************************** + *** + *** This header was automatically generated from a Linux kernel header + *** of the same name, to make information necessary for userspace to + *** call into the kernel available to libc. It contains only constants, + *** structures, and macros generated from the original header, and thus, + *** contains no copyrightable information. + *** + *** To edit the content of this header, modify the corresponding + *** source file (e.g. under external/kernel-headers/original/) then + *** run bionic/libc/kernel/tools/update_all.py + *** + *** Any manual change here will be lost the next time this script will + *** be run. You've been warned! + *** + **************************************************************************** + ****************************************************************************/ +#ifndef _AUDIO_EFFECTS_H +#define _AUDIO_EFFECTS_H +#define CONFIG_CACHE 0 +#define CONFIG_SET 1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define CONFIG_GET 2 +#define VIRTUALIZER_MODULE 0x00001000 +#define VIRTUALIZER_ENABLE 0x00001001 +#define VIRTUALIZER_STRENGTH 0x00001002 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VIRTUALIZER_OUT_TYPE 0x00001003 +#define VIRTUALIZER_GAIN_ADJUST 0x00001004 +#define VIRTUALIZER_ENABLE_PARAM_LEN 1 +#define VIRTUALIZER_STRENGTH_PARAM_LEN 1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VIRTUALIZER_OUT_TYPE_PARAM_LEN 1 +#define VIRTUALIZER_GAIN_ADJUST_PARAM_LEN 1 +#define REVERB_MODULE 0x00002000 +#define REVERB_ENABLE 0x00002001 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define REVERB_MODE 0x00002002 +#define REVERB_PRESET 0x00002003 +#define REVERB_WET_MIX 0x00002004 +#define REVERB_GAIN_ADJUST 0x00002005 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define REVERB_ROOM_LEVEL 0x00002006 +#define REVERB_ROOM_HF_LEVEL 0x00002007 +#define REVERB_DECAY_TIME 0x00002008 +#define REVERB_DECAY_HF_RATIO 0x00002009 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define REVERB_REFLECTIONS_LEVEL 0x0000200a +#define REVERB_REFLECTIONS_DELAY 0x0000200b +#define REVERB_LEVEL 0x0000200c +#define REVERB_DELAY 0x0000200d +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define REVERB_DIFFUSION 0x0000200e +#define REVERB_DENSITY 0x0000200f +#define REVERB_ENABLE_PARAM_LEN 1 +#define REVERB_MODE_PARAM_LEN 1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define REVERB_PRESET_PARAM_LEN 1 +#define REVERB_WET_MIX_PARAM_LEN 1 +#define REVERB_GAIN_ADJUST_PARAM_LEN 1 +#define REVERB_ROOM_LEVEL_PARAM_LEN 1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define REVERB_ROOM_HF_LEVEL_PARAM_LEN 1 +#define REVERB_DECAY_TIME_PARAM_LEN 1 +#define REVERB_DECAY_HF_RATIO_PARAM_LEN 1 +#define REVERB_REFLECTIONS_LEVEL_PARAM_LEN 1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define REVERB_REFLECTIONS_DELAY_PARAM_LEN 1 +#define REVERB_LEVEL_PARAM_LEN 1 +#define REVERB_DELAY_PARAM_LEN 1 +#define REVERB_DIFFUSION_PARAM_LEN 1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define REVERB_DENSITY_PARAM_LEN 1 +#define BASS_BOOST_MODULE 0x00003000 +#define BASS_BOOST_ENABLE 0x00003001 +#define BASS_BOOST_MODE 0x00003002 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define BASS_BOOST_STRENGTH 0x00003003 +#define BASS_BOOST_ENABLE_PARAM_LEN 1 +#define BASS_BOOST_MODE_PARAM_LEN 1 +#define BASS_BOOST_STRENGTH_PARAM_LEN 1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define EQ_MODULE 0x00004000 +#define EQ_ENABLE 0x00004001 +#define EQ_CONFIG 0x00004002 +#define EQ_NUM_BANDS 0x00004003 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define EQ_BAND_LEVELS 0x00004004 +#define EQ_BAND_LEVEL_RANGE 0x00004005 +#define EQ_BAND_FREQS 0x00004006 +#define EQ_SINGLE_BAND_FREQ_RANGE 0x00004007 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define EQ_SINGLE_BAND_FREQ 0x00004008 +#define EQ_BAND_INDEX 0x00004009 +#define EQ_PRESET_ID 0x0000400a +#define EQ_NUM_PRESETS 0x0000400b +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define EQ_PRESET_NAME 0x0000400c +#define EQ_ENABLE_PARAM_LEN 1 +#define EQ_CONFIG_PARAM_LEN 3 +#define EQ_CONFIG_PER_BAND_PARAM_LEN 5 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define EQ_NUM_BANDS_PARAM_LEN 1 +#define EQ_BAND_LEVELS_PARAM_LEN 13 +#define EQ_BAND_LEVEL_RANGE_PARAM_LEN 2 +#define EQ_BAND_FREQS_PARAM_LEN 13 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define EQ_SINGLE_BAND_FREQ_RANGE_PARAM_LEN 2 +#define EQ_SINGLE_BAND_FREQ_PARAM_LEN 1 +#define EQ_BAND_INDEX_PARAM_LEN 1 +#define EQ_PRESET_ID_PARAM_LEN 1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define EQ_NUM_PRESETS_PARAM_LEN 1 +#define EQ_PRESET_NAME_PARAM_LEN 32 +#define EQ_TYPE_NONE 0 +#define EQ_BASS_BOOST 1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define EQ_BASS_CUT 2 +#define EQ_TREBLE_BOOST 3 +#define EQ_TREBLE_CUT 4 +#define EQ_BAND_BOOST 5 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define EQ_BAND_CUT 6 +#define SOFT_VOLUME_MODULE 0x00006000 +#define SOFT_VOLUME_ENABLE 0x00006001 +#define SOFT_VOLUME_GAIN_2CH 0x00006002 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SOFT_VOLUME_GAIN_MASTER 0x00006003 +#define SOFT_VOLUME_ENABLE_PARAM_LEN 1 +#define SOFT_VOLUME_GAIN_2CH_PARAM_LEN 2 +#define SOFT_VOLUME_GAIN_MASTER_PARAM_LEN 1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SOFT_VOLUME2_MODULE 0x00007000 +#define SOFT_VOLUME2_ENABLE 0x00007001 +#define SOFT_VOLUME2_GAIN_2CH 0x00007002 +#define SOFT_VOLUME2_GAIN_MASTER 0x00007003 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SOFT_VOLUME2_ENABLE_PARAM_LEN SOFT_VOLUME_ENABLE_PARAM_LEN +#define SOFT_VOLUME2_GAIN_2CH_PARAM_LEN SOFT_VOLUME_GAIN_2CH_PARAM_LEN +#define SOFT_VOLUME2_GAIN_MASTER_PARAM_LEN SOFT_VOLUME_GAIN_MASTER_PARAM_LEN +#define COMMAND_PAYLOAD_LEN 3 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define COMMAND_PAYLOAD_SZ (COMMAND_PAYLOAD_LEN * sizeof(uint32_t)) +#define MAX_INBAND_PARAM_SZ 4096 +#define Q27_UNITY (1 << 27) +#define Q8_UNITY (1 << 8) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define CUSTOM_OPENSL_PRESET 18 +#define VIRTUALIZER_ENABLE_PARAM_SZ (VIRTUALIZER_ENABLE_PARAM_LEN*sizeof(uint32_t)) +#define VIRTUALIZER_STRENGTH_PARAM_SZ (VIRTUALIZER_STRENGTH_PARAM_LEN*sizeof(uint32_t)) +#define VIRTUALIZER_OUT_TYPE_PARAM_SZ (VIRTUALIZER_OUT_TYPE_PARAM_LEN*sizeof(uint32_t)) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VIRTUALIZER_GAIN_ADJUST_PARAM_SZ (VIRTUALIZER_GAIN_ADJUST_PARAM_LEN*sizeof(uint32_t)) +struct virtualizer_params { + uint32_t device; + uint32_t enable_flag; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t strength; + uint32_t out_type; + int32_t gain_adjust; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define NUM_OSL_REVERB_PRESETS_SUPPORTED 6 +#define REVERB_ENABLE_PARAM_SZ (REVERB_ENABLE_PARAM_LEN*sizeof(uint32_t)) +#define REVERB_MODE_PARAM_SZ (REVERB_MODE_PARAM_LEN*sizeof(uint32_t)) +#define REVERB_PRESET_PARAM_SZ (REVERB_PRESET_PARAM_LEN*sizeof(uint32_t)) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define REVERB_WET_MIX_PARAM_SZ (REVERB_WET_MIX_PARAM_LEN*sizeof(uint32_t)) +#define REVERB_GAIN_ADJUST_PARAM_SZ (REVERB_GAIN_ADJUST_PARAM_LEN*sizeof(uint32_t)) +#define REVERB_ROOM_LEVEL_PARAM_SZ (REVERB_ROOM_LEVEL_PARAM_LEN*sizeof(uint32_t)) +#define REVERB_ROOM_HF_LEVEL_PARAM_SZ (REVERB_ROOM_HF_LEVEL_PARAM_LEN*sizeof(uint32_t)) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define REVERB_DECAY_TIME_PARAM_SZ (REVERB_DECAY_TIME_PARAM_LEN*sizeof(uint32_t)) +#define REVERB_DECAY_HF_RATIO_PARAM_SZ (REVERB_DECAY_HF_RATIO_PARAM_LEN*sizeof(uint32_t)) +#define REVERB_REFLECTIONS_LEVEL_PARAM_SZ (REVERB_REFLECTIONS_LEVEL_PARAM_LEN*sizeof(uint32_t)) +#define REVERB_REFLECTIONS_DELAY_PARAM_SZ (REVERB_REFLECTIONS_DELAY_PARAM_LEN*sizeof(uint32_t)) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define REVERB_LEVEL_PARAM_SZ (REVERB_LEVEL_PARAM_LEN*sizeof(uint32_t)) +#define REVERB_DELAY_PARAM_SZ (REVERB_DELAY_PARAM_LEN*sizeof(uint32_t)) +#define REVERB_DIFFUSION_PARAM_SZ (REVERB_DIFFUSION_PARAM_LEN*sizeof(uint32_t)) +#define REVERB_DENSITY_PARAM_SZ (REVERB_DENSITY_PARAM_LEN*sizeof(uint32_t)) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct reverb_params { + uint32_t device; + uint32_t enable_flag; + uint32_t mode; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t preset; + uint32_t wet_mix; + int32_t gain_adjust; + int32_t room_level; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + int32_t room_hf_level; + uint32_t decay_time; + uint32_t decay_hf_ratio; + int32_t reflections_level; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t reflections_delay; + int32_t level; + uint32_t delay; + uint32_t diffusion; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t density; +}; +#define BASS_BOOST_ENABLE_PARAM_SZ (BASS_BOOST_ENABLE_PARAM_LEN*sizeof(uint32_t)) +#define BASS_BOOST_MODE_PARAM_SZ (BASS_BOOST_MODE_PARAM_LEN*sizeof(uint32_t)) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define BASS_BOOST_STRENGTH_PARAM_SZ (BASS_BOOST_STRENGTH_PARAM_LEN*sizeof(uint32_t)) +struct bass_boost_params { + uint32_t device; + uint32_t enable_flag; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t mode; + uint32_t strength; +}; +#define MAX_EQ_BANDS 12 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define MAX_OSL_EQ_BANDS 5 +#define EQ_ENABLE_PARAM_SZ (EQ_ENABLE_PARAM_LEN*sizeof(uint32_t)) +#define EQ_CONFIG_PARAM_SZ (EQ_CONFIG_PARAM_LEN*sizeof(uint32_t)) +#define EQ_CONFIG_PER_BAND_PARAM_SZ (EQ_CONFIG_PER_BAND_PARAM_LEN*sizeof(uint32_t)) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define EQ_CONFIG_PARAM_MAX_LEN (EQ_CONFIG_PARAM_LEN+ MAX_EQ_BANDS*EQ_CONFIG_PER_BAND_PARAM_LEN) +#define EQ_CONFIG_PARAM_MAX_SZ (EQ_CONFIG_PARAM_MAX_LEN*sizeof(uint32_t)) +#define EQ_NUM_BANDS_PARAM_SZ (EQ_NUM_BANDS_PARAM_LEN*sizeof(uint32_t)) +#define EQ_BAND_LEVELS_PARAM_SZ (EQ_BAND_LEVELS_PARAM_LEN*sizeof(uint32_t)) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define EQ_BAND_LEVEL_RANGE_PARAM_SZ (EQ_BAND_LEVEL_RANGE_PARAM_LEN*sizeof(uint32_t)) +#define EQ_BAND_FREQS_PARAM_SZ (EQ_BAND_FREQS_PARAM_LEN*sizeof(uint32_t)) +#define EQ_SINGLE_BAND_FREQ_RANGE_PARAM_SZ (EQ_SINGLE_BAND_FREQ_RANGE_PARAM_LEN*sizeof(uint32_t)) +#define EQ_SINGLE_BAND_FREQ_PARAM_SZ (EQ_SINGLE_BAND_FREQ_PARAM_LEN*sizeof(uint32_t)) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define EQ_BAND_INDEX_PARAM_SZ (EQ_BAND_INDEX_PARAM_LEN*sizeof(uint32_t)) +#define EQ_PRESET_ID_PARAM_SZ (EQ_PRESET_ID_PARAM_LEN*sizeof(uint32_t)) +#define EQ_NUM_PRESETS_PARAM_SZ (EQ_NUM_PRESETS_PARAM_LEN*sizeof(uint8_t)) +struct eq_config_t { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + int32_t eq_pregain; + int32_t preset_id; + uint32_t num_bands; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct eq_per_band_config_t { + int32_t band_idx; + uint32_t filter_type; + uint32_t freq_millihertz; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + int32_t gain_millibels; + uint32_t quality_factor; +}; +struct eq_per_band_freq_range_t { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t band_index; + uint32_t min_freq_millihertz; + uint32_t max_freq_millihertz; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct eq_params { + uint32_t device; + uint32_t enable_flag; + struct eq_config_t config; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + struct eq_per_band_config_t per_band_cfg[MAX_EQ_BANDS]; + struct eq_per_band_freq_range_t per_band_freq_range[MAX_EQ_BANDS]; + uint32_t band_index; + uint32_t freq_millihertz; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +#define SOFT_VOLUME_ENABLE_PARAM_SZ (SOFT_VOLUME_ENABLE_PARAM_LEN*sizeof(uint32_t)) +#define SOFT_VOLUME_GAIN_MASTER_PARAM_SZ (SOFT_VOLUME_GAIN_MASTER_PARAM_LEN*sizeof(uint32_t)) +#define SOFT_VOLUME_GAIN_2CH_PARAM_SZ (SOFT_VOLUME_GAIN_2CH_PARAM_LEN*sizeof(uint16_t)) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct soft_volume_params { + uint32_t device; + uint32_t enable_flag; + uint32_t master_gain; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t left_gain; + uint32_t right_gain; +}; +struct msm_nt_eff_all_config { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + struct bass_boost_params bass_boost; + struct virtualizer_params virtualizer; + struct reverb_params reverb; + struct eq_params equalizer; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + struct soft_volume_params saplus_vol; + struct soft_volume_params topo_switch_vol; +}; +#endif +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + diff --git a/kernel-headers/sound/compress_offload.h b/kernel-headers/sound/compress_offload.h new file mode 100644 index 0000000..9c65f9a --- /dev/null +++ b/kernel-headers/sound/compress_offload.h @@ -0,0 +1,117 @@ +/**************************************************************************** + **************************************************************************** + *** + *** This header was automatically generated from a Linux kernel header + *** of the same name, to make information necessary for userspace to + *** call into the kernel available to libc. It contains only constants, + *** structures, and macros generated from the original header, and thus, + *** contains no copyrightable information. + *** + *** To edit the content of this header, modify the corresponding + *** source file (e.g. under external/kernel-headers/original/) then + *** run bionic/libc/kernel/tools/update_all.py + *** + *** Any manual change here will be lost the next time this script will + *** be run. You've been warned! + *** + **************************************************************************** + ****************************************************************************/ +#ifndef __COMPRESS_OFFLOAD_H +#define __COMPRESS_OFFLOAD_H +#include <linux/types.h> +#include <sound/asound.h> +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#include <sound/compress_params.h> +#define SNDRV_COMPRESS_VERSION SNDRV_PROTOCOL_VERSION(0, 1, 2) +struct snd_compressed_buffer { + __u32 fragment_size; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u32 fragments; +}; +struct snd_compr_params { + struct snd_compressed_buffer buffer; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + struct snd_codec codec; + __u8 no_wake_mode; +}; +struct snd_compr_tstamp { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u32 byte_offset; + __u32 copied_total; + __u32 pcm_frames; + __u32 pcm_io_frames; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u32 sampling_rate; + uint64_t timestamp; +}; +struct snd_compr_avail { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u64 avail; + struct snd_compr_tstamp tstamp; +} __attribute__((packed)); +enum snd_compr_direction { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + SND_COMPRESS_PLAYBACK = 0, + SND_COMPRESS_CAPTURE +}; +struct snd_compr_caps { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u32 num_codecs; + __u32 direction; + __u32 min_fragment_size; + __u32 max_fragment_size; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u32 min_fragments; + __u32 max_fragments; + __u32 codecs[MAX_NUM_CODECS]; + __u32 reserved[11]; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +struct snd_compr_codec_caps { + __u32 codec; + __u32 num_descriptors; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + struct snd_codec_desc descriptor[MAX_NUM_CODEC_DESCRIPTORS]; +}; +struct snd_compr_audio_info { + uint32_t frame_size; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t reserved[15]; +}; +enum { + SNDRV_COMPRESS_ENCODER_PADDING = 1, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + SNDRV_COMPRESS_ENCODER_DELAY = 2, +}; +struct snd_compr_metadata { + __u32 key; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u32 value[8]; +}; +#define SNDRV_COMPRESS_IOCTL_VERSION _IOR('C', 0x00, int) +#define SNDRV_COMPRESS_GET_CAPS _IOWR('C', 0x10, struct snd_compr_caps) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SNDRV_COMPRESS_GET_CODEC_CAPS _IOWR('C', 0x11, struct snd_compr_codec_caps) +#define SNDRV_COMPRESS_SET_PARAMS _IOW('C', 0x12, struct snd_compr_params) +#define SNDRV_COMPRESS_GET_PARAMS _IOR('C', 0x13, struct snd_codec) +#define SNDRV_COMPRESS_SET_METADATA _IOW('C', 0x14, struct snd_compr_metadata) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SNDRV_COMPRESS_GET_METADATA _IOWR('C', 0x15, struct snd_compr_metadata) +#define SNDRV_COMPRESS_TSTAMP _IOR('C', 0x20, struct snd_compr_tstamp) +#define SNDRV_COMPRESS_AVAIL _IOR('C', 0x21, struct snd_compr_avail) +#define SNDRV_COMPRESS_PAUSE _IO('C', 0x30) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SNDRV_COMPRESS_RESUME _IO('C', 0x31) +#define SNDRV_COMPRESS_START _IO('C', 0x32) +#define SNDRV_COMPRESS_STOP _IO('C', 0x33) +#define SNDRV_COMPRESS_DRAIN _IO('C', 0x34) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SNDRV_COMPRESS_NEXT_TRACK _IO('C', 0x35) +#define SNDRV_COMPRESS_PARTIAL_DRAIN _IO('C', 0x36) +#define SND_COMPR_TRIGGER_DRAIN 7 +#define SND_COMPR_TRIGGER_NEXT_TRACK 8 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SND_COMPR_TRIGGER_PARTIAL_DRAIN 9 +#define SNDRV_COMPRESS_METADATA_MODE _IOW('C', 0x99, bool) +#endif + diff --git a/kernel-headers/sound/compress_params.h b/kernel-headers/sound/compress_params.h new file mode 100644 index 0000000..10bbb68 --- /dev/null +++ b/kernel-headers/sound/compress_params.h @@ -0,0 +1,291 @@ +/**************************************************************************** + **************************************************************************** + *** + *** This header was automatically generated from a Linux kernel header + *** of the same name, to make information necessary for userspace to + *** call into the kernel available to libc. It contains only constants, + *** structures, and macros generated from the original header, and thus, + *** contains no copyrightable information. + *** + *** To edit the content of this header, modify the corresponding + *** source file (e.g. under external/kernel-headers/original/) then + *** run bionic/libc/kernel/tools/update_all.py + *** + *** Any manual change here will be lost the next time this script will + *** be run. You've been warned! + *** + **************************************************************************** + ****************************************************************************/ +#ifndef __SND_COMPRESS_PARAMS_H +#define __SND_COMPRESS_PARAMS_H +#include <linux/types.h> +#define MAX_NUM_CODECS 32 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define MAX_NUM_CODEC_DESCRIPTORS 32 +#define MAX_NUM_BITRATES 32 +#define MAX_NUM_FRAMES_PER_BUFFER 1 +#define COMPRESSED_META_DATA_MODE 0x10 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define META_DATA_LEN_BYTES 36 +#define Q6_AC3_DECODER 0x00010BF6 +#define Q6_EAC3_DECODER 0x00010C3C +#define Q6_DTS 0x00010D88 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define Q6_DTS_LBR 0x00010DBB +#define SND_AUDIOCODEC_PCM ((__u32) 0x00000001) +#define SND_AUDIOCODEC_MP3 ((__u32) 0x00000002) +#define SND_AUDIOCODEC_AMR ((__u32) 0x00000003) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SND_AUDIOCODEC_AMRWB ((__u32) 0x00000004) +#define SND_AUDIOCODEC_AMRWBPLUS ((__u32) 0x00000005) +#define SND_AUDIOCODEC_AAC ((__u32) 0x00000006) +#define SND_AUDIOCODEC_WMA ((__u32) 0x00000007) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SND_AUDIOCODEC_REAL ((__u32) 0x00000008) +#define SND_AUDIOCODEC_VORBIS ((__u32) 0x00000009) +#define SND_AUDIOCODEC_FLAC ((__u32) 0x0000000A) +#define SND_AUDIOCODEC_IEC61937 ((__u32) 0x0000000B) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SND_AUDIOCODEC_G723_1 ((__u32) 0x0000000C) +#define SND_AUDIOCODEC_G729 ((__u32) 0x0000000D) +#define SND_AUDIOCODEC_DTS_PASS_THROUGH ((__u32) 0x0000000E) +#define SND_AUDIOCODEC_DTS_LBR ((__u32) 0x0000000F) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SND_AUDIOCODEC_DTS_TRANSCODE_LOOPBACK ((__u32) 0x00000010) +#define SND_AUDIOCODEC_PASS_THROUGH ((__u32) 0x00000011) +#define SND_AUDIOCODEC_MP2 ((__u32) 0x00000012) +#define SND_AUDIOCODEC_DTS_LBR_PASS_THROUGH ((__u32) 0x00000013) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SND_AUDIOCODEC_AC3 ((__u32) 0x00000014) +#define SND_AUDIOCODEC_AC3_PASS_THROUGH ((__u32) 0x00000015) +#define SND_AUDIOCODEC_WMA_PRO ((__u32) 0x00000016) +#define SND_AUDIOCODEC_DTS ((__u32) 0x00000017) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SND_AUDIOCODEC_EAC3 ((__u32) 0x00000018) +#define SND_AUDIOCODEC_MAX SND_AUDIOCODEC_EAC3 +#define SND_AUDIOPROFILE_PCM ((__u32) 0x00000001) +#define SND_AUDIOCHANMODE_MP3_MONO ((__u32) 0x00000001) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SND_AUDIOCHANMODE_MP3_STEREO ((__u32) 0x00000002) +#define SND_AUDIOCHANMODE_MP3_JOINTSTEREO ((__u32) 0x00000004) +#define SND_AUDIOCHANMODE_MP3_DUAL ((__u32) 0x00000008) +#define SND_AUDIOPROFILE_AMR ((__u32) 0x00000001) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SND_AUDIOMODE_AMR_DTX_OFF ((__u32) 0x00000001) +#define SND_AUDIOMODE_AMR_VAD1 ((__u32) 0x00000002) +#define SND_AUDIOMODE_AMR_VAD2 ((__u32) 0x00000004) +#define SND_AUDIOSTREAMFORMAT_UNDEFINED ((__u32) 0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SND_AUDIOSTREAMFORMAT_CONFORMANCE ((__u32) 0x00000001) +#define SND_AUDIOSTREAMFORMAT_IF1 ((__u32) 0x00000002) +#define SND_AUDIOSTREAMFORMAT_IF2 ((__u32) 0x00000004) +#define SND_AUDIOSTREAMFORMAT_FSF ((__u32) 0x00000008) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SND_AUDIOSTREAMFORMAT_RTPPAYLOAD ((__u32) 0x00000010) +#define SND_AUDIOSTREAMFORMAT_ITU ((__u32) 0x00000020) +#define SND_AUDIOPROFILE_AMRWB ((__u32) 0x00000001) +#define SND_AUDIOMODE_AMRWB_DTX_OFF ((__u32) 0x00000001) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SND_AUDIOMODE_AMRWB_VAD1 ((__u32) 0x00000002) +#define SND_AUDIOMODE_AMRWB_VAD2 ((__u32) 0x00000004) +#define SND_AUDIOPROFILE_AMRWBPLUS ((__u32) 0x00000001) +#define SND_AUDIOPROFILE_AAC ((__u32) 0x00000001) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SND_AUDIOMODE_AAC_MAIN ((__u32) 0x00000001) +#define SND_AUDIOMODE_AAC_LC ((__u32) 0x00000002) +#define SND_AUDIOMODE_AAC_SSR ((__u32) 0x00000004) +#define SND_AUDIOMODE_AAC_LTP ((__u32) 0x00000008) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SND_AUDIOMODE_AAC_HE ((__u32) 0x00000010) +#define SND_AUDIOMODE_AAC_SCALABLE ((__u32) 0x00000020) +#define SND_AUDIOMODE_AAC_ERLC ((__u32) 0x00000040) +#define SND_AUDIOMODE_AAC_LD ((__u32) 0x00000080) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SND_AUDIOMODE_AAC_HE_PS ((__u32) 0x00000100) +#define SND_AUDIOMODE_AAC_HE_MPS ((__u32) 0x00000200) +#define SND_AUDIOSTREAMFORMAT_MP2ADTS ((__u32) 0x00000001) +#define SND_AUDIOSTREAMFORMAT_MP4ADTS ((__u32) 0x00000002) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SND_AUDIOSTREAMFORMAT_MP4LOAS ((__u32) 0x00000004) +#define SND_AUDIOSTREAMFORMAT_MP4LATM ((__u32) 0x00000008) +#define SND_AUDIOSTREAMFORMAT_ADIF ((__u32) 0x00000010) +#define SND_AUDIOSTREAMFORMAT_MP4FF ((__u32) 0x00000020) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SND_AUDIOSTREAMFORMAT_RAW ((__u32) 0x00000040) +#define SND_AUDIOPROFILE_WMA7 ((__u32) 0x00000001) +#define SND_AUDIOPROFILE_WMA8 ((__u32) 0x00000002) +#define SND_AUDIOPROFILE_WMA9 ((__u32) 0x00000004) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SND_AUDIOPROFILE_WMA10 ((__u32) 0x00000008) +#define SND_AUDIOMODE_WMA_LEVEL1 ((__u32) 0x00000001) +#define SND_AUDIOMODE_WMA_LEVEL2 ((__u32) 0x00000002) +#define SND_AUDIOMODE_WMA_LEVEL3 ((__u32) 0x00000004) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SND_AUDIOMODE_WMA_LEVEL4 ((__u32) 0x00000008) +#define SND_AUDIOMODE_WMAPRO_LEVELM0 ((__u32) 0x00000010) +#define SND_AUDIOMODE_WMAPRO_LEVELM1 ((__u32) 0x00000020) +#define SND_AUDIOMODE_WMAPRO_LEVELM2 ((__u32) 0x00000040) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SND_AUDIOMODE_WMAPRO_LEVELM3 ((__u32) 0x00000080) +#define SND_AUDIOSTREAMFORMAT_WMA_ASF ((__u32) 0x00000001) +#define SND_AUDIOSTREAMFORMAT_WMA_NOASF_HDR ((__u32) 0x00000002) +#define SND_AUDIOPROFILE_REALAUDIO ((__u32) 0x00000001) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SND_AUDIOMODE_REALAUDIO_G2 ((__u32) 0x00000001) +#define SND_AUDIOMODE_REALAUDIO_8 ((__u32) 0x00000002) +#define SND_AUDIOMODE_REALAUDIO_10 ((__u32) 0x00000004) +#define SND_AUDIOMODE_REALAUDIO_SURROUND ((__u32) 0x00000008) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SND_AUDIOPROFILE_VORBIS ((__u32) 0x00000001) +#define SND_AUDIOMODE_VORBIS ((__u32) 0x00000001) +#define SND_AUDIOPROFILE_FLAC ((__u32) 0x00000001) +#define SND_AUDIOMODE_FLAC_LEVEL0 ((__u32) 0x00000001) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SND_AUDIOMODE_FLAC_LEVEL1 ((__u32) 0x00000002) +#define SND_AUDIOMODE_FLAC_LEVEL2 ((__u32) 0x00000004) +#define SND_AUDIOMODE_FLAC_LEVEL3 ((__u32) 0x00000008) +#define SND_AUDIOMODE_FLAC_LEVEL4 ((__u32) 0x00000010) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SND_AUDIOMODE_FLAC_LEVEL5 ((__u32) 0x00000020) +#define SND_AUDIOMODE_FLAC_LEVEL6 ((__u32) 0x00000040) +#define SND_AUDIOMODE_FLAC_LEVEL7 ((__u32) 0x00000080) +#define SND_AUDIOMODE_FLAC_LEVEL8 ((__u32) 0x00000100) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SND_AUDIOSTREAMFORMAT_FLAC ((__u32) 0x00000001) +#define SND_AUDIOSTREAMFORMAT_FLAC_OGG ((__u32) 0x00000002) +#define SND_AUDIOPROFILE_IEC61937 ((__u32) 0x00000001) +#define SND_AUDIOPROFILE_IEC61937_SPDIF ((__u32) 0x00000002) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SND_AUDIOMODE_IEC_REF_STREAM_HEADER ((__u32) 0x00000000) +#define SND_AUDIOMODE_IEC_LPCM ((__u32) 0x00000001) +#define SND_AUDIOMODE_IEC_AC3 ((__u32) 0x00000002) +#define SND_AUDIOMODE_IEC_MPEG1 ((__u32) 0x00000004) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SND_AUDIOMODE_IEC_MP3 ((__u32) 0x00000008) +#define SND_AUDIOMODE_IEC_MPEG2 ((__u32) 0x00000010) +#define SND_AUDIOMODE_IEC_AACLC ((__u32) 0x00000020) +#define SND_AUDIOMODE_IEC_DTS ((__u32) 0x00000040) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SND_AUDIOMODE_IEC_ATRAC ((__u32) 0x00000080) +#define SND_AUDIOMODE_IEC_SACD ((__u32) 0x00000100) +#define SND_AUDIOMODE_IEC_EAC3 ((__u32) 0x00000200) +#define SND_AUDIOMODE_IEC_DTS_HD ((__u32) 0x00000400) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SND_AUDIOMODE_IEC_MLP ((__u32) 0x00000800) +#define SND_AUDIOMODE_IEC_DST ((__u32) 0x00001000) +#define SND_AUDIOMODE_IEC_WMAPRO ((__u32) 0x00002000) +#define SND_AUDIOMODE_IEC_REF_CXT ((__u32) 0x00004000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SND_AUDIOMODE_IEC_HE_AAC ((__u32) 0x00008000) +#define SND_AUDIOMODE_IEC_HE_AAC2 ((__u32) 0x00010000) +#define SND_AUDIOMODE_IEC_MPEG_SURROUND ((__u32) 0x00020000) +#define SND_AUDIOPROFILE_G723_1 ((__u32) 0x00000001) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SND_AUDIOMODE_G723_1_ANNEX_A ((__u32) 0x00000001) +#define SND_AUDIOMODE_G723_1_ANNEX_B ((__u32) 0x00000002) +#define SND_AUDIOMODE_G723_1_ANNEX_C ((__u32) 0x00000004) +#define SND_AUDIOPROFILE_G729 ((__u32) 0x00000001) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SND_AUDIOMODE_G729_ANNEX_A ((__u32) 0x00000001) +#define SND_AUDIOMODE_G729_ANNEX_B ((__u32) 0x00000002) +#define SND_RATECONTROLMODE_CONSTANTBITRATE ((__u32) 0x00000001) +#define SND_RATECONTROLMODE_VARIABLEBITRATE ((__u32) 0x00000002) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct snd_enc_wma { + __u32 super_block_align; + __u32 bits_per_sample; + __u32 channelmask; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u32 encodeopt; + __u32 encodeopt1; + __u32 encodeopt2; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct snd_enc_vorbis { + __s32 quality; + __u32 managed; + __u32 max_bit_rate; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u32 min_bit_rate; + __u32 downmix; +}; +struct snd_enc_real { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u32 quant_bits; + __u32 start_region; + __u32 num_regions; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct snd_enc_flac { + __u32 num; + __u32 gain; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct snd_enc_generic { + __u32 bw; + __s32 reserved[15]; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct snd_dec_ddp { + __u32 params_length; + __u32 params_id[18]; + __u32 params_value[18]; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +struct snd_dec_flac { + __u16 sample_size; + __u16 min_blk_size; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u16 max_blk_size; + __u16 min_frame_size; + __u16 max_frame_size; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +union snd_codec_options { + struct snd_enc_wma wma; + struct snd_enc_vorbis vorbis; + struct snd_enc_real real; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + struct snd_enc_flac flac; + struct snd_enc_generic generic; + struct snd_dec_ddp ddp; + struct snd_dec_flac flac_dec; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +struct snd_codec_desc { + __u32 max_ch; + __u32 sample_rates; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u32 bit_rate[MAX_NUM_BITRATES]; + __u32 num_bitrates; + __u32 rate_control; + __u32 profiles; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u32 modes; + __u32 formats; + __u32 min_buffer; + __u32 reserved[15]; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +struct snd_codec { + __u32 id; + __u32 ch_in; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u32 ch_out; + __u32 sample_rate; + __u32 bit_rate; + __u32 rate_control; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u32 profile; + __u32 level; + __u32 ch_mode; + __u32 format; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u32 align; + __u32 compr_passthr; + union snd_codec_options options; + __u32 reserved[3]; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +#endif + diff --git a/kernel-headers/sound/lsm_params.h b/kernel-headers/sound/lsm_params.h new file mode 100644 index 0000000..34c6c55 --- /dev/null +++ b/kernel-headers/sound/lsm_params.h @@ -0,0 +1,95 @@ +/**************************************************************************** + **************************************************************************** + *** + *** This header was automatically generated from a Linux kernel header + *** of the same name, to make information necessary for userspace to + *** call into the kernel available to libc. It contains only constants, + *** structures, and macros generated from the original header, and thus, + *** contains no copyrightable information. + *** + *** To edit the content of this header, modify the corresponding + *** source file (e.g. under external/kernel-headers/original/) then + *** run bionic/libc/kernel/tools/update_all.py + *** + *** Any manual change here will be lost the next time this script will + *** be run. You've been warned! + *** + **************************************************************************** + ****************************************************************************/ +#ifndef _UAPI_LSM_PARAMS_H__ +#define _UAPI_LSM_PARAMS_H__ +#include <linux/types.h> +#include <sound/asound.h> +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SNDRV_LSM_VERSION SNDRV_PROTOCOL_VERSION(0, 1, 0) +enum lsm_app_id { + LSM_VOICE_WAKEUP_APP_ID = 1, + LSM_VOICE_WAKEUP_APP_ID_V2 = 2, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +enum lsm_detection_mode { + LSM_MODE_KEYWORD_ONLY_DETECTION = 1, + LSM_MODE_USER_KEYWORD_DETECTION +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +enum lsm_vw_status { + LSM_VOICE_WAKEUP_STATUS_RUNNING = 1, + LSM_VOICE_WAKEUP_STATUS_DETECTED, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + LSM_VOICE_WAKEUP_STATUS_END_SPEECH, + LSM_VOICE_WAKEUP_STATUS_REJECTED +}; +struct snd_lsm_sound_model { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u8 __user *data; + __u32 data_size; + enum lsm_detection_mode detection_mode; + __u16 min_keyw_confidence; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u16 min_user_confidence; + bool detect_failure; +}; +struct snd_lsm_sound_model_v2 { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u8 __user *data; + __u8 *confidence_level; + __u32 data_size; + enum lsm_detection_mode detection_mode; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u8 num_confidence_levels; + bool detect_failure; +}; +struct snd_lsm_session_data { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + enum lsm_app_id app_id; +}; +struct snd_lsm_event_status { + __u16 status; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u16 payload_size; + __u8 payload[0]; +}; +struct snd_lsm_detection_params { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u8 *conf_level; + enum lsm_detection_mode detect_mode; + __u8 num_confidence_levels; + bool detect_failure; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +#define SNDRV_LSM_REG_SND_MODEL _IOW('U', 0x00, struct snd_lsm_sound_model) +#define SNDRV_LSM_DEREG_SND_MODEL _IOW('U', 0x01, int) +#define SNDRV_LSM_EVENT_STATUS _IOW('U', 0x02, struct snd_lsm_event_status) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SNDRV_LSM_ABORT_EVENT _IOW('U', 0x03, int) +#define SNDRV_LSM_START _IOW('U', 0x04, int) +#define SNDRV_LSM_STOP _IOW('U', 0x05, int) +#define SNDRV_LSM_SET_SESSION_DATA _IOW('U', 0x06, struct snd_lsm_session_data) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SNDRV_LSM_REG_SND_MODEL_V2 _IOW('U', 0x07, struct snd_lsm_sound_model_v2) +#define SNDRV_LSM_LAB_CONTROL _IOW('U', 0x08, uint32_t) +#define SNDRV_LSM_STOP_LAB _IO('U', 0x09) +#define SNDRV_LSM_SET_PARAMS _IOW('U', 0x0A, struct snd_lsm_detection_params) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#endif + diff --git a/kernel-headers/sound/msmcal-hwdep.h b/kernel-headers/sound/msmcal-hwdep.h new file mode 100644 index 0000000..75600ee --- /dev/null +++ b/kernel-headers/sound/msmcal-hwdep.h @@ -0,0 +1,40 @@ +/**************************************************************************** + **************************************************************************** + *** + *** This header was automatically generated from a Linux kernel header + *** of the same name, to make information necessary for userspace to + *** call into the kernel available to libc. It contains only constants, + *** structures, and macros generated from the original header, and thus, + *** contains no copyrightable information. + *** + *** To edit the content of this header, modify the corresponding + *** source file (e.g. under external/kernel-headers/original/) then + *** run bionic/libc/kernel/tools/update_all.py + *** + *** Any manual change here will be lost the next time this script will + *** be run. You've been warned! + *** + **************************************************************************** + ****************************************************************************/ +#ifndef _CALIB_HWDEP_H +#define _CALIB_HWDEP_H +#define WCD9XXX_CODEC_HWDEP_NODE 1000 +enum wcd_cal_type { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + WCD9XXX_MIN_CAL, + WCD9XXX_ANC_CAL = WCD9XXX_MIN_CAL, + WCD9XXX_MAD_CAL, + WCD9XXX_MBHC_CAL, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + WCD9XXX_MAX_CAL, +}; +struct wcdcal_ioctl_buffer { + __u32 size; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u8 __user *buffer; + enum wcd_cal_type cal_type; +}; +#define SNDRV_CTL_IOCTL_HWDEP_CAL_TYPE _IOW('U', 0x1, struct wcdcal_ioctl_buffer) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#endif + diff --git a/kernel-headers/sound/voice_params.h b/kernel-headers/sound/voice_params.h new file mode 100644 index 0000000..89da779 --- /dev/null +++ b/kernel-headers/sound/voice_params.h @@ -0,0 +1,31 @@ +/**************************************************************************** + **************************************************************************** + *** + *** This header was automatically generated from a Linux kernel header + *** of the same name, to make information necessary for userspace to + *** call into the kernel available to libc. It contains only constants, + *** structures, and macros generated from the original header, and thus, + *** contains no copyrightable information. + *** + *** To edit the content of this header, modify the corresponding + *** source file (e.g. under external/kernel-headers/original/) then + *** run bionic/libc/kernel/tools/update_all.py + *** + *** Any manual change here will be lost the next time this script will + *** be run. You've been warned! + *** + **************************************************************************** + ****************************************************************************/ +#ifndef __VOICE_PARAMS_H__ +#define __VOICE_PARAMS_H__ +#include <linux/types.h> +#include <sound/asound.h> +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +enum voice_lch_mode { + VOICE_LCH_START = 1, + VOICE_LCH_STOP +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SNDRV_VOICE_IOCTL_LCH _IOW('U', 0x00, enum voice_lch_mode) +#endif + diff --git a/kernel-headers/video/msm_hdmi_modes.h b/kernel-headers/video/msm_hdmi_modes.h new file mode 100644 index 0000000..f2ff0b0 --- /dev/null +++ b/kernel-headers/video/msm_hdmi_modes.h @@ -0,0 +1,267 @@ +/**************************************************************************** + **************************************************************************** + *** + *** This header was automatically generated from a Linux kernel header + *** of the same name, to make information necessary for userspace to + *** call into the kernel available to libc. It contains only constants, + *** structures, and macros generated from the original header, and thus, + *** contains no copyrightable information. + *** + *** To edit the content of this header, modify the corresponding + *** source file (e.g. under external/kernel-headers/original/) then + *** run bionic/libc/kernel/tools/update_all.py + *** + *** Any manual change here will be lost the next time this script will + *** be run. You've been warned! + *** + **************************************************************************** + ****************************************************************************/ +#ifndef _UAPI_MSM_HDMI_MODES_H__ +#define _UAPI_MSM_HDMI_MODES_H__ +#include <linux/types.h> +enum aspect_ratio { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + HDMI_RES_AR_INVALID, + HDMI_RES_AR_4_3, + HDMI_RES_AR_5_4, + HDMI_RES_AR_16_9, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + HDMI_RES_AR_16_10, + HDMI_RES_AR_MAX, +}; +struct msm_hdmi_mode_timing_info { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t video_format; + uint32_t active_h; + uint32_t front_porch_h; + uint32_t pulse_width_h; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t back_porch_h; + uint32_t active_low_h; + uint32_t active_v; + uint32_t front_porch_v; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t pulse_width_v; + uint32_t back_porch_v; + uint32_t active_low_v; + uint32_t pixel_freq; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t refresh_rate; + uint32_t interlaced; + uint32_t supported; + enum aspect_ratio ar; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +#define MSM_HDMI_INIT_RES_PAGE 1 +#define MSM_HDMI_MODES_CEA (1 << 0) +#define MSM_HDMI_MODES_XTND (1 << 1) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define MSM_HDMI_MODES_DVI (1 << 2) +#define MSM_HDMI_MODES_ALL (MSM_HDMI_MODES_CEA | MSM_HDMI_MODES_XTND | MSM_HDMI_MODES_DVI) +#define HDMI_VFRMT_UNKNOWN 0 +#define HDMI_VFRMT_640x480p60_4_3 1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define HDMI_VFRMT_720x480p60_4_3 2 +#define HDMI_VFRMT_720x480p60_16_9 3 +#define HDMI_VFRMT_1280x720p60_16_9 4 +#define HDMI_VFRMT_1920x1080i60_16_9 5 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define HDMI_VFRMT_720x480i60_4_3 6 +#define HDMI_VFRMT_1440x480i60_4_3 HDMI_VFRMT_720x480i60_4_3 +#define HDMI_VFRMT_720x480i60_16_9 7 +#define HDMI_VFRMT_1440x480i60_16_9 HDMI_VFRMT_720x480i60_16_9 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define HDMI_VFRMT_720x240p60_4_3 8 +#define HDMI_VFRMT_1440x240p60_4_3 HDMI_VFRMT_720x240p60_4_3 +#define HDMI_VFRMT_720x240p60_16_9 9 +#define HDMI_VFRMT_1440x240p60_16_9 HDMI_VFRMT_720x240p60_16_9 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define HDMI_VFRMT_2880x480i60_4_3 10 +#define HDMI_VFRMT_2880x480i60_16_9 11 +#define HDMI_VFRMT_2880x240p60_4_3 12 +#define HDMI_VFRMT_2880x240p60_16_9 13 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define HDMI_VFRMT_1440x480p60_4_3 14 +#define HDMI_VFRMT_1440x480p60_16_9 15 +#define HDMI_VFRMT_1920x1080p60_16_9 16 +#define HDMI_VFRMT_720x576p50_4_3 17 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define HDMI_VFRMT_720x576p50_16_9 18 +#define HDMI_VFRMT_1280x720p50_16_9 19 +#define HDMI_VFRMT_1920x1080i50_16_9 20 +#define HDMI_VFRMT_720x576i50_4_3 21 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define HDMI_VFRMT_1440x576i50_4_3 HDMI_VFRMT_720x576i50_4_3 +#define HDMI_VFRMT_720x576i50_16_9 22 +#define HDMI_VFRMT_1440x576i50_16_9 HDMI_VFRMT_720x576i50_16_9 +#define HDMI_VFRMT_720x288p50_4_3 23 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define HDMI_VFRMT_1440x288p50_4_3 HDMI_VFRMT_720x288p50_4_3 +#define HDMI_VFRMT_720x288p50_16_9 24 +#define HDMI_VFRMT_1440x288p50_16_9 HDMI_VFRMT_720x288p50_16_9 +#define HDMI_VFRMT_2880x576i50_4_3 25 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define HDMI_VFRMT_2880x576i50_16_9 26 +#define HDMI_VFRMT_2880x288p50_4_3 27 +#define HDMI_VFRMT_2880x288p50_16_9 28 +#define HDMI_VFRMT_1440x576p50_4_3 29 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define HDMI_VFRMT_1440x576p50_16_9 30 +#define HDMI_VFRMT_1920x1080p50_16_9 31 +#define HDMI_VFRMT_1920x1080p24_16_9 32 +#define HDMI_VFRMT_1920x1080p25_16_9 33 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define HDMI_VFRMT_1920x1080p30_16_9 34 +#define HDMI_VFRMT_2880x480p60_4_3 35 +#define HDMI_VFRMT_2880x480p60_16_9 36 +#define HDMI_VFRMT_2880x576p50_4_3 37 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define HDMI_VFRMT_2880x576p50_16_9 38 +#define HDMI_VFRMT_1920x1250i50_16_9 39 +#define HDMI_VFRMT_1920x1080i100_16_9 40 +#define HDMI_VFRMT_1280x720p100_16_9 41 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define HDMI_VFRMT_720x576p100_4_3 42 +#define HDMI_VFRMT_720x576p100_16_9 43 +#define HDMI_VFRMT_720x576i100_4_3 44 +#define HDMI_VFRMT_1440x576i100_4_3 HDMI_VFRMT_720x576i100_4_3 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define HDMI_VFRMT_720x576i100_16_9 45 +#define HDMI_VFRMT_1440x576i100_16_9 HDMI_VFRMT_720x576i100_16_9 +#define HDMI_VFRMT_1920x1080i120_16_9 46 +#define HDMI_VFRMT_1280x720p120_16_9 47 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define HDMI_VFRMT_720x480p120_4_3 48 +#define HDMI_VFRMT_720x480p120_16_9 49 +#define HDMI_VFRMT_720x480i120_4_3 50 +#define HDMI_VFRMT_1440x480i120_4_3 HDMI_VFRMT_720x480i120_4_3 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define HDMI_VFRMT_720x480i120_16_9 51 +#define HDMI_VFRMT_1440x480i120_16_9 HDMI_VFRMT_720x480i120_16_9 +#define HDMI_VFRMT_720x576p200_4_3 52 +#define HDMI_VFRMT_720x576p200_16_9 53 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define HDMI_VFRMT_720x576i200_4_3 54 +#define HDMI_VFRMT_1440x576i200_4_3 HDMI_VFRMT_720x576i200_4_3 +#define HDMI_VFRMT_720x576i200_16_9 55 +#define HDMI_VFRMT_1440x576i200_16_9 HDMI_VFRMT_720x576i200_16_9 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define HDMI_VFRMT_720x480p240_4_3 56 +#define HDMI_VFRMT_720x480p240_16_9 57 +#define HDMI_VFRMT_720x480i240_4_3 58 +#define HDMI_VFRMT_1440x480i240_4_3 HDMI_VFRMT_720x480i240_4_3 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define HDMI_VFRMT_720x480i240_16_9 59 +#define HDMI_VFRMT_1440x480i240_16_9 HDMI_VFRMT_720x480i240_16_9 +#define HDMI_VFRMT_1280x720p24_16_9 60 +#define HDMI_VFRMT_1280x720p25_16_9 61 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define HDMI_VFRMT_1280x720p30_16_9 62 +#define HDMI_VFRMT_1920x1080p120_16_9 63 +#define HDMI_VFRMT_1920x1080p100_16_9 64 +#define HDMI_VFRMT_END 127 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define EVFRMT_OFF(x) (HDMI_VFRMT_END + x) +#define HDMI_VFRMT_3840x2160p30_16_9 EVFRMT_OFF(1) +#define HDMI_VFRMT_3840x2160p25_16_9 EVFRMT_OFF(2) +#define HDMI_VFRMT_3840x2160p24_16_9 EVFRMT_OFF(3) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define HDMI_VFRMT_4096x2160p24_16_9 EVFRMT_OFF(4) +#define HDMI_EVFRMT_END HDMI_VFRMT_4096x2160p24_16_9 +#define WQXGA_OFF(x) (HDMI_EVFRMT_END + x) +#define HDMI_VFRMT_2560x1600p60_16_9 WQXGA_OFF(1) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define HDMI_WQXGAFRMT_END HDMI_VFRMT_2560x1600p60_16_9 +#define WXGA_OFF(x) (HDMI_WQXGAFRMT_END + x) +#define HDMI_VFRMT_1280x800p60_16_10 WXGA_OFF(1) +#define HDMI_VFRMT_1366x768p60_16_10 WXGA_OFF(2) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define HDMI_WXGAFRMT_END HDMI_VFRMT_1366x768p60_16_10 +#define ETI_OFF(x) (HDMI_WXGAFRMT_END + x) +#define HDMI_VFRMT_800x600p60_4_3 ETI_OFF(1) +#define ETI_VFRMT_END HDMI_VFRMT_800x600p60_4_3 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define ETII_OFF(x) (ETI_VFRMT_END + x) +#define HDMI_VFRMT_1024x768p60_4_3 ETII_OFF(1) +#define HDMI_VFRMT_1280x1024p60_5_4 ETII_OFF(2) +#define ETII_VFRMT_END HDMI_VFRMT_1280x1024p60_5_4 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define ETIII_OFF(x) (ETII_VFRMT_END + x) +#define HDMI_VFRMT_848x480p60_16_9 ETIII_OFF(1) +#define HDMI_VFRMT_1280x960p60_4_3 ETIII_OFF(2) +#define HDMI_VFRMT_1360x768p60_16_9 ETIII_OFF(3) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define HDMI_VFRMT_1440x900p60_16_10 ETIII_OFF(4) +#define HDMI_VFRMT_1400x1050p60_4_3 ETIII_OFF(5) +#define HDMI_VFRMT_1680x1050p60_16_10 ETIII_OFF(6) +#define HDMI_VFRMT_1600x1200p60_4_3 ETIII_OFF(7) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define HDMI_VFRMT_1920x1200p60_16_10 ETIII_OFF(8) +#define ETIII_VFRMT_END HDMI_VFRMT_1920x1200p60_16_10 +#define RESERVE_OFF(x) (ETIII_VFRMT_END + x) +#define HDMI_VFRMT_RESERVE1 RESERVE_OFF(1) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define HDMI_VFRMT_RESERVE2 RESERVE_OFF(2) +#define HDMI_VFRMT_RESERVE3 RESERVE_OFF(3) +#define HDMI_VFRMT_RESERVE4 RESERVE_OFF(4) +#define HDMI_VFRMT_RESERVE5 RESERVE_OFF(5) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define HDMI_VFRMT_RESERVE6 RESERVE_OFF(6) +#define HDMI_VFRMT_RESERVE7 RESERVE_OFF(7) +#define HDMI_VFRMT_RESERVE8 RESERVE_OFF(8) +#define RESERVE_VFRMT_END HDMI_VFRMT_RESERVE8 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define HDMI_VFRMT_MAX (RESERVE_VFRMT_END + 1) +#define HDMI_VFRMT_FORCE_32BIT 0x7FFFFFFF +#define VFRMT_NOT_SUPPORTED(VFRMT) {VFRMT, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, false, HDMI_RES_AR_INVALID} +#define HDMI_VFRMT_640x480p60_4_3_TIMING {HDMI_VFRMT_640x480p60_4_3, 640, 16, 96, 48, true, 480, 10, 2, 33, true, 25200, 60000, false, true, HDMI_RES_AR_4_3} +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define HDMI_VFRMT_720x480p60_4_3_TIMING {HDMI_VFRMT_720x480p60_4_3, 720, 16, 62, 60, true, 480, 9, 6, 30, true, 27027, 60000, false, true, HDMI_RES_AR_4_3} +#define HDMI_VFRMT_720x480p60_16_9_TIMING {HDMI_VFRMT_720x480p60_16_9, 720, 16, 62, 60, true, 480, 9, 6, 30, true, 27027, 60000, false, true, HDMI_RES_AR_16_9} +#define HDMI_VFRMT_1280x720p60_16_9_TIMING {HDMI_VFRMT_1280x720p60_16_9, 1280, 110, 40, 220, false, 720, 5, 5, 20, false, 74250, 60000, false, true, HDMI_RES_AR_16_9} +#define HDMI_VFRMT_1920x1080i60_16_9_TIMING {HDMI_VFRMT_1920x1080i60_16_9, 1920, 88, 44, 148, false, 540, 2, 5, 5, false, 74250, 60000, false, true, HDMI_RES_AR_16_9} +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define HDMI_VFRMT_1440x480i60_4_3_TIMING {HDMI_VFRMT_1440x480i60_4_3, 1440, 38, 124, 114, true, 240, 4, 3, 15, true, 27000, 60000, true, true, HDMI_RES_AR_4_3} +#define HDMI_VFRMT_1440x480i60_16_9_TIMING {HDMI_VFRMT_1440x480i60_16_9, 1440, 38, 124, 114, true, 240, 4, 3, 15, true, 27000, 60000, true, true, HDMI_RES_AR_16_9} +#define HDMI_VFRMT_1920x1080p60_16_9_TIMING {HDMI_VFRMT_1920x1080p60_16_9, 1920, 88, 44, 148, false, 1080, 4, 5, 36, false, 148500, 60000, false, true, HDMI_RES_AR_16_9} +#define HDMI_VFRMT_720x576p50_4_3_TIMING {HDMI_VFRMT_720x576p50_4_3, 720, 12, 64, 68, true, 576, 5, 5, 39, true, 27000, 50000, false, true, HDMI_RES_AR_4_3} +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define HDMI_VFRMT_720x576p50_16_9_TIMING {HDMI_VFRMT_720x576p50_16_9, 720, 12, 64, 68, true, 576, 5, 5, 39, true, 27000, 50000, false, true, HDMI_RES_AR_16_9} +#define HDMI_VFRMT_1280x720p50_16_9_TIMING {HDMI_VFRMT_1280x720p50_16_9, 1280, 440, 40, 220, false, 720, 5, 5, 20, false, 74250, 50000, false, true, HDMI_RES_AR_16_9} +#define HDMI_VFRMT_1440x576i50_4_3_TIMING {HDMI_VFRMT_1440x576i50_4_3, 1440, 24, 126, 138, true, 288, 2, 3, 19, true, 27000, 50000, true, true, HDMI_RES_AR_4_3} +#define HDMI_VFRMT_1440x576i50_16_9_TIMING {HDMI_VFRMT_1440x576i50_16_9, 1440, 24, 126, 138, true, 288, 2, 3, 19, true, 27000, 50000, true, true, HDMI_RES_AR_16_9} +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define HDMI_VFRMT_1920x1080p50_16_9_TIMING {HDMI_VFRMT_1920x1080p50_16_9, 1920, 528, 44, 148, false, 1080, 4, 5, 36, false, 148500, 50000, false, true, HDMI_RES_AR_16_9} +#define HDMI_VFRMT_1920x1080p24_16_9_TIMING {HDMI_VFRMT_1920x1080p24_16_9, 1920, 638, 44, 148, false, 1080, 4, 5, 36, false, 74250, 24000, false, true, HDMI_RES_AR_16_9} +#define HDMI_VFRMT_1920x1080p25_16_9_TIMING {HDMI_VFRMT_1920x1080p25_16_9, 1920, 528, 44, 148, false, 1080, 4, 5, 36, false, 74250, 25000, false, true, HDMI_RES_AR_16_9} +#define HDMI_VFRMT_1920x1080p30_16_9_TIMING {HDMI_VFRMT_1920x1080p30_16_9, 1920, 88, 44, 148, false, 1080, 4, 5, 36, false, 74250, 30000, false, true, HDMI_RES_AR_16_9} +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define HDMI_VFRMT_1024x768p60_4_3_TIMING {HDMI_VFRMT_1024x768p60_4_3, 1024, 24, 136, 160, false, 768, 2, 6, 29, false, 65000, 60000, false, true, HDMI_RES_AR_4_3} +#define HDMI_VFRMT_1280x1024p60_5_4_TIMING {HDMI_VFRMT_1280x1024p60_5_4, 1280, 48, 112, 248, false, 1024, 1, 3, 38, false, 108000, 60000, false, true, HDMI_RES_AR_5_4} +#define HDMI_VFRMT_2560x1600p60_16_9_TIMING {HDMI_VFRMT_2560x1600p60_16_9, 2560, 48, 32, 80, false, 1600, 3, 6, 37, false, 268500, 60000, false, true, HDMI_RES_AR_16_9} +#define HDMI_VFRMT_3840x2160p30_16_9_TIMING {HDMI_VFRMT_3840x2160p30_16_9, 3840, 176, 88, 296, false, 2160, 8, 10, 72, false, 297000, 30000, false, true, HDMI_RES_AR_16_9} +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define HDMI_VFRMT_3840x2160p25_16_9_TIMING {HDMI_VFRMT_3840x2160p25_16_9, 3840, 1056, 88, 296, false, 2160, 8, 10, 72, false, 297000, 25000, false, true, HDMI_RES_AR_16_9} +#define HDMI_VFRMT_3840x2160p24_16_9_TIMING {HDMI_VFRMT_3840x2160p24_16_9, 3840, 1276, 88, 296, false, 2160, 8, 10, 72, false, 297000, 24000, false, true, HDMI_RES_AR_16_9} +#define HDMI_VFRMT_4096x2160p24_16_9_TIMING {HDMI_VFRMT_4096x2160p24_16_9, 4096, 1020, 88, 296, false, 2160, 8, 10, 72, false, 297000, 24000, false, true, HDMI_RES_AR_16_9} +#define HDMI_VFRMT_800x600p60_4_3_TIMING {HDMI_VFRMT_800x600p60_4_3, 800, 40, 128, 88, false, 600, 1, 4, 23, false, 40000, 60000, false, true, HDMI_RES_AR_4_3} +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define HDMI_VFRMT_848x480p60_16_9_TIMING {HDMI_VFRMT_848x480p60_16_9, 848, 16, 112, 112, false, 480, 6, 8, 23, false, 33750, 60000, false, true, HDMI_RES_AR_16_9} +#define HDMI_VFRMT_1280x960p60_4_3_TIMING {HDMI_VFRMT_1280x960p60_4_3, 1280, 96, 112, 312, false, 960, 1, 3, 36, false, 108000, 60000, false, true, HDMI_RES_AR_4_3} +#define HDMI_VFRMT_1360x768p60_16_9_TIMING {HDMI_VFRMT_1360x768p60_16_9, 1360, 64, 112, 256, false, 768, 3, 6, 18, false, 85500, 60000, false, true, HDMI_RES_AR_16_9} +#define HDMI_VFRMT_1440x900p60_16_10_TIMING {HDMI_VFRMT_1440x900p60_16_10, 1440, 48, 32, 80, false, 900, 3, 6, 17, true, 88750, 60000, false, true, HDMI_RES_AR_16_10} +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define HDMI_VFRMT_1400x1050p60_4_3_TIMING {HDMI_VFRMT_1400x1050p60_4_3, 1400, 48, 32, 80, false, 1050, 3, 4, 23, true, 101000, 60000, false, true, HDMI_RES_AR_4_3} +#define HDMI_VFRMT_1680x1050p60_16_10_TIMING {HDMI_VFRMT_1680x1050p60_16_10, 1680, 48, 32, 80, false, 1050, 3, 6, 21, true, 119000, 60000, false, true, HDMI_RES_AR_16_10} +#define HDMI_VFRMT_1600x1200p60_4_3_TIMING {HDMI_VFRMT_1600x1200p60_4_3, 1600, 64, 192, 304, false, 1200, 1, 3, 46, false, 162000, 60000, false, true, HDMI_RES_AR_4_3} +#define HDMI_VFRMT_1920x1200p60_16_10_TIMING {HDMI_VFRMT_1920x1200p60_16_10, 1920, 48, 32, 80, false, 1200, 3, 6, 26, true, 154000, 60000, false, true, HDMI_RES_AR_16_10} +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define HDMI_VFRMT_1366x768p60_16_10_TIMING {HDMI_VFRMT_1366x768p60_16_10, 1366, 70, 143, 213, false, 768, 3, 3, 24, false, 85500, 60000, false, true, HDMI_RES_AR_16_10} +#define HDMI_VFRMT_1280x800p60_16_10_TIMING {HDMI_VFRMT_1280x800p60_16_10, 1280, 72, 128, 200, true, 800, 3, 6, 22, false, 83500, 60000, false, true, HDMI_RES_AR_16_10} +#define MSM_HDMI_MODES_SET_TIMING(LUT, MODE) do { struct msm_hdmi_mode_timing_info mode = MODE##_TIMING; LUT[MODE] = mode; } while (0) +#define MSM_HDMI_MODES_INIT_TIMINGS(__lut) do { unsigned int i; for (i = 0; i < HDMI_VFRMT_MAX; i++) { struct msm_hdmi_mode_timing_info mode = VFRMT_NOT_SUPPORTED(i); (__lut)[i] = mode; } } while (0) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define MSM_HDMI_MODES_SET_SUPP_TIMINGS(__lut, __type) do { if (__type & MSM_HDMI_MODES_CEA) { MSM_HDMI_MODES_SET_TIMING(__lut, HDMI_VFRMT_640x480p60_4_3); MSM_HDMI_MODES_SET_TIMING(__lut, HDMI_VFRMT_720x480p60_4_3); MSM_HDMI_MODES_SET_TIMING(__lut, HDMI_VFRMT_720x480p60_16_9); MSM_HDMI_MODES_SET_TIMING(__lut, HDMI_VFRMT_1280x720p60_16_9); MSM_HDMI_MODES_SET_TIMING(__lut, HDMI_VFRMT_1920x1080i60_16_9); MSM_HDMI_MODES_SET_TIMING(__lut, HDMI_VFRMT_1440x480i60_4_3); MSM_HDMI_MODES_SET_TIMING(__lut, HDMI_VFRMT_1440x480i60_16_9); MSM_HDMI_MODES_SET_TIMING(__lut, HDMI_VFRMT_1920x1080p60_16_9); MSM_HDMI_MODES_SET_TIMING(__lut, HDMI_VFRMT_720x576p50_4_3); MSM_HDMI_MODES_SET_TIMING(__lut, HDMI_VFRMT_720x576p50_16_9); MSM_HDMI_MODES_SET_TIMING(__lut, HDMI_VFRMT_1280x720p50_16_9); MSM_HDMI_MODES_SET_TIMING(__lut, HDMI_VFRMT_1440x576i50_4_3); MSM_HDMI_MODES_SET_TIMING(__lut, HDMI_VFRMT_1440x576i50_16_9); MSM_HDMI_MODES_SET_TIMING(__lut, HDMI_VFRMT_1920x1080p50_16_9); MSM_HDMI_MODES_SET_TIMING(__lut, HDMI_VFRMT_1920x1080p24_16_9); MSM_HDMI_MODES_SET_TIMING(__lut, HDMI_VFRMT_1920x1080p25_16_9); MSM_HDMI_MODES_SET_TIMING(__lut, HDMI_VFRMT_1920x1080p30_16_9); } if (__type & MSM_HDMI_MODES_XTND) { MSM_HDMI_MODES_SET_TIMING(__lut, HDMI_VFRMT_3840x2160p30_16_9); MSM_HDMI_MODES_SET_TIMING(__lut, HDMI_VFRMT_3840x2160p25_16_9); MSM_HDMI_MODES_SET_TIMING(__lut, HDMI_VFRMT_3840x2160p24_16_9); MSM_HDMI_MODES_SET_TIMING(__lut, HDMI_VFRMT_4096x2160p24_16_9); } if (__type & MSM_HDMI_MODES_DVI) { MSM_HDMI_MODES_SET_TIMING(__lut, HDMI_VFRMT_1024x768p60_4_3); MSM_HDMI_MODES_SET_TIMING(__lut, HDMI_VFRMT_1280x1024p60_5_4); MSM_HDMI_MODES_SET_TIMING(__lut, HDMI_VFRMT_2560x1600p60_16_9); MSM_HDMI_MODES_SET_TIMING(__lut, HDMI_VFRMT_800x600p60_4_3); MSM_HDMI_MODES_SET_TIMING(__lut, HDMI_VFRMT_848x480p60_16_9); MSM_HDMI_MODES_SET_TIMING(__lut, HDMI_VFRMT_1280x960p60_4_3); MSM_HDMI_MODES_SET_TIMING(__lut, HDMI_VFRMT_1360x768p60_16_9); MSM_HDMI_MODES_SET_TIMING(__lut, HDMI_VFRMT_1440x900p60_16_10); MSM_HDMI_MODES_SET_TIMING(__lut, HDMI_VFRMT_1400x1050p60_4_3); MSM_HDMI_MODES_SET_TIMING(__lut, HDMI_VFRMT_1680x1050p60_16_10); MSM_HDMI_MODES_SET_TIMING(__lut, HDMI_VFRMT_1600x1200p60_4_3); MSM_HDMI_MODES_SET_TIMING(__lut, HDMI_VFRMT_1920x1200p60_16_10); MSM_HDMI_MODES_SET_TIMING(__lut, HDMI_VFRMT_1366x768p60_16_10); MSM_HDMI_MODES_SET_TIMING(__lut, HDMI_VFRMT_1280x800p60_16_10); } } while (0) +#define MSM_HDMI_MODES_GET_DETAILS(mode, MODE) do { struct msm_hdmi_mode_timing_info info = MODE##_TIMING; *mode = info; } while (0) +#endif + diff --git a/msm8992.mk b/msm8992.mk new file mode 100644 index 0000000..b2d1eff --- /dev/null +++ b/msm8992.mk @@ -0,0 +1,17 @@ +# Copyright (C) 2011 The Android Open Source Project +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +PRODUCT_VENDOR_KERNEL_HEADERS := hardware/qcom/msm8994/kernel-headers + +PRODUCT_PACKAGES += hwcomposer.msm8992 diff --git a/original-kernel-headers/linux/esoc_ctrl.h b/original-kernel-headers/linux/esoc_ctrl.h new file mode 100644 index 0000000..1e70483 --- /dev/null +++ b/original-kernel-headers/linux/esoc_ctrl.h @@ -0,0 +1,73 @@ +#ifndef _UAPI_ESOC_CTRL_H_ +#define _UAPI_ESOC_CTRL_H_ + +#define ESOC_CODE 0xCC + +#define ESOC_CMD_EXE _IOW(ESOC_CODE, 1, u32) +#define ESOC_WAIT_FOR_REQ _IOR(ESOC_CODE, 2, u32) +#define ESOC_NOTIFY _IOW(ESOC_CODE, 3, u32) +#define ESOC_GET_STATUS _IOR(ESOC_CODE, 4, u32) +#define ESOC_WAIT_FOR_CRASH _IOR(ESOC_CODE, 6, u32) +#define ESOC_REG_REQ_ENG _IO(ESOC_CODE, 7) +#define ESOC_REG_CMD_ENG _IO(ESOC_CODE, 8) + +/*Link types for communication with external SOCs*/ +#define HSIC "HSIC" +#define HSICPCIe "HSIC+PCIe" +#define PCIe "PCIe" + +enum esoc_evt { + ESOC_RUN_STATE = 0x1, + ESOC_UNEXPECTED_RESET, + ESOC_ERR_FATAL, + ESOC_IN_DEBUG, + ESOC_REQ_ENG_ON, + ESOC_REQ_ENG_OFF, + ESOC_CMD_ENG_ON, + ESOC_CMD_ENG_OFF, + ESOC_INVALID_STATE, +}; + +enum esoc_cmd { + ESOC_PWR_ON = 1, + ESOC_PWR_OFF, + ESOC_FORCE_PWR_OFF, + ESOC_RESET, + ESOC_PREPARE_DEBUG, + ESOC_EXE_DEBUG, + ESOC_EXIT_DEBUG, +}; + +enum esoc_notify { + ESOC_IMG_XFER_DONE = 1, + ESOC_BOOT_DONE, + ESOC_BOOT_FAIL, + ESOC_IMG_XFER_RETRY, + ESOC_IMG_XFER_FAIL, + ESOC_UPGRADE_AVAILABLE, + ESOC_DEBUG_DONE, + ESOC_DEBUG_FAIL, + ESOC_PRIMARY_CRASH, + ESOC_PRIMARY_REBOOT, +}; + +enum esoc_req { + ESOC_REQ_IMG = 1, + ESOC_REQ_DEBUG, + ESOC_REQ_SHUTDOWN, +}; + +#ifdef __KERNEL__ +/** + * struct esoc_handle: Handle for clients of esoc + * @name: name of the external soc. + * @link: link of external soc. + * @id: id of external soc. + */ +struct esoc_handle { + const char *name; + const char *link; + unsigned int id; +}; +#endif +#endif diff --git a/original-kernel-headers/linux/mfd/msm-adie-codec.h b/original-kernel-headers/linux/mfd/msm-adie-codec.h new file mode 100644 index 0000000..ef41d9c --- /dev/null +++ b/original-kernel-headers/linux/mfd/msm-adie-codec.h @@ -0,0 +1,146 @@ +#ifndef __UAPI_MFD_MSM_ADIE_CODEC_H +#define __UAPI_MFD_MSM_ADIE_CODEC_H + +#include <linux/types.h> + +/* Value Represents a entry */ +#define ADIE_CODEC_ACTION_ENTRY 0x1 +/* Value representing a delay wait */ +#define ADIE_CODEC_ACTION_DELAY_WAIT 0x2 +/* Value representing a stage reached */ +#define ADIE_CODEC_ACTION_STAGE_REACHED 0x3 + +/* This value is the state after the client sets the path */ +#define ADIE_CODEC_PATH_OFF 0x0050 + +/* State to which client asks the drv to proceed to where it can + * set up the clocks and 0-fill PCM buffers + */ +#define ADIE_CODEC_DIGITAL_READY 0x0100 + +/* State to which client asks the drv to proceed to where it can + * start sending data after internal steady state delay + */ +#define ADIE_CODEC_DIGITAL_ANALOG_READY 0x1000 + + +/* Client Asks adie to switch off the Analog portion of the + * the internal codec. After the use of this path + */ +#define ADIE_CODEC_ANALOG_OFF 0x0750 + + +/* Client Asks adie to switch off the digital portion of the + * the internal codec. After switching off the analog portion. + * + * 0-fill PCM may or maynot be sent at this point + * + */ +#define ADIE_CODEC_DIGITAL_OFF 0x0600 + +/* State to which client asks the drv to write the default values + * to the registers */ +#define ADIE_CODEC_FLASH_IMAGE 0x0001 + +/* Path type */ +#define ADIE_CODEC_RX 0 +#define ADIE_CODEC_TX 1 +#define ADIE_CODEC_LB 3 +#define ADIE_CODEC_MAX 4 + +#define ADIE_CODEC_PACK_ENTRY(reg, mask, val) ((val)|(mask << 8)|(reg << 16)) + +#define ADIE_CODEC_UNPACK_ENTRY(packed, reg, mask, val) \ + do { \ + ((reg) = ((packed >> 16) & (0xff))); \ + ((mask) = ((packed >> 8) & (0xff))); \ + ((val) = ((packed) & (0xff))); \ + } while (0); + +struct adie_codec_action_unit { + u32 type; + u32 action; +}; + +struct adie_codec_hwsetting_entry{ + struct adie_codec_action_unit *actions; + u32 action_sz; + u32 freq_plan; + u32 osr; + /* u32 VolMask; + * u32 SidetoneMask; + */ +}; + +struct adie_codec_dev_profile { + u32 path_type; /* RX or TX */ + u32 setting_sz; + struct adie_codec_hwsetting_entry *settings; +}; + +struct adie_codec_register { + u8 reg; + u8 mask; + u8 val; +}; + +struct adie_codec_register_image { + struct adie_codec_register *regs; + u32 img_sz; +}; + +struct adie_codec_path; + +struct adie_codec_anc_data { + u32 size; + u32 writes[]; +}; + +struct adie_codec_operations { + int codec_id; + int (*codec_open) (struct adie_codec_dev_profile *profile, + struct adie_codec_path **path_pptr); + int (*codec_close) (struct adie_codec_path *path_ptr); + int (*codec_setpath) (struct adie_codec_path *path_ptr, + u32 freq_plan, u32 osr); + int (*codec_proceed_stage) (struct adie_codec_path *path_ptr, + u32 state); + u32 (*codec_freq_supported) (struct adie_codec_dev_profile *profile, + u32 requested_freq); + int (*codec_enable_sidetone) (struct adie_codec_path *rx_path_ptr, + u32 enable); + int (*codec_enable_anc) (struct adie_codec_path *rx_path_ptr, + u32 enable, struct adie_codec_anc_data *calibration_writes); + int (*codec_set_device_digital_volume) ( + struct adie_codec_path *path_ptr, + u32 num_channels, + u32 vol_percentage); + + int (*codec_set_device_analog_volume) (struct adie_codec_path *path_ptr, + u32 num_channels, + u32 volume); + int (*codec_set_master_mode) (struct adie_codec_path *path_ptr, + u8 master); +}; + +int adie_codec_register_codec_operations( + const struct adie_codec_operations *codec_ops); +int adie_codec_open(struct adie_codec_dev_profile *profile, + struct adie_codec_path **path_pptr); +int adie_codec_setpath(struct adie_codec_path *path_ptr, + u32 freq_plan, u32 osr); +int adie_codec_proceed_stage(struct adie_codec_path *path_ptr, u32 state); +int adie_codec_close(struct adie_codec_path *path_ptr); +u32 adie_codec_freq_supported(struct adie_codec_dev_profile *profile, + u32 requested_freq); +int adie_codec_enable_sidetone(struct adie_codec_path *rx_path_ptr, u32 enable); +int adie_codec_enable_anc(struct adie_codec_path *rx_path_ptr, u32 enable, + struct adie_codec_anc_data *calibration_writes); +int adie_codec_set_device_digital_volume(struct adie_codec_path *path_ptr, + u32 num_channels, u32 vol_percentage /* in percentage */); + +int adie_codec_set_device_analog_volume(struct adie_codec_path *path_ptr, + u32 num_channels, u32 volume /* in percentage */); + +int adie_codec_set_master_mode(struct adie_codec_path *path_ptr, u8 master); +#endif diff --git a/original-kernel-headers/linux/mfd/wcd9xxx/wcd9320_registers.h b/original-kernel-headers/linux/mfd/wcd9xxx/wcd9320_registers.h new file mode 100644 index 0000000..63ab624 --- /dev/null +++ b/original-kernel-headers/linux/mfd/wcd9xxx/wcd9320_registers.h @@ -0,0 +1,1399 @@ +#ifndef WCD9320_REGISTERS_H +#define WCD9320_REGISTERS_H + +#include <linux/mfd/wcd9xxx/wcd9xxx_registers.h> + +#define TAIKO_A_CHIP_CTL WCD9XXX_A_CHIP_CTL +#define TAIKO_A_CHIP_CTL__POR WCD9XXX_A_CHIP_CTL__POR +#define TAIKO_A_CHIP_STATUS WCD9XXX_A_CHIP_STATUS +#define TAIKO_A_CHIP_STATUS__POR WCD9XXX_A_CHIP_STATUS__POR +#define TAIKO_A_CHIP_ID_BYTE_0 WCD9XXX_A_CHIP_ID_BYTE_0 +#define TAIKO_A_CHIP_ID_BYTE_0__POR WCD9XXX_A_CHIP_ID_BYTE_0__POR +#define TAIKO_A_CHIP_ID_BYTE_1 WCD9XXX_A_CHIP_ID_BYTE_1 +#define TAIKO_A_CHIP_ID_BYTE_1__POR WCD9XXX_A_CHIP_ID_BYTE_1__POR +#define TAIKO_A_CHIP_ID_BYTE_2 WCD9XXX_A_CHIP_ID_BYTE_2 +#define TAIKO_A_CHIP_ID_BYTE_2__POR WCD9XXX_A_CHIP_ID_BYTE_2__POR +#define TAIKO_A_CHIP_ID_BYTE_3 WCD9XXX_A_CHIP_ID_BYTE_3 +#define TAIKO_A_CHIP_ID_BYTE_3__POR WCD9XXX_A_CHIP_ID_BYTE_3__POR +#define TAIKO_A_CHIP_VERSION WCD9XXX_A_CHIP_VERSION +#define TAIKO_A_CHIP_VERSION__POR WCD9XXX_A_CHIP_VERSION__POR +#define TAIKO_A_SB_VERSION WCD9XXX_A_SB_VERSION +#define TAIKO_A_SB_VERSION__POR WCD9XXX_A_SB_VERSION__POR +#define TAIKO_A_SLAVE_ID_1 WCD9XXX_A_SLAVE_ID_1 +#define TAIKO_A_SLAVE_ID_1__POR WCD9XXX_A_SLAVE_ID_1__POR +#define TAIKO_A_SLAVE_ID_2 WCD9XXX_A_SLAVE_ID_2 +#define TAIKO_A_SLAVE_ID_2__POR WCD9XXX_A_SLAVE_ID_2__POR +#define TAIKO_A_SLAVE_ID_3 WCD9XXX_A_SLAVE_ID_3 +#define TAIKO_A_SLAVE_ID_3__POR WCD9XXX_A_SLAVE_ID_3__POR +#define TAIKO_A_PIN_CTL_OE0 (0x010) +#define TAIKO_A_PIN_CTL_OE0__POR (0x00) +#define TAIKO_A_PIN_CTL_OE1 (0x011) +#define TAIKO_A_PIN_CTL_OE1__POR (0x00) +#define TAIKO_A_PIN_CTL_DATA0 (0x012) +#define TAIKO_A_PIN_CTL_DATA0__POR (0x00) +#define TAIKO_A_PIN_CTL_DATA1 (0x013) +#define TAIKO_A_PIN_CTL_DATA1__POR (0x00) +#define TAIKO_A_HDRIVE_GENERIC (0x018) +#define TAIKO_A_HDRIVE_GENERIC__POR (0x00) +#define TAIKO_A_HDRIVE_OVERRIDE (0x019) +#define TAIKO_A_HDRIVE_OVERRIDE__POR (0x08) +#define TAIKO_A_ANA_CSR_WAIT_STATE (0x020) +#define TAIKO_A_ANA_CSR_WAIT_STATE__POR (0x44) +#define TAIKO_A_PROCESS_MONITOR_CTL0 (0x040) +#define TAIKO_A_PROCESS_MONITOR_CTL0__POR (0x80) +#define TAIKO_A_PROCESS_MONITOR_CTL1 (0x041) +#define TAIKO_A_PROCESS_MONITOR_CTL1__POR (0x00) +#define TAIKO_A_PROCESS_MONITOR_CTL2 (0x042) +#define TAIKO_A_PROCESS_MONITOR_CTL2__POR (0x00) +#define TAIKO_A_PROCESS_MONITOR_CTL3 (0x043) +#define TAIKO_A_PROCESS_MONITOR_CTL3__POR (0x01) +#define TAIKO_A_QFUSE_CTL (0x048) +#define TAIKO_A_QFUSE_CTL__POR (0x00) +#define TAIKO_A_QFUSE_STATUS (0x049) +#define TAIKO_A_QFUSE_STATUS__POR (0x00) +#define TAIKO_A_QFUSE_DATA_OUT0 (0x04A) +#define TAIKO_A_QFUSE_DATA_OUT0__POR (0x00) +#define TAIKO_A_QFUSE_DATA_OUT1 (0x04B) +#define TAIKO_A_QFUSE_DATA_OUT1__POR (0x00) +#define TAIKO_A_QFUSE_DATA_OUT2 (0x04C) +#define TAIKO_A_QFUSE_DATA_OUT2__POR (0x00) +#define TAIKO_A_QFUSE_DATA_OUT3 (0x04D) +#define TAIKO_A_QFUSE_DATA_OUT3__POR (0x00) +#define TAIKO_A_QFUSE_DATA_OUT4 (0x04E) +#define TAIKO_A_QFUSE_DATA_OUT4__POR (0x00) +#define TAIKO_A_QFUSE_DATA_OUT5 (0x04F) +#define TAIKO_A_QFUSE_DATA_OUT5__POR (0x00) +#define TAIKO_A_QFUSE_DATA_OUT6 (0x050) +#define TAIKO_A_QFUSE_DATA_OUT6__POR (0x00) +#define TAIKO_A_QFUSE_DATA_OUT7 (0x051) +#define TAIKO_A_QFUSE_DATA_OUT7__POR (0x00) +#define TAIKO_A_CDC_CTL WCD9XXX_A_CDC_CTL +#define TAIKO_A_CDC_CTL__POR WCD9XXX_A_CDC_CTL__POR +#define TAIKO_A_LEAKAGE_CTL WCD9XXX_A_LEAKAGE_CTL +#define TAIKO_A_LEAKAGE_CTL__POR WCD9XXX_A_LEAKAGE_CTL__POR +#define TAIKO_A_INTR_MODE (0x090) +#define TAIKO_A_INTR_MODE__POR (0x00) +#define TAIKO_A_INTR_MASK0 (0x094) +#define TAIKO_A_INTR_MASK0__POR (0xFF) +#define TAIKO_A_INTR_MASK1 (0x095) +#define TAIKO_A_INTR_MASK1__POR (0xFF) +#define TAIKO_A_INTR_MASK2 (0x096) +#define TAIKO_A_INTR_MASK2__POR (0x3F) +#define TAIKO_A_INTR_MASK3 (0x097) +#define TAIKO_A_INTR_MASK3__POR (0x3F) +#define TAIKO_A_INTR_STATUS0 (0x098) +#define TAIKO_A_INTR_STATUS0__POR (0x00) +#define TAIKO_A_INTR_STATUS1 (0x099) +#define TAIKO_A_INTR_STATUS1__POR (0x00) +#define TAIKO_A_INTR_STATUS2 (0x09A) +#define TAIKO_A_INTR_STATUS2__POR (0x00) +#define TAIKO_A_INTR_STATUS3 (0x09B) +#define TAIKO_A_INTR_STATUS3__POR (0x00) +#define TAIKO_A_INTR_CLEAR0 (0x09C) +#define TAIKO_A_INTR_CLEAR0__POR (0x00) +#define TAIKO_A_INTR_CLEAR1 (0x09D) +#define TAIKO_A_INTR_CLEAR1__POR (0x00) +#define TAIKO_A_INTR_CLEAR2 (0x09E) +#define TAIKO_A_INTR_CLEAR2__POR (0x00) +#define TAIKO_A_INTR_CLEAR3 (0x09F) +#define TAIKO_A_INTR_CLEAR3__POR (0x00) +#define TAIKO_A_INTR_LEVEL0 (0x0A0) +#define TAIKO_A_INTR_LEVEL0__POR (0x01) +#define TAIKO_A_INTR_LEVEL1 (0x0A1) +#define TAIKO_A_INTR_LEVEL1__POR (0x00) +#define TAIKO_A_INTR_LEVEL2 (0x0A2) +#define TAIKO_A_INTR_LEVEL2__POR (0x00) +#define TAIKO_A_INTR_LEVEL3 (0x0A3) +#define TAIKO_A_INTR_LEVEL3__POR (0x00) +#define TAIKO_A_INTR_TEST0 (0x0A4) +#define TAIKO_A_INTR_TEST0__POR (0x00) +#define TAIKO_A_INTR_TEST1 (0x0A5) +#define TAIKO_A_INTR_TEST1__POR (0x00) +#define TAIKO_A_INTR_TEST2 (0x0A6) +#define TAIKO_A_INTR_TEST2__POR (0x00) +#define TAIKO_A_INTR_TEST3 (0x0A7) +#define TAIKO_A_INTR_TEST3__POR (0x00) +#define TAIKO_A_INTR_SET0 (0x0A8) +#define TAIKO_A_INTR_SET0__POR (0x00) +#define TAIKO_A_INTR_SET1 (0x0A9) +#define TAIKO_A_INTR_SET1__POR (0x00) +#define TAIKO_A_INTR_SET2 (0x0AA) +#define TAIKO_A_INTR_SET2__POR (0x00) +#define TAIKO_A_INTR_SET3 (0x0AB) +#define TAIKO_A_INTR_SET3__POR (0x00) +#define TAIKO_A_INTR_DESTN0 (0x0AC) +#define TAIKO_A_INTR_DESTN0__POR (0x00) +#define TAIKO_A_INTR_DESTN1 (0x0AD) +#define TAIKO_A_INTR_DESTN1__POR (0x00) +#define TAIKO_A_INTR_DESTN2 (0x0AE) +#define TAIKO_A_INTR_DESTN2__POR (0x00) +#define TAIKO_A_INTR_DESTN3 (0x0AF) +#define TAIKO_A_INTR_DESTN3__POR (0x00) +#define TAIKO_A_CDC_TX_I2S_SCK_MODE (0x0C0) +#define TAIKO_A_CDC_TX_I2S_SCK_MODE__POR (0x00) +#define TAIKO_A_CDC_TX_I2S_WS_MODE (0x0C1) +#define TAIKO_A_CDC_TX_I2S_WS_MODE__POR (0x00) +#define TAIKO_A_CDC_DMIC_DATA0_MODE (0x0C4) +#define TAIKO_A_CDC_DMIC_DATA0_MODE__POR (0x00) +#define TAIKO_A_CDC_DMIC_CLK0_MODE (0x0C5) +#define TAIKO_A_CDC_DMIC_CLK0_MODE__POR (0x00) +#define TAIKO_A_CDC_DMIC_DATA1_MODE (0x0C6) +#define TAIKO_A_CDC_DMIC_DATA1_MODE__POR (0x00) +#define TAIKO_A_CDC_DMIC_CLK1_MODE (0x0C7) +#define TAIKO_A_CDC_DMIC_CLK1_MODE__POR (0x00) +#define TAIKO_A_CDC_RX_I2S_SCK_MODE (0x0C8) +#define TAIKO_A_CDC_RX_I2S_SCK_MODE__POR (0x00) +#define TAIKO_A_CDC_RX_I2S_WS_MODE (0x0C9) +#define TAIKO_A_CDC_RX_I2S_WS_MODE__POR (0x00) +#define TAIKO_A_CDC_DMIC_DATA2_MODE (0x0CA) +#define TAIKO_A_CDC_DMIC_DATA2_MODE__POR (0x00) +#define TAIKO_A_CDC_DMIC_CLK2_MODE (0x0CB) +#define TAIKO_A_CDC_DMIC_CLK2_MODE__POR (0x00) +#define TAIKO_A_CDC_INTR1_MODE (0x0CC) +#define TAIKO_A_CDC_INTR1_MODE__POR (0x00) +#define TAIKO_A_CDC_SB_NRZ_SEL_MODE (0x0CD) +#define TAIKO_A_CDC_SB_NRZ_SEL_MODE__POR (0x00) +#define TAIKO_A_CDC_INTR2_MODE (0x0CE) +#define TAIKO_A_CDC_INTR2_MODE__POR (0x00) +#define TAIKO_A_CDC_RF_PA_ON_MODE (0x0CF) +#define TAIKO_A_CDC_RF_PA_ON_MODE__POR (0x00) +#define TAIKO_A_BIAS_REF_CTL (0x100) +#define TAIKO_A_BIAS_REF_CTL__POR (0x1C) +#define TAIKO_A_BIAS_CENTRAL_BG_CTL (0x101) +#define TAIKO_A_BIAS_CENTRAL_BG_CTL__POR (0x50) +#define TAIKO_A_BIAS_PRECHRG_CTL (0x102) +#define TAIKO_A_BIAS_PRECHRG_CTL__POR (0x07) +#define TAIKO_A_BIAS_CURR_CTL_1 (0x103) +#define TAIKO_A_BIAS_CURR_CTL_1__POR (0x52) +#define TAIKO_A_BIAS_CURR_CTL_2 (0x104) +#define TAIKO_A_BIAS_CURR_CTL_2__POR (0x00) +#define TAIKO_A_BIAS_OSC_BG_CTL (0x105) +#define TAIKO_A_BIAS_OSC_BG_CTL__POR (0x16) +#define TAIKO_A_CLK_BUFF_EN1 (0x108) +#define TAIKO_A_CLK_BUFF_EN1__POR (0x04) +#define TAIKO_A_CLK_BUFF_EN2 (0x109) +#define TAIKO_A_CLK_BUFF_EN2__POR (0x02) +#define TAIKO_A_LDO_H_MODE_1 (0x110) +#define TAIKO_A_LDO_H_MODE_1__POR (0x65) +#define TAIKO_A_LDO_H_MODE_2 (0x111) +#define TAIKO_A_LDO_H_MODE_2__POR (0xA8) +#define TAIKO_A_LDO_H_LOOP_CTL (0x112) +#define TAIKO_A_LDO_H_LOOP_CTL__POR (0x6B) +#define TAIKO_A_LDO_H_COMP_1 (0x113) +#define TAIKO_A_LDO_H_COMP_1__POR (0x84) +#define TAIKO_A_LDO_H_COMP_2 (0x114) +#define TAIKO_A_LDO_H_COMP_2__POR (0xE0) +#define TAIKO_A_LDO_H_BIAS_1 (0x115) +#define TAIKO_A_LDO_H_BIAS_1__POR (0x6D) +#define TAIKO_A_LDO_H_BIAS_2 (0x116) +#define TAIKO_A_LDO_H_BIAS_2__POR (0xA5) +#define TAIKO_A_LDO_H_BIAS_3 (0x117) +#define TAIKO_A_LDO_H_BIAS_3__POR (0x60) +#define TAIKO_A_VBAT_CLK (0x118) +#define TAIKO_A_VBAT_CLK__POR (0x03) +#define TAIKO_A_VBAT_LOOP (0x119) +#define TAIKO_A_VBAT_LOOP__POR (0x02) +#define TAIKO_A_VBAT_REF (0x11A) +#define TAIKO_A_VBAT_REF__POR (0x20) +#define TAIKO_A_VBAT_ADC_TEST (0x11B) +#define TAIKO_A_VBAT_ADC_TEST__POR (0x00) +#define TAIKO_A_VBAT_FE (0x11C) +#define TAIKO_A_VBAT_FE__POR (0x48) +#define TAIKO_A_VBAT_BIAS_1 (0x11D) +#define TAIKO_A_VBAT_BIAS_1__POR (0x03) +#define TAIKO_A_VBAT_BIAS_2 (0x11E) +#define TAIKO_A_VBAT_BIAS_2__POR (0x00) +#define TAIKO_A_VBAT_ADC_DATA_MSB (0x11F) +#define TAIKO_A_VBAT_ADC_DATA_MSB__POR (0x00) +#define TAIKO_A_VBAT_ADC_DATA_LSB (0x120) +#define TAIKO_A_VBAT_ADC_DATA_LSB__POR (0x00) +#define TAIKO_A_MICB_CFILT_1_CTL (0x128) +#define TAIKO_A_MICB_CFILT_1_CTL__POR (0x40) +#define TAIKO_A_MICB_CFILT_1_VAL (0x129) +#define TAIKO_A_MICB_CFILT_1_VAL__POR (0x80) +#define TAIKO_A_MICB_CFILT_1_PRECHRG (0x12A) +#define TAIKO_A_MICB_CFILT_1_PRECHRG__POR (0x38) +#define TAIKO_A_MICB_1_CTL (0x12B) +#define TAIKO_A_MICB_1_CTL__POR (0x16) +#define TAIKO_A_MICB_1_INT_RBIAS (0x12C) +#define TAIKO_A_MICB_1_INT_RBIAS__POR (0x24) +#define TAIKO_A_MICB_1_MBHC (0x12D) +#define TAIKO_A_MICB_1_MBHC__POR (0x01) +#define TAIKO_A_MICB_CFILT_2_CTL (0x12E) +#define TAIKO_A_MICB_CFILT_2_CTL__POR (0x40) +#define TAIKO_A_MICB_CFILT_2_VAL (0x12F) +#define TAIKO_A_MICB_CFILT_2_VAL__POR (0x80) +#define TAIKO_A_MICB_CFILT_2_PRECHRG (0x130) +#define TAIKO_A_MICB_CFILT_2_PRECHRG__POR (0x38) +#define TAIKO_A_MICB_2_CTL (0x131) +#define TAIKO_A_MICB_2_CTL__POR (0x16) +#define TAIKO_A_MICB_2_INT_RBIAS (0x132) +#define TAIKO_A_MICB_2_INT_RBIAS__POR (0x24) +#define TAIKO_A_MICB_2_MBHC (0x133) +#define TAIKO_A_MICB_2_MBHC__POR (0x02) +#define TAIKO_A_MICB_CFILT_3_CTL (0x134) +#define TAIKO_A_MICB_CFILT_3_CTL__POR (0x40) +#define TAIKO_A_MICB_CFILT_3_VAL (0x135) +#define TAIKO_A_MICB_CFILT_3_VAL__POR (0x80) +#define TAIKO_A_MICB_CFILT_3_PRECHRG (0x136) +#define TAIKO_A_MICB_CFILT_3_PRECHRG__POR (0x38) +#define TAIKO_A_MICB_3_CTL (0x137) +#define TAIKO_A_MICB_3_CTL__POR (0x16) +#define TAIKO_A_MICB_3_INT_RBIAS (0x138) +#define TAIKO_A_MICB_3_INT_RBIAS__POR (0x24) +#define TAIKO_A_MICB_3_MBHC (0x139) +#define TAIKO_A_MICB_3_MBHC__POR (0x00) +#define TAIKO_A_MICB_4_CTL (0x13D) +#define TAIKO_A_MICB_4_CTL__POR (0x16) +#define TAIKO_A_MICB_4_INT_RBIAS (0x13E) +#define TAIKO_A_MICB_4_INT_RBIAS__POR (0x24) +#define TAIKO_A_MICB_4_MBHC (0x13F) +#define TAIKO_A_MICB_4_MBHC__POR (0x01) +#define TAIKO_A_MBHC_INSERT_DETECT (0x14A) +#define TAIKO_A_MBHC_INSERT_DETECT__POR (0x00) +#define TAIKO_A_MBHC_INSERT_DET_STATUS (0x14B) +#define TAIKO_A_MBHC_INSERT_DET_STATUS__POR (0x00) +#define TAIKO_A_TX_COM_BIAS (0x14C) +#define TAIKO_A_TX_COM_BIAS__POR (0xF0) +#define TAIKO_A_MBHC_SCALING_MUX_1 (0x14E) +#define TAIKO_A_MBHC_SCALING_MUX_1__POR (0x00) +#define TAIKO_A_MBHC_SCALING_MUX_2 (0x14F) +#define TAIKO_A_MBHC_SCALING_MUX_2__POR (0x80) +#define TAIKO_A_MAD_ANA_CTRL (0x150) +#define TAIKO_A_MAD_ANA_CTRL__POR (0xF1) +#define TAIKO_A_TX_SUP_SWITCH_CTRL_1 (0x151) +#define TAIKO_A_TX_SUP_SWITCH_CTRL_1__POR (0x00) +#define TAIKO_A_TX_SUP_SWITCH_CTRL_2 (0x152) +#define TAIKO_A_TX_SUP_SWITCH_CTRL_2__POR (0x80) +#define TAIKO_A_TX_1_2_EN (0x153) +#define TAIKO_A_TX_1_2_EN__POR (0x00) +#define TAIKO_A_TX_1_2_TEST_EN (0x154) +#define TAIKO_A_TX_1_2_TEST_EN__POR (0xCC) +#define TAIKO_A_TX_1_2_ADC_CH1 (0x155) +#define TAIKO_A_TX_1_2_ADC_CH1__POR (0x44) +#define TAIKO_A_TX_1_2_ADC_CH2 (0x156) +#define TAIKO_A_TX_1_2_ADC_CH2__POR (0x44) +#define TAIKO_A_TX_1_2_ATEST_REFCTRL (0x157) +#define TAIKO_A_TX_1_2_ATEST_REFCTRL__POR (0x00) +#define TAIKO_A_TX_1_2_TEST_CTL (0x158) +#define TAIKO_A_TX_1_2_TEST_CTL__POR (0x38) +#define TAIKO_A_TX_1_2_TEST_BLOCK_EN (0x159) +#define TAIKO_A_TX_1_2_TEST_BLOCK_EN__POR (0xFC) +#define TAIKO_A_TX_1_2_TXFE_CLKDIV (0x15A) +#define TAIKO_A_TX_1_2_TXFE_CLKDIV__POR (0x55) +#define TAIKO_A_TX_1_2_SAR_ERR_CH1 (0x15B) +#define TAIKO_A_TX_1_2_SAR_ERR_CH1__POR (0x00) +#define TAIKO_A_TX_1_2_SAR_ERR_CH2 (0x15C) +#define TAIKO_A_TX_1_2_SAR_ERR_CH2__POR (0x00) +#define TAIKO_A_TX_3_4_EN (0x15D) +#define TAIKO_A_TX_3_4_EN__POR (0x00) +#define TAIKO_A_TX_3_4_TEST_EN (0x15E) +#define TAIKO_A_TX_3_4_TEST_EN__POR (0xCC) +#define TAIKO_A_TX_3_4_ADC_CH3 (0x15F) +#define TAIKO_A_TX_3_4_ADC_CH3__POR (0x44) +#define TAIKO_A_TX_3_4_ADC_CH4 (0x160) +#define TAIKO_A_TX_3_4_ADC_CH4__POR (0x44) +#define TAIKO_A_TX_3_4_ATEST_REFCTRL (0x161) +#define TAIKO_A_TX_3_4_ATEST_REFCTRL__POR (0x00) +#define TAIKO_A_TX_3_4_TEST_CTL (0x162) +#define TAIKO_A_TX_3_4_TEST_CTL__POR (0x38) +#define TAIKO_A_TX_3_4_TEST_BLOCK_EN (0x163) +#define TAIKO_A_TX_3_4_TEST_BLOCK_EN__POR (0xFC) +#define TAIKO_A_TX_3_4_TXFE_CKDIV (0x164) +#define TAIKO_A_TX_3_4_TXFE_CKDIV__POR (0x55) +#define TAIKO_A_TX_3_4_SAR_ERR_CH3 (0x165) +#define TAIKO_A_TX_3_4_SAR_ERR_CH3__POR (0x00) +#define TAIKO_A_TX_3_4_SAR_ERR_CH4 (0x166) +#define TAIKO_A_TX_3_4_SAR_ERR_CH4__POR (0x00) +#define TAIKO_A_TX_5_6_EN (0x167) +#define TAIKO_A_TX_5_6_EN__POR (0x11) +#define TAIKO_A_TX_5_6_TEST_EN (0x168) +#define TAIKO_A_TX_5_6_TEST_EN__POR (0xCC) +#define TAIKO_A_TX_5_6_ADC_CH5 (0x169) +#define TAIKO_A_TX_5_6_ADC_CH5__POR (0x44) +#define TAIKO_A_TX_5_6_ADC_CH6 (0x16A) +#define TAIKO_A_TX_5_6_ADC_CH6__POR (0x44) +#define TAIKO_A_TX_5_6_ATEST_REFCTRL (0x16B) +#define TAIKO_A_TX_5_6_ATEST_REFCTRL__POR (0x00) +#define TAIKO_A_TX_5_6_TEST_CTL (0x16C) +#define TAIKO_A_TX_5_6_TEST_CTL__POR (0x38) +#define TAIKO_A_TX_5_6_TEST_BLOCK_EN (0x16D) +#define TAIKO_A_TX_5_6_TEST_BLOCK_EN__POR (0xFC) +#define TAIKO_A_TX_5_6_TXFE_CKDIV (0x16E) +#define TAIKO_A_TX_5_6_TXFE_CKDIV__POR (0x55) +#define TAIKO_A_TX_5_6_SAR_ERR_CH5 (0x16F) +#define TAIKO_A_TX_5_6_SAR_ERR_CH5__POR (0x00) +#define TAIKO_A_TX_5_6_SAR_ERR_CH6 (0x170) +#define TAIKO_A_TX_5_6_SAR_ERR_CH6__POR (0x00) +#define TAIKO_A_TX_7_MBHC_EN (0x171) +#define TAIKO_A_TX_7_MBHC_EN__POR (0x0C) +#define TAIKO_A_TX_7_MBHC_ATEST_REFCTRL (0x172) +#define TAIKO_A_TX_7_MBHC_ATEST_REFCTRL__POR (0x00) +#define TAIKO_A_TX_7_MBHC_ADC (0x173) +#define TAIKO_A_TX_7_MBHC_ADC__POR (0x44) +#define TAIKO_A_TX_7_MBHC_TEST_CTL (0x174) +#define TAIKO_A_TX_7_MBHC_TEST_CTL__POR (0x38) +#define TAIKO_A_TX_7_MBHC_SAR_ERR (0x175) +#define TAIKO_A_TX_7_MBHC_SAR_ERR__POR (0x00) +#define TAIKO_A_TX_7_TXFE_CLKDIV (0x176) +#define TAIKO_A_TX_7_TXFE_CLKDIV__POR (0x0B) +#define TAIKO_A_BUCK_MODE_1 (0x181) +#define TAIKO_A_BUCK_MODE_1__POR (0x21) +#define TAIKO_A_BUCK_MODE_2 (0x182) +#define TAIKO_A_BUCK_MODE_2__POR (0xFF) +#define TAIKO_A_BUCK_MODE_3 (0x183) +#define TAIKO_A_BUCK_MODE_3__POR (0xCC) +#define TAIKO_A_BUCK_MODE_4 (0x184) +#define TAIKO_A_BUCK_MODE_4__POR (0x3A) +#define TAIKO_A_BUCK_MODE_5 (0x185) +#define TAIKO_A_BUCK_MODE_5__POR (0x00) +#define TAIKO_A_BUCK_CTRL_VCL_1 (0x186) +#define TAIKO_A_BUCK_CTRL_VCL_1__POR (0x48) +#define TAIKO_A_BUCK_CTRL_VCL_2 (0x187) +#define TAIKO_A_BUCK_CTRL_VCL_2__POR (0xA3) +#define TAIKO_A_BUCK_CTRL_VCL_3 (0x188) +#define TAIKO_A_BUCK_CTRL_VCL_3__POR (0x82) +#define TAIKO_A_BUCK_CTRL_CCL_1 (0x189) +#define TAIKO_A_BUCK_CTRL_CCL_1__POR (0xAB) +#define TAIKO_A_BUCK_CTRL_CCL_2 (0x18A) +#define TAIKO_A_BUCK_CTRL_CCL_2__POR (0xDC) +#define TAIKO_A_BUCK_CTRL_CCL_3 (0x18B) +#define TAIKO_A_BUCK_CTRL_CCL_3__POR (0x6A) +#define TAIKO_A_BUCK_CTRL_CCL_4 (0x18C) +#define TAIKO_A_BUCK_CTRL_CCL_4__POR (0x58) +#define TAIKO_A_BUCK_CTRL_PWM_DRVR_1 (0x18D) +#define TAIKO_A_BUCK_CTRL_PWM_DRVR_1__POR (0x50) +#define TAIKO_A_BUCK_CTRL_PWM_DRVR_2 (0x18E) +#define TAIKO_A_BUCK_CTRL_PWM_DRVR_2__POR (0x64) +#define TAIKO_A_BUCK_CTRL_PWM_DRVR_3 (0x18F) +#define TAIKO_A_BUCK_CTRL_PWM_DRVR_3__POR (0x77) +#define TAIKO_A_BUCK_TMUX_A_D (0x190) +#define TAIKO_A_BUCK_TMUX_A_D__POR (0x00) +#define TAIKO_A_NCP_BUCKREF (0x191) +#define TAIKO_A_NCP_BUCKREF__POR (0x00) +#define TAIKO_A_NCP_EN (0x192) +#define TAIKO_A_NCP_EN__POR (0xFE) +#define TAIKO_A_NCP_CLK (0x193) +#define TAIKO_A_NCP_CLK__POR (0x94) +#define TAIKO_A_NCP_STATIC (0x194) +#define TAIKO_A_NCP_STATIC__POR (0x28) +#define TAIKO_A_NCP_VTH_LOW (0x195) +#define TAIKO_A_NCP_VTH_LOW__POR (0x88) +#define TAIKO_A_NCP_VTH_HIGH (0x196) +#define TAIKO_A_NCP_VTH_HIGH__POR (0xA0) +#define TAIKO_A_NCP_ATEST (0x197) +#define TAIKO_A_NCP_ATEST__POR (0x00) +#define TAIKO_A_NCP_DTEST (0x198) +#define TAIKO_A_NCP_DTEST__POR (0x00) +#define TAIKO_A_NCP_DLY1 (0x199) +#define TAIKO_A_NCP_DLY1__POR (0x06) +#define TAIKO_A_NCP_DLY2 (0x19A) +#define TAIKO_A_NCP_DLY2__POR (0x06) +#define TAIKO_A_RX_AUX_SW_CTL (0x19B) +#define TAIKO_A_RX_AUX_SW_CTL__POR (0x00) +#define TAIKO_A_RX_PA_AUX_IN_CONN (0x19C) +#define TAIKO_A_RX_PA_AUX_IN_CONN__POR (0x00) +#define TAIKO_A_RX_COM_TIMER_DIV (0x19E) +#define TAIKO_A_RX_COM_TIMER_DIV__POR (0xE8) +#define TAIKO_A_RX_COM_OCP_CTL (0x19F) +#define TAIKO_A_RX_COM_OCP_CTL__POR (0x1F) +#define TAIKO_A_RX_COM_OCP_COUNT (0x1A0) +#define TAIKO_A_RX_COM_OCP_COUNT__POR (0x77) +#define TAIKO_A_RX_COM_DAC_CTL (0x1A1) +#define TAIKO_A_RX_COM_DAC_CTL__POR (0x00) +#define TAIKO_A_RX_COM_BIAS (0x1A2) +#define TAIKO_A_RX_COM_BIAS__POR (0x00) +#define TAIKO_A_RX_HPH_AUTO_CHOP (0x1A4) +#define TAIKO_A_RX_HPH_AUTO_CHOP__POR (0x38) +#define TAIKO_A_RX_HPH_CHOP_CTL (0x1A5) +#define TAIKO_A_RX_HPH_CHOP_CTL__POR (0xB4) +#define TAIKO_A_RX_HPH_BIAS_PA (0x1A6) +#define TAIKO_A_RX_HPH_BIAS_PA__POR (0xAA) +#define TAIKO_A_RX_HPH_BIAS_LDO (0x1A7) +#define TAIKO_A_RX_HPH_BIAS_LDO__POR (0x87) +#define TAIKO_A_RX_HPH_BIAS_CNP (0x1A8) +#define TAIKO_A_RX_HPH_BIAS_CNP__POR (0x8A) +#define TAIKO_A_RX_HPH_BIAS_WG_OCP (0x1A9) +#define TAIKO_A_RX_HPH_BIAS_WG_OCP__POR (0x2A) +#define TAIKO_A_RX_HPH_OCP_CTL (0x1AA) +#define TAIKO_A_RX_HPH_OCP_CTL__POR (0x68) +#define TAIKO_A_RX_HPH_CNP_EN (0x1AB) +#define TAIKO_A_RX_HPH_CNP_EN__POR (0x80) +#define TAIKO_A_RX_HPH_CNP_WG_CTL (0x1AC) +#define TAIKO_A_RX_HPH_CNP_WG_CTL__POR (0xDE) +#define TAIKO_A_RX_HPH_CNP_WG_TIME (0x1AD) +#define TAIKO_A_RX_HPH_CNP_WG_TIME__POR (0x2A) +#define TAIKO_A_RX_HPH_L_GAIN (0x1AE) +#define TAIKO_A_RX_HPH_L_GAIN__POR (0x00) +#define TAIKO_A_RX_HPH_L_TEST (0x1AF) +#define TAIKO_A_RX_HPH_L_TEST__POR (0x00) +#define TAIKO_A_RX_HPH_L_PA_CTL (0x1B0) +#define TAIKO_A_RX_HPH_L_PA_CTL__POR (0x40) +#define TAIKO_A_RX_HPH_L_DAC_CTL (0x1B1) +#define TAIKO_A_RX_HPH_L_DAC_CTL__POR (0x00) +#define TAIKO_A_RX_HPH_L_ATEST (0x1B2) +#define TAIKO_A_RX_HPH_L_ATEST__POR (0x00) +#define TAIKO_A_RX_HPH_L_STATUS (0x1B3) +#define TAIKO_A_RX_HPH_L_STATUS__POR (0x00) +#define TAIKO_A_RX_HPH_R_GAIN (0x1B4) +#define TAIKO_A_RX_HPH_R_GAIN__POR (0x00) +#define TAIKO_A_RX_HPH_R_TEST (0x1B5) +#define TAIKO_A_RX_HPH_R_TEST__POR (0x00) +#define TAIKO_A_RX_HPH_R_PA_CTL (0x1B6) +#define TAIKO_A_RX_HPH_R_PA_CTL__POR (0x40) +#define TAIKO_A_RX_HPH_R_DAC_CTL (0x1B7) +#define TAIKO_A_RX_HPH_R_DAC_CTL__POR (0x00) +#define TAIKO_A_RX_HPH_R_ATEST (0x1B8) +#define TAIKO_A_RX_HPH_R_ATEST__POR (0x00) +#define TAIKO_A_RX_HPH_R_STATUS (0x1B9) +#define TAIKO_A_RX_HPH_R_STATUS__POR (0x00) +#define TAIKO_A_RX_EAR_BIAS_PA (0x1BA) +#define TAIKO_A_RX_EAR_BIAS_PA__POR (0xA6) +#define TAIKO_A_RX_EAR_BIAS_CMBUFF (0x1BB) +#define TAIKO_A_RX_EAR_BIAS_CMBUFF__POR (0xA0) +#define TAIKO_A_RX_EAR_EN (0x1BC) +#define TAIKO_A_RX_EAR_EN__POR (0x00) +#define TAIKO_A_RX_EAR_GAIN (0x1BD) +#define TAIKO_A_RX_EAR_GAIN__POR (0x02) +#define TAIKO_A_RX_EAR_CMBUFF (0x1BE) +#define TAIKO_A_RX_EAR_CMBUFF__POR (0x04) +#define TAIKO_A_RX_EAR_ICTL (0x1BF) +#define TAIKO_A_RX_EAR_ICTL__POR (0x40) +#define TAIKO_A_RX_EAR_CCOMP (0x1C0) +#define TAIKO_A_RX_EAR_CCOMP__POR (0x08) +#define TAIKO_A_RX_EAR_VCM (0x1C1) +#define TAIKO_A_RX_EAR_VCM__POR (0x03) +#define TAIKO_A_RX_EAR_CNP (0x1C2) +#define TAIKO_A_RX_EAR_CNP__POR (0xF2) +#define TAIKO_A_RX_EAR_DAC_CTL_ATEST (0x1C3) +#define TAIKO_A_RX_EAR_DAC_CTL_ATEST__POR (0x00) +#define TAIKO_A_RX_EAR_STATUS (0x1C5) +#define TAIKO_A_RX_EAR_STATUS__POR (0x04) +#define TAIKO_A_RX_LINE_BIAS_PA (0x1C6) +#define TAIKO_A_RX_LINE_BIAS_PA__POR (0xA8) +#define TAIKO_A_RX_BUCK_BIAS1 (0x1C7) +#define TAIKO_A_RX_BUCK_BIAS1__POR (0x42) +#define TAIKO_A_RX_BUCK_BIAS2 (0x1C8) +#define TAIKO_A_RX_BUCK_BIAS2__POR (0x84) +#define TAIKO_A_RX_LINE_COM (0x1C9) +#define TAIKO_A_RX_LINE_COM__POR (0x80) +#define TAIKO_A_RX_LINE_CNP_EN (0x1CA) +#define TAIKO_A_RX_LINE_CNP_EN__POR (0x00) +#define TAIKO_A_RX_LINE_CNP_WG_CTL (0x1CB) +#define TAIKO_A_RX_LINE_CNP_WG_CTL__POR (0x00) +#define TAIKO_A_RX_LINE_CNP_WG_TIME (0x1CC) +#define TAIKO_A_RX_LINE_CNP_WG_TIME__POR (0x04) +#define TAIKO_A_RX_LINE_1_GAIN (0x1CD) +#define TAIKO_A_RX_LINE_1_GAIN__POR (0x00) +#define TAIKO_A_RX_LINE_1_TEST (0x1CE) +#define TAIKO_A_RX_LINE_1_TEST__POR (0x00) +#define TAIKO_A_RX_LINE_1_DAC_CTL (0x1CF) +#define TAIKO_A_RX_LINE_1_DAC_CTL__POR (0x00) +#define TAIKO_A_RX_LINE_1_STATUS (0x1D0) +#define TAIKO_A_RX_LINE_1_STATUS__POR (0x00) +#define TAIKO_A_RX_LINE_2_GAIN (0x1D1) +#define TAIKO_A_RX_LINE_2_GAIN__POR (0x00) +#define TAIKO_A_RX_LINE_2_TEST (0x1D2) +#define TAIKO_A_RX_LINE_2_TEST__POR (0x00) +#define TAIKO_A_RX_LINE_2_DAC_CTL (0x1D3) +#define TAIKO_A_RX_LINE_2_DAC_CTL__POR (0x00) +#define TAIKO_A_RX_LINE_2_STATUS (0x1D4) +#define TAIKO_A_RX_LINE_2_STATUS__POR (0x00) +#define TAIKO_A_RX_LINE_3_GAIN (0x1D5) +#define TAIKO_A_RX_LINE_3_GAIN__POR (0x00) +#define TAIKO_A_RX_LINE_3_TEST (0x1D6) +#define TAIKO_A_RX_LINE_3_TEST__POR (0x00) +#define TAIKO_A_RX_LINE_3_DAC_CTL (0x1D7) +#define TAIKO_A_RX_LINE_3_DAC_CTL__POR (0x00) +#define TAIKO_A_RX_LINE_3_STATUS (0x1D8) +#define TAIKO_A_RX_LINE_3_STATUS__POR (0x00) +#define TAIKO_A_RX_LINE_4_GAIN (0x1D9) +#define TAIKO_A_RX_LINE_4_GAIN__POR (0x00) +#define TAIKO_A_RX_LINE_4_TEST (0x1DA) +#define TAIKO_A_RX_LINE_4_TEST__POR (0x00) +#define TAIKO_A_RX_LINE_4_DAC_CTL (0x1DB) +#define TAIKO_A_RX_LINE_4_DAC_CTL__POR (0x00) +#define TAIKO_A_RX_LINE_4_STATUS (0x1DC) +#define TAIKO_A_RX_LINE_4_STATUS__POR (0x00) +#define TAIKO_A_RX_LINE_CNP_DBG (0x1DD) +#define TAIKO_A_RX_LINE_CNP_DBG__POR (0x00) +#define TAIKO_A_SPKR_DRV_EN (0x1DF) +#define TAIKO_A_SPKR_DRV_EN__POR (0x6F) +#define TAIKO_A_SPKR_DRV_GAIN (0x1E0) +#define TAIKO_A_SPKR_DRV_GAIN__POR (0x00) +#define TAIKO_A_SPKR_DRV_DAC_CTL (0x1E1) +#define TAIKO_A_SPKR_DRV_DAC_CTL__POR (0x04) +#define TAIKO_A_SPKR_DRV_OCP_CTL (0x1E2) +#define TAIKO_A_SPKR_DRV_OCP_CTL__POR (0x98) +#define TAIKO_A_SPKR_DRV_CLIP_DET (0x1E3) +#define TAIKO_A_SPKR_DRV_CLIP_DET__POR (0x48) +#define TAIKO_A_SPKR_DRV_IEC (0x1E4) +#define TAIKO_A_SPKR_DRV_IEC__POR (0x20) +#define TAIKO_A_SPKR_DRV_DBG_DAC (0x1E5) +#define TAIKO_A_SPKR_DRV_DBG_DAC__POR (0x05) +#define TAIKO_A_SPKR_DRV_DBG_PA (0x1E6) +#define TAIKO_A_SPKR_DRV_DBG_PA__POR (0x18) +#define TAIKO_A_SPKR_DRV_DBG_PWRSTG (0x1E7) +#define TAIKO_A_SPKR_DRV_DBG_PWRSTG__POR (0x00) +#define TAIKO_A_SPKR_DRV_BIAS_LDO (0x1E8) +#define TAIKO_A_SPKR_DRV_BIAS_LDO__POR (0x45) +#define TAIKO_A_SPKR_DRV_BIAS_INT (0x1E9) +#define TAIKO_A_SPKR_DRV_BIAS_INT__POR (0xA5) +#define TAIKO_A_SPKR_DRV_BIAS_PA (0x1EA) +#define TAIKO_A_SPKR_DRV_BIAS_PA__POR (0x55) +#define TAIKO_A_SPKR_DRV_STATUS_OCP (0x1EB) +#define TAIKO_A_SPKR_DRV_STATUS_OCP__POR (0x00) +#define TAIKO_A_SPKR_DRV_STATUS_PA (0x1EC) +#define TAIKO_A_SPKR_DRV_STATUS_PA__POR (0x00) +#define TAIKO_A_SPKR_PROT_EN (0x1ED) +#define TAIKO_A_SPKR_PROT_EN__POR (0x00) +#define TAIKO_A_SPKR_PROT_ADC_EN (0x1EE) +#define TAIKO_A_SPKR_PROT_ADC_EN__POR (0x44) +#define TAIKO_A_SPKR_PROT_ISENSE_BIAS (0x1EF) +#define TAIKO_A_SPKR_PROT_ISENSE_BIAS__POR (0x44) +#define TAIKO_A_SPKR_PROT_VSENSE_BIAS (0x1F0) +#define TAIKO_A_SPKR_PROT_VSENSE_BIAS__POR (0x44) +#define TAIKO_A_SPKR_PROT_ADC_ATEST_REFCTRL (0x1F1) +#define TAIKO_A_SPKR_PROT_ADC_ATEST_REFCTRL__POR (0x00) +#define TAIKO_A_SPKR_PROT_ADC_TEST_CTL (0x1F2) +#define TAIKO_A_SPKR_PROT_ADC_TEST_CTL__POR (0x38) +#define TAIKO_A_SPKR_PROT_TEST_BLOCK_EN (0x1F3) +#define TAIKO_A_SPKR_PROT_TEST_BLOCK_EN__POR (0xFC) +#define TAIKO_A_SPKR_PROT_ATEST (0x1F4) +#define TAIKO_A_SPKR_PROT_ATEST__POR (0x00) +#define TAIKO_A_SPKR_PROT_V_SAR_ERR (0x1F5) +#define TAIKO_A_SPKR_PROT_V_SAR_ERR__POR (0x00) +#define TAIKO_A_SPKR_PROT_I_SAR_ERR (0x1F6) +#define TAIKO_A_SPKR_PROT_I_SAR_ERR__POR (0x00) +#define TAIKO_A_SPKR_PROT_LDO_CTRL (0x1F7) +#define TAIKO_A_SPKR_PROT_LDO_CTRL__POR (0x00) +#define TAIKO_A_SPKR_PROT_ISENSE_CTRL (0x1F8) +#define TAIKO_A_SPKR_PROT_ISENSE_CTRL__POR (0x00) +#define TAIKO_A_SPKR_PROT_VSENSE_CTRL (0x1F9) +#define TAIKO_A_SPKR_PROT_VSENSE_CTRL__POR (0x00) +#define TAIKO_A_RC_OSC_FREQ (0x1FA) +#define TAIKO_A_RC_OSC_FREQ__POR (0x46) +#define TAIKO_A_RC_OSC_TEST (0x1FB) +#define TAIKO_A_RC_OSC_TEST__POR (0x0A) +#define TAIKO_A_RC_OSC_STATUS (0x1FC) +#define TAIKO_A_RC_OSC_STATUS__POR (0x18) +#define TAIKO_A_RC_OSC_TUNER (0x1FD) +#define TAIKO_A_RC_OSC_TUNER__POR (0x00) +#define TAIKO_A_MBHC_HPH (0x1FE) +#define TAIKO_A_MBHC_HPH__POR (0x44) +#define TAIKO_A_CDC_ANC1_B1_CTL (0x200) +#define TAIKO_A_CDC_ANC1_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_ANC2_B1_CTL (0x280) +#define TAIKO_A_CDC_ANC2_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_ANC1_SHIFT (0x201) +#define TAIKO_A_CDC_ANC1_SHIFT__POR (0x00) +#define TAIKO_A_CDC_ANC2_SHIFT (0x281) +#define TAIKO_A_CDC_ANC2_SHIFT__POR (0x00) +#define TAIKO_A_CDC_ANC1_IIR_B1_CTL (0x202) +#define TAIKO_A_CDC_ANC1_IIR_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_ANC2_IIR_B1_CTL (0x282) +#define TAIKO_A_CDC_ANC2_IIR_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_ANC1_IIR_B2_CTL (0x203) +#define TAIKO_A_CDC_ANC1_IIR_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_ANC2_IIR_B2_CTL (0x283) +#define TAIKO_A_CDC_ANC2_IIR_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_ANC1_IIR_B3_CTL (0x204) +#define TAIKO_A_CDC_ANC1_IIR_B3_CTL__POR (0x00) +#define TAIKO_A_CDC_ANC2_IIR_B3_CTL (0x284) +#define TAIKO_A_CDC_ANC2_IIR_B3_CTL__POR (0x00) +#define TAIKO_A_CDC_ANC1_LPF_B1_CTL (0x206) +#define TAIKO_A_CDC_ANC1_LPF_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_ANC2_LPF_B1_CTL (0x286) +#define TAIKO_A_CDC_ANC2_LPF_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_ANC1_LPF_B2_CTL (0x207) +#define TAIKO_A_CDC_ANC1_LPF_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_ANC2_LPF_B2_CTL (0x287) +#define TAIKO_A_CDC_ANC2_LPF_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_ANC1_SPARE (0x209) +#define TAIKO_A_CDC_ANC1_SPARE__POR (0x00) +#define TAIKO_A_CDC_ANC2_SPARE (0x289) +#define TAIKO_A_CDC_ANC2_SPARE__POR (0x00) +#define TAIKO_A_CDC_ANC1_SMLPF_CTL (0x20A) +#define TAIKO_A_CDC_ANC1_SMLPF_CTL__POR (0x00) +#define TAIKO_A_CDC_ANC2_SMLPF_CTL (0x28A) +#define TAIKO_A_CDC_ANC2_SMLPF_CTL__POR (0x00) +#define TAIKO_A_CDC_ANC1_DCFLT_CTL (0x20B) +#define TAIKO_A_CDC_ANC1_DCFLT_CTL__POR (0x00) +#define TAIKO_A_CDC_ANC2_DCFLT_CTL (0x28B) +#define TAIKO_A_CDC_ANC2_DCFLT_CTL__POR (0x00) +#define TAIKO_A_CDC_ANC1_GAIN_CTL (0x20C) +#define TAIKO_A_CDC_ANC1_GAIN_CTL__POR (0x00) +#define TAIKO_A_CDC_ANC2_GAIN_CTL (0x28C) +#define TAIKO_A_CDC_ANC2_GAIN_CTL__POR (0x00) +#define TAIKO_A_CDC_ANC1_B2_CTL (0x20D) +#define TAIKO_A_CDC_ANC1_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_ANC2_B2_CTL (0x28D) +#define TAIKO_A_CDC_ANC2_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_TX1_VOL_CTL_TIMER (0x220) +#define TAIKO_A_CDC_TX1_VOL_CTL_TIMER__POR (0x00) +#define TAIKO_A_CDC_TX2_VOL_CTL_TIMER (0x228) +#define TAIKO_A_CDC_TX2_VOL_CTL_TIMER__POR (0x00) +#define TAIKO_A_CDC_TX3_VOL_CTL_TIMER (0x230) +#define TAIKO_A_CDC_TX3_VOL_CTL_TIMER__POR (0x00) +#define TAIKO_A_CDC_TX4_VOL_CTL_TIMER (0x238) +#define TAIKO_A_CDC_TX4_VOL_CTL_TIMER__POR (0x00) +#define TAIKO_A_CDC_TX5_VOL_CTL_TIMER (0x240) +#define TAIKO_A_CDC_TX5_VOL_CTL_TIMER__POR (0x00) +#define TAIKO_A_CDC_TX6_VOL_CTL_TIMER (0x248) +#define TAIKO_A_CDC_TX6_VOL_CTL_TIMER__POR (0x00) +#define TAIKO_A_CDC_TX7_VOL_CTL_TIMER (0x250) +#define TAIKO_A_CDC_TX7_VOL_CTL_TIMER__POR (0x00) +#define TAIKO_A_CDC_TX8_VOL_CTL_TIMER (0x258) +#define TAIKO_A_CDC_TX8_VOL_CTL_TIMER__POR (0x00) +#define TAIKO_A_CDC_TX9_VOL_CTL_TIMER (0x260) +#define TAIKO_A_CDC_TX9_VOL_CTL_TIMER__POR (0x00) +#define TAIKO_A_CDC_TX10_VOL_CTL_TIMER (0x268) +#define TAIKO_A_CDC_TX10_VOL_CTL_TIMER__POR (0x00) +#define TAIKO_A_CDC_TX1_VOL_CTL_GAIN (0x221) +#define TAIKO_A_CDC_TX1_VOL_CTL_GAIN__POR (0x00) +#define TAIKO_A_CDC_TX2_VOL_CTL_GAIN (0x229) +#define TAIKO_A_CDC_TX2_VOL_CTL_GAIN__POR (0x00) +#define TAIKO_A_CDC_TX3_VOL_CTL_GAIN (0x231) +#define TAIKO_A_CDC_TX3_VOL_CTL_GAIN__POR (0x00) +#define TAIKO_A_CDC_TX4_VOL_CTL_GAIN (0x239) +#define TAIKO_A_CDC_TX4_VOL_CTL_GAIN__POR (0x00) +#define TAIKO_A_CDC_TX5_VOL_CTL_GAIN (0x241) +#define TAIKO_A_CDC_TX5_VOL_CTL_GAIN__POR (0x00) +#define TAIKO_A_CDC_TX6_VOL_CTL_GAIN (0x249) +#define TAIKO_A_CDC_TX6_VOL_CTL_GAIN__POR (0x00) +#define TAIKO_A_CDC_TX7_VOL_CTL_GAIN (0x251) +#define TAIKO_A_CDC_TX7_VOL_CTL_GAIN__POR (0x00) +#define TAIKO_A_CDC_TX8_VOL_CTL_GAIN (0x259) +#define TAIKO_A_CDC_TX8_VOL_CTL_GAIN__POR (0x00) +#define TAIKO_A_CDC_TX9_VOL_CTL_GAIN (0x261) +#define TAIKO_A_CDC_TX9_VOL_CTL_GAIN__POR (0x00) +#define TAIKO_A_CDC_TX10_VOL_CTL_GAIN (0x269) +#define TAIKO_A_CDC_TX10_VOL_CTL_GAIN__POR (0x00) +#define TAIKO_A_CDC_TX1_VOL_CTL_CFG (0x222) +#define TAIKO_A_CDC_TX1_VOL_CTL_CFG__POR (0x00) +#define TAIKO_A_CDC_TX2_VOL_CTL_CFG (0x22A) +#define TAIKO_A_CDC_TX2_VOL_CTL_CFG__POR (0x00) +#define TAIKO_A_CDC_TX3_VOL_CTL_CFG (0x232) +#define TAIKO_A_CDC_TX3_VOL_CTL_CFG__POR (0x00) +#define TAIKO_A_CDC_TX4_VOL_CTL_CFG (0x23A) +#define TAIKO_A_CDC_TX4_VOL_CTL_CFG__POR (0x00) +#define TAIKO_A_CDC_TX5_VOL_CTL_CFG (0x242) +#define TAIKO_A_CDC_TX5_VOL_CTL_CFG__POR (0x00) +#define TAIKO_A_CDC_TX6_VOL_CTL_CFG (0x24A) +#define TAIKO_A_CDC_TX6_VOL_CTL_CFG__POR (0x00) +#define TAIKO_A_CDC_TX7_VOL_CTL_CFG (0x252) +#define TAIKO_A_CDC_TX7_VOL_CTL_CFG__POR (0x00) +#define TAIKO_A_CDC_TX8_VOL_CTL_CFG (0x25A) +#define TAIKO_A_CDC_TX8_VOL_CTL_CFG__POR (0x00) +#define TAIKO_A_CDC_TX9_VOL_CTL_CFG (0x262) +#define TAIKO_A_CDC_TX9_VOL_CTL_CFG__POR (0x00) +#define TAIKO_A_CDC_TX10_VOL_CTL_CFG (0x26A) +#define TAIKO_A_CDC_TX10_VOL_CTL_CFG__POR (0x00) +#define TAIKO_A_CDC_TX1_MUX_CTL (0x223) +#define TAIKO_A_CDC_TX1_MUX_CTL__POR (0x08) +#define TAIKO_A_CDC_TX2_MUX_CTL (0x22B) +#define TAIKO_A_CDC_TX2_MUX_CTL__POR (0x08) +#define TAIKO_A_CDC_TX3_MUX_CTL (0x233) +#define TAIKO_A_CDC_TX3_MUX_CTL__POR (0x08) +#define TAIKO_A_CDC_TX4_MUX_CTL (0x23B) +#define TAIKO_A_CDC_TX4_MUX_CTL__POR (0x08) +#define TAIKO_A_CDC_TX5_MUX_CTL (0x243) +#define TAIKO_A_CDC_TX5_MUX_CTL__POR (0x08) +#define TAIKO_A_CDC_TX6_MUX_CTL (0x24B) +#define TAIKO_A_CDC_TX6_MUX_CTL__POR (0x08) +#define TAIKO_A_CDC_TX7_MUX_CTL (0x253) +#define TAIKO_A_CDC_TX7_MUX_CTL__POR (0x08) +#define TAIKO_A_CDC_TX8_MUX_CTL (0x25B) +#define TAIKO_A_CDC_TX8_MUX_CTL__POR (0x08) +#define TAIKO_A_CDC_TX9_MUX_CTL (0x263) +#define TAIKO_A_CDC_TX9_MUX_CTL__POR (0x08) +#define TAIKO_A_CDC_TX10_MUX_CTL (0x26B) +#define TAIKO_A_CDC_TX10_MUX_CTL__POR (0x08) +#define TAIKO_A_CDC_TX1_CLK_FS_CTL (0x224) +#define TAIKO_A_CDC_TX1_CLK_FS_CTL__POR (0x03) +#define TAIKO_A_CDC_TX2_CLK_FS_CTL (0x22C) +#define TAIKO_A_CDC_TX2_CLK_FS_CTL__POR (0x03) +#define TAIKO_A_CDC_TX3_CLK_FS_CTL (0x234) +#define TAIKO_A_CDC_TX3_CLK_FS_CTL__POR (0x03) +#define TAIKO_A_CDC_TX4_CLK_FS_CTL (0x23C) +#define TAIKO_A_CDC_TX4_CLK_FS_CTL__POR (0x03) +#define TAIKO_A_CDC_TX5_CLK_FS_CTL (0x244) +#define TAIKO_A_CDC_TX5_CLK_FS_CTL__POR (0x03) +#define TAIKO_A_CDC_TX6_CLK_FS_CTL (0x24C) +#define TAIKO_A_CDC_TX6_CLK_FS_CTL__POR (0x03) +#define TAIKO_A_CDC_TX7_CLK_FS_CTL (0x254) +#define TAIKO_A_CDC_TX7_CLK_FS_CTL__POR (0x03) +#define TAIKO_A_CDC_TX8_CLK_FS_CTL (0x25C) +#define TAIKO_A_CDC_TX8_CLK_FS_CTL__POR (0x03) +#define TAIKO_A_CDC_TX9_CLK_FS_CTL (0x264) +#define TAIKO_A_CDC_TX9_CLK_FS_CTL__POR (0x03) +#define TAIKO_A_CDC_TX10_CLK_FS_CTL (0x26C) +#define TAIKO_A_CDC_TX10_CLK_FS_CTL__POR (0x03) +#define TAIKO_A_CDC_TX1_DMIC_CTL (0x225) +#define TAIKO_A_CDC_TX1_DMIC_CTL__POR (0x00) +#define TAIKO_A_CDC_TX2_DMIC_CTL (0x22D) +#define TAIKO_A_CDC_TX2_DMIC_CTL__POR (0x00) +#define TAIKO_A_CDC_TX3_DMIC_CTL (0x235) +#define TAIKO_A_CDC_TX3_DMIC_CTL__POR (0x00) +#define TAIKO_A_CDC_TX4_DMIC_CTL (0x23D) +#define TAIKO_A_CDC_TX4_DMIC_CTL__POR (0x00) +#define TAIKO_A_CDC_TX5_DMIC_CTL (0x245) +#define TAIKO_A_CDC_TX5_DMIC_CTL__POR (0x00) +#define TAIKO_A_CDC_TX6_DMIC_CTL (0x24D) +#define TAIKO_A_CDC_TX6_DMIC_CTL__POR (0x00) +#define TAIKO_A_CDC_TX7_DMIC_CTL (0x255) +#define TAIKO_A_CDC_TX7_DMIC_CTL__POR (0x00) +#define TAIKO_A_CDC_TX8_DMIC_CTL (0x25D) +#define TAIKO_A_CDC_TX8_DMIC_CTL__POR (0x00) +#define TAIKO_A_CDC_TX9_DMIC_CTL (0x265) +#define TAIKO_A_CDC_TX9_DMIC_CTL__POR (0x00) +#define TAIKO_A_CDC_TX10_DMIC_CTL (0x26D) +#define TAIKO_A_CDC_TX10_DMIC_CTL__POR (0x00) +#define TAIKO_A_CDC_DEBUG_B1_CTL (0x278) +#define TAIKO_A_CDC_DEBUG_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_DEBUG_B2_CTL (0x279) +#define TAIKO_A_CDC_DEBUG_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_DEBUG_B3_CTL (0x27A) +#define TAIKO_A_CDC_DEBUG_B3_CTL__POR (0x00) +#define TAIKO_A_CDC_DEBUG_B4_CTL (0x27B) +#define TAIKO_A_CDC_DEBUG_B4_CTL__POR (0x00) +#define TAIKO_A_CDC_DEBUG_B5_CTL (0x27C) +#define TAIKO_A_CDC_DEBUG_B5_CTL__POR (0x00) +#define TAIKO_A_CDC_DEBUG_B6_CTL (0x27D) +#define TAIKO_A_CDC_DEBUG_B6_CTL__POR (0x00) +#define TAIKO_A_CDC_DEBUG_B7_CTL (0x27E) +#define TAIKO_A_CDC_DEBUG_B7_CTL__POR (0x00) +#define TAIKO_A_CDC_SRC1_PDA_CFG (0x2A0) +#define TAIKO_A_CDC_SRC1_PDA_CFG__POR (0x00) +#define TAIKO_A_CDC_SRC2_PDA_CFG (0x2A8) +#define TAIKO_A_CDC_SRC2_PDA_CFG__POR (0x00) +#define TAIKO_A_CDC_SRC1_FS_CTL (0x2A1) +#define TAIKO_A_CDC_SRC1_FS_CTL__POR (0x1B) +#define TAIKO_A_CDC_SRC2_FS_CTL (0x2A9) +#define TAIKO_A_CDC_SRC2_FS_CTL__POR (0x1B) +#define TAIKO_A_CDC_RX1_B1_CTL (0x2B0) +#define TAIKO_A_CDC_RX1_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_RX2_B1_CTL (0x2B8) +#define TAIKO_A_CDC_RX2_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_RX3_B1_CTL (0x2C0) +#define TAIKO_A_CDC_RX3_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_RX4_B1_CTL (0x2C8) +#define TAIKO_A_CDC_RX4_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_RX5_B1_CTL (0x2D0) +#define TAIKO_A_CDC_RX5_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_RX6_B1_CTL (0x2D8) +#define TAIKO_A_CDC_RX6_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_RX7_B1_CTL (0x2E0) +#define TAIKO_A_CDC_RX7_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_RX1_B2_CTL (0x2B1) +#define TAIKO_A_CDC_RX1_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_RX2_B2_CTL (0x2B9) +#define TAIKO_A_CDC_RX2_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_RX3_B2_CTL (0x2C1) +#define TAIKO_A_CDC_RX3_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_RX4_B2_CTL (0x2C9) +#define TAIKO_A_CDC_RX4_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_RX5_B2_CTL (0x2D1) +#define TAIKO_A_CDC_RX5_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_RX6_B2_CTL (0x2D9) +#define TAIKO_A_CDC_RX6_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_RX7_B2_CTL (0x2E1) +#define TAIKO_A_CDC_RX7_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_RX1_B3_CTL (0x2B2) +#define TAIKO_A_CDC_RX1_B3_CTL__POR (0x00) +#define TAIKO_A_CDC_RX2_B3_CTL (0x2BA) +#define TAIKO_A_CDC_RX2_B3_CTL__POR (0x00) +#define TAIKO_A_CDC_RX3_B3_CTL (0x2C2) +#define TAIKO_A_CDC_RX3_B3_CTL__POR (0x00) +#define TAIKO_A_CDC_RX4_B3_CTL (0x2CA) +#define TAIKO_A_CDC_RX4_B3_CTL__POR (0x00) +#define TAIKO_A_CDC_RX5_B3_CTL (0x2D2) +#define TAIKO_A_CDC_RX5_B3_CTL__POR (0x00) +#define TAIKO_A_CDC_RX6_B3_CTL (0x2DA) +#define TAIKO_A_CDC_RX6_B3_CTL__POR (0x00) +#define TAIKO_A_CDC_RX7_B3_CTL (0x2E2) +#define TAIKO_A_CDC_RX7_B3_CTL__POR (0x00) +#define TAIKO_A_CDC_RX1_B4_CTL (0x2B3) +#define TAIKO_A_CDC_RX1_B4_CTL__POR (0x00) +#define TAIKO_A_CDC_RX2_B4_CTL (0x2BB) +#define TAIKO_A_CDC_RX2_B4_CTL__POR (0x00) +#define TAIKO_A_CDC_RX3_B4_CTL (0x2C3) +#define TAIKO_A_CDC_RX3_B4_CTL__POR (0x00) +#define TAIKO_A_CDC_RX4_B4_CTL (0x2CB) +#define TAIKO_A_CDC_RX4_B4_CTL__POR (0x00) +#define TAIKO_A_CDC_RX5_B4_CTL (0x2D3) +#define TAIKO_A_CDC_RX5_B4_CTL__POR (0x00) +#define TAIKO_A_CDC_RX6_B4_CTL (0x2DB) +#define TAIKO_A_CDC_RX6_B4_CTL__POR (0x00) +#define TAIKO_A_CDC_RX7_B4_CTL (0x2E3) +#define TAIKO_A_CDC_RX7_B4_CTL__POR (0x00) +#define TAIKO_A_CDC_RX1_B5_CTL (0x2B4) +#define TAIKO_A_CDC_RX1_B5_CTL__POR (0x78) +#define TAIKO_A_CDC_RX2_B5_CTL (0x2BC) +#define TAIKO_A_CDC_RX2_B5_CTL__POR (0x78) +#define TAIKO_A_CDC_RX3_B5_CTL (0x2C4) +#define TAIKO_A_CDC_RX3_B5_CTL__POR (0x78) +#define TAIKO_A_CDC_RX4_B5_CTL (0x2CC) +#define TAIKO_A_CDC_RX4_B5_CTL__POR (0x78) +#define TAIKO_A_CDC_RX5_B5_CTL (0x2D4) +#define TAIKO_A_CDC_RX5_B5_CTL__POR (0x78) +#define TAIKO_A_CDC_RX6_B5_CTL (0x2DC) +#define TAIKO_A_CDC_RX6_B5_CTL__POR (0x78) +#define TAIKO_A_CDC_RX7_B5_CTL (0x2E4) +#define TAIKO_A_CDC_RX7_B5_CTL__POR (0x78) +#define TAIKO_A_CDC_RX1_B6_CTL (0x2B5) +#define TAIKO_A_CDC_RX1_B6_CTL__POR (0x80) +#define TAIKO_A_CDC_RX2_B6_CTL (0x2BD) +#define TAIKO_A_CDC_RX2_B6_CTL__POR (0x80) +#define TAIKO_A_CDC_RX3_B6_CTL (0x2C5) +#define TAIKO_A_CDC_RX3_B6_CTL__POR (0x80) +#define TAIKO_A_CDC_RX4_B6_CTL (0x2CD) +#define TAIKO_A_CDC_RX4_B6_CTL__POR (0x80) +#define TAIKO_A_CDC_RX5_B6_CTL (0x2D5) +#define TAIKO_A_CDC_RX5_B6_CTL__POR (0x80) +#define TAIKO_A_CDC_RX6_B6_CTL (0x2DD) +#define TAIKO_A_CDC_RX6_B6_CTL__POR (0x80) +#define TAIKO_A_CDC_RX7_B6_CTL (0x2E5) +#define TAIKO_A_CDC_RX7_B6_CTL__POR (0x80) +#define TAIKO_A_CDC_RX1_VOL_CTL_B1_CTL (0x2B6) +#define TAIKO_A_CDC_RX1_VOL_CTL_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_RX2_VOL_CTL_B1_CTL (0x2BE) +#define TAIKO_A_CDC_RX2_VOL_CTL_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_RX3_VOL_CTL_B1_CTL (0x2C6) +#define TAIKO_A_CDC_RX3_VOL_CTL_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_RX4_VOL_CTL_B1_CTL (0x2CE) +#define TAIKO_A_CDC_RX4_VOL_CTL_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_RX5_VOL_CTL_B1_CTL (0x2D6) +#define TAIKO_A_CDC_RX5_VOL_CTL_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_RX6_VOL_CTL_B1_CTL (0x2DE) +#define TAIKO_A_CDC_RX6_VOL_CTL_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_RX7_VOL_CTL_B1_CTL (0x2E6) +#define TAIKO_A_CDC_RX7_VOL_CTL_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_RX1_VOL_CTL_B2_CTL (0x2B7) +#define TAIKO_A_CDC_RX1_VOL_CTL_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_RX2_VOL_CTL_B2_CTL (0x2BF) +#define TAIKO_A_CDC_RX2_VOL_CTL_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_RX3_VOL_CTL_B2_CTL (0x2C7) +#define TAIKO_A_CDC_RX3_VOL_CTL_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_RX4_VOL_CTL_B2_CTL (0x2CF) +#define TAIKO_A_CDC_RX4_VOL_CTL_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_RX5_VOL_CTL_B2_CTL (0x2D7) +#define TAIKO_A_CDC_RX5_VOL_CTL_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_RX6_VOL_CTL_B2_CTL (0x2DF) +#define TAIKO_A_CDC_RX6_VOL_CTL_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_RX7_VOL_CTL_B2_CTL (0x2E7) +#define TAIKO_A_CDC_RX7_VOL_CTL_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_VBAT_CFG (0x2E8) +#define TAIKO_A_CDC_VBAT_CFG__POR (0x1A) +#define TAIKO_A_CDC_VBAT_ADC_CAL1 (0x2E9) +#define TAIKO_A_CDC_VBAT_ADC_CAL1__POR (0x00) +#define TAIKO_A_CDC_VBAT_ADC_CAL2 (0x2EA) +#define TAIKO_A_CDC_VBAT_ADC_CAL2__POR (0x00) +#define TAIKO_A_CDC_VBAT_ADC_CAL3 (0x2EB) +#define TAIKO_A_CDC_VBAT_ADC_CAL3__POR (0x04) +#define TAIKO_A_CDC_VBAT_PK_EST1 (0x2EC) +#define TAIKO_A_CDC_VBAT_PK_EST1__POR (0xE0) +#define TAIKO_A_CDC_VBAT_PK_EST2 (0x2ED) +#define TAIKO_A_CDC_VBAT_PK_EST2__POR (0x01) +#define TAIKO_A_CDC_VBAT_PK_EST3 (0x2EE) +#define TAIKO_A_CDC_VBAT_PK_EST3__POR (0x40) +#define TAIKO_A_CDC_VBAT_RF_PROC1 (0x2EF) +#define TAIKO_A_CDC_VBAT_RF_PROC1__POR (0x2A) +#define TAIKO_A_CDC_VBAT_RF_PROC2 (0x2F0) +#define TAIKO_A_CDC_VBAT_RF_PROC2__POR (0x86) +#define TAIKO_A_CDC_VBAT_TAC1 (0x2F1) +#define TAIKO_A_CDC_VBAT_TAC1__POR (0x70) +#define TAIKO_A_CDC_VBAT_TAC2 (0x2F2) +#define TAIKO_A_CDC_VBAT_TAC2__POR (0x18) +#define TAIKO_A_CDC_VBAT_TAC3 (0x2F3) +#define TAIKO_A_CDC_VBAT_TAC3__POR (0x18) +#define TAIKO_A_CDC_VBAT_TAC4 (0x2F4) +#define TAIKO_A_CDC_VBAT_TAC4__POR (0x03) +#define TAIKO_A_CDC_VBAT_GAIN_UPD1 (0x2F5) +#define TAIKO_A_CDC_VBAT_GAIN_UPD1__POR (0x01) +#define TAIKO_A_CDC_VBAT_GAIN_UPD2 (0x2F6) +#define TAIKO_A_CDC_VBAT_GAIN_UPD2__POR (0x00) +#define TAIKO_A_CDC_VBAT_GAIN_UPD3 (0x2F7) +#define TAIKO_A_CDC_VBAT_GAIN_UPD3__POR (0x64) +#define TAIKO_A_CDC_VBAT_GAIN_UPD4 (0x2F8) +#define TAIKO_A_CDC_VBAT_GAIN_UPD4__POR (0x01) +#define TAIKO_A_CDC_VBAT_DEBUG1 (0x2F9) +#define TAIKO_A_CDC_VBAT_DEBUG1__POR (0x00) +#define TAIKO_A_CDC_CLK_ANC_RESET_CTL (0x300) +#define TAIKO_A_CDC_CLK_ANC_RESET_CTL__POR (0x00) +#define TAIKO_A_CDC_CLK_RX_RESET_CTL (0x301) +#define TAIKO_A_CDC_CLK_RX_RESET_CTL__POR (0x00) +#define TAIKO_A_CDC_CLK_TX_RESET_B1_CTL (0x302) +#define TAIKO_A_CDC_CLK_TX_RESET_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_CLK_TX_RESET_B2_CTL (0x303) +#define TAIKO_A_CDC_CLK_TX_RESET_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_CLK_DMIC_B1_CTL (0x304) +#define TAIKO_A_CDC_CLK_DMIC_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_CLK_DMIC_B2_CTL (0x305) +#define TAIKO_A_CDC_CLK_DMIC_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_CLK_RX_I2S_CTL (0x306) +#define TAIKO_A_CDC_CLK_RX_I2S_CTL__POR (0x03) +#define TAIKO_A_CDC_CLK_TX_I2S_CTL (0x307) +#define TAIKO_A_CDC_CLK_TX_I2S_CTL__POR (0x03) +#define TAIKO_A_CDC_CLK_OTHR_RESET_B1_CTL (0x308) +#define TAIKO_A_CDC_CLK_OTHR_RESET_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_CLK_OTHR_RESET_B2_CTL (0x309) +#define TAIKO_A_CDC_CLK_OTHR_RESET_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_CLK_TX_CLK_EN_B1_CTL (0x30A) +#define TAIKO_A_CDC_CLK_TX_CLK_EN_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_CLK_TX_CLK_EN_B2_CTL (0x30B) +#define TAIKO_A_CDC_CLK_TX_CLK_EN_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_CLK_OTHR_CTL (0x30C) +#define TAIKO_A_CDC_CLK_OTHR_CTL__POR (0x00) +#define TAIKO_A_CDC_CLK_RDAC_CLK_EN_CTL (0x30D) +#define TAIKO_A_CDC_CLK_RDAC_CLK_EN_CTL__POR (0x00) +#define TAIKO_A_CDC_CLK_ANC_CLK_EN_CTL (0x30E) +#define TAIKO_A_CDC_CLK_ANC_CLK_EN_CTL__POR (0x00) +#define TAIKO_A_CDC_CLK_RX_B1_CTL (0x30F) +#define TAIKO_A_CDC_CLK_RX_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_CLK_RX_B2_CTL (0x310) +#define TAIKO_A_CDC_CLK_RX_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_CLK_MCLK_CTL (0x311) +#define TAIKO_A_CDC_CLK_MCLK_CTL__POR (0x00) +#define TAIKO_A_CDC_CLK_PDM_CTL (0x312) +#define TAIKO_A_CDC_CLK_PDM_CTL__POR (0x00) +#define TAIKO_A_CDC_CLK_SD_CTL (0x313) +#define TAIKO_A_CDC_CLK_SD_CTL__POR (0x00) +#define TAIKO_A_CDC_CLK_POWER_CTL (0x314) +#define TAIKO_A_CDC_CLK_POWER_CTL__POR (0x00) +#define TAIKO_A_CDC_CLSH_B1_CTL (0x320) +#define TAIKO_A_CDC_CLSH_B1_CTL__POR (0xE4) +#define TAIKO_A_CDC_CLSH_B2_CTL (0x321) +#define TAIKO_A_CDC_CLSH_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_CLSH_B3_CTL (0x322) +#define TAIKO_A_CDC_CLSH_B3_CTL__POR (0x00) +#define TAIKO_A_CDC_CLSH_BUCK_NCP_VARS (0x323) +#define TAIKO_A_CDC_CLSH_BUCK_NCP_VARS__POR (0x00) +#define TAIKO_A_CDC_CLSH_IDLE_HPH_THSD (0x324) +#define TAIKO_A_CDC_CLSH_IDLE_HPH_THSD__POR (0x12) +#define TAIKO_A_CDC_CLSH_IDLE_EAR_THSD (0x325) +#define TAIKO_A_CDC_CLSH_IDLE_EAR_THSD__POR (0x0C) +#define TAIKO_A_CDC_CLSH_FCLKONLY_HPH_THSD (0x326) +#define TAIKO_A_CDC_CLSH_FCLKONLY_HPH_THSD__POR (0x18) +#define TAIKO_A_CDC_CLSH_FCLKONLY_EAR_THSD (0x327) +#define TAIKO_A_CDC_CLSH_FCLKONLY_EAR_THSD__POR (0x23) +#define TAIKO_A_CDC_CLSH_K_ADDR (0x328) +#define TAIKO_A_CDC_CLSH_K_ADDR__POR (0x00) +#define TAIKO_A_CDC_CLSH_K_DATA (0x329) +#define TAIKO_A_CDC_CLSH_K_DATA__POR (0xA4) +#define TAIKO_A_CDC_CLSH_I_PA_FACT_HPH_L (0x32A) +#define TAIKO_A_CDC_CLSH_I_PA_FACT_HPH_L__POR (0xD7) +#define TAIKO_A_CDC_CLSH_I_PA_FACT_HPH_U (0x32B) +#define TAIKO_A_CDC_CLSH_I_PA_FACT_HPH_U__POR (0x05) +#define TAIKO_A_CDC_CLSH_I_PA_FACT_EAR_L (0x32C) +#define TAIKO_A_CDC_CLSH_I_PA_FACT_EAR_L__POR (0x60) +#define TAIKO_A_CDC_CLSH_I_PA_FACT_EAR_U (0x32D) +#define TAIKO_A_CDC_CLSH_I_PA_FACT_EAR_U__POR (0x09) +#define TAIKO_A_CDC_CLSH_V_PA_HD_EAR (0x32E) +#define TAIKO_A_CDC_CLSH_V_PA_HD_EAR__POR (0x00) +#define TAIKO_A_CDC_CLSH_V_PA_HD_HPH (0x32F) +#define TAIKO_A_CDC_CLSH_V_PA_HD_HPH__POR (0x00) +#define TAIKO_A_CDC_CLSH_V_PA_MIN_EAR (0x330) +#define TAIKO_A_CDC_CLSH_V_PA_MIN_EAR__POR (0x00) +#define TAIKO_A_CDC_CLSH_V_PA_MIN_HPH (0x331) +#define TAIKO_A_CDC_CLSH_V_PA_MIN_HPH__POR (0x00) +#define TAIKO_A_CDC_IIR1_GAIN_B1_CTL (0x340) +#define TAIKO_A_CDC_IIR1_GAIN_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_IIR2_GAIN_B1_CTL (0x350) +#define TAIKO_A_CDC_IIR2_GAIN_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_IIR1_GAIN_B2_CTL (0x341) +#define TAIKO_A_CDC_IIR1_GAIN_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_IIR2_GAIN_B2_CTL (0x351) +#define TAIKO_A_CDC_IIR2_GAIN_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_IIR1_GAIN_B3_CTL (0x342) +#define TAIKO_A_CDC_IIR1_GAIN_B3_CTL__POR (0x00) +#define TAIKO_A_CDC_IIR2_GAIN_B3_CTL (0x352) +#define TAIKO_A_CDC_IIR2_GAIN_B3_CTL__POR (0x00) +#define TAIKO_A_CDC_IIR1_GAIN_B4_CTL (0x343) +#define TAIKO_A_CDC_IIR1_GAIN_B4_CTL__POR (0x00) +#define TAIKO_A_CDC_IIR2_GAIN_B4_CTL (0x353) +#define TAIKO_A_CDC_IIR2_GAIN_B4_CTL__POR (0x00) +#define TAIKO_A_CDC_IIR1_GAIN_B5_CTL (0x344) +#define TAIKO_A_CDC_IIR1_GAIN_B5_CTL__POR (0x00) +#define TAIKO_A_CDC_IIR2_GAIN_B5_CTL (0x354) +#define TAIKO_A_CDC_IIR2_GAIN_B5_CTL__POR (0x00) +#define TAIKO_A_CDC_IIR1_GAIN_B6_CTL (0x345) +#define TAIKO_A_CDC_IIR1_GAIN_B6_CTL__POR (0x00) +#define TAIKO_A_CDC_IIR2_GAIN_B6_CTL (0x355) +#define TAIKO_A_CDC_IIR2_GAIN_B6_CTL__POR (0x00) +#define TAIKO_A_CDC_IIR1_GAIN_B7_CTL (0x346) +#define TAIKO_A_CDC_IIR1_GAIN_B7_CTL__POR (0x00) +#define TAIKO_A_CDC_IIR2_GAIN_B7_CTL (0x356) +#define TAIKO_A_CDC_IIR2_GAIN_B7_CTL__POR (0x00) +#define TAIKO_A_CDC_IIR1_GAIN_B8_CTL (0x347) +#define TAIKO_A_CDC_IIR1_GAIN_B8_CTL__POR (0x00) +#define TAIKO_A_CDC_IIR2_GAIN_B8_CTL (0x357) +#define TAIKO_A_CDC_IIR2_GAIN_B8_CTL__POR (0x00) +#define TAIKO_A_CDC_IIR1_CTL (0x348) +#define TAIKO_A_CDC_IIR1_CTL__POR (0x40) +#define TAIKO_A_CDC_IIR2_CTL (0x358) +#define TAIKO_A_CDC_IIR2_CTL__POR (0x40) +#define TAIKO_A_CDC_IIR1_GAIN_TIMER_CTL (0x349) +#define TAIKO_A_CDC_IIR1_GAIN_TIMER_CTL__POR (0x00) +#define TAIKO_A_CDC_IIR2_GAIN_TIMER_CTL (0x359) +#define TAIKO_A_CDC_IIR2_GAIN_TIMER_CTL__POR (0x00) +#define TAIKO_A_CDC_IIR1_COEF_B1_CTL (0x34A) +#define TAIKO_A_CDC_IIR1_COEF_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_IIR2_COEF_B1_CTL (0x35A) +#define TAIKO_A_CDC_IIR2_COEF_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_IIR1_COEF_B2_CTL (0x34B) +#define TAIKO_A_CDC_IIR1_COEF_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_IIR2_COEF_B2_CTL (0x35B) +#define TAIKO_A_CDC_IIR2_COEF_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_TOP_GAIN_UPDATE (0x360) +#define TAIKO_A_CDC_TOP_GAIN_UPDATE__POR (0x00) +#define TAIKO_A_CDC_COMP0_B1_CTL (0x368) +#define TAIKO_A_CDC_COMP0_B1_CTL__POR (0x30) +#define TAIKO_A_CDC_COMP1_B1_CTL (0x370) +#define TAIKO_A_CDC_COMP1_B1_CTL__POR (0x30) +#define TAIKO_A_CDC_COMP2_B1_CTL (0x378) +#define TAIKO_A_CDC_COMP2_B1_CTL__POR (0x30) +#define TAIKO_A_CDC_COMP0_B2_CTL (0x369) +#define TAIKO_A_CDC_COMP0_B2_CTL__POR (0xB5) +#define TAIKO_A_CDC_COMP1_B2_CTL (0x371) +#define TAIKO_A_CDC_COMP1_B2_CTL__POR (0xB5) +#define TAIKO_A_CDC_COMP2_B2_CTL (0x379) +#define TAIKO_A_CDC_COMP2_B2_CTL__POR (0xB5) +#define TAIKO_A_CDC_COMP0_B3_CTL (0x36A) +#define TAIKO_A_CDC_COMP0_B3_CTL__POR (0x28) +#define TAIKO_A_CDC_COMP1_B3_CTL (0x372) +#define TAIKO_A_CDC_COMP1_B3_CTL__POR (0x28) +#define TAIKO_A_CDC_COMP2_B3_CTL (0x37A) +#define TAIKO_A_CDC_COMP2_B3_CTL__POR (0x28) +#define TAIKO_A_CDC_COMP0_B4_CTL (0x36B) +#define TAIKO_A_CDC_COMP0_B4_CTL__POR (0x3C) +#define TAIKO_A_CDC_COMP1_B4_CTL (0x373) +#define TAIKO_A_CDC_COMP1_B4_CTL__POR (0x3C) +#define TAIKO_A_CDC_COMP2_B4_CTL (0x37B) +#define TAIKO_A_CDC_COMP2_B4_CTL__POR (0x3C) +#define TAIKO_A_CDC_COMP0_B5_CTL (0x36C) +#define TAIKO_A_CDC_COMP0_B5_CTL__POR (0x1F) +#define TAIKO_A_CDC_COMP1_B5_CTL (0x374) +#define TAIKO_A_CDC_COMP1_B5_CTL__POR (0x1F) +#define TAIKO_A_CDC_COMP2_B5_CTL (0x37C) +#define TAIKO_A_CDC_COMP2_B5_CTL__POR (0x1F) +#define TAIKO_A_CDC_COMP0_B6_CTL (0x36D) +#define TAIKO_A_CDC_COMP0_B6_CTL__POR (0x00) +#define TAIKO_A_CDC_COMP1_B6_CTL (0x375) +#define TAIKO_A_CDC_COMP1_B6_CTL__POR (0x00) +#define TAIKO_A_CDC_COMP2_B6_CTL (0x37D) +#define TAIKO_A_CDC_COMP2_B6_CTL__POR (0x00) +#define TAIKO_A_CDC_COMP0_SHUT_DOWN_STATUS (0x36E) +#define TAIKO_A_CDC_COMP0_SHUT_DOWN_STATUS__POR (0x03) +#define TAIKO_A_CDC_COMP1_SHUT_DOWN_STATUS (0x376) +#define TAIKO_A_CDC_COMP1_SHUT_DOWN_STATUS__POR (0x03) +#define TAIKO_A_CDC_COMP2_SHUT_DOWN_STATUS (0x37E) +#define TAIKO_A_CDC_COMP2_SHUT_DOWN_STATUS__POR (0x03) +#define TAIKO_A_CDC_COMP0_FS_CFG (0x36F) +#define TAIKO_A_CDC_COMP0_FS_CFG__POR (0x03) +#define TAIKO_A_CDC_COMP1_FS_CFG (0x377) +#define TAIKO_A_CDC_COMP1_FS_CFG__POR (0x03) +#define TAIKO_A_CDC_COMP2_FS_CFG (0x37F) +#define TAIKO_A_CDC_COMP2_FS_CFG__POR (0x03) +#define TAIKO_A_CDC_CONN_RX1_B1_CTL (0x380) +#define TAIKO_A_CDC_CONN_RX1_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_RX1_B2_CTL (0x381) +#define TAIKO_A_CDC_CONN_RX1_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_RX1_B3_CTL (0x382) +#define TAIKO_A_CDC_CONN_RX1_B3_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_RX2_B1_CTL (0x383) +#define TAIKO_A_CDC_CONN_RX2_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_RX2_B2_CTL (0x384) +#define TAIKO_A_CDC_CONN_RX2_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_RX2_B3_CTL (0x385) +#define TAIKO_A_CDC_CONN_RX2_B3_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_RX3_B1_CTL (0x386) +#define TAIKO_A_CDC_CONN_RX3_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_RX3_B2_CTL (0x387) +#define TAIKO_A_CDC_CONN_RX3_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_RX4_B1_CTL (0x388) +#define TAIKO_A_CDC_CONN_RX4_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_RX4_B2_CTL (0x389) +#define TAIKO_A_CDC_CONN_RX4_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_RX5_B1_CTL (0x38A) +#define TAIKO_A_CDC_CONN_RX5_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_RX5_B2_CTL (0x38B) +#define TAIKO_A_CDC_CONN_RX5_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_RX6_B1_CTL (0x38C) +#define TAIKO_A_CDC_CONN_RX6_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_RX6_B2_CTL (0x38D) +#define TAIKO_A_CDC_CONN_RX6_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_RX7_B1_CTL (0x38E) +#define TAIKO_A_CDC_CONN_RX7_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_RX7_B2_CTL (0x38F) +#define TAIKO_A_CDC_CONN_RX7_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_RX7_B3_CTL (0x390) +#define TAIKO_A_CDC_CONN_RX7_B3_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_ANC_B1_CTL (0x391) +#define TAIKO_A_CDC_CONN_ANC_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_ANC_B2_CTL (0x392) +#define TAIKO_A_CDC_CONN_ANC_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_TX_B1_CTL (0x393) +#define TAIKO_A_CDC_CONN_TX_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_TX_B2_CTL (0x394) +#define TAIKO_A_CDC_CONN_TX_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_TX_B3_CTL (0x395) +#define TAIKO_A_CDC_CONN_TX_B3_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_TX_B4_CTL (0x396) +#define TAIKO_A_CDC_CONN_TX_B4_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_EQ1_B1_CTL (0x397) +#define TAIKO_A_CDC_CONN_EQ1_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_EQ1_B2_CTL (0x398) +#define TAIKO_A_CDC_CONN_EQ1_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_EQ1_B3_CTL (0x399) +#define TAIKO_A_CDC_CONN_EQ1_B3_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_EQ1_B4_CTL (0x39A) +#define TAIKO_A_CDC_CONN_EQ1_B4_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_EQ2_B1_CTL (0x39B) +#define TAIKO_A_CDC_CONN_EQ2_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_EQ2_B2_CTL (0x39C) +#define TAIKO_A_CDC_CONN_EQ2_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_EQ2_B3_CTL (0x39D) +#define TAIKO_A_CDC_CONN_EQ2_B3_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_EQ2_B4_CTL (0x39E) +#define TAIKO_A_CDC_CONN_EQ2_B4_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_SRC1_B1_CTL (0x39F) +#define TAIKO_A_CDC_CONN_SRC1_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_SRC1_B2_CTL (0x3A0) +#define TAIKO_A_CDC_CONN_SRC1_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_SRC2_B1_CTL (0x3A1) +#define TAIKO_A_CDC_CONN_SRC2_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_SRC2_B2_CTL (0x3A2) +#define TAIKO_A_CDC_CONN_SRC2_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_TX_SB_B1_CTL (0x3A3) +#define TAIKO_A_CDC_CONN_TX_SB_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_TX_SB_B2_CTL (0x3A4) +#define TAIKO_A_CDC_CONN_TX_SB_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_TX_SB_B3_CTL (0x3A5) +#define TAIKO_A_CDC_CONN_TX_SB_B3_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_TX_SB_B4_CTL (0x3A6) +#define TAIKO_A_CDC_CONN_TX_SB_B4_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_TX_SB_B5_CTL (0x3A7) +#define TAIKO_A_CDC_CONN_TX_SB_B5_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_TX_SB_B6_CTL (0x3A8) +#define TAIKO_A_CDC_CONN_TX_SB_B6_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_TX_SB_B7_CTL (0x3A9) +#define TAIKO_A_CDC_CONN_TX_SB_B7_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_TX_SB_B8_CTL (0x3AA) +#define TAIKO_A_CDC_CONN_TX_SB_B8_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_TX_SB_B9_CTL (0x3AB) +#define TAIKO_A_CDC_CONN_TX_SB_B9_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_TX_SB_B10_CTL (0x3AC) +#define TAIKO_A_CDC_CONN_TX_SB_B10_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_TX_SB_B11_CTL (0x3AD) +#define TAIKO_A_CDC_CONN_TX_SB_B11_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_RX_SB_B1_CTL (0x3AE) +#define TAIKO_A_CDC_CONN_RX_SB_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_RX_SB_B2_CTL (0x3AF) +#define TAIKO_A_CDC_CONN_RX_SB_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_CLSH_CTL (0x3B0) +#define TAIKO_A_CDC_CONN_CLSH_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_MISC (0x3B1) +#define TAIKO_A_CDC_CONN_MISC__POR (0x01) +#define TAIKO_A_CDC_CONN_MAD (0x3B2) +#define TAIKO_A_CDC_CONN_MAD__POR (0x01) +#define TAIKO_A_CDC_MBHC_EN_CTL (0x3C0) +#define TAIKO_A_CDC_MBHC_EN_CTL__POR (0x00) +#define TAIKO_A_CDC_MBHC_FIR_B1_CFG (0x3C1) +#define TAIKO_A_CDC_MBHC_FIR_B1_CFG__POR (0x00) +#define TAIKO_A_CDC_MBHC_FIR_B2_CFG (0x3C2) +#define TAIKO_A_CDC_MBHC_FIR_B2_CFG__POR (0x06) +#define TAIKO_A_CDC_MBHC_TIMER_B1_CTL (0x3C3) +#define TAIKO_A_CDC_MBHC_TIMER_B1_CTL__POR (0x03) +#define TAIKO_A_CDC_MBHC_TIMER_B2_CTL (0x3C4) +#define TAIKO_A_CDC_MBHC_TIMER_B2_CTL__POR (0x09) +#define TAIKO_A_CDC_MBHC_TIMER_B3_CTL (0x3C5) +#define TAIKO_A_CDC_MBHC_TIMER_B3_CTL__POR (0x1E) +#define TAIKO_A_CDC_MBHC_TIMER_B4_CTL (0x3C6) +#define TAIKO_A_CDC_MBHC_TIMER_B4_CTL__POR (0x45) +#define TAIKO_A_CDC_MBHC_TIMER_B5_CTL (0x3C7) +#define TAIKO_A_CDC_MBHC_TIMER_B5_CTL__POR (0x04) +#define TAIKO_A_CDC_MBHC_TIMER_B6_CTL (0x3C8) +#define TAIKO_A_CDC_MBHC_TIMER_B6_CTL__POR (0x78) +#define TAIKO_A_CDC_MBHC_B1_STATUS (0x3C9) +#define TAIKO_A_CDC_MBHC_B1_STATUS__POR (0x00) +#define TAIKO_A_CDC_MBHC_B2_STATUS (0x3CA) +#define TAIKO_A_CDC_MBHC_B2_STATUS__POR (0x00) +#define TAIKO_A_CDC_MBHC_B3_STATUS (0x3CB) +#define TAIKO_A_CDC_MBHC_B3_STATUS__POR (0x00) +#define TAIKO_A_CDC_MBHC_B4_STATUS (0x3CC) +#define TAIKO_A_CDC_MBHC_B4_STATUS__POR (0x00) +#define TAIKO_A_CDC_MBHC_B5_STATUS (0x3CD) +#define TAIKO_A_CDC_MBHC_B5_STATUS__POR (0x00) +#define TAIKO_A_CDC_MBHC_B1_CTL (0x3CE) +#define TAIKO_A_CDC_MBHC_B1_CTL__POR (0xC0) +#define TAIKO_A_CDC_MBHC_B2_CTL (0x3CF) +#define TAIKO_A_CDC_MBHC_B2_CTL__POR (0x5D) +#define TAIKO_A_CDC_MBHC_VOLT_B1_CTL (0x3D0) +#define TAIKO_A_CDC_MBHC_VOLT_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_MBHC_VOLT_B2_CTL (0x3D1) +#define TAIKO_A_CDC_MBHC_VOLT_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_MBHC_VOLT_B3_CTL (0x3D2) +#define TAIKO_A_CDC_MBHC_VOLT_B3_CTL__POR (0x00) +#define TAIKO_A_CDC_MBHC_VOLT_B4_CTL (0x3D3) +#define TAIKO_A_CDC_MBHC_VOLT_B4_CTL__POR (0x00) +#define TAIKO_A_CDC_MBHC_VOLT_B5_CTL (0x3D4) +#define TAIKO_A_CDC_MBHC_VOLT_B5_CTL__POR (0x00) +#define TAIKO_A_CDC_MBHC_VOLT_B6_CTL (0x3D5) +#define TAIKO_A_CDC_MBHC_VOLT_B6_CTL__POR (0x00) +#define TAIKO_A_CDC_MBHC_VOLT_B7_CTL (0x3D6) +#define TAIKO_A_CDC_MBHC_VOLT_B7_CTL__POR (0xFF) +#define TAIKO_A_CDC_MBHC_VOLT_B8_CTL (0x3D7) +#define TAIKO_A_CDC_MBHC_VOLT_B8_CTL__POR (0x07) +#define TAIKO_A_CDC_MBHC_VOLT_B9_CTL (0x3D8) +#define TAIKO_A_CDC_MBHC_VOLT_B9_CTL__POR (0xFF) +#define TAIKO_A_CDC_MBHC_VOLT_B10_CTL (0x3D9) +#define TAIKO_A_CDC_MBHC_VOLT_B10_CTL__POR (0x7F) +#define TAIKO_A_CDC_MBHC_VOLT_B11_CTL (0x3DA) +#define TAIKO_A_CDC_MBHC_VOLT_B11_CTL__POR (0x00) +#define TAIKO_A_CDC_MBHC_VOLT_B12_CTL (0x3DB) +#define TAIKO_A_CDC_MBHC_VOLT_B12_CTL__POR (0x80) +#define TAIKO_A_CDC_MBHC_CLK_CTL (0x3DC) +#define TAIKO_A_CDC_MBHC_CLK_CTL__POR (0x00) +#define TAIKO_A_CDC_MBHC_INT_CTL (0x3DD) +#define TAIKO_A_CDC_MBHC_INT_CTL__POR (0x00) +#define TAIKO_A_CDC_MBHC_DEBUG_CTL (0x3DE) +#define TAIKO_A_CDC_MBHC_DEBUG_CTL__POR (0x00) +#define TAIKO_A_CDC_MBHC_SPARE (0x3DF) +#define TAIKO_A_CDC_MBHC_SPARE__POR (0x00) +#define TAIKO_A_CDC_MAD_MAIN_CTL_1 (0x3E0) +#define TAIKO_A_CDC_MAD_MAIN_CTL_1__POR (0x00) +#define TAIKO_A_CDC_MAD_MAIN_CTL_2 (0x3E1) +#define TAIKO_A_CDC_MAD_MAIN_CTL_2__POR (0x00) +#define TAIKO_A_CDC_MAD_AUDIO_CTL_1 (0x3E2) +#define TAIKO_A_CDC_MAD_AUDIO_CTL_1__POR (0x00) +#define TAIKO_A_CDC_MAD_AUDIO_CTL_2 (0x3E3) +#define TAIKO_A_CDC_MAD_AUDIO_CTL_2__POR (0x00) +#define TAIKO_A_CDC_MAD_AUDIO_CTL_3 (0x3E4) +#define TAIKO_A_CDC_MAD_AUDIO_CTL_3__POR (0x00) +#define TAIKO_A_CDC_MAD_AUDIO_CTL_4 (0x3E5) +#define TAIKO_A_CDC_MAD_AUDIO_CTL_4__POR (0x00) +#define TAIKO_A_CDC_MAD_AUDIO_CTL_5 (0x3E6) +#define TAIKO_A_CDC_MAD_AUDIO_CTL_5__POR (0x00) +#define TAIKO_A_CDC_MAD_AUDIO_CTL_6 (0x3E7) +#define TAIKO_A_CDC_MAD_AUDIO_CTL_6__POR (0x00) +#define TAIKO_A_CDC_MAD_AUDIO_CTL_7 (0x3E8) +#define TAIKO_A_CDC_MAD_AUDIO_CTL_7__POR (0x00) +#define TAIKO_A_CDC_MAD_AUDIO_CTL_8 (0x3E9) +#define TAIKO_A_CDC_MAD_AUDIO_CTL_8__POR (0x00) +#define TAIKO_A_CDC_MAD_AUDIO_IIR_CTL_PTR (0x3EA) +#define TAIKO_A_CDC_MAD_AUDIO_IIR_CTL_PTR__POR (0x00) +#define TAIKO_A_CDC_MAD_AUDIO_IIR_CTL_VAL (0x3EB) +#define TAIKO_A_CDC_MAD_AUDIO_IIR_CTL_VAL__POR (0x40) +#define TAIKO_A_CDC_MAD_ULTR_CTL_1 (0x3EC) +#define TAIKO_A_CDC_MAD_ULTR_CTL_1__POR (0x00) +#define TAIKO_A_CDC_MAD_ULTR_CTL_2 (0x3ED) +#define TAIKO_A_CDC_MAD_ULTR_CTL_2__POR (0x00) +#define TAIKO_A_CDC_MAD_ULTR_CTL_3 (0x3EE) +#define TAIKO_A_CDC_MAD_ULTR_CTL_3__POR (0x00) +#define TAIKO_A_CDC_MAD_ULTR_CTL_4 (0x3EF) +#define TAIKO_A_CDC_MAD_ULTR_CTL_4__POR (0x00) +#define TAIKO_A_CDC_MAD_ULTR_CTL_5 (0x3F0) +#define TAIKO_A_CDC_MAD_ULTR_CTL_5__POR (0x00) +#define TAIKO_A_CDC_MAD_ULTR_CTL_6 (0x3F1) +#define TAIKO_A_CDC_MAD_ULTR_CTL_6__POR (0x00) +#define TAIKO_A_CDC_MAD_ULTR_CTL_7 (0x3F2) +#define TAIKO_A_CDC_MAD_ULTR_CTL_7__POR (0x00) +#define TAIKO_A_CDC_MAD_BEACON_CTL_1 (0x3F3) +#define TAIKO_A_CDC_MAD_BEACON_CTL_1__POR (0x00) +#define TAIKO_A_CDC_MAD_BEACON_CTL_2 (0x3F4) +#define TAIKO_A_CDC_MAD_BEACON_CTL_2__POR (0x00) +#define TAIKO_A_CDC_MAD_BEACON_CTL_3 (0x3F5) +#define TAIKO_A_CDC_MAD_BEACON_CTL_3__POR (0x00) +#define TAIKO_A_CDC_MAD_BEACON_CTL_4 (0x3F6) +#define TAIKO_A_CDC_MAD_BEACON_CTL_4__POR (0x00) +#define TAIKO_A_CDC_MAD_BEACON_CTL_5 (0x3F7) +#define TAIKO_A_CDC_MAD_BEACON_CTL_5__POR (0x00) +#define TAIKO_A_CDC_MAD_BEACON_CTL_6 (0x3F8) +#define TAIKO_A_CDC_MAD_BEACON_CTL_6__POR (0x00) +#define TAIKO_A_CDC_MAD_BEACON_CTL_7 (0x3F9) +#define TAIKO_A_CDC_MAD_BEACON_CTL_7__POR (0x00) +#define TAIKO_A_CDC_MAD_BEACON_CTL_8 (0x3FA) +#define TAIKO_A_CDC_MAD_BEACON_CTL_8__POR (0x00) +#define TAIKO_A_CDC_MAD_BEACON_IIR_CTL_PTR (0x3FB) +#define TAIKO_A_CDC_MAD_BEACON_IIR_CTL_PTR__POR (0x00) +#define TAIKO_A_CDC_MAD_BEACON_IIR_CTL_VAL (0x3FC) +#define TAIKO_A_CDC_MAD_BEACON_IIR_CTL_VAL__POR (0x00) + +/* Taiko v2+ registers */ +#define TAIKO_A_CDC_TX_1_GAIN (0x153) +#define TAIKO_A_CDC_TX_1_GAIN__POR (0x02) +#define TAIKO_A_CDC_TX_2_GAIN (0x155) +#define TAIKO_A_CDC_TX_2_GAIN__POR (0x02) +#define TAIKO_A_CDC_TX_1_2_ADC_IB (0x156) +#define TAIKO_A_CDC_TX_1_2_ADC_IB__POR (0x44) +#define TAIKO_A_CDC_TX_3_GAIN (0x15D) +#define TAIKO_A_CDC_TX_3_GAIN__POR (0x02) +#define TAIKO_A_CDC_TX_4_GAIN (0x15F) +#define TAIKO_A_CDC_TX_4_GAIN__POR (0x02) +#define TAIKO_A_CDC_TX_3_4_ADC_IB (0x160) +#define TAIKO_A_CDC_TX_3_4_ADC_IB__POR (0x44) +#define TAIKO_A_CDC_TX_5_GAIN (0x167) +#define TAIKO_A_CDC_TX_5_GAIN__POR (0x02) +#define TAIKO_A_CDC_TX_6_GAIN (0x169) +#define TAIKO_A_CDC_TX_6_GAIN__POR (0x02) +#define TAIKO_A_CDC_TX_5_6_ADC_IB (0x16A) +#define TAIKO_A_CDC_TX_5_6_ADC_IB__POR (0x44) +#define TAIKO_A_CDC_SPKR_CLIPDET_VAL0 (0x270) +#define TAIKO_A_CDC_SPKR_CLIPDET_VAL0__POR (0x00) +#define TAIKO_A_CDC_SPKR_CLIPDET_VAL1 (0x271) +#define TAIKO_A_CDC_SPKR_CLIPDET_VAL1__POR (0x00) +#define TAIKO_A_CDC_SPKR_CLIPDET_VAL2 (0x272) +#define TAIKO_A_CDC_SPKR_CLIPDET_VAL2__POR (0x00) +#define TAIKO_A_CDC_SPKR_CLIPDET_VAL3 (0x273) +#define TAIKO_A_CDC_SPKR_CLIPDET_VAL3__POR (0x00) +#define TAIKO_A_CDC_SPKR_CLIPDET_VAL4 (0x274) +#define TAIKO_A_CDC_SPKR_CLIPDET_VAL4__POR (0x00) +#define TAIKO_A_CDC_SPKR_CLIPDET_VAL5 (0x275) +#define TAIKO_A_CDC_SPKR_CLIPDET_VAL5__POR (0x00) +#define TAIKO_A_CDC_SPKR_CLIPDET_VAL6 (0x276) +#define TAIKO_A_CDC_SPKR_CLIPDET_VAL6__POR (0x00) +#define TAIKO_A_CDC_SPKR_CLIPDET_VAL7 (0x277) +#define TAIKO_A_CDC_SPKR_CLIPDET_VAL7__POR (0x00) +#define TAIKO_A_CDC_VBAT_GAIN_UPD_MON (0x2FA) +#define TAIKO_A_CDC_VBAT_GAIN_UPD_MON__POR (0x00) +#define TAIKO_A_CDC_VBAT_GAIN_MON_VAL (0x2FB) +#define TAIKO_A_CDC_VBAT_GAIN_MON_VAL__POR (0x00) +#define TAIKO_A_CDC_PA_RAMP_B1_CTL (0x361) +#define TAIKO_A_CDC_PA_RAMP_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_PA_RAMP_B2_CTL (0x362) +#define TAIKO_A_CDC_PA_RAMP_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_PA_RAMP_B3_CTL (0x363) +#define TAIKO_A_CDC_PA_RAMP_B3_CTL__POR (0x00) +#define TAIKO_A_CDC_PA_RAMP_B4_CTL (0x364) +#define TAIKO_A_CDC_PA_RAMP_B4_CTL__POR (0x00) +#define TAIKO_A_CDC_SPKR_CLIPDET_B1_CTL (0x365) +#define TAIKO_A_CDC_SPKR_CLIPDET_B1_CTL__POR (0x00) + +/* SLIMBUS Slave Registers */ +#define TAIKO_SLIM_PGD_PORT_INT_EN0 (0x30) +#define TAIKO_SLIM_PGD_PORT_INT_STATUS_RX_0 (0x34) +#define TAIKO_SLIM_PGD_PORT_INT_STATUS_RX_1 (0x35) +#define TAIKO_SLIM_PGD_PORT_INT_STATUS_TX_0 (0x36) +#define TAIKO_SLIM_PGD_PORT_INT_STATUS_TX_1 (0x37) +#define TAIKO_SLIM_PGD_PORT_INT_CLR_RX_0 (0x38) +#define TAIKO_SLIM_PGD_PORT_INT_CLR_RX_1 (0x39) +#define TAIKO_SLIM_PGD_PORT_INT_CLR_TX_0 (0x3A) +#define TAIKO_SLIM_PGD_PORT_INT_CLR_TX_1 (0x3B) +#define TAIKO_SLIM_PGD_PORT_INT_RX_SOURCE0 (0x60) +#define TAIKO_SLIM_PGD_PORT_INT_TX_SOURCE0 (0x70) + +/* Macros for Packing Register Writes into a U32 */ +#define TAIKO_PACKED_REG_SIZE sizeof(u32) + +#define TAIKO_CODEC_PACK_ENTRY(reg, mask, val) ((val & 0xff)|\ + ((mask & 0xff) << 8)|((reg & 0xffff) << 16)) + +#define TAIKO_CODEC_UNPACK_ENTRY(packed, reg, mask, val) \ + do { \ + ((reg) = ((packed >> 16) & (0xffff))); \ + ((mask) = ((packed >> 8) & (0xff))); \ + ((val) = ((packed) & (0xff))); \ + } while (0); + +#endif diff --git a/original-kernel-headers/linux/mfd/wcd9xxx/wcd9xxx_registers.h b/original-kernel-headers/linux/mfd/wcd9xxx/wcd9xxx_registers.h new file mode 100644 index 0000000..2ccb4bd --- /dev/null +++ b/original-kernel-headers/linux/mfd/wcd9xxx/wcd9xxx_registers.h @@ -0,0 +1,322 @@ +#ifndef WCD9XXX_CODEC_DIGITAL_H + +#define WCD9XXX_CODEC_DIGITAL_H + +#define WCD9XXX_A_CHIP_CTL (0x00) +#define WCD9XXX_A_CHIP_CTL__POR (0x00000000) +#define WCD9XXX_A_CHIP_STATUS (0x01) +#define WCD9XXX_A_CHIP_STATUS__POR (0x00000000) +#define WCD9XXX_A_CHIP_ID_BYTE_0 (0x04) +#define WCD9XXX_A_CHIP_ID_BYTE_0__POR (0x00000000) +#define WCD9XXX_A_CHIP_ID_BYTE_1 (0x05) +#define WCD9XXX_A_CHIP_ID_BYTE_1__POR (0x00000000) +#define WCD9XXX_A_CHIP_ID_BYTE_2 (0x06) +#define WCD9XXX_A_CHIP_ID_BYTE_2__POR (0x00000000) +#define WCD9XXX_A_CHIP_ID_BYTE_3 (0x07) +#define WCD9XXX_A_CHIP_ID_BYTE_3__POR (0x00000001) +#define WCD9XXX_A_CHIP_VERSION (0x08) +#define WCD9XXX_A_CHIP_VERSION__POR (0x00000020) +#define WCD9XXX_A_SB_VERSION (0x09) +#define WCD9XXX_A_SB_VERSION__POR (0x00000010) +#define WCD9XXX_A_SLAVE_ID_1 (0x0C) +#define WCD9XXX_A_SLAVE_ID_1__POR (0x00000077) +#define WCD9XXX_A_SLAVE_ID_2 (0x0D) +#define WCD9XXX_A_SLAVE_ID_2__POR (0x00000066) +#define WCD9XXX_A_SLAVE_ID_3 (0x0E) +#define WCD9XXX_A_SLAVE_ID_3__POR (0x00000055) +#define WCD9XXX_A_CDC_CTL (0x80) +#define WCD9XXX_A_CDC_CTL__POR (0x00000000) +#define WCD9XXX_A_LEAKAGE_CTL (0x88) +#define WCD9XXX_A_LEAKAGE_CTL__POR (0x00000004) +#define WCD9XXX_A_INTR_MODE (0x90) +#define WCD9XXX_A_INTR_MASK0 (0x94) +#define WCD9XXX_A_INTR_STATUS0 (0x98) +#define WCD9XXX_A_INTR_CLEAR0 (0x9C) +#define WCD9XXX_A_INTR_LEVEL0 (0xA0) +#define WCD9XXX_A_INTR_LEVEL1 (0xA1) +#define WCD9XXX_A_INTR_LEVEL2 (0xA2) +#define WCD9XXX_A_RX_HPH_CNP_EN (0x1AB) +#define WCD9XXX_A_RX_HPH_CNP_EN__POR (0x80) +#define WCD9XXX_A_RX_HPH_CNP_EN (0x1AB) +#define WCD9XXX_A_RX_HPH_CNP_EN__POR (0x80) +#define WCD9XXX_A_BIAS_CENTRAL_BG_CTL (0x101) +#define WCD9XXX_A_BIAS_CENTRAL_BG_CTL__POR (0x50) +#define WCD9XXX_A_CLK_BUFF_EN1 (0x108) +#define WCD9XXX_A_CLK_BUFF_EN1__POR (0x04) +#define WCD9XXX_A_CLK_BUFF_EN2 (0x109) +#define WCD9XXX_A_CLK_BUFF_EN2__POR (0x02) +#define WCD9XXX_A_RX_COM_BIAS (0x1A2) +#define WCD9XXX_A_RX_COM_BIAS__POR (0x00) +#define WCD9XXX_A_RC_OSC_FREQ (0x1FA) +#define WCD9XXX_A_RC_OSC_FREQ__POR (0x46) +#define WCD9XXX_A_BIAS_OSC_BG_CTL (0x105) +#define WCD9XXX_A_BIAS_OSC_BG_CTL__POR (0x16) +#define WCD9XXX_A_RC_OSC_TEST (0x1FB) +#define WCD9XXX_A_RC_OSC_TEST__POR (0x0A) +#define WCD9XXX_A_CDC_CLK_MCLK_CTL (0x311) +#define WCD9XXX_A_CDC_CLK_MCLK_CTL__POR (0x00) + +#define WCD9XXX_A_CDC_MBHC_EN_CTL (0x3C0) +#define WCD9XXX_A_CDC_MBHC_EN_CTL__POR (0x00) +#define WCD9XXX_A_CDC_MBHC_FIR_B1_CFG (0x3C1) +#define WCD9XXX_A_CDC_MBHC_FIR_B1_CFG__POR (0x00) +#define WCD9XXX_A_CDC_MBHC_FIR_B2_CFG (0x3C2) +#define WCD9XXX_A_CDC_MBHC_FIR_B2_CFG__POR (0x06) +#define WCD9XXX_A_CDC_MBHC_TIMER_B1_CTL (0x3C3) +#define WCD9XXX_A_CDC_MBHC_TIMER_B1_CTL__POR (0x03) +#define WCD9XXX_A_CDC_MBHC_TIMER_B2_CTL (0x3C4) +#define WCD9XXX_A_CDC_MBHC_TIMER_B2_CTL__POR (0x09) +#define WCD9XXX_A_CDC_MBHC_TIMER_B3_CTL (0x3C5) +#define WCD9XXX_A_CDC_MBHC_TIMER_B3_CTL__POR (0x1E) +#define WCD9XXX_A_CDC_MBHC_TIMER_B4_CTL (0x3C6) +#define WCD9XXX_A_CDC_MBHC_TIMER_B4_CTL__POR (0x45) +#define WCD9XXX_A_CDC_MBHC_TIMER_B5_CTL (0x3C7) +#define WCD9XXX_A_CDC_MBHC_TIMER_B5_CTL__POR (0x04) +#define WCD9XXX_A_CDC_MBHC_TIMER_B6_CTL (0x3C8) +#define WCD9XXX_A_CDC_MBHC_TIMER_B6_CTL__POR (0x78) +#define WCD9XXX_A_CDC_MBHC_B1_STATUS (0x3C9) +#define WCD9XXX_A_CDC_MBHC_B1_STATUS__POR (0x00) +#define WCD9XXX_A_CDC_MBHC_B2_STATUS (0x3CA) +#define WCD9XXX_A_CDC_MBHC_B2_STATUS__POR (0x00) +#define WCD9XXX_A_CDC_MBHC_B3_STATUS (0x3CB) +#define WCD9XXX_A_CDC_MBHC_B3_STATUS__POR (0x00) +#define WCD9XXX_A_CDC_MBHC_B4_STATUS (0x3CC) +#define WCD9XXX_A_CDC_MBHC_B4_STATUS__POR (0x00) +#define WCD9XXX_A_CDC_MBHC_B5_STATUS (0x3CD) +#define WCD9XXX_A_CDC_MBHC_B5_STATUS__POR (0x00) +#define WCD9XXX_A_CDC_MBHC_B1_CTL (0x3CE) +#define WCD9XXX_A_CDC_MBHC_B1_CTL__POR (0xC0) +#define WCD9XXX_A_CDC_MBHC_B2_CTL (0x3CF) +#define WCD9XXX_A_CDC_MBHC_B2_CTL__POR (0x5D) +#define WCD9XXX_A_CDC_MBHC_VOLT_B1_CTL (0x3D0) +#define WCD9XXX_A_CDC_MBHC_VOLT_B1_CTL__POR (0x00) +#define WCD9XXX_A_CDC_MBHC_VOLT_B2_CTL (0x3D1) +#define WCD9XXX_A_CDC_MBHC_VOLT_B2_CTL__POR (0x00) +#define WCD9XXX_A_CDC_MBHC_VOLT_B3_CTL (0x3D2) +#define WCD9XXX_A_CDC_MBHC_VOLT_B3_CTL__POR (0x00) +#define WCD9XXX_A_CDC_MBHC_VOLT_B4_CTL (0x3D3) +#define WCD9XXX_A_CDC_MBHC_VOLT_B4_CTL__POR (0x00) +#define WCD9XXX_A_CDC_MBHC_VOLT_B5_CTL (0x3D4) +#define WCD9XXX_A_CDC_MBHC_VOLT_B5_CTL__POR (0x00) +#define WCD9XXX_A_CDC_MBHC_VOLT_B6_CTL (0x3D5) +#define WCD9XXX_A_CDC_MBHC_VOLT_B6_CTL__POR (0x00) +#define WCD9XXX_A_CDC_MBHC_VOLT_B7_CTL (0x3D6) +#define WCD9XXX_A_CDC_MBHC_VOLT_B7_CTL__POR (0xFF) +#define WCD9XXX_A_CDC_MBHC_VOLT_B8_CTL (0x3D7) +#define WCD9XXX_A_CDC_MBHC_VOLT_B8_CTL__POR (0x07) +#define WCD9XXX_A_CDC_MBHC_VOLT_B9_CTL (0x3D8) +#define WCD9XXX_A_CDC_MBHC_VOLT_B9_CTL__POR (0xFF) +#define WCD9XXX_A_CDC_MBHC_VOLT_B10_CTL (0x3D9) +#define WCD9XXX_A_CDC_MBHC_VOLT_B10_CTL__POR (0x7F) +#define WCD9XXX_A_CDC_MBHC_VOLT_B11_CTL (0x3DA) +#define WCD9XXX_A_CDC_MBHC_VOLT_B11_CTL__POR (0x00) +#define WCD9XXX_A_CDC_MBHC_VOLT_B12_CTL (0x3DB) +#define WCD9XXX_A_CDC_MBHC_VOLT_B12_CTL__POR (0x80) +#define WCD9XXX_A_CDC_MBHC_CLK_CTL (0x3DC) +#define WCD9XXX_A_CDC_MBHC_CLK_CTL__POR (0x00) +#define WCD9XXX_A_CDC_MBHC_INT_CTL (0x3DD) +#define WCD9XXX_A_CDC_MBHC_INT_CTL__POR (0x00) +#define WCD9XXX_A_CDC_MBHC_DEBUG_CTL (0x3DE) +#define WCD9XXX_A_CDC_MBHC_DEBUG_CTL__POR (0x00) +#define WCD9XXX_A_CDC_MBHC_SPARE (0x3DF) +#define WCD9XXX_A_CDC_MBHC_SPARE__POR (0x00) +#define WCD9XXX_A_MBHC_SCALING_MUX_1 (0x14E) +#define WCD9XXX_A_MBHC_SCALING_MUX_1__POR (0x00) +#define WCD9XXX_A_RX_HPH_OCP_CTL (0x1AA) +#define WCD9XXX_A_RX_HPH_OCP_CTL__POR (0x68) +#define WCD9XXX_A_MICB_1_CTL (0x12B) +#define WCD9XXX_A_MICB_1_CTL__POR (0x16) +#define WCD9XXX_A_MICB_1_INT_RBIAS (0x12C) +#define WCD9XXX_A_MICB_1_INT_RBIAS__POR (0x24) +#define WCD9XXX_A_MICB_1_MBHC (0x12D) +#define WCD9XXX_A_MICB_1_MBHC__POR (0x01) +#define WCD9XXX_A_MICB_CFILT_2_CTL (0x12E) +#define WCD9XXX_A_MICB_CFILT_2_CTL__POR (0x40) +#define WCD9XXX_A_MICB_CFILT_2_VAL (0x12F) +#define WCD9XXX_A_MICB_CFILT_2_VAL__POR (0x80) +#define WCD9XXX_A_MICB_CFILT_2_PRECHRG (0x130) +#define WCD9XXX_A_MICB_CFILT_2_PRECHRG__POR (0x38) +#define WCD9XXX_A_MICB_2_CTL (0x131) +#define WCD9XXX_A_MICB_2_CTL__POR (0x16) +#define WCD9XXX_A_MICB_2_INT_RBIAS (0x132) +#define WCD9XXX_A_MICB_2_INT_RBIAS__POR (0x24) +#define WCD9XXX_A_MICB_2_MBHC (0x133) +#define WCD9XXX_A_MICB_2_MBHC__POR (0x02) +#define WCD9XXX_A_MICB_CFILT_3_CTL (0x134) +#define WCD9XXX_A_MICB_CFILT_3_CTL__POR (0x40) +#define WCD9XXX_A_MICB_CFILT_3_VAL (0x135) +#define WCD9XXX_A_MICB_CFILT_3_VAL__POR (0x80) +#define WCD9XXX_A_MICB_CFILT_3_PRECHRG (0x136) +#define WCD9XXX_A_MICB_CFILT_3_PRECHRG__POR (0x38) +#define WCD9XXX_A_MICB_3_CTL (0x137) +#define WCD9XXX_A_MICB_3_CTL__POR (0x16) +#define WCD9XXX_A_MICB_3_INT_RBIAS (0x138) +#define WCD9XXX_A_MICB_3_INT_RBIAS__POR (0x24) +#define WCD9XXX_A_MICB_3_MBHC (0x139) +#define WCD9XXX_A_MICB_3_MBHC__POR (0x00) +#define WCD9XXX_A_MICB_4_CTL (0x13D) +#define WCD9XXX_A_MICB_4_CTL__POR (0x16) +#define WCD9XXX_A_MICB_4_INT_RBIAS (0x13E) +#define WCD9XXX_A_MICB_4_INT_RBIAS__POR (0x24) +#define WCD9XXX_A_MICB_4_MBHC (0x13F) +#define WCD9XXX_A_MICB_4_MBHC__POR (0x01) +#define WCD9XXX_A_MICB_CFILT_1_VAL (0x129) +#define WCD9XXX_A_MICB_CFILT_1_VAL__POR (0x80) +#define WCD9XXX_A_RX_HPH_L_STATUS (0x1B3) +#define WCD9XXX_A_RX_HPH_L_STATUS__POR (0x00) +#define WCD9XXX_A_MBHC_HPH (0x1FE) +#define WCD9XXX_A_MBHC_HPH__POR (0x44) +#define WCD9XXX_A_RX_HPH_CNP_WG_TIME (0x1AD) +#define WCD9XXX_A_RX_HPH_CNP_WG_TIME__POR (0x2A) +#define WCD9XXX_A_RX_HPH_R_DAC_CTL (0x1B7) +#define WCD9XXX_A_RX_HPH_R_DAC_CTL__POR (0x00) +#define WCD9XXX_A_RX_HPH_L_DAC_CTL (0x1B1) +#define WCD9XXX_A_RX_HPH_L_DAC_CTL__POR (0x00) +#define WCD9XXX_A_TX_7_MBHC_EN (0x171) +#define WCD9XXX_A_TX_7_MBHC_EN__POR (0x0C) +#define WCD9XXX_A_PIN_CTL_OE0 (0x010) +#define WCD9XXX_A_PIN_CTL_OE0__POR (0x00) +#define WCD9XXX_A_PIN_CTL_OE1 (0x011) +#define WCD9XXX_A_PIN_CTL_OE1__POR (0x00) +#define WCD9XXX_A_MICB_CFILT_1_CTL (0x128) +#define WCD9XXX_A_LDO_H_MODE_1 (0x110) +#define WCD9XXX_A_LDO_H_MODE_1__POR (0x65) +#define WCD9XXX_A_MICB_CFILT_1_CTL__POR (0x40) +#define WCD9XXX_A_TX_7_MBHC_TEST_CTL (0x174) +#define WCD9XXX_A_TX_7_MBHC_TEST_CTL__POR (0x38) +#define WCD9XXX_A_MBHC_SCALING_MUX_2 (0x14F) +#define WCD9XXX_A_MBHC_SCALING_MUX_2__POR (0x80) +#define WCD9XXX_A_TX_COM_BIAS (0x14C) +#define WCD9XXX_A_TX_COM_BIAS__POR (0xF0) + +#define WCD9XXX_A_MBHC_INSERT_DETECT (0x14A) /* TAIKO and later */ +#define WCD9XXX_A_MBHC_INSERT_DETECT__POR (0x00) +#define WCD9XXX_A_MBHC_INSERT_DET_STATUS (0x14B) /* TAIKO and later */ +#define WCD9XXX_A_MBHC_INSERT_DET_STATUS__POR (0x00) +#define WCD9XXX_A_MAD_ANA_CTRL (0x150) +#define WCD9XXX_A_MAD_ANA_CTRL__POR (0xF1) + + +#define WCD9XXX_A_CDC_CLK_OTHR_CTL (0x30C) +#define WCD9XXX_A_CDC_CLK_OTHR_CTL__POR (0x00) + +/* Class H related common registers */ +#define WCD9XXX_A_BUCK_MODE_1 (0x181) +#define WCD9XXX_A_BUCK_MODE_1__POR (0x21) +#define WCD9XXX_A_BUCK_MODE_2 (0x182) +#define WCD9XXX_A_BUCK_MODE_2__POR (0xFF) +#define WCD9XXX_A_BUCK_MODE_3 (0x183) +#define WCD9XXX_A_BUCK_MODE_3__POR (0xCC) +#define WCD9XXX_A_BUCK_MODE_4 (0x184) +#define WCD9XXX_A_BUCK_MODE_4__POR (0x3A) +#define WCD9XXX_A_BUCK_MODE_5 (0x185) +#define WCD9XXX_A_BUCK_MODE_5__POR (0x00) +#define WCD9XXX_A_BUCK_CTRL_VCL_1 (0x186) +#define WCD9XXX_A_BUCK_CTRL_VCL_1__POR (0x48) +#define WCD9XXX_A_BUCK_CTRL_VCL_2 (0x187) +#define WCD9XXX_A_BUCK_CTRL_VCL_2__POR (0xA3) +#define WCD9XXX_A_BUCK_CTRL_VCL_3 (0x188) +#define WCD9XXX_A_BUCK_CTRL_VCL_3__POR (0x82) +#define WCD9XXX_A_BUCK_CTRL_CCL_1 (0x189) +#define WCD9XXX_A_BUCK_CTRL_CCL_1__POR (0xAB) +#define WCD9XXX_A_BUCK_CTRL_CCL_2 (0x18A) +#define WCD9XXX_A_BUCK_CTRL_CCL_2__POR (0xDC) +#define WCD9XXX_A_BUCK_CTRL_CCL_3 (0x18B) +#define WCD9XXX_A_BUCK_CTRL_CCL_3__POR (0x6A) +#define WCD9XXX_A_BUCK_CTRL_CCL_4 (0x18C) +#define WCD9XXX_A_BUCK_CTRL_CCL_4__POR (0x58) +#define WCD9XXX_A_BUCK_CTRL_PWM_DRVR_1 (0x18D) +#define WCD9XXX_A_BUCK_CTRL_PWM_DRVR_1__POR (0x50) +#define WCD9XXX_A_BUCK_CTRL_PWM_DRVR_2 (0x18E) +#define WCD9XXX_A_BUCK_CTRL_PWM_DRVR_2__POR (0x64) +#define WCD9XXX_A_BUCK_CTRL_PWM_DRVR_3 (0x18F) +#define WCD9XXX_A_BUCK_CTRL_PWM_DRVR_3__POR (0x77) +#define WCD9XXX_A_BUCK_TMUX_A_D (0x190) +#define WCD9XXX_A_BUCK_TMUX_A_D__POR (0x00) +#define WCD9XXX_A_NCP_EN (0x192) +#define WCD9XXX_A_NCP_EN__POR (0xFE) +#define WCD9XXX_A_NCP_STATIC (0x194) +#define WCD9XXX_A_NCP_STATIC__POR (0x28) +#define WCD9XXX_A_NCP_BUCKREF (0x191) +#define WCD9XXX_A_NCP_BUCKREF__POR (0x00) +#define WCD9XXX_A_CDC_CLSH_B1_CTL (0x320) +#define WCD9XXX_A_CDC_CLSH_B1_CTL__POR (0xE4) +#define WCD9XXX_A_CDC_CLSH_B2_CTL (0x321) +#define WCD9XXX_A_CDC_CLSH_B2_CTL__POR (0x00) +#define WCD9XXX_A_CDC_CLSH_B3_CTL (0x322) +#define WCD9XXX_A_CDC_CLSH_B3_CTL__POR (0x00) +#define WCD9XXX_A_CDC_CLSH_BUCK_NCP_VARS (0x323) +#define WCD9XXX_A_CDC_CLSH_BUCK_NCP_VARS__POR (0x00) +#define WCD9XXX_A_CDC_CLSH_IDLE_HPH_THSD (0x324) +#define WCD9XXX_A_CDC_CLSH_IDLE_HPH_THSD__POR (0x12) +#define WCD9XXX_A_CDC_CLSH_IDLE_EAR_THSD (0x325) +#define WCD9XXX_A_CDC_CLSH_IDLE_EAR_THSD__POR (0x0C) +#define WCD9XXX_A_CDC_CLSH_FCLKONLY_HPH_THSD (0x326) +#define WCD9XXX_A_CDC_CLSH_FCLKONLY_HPH_THSD__POR (0x18) +#define WCD9XXX_A_CDC_CLSH_FCLKONLY_EAR_THSD (0x327) +#define WCD9XXX_A_CDC_CLSH_FCLKONLY_EAR_THSD__POR (0x23) +#define WCD9XXX_A_CDC_CLSH_K_ADDR (0x328) +#define WCD9XXX_A_CDC_CLSH_K_ADDR__POR (0x00) +#define WCD9XXX_A_CDC_CLSH_K_DATA (0x329) +#define WCD9XXX_A_CDC_CLSH_K_DATA__POR (0xA4) +#define WCD9XXX_A_CDC_CLSH_I_PA_FACT_HPH_L (0x32A) +#define WCD9XXX_A_CDC_CLSH_I_PA_FACT_HPH_L__POR (0xD7) +#define WCD9XXX_A_CDC_CLSH_I_PA_FACT_HPH_U (0x32B) +#define WCD9XXX_A_CDC_CLSH_I_PA_FACT_HPH_U__POR (0x05) +#define WCD9XXX_A_CDC_CLSH_I_PA_FACT_EAR_L (0x32C) +#define WCD9XXX_A_CDC_CLSH_I_PA_FACT_EAR_L__POR (0x60) +#define WCD9XXX_A_CDC_CLSH_I_PA_FACT_EAR_U (0x32D) +#define WCD9XXX_A_CDC_CLSH_I_PA_FACT_EAR_U__POR (0x09) +#define WCD9XXX_A_CDC_CLSH_V_PA_HD_EAR (0x32E) +#define WCD9XXX_A_CDC_CLSH_V_PA_HD_EAR__POR (0x00) +#define WCD9XXX_A_CDC_CLSH_V_PA_HD_HPH (0x32F) +#define WCD9XXX_A_CDC_CLSH_V_PA_HD_HPH__POR (0x00) +#define WCD9XXX_A_CDC_CLSH_V_PA_MIN_EAR (0x330) +#define WCD9XXX_A_CDC_CLSH_V_PA_MIN_EAR__POR (0x00) +#define WCD9XXX_A_CDC_CLSH_V_PA_MIN_HPH (0x331) +#define WCD9XXX_A_CDC_CLSH_V_PA_MIN_HPH__POR (0x00) + +#define WCD9XXX_A_CDC_RX1_B6_CTL (0x2B5) +#define WCD9XXX_A_CDC_RX1_B6_CTL__POR (0x80) +#define WCD9XXX_A_CDC_RX2_B6_CTL (0x2BD) +#define WCD9XXX_A_CDC_RX2_B6_CTL__POR (0x80) +#define WCD9XXX_A_RX_HPH_L_GAIN (0x1AE) +#define WCD9XXX_A_RX_HPH_L_GAIN__POR (0x00) +#define WCD9XXX_A_RX_HPH_R_GAIN (0x1B4) +#define WCD9XXX_A_RX_HPH_R_GAIN__POR (0x00) +#define WCD9XXX_A_RX_HPH_CHOP_CTL (0x1A5) +#define WCD9XXX_A_RX_HPH_CHOP_CTL__POR (0xB4) +#define WCD9XXX_A_RX_HPH_BIAS_PA (0x1A6) +#define WCD9XXX_A_RX_HPH_BIAS_PA__POR (0x7A) +#define WCD9XXX_A_RX_HPH_L_TEST (0x1AF) +#define WCD9XXX_A_RX_HPH_L_TEST__POR (0x00) +#define WCD9XXX_A_RX_HPH_R_TEST (0x1B5) +#define WCD9XXX_A_RX_HPH_R_TEST__POR (0x00) +#define WCD9XXX_A_CDC_CLK_RX_B1_CTL (0x30F) +#define WCD9XXX_A_CDC_CLK_RX_B1_CTL__POR (0x00) +#define WCD9XXX_A_NCP_CLK (0x193) +#define WCD9XXX_A_NCP_CLK__POR (0x94) +#define WCD9XXX_A_RX_HPH_BIAS_WG_OCP (0x1A9) +#define WCD9XXX_A_RX_HPH_BIAS_WG_OCP__POR (0x2A) +#define WCD9XXX_A_RX_HPH_CNP_WG_CTL (0x1AC) +#define WCD9XXX_A_RX_HPH_CNP_WG_CTL__POR (0xDE) +#define WCD9XXX_A_RX_HPH_L_PA_CTL (0x1B0) +#define WCD9XXX_A_RX_HPH_L_PA_CTL__POR (0x42) +#define WCD9XXX_A_RX_HPH_R_PA_CTL (0x1B6) +#define WCD9XXX_A_RX_HPH_R_PA_CTL__POR (0x42) +#define WCD9XXX_A_CDC_CONN_RX2_B1_CTL (0x383) +#define WCD9XXX_A_CDC_CONN_RX2_B1_CTL__POR (0x00) +#define WCD9XXX_A_CDC_PA_RAMP_B1_CTL (0x361) +#define WCD9XXX_A_CDC_PA_RAMP_B1_CTL__POR (0x00) +#define WCD9XXX_A_CDC_PA_RAMP_B2_CTL (0x362) +#define WCD9XXX_A_CDC_PA_RAMP_B2_CTL__POR (0x00) +#define WCD9XXX_A_CDC_PA_RAMP_B3_CTL (0x363) +#define WCD9XXX_A_CDC_PA_RAMP_B3_CTL__POR (0x00) +#define WCD9XXX_A_CDC_PA_RAMP_B4_CTL (0x364) +#define WCD9XXX_A_CDC_PA_RAMP_B4_CTL__POR (0x00) + +#define WCD9330_A_LEAKAGE_CTL (0x03C) +#define WCD9330_A_LEAKAGE_CTL__POR (0x04) +#define WCD9330_A_CDC_CTL (0x034) +#define WCD9330_A_CDC_CTL__POR (0x00) +#endif diff --git a/original-kernel-headers/linux/msm_adsp.h b/original-kernel-headers/linux/msm_adsp.h new file mode 100644 index 0000000..65c31ac --- /dev/null +++ b/original-kernel-headers/linux/msm_adsp.h @@ -0,0 +1,77 @@ +/* + * Copyright (C) 2007 Google, Inc. + * Author: Iliyan Malchev <ibm@android.com> + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ +#ifndef _UAPI_LINUX_MSM_ADSP_H +#define _UAPI_LINUX_MSM_ADSP_H + +#include <linux/types.h> +#include <linux/ioctl.h> + +#define ADSP_IOCTL_MAGIC 'q' + +/* ADSP_IOCTL_WRITE_COMMAND */ +struct adsp_command_t { + uint16_t queue; + uint32_t len; /* bytes */ + uint8_t *data; +}; + +/* ADSP_IOCTL_GET_EVENT */ +struct adsp_event_t { + uint16_t type; /* 1 == event (RPC), 0 == message (adsp) */ + uint32_t timeout_ms; /* -1 for infinite, 0 for immediate return */ + uint16_t msg_id; + uint16_t flags; /* 1 == 16--bit event, 0 == 32-bit event */ + uint32_t len; /* size in, number of bytes out */ + uint8_t *data; +}; + +#define ADSP_IOCTL_ENABLE \ + _IOR(ADSP_IOCTL_MAGIC, 1, unsigned) + +#define ADSP_IOCTL_DISABLE \ + _IOR(ADSP_IOCTL_MAGIC, 2, unsigned) + +#define ADSP_IOCTL_DISABLE_ACK \ + _IOR(ADSP_IOCTL_MAGIC, 3, unsigned) + +#define ADSP_IOCTL_WRITE_COMMAND \ + _IOR(ADSP_IOCTL_MAGIC, 4, struct adsp_command_t *) + +#define ADSP_IOCTL_GET_EVENT \ + _IOWR(ADSP_IOCTL_MAGIC, 5, struct adsp_event_data_t *) + +#define ADSP_IOCTL_SET_CLKRATE \ + _IOR(ADSP_IOCTL_MAGIC, 6, unsigned) + +#define ADSP_IOCTL_DISABLE_EVENT_RSP \ + _IOR(ADSP_IOCTL_MAGIC, 10, unsigned) + +#define ADSP_IOCTL_REGISTER_PMEM \ + _IOW(ADSP_IOCTL_MAGIC, 13, unsigned) + +#define ADSP_IOCTL_UNREGISTER_PMEM \ + _IOW(ADSP_IOCTL_MAGIC, 14, unsigned) + +/* Cause any further GET_EVENT ioctls to fail (-ENODEV) + * until the device is closed and reopened. Useful for + * terminating event dispatch threads + */ +#define ADSP_IOCTL_ABORT_EVENT_READ \ + _IOW(ADSP_IOCTL_MAGIC, 15, unsigned) + +#define ADSP_IOCTL_LINK_TASK \ + _IOW(ADSP_IOCTL_MAGIC, 16, unsigned) + +#endif diff --git a/original-kernel-headers/linux/msm_audio.h b/original-kernel-headers/linux/msm_audio.h new file mode 100644 index 0000000..5005cd5 --- /dev/null +++ b/original-kernel-headers/linux/msm_audio.h @@ -0,0 +1,460 @@ +/* include/linux/msm_audio.h + * + * Copyright (C) 2008 Google, Inc. + * Copyright (c) 2012, 2014 The Linux Foundation. All rights reserved. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef _UAPI_LINUX_MSM_AUDIO_H +#define _UAPI_LINUX_MSM_AUDIO_H + +#include <linux/types.h> +#include <linux/ioctl.h> + +/* PCM Audio */ + +#define AUDIO_IOCTL_MAGIC 'a' + +#define AUDIO_START _IOW(AUDIO_IOCTL_MAGIC, 0, unsigned) +#define AUDIO_STOP _IOW(AUDIO_IOCTL_MAGIC, 1, unsigned) +#define AUDIO_FLUSH _IOW(AUDIO_IOCTL_MAGIC, 2, unsigned) +#define AUDIO_GET_CONFIG _IOR(AUDIO_IOCTL_MAGIC, 3, \ + struct msm_audio_config) +#define AUDIO_SET_CONFIG _IOW(AUDIO_IOCTL_MAGIC, 4, \ + struct msm_audio_config) +#define AUDIO_GET_STATS _IOR(AUDIO_IOCTL_MAGIC, 5, \ + struct msm_audio_stats) +#define AUDIO_ENABLE_AUDPP _IOW(AUDIO_IOCTL_MAGIC, 6, unsigned) +#define AUDIO_SET_ADRC _IOW(AUDIO_IOCTL_MAGIC, 7, unsigned) +#define AUDIO_SET_EQ _IOW(AUDIO_IOCTL_MAGIC, 8, unsigned) +#define AUDIO_SET_RX_IIR _IOW(AUDIO_IOCTL_MAGIC, 9, unsigned) +#define AUDIO_SET_VOLUME _IOW(AUDIO_IOCTL_MAGIC, 10, unsigned) +#define AUDIO_PAUSE _IOW(AUDIO_IOCTL_MAGIC, 11, unsigned) +#define AUDIO_PLAY_DTMF _IOW(AUDIO_IOCTL_MAGIC, 12, unsigned) +#define AUDIO_GET_EVENT _IOR(AUDIO_IOCTL_MAGIC, 13, \ + struct msm_audio_event) +#define AUDIO_ABORT_GET_EVENT _IOW(AUDIO_IOCTL_MAGIC, 14, unsigned) +#define AUDIO_REGISTER_PMEM _IOW(AUDIO_IOCTL_MAGIC, 15, unsigned) +#define AUDIO_DEREGISTER_PMEM _IOW(AUDIO_IOCTL_MAGIC, 16, unsigned) +#define AUDIO_ASYNC_WRITE _IOW(AUDIO_IOCTL_MAGIC, 17, \ + struct msm_audio_aio_buf) +#define AUDIO_ASYNC_READ _IOW(AUDIO_IOCTL_MAGIC, 18, \ + struct msm_audio_aio_buf) +#define AUDIO_SET_INCALL _IOW(AUDIO_IOCTL_MAGIC, 19, struct msm_voicerec_mode) +#define AUDIO_GET_NUM_SND_DEVICE _IOR(AUDIO_IOCTL_MAGIC, 20, unsigned) +#define AUDIO_GET_SND_DEVICES _IOWR(AUDIO_IOCTL_MAGIC, 21, \ + struct msm_snd_device_list) +#define AUDIO_ENABLE_SND_DEVICE _IOW(AUDIO_IOCTL_MAGIC, 22, unsigned) +#define AUDIO_DISABLE_SND_DEVICE _IOW(AUDIO_IOCTL_MAGIC, 23, unsigned) +#define AUDIO_ROUTE_STREAM _IOW(AUDIO_IOCTL_MAGIC, 24, \ + struct msm_audio_route_config) +#define AUDIO_GET_PCM_CONFIG _IOR(AUDIO_IOCTL_MAGIC, 30, unsigned) +#define AUDIO_SET_PCM_CONFIG _IOW(AUDIO_IOCTL_MAGIC, 31, unsigned) +#define AUDIO_SWITCH_DEVICE _IOW(AUDIO_IOCTL_MAGIC, 32, unsigned) +#define AUDIO_SET_MUTE _IOW(AUDIO_IOCTL_MAGIC, 33, unsigned) +#define AUDIO_UPDATE_ACDB _IOW(AUDIO_IOCTL_MAGIC, 34, unsigned) +#define AUDIO_START_VOICE _IOW(AUDIO_IOCTL_MAGIC, 35, unsigned) +#define AUDIO_STOP_VOICE _IOW(AUDIO_IOCTL_MAGIC, 36, unsigned) +#define AUDIO_REINIT_ACDB _IOW(AUDIO_IOCTL_MAGIC, 39, unsigned) +#define AUDIO_OUTPORT_FLUSH _IOW(AUDIO_IOCTL_MAGIC, 40, unsigned short) +#define AUDIO_SET_ERR_THRESHOLD_VALUE _IOW(AUDIO_IOCTL_MAGIC, 41, \ + unsigned short) +#define AUDIO_GET_BITSTREAM_ERROR_INFO _IOR(AUDIO_IOCTL_MAGIC, 42, \ + struct msm_audio_bitstream_error_info) + +#define AUDIO_SET_SRS_TRUMEDIA_PARAM _IOW(AUDIO_IOCTL_MAGIC, 43, unsigned) + +/* Qualcomm extensions */ +#define AUDIO_SET_STREAM_CONFIG _IOW(AUDIO_IOCTL_MAGIC, 80, \ + struct msm_audio_stream_config) +#define AUDIO_GET_STREAM_CONFIG _IOR(AUDIO_IOCTL_MAGIC, 81, \ + struct msm_audio_stream_config) +#define AUDIO_GET_SESSION_ID _IOR(AUDIO_IOCTL_MAGIC, 82, unsigned short) +#define AUDIO_GET_STREAM_INFO _IOR(AUDIO_IOCTL_MAGIC, 83, \ + struct msm_audio_bitstream_info) +#define AUDIO_SET_PAN _IOW(AUDIO_IOCTL_MAGIC, 84, unsigned) +#define AUDIO_SET_QCONCERT_PLUS _IOW(AUDIO_IOCTL_MAGIC, 85, unsigned) +#define AUDIO_SET_MBADRC _IOW(AUDIO_IOCTL_MAGIC, 86, unsigned) +#define AUDIO_SET_VOLUME_PATH _IOW(AUDIO_IOCTL_MAGIC, 87, \ + struct msm_vol_info) +#define AUDIO_SET_MAX_VOL_ALL _IOW(AUDIO_IOCTL_MAGIC, 88, unsigned) +#define AUDIO_ENABLE_AUDPRE _IOW(AUDIO_IOCTL_MAGIC, 89, unsigned) +#define AUDIO_SET_AGC _IOW(AUDIO_IOCTL_MAGIC, 90, unsigned) +#define AUDIO_SET_NS _IOW(AUDIO_IOCTL_MAGIC, 91, unsigned) +#define AUDIO_SET_TX_IIR _IOW(AUDIO_IOCTL_MAGIC, 92, unsigned) +#define AUDIO_GET_BUF_CFG _IOW(AUDIO_IOCTL_MAGIC, 93, \ + struct msm_audio_buf_cfg) +#define AUDIO_SET_BUF_CFG _IOW(AUDIO_IOCTL_MAGIC, 94, \ + struct msm_audio_buf_cfg) +#define AUDIO_SET_ACDB_BLK _IOW(AUDIO_IOCTL_MAGIC, 95, \ + struct msm_acdb_cmd_device) +#define AUDIO_GET_ACDB_BLK _IOW(AUDIO_IOCTL_MAGIC, 96, \ + struct msm_acdb_cmd_device) + +#define AUDIO_REGISTER_ION _IOW(AUDIO_IOCTL_MAGIC, 97, \ + struct msm_audio_ion_info) +#define AUDIO_DEREGISTER_ION _IOW(AUDIO_IOCTL_MAGIC, 98, \ + struct msm_audio_ion_info) +#define AUDIO_SET_EFFECTS_CONFIG _IOW(AUDIO_IOCTL_MAGIC, 99, \ + struct msm_hwacc_effects_config) +#define AUDIO_EFFECTS_SET_BUF_LEN _IOW(AUDIO_IOCTL_MAGIC, 100, \ + struct msm_hwacc_buf_cfg) +#define AUDIO_EFFECTS_GET_BUF_AVAIL _IOW(AUDIO_IOCTL_MAGIC, 101, \ + struct msm_hwacc_buf_avail) +#define AUDIO_EFFECTS_WRITE _IOW(AUDIO_IOCTL_MAGIC, 102, void *) +#define AUDIO_EFFECTS_READ _IOWR(AUDIO_IOCTL_MAGIC, 103, void *) +#define AUDIO_EFFECTS_SET_PP_PARAMS _IOW(AUDIO_IOCTL_MAGIC, 104, void *) + +#define AUDIO_MAX_COMMON_IOCTL_NUM 105 + + +#define HANDSET_MIC 0x01 +#define HANDSET_SPKR 0x02 +#define HEADSET_MIC 0x03 +#define HEADSET_SPKR_MONO 0x04 +#define HEADSET_SPKR_STEREO 0x05 +#define SPKR_PHONE_MIC 0x06 +#define SPKR_PHONE_MONO 0x07 +#define SPKR_PHONE_STEREO 0x08 +#define BT_SCO_MIC 0x09 +#define BT_SCO_SPKR 0x0A +#define BT_A2DP_SPKR 0x0B +#define TTY_HEADSET_MIC 0x0C +#define TTY_HEADSET_SPKR 0x0D + +/* Default devices are not supported in a */ +/* device switching context. Only supported */ +/* for stream devices. */ +/* DO NOT USE */ +#define DEFAULT_TX 0x0E +#define DEFAULT_RX 0x0F + +#define BT_A2DP_TX 0x10 + +#define HEADSET_MONO_PLUS_SPKR_MONO_RX 0x11 +#define HEADSET_MONO_PLUS_SPKR_STEREO_RX 0x12 +#define HEADSET_STEREO_PLUS_SPKR_MONO_RX 0x13 +#define HEADSET_STEREO_PLUS_SPKR_STEREO_RX 0x14 + +#define I2S_RX 0x20 +#define I2S_TX 0x21 + +#define ADRC_ENABLE 0x0001 +#define EQUALIZER_ENABLE 0x0002 +#define IIR_ENABLE 0x0004 +#define QCONCERT_PLUS_ENABLE 0x0008 +#define MBADRC_ENABLE 0x0010 +#define SRS_ENABLE 0x0020 +#define SRS_DISABLE 0x0040 + +#define AGC_ENABLE 0x0001 +#define NS_ENABLE 0x0002 +#define TX_IIR_ENABLE 0x0004 +#define FLUENCE_ENABLE 0x0008 + +#define VOC_REC_UPLINK 0x00 +#define VOC_REC_DOWNLINK 0x01 +#define VOC_REC_BOTH 0x02 + +struct msm_audio_config { + uint32_t buffer_size; + uint32_t buffer_count; + uint32_t channel_count; + uint32_t sample_rate; + uint32_t type; + uint32_t meta_field; + uint32_t bits; + uint32_t unused[3]; +}; + +struct msm_audio_stream_config { + uint32_t buffer_size; + uint32_t buffer_count; +}; + +struct msm_audio_buf_cfg{ + uint32_t meta_info_enable; + uint32_t frames_per_buf; +}; + +struct msm_audio_stats { + uint32_t byte_count; + uint32_t sample_count; + uint32_t unused[2]; +}; + +struct msm_audio_ion_info { + int fd; + void *vaddr; +}; + +struct msm_audio_pmem_info { + int fd; + void *vaddr; +}; + +struct msm_audio_aio_buf { + void *buf_addr; + uint32_t buf_len; + uint32_t data_len; + void *private_data; + unsigned short mfield_sz; /*only useful for data has meta field */ +}; + +/* Audio routing */ + +#define SND_IOCTL_MAGIC 's' + +#define SND_MUTE_UNMUTED 0 +#define SND_MUTE_MUTED 1 + +struct msm_mute_info { + uint32_t mute; + uint32_t path; +}; + +struct msm_vol_info { + uint32_t vol; + uint32_t path; +}; + +struct msm_voicerec_mode { + uint32_t rec_mode; +}; + +struct msm_snd_device_config { + uint32_t device; + uint32_t ear_mute; + uint32_t mic_mute; +}; + +#define SND_SET_DEVICE _IOW(SND_IOCTL_MAGIC, 2, struct msm_device_config *) + +enum cad_device_path_type { + CAD_DEVICE_PATH_RX, /*For Decoding session*/ + CAD_DEVICE_PATH_TX, /* For Encoding session*/ + CAD_DEVICE_PATH_RX_TX, /* For Voice call */ + CAD_DEVICE_PATH_LB, /* For loopback (FM Analog)*/ + CAD_DEVICE_PATH_MAX +}; + +struct cad_devices_type { + uint32_t rx_device; + uint32_t tx_device; + enum cad_device_path_type pathtype; +}; + +struct msm_cad_device_config { + struct cad_devices_type device; + uint32_t ear_mute; + uint32_t mic_mute; +}; + +#define CAD_SET_DEVICE _IOW(SND_IOCTL_MAGIC, 2, struct msm_cad_device_config *) + +#define SND_METHOD_VOICE 0 +#define SND_METHOD_MIDI 4 + +struct msm_snd_volume_config { + uint32_t device; + uint32_t method; + uint32_t volume; +}; + +#define SND_SET_VOLUME _IOW(SND_IOCTL_MAGIC, 3, struct msm_snd_volume_config *) + +struct msm_cad_volume_config { + struct cad_devices_type device; + uint32_t method; + uint32_t volume; +}; + +#define CAD_SET_VOLUME _IOW(SND_IOCTL_MAGIC, 3, struct msm_cad_volume_config *) + +/* Returns the number of SND endpoints supported. */ + +#define SND_GET_NUM_ENDPOINTS _IOR(SND_IOCTL_MAGIC, 4, unsigned *) + +struct msm_snd_endpoint { + int id; /* input and output */ + char name[64]; /* output only */ +}; + +/* Takes an index between 0 and one less than the number returned by + * SND_GET_NUM_ENDPOINTS, and returns the SND index and name of a + * SND endpoint. On input, the .id field contains the number of the + * endpoint, and on exit it contains the SND index, while .name contains + * the description of the endpoint. + */ + +#define SND_GET_ENDPOINT _IOWR(SND_IOCTL_MAGIC, 5, struct msm_snd_endpoint *) + + +#define SND_AVC_CTL _IOW(SND_IOCTL_MAGIC, 6, unsigned *) +#define SND_AGC_CTL _IOW(SND_IOCTL_MAGIC, 7, unsigned *) + +/*return the number of CAD endpoints supported. */ + +#define CAD_GET_NUM_ENDPOINTS _IOR(SND_IOCTL_MAGIC, 4, unsigned *) + +struct msm_cad_endpoint { + int id; /* input and output */ + char name[64]; /* output only */ +}; + +/* Takes an index between 0 and one less than the number returned by + * SND_GET_NUM_ENDPOINTS, and returns the CAD index and name of a + * CAD endpoint. On input, the .id field contains the number of the + * endpoint, and on exit it contains the SND index, while .name contains + * the description of the endpoint. + */ + +#define CAD_GET_ENDPOINT _IOWR(SND_IOCTL_MAGIC, 5, struct msm_cad_endpoint *) + +struct msm_audio_pcm_config { + uint32_t pcm_feedback; /* 0 - disable > 0 - enable */ + uint32_t buffer_count; /* Number of buffers to allocate */ + uint32_t buffer_size; /* Size of buffer for capturing of + PCM samples */ +}; + +#define AUDIO_EVENT_SUSPEND 0 +#define AUDIO_EVENT_RESUME 1 +#define AUDIO_EVENT_WRITE_DONE 2 +#define AUDIO_EVENT_READ_DONE 3 +#define AUDIO_EVENT_STREAM_INFO 4 +#define AUDIO_EVENT_BITSTREAM_ERROR_INFO 5 + +#define AUDIO_CODEC_TYPE_MP3 0 +#define AUDIO_CODEC_TYPE_AAC 1 + +struct msm_audio_bitstream_info { + uint32_t codec_type; + uint32_t chan_info; + uint32_t sample_rate; + uint32_t bit_stream_info; + uint32_t bit_rate; + uint32_t unused[3]; +}; + +struct msm_audio_bitstream_error_info { + uint32_t dec_id; + uint32_t err_msg_indicator; + uint32_t err_type; +}; + +union msm_audio_event_payload { + struct msm_audio_aio_buf aio_buf; + struct msm_audio_bitstream_info stream_info; + struct msm_audio_bitstream_error_info error_info; + int reserved; +}; + +struct msm_audio_event { + int event_type; + int timeout_ms; + union msm_audio_event_payload event_payload; +}; + +#define MSM_SNDDEV_CAP_RX 0x1 +#define MSM_SNDDEV_CAP_TX 0x2 +#define MSM_SNDDEV_CAP_VOICE 0x4 + +struct msm_snd_device_info { + uint32_t dev_id; + uint32_t dev_cap; /* bitmask describe capability of device */ + char dev_name[64]; +}; + +struct msm_snd_device_list { + uint32_t num_dev; /* Indicate number of device info to be retrieved */ + struct msm_snd_device_info *list; +}; + +struct msm_dtmf_config { + uint16_t path; + uint16_t dtmf_hi; + uint16_t dtmf_low; + uint16_t duration; + uint16_t tx_gain; + uint16_t rx_gain; + uint16_t mixing; +}; + +#define AUDIO_ROUTE_STREAM_VOICE_RX 0 +#define AUDIO_ROUTE_STREAM_VOICE_TX 1 +#define AUDIO_ROUTE_STREAM_PLAYBACK 2 +#define AUDIO_ROUTE_STREAM_REC 3 + +struct msm_audio_route_config { + uint32_t stream_type; + uint32_t stream_id; + uint32_t dev_id; +}; + +#define AUDIO_MAX_EQ_BANDS 12 + +struct msm_audio_eq_band { + uint16_t band_idx; /* The band index, 0 .. 11 */ + uint32_t filter_type; /* Filter band type */ + uint32_t center_freq_hz; /* Filter band center frequency */ + uint32_t filter_gain; /* Filter band initial gain (dB) */ + /* Range is +12 dB to -12 dB with 1dB increments. */ + uint32_t q_factor; +} __attribute__ ((packed)); + +struct msm_audio_eq_stream_config { + uint32_t enable; /* Number of consequtive bands specified */ + uint32_t num_bands; + struct msm_audio_eq_band eq_bands[AUDIO_MAX_EQ_BANDS]; +} __attribute__ ((packed)); + +struct msm_acdb_cmd_device { + uint32_t command_id; + uint32_t device_id; + uint32_t network_id; + uint32_t sample_rate_id; /* Actual sample rate value */ + uint32_t interface_id; /* See interface id's above */ + uint32_t algorithm_block_id; /* See enumerations above */ + uint32_t total_bytes; /* Length in bytes used by buffer */ + uint32_t *phys_buf; /* Physical Address of data */ +}; + +struct msm_hwacc_data_config { + __u32 buf_size; + __u32 num_buf; + __u32 num_channels; + __u8 channel_map[8]; + __u32 sample_rate; + __u32 bits_per_sample; +}; + +struct msm_hwacc_buf_cfg { + __u32 input_len; + __u32 output_len; +}; + +struct msm_hwacc_buf_avail { + __u32 input_num_avail; + __u32 output_num_avail; +}; + +struct msm_hwacc_effects_config { + struct msm_hwacc_data_config input; + struct msm_hwacc_data_config output; + struct msm_hwacc_buf_cfg buf_cfg; + __u32 meta_mode_enabled; + __u32 overwrite_topology; + __s32 topology; +}; + +#endif diff --git a/original-kernel-headers/linux/msm_audio_aac.h b/original-kernel-headers/linux/msm_audio_aac.h new file mode 100644 index 0000000..fadeb74 --- /dev/null +++ b/original-kernel-headers/linux/msm_audio_aac.h @@ -0,0 +1,76 @@ +#ifndef _UAPI_MSM_AUDIO_AAC_H +#define _UAPI_MSM_AUDIO_AAC_H + +#include <linux/msm_audio.h> + +#define AUDIO_SET_AAC_CONFIG _IOW(AUDIO_IOCTL_MAGIC, \ + (AUDIO_MAX_COMMON_IOCTL_NUM+0), struct msm_audio_aac_config) +#define AUDIO_GET_AAC_CONFIG _IOR(AUDIO_IOCTL_MAGIC, \ + (AUDIO_MAX_COMMON_IOCTL_NUM+1), struct msm_audio_aac_config) + +#define AUDIO_SET_AAC_ENC_CONFIG _IOW(AUDIO_IOCTL_MAGIC, \ + (AUDIO_MAX_COMMON_IOCTL_NUM+3), struct msm_audio_aac_enc_config) + +#define AUDIO_GET_AAC_ENC_CONFIG _IOR(AUDIO_IOCTL_MAGIC, \ + (AUDIO_MAX_COMMON_IOCTL_NUM+4), struct msm_audio_aac_enc_config) + +#define AUDIO_SET_AAC_MIX_CONFIG _IOR(AUDIO_IOCTL_MAGIC, \ + (AUDIO_MAX_COMMON_IOCTL_NUM+5), uint32_t) + +#define AUDIO_AAC_FORMAT_ADTS -1 +#define AUDIO_AAC_FORMAT_RAW 0x0000 +#define AUDIO_AAC_FORMAT_PSUEDO_RAW 0x0001 +#define AUDIO_AAC_FORMAT_LOAS 0x0002 +#define AUDIO_AAC_FORMAT_ADIF 0x0003 + +#define AUDIO_AAC_OBJECT_LC 0x0002 +#define AUDIO_AAC_OBJECT_LTP 0x0004 +#define AUDIO_AAC_OBJECT_ERLC 0x0011 +#define AUDIO_AAC_OBJECT_BSAC 0x0016 + +#define AUDIO_AAC_SEC_DATA_RES_ON 0x0001 +#define AUDIO_AAC_SEC_DATA_RES_OFF 0x0000 + +#define AUDIO_AAC_SCA_DATA_RES_ON 0x0001 +#define AUDIO_AAC_SCA_DATA_RES_OFF 0x0000 + +#define AUDIO_AAC_SPEC_DATA_RES_ON 0x0001 +#define AUDIO_AAC_SPEC_DATA_RES_OFF 0x0000 + +#define AUDIO_AAC_SBR_ON_FLAG_ON 0x0001 +#define AUDIO_AAC_SBR_ON_FLAG_OFF 0x0000 + +#define AUDIO_AAC_SBR_PS_ON_FLAG_ON 0x0001 +#define AUDIO_AAC_SBR_PS_ON_FLAG_OFF 0x0000 + +/* Primary channel on both left and right channels */ +#define AUDIO_AAC_DUAL_MONO_PL_PR 0 +/* Secondary channel on both left and right channels */ +#define AUDIO_AAC_DUAL_MONO_SL_SR 1 +/* Primary channel on right channel and 2nd on left channel */ +#define AUDIO_AAC_DUAL_MONO_SL_PR 2 +/* 2nd channel on right channel and primary on left channel */ +#define AUDIO_AAC_DUAL_MONO_PL_SR 3 + +struct msm_audio_aac_config { + signed short format; + unsigned short audio_object; + unsigned short ep_config; /* 0 ~ 3 useful only obj = ERLC */ + unsigned short aac_section_data_resilience_flag; + unsigned short aac_scalefactor_data_resilience_flag; + unsigned short aac_spectral_data_resilience_flag; + unsigned short sbr_on_flag; + unsigned short sbr_ps_on_flag; + unsigned short dual_mono_mode; + unsigned short channel_configuration; + unsigned short sample_rate; +}; + +struct msm_audio_aac_enc_config { + uint32_t channels; + uint32_t sample_rate; + uint32_t bit_rate; + uint32_t stream_format; +}; + +#endif /* _UAPI_MSM_AUDIO_AAC_H */ diff --git a/original-kernel-headers/linux/msm_audio_amrwbplus.h b/original-kernel-headers/linux/msm_audio_amrwbplus.h new file mode 100644 index 0000000..ba2d06e --- /dev/null +++ b/original-kernel-headers/linux/msm_audio_amrwbplus.h @@ -0,0 +1,18 @@ +#ifndef _UAPI_MSM_AUDIO_AMR_WB_PLUS_H +#define _UAPI_MSM_AUDIO_AMR_WB_PLUS_H + +#define AUDIO_GET_AMRWBPLUS_CONFIG_V2 _IOR(AUDIO_IOCTL_MAGIC, \ + (AUDIO_MAX_COMMON_IOCTL_NUM+2), struct msm_audio_amrwbplus_config_v2) +#define AUDIO_SET_AMRWBPLUS_CONFIG_V2 _IOW(AUDIO_IOCTL_MAGIC, \ + (AUDIO_MAX_COMMON_IOCTL_NUM+3), struct msm_audio_amrwbplus_config_v2) + +struct msm_audio_amrwbplus_config_v2 { + unsigned int size_bytes; + unsigned int version; + unsigned int num_channels; + unsigned int amr_band_mode; + unsigned int amr_dtx_mode; + unsigned int amr_frame_fmt; + unsigned int amr_lsf_idx; +}; +#endif /* _UAPI_MSM_AUDIO_AMR_WB_PLUS_H */ diff --git a/original-kernel-headers/linux/msm_audio_wma.h b/original-kernel-headers/linux/msm_audio_wma.h new file mode 100644 index 0000000..76dac7b --- /dev/null +++ b/original-kernel-headers/linux/msm_audio_wma.h @@ -0,0 +1,33 @@ +#ifndef _UAPI_MSM_AUDIO_WMA_H +#define _UAPI_MSM_AUDIO_WMA_H + +#define AUDIO_GET_WMA_CONFIG _IOR(AUDIO_IOCTL_MAGIC, \ + (AUDIO_MAX_COMMON_IOCTL_NUM+0), unsigned) +#define AUDIO_SET_WMA_CONFIG _IOW(AUDIO_IOCTL_MAGIC, \ + (AUDIO_MAX_COMMON_IOCTL_NUM+1), unsigned) + +#define AUDIO_GET_WMA_CONFIG_V2 _IOR(AUDIO_IOCTL_MAGIC, \ + (AUDIO_MAX_COMMON_IOCTL_NUM+2), struct msm_audio_wma_config_v2) +#define AUDIO_SET_WMA_CONFIG_V2 _IOW(AUDIO_IOCTL_MAGIC, \ + (AUDIO_MAX_COMMON_IOCTL_NUM+3), struct msm_audio_wma_config_v2) + +struct msm_audio_wma_config { + unsigned short armdatareqthr; + unsigned short channelsdecoded; + unsigned short wmabytespersec; + unsigned short wmasamplingfreq; + unsigned short wmaencoderopts; +}; + +struct msm_audio_wma_config_v2 { + unsigned short format_tag; + unsigned short numchannels; + uint32_t samplingrate; + uint32_t avgbytespersecond; + unsigned short block_align; + unsigned short validbitspersample; + uint32_t channelmask; + unsigned short encodeopt; +}; + +#endif /* _UAPI_MSM_AUDIO_WMA_H */ diff --git a/original-kernel-headers/linux/msm_audio_wmapro.h b/original-kernel-headers/linux/msm_audio_wmapro.h new file mode 100644 index 0000000..195394e --- /dev/null +++ b/original-kernel-headers/linux/msm_audio_wmapro.h @@ -0,0 +1,22 @@ +#ifndef _UAPI_MSM_AUDIO_WMAPRO_H +#define _UAPI_MSM_AUDIO_WMAPRO_H + +#define AUDIO_GET_WMAPRO_CONFIG _IOR(AUDIO_IOCTL_MAGIC, \ + (AUDIO_MAX_COMMON_IOCTL_NUM+0), struct msm_audio_wmapro_config) +#define AUDIO_SET_WMAPRO_CONFIG _IOW(AUDIO_IOCTL_MAGIC, \ + (AUDIO_MAX_COMMON_IOCTL_NUM+1), struct msm_audio_wmapro_config) + +struct msm_audio_wmapro_config { + unsigned short armdatareqthr; + uint8_t validbitspersample; + uint8_t numchannels; + unsigned short formattag; + unsigned short samplingrate; + unsigned short avgbytespersecond; + unsigned short asfpacketlength; + unsigned short channelmask; + unsigned short encodeopt; + unsigned short advancedencodeopt; + uint32_t advancedencodeopt2; +}; +#endif /* _UAPI_MSM_AUDIO_WMAPRO_H */ diff --git a/original-kernel-headers/linux/msm_ion.h b/original-kernel-headers/linux/msm_ion.h new file mode 100644 index 0000000..9c010a6 --- /dev/null +++ b/original-kernel-headers/linux/msm_ion.h @@ -0,0 +1,181 @@ +#ifndef _UAPI_MSM_ION_H +#define _UAPI_MSM_ION_H + +#include "ion.h" + +enum msm_ion_heap_types { + ION_HEAP_TYPE_MSM_START = ION_HEAP_TYPE_CUSTOM + 1, + ION_HEAP_TYPE_SECURE_DMA = ION_HEAP_TYPE_MSM_START, + ION_HEAP_TYPE_REMOVED, + /* + * if you add a heap type here you should also add it to + * heap_types_info[] in msm_ion.c + */ +}; + +/** + * These are the only ids that should be used for Ion heap ids. + * The ids listed are the order in which allocation will be attempted + * if specified. Don't swap the order of heap ids unless you know what + * you are doing! + * Id's are spaced by purpose to allow new Id's to be inserted in-between (for + * possible fallbacks) + */ + +enum ion_heap_ids { + INVALID_HEAP_ID = -1, + ION_CP_MM_HEAP_ID = 8, + ION_CP_MFC_HEAP_ID = 12, + ION_CP_WB_HEAP_ID = 16, /* 8660 only */ + ION_CAMERA_HEAP_ID = 20, /* 8660 only */ + ION_SYSTEM_CONTIG_HEAP_ID = 21, + ION_ADSP_HEAP_ID = 22, + ION_PIL1_HEAP_ID = 23, /* Currently used for other PIL images */ + ION_SF_HEAP_ID = 24, + ION_SYSTEM_HEAP_ID = 25, + ION_PIL2_HEAP_ID = 26, /* Currently used for modem firmware images */ + ION_QSECOM_HEAP_ID = 27, + ION_AUDIO_HEAP_ID = 28, + + ION_MM_FIRMWARE_HEAP_ID = 29, + + ION_HEAP_ID_RESERVED = 31 /** Bit reserved for ION_FLAG_SECURE flag */ +}; + +/* + * The IOMMU heap is deprecated! Here are some aliases for backwards + * compatibility: + */ +#define ION_IOMMU_HEAP_ID ION_SYSTEM_HEAP_ID +#define ION_HEAP_TYPE_IOMMU ION_HEAP_TYPE_SYSTEM + +enum ion_fixed_position { + NOT_FIXED, + FIXED_LOW, + FIXED_MIDDLE, + FIXED_HIGH, +}; + +enum cp_mem_usage { + VIDEO_BITSTREAM = 0x1, + VIDEO_PIXEL = 0x2, + VIDEO_NONPIXEL = 0x3, + DISPLAY_SECURE_CP_USAGE = 0x4, + CAMERA_SECURE_CP_USAGE = 0x5, + MAX_USAGE = 0x6, + UNKNOWN = 0x7FFFFFFF, +}; + +/** + * Flag to allow non continguous allocation of memory from secure + * heap + */ +#define ION_FLAG_ALLOW_NON_CONTIG (1 << 24) + +/** + * Flag to use when allocating to indicate that a heap is secure. + */ +#define ION_FLAG_SECURE (1 << ION_HEAP_ID_RESERVED) + +/** + * Flag for clients to force contiguous memort allocation + * + * Use of this flag is carefully monitored! + */ +#define ION_FLAG_FORCE_CONTIGUOUS (1 << 30) + +/* + * Used in conjunction with heap which pool memory to force an allocation + * to come from the page allocator directly instead of from the pool allocation + */ +#define ION_FLAG_POOL_FORCE_ALLOC (1 << 16) + +/** +* Deprecated! Please use the corresponding ION_FLAG_* +*/ +#define ION_SECURE ION_FLAG_SECURE +#define ION_FORCE_CONTIGUOUS ION_FLAG_FORCE_CONTIGUOUS + +/** + * Macro should be used with ion_heap_ids defined above. + */ +#define ION_HEAP(bit) (1 << (bit)) + +#define ION_ADSP_HEAP_NAME "adsp" +#define ION_SYSTEM_HEAP_NAME "system" +#define ION_VMALLOC_HEAP_NAME ION_SYSTEM_HEAP_NAME +#define ION_KMALLOC_HEAP_NAME "kmalloc" +#define ION_AUDIO_HEAP_NAME "audio" +#define ION_SF_HEAP_NAME "sf" +#define ION_MM_HEAP_NAME "mm" +#define ION_CAMERA_HEAP_NAME "camera_preview" +#define ION_IOMMU_HEAP_NAME "iommu" +#define ION_MFC_HEAP_NAME "mfc" +#define ION_WB_HEAP_NAME "wb" +#define ION_MM_FIRMWARE_HEAP_NAME "mm_fw" +#define ION_PIL1_HEAP_NAME "pil_1" +#define ION_PIL2_HEAP_NAME "pil_2" +#define ION_QSECOM_HEAP_NAME "qsecom" + +#define ION_SET_CACHED(__cache) (__cache | ION_FLAG_CACHED) +#define ION_SET_UNCACHED(__cache) (__cache & ~ION_FLAG_CACHED) + +#define ION_IS_CACHED(__flags) ((__flags) & ION_FLAG_CACHED) + +/* struct ion_flush_data - data passed to ion for flushing caches + * + * @handle: handle with data to flush + * @fd: fd to flush + * @vaddr: userspace virtual address mapped with mmap + * @offset: offset into the handle to flush + * @length: length of handle to flush + * + * Performs cache operations on the handle. If p is the start address + * of the handle, p + offset through p + offset + length will have + * the cache operations performed + */ +struct ion_flush_data { + ion_user_handle_t handle; + int fd; + void *vaddr; + unsigned int offset; + unsigned int length; +}; + + +struct ion_prefetch_data { + int heap_id; + unsigned long len; +}; + +#define ION_IOC_MSM_MAGIC 'M' + +/** + * DOC: ION_IOC_CLEAN_CACHES - clean the caches + * + * Clean the caches of the handle specified. + */ +#define ION_IOC_CLEAN_CACHES _IOWR(ION_IOC_MSM_MAGIC, 0, \ + struct ion_flush_data) +/** + * DOC: ION_IOC_INV_CACHES - invalidate the caches + * + * Invalidate the caches of the handle specified. + */ +#define ION_IOC_INV_CACHES _IOWR(ION_IOC_MSM_MAGIC, 1, \ + struct ion_flush_data) +/** + * DOC: ION_IOC_CLEAN_INV_CACHES - clean and invalidate the caches + * + * Clean and invalidate the caches of the handle specified. + */ +#define ION_IOC_CLEAN_INV_CACHES _IOWR(ION_IOC_MSM_MAGIC, 2, \ + struct ion_flush_data) + +#define ION_IOC_PREFETCH _IOWR(ION_IOC_MSM_MAGIC, 3, \ + struct ion_prefetch_data) + +#define ION_IOC_DRAIN _IOWR(ION_IOC_MSM_MAGIC, 4, \ + struct ion_prefetch_data) + +#endif diff --git a/original-kernel-headers/linux/msm_kgsl.h b/original-kernel-headers/linux/msm_kgsl.h new file mode 100644 index 0000000..9bcdaf7 --- /dev/null +++ b/original-kernel-headers/linux/msm_kgsl.h @@ -0,0 +1,1097 @@ +#ifndef _UAPI_MSM_KGSL_H +#define _UAPI_MSM_KGSL_H + +/* + * The KGSL version has proven not to be very useful in userspace if features + * are cherry picked into other trees out of order so it is frozen as of 3.14. + * It is left here for backwards compatabilty and as a reminder that + * software releases are never linear. Also, I like pie. + */ + +#define KGSL_VERSION_MAJOR 3 +#define KGSL_VERSION_MINOR 14 + +/* + * We have traditionally mixed context and issueibcmds / command batch flags + * together into a big flag stew. This worked fine until we started adding a + * lot more command batch flags and we started running out of bits. Turns out + * we have a bit of room in the context type / priority mask that we could use + * for command batches, but that means we need to split out the flags into two + * coherent sets. + * + * If any future definitions are for both context and cmdbatch add both defines + * and link the cmdbatch to the context define as we do below. Otherwise feel + * free to add exclusive bits to either set. + */ + +/* --- context flags --- */ +#define KGSL_CONTEXT_SAVE_GMEM 0x00000001 +#define KGSL_CONTEXT_NO_GMEM_ALLOC 0x00000002 +/* This is a cmdbatch exclusive flag - use the CMDBATCH equivalent instead */ +#define KGSL_CONTEXT_SUBMIT_IB_LIST 0x00000004 +#define KGSL_CONTEXT_CTX_SWITCH 0x00000008 +#define KGSL_CONTEXT_PREAMBLE 0x00000010 +#define KGSL_CONTEXT_TRASH_STATE 0x00000020 +#define KGSL_CONTEXT_PER_CONTEXT_TS 0x00000040 +#define KGSL_CONTEXT_USER_GENERATED_TS 0x00000080 +/* This is a cmdbatch exclusive flag - use the CMDBATCH equivalent instead */ +#define KGSL_CONTEXT_END_OF_FRAME 0x00000100 +#define KGSL_CONTEXT_NO_FAULT_TOLERANCE 0x00000200 +/* This is a cmdbatch exclusive flag - use the CMDBATCH equivalent instead */ +#define KGSL_CONTEXT_SYNC 0x00000400 +#define KGSL_CONTEXT_PWR_CONSTRAINT 0x00000800 + +#define KGSL_CONTEXT_PRIORITY_MASK 0x0000F000 +#define KGSL_CONTEXT_PRIORITY_SHIFT 12 +#define KGSL_CONTEXT_PRIORITY_UNDEF 0 + +#define KGSL_CONTEXT_IFH_NOP 0x00010000 +#define KGSL_CONTEXT_SECURE 0x00020000 + +#define KGSL_CONTEXT_TYPE_MASK 0x01F00000 +#define KGSL_CONTEXT_TYPE_SHIFT 20 +#define KGSL_CONTEXT_TYPE_ANY 0 +#define KGSL_CONTEXT_TYPE_GL 1 +#define KGSL_CONTEXT_TYPE_CL 2 +#define KGSL_CONTEXT_TYPE_C2D 3 +#define KGSL_CONTEXT_TYPE_RS 4 +#define KGSL_CONTEXT_TYPE_UNKNOWN 0x1E + +#define KGSL_CONTEXT_INVALID 0xffffffff + +/* + * --- command batch flags --- + * The bits that are linked to a KGSL_CONTEXT equivalent are either legacy + * definitions or bits that are valid for both contexts and cmdbatches. To be + * safe the other 8 bits that are still available in the context field should be + * omitted here in case we need to share - the other bits are available for + * cmdbatch only flags as needed + */ +#define KGSL_CMDBATCH_MEMLIST 0x00000001 +#define KGSL_CMDBATCH_MARKER 0x00000002 +#define KGSL_CMDBATCH_SUBMIT_IB_LIST KGSL_CONTEXT_SUBMIT_IB_LIST /* 0x004 */ +#define KGSL_CMDBATCH_CTX_SWITCH KGSL_CONTEXT_CTX_SWITCH /* 0x008 */ +#define KGSL_CMDBATCH_PROFILING 0x00000010 +#define KGSL_CMDBATCH_END_OF_FRAME KGSL_CONTEXT_END_OF_FRAME /* 0x100 */ +#define KGSL_CMDBATCH_SYNC KGSL_CONTEXT_SYNC /* 0x400 */ +#define KGSL_CMDBATCH_PWR_CONSTRAINT KGSL_CONTEXT_PWR_CONSTRAINT /* 0x800 */ + +/* + * Reserve bits [16:19] and bits [28:31] for possible bits shared between + * contexts and command batches. Update this comment as new flags are added. + */ + +/* --- Memory allocation flags --- */ + +/* General allocation hints */ +#define KGSL_MEMFLAGS_GPUREADONLY 0x01000000 +#define KGSL_MEMFLAGS_USE_CPU_MAP 0x10000000 + +/* Memory is secure */ +#define KGSL_MEMFLAGS_SECURE 0x00000008 + +/* Memory caching hints */ +#define KGSL_CACHEMODE_MASK 0x0C000000 +#define KGSL_CACHEMODE_SHIFT 26 + +#define KGSL_CACHEMODE_WRITECOMBINE 0 +#define KGSL_CACHEMODE_UNCACHED 1 +#define KGSL_CACHEMODE_WRITETHROUGH 2 +#define KGSL_CACHEMODE_WRITEBACK 3 + +/* Memory types for which allocations are made */ +#define KGSL_MEMTYPE_MASK 0x0000FF00 +#define KGSL_MEMTYPE_SHIFT 8 + +#define KGSL_MEMTYPE_OBJECTANY 0 +#define KGSL_MEMTYPE_FRAMEBUFFER 1 +#define KGSL_MEMTYPE_RENDERBUFFER 2 +#define KGSL_MEMTYPE_ARRAYBUFFER 3 +#define KGSL_MEMTYPE_ELEMENTARRAYBUFFER 4 +#define KGSL_MEMTYPE_VERTEXARRAYBUFFER 5 +#define KGSL_MEMTYPE_TEXTURE 6 +#define KGSL_MEMTYPE_SURFACE 7 +#define KGSL_MEMTYPE_EGL_SURFACE 8 +#define KGSL_MEMTYPE_GL 9 +#define KGSL_MEMTYPE_CL 10 +#define KGSL_MEMTYPE_CL_BUFFER_MAP 11 +#define KGSL_MEMTYPE_CL_BUFFER_NOMAP 12 +#define KGSL_MEMTYPE_CL_IMAGE_MAP 13 +#define KGSL_MEMTYPE_CL_IMAGE_NOMAP 14 +#define KGSL_MEMTYPE_CL_KERNEL_STACK 15 +#define KGSL_MEMTYPE_COMMAND 16 +#define KGSL_MEMTYPE_2D 17 +#define KGSL_MEMTYPE_EGL_IMAGE 18 +#define KGSL_MEMTYPE_EGL_SHADOW 19 +#define KGSL_MEMTYPE_MULTISAMPLE 20 +#define KGSL_MEMTYPE_KERNEL 255 + +/* + * Alignment hint, passed as the power of 2 exponent. + * i.e 4k (2^12) would be 12, 64k (2^16)would be 16. + */ +#define KGSL_MEMALIGN_MASK 0x00FF0000 +#define KGSL_MEMALIGN_SHIFT 16 + +enum kgsl_user_mem_type { + KGSL_USER_MEM_TYPE_PMEM = 0x00000000, + KGSL_USER_MEM_TYPE_ASHMEM = 0x00000001, + KGSL_USER_MEM_TYPE_ADDR = 0x00000002, + KGSL_USER_MEM_TYPE_ION = 0x00000003, + KGSL_USER_MEM_TYPE_MAX = 0x00000007, +}; +#define KGSL_MEMFLAGS_USERMEM_MASK 0x000000e0 +#define KGSL_MEMFLAGS_USERMEM_SHIFT 5 + +/* + * Unfortunately, enum kgsl_user_mem_type starts at 0 which does not + * leave a good value for allocated memory. In the flags we use + * 0 to indicate allocated memory and thus need to add 1 to the enum + * values. + */ +#define KGSL_USERMEM_FLAG(x) (((x) + 1) << KGSL_MEMFLAGS_USERMEM_SHIFT) + +#define KGSL_MEMFLAGS_NOT_USERMEM 0 +#define KGSL_MEMFLAGS_USERMEM_PMEM KGSL_USERMEM_FLAG(KGSL_USER_MEM_TYPE_PMEM) +#define KGSL_MEMFLAGS_USERMEM_ASHMEM \ + KGSL_USERMEM_FLAG(KGSL_USER_MEM_TYPE_ASHMEM) +#define KGSL_MEMFLAGS_USERMEM_ADDR KGSL_USERMEM_FLAG(KGSL_USER_MEM_TYPE_ADDR) +#define KGSL_MEMFLAGS_USERMEM_ION KGSL_USERMEM_FLAG(KGSL_USER_MEM_TYPE_ION) + +/* --- generic KGSL flag values --- */ + +#define KGSL_FLAGS_NORMALMODE 0x00000000 +#define KGSL_FLAGS_SAFEMODE 0x00000001 +#define KGSL_FLAGS_INITIALIZED0 0x00000002 +#define KGSL_FLAGS_INITIALIZED 0x00000004 +#define KGSL_FLAGS_STARTED 0x00000008 +#define KGSL_FLAGS_ACTIVE 0x00000010 +#define KGSL_FLAGS_RESERVED0 0x00000020 +#define KGSL_FLAGS_RESERVED1 0x00000040 +#define KGSL_FLAGS_RESERVED2 0x00000080 +#define KGSL_FLAGS_SOFT_RESET 0x00000100 +#define KGSL_FLAGS_PER_CONTEXT_TIMESTAMPS 0x00000200 + +/* Clock flags to show which clocks should be controled by a given platform */ +#define KGSL_CLK_SRC 0x00000001 +#define KGSL_CLK_CORE 0x00000002 +#define KGSL_CLK_IFACE 0x00000004 +#define KGSL_CLK_MEM 0x00000008 +#define KGSL_CLK_MEM_IFACE 0x00000010 +#define KGSL_CLK_AXI 0x00000020 + +/* Server Side Sync Timeout in milliseconds */ +#define KGSL_SYNCOBJ_SERVER_TIMEOUT 2000 + +/* + * Reset status values for context + */ +enum kgsl_ctx_reset_stat { + KGSL_CTX_STAT_NO_ERROR = 0x00000000, + KGSL_CTX_STAT_GUILTY_CONTEXT_RESET_EXT = 0x00000001, + KGSL_CTX_STAT_INNOCENT_CONTEXT_RESET_EXT = 0x00000002, + KGSL_CTX_STAT_UNKNOWN_CONTEXT_RESET_EXT = 0x00000003 +}; + +#define KGSL_CONVERT_TO_MBPS(val) \ + (val*1000*1000U) + +/* device id */ +enum kgsl_deviceid { + KGSL_DEVICE_3D0 = 0x00000000, + KGSL_DEVICE_2D0 = 0x00000001, + KGSL_DEVICE_2D1 = 0x00000002, + KGSL_DEVICE_MAX = 0x00000003 +}; + +struct kgsl_devinfo { + + unsigned int device_id; + /* chip revision id + * coreid:8 majorrev:8 minorrev:8 patch:8 + */ + unsigned int chip_id; + unsigned int mmu_enabled; + unsigned long gmem_gpubaseaddr; + /* + * This field contains the adreno revision + * number 200, 205, 220, etc... + */ + unsigned int gpu_id; + size_t gmem_sizebytes; +}; + +/* this structure defines the region of memory that can be mmap()ed from this + driver. The timestamp fields are volatile because they are written by the + GPU +*/ +struct kgsl_devmemstore { + volatile unsigned int soptimestamp; + unsigned int sbz; + volatile unsigned int eoptimestamp; + unsigned int sbz2; + volatile unsigned int ts_cmp_enable; + unsigned int sbz3; + volatile unsigned int ref_wait_ts; + unsigned int sbz4; + unsigned int current_context; + unsigned int sbz5; +}; + +#define KGSL_MEMSTORE_OFFSET(ctxt_id, field) \ + ((ctxt_id)*sizeof(struct kgsl_devmemstore) + \ + offsetof(struct kgsl_devmemstore, field)) + +/* timestamp id*/ +enum kgsl_timestamp_type { + KGSL_TIMESTAMP_CONSUMED = 0x00000001, /* start-of-pipeline timestamp */ + KGSL_TIMESTAMP_RETIRED = 0x00000002, /* end-of-pipeline timestamp*/ + KGSL_TIMESTAMP_QUEUED = 0x00000003, +}; + +/* property types - used with kgsl_device_getproperty */ +enum kgsl_property_type { + KGSL_PROP_DEVICE_INFO = 0x00000001, + KGSL_PROP_DEVICE_SHADOW = 0x00000002, + KGSL_PROP_DEVICE_POWER = 0x00000003, + KGSL_PROP_SHMEM = 0x00000004, + KGSL_PROP_SHMEM_APERTURES = 0x00000005, + KGSL_PROP_MMU_ENABLE = 0x00000006, + KGSL_PROP_INTERRUPT_WAITS = 0x00000007, + KGSL_PROP_VERSION = 0x00000008, + KGSL_PROP_GPU_RESET_STAT = 0x00000009, + KGSL_PROP_PWRCTRL = 0x0000000E, + KGSL_PROP_PWR_CONSTRAINT = 0x00000012, +}; + +struct kgsl_shadowprop { + unsigned long gpuaddr; + size_t size; + unsigned int flags; /* contains KGSL_FLAGS_ values */ +}; + +struct kgsl_version { + unsigned int drv_major; + unsigned int drv_minor; + unsigned int dev_major; + unsigned int dev_minor; +}; + +/* Performance counter groups */ + +#define KGSL_PERFCOUNTER_GROUP_CP 0x0 +#define KGSL_PERFCOUNTER_GROUP_RBBM 0x1 +#define KGSL_PERFCOUNTER_GROUP_PC 0x2 +#define KGSL_PERFCOUNTER_GROUP_VFD 0x3 +#define KGSL_PERFCOUNTER_GROUP_HLSQ 0x4 +#define KGSL_PERFCOUNTER_GROUP_VPC 0x5 +#define KGSL_PERFCOUNTER_GROUP_TSE 0x6 +#define KGSL_PERFCOUNTER_GROUP_RAS 0x7 +#define KGSL_PERFCOUNTER_GROUP_UCHE 0x8 +#define KGSL_PERFCOUNTER_GROUP_TP 0x9 +#define KGSL_PERFCOUNTER_GROUP_SP 0xA +#define KGSL_PERFCOUNTER_GROUP_RB 0xB +#define KGSL_PERFCOUNTER_GROUP_PWR 0xC +#define KGSL_PERFCOUNTER_GROUP_VBIF 0xD +#define KGSL_PERFCOUNTER_GROUP_VBIF_PWR 0xE +#define KGSL_PERFCOUNTER_GROUP_MH 0xF +#define KGSL_PERFCOUNTER_GROUP_PA_SU 0x10 +#define KGSL_PERFCOUNTER_GROUP_SQ 0x11 +#define KGSL_PERFCOUNTER_GROUP_SX 0x12 +#define KGSL_PERFCOUNTER_GROUP_TCF 0x13 +#define KGSL_PERFCOUNTER_GROUP_TCM 0x14 +#define KGSL_PERFCOUNTER_GROUP_TCR 0x15 +#define KGSL_PERFCOUNTER_GROUP_L2 0x16 +#define KGSL_PERFCOUNTER_GROUP_VSC 0x17 +#define KGSL_PERFCOUNTER_GROUP_CCU 0x18 +#define KGSL_PERFCOUNTER_GROUP_ALWAYSON 0x1B +#define KGSL_PERFCOUNTER_GROUP_MAX 0x1C + +#define KGSL_PERFCOUNTER_NOT_USED 0xFFFFFFFF +#define KGSL_PERFCOUNTER_BROKEN 0xFFFFFFFE + +/* structure holds list of ibs */ +struct kgsl_ibdesc { + unsigned long gpuaddr; + unsigned long __pad; + size_t sizedwords; + unsigned int ctrl; +}; + +/** + * struct kgsl_cmdbatch_profiling_buffer + * @wall_clock_s: Wall clock at ringbuffer submission time (seconds) + * @wall_clock_ns: Wall clock at ringbuffer submission time (nanoseconds) + * @gpu_ticks_queued: GPU ticks at ringbuffer submission + * @gpu_ticks_submitted: GPU ticks when starting cmdbatch execution + * @gpu_ticks_retired: GPU ticks when finishing cmdbatch execution + * + * This structure defines the profiling buffer used to measure cmdbatch + * execution time + */ +struct kgsl_cmdbatch_profiling_buffer { + uint64_t wall_clock_s; + uint64_t wall_clock_ns; + uint64_t gpu_ticks_queued; + uint64_t gpu_ticks_submitted; + uint64_t gpu_ticks_retired; +}; + +/* ioctls */ +#define KGSL_IOC_TYPE 0x09 + +/* get misc info about the GPU + type should be a value from enum kgsl_property_type + value points to a structure that varies based on type + sizebytes is sizeof() that structure + for KGSL_PROP_DEVICE_INFO, use struct kgsl_devinfo + this structure contaings hardware versioning info. + for KGSL_PROP_DEVICE_SHADOW, use struct kgsl_shadowprop + this is used to find mmap() offset and sizes for mapping + struct kgsl_memstore into userspace. +*/ +struct kgsl_device_getproperty { + unsigned int type; + void __user *value; + size_t sizebytes; +}; + +#define IOCTL_KGSL_DEVICE_GETPROPERTY \ + _IOWR(KGSL_IOC_TYPE, 0x2, struct kgsl_device_getproperty) + +/* IOCTL_KGSL_DEVICE_READ (0x3) - removed 03/2012 + */ + +/* block until the GPU has executed past a given timestamp + * timeout is in milliseconds. + */ +struct kgsl_device_waittimestamp { + unsigned int timestamp; + unsigned int timeout; +}; + +#define IOCTL_KGSL_DEVICE_WAITTIMESTAMP \ + _IOW(KGSL_IOC_TYPE, 0x6, struct kgsl_device_waittimestamp) + +struct kgsl_device_waittimestamp_ctxtid { + unsigned int context_id; + unsigned int timestamp; + unsigned int timeout; +}; + +#define IOCTL_KGSL_DEVICE_WAITTIMESTAMP_CTXTID \ + _IOW(KGSL_IOC_TYPE, 0x7, struct kgsl_device_waittimestamp_ctxtid) + +/* DEPRECATED: issue indirect commands to the GPU. + * drawctxt_id must have been created with IOCTL_KGSL_DRAWCTXT_CREATE + * ibaddr and sizedwords must specify a subset of a buffer created + * with IOCTL_KGSL_SHAREDMEM_FROM_PMEM + * flags may be a mask of KGSL_CONTEXT_ values + * timestamp is a returned counter value which can be passed to + * other ioctls to determine when the commands have been executed by + * the GPU. + * + * This fucntion is deprecated - consider using IOCTL_KGSL_SUBMIT_COMMANDS + * instead + */ +struct kgsl_ringbuffer_issueibcmds { + unsigned int drawctxt_id; + unsigned long ibdesc_addr; + unsigned int numibs; + unsigned int timestamp; /*output param */ + unsigned int flags; +}; + +#define IOCTL_KGSL_RINGBUFFER_ISSUEIBCMDS \ + _IOWR(KGSL_IOC_TYPE, 0x10, struct kgsl_ringbuffer_issueibcmds) + +/* read the most recently executed timestamp value + * type should be a value from enum kgsl_timestamp_type + */ +struct kgsl_cmdstream_readtimestamp { + unsigned int type; + unsigned int timestamp; /*output param */ +}; + +#define IOCTL_KGSL_CMDSTREAM_READTIMESTAMP_OLD \ + _IOR(KGSL_IOC_TYPE, 0x11, struct kgsl_cmdstream_readtimestamp) + +#define IOCTL_KGSL_CMDSTREAM_READTIMESTAMP \ + _IOWR(KGSL_IOC_TYPE, 0x11, struct kgsl_cmdstream_readtimestamp) + +/* free memory when the GPU reaches a given timestamp. + * gpuaddr specify a memory region created by a + * IOCTL_KGSL_SHAREDMEM_FROM_PMEM call + * type should be a value from enum kgsl_timestamp_type + */ +struct kgsl_cmdstream_freememontimestamp { + unsigned long gpuaddr; + unsigned int type; + unsigned int timestamp; +}; + +#define IOCTL_KGSL_CMDSTREAM_FREEMEMONTIMESTAMP \ + _IOW(KGSL_IOC_TYPE, 0x12, struct kgsl_cmdstream_freememontimestamp) + +/* Previous versions of this header had incorrectly defined + IOCTL_KGSL_CMDSTREAM_FREEMEMONTIMESTAMP as a read-only ioctl instead + of a write only ioctl. To ensure binary compatability, the following + #define will be used to intercept the incorrect ioctl +*/ + +#define IOCTL_KGSL_CMDSTREAM_FREEMEMONTIMESTAMP_OLD \ + _IOR(KGSL_IOC_TYPE, 0x12, struct kgsl_cmdstream_freememontimestamp) + +/* create a draw context, which is used to preserve GPU state. + * The flags field may contain a mask KGSL_CONTEXT_* values + */ +struct kgsl_drawctxt_create { + unsigned int flags; + unsigned int drawctxt_id; /*output param */ +}; + +#define IOCTL_KGSL_DRAWCTXT_CREATE \ + _IOWR(KGSL_IOC_TYPE, 0x13, struct kgsl_drawctxt_create) + +/* destroy a draw context */ +struct kgsl_drawctxt_destroy { + unsigned int drawctxt_id; +}; + +#define IOCTL_KGSL_DRAWCTXT_DESTROY \ + _IOW(KGSL_IOC_TYPE, 0x14, struct kgsl_drawctxt_destroy) + +/* add a block of pmem, fb, ashmem or user allocated address + * into the GPU address space */ +struct kgsl_map_user_mem { + int fd; + unsigned long gpuaddr; /*output param */ + size_t len; + size_t offset; + unsigned long hostptr; /*input param */ + enum kgsl_user_mem_type memtype; + unsigned int flags; +}; + +#define IOCTL_KGSL_MAP_USER_MEM \ + _IOWR(KGSL_IOC_TYPE, 0x15, struct kgsl_map_user_mem) + +struct kgsl_cmdstream_readtimestamp_ctxtid { + unsigned int context_id; + unsigned int type; + unsigned int timestamp; /*output param */ +}; + +#define IOCTL_KGSL_CMDSTREAM_READTIMESTAMP_CTXTID \ + _IOWR(KGSL_IOC_TYPE, 0x16, struct kgsl_cmdstream_readtimestamp_ctxtid) + +struct kgsl_cmdstream_freememontimestamp_ctxtid { + unsigned int context_id; + unsigned long gpuaddr; + unsigned int type; + unsigned int timestamp; +}; + +#define IOCTL_KGSL_CMDSTREAM_FREEMEMONTIMESTAMP_CTXTID \ + _IOW(KGSL_IOC_TYPE, 0x17, \ + struct kgsl_cmdstream_freememontimestamp_ctxtid) + +/* add a block of pmem or fb into the GPU address space */ +struct kgsl_sharedmem_from_pmem { + int pmem_fd; + unsigned long gpuaddr; /*output param */ + unsigned int len; + unsigned int offset; +}; + +#define IOCTL_KGSL_SHAREDMEM_FROM_PMEM \ + _IOWR(KGSL_IOC_TYPE, 0x20, struct kgsl_sharedmem_from_pmem) + +/* remove memory from the GPU's address space */ +struct kgsl_sharedmem_free { + unsigned long gpuaddr; +}; + +#define IOCTL_KGSL_SHAREDMEM_FREE \ + _IOW(KGSL_IOC_TYPE, 0x21, struct kgsl_sharedmem_free) + +struct kgsl_cff_user_event { + unsigned char cff_opcode; + unsigned int op1; + unsigned int op2; + unsigned int op3; + unsigned int op4; + unsigned int op5; + unsigned int __pad[2]; +}; + +#define IOCTL_KGSL_CFF_USER_EVENT \ + _IOW(KGSL_IOC_TYPE, 0x31, struct kgsl_cff_user_event) + +struct kgsl_gmem_desc { + unsigned int x; + unsigned int y; + unsigned int width; + unsigned int height; + unsigned int pitch; +}; + +struct kgsl_buffer_desc { + void *hostptr; + unsigned long gpuaddr; + int size; + unsigned int format; + unsigned int pitch; + unsigned int enabled; +}; + +struct kgsl_bind_gmem_shadow { + unsigned int drawctxt_id; + struct kgsl_gmem_desc gmem_desc; + unsigned int shadow_x; + unsigned int shadow_y; + struct kgsl_buffer_desc shadow_buffer; + unsigned int buffer_id; +}; + +#define IOCTL_KGSL_DRAWCTXT_BIND_GMEM_SHADOW \ + _IOW(KGSL_IOC_TYPE, 0x22, struct kgsl_bind_gmem_shadow) + +/* add a block of memory into the GPU address space */ + +/* + * IOCTL_KGSL_SHAREDMEM_FROM_VMALLOC deprecated 09/2012 + * use IOCTL_KGSL_GPUMEM_ALLOC instead + */ + +struct kgsl_sharedmem_from_vmalloc { + unsigned long gpuaddr; /*output param */ + unsigned int hostptr; + unsigned int flags; +}; + +#define IOCTL_KGSL_SHAREDMEM_FROM_VMALLOC \ + _IOWR(KGSL_IOC_TYPE, 0x23, struct kgsl_sharedmem_from_vmalloc) + +/* + * This is being deprecated in favor of IOCTL_KGSL_GPUMEM_CACHE_SYNC which + * supports both directions (flush and invalidate). This code will still + * work, but by definition it will do a flush of the cache which might not be + * what you want to have happen on a buffer following a GPU operation. It is + * safer to go with IOCTL_KGSL_GPUMEM_CACHE_SYNC + */ + +#define IOCTL_KGSL_SHAREDMEM_FLUSH_CACHE \ + _IOW(KGSL_IOC_TYPE, 0x24, struct kgsl_sharedmem_free) + +struct kgsl_drawctxt_set_bin_base_offset { + unsigned int drawctxt_id; + unsigned int offset; +}; + +#define IOCTL_KGSL_DRAWCTXT_SET_BIN_BASE_OFFSET \ + _IOW(KGSL_IOC_TYPE, 0x25, struct kgsl_drawctxt_set_bin_base_offset) + +enum kgsl_cmdwindow_type { + KGSL_CMDWINDOW_MIN = 0x00000000, + KGSL_CMDWINDOW_2D = 0x00000000, + KGSL_CMDWINDOW_3D = 0x00000001, /* legacy */ + KGSL_CMDWINDOW_MMU = 0x00000002, + KGSL_CMDWINDOW_ARBITER = 0x000000FF, + KGSL_CMDWINDOW_MAX = 0x000000FF, +}; + +/* write to the command window */ +struct kgsl_cmdwindow_write { + enum kgsl_cmdwindow_type target; + unsigned int addr; + unsigned int data; +}; + +#define IOCTL_KGSL_CMDWINDOW_WRITE \ + _IOW(KGSL_IOC_TYPE, 0x2e, struct kgsl_cmdwindow_write) + +struct kgsl_gpumem_alloc { + unsigned long gpuaddr; /* output param */ + size_t size; + unsigned int flags; +}; + +#define IOCTL_KGSL_GPUMEM_ALLOC \ + _IOWR(KGSL_IOC_TYPE, 0x2f, struct kgsl_gpumem_alloc) + +struct kgsl_cff_syncmem { + unsigned long gpuaddr; + size_t len; + unsigned int __pad[2]; /* For future binary compatibility */ +}; + +#define IOCTL_KGSL_CFF_SYNCMEM \ + _IOW(KGSL_IOC_TYPE, 0x30, struct kgsl_cff_syncmem) + +/* + * A timestamp event allows the user space to register an action following an + * expired timestamp. Note IOCTL_KGSL_TIMESTAMP_EVENT has been redefined to + * _IOWR to support fences which need to return a fd for the priv parameter. + */ + +struct kgsl_timestamp_event { + int type; /* Type of event (see list below) */ + unsigned int timestamp; /* Timestamp to trigger event on */ + unsigned int context_id; /* Context for the timestamp */ + void __user *priv; /* Pointer to the event specific blob */ + size_t len; /* Size of the event specific blob */ +}; + +#define IOCTL_KGSL_TIMESTAMP_EVENT_OLD \ + _IOW(KGSL_IOC_TYPE, 0x31, struct kgsl_timestamp_event) + +/* A genlock timestamp event releases an existing lock on timestamp expire */ + +#define KGSL_TIMESTAMP_EVENT_GENLOCK 1 + +struct kgsl_timestamp_event_genlock { + int handle; /* Handle of the genlock lock to release */ +}; + +/* A fence timestamp event releases an existing lock on timestamp expire */ + +#define KGSL_TIMESTAMP_EVENT_FENCE 2 + +struct kgsl_timestamp_event_fence { + int fence_fd; /* Fence to signal */ +}; + +/* + * Set a property within the kernel. Uses the same structure as + * IOCTL_KGSL_GETPROPERTY + */ + +#define IOCTL_KGSL_SETPROPERTY \ + _IOW(KGSL_IOC_TYPE, 0x32, struct kgsl_device_getproperty) + +#define IOCTL_KGSL_TIMESTAMP_EVENT \ + _IOWR(KGSL_IOC_TYPE, 0x33, struct kgsl_timestamp_event) + +/** + * struct kgsl_gpumem_alloc_id - argument to IOCTL_KGSL_GPUMEM_ALLOC_ID + * @id: returned id value for this allocation. + * @flags: mask of KGSL_MEM* values requested and actual flags on return. + * @size: requested size of the allocation and actual size on return. + * @mmapsize: returned size to pass to mmap() which may be larger than 'size' + * @gpuaddr: returned GPU address for the allocation + * + * Allocate memory for access by the GPU. The flags and size fields are echoed + * back by the kernel, so that the caller can know if the request was + * adjusted. + * + * Supported flags: + * KGSL_MEMFLAGS_GPUREADONLY: the GPU will be unable to write to the buffer + * KGSL_MEMTYPE*: usage hint for debugging aid + * KGSL_MEMALIGN*: alignment hint, may be ignored or adjusted by the kernel. + * KGSL_MEMFLAGS_USE_CPU_MAP: If set on call and return, the returned GPU + * address will be 0. Calling mmap() will set the GPU address. + */ +struct kgsl_gpumem_alloc_id { + unsigned int id; + unsigned int flags; + size_t size; + size_t mmapsize; + unsigned long gpuaddr; +/* private: reserved for future use*/ + unsigned long __pad[2]; +}; + +#define IOCTL_KGSL_GPUMEM_ALLOC_ID \ + _IOWR(KGSL_IOC_TYPE, 0x34, struct kgsl_gpumem_alloc_id) + +/** + * struct kgsl_gpumem_free_id - argument to IOCTL_KGSL_GPUMEM_FREE_ID + * @id: GPU allocation id to free + * + * Free an allocation by id, in case a GPU address has not been assigned or + * is unknown. Freeing an allocation by id with this ioctl or by GPU address + * with IOCTL_KGSL_SHAREDMEM_FREE are equivalent. + */ +struct kgsl_gpumem_free_id { + unsigned int id; +/* private: reserved for future use*/ + unsigned int __pad; +}; + +#define IOCTL_KGSL_GPUMEM_FREE_ID \ + _IOWR(KGSL_IOC_TYPE, 0x35, struct kgsl_gpumem_free_id) + +/** + * struct kgsl_gpumem_get_info - argument to IOCTL_KGSL_GPUMEM_GET_INFO + * @gpuaddr: GPU address to query. Also set on return. + * @id: GPU allocation id to query. Also set on return. + * @flags: returned mask of KGSL_MEM* values. + * @size: returned size of the allocation. + * @mmapsize: returned size to pass mmap(), which may be larger than 'size' + * @useraddr: returned address of the userspace mapping for this buffer + * + * This ioctl allows querying of all user visible attributes of an existing + * allocation, by either the GPU address or the id returned by a previous + * call to IOCTL_KGSL_GPUMEM_ALLOC_ID. Legacy allocation ioctls may not + * return all attributes so this ioctl can be used to look them up if needed. + * + */ +struct kgsl_gpumem_get_info { + unsigned long gpuaddr; + unsigned int id; + unsigned int flags; + size_t size; + size_t mmapsize; + unsigned long useraddr; +/* private: reserved for future use*/ + unsigned long __pad[4]; +}; + +#define IOCTL_KGSL_GPUMEM_GET_INFO\ + _IOWR(KGSL_IOC_TYPE, 0x36, struct kgsl_gpumem_get_info) + +/** + * struct kgsl_gpumem_sync_cache - argument to IOCTL_KGSL_GPUMEM_SYNC_CACHE + * @gpuaddr: GPU address of the buffer to sync. + * @id: id of the buffer to sync. Either gpuaddr or id is sufficient. + * @op: a mask of KGSL_GPUMEM_CACHE_* values + * @offset: offset into the buffer + * @length: number of bytes starting from offset to perform + * the cache operation on + * + * Sync the L2 cache for memory headed to and from the GPU - this replaces + * KGSL_SHAREDMEM_FLUSH_CACHE since it can handle cache management for both + * directions + * + */ +struct kgsl_gpumem_sync_cache { + unsigned long gpuaddr; + unsigned int id; + unsigned int op; + size_t offset; + size_t length; +}; + +#define KGSL_GPUMEM_CACHE_CLEAN (1 << 0) +#define KGSL_GPUMEM_CACHE_TO_GPU KGSL_GPUMEM_CACHE_CLEAN + +#define KGSL_GPUMEM_CACHE_INV (1 << 1) +#define KGSL_GPUMEM_CACHE_FROM_GPU KGSL_GPUMEM_CACHE_INV + +#define KGSL_GPUMEM_CACHE_FLUSH \ + (KGSL_GPUMEM_CACHE_CLEAN | KGSL_GPUMEM_CACHE_INV) + +/* Flag to ensure backwards compatibility of kgsl_gpumem_sync_cache struct */ +#define KGSL_GPUMEM_CACHE_RANGE (1 << 31U) + +#define IOCTL_KGSL_GPUMEM_SYNC_CACHE \ + _IOW(KGSL_IOC_TYPE, 0x37, struct kgsl_gpumem_sync_cache) + +/** + * struct kgsl_perfcounter_get - argument to IOCTL_KGSL_PERFCOUNTER_GET + * @groupid: Performance counter group ID + * @countable: Countable to select within the group + * @offset: Return offset of the reserved LO counter + * @offset_hi: Return offset of the reserved HI counter + * + * Get an available performance counter from a specified groupid. The offset + * of the performance counter will be returned after successfully assigning + * the countable to the counter for the specified group. An error will be + * returned and an offset of 0 if the groupid is invalid or there are no + * more counters left. After successfully getting a perfcounter, the user + * must call kgsl_perfcounter_put(groupid, contable) when finished with + * the perfcounter to clear up perfcounter resources. + * + */ +struct kgsl_perfcounter_get { + unsigned int groupid; + unsigned int countable; + unsigned int offset; + unsigned int offset_hi; +/* private: reserved for future use */ + unsigned int __pad; /* For future binary compatibility */ +}; + +#define IOCTL_KGSL_PERFCOUNTER_GET \ + _IOWR(KGSL_IOC_TYPE, 0x38, struct kgsl_perfcounter_get) + +/** + * struct kgsl_perfcounter_put - argument to IOCTL_KGSL_PERFCOUNTER_PUT + * @groupid: Performance counter group ID + * @countable: Countable to release within the group + * + * Put an allocated performance counter to allow others to have access to the + * resource that was previously taken. This is only to be called after + * successfully getting a performance counter from kgsl_perfcounter_get(). + * + */ +struct kgsl_perfcounter_put { + unsigned int groupid; + unsigned int countable; +/* private: reserved for future use */ + unsigned int __pad[2]; /* For future binary compatibility */ +}; + +#define IOCTL_KGSL_PERFCOUNTER_PUT \ + _IOW(KGSL_IOC_TYPE, 0x39, struct kgsl_perfcounter_put) + +/** + * struct kgsl_perfcounter_query - argument to IOCTL_KGSL_PERFCOUNTER_QUERY + * @groupid: Performance counter group ID + * @countable: Return active countables array + * @size: Size of active countables array + * @max_counters: Return total number counters for the group ID + * + * Query the available performance counters given a groupid. The array + * *countables is used to return the current active countables in counters. + * The size of the array is passed in so the kernel will only write at most + * size or counter->size for the group id. The total number of available + * counters for the group ID is returned in max_counters. + * If the array or size passed in are invalid, then only the maximum number + * of counters will be returned, no data will be written to *countables. + * If the groupid is invalid an error code will be returned. + * + */ +struct kgsl_perfcounter_query { + unsigned int groupid; + /* Array to return the current countable for up to size counters */ + unsigned int __user *countables; + unsigned int count; + unsigned int max_counters; +/* private: reserved for future use */ + unsigned int __pad[2]; /* For future binary compatibility */ +}; + +#define IOCTL_KGSL_PERFCOUNTER_QUERY \ + _IOWR(KGSL_IOC_TYPE, 0x3A, struct kgsl_perfcounter_query) + +/** + * struct kgsl_perfcounter_query - argument to IOCTL_KGSL_PERFCOUNTER_QUERY + * @groupid: Performance counter group IDs + * @countable: Performance counter countable IDs + * @value: Return performance counter reads + * @size: Size of all arrays (groupid/countable pair and return value) + * + * Read in the current value of a performance counter given by the groupid + * and countable. + * + */ + +struct kgsl_perfcounter_read_group { + unsigned int groupid; + unsigned int countable; + unsigned long long value; +}; + +struct kgsl_perfcounter_read { + struct kgsl_perfcounter_read_group __user *reads; + unsigned int count; +/* private: reserved for future use */ + unsigned int __pad[2]; /* For future binary compatibility */ +}; + +#define IOCTL_KGSL_PERFCOUNTER_READ \ + _IOWR(KGSL_IOC_TYPE, 0x3B, struct kgsl_perfcounter_read) +/* + * struct kgsl_gpumem_sync_cache_bulk - argument to + * IOCTL_KGSL_GPUMEM_SYNC_CACHE_BULK + * @id_list: list of GPU buffer ids of the buffers to sync + * @count: number of GPU buffer ids in id_list + * @op: a mask of KGSL_GPUMEM_CACHE_* values + * + * Sync the cache for memory headed to and from the GPU. Certain + * optimizations can be made on the cache operation based on the total + * size of the working set of memory to be managed. + */ +struct kgsl_gpumem_sync_cache_bulk { + unsigned int __user *id_list; + unsigned int count; + unsigned int op; +/* private: reserved for future use */ + unsigned int __pad[2]; /* For future binary compatibility */ +}; + +#define IOCTL_KGSL_GPUMEM_SYNC_CACHE_BULK \ + _IOWR(KGSL_IOC_TYPE, 0x3C, struct kgsl_gpumem_sync_cache_bulk) + +/* + * struct kgsl_cmd_syncpoint_timestamp + * @context_id: ID of a KGSL context + * @timestamp: GPU timestamp + * + * This structure defines a syncpoint comprising a context/timestamp pair. A + * list of these may be passed by IOCTL_KGSL_SUBMIT_COMMANDS to define + * dependencies that must be met before the command can be submitted to the + * hardware + */ +struct kgsl_cmd_syncpoint_timestamp { + unsigned int context_id; + unsigned int timestamp; +}; + +#define KGSL_CMD_SYNCPOINT_TYPE_TIMESTAMP 0 + +struct kgsl_cmd_syncpoint_fence { + int fd; +}; + +#define KGSL_CMD_SYNCPOINT_TYPE_FENCE 1 + +/** + * struct kgsl_cmd_syncpoint - Define a sync point for a command batch + * @type: type of sync point defined here + * @priv: Pointer to the type specific buffer + * @size: Size of the type specific buffer + * + * This structure contains pointers defining a specific command sync point. + * The pointer and size should point to a type appropriate structure. + */ +struct kgsl_cmd_syncpoint { + int type; + void __user *priv; + size_t size; +}; + +/* Flag to indicate that the cmdlist may contain memlists */ +#define KGSL_IBDESC_MEMLIST 0x1 + +/* Flag to point out the cmdbatch profiling buffer in the memlist */ +#define KGSL_IBDESC_PROFILING_BUFFER 0x2 + +/** + * struct kgsl_submit_commands - Argument to IOCTL_KGSL_SUBMIT_COMMANDS + * @context_id: KGSL context ID that owns the commands + * @flags: + * @cmdlist: User pointer to a list of kgsl_ibdesc structures + * @numcmds: Number of commands listed in cmdlist + * @synclist: User pointer to a list of kgsl_cmd_syncpoint structures + * @numsyncs: Number of sync points listed in synclist + * @timestamp: On entry the a user defined timestamp, on exist the timestamp + * assigned to the command batch + * + * This structure specifies a command to send to the GPU hardware. This is + * similar to kgsl_issueibcmds expect that it doesn't support the legacy way to + * submit IB lists and it adds sync points to block the IB until the + * dependencies are satisified. This entry point is the new and preferred way + * to submit commands to the GPU. The memory list can be used to specify all + * memory that is referrenced in the current set of commands. + */ + +struct kgsl_submit_commands { + unsigned int context_id; + unsigned int flags; + struct kgsl_ibdesc __user *cmdlist; + unsigned int numcmds; + struct kgsl_cmd_syncpoint __user *synclist; + unsigned int numsyncs; + unsigned int timestamp; +/* private: reserved for future use */ + unsigned int __pad[4]; +}; + +#define IOCTL_KGSL_SUBMIT_COMMANDS \ + _IOWR(KGSL_IOC_TYPE, 0x3D, struct kgsl_submit_commands) + +/** + * struct kgsl_device_constraint - device constraint argument + * @context_id: KGSL context ID + * @type: type of constraint i.e pwrlevel/none + * @data: constraint data + * @size: size of the constraint data + */ +struct kgsl_device_constraint { + unsigned int type; + unsigned int context_id; + void __user *data; + size_t size; +}; + +/* Constraint Type*/ +#define KGSL_CONSTRAINT_NONE 0 +#define KGSL_CONSTRAINT_PWRLEVEL 1 + +/* PWRLEVEL constraint level*/ +/* set to min frequency */ +#define KGSL_CONSTRAINT_PWR_MIN 0 +/* set to max frequency */ +#define KGSL_CONSTRAINT_PWR_MAX 1 + +struct kgsl_device_constraint_pwrlevel { + unsigned int level; +}; + +/** + * struct kgsl_syncsource_create - Argument to IOCTL_KGSL_SYNCSOURCE_CREATE + * @id: returned id for the syncsource that was created. + * + * This ioctl creates a userspace sync timeline. + */ + +struct kgsl_syncsource_create { + unsigned int id; +/* private: reserved for future use */ + unsigned int __pad[3]; +}; + +#define IOCTL_KGSL_SYNCSOURCE_CREATE \ + _IOWR(KGSL_IOC_TYPE, 0x40, struct kgsl_syncsource_create) + +/** + * struct kgsl_syncsource_destroy - Argument to IOCTL_KGSL_SYNCSOURCE_DESTROY + * @id: syncsource id to destroy + * + * This ioctl creates a userspace sync timeline. + */ + +struct kgsl_syncsource_destroy { + unsigned int id; +/* private: reserved for future use */ + unsigned int __pad[3]; +}; + +#define IOCTL_KGSL_SYNCSOURCE_DESTROY \ + _IOWR(KGSL_IOC_TYPE, 0x41, struct kgsl_syncsource_destroy) + +/** + * struct kgsl_syncsource_create_fence - Argument to + * IOCTL_KGSL_SYNCSOURCE_CREATE_FENCE + * @id: syncsource id + * @fence_fd: returned sync_fence fd + * + * Create a fence that may be signaled by userspace by calling + * IOCTL_KGSL_SYNCSOURCE_SIGNAL_FENCE. There are no order dependencies between + * these fences. + */ +struct kgsl_syncsource_create_fence { + unsigned int id; + int fence_fd; +/* private: reserved for future use */ + unsigned int __pad[4]; +}; + +/** + * struct kgsl_syncsource_signal_fence - Argument to + * IOCTL_KGSL_SYNCSOURCE_SIGNAL_FENCE + * @id: syncsource id + * @fence_fd: sync_fence fd to signal + * + * Signal a fence that was created by a IOCTL_KGSL_SYNCSOURCE_CREATE_FENCE + * call using the same syncsource id. This allows a fence to be shared + * to other processes but only signaled by the process owning the fd + * used to create the fence. + */ +#define IOCTL_KGSL_SYNCSOURCE_CREATE_FENCE \ + _IOWR(KGSL_IOC_TYPE, 0x42, struct kgsl_syncsource_create_fence) + +struct kgsl_syncsource_signal_fence { + unsigned int id; + int fence_fd; +/* private: reserved for future use */ + unsigned int __pad[4]; +}; + +#define IOCTL_KGSL_SYNCSOURCE_SIGNAL_FENCE \ + _IOWR(KGSL_IOC_TYPE, 0x43, struct kgsl_syncsource_signal_fence) + +#endif /* _UAPI_MSM_KGSL_H */ diff --git a/original-kernel-headers/linux/msm_mdp.h b/original-kernel-headers/linux/msm_mdp.h new file mode 100644 index 0000000..aa1ad59 --- /dev/null +++ b/original-kernel-headers/linux/msm_mdp.h @@ -0,0 +1,1156 @@ +#ifndef _UAPI_MSM_MDP_H_ +#define _UAPI_MSM_MDP_H_ + +#include <linux/types.h> +#include <linux/fb.h> + +#define MSMFB_IOCTL_MAGIC 'm' +#define MSMFB_GRP_DISP _IOW(MSMFB_IOCTL_MAGIC, 1, unsigned int) +#define MSMFB_BLIT _IOW(MSMFB_IOCTL_MAGIC, 2, unsigned int) +#define MSMFB_SUSPEND_SW_REFRESHER _IOW(MSMFB_IOCTL_MAGIC, 128, unsigned int) +#define MSMFB_RESUME_SW_REFRESHER _IOW(MSMFB_IOCTL_MAGIC, 129, unsigned int) +#define MSMFB_CURSOR _IOW(MSMFB_IOCTL_MAGIC, 130, struct fb_cursor) +#define MSMFB_SET_LUT _IOW(MSMFB_IOCTL_MAGIC, 131, struct fb_cmap) +#define MSMFB_HISTOGRAM _IOWR(MSMFB_IOCTL_MAGIC, 132, struct mdp_histogram_data) +/* new ioctls's for set/get ccs matrix */ +#define MSMFB_GET_CCS_MATRIX _IOWR(MSMFB_IOCTL_MAGIC, 133, struct mdp_ccs) +#define MSMFB_SET_CCS_MATRIX _IOW(MSMFB_IOCTL_MAGIC, 134, struct mdp_ccs) +#define MSMFB_OVERLAY_SET _IOWR(MSMFB_IOCTL_MAGIC, 135, \ + struct mdp_overlay) +#define MSMFB_OVERLAY_UNSET _IOW(MSMFB_IOCTL_MAGIC, 136, unsigned int) + +#define MSMFB_OVERLAY_PLAY _IOW(MSMFB_IOCTL_MAGIC, 137, \ + struct msmfb_overlay_data) +#define MSMFB_OVERLAY_QUEUE MSMFB_OVERLAY_PLAY + +#define MSMFB_GET_PAGE_PROTECTION _IOR(MSMFB_IOCTL_MAGIC, 138, \ + struct mdp_page_protection) +#define MSMFB_SET_PAGE_PROTECTION _IOW(MSMFB_IOCTL_MAGIC, 139, \ + struct mdp_page_protection) +#define MSMFB_OVERLAY_GET _IOR(MSMFB_IOCTL_MAGIC, 140, \ + struct mdp_overlay) +#define MSMFB_OVERLAY_PLAY_ENABLE _IOW(MSMFB_IOCTL_MAGIC, 141, unsigned int) +#define MSMFB_OVERLAY_BLT _IOWR(MSMFB_IOCTL_MAGIC, 142, \ + struct msmfb_overlay_blt) +#define MSMFB_OVERLAY_BLT_OFFSET _IOW(MSMFB_IOCTL_MAGIC, 143, unsigned int) +#define MSMFB_HISTOGRAM_START _IOR(MSMFB_IOCTL_MAGIC, 144, \ + struct mdp_histogram_start_req) +#define MSMFB_HISTOGRAM_STOP _IOR(MSMFB_IOCTL_MAGIC, 145, unsigned int) +#define MSMFB_NOTIFY_UPDATE _IOWR(MSMFB_IOCTL_MAGIC, 146, unsigned int) + +#define MSMFB_OVERLAY_3D _IOWR(MSMFB_IOCTL_MAGIC, 147, \ + struct msmfb_overlay_3d) + +#define MSMFB_MIXER_INFO _IOWR(MSMFB_IOCTL_MAGIC, 148, \ + struct msmfb_mixer_info_req) +#define MSMFB_OVERLAY_PLAY_WAIT _IOWR(MSMFB_IOCTL_MAGIC, 149, \ + struct msmfb_overlay_data) +#define MSMFB_WRITEBACK_INIT _IO(MSMFB_IOCTL_MAGIC, 150) +#define MSMFB_WRITEBACK_START _IO(MSMFB_IOCTL_MAGIC, 151) +#define MSMFB_WRITEBACK_STOP _IO(MSMFB_IOCTL_MAGIC, 152) +#define MSMFB_WRITEBACK_QUEUE_BUFFER _IOW(MSMFB_IOCTL_MAGIC, 153, \ + struct msmfb_data) +#define MSMFB_WRITEBACK_DEQUEUE_BUFFER _IOW(MSMFB_IOCTL_MAGIC, 154, \ + struct msmfb_data) +#define MSMFB_WRITEBACK_TERMINATE _IO(MSMFB_IOCTL_MAGIC, 155) +#define MSMFB_MDP_PP _IOWR(MSMFB_IOCTL_MAGIC, 156, struct msmfb_mdp_pp) +#define MSMFB_OVERLAY_VSYNC_CTRL _IOW(MSMFB_IOCTL_MAGIC, 160, unsigned int) +#define MSMFB_VSYNC_CTRL _IOW(MSMFB_IOCTL_MAGIC, 161, unsigned int) +#define MSMFB_BUFFER_SYNC _IOW(MSMFB_IOCTL_MAGIC, 162, struct mdp_buf_sync) +#define MSMFB_OVERLAY_COMMIT _IO(MSMFB_IOCTL_MAGIC, 163) +#define MSMFB_DISPLAY_COMMIT _IOW(MSMFB_IOCTL_MAGIC, 164, \ + struct mdp_display_commit) +#define MSMFB_METADATA_SET _IOW(MSMFB_IOCTL_MAGIC, 165, struct msmfb_metadata) +#define MSMFB_METADATA_GET _IOW(MSMFB_IOCTL_MAGIC, 166, struct msmfb_metadata) +#define MSMFB_WRITEBACK_SET_MIRRORING_HINT _IOW(MSMFB_IOCTL_MAGIC, 167, \ + unsigned int) +#define MSMFB_ASYNC_BLIT _IOW(MSMFB_IOCTL_MAGIC, 168, unsigned int) +#define MSMFB_OVERLAY_PREPARE _IOWR(MSMFB_IOCTL_MAGIC, 169, \ + struct mdp_overlay_list) +#define MSMFB_LPM_ENABLE _IOWR(MSMFB_IOCTL_MAGIC, 170, unsigned int) + +#define FB_TYPE_3D_PANEL 0x10101010 +#define MDP_IMGTYPE2_START 0x10000 +#define MSMFB_DRIVER_VERSION 0xF9E8D701 + +/* HW Revisions for different MDSS targets */ +#define MDSS_GET_MAJOR(rev) ((rev) >> 28) +#define MDSS_GET_MINOR(rev) (((rev) >> 16) & 0xFFF) +#define MDSS_GET_STEP(rev) ((rev) & 0xFFFF) +#define MDSS_GET_MAJOR_MINOR(rev) ((rev) >> 16) + +#define IS_MDSS_MAJOR_MINOR_SAME(rev1, rev2) \ + (MDSS_GET_MAJOR_MINOR((rev1)) == MDSS_GET_MAJOR_MINOR((rev2))) + +#define MDSS_MDP_REV(major, minor, step) \ + ((((major) & 0x000F) << 28) | \ + (((minor) & 0x0FFF) << 16) | \ + ((step) & 0xFFFF)) + +#define MDSS_MDP_HW_REV_100 MDSS_MDP_REV(1, 0, 0) /* 8974 v1.0 */ +#define MDSS_MDP_HW_REV_101 MDSS_MDP_REV(1, 1, 0) /* 8x26 v1.0 */ +#define MDSS_MDP_HW_REV_101_1 MDSS_MDP_REV(1, 1, 1) /* 8x26 v2.0, 8926 v1.0 */ +#define MDSS_MDP_HW_REV_101_2 MDSS_MDP_REV(1, 1, 2) /* 8926 v2.0 */ +#define MDSS_MDP_HW_REV_102 MDSS_MDP_REV(1, 2, 0) /* 8974 v2.0 */ +#define MDSS_MDP_HW_REV_102_1 MDSS_MDP_REV(1, 2, 1) /* 8974 v3.0 (Pro) */ +#define MDSS_MDP_HW_REV_103 MDSS_MDP_REV(1, 3, 0) /* 8084 v1.0 */ +#define MDSS_MDP_HW_REV_103_1 MDSS_MDP_REV(1, 3, 1) /* 8084 v1.1 */ +#define MDSS_MDP_HW_REV_105 MDSS_MDP_REV(1, 5, 0) /* 8994 v1.0 */ +#define MDSS_MDP_HW_REV_106 MDSS_MDP_REV(1, 6, 0) /* 8916 v1.0 */ +#define MDSS_MDP_HW_REV_107 MDSS_MDP_REV(1, 7, 0) +#define MDSS_MDP_HW_REV_108 MDSS_MDP_REV(1, 8, 0) /* 8939 v1.0 */ +#define MDSS_MDP_HW_REV_109 MDSS_MDP_REV(1, 9, 0) /* 8994 v2.0 */ +#define MDSS_MDP_HW_REV_110 MDSS_MDP_REV(1, 10, 0) /* 8992 v1.0 */ +#define MDSS_MDP_HW_REV_200 MDSS_MDP_REV(2, 0, 0) /* 8092 v1.0 */ + +enum { + NOTIFY_UPDATE_START, + NOTIFY_UPDATE_STOP, + NOTIFY_UPDATE_POWER_OFF, +}; + +enum { + NOTIFY_TYPE_NO_UPDATE, + NOTIFY_TYPE_SUSPEND, + NOTIFY_TYPE_UPDATE, + NOTIFY_TYPE_BL_UPDATE, +}; + +enum { + MDP_RGB_565, /* RGB 565 planer */ + MDP_XRGB_8888, /* RGB 888 padded */ + MDP_Y_CBCR_H2V2, /* Y and CbCr, pseudo planer w/ Cb is in MSB */ + MDP_Y_CBCR_H2V2_ADRENO, + MDP_ARGB_8888, /* ARGB 888 */ + MDP_RGB_888, /* RGB 888 planer */ + MDP_Y_CRCB_H2V2, /* Y and CrCb, pseudo planer w/ Cr is in MSB */ + MDP_YCRYCB_H2V1, /* YCrYCb interleave */ + MDP_CBYCRY_H2V1, /* CbYCrY interleave */ + MDP_Y_CRCB_H2V1, /* Y and CrCb, pseduo planer w/ Cr is in MSB */ + MDP_Y_CBCR_H2V1, /* Y and CrCb, pseduo planer w/ Cr is in MSB */ + MDP_Y_CRCB_H1V2, + MDP_Y_CBCR_H1V2, + MDP_RGBA_8888, /* ARGB 888 */ + MDP_BGRA_8888, /* ABGR 888 */ + MDP_RGBX_8888, /* RGBX 888 */ + MDP_Y_CRCB_H2V2_TILE, /* Y and CrCb, pseudo planer tile */ + MDP_Y_CBCR_H2V2_TILE, /* Y and CbCr, pseudo planer tile */ + MDP_Y_CR_CB_H2V2, /* Y, Cr and Cb, planar */ + MDP_Y_CR_CB_GH2V2, /* Y, Cr and Cb, planar aligned to Android YV12 */ + MDP_Y_CB_CR_H2V2, /* Y, Cb and Cr, planar */ + MDP_Y_CRCB_H1V1, /* Y and CrCb, pseduo planer w/ Cr is in MSB */ + MDP_Y_CBCR_H1V1, /* Y and CbCr, pseduo planer w/ Cb is in MSB */ + MDP_YCRCB_H1V1, /* YCrCb interleave */ + MDP_YCBCR_H1V1, /* YCbCr interleave */ + MDP_BGR_565, /* BGR 565 planer */ + MDP_BGR_888, /* BGR 888 */ + MDP_Y_CBCR_H2V2_VENUS, + MDP_BGRX_8888, /* BGRX 8888 */ + MDP_RGBA_8888_TILE, /* RGBA 8888 in tile format */ + MDP_ARGB_8888_TILE, /* ARGB 8888 in tile format */ + MDP_ABGR_8888_TILE, /* ABGR 8888 in tile format */ + MDP_BGRA_8888_TILE, /* BGRA 8888 in tile format */ + MDP_RGBX_8888_TILE, /* RGBX 8888 in tile format */ + MDP_XRGB_8888_TILE, /* XRGB 8888 in tile format */ + MDP_XBGR_8888_TILE, /* XBGR 8888 in tile format */ + MDP_BGRX_8888_TILE, /* BGRX 8888 in tile format */ + MDP_YCBYCR_H2V1, /* YCbYCr interleave */ + MDP_RGB_565_TILE, /* RGB 565 in tile format */ + MDP_BGR_565_TILE, /* BGR 565 in tile format */ + MDP_ARGB_1555, /*ARGB 1555*/ + MDP_RGBA_5551, /*RGBA 5551*/ + MDP_ARGB_4444, /*ARGB 4444*/ + MDP_RGBA_4444, /*RGBA 4444*/ + MDP_RGB_565_UBWC, + MDP_RGBA_8888_UBWC, + MDP_Y_CBCR_H2V2_UBWC, + MDP_IMGTYPE_LIMIT, + MDP_RGB_BORDERFILL, /* border fill pipe */ + MDP_FB_FORMAT = MDP_IMGTYPE2_START, /* framebuffer format */ + MDP_IMGTYPE_LIMIT2 /* Non valid image type after this enum */ +}; + +enum { + PMEM_IMG, + FB_IMG, +}; + +enum { + HSIC_HUE = 0, + HSIC_SAT, + HSIC_INT, + HSIC_CON, + NUM_HSIC_PARAM, +}; + +#define MDSS_MDP_ROT_ONLY 0x80 +#define MDSS_MDP_RIGHT_MIXER 0x100 +#define MDSS_MDP_DUAL_PIPE 0x200 + +/* mdp_blit_req flag values */ +#define MDP_ROT_NOP 0 +#define MDP_FLIP_LR 0x1 +#define MDP_FLIP_UD 0x2 +#define MDP_ROT_90 0x4 +#define MDP_ROT_180 (MDP_FLIP_UD|MDP_FLIP_LR) +#define MDP_ROT_270 (MDP_ROT_90|MDP_FLIP_UD|MDP_FLIP_LR) +#define MDP_DITHER 0x8 +#define MDP_BLUR 0x10 +#define MDP_BLEND_FG_PREMULT 0x20000 +#define MDP_IS_FG 0x40000 +#define MDP_SOLID_FILL 0x00000020 +#define MDP_VPU_PIPE 0x00000040 +#define MDP_DEINTERLACE 0x80000000 +#define MDP_SHARPENING 0x40000000 +#define MDP_NO_DMA_BARRIER_START 0x20000000 +#define MDP_NO_DMA_BARRIER_END 0x10000000 +#define MDP_NO_BLIT 0x08000000 +#define MDP_BLIT_WITH_DMA_BARRIERS 0x000 +#define MDP_BLIT_WITH_NO_DMA_BARRIERS \ + (MDP_NO_DMA_BARRIER_START | MDP_NO_DMA_BARRIER_END) +#define MDP_BLIT_SRC_GEM 0x04000000 +#define MDP_BLIT_DST_GEM 0x02000000 +#define MDP_BLIT_NON_CACHED 0x01000000 +#define MDP_OV_PIPE_SHARE 0x00800000 +#define MDP_DEINTERLACE_ODD 0x00400000 +#define MDP_OV_PLAY_NOWAIT 0x00200000 +#define MDP_SOURCE_ROTATED_90 0x00100000 +#define MDP_OVERLAY_PP_CFG_EN 0x00080000 +#define MDP_BACKEND_COMPOSITION 0x00040000 +#define MDP_BORDERFILL_SUPPORTED 0x00010000 +#define MDP_SECURE_OVERLAY_SESSION 0x00008000 +#define MDP_SECURE_DISPLAY_OVERLAY_SESSION 0x00002000 +#define MDP_OV_PIPE_FORCE_DMA 0x00004000 +#define MDP_MEMORY_ID_TYPE_FB 0x00001000 +#define MDP_BWC_EN 0x00000400 +#define MDP_DECIMATION_EN 0x00000800 +#define MDP_SMP_FORCE_ALLOC 0x00200000 +#define MDP_TRANSP_NOP 0xffffffff +#define MDP_ALPHA_NOP 0xff + +#define MDP_FB_PAGE_PROTECTION_NONCACHED (0) +#define MDP_FB_PAGE_PROTECTION_WRITECOMBINE (1) +#define MDP_FB_PAGE_PROTECTION_WRITETHROUGHCACHE (2) +#define MDP_FB_PAGE_PROTECTION_WRITEBACKCACHE (3) +#define MDP_FB_PAGE_PROTECTION_WRITEBACKWACACHE (4) +/* Sentinel: Don't use! */ +#define MDP_FB_PAGE_PROTECTION_INVALID (5) +/* Count of the number of MDP_FB_PAGE_PROTECTION_... values. */ +#define MDP_NUM_FB_PAGE_PROTECTION_VALUES (5) + +struct mdp_rect { + uint32_t x; + uint32_t y; + uint32_t w; + uint32_t h; +}; + +struct mdp_img { + uint32_t width; + uint32_t height; + uint32_t format; + uint32_t offset; + int memory_id; /* the file descriptor */ + uint32_t priv; +}; + +/* + * {3x3} + {3} ccs matrix + */ + +#define MDP_CCS_RGB2YUV 0 +#define MDP_CCS_YUV2RGB 1 + +#define MDP_CCS_SIZE 9 +#define MDP_BV_SIZE 3 + +struct mdp_ccs { + int direction; /* MDP_CCS_RGB2YUV or YUV2RGB */ + uint16_t ccs[MDP_CCS_SIZE]; /* 3x3 color coefficients */ + uint16_t bv[MDP_BV_SIZE]; /* 1x3 bias vector */ +}; + +struct mdp_csc { + int id; + uint32_t csc_mv[9]; + uint32_t csc_pre_bv[3]; + uint32_t csc_post_bv[3]; + uint32_t csc_pre_lv[6]; + uint32_t csc_post_lv[6]; +}; + +/* The version of the mdp_blit_req structure so that + * user applications can selectively decide which functionality + * to include + */ + +#define MDP_BLIT_REQ_VERSION 2 + +struct color { + uint32_t r; + uint32_t g; + uint32_t b; + uint32_t alpha; +}; + +struct mdp_blit_req { + struct mdp_img src; + struct mdp_img dst; + struct mdp_rect src_rect; + struct mdp_rect dst_rect; + struct color const_color; + uint32_t alpha; + uint32_t transp_mask; + uint32_t flags; + int sharpening_strength; /* -127 <--> 127, default 64 */ + uint8_t color_space; + uint32_t fps; +}; + +struct mdp_blit_req_list { + uint32_t count; + struct mdp_blit_req req[]; +}; + +#define MSMFB_DATA_VERSION 2 + +struct msmfb_data { + uint32_t offset; + int memory_id; + int id; + uint32_t flags; + uint32_t priv; + uint32_t iova; +}; + +#define MSMFB_NEW_REQUEST -1 + +struct msmfb_overlay_data { + uint32_t id; + struct msmfb_data data; + uint32_t version_key; + struct msmfb_data plane1_data; + struct msmfb_data plane2_data; + struct msmfb_data dst_data; +}; + +struct msmfb_img { + uint32_t width; + uint32_t height; + uint32_t format; +}; + +#define MSMFB_WRITEBACK_DEQUEUE_BLOCKING 0x1 +struct msmfb_writeback_data { + struct msmfb_data buf_info; + struct msmfb_img img; +}; + +#define MDP_PP_OPS_ENABLE 0x1 +#define MDP_PP_OPS_READ 0x2 +#define MDP_PP_OPS_WRITE 0x4 +#define MDP_PP_OPS_DISABLE 0x8 +#define MDP_PP_IGC_FLAG_ROM0 0x10 +#define MDP_PP_IGC_FLAG_ROM1 0x20 + +#define MDP_PP_PA_HUE_ENABLE 0x10 +#define MDP_PP_PA_SAT_ENABLE 0x20 +#define MDP_PP_PA_VAL_ENABLE 0x40 +#define MDP_PP_PA_CONT_ENABLE 0x80 +#define MDP_PP_PA_SIX_ZONE_ENABLE 0x100 +#define MDP_PP_PA_SKIN_ENABLE 0x200 +#define MDP_PP_PA_SKY_ENABLE 0x400 +#define MDP_PP_PA_FOL_ENABLE 0x800 +#define MDP_PP_PA_HUE_MASK 0x1000 +#define MDP_PP_PA_SAT_MASK 0x2000 +#define MDP_PP_PA_VAL_MASK 0x4000 +#define MDP_PP_PA_CONT_MASK 0x8000 +#define MDP_PP_PA_SIX_ZONE_HUE_MASK 0x10000 +#define MDP_PP_PA_SIX_ZONE_SAT_MASK 0x20000 +#define MDP_PP_PA_SIX_ZONE_VAL_MASK 0x40000 +#define MDP_PP_PA_MEM_COL_SKIN_MASK 0x80000 +#define MDP_PP_PA_MEM_COL_SKY_MASK 0x100000 +#define MDP_PP_PA_MEM_COL_FOL_MASK 0x200000 +#define MDP_PP_PA_MEM_PROTECT_EN 0x400000 +#define MDP_PP_PA_SAT_ZERO_EXP_EN 0x800000 + +#define MDSS_PP_DSPP_CFG 0x000 +#define MDSS_PP_SSPP_CFG 0x100 +#define MDSS_PP_LM_CFG 0x200 +#define MDSS_PP_WB_CFG 0x300 + +#define MDSS_PP_ARG_MASK 0x3C00 +#define MDSS_PP_ARG_NUM 4 +#define MDSS_PP_ARG_SHIFT 10 +#define MDSS_PP_LOCATION_MASK 0x0300 +#define MDSS_PP_LOGICAL_MASK 0x00FF + +#define MDSS_PP_ADD_ARG(var, arg) ((var) | (0x1 << (MDSS_PP_ARG_SHIFT + (arg)))) +#define PP_ARG(x, var) ((var) & (0x1 << (MDSS_PP_ARG_SHIFT + (x)))) +#define PP_LOCAT(var) ((var) & MDSS_PP_LOCATION_MASK) +#define PP_BLOCK(var) ((var) & MDSS_PP_LOGICAL_MASK) + + +struct mdp_qseed_cfg { + uint32_t table_num; + uint32_t ops; + uint32_t len; + uint32_t *data; +}; + +struct mdp_sharp_cfg { + uint32_t flags; + uint32_t strength; + uint32_t edge_thr; + uint32_t smooth_thr; + uint32_t noise_thr; +}; + +struct mdp_qseed_cfg_data { + uint32_t block; + struct mdp_qseed_cfg qseed_data; +}; + +#define MDP_OVERLAY_PP_CSC_CFG 0x1 +#define MDP_OVERLAY_PP_QSEED_CFG 0x2 +#define MDP_OVERLAY_PP_PA_CFG 0x4 +#define MDP_OVERLAY_PP_IGC_CFG 0x8 +#define MDP_OVERLAY_PP_SHARP_CFG 0x10 +#define MDP_OVERLAY_PP_HIST_CFG 0x20 +#define MDP_OVERLAY_PP_HIST_LUT_CFG 0x40 +#define MDP_OVERLAY_PP_PA_V2_CFG 0x80 + +#define MDP_CSC_FLAG_ENABLE 0x1 +#define MDP_CSC_FLAG_YUV_IN 0x2 +#define MDP_CSC_FLAG_YUV_OUT 0x4 + +struct mdp_csc_cfg { + /* flags for enable CSC, toggling RGB,YUV input/output */ + uint32_t flags; + uint32_t csc_mv[9]; + uint32_t csc_pre_bv[3]; + uint32_t csc_post_bv[3]; + uint32_t csc_pre_lv[6]; + uint32_t csc_post_lv[6]; +}; + +struct mdp_csc_cfg_data { + uint32_t block; + struct mdp_csc_cfg csc_data; +}; + +struct mdp_pa_cfg { + uint32_t flags; + uint32_t hue_adj; + uint32_t sat_adj; + uint32_t val_adj; + uint32_t cont_adj; +}; + +struct mdp_pa_mem_col_cfg { + uint32_t color_adjust_p0; + uint32_t color_adjust_p1; + uint32_t hue_region; + uint32_t sat_region; + uint32_t val_region; +}; + +#define MDP_SIX_ZONE_LUT_SIZE 384 + +struct mdp_pa_v2_data { + /* Mask bits for PA features */ + uint32_t flags; + uint32_t global_hue_adj; + uint32_t global_sat_adj; + uint32_t global_val_adj; + uint32_t global_cont_adj; + struct mdp_pa_mem_col_cfg skin_cfg; + struct mdp_pa_mem_col_cfg sky_cfg; + struct mdp_pa_mem_col_cfg fol_cfg; + uint32_t six_zone_len; + uint32_t six_zone_thresh; + uint32_t *six_zone_curve_p0; + uint32_t *six_zone_curve_p1; +}; + +struct mdp_igc_lut_data { + uint32_t block; + uint32_t len, ops; + uint32_t *c0_c1_data; + uint32_t *c2_data; +}; + +struct mdp_histogram_cfg { + uint32_t ops; + uint32_t block; + uint8_t frame_cnt; + uint8_t bit_mask; + uint16_t num_bins; +}; + +struct mdp_hist_lut_data { + uint32_t block; + uint32_t ops; + uint32_t len; + uint32_t *data; +}; + +struct mdp_overlay_pp_params { + uint32_t config_ops; + struct mdp_csc_cfg csc_cfg; + struct mdp_qseed_cfg qseed_cfg[2]; + struct mdp_pa_cfg pa_cfg; + struct mdp_pa_v2_data pa_v2_cfg; + struct mdp_igc_lut_data igc_cfg; + struct mdp_sharp_cfg sharp_cfg; + struct mdp_histogram_cfg hist_cfg; + struct mdp_hist_lut_data hist_lut_cfg; +}; + +/** + * enum mdss_mdp_blend_op - Different blend operations set by userspace + * + * @BLEND_OP_NOT_DEFINED: No blend operation defined for the layer. + * @BLEND_OP_OPAQUE: Apply a constant blend operation. The layer + * would appear opaque in case fg plane alpha is + * 0xff. + * @BLEND_OP_PREMULTIPLIED: Apply source over blend rule. Layer already has + * alpha pre-multiplication done. If fg plane alpha + * is less than 0xff, apply modulation as well. This + * operation is intended on layers having alpha + * channel. + * @BLEND_OP_COVERAGE: Apply source over blend rule. Layer is not alpha + * pre-multiplied. Apply pre-multiplication. If fg + * plane alpha is less than 0xff, apply modulation as + * well. + * @BLEND_OP_MAX: Used to track maximum blend operation possible by + * mdp. + */ +enum mdss_mdp_blend_op { + BLEND_OP_NOT_DEFINED = 0, + BLEND_OP_OPAQUE, + BLEND_OP_PREMULTIPLIED, + BLEND_OP_COVERAGE, + BLEND_OP_MAX, +}; + +#define MAX_PLANES 4 +struct mdp_scale_data { + uint8_t enable_pxl_ext; + + int init_phase_x[MAX_PLANES]; + int phase_step_x[MAX_PLANES]; + int init_phase_y[MAX_PLANES]; + int phase_step_y[MAX_PLANES]; + + int num_ext_pxls_left[MAX_PLANES]; + int num_ext_pxls_right[MAX_PLANES]; + int num_ext_pxls_top[MAX_PLANES]; + int num_ext_pxls_btm[MAX_PLANES]; + + int left_ftch[MAX_PLANES]; + int left_rpt[MAX_PLANES]; + int right_ftch[MAX_PLANES]; + int right_rpt[MAX_PLANES]; + + int top_rpt[MAX_PLANES]; + int btm_rpt[MAX_PLANES]; + int top_ftch[MAX_PLANES]; + int btm_ftch[MAX_PLANES]; + + uint32_t roi_w[MAX_PLANES]; +}; + +/** + * enum mdp_overlay_pipe_type - Different pipe type set by userspace + * + * @PIPE_TYPE_AUTO: Not specified, pipe will be selected according to flags. + * @PIPE_TYPE_VIG: VIG pipe. + * @PIPE_TYPE_RGB: RGB pipe. + * @PIPE_TYPE_DMA: DMA pipe. + * @PIPE_TYPE_CURSOR: CURSOR pipe. + * @PIPE_TYPE_MAX: Used to track maximum number of pipe type. + */ +enum mdp_overlay_pipe_type { + PIPE_TYPE_AUTO = 0, + PIPE_TYPE_VIG, + PIPE_TYPE_RGB, + PIPE_TYPE_DMA, + PIPE_TYPE_CURSOR, + PIPE_TYPE_MAX, +}; + +/** + * struct mdp_overlay - overlay surface structure + * @src: Source image information (width, height, format). + * @src_rect: Source crop rectangle, portion of image that will be fetched. + * This should always be within boundaries of source image. + * @dst_rect: Destination rectangle, the position and size of image on screen. + * This should always be within panel boundaries. + * @z_order: Blending stage to occupy in display, if multiple layers are + * present, highest z_order usually means the top most visible + * layer. The range acceptable is from 0-3 to support blending + * up to 4 layers. + * @is_fg: This flag is used to disable blending of any layers with z_order + * less than this overlay. It means that any layers with z_order + * less than this layer will not be blended and will be replaced + * by the background border color. + * @alpha: Used to set plane opacity. The range can be from 0-255, where + * 0 means completely transparent and 255 means fully opaque. + * @transp_mask: Color used as color key for transparency. Any pixel in fetched + * image matching this color will be transparent when blending. + * The color should be in same format as the source image format. + * @flags: This is used to customize operation of overlay. See MDP flags + * for more information. + * @pipe_type: Used to specify the type of overlay pipe. + * @user_data: DEPRECATED* Used to store user application specific information. + * @bg_color: Solid color used to fill the overlay surface when no source + * buffer is provided. + * @horz_deci: Horizontal decimation value, this indicates the amount of pixels + * dropped for each pixel that is fetched from a line. The value + * given should be power of two of decimation amount. + * 0: no decimation + * 1: decimate by 2 (drop 1 pixel for each pixel fetched) + * 2: decimate by 4 (drop 3 pixels for each pixel fetched) + * 3: decimate by 8 (drop 7 pixels for each pixel fetched) + * 4: decimate by 16 (drop 15 pixels for each pixel fetched) + * @vert_deci: Vertical decimation value, this indicates the amount of lines + * dropped for each line that is fetched from overlay. The value + * given should be power of two of decimation amount. + * 0: no decimation + * 1: decimation by 2 (drop 1 line for each line fetched) + * 2: decimation by 4 (drop 3 lines for each line fetched) + * 3: decimation by 8 (drop 7 lines for each line fetched) + * 4: decimation by 16 (drop 15 lines for each line fetched) + * @overlay_pp_cfg: Overlay post processing configuration, for more information + * see struct mdp_overlay_pp_params. + * @priority: Priority is returned by the driver when overlay is set for the + * first time. It indicates the priority of the underlying pipe + * serving the overlay. This priority can be used by user-space + * in source split when pipes are re-used and shuffled around to + * reduce fallbacks. + */ +struct mdp_overlay { + struct msmfb_img src; + struct mdp_rect src_rect; + struct mdp_rect dst_rect; + uint32_t z_order; /* stage number */ + uint32_t is_fg; /* control alpha & transp */ + uint32_t alpha; + uint32_t blend_op; + uint32_t transp_mask; + uint32_t flags; + uint32_t pipe_type; + uint32_t id; + uint8_t priority; + uint32_t user_data[6]; + uint32_t bg_color; + uint8_t horz_deci; + uint8_t vert_deci; + struct mdp_overlay_pp_params overlay_pp_cfg; + struct mdp_scale_data scale; + uint8_t color_space; +}; + +struct msmfb_overlay_3d { + uint32_t is_3d; + uint32_t width; + uint32_t height; +}; + + +struct msmfb_overlay_blt { + uint32_t enable; + uint32_t offset; + uint32_t width; + uint32_t height; + uint32_t bpp; +}; + +struct mdp_histogram { + uint32_t frame_cnt; + uint32_t bin_cnt; + uint32_t *r; + uint32_t *g; + uint32_t *b; +}; + +#define MISR_CRC_BATCH_SIZE 32 +enum { + DISPLAY_MISR_EDP, + DISPLAY_MISR_DSI0, + DISPLAY_MISR_DSI1, + DISPLAY_MISR_HDMI, + DISPLAY_MISR_LCDC, + DISPLAY_MISR_MDP, + DISPLAY_MISR_ATV, + DISPLAY_MISR_DSI_CMD, + DISPLAY_MISR_MAX +}; + +enum { + MISR_OP_NONE, + MISR_OP_SFM, + MISR_OP_MFM, + MISR_OP_BM, + MISR_OP_MAX +}; + +struct mdp_misr { + uint32_t block_id; + uint32_t frame_count; + uint32_t crc_op_mode; + uint32_t crc_value[MISR_CRC_BATCH_SIZE]; +}; + +/* + + mdp_block_type defines the identifiers for pipes in MDP 4.3 and up + + MDP_BLOCK_RESERVED is provided for backward compatibility and is + deprecated. It corresponds to DMA_P. So MDP_BLOCK_DMA_P should be used + instead. + + MDP_LOGICAL_BLOCK_DISP_0 identifies the display pipe which fb0 uses, + same for others. + +*/ + +enum { + MDP_BLOCK_RESERVED = 0, + MDP_BLOCK_OVERLAY_0, + MDP_BLOCK_OVERLAY_1, + MDP_BLOCK_VG_1, + MDP_BLOCK_VG_2, + MDP_BLOCK_RGB_1, + MDP_BLOCK_RGB_2, + MDP_BLOCK_DMA_P, + MDP_BLOCK_DMA_S, + MDP_BLOCK_DMA_E, + MDP_BLOCK_OVERLAY_2, + MDP_LOGICAL_BLOCK_DISP_0 = 0x10, + MDP_LOGICAL_BLOCK_DISP_1, + MDP_LOGICAL_BLOCK_DISP_2, + MDP_BLOCK_MAX, +}; + +/* + * mdp_histogram_start_req is used to provide the parameters for + * histogram start request + */ + +struct mdp_histogram_start_req { + uint32_t block; + uint8_t frame_cnt; + uint8_t bit_mask; + uint16_t num_bins; +}; + +/* + * mdp_histogram_data is used to return the histogram data, once + * the histogram is done/stopped/cance + */ + +struct mdp_histogram_data { + uint32_t block; + uint32_t bin_cnt; + uint32_t *c0; + uint32_t *c1; + uint32_t *c2; + uint32_t *extra_info; +}; + +struct mdp_pcc_coeff { + uint32_t c, r, g, b, rr, gg, bb, rg, gb, rb, rgb_0, rgb_1; +}; + +struct mdp_pcc_cfg_data { + uint32_t block; + uint32_t ops; + struct mdp_pcc_coeff r, g, b; +}; + +#define MDP_GAMUT_TABLE_NUM 8 + +enum { + mdp_lut_igc, + mdp_lut_pgc, + mdp_lut_hist, + mdp_lut_max, +}; + +struct mdp_ar_gc_lut_data { + uint32_t x_start; + uint32_t slope; + uint32_t offset; +}; + +struct mdp_pgc_lut_data { + uint32_t block; + uint32_t flags; + uint8_t num_r_stages; + uint8_t num_g_stages; + uint8_t num_b_stages; + struct mdp_ar_gc_lut_data *r_data; + struct mdp_ar_gc_lut_data *g_data; + struct mdp_ar_gc_lut_data *b_data; +}; + + +struct mdp_lut_cfg_data { + uint32_t lut_type; + union { + struct mdp_igc_lut_data igc_lut_data; + struct mdp_pgc_lut_data pgc_lut_data; + struct mdp_hist_lut_data hist_lut_data; + } data; +}; + +struct mdp_bl_scale_data { + uint32_t min_lvl; + uint32_t scale; +}; + +struct mdp_pa_cfg_data { + uint32_t block; + struct mdp_pa_cfg pa_data; +}; + +struct mdp_pa_v2_cfg_data { + uint32_t block; + struct mdp_pa_v2_data pa_v2_data; +}; + +struct mdp_dither_cfg_data { + uint32_t block; + uint32_t flags; + uint32_t g_y_depth; + uint32_t r_cr_depth; + uint32_t b_cb_depth; +}; + +struct mdp_gamut_cfg_data { + uint32_t block; + uint32_t flags; + uint32_t gamut_first; + uint32_t tbl_size[MDP_GAMUT_TABLE_NUM]; + uint16_t *r_tbl[MDP_GAMUT_TABLE_NUM]; + uint16_t *g_tbl[MDP_GAMUT_TABLE_NUM]; + uint16_t *b_tbl[MDP_GAMUT_TABLE_NUM]; +}; + +struct mdp_calib_config_data { + uint32_t ops; + uint32_t addr; + uint32_t data; +}; + +struct mdp_calib_config_buffer { + uint32_t ops; + uint32_t size; + uint32_t *buffer; +}; + +struct mdp_calib_dcm_state { + uint32_t ops; + uint32_t dcm_state; +}; + +struct mdp_pp_init_data { + uint32_t init_request; +}; + +enum { + MDP_PP_DISABLE, + MDP_PP_ENABLE, +}; + +enum { + DCM_UNINIT, + DCM_UNBLANK, + DCM_ENTER, + DCM_EXIT, + DCM_BLANK, + DTM_ENTER, + DTM_EXIT, +}; + +#define MDSS_PP_SPLIT_LEFT_ONLY 0x10000000 +#define MDSS_PP_SPLIT_RIGHT_ONLY 0x20000000 +#define MDSS_PP_SPLIT_MASK 0x30000000 + +#define MDSS_MAX_BL_BRIGHTNESS 255 +#define AD_BL_LIN_LEN 256 +#define AD_BL_ATT_LUT_LEN 33 + +#define MDSS_AD_MODE_AUTO_BL 0x0 +#define MDSS_AD_MODE_AUTO_STR 0x1 +#define MDSS_AD_MODE_TARG_STR 0x3 +#define MDSS_AD_MODE_MAN_STR 0x7 +#define MDSS_AD_MODE_CALIB 0xF + +#define MDP_PP_AD_INIT 0x10 +#define MDP_PP_AD_CFG 0x20 + +struct mdss_ad_init { + uint32_t asym_lut[33]; + uint32_t color_corr_lut[33]; + uint8_t i_control[2]; + uint16_t black_lvl; + uint16_t white_lvl; + uint8_t var; + uint8_t limit_ampl; + uint8_t i_dither; + uint8_t slope_max; + uint8_t slope_min; + uint8_t dither_ctl; + uint8_t format; + uint8_t auto_size; + uint16_t frame_w; + uint16_t frame_h; + uint8_t logo_v; + uint8_t logo_h; + uint32_t alpha; + uint32_t alpha_base; + uint32_t bl_lin_len; + uint32_t bl_att_len; + uint32_t *bl_lin; + uint32_t *bl_lin_inv; + uint32_t *bl_att_lut; +}; + +#define MDSS_AD_BL_CTRL_MODE_EN 1 +#define MDSS_AD_BL_CTRL_MODE_DIS 0 +struct mdss_ad_cfg { + uint32_t mode; + uint32_t al_calib_lut[33]; + uint16_t backlight_min; + uint16_t backlight_max; + uint16_t backlight_scale; + uint16_t amb_light_min; + uint16_t filter[2]; + uint16_t calib[4]; + uint8_t strength_limit; + uint8_t t_filter_recursion; + uint16_t stab_itr; + uint32_t bl_ctrl_mode; +}; + +/* ops uses standard MDP_PP_* flags */ +struct mdss_ad_init_cfg { + uint32_t ops; + union { + struct mdss_ad_init init; + struct mdss_ad_cfg cfg; + } params; +}; + +/* mode uses MDSS_AD_MODE_* flags */ +struct mdss_ad_input { + uint32_t mode; + union { + uint32_t amb_light; + uint32_t strength; + uint32_t calib_bl; + } in; + uint32_t output; +}; + +#define MDSS_CALIB_MODE_BL 0x1 +struct mdss_calib_cfg { + uint32_t ops; + uint32_t calib_mask; +}; + +enum { + mdp_op_pcc_cfg, + mdp_op_csc_cfg, + mdp_op_lut_cfg, + mdp_op_qseed_cfg, + mdp_bl_scale_cfg, + mdp_op_pa_cfg, + mdp_op_pa_v2_cfg, + mdp_op_dither_cfg, + mdp_op_gamut_cfg, + mdp_op_calib_cfg, + mdp_op_ad_cfg, + mdp_op_ad_input, + mdp_op_calib_mode, + mdp_op_calib_buffer, + mdp_op_calib_dcm_state, + mdp_op_max, + mdp_op_pp_init_cfg, +}; + +enum { + WB_FORMAT_NV12, + WB_FORMAT_RGB_565, + WB_FORMAT_RGB_888, + WB_FORMAT_xRGB_8888, + WB_FORMAT_ARGB_8888, + WB_FORMAT_BGRA_8888, + WB_FORMAT_BGRX_8888, + WB_FORMAT_ARGB_8888_INPUT_ALPHA /* Need to support */ +}; + +struct msmfb_mdp_pp { + uint32_t op; + union { + struct mdp_pcc_cfg_data pcc_cfg_data; + struct mdp_csc_cfg_data csc_cfg_data; + struct mdp_lut_cfg_data lut_cfg_data; + struct mdp_qseed_cfg_data qseed_cfg_data; + struct mdp_bl_scale_data bl_scale_data; + struct mdp_pa_cfg_data pa_cfg_data; + struct mdp_pa_v2_cfg_data pa_v2_cfg_data; + struct mdp_dither_cfg_data dither_cfg_data; + struct mdp_gamut_cfg_data gamut_cfg_data; + struct mdp_calib_config_data calib_cfg; + struct mdss_ad_init_cfg ad_init_cfg; + struct mdss_calib_cfg mdss_calib_cfg; + struct mdss_ad_input ad_input; + struct mdp_calib_config_buffer calib_buffer; + struct mdp_calib_dcm_state calib_dcm; + struct mdp_pp_init_data init_data; + } data; +}; + +#define FB_METADATA_VIDEO_INFO_CODE_SUPPORT 1 +enum { + metadata_op_none, + metadata_op_base_blend, + metadata_op_frame_rate, + metadata_op_vic, + metadata_op_wb_format, + metadata_op_wb_secure, + metadata_op_get_caps, + metadata_op_crc, + metadata_op_get_ion_fd, + metadata_op_max +}; + +struct mdp_blend_cfg { + uint32_t is_premultiplied; +}; + +struct mdp_mixer_cfg { + uint32_t writeback_format; + uint32_t alpha; +}; + +struct mdss_hw_caps { + uint32_t mdp_rev; + uint8_t rgb_pipes; + uint8_t vig_pipes; + uint8_t dma_pipes; + uint8_t max_smp_cnt; + uint8_t smp_per_pipe; + uint32_t features; +}; + +struct msmfb_metadata { + uint32_t op; + uint32_t flags; + union { + struct mdp_misr misr_request; + struct mdp_blend_cfg blend_cfg; + struct mdp_mixer_cfg mixer_cfg; + uint32_t panel_frame_rate; + uint32_t video_info_code; + struct mdss_hw_caps caps; + uint8_t secure_en; + int fbmem_ionfd; + } data; +}; + +#define MDP_MAX_FENCE_FD 32 +#define MDP_BUF_SYNC_FLAG_WAIT 1 +#define MDP_BUF_SYNC_FLAG_RETIRE_FENCE 0x10 + +struct mdp_buf_sync { + uint32_t flags; + uint32_t acq_fen_fd_cnt; + uint32_t session_id; + int *acq_fen_fd; + int *rel_fen_fd; + int *retire_fen_fd; +}; + +struct mdp_async_blit_req_list { + struct mdp_buf_sync sync; + uint32_t count; + struct mdp_blit_req req[]; +}; + +#define MDP_DISPLAY_COMMIT_OVERLAY 1 + +struct mdp_display_commit { + uint32_t flags; + uint32_t wait_for_finish; + struct fb_var_screeninfo var; + struct mdp_rect l_roi; + struct mdp_rect r_roi; +}; + +/** + * struct mdp_overlay_list - argument for ioctl MSMFB_OVERLAY_PREPARE + * @num_overlays: Number of overlay layers as part of the frame. + * @overlay_list: Pointer to a list of overlay structures identifying + * the layers as part of the frame + * @flags: Flags can be used to extend behavior. + * @processed_overlays: Output parameter indicating how many pipes were + * successful. If there are no errors this number should + * match num_overlays. Otherwise it will indicate the last + * successful index for overlay that couldn't be set. + */ +struct mdp_overlay_list { + uint32_t num_overlays; + struct mdp_overlay **overlay_list; + uint32_t flags; + uint32_t processed_overlays; +}; + +struct mdp_page_protection { + uint32_t page_protection; +}; + + +struct mdp_mixer_info { + int pndx; + int pnum; + int ptype; + int mixer_num; + int z_order; +}; + +#define MAX_PIPE_PER_MIXER 7 + +struct msmfb_mixer_info_req { + int mixer_num; + int cnt; + struct mdp_mixer_info info[MAX_PIPE_PER_MIXER]; +}; + +enum { + DISPLAY_SUBSYSTEM_ID, + ROTATOR_SUBSYSTEM_ID, +}; + +enum { + MDP_IOMMU_DOMAIN_CP, + MDP_IOMMU_DOMAIN_NS, +}; + +enum { + MDP_WRITEBACK_MIRROR_OFF, + MDP_WRITEBACK_MIRROR_ON, + MDP_WRITEBACK_MIRROR_PAUSE, + MDP_WRITEBACK_MIRROR_RESUME, +}; + +enum { + MDP_CSC_ITU_R_601, + MDP_CSC_ITU_R_601_FR, + MDP_CSC_ITU_R_709, +}; +#endif /*_UAPI_MSM_MDP_H_*/ diff --git a/original-kernel-headers/linux/msm_rmnet.h b/original-kernel-headers/linux/msm_rmnet.h new file mode 100644 index 0000000..6004cc2 --- /dev/null +++ b/original-kernel-headers/linux/msm_rmnet.h @@ -0,0 +1,147 @@ +#ifndef _UAPI_MSM_RMNET_H_ +#define _UAPI_MSM_RMNET_H_ + +/* Bitmap macros for RmNET driver operation mode. */ +#define RMNET_MODE_NONE (0x00) +#define RMNET_MODE_LLP_ETH (0x01) +#define RMNET_MODE_LLP_IP (0x02) +#define RMNET_MODE_QOS (0x04) +#define RMNET_MODE_MASK (RMNET_MODE_LLP_ETH | \ + RMNET_MODE_LLP_IP | \ + RMNET_MODE_QOS) + +#define RMNET_IS_MODE_QOS(mode) \ + ((mode & RMNET_MODE_QOS) == RMNET_MODE_QOS) +#define RMNET_IS_MODE_IP(mode) \ + ((mode & RMNET_MODE_LLP_IP) == RMNET_MODE_LLP_IP) + +/* IOCTL command enum + * Values chosen to not conflict with other drivers in the ecosystem */ +enum rmnet_ioctl_cmds_e { + RMNET_IOCTL_SET_LLP_ETHERNET = 0x000089F1, /* Set Ethernet protocol */ + RMNET_IOCTL_SET_LLP_IP = 0x000089F2, /* Set RAWIP protocol */ + RMNET_IOCTL_GET_LLP = 0x000089F3, /* Get link protocol */ + RMNET_IOCTL_SET_QOS_ENABLE = 0x000089F4, /* Set QoS header enabled */ + RMNET_IOCTL_SET_QOS_DISABLE = 0x000089F5, /* Set QoS header disabled*/ + RMNET_IOCTL_GET_QOS = 0x000089F6, /* Get QoS header state */ + RMNET_IOCTL_GET_OPMODE = 0x000089F7, /* Get operation mode */ + RMNET_IOCTL_OPEN = 0x000089F8, /* Open transport port */ + RMNET_IOCTL_CLOSE = 0x000089F9, /* Close transport port */ + RMNET_IOCTL_FLOW_ENABLE = 0x000089FA, /* Flow enable */ + RMNET_IOCTL_FLOW_DISABLE = 0x000089FB, /* Flow disable */ + RMNET_IOCTL_FLOW_SET_HNDL = 0x000089FC, /* Set flow handle */ + RMNET_IOCTL_EXTENDED = 0x000089FD, /* Extended IOCTLs */ + RMNET_IOCTL_MAX +}; + +enum rmnet_ioctl_extended_cmds_e { +/* RmNet Data Required IOCTLs */ + RMNET_IOCTL_GET_SUPPORTED_FEATURES = 0x0000, /* Get features */ + RMNET_IOCTL_SET_MRU = 0x0001, /* Set MRU */ + RMNET_IOCTL_GET_MRU = 0x0002, /* Get MRU */ + RMNET_IOCTL_GET_EPID = 0x0003, /* Get endpoint ID */ + RMNET_IOCTL_GET_DRIVER_NAME = 0x0004, /* Get driver name */ + RMNET_IOCTL_ADD_MUX_CHANNEL = 0x0005, /* Add MUX ID */ + RMNET_IOCTL_SET_EGRESS_DATA_FORMAT = 0x0006, /* Set EDF */ + RMNET_IOCTL_SET_INGRESS_DATA_FORMAT = 0x0007, /* Set IDF */ + RMNET_IOCTL_SET_AGGREGATION_COUNT = 0x0008, /* Set agg count */ + RMNET_IOCTL_GET_AGGREGATION_COUNT = 0x0009, /* Get agg count */ + RMNET_IOCTL_SET_AGGREGATION_SIZE = 0x000A, /* Set agg size */ + RMNET_IOCTL_GET_AGGREGATION_SIZE = 0x000B, /* Get agg size */ + RMNET_IOCTL_FLOW_CONTROL = 0x000C, /* Do flow control */ + RMNET_IOCTL_GET_DFLT_CONTROL_CHANNEL = 0x000D, /* For legacy use */ + RMNET_IOCTL_GET_HWSW_MAP = 0x000E, /* Get HW/SW map */ + RMNET_IOCTL_SET_RX_HEADROOM = 0x000F, /* RX Headroom */ + RMNET_IOCTL_GET_EP_PAIR = 0x0010, /* Endpoint pair */ + RMNET_IOCTL_SET_QOS_VERSION = 0x0011, /* 8/6 byte QoS hdr*/ + RMNET_IOCTL_GET_QOS_VERSION = 0x0012, /* 8/6 byte QoS hdr*/ + RMNET_IOCTL_GET_SUPPORTED_QOS_MODES = 0x0013, /* Get QoS modes */ + RMNET_IOCTL_SET_SLEEP_STATE = 0x0014, /* Set sleep state */ + RMNET_IOCTL_SET_XLAT_DEV_INFO = 0x0015, /* xlat dev name */ + RMNET_IOCTL_EXTENDED_MAX = 0x0016 +}; + +/* Return values for the RMNET_IOCTL_GET_SUPPORTED_FEATURES IOCTL */ +#define RMNET_IOCTL_FEAT_NOTIFY_MUX_CHANNEL (1<<0) +#define RMNET_IOCTL_FEAT_SET_EGRESS_DATA_FORMAT (1<<1) +#define RMNET_IOCTL_FEAT_SET_INGRESS_DATA_FORMAT (1<<2) +#define RMNET_IOCTL_FEAT_SET_AGGREGATION_COUNT (1<<3) +#define RMNET_IOCTL_FEAT_GET_AGGREGATION_COUNT (1<<4) +#define RMNET_IOCTL_FEAT_SET_AGGREGATION_SIZE (1<<5) +#define RMNET_IOCTL_FEAT_GET_AGGREGATION_SIZE (1<<6) +#define RMNET_IOCTL_FEAT_FLOW_CONTROL (1<<7) +#define RMNET_IOCTL_FEAT_GET_DFLT_CONTROL_CHANNEL (1<<8) +#define RMNET_IOCTL_FEAT_GET_HWSW_MAP (1<<9) + +/* Input values for the RMNET_IOCTL_SET_EGRESS_DATA_FORMAT IOCTL */ +#define RMNET_IOCTL_EGRESS_FORMAT_MAP (1<<1) +#define RMNET_IOCTL_EGRESS_FORMAT_AGGREGATION (1<<2) +#define RMNET_IOCTL_EGRESS_FORMAT_MUXING (1<<3) +#define RMNET_IOCTL_EGRESS_FORMAT_CHECKSUM (1<<4) + +/* Input values for the RMNET_IOCTL_SET_INGRESS_DATA_FORMAT IOCTL */ +#define RMNET_IOCTL_INGRESS_FORMAT_MAP (1<<1) +#define RMNET_IOCTL_INGRESS_FORMAT_DEAGGREGATION (1<<2) +#define RMNET_IOCTL_INGRESS_FORMAT_DEMUXING (1<<3) +#define RMNET_IOCTL_INGRESS_FORMAT_CHECKSUM (1<<4) + +/* User space may not have this defined. */ +#ifndef IFNAMSIZ +#define IFNAMSIZ 16 +#endif + +struct rmnet_ioctl_extended_s { + uint32_t extended_ioctl; + union { + uint32_t data; /* Generic data field for most extended IOCTLs */ + + /* Return values for + * RMNET_IOCTL_GET_DRIVER_NAME + * RMNET_IOCTL_GET_DFLT_CONTROL_CHANNEL */ + int8_t if_name[IFNAMSIZ]; + + /* Input values for the RMNET_IOCTL_ADD_MUX_CHANNEL IOCTL */ + struct { + uint32_t mux_id; + int8_t vchannel_name[IFNAMSIZ]; + } rmnet_mux_val; + + /* Input values for the RMNET_IOCTL_FLOW_CONTROL IOCTL */ + struct { + uint8_t flow_mode; + uint8_t mux_id; + } flow_control_prop; + + /* Return values for RMNET_IOCTL_GET_EP_PAIR */ + struct { + uint32_t consumer_pipe_num; + uint32_t producer_pipe_num; + } ipa_ep_pair; + } u; +}; + +struct rmnet_ioctl_data_s { + union { + uint32_t operation_mode; + uint32_t tcm_handle; + } u; +}; + +#define RMNET_IOCTL_QOS_MODE_6 (1<<0) +#define RMNET_IOCTL_QOS_MODE_8 (1<<1) + +/* QMI QoS header definition */ +#define QMI_QOS_HDR_S __attribute((__packed__)) qmi_qos_hdr_s +struct QMI_QOS_HDR_S { + unsigned char version; + unsigned char flags; + uint32_t flow_id; +}; + +/* QMI QoS 8-byte header. */ +struct qmi_qos_hdr8_s { + struct QMI_QOS_HDR_S hdr; + uint8_t reserved[2]; +} __attribute((__packed__)); + +#endif /* _UAPI_MSM_RMNET_H_ */ diff --git a/original-kernel-headers/linux/msm_rotator.h b/original-kernel-headers/linux/msm_rotator.h new file mode 100644 index 0000000..16b2490 --- /dev/null +++ b/original-kernel-headers/linux/msm_rotator.h @@ -0,0 +1,62 @@ +#ifndef _UAPI__MSM_ROTATOR_H__ +#define _UAPI__MSM_ROTATOR_H__ + +#include <linux/types.h> +#include <linux/msm_mdp.h> + +#define MSM_ROTATOR_IOCTL_MAGIC 'R' + +#define MSM_ROTATOR_IOCTL_START \ + _IOWR(MSM_ROTATOR_IOCTL_MAGIC, 1, struct msm_rotator_img_info) +#define MSM_ROTATOR_IOCTL_ROTATE \ + _IOW(MSM_ROTATOR_IOCTL_MAGIC, 2, struct msm_rotator_data_info) +#define MSM_ROTATOR_IOCTL_FINISH \ + _IOW(MSM_ROTATOR_IOCTL_MAGIC, 3, int) + +#define ROTATOR_VERSION_01 0xA5B4C301 + +enum rotator_clk_type { + ROTATOR_CORE_CLK, + ROTATOR_PCLK, + ROTATOR_IMEM_CLK +}; + +struct msm_rotator_img_info { + unsigned int session_id; + struct msmfb_img src; + struct msmfb_img dst; + struct mdp_rect src_rect; + unsigned int dst_x; + unsigned int dst_y; + unsigned char rotations; + int enable; + unsigned int downscale_ratio; + unsigned int secure; +}; + +struct msm_rotator_data_info { + int session_id; + struct msmfb_data src; + struct msmfb_data dst; + unsigned int version_key; + struct msmfb_data src_chroma; + struct msmfb_data dst_chroma; +}; + +struct msm_rot_clocks { + const char *clk_name; + enum rotator_clk_type clk_type; + unsigned int clk_rate; +}; + +struct msm_rotator_platform_data { + unsigned int number_of_clocks; + unsigned int hardware_version_number; + struct msm_rot_clocks *rotator_clks; +#ifdef CONFIG_MSM_BUS_SCALING + struct msm_bus_scale_pdata *bus_scale_table; +#endif + char rot_iommu_split_domain; +}; +#endif + diff --git a/original-kernel-headers/linux/msm_thermal_ioctl.h b/original-kernel-headers/linux/msm_thermal_ioctl.h new file mode 100644 index 0000000..6797d39 --- /dev/null +++ b/original-kernel-headers/linux/msm_thermal_ioctl.h @@ -0,0 +1,97 @@ +#ifndef _MSM_THERMAL_IOCTL_H +#define _MSM_THERMAL_IOCTL_H + +#include <linux/ioctl.h> + +#define MSM_THERMAL_IOCTL_NAME "msm_thermal_query" +#define MSM_IOCTL_FREQ_SIZE 16 + +struct __attribute__((__packed__)) cpu_freq_arg { + uint32_t cpu_num; + uint32_t freq_req; +}; + +struct __attribute__((__packed__)) clock_plan_arg { + uint32_t cluster_num; + /* + ** A value of zero for freq_table_len, will fetch the length of the + ** cluster frequency table. A non-zero value will fetch the frequency + ** table contents. + */ + uint32_t freq_table_len; + /* + ** For clusters with frequency table length greater than + ** MSM_IOCTL_FREQ_SIZE, the frequency table is fetched from kernel + ** in multiple sets or iterations. The set_idx variable, + ** indicates, which set/part of frequency table the user is requesting. + ** The set index value starts from zero. A set index value of 'Z', + ** will fetch MSM_IOCTL_FREQ_SIZE or maximum available number of + ** frequency values (if it is less than MSM_IOCTL_FREQ_SIZE) + ** from the frequency table, starting from the index + ** (Z * MSM_IOCTL_FREQ_SIZE). + ** For example, in a device supporting 19 different frequencies, a set + ** index value of 0 will fetch the first 16 (MSM_IOCTL_FREQ_SIZE) + ** frequencies starting from the index 0 and a set value of 1 will fetch + ** the remaining 3 frequencies starting from the index 16. + ** A successful get, will populate the freq_table_len with the + ** number of frequency table entries fetched. + */ + uint32_t set_idx; + unsigned int freq_table[MSM_IOCTL_FREQ_SIZE]; +}; + +struct __attribute__((__packed__)) voltage_plan_arg { + uint32_t cluster_num; + uint32_t voltage_table_len; + uint32_t set_idx; + uint32_t voltage_table[MSM_IOCTL_FREQ_SIZE]; +}; + +struct __attribute__((__packed__)) msm_thermal_ioctl { + uint32_t size; + union { + struct cpu_freq_arg cpu_freq; + struct clock_plan_arg clock_freq; + struct voltage_plan_arg voltage; + }; +}; + +enum { + /*Set CPU Frequency*/ + MSM_SET_CPU_MAX_FREQ = 0x00, + MSM_SET_CPU_MIN_FREQ = 0x01, + /*Set cluster frequency*/ + MSM_SET_CLUSTER_MAX_FREQ = 0x02, + MSM_SET_CLUSTER_MIN_FREQ = 0x03, + /*Get cluster frequency plan*/ + MSM_GET_CLUSTER_FREQ_PLAN = 0x04, + /*Get cluster voltage plan */ + MSM_GET_CLUSTER_VOLTAGE_PLAN = 0x05, + MSM_CMD_MAX_NR, +}; + +#define MSM_THERMAL_MAGIC_NUM 0xCA /*Unique magic number*/ + +#define MSM_THERMAL_SET_CPU_MAX_FREQUENCY _IOW(MSM_THERMAL_MAGIC_NUM,\ + MSM_SET_CPU_MAX_FREQ, struct msm_thermal_ioctl) + +#define MSM_THERMAL_SET_CPU_MIN_FREQUENCY _IOW(MSM_THERMAL_MAGIC_NUM,\ + MSM_SET_CPU_MIN_FREQ, struct msm_thermal_ioctl) + +#define MSM_THERMAL_SET_CLUSTER_MAX_FREQUENCY _IOW(MSM_THERMAL_MAGIC_NUM,\ + MSM_SET_CLUSTER_MAX_FREQ, struct msm_thermal_ioctl) + +#define MSM_THERMAL_SET_CLUSTER_MIN_FREQUENCY _IOW(MSM_THERMAL_MAGIC_NUM,\ + MSM_SET_CLUSTER_MIN_FREQ, struct msm_thermal_ioctl) + +#define MSM_THERMAL_GET_CLUSTER_FREQUENCY_PLAN _IOR(MSM_THERMAL_MAGIC_NUM,\ + MSM_GET_CLUSTER_FREQ_PLAN, struct msm_thermal_ioctl) + +#define MSM_THERMAL_GET_CLUSTER_VOLTAGE_PLAN _IOR(MSM_THERMAL_MAGIC_NUM,\ + MSM_GET_CLUSTER_VOLTAGE_PLAN, struct msm_thermal_ioctl) +#ifdef __KERNEL__ +extern int msm_thermal_ioctl_init(void); +extern void msm_thermal_ioctl_cleanup(void); +#endif + +#endif diff --git a/original-kernel-headers/linux/msm_vidc_dec.h b/original-kernel-headers/linux/msm_vidc_dec.h new file mode 100644 index 0000000..d5c0d63 --- /dev/null +++ b/original-kernel-headers/linux/msm_vidc_dec.h @@ -0,0 +1,602 @@ +#ifndef _UAPI_MSM_VIDC_DEC_H_ +#define _UAPI_MSM_VIDC_DEC_H_ + +#include <linux/types.h> +#include <linux/ioctl.h> + +/* STATUS CODES */ +/* Base value for status codes */ +#define VDEC_S_BASE 0x40000000 +/* Success */ +#define VDEC_S_SUCCESS (VDEC_S_BASE) +/* General failure */ +#define VDEC_S_EFAIL (VDEC_S_BASE + 1) +/* Fatal irrecoverable failure. Need to tear down session. */ +#define VDEC_S_EFATAL (VDEC_S_BASE + 2) +/* Error detected in the passed parameters */ +#define VDEC_S_EBADPARAM (VDEC_S_BASE + 3) +/* Command called in invalid state. */ +#define VDEC_S_EINVALSTATE (VDEC_S_BASE + 4) + /* Insufficient OS resources - thread, memory etc. */ +#define VDEC_S_ENOSWRES (VDEC_S_BASE + 5) + /* Insufficient HW resources - core capacity maxed out. */ +#define VDEC_S_ENOHWRES (VDEC_S_BASE + 6) +/* Invalid command called */ +#define VDEC_S_EINVALCMD (VDEC_S_BASE + 7) +/* Command timeout. */ +#define VDEC_S_ETIMEOUT (VDEC_S_BASE + 8) +/* Pre-requirement is not met for API. */ +#define VDEC_S_ENOPREREQ (VDEC_S_BASE + 9) +/* Command queue is full. */ +#define VDEC_S_ECMDQFULL (VDEC_S_BASE + 10) +/* Command is not supported by this driver */ +#define VDEC_S_ENOTSUPP (VDEC_S_BASE + 11) +/* Command is not implemented by thedriver. */ +#define VDEC_S_ENOTIMPL (VDEC_S_BASE + 12) +/* Command is not implemented by the driver. */ +#define VDEC_S_BUSY (VDEC_S_BASE + 13) +#define VDEC_S_INPUT_BITSTREAM_ERR (VDEC_S_BASE + 14) + +#define VDEC_INTF_VER 1 +#define VDEC_MSG_BASE 0x0000000 +/* Codes to identify asynchronous message responses and events that driver + wants to communicate to the app.*/ +#define VDEC_MSG_INVALID (VDEC_MSG_BASE + 0) +#define VDEC_MSG_RESP_INPUT_BUFFER_DONE (VDEC_MSG_BASE + 1) +#define VDEC_MSG_RESP_OUTPUT_BUFFER_DONE (VDEC_MSG_BASE + 2) +#define VDEC_MSG_RESP_INPUT_FLUSHED (VDEC_MSG_BASE + 3) +#define VDEC_MSG_RESP_OUTPUT_FLUSHED (VDEC_MSG_BASE + 4) +#define VDEC_MSG_RESP_FLUSH_INPUT_DONE (VDEC_MSG_BASE + 5) +#define VDEC_MSG_RESP_FLUSH_OUTPUT_DONE (VDEC_MSG_BASE + 6) +#define VDEC_MSG_RESP_START_DONE (VDEC_MSG_BASE + 7) +#define VDEC_MSG_RESP_STOP_DONE (VDEC_MSG_BASE + 8) +#define VDEC_MSG_RESP_PAUSE_DONE (VDEC_MSG_BASE + 9) +#define VDEC_MSG_RESP_RESUME_DONE (VDEC_MSG_BASE + 10) +#define VDEC_MSG_RESP_RESOURCE_LOADED (VDEC_MSG_BASE + 11) +#define VDEC_EVT_RESOURCES_LOST (VDEC_MSG_BASE + 12) +#define VDEC_MSG_EVT_CONFIG_CHANGED (VDEC_MSG_BASE + 13) +#define VDEC_MSG_EVT_HW_ERROR (VDEC_MSG_BASE + 14) +#define VDEC_MSG_EVT_INFO_CONFIG_CHANGED (VDEC_MSG_BASE + 15) +#define VDEC_MSG_EVT_INFO_FIELD_DROPPED (VDEC_MSG_BASE + 16) +#define VDEC_MSG_EVT_HW_OVERLOAD (VDEC_MSG_BASE + 17) +#define VDEC_MSG_EVT_MAX_CLIENTS (VDEC_MSG_BASE + 18) +#define VDEC_MSG_EVT_HW_UNSUPPORTED (VDEC_MSG_BASE + 19) + +/*Buffer flags bits masks.*/ +#define VDEC_BUFFERFLAG_EOS 0x00000001 +#define VDEC_BUFFERFLAG_DECODEONLY 0x00000004 +#define VDEC_BUFFERFLAG_DATACORRUPT 0x00000008 +#define VDEC_BUFFERFLAG_ENDOFFRAME 0x00000010 +#define VDEC_BUFFERFLAG_SYNCFRAME 0x00000020 +#define VDEC_BUFFERFLAG_EXTRADATA 0x00000040 +#define VDEC_BUFFERFLAG_CODECCONFIG 0x00000080 + +/*Post processing flags bit masks*/ +#define VDEC_EXTRADATA_NONE 0x001 +#define VDEC_EXTRADATA_QP 0x004 +#define VDEC_EXTRADATA_MB_ERROR_MAP 0x008 +#define VDEC_EXTRADATA_SEI 0x010 +#define VDEC_EXTRADATA_VUI 0x020 +#define VDEC_EXTRADATA_VC1 0x040 + +#define VDEC_EXTRADATA_EXT_DATA 0x0800 +#define VDEC_EXTRADATA_USER_DATA 0x1000 +#define VDEC_EXTRADATA_EXT_BUFFER 0x2000 + +#define VDEC_CMDBASE 0x800 +#define VDEC_CMD_SET_INTF_VERSION (VDEC_CMDBASE) + +#define VDEC_IOCTL_MAGIC 'v' + +struct vdec_ioctl_msg { + void __user *in; + void __user *out; +}; + +/* CMD params: InputParam:enum vdec_codec + OutputParam: struct vdec_profile_level*/ +#define VDEC_IOCTL_GET_PROFILE_LEVEL_SUPPORTED \ + _IOWR(VDEC_IOCTL_MAGIC, 0, struct vdec_ioctl_msg) + +/*CMD params:InputParam: NULL + OutputParam: uint32_t(bitmask)*/ +#define VDEC_IOCTL_GET_INTERLACE_FORMAT \ + _IOR(VDEC_IOCTL_MAGIC, 1, struct vdec_ioctl_msg) + +/* CMD params: InputParam: enum vdec_codec + OutputParam: struct vdec_profile_level*/ +#define VDEC_IOCTL_GET_CURRENT_PROFILE_LEVEL \ + _IOWR(VDEC_IOCTL_MAGIC, 2, struct vdec_ioctl_msg) + +/*CMD params: SET: InputParam: enum vdec_output_fromat OutputParam: NULL + GET: InputParam: NULL OutputParam: enum vdec_output_fromat*/ +#define VDEC_IOCTL_SET_OUTPUT_FORMAT \ + _IOWR(VDEC_IOCTL_MAGIC, 3, struct vdec_ioctl_msg) +#define VDEC_IOCTL_GET_OUTPUT_FORMAT \ + _IOWR(VDEC_IOCTL_MAGIC, 4, struct vdec_ioctl_msg) + +/*CMD params: SET: InputParam: enum vdec_codec OutputParam: NULL + GET: InputParam: NULL OutputParam: enum vdec_codec*/ +#define VDEC_IOCTL_SET_CODEC \ + _IOW(VDEC_IOCTL_MAGIC, 5, struct vdec_ioctl_msg) +#define VDEC_IOCTL_GET_CODEC \ + _IOR(VDEC_IOCTL_MAGIC, 6, struct vdec_ioctl_msg) + +/*CMD params: SET: InputParam: struct vdec_picsize outputparam: NULL + GET: InputParam: NULL outputparam: struct vdec_picsize*/ +#define VDEC_IOCTL_SET_PICRES \ + _IOW(VDEC_IOCTL_MAGIC, 7, struct vdec_ioctl_msg) +#define VDEC_IOCTL_GET_PICRES \ + _IOR(VDEC_IOCTL_MAGIC, 8, struct vdec_ioctl_msg) + +#define VDEC_IOCTL_SET_EXTRADATA \ + _IOW(VDEC_IOCTL_MAGIC, 9, struct vdec_ioctl_msg) +#define VDEC_IOCTL_GET_EXTRADATA \ + _IOR(VDEC_IOCTL_MAGIC, 10, struct vdec_ioctl_msg) + +#define VDEC_IOCTL_SET_SEQUENCE_HEADER \ + _IOW(VDEC_IOCTL_MAGIC, 11, struct vdec_ioctl_msg) + +/* CMD params: SET: InputParam - vdec_allocatorproperty, OutputParam - NULL + GET: InputParam - NULL, OutputParam - vdec_allocatorproperty*/ +#define VDEC_IOCTL_SET_BUFFER_REQ \ + _IOW(VDEC_IOCTL_MAGIC, 12, struct vdec_ioctl_msg) +#define VDEC_IOCTL_GET_BUFFER_REQ \ + _IOR(VDEC_IOCTL_MAGIC, 13, struct vdec_ioctl_msg) +/* CMD params: InputParam - vdec_buffer, OutputParam - uint8_t** */ +#define VDEC_IOCTL_ALLOCATE_BUFFER \ + _IOWR(VDEC_IOCTL_MAGIC, 14, struct vdec_ioctl_msg) +/* CMD params: InputParam - uint8_t *, OutputParam - NULL.*/ +#define VDEC_IOCTL_FREE_BUFFER \ + _IOW(VDEC_IOCTL_MAGIC, 15, struct vdec_ioctl_msg) + +/*CMD params: CMD: InputParam - struct vdec_setbuffer_cmd, OutputParam - NULL*/ +#define VDEC_IOCTL_SET_BUFFER \ + _IOW(VDEC_IOCTL_MAGIC, 16, struct vdec_ioctl_msg) + +/* CMD params: InputParam - struct vdec_fillbuffer_cmd, OutputParam - NULL*/ +#define VDEC_IOCTL_FILL_OUTPUT_BUFFER \ + _IOW(VDEC_IOCTL_MAGIC, 17, struct vdec_ioctl_msg) + +/*CMD params: InputParam - struct vdec_frameinfo , OutputParam - NULL*/ +#define VDEC_IOCTL_DECODE_FRAME \ + _IOW(VDEC_IOCTL_MAGIC, 18, struct vdec_ioctl_msg) + +#define VDEC_IOCTL_LOAD_RESOURCES _IO(VDEC_IOCTL_MAGIC, 19) +#define VDEC_IOCTL_CMD_START _IO(VDEC_IOCTL_MAGIC, 20) +#define VDEC_IOCTL_CMD_STOP _IO(VDEC_IOCTL_MAGIC, 21) +#define VDEC_IOCTL_CMD_PAUSE _IO(VDEC_IOCTL_MAGIC, 22) +#define VDEC_IOCTL_CMD_RESUME _IO(VDEC_IOCTL_MAGIC, 23) + +/*CMD params: InputParam - enum vdec_bufferflush , OutputParam - NULL */ +#define VDEC_IOCTL_CMD_FLUSH _IOW(VDEC_IOCTL_MAGIC, 24, struct vdec_ioctl_msg) + +/* ======================================================== + * IOCTL for getting asynchronous notification from driver + * ========================================================*/ + +/*IOCTL params: InputParam - NULL, OutputParam - struct vdec_msginfo*/ +#define VDEC_IOCTL_GET_NEXT_MSG \ + _IOR(VDEC_IOCTL_MAGIC, 25, struct vdec_ioctl_msg) + +#define VDEC_IOCTL_STOP_NEXT_MSG _IO(VDEC_IOCTL_MAGIC, 26) + +#define VDEC_IOCTL_GET_NUMBER_INSTANCES \ + _IOR(VDEC_IOCTL_MAGIC, 27, struct vdec_ioctl_msg) + +#define VDEC_IOCTL_SET_PICTURE_ORDER \ + _IOW(VDEC_IOCTL_MAGIC, 28, struct vdec_ioctl_msg) + +#define VDEC_IOCTL_SET_FRAME_RATE \ + _IOW(VDEC_IOCTL_MAGIC, 29, struct vdec_ioctl_msg) + +#define VDEC_IOCTL_SET_H264_MV_BUFFER \ + _IOW(VDEC_IOCTL_MAGIC, 30, struct vdec_ioctl_msg) + +#define VDEC_IOCTL_FREE_H264_MV_BUFFER \ + _IOW(VDEC_IOCTL_MAGIC, 31, struct vdec_ioctl_msg) + +#define VDEC_IOCTL_GET_MV_BUFFER_SIZE \ + _IOR(VDEC_IOCTL_MAGIC, 32, struct vdec_ioctl_msg) + +#define VDEC_IOCTL_SET_IDR_ONLY_DECODING \ + _IO(VDEC_IOCTL_MAGIC, 33) + +#define VDEC_IOCTL_SET_CONT_ON_RECONFIG \ + _IO(VDEC_IOCTL_MAGIC, 34) + +#define VDEC_IOCTL_SET_DISABLE_DMX \ + _IOW(VDEC_IOCTL_MAGIC, 35, struct vdec_ioctl_msg) + +#define VDEC_IOCTL_GET_DISABLE_DMX \ + _IOR(VDEC_IOCTL_MAGIC, 36, struct vdec_ioctl_msg) + +#define VDEC_IOCTL_GET_DISABLE_DMX_SUPPORT \ + _IOR(VDEC_IOCTL_MAGIC, 37, struct vdec_ioctl_msg) + +#define VDEC_IOCTL_SET_PERF_CLK \ + _IOR(VDEC_IOCTL_MAGIC, 38, struct vdec_ioctl_msg) + +#define VDEC_IOCTL_SET_META_BUFFERS \ + _IOW(VDEC_IOCTL_MAGIC, 39, struct vdec_ioctl_msg) + +#define VDEC_IOCTL_FREE_META_BUFFERS \ + _IO(VDEC_IOCTL_MAGIC, 40) + +enum vdec_picture { + PICTURE_TYPE_I, + PICTURE_TYPE_P, + PICTURE_TYPE_B, + PICTURE_TYPE_BI, + PICTURE_TYPE_SKIP, + PICTURE_TYPE_IDR, + PICTURE_TYPE_UNKNOWN +}; + +enum vdec_buffer { + VDEC_BUFFER_TYPE_INPUT, + VDEC_BUFFER_TYPE_OUTPUT +}; + +struct vdec_allocatorproperty { + enum vdec_buffer buffer_type; + uint32_t mincount; + uint32_t maxcount; + uint32_t actualcount; + size_t buffer_size; + uint32_t alignment; + uint32_t buf_poolid; + size_t meta_buffer_size; +}; + +struct vdec_bufferpayload { + void __user *bufferaddr; + size_t buffer_len; + int pmem_fd; + size_t offset; + size_t mmaped_size; +}; + +struct vdec_setbuffer_cmd { + enum vdec_buffer buffer_type; + struct vdec_bufferpayload buffer; +}; + +struct vdec_fillbuffer_cmd { + struct vdec_bufferpayload buffer; + void *client_data; +}; + +enum vdec_bufferflush { + VDEC_FLUSH_TYPE_INPUT, + VDEC_FLUSH_TYPE_OUTPUT, + VDEC_FLUSH_TYPE_ALL +}; + +enum vdec_codec { + VDEC_CODECTYPE_H264 = 0x1, + VDEC_CODECTYPE_H263 = 0x2, + VDEC_CODECTYPE_MPEG4 = 0x3, + VDEC_CODECTYPE_DIVX_3 = 0x4, + VDEC_CODECTYPE_DIVX_4 = 0x5, + VDEC_CODECTYPE_DIVX_5 = 0x6, + VDEC_CODECTYPE_DIVX_6 = 0x7, + VDEC_CODECTYPE_XVID = 0x8, + VDEC_CODECTYPE_MPEG1 = 0x9, + VDEC_CODECTYPE_MPEG2 = 0xa, + VDEC_CODECTYPE_VC1 = 0xb, + VDEC_CODECTYPE_VC1_RCV = 0xc, + VDEC_CODECTYPE_HEVC = 0xd, + VDEC_CODECTYPE_MVC = 0xe, +}; + +enum vdec_mpeg2_profile { + VDEC_MPEG2ProfileSimple = 0x1, + VDEC_MPEG2ProfileMain = 0x2, + VDEC_MPEG2Profile422 = 0x4, + VDEC_MPEG2ProfileSNR = 0x8, + VDEC_MPEG2ProfileSpatial = 0x10, + VDEC_MPEG2ProfileHigh = 0x20, + VDEC_MPEG2ProfileKhronosExtensions = 0x6F000000, + VDEC_MPEG2ProfileVendorStartUnused = 0x7F000000, + VDEC_MPEG2ProfileMax = 0x7FFFFFFF +}; + +enum vdec_mpeg2_level { + + VDEC_MPEG2LevelLL = 0x1, + VDEC_MPEG2LevelML = 0x2, + VDEC_MPEG2LevelH14 = 0x4, + VDEC_MPEG2LevelHL = 0x8, + VDEC_MPEG2LevelKhronosExtensions = 0x6F000000, + VDEC_MPEG2LevelVendorStartUnused = 0x7F000000, + VDEC_MPEG2LevelMax = 0x7FFFFFFF +}; + +enum vdec_mpeg4_profile { + VDEC_MPEG4ProfileSimple = 0x01, + VDEC_MPEG4ProfileSimpleScalable = 0x02, + VDEC_MPEG4ProfileCore = 0x04, + VDEC_MPEG4ProfileMain = 0x08, + VDEC_MPEG4ProfileNbit = 0x10, + VDEC_MPEG4ProfileScalableTexture = 0x20, + VDEC_MPEG4ProfileSimpleFace = 0x40, + VDEC_MPEG4ProfileSimpleFBA = 0x80, + VDEC_MPEG4ProfileBasicAnimated = 0x100, + VDEC_MPEG4ProfileHybrid = 0x200, + VDEC_MPEG4ProfileAdvancedRealTime = 0x400, + VDEC_MPEG4ProfileCoreScalable = 0x800, + VDEC_MPEG4ProfileAdvancedCoding = 0x1000, + VDEC_MPEG4ProfileAdvancedCore = 0x2000, + VDEC_MPEG4ProfileAdvancedScalable = 0x4000, + VDEC_MPEG4ProfileAdvancedSimple = 0x8000, + VDEC_MPEG4ProfileKhronosExtensions = 0x6F000000, + VDEC_MPEG4ProfileVendorStartUnused = 0x7F000000, + VDEC_MPEG4ProfileMax = 0x7FFFFFFF +}; + +enum vdec_mpeg4_level { + VDEC_MPEG4Level0 = 0x01, + VDEC_MPEG4Level0b = 0x02, + VDEC_MPEG4Level1 = 0x04, + VDEC_MPEG4Level2 = 0x08, + VDEC_MPEG4Level3 = 0x10, + VDEC_MPEG4Level4 = 0x20, + VDEC_MPEG4Level4a = 0x40, + VDEC_MPEG4Level5 = 0x80, + VDEC_MPEG4LevelKhronosExtensions = 0x6F000000, + VDEC_MPEG4LevelVendorStartUnused = 0x7F000000, + VDEC_MPEG4LevelMax = 0x7FFFFFFF +}; + +enum vdec_avc_profile { + VDEC_AVCProfileBaseline = 0x01, + VDEC_AVCProfileMain = 0x02, + VDEC_AVCProfileExtended = 0x04, + VDEC_AVCProfileHigh = 0x08, + VDEC_AVCProfileHigh10 = 0x10, + VDEC_AVCProfileHigh422 = 0x20, + VDEC_AVCProfileHigh444 = 0x40, + VDEC_AVCProfileKhronosExtensions = 0x6F000000, + VDEC_AVCProfileVendorStartUnused = 0x7F000000, + VDEC_AVCProfileMax = 0x7FFFFFFF +}; + +enum vdec_avc_level { + VDEC_AVCLevel1 = 0x01, + VDEC_AVCLevel1b = 0x02, + VDEC_AVCLevel11 = 0x04, + VDEC_AVCLevel12 = 0x08, + VDEC_AVCLevel13 = 0x10, + VDEC_AVCLevel2 = 0x20, + VDEC_AVCLevel21 = 0x40, + VDEC_AVCLevel22 = 0x80, + VDEC_AVCLevel3 = 0x100, + VDEC_AVCLevel31 = 0x200, + VDEC_AVCLevel32 = 0x400, + VDEC_AVCLevel4 = 0x800, + VDEC_AVCLevel41 = 0x1000, + VDEC_AVCLevel42 = 0x2000, + VDEC_AVCLevel5 = 0x4000, + VDEC_AVCLevel51 = 0x8000, + VDEC_AVCLevelKhronosExtensions = 0x6F000000, + VDEC_AVCLevelVendorStartUnused = 0x7F000000, + VDEC_AVCLevelMax = 0x7FFFFFFF +}; + +enum vdec_divx_profile { + VDEC_DIVXProfile_qMobile = 0x01, + VDEC_DIVXProfile_Mobile = 0x02, + VDEC_DIVXProfile_HD = 0x04, + VDEC_DIVXProfile_Handheld = 0x08, + VDEC_DIVXProfile_Portable = 0x10, + VDEC_DIVXProfile_HomeTheater = 0x20 +}; + +enum vdec_xvid_profile { + VDEC_XVIDProfile_Simple = 0x1, + VDEC_XVIDProfile_Advanced_Realtime_Simple = 0x2, + VDEC_XVIDProfile_Advanced_Simple = 0x4 +}; + +enum vdec_xvid_level { + VDEC_XVID_LEVEL_S_L0 = 0x1, + VDEC_XVID_LEVEL_S_L1 = 0x2, + VDEC_XVID_LEVEL_S_L2 = 0x4, + VDEC_XVID_LEVEL_S_L3 = 0x8, + VDEC_XVID_LEVEL_ARTS_L1 = 0x10, + VDEC_XVID_LEVEL_ARTS_L2 = 0x20, + VDEC_XVID_LEVEL_ARTS_L3 = 0x40, + VDEC_XVID_LEVEL_ARTS_L4 = 0x80, + VDEC_XVID_LEVEL_AS_L0 = 0x100, + VDEC_XVID_LEVEL_AS_L1 = 0x200, + VDEC_XVID_LEVEL_AS_L2 = 0x400, + VDEC_XVID_LEVEL_AS_L3 = 0x800, + VDEC_XVID_LEVEL_AS_L4 = 0x1000 +}; + +enum vdec_h263profile { + VDEC_H263ProfileBaseline = 0x01, + VDEC_H263ProfileH320Coding = 0x02, + VDEC_H263ProfileBackwardCompatible = 0x04, + VDEC_H263ProfileISWV2 = 0x08, + VDEC_H263ProfileISWV3 = 0x10, + VDEC_H263ProfileHighCompression = 0x20, + VDEC_H263ProfileInternet = 0x40, + VDEC_H263ProfileInterlace = 0x80, + VDEC_H263ProfileHighLatency = 0x100, + VDEC_H263ProfileKhronosExtensions = 0x6F000000, + VDEC_H263ProfileVendorStartUnused = 0x7F000000, + VDEC_H263ProfileMax = 0x7FFFFFFF +}; + +enum vdec_h263level { + VDEC_H263Level10 = 0x01, + VDEC_H263Level20 = 0x02, + VDEC_H263Level30 = 0x04, + VDEC_H263Level40 = 0x08, + VDEC_H263Level45 = 0x10, + VDEC_H263Level50 = 0x20, + VDEC_H263Level60 = 0x40, + VDEC_H263Level70 = 0x80, + VDEC_H263LevelKhronosExtensions = 0x6F000000, + VDEC_H263LevelVendorStartUnused = 0x7F000000, + VDEC_H263LevelMax = 0x7FFFFFFF +}; + +enum vdec_wmv_format { + VDEC_WMVFormatUnused = 0x01, + VDEC_WMVFormat7 = 0x02, + VDEC_WMVFormat8 = 0x04, + VDEC_WMVFormat9 = 0x08, + VDEC_WMFFormatKhronosExtensions = 0x6F000000, + VDEC_WMFFormatVendorStartUnused = 0x7F000000, + VDEC_WMVFormatMax = 0x7FFFFFFF +}; + +enum vdec_vc1_profile { + VDEC_VC1ProfileSimple = 0x1, + VDEC_VC1ProfileMain = 0x2, + VDEC_VC1ProfileAdvanced = 0x4 +}; + +enum vdec_vc1_level { + VDEC_VC1_LEVEL_S_Low = 0x1, + VDEC_VC1_LEVEL_S_Medium = 0x2, + VDEC_VC1_LEVEL_M_Low = 0x4, + VDEC_VC1_LEVEL_M_Medium = 0x8, + VDEC_VC1_LEVEL_M_High = 0x10, + VDEC_VC1_LEVEL_A_L0 = 0x20, + VDEC_VC1_LEVEL_A_L1 = 0x40, + VDEC_VC1_LEVEL_A_L2 = 0x80, + VDEC_VC1_LEVEL_A_L3 = 0x100, + VDEC_VC1_LEVEL_A_L4 = 0x200 +}; + +struct vdec_profile_level { + uint32_t profiles; + uint32_t levels; +}; + +enum vdec_interlaced_format { + VDEC_InterlaceFrameProgressive = 0x1, + VDEC_InterlaceInterleaveFrameTopFieldFirst = 0x2, + VDEC_InterlaceInterleaveFrameBottomFieldFirst = 0x4 +}; + +enum vdec_output_fromat { + VDEC_YUV_FORMAT_NV12 = 0x1, + VDEC_YUV_FORMAT_TILE_4x2 = 0x2 +}; + +enum vdec_output_order { + VDEC_ORDER_DISPLAY = 0x1, + VDEC_ORDER_DECODE = 0x2 +}; + +struct vdec_picsize { + uint32_t frame_width; + uint32_t frame_height; + uint32_t stride; + uint32_t scan_lines; +}; + +struct vdec_seqheader { + void __user *ptr_seqheader; + size_t seq_header_len; + int pmem_fd; + size_t pmem_offset; +}; + +struct vdec_mberror { + void __user *ptr_errormap; + size_t err_mapsize; +}; + +struct vdec_input_frameinfo { + void __user *bufferaddr; + size_t offset; + size_t datalen; + uint32_t flags; + int64_t timestamp; + void *client_data; + int pmem_fd; + size_t pmem_offset; + void __user *desc_addr; + uint32_t desc_size; +}; + +struct vdec_framesize { + uint32_t left; + uint32_t top; + uint32_t right; + uint32_t bottom; +}; + +struct vdec_aspectratioinfo { + uint32_t aspect_ratio; + uint32_t par_width; + uint32_t par_height; +}; + +struct vdec_sep_metadatainfo { + void __user *metabufaddr; + uint32_t size; +}; + +struct vdec_output_frameinfo { + void __user *bufferaddr; + size_t offset; + size_t len; + uint32_t flags; + int64_t time_stamp; + enum vdec_picture pic_type; + void *client_data; + void *input_frame_clientdata; + struct vdec_picsize picsize; + struct vdec_framesize framesize; + enum vdec_interlaced_format interlaced_format; + struct vdec_aspectratioinfo aspect_ratio_info; + struct vdec_sep_metadatainfo metadata_info; +}; + +union vdec_msgdata { + struct vdec_output_frameinfo output_frame; + void *input_frame_clientdata; +}; + +struct vdec_msginfo { + uint32_t status_code; + uint32_t msgcode; + union vdec_msgdata msgdata; + size_t msgdatasize; +}; + +struct vdec_framerate { + unsigned long fps_denominator; + unsigned long fps_numerator; +}; + +struct vdec_h264_mv{ + size_t size; + int count; + int pmem_fd; + int offset; +}; + +struct vdec_mv_buff_size{ + int width; + int height; + int size; + int alignment; +}; + +struct vdec_meta_buffers { + size_t size; + int count; + int pmem_fd; + int pmem_fd_iommu; + int offset; +}; + +#endif /* end of macro _VDECDECODER_H_ */ diff --git a/original-kernel-headers/linux/msm_vidc_enc.h b/original-kernel-headers/linux/msm_vidc_enc.h new file mode 100644 index 0000000..c677998 --- /dev/null +++ b/original-kernel-headers/linux/msm_vidc_enc.h @@ -0,0 +1,700 @@ +#ifndef _UAPI_MSM_VIDC_ENC_H_ +#define _UAPI_MSM_VIDC_ENC_H_ + +#include <linux/types.h> +#include <linux/ioctl.h> + +/** STATUS CODES*/ +/* Base value for status codes */ +#define VEN_S_BASE 0x00000000 +#define VEN_S_SUCCESS (VEN_S_BASE)/* Success */ +#define VEN_S_EFAIL (VEN_S_BASE+1)/* General failure */ +#define VEN_S_EFATAL (VEN_S_BASE+2)/* Fatal irrecoverable failure*/ +#define VEN_S_EBADPARAM (VEN_S_BASE+3)/* Error passed parameters*/ +/*Command called in invalid state*/ +#define VEN_S_EINVALSTATE (VEN_S_BASE+4) +#define VEN_S_ENOSWRES (VEN_S_BASE+5)/* Insufficient OS resources*/ +#define VEN_S_ENOHWRES (VEN_S_BASE+6)/*Insufficient HW resources */ +#define VEN_S_EBUFFREQ (VEN_S_BASE+7)/* Buffer requirements were not met*/ +#define VEN_S_EINVALCMD (VEN_S_BASE+8)/* Invalid command called */ +#define VEN_S_ETIMEOUT (VEN_S_BASE+9)/* Command timeout. */ +/*Re-attempt was made when multiple invocation not supported for API.*/ +#define VEN_S_ENOREATMPT (VEN_S_BASE+10) +#define VEN_S_ENOPREREQ (VEN_S_BASE+11)/*Pre-requirement is not met for API*/ +#define VEN_S_ECMDQFULL (VEN_S_BASE+12)/*Command queue is full*/ +#define VEN_S_ENOTSUPP (VEN_S_BASE+13)/*Command not supported*/ +#define VEN_S_ENOTIMPL (VEN_S_BASE+14)/*Command not implemented.*/ +#define VEN_S_ENOTPMEM (VEN_S_BASE+15)/*Buffer is not from PMEM*/ +#define VEN_S_EFLUSHED (VEN_S_BASE+16)/*returned buffer was flushed*/ +#define VEN_S_EINSUFBUF (VEN_S_BASE+17)/*provided buffer size insufficient*/ +#define VEN_S_ESAMESTATE (VEN_S_BASE+18) +#define VEN_S_EINVALTRANS (VEN_S_BASE+19) + +#define VEN_INTF_VER 1 + +/*Asynchronous messages from driver*/ +#define VEN_MSG_INDICATION 0 +#define VEN_MSG_INPUT_BUFFER_DONE 1 +#define VEN_MSG_OUTPUT_BUFFER_DONE 2 +#define VEN_MSG_NEED_OUTPUT_BUFFER 3 +#define VEN_MSG_FLUSH_INPUT_DONE 4 +#define VEN_MSG_FLUSH_OUPUT_DONE 5 +#define VEN_MSG_START 6 +#define VEN_MSG_STOP 7 +#define VEN_MSG_PAUSE 8 +#define VEN_MSG_RESUME 9 +#define VEN_MSG_STOP_READING_MSG 10 +#define VEN_MSG_LTRUSE_FAILED 11 +#define VEN_MSG_HW_OVERLOAD 12 +#define VEN_MSG_MAX_CLIENTS 13 + + +/*Buffer flags bits masks*/ +#define VEN_BUFFLAG_EOS 0x00000001 +#define VEN_BUFFLAG_ENDOFFRAME 0x00000010 +#define VEN_BUFFLAG_SYNCFRAME 0x00000020 +#define VEN_BUFFLAG_EXTRADATA 0x00000040 +#define VEN_BUFFLAG_CODECCONFIG 0x00000080 + +/*Post processing flags bit masks*/ +#define VEN_EXTRADATA_NONE 0x001 +#define VEN_EXTRADATA_QCOMFILLER 0x002 +#define VEN_EXTRADATA_SLICEINFO 0x100 +#define VEN_EXTRADATA_LTRINFO 0x200 +#define VEN_EXTRADATA_MBINFO 0x400 + +/*ENCODER CONFIGURATION CONSTANTS*/ + +/*Encoded video frame types*/ +#define VEN_FRAME_TYPE_I 1/* I frame type */ +#define VEN_FRAME_TYPE_P 2/* P frame type */ +#define VEN_FRAME_TYPE_B 3/* B frame type */ + +/*Video codec types*/ +#define VEN_CODEC_MPEG4 1/* MPEG4 Codec */ +#define VEN_CODEC_H264 2/* H.264 Codec */ +#define VEN_CODEC_H263 3/* H.263 Codec */ + +/*Video codec profile types.*/ +#define VEN_PROFILE_MPEG4_SP 1/* 1 - MPEG4 SP profile */ +#define VEN_PROFILE_MPEG4_ASP 2/* 2 - MPEG4 ASP profile */ +#define VEN_PROFILE_H264_BASELINE 3/* 3 - H264 Baseline profile */ +#define VEN_PROFILE_H264_MAIN 4/* 4 - H264 Main profile */ +#define VEN_PROFILE_H264_HIGH 5/* 5 - H264 High profile */ +#define VEN_PROFILE_H263_BASELINE 6/* 6 - H263 Baseline profile */ + +/*Video codec profile level types.*/ +#define VEN_LEVEL_MPEG4_0 0x1/* MPEG4 Level 0 */ +#define VEN_LEVEL_MPEG4_1 0x2/* MPEG4 Level 1 */ +#define VEN_LEVEL_MPEG4_2 0x3/* MPEG4 Level 2 */ +#define VEN_LEVEL_MPEG4_3 0x4/* MPEG4 Level 3 */ +#define VEN_LEVEL_MPEG4_4 0x5/* MPEG4 Level 4 */ +#define VEN_LEVEL_MPEG4_5 0x6/* MPEG4 Level 5 */ +#define VEN_LEVEL_MPEG4_3b 0x7/* MPEG4 Level 3b */ +#define VEN_LEVEL_MPEG4_6 0x8/* MPEG4 Level 6 */ + +#define VEN_LEVEL_H264_1 0x9/* H.264 Level 1 */ +#define VEN_LEVEL_H264_1b 0xA/* H.264 Level 1b */ +#define VEN_LEVEL_H264_1p1 0xB/* H.264 Level 1.1 */ +#define VEN_LEVEL_H264_1p2 0xC/* H.264 Level 1.2 */ +#define VEN_LEVEL_H264_1p3 0xD/* H.264 Level 1.3 */ +#define VEN_LEVEL_H264_2 0xE/* H.264 Level 2 */ +#define VEN_LEVEL_H264_2p1 0xF/* H.264 Level 2.1 */ +#define VEN_LEVEL_H264_2p2 0x10/* H.264 Level 2.2 */ +#define VEN_LEVEL_H264_3 0x11/* H.264 Level 3 */ +#define VEN_LEVEL_H264_3p1 0x12/* H.264 Level 3.1 */ +#define VEN_LEVEL_H264_3p2 0x13/* H.264 Level 3.2 */ +#define VEN_LEVEL_H264_4 0x14/* H.264 Level 4 */ + +#define VEN_LEVEL_H263_10 0x15/* H.263 Level 10 */ +#define VEN_LEVEL_H263_20 0x16/* H.263 Level 20 */ +#define VEN_LEVEL_H263_30 0x17/* H.263 Level 30 */ +#define VEN_LEVEL_H263_40 0x18/* H.263 Level 40 */ +#define VEN_LEVEL_H263_45 0x19/* H.263 Level 45 */ +#define VEN_LEVEL_H263_50 0x1A/* H.263 Level 50 */ +#define VEN_LEVEL_H263_60 0x1B/* H.263 Level 60 */ +#define VEN_LEVEL_H263_70 0x1C/* H.263 Level 70 */ + +/*Entropy coding model selection for H.264 encoder.*/ +#define VEN_ENTROPY_MODEL_CAVLC 1 +#define VEN_ENTROPY_MODEL_CABAC 2 +/*Cabac model number (0,1,2) for encoder.*/ +#define VEN_CABAC_MODEL_0 1/* CABAC Model 0. */ +#define VEN_CABAC_MODEL_1 2/* CABAC Model 1. */ +#define VEN_CABAC_MODEL_2 3/* CABAC Model 2. */ + +/*Deblocking filter control type for encoder.*/ +#define VEN_DB_DISABLE 1/* 1 - Disable deblocking filter*/ +#define VEN_DB_ALL_BLKG_BNDRY 2/* 2 - All blocking boundary filtering*/ +#define VEN_DB_SKIP_SLICE_BNDRY 3/* 3 - Filtering except sliceboundary*/ + +/*Different methods of Multi slice selection.*/ +#define VEN_MSLICE_OFF 1 +#define VEN_MSLICE_CNT_MB 2 /*number of MBscount per slice*/ +#define VEN_MSLICE_CNT_BYTE 3 /*number of bytes count per slice.*/ +#define VEN_MSLICE_GOB 4 /*Multi slice by GOB for H.263 only.*/ + +/*Different modes for Rate Control.*/ +#define VEN_RC_OFF 1 +#define VEN_RC_VBR_VFR 2 +#define VEN_RC_VBR_CFR 3 +#define VEN_RC_CBR_VFR 4 +#define VEN_RC_CBR_CFR 5 + +/*Different modes for flushing buffers*/ +#define VEN_FLUSH_INPUT 1 +#define VEN_FLUSH_OUTPUT 2 +#define VEN_FLUSH_ALL 3 + +/*Different input formats for YUV data.*/ +#define VEN_INPUTFMT_NV12 1/* NV12 Linear */ +#define VEN_INPUTFMT_NV21 2/* NV21 Linear */ +#define VEN_INPUTFMT_NV12_16M2KA 3/* NV12 Linear */ + +/*Different allowed rotation modes.*/ +#define VEN_ROTATION_0 1/* 0 degrees */ +#define VEN_ROTATION_90 2/* 90 degrees */ +#define VEN_ROTATION_180 3/* 180 degrees */ +#define VEN_ROTATION_270 4/* 270 degrees */ + +/*IOCTL timeout values*/ +#define VEN_TIMEOUT_INFINITE 0xffffffff + +/*Different allowed intra refresh modes.*/ +#define VEN_IR_OFF 1 +#define VEN_IR_CYCLIC 2 +#define VEN_IR_RANDOM 3 + +/*IOCTL BASE CODES Not to be used directly by the client.*/ +/* Base value for ioctls that are not related to encoder configuration.*/ +#define VEN_IOCTLBASE_NENC 0x800 +/* Base value for encoder configuration ioctls*/ +#define VEN_IOCTLBASE_ENC 0x850 + +struct venc_ioctl_msg{ + void __user *in; + void __user *out; +}; + +/*NON ENCODER CONFIGURATION IOCTLs*/ + +/*IOCTL params:SET: InputData - unsigned long, OutputData - NULL*/ +#define VEN_IOCTL_SET_INTF_VERSION \ + _IOW(VEN_IOCTLBASE_NENC, 0, struct venc_ioctl_msg) + +/*IOCTL params:CMD: InputData - venc_timeout, OutputData - venc_msg*/ +#define VEN_IOCTL_CMD_READ_NEXT_MSG \ + _IOWR(VEN_IOCTLBASE_NENC, 1, struct venc_ioctl_msg) + +/*IOCTL params:CMD: InputData - NULL, OutputData - NULL*/ +#define VEN_IOCTL_CMD_STOP_READ_MSG _IO(VEN_IOCTLBASE_NENC, 2) + +/*IOCTL params:SET: InputData - venc_allocatorproperty, OutputData - NULL + GET: InputData - NULL, OutputData - venc_allocatorproperty*/ +#define VEN_IOCTL_SET_INPUT_BUFFER_REQ \ + _IOW(VEN_IOCTLBASE_NENC, 3, struct venc_ioctl_msg) +#define VEN_IOCTL_GET_INPUT_BUFFER_REQ \ + _IOR(VEN_IOCTLBASE_NENC, 4, struct venc_ioctl_msg) + +/*IOCTL params:CMD: InputData - venc_bufferpayload, OutputData - NULL*/ +#define VEN_IOCTL_CMD_ALLOC_INPUT_BUFFER \ + _IOW(VEN_IOCTLBASE_NENC, 5, struct venc_ioctl_msg) + +/*IOCTL params:CMD: InputData - venc_bufferpayload, OutputData - NULL*/ +#define VEN_IOCTL_SET_INPUT_BUFFER \ + _IOW(VEN_IOCTLBASE_NENC, 6, struct venc_ioctl_msg) + +/*IOCTL params: CMD: InputData - venc_bufferpayload, OutputData - NULL*/ +#define VEN_IOCTL_CMD_FREE_INPUT_BUFFER \ + _IOW(VEN_IOCTLBASE_NENC, 7, struct venc_ioctl_msg) + +/*IOCTL params:SET: InputData - venc_allocatorproperty, OutputData - NULL + GET: InputData - NULL, OutputData - venc_allocatorproperty*/ +#define VEN_IOCTL_SET_OUTPUT_BUFFER_REQ \ + _IOW(VEN_IOCTLBASE_NENC, 8, struct venc_ioctl_msg) +#define VEN_IOCTL_GET_OUTPUT_BUFFER_REQ \ + _IOR(VEN_IOCTLBASE_NENC, 9, struct venc_ioctl_msg) + +/*IOCTL params:CMD: InputData - venc_bufferpayload, OutputData - NULL*/ +#define VEN_IOCTL_CMD_ALLOC_OUTPUT_BUFFER \ + _IOW(VEN_IOCTLBASE_NENC, 10, struct venc_ioctl_msg) + + +/*IOCTL params:CMD: InputData - venc_bufferpayload, OutputData - NULL*/ +#define VEN_IOCTL_SET_OUTPUT_BUFFER \ + _IOW(VEN_IOCTLBASE_NENC, 11, struct venc_ioctl_msg) + +/*IOCTL params:CMD: InputData - venc_bufferpayload, OutputData - NULL.*/ +#define VEN_IOCTL_CMD_FREE_OUTPUT_BUFFER \ + _IOW(VEN_IOCTLBASE_NENC, 12, struct venc_ioctl_msg) + + +/* Asynchronous respone message code:* VEN_MSG_START*/ +#define VEN_IOCTL_CMD_START _IO(VEN_IOCTLBASE_NENC, 13) + + +/*IOCTL params:CMD: InputData - venc_buffer, OutputData - NULL + Asynchronous respone message code:VEN_MSG_INPUT_BUFFER_DONE*/ +#define VEN_IOCTL_CMD_ENCODE_FRAME \ + _IOW(VEN_IOCTLBASE_NENC, 14, struct venc_ioctl_msg) + + +/*IOCTL params:CMD: InputData - venc_buffer, OutputData - NULL + Asynchronous response message code:VEN_MSG_OUTPUT_BUFFER_DONE*/ +#define VEN_IOCTL_CMD_FILL_OUTPUT_BUFFER \ + _IOW(VEN_IOCTLBASE_NENC, 15, struct venc_ioctl_msg) + +/*IOCTL params:CMD: InputData - venc_bufferflush, OutputData - NULL + * Asynchronous response message code:VEN_MSG_INPUT_BUFFER_DONE*/ +#define VEN_IOCTL_CMD_FLUSH \ + _IOW(VEN_IOCTLBASE_NENC, 16, struct venc_ioctl_msg) + + +/*Asynchronous respone message code:VEN_MSG_PAUSE*/ +#define VEN_IOCTL_CMD_PAUSE _IO(VEN_IOCTLBASE_NENC, 17) + +/*Asynchronous respone message code:VEN_MSG_RESUME*/ +#define VEN_IOCTL_CMD_RESUME _IO(VEN_IOCTLBASE_NENC, 18) + +/* Asynchronous respone message code:VEN_MSG_STOP*/ +#define VEN_IOCTL_CMD_STOP _IO(VEN_IOCTLBASE_NENC, 19) + +#define VEN_IOCTL_SET_RECON_BUFFER \ + _IOW(VEN_IOCTLBASE_NENC, 20, struct venc_ioctl_msg) + +#define VEN_IOCTL_FREE_RECON_BUFFER \ + _IOW(VEN_IOCTLBASE_NENC, 21, struct venc_ioctl_msg) + +#define VEN_IOCTL_GET_RECON_BUFFER_SIZE \ + _IOW(VEN_IOCTLBASE_NENC, 22, struct venc_ioctl_msg) + + + +/*ENCODER PROPERTY CONFIGURATION & CAPABILITY IOCTLs*/ + +/*IOCTL params:SET: InputData - venc_basecfg, OutputData - NULL + GET: InputData - NULL, OutputData - venc_basecfg*/ +#define VEN_IOCTL_SET_BASE_CFG \ + _IOW(VEN_IOCTLBASE_ENC, 1, struct venc_ioctl_msg) +#define VEN_IOCTL_GET_BASE_CFG \ + _IOR(VEN_IOCTLBASE_ENC, 2, struct venc_ioctl_msg) + +/*IOCTL params:SET: InputData - venc_switch, OutputData - NULL + GET: InputData - NULL, OutputData - venc_switch*/ +#define VEN_IOCTL_SET_LIVE_MODE \ + _IOW(VEN_IOCTLBASE_ENC, 3, struct venc_ioctl_msg) +#define VEN_IOCTL_GET_LIVE_MODE \ + _IOR(VEN_IOCTLBASE_ENC, 4, struct venc_ioctl_msg) + + +/*IOCTL params:SET: InputData - venc_profile, OutputData - NULL + GET: InputData - NULL, OutputData - venc_profile*/ +#define VEN_IOCTL_SET_CODEC_PROFILE \ + _IOW(VEN_IOCTLBASE_ENC, 5, struct venc_ioctl_msg) +#define VEN_IOCTL_GET_CODEC_PROFILE \ + _IOR(VEN_IOCTLBASE_ENC, 6, struct venc_ioctl_msg) + + +/*IOCTL params:SET: InputData - ven_profilelevel, OutputData - NULL + GET: InputData - NULL, OutputData - ven_profilelevel*/ +#define VEN_IOCTL_SET_PROFILE_LEVEL \ + _IOW(VEN_IOCTLBASE_ENC, 7, struct venc_ioctl_msg) + +#define VEN_IOCTL_GET_PROFILE_LEVEL \ + _IOR(VEN_IOCTLBASE_ENC, 8, struct venc_ioctl_msg) + +/*IOCTL params:SET: InputData - venc_switch, OutputData - NULL + GET: InputData - NULL, OutputData - venc_switch*/ +#define VEN_IOCTL_SET_SHORT_HDR \ + _IOW(VEN_IOCTLBASE_ENC, 9, struct venc_ioctl_msg) +#define VEN_IOCTL_GET_SHORT_HDR \ + _IOR(VEN_IOCTLBASE_ENC, 10, struct venc_ioctl_msg) + + +/*IOCTL params: SET: InputData - venc_sessionqp, OutputData - NULL + GET: InputData - NULL, OutputData - venc_sessionqp*/ +#define VEN_IOCTL_SET_SESSION_QP \ + _IOW(VEN_IOCTLBASE_ENC, 11, struct venc_ioctl_msg) +#define VEN_IOCTL_GET_SESSION_QP \ + _IOR(VEN_IOCTLBASE_ENC, 12, struct venc_ioctl_msg) + + +/*IOCTL params:SET: InputData - venc_intraperiod, OutputData - NULL + GET: InputData - NULL, OutputData - venc_intraperiod*/ +#define VEN_IOCTL_SET_INTRA_PERIOD \ + _IOW(VEN_IOCTLBASE_ENC, 13, struct venc_ioctl_msg) +#define VEN_IOCTL_GET_INTRA_PERIOD \ + _IOR(VEN_IOCTLBASE_ENC, 14, struct venc_ioctl_msg) + + +/* Request an Iframe*/ +#define VEN_IOCTL_CMD_REQUEST_IFRAME _IO(VEN_IOCTLBASE_ENC, 15) + +/*IOCTL params:GET: InputData - NULL, OutputData - venc_capability*/ +#define VEN_IOCTL_GET_CAPABILITY \ + _IOR(VEN_IOCTLBASE_ENC, 16, struct venc_ioctl_msg) + + +/*IOCTL params:GET: InputData - NULL, OutputData - venc_seqheader*/ +#define VEN_IOCTL_GET_SEQUENCE_HDR \ + _IOR(VEN_IOCTLBASE_ENC, 17, struct venc_ioctl_msg) + +/*IOCTL params:SET: InputData - venc_entropycfg, OutputData - NULL + GET: InputData - NULL, OutputData - venc_entropycfg*/ +#define VEN_IOCTL_SET_ENTROPY_CFG \ + _IOW(VEN_IOCTLBASE_ENC, 18, struct venc_ioctl_msg) +#define VEN_IOCTL_GET_ENTROPY_CFG \ + _IOR(VEN_IOCTLBASE_ENC, 19, struct venc_ioctl_msg) + +/*IOCTL params:SET: InputData - venc_dbcfg, OutputData - NULL + GET: InputData - NULL, OutputData - venc_dbcfg*/ +#define VEN_IOCTL_SET_DEBLOCKING_CFG \ + _IOW(VEN_IOCTLBASE_ENC, 20, struct venc_ioctl_msg) +#define VEN_IOCTL_GET_DEBLOCKING_CFG \ + _IOR(VEN_IOCTLBASE_ENC, 21, struct venc_ioctl_msg) + + +/*IOCTL params:SET: InputData - venc_intrarefresh, OutputData - NULL + GET: InputData - NULL, OutputData - venc_intrarefresh*/ +#define VEN_IOCTL_SET_INTRA_REFRESH \ + _IOW(VEN_IOCTLBASE_ENC, 22, struct venc_ioctl_msg) +#define VEN_IOCTL_GET_INTRA_REFRESH \ + _IOR(VEN_IOCTLBASE_ENC, 23, struct venc_ioctl_msg) + + +/*IOCTL params:SET: InputData - venc_multiclicecfg, OutputData - NULL + GET: InputData - NULL, OutputData - venc_multiclicecfg*/ +#define VEN_IOCTL_SET_MULTI_SLICE_CFG \ + _IOW(VEN_IOCTLBASE_ENC, 24, struct venc_ioctl_msg) +#define VEN_IOCTL_GET_MULTI_SLICE_CFG \ + _IOR(VEN_IOCTLBASE_ENC, 25, struct venc_ioctl_msg) + +/*IOCTL params:SET: InputData - venc_ratectrlcfg, OutputData - NULL + GET: InputData - NULL, OutputData - venc_ratectrlcfg*/ +#define VEN_IOCTL_SET_RATE_CTRL_CFG \ + _IOW(VEN_IOCTLBASE_ENC, 26, struct venc_ioctl_msg) +#define VEN_IOCTL_GET_RATE_CTRL_CFG \ + _IOR(VEN_IOCTLBASE_ENC, 27, struct venc_ioctl_msg) + + +/*IOCTL params:SET: InputData - venc_voptimingcfg, OutputData - NULL + GET: InputData - NULL, OutputData - venc_voptimingcfg*/ +#define VEN_IOCTL_SET_VOP_TIMING_CFG \ + _IOW(VEN_IOCTLBASE_ENC, 28, struct venc_ioctl_msg) +#define VEN_IOCTL_GET_VOP_TIMING_CFG \ + _IOR(VEN_IOCTLBASE_ENC, 29, struct venc_ioctl_msg) + + +/*IOCTL params:SET: InputData - venc_framerate, OutputData - NULL + GET: InputData - NULL, OutputData - venc_framerate*/ +#define VEN_IOCTL_SET_FRAME_RATE \ + _IOW(VEN_IOCTLBASE_ENC, 30, struct venc_ioctl_msg) +#define VEN_IOCTL_GET_FRAME_RATE \ + _IOR(VEN_IOCTLBASE_ENC, 31, struct venc_ioctl_msg) + + +/*IOCTL params:SET: InputData - venc_targetbitrate, OutputData - NULL + GET: InputData - NULL, OutputData - venc_targetbitrate*/ +#define VEN_IOCTL_SET_TARGET_BITRATE \ + _IOW(VEN_IOCTLBASE_ENC, 32, struct venc_ioctl_msg) +#define VEN_IOCTL_GET_TARGET_BITRATE \ + _IOR(VEN_IOCTLBASE_ENC, 33, struct venc_ioctl_msg) + + +/*IOCTL params:SET: InputData - venc_rotation, OutputData - NULL + GET: InputData - NULL, OutputData - venc_rotation*/ +#define VEN_IOCTL_SET_ROTATION \ + _IOW(VEN_IOCTLBASE_ENC, 34, struct venc_ioctl_msg) +#define VEN_IOCTL_GET_ROTATION \ + _IOR(VEN_IOCTLBASE_ENC, 35, struct venc_ioctl_msg) + + +/*IOCTL params:SET: InputData - venc_headerextension, OutputData - NULL + GET: InputData - NULL, OutputData - venc_headerextension*/ +#define VEN_IOCTL_SET_HEC \ + _IOW(VEN_IOCTLBASE_ENC, 36, struct venc_ioctl_msg) +#define VEN_IOCTL_GET_HEC \ + _IOR(VEN_IOCTLBASE_ENC, 37, struct venc_ioctl_msg) + +/*IOCTL params:SET: InputData - venc_switch, OutputData - NULL + GET: InputData - NULL, OutputData - venc_switch*/ +#define VEN_IOCTL_SET_DATA_PARTITION \ + _IOW(VEN_IOCTLBASE_ENC, 38, struct venc_ioctl_msg) +#define VEN_IOCTL_GET_DATA_PARTITION \ + _IOR(VEN_IOCTLBASE_ENC, 39, struct venc_ioctl_msg) + +/*IOCTL params:SET: InputData - venc_switch, OutputData - NULL + GET: InputData - NULL, OutputData - venc_switch*/ +#define VEN_IOCTL_SET_RVLC \ + _IOW(VEN_IOCTLBASE_ENC, 40, struct venc_ioctl_msg) +#define VEN_IOCTL_GET_RVLC \ + _IOR(VEN_IOCTLBASE_ENC, 41, struct venc_ioctl_msg) + + +/*IOCTL params:SET: InputData - venc_switch, OutputData - NULL + GET: InputData - NULL, OutputData - venc_switch*/ +#define VEN_IOCTL_SET_AC_PREDICTION \ + _IOW(VEN_IOCTLBASE_ENC, 42, struct venc_ioctl_msg) +#define VEN_IOCTL_GET_AC_PREDICTION \ + _IOR(VEN_IOCTLBASE_ENC, 43, struct venc_ioctl_msg) + + +/*IOCTL params:SET: InputData - venc_qprange, OutputData - NULL + GET: InputData - NULL, OutputData - venc_qprange*/ +#define VEN_IOCTL_SET_QP_RANGE \ + _IOW(VEN_IOCTLBASE_ENC, 44, struct venc_ioctl_msg) +#define VEN_IOCTL_GET_QP_RANGE \ + _IOR(VEN_IOCTLBASE_ENC, 45, struct venc_ioctl_msg) + +#define VEN_IOCTL_GET_NUMBER_INSTANCES \ + _IOR(VEN_IOCTLBASE_ENC, 46, struct venc_ioctl_msg) + +#define VEN_IOCTL_SET_METABUFFER_MODE \ + _IOW(VEN_IOCTLBASE_ENC, 47, struct venc_ioctl_msg) + + +/*IOCTL params:SET: InputData - unsigned int, OutputData - NULL.*/ +#define VEN_IOCTL_SET_EXTRADATA \ + _IOW(VEN_IOCTLBASE_ENC, 48, struct venc_ioctl_msg) +/*IOCTL params:GET: InputData - NULL, OutputData - unsigned int.*/ +#define VEN_IOCTL_GET_EXTRADATA \ + _IOR(VEN_IOCTLBASE_ENC, 49, struct venc_ioctl_msg) + +/*IOCTL params:SET: InputData - NULL, OutputData - NULL.*/ +#define VEN_IOCTL_SET_SLICE_DELIVERY_MODE \ + _IO(VEN_IOCTLBASE_ENC, 50) + +#define VEN_IOCTL_SET_H263_PLUSPTYPE \ + _IOW(VEN_IOCTLBASE_ENC, 51, struct venc_ioctl_msg) + +/*IOCTL params:SET: InputData - venc_range, OutputData - NULL.*/ +#define VEN_IOCTL_SET_CAPABILITY_LTRCOUNT \ + _IOW(VEN_IOCTLBASE_ENC, 52, struct venc_ioctl_msg) +/*IOCTL params:GET: InputData - NULL, OutputData - venc_range.*/ +#define VEN_IOCTL_GET_CAPABILITY_LTRCOUNT \ + _IOR(VEN_IOCTLBASE_ENC, 53, struct venc_ioctl_msg) + +/*IOCTL params:SET: InputData - venc_ltrmode, OutputData - NULL.*/ +#define VEN_IOCTL_SET_LTRMODE \ + _IOW(VEN_IOCTLBASE_ENC, 54, struct venc_ioctl_msg) +/*IOCTL params:GET: InputData - NULL, OutputData - venc_ltrmode.*/ +#define VEN_IOCTL_GET_LTRMODE \ + _IOR(VEN_IOCTLBASE_ENC, 55, struct venc_ioctl_msg) + +/*IOCTL params:SET: InputData - venc_ltrcount, OutputData - NULL.*/ +#define VEN_IOCTL_SET_LTRCOUNT \ + _IOW(VEN_IOCTLBASE_ENC, 56, struct venc_ioctl_msg) +/*IOCTL params:GET: InputData - NULL, OutputData - venc_ltrcount.*/ +#define VEN_IOCTL_GET_LTRCOUNT \ + _IOR(VEN_IOCTLBASE_ENC, 57, struct venc_ioctl_msg) + +/*IOCTL params:SET: InputData - venc_ltrperiod, OutputData - NULL.*/ +#define VEN_IOCTL_SET_LTRPERIOD \ + _IOW(VEN_IOCTLBASE_ENC, 58, struct venc_ioctl_msg) +/*IOCTL params:GET: InputData - NULL, OutputData - venc_ltrperiod.*/ +#define VEN_IOCTL_GET_LTRPERIOD \ + _IOR(VEN_IOCTLBASE_ENC, 59, struct venc_ioctl_msg) + +/*IOCTL params:SET: InputData - venc_ltruse, OutputData - NULL.*/ +#define VEN_IOCTL_SET_LTRUSE \ + _IOW(VEN_IOCTLBASE_ENC, 60, struct venc_ioctl_msg) +/*IOCTL params:GET: InputData - NULL, OutputData - venc_ltruse.*/ +#define VEN_IOCTL_GET_LTRUSE \ + _IOR(VEN_IOCTLBASE_ENC, 61, struct venc_ioctl_msg) + +/*IOCTL params:SET: InputData - venc_ltrmark, OutputData - NULL.*/ +#define VEN_IOCTL_SET_LTRMARK \ + _IOW(VEN_IOCTLBASE_ENC, 62, struct venc_ioctl_msg) +/*IOCTL params:GET: InputData - NULL, OutputData - venc_ltrmark.*/ +#define VEN_IOCTL_GET_LTRMARK \ + _IOR(VEN_IOCTLBASE_ENC, 63, struct venc_ioctl_msg) + +/*IOCTL params:SET: InputData - unsigned int, OutputData - NULL*/ +#define VEN_IOCTL_SET_SPS_PPS_FOR_IDR \ + _IOW(VEN_IOCTLBASE_ENC, 64, struct venc_ioctl_msg) + +struct venc_range { + unsigned long max; + unsigned long min; + unsigned long step_size; +}; + +struct venc_switch{ + unsigned char status; +}; + +struct venc_allocatorproperty{ + unsigned long mincount; + unsigned long maxcount; + unsigned long actualcount; + unsigned long datasize; + unsigned long suffixsize; + unsigned long alignment; + unsigned long bufpoolid; +}; + +struct venc_bufferpayload{ + unsigned char *pbuffer; + size_t sz; + int fd; + unsigned int offset; + unsigned int maped_size; + unsigned long filled_len; +}; + +struct venc_buffer{ + unsigned char *ptrbuffer; + unsigned long sz; + unsigned long len; + unsigned long offset; + long long timestamp; + unsigned long flags; + void *clientdata; +}; + +struct venc_basecfg{ + unsigned long input_width; + unsigned long input_height; + unsigned long dvs_width; + unsigned long dvs_height; + unsigned long codectype; + unsigned long fps_num; + unsigned long fps_den; + unsigned long targetbitrate; + unsigned long inputformat; +}; + +struct venc_profile{ + unsigned long profile; +}; +struct ven_profilelevel{ + unsigned long level; +}; + +struct venc_sessionqp{ + unsigned long iframeqp; + unsigned long pframqp; +}; + +struct venc_qprange{ + unsigned long maxqp; + unsigned long minqp; +}; + +struct venc_plusptype { + unsigned long plusptype_enable; +}; + +struct venc_intraperiod{ + unsigned long num_pframes; + unsigned long num_bframes; +}; +struct venc_seqheader{ + unsigned char *hdrbufptr; + unsigned long bufsize; + unsigned long hdrlen; +}; + +struct venc_capability{ + unsigned long codec_types; + unsigned long maxframe_width; + unsigned long maxframe_height; + unsigned long maxtarget_bitrate; + unsigned long maxframe_rate; + unsigned long input_formats; + unsigned char dvs; +}; + +struct venc_entropycfg{ + unsigned longentropysel; + unsigned long cabacmodel; +}; + +struct venc_dbcfg{ + unsigned long db_mode; + unsigned long slicealpha_offset; + unsigned long slicebeta_offset; +}; + +struct venc_intrarefresh{ + unsigned long irmode; + unsigned long mbcount; +}; + +struct venc_multiclicecfg{ + unsigned long mslice_mode; + unsigned long mslice_size; +}; + +struct venc_bufferflush{ + unsigned long flush_mode; +}; + +struct venc_ratectrlcfg{ + unsigned long rcmode; +}; + +struct venc_voptimingcfg{ + unsigned long voptime_resolution; +}; +struct venc_framerate{ + unsigned long fps_denominator; + unsigned long fps_numerator; +}; + +struct venc_targetbitrate{ + unsigned long target_bitrate; +}; + + +struct venc_rotation{ + unsigned long rotation; +}; + +struct venc_timeout{ + unsigned long millisec; +}; + +struct venc_headerextension{ + unsigned long header_extension; +}; + +struct venc_msg{ + unsigned long statuscode; + unsigned long msgcode; + struct venc_buffer buf; + unsigned long msgdata_size; +}; + +struct venc_recon_addr{ + unsigned char *pbuffer; + unsigned long buffer_size; + unsigned long pmem_fd; + unsigned long offset; +}; + +struct venc_recon_buff_size{ + int width; + int height; + int size; + int alignment; +}; + +struct venc_ltrmode { + unsigned long ltr_mode; +}; + +struct venc_ltrcount { + unsigned long ltr_count; +}; + +struct venc_ltrperiod { + unsigned long ltr_period; +}; + +struct venc_ltruse { + unsigned long ltr_id; + unsigned long ltr_frames; +}; + +#endif /* _UAPI_MSM_VIDC_ENC_H_ */ diff --git a/original-kernel-headers/linux/netlink.h b/original-kernel-headers/linux/netlink.h new file mode 100644 index 0000000..de33c60 --- /dev/null +++ b/original-kernel-headers/linux/netlink.h @@ -0,0 +1,184 @@ +#ifndef _UAPI__LINUX_NETLINK_H +#define _UAPI__LINUX_NETLINK_H + +#include <linux/socket.h> /* for __kernel_sa_family_t */ +#include <linux/types.h> + +#define NETLINK_ROUTE 0 /* Routing/device hook */ +#define NETLINK_UNUSED 1 /* Unused number */ +#define NETLINK_USERSOCK 2 /* Reserved for user mode socket protocols */ +#define NETLINK_FIREWALL 3 /* Unused number, formerly ip_queue */ +#define NETLINK_SOCK_DIAG 4 /* socket monitoring */ +#define NETLINK_NFLOG 5 /* netfilter/iptables ULOG */ +#define NETLINK_XFRM 6 /* ipsec */ +#define NETLINK_SELINUX 7 /* SELinux event notifications */ +#define NETLINK_ISCSI 8 /* Open-iSCSI */ +#define NETLINK_AUDIT 9 /* auditing */ +#define NETLINK_FIB_LOOKUP 10 +#define NETLINK_CONNECTOR 11 +#define NETLINK_NETFILTER 12 /* netfilter subsystem */ +#define NETLINK_IP6_FW 13 +#define NETLINK_DNRTMSG 14 /* DECnet routing messages */ +#define NETLINK_KOBJECT_UEVENT 15 /* Kernel messages to userspace */ +#define NETLINK_GENERIC 16 +/* leave room for NETLINK_DM (DM Events) */ +#define NETLINK_SCSITRANSPORT 18 /* SCSI Transports */ +#define NETLINK_ECRYPTFS 19 +#define NETLINK_RDMA 20 +#define NETLINK_CRYPTO 21 /* Crypto layer */ +#define NETLINK_SOCKEV 22 /* Socket Administrative Events */ +#define NETLINK_INET_DIAG NETLINK_SOCK_DIAG + +#define MAX_LINKS 32 + +struct sockaddr_nl { + __kernel_sa_family_t nl_family; /* AF_NETLINK */ + unsigned short nl_pad; /* zero */ + __u32 nl_pid; /* port ID */ + __u32 nl_groups; /* multicast groups mask */ +}; + +struct nlmsghdr { + __u32 nlmsg_len; /* Length of message including header */ + __u16 nlmsg_type; /* Message content */ + __u16 nlmsg_flags; /* Additional flags */ + __u32 nlmsg_seq; /* Sequence number */ + __u32 nlmsg_pid; /* Sending process port ID */ +}; + +/* Flags values */ + +#define NLM_F_REQUEST 1 /* It is request message. */ +#define NLM_F_MULTI 2 /* Multipart message, terminated by NLMSG_DONE */ +#define NLM_F_ACK 4 /* Reply with ack, with zero or error code */ +#define NLM_F_ECHO 8 /* Echo this request */ +#define NLM_F_DUMP_INTR 16 /* Dump was inconsistent due to sequence change */ + +/* Modifiers to GET request */ +#define NLM_F_ROOT 0x100 /* specify tree root */ +#define NLM_F_MATCH 0x200 /* return all matching */ +#define NLM_F_ATOMIC 0x400 /* atomic GET */ +#define NLM_F_DUMP (NLM_F_ROOT|NLM_F_MATCH) + +/* Modifiers to NEW request */ +#define NLM_F_REPLACE 0x100 /* Override existing */ +#define NLM_F_EXCL 0x200 /* Do not touch, if it exists */ +#define NLM_F_CREATE 0x400 /* Create, if it does not exist */ +#define NLM_F_APPEND 0x800 /* Add to end of list */ + +/* + 4.4BSD ADD NLM_F_CREATE|NLM_F_EXCL + 4.4BSD CHANGE NLM_F_REPLACE + + True CHANGE NLM_F_CREATE|NLM_F_REPLACE + Append NLM_F_CREATE + Check NLM_F_EXCL + */ + +#define NLMSG_ALIGNTO 4U +#define NLMSG_ALIGN(len) ( ((len)+NLMSG_ALIGNTO-1) & ~(NLMSG_ALIGNTO-1) ) +#define NLMSG_HDRLEN ((int) NLMSG_ALIGN(sizeof(struct nlmsghdr))) +#define NLMSG_LENGTH(len) ((len) + NLMSG_HDRLEN) +#define NLMSG_SPACE(len) NLMSG_ALIGN(NLMSG_LENGTH(len)) +#define NLMSG_DATA(nlh) ((void*)(((char*)nlh) + NLMSG_LENGTH(0))) +#define NLMSG_NEXT(nlh,len) ((len) -= NLMSG_ALIGN((nlh)->nlmsg_len), \ + (struct nlmsghdr*)(((char*)(nlh)) + NLMSG_ALIGN((nlh)->nlmsg_len))) +#define NLMSG_OK(nlh,len) ((len) >= (int)sizeof(struct nlmsghdr) && \ + (nlh)->nlmsg_len >= sizeof(struct nlmsghdr) && \ + (nlh)->nlmsg_len <= (len)) +#define NLMSG_PAYLOAD(nlh,len) ((nlh)->nlmsg_len - NLMSG_SPACE((len))) + +#define NLMSG_NOOP 0x1 /* Nothing. */ +#define NLMSG_ERROR 0x2 /* Error */ +#define NLMSG_DONE 0x3 /* End of a dump */ +#define NLMSG_OVERRUN 0x4 /* Data lost */ + +#define NLMSG_MIN_TYPE 0x10 /* < 0x10: reserved control messages */ + +struct nlmsgerr { + int error; + struct nlmsghdr msg; +}; + +#define NETLINK_ADD_MEMBERSHIP 1 +#define NETLINK_DROP_MEMBERSHIP 2 +#define NETLINK_PKTINFO 3 +#define NETLINK_BROADCAST_ERROR 4 +#define NETLINK_NO_ENOBUFS 5 +#define NETLINK_RX_RING 6 +#define NETLINK_TX_RING 7 + +struct nl_pktinfo { + __u32 group; +}; + +struct nl_mmap_req { + unsigned int nm_block_size; + unsigned int nm_block_nr; + unsigned int nm_frame_size; + unsigned int nm_frame_nr; +}; + +struct nl_mmap_hdr { + unsigned int nm_status; + unsigned int nm_len; + __u32 nm_group; + /* credentials */ + __u32 nm_pid; + __u32 nm_uid; + __u32 nm_gid; +}; + +enum nl_mmap_status { + NL_MMAP_STATUS_UNUSED, + NL_MMAP_STATUS_RESERVED, + NL_MMAP_STATUS_VALID, + NL_MMAP_STATUS_COPY, + NL_MMAP_STATUS_SKIP, +}; + +#define NL_MMAP_MSG_ALIGNMENT NLMSG_ALIGNTO +#define NL_MMAP_MSG_ALIGN(sz) __ALIGN_KERNEL(sz, NL_MMAP_MSG_ALIGNMENT) +#define NL_MMAP_HDRLEN NL_MMAP_MSG_ALIGN(sizeof(struct nl_mmap_hdr)) + +#define NET_MAJOR 36 /* Major 36 is reserved for networking */ + +enum { + NETLINK_UNCONNECTED = 0, + NETLINK_CONNECTED, +}; + +/* + * <------- NLA_HDRLEN ------> <-- NLA_ALIGN(payload)--> + * +---------------------+- - -+- - - - - - - - - -+- - -+ + * | Header | Pad | Payload | Pad | + * | (struct nlattr) | ing | | ing | + * +---------------------+- - -+- - - - - - - - - -+- - -+ + * <-------------- nlattr->nla_len --------------> + */ + +struct nlattr { + __u16 nla_len; + __u16 nla_type; +}; + +/* + * nla_type (16 bits) + * +---+---+-------------------------------+ + * | N | O | Attribute Type | + * +---+---+-------------------------------+ + * N := Carries nested attributes + * O := Payload stored in network byte order + * + * Note: The N and O flag are mutually exclusive. + */ +#define NLA_F_NESTED (1 << 15) +#define NLA_F_NET_BYTEORDER (1 << 14) +#define NLA_TYPE_MASK ~(NLA_F_NESTED | NLA_F_NET_BYTEORDER) + +#define NLA_ALIGNTO 4 +#define NLA_ALIGN(len) (((len) + NLA_ALIGNTO - 1) & ~(NLA_ALIGNTO - 1)) +#define NLA_HDRLEN ((int) NLA_ALIGN(sizeof(struct nlattr))) + + +#endif /* _UAPI__LINUX_NETLINK_H */ diff --git a/original-kernel-headers/linux/qseecom.h b/original-kernel-headers/linux/qseecom.h new file mode 100644 index 0000000..3caddce --- /dev/null +++ b/original-kernel-headers/linux/qseecom.h @@ -0,0 +1,296 @@ +#ifndef _UAPI_QSEECOM_H_ +#define _UAPI_QSEECOM_H_ + +#include <linux/types.h> +#include <linux/ioctl.h> + +#define MAX_ION_FD 4 +#define MAX_APP_NAME_SIZE 32 +#define QSEECOM_HASH_SIZE 32 +/* + * struct qseecom_register_listener_req - + * for register listener ioctl request + * @listener_id - service id (shared between userspace and QSE) + * @ifd_data_fd - ion handle + * @virt_sb_base - shared buffer base in user space + * @sb_size - shared buffer size + */ +struct qseecom_register_listener_req { + uint32_t listener_id; /* in */ + int32_t ifd_data_fd; /* in */ + void *virt_sb_base; /* in */ + uint32_t sb_size; /* in */ +}; + +/* + * struct qseecom_send_cmd_req - for send command ioctl request + * @cmd_req_len - command buffer length + * @cmd_req_buf - command buffer + * @resp_len - response buffer length + * @resp_buf - response buffer + */ +struct qseecom_send_cmd_req { + void *cmd_req_buf; /* in */ + unsigned int cmd_req_len; /* in */ + void *resp_buf; /* in/out */ + unsigned int resp_len; /* in/out */ +}; + +/* + * struct qseecom_ion_fd_info - ion fd handle data information + * @fd - ion handle to some memory allocated in user space + * @cmd_buf_offset - command buffer offset + */ +struct qseecom_ion_fd_info { + int32_t fd; + uint32_t cmd_buf_offset; +}; +/* + * struct qseecom_send_modfd_cmd_req - for send command ioctl request + * @cmd_req_len - command buffer length + * @cmd_req_buf - command buffer + * @resp_len - response buffer length + * @resp_buf - response buffer + * @ifd_data_fd - ion handle to memory allocated in user space + * @cmd_buf_offset - command buffer offset + */ +struct qseecom_send_modfd_cmd_req { + void *cmd_req_buf; /* in */ + unsigned int cmd_req_len; /* in */ + void *resp_buf; /* in/out */ + unsigned int resp_len; /* in/out */ + struct qseecom_ion_fd_info ifd_data[MAX_ION_FD]; +}; + +/* + * struct qseecom_listener_send_resp_req - signal to continue the send_cmd req. + * Used as a trigger from HLOS service to notify QSEECOM that it's done with its + * operation and provide the response for QSEECOM can continue the incomplete + * command execution + * @resp_len - Length of the response + * @resp_buf - Response buffer where the response of the cmd should go. + */ +struct qseecom_send_resp_req { + void *resp_buf; /* in */ + unsigned int resp_len; /* in */ +}; + +/* + * struct qseecom_load_img_data - for sending image length information and + * ion file descriptor to the qseecom driver. ion file descriptor is used + * for retrieving the ion file handle and in turn the physical address of + * the image location. + * @mdt_len - Length of the .mdt file in bytes. + * @img_len - Length of the .mdt + .b00 +..+.bxx images files in bytes + * @ion_fd - Ion file descriptor used when allocating memory. + * @img_name - Name of the image. +*/ +struct qseecom_load_img_req { + uint32_t mdt_len; /* in */ + uint32_t img_len; /* in */ + int32_t ifd_data_fd; /* in */ + char img_name[MAX_APP_NAME_SIZE]; /* in */ + int app_id; /* out*/ +}; + +struct qseecom_set_sb_mem_param_req { + int32_t ifd_data_fd; /* in */ + void *virt_sb_base; /* in */ + uint32_t sb_len; /* in */ +}; + +/* + * struct qseecom_qseos_version_req - get qseos version + * @qseos_version - version number + */ +struct qseecom_qseos_version_req { + unsigned int qseos_version; /* in */ +}; + +/* + * struct qseecom_qseos_app_load_query - verify if app is loaded in qsee + * @app_name[MAX_APP_NAME_SIZE]- name of the app. + * @app_id - app id. + */ +struct qseecom_qseos_app_load_query { + char app_name[MAX_APP_NAME_SIZE]; /* in */ + int app_id; /* out */ +}; + +struct qseecom_send_svc_cmd_req { + uint32_t cmd_id; + void *cmd_req_buf; /* in */ + unsigned int cmd_req_len; /* in */ + void *resp_buf; /* in/out */ + unsigned int resp_len; /* in/out */ +}; + +enum qseecom_key_management_usage_type { + QSEOS_KM_USAGE_DISK_ENCRYPTION = 0x01, + QSEOS_KM_USAGE_FILE_ENCRYPTION = 0x02, + QSEOS_KM_USAGE_ICE_DISK_ENCRYPTION = 0x03, + QSEOS_KM_USAGE_ICE_FILE_ENCRYPTION = 0x04, + QSEOS_KM_USAGE_MAX +}; + +struct qseecom_create_key_req { + unsigned char hash32[QSEECOM_HASH_SIZE]; + enum qseecom_key_management_usage_type usage; +}; + +struct qseecom_wipe_key_req { + enum qseecom_key_management_usage_type usage; + int wipe_key_flag;/* 1->remove key from storage(alone with clear key) */ + /* 0->do not remove from storage (clear key) */ +}; + +struct qseecom_update_key_userinfo_req { + unsigned char current_hash32[QSEECOM_HASH_SIZE]; + unsigned char new_hash32[QSEECOM_HASH_SIZE]; + enum qseecom_key_management_usage_type usage; +}; + +#define SHA256_DIGEST_LENGTH (256/8) +/* + * struct qseecom_save_partition_hash_req + * @partition_id - partition id. + * @hash[SHA256_DIGEST_LENGTH] - sha256 digest. + */ +struct qseecom_save_partition_hash_req { + int partition_id; /* in */ + char digest[SHA256_DIGEST_LENGTH]; /* in */ +}; + +/* + * struct qseecom_is_es_activated_req + * @is_activated - 1=true , 0=false + */ +struct qseecom_is_es_activated_req { + int is_activated; /* out */ +}; + +enum qseecom_bandwidth_request_mode { + INACTIVE = 0, + LOW, + MEDIUM, + HIGH, +}; + +/* + * struct qseecom_send_modfd_resp - for send command ioctl request + * @req_len - command buffer length + * @req_buf - command buffer + * @ifd_data_fd - ion handle to memory allocated in user space + * @cmd_buf_offset - command buffer offset + */ +struct qseecom_send_modfd_listener_resp { + void *resp_buf_ptr; /* in */ + unsigned int resp_len; /* in */ + struct qseecom_ion_fd_info ifd_data[MAX_ION_FD]; /* in */ +}; + +struct qseecom_qteec_req { + void *req_ptr; + uint32_t req_len; + void *resp_ptr; + uint32_t resp_len; +}; + +struct qseecom_qteec_modfd_req { + void *req_ptr; + uint32_t req_len; + void *resp_ptr; + uint32_t resp_len; + struct qseecom_ion_fd_info ifd_data[MAX_ION_FD]; +}; + +struct file; + +extern long qseecom_ioctl(struct file *file, + unsigned cmd, unsigned long arg); + +#define QSEECOM_IOC_MAGIC 0x97 + + +#define QSEECOM_IOCTL_REGISTER_LISTENER_REQ \ + _IOWR(QSEECOM_IOC_MAGIC, 1, struct qseecom_register_listener_req) + +#define QSEECOM_IOCTL_UNREGISTER_LISTENER_REQ \ + _IO(QSEECOM_IOC_MAGIC, 2) + +#define QSEECOM_IOCTL_SEND_CMD_REQ \ + _IOWR(QSEECOM_IOC_MAGIC, 3, struct qseecom_send_cmd_req) + +#define QSEECOM_IOCTL_SEND_MODFD_CMD_REQ \ + _IOWR(QSEECOM_IOC_MAGIC, 4, struct qseecom_send_modfd_cmd_req) + +#define QSEECOM_IOCTL_RECEIVE_REQ \ + _IO(QSEECOM_IOC_MAGIC, 5) + +#define QSEECOM_IOCTL_SEND_RESP_REQ \ + _IO(QSEECOM_IOC_MAGIC, 6) + +#define QSEECOM_IOCTL_LOAD_APP_REQ \ + _IOWR(QSEECOM_IOC_MAGIC, 7, struct qseecom_load_img_req) + +#define QSEECOM_IOCTL_SET_MEM_PARAM_REQ \ + _IOWR(QSEECOM_IOC_MAGIC, 8, struct qseecom_set_sb_mem_param_req) + +#define QSEECOM_IOCTL_UNLOAD_APP_REQ \ + _IO(QSEECOM_IOC_MAGIC, 9) + +#define QSEECOM_IOCTL_GET_QSEOS_VERSION_REQ \ + _IOWR(QSEECOM_IOC_MAGIC, 10, struct qseecom_qseos_version_req) + +#define QSEECOM_IOCTL_PERF_ENABLE_REQ \ + _IO(QSEECOM_IOC_MAGIC, 11) + +#define QSEECOM_IOCTL_PERF_DISABLE_REQ \ + _IO(QSEECOM_IOC_MAGIC, 12) + +#define QSEECOM_IOCTL_LOAD_EXTERNAL_ELF_REQ \ + _IOWR(QSEECOM_IOC_MAGIC, 13, struct qseecom_load_img_req) + +#define QSEECOM_IOCTL_UNLOAD_EXTERNAL_ELF_REQ \ + _IO(QSEECOM_IOC_MAGIC, 14) + +#define QSEECOM_IOCTL_APP_LOADED_QUERY_REQ \ + _IOWR(QSEECOM_IOC_MAGIC, 15, struct qseecom_qseos_app_load_query) + +#define QSEECOM_IOCTL_SEND_CMD_SERVICE_REQ \ + _IOWR(QSEECOM_IOC_MAGIC, 16, struct qseecom_send_svc_cmd_req) + +#define QSEECOM_IOCTL_CREATE_KEY_REQ \ + _IOWR(QSEECOM_IOC_MAGIC, 17, struct qseecom_create_key_req) + +#define QSEECOM_IOCTL_WIPE_KEY_REQ \ + _IOWR(QSEECOM_IOC_MAGIC, 18, struct qseecom_wipe_key_req) + +#define QSEECOM_IOCTL_SAVE_PARTITION_HASH_REQ \ + _IOWR(QSEECOM_IOC_MAGIC, 19, struct qseecom_save_partition_hash_req) + +#define QSEECOM_IOCTL_IS_ES_ACTIVATED_REQ \ + _IOWR(QSEECOM_IOC_MAGIC, 20, struct qseecom_is_es_activated_req) + +#define QSEECOM_IOCTL_SEND_MODFD_RESP \ + _IOWR(QSEECOM_IOC_MAGIC, 21, struct qseecom_send_modfd_listener_resp) + +#define QSEECOM_IOCTL_SET_BUS_SCALING_REQ \ + _IOWR(QSEECOM_IOC_MAGIC, 23, int) + +#define QSEECOM_IOCTL_UPDATE_KEY_USER_INFO_REQ \ + _IOWR(QSEECOM_IOC_MAGIC, 24, struct qseecom_update_key_userinfo_req) + +#define QSEECOM_QTEEC_IOCTL_OPEN_SESSION_REQ \ + _IOWR(QSEECOM_IOC_MAGIC, 30, struct qseecom_qteec_modfd_req) + +#define QSEECOM_QTEEC_IOCTL_CLOSE_SESSION_REQ \ + _IOWR(QSEECOM_IOC_MAGIC, 31, struct qseecom_qteec_req) + +#define QSEECOM_QTEEC_IOCTL_INVOKE_MODFD_CMD_REQ \ + _IOWR(QSEECOM_IOC_MAGIC, 32, struct qseecom_qteec_modfd_req) + +#define QSEECOM_QTEEC_IOCTL_REQUEST_CANCELLATION_REQ \ + _IOWR(QSEECOM_IOC_MAGIC, 33, struct qseecom_qteec_modfd_req) + +#endif /* _UAPI_QSEECOM_H_ */ diff --git a/original-kernel-headers/linux/rmnet_data.h b/original-kernel-headers/linux/rmnet_data.h new file mode 100644 index 0000000..aa47160 --- /dev/null +++ b/original-kernel-headers/linux/rmnet_data.h @@ -0,0 +1,251 @@ + /* + * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * RMNET Data configuration specification + */ + +#ifndef _RMNET_DATA_H_ +#define _RMNET_DATA_H_ + +/* ***************** Constants ********************************************** */ +#define RMNET_LOCAL_LOGICAL_ENDPOINT -1 + +#define RMNET_EGRESS_FORMAT__RESERVED__ (1<<0) +#define RMNET_EGRESS_FORMAT_MAP (1<<1) +#define RMNET_EGRESS_FORMAT_AGGREGATION (1<<2) +#define RMNET_EGRESS_FORMAT_MUXING (1<<3) +#define RMNET_EGRESS_FORMAT_MAP_CKSUMV3 (1<<4) + +#define RMNET_INGRESS_FIX_ETHERNET (1<<0) +#define RMNET_INGRESS_FORMAT_MAP (1<<1) +#define RMNET_INGRESS_FORMAT_DEAGGREGATION (1<<2) +#define RMNET_INGRESS_FORMAT_DEMUXING (1<<3) +#define RMNET_INGRESS_FORMAT_MAP_COMMANDS (1<<4) +#define RMNET_INGRESS_FORMAT_MAP_CKSUMV3 (1<<5) + +/* ***************** Netlink API ******************************************** */ +#define RMNET_NETLINK_PROTO 31 +#define RMNET_MAX_STR_LEN 16 +#define RMNET_NL_DATA_MAX_LEN 64 + +#define RMNET_NETLINK_MSG_COMMAND 0 +#define RMNET_NETLINK_MSG_RETURNCODE 1 +#define RMNET_NETLINK_MSG_RETURNDATA 2 + +struct rmnet_nl_msg_s { + uint16_t reserved; + uint16_t message_type; + uint16_t reserved2:14; + uint16_t crd:2; + union { + uint16_t arg_length; + uint16_t return_code; + }; + union { + uint8_t data[RMNET_NL_DATA_MAX_LEN]; + struct { + uint8_t dev[RMNET_MAX_STR_LEN]; + uint32_t flags; + uint16_t agg_size; + uint16_t agg_count; + uint8_t tail_spacing; + } data_format; + struct { + uint8_t dev[RMNET_MAX_STR_LEN]; + int32_t ep_id; + uint8_t operating_mode; + uint8_t next_dev[RMNET_MAX_STR_LEN]; + } local_ep_config; + struct { + uint32_t id; + uint8_t vnd_name[RMNET_MAX_STR_LEN]; + } vnd; + struct { + uint32_t id; + uint32_t map_flow_id; + uint32_t tc_flow_id; + } flow_control; + }; +}; + +enum rmnet_netlink_message_types_e { + /* + * RMNET_NETLINK_ASSOCIATE_NETWORK_DEVICE - Register RMNET data driver + * on a particular device. + * Args: char[] dev_name: Null terminated ASCII string, max length: 15 + * Returns: status code + */ + RMNET_NETLINK_ASSOCIATE_NETWORK_DEVICE, + + /* + * RMNET_NETLINK_UNASSOCIATE_NETWORK_DEVICE - Unregister RMNET data + * driver on a particular + * device. + * Args: char[] dev_name: Null terminated ASCII string, max length: 15 + * Returns: status code + */ + RMNET_NETLINK_UNASSOCIATE_NETWORK_DEVICE, + + /* + * RMNET_NETLINK_GET_NETWORK_DEVICE_ASSOCIATED - Get if RMNET data + * driver is registered on a + * particular device. + * Args: char[] dev_name: Null terminated ASCII string, max length: 15 + * Returns: 1 if registered, 0 if not + */ + RMNET_NETLINK_GET_NETWORK_DEVICE_ASSOCIATED, + + /* + * RMNET_NETLINK_SET_LINK_EGRESS_DATA_FORMAT - Sets the egress data + * format for a particular + * link. + * Args: uint32_t egress_flags + * char[] dev_name: Null terminated ASCII string, max length: 15 + * Returns: status code + */ + RMNET_NETLINK_SET_LINK_EGRESS_DATA_FORMAT, + + /* + * RMNET_NETLINK_GET_LINK_EGRESS_DATA_FORMAT - Gets the egress data + * format for a particular + * link. + * Args: char[] dev_name: Null terminated ASCII string, max length: 15 + * Returns: 4-bytes data: uint32_t egress_flags + */ + RMNET_NETLINK_GET_LINK_EGRESS_DATA_FORMAT, + + /* + * RMNET_NETLINK_SET_LINK_INGRESS_DATA_FORMAT - Sets the ingress data + * format for a particular + * link. + * Args: uint32_t ingress_flags + * char[] dev_name: Null terminated ASCII string, max length: 15 + * Returns: status code + */ + RMNET_NETLINK_SET_LINK_INGRESS_DATA_FORMAT, + + /* + * RMNET_NETLINK_GET_LINK_INGRESS_DATA_FORMAT - Gets the ingress data + * format for a particular + * link. + * Args: char[] dev_name: Null terminated ASCII string, max length: 15 + * Returns: 4-bytes data: uint32_t ingress_flags + */ + RMNET_NETLINK_GET_LINK_INGRESS_DATA_FORMAT, + + /* + * RMNET_NETLINK_SET_LOGICAL_EP_CONFIG - Sets the logical endpoint + * configuration for a particular + * link. + * Args: char[] dev_name: Null terminated ASCII string, max length: 15 + * int32_t logical_ep_id, valid values are -1 through 31 + * uint8_t rmnet_mode: one of none, vnd, bridged + * char[] egress_dev_name: Egress device if operating in bridge mode + * Returns: status code + */ + RMNET_NETLINK_SET_LOGICAL_EP_CONFIG, + + /* + * RMNET_NETLINK_UNSET_LOGICAL_EP_CONFIG - Un-sets the logical endpoint + * configuration for a particular + * link. + * Args: char[] dev_name: Null terminated ASCII string, max length: 15 + * int32_t logical_ep_id, valid values are -1 through 31 + * Returns: status code + */ + RMNET_NETLINK_UNSET_LOGICAL_EP_CONFIG, + + /* + * RMNET_NETLINK_GET_LOGICAL_EP_CONFIG - Gets the logical endpoint + * configuration for a particular + * link. + * Args: char[] dev_name: Null terminated ASCII string, max length: 15 + * int32_t logical_ep_id, valid values are -1 through 31 + * Returns: uint8_t rmnet_mode: one of none, vnd, bridged + * char[] egress_dev_name: Egress device + */ + RMNET_NETLINK_GET_LOGICAL_EP_CONFIG, + + /* + * RMNET_NETLINK_NEW_VND - Creates a new virtual network device node + * Args: int32_t node number + * Returns: status code + */ + RMNET_NETLINK_NEW_VND, + + /* + * RMNET_NETLINK_NEW_VND_WITH_PREFIX - Creates a new virtual network + * device node with the specified + * prefix for the device name + * Args: int32_t node number + * char[] vnd_name - Use as prefix + * Returns: status code + */ + RMNET_NETLINK_NEW_VND_WITH_PREFIX, + + /* + * RMNET_NETLINK_GET_VND_NAME - Gets the string name of a VND from ID + * Args: int32_t node number + * Returns: char[] vnd_name + */ + RMNET_NETLINK_GET_VND_NAME, + + /* + * RMNET_NETLINK_FREE_VND - Removes virtual network device node + * Args: int32_t node number + * Returns: status code + */ + RMNET_NETLINK_FREE_VND, + + /* + * RMNET_NETLINK_ADD_VND_TC_FLOW - Add flow control handle on VND + * Args: int32_t node number + * uint32_t MAP Flow Handle + * uint32_t TC Flow Handle + * Returns: status code + */ + RMNET_NETLINK_ADD_VND_TC_FLOW, + + /* + * RMNET_NETLINK_DEL_VND_TC_FLOW - Removes flow control handle on VND + * Args: int32_t node number + * uint32_t MAP Flow Handle + * Returns: status code + */ + RMNET_NETLINK_DEL_VND_TC_FLOW +}; + +enum rmnet_config_endpoint_modes_e { + /* Pass the frame up the stack with no modifications to skb->dev */ + RMNET_EPMODE_NONE, + /* Replace skb->dev to a virtual rmnet device and pass up the stack */ + RMNET_EPMODE_VND, + /* Pass the frame directly to another device with dev_queue_xmit(). */ + RMNET_EPMODE_BRIDGE, + /* Must be the last item in the list */ + RMNET_EPMODE_LENGTH +}; + +enum rmnet_config_return_codes_e { + RMNET_CONFIG_OK, + RMNET_CONFIG_UNKNOWN_MESSAGE, + RMNET_CONFIG_UNKNOWN_ERROR, + RMNET_CONFIG_NOMEM, + RMNET_CONFIG_DEVICE_IN_USE, + RMNET_CONFIG_INVALID_REQUEST, + RMNET_CONFIG_NO_SUCH_DEVICE, + RMNET_CONFIG_BAD_ARGUMENTS, + RMNET_CONFIG_BAD_EGRESS_DEVICE, + RMNET_CONFIG_TC_HANDLE_FULL +}; + +#endif /* _RMNET_DATA_H_ */ diff --git a/original-kernel-headers/linux/sockev.h b/original-kernel-headers/linux/sockev.h new file mode 100644 index 0000000..fe6f35a --- /dev/null +++ b/original-kernel-headers/linux/sockev.h @@ -0,0 +1,31 @@ +#ifndef _SOCKEV_H_ +#define _SOCKEV_H_ + +#include <linux/types.h> +#include <linux/netlink.h> +#include <linux/socket.h> + +enum sknetlink_groups { + SKNLGRP_UNICAST, + SKNLGRP_SOCKEV, + __SKNLGRP_MAX +}; + +#define SOCKEV_STR_MAX 32 + +/******************************************************************** +* Socket operation messages +****/ + +struct sknlsockevmsg { + __u8 event[SOCKEV_STR_MAX]; + __u32 pid; /* (struct task_struct*)->pid */ + __u16 skfamily; /* (struct socket*)->sk->sk_family */ + __u8 skstate; /* (struct socket*)->sk->sk_state */ + __u8 skprotocol; /* (struct socket*)->sk->sk_protocol */ + __u16 sktype; /* (struct socket*)->sk->sk_type */ + __u64 skflags; /* (struct socket*)->sk->sk_flags */ +}; + +#endif /* _SOCKEV_H_ */ + diff --git a/original-kernel-headers/linux/sockios.h b/original-kernel-headers/linux/sockios.h new file mode 100644 index 0000000..f7ffe36 --- /dev/null +++ b/original-kernel-headers/linux/sockios.h @@ -0,0 +1,149 @@ +/* + * INET An implementation of the TCP/IP protocol suite for the LINUX + * operating system. INET is implemented using the BSD Socket + * interface as the means of communication with the user level. + * + * Definitions of the socket-level I/O control calls. + * + * Version: @(#)sockios.h 1.0.2 03/09/93 + * + * Authors: Ross Biro + * Fred N. van Kempen, <waltje@uWalt.NL.Mugnet.ORG> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ +#ifndef _LINUX_SOCKIOS_H +#define _LINUX_SOCKIOS_H + +#include <asm/sockios.h> + +/* Linux-specific socket ioctls */ +#define SIOCINQ FIONREAD +#define SIOCOUTQ TIOCOUTQ /* output queue size (not sent + not acked) */ + +/* Routing table calls. */ +#define SIOCADDRT 0x890B /* add routing table entry */ +#define SIOCDELRT 0x890C /* delete routing table entry */ +#define SIOCRTMSG 0x890D /* call to routing system */ + +/* Socket configuration controls. */ +#define SIOCGIFNAME 0x8910 /* get iface name */ +#define SIOCSIFLINK 0x8911 /* set iface channel */ +#define SIOCGIFCONF 0x8912 /* get iface list */ +#define SIOCGIFFLAGS 0x8913 /* get flags */ +#define SIOCSIFFLAGS 0x8914 /* set flags */ +#define SIOCGIFADDR 0x8915 /* get PA address */ +#define SIOCSIFADDR 0x8916 /* set PA address */ +#define SIOCGIFDSTADDR 0x8917 /* get remote PA address */ +#define SIOCSIFDSTADDR 0x8918 /* set remote PA address */ +#define SIOCGIFBRDADDR 0x8919 /* get broadcast PA address */ +#define SIOCSIFBRDADDR 0x891a /* set broadcast PA address */ +#define SIOCGIFNETMASK 0x891b /* get network PA mask */ +#define SIOCSIFNETMASK 0x891c /* set network PA mask */ +#define SIOCGIFMETRIC 0x891d /* get metric */ +#define SIOCSIFMETRIC 0x891e /* set metric */ +#define SIOCGIFMEM 0x891f /* get memory address (BSD) */ +#define SIOCSIFMEM 0x8920 /* set memory address (BSD) */ +#define SIOCGIFMTU 0x8921 /* get MTU size */ +#define SIOCSIFMTU 0x8922 /* set MTU size */ +#define SIOCSIFNAME 0x8923 /* set interface name */ +#define SIOCSIFHWADDR 0x8924 /* set hardware address */ +#define SIOCGIFENCAP 0x8925 /* get/set encapsulations */ +#define SIOCSIFENCAP 0x8926 +#define SIOCGIFHWADDR 0x8927 /* Get hardware address */ +#define SIOCGIFSLAVE 0x8929 /* Driver slaving support */ +#define SIOCSIFSLAVE 0x8930 +#define SIOCADDMULTI 0x8931 /* Multicast address lists */ +#define SIOCDELMULTI 0x8932 +#define SIOCGIFINDEX 0x8933 /* name -> if_index mapping */ +#define SIOGIFINDEX SIOCGIFINDEX /* misprint compatibility :-) */ +#define SIOCSIFPFLAGS 0x8934 /* set/get extended flags set */ +#define SIOCGIFPFLAGS 0x8935 +#define SIOCDIFADDR 0x8936 /* delete PA address */ +#define SIOCSIFHWBROADCAST 0x8937 /* set hardware broadcast addr */ +#define SIOCGIFCOUNT 0x8938 /* get number of devices */ +#define SIOCKILLADDR 0x8939 /* kill sockets with this local addr */ + +#define SIOCGIFBR 0x8940 /* Bridging support */ +#define SIOCSIFBR 0x8941 /* Set bridging options */ + +#define SIOCGIFTXQLEN 0x8942 /* Get the tx queue length */ +#define SIOCSIFTXQLEN 0x8943 /* Set the tx queue length */ + +/* SIOCGIFDIVERT was: 0x8944 Frame diversion support */ +/* SIOCSIFDIVERT was: 0x8945 Set frame diversion options */ + +#define SIOCETHTOOL 0x8946 /* Ethtool interface */ + +#define SIOCGMIIPHY 0x8947 /* Get address of MII PHY in use. */ +#define SIOCGMIIREG 0x8948 /* Read MII PHY register. */ +#define SIOCSMIIREG 0x8949 /* Write MII PHY register. */ + +#define SIOCWANDEV 0x894A /* get/set netdev parameters */ + +#define SIOCOUTQNSD 0x894B /* output queue size (not sent only) */ + +/* ARP cache control calls. */ + /* 0x8950 - 0x8952 * obsolete calls, don't re-use */ +#define SIOCDARP 0x8953 /* delete ARP table entry */ +#define SIOCGARP 0x8954 /* get ARP table entry */ +#define SIOCSARP 0x8955 /* set ARP table entry */ + +/* RARP cache control calls. */ +#define SIOCDRARP 0x8960 /* delete RARP table entry */ +#define SIOCGRARP 0x8961 /* get RARP table entry */ +#define SIOCSRARP 0x8962 /* set RARP table entry */ + +/* Driver configuration calls */ + +#define SIOCGIFMAP 0x8970 /* Get device parameters */ +#define SIOCSIFMAP 0x8971 /* Set device parameters */ + +/* DLCI configuration calls */ + +#define SIOCADDDLCI 0x8980 /* Create new DLCI device */ +#define SIOCDELDLCI 0x8981 /* Delete DLCI device */ + +#define SIOCGIFVLAN 0x8982 /* 802.1Q VLAN support */ +#define SIOCSIFVLAN 0x8983 /* Set 802.1Q VLAN options */ + +/* bonding calls */ + +#define SIOCBONDENSLAVE 0x8990 /* enslave a device to the bond */ +#define SIOCBONDRELEASE 0x8991 /* release a slave from the bond*/ +#define SIOCBONDSETHWADDR 0x8992 /* set the hw addr of the bond */ +#define SIOCBONDSLAVEINFOQUERY 0x8993 /* rtn info about slave state */ +#define SIOCBONDINFOQUERY 0x8994 /* rtn info about bond state */ +#define SIOCBONDCHANGEACTIVE 0x8995 /* update to a new active slave */ + +/* bridge calls */ +#define SIOCBRADDBR 0x89a0 /* create new bridge device */ +#define SIOCBRDELBR 0x89a1 /* remove bridge device */ +#define SIOCBRADDIF 0x89a2 /* add interface to bridge */ +#define SIOCBRDELIF 0x89a3 /* remove interface from bridge */ + +/* hardware time stamping: parameters in linux/net_tstamp.h */ +#define SIOCSHWTSTAMP 0x89b0 + +/* Device private ioctl calls */ + +/* + * These 16 ioctls are available to devices via the do_ioctl() device + * vector. Each device should include this file and redefine these names + * as their own. Because these are device dependent it is a good idea + * _NOT_ to issue them to random objects and hope. + * + * THESE IOCTLS ARE _DEPRECATED_ AND WILL DISAPPEAR IN 2.5.X -DaveM + */ + +#define SIOCDEVPRIVATE 0x89F0 /* to 89FF */ + +/* + * These 16 ioctl calls are protocol private + */ + +#define SIOCPROTOPRIVATE 0x89E0 /* to 89EF */ +#endif /* _LINUX_SOCKIOS_H */ diff --git a/original-kernel-headers/linux/sound/lsm_params.h b/original-kernel-headers/linux/sound/lsm_params.h new file mode 100644 index 0000000..a7e8187 --- /dev/null +++ b/original-kernel-headers/linux/sound/lsm_params.h @@ -0,0 +1,75 @@ +#ifndef _UAPI_LSM_PARAMS_H__ +#define _UAPI_LSM_PARAMS_H__ + +#include <linux/types.h> +#include <sound/asound.h> + +#define SNDRV_LSM_VERSION SNDRV_PROTOCOL_VERSION(0, 1, 0) + +enum lsm_app_id { + LSM_VOICE_WAKEUP_APP_ID = 1, + LSM_VOICE_WAKEUP_APP_ID_V2 = 2, +}; + +enum lsm_detection_mode { + LSM_MODE_KEYWORD_ONLY_DETECTION = 1, + LSM_MODE_USER_KEYWORD_DETECTION +}; + +enum lsm_vw_status { + LSM_VOICE_WAKEUP_STATUS_RUNNING = 1, + LSM_VOICE_WAKEUP_STATUS_DETECTED, + LSM_VOICE_WAKEUP_STATUS_END_SPEECH, + LSM_VOICE_WAKEUP_STATUS_REJECTED +}; + +struct snd_lsm_sound_model { + __u8 __user *data; + __u32 data_size; + enum lsm_detection_mode detection_mode; + __u16 min_keyw_confidence; + __u16 min_user_confidence; + bool detect_failure; +}; + +struct snd_lsm_sound_model_v2 { + __u8 __user *data; + __u8 *confidence_level; + __u32 data_size; + enum lsm_detection_mode detection_mode; + __u8 num_confidence_levels; + bool detect_failure; +}; + +struct snd_lsm_session_data { + enum lsm_app_id app_id; +}; + +struct snd_lsm_event_status { + __u16 status; + __u16 payload_size; + __u8 payload[0]; +}; + +struct snd_lsm_detection_params { + __u8 *conf_level; + enum lsm_detection_mode detect_mode; + __u8 num_confidence_levels; + bool detect_failure; +}; + +#define SNDRV_LSM_REG_SND_MODEL _IOW('U', 0x00, struct snd_lsm_sound_model) +#define SNDRV_LSM_DEREG_SND_MODEL _IOW('U', 0x01, int) +#define SNDRV_LSM_EVENT_STATUS _IOW('U', 0x02, struct snd_lsm_event_status) +#define SNDRV_LSM_ABORT_EVENT _IOW('U', 0x03, int) +#define SNDRV_LSM_START _IOW('U', 0x04, int) +#define SNDRV_LSM_STOP _IOW('U', 0x05, int) +#define SNDRV_LSM_SET_SESSION_DATA _IOW('U', 0x06, struct snd_lsm_session_data) +#define SNDRV_LSM_REG_SND_MODEL_V2 _IOW('U', 0x07,\ + struct snd_lsm_sound_model_v2) +#define SNDRV_LSM_LAB_CONTROL _IOW('U', 0x08, uint32_t) +#define SNDRV_LSM_STOP_LAB _IO('U', 0x09) +#define SNDRV_LSM_SET_PARAMS _IOW('U', 0x0A, \ + struct snd_lsm_detection_params) + +#endif diff --git a/original-kernel-headers/linux/v4l2-common.h b/original-kernel-headers/linux/v4l2-common.h new file mode 100644 index 0000000..4f0667e --- /dev/null +++ b/original-kernel-headers/linux/v4l2-common.h @@ -0,0 +1,71 @@ +/* + * include/linux/v4l2-common.h + * + * Common V4L2 and V4L2 subdev definitions. + * + * Users are advised to #include this file either through videodev2.h + * (V4L2) or through v4l2-subdev.h (V4L2 subdev) rather than to refer + * to this file directly. + * + * Copyright (C) 2012 Nokia Corporation + * Contact: Sakari Ailus <sakari.ailus@iki.fi> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA + * 02110-1301 USA + * + */ + +#ifndef __V4L2_COMMON__ +#define __V4L2_COMMON__ + +/* + * + * Selection interface definitions + * + */ + +/* Current cropping area */ +#define V4L2_SEL_TGT_CROP 0x0000 +/* Default cropping area */ +#define V4L2_SEL_TGT_CROP_DEFAULT 0x0001 +/* Cropping bounds */ +#define V4L2_SEL_TGT_CROP_BOUNDS 0x0002 +/* Current composing area */ +#define V4L2_SEL_TGT_COMPOSE 0x0100 +/* Default composing area */ +#define V4L2_SEL_TGT_COMPOSE_DEFAULT 0x0101 +/* Composing bounds */ +#define V4L2_SEL_TGT_COMPOSE_BOUNDS 0x0102 +/* Current composing area plus all padding pixels */ +#define V4L2_SEL_TGT_COMPOSE_PADDED 0x0103 + +/* Backward compatibility target definitions --- to be removed. */ +#define V4L2_SEL_TGT_CROP_ACTIVE V4L2_SEL_TGT_CROP +#define V4L2_SEL_TGT_COMPOSE_ACTIVE V4L2_SEL_TGT_COMPOSE +#define V4L2_SUBDEV_SEL_TGT_CROP_ACTUAL V4L2_SEL_TGT_CROP +#define V4L2_SUBDEV_SEL_TGT_COMPOSE_ACTUAL V4L2_SEL_TGT_COMPOSE +#define V4L2_SUBDEV_SEL_TGT_CROP_BOUNDS V4L2_SEL_TGT_CROP_BOUNDS +#define V4L2_SUBDEV_SEL_TGT_COMPOSE_BOUNDS V4L2_SEL_TGT_COMPOSE_BOUNDS + +/* Selection flags */ +#define V4L2_SEL_FLAG_GE (1 << 0) +#define V4L2_SEL_FLAG_LE (1 << 1) +#define V4L2_SEL_FLAG_KEEP_CONFIG (1 << 2) + +/* Backward compatibility flag definitions --- to be removed. */ +#define V4L2_SUBDEV_SEL_FLAG_SIZE_GE V4L2_SEL_FLAG_GE +#define V4L2_SUBDEV_SEL_FLAG_SIZE_LE V4L2_SEL_FLAG_LE +#define V4L2_SUBDEV_SEL_FLAG_KEEP_CONFIG V4L2_SEL_FLAG_KEEP_CONFIG + +#endif /* __V4L2_COMMON__ */ diff --git a/original-kernel-headers/linux/v4l2-controls.h b/original-kernel-headers/linux/v4l2-controls.h new file mode 100644 index 0000000..216abb7 --- /dev/null +++ b/original-kernel-headers/linux/v4l2-controls.h @@ -0,0 +1,1257 @@ +/* + * Video for Linux Two controls header file + * + * Copyright (C) 1999-2012 the contributors + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Alternatively you can redistribute this file under the terms of the + * BSD license as stated below: + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. The names of its contributors may not be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * The contents of this header was split off from videodev2.h. All control + * definitions should be added to this header, which is included by + * videodev2.h. + */ + +#ifndef __LINUX_V4L2_CONTROLS_H +#define __LINUX_V4L2_CONTROLS_H + +/* Control classes */ +#define V4L2_CTRL_CLASS_USER 0x00980000 /* Old-style 'user' controls */ +#define V4L2_CTRL_CLASS_MPEG 0x00990000 /* MPEG-compression controls */ +#define V4L2_CTRL_CLASS_CAMERA 0x009a0000 /* Camera class controls */ +#define V4L2_CTRL_CLASS_FM_TX 0x009b0000 /* FM Modulator control class */ +#define V4L2_CTRL_CLASS_FLASH 0x009c0000 /* Camera flash controls */ +#define V4L2_CTRL_CLASS_JPEG 0x009d0000 /* JPEG-compression controls */ +#define V4L2_CTRL_CLASS_IMAGE_SOURCE 0x009e0000 /* Image source controls */ +#define V4L2_CTRL_CLASS_IMAGE_PROC 0x009f0000 /* Image processing controls */ +#define V4L2_CTRL_CLASS_DV 0x00a00000 /* Digital Video controls */ +#define V4L2_CTRL_CLASS_FM_RX 0x00a10000 /* Digital Video controls */ + +/* User-class control IDs */ + +#define V4L2_CID_BASE (V4L2_CTRL_CLASS_USER | 0x900) +#define V4L2_CID_USER_BASE V4L2_CID_BASE +#define V4L2_CID_USER_CLASS (V4L2_CTRL_CLASS_USER | 1) +#define V4L2_CID_BRIGHTNESS (V4L2_CID_BASE+0) +#define V4L2_CID_CONTRAST (V4L2_CID_BASE+1) +#define V4L2_CID_SATURATION (V4L2_CID_BASE+2) +#define V4L2_CID_HUE (V4L2_CID_BASE+3) +#define V4L2_CID_AUDIO_VOLUME (V4L2_CID_BASE+5) +#define V4L2_CID_AUDIO_BALANCE (V4L2_CID_BASE+6) +#define V4L2_CID_AUDIO_BASS (V4L2_CID_BASE+7) +#define V4L2_CID_AUDIO_TREBLE (V4L2_CID_BASE+8) +#define V4L2_CID_AUDIO_MUTE (V4L2_CID_BASE+9) +#define V4L2_CID_AUDIO_LOUDNESS (V4L2_CID_BASE+10) +#define V4L2_CID_BLACK_LEVEL (V4L2_CID_BASE+11) /* Deprecated */ +#define V4L2_CID_AUTO_WHITE_BALANCE (V4L2_CID_BASE+12) +#define V4L2_CID_DO_WHITE_BALANCE (V4L2_CID_BASE+13) +#define V4L2_CID_RED_BALANCE (V4L2_CID_BASE+14) +#define V4L2_CID_BLUE_BALANCE (V4L2_CID_BASE+15) +#define V4L2_CID_GAMMA (V4L2_CID_BASE+16) +#define V4L2_CID_WHITENESS (V4L2_CID_GAMMA) /* Deprecated */ +#define V4L2_CID_EXPOSURE (V4L2_CID_BASE+17) +#define V4L2_CID_AUTOGAIN (V4L2_CID_BASE+18) +#define V4L2_CID_GAIN (V4L2_CID_BASE+19) +#define V4L2_CID_HFLIP (V4L2_CID_BASE+20) +#define V4L2_CID_VFLIP (V4L2_CID_BASE+21) + +#define V4L2_CID_POWER_LINE_FREQUENCY (V4L2_CID_BASE+24) +enum v4l2_power_line_frequency { + V4L2_CID_POWER_LINE_FREQUENCY_DISABLED = 0, + V4L2_CID_POWER_LINE_FREQUENCY_50HZ = 1, + V4L2_CID_POWER_LINE_FREQUENCY_60HZ = 2, + V4L2_CID_POWER_LINE_FREQUENCY_AUTO = 3, +}; +#define V4L2_CID_HUE_AUTO (V4L2_CID_BASE+25) +#define V4L2_CID_WHITE_BALANCE_TEMPERATURE (V4L2_CID_BASE+26) +#define V4L2_CID_SHARPNESS (V4L2_CID_BASE+27) +#define V4L2_CID_BACKLIGHT_COMPENSATION (V4L2_CID_BASE+28) +#define V4L2_CID_CHROMA_AGC (V4L2_CID_BASE+29) +#define V4L2_CID_COLOR_KILLER (V4L2_CID_BASE+30) +#define V4L2_CID_COLORFX (V4L2_CID_BASE+31) +enum v4l2_colorfx { + V4L2_COLORFX_NONE = 0, + V4L2_COLORFX_BW = 1, + V4L2_COLORFX_SEPIA = 2, + V4L2_COLORFX_NEGATIVE = 3, + V4L2_COLORFX_EMBOSS = 4, + V4L2_COLORFX_SKETCH = 5, + V4L2_COLORFX_SKY_BLUE = 6, + V4L2_COLORFX_GRASS_GREEN = 7, + V4L2_COLORFX_SKIN_WHITEN = 8, + V4L2_COLORFX_VIVID = 9, + V4L2_COLORFX_AQUA = 10, + V4L2_COLORFX_ART_FREEZE = 11, + V4L2_COLORFX_SILHOUETTE = 12, + V4L2_COLORFX_SOLARIZATION = 13, + V4L2_COLORFX_ANTIQUE = 14, + V4L2_COLORFX_SET_CBCR = 15, +}; +#define V4L2_CID_AUTOBRIGHTNESS (V4L2_CID_BASE+32) +#define V4L2_CID_BAND_STOP_FILTER (V4L2_CID_BASE+33) + +#define V4L2_CID_ROTATE (V4L2_CID_BASE+34) +#define V4L2_CID_BG_COLOR (V4L2_CID_BASE+35) + +#define V4L2_CID_CHROMA_GAIN (V4L2_CID_BASE+36) + +#define V4L2_CID_ILLUMINATORS_1 (V4L2_CID_BASE+37) +#define V4L2_CID_ILLUMINATORS_2 (V4L2_CID_BASE+38) + +#define V4L2_CID_MIN_BUFFERS_FOR_CAPTURE (V4L2_CID_BASE+39) +#define V4L2_CID_MIN_BUFFERS_FOR_OUTPUT (V4L2_CID_BASE+40) + +#define V4L2_CID_ALPHA_COMPONENT (V4L2_CID_BASE+41) +#define V4L2_CID_COLORFX_CBCR (V4L2_CID_BASE+42) + +/* last CID + 1 */ +#define V4L2_CID_LASTP1 (V4L2_CID_BASE+43) +#define V4L2_CID_SPECIAL_EFFECT (V4L2_CID_BASE+44) +/* Minimum number of buffer neede by the device */ + +/* USER-class private control IDs */ + +/* The base for the meye driver controls. See linux/meye.h for the list + * of controls. We reserve 16 controls for this driver. */ +#define V4L2_CID_USER_MEYE_BASE (V4L2_CID_USER_BASE + 0x1000) + +/* The base for the bttv driver controls. + * We reserve 32 controls for this driver. */ +#define V4L2_CID_USER_BTTV_BASE (V4L2_CID_USER_BASE + 0x1010) + + +/* The base for the s2255 driver controls. + * We reserve 16 controls for this driver. */ +#define V4L2_CID_USER_S2255_BASE (V4L2_CID_USER_BASE + 0x1030) + +/* The base for the si476x driver controls. See include/media/si476x.h for the list + * of controls. Total of 16 controls is reserved for this driver */ +#define V4L2_CID_USER_SI476X_BASE (V4L2_CID_USER_BASE + 0x1040) + +/* MPEG-class control IDs */ + +#define V4L2_CID_MPEG_BASE (V4L2_CTRL_CLASS_MPEG | 0x900) +#define V4L2_CID_MPEG_CLASS (V4L2_CTRL_CLASS_MPEG | 1) + +/* MPEG streams, specific to multiplexed streams */ +#define V4L2_CID_MPEG_STREAM_TYPE (V4L2_CID_MPEG_BASE+0) +enum v4l2_mpeg_stream_type { + V4L2_MPEG_STREAM_TYPE_MPEG2_PS = 0, /* MPEG-2 program stream */ + V4L2_MPEG_STREAM_TYPE_MPEG2_TS = 1, /* MPEG-2 transport stream */ + V4L2_MPEG_STREAM_TYPE_MPEG1_SS = 2, /* MPEG-1 system stream */ + V4L2_MPEG_STREAM_TYPE_MPEG2_DVD = 3, /* MPEG-2 DVD-compatible stream */ + V4L2_MPEG_STREAM_TYPE_MPEG1_VCD = 4, /* MPEG-1 VCD-compatible stream */ + V4L2_MPEG_STREAM_TYPE_MPEG2_SVCD = 5, /* MPEG-2 SVCD-compatible stream */ +}; +#define V4L2_CID_MPEG_STREAM_PID_PMT (V4L2_CID_MPEG_BASE+1) +#define V4L2_CID_MPEG_STREAM_PID_AUDIO (V4L2_CID_MPEG_BASE+2) +#define V4L2_CID_MPEG_STREAM_PID_VIDEO (V4L2_CID_MPEG_BASE+3) +#define V4L2_CID_MPEG_STREAM_PID_PCR (V4L2_CID_MPEG_BASE+4) +#define V4L2_CID_MPEG_STREAM_PES_ID_AUDIO (V4L2_CID_MPEG_BASE+5) +#define V4L2_CID_MPEG_STREAM_PES_ID_VIDEO (V4L2_CID_MPEG_BASE+6) +#define V4L2_CID_MPEG_STREAM_VBI_FMT (V4L2_CID_MPEG_BASE+7) +enum v4l2_mpeg_stream_vbi_fmt { + V4L2_MPEG_STREAM_VBI_FMT_NONE = 0, /* No VBI in the MPEG stream */ + V4L2_MPEG_STREAM_VBI_FMT_IVTV = 1, /* VBI in private packets, IVTV format */ +}; + +/* MPEG audio controls specific to multiplexed streams */ +#define V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ (V4L2_CID_MPEG_BASE+100) +enum v4l2_mpeg_audio_sampling_freq { + V4L2_MPEG_AUDIO_SAMPLING_FREQ_44100 = 0, + V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000 = 1, + V4L2_MPEG_AUDIO_SAMPLING_FREQ_32000 = 2, +}; +#define V4L2_CID_MPEG_AUDIO_ENCODING (V4L2_CID_MPEG_BASE+101) +enum v4l2_mpeg_audio_encoding { + V4L2_MPEG_AUDIO_ENCODING_LAYER_1 = 0, + V4L2_MPEG_AUDIO_ENCODING_LAYER_2 = 1, + V4L2_MPEG_AUDIO_ENCODING_LAYER_3 = 2, + V4L2_MPEG_AUDIO_ENCODING_AAC = 3, + V4L2_MPEG_AUDIO_ENCODING_AC3 = 4, +}; +#define V4L2_CID_MPEG_AUDIO_L1_BITRATE (V4L2_CID_MPEG_BASE+102) +enum v4l2_mpeg_audio_l1_bitrate { + V4L2_MPEG_AUDIO_L1_BITRATE_32K = 0, + V4L2_MPEG_AUDIO_L1_BITRATE_64K = 1, + V4L2_MPEG_AUDIO_L1_BITRATE_96K = 2, + V4L2_MPEG_AUDIO_L1_BITRATE_128K = 3, + V4L2_MPEG_AUDIO_L1_BITRATE_160K = 4, + V4L2_MPEG_AUDIO_L1_BITRATE_192K = 5, + V4L2_MPEG_AUDIO_L1_BITRATE_224K = 6, + V4L2_MPEG_AUDIO_L1_BITRATE_256K = 7, + V4L2_MPEG_AUDIO_L1_BITRATE_288K = 8, + V4L2_MPEG_AUDIO_L1_BITRATE_320K = 9, + V4L2_MPEG_AUDIO_L1_BITRATE_352K = 10, + V4L2_MPEG_AUDIO_L1_BITRATE_384K = 11, + V4L2_MPEG_AUDIO_L1_BITRATE_416K = 12, + V4L2_MPEG_AUDIO_L1_BITRATE_448K = 13, +}; +#define V4L2_CID_MPEG_AUDIO_L2_BITRATE (V4L2_CID_MPEG_BASE+103) +enum v4l2_mpeg_audio_l2_bitrate { + V4L2_MPEG_AUDIO_L2_BITRATE_32K = 0, + V4L2_MPEG_AUDIO_L2_BITRATE_48K = 1, + V4L2_MPEG_AUDIO_L2_BITRATE_56K = 2, + V4L2_MPEG_AUDIO_L2_BITRATE_64K = 3, + V4L2_MPEG_AUDIO_L2_BITRATE_80K = 4, + V4L2_MPEG_AUDIO_L2_BITRATE_96K = 5, + V4L2_MPEG_AUDIO_L2_BITRATE_112K = 6, + V4L2_MPEG_AUDIO_L2_BITRATE_128K = 7, + V4L2_MPEG_AUDIO_L2_BITRATE_160K = 8, + V4L2_MPEG_AUDIO_L2_BITRATE_192K = 9, + V4L2_MPEG_AUDIO_L2_BITRATE_224K = 10, + V4L2_MPEG_AUDIO_L2_BITRATE_256K = 11, + V4L2_MPEG_AUDIO_L2_BITRATE_320K = 12, + V4L2_MPEG_AUDIO_L2_BITRATE_384K = 13, +}; +#define V4L2_CID_MPEG_AUDIO_L3_BITRATE (V4L2_CID_MPEG_BASE+104) +enum v4l2_mpeg_audio_l3_bitrate { + V4L2_MPEG_AUDIO_L3_BITRATE_32K = 0, + V4L2_MPEG_AUDIO_L3_BITRATE_40K = 1, + V4L2_MPEG_AUDIO_L3_BITRATE_48K = 2, + V4L2_MPEG_AUDIO_L3_BITRATE_56K = 3, + V4L2_MPEG_AUDIO_L3_BITRATE_64K = 4, + V4L2_MPEG_AUDIO_L3_BITRATE_80K = 5, + V4L2_MPEG_AUDIO_L3_BITRATE_96K = 6, + V4L2_MPEG_AUDIO_L3_BITRATE_112K = 7, + V4L2_MPEG_AUDIO_L3_BITRATE_128K = 8, + V4L2_MPEG_AUDIO_L3_BITRATE_160K = 9, + V4L2_MPEG_AUDIO_L3_BITRATE_192K = 10, + V4L2_MPEG_AUDIO_L3_BITRATE_224K = 11, + V4L2_MPEG_AUDIO_L3_BITRATE_256K = 12, + V4L2_MPEG_AUDIO_L3_BITRATE_320K = 13, +}; +#define V4L2_CID_MPEG_AUDIO_MODE (V4L2_CID_MPEG_BASE+105) +enum v4l2_mpeg_audio_mode { + V4L2_MPEG_AUDIO_MODE_STEREO = 0, + V4L2_MPEG_AUDIO_MODE_JOINT_STEREO = 1, + V4L2_MPEG_AUDIO_MODE_DUAL = 2, + V4L2_MPEG_AUDIO_MODE_MONO = 3, +}; +#define V4L2_CID_MPEG_AUDIO_MODE_EXTENSION (V4L2_CID_MPEG_BASE+106) +enum v4l2_mpeg_audio_mode_extension { + V4L2_MPEG_AUDIO_MODE_EXTENSION_BOUND_4 = 0, + V4L2_MPEG_AUDIO_MODE_EXTENSION_BOUND_8 = 1, + V4L2_MPEG_AUDIO_MODE_EXTENSION_BOUND_12 = 2, + V4L2_MPEG_AUDIO_MODE_EXTENSION_BOUND_16 = 3, +}; +#define V4L2_CID_MPEG_AUDIO_EMPHASIS (V4L2_CID_MPEG_BASE+107) +enum v4l2_mpeg_audio_emphasis { + V4L2_MPEG_AUDIO_EMPHASIS_NONE = 0, + V4L2_MPEG_AUDIO_EMPHASIS_50_DIV_15_uS = 1, + V4L2_MPEG_AUDIO_EMPHASIS_CCITT_J17 = 2, +}; +#define V4L2_CID_MPEG_AUDIO_CRC (V4L2_CID_MPEG_BASE+108) +enum v4l2_mpeg_audio_crc { + V4L2_MPEG_AUDIO_CRC_NONE = 0, + V4L2_MPEG_AUDIO_CRC_CRC16 = 1, +}; +#define V4L2_CID_MPEG_AUDIO_MUTE (V4L2_CID_MPEG_BASE+109) +#define V4L2_CID_MPEG_AUDIO_AAC_BITRATE (V4L2_CID_MPEG_BASE+110) +#define V4L2_CID_MPEG_AUDIO_AC3_BITRATE (V4L2_CID_MPEG_BASE+111) +enum v4l2_mpeg_audio_ac3_bitrate { + V4L2_MPEG_AUDIO_AC3_BITRATE_32K = 0, + V4L2_MPEG_AUDIO_AC3_BITRATE_40K = 1, + V4L2_MPEG_AUDIO_AC3_BITRATE_48K = 2, + V4L2_MPEG_AUDIO_AC3_BITRATE_56K = 3, + V4L2_MPEG_AUDIO_AC3_BITRATE_64K = 4, + V4L2_MPEG_AUDIO_AC3_BITRATE_80K = 5, + V4L2_MPEG_AUDIO_AC3_BITRATE_96K = 6, + V4L2_MPEG_AUDIO_AC3_BITRATE_112K = 7, + V4L2_MPEG_AUDIO_AC3_BITRATE_128K = 8, + V4L2_MPEG_AUDIO_AC3_BITRATE_160K = 9, + V4L2_MPEG_AUDIO_AC3_BITRATE_192K = 10, + V4L2_MPEG_AUDIO_AC3_BITRATE_224K = 11, + V4L2_MPEG_AUDIO_AC3_BITRATE_256K = 12, + V4L2_MPEG_AUDIO_AC3_BITRATE_320K = 13, + V4L2_MPEG_AUDIO_AC3_BITRATE_384K = 14, + V4L2_MPEG_AUDIO_AC3_BITRATE_448K = 15, + V4L2_MPEG_AUDIO_AC3_BITRATE_512K = 16, + V4L2_MPEG_AUDIO_AC3_BITRATE_576K = 17, + V4L2_MPEG_AUDIO_AC3_BITRATE_640K = 18, +}; +#define V4L2_CID_MPEG_AUDIO_DEC_PLAYBACK (V4L2_CID_MPEG_BASE+112) +enum v4l2_mpeg_audio_dec_playback { + V4L2_MPEG_AUDIO_DEC_PLAYBACK_AUTO = 0, + V4L2_MPEG_AUDIO_DEC_PLAYBACK_STEREO = 1, + V4L2_MPEG_AUDIO_DEC_PLAYBACK_LEFT = 2, + V4L2_MPEG_AUDIO_DEC_PLAYBACK_RIGHT = 3, + V4L2_MPEG_AUDIO_DEC_PLAYBACK_MONO = 4, + V4L2_MPEG_AUDIO_DEC_PLAYBACK_SWAPPED_STEREO = 5, +}; +#define V4L2_CID_MPEG_AUDIO_DEC_MULTILINGUAL_PLAYBACK (V4L2_CID_MPEG_BASE+113) + +/* MPEG video controls specific to multiplexed streams */ +#define V4L2_CID_MPEG_VIDEO_ENCODING (V4L2_CID_MPEG_BASE+200) +enum v4l2_mpeg_video_encoding { + V4L2_MPEG_VIDEO_ENCODING_MPEG_1 = 0, + V4L2_MPEG_VIDEO_ENCODING_MPEG_2 = 1, + V4L2_MPEG_VIDEO_ENCODING_MPEG_4_AVC = 2, +}; +#define V4L2_CID_MPEG_VIDEO_ASPECT (V4L2_CID_MPEG_BASE+201) +enum v4l2_mpeg_video_aspect { + V4L2_MPEG_VIDEO_ASPECT_1x1 = 0, + V4L2_MPEG_VIDEO_ASPECT_4x3 = 1, + V4L2_MPEG_VIDEO_ASPECT_16x9 = 2, + V4L2_MPEG_VIDEO_ASPECT_221x100 = 3, +}; +#define V4L2_CID_MPEG_VIDEO_B_FRAMES (V4L2_CID_MPEG_BASE+202) +#define V4L2_CID_MPEG_VIDEO_GOP_SIZE (V4L2_CID_MPEG_BASE+203) +#define V4L2_CID_MPEG_VIDEO_GOP_CLOSURE (V4L2_CID_MPEG_BASE+204) +#define V4L2_CID_MPEG_VIDEO_PULLDOWN (V4L2_CID_MPEG_BASE+205) +#define V4L2_CID_MPEG_VIDEO_BITRATE_MODE (V4L2_CID_MPEG_BASE+206) +enum v4l2_mpeg_video_bitrate_mode { + V4L2_MPEG_VIDEO_BITRATE_MODE_VBR = 0, + V4L2_MPEG_VIDEO_BITRATE_MODE_CBR = 1, +}; +#define V4L2_CID_MPEG_VIDEO_BITRATE (V4L2_CID_MPEG_BASE+207) +#define V4L2_CID_MPEG_VIDEO_BITRATE_PEAK (V4L2_CID_MPEG_BASE+208) +#define V4L2_CID_MPEG_VIDEO_TEMPORAL_DECIMATION (V4L2_CID_MPEG_BASE+209) +#define V4L2_CID_MPEG_VIDEO_MUTE (V4L2_CID_MPEG_BASE+210) +#define V4L2_CID_MPEG_VIDEO_MUTE_YUV (V4L2_CID_MPEG_BASE+211) +#define V4L2_CID_MPEG_VIDEO_DECODER_SLICE_INTERFACE (V4L2_CID_MPEG_BASE+212) +#define V4L2_CID_MPEG_VIDEO_DECODER_MPEG4_DEBLOCK_FILTER (V4L2_CID_MPEG_BASE+213) +#define V4L2_CID_MPEG_VIDEO_CYCLIC_INTRA_REFRESH_MB (V4L2_CID_MPEG_BASE+214) +#define V4L2_CID_MPEG_VIDEO_FRAME_RC_ENABLE (V4L2_CID_MPEG_BASE+215) +#define V4L2_CID_MPEG_VIDEO_HEADER_MODE (V4L2_CID_MPEG_BASE+216) +enum v4l2_mpeg_video_header_mode { + V4L2_MPEG_VIDEO_HEADER_MODE_SEPARATE = 0, + V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME = 1, + V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_I_FRAME = 2, + +}; +#define V4L2_CID_MPEG_VIDEO_MAX_REF_PIC (V4L2_CID_MPEG_BASE+217) +#define V4L2_CID_MPEG_VIDEO_MB_RC_ENABLE (V4L2_CID_MPEG_BASE+218) +#define V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MAX_BYTES (V4L2_CID_MPEG_BASE+219) +#define V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MAX_MB (V4L2_CID_MPEG_BASE+220) +#define V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MODE (V4L2_CID_MPEG_BASE+221) +enum v4l2_mpeg_video_multi_slice_mode { + V4L2_MPEG_VIDEO_MULTI_SLICE_MODE_SINGLE = 0, + V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_MB = 1, + V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_BYTES = 2, + V4L2_MPEG_VIDEO_MULTI_SLICE_GOB = 3, +}; +#define V4L2_CID_MPEG_VIDEO_VBV_SIZE (V4L2_CID_MPEG_BASE+222) +#define V4L2_CID_MPEG_VIDEO_DEC_PTS (V4L2_CID_MPEG_BASE+223) +#define V4L2_CID_MPEG_VIDEO_DEC_FRAME (V4L2_CID_MPEG_BASE+224) +#define V4L2_CID_MPEG_VIDEO_VBV_DELAY (V4L2_CID_MPEG_BASE+225) +#define V4L2_CID_MPEG_VIDEO_REPEAT_SEQ_HEADER (V4L2_CID_MPEG_BASE+226) + +#define V4L2_CID_MPEG_VIDEO_H263_I_FRAME_QP (V4L2_CID_MPEG_BASE+300) +#define V4L2_CID_MPEG_VIDEO_H263_P_FRAME_QP (V4L2_CID_MPEG_BASE+301) +#define V4L2_CID_MPEG_VIDEO_H263_B_FRAME_QP (V4L2_CID_MPEG_BASE+302) +#define V4L2_CID_MPEG_VIDEO_H263_MIN_QP (V4L2_CID_MPEG_BASE+303) +#define V4L2_CID_MPEG_VIDEO_H263_MAX_QP (V4L2_CID_MPEG_BASE+304) +#define V4L2_CID_MPEG_VIDEO_H264_I_FRAME_QP (V4L2_CID_MPEG_BASE+350) +#define V4L2_CID_MPEG_VIDEO_H264_P_FRAME_QP (V4L2_CID_MPEG_BASE+351) +#define V4L2_CID_MPEG_VIDEO_H264_B_FRAME_QP (V4L2_CID_MPEG_BASE+352) +#define V4L2_CID_MPEG_VIDEO_H264_MIN_QP (V4L2_CID_MPEG_BASE+353) +#define V4L2_CID_MPEG_VIDEO_H264_MAX_QP (V4L2_CID_MPEG_BASE+354) +#define V4L2_CID_MPEG_VIDEO_H264_8X8_TRANSFORM (V4L2_CID_MPEG_BASE+355) +#define V4L2_CID_MPEG_VIDEO_H264_CPB_SIZE (V4L2_CID_MPEG_BASE+356) +#define V4L2_CID_MPEG_VIDEO_H264_ENTROPY_MODE (V4L2_CID_MPEG_BASE+357) +enum v4l2_mpeg_video_h264_entropy_mode { + V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CAVLC = 0, + V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CABAC = 1, +}; +#define V4L2_CID_MPEG_VIDEO_H264_I_PERIOD (V4L2_CID_MPEG_BASE+358) +#define V4L2_CID_MPEG_VIDEO_H264_LEVEL (V4L2_CID_MPEG_BASE+359) +enum v4l2_mpeg_video_h264_level { + V4L2_MPEG_VIDEO_H264_LEVEL_1_0 = 0, + V4L2_MPEG_VIDEO_H264_LEVEL_1B = 1, + V4L2_MPEG_VIDEO_H264_LEVEL_1_1 = 2, + V4L2_MPEG_VIDEO_H264_LEVEL_1_2 = 3, + V4L2_MPEG_VIDEO_H264_LEVEL_1_3 = 4, + V4L2_MPEG_VIDEO_H264_LEVEL_2_0 = 5, + V4L2_MPEG_VIDEO_H264_LEVEL_2_1 = 6, + V4L2_MPEG_VIDEO_H264_LEVEL_2_2 = 7, + V4L2_MPEG_VIDEO_H264_LEVEL_3_0 = 8, + V4L2_MPEG_VIDEO_H264_LEVEL_3_1 = 9, + V4L2_MPEG_VIDEO_H264_LEVEL_3_2 = 10, + V4L2_MPEG_VIDEO_H264_LEVEL_4_0 = 11, + V4L2_MPEG_VIDEO_H264_LEVEL_4_1 = 12, + V4L2_MPEG_VIDEO_H264_LEVEL_4_2 = 13, + V4L2_MPEG_VIDEO_H264_LEVEL_5_0 = 14, + V4L2_MPEG_VIDEO_H264_LEVEL_5_1 = 15, + V4L2_MPEG_VIDEO_H264_LEVEL_5_2 = 16, +}; +#define V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_ALPHA (V4L2_CID_MPEG_BASE+360) +#define V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_BETA (V4L2_CID_MPEG_BASE+361) +#define V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_MODE (V4L2_CID_MPEG_BASE+362) +enum v4l2_mpeg_video_h264_loop_filter_mode { + V4L2_MPEG_VIDEO_H264_LOOP_FILTER_MODE_DISABLED = 0, + V4L2_MPEG_VIDEO_H264_LOOP_FILTER_MODE_ENABLED = 1, + V4L2_MPEG_VIDEO_H264_LOOP_FILTER_MODE_DISABLED_AT_SLICE_BOUNDARY + = 2, +}; +#define V4L2_CID_MPEG_VIDEO_H264_PROFILE (V4L2_CID_MPEG_BASE+363) +enum v4l2_mpeg_video_h264_profile { + V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE = 0, + V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_BASELINE = 1, + V4L2_MPEG_VIDEO_H264_PROFILE_MAIN = 2, + V4L2_MPEG_VIDEO_H264_PROFILE_EXTENDED = 3, + V4L2_MPEG_VIDEO_H264_PROFILE_HIGH = 4, + V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_10 = 5, + V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_422 = 6, + V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_444_PREDICTIVE = 7, + V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_10_INTRA = 8, + V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_422_INTRA = 9, + V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_444_INTRA = 10, + V4L2_MPEG_VIDEO_H264_PROFILE_CAVLC_444_INTRA = 11, + V4L2_MPEG_VIDEO_H264_PROFILE_SCALABLE_BASELINE = 12, + V4L2_MPEG_VIDEO_H264_PROFILE_SCALABLE_HIGH = 13, + V4L2_MPEG_VIDEO_H264_PROFILE_SCALABLE_HIGH_INTRA = 14, + V4L2_MPEG_VIDEO_H264_PROFILE_STEREO_HIGH = 15, + V4L2_MPEG_VIDEO_H264_PROFILE_MULTIVIEW_HIGH = 16, + V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_HIGH = 17, +}; +#define V4L2_CID_MPEG_VIDEO_H264_VUI_EXT_SAR_HEIGHT (V4L2_CID_MPEG_BASE+364) +#define V4L2_CID_MPEG_VIDEO_H264_VUI_EXT_SAR_WIDTH (V4L2_CID_MPEG_BASE+365) +#define V4L2_CID_MPEG_VIDEO_H264_VUI_SAR_ENABLE (V4L2_CID_MPEG_BASE+366) +#define V4L2_CID_MPEG_VIDEO_H264_VUI_SAR_IDC (V4L2_CID_MPEG_BASE+367) +enum v4l2_mpeg_video_h264_vui_sar_idc { + V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_UNSPECIFIED = 0, + V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_1x1 = 1, + V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_12x11 = 2, + V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_10x11 = 3, + V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_16x11 = 4, + V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_40x33 = 5, + V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_24x11 = 6, + V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_20x11 = 7, + V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_32x11 = 8, + V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_80x33 = 9, + V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_18x11 = 10, + V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_15x11 = 11, + V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_64x33 = 12, + V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_160x99 = 13, + V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_4x3 = 14, + V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_3x2 = 15, + V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_2x1 = 16, + V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_EXTENDED = 17, +}; +#define V4L2_CID_MPEG_VIDEO_H264_SEI_FRAME_PACKING (V4L2_CID_MPEG_BASE+368) +#define V4L2_CID_MPEG_VIDEO_H264_SEI_FP_CURRENT_FRAME_0 (V4L2_CID_MPEG_BASE+369) +#define V4L2_CID_MPEG_VIDEO_H264_SEI_FP_ARRANGEMENT_TYPE (V4L2_CID_MPEG_BASE+370) +enum v4l2_mpeg_video_h264_sei_fp_arrangement_type { + V4L2_MPEG_VIDEO_H264_SEI_FP_ARRANGEMENT_TYPE_CHECKERBOARD = 0, + V4L2_MPEG_VIDEO_H264_SEI_FP_ARRANGEMENT_TYPE_COLUMN = 1, + V4L2_MPEG_VIDEO_H264_SEI_FP_ARRANGEMENT_TYPE_ROW = 2, + V4L2_MPEG_VIDEO_H264_SEI_FP_ARRANGEMENT_TYPE_SIDE_BY_SIDE = 3, + V4L2_MPEG_VIDEO_H264_SEI_FP_ARRANGEMENT_TYPE_TOP_BOTTOM = 4, + V4L2_MPEG_VIDEO_H264_SEI_FP_ARRANGEMENT_TYPE_TEMPORAL = 5, +}; +#define V4L2_CID_MPEG_VIDEO_H264_FMO (V4L2_CID_MPEG_BASE+371) +#define V4L2_CID_MPEG_VIDEO_H264_FMO_MAP_TYPE (V4L2_CID_MPEG_BASE+372) +enum v4l2_mpeg_video_h264_fmo_map_type { + V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_INTERLEAVED_SLICES = 0, + V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_SCATTERED_SLICES = 1, + V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_FOREGROUND_WITH_LEFT_OVER = 2, + V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_BOX_OUT = 3, + V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_RASTER_SCAN = 4, + V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_WIPE_SCAN = 5, + V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_EXPLICIT = 6, +}; +#define V4L2_CID_MPEG_VIDEO_H264_FMO_SLICE_GROUP (V4L2_CID_MPEG_BASE+373) +#define V4L2_CID_MPEG_VIDEO_H264_FMO_CHANGE_DIRECTION (V4L2_CID_MPEG_BASE+374) +enum v4l2_mpeg_video_h264_fmo_change_dir { + V4L2_MPEG_VIDEO_H264_FMO_CHANGE_DIR_RIGHT = 0, + V4L2_MPEG_VIDEO_H264_FMO_CHANGE_DIR_LEFT = 1, +}; +#define V4L2_CID_MPEG_VIDEO_H264_FMO_CHANGE_RATE (V4L2_CID_MPEG_BASE+375) +#define V4L2_CID_MPEG_VIDEO_H264_FMO_RUN_LENGTH (V4L2_CID_MPEG_BASE+376) +#define V4L2_CID_MPEG_VIDEO_H264_ASO (V4L2_CID_MPEG_BASE+377) +#define V4L2_CID_MPEG_VIDEO_H264_ASO_SLICE_ORDER (V4L2_CID_MPEG_BASE+378) +#define V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING (V4L2_CID_MPEG_BASE+379) +#define V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING_TYPE (V4L2_CID_MPEG_BASE+380) +enum v4l2_mpeg_video_h264_hierarchical_coding_type { + V4L2_MPEG_VIDEO_H264_HIERARCHICAL_CODING_B = 0, + V4L2_MPEG_VIDEO_H264_HIERARCHICAL_CODING_P = 1, +}; +#define V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING_LAYER (V4L2_CID_MPEG_BASE+381) +#define V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING_LAYER_QP (V4L2_CID_MPEG_BASE+382) +#define V4L2_CID_MPEG_VIDEO_MPEG4_I_FRAME_QP (V4L2_CID_MPEG_BASE+400) +#define V4L2_CID_MPEG_VIDEO_MPEG4_P_FRAME_QP (V4L2_CID_MPEG_BASE+401) +#define V4L2_CID_MPEG_VIDEO_MPEG4_B_FRAME_QP (V4L2_CID_MPEG_BASE+402) +#define V4L2_CID_MPEG_VIDEO_MPEG4_MIN_QP (V4L2_CID_MPEG_BASE+403) +#define V4L2_CID_MPEG_VIDEO_MPEG4_MAX_QP (V4L2_CID_MPEG_BASE+404) +#define V4L2_CID_MPEG_VIDEO_MPEG4_LEVEL (V4L2_CID_MPEG_BASE+405) +enum v4l2_mpeg_video_mpeg4_level { + V4L2_MPEG_VIDEO_MPEG4_LEVEL_0 = 0, + V4L2_MPEG_VIDEO_MPEG4_LEVEL_0B = 1, + V4L2_MPEG_VIDEO_MPEG4_LEVEL_1 = 2, + V4L2_MPEG_VIDEO_MPEG4_LEVEL_2 = 3, + V4L2_MPEG_VIDEO_MPEG4_LEVEL_3 = 4, + V4L2_MPEG_VIDEO_MPEG4_LEVEL_3B = 5, + V4L2_MPEG_VIDEO_MPEG4_LEVEL_4 = 6, + V4L2_MPEG_VIDEO_MPEG4_LEVEL_5 = 7, +}; +#define V4L2_CID_MPEG_VIDEO_MPEG4_PROFILE (V4L2_CID_MPEG_BASE+406) +enum v4l2_mpeg_video_mpeg4_profile { + V4L2_MPEG_VIDEO_MPEG4_PROFILE_SIMPLE = 0, + V4L2_MPEG_VIDEO_MPEG4_PROFILE_ADVANCED_SIMPLE = 1, + V4L2_MPEG_VIDEO_MPEG4_PROFILE_CORE = 2, + V4L2_MPEG_VIDEO_MPEG4_PROFILE_SIMPLE_SCALABLE = 3, + V4L2_MPEG_VIDEO_MPEG4_PROFILE_ADVANCED_CODING_EFFICIENCY = 4, +}; +#define V4L2_CID_MPEG_VIDEO_MPEG4_QPEL (V4L2_CID_MPEG_BASE+407) +#define V4L2_CID_QCOM_VIDEO_SYNC_FRAME_SEQ_HDR (V4L2_CID_MPEG_BASE+408) + +/* MPEG-class control IDs specific to the CX2341x driver as defined by V4L2 */ +#define V4L2_CID_MPEG_CX2341X_BASE (V4L2_CTRL_CLASS_MPEG | 0x1000) +#define V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER_MODE (V4L2_CID_MPEG_CX2341X_BASE+0) +enum v4l2_mpeg_cx2341x_video_spatial_filter_mode { + V4L2_MPEG_CX2341X_VIDEO_SPATIAL_FILTER_MODE_MANUAL = 0, + V4L2_MPEG_CX2341X_VIDEO_SPATIAL_FILTER_MODE_AUTO = 1, +}; +#define V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER (V4L2_CID_MPEG_CX2341X_BASE+1) +#define V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE (V4L2_CID_MPEG_CX2341X_BASE+2) +enum v4l2_mpeg_cx2341x_video_luma_spatial_filter_type { + V4L2_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE_OFF = 0, + V4L2_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE_1D_HOR = 1, + V4L2_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE_1D_VERT = 2, + V4L2_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE_2D_HV_SEPARABLE = 3, + V4L2_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE_2D_SYM_NON_SEPARABLE = 4, +}; +#define V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_SPATIAL_FILTER_TYPE (V4L2_CID_MPEG_CX2341X_BASE+3) +enum v4l2_mpeg_cx2341x_video_chroma_spatial_filter_type { + V4L2_MPEG_CX2341X_VIDEO_CHROMA_SPATIAL_FILTER_TYPE_OFF = 0, + V4L2_MPEG_CX2341X_VIDEO_CHROMA_SPATIAL_FILTER_TYPE_1D_HOR = 1, +}; +#define V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER_MODE (V4L2_CID_MPEG_CX2341X_BASE+4) +enum v4l2_mpeg_cx2341x_video_temporal_filter_mode { + V4L2_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER_MODE_MANUAL = 0, + V4L2_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER_MODE_AUTO = 1, +}; +#define V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER (V4L2_CID_MPEG_CX2341X_BASE+5) +#define V4L2_CID_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE (V4L2_CID_MPEG_CX2341X_BASE+6) +enum v4l2_mpeg_cx2341x_video_median_filter_type { + V4L2_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE_OFF = 0, + V4L2_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE_HOR = 1, + V4L2_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE_VERT = 2, + V4L2_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE_HOR_VERT = 3, + V4L2_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE_DIAG = 4, +}; +#define V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_BOTTOM (V4L2_CID_MPEG_CX2341X_BASE+7) +#define V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_TOP (V4L2_CID_MPEG_CX2341X_BASE+8) +#define V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_BOTTOM (V4L2_CID_MPEG_CX2341X_BASE+9) +#define V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_TOP (V4L2_CID_MPEG_CX2341X_BASE+10) +#define V4L2_CID_MPEG_CX2341X_STREAM_INSERT_NAV_PACKETS (V4L2_CID_MPEG_CX2341X_BASE+11) + +/* MPEG-class control IDs specific to the Samsung MFC 5.1 driver as defined by V4L2 */ +#define V4L2_CID_MPEG_MFC51_BASE (V4L2_CTRL_CLASS_MPEG | 0x1100) + +#define V4L2_CID_MPEG_MFC51_VIDEO_DECODER_H264_DISPLAY_DELAY (V4L2_CID_MPEG_MFC51_BASE+0) +#define V4L2_CID_MPEG_MFC51_VIDEO_DECODER_H264_DISPLAY_DELAY_ENABLE (V4L2_CID_MPEG_MFC51_BASE+1) +#define V4L2_CID_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE (V4L2_CID_MPEG_MFC51_BASE+2) +enum v4l2_mpeg_mfc51_video_frame_skip_mode { + V4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_DISABLED = 0, + V4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_LEVEL_LIMIT = 1, + V4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT = 2, +}; +#define V4L2_CID_MPEG_MFC51_VIDEO_FORCE_FRAME_TYPE (V4L2_CID_MPEG_MFC51_BASE+3) +enum v4l2_mpeg_mfc51_video_force_frame_type { + V4L2_MPEG_MFC51_VIDEO_FORCE_FRAME_TYPE_DISABLED = 0, + V4L2_MPEG_MFC51_VIDEO_FORCE_FRAME_TYPE_I_FRAME = 1, + V4L2_MPEG_MFC51_VIDEO_FORCE_FRAME_TYPE_NOT_CODED = 2, +}; +#define V4L2_CID_MPEG_MFC51_VIDEO_PADDING (V4L2_CID_MPEG_MFC51_BASE+4) +#define V4L2_CID_MPEG_MFC51_VIDEO_PADDING_YUV (V4L2_CID_MPEG_MFC51_BASE+5) +#define V4L2_CID_MPEG_MFC51_VIDEO_RC_FIXED_TARGET_BIT (V4L2_CID_MPEG_MFC51_BASE+6) +#define V4L2_CID_MPEG_MFC51_VIDEO_RC_REACTION_COEFF (V4L2_CID_MPEG_MFC51_BASE+7) +#define V4L2_CID_MPEG_MFC51_VIDEO_H264_ADAPTIVE_RC_ACTIVITY (V4L2_CID_MPEG_MFC51_BASE+50) +#define V4L2_CID_MPEG_MFC51_VIDEO_H264_ADAPTIVE_RC_DARK (V4L2_CID_MPEG_MFC51_BASE+51) +#define V4L2_CID_MPEG_MFC51_VIDEO_H264_ADAPTIVE_RC_SMOOTH (V4L2_CID_MPEG_MFC51_BASE+52) +#define V4L2_CID_MPEG_MFC51_VIDEO_H264_ADAPTIVE_RC_STATIC (V4L2_CID_MPEG_MFC51_BASE+53) +#define V4L2_CID_MPEG_MFC51_VIDEO_H264_NUM_REF_PIC_FOR_P (V4L2_CID_MPEG_MFC51_BASE+54) + +/* MPEG-class control IDs specific to the msm_vidc driver */ +#define V4L2_CID_MPEG_MSM_VIDC_BASE (V4L2_CTRL_CLASS_MPEG | 0x2000) + +#define V4L2_CID_MPEG_VIDC_VIDEO_ENABLE_PICTURE_TYPE \ + (V4L2_CID_MPEG_MSM_VIDC_BASE+0) +#define V4L2_CID_MPEG_VIDC_VIDEO_KEEP_ASPECT_RATIO \ + (V4L2_CID_MPEG_MSM_VIDC_BASE+1) +#define V4L2_CID_MPEG_VIDC_VIDEO_POST_LOOP_DEBLOCKER_MODE \ + (V4L2_CID_MPEG_MSM_VIDC_BASE+2) +#define V4L2_CID_MPEG_VIDC_VIDEO_DIVX_FORMAT \ + (V4L2_CID_MPEG_MSM_VIDC_BASE+3) +enum v4l2_mpeg_vidc_video_divx_format_type { + V4L2_MPEG_VIDC_VIDEO_DIVX_FORMAT_4 = 0, + V4L2_MPEG_VIDC_VIDEO_DIVX_FORMAT_5 = 1, + V4L2_MPEG_VIDC_VIDEO_DIVX_FORMAT_6 = 2, +}; +#define V4L2_CID_MPEG_VIDC_VIDEO_MB_ERROR_MAP_REPORTING \ + (V4L2_CID_MPEG_MSM_VIDC_BASE+4) +#define V4L2_CID_MPEG_VIDC_VIDEO_CONTINUE_DATA_TRANSFER \ + (V4L2_CID_MPEG_MSM_VIDC_BASE+5) + +#define V4L2_CID_MPEG_VIDC_VIDEO_STREAM_FORMAT (V4L2_CID_MPEG_MSM_VIDC_BASE+6) +enum v4l2_mpeg_vidc_video_stream_format { + V4L2_MPEG_VIDC_VIDEO_NAL_FORMAT_STARTCODES = 0, + V4L2_MPEG_VIDC_VIDEO_NAL_FORMAT_ONE_NAL_PER_BUFFER = 1, + V4L2_MPEG_VIDC_VIDEO_NAL_FORMAT_ONE_BYTE_LENGTH = 2, + V4L2_MPEG_VIDC_VIDEO_NAL_FORMAT_TWO_BYTE_LENGTH = 3, + V4L2_MPEG_VIDC_VIDEO_NAL_FORMAT_FOUR_BYTE_LENGTH = 4, +}; + +#define V4L2_CID_MPEG_VIDC_VIDEO_OUTPUT_ORDER (V4L2_CID_MPEG_MSM_VIDC_BASE+7) +enum v4l2_mpeg_vidc_video_output_order { + V4L2_MPEG_VIDC_VIDEO_OUTPUT_ORDER_DISPLAY = 0, + V4L2_MPEG_VIDC_VIDEO_OUTPUT_ORDER_DECODE = 1, +}; + +#define V4L2_CID_MPEG_VIDC_VIDEO_FRAME_RATE (V4L2_CID_MPEG_MSM_VIDC_BASE+8) +#define V4L2_CID_MPEG_VIDC_VIDEO_IDR_PERIOD (V4L2_CID_MPEG_MSM_VIDC_BASE+9) +#define V4L2_CID_MPEG_VIDC_VIDEO_NUM_P_FRAMES (V4L2_CID_MPEG_MSM_VIDC_BASE+10) +#define V4L2_CID_MPEG_VIDC_VIDEO_NUM_B_FRAMES (V4L2_CID_MPEG_MSM_VIDC_BASE+11) +#define V4L2_CID_MPEG_VIDC_VIDEO_REQUEST_IFRAME (V4L2_CID_MPEG_MSM_VIDC_BASE+12) + +#define V4L2_CID_MPEG_VIDC_VIDEO_RATE_CONTROL (V4L2_CID_MPEG_MSM_VIDC_BASE+13) +enum v4l2_mpeg_vidc_video_rate_control { + V4L2_CID_MPEG_VIDC_VIDEO_RATE_CONTROL_OFF = 0, + V4L2_CID_MPEG_VIDC_VIDEO_RATE_CONTROL_VBR_VFR = 1, + V4L2_CID_MPEG_VIDC_VIDEO_RATE_CONTROL_VBR_CFR = 2, + V4L2_CID_MPEG_VIDC_VIDEO_RATE_CONTROL_CBR_VFR = 3, + V4L2_CID_MPEG_VIDC_VIDEO_RATE_CONTROL_CBR_CFR = 4, +}; + +#define V4L2_CID_MPEG_VIDC_VIDEO_ROTATION (V4L2_CID_MPEG_MSM_VIDC_BASE+14) +enum v4l2_mpeg_vidc_video_rotation { + V4L2_CID_MPEG_VIDC_VIDEO_ROTATION_NONE = 0, + V4L2_CID_MPEG_VIDC_VIDEO_ROTATION_90 = 1, + V4L2_CID_MPEG_VIDC_VIDEO_ROTATION_180 = 2, + V4L2_CID_MPEG_VIDC_VIDEO_ROTATION_270 = 3, +}; +#define MSM_VIDC_BASE V4L2_CID_MPEG_MSM_VIDC_BASE +#define V4L2_CID_MPEG_VIDC_VIDEO_H264_CABAC_MODEL (MSM_VIDC_BASE+15) +enum v4l2_mpeg_vidc_h264_cabac_model { + V4L2_CID_MPEG_VIDC_VIDEO_H264_CABAC_MODEL_0 = 0, + V4L2_CID_MPEG_VIDC_VIDEO_H264_CABAC_MODEL_1 = 1, + V4L2_CID_MPEG_VIDC_VIDEO_H264_CABAC_MODEL_2 = 2, +}; + +#define V4L2_CID_MPEG_VIDC_VIDEO_INTRA_REFRESH_MODE (MSM_VIDC_BASE+16) +enum v4l2_mpeg_vidc_video_intra_refresh_mode { + V4L2_CID_MPEG_VIDC_VIDEO_INTRA_REFRESH_NONE = 0, + V4L2_CID_MPEG_VIDC_VIDEO_INTRA_REFRESH_CYCLIC = 1, + V4L2_CID_MPEG_VIDC_VIDEO_INTRA_REFRESH_ADAPTIVE = 2, + V4L2_CID_MPEG_VIDC_VIDEO_INTRA_REFRESH_CYCLIC_ADAPTIVE = 3, + V4L2_CID_MPEG_VIDC_VIDEO_INTRA_REFRESH_RANDOM = 4, +}; +#define V4L2_CID_MPEG_VIDC_VIDEO_AIR_MBS (V4L2_CID_MPEG_MSM_VIDC_BASE+17) +#define V4L2_CID_MPEG_VIDC_VIDEO_AIR_REF (V4L2_CID_MPEG_MSM_VIDC_BASE+18) +#define V4L2_CID_MPEG_VIDC_VIDEO_CIR_MBS (V4L2_CID_MPEG_MSM_VIDC_BASE+19) + +#define V4L2_CID_MPEG_VIDC_VIDEO_H263_PROFILE (V4L2_CID_MPEG_MSM_VIDC_BASE+20) +enum v4l2_mpeg_vidc_video_h263_profile { + V4L2_MPEG_VIDC_VIDEO_H263_PROFILE_BASELINE = 0, + V4L2_MPEG_VIDC_VIDEO_H263_PROFILE_H320CODING = 1, + V4L2_MPEG_VIDC_VIDEO_H263_PROFILE_BACKWARDCOMPATIBLE = 2, + V4L2_MPEG_VIDC_VIDEO_H263_PROFILE_ISWV2 = 3, + V4L2_MPEG_VIDC_VIDEO_H263_PROFILE_ISWV3 = 4, + V4L2_MPEG_VIDC_VIDEO_H263_PROFILE_HIGHCOMPRESSION = 5, + V4L2_MPEG_VIDC_VIDEO_H263_PROFILE_INTERNET = 6, + V4L2_MPEG_VIDC_VIDEO_H263_PROFILE_INTERLACE = 7, + V4L2_MPEG_VIDC_VIDEO_H263_PROFILE_HIGHLATENCY = 8, +}; + +#define V4L2_CID_MPEG_VIDC_VIDEO_H263_LEVEL (V4L2_CID_MPEG_MSM_VIDC_BASE+21) +enum v4l2_mpeg_vidc_video_h263_level { + V4L2_MPEG_VIDC_VIDEO_H263_LEVEL_1_0 = 0, + V4L2_MPEG_VIDC_VIDEO_H263_LEVEL_2_0 = 1, + V4L2_MPEG_VIDC_VIDEO_H263_LEVEL_3_0 = 2, + V4L2_MPEG_VIDC_VIDEO_H263_LEVEL_4_0 = 3, + V4L2_MPEG_VIDC_VIDEO_H263_LEVEL_4_5 = 4, + V4L2_MPEG_VIDC_VIDEO_H263_LEVEL_5_0 = 5, + V4L2_MPEG_VIDC_VIDEO_H263_LEVEL_6_0 = 6, + V4L2_MPEG_VIDC_VIDEO_H263_LEVEL_7_0 = 7, +}; + +#define V4L2_CID_MPEG_VIDC_VIDEO_H264_AU_DELIMITER \ + (V4L2_CID_MPEG_MSM_VIDC_BASE + 22) +enum v4l2_mpeg_vidc_video_h264_au_delimiter { + V4L2_MPEG_VIDC_VIDEO_H264_AU_DELIMITER_DISABLED = 0, + V4L2_MPEG_VIDC_VIDEO_H264_AU_DELIMITER_ENABLED = 1 +}; +#define V4L2_CID_MPEG_VIDC_VIDEO_SYNC_FRAME_DECODE \ + (V4L2_CID_MPEG_MSM_VIDC_BASE + 23) +enum v4l2_mpeg_vidc_video_sync_frame_decode { + V4L2_MPEG_VIDC_VIDEO_SYNC_FRAME_DECODE_DISABLE = 0, + V4L2_MPEG_VIDC_VIDEO_SYNC_FRAME_DECODE_ENABLE = 1 +}; +#define V4L2_CID_MPEG_VIDC_VIDEO_SECURE (V4L2_CID_MPEG_MSM_VIDC_BASE+24) +#define V4L2_CID_MPEG_VIDC_VIDEO_EXTRADATA \ + (V4L2_CID_MPEG_MSM_VIDC_BASE + 25) +enum v4l2_mpeg_vidc_extradata { + V4L2_MPEG_VIDC_EXTRADATA_NONE = 0, + V4L2_MPEG_VIDC_EXTRADATA_MB_QUANTIZATION = 1, + V4L2_MPEG_VIDC_EXTRADATA_INTERLACE_VIDEO = 2, + V4L2_MPEG_VIDC_EXTRADATA_VC1_FRAMEDISP = 3, + V4L2_MPEG_VIDC_EXTRADATA_VC1_SEQDISP = 4, + V4L2_MPEG_VIDC_EXTRADATA_TIMESTAMP = 5, + V4L2_MPEG_VIDC_EXTRADATA_S3D_FRAME_PACKING = 6, + V4L2_MPEG_VIDC_EXTRADATA_FRAME_RATE = 7, + V4L2_MPEG_VIDC_EXTRADATA_PANSCAN_WINDOW = 8, + V4L2_MPEG_VIDC_EXTRADATA_RECOVERY_POINT_SEI = 9, + V4L2_MPEG_VIDC_EXTRADATA_MULTISLICE_INFO = 10, + V4L2_MPEG_VIDC_EXTRADATA_NUM_CONCEALED_MB = 11, + V4L2_MPEG_VIDC_EXTRADATA_METADATA_FILLER = 12, + V4L2_MPEG_VIDC_EXTRADATA_INPUT_CROP = 13, + V4L2_MPEG_VIDC_EXTRADATA_DIGITAL_ZOOM = 14, + V4L2_MPEG_VIDC_EXTRADATA_ASPECT_RATIO = 15, + V4L2_MPEG_VIDC_EXTRADATA_MPEG2_SEQDISP = 16, + V4L2_MPEG_VIDC_EXTRADATA_STREAM_USERDATA = 17, + V4L2_MPEG_VIDC_EXTRADATA_FRAME_QP = 18, + V4L2_MPEG_VIDC_EXTRADATA_FRAME_BITS_INFO = 19, + V4L2_MPEG_VIDC_EXTRADATA_LTR = 20, + V4L2_MPEG_VIDC_EXTRADATA_METADATA_MBI = 21, +}; + +#define V4L2_CID_MPEG_VIDC_SET_PERF_LEVEL (V4L2_CID_MPEG_MSM_VIDC_BASE + 26) +enum v4l2_mpeg_vidc_perf_level { + V4L2_CID_MPEG_VIDC_PERF_LEVEL_NOMINAL = 0, + V4L2_CID_MPEG_VIDC_PERF_LEVEL_PERFORMANCE = 1, + V4L2_CID_MPEG_VIDC_PERF_LEVEL_TURBO = 2, +}; +#define V4L2_CID_MPEG_VIDEO_MULTI_SLICE_GOB \ + (V4L2_CID_MPEG_MSM_VIDC_BASE + 27) + +#define V4L2_CID_MPEG_VIDEO_MULTI_SLICE_DELIVERY_MODE \ + (V4L2_CID_MPEG_MSM_VIDC_BASE + 28) + +#define V4L2_CID_MPEG_VIDC_VIDEO_H264_VUI_TIMING_INFO \ + (V4L2_CID_MPEG_MSM_VIDC_BASE + 29) +enum v4l2_mpeg_vidc_video_h264_vui_timing_info { + V4L2_MPEG_VIDC_VIDEO_H264_VUI_TIMING_INFO_DISABLED = 0, + V4L2_MPEG_VIDC_VIDEO_H264_VUI_TIMING_INFO_ENABLED = 1 +}; + +#define V4L2_CID_MPEG_VIDC_VIDEO_ALLOC_MODE_INPUT \ + (V4L2_CID_MPEG_MSM_VIDC_BASE + 30) +#define V4L2_CID_MPEG_VIDC_VIDEO_ALLOC_MODE_OUTPUT \ + (V4L2_CID_MPEG_MSM_VIDC_BASE + 31) +enum v4l2_mpeg_vidc_video_alloc_mode_type { + V4L2_MPEG_VIDC_VIDEO_STATIC = 0, + V4L2_MPEG_VIDC_VIDEO_RING = 1, + V4L2_MPEG_VIDC_VIDEO_DYNAMIC = 2, +}; + +#define V4L2_CID_MPEG_VIDC_VIDEO_FRAME_ASSEMBLY \ + (V4L2_CID_MPEG_MSM_VIDC_BASE + 32) +enum v4l2_mpeg_vidc_video_assembly { + V4L2_MPEG_VIDC_FRAME_ASSEMBLY_DISABLE = 0, + V4L2_MPEG_VIDC_FRAME_ASSEMBLY_ENABLE = 1, +}; + +#define V4L2_CID_MPEG_VIDC_VIDEO_VP8_PROFILE_LEVEL \ + (V4L2_CID_MPEG_MSM_VIDC_BASE + 33) +enum v4l2_mpeg_vidc_video_vp8_profile_level { + V4L2_MPEG_VIDC_VIDEO_VP8_UNUSED, + V4L2_MPEG_VIDC_VIDEO_VP8_VERSION_0, + V4L2_MPEG_VIDC_VIDEO_VP8_VERSION_1, + V4L2_MPEG_VIDC_VIDEO_VP8_VERSION_2, + V4L2_MPEG_VIDC_VIDEO_VP8_VERSION_3, +}; + +#define V4L2_CID_MPEG_VIDC_VIDEO_H264_VUI_BITSTREAM_RESTRICT \ + (V4L2_CID_MPEG_MSM_VIDC_BASE + 34) +enum v4l2_mpeg_vidc_video_h264_vui_bitstream_restrict { + V4L2_MPEG_VIDC_VIDEO_H264_VUI_BITSTREAM_RESTRICT_DISABLED = 0, + V4L2_MPEG_VIDC_VIDEO_H264_VUI_BITSTREAM_RESTRICT_ENABLED = 1 +}; + +#define V4L2_CID_MPEG_VIDC_VIDEO_PRESERVE_TEXT_QUALITY \ + (V4L2_CID_MPEG_MSM_VIDC_BASE + 35) +enum v4l2_mpeg_vidc_video_preserve_text_quality { + V4L2_MPEG_VIDC_VIDEO_PRESERVE_TEXT_QUALITY_DISABLED = 0, + V4L2_MPEG_VIDC_VIDEO_PRESERVE_TEXT_QUALITY_ENABLED = 1 +}; + +#define V4L2_CID_MPEG_VIDC_VIDEO_DEINTERLACE \ + (V4L2_CID_MPEG_MSM_VIDC_BASE + 36) +enum v4l2_mpeg_vidc_video_deinterlace { + V4L2_CID_MPEG_VIDC_VIDEO_DEINTERLACE_DISABLED = 0, + V4L2_CID_MPEG_VIDC_VIDEO_DEINTERLACE_ENABLED = 1 +}; + +#define V4L2_CID_MPEG_VIDC_VIDEO_MPEG4_TIME_RESOLUTION \ + (V4L2_CID_MPEG_MSM_VIDC_BASE + 37) + +#define V4L2_CID_MPEG_VIDC_VIDEO_STREAM_OUTPUT_MODE \ + (V4L2_CID_MPEG_MSM_VIDC_BASE + 38) +enum v4l2_mpeg_vidc_video_decoder_multi_stream { + V4L2_CID_MPEG_VIDC_VIDEO_STREAM_OUTPUT_PRIMARY = 0, + V4L2_CID_MPEG_VIDC_VIDEO_STREAM_OUTPUT_SECONDARY = 1, +}; +#define V4L2_CID_MPEG_VIDC_VIDEO_SCS_THRESHOLD \ + (V4L2_CID_MPEG_MSM_VIDC_BASE + 39) + +#define V4L2_CID_MPEG_VIDC_VIDEO_MPEG2_LEVEL (V4L2_CID_MPEG_MSM_VIDC_BASE+40) +enum v4l2_mpeg_vidc_video_mpeg2_level { + V4L2_MPEG_VIDC_VIDEO_MPEG2_LEVEL_0 = 0, + V4L2_MPEG_VIDC_VIDEO_MPEG2_LEVEL_1 = 1, + V4L2_MPEG_VIDC_VIDEO_MPEG2_LEVEL_2 = 2, + V4L2_MPEG_VIDC_VIDEO_MPEG2_LEVEL_3 = 3, +}; +#define V4L2_CID_MPEG_VIDC_VIDEO_MPEG2_PROFILE (V4L2_CID_MPEG_MSM_VIDC_BASE+41) +enum v4l2_mpeg_vidc_video_mpeg2_profile { + V4L2_MPEG_VIDC_VIDEO_MPEG2_PROFILE_SIMPLE = 0, + V4L2_MPEG_VIDC_VIDEO_MPEG2_PROFILE_MAIN = 1, + V4L2_MPEG_VIDC_VIDEO_MPEG2_PROFILE_422 = 2, + V4L2_MPEG_VIDC_VIDEO_MPEG2_PROFILE_SNR_SCALABLE = 3, + V4L2_MPEG_VIDC_VIDEO_MPEG2_PROFILE_SPATIAL_SCALABLE = 4, + V4L2_MPEG_VIDC_VIDEO_MPEG2_PROFILE_HIGH = 5, +}; +#define V4L2_CID_MPEG_VIDC_VIDEO_REQUEST_SEQ_HEADER \ + (V4L2_CID_MPEG_MSM_VIDC_BASE + 42) + +#define V4L2_CID_MPEG_VIDC_VIDEO_MVC_BUFFER_LAYOUT \ + (V4L2_CID_MPEG_MSM_VIDC_BASE + 43) +enum v4l2_mpeg_vidc_video_mvc_layout { + V4L2_MPEG_VIDC_VIDEO_MVC_SEQUENTIAL = 0, + V4L2_MPEG_VIDC_VIDEO_MVC_TOP_BOTTOM = 1 +}; + +#define V4L2_CID_MPEG_VIDC_VIDEO_VP8_MIN_QP (V4L2_CID_MPEG_MSM_VIDC_BASE + 44) +#define V4L2_CID_MPEG_VIDC_VIDEO_VP8_MAX_QP (V4L2_CID_MPEG_MSM_VIDC_BASE + 45) +#define V4L2_CID_MPEG_VIDC_VIDEO_CONCEAL_COLOR \ + (V4L2_CID_MPEG_MSM_VIDC_BASE + 46) + +#define V4L2_CID_MPEG_VIDC_VIDEO_LTRMODE \ + (V4L2_CID_MPEG_MSM_VIDC_BASE + 47) + +enum v4l2_mpeg_vidc_video_ltrmode { + V4L2_MPEG_VIDC_VIDEO_LTR_MODE_DISABLE = 0, + V4L2_MPEG_VIDC_VIDEO_LTR_MODE_MANUAL = 1, + V4L2_MPEG_VIDC_VIDEO_LTR_MODE_PERIODIC = 2 +}; + +#define V4L2_CID_MPEG_VIDC_VIDEO_LTRCOUNT \ + (V4L2_CID_MPEG_MSM_VIDC_BASE + 48) + +#define V4L2_CID_MPEG_VIDC_VIDEO_USELTRFRAME \ + (V4L2_CID_MPEG_MSM_VIDC_BASE + 49) + +#define V4L2_CID_MPEG_VIDC_VIDEO_MARKLTRFRAME \ + (V4L2_CID_MPEG_MSM_VIDC_BASE + 50) + +#define V4L2_CID_MPEG_VIDC_VIDEO_HIER_P_NUM_LAYERS \ + (V4L2_CID_MPEG_MSM_VIDC_BASE + 51) + +#define V4L2_CID_MPEG_VIDC_VIDEO_RATE_CONTROL_TIMESTAMP_MODE \ + (V4L2_CID_MPEG_MSM_VIDC_BASE + 52) +enum v4l2_mpeg_vidc_video_rate_control_timestamp_mode { + V4L2_MPEG_VIDC_VIDEO_RATE_CONTROL_TIMESTAMP_MODE_HONOR = 0, + V4L2_MPEG_VIDC_VIDEO_RATE_CONTROL_TIMESTAMP_MODE_IGNORE = 1, +}; + +#define V4L2_CID_MPEG_VIDC_VIDEO_ENABLE_INITIAL_QP \ + (V4L2_CID_MPEG_MSM_VIDC_BASE + 53) +enum vl42_mpeg_vidc_video_enable_initial_qp { + V4L2_CID_MPEG_VIDC_VIDEO_ENABLE_INITIAL_QP_IFRAME = 0x1, + V4L2_CID_MPEG_VIDC_VIDEO_ENABLE_INITIAL_QP_PFRAME = 0x2, + V4L2_CID_MPEG_VIDC_VIDEO_ENABLE_INITIAL_QP_BFRAME = 0x4, +}; + +#define V4L2_CID_MPEG_VIDC_VIDEO_I_FRAME_QP \ + (V4L2_CID_MPEG_MSM_VIDC_BASE + 54) + +#define V4L2_CID_MPEG_VIDC_VIDEO_P_FRAME_QP \ + (V4L2_CID_MPEG_MSM_VIDC_BASE + 55) + +#define V4L2_CID_MPEG_VIDC_VIDEO_B_FRAME_QP \ + (V4L2_CID_MPEG_MSM_VIDC_BASE + 56) + +#define V4L2_CID_MPEG_VIDC_VIDEO_IFRAME_X_RANGE \ + (V4L2_CID_MPEG_MSM_VIDC_BASE + 57) + +#define V4L2_CID_MPEG_VIDC_VIDEO_PFRAME_X_RANGE \ + (V4L2_CID_MPEG_MSM_VIDC_BASE + 58) + +#define V4L2_CID_MPEG_VIDC_VIDEO_BFRAME_X_RANGE \ + (V4L2_CID_MPEG_MSM_VIDC_BASE + 59) + +#define V4L2_CID_MPEG_VIDC_VIDEO_IFRAME_Y_RANGE \ + (V4L2_CID_MPEG_MSM_VIDC_BASE + 60) + +#define V4L2_CID_MPEG_VIDC_VIDEO_PFRAME_Y_RANGE \ + (V4L2_CID_MPEG_MSM_VIDC_BASE + 61) + +#define V4L2_CID_MPEG_VIDC_VIDEO_BFRAME_Y_RANGE \ + (V4L2_CID_MPEG_MSM_VIDC_BASE + 62) + +#define V4L2_CID_MPEG_VIDC_VIDEO_VPX_ERROR_RESILIENCE \ + (V4L2_CID_MPEG_MSM_VIDC_BASE + 63) + +#define V4L2_CID_MPEG_VIDC_VIDEO_BUFFER_SIZE_LIMIT \ + (V4L2_CID_MPEG_MSM_VIDC_BASE + 64) + +enum vl42_mpeg_vidc_video_vpx_error_resilience { + V4L2_MPEG_VIDC_VIDEO_VPX_ERROR_RESILIENCE_DISABLED = 0, + V4L2_MPEG_VIDC_VIDEO_VPX_ERROR_RESILIENCE_ENABLED = 1, +}; + +#define V4L2_CID_MPEG_VIDC_VIDEO_HEVC_PROFILE \ + (V4L2_CID_MPEG_MSM_VIDC_BASE + 65) +enum v4l2_mpeg_video_hevc_profile { + V4L2_MPEG_VIDC_VIDEO_HEVC_PROFILE_MAIN = 0, + V4L2_MPEG_VIDC_VIDEO_HEVC_PROFILE_MAIN10 = 1, + V4L2_MPEG_VIDC_VIDEO_HEVC_PROFILE_MAIN_STILL_PIC = 2, +}; + +#define V4L2_CID_MPEG_VIDC_VIDEO_HEVC_TIER_LEVEL \ + (V4L2_CID_MPEG_MSM_VIDC_BASE + 66) +enum v4l2_mpeg_video_hevc_level { + V4L2_MPEG_VIDC_VIDEO_HEVC_LEVEL_MAIN_TIER_LEVEL_1 = 0, + V4L2_MPEG_VIDC_VIDEO_HEVC_LEVEL_HIGH_TIER_LEVEL_1 = 1, + V4L2_MPEG_VIDC_VIDEO_HEVC_LEVEL_MAIN_TIER_LEVEL_2 = 2, + V4L2_MPEG_VIDC_VIDEO_HEVC_LEVEL_HIGH_TIER_LEVEL_2 = 3, + V4L2_MPEG_VIDC_VIDEO_HEVC_LEVEL_MAIN_TIER_LEVEL_2_1 = 4, + V4L2_MPEG_VIDC_VIDEO_HEVC_LEVEL_HIGH_TIER_LEVEL_2_1 = 5, + V4L2_MPEG_VIDC_VIDEO_HEVC_LEVEL_MAIN_TIER_LEVEL_3 = 6, + V4L2_MPEG_VIDC_VIDEO_HEVC_LEVEL_HIGH_TIER_LEVEL_3 = 7, + V4L2_MPEG_VIDC_VIDEO_HEVC_LEVEL_MAIN_TIER_LEVEL_3_1 = 8, + V4L2_MPEG_VIDC_VIDEO_HEVC_LEVEL_HIGH_TIER_LEVEL_3_1 = 9, + V4L2_MPEG_VIDC_VIDEO_HEVC_LEVEL_MAIN_TIER_LEVEL_4 = 10, + V4L2_MPEG_VIDC_VIDEO_HEVC_LEVEL_HIGH_TIER_LEVEL_4 = 11, + V4L2_MPEG_VIDC_VIDEO_HEVC_LEVEL_MAIN_TIER_LEVEL_4_1 = 12, + V4L2_MPEG_VIDC_VIDEO_HEVC_LEVEL_HIGH_TIER_LEVEL_4_1 = 13, + V4L2_MPEG_VIDC_VIDEO_HEVC_LEVEL_MAIN_TIER_LEVEL_5 = 14, + V4L2_MPEG_VIDC_VIDEO_HEVC_LEVEL_HIGH_TIER_LEVEL_5 = 15, + V4L2_MPEG_VIDC_VIDEO_HEVC_LEVEL_MAIN_TIER_LEVEL_5_1 = 16, + V4L2_MPEG_VIDC_VIDEO_HEVC_LEVEL_HIGH_TIER_LEVEL_5_1 = 17, + V4L2_MPEG_VIDC_VIDEO_HEVC_LEVEL_MAIN_TIER_LEVEL_5_2 = 18, + V4L2_MPEG_VIDC_VIDEO_HEVC_LEVEL_HIGH_TIER_LEVEL_5_2 = 19, + V4L2_MPEG_VIDC_VIDEO_HEVC_LEVEL_MAIN_TIER_LEVEL_6 = 20, + V4L2_MPEG_VIDC_VIDEO_HEVC_LEVEL_HIGH_TIER_LEVEL_6 = 21, + V4L2_MPEG_VIDC_VIDEO_HEVC_LEVEL_MAIN_TIER_LEVEL_6_1 = 22, + V4L2_MPEG_VIDC_VIDEO_HEVC_LEVEL_HIGH_TIER_LEVEL_6_1 = 23, + V4L2_MPEG_VIDC_VIDEO_HEVC_LEVEL_MAIN_TIER_LEVEL_6_2 = 24, + V4L2_MPEG_VIDC_VIDEO_HEVC_LEVEL_HIGH_TIER_LEVEL_6_2 = 25, +}; + +#define V4L2_CID_MPEG_VIDC_VIDEO_H264_NAL_SVC \ + (V4L2_CID_MPEG_MSM_VIDC_BASE + 67) + +enum vl42_mpeg_vidc_video_h264_svc_nal { + V4L2_CID_MPEG_VIDC_VIDEO_H264_NAL_SVC_DISABLED = 0, + V4L2_CID_MPEG_VIDC_VIDEO_H264_NAL_SVC_ENABLED = 1, +}; + +#define V4L2_CID_MPEG_VIDC_VIDEO_PERF_MODE \ + (V4L2_CID_MPEG_MSM_VIDC_BASE + 68) + +enum v4l2_mpeg_vidc_video_perf_mode { + V4L2_MPEG_VIDC_VIDEO_PERF_MAX_QUALITY = 1, + V4L2_MPEG_VIDC_VIDEO_PERF_POWER_SAVE = 2 +}; + +#define V4L2_CID_MPEG_VIDC_VIDEO_HIER_B_NUM_LAYERS \ + (V4L2_CID_MPEG_MSM_VIDC_BASE + 69) + +#define V4L2_CID_MPEG_VIDC_VIDEO_SECURE_SCALING_THRESHOLD \ + (V4L2_CID_MPEG_MSM_VIDC_BASE + 70) + +#define V4L2_CID_MPEG_VIDC_VIDEO_NON_SECURE_OUTPUT2 \ + (V4L2_CID_MPEG_MSM_VIDC_BASE + 71) + +#define V4L2_CID_MPEG_VIDC_VIDEO_HYBRID_HIERP_MODE \ + (V4L2_CID_MPEG_MSM_VIDC_BASE + 72) + +/* Camera class control IDs */ + +#define V4L2_CID_CAMERA_CLASS_BASE (V4L2_CTRL_CLASS_CAMERA | 0x900) +#define V4L2_CID_CAMERA_CLASS (V4L2_CTRL_CLASS_CAMERA | 1) + +#define V4L2_CID_EXPOSURE_AUTO (V4L2_CID_CAMERA_CLASS_BASE+1) +enum v4l2_exposure_auto_type { + V4L2_EXPOSURE_AUTO = 0, + V4L2_EXPOSURE_MANUAL = 1, + V4L2_EXPOSURE_SHUTTER_PRIORITY = 2, + V4L2_EXPOSURE_APERTURE_PRIORITY = 3 +}; +#define V4L2_CID_EXPOSURE_ABSOLUTE (V4L2_CID_CAMERA_CLASS_BASE+2) +#define V4L2_CID_EXPOSURE_AUTO_PRIORITY (V4L2_CID_CAMERA_CLASS_BASE+3) + +#define V4L2_CID_PAN_RELATIVE (V4L2_CID_CAMERA_CLASS_BASE+4) +#define V4L2_CID_TILT_RELATIVE (V4L2_CID_CAMERA_CLASS_BASE+5) +#define V4L2_CID_PAN_RESET (V4L2_CID_CAMERA_CLASS_BASE+6) +#define V4L2_CID_TILT_RESET (V4L2_CID_CAMERA_CLASS_BASE+7) + +#define V4L2_CID_PAN_ABSOLUTE (V4L2_CID_CAMERA_CLASS_BASE+8) +#define V4L2_CID_TILT_ABSOLUTE (V4L2_CID_CAMERA_CLASS_BASE+9) + +#define V4L2_CID_FOCUS_ABSOLUTE (V4L2_CID_CAMERA_CLASS_BASE+10) +#define V4L2_CID_FOCUS_RELATIVE (V4L2_CID_CAMERA_CLASS_BASE+11) +#define V4L2_CID_FOCUS_AUTO (V4L2_CID_CAMERA_CLASS_BASE+12) + +#define V4L2_CID_ZOOM_ABSOLUTE (V4L2_CID_CAMERA_CLASS_BASE+13) +#define V4L2_CID_ZOOM_RELATIVE (V4L2_CID_CAMERA_CLASS_BASE+14) +#define V4L2_CID_ZOOM_CONTINUOUS (V4L2_CID_CAMERA_CLASS_BASE+15) + +#define V4L2_CID_PRIVACY (V4L2_CID_CAMERA_CLASS_BASE+16) + +#define V4L2_CID_IRIS_ABSOLUTE (V4L2_CID_CAMERA_CLASS_BASE+17) +#define V4L2_CID_IRIS_RELATIVE (V4L2_CID_CAMERA_CLASS_BASE+18) + +#define V4L2_CID_AUTO_EXPOSURE_BIAS (V4L2_CID_CAMERA_CLASS_BASE+19) + +#define V4L2_CID_AUTO_N_PRESET_WHITE_BALANCE (V4L2_CID_CAMERA_CLASS_BASE+20) +enum v4l2_auto_n_preset_white_balance { + V4L2_WHITE_BALANCE_MANUAL = 0, + V4L2_WHITE_BALANCE_AUTO = 1, + V4L2_WHITE_BALANCE_INCANDESCENT = 2, + V4L2_WHITE_BALANCE_FLUORESCENT = 3, + V4L2_WHITE_BALANCE_FLUORESCENT_H = 4, + V4L2_WHITE_BALANCE_HORIZON = 5, + V4L2_WHITE_BALANCE_DAYLIGHT = 6, + V4L2_WHITE_BALANCE_FLASH = 7, + V4L2_WHITE_BALANCE_CLOUDY = 8, + V4L2_WHITE_BALANCE_SHADE = 9, +}; + +#define V4L2_CID_WIDE_DYNAMIC_RANGE (V4L2_CID_CAMERA_CLASS_BASE+21) +#define V4L2_CID_IMAGE_STABILIZATION (V4L2_CID_CAMERA_CLASS_BASE+22) + +#define V4L2_CID_ISO_SENSITIVITY (V4L2_CID_CAMERA_CLASS_BASE+23) +#define V4L2_CID_ISO_SENSITIVITY_AUTO (V4L2_CID_CAMERA_CLASS_BASE+24) +enum v4l2_iso_sensitivity_auto_type { + V4L2_ISO_SENSITIVITY_MANUAL = 0, + V4L2_ISO_SENSITIVITY_AUTO = 1, +}; + +#define V4L2_CID_EXPOSURE_METERING (V4L2_CID_CAMERA_CLASS_BASE+25) +enum v4l2_exposure_metering { + V4L2_EXPOSURE_METERING_AVERAGE = 0, + V4L2_EXPOSURE_METERING_CENTER_WEIGHTED = 1, + V4L2_EXPOSURE_METERING_SPOT = 2, + V4L2_EXPOSURE_METERING_MATRIX = 3, +}; + +#define V4L2_CID_SCENE_MODE (V4L2_CID_CAMERA_CLASS_BASE+26) +enum v4l2_scene_mode { + V4L2_SCENE_MODE_NONE = 0, + V4L2_SCENE_MODE_BACKLIGHT = 1, + V4L2_SCENE_MODE_BEACH_SNOW = 2, + V4L2_SCENE_MODE_CANDLE_LIGHT = 3, + V4L2_SCENE_MODE_DAWN_DUSK = 4, + V4L2_SCENE_MODE_FALL_COLORS = 5, + V4L2_SCENE_MODE_FIREWORKS = 6, + V4L2_SCENE_MODE_LANDSCAPE = 7, + V4L2_SCENE_MODE_NIGHT = 8, + V4L2_SCENE_MODE_PARTY_INDOOR = 9, + V4L2_SCENE_MODE_PORTRAIT = 10, + V4L2_SCENE_MODE_SPORTS = 11, + V4L2_SCENE_MODE_SUNSET = 12, + V4L2_SCENE_MODE_TEXT = 13, +}; + +#define V4L2_CID_3A_LOCK (V4L2_CID_CAMERA_CLASS_BASE+27) +#define V4L2_LOCK_EXPOSURE (1 << 0) +#define V4L2_LOCK_WHITE_BALANCE (1 << 1) +#define V4L2_LOCK_FOCUS (1 << 2) + +#define V4L2_CID_AUTO_FOCUS_START (V4L2_CID_CAMERA_CLASS_BASE+28) +#define V4L2_CID_AUTO_FOCUS_STOP (V4L2_CID_CAMERA_CLASS_BASE+29) +#define V4L2_CID_AUTO_FOCUS_STATUS (V4L2_CID_CAMERA_CLASS_BASE+30) +#define V4L2_AUTO_FOCUS_STATUS_IDLE (0 << 0) +#define V4L2_AUTO_FOCUS_STATUS_BUSY (1 << 0) +#define V4L2_AUTO_FOCUS_STATUS_REACHED (1 << 1) +#define V4L2_AUTO_FOCUS_STATUS_FAILED (1 << 2) + +#define V4L2_CID_AUTO_FOCUS_RANGE (V4L2_CID_CAMERA_CLASS_BASE+31) +enum v4l2_auto_focus_range { + V4L2_AUTO_FOCUS_RANGE_AUTO = 0, + V4L2_AUTO_FOCUS_RANGE_NORMAL = 1, + V4L2_AUTO_FOCUS_RANGE_MACRO = 2, + V4L2_AUTO_FOCUS_RANGE_INFINITY = 3, +}; + + +/* FM Modulator class control IDs */ + +#define V4L2_CID_FM_TX_CLASS_BASE (V4L2_CTRL_CLASS_FM_TX | 0x900) +#define V4L2_CID_FM_TX_CLASS (V4L2_CTRL_CLASS_FM_TX | 1) + +#define V4L2_CID_RDS_TX_DEVIATION (V4L2_CID_FM_TX_CLASS_BASE + 1) +#define V4L2_CID_RDS_TX_PI (V4L2_CID_FM_TX_CLASS_BASE + 2) +#define V4L2_CID_RDS_TX_PTY (V4L2_CID_FM_TX_CLASS_BASE + 3) +#define V4L2_CID_RDS_TX_PS_NAME (V4L2_CID_FM_TX_CLASS_BASE + 5) +#define V4L2_CID_RDS_TX_RADIO_TEXT (V4L2_CID_FM_TX_CLASS_BASE + 6) + +#define V4L2_CID_AUDIO_LIMITER_ENABLED (V4L2_CID_FM_TX_CLASS_BASE + 64) +#define V4L2_CID_AUDIO_LIMITER_RELEASE_TIME (V4L2_CID_FM_TX_CLASS_BASE + 65) +#define V4L2_CID_AUDIO_LIMITER_DEVIATION (V4L2_CID_FM_TX_CLASS_BASE + 66) + +#define V4L2_CID_AUDIO_COMPRESSION_ENABLED (V4L2_CID_FM_TX_CLASS_BASE + 80) +#define V4L2_CID_AUDIO_COMPRESSION_GAIN (V4L2_CID_FM_TX_CLASS_BASE + 81) +#define V4L2_CID_AUDIO_COMPRESSION_THRESHOLD (V4L2_CID_FM_TX_CLASS_BASE + 82) +#define V4L2_CID_AUDIO_COMPRESSION_ATTACK_TIME (V4L2_CID_FM_TX_CLASS_BASE + 83) +#define V4L2_CID_AUDIO_COMPRESSION_RELEASE_TIME (V4L2_CID_FM_TX_CLASS_BASE + 84) + +#define V4L2_CID_PILOT_TONE_ENABLED (V4L2_CID_FM_TX_CLASS_BASE + 96) +#define V4L2_CID_PILOT_TONE_DEVIATION (V4L2_CID_FM_TX_CLASS_BASE + 97) +#define V4L2_CID_PILOT_TONE_FREQUENCY (V4L2_CID_FM_TX_CLASS_BASE + 98) + +#define V4L2_CID_TUNE_PREEMPHASIS (V4L2_CID_FM_TX_CLASS_BASE + 112) +enum v4l2_preemphasis { + V4L2_PREEMPHASIS_DISABLED = 0, + V4L2_PREEMPHASIS_50_uS = 1, + V4L2_PREEMPHASIS_75_uS = 2, +}; +#define V4L2_CID_TUNE_POWER_LEVEL (V4L2_CID_FM_TX_CLASS_BASE + 113) +#define V4L2_CID_TUNE_ANTENNA_CAPACITOR (V4L2_CID_FM_TX_CLASS_BASE + 114) + + +/* Flash and privacy (indicator) light controls */ + +#define V4L2_CID_FLASH_CLASS_BASE (V4L2_CTRL_CLASS_FLASH | 0x900) +#define V4L2_CID_FLASH_CLASS (V4L2_CTRL_CLASS_FLASH | 1) + +#define V4L2_CID_FLASH_LED_MODE (V4L2_CID_FLASH_CLASS_BASE + 1) +enum v4l2_flash_led_mode { + V4L2_FLASH_LED_MODE_NONE, + V4L2_FLASH_LED_MODE_FLASH, + V4L2_FLASH_LED_MODE_TORCH, +}; + +#define V4L2_CID_FLASH_STROBE_SOURCE (V4L2_CID_FLASH_CLASS_BASE + 2) +enum v4l2_flash_strobe_source { + V4L2_FLASH_STROBE_SOURCE_SOFTWARE, + V4L2_FLASH_STROBE_SOURCE_EXTERNAL, +}; + +#define V4L2_CID_FLASH_STROBE (V4L2_CID_FLASH_CLASS_BASE + 3) +#define V4L2_CID_FLASH_STROBE_STOP (V4L2_CID_FLASH_CLASS_BASE + 4) +#define V4L2_CID_FLASH_STROBE_STATUS (V4L2_CID_FLASH_CLASS_BASE + 5) + +#define V4L2_CID_FLASH_TIMEOUT (V4L2_CID_FLASH_CLASS_BASE + 6) +#define V4L2_CID_FLASH_INTENSITY (V4L2_CID_FLASH_CLASS_BASE + 7) +#define V4L2_CID_FLASH_TORCH_INTENSITY (V4L2_CID_FLASH_CLASS_BASE + 8) +#define V4L2_CID_FLASH_INDICATOR_INTENSITY (V4L2_CID_FLASH_CLASS_BASE + 9) + +#define V4L2_CID_FLASH_FAULT (V4L2_CID_FLASH_CLASS_BASE + 10) +#define V4L2_FLASH_FAULT_OVER_VOLTAGE (1 << 0) +#define V4L2_FLASH_FAULT_TIMEOUT (1 << 1) +#define V4L2_FLASH_FAULT_OVER_TEMPERATURE (1 << 2) +#define V4L2_FLASH_FAULT_SHORT_CIRCUIT (1 << 3) +#define V4L2_FLASH_FAULT_OVER_CURRENT (1 << 4) +#define V4L2_FLASH_FAULT_INDICATOR (1 << 5) + +#define V4L2_CID_FLASH_CHARGE (V4L2_CID_FLASH_CLASS_BASE + 11) +#define V4L2_CID_FLASH_READY (V4L2_CID_FLASH_CLASS_BASE + 12) + + +/* JPEG-class control IDs */ + +#define V4L2_CID_JPEG_CLASS_BASE (V4L2_CTRL_CLASS_JPEG | 0x900) +#define V4L2_CID_JPEG_CLASS (V4L2_CTRL_CLASS_JPEG | 1) + +#define V4L2_CID_JPEG_CHROMA_SUBSAMPLING (V4L2_CID_JPEG_CLASS_BASE + 1) +enum v4l2_jpeg_chroma_subsampling { + V4L2_JPEG_CHROMA_SUBSAMPLING_444 = 0, + V4L2_JPEG_CHROMA_SUBSAMPLING_422 = 1, + V4L2_JPEG_CHROMA_SUBSAMPLING_420 = 2, + V4L2_JPEG_CHROMA_SUBSAMPLING_411 = 3, + V4L2_JPEG_CHROMA_SUBSAMPLING_410 = 4, + V4L2_JPEG_CHROMA_SUBSAMPLING_GRAY = 5, +}; +#define V4L2_CID_JPEG_RESTART_INTERVAL (V4L2_CID_JPEG_CLASS_BASE + 2) +#define V4L2_CID_JPEG_COMPRESSION_QUALITY (V4L2_CID_JPEG_CLASS_BASE + 3) + +#define V4L2_CID_JPEG_ACTIVE_MARKER (V4L2_CID_JPEG_CLASS_BASE + 4) +#define V4L2_JPEG_ACTIVE_MARKER_APP0 (1 << 0) +#define V4L2_JPEG_ACTIVE_MARKER_APP1 (1 << 1) +#define V4L2_JPEG_ACTIVE_MARKER_COM (1 << 16) +#define V4L2_JPEG_ACTIVE_MARKER_DQT (1 << 17) +#define V4L2_JPEG_ACTIVE_MARKER_DHT (1 << 18) + + +/* Image source controls */ +#define V4L2_CID_IMAGE_SOURCE_CLASS_BASE (V4L2_CTRL_CLASS_IMAGE_SOURCE | 0x900) +#define V4L2_CID_IMAGE_SOURCE_CLASS (V4L2_CTRL_CLASS_IMAGE_SOURCE | 1) + +#define V4L2_CID_VBLANK (V4L2_CID_IMAGE_SOURCE_CLASS_BASE + 1) +#define V4L2_CID_HBLANK (V4L2_CID_IMAGE_SOURCE_CLASS_BASE + 2) +#define V4L2_CID_ANALOGUE_GAIN (V4L2_CID_IMAGE_SOURCE_CLASS_BASE + 3) + + +/* Image processing controls */ + +#define V4L2_CID_IMAGE_PROC_CLASS_BASE (V4L2_CTRL_CLASS_IMAGE_PROC | 0x900) +#define V4L2_CID_IMAGE_PROC_CLASS (V4L2_CTRL_CLASS_IMAGE_PROC | 1) + +#define V4L2_CID_LINK_FREQ (V4L2_CID_IMAGE_PROC_CLASS_BASE + 1) +#define V4L2_CID_PIXEL_RATE (V4L2_CID_IMAGE_PROC_CLASS_BASE + 2) +#define V4L2_CID_TEST_PATTERN (V4L2_CID_IMAGE_PROC_CLASS_BASE + 3) + + +/* DV-class control IDs defined by V4L2 */ +#define V4L2_CID_DV_CLASS_BASE (V4L2_CTRL_CLASS_DV | 0x900) +#define V4L2_CID_DV_CLASS (V4L2_CTRL_CLASS_DV | 1) + +#define V4L2_CID_DV_TX_HOTPLUG (V4L2_CID_DV_CLASS_BASE + 1) +#define V4L2_CID_DV_TX_RXSENSE (V4L2_CID_DV_CLASS_BASE + 2) +#define V4L2_CID_DV_TX_EDID_PRESENT (V4L2_CID_DV_CLASS_BASE + 3) +#define V4L2_CID_DV_TX_MODE (V4L2_CID_DV_CLASS_BASE + 4) +enum v4l2_dv_tx_mode { + V4L2_DV_TX_MODE_DVI_D = 0, + V4L2_DV_TX_MODE_HDMI = 1, +}; +#define V4L2_CID_DV_TX_RGB_RANGE (V4L2_CID_DV_CLASS_BASE + 5) +enum v4l2_dv_rgb_range { + V4L2_DV_RGB_RANGE_AUTO = 0, + V4L2_DV_RGB_RANGE_LIMITED = 1, + V4L2_DV_RGB_RANGE_FULL = 2, +}; + +#define V4L2_CID_DV_RX_POWER_PRESENT (V4L2_CID_DV_CLASS_BASE + 100) +#define V4L2_CID_DV_RX_RGB_RANGE (V4L2_CID_DV_CLASS_BASE + 101) + +#define V4L2_CID_FM_RX_CLASS_BASE (V4L2_CTRL_CLASS_FM_RX | 0x900) +#define V4L2_CID_FM_RX_CLASS (V4L2_CTRL_CLASS_FM_RX | 1) + +#define V4L2_CID_TUNE_DEEMPHASIS (V4L2_CID_FM_RX_CLASS_BASE + 1) +enum v4l2_deemphasis { + V4L2_DEEMPHASIS_DISABLED = V4L2_PREEMPHASIS_DISABLED, + V4L2_DEEMPHASIS_50_uS = V4L2_PREEMPHASIS_50_uS, + V4L2_DEEMPHASIS_75_uS = V4L2_PREEMPHASIS_75_uS, +}; + +#define V4L2_CID_RDS_RECEPTION (V4L2_CID_FM_RX_CLASS_BASE + 2) + +#endif diff --git a/original-kernel-headers/linux/videodev2.h b/original-kernel-headers/linux/videodev2.h new file mode 100644 index 0000000..3242305 --- /dev/null +++ b/original-kernel-headers/linux/videodev2.h @@ -0,0 +1,2030 @@ +/* + * Video for Linux Two header file + * + * Copyright (C) 1999-2012 the contributors + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Alternatively you can redistribute this file under the terms of the + * BSD license as stated below: + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. The names of its contributors may not be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Header file for v4l or V4L2 drivers and applications + * with public API. + * All kernel-specific stuff were moved to media/v4l2-dev.h, so + * no #if __KERNEL tests are allowed here + * + * See http://linuxtv.org for more info + * + * Author: Bill Dirks <bill@thedirks.org> + * Justin Schoeman + * Hans Verkuil <hverkuil@xs4all.nl> + * et al. + */ +#ifndef _UAPI__LINUX_VIDEODEV2_H +#define _UAPI__LINUX_VIDEODEV2_H + +#ifndef __KERNEL__ +#include <sys/time.h> +#endif +#include <linux/compiler.h> +#include <linux/ioctl.h> +#include <linux/types.h> +#include <linux/v4l2-common.h> +#include <linux/v4l2-controls.h> + +/* + * Common stuff for both V4L1 and V4L2 + * Moved from videodev.h + */ +#define VIDEO_MAX_FRAME 32 +#define VIDEO_MAX_PLANES 8 + +/* + * M I S C E L L A N E O U S + */ + +/* Four-character-code (FOURCC) */ +#define v4l2_fourcc(a, b, c, d)\ + ((__u32)(a) | ((__u32)(b) << 8) | ((__u32)(c) << 16) | ((__u32)(d) << 24)) + +/* + * E N U M S + */ +enum v4l2_field { + V4L2_FIELD_ANY = 0, /* driver can choose from none, + top, bottom, interlaced + depending on whatever it thinks + is approximate ... */ + V4L2_FIELD_NONE = 1, /* this device has no fields ... */ + V4L2_FIELD_TOP = 2, /* top field only */ + V4L2_FIELD_BOTTOM = 3, /* bottom field only */ + V4L2_FIELD_INTERLACED = 4, /* both fields interlaced */ + V4L2_FIELD_SEQ_TB = 5, /* both fields sequential into one + buffer, top-bottom order */ + V4L2_FIELD_SEQ_BT = 6, /* same as above + bottom-top order */ + V4L2_FIELD_ALTERNATE = 7, /* both fields alternating into + separate buffers */ + V4L2_FIELD_INTERLACED_TB = 8, /* both fields interlaced, top field + first and the top field is + transmitted first */ + V4L2_FIELD_INTERLACED_BT = 9, /* both fields interlaced, top field + first and the bottom field is + transmitted first */ +}; +#define V4L2_FIELD_HAS_TOP(field) \ + ((field) == V4L2_FIELD_TOP ||\ + (field) == V4L2_FIELD_INTERLACED ||\ + (field) == V4L2_FIELD_INTERLACED_TB ||\ + (field) == V4L2_FIELD_INTERLACED_BT ||\ + (field) == V4L2_FIELD_SEQ_TB ||\ + (field) == V4L2_FIELD_SEQ_BT) +#define V4L2_FIELD_HAS_BOTTOM(field) \ + ((field) == V4L2_FIELD_BOTTOM ||\ + (field) == V4L2_FIELD_INTERLACED ||\ + (field) == V4L2_FIELD_INTERLACED_TB ||\ + (field) == V4L2_FIELD_INTERLACED_BT ||\ + (field) == V4L2_FIELD_SEQ_TB ||\ + (field) == V4L2_FIELD_SEQ_BT) +#define V4L2_FIELD_HAS_BOTH(field) \ + ((field) == V4L2_FIELD_INTERLACED ||\ + (field) == V4L2_FIELD_INTERLACED_TB ||\ + (field) == V4L2_FIELD_INTERLACED_BT ||\ + (field) == V4L2_FIELD_SEQ_TB ||\ + (field) == V4L2_FIELD_SEQ_BT) + +enum v4l2_buf_type { + V4L2_BUF_TYPE_VIDEO_CAPTURE = 1, + V4L2_BUF_TYPE_VIDEO_OUTPUT = 2, + V4L2_BUF_TYPE_VIDEO_OVERLAY = 3, + V4L2_BUF_TYPE_VBI_CAPTURE = 4, + V4L2_BUF_TYPE_VBI_OUTPUT = 5, + V4L2_BUF_TYPE_SLICED_VBI_CAPTURE = 6, + V4L2_BUF_TYPE_SLICED_VBI_OUTPUT = 7, +#if 1 + /* Experimental */ + V4L2_BUF_TYPE_VIDEO_OUTPUT_OVERLAY = 8, +#endif + V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE = 9, + V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE = 10, + /* Deprecated, do not use */ + V4L2_BUF_TYPE_PRIVATE = 0x80, +}; + +#define V4L2_TYPE_IS_MULTIPLANAR(type) \ + ((type) == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE \ + || (type) == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) + +#define V4L2_TYPE_IS_OUTPUT(type) \ + ((type) == V4L2_BUF_TYPE_VIDEO_OUTPUT \ + || (type) == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE \ + || (type) == V4L2_BUF_TYPE_VIDEO_OVERLAY \ + || (type) == V4L2_BUF_TYPE_VIDEO_OUTPUT_OVERLAY \ + || (type) == V4L2_BUF_TYPE_VBI_OUTPUT \ + || (type) == V4L2_BUF_TYPE_SLICED_VBI_OUTPUT) + +#define V4L2_TYPE_IS_PRIVATE(type) \ + ((type) == V4L2_BUF_TYPE_PRIVATE) + +enum v4l2_tuner_type { + V4L2_TUNER_RADIO = 1, + V4L2_TUNER_ANALOG_TV = 2, + V4L2_TUNER_DIGITAL_TV = 3, +}; + +enum v4l2_memory { + V4L2_MEMORY_MMAP = 1, + V4L2_MEMORY_USERPTR = 2, + V4L2_MEMORY_OVERLAY = 3, + V4L2_MEMORY_DMABUF = 4, +}; + +/* see also http://vektor.theorem.ca/graphics/ycbcr/ */ +enum v4l2_colorspace { + /* ITU-R 601 -- broadcast NTSC/PAL */ + V4L2_COLORSPACE_SMPTE170M = 1, + + /* 1125-Line (US) HDTV */ + V4L2_COLORSPACE_SMPTE240M = 2, + + /* HD and modern captures. */ + V4L2_COLORSPACE_REC709 = 3, + + /* broken BT878 extents (601, luma range 16-253 instead of 16-235) */ + V4L2_COLORSPACE_BT878 = 4, + + /* These should be useful. Assume 601 extents. */ + V4L2_COLORSPACE_470_SYSTEM_M = 5, + V4L2_COLORSPACE_470_SYSTEM_BG = 6, + + /* I know there will be cameras that send this. So, this is + * unspecified chromaticities and full 0-255 on each of the + * Y'CbCr components + */ + V4L2_COLORSPACE_JPEG = 7, + + /* For RGB colourspaces, this is probably a good start. */ + V4L2_COLORSPACE_SRGB = 8, +}; + +enum v4l2_priority { + V4L2_PRIORITY_UNSET = 0, /* not initialized */ + V4L2_PRIORITY_BACKGROUND = 1, + V4L2_PRIORITY_INTERACTIVE = 2, + V4L2_PRIORITY_RECORD = 3, + V4L2_PRIORITY_DEFAULT = V4L2_PRIORITY_INTERACTIVE, +}; + +struct v4l2_rect { + __s32 left; + __s32 top; + __s32 width; + __s32 height; +}; + +struct v4l2_fract { + __u32 numerator; + __u32 denominator; +}; + +/** + * struct v4l2_capability - Describes V4L2 device caps returned by VIDIOC_QUERYCAP + * + * @driver: name of the driver module (e.g. "bttv") + * @card: name of the card (e.g. "Hauppauge WinTV") + * @bus_info: name of the bus (e.g. "PCI:" + pci_name(pci_dev) ) + * @version: KERNEL_VERSION + * @capabilities: capabilities of the physical device as a whole + * @device_caps: capabilities accessed via this particular device (node) + * @reserved: reserved fields for future extensions + */ +struct v4l2_capability { + __u8 driver[16]; + __u8 card[32]; + __u8 bus_info[32]; + __u32 version; + __u32 capabilities; + __u32 device_caps; + __u32 reserved[3]; +}; + +/* Values for 'capabilities' field */ +#define V4L2_CAP_VIDEO_CAPTURE 0x00000001 /* Is a video capture device */ +#define V4L2_CAP_VIDEO_OUTPUT 0x00000002 /* Is a video output device */ +#define V4L2_CAP_VIDEO_OVERLAY 0x00000004 /* Can do video overlay */ +#define V4L2_CAP_VBI_CAPTURE 0x00000010 /* Is a raw VBI capture device */ +#define V4L2_CAP_VBI_OUTPUT 0x00000020 /* Is a raw VBI output device */ +#define V4L2_CAP_SLICED_VBI_CAPTURE 0x00000040 /* Is a sliced VBI capture device */ +#define V4L2_CAP_SLICED_VBI_OUTPUT 0x00000080 /* Is a sliced VBI output device */ +#define V4L2_CAP_RDS_CAPTURE 0x00000100 /* RDS data capture */ +#define V4L2_CAP_VIDEO_OUTPUT_OVERLAY 0x00000200 /* Can do video output overlay */ +#define V4L2_CAP_HW_FREQ_SEEK 0x00000400 /* Can do hardware frequency seek */ +#define V4L2_CAP_RDS_OUTPUT 0x00000800 /* Is an RDS encoder */ + +/* Is a video capture device that supports multiplanar formats */ +#define V4L2_CAP_VIDEO_CAPTURE_MPLANE 0x00001000 +/* Is a video output device that supports multiplanar formats */ +#define V4L2_CAP_VIDEO_OUTPUT_MPLANE 0x00002000 +/* Is a video mem-to-mem device that supports multiplanar formats */ +#define V4L2_CAP_VIDEO_M2M_MPLANE 0x00004000 +/* Is a video mem-to-mem device */ +#define V4L2_CAP_VIDEO_M2M 0x00008000 + +#define V4L2_CAP_TUNER 0x00010000 /* has a tuner */ +#define V4L2_CAP_AUDIO 0x00020000 /* has audio support */ +#define V4L2_CAP_RADIO 0x00040000 /* is a radio device */ +#define V4L2_CAP_MODULATOR 0x00080000 /* has a modulator */ + +#define V4L2_CAP_READWRITE 0x01000000 /* read/write systemcalls */ +#define V4L2_CAP_ASYNCIO 0x02000000 /* async I/O */ +#define V4L2_CAP_STREAMING 0x04000000 /* streaming I/O ioctls */ + +#define V4L2_CAP_DEVICE_CAPS 0x80000000 /* sets device capabilities field */ + +/* + * V I D E O I M A G E F O R M A T + */ +struct v4l2_pix_format { + __u32 width; + __u32 height; + __u32 pixelformat; + __u32 field; /* enum v4l2_field */ + __u32 bytesperline; /* for padding, zero if unused */ + __u32 sizeimage; + __u32 colorspace; /* enum v4l2_colorspace */ + __u32 priv; /* private data, depends on pixelformat */ +}; + +/* Pixel format FOURCC depth Description */ + +/* RGB formats */ +#define V4L2_PIX_FMT_RGB332 v4l2_fourcc('R', 'G', 'B', '1') /* 8 RGB-3-3-2 */ +#define V4L2_PIX_FMT_RGB444 v4l2_fourcc('R', '4', '4', '4') /* 16 xxxxrrrr ggggbbbb */ +#define V4L2_PIX_FMT_RGB555 v4l2_fourcc('R', 'G', 'B', 'O') /* 16 RGB-5-5-5 */ +#define V4L2_PIX_FMT_RGB565 v4l2_fourcc('R', 'G', 'B', 'P') /* 16 RGB-5-6-5 */ +#define V4L2_PIX_FMT_RGB555X v4l2_fourcc('R', 'G', 'B', 'Q') /* 16 RGB-5-5-5 BE */ +#define V4L2_PIX_FMT_RGB565X v4l2_fourcc('R', 'G', 'B', 'R') /* 16 RGB-5-6-5 BE */ +#define V4L2_PIX_FMT_BGR666 v4l2_fourcc('B', 'G', 'R', 'H') /* 18 BGR-6-6-6 */ +#define V4L2_PIX_FMT_BGR24 v4l2_fourcc('B', 'G', 'R', '3') /* 24 BGR-8-8-8 */ +#define V4L2_PIX_FMT_RGB24 v4l2_fourcc('R', 'G', 'B', '3') /* 24 RGB-8-8-8 */ +#define V4L2_PIX_FMT_BGR32 v4l2_fourcc('B', 'G', 'R', '4') /* 32 BGR-8-8-8-8 */ +#define V4L2_PIX_FMT_RGB32 v4l2_fourcc('R', 'G', 'B', '4') /* 32 RGB-8-8-8-8 */ + +/* Grey formats */ +#define V4L2_PIX_FMT_GREY v4l2_fourcc('G', 'R', 'E', 'Y') /* 8 Greyscale */ +#define V4L2_PIX_FMT_Y4 v4l2_fourcc('Y', '0', '4', ' ') /* 4 Greyscale */ +#define V4L2_PIX_FMT_Y6 v4l2_fourcc('Y', '0', '6', ' ') /* 6 Greyscale */ +#define V4L2_PIX_FMT_Y10 v4l2_fourcc('Y', '1', '0', ' ') /* 10 Greyscale */ +#define V4L2_PIX_FMT_Y12 v4l2_fourcc('Y', '1', '2', ' ') /* 12 Greyscale */ +#define V4L2_PIX_FMT_Y16 v4l2_fourcc('Y', '1', '6', ' ') /* 16 Greyscale */ + +/* Grey bit-packed formats */ +#define V4L2_PIX_FMT_Y10BPACK v4l2_fourcc('Y', '1', '0', 'B') /* 10 Greyscale bit-packed */ + +/* Palette formats */ +#define V4L2_PIX_FMT_PAL8 v4l2_fourcc('P', 'A', 'L', '8') /* 8 8-bit palette */ + +/* Chrominance formats */ +#define V4L2_PIX_FMT_UV8 v4l2_fourcc('U', 'V', '8', ' ') /* 8 UV 4:4 */ + +/* Luminance+Chrominance formats */ +#define V4L2_PIX_FMT_YVU410 v4l2_fourcc('Y', 'V', 'U', '9') /* 9 YVU 4:1:0 */ +#define V4L2_PIX_FMT_YVU420 v4l2_fourcc('Y', 'V', '1', '2') /* 12 YVU 4:2:0 */ +#define V4L2_PIX_FMT_YUYV v4l2_fourcc('Y', 'U', 'Y', 'V') /* 16 YUV 4:2:2 */ +#define V4L2_PIX_FMT_YYUV v4l2_fourcc('Y', 'Y', 'U', 'V') /* 16 YUV 4:2:2 */ +#define V4L2_PIX_FMT_YVYU v4l2_fourcc('Y', 'V', 'Y', 'U') /* 16 YVU 4:2:2 */ +#define V4L2_PIX_FMT_UYVY v4l2_fourcc('U', 'Y', 'V', 'Y') /* 16 YUV 4:2:2 */ +#define V4L2_PIX_FMT_VYUY v4l2_fourcc('V', 'Y', 'U', 'Y') /* 16 YUV 4:2:2 */ +#define V4L2_PIX_FMT_YUV422P v4l2_fourcc('4', '2', '2', 'P') /* 16 YVU422 planar */ +#define V4L2_PIX_FMT_YUV411P v4l2_fourcc('4', '1', '1', 'P') /* 16 YVU411 planar */ +#define V4L2_PIX_FMT_Y41P v4l2_fourcc('Y', '4', '1', 'P') /* 12 YUV 4:1:1 */ +#define V4L2_PIX_FMT_YUV444 v4l2_fourcc('Y', '4', '4', '4') /* 16 xxxxyyyy uuuuvvvv */ +#define V4L2_PIX_FMT_YUV555 v4l2_fourcc('Y', 'U', 'V', 'O') /* 16 YUV-5-5-5 */ +#define V4L2_PIX_FMT_YUV565 v4l2_fourcc('Y', 'U', 'V', 'P') /* 16 YUV-5-6-5 */ +#define V4L2_PIX_FMT_YUV32 v4l2_fourcc('Y', 'U', 'V', '4') /* 32 YUV-8-8-8-8 */ +#define V4L2_PIX_FMT_YUV410 v4l2_fourcc('Y', 'U', 'V', '9') /* 9 YUV 4:1:0 */ +#define V4L2_PIX_FMT_YUV420 v4l2_fourcc('Y', 'U', '1', '2') /* 12 YUV 4:2:0 */ +#define V4L2_PIX_FMT_HI240 v4l2_fourcc('H', 'I', '2', '4') /* 8 8-bit color */ +#define V4L2_PIX_FMT_HM12 v4l2_fourcc('H', 'M', '1', '2') /* 8 YUV 4:2:0 16x16 macroblocks */ +#define V4L2_PIX_FMT_M420 v4l2_fourcc('M', '4', '2', '0') /* 12 YUV 4:2:0 2 lines y, 1 line uv interleaved */ + +/* two planes -- one Y, one Cr + Cb interleaved */ +#define V4L2_PIX_FMT_NV12 v4l2_fourcc('N', 'V', '1', '2') /* 12 Y/CbCr 4:2:0 */ +#define V4L2_PIX_FMT_NV21 v4l2_fourcc('N', 'V', '2', '1') /* 12 Y/CrCb 4:2:0 */ +#define V4L2_PIX_FMT_NV16 v4l2_fourcc('N', 'V', '1', '6') /* 16 Y/CbCr 4:2:2 */ +#define V4L2_PIX_FMT_NV61 v4l2_fourcc('N', 'V', '6', '1') /* 16 Y/CrCb 4:2:2 */ +#define V4L2_PIX_FMT_NV24 v4l2_fourcc('N', 'V', '2', '4') /* 24 Y/CbCr 4:4:4 */ +#define V4L2_PIX_FMT_NV42 v4l2_fourcc('N', 'V', '4', '2') /* 24 Y/CrCb 4:4:4 */ + +/* two non contiguous planes - one Y, one Cr + Cb interleaved */ +#define V4L2_PIX_FMT_NV12M v4l2_fourcc('N', 'M', '1', '2') /* 12 Y/CbCr 4:2:0 */ +#define V4L2_PIX_FMT_NV21M v4l2_fourcc('N', 'M', '2', '1') /* 21 Y/CrCb 4:2:0 */ +#define V4L2_PIX_FMT_NV12MT v4l2_fourcc('T', 'M', '1', '2') /* 12 Y/CbCr 4:2:0 64x32 macroblocks */ +#define V4L2_PIX_FMT_NV12MT_16X16 v4l2_fourcc('V', 'M', '1', '2') /* 12 Y/CbCr 4:2:0 16x16 macroblocks */ + +/* three non contiguous planes - Y, Cb, Cr */ +#define V4L2_PIX_FMT_YUV420M v4l2_fourcc('Y', 'M', '1', '2') /* 12 YUV420 planar */ +#define V4L2_PIX_FMT_YVU420M v4l2_fourcc('Y', 'M', '2', '1') /* 12 YVU420 planar */ + +/* Bayer formats - see http://www.siliconimaging.com/RGB%20Bayer.htm */ +#define V4L2_PIX_FMT_SBGGR8 v4l2_fourcc('B', 'A', '8', '1') /* 8 BGBG.. GRGR.. */ +#define V4L2_PIX_FMT_SGBRG8 v4l2_fourcc('G', 'B', 'R', 'G') /* 8 GBGB.. RGRG.. */ +#define V4L2_PIX_FMT_SGRBG8 v4l2_fourcc('G', 'R', 'B', 'G') /* 8 GRGR.. BGBG.. */ +#define V4L2_PIX_FMT_SRGGB8 v4l2_fourcc('R', 'G', 'G', 'B') /* 8 RGRG.. GBGB.. */ +#define V4L2_PIX_FMT_SBGGR10 v4l2_fourcc('B', 'G', '1', '0') /* 10 BGBG.. GRGR.. */ +#define V4L2_PIX_FMT_SGBRG10 v4l2_fourcc('G', 'B', '1', '0') /* 10 GBGB.. RGRG.. */ +#define V4L2_PIX_FMT_SGRBG10 v4l2_fourcc('B', 'A', '1', '0') /* 10 GRGR.. BGBG.. */ +#define V4L2_PIX_FMT_SRGGB10 v4l2_fourcc('R', 'G', '1', '0') /* 10 RGRG.. GBGB.. */ +#define V4L2_PIX_FMT_SBGGR12 v4l2_fourcc('B', 'G', '1', '2') /* 12 BGBG.. GRGR.. */ +#define V4L2_PIX_FMT_SGBRG12 v4l2_fourcc('G', 'B', '1', '2') /* 12 GBGB.. RGRG.. */ +#define V4L2_PIX_FMT_SGRBG12 v4l2_fourcc('B', 'A', '1', '2') /* 12 GRGR.. BGBG.. */ +#define V4L2_PIX_FMT_SRGGB12 v4l2_fourcc('R', 'G', '1', '2') /* 12 RGRG.. GBGB.. */ + /* 10bit raw bayer a-law compressed to 8 bits */ +#define V4L2_PIX_FMT_SBGGR10ALAW8 v4l2_fourcc('a', 'B', 'A', '8') +#define V4L2_PIX_FMT_SGBRG10ALAW8 v4l2_fourcc('a', 'G', 'A', '8') +#define V4L2_PIX_FMT_SGRBG10ALAW8 v4l2_fourcc('a', 'g', 'A', '8') +#define V4L2_PIX_FMT_SRGGB10ALAW8 v4l2_fourcc('a', 'R', 'A', '8') + /* 10bit raw bayer DPCM compressed to 8 bits */ +#define V4L2_PIX_FMT_SBGGR10DPCM8 v4l2_fourcc('b', 'B', 'A', '8') +#define V4L2_PIX_FMT_SGBRG10DPCM8 v4l2_fourcc('b', 'G', 'A', '8') +#define V4L2_PIX_FMT_SGRBG10DPCM8 v4l2_fourcc('B', 'D', '1', '0') +#define V4L2_PIX_FMT_SRGGB10DPCM8 v4l2_fourcc('b', 'R', 'A', '8') + /* + * 10bit raw bayer, expanded to 16 bits + * xxxxrrrrrrrrrrxxxxgggggggggg xxxxggggggggggxxxxbbbbbbbbbb... + */ +#define V4L2_PIX_FMT_SBGGR16 v4l2_fourcc('B', 'Y', 'R', '2') /* 16 BGBG.. GRGR.. */ + +/* compressed formats */ +#define V4L2_PIX_FMT_MJPEG v4l2_fourcc('M', 'J', 'P', 'G') /* Motion-JPEG */ +#define V4L2_PIX_FMT_JPEG v4l2_fourcc('J', 'P', 'E', 'G') /* JFIF JPEG */ +#define V4L2_PIX_FMT_DV v4l2_fourcc('d', 'v', 's', 'd') /* 1394 */ +#define V4L2_PIX_FMT_MPEG v4l2_fourcc('M', 'P', 'E', 'G') /* MPEG-1/2/4 Multiplexed */ +#define V4L2_PIX_FMT_H264 v4l2_fourcc('H', '2', '6', '4') /* H264 with start codes */ +#define V4L2_PIX_FMT_H264_NO_SC v4l2_fourcc('A', 'V', 'C', '1') /* H264 without start codes */ +#define V4L2_PIX_FMT_H264_MVC v4l2_fourcc('M', '2', '6', '4') /* H264 MVC */ +#define V4L2_PIX_FMT_H263 v4l2_fourcc('H', '2', '6', '3') /* H263 */ +#define V4L2_PIX_FMT_MPEG1 v4l2_fourcc('M', 'P', 'G', '1') /* MPEG-1 ES */ +#define V4L2_PIX_FMT_MPEG2 v4l2_fourcc('M', 'P', 'G', '2') /* MPEG-2 ES */ +#define V4L2_PIX_FMT_MPEG4 v4l2_fourcc('M', 'P', 'G', '4') /* MPEG-4 ES */ +#define V4L2_PIX_FMT_XVID v4l2_fourcc('X', 'V', 'I', 'D') /* Xvid */ +#define V4L2_PIX_FMT_VC1_ANNEX_G v4l2_fourcc('V', 'C', '1', 'G') /* SMPTE 421M Annex G compliant stream */ +#define V4L2_PIX_FMT_VC1_ANNEX_L v4l2_fourcc('V', 'C', '1', 'L') /* SMPTE 421M Annex L compliant stream */ +#define V4L2_PIX_FMT_DIVX_311 v4l2_fourcc('D', 'I', 'V', '3') /* DIVX311 */ +#define V4L2_PIX_FMT_DIVX v4l2_fourcc('D', 'I', 'V', 'X') /* DIVX */ +#define V4L2_PIX_FMT_VP8 v4l2_fourcc('V', 'P', '8', '0') /* VP8 */ +#define V4L2_PIX_FMT_HEVC v4l2_fourcc('H', 'E', 'V', 'C') /* for HEVC stream */ +#define V4L2_PIX_FMT_HEVC_HYBRID v4l2_fourcc('H', 'V', 'C', 'H') + +/* Vendor-specific formats */ +#define V4L2_PIX_FMT_CPIA1 v4l2_fourcc('C', 'P', 'I', 'A') /* cpia1 YUV */ +#define V4L2_PIX_FMT_WNVA v4l2_fourcc('W', 'N', 'V', 'A') /* Winnov hw compress */ +#define V4L2_PIX_FMT_SN9C10X v4l2_fourcc('S', '9', '1', '0') /* SN9C10x compression */ +#define V4L2_PIX_FMT_SN9C20X_I420 v4l2_fourcc('S', '9', '2', '0') /* SN9C20x YUV 4:2:0 */ +#define V4L2_PIX_FMT_PWC1 v4l2_fourcc('P', 'W', 'C', '1') /* pwc older webcam */ +#define V4L2_PIX_FMT_PWC2 v4l2_fourcc('P', 'W', 'C', '2') /* pwc newer webcam */ +#define V4L2_PIX_FMT_ET61X251 v4l2_fourcc('E', '6', '2', '5') /* ET61X251 compression */ +#define V4L2_PIX_FMT_SPCA501 v4l2_fourcc('S', '5', '0', '1') /* YUYV per line */ +#define V4L2_PIX_FMT_SPCA505 v4l2_fourcc('S', '5', '0', '5') /* YYUV per line */ +#define V4L2_PIX_FMT_SPCA508 v4l2_fourcc('S', '5', '0', '8') /* YUVY per line */ +#define V4L2_PIX_FMT_SPCA561 v4l2_fourcc('S', '5', '6', '1') /* compressed GBRG bayer */ +#define V4L2_PIX_FMT_PAC207 v4l2_fourcc('P', '2', '0', '7') /* compressed BGGR bayer */ +#define V4L2_PIX_FMT_MR97310A v4l2_fourcc('M', '3', '1', '0') /* compressed BGGR bayer */ +#define V4L2_PIX_FMT_JL2005BCD v4l2_fourcc('J', 'L', '2', '0') /* compressed RGGB bayer */ +#define V4L2_PIX_FMT_SN9C2028 v4l2_fourcc('S', 'O', 'N', 'X') /* compressed GBRG bayer */ +#define V4L2_PIX_FMT_SQ905C v4l2_fourcc('9', '0', '5', 'C') /* compressed RGGB bayer */ +#define V4L2_PIX_FMT_PJPG v4l2_fourcc('P', 'J', 'P', 'G') /* Pixart 73xx JPEG */ +#define V4L2_PIX_FMT_OV511 v4l2_fourcc('O', '5', '1', '1') /* ov511 JPEG */ +#define V4L2_PIX_FMT_OV518 v4l2_fourcc('O', '5', '1', '8') /* ov518 JPEG */ +#define V4L2_PIX_FMT_STV0680 v4l2_fourcc('S', '6', '8', '0') /* stv0680 bayer */ +#define V4L2_PIX_FMT_TM6000 v4l2_fourcc('T', 'M', '6', '0') /* tm5600/tm60x0 */ +#define V4L2_PIX_FMT_CIT_YYVYUY v4l2_fourcc('C', 'I', 'T', 'V') /* one line of Y then 1 line of VYUY */ +#define V4L2_PIX_FMT_KONICA420 v4l2_fourcc('K', 'O', 'N', 'I') /* YUV420 planar in blocks of 256 pixels */ +#define V4L2_PIX_FMT_JPGL v4l2_fourcc('J', 'P', 'G', 'L') /* JPEG-Lite */ +#define V4L2_PIX_FMT_SE401 v4l2_fourcc('S', '4', '0', '1') /* se401 janggu compressed rgb */ +#define V4L2_PIX_FMT_S5C_UYVY_JPG v4l2_fourcc('S', '5', 'C', 'I') /* S5C73M3 interleaved UYVY/JPEG */ +#define V4L2_PIX_FMT_STATS_COMB v4l2_fourcc('S', 'T', 'C', 'M') /* Composite stats */ + +#define V4L2_PIX_FMT_STATS_AE v4l2_fourcc('S', 'T', 'A', 'E') /* AEC stats */ +#define V4L2_PIX_FMT_STATS_AF v4l2_fourcc('S', 'T', 'A', 'F') /* AF stats */ +#define V4L2_PIX_FMT_STATS_AWB v4l2_fourcc('S', 'T', 'W', 'B') /* AWB stats */ +#define V4L2_PIX_FMT_STATS_IHST v4l2_fourcc('I', 'H', 'S', 'T') /* IHIST stats */ +#define V4L2_PIX_FMT_STATS_CS v4l2_fourcc('S', 'T', 'C', 'S') /* Column count stats */ +#define V4L2_PIX_FMT_STATS_RS v4l2_fourcc('S', 'T', 'R', 'S') /* Row count stats */ +#define V4L2_PIX_FMT_STATS_BG v4l2_fourcc('S', 'T', 'B', 'G') /* Bayer Grid stats */ +#define V4L2_PIX_FMT_STATS_BF v4l2_fourcc('S', 'T', 'B', 'F') /* Bayer focus stats */ +#define V4L2_PIX_FMT_STATS_BHST v4l2_fourcc('B', 'H', 'S', 'T') /* Bayer hist stats */ + +/* + * F O R M A T E N U M E R A T I O N + */ +struct v4l2_fmtdesc { + __u32 index; /* Format number */ + __u32 type; /* enum v4l2_buf_type */ + __u32 flags; + __u8 description[32]; /* Description string */ + __u32 pixelformat; /* Format fourcc */ + __u32 reserved[4]; +}; + +#define V4L2_FMT_FLAG_COMPRESSED 0x0001 +#define V4L2_FMT_FLAG_EMULATED 0x0002 + +#if 1 + /* Experimental Frame Size and frame rate enumeration */ +/* + * F R A M E S I Z E E N U M E R A T I O N + */ +enum v4l2_frmsizetypes { + V4L2_FRMSIZE_TYPE_DISCRETE = 1, + V4L2_FRMSIZE_TYPE_CONTINUOUS = 2, + V4L2_FRMSIZE_TYPE_STEPWISE = 3, +}; + +struct v4l2_frmsize_discrete { + __u32 width; /* Frame width [pixel] */ + __u32 height; /* Frame height [pixel] */ +}; + +struct v4l2_frmsize_stepwise { + __u32 min_width; /* Minimum frame width [pixel] */ + __u32 max_width; /* Maximum frame width [pixel] */ + __u32 step_width; /* Frame width step size [pixel] */ + __u32 min_height; /* Minimum frame height [pixel] */ + __u32 max_height; /* Maximum frame height [pixel] */ + __u32 step_height; /* Frame height step size [pixel] */ +}; + +struct v4l2_frmsizeenum { + __u32 index; /* Frame size number */ + __u32 pixel_format; /* Pixel format */ + __u32 type; /* Frame size type the device supports. */ + + union { /* Frame size */ + struct v4l2_frmsize_discrete discrete; + struct v4l2_frmsize_stepwise stepwise; + }; + + __u32 reserved[2]; /* Reserved space for future use */ +}; + +/* + * F R A M E R A T E E N U M E R A T I O N + */ +enum v4l2_frmivaltypes { + V4L2_FRMIVAL_TYPE_DISCRETE = 1, + V4L2_FRMIVAL_TYPE_CONTINUOUS = 2, + V4L2_FRMIVAL_TYPE_STEPWISE = 3, +}; + +struct v4l2_frmival_stepwise { + struct v4l2_fract min; /* Minimum frame interval [s] */ + struct v4l2_fract max; /* Maximum frame interval [s] */ + struct v4l2_fract step; /* Frame interval step size [s] */ +}; + +struct v4l2_frmivalenum { + __u32 index; /* Frame format index */ + __u32 pixel_format; /* Pixel format */ + __u32 width; /* Frame width */ + __u32 height; /* Frame height */ + __u32 type; /* Frame interval type the device supports. */ + + union { /* Frame interval */ + struct v4l2_fract discrete; + struct v4l2_frmival_stepwise stepwise; + }; + + __u32 reserved[2]; /* Reserved space for future use */ +}; +#endif + +/* + * T I M E C O D E + */ +struct v4l2_timecode { + __u32 type; + __u32 flags; + __u8 frames; + __u8 seconds; + __u8 minutes; + __u8 hours; + __u8 userbits[4]; +}; + +/* Type */ +#define V4L2_TC_TYPE_24FPS 1 +#define V4L2_TC_TYPE_25FPS 2 +#define V4L2_TC_TYPE_30FPS 3 +#define V4L2_TC_TYPE_50FPS 4 +#define V4L2_TC_TYPE_60FPS 5 + +/* Flags */ +#define V4L2_TC_FLAG_DROPFRAME 0x0001 /* "drop-frame" mode */ +#define V4L2_TC_FLAG_COLORFRAME 0x0002 +#define V4L2_TC_USERBITS_field 0x000C +#define V4L2_TC_USERBITS_USERDEFINED 0x0000 +#define V4L2_TC_USERBITS_8BITCHARS 0x0008 +/* The above is based on SMPTE timecodes */ + +struct v4l2_jpegcompression { + int quality; + + int APPn; /* Number of APP segment to be written, + * must be 0..15 */ + int APP_len; /* Length of data in JPEG APPn segment */ + char APP_data[60]; /* Data in the JPEG APPn segment. */ + + int COM_len; /* Length of data in JPEG COM segment */ + char COM_data[60]; /* Data in JPEG COM segment */ + + __u32 jpeg_markers; /* Which markers should go into the JPEG + * output. Unless you exactly know what + * you do, leave them untouched. + * Inluding less markers will make the + * resulting code smaller, but there will + * be fewer applications which can read it. + * The presence of the APP and COM marker + * is influenced by APP_len and COM_len + * ONLY, not by this property! */ + +#define V4L2_JPEG_MARKER_DHT (1<<3) /* Define Huffman Tables */ +#define V4L2_JPEG_MARKER_DQT (1<<4) /* Define Quantization Tables */ +#define V4L2_JPEG_MARKER_DRI (1<<5) /* Define Restart Interval */ +#define V4L2_JPEG_MARKER_COM (1<<6) /* Comment segment */ +#define V4L2_JPEG_MARKER_APP (1<<7) /* App segment, driver will + * allways use APP0 */ +}; + +/* + * M E M O R Y - M A P P I N G B U F F E R S + */ +struct v4l2_requestbuffers { + __u32 count; + __u32 type; /* enum v4l2_buf_type */ + __u32 memory; /* enum v4l2_memory */ + __u32 reserved[2]; +}; + +/** + * struct v4l2_plane - plane info for multi-planar buffers + * @bytesused: number of bytes occupied by data in the plane (payload) + * @length: size of this plane (NOT the payload) in bytes + * @mem_offset: when memory in the associated struct v4l2_buffer is + * V4L2_MEMORY_MMAP, equals the offset from the start of + * the device memory for this plane (or is a "cookie" that + * should be passed to mmap() called on the video node) + * @userptr: when memory is V4L2_MEMORY_USERPTR, a userspace pointer + * pointing to this plane + * @fd: when memory is V4L2_MEMORY_DMABUF, a userspace file + * descriptor associated with this plane + * @data_offset: offset in the plane to the start of data; usually 0, + * unless there is a header in front of the data + * + * Multi-planar buffers consist of one or more planes, e.g. an YCbCr buffer + * with two planes can have one plane for Y, and another for interleaved CbCr + * components. Each plane can reside in a separate memory buffer, or even in + * a completely separate memory node (e.g. in embedded devices). + */ +struct v4l2_plane { + __u32 bytesused; + __u32 length; + union { + __u32 mem_offset; + unsigned long userptr; + __s32 fd; + } m; + __u32 data_offset; + __u32 reserved[11]; +}; + +/** + * struct v4l2_buffer - video buffer info + * @index: id number of the buffer + * @type: enum v4l2_buf_type; buffer type (type == *_MPLANE for + * multiplanar buffers); + * @bytesused: number of bytes occupied by data in the buffer (payload); + * unused (set to 0) for multiplanar buffers + * @flags: buffer informational flags + * @field: enum v4l2_field; field order of the image in the buffer + * @timestamp: frame timestamp + * @timecode: frame timecode + * @sequence: sequence count of this frame + * @memory: enum v4l2_memory; the method, in which the actual video data is + * passed + * @offset: for non-multiplanar buffers with memory == V4L2_MEMORY_MMAP; + * offset from the start of the device memory for this plane, + * (or a "cookie" that should be passed to mmap() as offset) + * @userptr: for non-multiplanar buffers with memory == V4L2_MEMORY_USERPTR; + * a userspace pointer pointing to this buffer + * @fd: for non-multiplanar buffers with memory == V4L2_MEMORY_DMABUF; + * a userspace file descriptor associated with this buffer + * @planes: for multiplanar buffers; userspace pointer to the array of plane + * info structs for this buffer + * @length: size in bytes of the buffer (NOT its payload) for single-plane + * buffers (when type != *_MPLANE); number of elements in the + * planes array for multi-plane buffers + * @input: input number from which the video data has has been captured + * + * Contains data exchanged by application and driver using one of the Streaming + * I/O methods. + */ +struct v4l2_buffer { + __u32 index; + __u32 type; + __u32 bytesused; + __u32 flags; + __u32 field; + struct timeval timestamp; + struct v4l2_timecode timecode; + __u32 sequence; + + /* memory location */ + __u32 memory; + union { + __u32 offset; + unsigned long userptr; + struct v4l2_plane *planes; + __s32 fd; + } m; + __u32 length; + __u32 reserved2; + __u32 reserved; +}; + +/* Flags for 'flags' field */ +#define V4L2_BUF_FLAG_MAPPED 0x0001 /* Buffer is mapped (flag) */ +#define V4L2_BUF_FLAG_QUEUED 0x0002 /* Buffer is queued for processing */ +#define V4L2_BUF_FLAG_DONE 0x0004 /* Buffer is ready */ +#define V4L2_BUF_FLAG_KEYFRAME 0x0008 /* Image is a keyframe (I-frame) */ +#define V4L2_BUF_FLAG_PFRAME 0x0010 /* Image is a P-frame */ +#define V4L2_BUF_FLAG_BFRAME 0x0020 /* Image is a B-frame */ +/* Buffer is ready, but the data contained within is corrupted. */ +#define V4L2_BUF_FLAG_ERROR 0x0040 +#define V4L2_BUF_FLAG_TIMECODE 0x0100 /* timecode field is valid */ +#define V4L2_BUF_FLAG_PREPARED 0x0400 /* Buffer is prepared for queuing */ +/* Cache handling flags */ +#define V4L2_BUF_FLAG_NO_CACHE_INVALIDATE 0x0800 +#define V4L2_BUF_FLAG_NO_CACHE_CLEAN 0x1000 +/* Timestamp type */ +#define V4L2_BUF_FLAG_TIMESTAMP_MASK 0xe000 +#define V4L2_BUF_FLAG_TIMESTAMP_UNKNOWN 0x0000 +#define V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC 0x2000 +#define V4L2_BUF_FLAG_TIMESTAMP_COPY 0x4000 +/* Vendor extensions */ +#define V4L2_QCOM_BUF_FLAG_CODECCONFIG 0x10000 +#define V4L2_QCOM_BUF_FLAG_EOSEQ 0x20000 +#define V4L2_QCOM_BUF_TIMESTAMP_INVALID 0x40000 +#define V4L2_QCOM_BUF_FLAG_IDRFRAME 0x80000 /*Image is a IDR-frame*/ +#define V4L2_QCOM_BUF_FLAG_DECODEONLY 0x100000 +#define V4L2_QCOM_BUF_DATA_CORRUPT 0x200000 +#define V4L2_QCOM_BUF_DROP_FRAME 0x400000 +#define V4L2_QCOM_BUF_INPUT_UNSUPPORTED 0x800000 +#define V4L2_QCOM_BUF_FLAG_EOS 0x1000000 +#define V4L2_QCOM_BUF_TS_DISCONTINUITY 0x2000000 +#define V4L2_QCOM_BUF_TS_ERROR 0x4000000 +#define V4L2_QCOM_BUF_FLAG_READONLY 0x8000000 +#define V4L2_MSM_VIDC_BUF_START_CODE_NOT_FOUND 0x10000000 +#define V4L2_MSM_BUF_FLAG_YUV_601_709_CLAMP 0x20000000 +#define V4L2_MSM_BUF_FLAG_MBAFF 0x40000000 + +/** + * struct v4l2_exportbuffer - export of video buffer as DMABUF file descriptor + * + * @index: id number of the buffer + * @type: enum v4l2_buf_type; buffer type (type == *_MPLANE for + * multiplanar buffers); + * @plane: index of the plane to be exported, 0 for single plane queues + * @flags: flags for newly created file, currently only O_CLOEXEC is + * supported, refer to manual of open syscall for more details + * @fd: file descriptor associated with DMABUF (set by driver) + * + * Contains data used for exporting a video buffer as DMABUF file descriptor. + * The buffer is identified by a 'cookie' returned by VIDIOC_QUERYBUF + * (identical to the cookie used to mmap() the buffer to userspace). All + * reserved fields must be set to zero. The field reserved0 is expected to + * become a structure 'type' allowing an alternative layout of the structure + * content. Therefore this field should not be used for any other extensions. + */ +struct v4l2_exportbuffer { + __u32 type; /* enum v4l2_buf_type */ + __u32 index; + __u32 plane; + __u32 flags; + __s32 fd; + __u32 reserved[11]; +}; + +/* + * O V E R L A Y P R E V I E W + */ +struct v4l2_framebuffer { + __u32 capability; + __u32 flags; +/* FIXME: in theory we should pass something like PCI device + memory + * region + offset instead of some physical address */ + void *base; + struct v4l2_pix_format fmt; +}; +/* Flags for the 'capability' field. Read only */ +#define V4L2_FBUF_CAP_EXTERNOVERLAY 0x0001 +#define V4L2_FBUF_CAP_CHROMAKEY 0x0002 +#define V4L2_FBUF_CAP_LIST_CLIPPING 0x0004 +#define V4L2_FBUF_CAP_BITMAP_CLIPPING 0x0008 +#define V4L2_FBUF_CAP_LOCAL_ALPHA 0x0010 +#define V4L2_FBUF_CAP_GLOBAL_ALPHA 0x0020 +#define V4L2_FBUF_CAP_LOCAL_INV_ALPHA 0x0040 +#define V4L2_FBUF_CAP_SRC_CHROMAKEY 0x0080 +/* Flags for the 'flags' field. */ +#define V4L2_FBUF_FLAG_PRIMARY 0x0001 +#define V4L2_FBUF_FLAG_OVERLAY 0x0002 +#define V4L2_FBUF_FLAG_CHROMAKEY 0x0004 +#define V4L2_FBUF_FLAG_LOCAL_ALPHA 0x0008 +#define V4L2_FBUF_FLAG_GLOBAL_ALPHA 0x0010 +#define V4L2_FBUF_FLAG_LOCAL_INV_ALPHA 0x0020 +#define V4L2_FBUF_FLAG_SRC_CHROMAKEY 0x0040 + +struct v4l2_clip { + struct v4l2_rect c; + struct v4l2_clip __user *next; +}; + +struct v4l2_window { + struct v4l2_rect w; + __u32 field; /* enum v4l2_field */ + __u32 chromakey; + struct v4l2_clip __user *clips; + __u32 clipcount; + void __user *bitmap; + __u8 global_alpha; +}; + +/* + * C A P T U R E P A R A M E T E R S + */ +struct v4l2_captureparm { + __u32 capability; /* Supported modes */ + __u32 capturemode; /* Current mode */ + struct v4l2_fract timeperframe; /* Time per frame in seconds */ + __u32 extendedmode; /* Driver-specific extensions */ + __u32 readbuffers; /* # of buffers for read */ + __u32 reserved[4]; +}; + +/* Flags for 'capability' and 'capturemode' fields */ +#define V4L2_MODE_HIGHQUALITY 0x0001 /* High quality imaging mode */ +#define V4L2_CAP_TIMEPERFRAME 0x1000 /* timeperframe field is supported */ +#define V4L2_CAP_QCOM_FRAMESKIP 0x2000 /* frame skipping is supported */ + +struct v4l2_qcom_frameskip { + __u64 maxframeinterval; + __u8 fpsvariance; +}; + +struct v4l2_outputparm { + __u32 capability; /* Supported modes */ + __u32 outputmode; /* Current mode */ + struct v4l2_fract timeperframe; /* Time per frame in seconds */ + __u32 extendedmode; /* Driver-specific extensions */ + __u32 writebuffers; /* # of buffers for write */ + __u32 reserved[4]; +}; + +/* + * I N P U T I M A G E C R O P P I N G + */ +struct v4l2_cropcap { + __u32 type; /* enum v4l2_buf_type */ + struct v4l2_rect bounds; + struct v4l2_rect defrect; + struct v4l2_fract pixelaspect; +}; + +struct v4l2_crop { + __u32 type; /* enum v4l2_buf_type */ + struct v4l2_rect c; +}; + +/** + * struct v4l2_selection - selection info + * @type: buffer type (do not use *_MPLANE types) + * @target: Selection target, used to choose one of possible rectangles; + * defined in v4l2-common.h; V4L2_SEL_TGT_* . + * @flags: constraints flags, defined in v4l2-common.h; V4L2_SEL_FLAG_*. + * @r: coordinates of selection window + * @reserved: for future use, rounds structure size to 64 bytes, set to zero + * + * Hardware may use multiple helper windows to process a video stream. + * The structure is used to exchange this selection areas between + * an application and a driver. + */ +struct v4l2_selection { + __u32 type; + __u32 target; + __u32 flags; + struct v4l2_rect r; + __u32 reserved[9]; +}; + + +/* + * A N A L O G V I D E O S T A N D A R D + */ + +typedef __u64 v4l2_std_id; + +/* one bit for each */ +#define V4L2_STD_PAL_B ((v4l2_std_id)0x00000001) +#define V4L2_STD_PAL_B1 ((v4l2_std_id)0x00000002) +#define V4L2_STD_PAL_G ((v4l2_std_id)0x00000004) +#define V4L2_STD_PAL_H ((v4l2_std_id)0x00000008) +#define V4L2_STD_PAL_I ((v4l2_std_id)0x00000010) +#define V4L2_STD_PAL_D ((v4l2_std_id)0x00000020) +#define V4L2_STD_PAL_D1 ((v4l2_std_id)0x00000040) +#define V4L2_STD_PAL_K ((v4l2_std_id)0x00000080) + +#define V4L2_STD_PAL_M ((v4l2_std_id)0x00000100) +#define V4L2_STD_PAL_N ((v4l2_std_id)0x00000200) +#define V4L2_STD_PAL_Nc ((v4l2_std_id)0x00000400) +#define V4L2_STD_PAL_60 ((v4l2_std_id)0x00000800) + +#define V4L2_STD_NTSC_M ((v4l2_std_id)0x00001000) /* BTSC */ +#define V4L2_STD_NTSC_M_JP ((v4l2_std_id)0x00002000) /* EIA-J */ +#define V4L2_STD_NTSC_443 ((v4l2_std_id)0x00004000) +#define V4L2_STD_NTSC_M_KR ((v4l2_std_id)0x00008000) /* FM A2 */ + +#define V4L2_STD_SECAM_B ((v4l2_std_id)0x00010000) +#define V4L2_STD_SECAM_D ((v4l2_std_id)0x00020000) +#define V4L2_STD_SECAM_G ((v4l2_std_id)0x00040000) +#define V4L2_STD_SECAM_H ((v4l2_std_id)0x00080000) +#define V4L2_STD_SECAM_K ((v4l2_std_id)0x00100000) +#define V4L2_STD_SECAM_K1 ((v4l2_std_id)0x00200000) +#define V4L2_STD_SECAM_L ((v4l2_std_id)0x00400000) +#define V4L2_STD_SECAM_LC ((v4l2_std_id)0x00800000) + +/* ATSC/HDTV */ +#define V4L2_STD_ATSC_8_VSB ((v4l2_std_id)0x01000000) +#define V4L2_STD_ATSC_16_VSB ((v4l2_std_id)0x02000000) + +/* FIXME: + Although std_id is 64 bits, there is an issue on PPC32 architecture that + makes switch(__u64) to break. So, there's a hack on v4l2-common.c rounding + this value to 32 bits. + As, currently, the max value is for V4L2_STD_ATSC_16_VSB (30 bits wide), + it should work fine. However, if needed to add more than two standards, + v4l2-common.c should be fixed. + */ + +/* + * Some macros to merge video standards in order to make live easier for the + * drivers and V4L2 applications + */ + +/* + * "Common" NTSC/M - It should be noticed that V4L2_STD_NTSC_443 is + * Missing here. + */ +#define V4L2_STD_NTSC (V4L2_STD_NTSC_M |\ + V4L2_STD_NTSC_M_JP |\ + V4L2_STD_NTSC_M_KR) +/* Secam macros */ +#define V4L2_STD_SECAM_DK (V4L2_STD_SECAM_D |\ + V4L2_STD_SECAM_K |\ + V4L2_STD_SECAM_K1) +/* All Secam Standards */ +#define V4L2_STD_SECAM (V4L2_STD_SECAM_B |\ + V4L2_STD_SECAM_G |\ + V4L2_STD_SECAM_H |\ + V4L2_STD_SECAM_DK |\ + V4L2_STD_SECAM_L |\ + V4L2_STD_SECAM_LC) +/* PAL macros */ +#define V4L2_STD_PAL_BG (V4L2_STD_PAL_B |\ + V4L2_STD_PAL_B1 |\ + V4L2_STD_PAL_G) +#define V4L2_STD_PAL_DK (V4L2_STD_PAL_D |\ + V4L2_STD_PAL_D1 |\ + V4L2_STD_PAL_K) +/* + * "Common" PAL - This macro is there to be compatible with the old + * V4L1 concept of "PAL": /BGDKHI. + * Several PAL standards are mising here: /M, /N and /Nc + */ +#define V4L2_STD_PAL (V4L2_STD_PAL_BG |\ + V4L2_STD_PAL_DK |\ + V4L2_STD_PAL_H |\ + V4L2_STD_PAL_I) +/* Chroma "agnostic" standards */ +#define V4L2_STD_B (V4L2_STD_PAL_B |\ + V4L2_STD_PAL_B1 |\ + V4L2_STD_SECAM_B) +#define V4L2_STD_G (V4L2_STD_PAL_G |\ + V4L2_STD_SECAM_G) +#define V4L2_STD_H (V4L2_STD_PAL_H |\ + V4L2_STD_SECAM_H) +#define V4L2_STD_L (V4L2_STD_SECAM_L |\ + V4L2_STD_SECAM_LC) +#define V4L2_STD_GH (V4L2_STD_G |\ + V4L2_STD_H) +#define V4L2_STD_DK (V4L2_STD_PAL_DK |\ + V4L2_STD_SECAM_DK) +#define V4L2_STD_BG (V4L2_STD_B |\ + V4L2_STD_G) +#define V4L2_STD_MN (V4L2_STD_PAL_M |\ + V4L2_STD_PAL_N |\ + V4L2_STD_PAL_Nc |\ + V4L2_STD_NTSC) + +/* Standards where MTS/BTSC stereo could be found */ +#define V4L2_STD_MTS (V4L2_STD_NTSC_M |\ + V4L2_STD_PAL_M |\ + V4L2_STD_PAL_N |\ + V4L2_STD_PAL_Nc) + +/* Standards for Countries with 60Hz Line frequency */ +#define V4L2_STD_525_60 (V4L2_STD_PAL_M |\ + V4L2_STD_PAL_60 |\ + V4L2_STD_NTSC |\ + V4L2_STD_NTSC_443) +/* Standards for Countries with 50Hz Line frequency */ +#define V4L2_STD_625_50 (V4L2_STD_PAL |\ + V4L2_STD_PAL_N |\ + V4L2_STD_PAL_Nc |\ + V4L2_STD_SECAM) + +#define V4L2_STD_ATSC (V4L2_STD_ATSC_8_VSB |\ + V4L2_STD_ATSC_16_VSB) +/* Macros with none and all analog standards */ +#define V4L2_STD_UNKNOWN 0 +#define V4L2_STD_ALL (V4L2_STD_525_60 |\ + V4L2_STD_625_50) + +struct v4l2_standard { + __u32 index; + v4l2_std_id id; + __u8 name[24]; + struct v4l2_fract frameperiod; /* Frames, not fields */ + __u32 framelines; + __u32 reserved[4]; +}; + +/* + * D V B T T I M I N G S + */ + +/** struct v4l2_bt_timings - BT.656/BT.1120 timing data + * @width: total width of the active video in pixels + * @height: total height of the active video in lines + * @interlaced: Interlaced or progressive + * @polarities: Positive or negative polarities + * @pixelclock: Pixel clock in HZ. Ex. 74.25MHz->74250000 + * @hfrontporch:Horizontal front porch in pixels + * @hsync: Horizontal Sync length in pixels + * @hbackporch: Horizontal back porch in pixels + * @vfrontporch:Vertical front porch in lines + * @vsync: Vertical Sync length in lines + * @vbackporch: Vertical back porch in lines + * @il_vfrontporch:Vertical front porch for the even field + * (aka field 2) of interlaced field formats + * @il_vsync: Vertical Sync length for the even field + * (aka field 2) of interlaced field formats + * @il_vbackporch:Vertical back porch for the even field + * (aka field 2) of interlaced field formats + * @standards: Standards the timing belongs to + * @flags: Flags + * @reserved: Reserved fields, must be zeroed. + * + * A note regarding vertical interlaced timings: height refers to the total + * height of the active video frame (= two fields). The blanking timings refer + * to the blanking of each field. So the height of the total frame is + * calculated as follows: + * + * tot_height = height + vfrontporch + vsync + vbackporch + + * il_vfrontporch + il_vsync + il_vbackporch + * + * The active height of each field is height / 2. + */ +struct v4l2_bt_timings { + __u32 width; + __u32 height; + __u32 interlaced; + __u32 polarities; + __u64 pixelclock; + __u32 hfrontporch; + __u32 hsync; + __u32 hbackporch; + __u32 vfrontporch; + __u32 vsync; + __u32 vbackporch; + __u32 il_vfrontporch; + __u32 il_vsync; + __u32 il_vbackporch; + __u32 standards; + __u32 flags; + __u32 reserved[14]; +} __attribute__ ((packed)); + +/* Interlaced or progressive format */ +#define V4L2_DV_PROGRESSIVE 0 +#define V4L2_DV_INTERLACED 1 + +/* Polarities. If bit is not set, it is assumed to be negative polarity */ +#define V4L2_DV_VSYNC_POS_POL 0x00000001 +#define V4L2_DV_HSYNC_POS_POL 0x00000002 + +/* Timings standards */ +#define V4L2_DV_BT_STD_CEA861 (1 << 0) /* CEA-861 Digital TV Profile */ +#define V4L2_DV_BT_STD_DMT (1 << 1) /* VESA Discrete Monitor Timings */ +#define V4L2_DV_BT_STD_CVT (1 << 2) /* VESA Coordinated Video Timings */ +#define V4L2_DV_BT_STD_GTF (1 << 3) /* VESA Generalized Timings Formula */ + +/* Flags */ + +/* CVT/GTF specific: timing uses reduced blanking (CVT) or the 'Secondary + GTF' curve (GTF). In both cases the horizontal and/or vertical blanking + intervals are reduced, allowing a higher resolution over the same + bandwidth. This is a read-only flag. */ +#define V4L2_DV_FL_REDUCED_BLANKING (1 << 0) +/* CEA-861 specific: set for CEA-861 formats with a framerate of a multiple + of six. These formats can be optionally played at 1 / 1.001 speed. + This is a read-only flag. */ +#define V4L2_DV_FL_CAN_REDUCE_FPS (1 << 1) +/* CEA-861 specific: only valid for video transmitters, the flag is cleared + by receivers. + If the framerate of the format is a multiple of six, then the pixelclock + used to set up the transmitter is divided by 1.001 to make it compatible + with 60 Hz based standards such as NTSC and PAL-M that use a framerate of + 29.97 Hz. Otherwise this flag is cleared. If the transmitter can't generate + such frequencies, then the flag will also be cleared. */ +#define V4L2_DV_FL_REDUCED_FPS (1 << 2) +/* Specific to interlaced formats: if set, then field 1 is really one half-line + longer and field 2 is really one half-line shorter, so each field has + exactly the same number of half-lines. Whether half-lines can be detected + or used depends on the hardware. */ +#define V4L2_DV_FL_HALF_LINE (1 << 3) + + +/** struct v4l2_dv_timings - DV timings + * @type: the type of the timings + * @bt: BT656/1120 timings + */ +struct v4l2_dv_timings { + __u32 type; + union { + struct v4l2_bt_timings bt; + __u32 reserved[32]; + }; +} __attribute__ ((packed)); + +/* Values for the type field */ +#define V4L2_DV_BT_656_1120 0 /* BT.656/1120 timing type */ + + +/** struct v4l2_enum_dv_timings - DV timings enumeration + * @index: enumeration index + * @reserved: must be zeroed + * @timings: the timings for the given index + */ +struct v4l2_enum_dv_timings { + __u32 index; + __u32 reserved[3]; + struct v4l2_dv_timings timings; +}; + +/** struct v4l2_bt_timings_cap - BT.656/BT.1120 timing capabilities + * @min_width: width in pixels + * @max_width: width in pixels + * @min_height: height in lines + * @max_height: height in lines + * @min_pixelclock: Pixel clock in HZ. Ex. 74.25MHz->74250000 + * @max_pixelclock: Pixel clock in HZ. Ex. 74.25MHz->74250000 + * @standards: Supported standards + * @capabilities: Supported capabilities + * @reserved: Must be zeroed + */ +struct v4l2_bt_timings_cap { + __u32 min_width; + __u32 max_width; + __u32 min_height; + __u32 max_height; + __u64 min_pixelclock; + __u64 max_pixelclock; + __u32 standards; + __u32 capabilities; + __u32 reserved[16]; +} __attribute__ ((packed)); + +/* Supports interlaced formats */ +#define V4L2_DV_BT_CAP_INTERLACED (1 << 0) +/* Supports progressive formats */ +#define V4L2_DV_BT_CAP_PROGRESSIVE (1 << 1) +/* Supports CVT/GTF reduced blanking */ +#define V4L2_DV_BT_CAP_REDUCED_BLANKING (1 << 2) +/* Supports custom formats */ +#define V4L2_DV_BT_CAP_CUSTOM (1 << 3) + +/** struct v4l2_dv_timings_cap - DV timings capabilities + * @type: the type of the timings (same as in struct v4l2_dv_timings) + * @bt: the BT656/1120 timings capabilities + */ +struct v4l2_dv_timings_cap { + __u32 type; + __u32 reserved[3]; + union { + struct v4l2_bt_timings_cap bt; + __u32 raw_data[32]; + }; +}; + + +/* + * V I D E O I N P U T S + */ +struct v4l2_input { + __u32 index; /* Which input */ + __u8 name[32]; /* Label */ + __u32 type; /* Type of input */ + __u32 audioset; /* Associated audios (bitfield) */ + __u32 tuner; /* enum v4l2_tuner_type */ + v4l2_std_id std; + __u32 status; + __u32 capabilities; + __u32 reserved[3]; +}; + +/* Values for the 'type' field */ +#define V4L2_INPUT_TYPE_TUNER 1 +#define V4L2_INPUT_TYPE_CAMERA 2 + +/* field 'status' - general */ +#define V4L2_IN_ST_NO_POWER 0x00000001 /* Attached device is off */ +#define V4L2_IN_ST_NO_SIGNAL 0x00000002 +#define V4L2_IN_ST_NO_COLOR 0x00000004 + +/* field 'status' - sensor orientation */ +/* If sensor is mounted upside down set both bits */ +#define V4L2_IN_ST_HFLIP 0x00000010 /* Frames are flipped horizontally */ +#define V4L2_IN_ST_VFLIP 0x00000020 /* Frames are flipped vertically */ + +/* field 'status' - analog */ +#define V4L2_IN_ST_NO_H_LOCK 0x00000100 /* No horizontal sync lock */ +#define V4L2_IN_ST_COLOR_KILL 0x00000200 /* Color killer is active */ + +/* field 'status' - digital */ +#define V4L2_IN_ST_NO_SYNC 0x00010000 /* No synchronization lock */ +#define V4L2_IN_ST_NO_EQU 0x00020000 /* No equalizer lock */ +#define V4L2_IN_ST_NO_CARRIER 0x00040000 /* Carrier recovery failed */ + +/* field 'status' - VCR and set-top box */ +#define V4L2_IN_ST_MACROVISION 0x01000000 /* Macrovision detected */ +#define V4L2_IN_ST_NO_ACCESS 0x02000000 /* Conditional access denied */ +#define V4L2_IN_ST_VTR 0x04000000 /* VTR time constant */ + +/* capabilities flags */ +#define V4L2_IN_CAP_DV_TIMINGS 0x00000002 /* Supports S_DV_TIMINGS */ +#define V4L2_IN_CAP_CUSTOM_TIMINGS V4L2_IN_CAP_DV_TIMINGS /* For compatibility */ +#define V4L2_IN_CAP_STD 0x00000004 /* Supports S_STD */ + +/* + * V I D E O O U T P U T S + */ +struct v4l2_output { + __u32 index; /* Which output */ + __u8 name[32]; /* Label */ + __u32 type; /* Type of output */ + __u32 audioset; /* Associated audios (bitfield) */ + __u32 modulator; /* Associated modulator */ + v4l2_std_id std; + __u32 capabilities; + __u32 reserved[3]; +}; +/* Values for the 'type' field */ +#define V4L2_OUTPUT_TYPE_MODULATOR 1 +#define V4L2_OUTPUT_TYPE_ANALOG 2 +#define V4L2_OUTPUT_TYPE_ANALOGVGAOVERLAY 3 + +/* capabilities flags */ +#define V4L2_OUT_CAP_DV_TIMINGS 0x00000002 /* Supports S_DV_TIMINGS */ +#define V4L2_OUT_CAP_CUSTOM_TIMINGS V4L2_OUT_CAP_DV_TIMINGS /* For compatibility */ +#define V4L2_OUT_CAP_STD 0x00000004 /* Supports S_STD */ + +/* + * C O N T R O L S + */ +struct v4l2_control { + __u32 id; + __s32 value; +}; + +struct v4l2_ext_control { + __u32 id; + __u32 size; + __u32 reserved2[1]; + union { + __s32 value; + __s64 value64; + char *string; + }; +} __attribute__ ((packed)); + +struct v4l2_ext_controls { + __u32 ctrl_class; + __u32 count; + __u32 error_idx; + __u32 reserved[2]; + struct v4l2_ext_control *controls; +}; + +#define V4L2_CTRL_ID_MASK (0x0fffffff) +#define V4L2_CTRL_ID2CLASS(id) ((id) & 0x0fff0000UL) +#define V4L2_CTRL_DRIVER_PRIV(id) (((id) & 0xffff) >= 0x1000) + +enum v4l2_ctrl_type { + V4L2_CTRL_TYPE_INTEGER = 1, + V4L2_CTRL_TYPE_BOOLEAN = 2, + V4L2_CTRL_TYPE_MENU = 3, + V4L2_CTRL_TYPE_BUTTON = 4, + V4L2_CTRL_TYPE_INTEGER64 = 5, + V4L2_CTRL_TYPE_CTRL_CLASS = 6, + V4L2_CTRL_TYPE_STRING = 7, + V4L2_CTRL_TYPE_BITMASK = 8, + V4L2_CTRL_TYPE_INTEGER_MENU = 9, +}; + +/* Used in the VIDIOC_QUERYCTRL ioctl for querying controls */ +struct v4l2_queryctrl { + __u32 id; + __u32 type; /* enum v4l2_ctrl_type */ + __u8 name[32]; /* Whatever */ + __s32 minimum; /* Note signedness */ + __s32 maximum; + __s32 step; + __s32 default_value; + __u32 flags; + __u32 reserved[2]; +}; + +/* Used in the VIDIOC_QUERYMENU ioctl for querying menu items */ +struct v4l2_querymenu { + __u32 id; + __u32 index; + union { + __u8 name[32]; /* Whatever */ + __s64 value; + }; + __u32 reserved; +} __attribute__ ((packed)); + +/* Control flags */ +#define V4L2_CTRL_FLAG_DISABLED 0x0001 +#define V4L2_CTRL_FLAG_GRABBED 0x0002 +#define V4L2_CTRL_FLAG_READ_ONLY 0x0004 +#define V4L2_CTRL_FLAG_UPDATE 0x0008 +#define V4L2_CTRL_FLAG_INACTIVE 0x0010 +#define V4L2_CTRL_FLAG_SLIDER 0x0020 +#define V4L2_CTRL_FLAG_WRITE_ONLY 0x0040 +#define V4L2_CTRL_FLAG_VOLATILE 0x0080 + +/* Query flag, to be ORed with the control ID */ +#define V4L2_CTRL_FLAG_NEXT_CTRL 0x80000000 + +/* User-class control IDs defined by V4L2 */ +#define V4L2_CID_MAX_CTRLS 1024 +/* IDs reserved for driver specific controls */ +#define V4L2_CID_PRIVATE_BASE 0x08000000 + + +/* + * T U N I N G + */ +struct v4l2_tuner { + __u32 index; + __u8 name[32]; + __u32 type; /* enum v4l2_tuner_type */ + __u32 capability; + __u32 rangelow; + __u32 rangehigh; + __u32 rxsubchans; + __u32 audmode; + __s32 signal; + __s32 afc; + __u32 reserved[4]; +}; + +struct v4l2_modulator { + __u32 index; + __u8 name[32]; + __u32 capability; + __u32 rangelow; + __u32 rangehigh; + __u32 txsubchans; + __u32 reserved[4]; +}; + +/* Flags for the 'capability' field */ +#define V4L2_TUNER_CAP_LOW 0x0001 +#define V4L2_TUNER_CAP_NORM 0x0002 +#define V4L2_TUNER_CAP_HWSEEK_BOUNDED 0x0004 +#define V4L2_TUNER_CAP_HWSEEK_WRAP 0x0008 +#define V4L2_TUNER_CAP_STEREO 0x0010 +#define V4L2_TUNER_CAP_LANG2 0x0020 +#define V4L2_TUNER_CAP_SAP 0x0020 +#define V4L2_TUNER_CAP_LANG1 0x0040 +#define V4L2_TUNER_CAP_RDS 0x0080 +#define V4L2_TUNER_CAP_RDS_BLOCK_IO 0x0100 +#define V4L2_TUNER_CAP_RDS_CONTROLS 0x0200 +#define V4L2_TUNER_CAP_FREQ_BANDS 0x0400 +#define V4L2_TUNER_CAP_HWSEEK_PROG_LIM 0x0800 + +/* Flags for the 'rxsubchans' field */ +#define V4L2_TUNER_SUB_MONO 0x0001 +#define V4L2_TUNER_SUB_STEREO 0x0002 +#define V4L2_TUNER_SUB_LANG2 0x0004 +#define V4L2_TUNER_SUB_SAP 0x0004 +#define V4L2_TUNER_SUB_LANG1 0x0008 +#define V4L2_TUNER_SUB_RDS 0x0010 + +/* Values for the 'audmode' field */ +#define V4L2_TUNER_MODE_MONO 0x0000 +#define V4L2_TUNER_MODE_STEREO 0x0001 +#define V4L2_TUNER_MODE_LANG2 0x0002 +#define V4L2_TUNER_MODE_SAP 0x0002 +#define V4L2_TUNER_MODE_LANG1 0x0003 +#define V4L2_TUNER_MODE_LANG1_LANG2 0x0004 + +struct v4l2_frequency { + __u32 tuner; + __u32 type; /* enum v4l2_tuner_type */ + __u32 frequency; + __u32 reserved[8]; +}; + +#define V4L2_BAND_MODULATION_VSB (1 << 1) +#define V4L2_BAND_MODULATION_FM (1 << 2) +#define V4L2_BAND_MODULATION_AM (1 << 3) + +struct v4l2_frequency_band { + __u32 tuner; + __u32 type; /* enum v4l2_tuner_type */ + __u32 index; + __u32 capability; + __u32 rangelow; + __u32 rangehigh; + __u32 modulation; + __u32 reserved[9]; +}; + +struct v4l2_hw_freq_seek { + __u32 tuner; + __u32 type; /* enum v4l2_tuner_type */ + __u32 seek_upward; + __u32 wrap_around; + __u32 spacing; + __u32 rangelow; + __u32 rangehigh; + __u32 reserved[5]; +}; + +/* + * R D S + */ + +struct v4l2_rds_data { + __u8 lsb; + __u8 msb; + __u8 block; +} __attribute__ ((packed)); + +#define V4L2_RDS_BLOCK_MSK 0x7 +#define V4L2_RDS_BLOCK_A 0 +#define V4L2_RDS_BLOCK_B 1 +#define V4L2_RDS_BLOCK_C 2 +#define V4L2_RDS_BLOCK_D 3 +#define V4L2_RDS_BLOCK_C_ALT 4 +#define V4L2_RDS_BLOCK_INVALID 7 + +#define V4L2_RDS_BLOCK_CORRECTED 0x40 +#define V4L2_RDS_BLOCK_ERROR 0x80 + +/* + * A U D I O + */ +struct v4l2_audio { + __u32 index; + __u8 name[32]; + __u32 capability; + __u32 mode; + __u32 reserved[2]; +}; + +/* Flags for the 'capability' field */ +#define V4L2_AUDCAP_STEREO 0x00001 +#define V4L2_AUDCAP_AVL 0x00002 + +/* Flags for the 'mode' field */ +#define V4L2_AUDMODE_AVL 0x00001 + +struct v4l2_audioout { + __u32 index; + __u8 name[32]; + __u32 capability; + __u32 mode; + __u32 reserved[2]; +}; + +/* + * M P E G S E R V I C E S + * + * NOTE: EXPERIMENTAL API + */ +#if 1 +#define V4L2_ENC_IDX_FRAME_I (0) +#define V4L2_ENC_IDX_FRAME_P (1) +#define V4L2_ENC_IDX_FRAME_B (2) +#define V4L2_ENC_IDX_FRAME_MASK (0xf) + +struct v4l2_enc_idx_entry { + __u64 offset; + __u64 pts; + __u32 length; + __u32 flags; + __u32 reserved[2]; +}; + +#define V4L2_ENC_IDX_ENTRIES (64) +struct v4l2_enc_idx { + __u32 entries; + __u32 entries_cap; + __u32 reserved[4]; + struct v4l2_enc_idx_entry entry[V4L2_ENC_IDX_ENTRIES]; +}; + + +#define V4L2_ENC_CMD_START (0) +#define V4L2_ENC_CMD_STOP (1) +#define V4L2_ENC_CMD_PAUSE (2) +#define V4L2_ENC_CMD_RESUME (3) +#define V4L2_ENC_QCOM_CMD_FLUSH (4) + +/* Flags for V4L2_ENC_CMD_STOP */ +#define V4L2_ENC_CMD_STOP_AT_GOP_END (1 << 0) + +struct v4l2_encoder_cmd { + __u32 cmd; + __u32 flags; + union { + struct { + __u32 data[8]; + } raw; + }; +}; + +/* Decoder commands */ +#define V4L2_DEC_CMD_START (0) +#define V4L2_DEC_CMD_STOP (1) +#define V4L2_DEC_CMD_PAUSE (2) +#define V4L2_DEC_CMD_RESUME (3) +#define V4L2_DEC_QCOM_CMD_FLUSH (4) + +/* Flags for V4L2_DEC_CMD_START */ +#define V4L2_DEC_CMD_START_MUTE_AUDIO (1 << 0) + +/* Flags for V4L2_DEC_CMD_PAUSE */ +#define V4L2_DEC_CMD_PAUSE_TO_BLACK (1 << 0) + +/* Flags for V4L2_DEC_CMD_STOP */ +#define V4L2_DEC_CMD_STOP_TO_BLACK (1 << 0) +#define V4L2_DEC_CMD_STOP_IMMEDIATELY (1 << 1) + +/* Flags for V4L2_DEC_QCOM_CMD_FLUSH */ +#define V4L2_DEC_QCOM_CMD_FLUSH_OUTPUT (1 << 0) +#define V4L2_DEC_QCOM_CMD_FLUSH_CAPTURE (1 << 1) + +#define V4L2_QCOM_CMD_FLUSH_OUTPUT (1 << 0) +#define V4L2_QCOM_CMD_FLUSH_CAPTURE (1 << 1) + +/* Play format requirements (returned by the driver): */ + +/* The decoder has no special format requirements */ +#define V4L2_DEC_START_FMT_NONE (0) +/* The decoder requires full GOPs */ +#define V4L2_DEC_START_FMT_GOP (1) + +/* The structure must be zeroed before use by the application + This ensures it can be extended safely in the future. */ +struct v4l2_decoder_cmd { + __u32 cmd; + __u32 flags; + union { + struct { + __u64 pts; + } stop; + + struct { + /* 0 or 1000 specifies normal speed, + 1 specifies forward single stepping, + -1 specifies backward single stepping, + >1: playback at speed/1000 of the normal speed, + <-1: reverse playback at (-speed/1000) of the normal speed. */ + __s32 speed; + __u32 format; + } start; + + struct { + __u32 data[16]; + } raw; + }; +}; +#endif + + +/* + * D A T A S E R V I C E S ( V B I ) + * + * Data services API by Michael Schimek + */ + +/* Raw VBI */ +struct v4l2_vbi_format { + __u32 sampling_rate; /* in 1 Hz */ + __u32 offset; + __u32 samples_per_line; + __u32 sample_format; /* V4L2_PIX_FMT_* */ + __s32 start[2]; + __u32 count[2]; + __u32 flags; /* V4L2_VBI_* */ + __u32 reserved[2]; /* must be zero */ +}; + +/* VBI flags */ +#define V4L2_VBI_UNSYNC (1 << 0) +#define V4L2_VBI_INTERLACED (1 << 1) + +/* Sliced VBI + * + * This implements is a proposal V4L2 API to allow SLICED VBI + * required for some hardware encoders. It should change without + * notice in the definitive implementation. + */ + +struct v4l2_sliced_vbi_format { + __u16 service_set; + /* service_lines[0][...] specifies lines 0-23 (1-23 used) of the first field + service_lines[1][...] specifies lines 0-23 (1-23 used) of the second field + (equals frame lines 313-336 for 625 line video + standards, 263-286 for 525 line standards) */ + __u16 service_lines[2][24]; + __u32 io_size; + __u32 reserved[2]; /* must be zero */ +}; + +/* Teletext World System Teletext + (WST), defined on ITU-R BT.653-2 */ +#define V4L2_SLICED_TELETEXT_B (0x0001) +/* Video Program System, defined on ETS 300 231*/ +#define V4L2_SLICED_VPS (0x0400) +/* Closed Caption, defined on EIA-608 */ +#define V4L2_SLICED_CAPTION_525 (0x1000) +/* Wide Screen System, defined on ITU-R BT1119.1 */ +#define V4L2_SLICED_WSS_625 (0x4000) + +#define V4L2_SLICED_VBI_525 (V4L2_SLICED_CAPTION_525) +#define V4L2_SLICED_VBI_625 (V4L2_SLICED_TELETEXT_B | V4L2_SLICED_VPS | V4L2_SLICED_WSS_625) + +struct v4l2_sliced_vbi_cap { + __u16 service_set; + /* service_lines[0][...] specifies lines 0-23 (1-23 used) of the first field + service_lines[1][...] specifies lines 0-23 (1-23 used) of the second field + (equals frame lines 313-336 for 625 line video + standards, 263-286 for 525 line standards) */ + __u16 service_lines[2][24]; + __u32 type; /* enum v4l2_buf_type */ + __u32 reserved[3]; /* must be 0 */ +}; + +struct v4l2_sliced_vbi_data { + __u32 id; + __u32 field; /* 0: first field, 1: second field */ + __u32 line; /* 1-23 */ + __u32 reserved; /* must be 0 */ + __u8 data[48]; +}; + +/* + * Sliced VBI data inserted into MPEG Streams + */ + +/* + * V4L2_MPEG_STREAM_VBI_FMT_IVTV: + * + * Structure of payload contained in an MPEG 2 Private Stream 1 PES Packet in an + * MPEG-2 Program Pack that contains V4L2_MPEG_STREAM_VBI_FMT_IVTV Sliced VBI + * data + * + * Note, the MPEG-2 Program Pack and Private Stream 1 PES packet header + * definitions are not included here. See the MPEG-2 specifications for details + * on these headers. + */ + +/* Line type IDs */ +#define V4L2_MPEG_VBI_IVTV_TELETEXT_B (1) +#define V4L2_MPEG_VBI_IVTV_CAPTION_525 (4) +#define V4L2_MPEG_VBI_IVTV_WSS_625 (5) +#define V4L2_MPEG_VBI_IVTV_VPS (7) + +struct v4l2_mpeg_vbi_itv0_line { + __u8 id; /* One of V4L2_MPEG_VBI_IVTV_* above */ + __u8 data[42]; /* Sliced VBI data for the line */ +} __attribute__ ((packed)); + +struct v4l2_mpeg_vbi_itv0 { + __le32 linemask[2]; /* Bitmasks of VBI service lines present */ + struct v4l2_mpeg_vbi_itv0_line line[35]; +} __attribute__ ((packed)); + +struct v4l2_mpeg_vbi_ITV0 { + struct v4l2_mpeg_vbi_itv0_line line[36]; +} __attribute__ ((packed)); + +#define V4L2_MPEG_VBI_IVTV_MAGIC0 "itv0" +#define V4L2_MPEG_VBI_IVTV_MAGIC1 "ITV0" + +struct v4l2_mpeg_vbi_fmt_ivtv { + __u8 magic[4]; + union { + struct v4l2_mpeg_vbi_itv0 itv0; + struct v4l2_mpeg_vbi_ITV0 ITV0; + }; +} __attribute__ ((packed)); + +/* + * A G G R E G A T E S T R U C T U R E S + */ + +/** + * struct v4l2_plane_pix_format - additional, per-plane format definition + * @sizeimage: maximum size in bytes required for data, for which + * this plane will be used + * @bytesperline: distance in bytes between the leftmost pixels in two + * adjacent lines + */ +struct v4l2_plane_pix_format { + __u32 sizeimage; + __u16 bytesperline; + __u16 reserved[7]; +} __attribute__ ((packed)); + +/** + * struct v4l2_pix_format_mplane - multiplanar format definition + * @width: image width in pixels + * @height: image height in pixels + * @pixelformat: little endian four character code (fourcc) + * @field: enum v4l2_field; field order (for interlaced video) + * @colorspace: enum v4l2_colorspace; supplemental to pixelformat + * @plane_fmt: per-plane information + * @num_planes: number of planes for this format + */ +struct v4l2_pix_format_mplane { + __u32 width; + __u32 height; + __u32 pixelformat; + __u32 field; + __u32 colorspace; + + struct v4l2_plane_pix_format plane_fmt[VIDEO_MAX_PLANES]; + __u8 num_planes; + __u8 reserved[11]; +} __attribute__ ((packed)); + +/** + * struct v4l2_format - stream data format + * @type: enum v4l2_buf_type; type of the data stream + * @pix: definition of an image format + * @pix_mp: definition of a multiplanar image format + * @win: definition of an overlaid image + * @vbi: raw VBI capture or output parameters + * @sliced: sliced VBI capture or output parameters + * @raw_data: placeholder for future extensions and custom formats + */ +struct v4l2_format { + __u32 type; + union { + struct v4l2_pix_format pix; /* V4L2_BUF_TYPE_VIDEO_CAPTURE */ + struct v4l2_pix_format_mplane pix_mp; /* V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE */ + struct v4l2_window win; /* V4L2_BUF_TYPE_VIDEO_OVERLAY */ + struct v4l2_vbi_format vbi; /* V4L2_BUF_TYPE_VBI_CAPTURE */ + struct v4l2_sliced_vbi_format sliced; /* V4L2_BUF_TYPE_SLICED_VBI_CAPTURE */ + __u8 raw_data[200]; /* user-defined */ + } fmt; +}; + +/* Stream type-dependent parameters + */ +struct v4l2_streamparm { + __u32 type; /* enum v4l2_buf_type */ + union { + struct v4l2_captureparm capture; + struct v4l2_outputparm output; + __u8 raw_data[200]; /* user-defined */ + } parm; +}; + +/* + * E V E N T S + */ + +#define V4L2_EVENT_ALL 0 +#define V4L2_EVENT_VSYNC 1 +#define V4L2_EVENT_EOS 2 +#define V4L2_EVENT_CTRL 3 +#define V4L2_EVENT_FRAME_SYNC 4 +#define V4L2_EVENT_PRIVATE_START 0x08000000 + +#define V4L2_EVENT_MSM_VIDC_START (V4L2_EVENT_PRIVATE_START + 0x00001000) +#define V4L2_EVENT_MSM_VIDC_FLUSH_DONE (V4L2_EVENT_MSM_VIDC_START + 1) +#define V4L2_EVENT_MSM_VIDC_PORT_SETTINGS_CHANGED_SUFFICIENT \ + (V4L2_EVENT_MSM_VIDC_START + 2) +#define V4L2_EVENT_MSM_VIDC_PORT_SETTINGS_CHANGED_INSUFFICIENT \ + (V4L2_EVENT_MSM_VIDC_START + 3) +#define V4L2_EVENT_MSM_VIDC_CLOSE_DONE (V4L2_EVENT_MSM_VIDC_START + 4) +#define V4L2_EVENT_MSM_VIDC_SYS_ERROR (V4L2_EVENT_MSM_VIDC_START + 5) +#define V4L2_EVENT_MSM_VIDC_RELEASE_BUFFER_REFERENCE \ + (V4L2_EVENT_MSM_VIDC_START + 6) +#define V4L2_EVENT_MSM_VIDC_RELEASE_UNQUEUED_BUFFER \ + (V4L2_EVENT_MSM_VIDC_START + 7) +#define V4L2_EVENT_MSM_VIDC_HW_OVERLOAD (V4L2_EVENT_MSM_VIDC_START + 8) +#define V4L2_EVENT_MSM_VIDC_MAX_CLIENTS (V4L2_EVENT_MSM_VIDC_START + 9) +#define V4L2_EVENT_MSM_VIDC_HW_UNSUPPORTED (V4L2_EVENT_MSM_VIDC_START + 10) + +/* Payload for V4L2_EVENT_VSYNC */ +struct v4l2_event_vsync { + /* Can be V4L2_FIELD_ANY, _NONE, _TOP or _BOTTOM */ + __u8 field; +} __attribute__ ((packed)); + +/* Payload for V4L2_EVENT_CTRL */ +#define V4L2_EVENT_CTRL_CH_VALUE (1 << 0) +#define V4L2_EVENT_CTRL_CH_FLAGS (1 << 1) +#define V4L2_EVENT_CTRL_CH_RANGE (1 << 2) + +struct v4l2_event_ctrl { + __u32 changes; + __u32 type; + union { + __s32 value; + __s64 value64; + }; + __u32 flags; + __s32 minimum; + __s32 maximum; + __s32 step; + __s32 default_value; +}; + +struct v4l2_event_frame_sync { + __u32 frame_sequence; +}; + +struct v4l2_event { + __u32 type; + union { + struct v4l2_event_vsync vsync; + struct v4l2_event_ctrl ctrl; + struct v4l2_event_frame_sync frame_sync; + __u8 data[64]; + } u; + __u32 pending; + __u32 sequence; + struct timespec timestamp; + __u32 id; + __u32 reserved[8]; +}; + +#define V4L2_EVENT_SUB_FL_SEND_INITIAL (1 << 0) +#define V4L2_EVENT_SUB_FL_ALLOW_FEEDBACK (1 << 1) + +struct v4l2_event_subscription { + __u32 type; + __u32 id; + __u32 flags; + __u32 reserved[5]; +}; + +/* + * A D V A N C E D D E B U G G I N G + * + * NOTE: EXPERIMENTAL API, NEVER RELY ON THIS IN APPLICATIONS! + * FOR DEBUGGING, TESTING AND INTERNAL USE ONLY! + */ + +/* VIDIOC_DBG_G_REGISTER and VIDIOC_DBG_S_REGISTER */ + +#define V4L2_CHIP_MATCH_BRIDGE 0 /* Match against chip ID on the bridge (0 for the bridge) */ +#define V4L2_CHIP_MATCH_HOST V4L2_CHIP_MATCH_BRIDGE +#define V4L2_CHIP_MATCH_I2C_DRIVER 1 /* Match against I2C driver name */ +#define V4L2_CHIP_MATCH_I2C_ADDR 2 /* Match against I2C 7-bit address */ +#define V4L2_CHIP_MATCH_AC97 3 /* Match against anciliary AC97 chip */ +#define V4L2_CHIP_MATCH_SUBDEV 4 /* Match against subdev index */ + +struct v4l2_dbg_match { + __u32 type; /* Match type */ + union { /* Match this chip, meaning determined by type */ + __u32 addr; + char name[32]; + }; +} __attribute__ ((packed)); + +struct v4l2_dbg_register { + struct v4l2_dbg_match match; + __u32 size; /* register size in bytes */ + __u64 reg; + __u64 val; +} __attribute__ ((packed)); + +/* VIDIOC_DBG_G_CHIP_IDENT */ +struct v4l2_dbg_chip_ident { + struct v4l2_dbg_match match; + __u32 ident; /* chip identifier as specified in <media/v4l2-chip-ident.h> */ + __u32 revision; /* chip revision, chip specific */ +} __attribute__ ((packed)); + +#define V4L2_CHIP_FL_READABLE (1 << 0) +#define V4L2_CHIP_FL_WRITABLE (1 << 1) + +/* VIDIOC_DBG_G_CHIP_INFO */ +struct v4l2_dbg_chip_info { + struct v4l2_dbg_match match; + char name[32]; + __u32 flags; + __u32 reserved[32]; +} __attribute__ ((packed)); + +/** + * struct v4l2_create_buffers - VIDIOC_CREATE_BUFS argument + * @index: on return, index of the first created buffer + * @count: entry: number of requested buffers, + * return: number of created buffers + * @memory: enum v4l2_memory; buffer memory type + * @format: frame format, for which buffers are requested + * @reserved: future extensions + */ +struct v4l2_create_buffers { + __u32 index; + __u32 count; + __u32 memory; + struct v4l2_format format; + __u32 reserved[8]; +}; + +/* + * I O C T L C O D E S F O R V I D E O D E V I C E S + * + */ +#define VIDIOC_QUERYCAP _IOR('V', 0, struct v4l2_capability) +#define VIDIOC_RESERVED _IO('V', 1) +#define VIDIOC_ENUM_FMT _IOWR('V', 2, struct v4l2_fmtdesc) +#define VIDIOC_G_FMT _IOWR('V', 4, struct v4l2_format) +#define VIDIOC_S_FMT _IOWR('V', 5, struct v4l2_format) +#define VIDIOC_REQBUFS _IOWR('V', 8, struct v4l2_requestbuffers) +#define VIDIOC_QUERYBUF _IOWR('V', 9, struct v4l2_buffer) +#define VIDIOC_G_FBUF _IOR('V', 10, struct v4l2_framebuffer) +#define VIDIOC_S_FBUF _IOW('V', 11, struct v4l2_framebuffer) +#define VIDIOC_OVERLAY _IOW('V', 14, int) +#define VIDIOC_QBUF _IOWR('V', 15, struct v4l2_buffer) +#define VIDIOC_EXPBUF _IOWR('V', 16, struct v4l2_exportbuffer) +#define VIDIOC_DQBUF _IOWR('V', 17, struct v4l2_buffer) +#define VIDIOC_STREAMON _IOW('V', 18, int) +#define VIDIOC_STREAMOFF _IOW('V', 19, int) +#define VIDIOC_G_PARM _IOWR('V', 21, struct v4l2_streamparm) +#define VIDIOC_S_PARM _IOWR('V', 22, struct v4l2_streamparm) +#define VIDIOC_G_STD _IOR('V', 23, v4l2_std_id) +#define VIDIOC_S_STD _IOW('V', 24, v4l2_std_id) +#define VIDIOC_ENUMSTD _IOWR('V', 25, struct v4l2_standard) +#define VIDIOC_ENUMINPUT _IOWR('V', 26, struct v4l2_input) +#define VIDIOC_G_CTRL _IOWR('V', 27, struct v4l2_control) +#define VIDIOC_S_CTRL _IOWR('V', 28, struct v4l2_control) +#define VIDIOC_G_TUNER _IOWR('V', 29, struct v4l2_tuner) +#define VIDIOC_S_TUNER _IOW('V', 30, struct v4l2_tuner) +#define VIDIOC_G_AUDIO _IOR('V', 33, struct v4l2_audio) +#define VIDIOC_S_AUDIO _IOW('V', 34, struct v4l2_audio) +#define VIDIOC_QUERYCTRL _IOWR('V', 36, struct v4l2_queryctrl) +#define VIDIOC_QUERYMENU _IOWR('V', 37, struct v4l2_querymenu) +#define VIDIOC_G_INPUT _IOR('V', 38, int) +#define VIDIOC_S_INPUT _IOWR('V', 39, int) +#define VIDIOC_G_OUTPUT _IOR('V', 46, int) +#define VIDIOC_S_OUTPUT _IOWR('V', 47, int) +#define VIDIOC_ENUMOUTPUT _IOWR('V', 48, struct v4l2_output) +#define VIDIOC_G_AUDOUT _IOR('V', 49, struct v4l2_audioout) +#define VIDIOC_S_AUDOUT _IOW('V', 50, struct v4l2_audioout) +#define VIDIOC_G_MODULATOR _IOWR('V', 54, struct v4l2_modulator) +#define VIDIOC_S_MODULATOR _IOW('V', 55, struct v4l2_modulator) +#define VIDIOC_G_FREQUENCY _IOWR('V', 56, struct v4l2_frequency) +#define VIDIOC_S_FREQUENCY _IOW('V', 57, struct v4l2_frequency) +#define VIDIOC_CROPCAP _IOWR('V', 58, struct v4l2_cropcap) +#define VIDIOC_G_CROP _IOWR('V', 59, struct v4l2_crop) +#define VIDIOC_S_CROP _IOW('V', 60, struct v4l2_crop) +#define VIDIOC_G_JPEGCOMP _IOR('V', 61, struct v4l2_jpegcompression) +#define VIDIOC_S_JPEGCOMP _IOW('V', 62, struct v4l2_jpegcompression) +#define VIDIOC_QUERYSTD _IOR('V', 63, v4l2_std_id) +#define VIDIOC_TRY_FMT _IOWR('V', 64, struct v4l2_format) +#define VIDIOC_ENUMAUDIO _IOWR('V', 65, struct v4l2_audio) +#define VIDIOC_ENUMAUDOUT _IOWR('V', 66, struct v4l2_audioout) +#define VIDIOC_G_PRIORITY _IOR('V', 67, __u32) /* enum v4l2_priority */ +#define VIDIOC_S_PRIORITY _IOW('V', 68, __u32) /* enum v4l2_priority */ +#define VIDIOC_G_SLICED_VBI_CAP _IOWR('V', 69, struct v4l2_sliced_vbi_cap) +#define VIDIOC_LOG_STATUS _IO('V', 70) +#define VIDIOC_G_EXT_CTRLS _IOWR('V', 71, struct v4l2_ext_controls) +#define VIDIOC_S_EXT_CTRLS _IOWR('V', 72, struct v4l2_ext_controls) +#define VIDIOC_TRY_EXT_CTRLS _IOWR('V', 73, struct v4l2_ext_controls) +#define VIDIOC_ENUM_FRAMESIZES _IOWR('V', 74, struct v4l2_frmsizeenum) +#define VIDIOC_ENUM_FRAMEINTERVALS _IOWR('V', 75, struct v4l2_frmivalenum) +#define VIDIOC_G_ENC_INDEX _IOR('V', 76, struct v4l2_enc_idx) +#define VIDIOC_ENCODER_CMD _IOWR('V', 77, struct v4l2_encoder_cmd) +#define VIDIOC_TRY_ENCODER_CMD _IOWR('V', 78, struct v4l2_encoder_cmd) + +/* Experimental, meant for debugging, testing and internal use. + Only implemented if CONFIG_VIDEO_ADV_DEBUG is defined. + You must be root to use these ioctls. Never use these in applications! */ +#define VIDIOC_DBG_S_REGISTER _IOW('V', 79, struct v4l2_dbg_register) +#define VIDIOC_DBG_G_REGISTER _IOWR('V', 80, struct v4l2_dbg_register) + +/* Experimental, meant for debugging, testing and internal use. + Never use this ioctl in applications! + Note: this ioctl is deprecated in favor of VIDIOC_DBG_G_CHIP_INFO and + will go away in the future. */ +#define VIDIOC_DBG_G_CHIP_IDENT _IOWR('V', 81, struct v4l2_dbg_chip_ident) + +#define VIDIOC_S_HW_FREQ_SEEK _IOW('V', 82, struct v4l2_hw_freq_seek) + +#define VIDIOC_S_DV_TIMINGS _IOWR('V', 87, struct v4l2_dv_timings) +#define VIDIOC_G_DV_TIMINGS _IOWR('V', 88, struct v4l2_dv_timings) +#define VIDIOC_DQEVENT _IOR('V', 89, struct v4l2_event) +#define VIDIOC_SUBSCRIBE_EVENT _IOW('V', 90, struct v4l2_event_subscription) +#define VIDIOC_UNSUBSCRIBE_EVENT _IOW('V', 91, struct v4l2_event_subscription) + +/* Experimental, the below two ioctls may change over the next couple of kernel + versions */ +#define VIDIOC_CREATE_BUFS _IOWR('V', 92, struct v4l2_create_buffers) +#define VIDIOC_PREPARE_BUF _IOWR('V', 93, struct v4l2_buffer) + +/* Experimental selection API */ +#define VIDIOC_G_SELECTION _IOWR('V', 94, struct v4l2_selection) +#define VIDIOC_S_SELECTION _IOWR('V', 95, struct v4l2_selection) + +/* Experimental, these two ioctls may change over the next couple of kernel + versions. */ +#define VIDIOC_DECODER_CMD _IOWR('V', 96, struct v4l2_decoder_cmd) +#define VIDIOC_TRY_DECODER_CMD _IOWR('V', 97, struct v4l2_decoder_cmd) + +/* Experimental, these three ioctls may change over the next couple of kernel + versions. */ +#define VIDIOC_ENUM_DV_TIMINGS _IOWR('V', 98, struct v4l2_enum_dv_timings) +#define VIDIOC_QUERY_DV_TIMINGS _IOR('V', 99, struct v4l2_dv_timings) +#define VIDIOC_DV_TIMINGS_CAP _IOWR('V', 100, struct v4l2_dv_timings_cap) + +/* Experimental, this ioctl may change over the next couple of kernel + versions. */ +#define VIDIOC_ENUM_FREQ_BANDS _IOWR('V', 101, struct v4l2_frequency_band) + +/* Experimental, meant for debugging, testing and internal use. + Never use these in applications! */ +#define VIDIOC_DBG_G_CHIP_INFO _IOWR('V', 102, struct v4l2_dbg_chip_info) + +/* Reminder: when adding new ioctls please add support for them to + drivers/media/video/v4l2-compat-ioctl32.c as well! */ + +#define BASE_VIDIOC_PRIVATE 192 /* 192-255 are private */ + +#endif /* _UAPI__LINUX_VIDEODEV2_H */ diff --git a/original-kernel-headers/media/msm_cam_sensor.h b/original-kernel-headers/media/msm_cam_sensor.h new file mode 100644 index 0000000..6cf6e47 --- /dev/null +++ b/original-kernel-headers/media/msm_cam_sensor.h @@ -0,0 +1,771 @@ +#ifndef __LINUX_MSM_CAM_SENSOR_H +#define __LINUX_MSM_CAM_SENSOR_H + +#ifdef MSM_CAMERA_BIONIC +#include <sys/types.h> +#endif + +#include <media/msm_camsensor_sdk.h> + +#include <linux/types.h> +#include <linux/i2c.h> +#ifdef CONFIG_COMPAT +#include <linux/compat.h> +#endif + +#define I2C_SEQ_REG_SETTING_MAX 5 + +#define MSM_SENSOR_MCLK_8HZ 8000000 +#define MSM_SENSOR_MCLK_16HZ 16000000 +#define MSM_SENSOR_MCLK_24HZ 24000000 + +#define MAX_SENSOR_NAME 32 +#define MAX_ACTUATOR_AF_TOTAL_STEPS 1024 + +#define MAX_OIS_MOD_NAME_SIZE 32 +#define MAX_OIS_NAME_SIZE 32 +#define MAX_OIS_REG_SETTINGS 800 + +#define MOVE_NEAR 0 +#define MOVE_FAR 1 + +#define MSM_ACTUATOR_MOVE_SIGNED_FAR -1 +#define MSM_ACTUATOR_MOVE_SIGNED_NEAR 1 + +#define MAX_EEPROM_NAME 32 + +#define MAX_AF_ITERATIONS 3 +#define MAX_NUMBER_OF_STEPS 47 + +enum flash_type { + LED_FLASH = 1, + STROBE_FLASH, + GPIO_FLASH +}; + +enum msm_sensor_resolution_t { + MSM_SENSOR_RES_FULL, + MSM_SENSOR_RES_QTR, + MSM_SENSOR_RES_2, + MSM_SENSOR_RES_3, + MSM_SENSOR_RES_4, + MSM_SENSOR_RES_5, + MSM_SENSOR_RES_6, + MSM_SENSOR_RES_7, + MSM_SENSOR_INVALID_RES, +}; + +enum msm_camera_stream_type_t { + MSM_CAMERA_STREAM_PREVIEW, + MSM_CAMERA_STREAM_SNAPSHOT, + MSM_CAMERA_STREAM_VIDEO, + MSM_CAMERA_STREAM_INVALID, +}; + +enum sensor_sub_module_t { + SUB_MODULE_SENSOR, + SUB_MODULE_CHROMATIX, + SUB_MODULE_ACTUATOR, + SUB_MODULE_EEPROM, + SUB_MODULE_LED_FLASH, + SUB_MODULE_STROBE_FLASH, + SUB_MODULE_CSID, + SUB_MODULE_CSID_3D, + SUB_MODULE_CSIPHY, + SUB_MODULE_CSIPHY_3D, + SUB_MODULE_OIS, + SUB_MODULE_MAX, +}; + +enum { + MSM_CAMERA_EFFECT_MODE_OFF, + MSM_CAMERA_EFFECT_MODE_MONO, + MSM_CAMERA_EFFECT_MODE_NEGATIVE, + MSM_CAMERA_EFFECT_MODE_SOLARIZE, + MSM_CAMERA_EFFECT_MODE_SEPIA, + MSM_CAMERA_EFFECT_MODE_POSTERIZE, + MSM_CAMERA_EFFECT_MODE_WHITEBOARD, + MSM_CAMERA_EFFECT_MODE_BLACKBOARD, + MSM_CAMERA_EFFECT_MODE_AQUA, + MSM_CAMERA_EFFECT_MODE_EMBOSS, + MSM_CAMERA_EFFECT_MODE_SKETCH, + MSM_CAMERA_EFFECT_MODE_NEON, + MSM_CAMERA_EFFECT_MODE_MAX +}; + +enum { + MSM_CAMERA_WB_MODE_AUTO, + MSM_CAMERA_WB_MODE_CUSTOM, + MSM_CAMERA_WB_MODE_INCANDESCENT, + MSM_CAMERA_WB_MODE_FLUORESCENT, + MSM_CAMERA_WB_MODE_WARM_FLUORESCENT, + MSM_CAMERA_WB_MODE_DAYLIGHT, + MSM_CAMERA_WB_MODE_CLOUDY_DAYLIGHT, + MSM_CAMERA_WB_MODE_TWILIGHT, + MSM_CAMERA_WB_MODE_SHADE, + MSM_CAMERA_WB_MODE_OFF, + MSM_CAMERA_WB_MODE_MAX +}; + +enum { + MSM_CAMERA_SCENE_MODE_OFF, + MSM_CAMERA_SCENE_MODE_AUTO, + MSM_CAMERA_SCENE_MODE_LANDSCAPE, + MSM_CAMERA_SCENE_MODE_SNOW, + MSM_CAMERA_SCENE_MODE_BEACH, + MSM_CAMERA_SCENE_MODE_SUNSET, + MSM_CAMERA_SCENE_MODE_NIGHT, + MSM_CAMERA_SCENE_MODE_PORTRAIT, + MSM_CAMERA_SCENE_MODE_BACKLIGHT, + MSM_CAMERA_SCENE_MODE_SPORTS, + MSM_CAMERA_SCENE_MODE_ANTISHAKE, + MSM_CAMERA_SCENE_MODE_FLOWERS, + MSM_CAMERA_SCENE_MODE_CANDLELIGHT, + MSM_CAMERA_SCENE_MODE_FIREWORKS, + MSM_CAMERA_SCENE_MODE_PARTY, + MSM_CAMERA_SCENE_MODE_NIGHT_PORTRAIT, + MSM_CAMERA_SCENE_MODE_THEATRE, + MSM_CAMERA_SCENE_MODE_ACTION, + MSM_CAMERA_SCENE_MODE_AR, + MSM_CAMERA_SCENE_MODE_FACE_PRIORITY, + MSM_CAMERA_SCENE_MODE_BARCODE, + MSM_CAMERA_SCENE_MODE_HDR, + MSM_CAMERA_SCENE_MODE_MAX +}; + +enum csid_cfg_type_t { + CSID_INIT, + CSID_CFG, + CSID_RELEASE, +}; + +enum csiphy_cfg_type_t { + CSIPHY_INIT, + CSIPHY_CFG, + CSIPHY_RELEASE, +}; + +enum camera_vreg_type { + VREG_TYPE_DEFAULT, + VREG_TYPE_CUSTOM, +}; + +enum sensor_af_t { + SENSOR_AF_FOCUSSED, + SENSOR_AF_NOT_FOCUSSED, +}; + +enum cci_i2c_master_t { + MASTER_0, + MASTER_1, + MASTER_MAX, +}; + +struct msm_camera_i2c_array_write_config { + struct msm_camera_i2c_reg_setting conf_array; + uint16_t slave_addr; +}; + +struct msm_camera_i2c_read_config { + uint16_t slave_addr; + uint16_t reg_addr; + enum msm_camera_i2c_data_type data_type; + uint16_t data; +}; + +struct msm_camera_csi2_params { + struct msm_camera_csid_params csid_params; + struct msm_camera_csiphy_params csiphy_params; + uint8_t csi_clk_scale_enable; +}; + +struct msm_camera_csi_lane_params { + uint16_t csi_lane_assign; + uint16_t csi_lane_mask; +}; + +struct csi_lane_params_t { + uint16_t csi_lane_assign; + uint8_t csi_lane_mask; + uint8_t csi_if; + int8_t csid_core[2]; + uint8_t csi_phy_sel; +}; + +struct msm_sensor_info_t { + char sensor_name[MAX_SENSOR_NAME]; + uint32_t session_id; + int32_t subdev_id[SUB_MODULE_MAX]; + int32_t subdev_intf[SUB_MODULE_MAX]; + uint8_t is_mount_angle_valid; + uint32_t sensor_mount_angle; + int modes_supported; + enum camb_position_t position; +}; + +struct camera_vreg_t { + const char *reg_name; + int min_voltage; + int max_voltage; + int op_mode; + uint32_t delay; + const char *custom_vreg_name; + enum camera_vreg_type type; +}; + +struct sensorb_cfg_data { + int cfgtype; + union { + struct msm_sensor_info_t sensor_info; + struct msm_sensor_init_params sensor_init_params; + void *setting; + } cfg; +}; + +struct csid_cfg_data { + enum csid_cfg_type_t cfgtype; + union { + uint32_t csid_version; + struct msm_camera_csid_params *csid_params; + } cfg; +}; + +struct csiphy_cfg_data { + enum csiphy_cfg_type_t cfgtype; + union { + struct msm_camera_csiphy_params *csiphy_params; + struct msm_camera_csi_lane_params *csi_lane_params; + } cfg; +}; + +enum eeprom_cfg_type_t { + CFG_EEPROM_GET_INFO, + CFG_EEPROM_GET_CAL_DATA, + CFG_EEPROM_READ_CAL_DATA, + CFG_EEPROM_WRITE_DATA, + CFG_EEPROM_GET_MM_INFO, +}; + +struct eeprom_get_t { + uint32_t num_bytes; +}; + +struct eeprom_read_t { + uint8_t *dbuffer; + uint32_t num_bytes; +}; + +struct eeprom_write_t { + uint8_t *dbuffer; + uint32_t num_bytes; +}; + +struct eeprom_get_cmm_t { + uint32_t cmm_support; + uint32_t cmm_compression; + uint32_t cmm_size; +}; + +struct msm_eeprom_cfg_data { + enum eeprom_cfg_type_t cfgtype; + uint8_t is_supported; + union { + char eeprom_name[MAX_SENSOR_NAME]; + struct eeprom_get_t get_data; + struct eeprom_read_t read_data; + struct eeprom_write_t write_data; + struct eeprom_get_cmm_t get_cmm_data; + } cfg; +}; + +#ifdef CONFIG_COMPAT +struct msm_sensor_power_setting32 { + enum msm_sensor_power_seq_type_t seq_type; + uint16_t seq_val; + compat_uint_t config_val; + uint16_t delay; + compat_uptr_t data[10]; +}; + +struct msm_sensor_power_setting_array32 { + struct msm_sensor_power_setting32 power_setting_a[MAX_POWER_CONFIG]; + compat_uptr_t power_setting; + uint16_t size; + struct msm_sensor_power_setting32 + power_down_setting_a[MAX_POWER_CONFIG]; + compat_uptr_t power_down_setting; + uint16_t size_down; +}; + +struct msm_camera_sensor_slave_info32 { + char sensor_name[32]; + char eeprom_name[32]; + char actuator_name[32]; + char ois_name[32]; + char flash_name[32]; + enum msm_sensor_camera_id_t camera_id; + uint16_t slave_addr; + enum i2c_freq_mode_t i2c_freq_mode; + enum msm_camera_i2c_reg_addr_type addr_type; + struct msm_sensor_id_info_t sensor_id_info; + struct msm_sensor_power_setting_array32 power_setting_array; + uint8_t is_init_params_valid; + struct msm_sensor_init_params sensor_init_params; + uint8_t is_flash_supported; +}; + +struct msm_camera_csid_lut_params32 { + uint8_t num_cid; + struct msm_camera_csid_vc_cfg vc_cfg_a[MAX_CID]; + compat_uptr_t vc_cfg[MAX_CID]; +}; + +struct msm_camera_csid_params32 { + uint8_t lane_cnt; + uint16_t lane_assign; + uint8_t phy_sel; + uint32_t csi_clk; + struct msm_camera_csid_lut_params32 lut_params; +}; + +struct msm_camera_csi2_params32 { + struct msm_camera_csid_params32 csid_params; + struct msm_camera_csiphy_params csiphy_params; + uint8_t csi_clk_scale_enable; +}; + +struct csid_cfg_data32 { + enum csid_cfg_type_t cfgtype; + union { + uint32_t csid_version; + compat_uptr_t csid_params; + } cfg; +}; + +struct eeprom_read_t32 { + compat_uptr_t dbuffer; + uint32_t num_bytes; +}; + +struct eeprom_write_t32 { + compat_uptr_t dbuffer; + uint32_t num_bytes; +}; + +struct msm_eeprom_cfg_data32 { + enum eeprom_cfg_type_t cfgtype; + uint8_t is_supported; + union { + char eeprom_name[MAX_SENSOR_NAME]; + struct eeprom_get_t get_data; + struct eeprom_read_t32 read_data; + struct eeprom_write_t32 write_data; + } cfg; +}; + +struct msm_camera_i2c_seq_reg_setting32 { + compat_uptr_t reg_setting; + uint16_t size; + enum msm_camera_i2c_reg_addr_type addr_type; + uint16_t delay; +}; +#endif + +enum msm_sensor_cfg_type_t { + CFG_SET_SLAVE_INFO, + CFG_SLAVE_READ_I2C, + CFG_WRITE_I2C_ARRAY, + CFG_SLAVE_WRITE_I2C_ARRAY, + CFG_WRITE_I2C_SEQ_ARRAY, + CFG_POWER_UP, + CFG_POWER_DOWN, + CFG_SET_STOP_STREAM_SETTING, + CFG_GET_SENSOR_INFO, + CFG_GET_SENSOR_INIT_PARAMS, + CFG_SET_INIT_SETTING, + CFG_SET_RESOLUTION, + CFG_SET_STOP_STREAM, + CFG_SET_START_STREAM, + CFG_SET_SATURATION, + CFG_SET_CONTRAST, + CFG_SET_SHARPNESS, + CFG_SET_ISO, + CFG_SET_EXPOSURE_COMPENSATION, + CFG_SET_ANTIBANDING, + CFG_SET_BESTSHOT_MODE, + CFG_SET_EFFECT, + CFG_SET_WHITE_BALANCE, + CFG_SET_AUTOFOCUS, + CFG_CANCEL_AUTOFOCUS, + CFG_SET_STREAM_TYPE, +}; + +enum msm_actuator_cfg_type_t { + CFG_GET_ACTUATOR_INFO, + CFG_SET_ACTUATOR_INFO, + CFG_SET_DEFAULT_FOCUS, + CFG_MOVE_FOCUS, + CFG_SET_POSITION, + CFG_ACTUATOR_POWERDOWN, + CFG_ACTUATOR_POWERUP, + CFG_ACTUATOR_INIT, +}; + +enum msm_ois_cfg_type_t { + CFG_OIS_INIT, + CFG_OIS_POWERDOWN, + CFG_OIS_POWERUP, + CFG_OIS_CONTROL, + CFG_OIS_I2C_WRITE_SEQ_TABLE, +}; + +enum msm_ois_i2c_operation { + MSM_OIS_WRITE = 0, + MSM_OIS_POLL, +}; + +struct reg_settings_ois_t { + uint16_t reg_addr; + enum msm_camera_i2c_reg_addr_type addr_type; + uint32_t reg_data; + enum msm_camera_i2c_data_type data_type; + enum msm_ois_i2c_operation i2c_operation; + uint32_t delay; +}; + +struct msm_ois_params_t { + uint16_t data_size; + uint16_t setting_size; + uint32_t i2c_addr; + enum msm_camera_i2c_reg_addr_type i2c_addr_type; + enum msm_camera_i2c_data_type i2c_data_type; + struct reg_settings_ois_t *settings; +}; + +struct msm_ois_set_info_t { + struct msm_ois_params_t ois_params; +}; + +struct msm_actuator_move_params_t { + int8_t dir; + int8_t sign_dir; + int16_t dest_step_pos; + int32_t num_steps; + uint16_t curr_lens_pos; + struct damping_params_t *ringing_params; +}; + +struct msm_actuator_tuning_params_t { + int16_t initial_code; + uint16_t pwd_step; + uint16_t region_size; + uint32_t total_steps; + struct region_params_t *region_params; +}; + +struct park_lens_data_t { + uint32_t damping_step; + uint32_t damping_delay; + uint32_t hw_params; + uint32_t max_step; +}; + +struct msm_actuator_params_t { + enum actuator_type act_type; + uint8_t reg_tbl_size; + uint16_t data_size; + uint16_t init_setting_size; + uint32_t i2c_addr; + enum msm_actuator_addr_type i2c_addr_type; + enum msm_actuator_data_type i2c_data_type; + struct msm_actuator_reg_params_t *reg_tbl_params; + struct reg_settings_t *init_settings; + struct park_lens_data_t park_lens; +}; + +struct msm_actuator_set_info_t { + struct msm_actuator_params_t actuator_params; + struct msm_actuator_tuning_params_t af_tuning_params; +}; + +struct msm_actuator_get_info_t { + uint32_t focal_length_num; + uint32_t focal_length_den; + uint32_t f_number_num; + uint32_t f_number_den; + uint32_t f_pix_num; + uint32_t f_pix_den; + uint32_t total_f_dist_num; + uint32_t total_f_dist_den; + uint32_t hor_view_angle_num; + uint32_t hor_view_angle_den; + uint32_t ver_view_angle_num; + uint32_t ver_view_angle_den; +}; + +enum af_camera_name { + ACTUATOR_MAIN_CAM_0, + ACTUATOR_MAIN_CAM_1, + ACTUATOR_MAIN_CAM_2, + ACTUATOR_MAIN_CAM_3, + ACTUATOR_MAIN_CAM_4, + ACTUATOR_MAIN_CAM_5, + ACTUATOR_WEB_CAM_0, + ACTUATOR_WEB_CAM_1, + ACTUATOR_WEB_CAM_2, +}; + +struct msm_ois_cfg_data { + int cfgtype; + union { + struct msm_ois_set_info_t set_info; + struct msm_camera_i2c_seq_reg_setting *settings; + } cfg; +}; + +struct msm_actuator_set_position_t { + uint16_t number_of_steps; + uint16_t pos[MAX_NUMBER_OF_STEPS]; + uint16_t delay[MAX_NUMBER_OF_STEPS]; +}; + +struct msm_actuator_cfg_data { + int cfgtype; + uint8_t is_af_supported; + union { + struct msm_actuator_move_params_t move; + struct msm_actuator_set_info_t set_info; + struct msm_actuator_get_info_t get_info; + struct msm_actuator_set_position_t setpos; + enum af_camera_name cam_name; + } cfg; +}; + +enum msm_camera_led_config_t { + MSM_CAMERA_LED_OFF, + MSM_CAMERA_LED_LOW, + MSM_CAMERA_LED_HIGH, + MSM_CAMERA_LED_INIT, + MSM_CAMERA_LED_RELEASE, +}; + +struct msm_camera_led_cfg_t { + enum msm_camera_led_config_t cfgtype; + int32_t torch_current[MAX_LED_TRIGGERS]; + int32_t flash_current[MAX_LED_TRIGGERS]; + int32_t flash_duration[MAX_LED_TRIGGERS]; +}; + +struct msm_flash_init_info_t { + enum msm_flash_driver_type flash_driver_type; + struct msm_sensor_power_setting_array *power_setting_array; + struct msm_camera_i2c_reg_setting_array *settings; +}; + +struct msm_flash_cfg_data_t { + enum msm_flash_cfg_type_t cfg_type; + int32_t flash_current[MAX_LED_TRIGGERS]; + int32_t flash_duration[MAX_LED_TRIGGERS]; + union { + struct msm_flash_init_info_t *flash_init_info; + struct msm_camera_i2c_reg_setting_array *settings; + } cfg; +}; + +/* sensor init structures and enums */ +enum msm_sensor_init_cfg_type_t { + CFG_SINIT_PROBE, + CFG_SINIT_PROBE_DONE, + CFG_SINIT_PROBE_WAIT_DONE, +}; + +struct sensor_init_cfg_data { + enum msm_sensor_init_cfg_type_t cfgtype; + struct msm_sensor_info_t probed_info; + char entity_name[MAX_SENSOR_NAME]; + union { + void *setting; + } cfg; +}; + +#define VIDIOC_MSM_SENSOR_CFG \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 1, struct sensorb_cfg_data) + +#define VIDIOC_MSM_SENSOR_RELEASE \ + _IO('V', BASE_VIDIOC_PRIVATE + 2) + +#define VIDIOC_MSM_SENSOR_GET_SUBDEV_ID \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 3, uint32_t) + +#define VIDIOC_MSM_CSIPHY_IO_CFG \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 4, struct csiphy_cfg_data) + +#define VIDIOC_MSM_CSID_IO_CFG \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 5, struct csid_cfg_data) + +#define VIDIOC_MSM_ACTUATOR_CFG \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 6, struct msm_actuator_cfg_data) + +#define VIDIOC_MSM_FLASH_LED_DATA_CFG \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 7, struct msm_camera_led_cfg_t) + +#define VIDIOC_MSM_EEPROM_CFG \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 8, struct msm_eeprom_cfg_data) + +#define VIDIOC_MSM_SENSOR_GET_AF_STATUS \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 9, uint32_t) + +#define VIDIOC_MSM_SENSOR_INIT_CFG \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 10, struct sensor_init_cfg_data) + +#define VIDIOC_MSM_OIS_CFG \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 11, struct msm_ois_cfg_data) + +#define VIDIOC_MSM_FLASH_CFG \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 13, struct msm_flash_cfg_data_t) + +#ifdef CONFIG_COMPAT +struct msm_camera_i2c_reg_setting32 { + compat_uptr_t reg_setting; + uint16_t size; + enum msm_camera_i2c_reg_addr_type addr_type; + enum msm_camera_i2c_data_type data_type; + uint16_t delay; +}; + +struct msm_actuator_tuning_params_t32 { + int16_t initial_code; + uint16_t pwd_step; + uint16_t region_size; + uint32_t total_steps; + compat_uptr_t region_params; +}; + +struct msm_actuator_params_t32 { + enum actuator_type act_type; + uint8_t reg_tbl_size; + uint16_t data_size; + uint16_t init_setting_size; + uint32_t i2c_addr; + enum msm_actuator_addr_type i2c_addr_type; + enum msm_actuator_data_type i2c_data_type; + compat_uptr_t reg_tbl_params; + compat_uptr_t init_settings; + struct park_lens_data_t park_lens; +}; + +struct msm_actuator_set_info_t32 { + struct msm_actuator_params_t32 actuator_params; + struct msm_actuator_tuning_params_t32 af_tuning_params; +}; + +struct sensor_init_cfg_data32 { + enum msm_sensor_init_cfg_type_t cfgtype; + struct msm_sensor_info_t probed_info; + char entity_name[MAX_SENSOR_NAME]; + union { + compat_uptr_t setting; + } cfg; +}; + +struct msm_actuator_move_params_t32 { + int8_t dir; + int8_t sign_dir; + int16_t dest_step_pos; + int32_t num_steps; + uint16_t curr_lens_pos; + compat_uptr_t ringing_params; +}; + +struct msm_actuator_cfg_data32 { + int cfgtype; + uint8_t is_af_supported; + union { + struct msm_actuator_move_params_t32 move; + struct msm_actuator_set_info_t32 set_info; + struct msm_actuator_get_info_t get_info; + struct msm_actuator_set_position_t setpos; + enum af_camera_name cam_name; + } cfg; +}; + +struct csiphy_cfg_data32 { + enum csiphy_cfg_type_t cfgtype; + union { + compat_uptr_t csiphy_params; + compat_uptr_t csi_lane_params; + } cfg; +}; + +struct sensorb_cfg_data32 { + int cfgtype; + union { + struct msm_sensor_info_t sensor_info; + struct msm_sensor_init_params sensor_init_params; + compat_uptr_t setting; + } cfg; +}; + +struct msm_ois_params_t32 { + uint16_t data_size; + uint16_t setting_size; + uint32_t i2c_addr; + enum msm_camera_i2c_reg_addr_type i2c_addr_type; + enum msm_camera_i2c_data_type i2c_data_type; + compat_uptr_t settings; +}; + +struct msm_ois_set_info_t32 { + struct msm_ois_params_t32 ois_params; +}; + +struct msm_ois_cfg_data32 { + int cfgtype; + union { + struct msm_ois_set_info_t32 set_info; + compat_uptr_t settings; + } cfg; +}; + +struct msm_flash_init_info_t32 { + enum msm_flash_driver_type flash_driver_type; + compat_uptr_t power_setting_array; + compat_uptr_t settings; +}; + +struct msm_flash_cfg_data_t32 { + enum msm_flash_cfg_type_t cfg_type; + int32_t flash_current[MAX_LED_TRIGGERS]; + int32_t flash_duration[MAX_LED_TRIGGERS]; + union { + compat_uptr_t flash_init_info; + compat_uptr_t settings; + } cfg; +}; + +#define VIDIOC_MSM_ACTUATOR_CFG32 \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 6, struct msm_actuator_cfg_data32) + +#define VIDIOC_MSM_SENSOR_INIT_CFG32 \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 10, struct sensor_init_cfg_data32) + +#define VIDIOC_MSM_CSIPHY_IO_CFG32 \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 4, struct csiphy_cfg_data32) + +#define VIDIOC_MSM_SENSOR_CFG32 \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 1, struct sensorb_cfg_data32) + +#define VIDIOC_MSM_EEPROM_CFG32 \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 8, struct msm_eeprom_cfg_data32) + +#define VIDIOC_MSM_OIS_CFG32 \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 11, struct msm_ois_cfg_data32) + +#define VIDIOC_MSM_CSID_IO_CFG32 \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 5, struct csid_cfg_data32) + +#define VIDIOC_MSM_FLASH_CFG32 \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 13, struct msm_flash_cfg_data_t32) +#endif + +#endif /* __LINUX_MSM_CAM_SENSOR_H */ diff --git a/original-kernel-headers/media/msm_camsensor_sdk.h b/original-kernel-headers/media/msm_camsensor_sdk.h new file mode 100644 index 0000000..5b41578 --- /dev/null +++ b/original-kernel-headers/media/msm_camsensor_sdk.h @@ -0,0 +1,333 @@ +#ifndef __LINUX_MSM_CAMSENSOR_SDK_H +#define __LINUX_MSM_CAMSENSOR_SDK_H + +#include <linux/v4l2-mediabus.h> + +#define KVERSION 0x1 + +#define MAX_POWER_CONFIG 12 +#define GPIO_OUT_LOW (0 << 1) +#define GPIO_OUT_HIGH (1 << 1) +#define CSI_EMBED_DATA 0x12 +#define CSI_RESERVED_DATA_0 0x13 +#define CSI_YUV422_8 0x1E +#define CSI_RAW8 0x2A +#define CSI_RAW10 0x2B +#define CSI_RAW12 0x2C +#define CSI_DECODE_6BIT 0 +#define CSI_DECODE_8BIT 1 +#define CSI_DECODE_10BIT 2 +#define CSI_DECODE_DPCM_10_8_10 5 +#define MAX_CID 16 +#define I2C_SEQ_REG_DATA_MAX 256 +#define MSM_V4L2_PIX_FMT_META v4l2_fourcc('M', 'E', 'T', 'A') /* META */ +#define MSM_V4L2_PIX_FMT_SBGGR14 v4l2_fourcc('B', 'G', '1', '4') + /* 14 BGBG.. GRGR.. */ +#define MSM_V4L2_PIX_FMT_SGBRG14 v4l2_fourcc('G', 'B', '1', '4') + /* 14 GBGB.. RGRG.. */ +#define MSM_V4L2_PIX_FMT_SGRBG14 v4l2_fourcc('B', 'A', '1', '4') + /* 14 GRGR.. BGBG.. */ +#define MSM_V4L2_PIX_FMT_SRGGB14 v4l2_fourcc('R', 'G', '1', '4') + /* 14 RGRG.. GBGB.. */ + +#define MAX_ACTUATOR_REG_TBL_SIZE 8 +#define MAX_ACTUATOR_REGION 5 +#define NUM_ACTUATOR_DIR 2 +#define MAX_ACTUATOR_SCENARIO 8 +#define MAX_ACT_MOD_NAME_SIZE 32 +#define MAX_ACT_NAME_SIZE 32 +#define MAX_ACTUATOR_INIT_SET 120 +#define MAX_I2C_REG_SET 12 + +#define MAX_NAME_SIZE 32 +#define MAX_LED_TRIGGERS 3 + +enum msm_sensor_camera_id_t { + CAMERA_0, + CAMERA_1, + CAMERA_2, + CAMERA_3, + MAX_CAMERAS, +}; + +enum i2c_freq_mode_t { + I2C_STANDARD_MODE, + I2C_FAST_MODE, + I2C_CUSTOM_MODE, + I2C_FAST_PLUS_MODE, + I2C_MAX_MODES, +}; + +enum camb_position_t { + BACK_CAMERA_B, + FRONT_CAMERA_B, + INVALID_CAMERA_B, +}; + +enum msm_sensor_power_seq_type_t { + SENSOR_CLK, + SENSOR_GPIO, + SENSOR_VREG, + SENSOR_I2C_MUX, + SENSOR_I2C, +}; + +enum msm_camera_i2c_reg_addr_type { + MSM_CAMERA_I2C_BYTE_ADDR = 1, + MSM_CAMERA_I2C_WORD_ADDR, + MSM_CAMERA_I2C_3B_ADDR, + MSM_CAMERA_I2C_ADDR_TYPE_MAX, +}; + +enum msm_camera_i2c_data_type { + MSM_CAMERA_I2C_BYTE_DATA = 1, + MSM_CAMERA_I2C_WORD_DATA, + MSM_CAMERA_I2C_DWORD_DATA, + MSM_CAMERA_I2C_SET_BYTE_MASK, + MSM_CAMERA_I2C_UNSET_BYTE_MASK, + MSM_CAMERA_I2C_SET_WORD_MASK, + MSM_CAMERA_I2C_UNSET_WORD_MASK, + MSM_CAMERA_I2C_SET_BYTE_WRITE_MASK_DATA, + MSM_CAMERA_I2C_DATA_TYPE_MAX, +}; + +enum msm_sensor_power_seq_gpio_t { + SENSOR_GPIO_RESET, + SENSOR_GPIO_STANDBY, + SENSOR_GPIO_AF_PWDM, + SENSOR_GPIO_VIO, + SENSOR_GPIO_VANA, + SENSOR_GPIO_VDIG, + SENSOR_GPIO_VAF, + SENSOR_GPIO_FL_EN, + SENSOR_GPIO_FL_NOW, + SENSOR_GPIO_FL_RESET, + SENSOR_GPIO_CUSTOM1, + SENSOR_GPIO_CUSTOM2, + SENSOR_GPIO_MAX, +}; + +enum msm_camera_vreg_name_t { + CAM_VDIG, + CAM_VIO, + CAM_VANA, + CAM_VAF, + CAM_V_CUSTOM1, + CAM_V_CUSTOM2, + CAM_VREG_MAX, +}; + +enum msm_sensor_clk_type_t { + SENSOR_CAM_MCLK, + SENSOR_CAM_CLK, + SENSOR_CAM_CLK_MAX, +}; + +enum camerab_mode_t { + CAMERA_MODE_2D_B = (1<<0), + CAMERA_MODE_3D_B = (1<<1), + CAMERA_MODE_INVALID = (1<<2), +}; + +enum sensor_stats_type { + YRGB, + YYYY, +}; + +enum msm_actuator_data_type { + MSM_ACTUATOR_BYTE_DATA = 1, + MSM_ACTUATOR_WORD_DATA, +}; + +enum msm_actuator_addr_type { + MSM_ACTUATOR_BYTE_ADDR = 1, + MSM_ACTUATOR_WORD_ADDR, +}; + +enum msm_actuator_write_type { + MSM_ACTUATOR_WRITE_HW_DAMP, + MSM_ACTUATOR_WRITE_DAC, + MSM_ACTUATOR_WRITE, + MSM_ACTUATOR_WRITE_DIR_REG, + MSM_ACTUATOR_POLL, + MSM_ACTUATOR_READ_WRITE, +}; + +enum msm_actuator_i2c_operation { + MSM_ACT_WRITE = 0, + MSM_ACT_POLL, +}; + +enum actuator_type { + ACTUATOR_VCM, + ACTUATOR_PIEZO, + ACTUATOR_HVCM, + ACTUATOR_BIVCM, +}; + +enum msm_flash_driver_type { + FLASH_DRIVER_PMIC, + FLASH_DRIVER_I2C, + FLASH_DRIVER_GPIO, + FLASH_DRIVER_DEFAULT +}; + +enum msm_flash_cfg_type_t { + CFG_FLASH_INIT, + CFG_FLASH_RELEASE, + CFG_FLASH_OFF, + CFG_FLASH_LOW, + CFG_FLASH_HIGH, +}; + +struct msm_sensor_power_setting { + enum msm_sensor_power_seq_type_t seq_type; + uint16_t seq_val; + long config_val; + uint16_t delay; + void *data[10]; +}; + +struct msm_sensor_power_setting_array { + struct msm_sensor_power_setting power_setting_a[MAX_POWER_CONFIG]; + struct msm_sensor_power_setting *power_setting; + uint16_t size; + struct msm_sensor_power_setting power_down_setting_a[MAX_POWER_CONFIG]; + struct msm_sensor_power_setting *power_down_setting; + uint16_t size_down; +}; + +struct msm_sensor_init_params { + /* mask of modes supported: 2D, 3D */ + int modes_supported; + /* sensor position: front, back */ + enum camb_position_t position; + /* sensor mount angle */ + uint32_t sensor_mount_angle; +}; + +struct msm_sensor_id_info_t { + uint16_t sensor_id_reg_addr; + uint16_t sensor_id; + uint16_t sensor_id_mask; +}; + +struct msm_camera_sensor_slave_info { + char sensor_name[32]; + char eeprom_name[32]; + char actuator_name[32]; + char ois_name[32]; + char flash_name[32]; + enum msm_sensor_camera_id_t camera_id; + uint16_t slave_addr; + enum i2c_freq_mode_t i2c_freq_mode; + enum msm_camera_i2c_reg_addr_type addr_type; + struct msm_sensor_id_info_t sensor_id_info; + struct msm_sensor_power_setting_array power_setting_array; + uint8_t is_init_params_valid; + struct msm_sensor_init_params sensor_init_params; + uint8_t is_flash_supported; +}; + +struct msm_camera_i2c_reg_array { + uint16_t reg_addr; + uint16_t reg_data; + uint32_t delay; +}; + +struct msm_camera_i2c_reg_setting { + struct msm_camera_i2c_reg_array *reg_setting; + uint16_t size; + enum msm_camera_i2c_reg_addr_type addr_type; + enum msm_camera_i2c_data_type data_type; + uint16_t delay; +}; + +struct msm_camera_csid_vc_cfg { + uint8_t cid; + uint8_t dt; + uint8_t decode_format; +}; + +struct msm_camera_csid_lut_params { + uint8_t num_cid; + struct msm_camera_csid_vc_cfg vc_cfg_a[MAX_CID]; + struct msm_camera_csid_vc_cfg *vc_cfg[MAX_CID]; +}; + +struct msm_camera_csid_params { + uint8_t lane_cnt; + uint16_t lane_assign; + uint8_t phy_sel; + uint32_t csi_clk; + struct msm_camera_csid_lut_params lut_params; +}; + +struct msm_camera_csiphy_params { + uint8_t lane_cnt; + uint8_t settle_cnt; + uint16_t lane_mask; + uint8_t combo_mode; + uint8_t csid_core; + uint32_t csiphy_clk; +}; + +struct msm_camera_i2c_seq_reg_array { + uint16_t reg_addr; + uint8_t reg_data[I2C_SEQ_REG_DATA_MAX]; + uint16_t reg_data_size; +}; + +struct msm_camera_i2c_seq_reg_setting { + struct msm_camera_i2c_seq_reg_array *reg_setting; + uint16_t size; + enum msm_camera_i2c_reg_addr_type addr_type; + uint16_t delay; +}; + +struct msm_actuator_reg_params_t { + enum msm_actuator_write_type reg_write_type; + uint32_t hw_mask; + uint16_t reg_addr; + uint16_t hw_shift; + uint16_t data_shift; + uint16_t data_type; + uint16_t addr_type; + uint16_t reg_data; + uint16_t delay; +}; + + +struct damping_params_t { + uint32_t damping_step; + uint32_t damping_delay; + uint32_t hw_params; +}; + +struct region_params_t { + /* [0] = ForwardDirection Macro boundary + [1] = ReverseDirection Inf boundary + */ + uint16_t step_bound[2]; + uint16_t code_per_step; + /* qvalue for converting float type numbers to integer format */ + uint32_t qvalue; +}; + +struct reg_settings_t { + uint16_t reg_addr; + enum msm_actuator_addr_type addr_type; + uint16_t reg_data; + enum msm_actuator_data_type data_type; + enum msm_actuator_i2c_operation i2c_operation; + uint32_t delay; +}; + +struct msm_camera_i2c_reg_setting_array { + struct msm_camera_i2c_reg_array reg_setting_a[MAX_I2C_REG_SET]; + uint16_t size; + enum msm_camera_i2c_reg_addr_type addr_type; + enum msm_camera_i2c_data_type data_type; + uint16_t delay; +}; +#endif /* __LINUX_MSM_CAM_SENSOR_H */ diff --git a/original-kernel-headers/media/msm_fd.h b/original-kernel-headers/media/msm_fd.h new file mode 100644 index 0000000..229ee32 --- /dev/null +++ b/original-kernel-headers/media/msm_fd.h @@ -0,0 +1,104 @@ +/* Copyright (c) 2014, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#ifndef __UAPI_MSM_FD__ +#define __UAPI_MSM_FD__ + +#include <linux/videodev2.h> + +/* + * struct msm_fd_event - Structure contain event info. + * @buf_index: Buffer index. + * @frame_id: Frame id. + * @face_cnt: Detected faces. + */ +struct msm_fd_event { + __u32 buf_index; + __u32 frame_id; + __u32 face_cnt; +}; + +/* + * enum msm_fd_pose - Face pose. + */ +enum msm_fd_pose { + MSM_FD_POSE_FRONT, + MSM_FD_POSE_RIGHT_DIAGONAL, + MSM_FD_POSE_RIGHT, + MSM_FD_POSE_LEFT_DIAGONAL, + MSM_FD_POSE_LEFT, +}; + +/* + * struct msm_fd_face_data - Structure contain detected face data. + * @pose: refer to enum msm_fd_pose. + * @angle: Face angle + * @confidence: Face confidence level. + * @reserved: Reserved data for future use. + * @face: Face rectangle. + */ +struct msm_fd_face_data { + __u32 pose; + __u32 angle; + __u32 confidence; + __u32 reserved; + struct v4l2_rect face; +}; + +/* + * struct msm_fd_result - Structure contain detected faces result. + * @frame_id: Frame id of requested result. + * @face_cnt: Number of result faces, driver can modify this value (to smaller) + * @face_data: Pointer to array of face data structures. + * Array size should not be smaller then face_cnt. + */ +struct msm_fd_result { + __u32 frame_id; + __u32 face_cnt; + struct msm_fd_face_data __user *face_data; +}; + +#ifdef CONFIG_COMPAT +/* + * struct msm_fd_result32 - Compat structure contain detected faces result. + * @frame_id: Frame id of requested result. + * @face_cnt: Number of result faces, driver can modify this value (to smaller) + * @face_data: Pointer to array of face data structures. + * Array size should not be smaller then face_cnt. + */ +struct msm_fd_result32 { + __u32 frame_id; + __u32 face_cnt; + compat_uptr_t face_data; +}; + +/* MSM FD compat private ioctl ID */ +#define VIDIOC_MSM_FD_GET_RESULT32 \ + _IOWR('V', BASE_VIDIOC_PRIVATE, struct msm_fd_result32) +#endif + +/* MSM FD private ioctl ID */ +#define VIDIOC_MSM_FD_GET_RESULT \ + _IOWR('V', BASE_VIDIOC_PRIVATE, struct msm_fd_result) + +/* MSM FD event ID */ +#define MSM_EVENT_FD (V4L2_EVENT_PRIVATE_START) + +/* MSM FD control ID's */ +#define V4L2_CID_FD_SPEED (V4L2_CID_PRIVATE_BASE) +#define V4L2_CID_FD_FACE_ANGLE (V4L2_CID_PRIVATE_BASE + 1) +#define V4L2_CID_FD_MIN_FACE_SIZE (V4L2_CID_PRIVATE_BASE + 2) +#define V4L2_CID_FD_FACE_DIRECTION (V4L2_CID_PRIVATE_BASE + 3) +#define V4L2_CID_FD_DETECTION_THRESHOLD (V4L2_CID_PRIVATE_BASE + 4) +#define V4L2_CID_FD_WORK_MEMORY_SIZE (V4L2_CID_PRIVATE_BASE + 5) +#define V4L2_CID_FD_WORK_MEMORY_FD (V4L2_CID_PRIVATE_BASE + 6) + +#endif /* __UAPI_MSM_FD__ */ diff --git a/original-kernel-headers/media/msm_isp.h b/original-kernel-headers/media/msm_isp.h new file mode 100644 index 0000000..90d87c2 --- /dev/null +++ b/original-kernel-headers/media/msm_isp.h @@ -0,0 +1,344 @@ +#ifndef __UAPI_MSM_ISP_H__ +#define __UAPI_MSM_ISP_H__ + +#define BIT(nr) (1UL << (nr)) + +/* ISP message IDs */ +#define MSG_ID_RESET_ACK 0 +#define MSG_ID_START_ACK 1 +#define MSG_ID_STOP_ACK 2 +#define MSG_ID_UPDATE_ACK 3 +#define MSG_ID_OUTPUT_P 4 +#define MSG_ID_OUTPUT_T 5 +#define MSG_ID_OUTPUT_S 6 +#define MSG_ID_OUTPUT_V 7 +#define MSG_ID_SNAPSHOT_DONE 8 +#define MSG_ID_STATS_AEC 9 +#define MSG_ID_STATS_AF 10 +#define MSG_ID_STATS_AWB 11 +#define MSG_ID_STATS_RS 12 +#define MSG_ID_STATS_CS 13 +#define MSG_ID_STATS_IHIST 14 +#define MSG_ID_STATS_SKIN 15 +#define MSG_ID_EPOCH1 16 +#define MSG_ID_EPOCH2 17 +#define MSG_ID_SYNC_TIMER0_DONE 18 +#define MSG_ID_SYNC_TIMER1_DONE 19 +#define MSG_ID_SYNC_TIMER2_DONE 20 +#define MSG_ID_ASYNC_TIMER0_DONE 21 +#define MSG_ID_ASYNC_TIMER1_DONE 22 +#define MSG_ID_ASYNC_TIMER2_DONE 23 +#define MSG_ID_ASYNC_TIMER3_DONE 24 +#define MSG_ID_AE_OVERFLOW 25 +#define MSG_ID_AF_OVERFLOW 26 +#define MSG_ID_AWB_OVERFLOW 27 +#define MSG_ID_RS_OVERFLOW 28 +#define MSG_ID_CS_OVERFLOW 29 +#define MSG_ID_IHIST_OVERFLOW 30 +#define MSG_ID_SKIN_OVERFLOW 31 +#define MSG_ID_AXI_ERROR 32 +#define MSG_ID_CAMIF_OVERFLOW 33 +#define MSG_ID_VIOLATION 34 +#define MSG_ID_CAMIF_ERROR 35 +#define MSG_ID_BUS_OVERFLOW 36 +#define MSG_ID_SOF_ACK 37 +#define MSG_ID_STOP_REC_ACK 38 +#define MSG_ID_STATS_AWB_AEC 39 +#define MSG_ID_OUTPUT_PRIMARY 40 +#define MSG_ID_OUTPUT_SECONDARY 41 +#define MSG_ID_STATS_COMPOSITE 42 +#define MSG_ID_OUTPUT_TERTIARY1 43 +#define MSG_ID_STOP_LS_ACK 44 +#define MSG_ID_OUTPUT_TERTIARY2 45 +#define MSG_ID_STATS_BG 46 +#define MSG_ID_STATS_BF 47 +#define MSG_ID_STATS_BHIST 48 +#define MSG_ID_RDI0_UPDATE_ACK 49 +#define MSG_ID_RDI1_UPDATE_ACK 50 +#define MSG_ID_RDI2_UPDATE_ACK 51 +#define MSG_ID_PIX0_UPDATE_ACK 52 +#define MSG_ID_PREV_STOP_ACK 53 +#define MSG_ID_STATS_BE 54 + + +/* ISP command IDs */ +#define VFE_CMD_DUMMY_0 0 +#define VFE_CMD_SET_CLK 1 +#define VFE_CMD_RESET 2 +#define VFE_CMD_START 3 +#define VFE_CMD_TEST_GEN_START 4 +#define VFE_CMD_OPERATION_CFG 5 +#define VFE_CMD_AXI_OUT_CFG 6 +#define VFE_CMD_CAMIF_CFG 7 +#define VFE_CMD_AXI_INPUT_CFG 8 +#define VFE_CMD_BLACK_LEVEL_CFG 9 +#define VFE_CMD_MESH_ROLL_OFF_CFG 10 +#define VFE_CMD_DEMUX_CFG 11 +#define VFE_CMD_FOV_CFG 12 +#define VFE_CMD_MAIN_SCALER_CFG 13 +#define VFE_CMD_WB_CFG 14 +#define VFE_CMD_COLOR_COR_CFG 15 +#define VFE_CMD_RGB_G_CFG 16 +#define VFE_CMD_LA_CFG 17 +#define VFE_CMD_CHROMA_EN_CFG 18 +#define VFE_CMD_CHROMA_SUP_CFG 19 +#define VFE_CMD_MCE_CFG 20 +#define VFE_CMD_SK_ENHAN_CFG 21 +#define VFE_CMD_ASF_CFG 22 +#define VFE_CMD_S2Y_CFG 23 +#define VFE_CMD_S2CbCr_CFG 24 +#define VFE_CMD_CHROMA_SUBS_CFG 25 +#define VFE_CMD_OUT_CLAMP_CFG 26 +#define VFE_CMD_FRAME_SKIP_CFG 27 +#define VFE_CMD_DUMMY_1 28 +#define VFE_CMD_DUMMY_2 29 +#define VFE_CMD_DUMMY_3 30 +#define VFE_CMD_UPDATE 31 +#define VFE_CMD_BL_LVL_UPDATE 32 +#define VFE_CMD_DEMUX_UPDATE 33 +#define VFE_CMD_FOV_UPDATE 34 +#define VFE_CMD_MAIN_SCALER_UPDATE 35 +#define VFE_CMD_WB_UPDATE 36 +#define VFE_CMD_COLOR_COR_UPDATE 37 +#define VFE_CMD_RGB_G_UPDATE 38 +#define VFE_CMD_LA_UPDATE 39 +#define VFE_CMD_CHROMA_EN_UPDATE 40 +#define VFE_CMD_CHROMA_SUP_UPDATE 41 +#define VFE_CMD_MCE_UPDATE 42 +#define VFE_CMD_SK_ENHAN_UPDATE 43 +#define VFE_CMD_S2CbCr_UPDATE 44 +#define VFE_CMD_S2Y_UPDATE 45 +#define VFE_CMD_ASF_UPDATE 46 +#define VFE_CMD_FRAME_SKIP_UPDATE 47 +#define VFE_CMD_CAMIF_FRAME_UPDATE 48 +#define VFE_CMD_STATS_AF_UPDATE 49 +#define VFE_CMD_STATS_AE_UPDATE 50 +#define VFE_CMD_STATS_AWB_UPDATE 51 +#define VFE_CMD_STATS_RS_UPDATE 52 +#define VFE_CMD_STATS_CS_UPDATE 53 +#define VFE_CMD_STATS_SKIN_UPDATE 54 +#define VFE_CMD_STATS_IHIST_UPDATE 55 +#define VFE_CMD_DUMMY_4 56 +#define VFE_CMD_EPOCH1_ACK 57 +#define VFE_CMD_EPOCH2_ACK 58 +#define VFE_CMD_START_RECORDING 59 +#define VFE_CMD_STOP_RECORDING 60 +#define VFE_CMD_DUMMY_5 61 +#define VFE_CMD_DUMMY_6 62 +#define VFE_CMD_CAPTURE 63 +#define VFE_CMD_DUMMY_7 64 +#define VFE_CMD_STOP 65 +#define VFE_CMD_GET_HW_VERSION 66 +#define VFE_CMD_GET_FRAME_SKIP_COUNTS 67 +#define VFE_CMD_OUTPUT1_BUFFER_ENQ 68 +#define VFE_CMD_OUTPUT2_BUFFER_ENQ 69 +#define VFE_CMD_OUTPUT3_BUFFER_ENQ 70 +#define VFE_CMD_JPEG_OUT_BUF_ENQ 71 +#define VFE_CMD_RAW_OUT_BUF_ENQ 72 +#define VFE_CMD_RAW_IN_BUF_ENQ 73 +#define VFE_CMD_STATS_AF_ENQ 74 +#define VFE_CMD_STATS_AE_ENQ 75 +#define VFE_CMD_STATS_AWB_ENQ 76 +#define VFE_CMD_STATS_RS_ENQ 77 +#define VFE_CMD_STATS_CS_ENQ 78 +#define VFE_CMD_STATS_SKIN_ENQ 79 +#define VFE_CMD_STATS_IHIST_ENQ 80 +#define VFE_CMD_DUMMY_8 81 +#define VFE_CMD_JPEG_ENC_CFG 82 +#define VFE_CMD_DUMMY_9 83 +#define VFE_CMD_STATS_AF_START 84 +#define VFE_CMD_STATS_AF_STOP 85 +#define VFE_CMD_STATS_AE_START 86 +#define VFE_CMD_STATS_AE_STOP 87 +#define VFE_CMD_STATS_AWB_START 88 +#define VFE_CMD_STATS_AWB_STOP 89 +#define VFE_CMD_STATS_RS_START 90 +#define VFE_CMD_STATS_RS_STOP 91 +#define VFE_CMD_STATS_CS_START 92 +#define VFE_CMD_STATS_CS_STOP 93 +#define VFE_CMD_STATS_SKIN_START 94 +#define VFE_CMD_STATS_SKIN_STOP 95 +#define VFE_CMD_STATS_IHIST_START 96 +#define VFE_CMD_STATS_IHIST_STOP 97 +#define VFE_CMD_DUMMY_10 98 +#define VFE_CMD_SYNC_TIMER_SETTING 99 +#define VFE_CMD_ASYNC_TIMER_SETTING 100 +#define VFE_CMD_LIVESHOT 101 +#define VFE_CMD_LA_SETUP 102 +#define VFE_CMD_LINEARIZATION_CFG 103 +#define VFE_CMD_DEMOSAICV3 104 +#define VFE_CMD_DEMOSAICV3_ABCC_CFG 105 +#define VFE_CMD_DEMOSAICV3_DBCC_CFG 106 +#define VFE_CMD_DEMOSAICV3_DBPC_CFG 107 +#define VFE_CMD_DEMOSAICV3_ABF_CFG 108 +#define VFE_CMD_DEMOSAICV3_ABCC_UPDATE 109 +#define VFE_CMD_DEMOSAICV3_DBCC_UPDATE 110 +#define VFE_CMD_DEMOSAICV3_DBPC_UPDATE 111 +#define VFE_CMD_XBAR_CFG 112 +#define VFE_CMD_MODULE_CFG 113 +#define VFE_CMD_ZSL 114 +#define VFE_CMD_LINEARIZATION_UPDATE 115 +#define VFE_CMD_DEMOSAICV3_ABF_UPDATE 116 +#define VFE_CMD_CLF_CFG 117 +#define VFE_CMD_CLF_LUMA_UPDATE 118 +#define VFE_CMD_CLF_CHROMA_UPDATE 119 +#define VFE_CMD_PCA_ROLL_OFF_CFG 120 +#define VFE_CMD_PCA_ROLL_OFF_UPDATE 121 +#define VFE_CMD_GET_REG_DUMP 122 +#define VFE_CMD_GET_LINEARIZATON_TABLE 123 +#define VFE_CMD_GET_MESH_ROLLOFF_TABLE 124 +#define VFE_CMD_GET_PCA_ROLLOFF_TABLE 125 +#define VFE_CMD_GET_RGB_G_TABLE 126 +#define VFE_CMD_GET_LA_TABLE 127 +#define VFE_CMD_DEMOSAICV3_UPDATE 128 +#define VFE_CMD_ACTIVE_REGION_CFG 129 +#define VFE_CMD_COLOR_PROCESSING_CONFIG 130 +#define VFE_CMD_STATS_WB_AEC_CONFIG 131 +#define VFE_CMD_STATS_WB_AEC_UPDATE 132 +#define VFE_CMD_Y_GAMMA_CONFIG 133 +#define VFE_CMD_SCALE_OUTPUT1_CONFIG 134 +#define VFE_CMD_SCALE_OUTPUT2_CONFIG 135 +#define VFE_CMD_CAPTURE_RAW 136 +#define VFE_CMD_STOP_LIVESHOT 137 +#define VFE_CMD_RECONFIG_VFE 138 +#define VFE_CMD_STATS_REQBUF 139 +#define VFE_CMD_STATS_ENQUEUEBUF 140 +#define VFE_CMD_STATS_FLUSH_BUFQ 141 +#define VFE_CMD_STATS_UNREGBUF 142 +#define VFE_CMD_STATS_BG_START 143 +#define VFE_CMD_STATS_BG_STOP 144 +#define VFE_CMD_STATS_BF_START 145 +#define VFE_CMD_STATS_BF_STOP 146 +#define VFE_CMD_STATS_BHIST_START 147 +#define VFE_CMD_STATS_BHIST_STOP 148 +#define VFE_CMD_RESET_2 149 +#define VFE_CMD_FOV_ENC_CFG 150 +#define VFE_CMD_FOV_VIEW_CFG 151 +#define VFE_CMD_FOV_ENC_UPDATE 152 +#define VFE_CMD_FOV_VIEW_UPDATE 153 +#define VFE_CMD_SCALER_ENC_CFG 154 +#define VFE_CMD_SCALER_VIEW_CFG 155 +#define VFE_CMD_SCALER_ENC_UPDATE 156 +#define VFE_CMD_SCALER_VIEW_UPDATE 157 +#define VFE_CMD_COLORXFORM_ENC_CFG 158 +#define VFE_CMD_COLORXFORM_VIEW_CFG 159 +#define VFE_CMD_COLORXFORM_ENC_UPDATE 160 +#define VFE_CMD_COLORXFORM_VIEW_UPDATE 161 +#define VFE_CMD_TEST_GEN_CFG 162 +#define VFE_CMD_STATS_BE_START 163 +#define VFE_CMD_STATS_BE_STOP 164 +struct msm_isp_cmd { + int32_t id; + uint16_t length; + void *value; +}; + +#define VPE_CMD_DUMMY_0 0 +#define VPE_CMD_INIT 1 +#define VPE_CMD_DEINIT 2 +#define VPE_CMD_ENABLE 3 +#define VPE_CMD_DISABLE 4 +#define VPE_CMD_RESET 5 +#define VPE_CMD_FLUSH 6 +#define VPE_CMD_OPERATION_MODE_CFG 7 +#define VPE_CMD_INPUT_PLANE_CFG 8 +#define VPE_CMD_OUTPUT_PLANE_CFG 9 +#define VPE_CMD_INPUT_PLANE_UPDATE 10 +#define VPE_CMD_SCALE_CFG_TYPE 11 +#define VPE_CMD_ZOOM 13 +#define VPE_CMD_MAX 14 + +#define MSM_PP_CMD_TYPE_NOT_USED 0 /* not used */ +#define MSM_PP_CMD_TYPE_VPE 1 /* VPE cmd */ +#define MSM_PP_CMD_TYPE_MCTL 2 /* MCTL cmd */ + +#define MCTL_CMD_DUMMY_0 0 /* not used */ +#define MCTL_CMD_GET_FRAME_BUFFER 1 /* reserve a free frame buffer */ +#define MCTL_CMD_PUT_FRAME_BUFFER 2 /* return the free frame buffer */ +#define MCTL_CMD_DIVERT_FRAME_PP_PATH 3 /* divert frame for pp */ + +/* event typese sending to MCTL PP module */ +#define MCTL_PP_EVENT_NOTUSED 0 +#define MCTL_PP_EVENT_CMD_ACK 1 + +#define VPE_OPERATION_MODE_CFG_LEN 4 +#define VPE_INPUT_PLANE_CFG_LEN 24 +#define VPE_OUTPUT_PLANE_CFG_LEN 20 +#define VPE_INPUT_PLANE_UPDATE_LEN 12 +#define VPE_SCALER_CONFIG_LEN 260 +#define VPE_DIS_OFFSET_CFG_LEN 12 + + +#define CAPTURE_WIDTH 1280 +#define IMEM_Y_SIZE (CAPTURE_WIDTH*16) +#define IMEM_CBCR_SIZE (CAPTURE_WIDTH*8) + +#define IMEM_Y_PING_OFFSET 0x2E000000 +#define IMEM_CBCR_PING_OFFSET (IMEM_Y_PING_OFFSET + IMEM_Y_SIZE) + +#define IMEM_Y_PONG_OFFSET (IMEM_CBCR_PING_OFFSET + IMEM_CBCR_SIZE) +#define IMEM_CBCR_PONG_OFFSET (IMEM_Y_PONG_OFFSET + IMEM_Y_SIZE) + + +struct msm_vpe_op_mode_cfg { + uint8_t op_mode_cfg[VPE_OPERATION_MODE_CFG_LEN]; +}; + +struct msm_vpe_input_plane_cfg { + uint8_t input_plane_cfg[VPE_INPUT_PLANE_CFG_LEN]; +}; + +struct msm_vpe_output_plane_cfg { + uint8_t output_plane_cfg[VPE_OUTPUT_PLANE_CFG_LEN]; +}; + +struct msm_vpe_input_plane_update_cfg { + uint8_t input_plane_update_cfg[VPE_INPUT_PLANE_UPDATE_LEN]; +}; + +struct msm_vpe_scaler_cfg { + uint8_t scaler_cfg[VPE_SCALER_CONFIG_LEN]; +}; + +struct msm_vpe_flush_frame_buffer { + uint32_t src_buf_handle; + uint32_t dest_buf_handle; + int path; +}; + +struct msm_mctl_pp_frame_buffer { + uint32_t buf_handle; + int path; +}; +struct msm_mctl_pp_divert_pp { + int path; + int enable; +}; +struct msm_vpe_clock_rate { + uint32_t rate; +}; + +#define MSM_MCTL_PP_VPE_FRAME_ACK (1<<0) +#define MSM_MCTL_PP_VPE_FRAME_TO_APP (1<<1) + +#define VFE_OUTPUTS_MAIN_AND_PREVIEW BIT(0) +#define VFE_OUTPUTS_MAIN_AND_VIDEO BIT(1) +#define VFE_OUTPUTS_MAIN_AND_THUMB BIT(2) +#define VFE_OUTPUTS_THUMB_AND_MAIN BIT(3) +#define VFE_OUTPUTS_PREVIEW_AND_VIDEO BIT(4) +#define VFE_OUTPUTS_VIDEO_AND_PREVIEW BIT(5) +#define VFE_OUTPUTS_PREVIEW BIT(6) +#define VFE_OUTPUTS_VIDEO BIT(7) +#define VFE_OUTPUTS_RAW BIT(8) +#define VFE_OUTPUTS_JPEG_AND_THUMB BIT(9) +#define VFE_OUTPUTS_THUMB_AND_JPEG BIT(10) +#define VFE_OUTPUTS_RDI0 BIT(11) +#define VFE_OUTPUTS_RDI1 BIT(12) + +struct msm_frame_info { + uint32_t inst_handle; + uint32_t path; +}; + +#endif /*__UAPI_MSM_ISP_H__*/ + diff --git a/original-kernel-headers/media/msm_jpeg.h b/original-kernel-headers/media/msm_jpeg.h new file mode 100644 index 0000000..6c9a487 --- /dev/null +++ b/original-kernel-headers/media/msm_jpeg.h @@ -0,0 +1,124 @@ +#ifndef __LINUX_MSM_JPEG_H +#define __LINUX_MSM_JPEG_H + +#include <linux/types.h> +#include <linux/ioctl.h> + +#define OUTPUT_H2V1 0 +#define OUTPUT_H2V2 1 +#define OUTPUT_BYTE 6 + +#define MSM_JPEG_IOCTL_MAGIC 'g' + +#define MSM_JPEG_IOCTL_GET_HW_VERSION \ + _IOW(MSM_JPEG_IOCTL_MAGIC, 1, struct msm_jpeg_hw_cmd) + +#define MSM_JPEG_IOCTL_RESET \ + _IOW(MSM_JPEG_IOCTL_MAGIC, 2, struct msm_jpeg_ctrl_cmd) + +#define MSM_JPEG_IOCTL_STOP \ + _IOW(MSM_JPEG_IOCTL_MAGIC, 3, struct msm_jpeg_hw_cmds) + +#define MSM_JPEG_IOCTL_START \ + _IOW(MSM_JPEG_IOCTL_MAGIC, 4, struct msm_jpeg_hw_cmds) + +#define MSM_JPEG_IOCTL_INPUT_BUF_ENQUEUE \ + _IOW(MSM_JPEG_IOCTL_MAGIC, 5, struct msm_jpeg_buf) + +#define MSM_JPEG_IOCTL_INPUT_GET \ + _IOW(MSM_JPEG_IOCTL_MAGIC, 6, struct msm_jpeg_buf) + +#define MSM_JPEG_IOCTL_INPUT_GET_UNBLOCK \ + _IOW(MSM_JPEG_IOCTL_MAGIC, 7, int) + +#define MSM_JPEG_IOCTL_OUTPUT_BUF_ENQUEUE \ + _IOW(MSM_JPEG_IOCTL_MAGIC, 8, struct msm_jpeg_buf) + +#define MSM_JPEG_IOCTL_OUTPUT_GET \ + _IOW(MSM_JPEG_IOCTL_MAGIC, 9, struct msm_jpeg_buf) + +#define MSM_JPEG_IOCTL_OUTPUT_GET_UNBLOCK \ + _IOW(MSM_JPEG_IOCTL_MAGIC, 10, int) + +#define MSM_JPEG_IOCTL_EVT_GET \ + _IOW(MSM_JPEG_IOCTL_MAGIC, 11, struct msm_jpeg_ctrl_cmd) + +#define MSM_JPEG_IOCTL_EVT_GET_UNBLOCK \ + _IOW(MSM_JPEG_IOCTL_MAGIC, 12, int) + +#define MSM_JPEG_IOCTL_HW_CMD \ + _IOW(MSM_JPEG_IOCTL_MAGIC, 13, struct msm_jpeg_hw_cmd) + +#define MSM_JPEG_IOCTL_HW_CMDS \ + _IOW(MSM_JPEG_IOCTL_MAGIC, 14, struct msm_jpeg_hw_cmds) + +#define MSM_JPEG_IOCTL_TEST_DUMP_REGION \ + _IOW(MSM_JPEG_IOCTL_MAGIC, 15, unsigned long) + +#define MSM_JPEG_IOCTL_SET_CLK_RATE \ + _IOW(MSM_JPEG_IOCTL_MAGIC, 16, unsigned int) + +#define MSM_JPEG_MODE_REALTIME_ENCODE 0 +#define MSM_JPEG_MODE_OFFLINE_ENCODE 1 +#define MSM_JPEG_MODE_REALTIME_ROTATION 2 +#define MSM_JPEG_MODE_OFFLINE_ROTATION 3 + +struct msm_jpeg_ctrl_cmd { + uint32_t type; + uint32_t len; + void *value; +}; + +#define MSM_JPEG_EVT_RESET 0 +#define MSM_JPEG_EVT_SESSION_DONE 1 +#define MSM_JPEG_EVT_ERR 2 + +struct msm_jpeg_buf { + uint32_t type; + int fd; + + void *vaddr; + + uint32_t y_off; + uint32_t y_len; + uint32_t framedone_len; + + uint32_t cbcr_off; + uint32_t cbcr_len; + + uint32_t num_of_mcu_rows; + uint32_t offset; + uint32_t pln2_off; + uint32_t pln2_len; +}; + +#define MSM_JPEG_HW_CMD_TYPE_READ 0 +#define MSM_JPEG_HW_CMD_TYPE_WRITE 1 +#define MSM_JPEG_HW_CMD_TYPE_WRITE_OR 2 +#define MSM_JPEG_HW_CMD_TYPE_UWAIT 3 +#define MSM_JPEG_HW_CMD_TYPE_MWAIT 4 +#define MSM_JPEG_HW_CMD_TYPE_MDELAY 5 +#define MSM_JPEG_HW_CMD_TYPE_UDELAY 6 +struct msm_jpeg_hw_cmd { + + uint32_t type:4; + + /* n microseconds of timeout for WAIT */ + /* n microseconds of time for DELAY */ + /* repeat n times for READ/WRITE */ + /* max is 0xFFF, 4095 */ + uint32_t n:12; + uint32_t offset:16; + uint32_t mask; + union { + uint32_t data; /* for single READ/WRITE/WAIT, n = 1 */ + uint32_t *pdata; /* for multiple READ/WRITE/WAIT, n > 1 */ + }; +}; + +struct msm_jpeg_hw_cmds { + uint32_t m; /* number of elements in the hw_cmd array */ + struct msm_jpeg_hw_cmd hw_cmd[1]; +}; + +#endif /* __LINUX_MSM_JPEG_H */ diff --git a/original-kernel-headers/media/msm_media_info.h b/original-kernel-headers/media/msm_media_info.h new file mode 100644 index 0000000..83aa7ee --- /dev/null +++ b/original-kernel-headers/media/msm_media_info.h @@ -0,0 +1,611 @@ +#ifndef __MEDIA_INFO_H__ +#define __MEDIA_INFO_H__ + +#ifndef MSM_MEDIA_ALIGN +#define MSM_MEDIA_ALIGN(__sz, __align) (((__sz) + (__align-1)) & (~(__align-1))) +#endif + +#ifndef MSM_MEDIA_ROUNDUP +#define MSM_MEDIA_ROUNDUP(__sz, __r) (((__sz) + ((__r) - 1)) / (__r)) +#endif + +enum color_fmts { + /* Venus NV12: + * YUV 4:2:0 image with a plane of 8 bit Y samples followed + * by an interleaved U/V plane containing 8 bit 2x2 subsampled + * colour difference samples. + * + * <-------- Y/UV_Stride --------> + * <------- Width -------> + * Y Y Y Y Y Y Y Y Y Y Y Y . . . . ^ ^ + * Y Y Y Y Y Y Y Y Y Y Y Y . . . . | | + * Y Y Y Y Y Y Y Y Y Y Y Y . . . . Height | + * Y Y Y Y Y Y Y Y Y Y Y Y . . . . | Y_Scanlines + * Y Y Y Y Y Y Y Y Y Y Y Y . . . . | | + * Y Y Y Y Y Y Y Y Y Y Y Y . . . . | | + * Y Y Y Y Y Y Y Y Y Y Y Y . . . . | | + * Y Y Y Y Y Y Y Y Y Y Y Y . . . . V | + * . . . . . . . . . . . . . . . . | + * . . . . . . . . . . . . . . . . | + * . . . . . . . . . . . . . . . . | + * . . . . . . . . . . . . . . . . V + * U V U V U V U V U V U V . . . . ^ + * U V U V U V U V U V U V . . . . | + * U V U V U V U V U V U V . . . . | + * U V U V U V U V U V U V . . . . UV_Scanlines + * . . . . . . . . . . . . . . . . | + * . . . . . . . . . . . . . . . . V + * . . . . . . . . . . . . . . . . --> Buffer size alignment + * + * Y_Stride : Width aligned to 128 + * UV_Stride : Width aligned to 128 + * Y_Scanlines: Height aligned to 32 + * UV_Scanlines: Height/2 aligned to 16 + * Extradata: Arbitrary (software-imposed) padding + * Total size = align((Y_Stride * Y_Scanlines + * + UV_Stride * UV_Scanlines + Extradata), 4096) + */ + COLOR_FMT_NV12, + + /* Venus NV21: + * YUV 4:2:0 image with a plane of 8 bit Y samples followed + * by an interleaved V/U plane containing 8 bit 2x2 subsampled + * colour difference samples. + * + * <-------- Y/UV_Stride --------> + * <------- Width -------> + * Y Y Y Y Y Y Y Y Y Y Y Y . . . . ^ ^ + * Y Y Y Y Y Y Y Y Y Y Y Y . . . . | | + * Y Y Y Y Y Y Y Y Y Y Y Y . . . . Height | + * Y Y Y Y Y Y Y Y Y Y Y Y . . . . | Y_Scanlines + * Y Y Y Y Y Y Y Y Y Y Y Y . . . . | | + * Y Y Y Y Y Y Y Y Y Y Y Y . . . . | | + * Y Y Y Y Y Y Y Y Y Y Y Y . . . . | | + * Y Y Y Y Y Y Y Y Y Y Y Y . . . . V | + * . . . . . . . . . . . . . . . . | + * . . . . . . . . . . . . . . . . | + * . . . . . . . . . . . . . . . . | + * . . . . . . . . . . . . . . . . V + * V U V U V U V U V U V U . . . . ^ + * V U V U V U V U V U V U . . . . | + * V U V U V U V U V U V U . . . . | + * V U V U V U V U V U V U . . . . UV_Scanlines + * . . . . . . . . . . . . . . . . | + * . . . . . . . . . . . . . . . . V + * . . . . . . . . . . . . . . . . --> Padding & Buffer size alignment + * + * Y_Stride : Width aligned to 128 + * UV_Stride : Width aligned to 128 + * Y_Scanlines: Height aligned to 32 + * UV_Scanlines: Height/2 aligned to 16 + * Extradata: Arbitrary (software-imposed) padding + * Total size = align((Y_Stride * Y_Scanlines + * + UV_Stride * UV_Scanlines + Extradata), 4096) + */ + COLOR_FMT_NV21, + /* Venus NV12_MVTB: + * Two YUV 4:2:0 images/views one after the other + * in a top-bottom layout, same as NV12 + * with a plane of 8 bit Y samples followed + * by an interleaved U/V plane containing 8 bit 2x2 subsampled + * colour difference samples. + * + * + * <-------- Y/UV_Stride --------> + * <------- Width -------> + * Y Y Y Y Y Y Y Y Y Y Y Y . . . . ^ ^ ^ + * Y Y Y Y Y Y Y Y Y Y Y Y . . . . | | | + * Y Y Y Y Y Y Y Y Y Y Y Y . . . . Height | | + * Y Y Y Y Y Y Y Y Y Y Y Y . . . . | Y_Scanlines | + * Y Y Y Y Y Y Y Y Y Y Y Y . . . . | | | + * Y Y Y Y Y Y Y Y Y Y Y Y . . . . | | | + * Y Y Y Y Y Y Y Y Y Y Y Y . . . . | | | + * Y Y Y Y Y Y Y Y Y Y Y Y . . . . V | | + * . . . . . . . . . . . . . . . . | View_1 + * . . . . . . . . . . . . . . . . | | + * . . . . . . . . . . . . . . . . | | + * . . . . . . . . . . . . . . . . V | + * U V U V U V U V U V U V . . . . ^ | + * U V U V U V U V U V U V . . . . | | + * U V U V U V U V U V U V . . . . | | + * U V U V U V U V U V U V . . . . UV_Scanlines | + * . . . . . . . . . . . . . . . . | | + * . . . . . . . . . . . . . . . . V V + * Y Y Y Y Y Y Y Y Y Y Y Y . . . . ^ ^ ^ + * Y Y Y Y Y Y Y Y Y Y Y Y . . . . | | | + * Y Y Y Y Y Y Y Y Y Y Y Y . . . . Height | | + * Y Y Y Y Y Y Y Y Y Y Y Y . . . . | Y_Scanlines | + * Y Y Y Y Y Y Y Y Y Y Y Y . . . . | | | + * Y Y Y Y Y Y Y Y Y Y Y Y . . . . | | | + * Y Y Y Y Y Y Y Y Y Y Y Y . . . . | | | + * Y Y Y Y Y Y Y Y Y Y Y Y . . . . V | | + * . . . . . . . . . . . . . . . . | View_2 + * . . . . . . . . . . . . . . . . | | + * . . . . . . . . . . . . . . . . | | + * . . . . . . . . . . . . . . . . V | + * U V U V U V U V U V U V . . . . ^ | + * U V U V U V U V U V U V . . . . | | + * U V U V U V U V U V U V . . . . | | + * U V U V U V U V U V U V . . . . UV_Scanlines | + * . . . . . . . . . . . . . . . . | | + * . . . . . . . . . . . . . . . . V V + * . . . . . . . . . . . . . . . . --> Buffer size alignment + * + * Y_Stride : Width aligned to 128 + * UV_Stride : Width aligned to 128 + * Y_Scanlines: Height aligned to 32 + * UV_Scanlines: Height/2 aligned to 16 + * View_1 begin at: 0 (zero) + * View_2 begin at: Y_Stride * Y_Scanlines + UV_Stride * UV_Scanlines + * Extradata: Arbitrary (software-imposed) padding + * Total size = align((2*(Y_Stride * Y_Scanlines) + * + 2*(UV_Stride * UV_Scanlines) + Extradata), 4096) + */ + COLOR_FMT_NV12_MVTB, + /* Venus NV12 UBWC: + * Compressed Macro-tile format for NV12. + * Contains 4 planes in the following order - + * (A) Y_Meta_Plane + * (B) Y_UBWC_Plane + * (C) UV_Meta_Plane + * (D) UV_UBWC_Plane + * + * Y_Meta_Plane consists of meta information to decode compressed + * tile data in Y_UBWC_Plane. + * Y_UBWC_Plane consists of Y data in compressed macro-tile format. + * UBWC decoder block will use the Y_Meta_Plane data together with + * Y_UBWC_Plane data to produce loss-less uncompressed 8 bit Y samples. + * + * UV_Meta_Plane consists of meta information to decode compressed + * tile data in UV_UBWC_Plane. + * UV_UBWC_Plane consists of UV data in compressed macro-tile format. + * UBWC decoder block will use UV_Meta_Plane data together with + * UV_UBWC_Plane data to produce loss-less uncompressed 8 bit 2x2 + * subsampled color difference samples. + * + * Each tile in Y_UBWC_Plane/UV_UBWC_Plane is independently decodable + * and randomly accessible. There is no dependency between tiles. + * + * <----- Y_Meta_Stride ----> + * <-------- Width ------> + * M M M M M M M M M M M M . . ^ ^ + * M M M M M M M M M M M M . . | | + * M M M M M M M M M M M M . . Height | + * M M M M M M M M M M M M . . | Meta_Y_Scanlines + * M M M M M M M M M M M M . . | | + * M M M M M M M M M M M M . . | | + * M M M M M M M M M M M M . . | | + * M M M M M M M M M M M M . . V | + * . . . . . . . . . . . . . . | + * . . . . . . . . . . . . . . | + * . . . . . . . . . . . . . . -------> Buffer size aligned to 4k + * . . . . . . . . . . . . . . V + * <--Compressed tile Y Stride---> + * <------- Width -------> + * Y* Y* Y* Y* Y* Y* Y* Y* . . . . ^ ^ + * Y* Y* Y* Y* Y* Y* Y* Y* . . . . | | + * Y* Y* Y* Y* Y* Y* Y* Y* . . . . Height | + * Y* Y* Y* Y* Y* Y* Y* Y* . . . . | Macro_tile_Y_Scanlines + * Y* Y* Y* Y* Y* Y* Y* Y* . . . . | | + * Y* Y* Y* Y* Y* Y* Y* Y* . . . . | | + * Y* Y* Y* Y* Y* Y* Y* Y* . . . . | | + * Y* Y* Y* Y* Y* Y* Y* Y* . . . . V | + * . . . . . . . . . . . . . . . . | + * . . . . . . . . . . . . . . . . | + * . . . . . . . . . . . . . . . . -------> Buffer size aligned to 4k + * . . . . . . . . . . . . . . . . V + * <----- UV_Meta_Stride ----> + * M M M M M M M M M M M M . . ^ + * M M M M M M M M M M M M . . | + * M M M M M M M M M M M M . . | + * M M M M M M M M M M M M . . M_UV_Scanlines + * . . . . . . . . . . . . . . | + * . . . . . . . . . . . . . . V + * . . . . . . . . . . . . . . -------> Buffer size aligned to 4k + * <--Compressed tile UV Stride---> + * U* V* U* V* U* V* U* V* . . . . ^ + * U* V* U* V* U* V* U* V* . . . . | + * U* V* U* V* U* V* U* V* . . . . | + * U* V* U* V* U* V* U* V* . . . . UV_Scanlines + * . . . . . . . . . . . . . . . . | + * . . . . . . . . . . . . . . . . V + * . . . . . . . . . . . . . . . . -------> Buffer size aligned to 4k + * + * Y_Stride = align(Width, 128) + * UV_Stride = align(Width, 128) + * Y_Scanlines = align(Height, 32) + * UV_Scanlines = align(Height/2, 16) + * Y_UBWC_Plane_size = align(Y_Stride * Y_Scanlines, 4096) + * UV_UBWC_Plane_size = align(UV_Stride * UV_Scanlines, 4096) + * Y_Meta_Stride = align(roundup(Width, Y_TileWidth), 64) + * Y_Meta_Scanlines = align(roundup(Height, Y_TileHeight), 16) + * Y_Meta_Plane_size = align(Y_Meta_Stride * Y_Meta_Scanlines, 4096) + * UV_Meta_Stride = align(roundup(Width, UV_TileWidth), 64) + * UV_Meta_Scanlines = align(roundup(Height, UV_TileHeight), 16) + * UV_Meta_Plane_size = align(UV_Meta_Stride * UV_Meta_Scanlines, 4096) + * Extradata = 8k + * + * Total size = align( Y_UBWC_Plane_size + UV_UBWC_Plane_size + + * Y_Meta_Plane_size + UV_Meta_Plane_size + Extradata, 4096) + */ + COLOR_FMT_NV12_UBWC, + /* Venus NV12 10-bit UBWC: + * Compressed Macro-tile format for NV12. + * Contains 4 planes in the following order - + * (A) Y_Meta_Plane + * (B) Y_UBWC_Plane + * (C) UV_Meta_Plane + * (D) UV_UBWC_Plane + * + * Y_Meta_Plane consists of meta information to decode compressed + * tile data in Y_UBWC_Plane. + * Y_UBWC_Plane consists of Y data in compressed macro-tile format. + * UBWC decoder block will use the Y_Meta_Plane data together with + * Y_UBWC_Plane data to produce loss-less uncompressed 10 bit Y samples. + * + * UV_Meta_Plane consists of meta information to decode compressed + * tile data in UV_UBWC_Plane. + * UV_UBWC_Plane consists of UV data in compressed macro-tile format. + * UBWC decoder block will use UV_Meta_Plane data together with + * UV_UBWC_Plane data to produce loss-less uncompressed 10 bit 2x2 + * subsampled color difference samples. + * + * Each tile in Y_UBWC_Plane/UV_UBWC_Plane is independently decodable + * and randomly accessible. There is no dependency between tiles. + * + * <----- Y_Meta_Stride -----> + * <-------- Width ------> + * M M M M M M M M M M M M . . ^ ^ + * M M M M M M M M M M M M . . | | + * M M M M M M M M M M M M . . Height | + * M M M M M M M M M M M M . . | Meta_Y_Scanlines + * M M M M M M M M M M M M . . | | + * M M M M M M M M M M M M . . | | + * M M M M M M M M M M M M . . | | + * M M M M M M M M M M M M . . V | + * . . . . . . . . . . . . . . | + * . . . . . . . . . . . . . . | + * . . . . . . . . . . . . . . -------> Buffer size aligned to 4k + * . . . . . . . . . . . . . . V + * <--Compressed tile Y Stride---> + * <------- Width -------> + * Y* Y* Y* Y* Y* Y* Y* Y* . . . . ^ ^ + * Y* Y* Y* Y* Y* Y* Y* Y* . . . . | | + * Y* Y* Y* Y* Y* Y* Y* Y* . . . . Height | + * Y* Y* Y* Y* Y* Y* Y* Y* . . . . | Macro_tile_Y_Scanlines + * Y* Y* Y* Y* Y* Y* Y* Y* . . . . | | + * Y* Y* Y* Y* Y* Y* Y* Y* . . . . | | + * Y* Y* Y* Y* Y* Y* Y* Y* . . . . | | + * Y* Y* Y* Y* Y* Y* Y* Y* . . . . V | + * . . . . . . . . . . . . . . . . | + * . . . . . . . . . . . . . . . . | + * . . . . . . . . . . . . . . . . -------> Buffer size aligned to 4k + * . . . . . . . . . . . . . . . . V + * <----- UV_Meta_Stride ----> + * M M M M M M M M M M M M . . ^ + * M M M M M M M M M M M M . . | + * M M M M M M M M M M M M . . | + * M M M M M M M M M M M M . . M_UV_Scanlines + * . . . . . . . . . . . . . . | + * . . . . . . . . . . . . . . V + * . . . . . . . . . . . . . . -------> Buffer size aligned to 4k + * <--Compressed tile UV Stride---> + * U* V* U* V* U* V* U* V* . . . . ^ + * U* V* U* V* U* V* U* V* . . . . | + * U* V* U* V* U* V* U* V* . . . . | + * U* V* U* V* U* V* U* V* . . . . UV_Scanlines + * . . . . . . . . . . . . . . . . | + * . . . . . . . . . . . . . . . . V + * . . . . . . . . . . . . . . . . -------> Buffer size aligned to 4k + * + * + * Y_Stride = align(Width * 4/3, 128) + * UV_Stride = align(Width * 4/3, 128) + * Y_Scanlines = align(Height, 32) + * UV_Scanlines = align(Height/2, 16) + * Y_UBWC_Plane_Size = align(Y_Stride * Y_Scanlines, 4096) + * UV_UBWC_Plane_Size = align(UV_Stride * UV_Scanlines, 4096) + * Y_Meta_Stride = align(roundup(Width, Y_TileWidth), 64) + * Y_Meta_Scanlines = align(roundup(Height, Y_TileHeight), 16) + * Y_Meta_Plane_size = align(Y_Meta_Stride * Y_Meta_Scanlines, 4096) + * UV_Meta_Stride = align(roundup(Width, UV_TileWidth), 64) + * UV_Meta_Scanlines = align(roundup(Height, UV_TileHeight), 16) + * UV_Meta_Plane_size = align(UV_Meta_Stride * UV_Meta_Scanlines, 4096) + * Extradata = 8k + */ + COLOR_FMT_NV12_BPP10_UBWC, +}; + +static inline unsigned int VENUS_EXTRADATA_SIZE(int width, int height) +{ + (void)height; + (void)width; + + /* + * In the future, calculate the size based on the w/h but just + * hardcode it for now since 8K satisfies all current usecases. + */ + return 8 * 1024; +} + +static inline unsigned int VENUS_Y_STRIDE(int color_fmt, int width) +{ + unsigned int alignment, stride = 0; + if (!width) + goto invalid_input; + + switch (color_fmt) { + case COLOR_FMT_NV21: + case COLOR_FMT_NV12: + case COLOR_FMT_NV12_MVTB: + case COLOR_FMT_NV12_UBWC: + alignment = 128; + stride = MSM_MEDIA_ALIGN(width, alignment); + break; + case COLOR_FMT_NV12_BPP10_UBWC: + alignment = 128; + stride = MSM_MEDIA_ALIGN(width * 4/3, alignment); + break; + default: + break; + } +invalid_input: + return stride; +} + +static inline unsigned int VENUS_UV_STRIDE(int color_fmt, int width) +{ + unsigned int alignment, stride = 0; + if (!width) + goto invalid_input; + + switch (color_fmt) { + case COLOR_FMT_NV21: + case COLOR_FMT_NV12: + case COLOR_FMT_NV12_MVTB: + case COLOR_FMT_NV12_UBWC: + alignment = 128; + stride = MSM_MEDIA_ALIGN(width, alignment); + break; + case COLOR_FMT_NV12_BPP10_UBWC: + alignment = 128; + stride = MSM_MEDIA_ALIGN(width * 4/3, alignment); + break; + default: + break; + } +invalid_input: + return stride; +} + +static inline unsigned int VENUS_Y_SCANLINES(int color_fmt, int height) +{ + unsigned int alignment, sclines = 0; + if (!height) + goto invalid_input; + + switch (color_fmt) { + case COLOR_FMT_NV21: + case COLOR_FMT_NV12: + case COLOR_FMT_NV12_MVTB: + case COLOR_FMT_NV12_UBWC: + case COLOR_FMT_NV12_BPP10_UBWC: + alignment = 32; + sclines = MSM_MEDIA_ALIGN(height, alignment); + break; + default: + break; + } +invalid_input: + return sclines; +} + +static inline unsigned int VENUS_UV_SCANLINES(int color_fmt, int height) +{ + unsigned int alignment, sclines = 0; + if (!height) + goto invalid_input; + + switch (color_fmt) { + case COLOR_FMT_NV21: + case COLOR_FMT_NV12: + case COLOR_FMT_NV12_MVTB: + case COLOR_FMT_NV12_UBWC: + case COLOR_FMT_NV12_BPP10_UBWC: + alignment = 16; + sclines = MSM_MEDIA_ALIGN(((height + 1) >> 1), alignment); + break; + default: + break; + } +invalid_input: + return sclines; +} + +static inline unsigned int VENUS_Y_META_STRIDE(int color_fmt, int width) +{ + int y_tile_width = 0, y_meta_stride = 0; + + if (!width) + goto invalid_input; + + switch (color_fmt) { + case COLOR_FMT_NV12_UBWC: + y_tile_width = 32; + break; + case COLOR_FMT_NV12_BPP10_UBWC: + y_tile_width = 48; + break; + default: + goto invalid_input; + } + + y_meta_stride = MSM_MEDIA_ROUNDUP(width, y_tile_width); + y_meta_stride = MSM_MEDIA_ALIGN(y_meta_stride, 64); + +invalid_input: + return y_meta_stride; +} + +static inline unsigned int VENUS_Y_META_SCANLINES(int color_fmt, int height) +{ + int y_tile_height = 0, y_meta_scanlines = 0; + + if (!height) + goto invalid_input; + + switch (color_fmt) { + case COLOR_FMT_NV12_UBWC: + y_tile_height = 8; + break; + case COLOR_FMT_NV12_BPP10_UBWC: + y_tile_height = 4; + break; + default: + goto invalid_input; + } + + y_meta_scanlines = MSM_MEDIA_ROUNDUP(height, y_tile_height); + y_meta_scanlines = MSM_MEDIA_ALIGN(y_meta_scanlines, 16); + +invalid_input: + return y_meta_scanlines; +} + +static inline unsigned int VENUS_UV_META_STRIDE(int color_fmt, int width) +{ + int uv_tile_width = 0, uv_meta_stride = 0; + + if (!width) + goto invalid_input; + + switch (color_fmt) { + case COLOR_FMT_NV12_UBWC: + uv_tile_width = 16; + break; + case COLOR_FMT_NV12_BPP10_UBWC: + uv_tile_width = 24; + break; + default: + goto invalid_input; + } + + uv_meta_stride = MSM_MEDIA_ROUNDUP(width, uv_tile_width); + uv_meta_stride = MSM_MEDIA_ALIGN(uv_meta_stride, 64); + +invalid_input: + return uv_meta_stride; +} + +static inline unsigned int VENUS_UV_META_SCANLINES(int color_fmt, int height) +{ + int uv_tile_height = 0, uv_meta_scanlines = 0; + + if (!height) + goto invalid_input; + + switch (color_fmt) { + case COLOR_FMT_NV12_UBWC: + uv_tile_height = 8; + break; + case COLOR_FMT_NV12_BPP10_UBWC: + uv_tile_height = 4; + break; + default: + goto invalid_input; + } + + uv_meta_scanlines = MSM_MEDIA_ROUNDUP(height, uv_tile_height); + uv_meta_scanlines = MSM_MEDIA_ALIGN(uv_meta_scanlines, 16); + +invalid_input: + return uv_meta_scanlines; +} + +static inline unsigned int VENUS_BUFFER_SIZE( + int color_fmt, int width, int height) +{ + const unsigned int extra_size = VENUS_EXTRADATA_SIZE(width, height); + unsigned int uv_alignment = 0, size = 0; + unsigned int y_plane, uv_plane, y_stride, + uv_stride, y_sclines, uv_sclines; + unsigned int y_ubwc_plane = 0, uv_ubwc_plane = 0; + unsigned int y_meta_stride = 0, y_meta_scanlines = 0; + unsigned int uv_meta_stride = 0, uv_meta_scanlines = 0; + unsigned int y_meta_plane = 0, uv_meta_plane = 0; + + if (!width || !height) + goto invalid_input; + + y_stride = VENUS_Y_STRIDE(color_fmt, width); + uv_stride = VENUS_UV_STRIDE(color_fmt, width); + y_sclines = VENUS_Y_SCANLINES(color_fmt, height); + uv_sclines = VENUS_UV_SCANLINES(color_fmt, height); + switch (color_fmt) { + case COLOR_FMT_NV21: + case COLOR_FMT_NV12: + uv_alignment = 4096; + y_plane = y_stride * y_sclines; + uv_plane = uv_stride * uv_sclines + uv_alignment; + size = y_plane + uv_plane + extra_size; + size = MSM_MEDIA_ALIGN(size, 4096); + break; + case COLOR_FMT_NV12_MVTB: + uv_alignment = 4096; + y_plane = y_stride * y_sclines; + uv_plane = uv_stride * uv_sclines + uv_alignment; + size = y_plane + uv_plane; + size = 2 * size + extra_size; + size = MSM_MEDIA_ALIGN(size, 4096); + break; + case COLOR_FMT_NV12_UBWC: + case COLOR_FMT_NV12_BPP10_UBWC: + y_ubwc_plane = MSM_MEDIA_ALIGN(y_stride * y_sclines, 4096); + uv_ubwc_plane = MSM_MEDIA_ALIGN(uv_stride * uv_sclines, 4096); + y_meta_stride = VENUS_Y_META_STRIDE(color_fmt, width); + y_meta_scanlines = VENUS_Y_META_SCANLINES(color_fmt, height); + y_meta_plane = MSM_MEDIA_ALIGN( + y_meta_stride * y_meta_scanlines, 4096); + uv_meta_stride = VENUS_UV_META_STRIDE(color_fmt, width); + uv_meta_scanlines = VENUS_UV_META_SCANLINES(color_fmt, height); + uv_meta_plane = MSM_MEDIA_ALIGN(uv_meta_stride * + uv_meta_scanlines, 4096); + + size = y_ubwc_plane + uv_ubwc_plane + y_meta_plane + + uv_meta_plane + extra_size; + size = MSM_MEDIA_ALIGN(size, 4096); + break; + default: + break; + } +invalid_input: + return size; +} + +static inline unsigned int VENUS_VIEW2_OFFSET( + int color_fmt, int width, int height) +{ + unsigned int offset = 0; + unsigned int y_plane, uv_plane, y_stride, + uv_stride, y_sclines, uv_sclines; + if (!width || !height) + goto invalid_input; + + y_stride = VENUS_Y_STRIDE(color_fmt, width); + uv_stride = VENUS_UV_STRIDE(color_fmt, width); + y_sclines = VENUS_Y_SCANLINES(color_fmt, height); + uv_sclines = VENUS_UV_SCANLINES(color_fmt, height); + switch (color_fmt) { + case COLOR_FMT_NV12_MVTB: + y_plane = y_stride * y_sclines; + uv_plane = uv_stride * uv_sclines; + offset = y_plane + uv_plane; + break; + default: + break; + } +invalid_input: + return offset; +} + +#endif diff --git a/original-kernel-headers/media/msm_vidc.h b/original-kernel-headers/media/msm_vidc.h new file mode 100644 index 0000000..6fa53ad --- /dev/null +++ b/original-kernel-headers/media/msm_vidc.h @@ -0,0 +1,154 @@ +#ifndef __MSM_VIDC_H__ +#define __MSM_VIDC_H__ + +#include <linux/types.h> + +struct msm_vidc_extradata_header { + unsigned int size; + unsigned int:32; /** Keeping binary compatibility */ + unsigned int:32; /* with firmware and OpenMAX IL **/ + unsigned int type; /* msm_vidc_extradata_type */ + unsigned int data_size; + unsigned char data[1]; +}; +struct msm_vidc_interlace_payload { + unsigned int format; +}; +struct msm_vidc_framerate_payload { + unsigned int frame_rate; +}; +struct msm_vidc_ts_payload { + unsigned int timestamp_lo; + unsigned int timestamp_hi; +}; +struct msm_vidc_concealmb_payload { + unsigned int num_mbs; +}; +struct msm_vidc_recoverysei_payload { + unsigned int flags; +}; +struct msm_vidc_aspect_ratio_payload { + unsigned int size; + unsigned int version; + unsigned int port_index; + unsigned int aspect_width; + unsigned int aspect_height; +}; +struct msm_vidc_mpeg2_seqdisp_payload { + unsigned int video_format; + unsigned int color_descp; + unsigned int color_primaries; + unsigned int transfer_char; + unsigned int matrix_coeffs; + unsigned int disp_width; + unsigned int disp_height; +}; +struct msm_vidc_input_crop_payload { + unsigned int size; + unsigned int version; + unsigned int port_index; + unsigned int left; + unsigned int top; + unsigned int width; + unsigned int height; +}; +struct msm_vidc_digital_zoom_payload { + unsigned int size; + unsigned int version; + unsigned int port_index; + unsigned int zoom_width; + unsigned int zoom_height; +}; +struct msm_vidc_extradata_index { + unsigned int type; + union { + struct msm_vidc_input_crop_payload input_crop; + struct msm_vidc_digital_zoom_payload digital_zoom; + struct msm_vidc_aspect_ratio_payload aspect_ratio; + }; +}; +struct msm_vidc_panscan_window { + unsigned int panscan_height_offset; + unsigned int panscan_width_offset; + unsigned int panscan_window_width; + unsigned int panscan_window_height; +}; +struct msm_vidc_panscan_window_payload { + unsigned int num_panscan_windows; + struct msm_vidc_panscan_window wnd[1]; +}; +struct msm_vidc_stream_userdata_payload { + unsigned int type; + unsigned int data[1]; +}; +struct msm_vidc_frame_qp_payload { + unsigned int frame_qp; +}; +struct msm_vidc_frame_bits_info_payload { + unsigned int frame_bits; + unsigned int header_bits; +}; +struct msm_vidc_s3d_frame_packing_payload { + unsigned int fpa_id; + unsigned int cancel_flag; + unsigned int fpa_type; + unsigned int quin_cunx_flag; + unsigned int content_interprtation_type; + unsigned int spatial_flipping_flag; + unsigned int frame0_flipped_flag; + unsigned int field_views_flag; + unsigned int current_frame_is_frame0_flag; + unsigned int frame0_self_contained_flag; + unsigned int frame1_self_contained_flag; + unsigned int frame0_graid_pos_x; + unsigned int frame0_graid_pos_y; + unsigned int frame1_graid_pos_x; + unsigned int frame1_graid_pos_y; + unsigned int fpa_reserved_byte; + unsigned int fpa_repetition_period; + unsigned int fpa_extension_flag; +}; + +enum msm_vidc_extradata_type { + MSM_VIDC_EXTRADATA_NONE = 0x00000000, + MSM_VIDC_EXTRADATA_MB_QUANTIZATION = 0x00000001, + MSM_VIDC_EXTRADATA_INTERLACE_VIDEO = 0x00000002, + MSM_VIDC_EXTRADATA_VC1_FRAMEDISP = 0x00000003, + MSM_VIDC_EXTRADATA_VC1_SEQDISP = 0x00000004, + MSM_VIDC_EXTRADATA_TIMESTAMP = 0x00000005, + MSM_VIDC_EXTRADATA_S3D_FRAME_PACKING = 0x00000006, + MSM_VIDC_EXTRADATA_FRAME_RATE = 0x00000007, + MSM_VIDC_EXTRADATA_PANSCAN_WINDOW = 0x00000008, + MSM_VIDC_EXTRADATA_RECOVERY_POINT_SEI = 0x00000009, + MSM_VIDC_EXTRADATA_MPEG2_SEQDISP = 0x0000000D, + MSM_VIDC_EXTRADATA_STREAM_USERDATA = 0x0000000E, + MSM_VIDC_EXTRADATA_FRAME_QP = 0x0000000F, + MSM_VIDC_EXTRADATA_FRAME_BITS_INFO = 0x00000010, + MSM_VIDC_EXTRADATA_INPUT_CROP = 0x0700000E, + MSM_VIDC_EXTRADATA_DIGITAL_ZOOM = 0x07000010, + MSM_VIDC_EXTRADATA_MULTISLICE_INFO = 0x7F100000, + MSM_VIDC_EXTRADATA_NUM_CONCEALED_MB = 0x7F100001, + MSM_VIDC_EXTRADATA_INDEX = 0x7F100002, + MSM_VIDC_EXTRADATA_ASPECT_RATIO = 0x7F100003, + MSM_VIDC_EXTRADATA_METADATA_LTR = 0x7F100004, + MSM_VIDC_EXTRADATA_METADATA_FILLER = 0x7FE00002, + MSM_VIDC_EXTRADATA_METADATA_MBI = 0x7F100005, +}; +enum msm_vidc_interlace_type { + MSM_VIDC_INTERLACE_FRAME_PROGRESSIVE = 0x01, + MSM_VIDC_INTERLACE_INTERLEAVE_FRAME_TOPFIELDFIRST = 0x02, + MSM_VIDC_INTERLACE_INTERLEAVE_FRAME_BOTTOMFIELDFIRST = 0x04, + MSM_VIDC_INTERLACE_FRAME_TOPFIELDFIRST = 0x08, + MSM_VIDC_INTERLACE_FRAME_BOTTOMFIELDFIRST = 0x10, +}; +enum msm_vidc_recovery_sei { + MSM_VIDC_FRAME_RECONSTRUCTION_INCORRECT = 0x0, + MSM_VIDC_FRAME_RECONSTRUCTION_CORRECT = 0x01, + MSM_VIDC_FRAME_RECONSTRUCTION_APPROXIMATELY_CORRECT = 0x02, +}; +enum msm_vidc_userdata_type { + MSM_VIDC_USERDATA_TYPE_FRAME = 0x1, + MSM_VIDC_USERDATA_TYPE_TOP_FIELD = 0x2, + MSM_VIDC_USERDATA_TYPE_BOTTOM_FIELD = 0x3, +}; +#endif diff --git a/original-kernel-headers/media/msm_vpu.h b/original-kernel-headers/media/msm_vpu.h new file mode 100644 index 0000000..7bcbc4f --- /dev/null +++ b/original-kernel-headers/media/msm_vpu.h @@ -0,0 +1,475 @@ +#ifndef _H_MSM_VPU_H_ +#define _H_MSM_VPU_H_ + +#include <linux/videodev2.h> + +/* + * V 4 L 2 E X T E N S I O N S B Y V P U + */ + +/* + * v4l2_buffer: + * + * VPU uses standard V4L2 buffer flags, and defines some custom + * flags (used in v4l2_buffer.flags field): + * V4L2_QCOM_BUF_FLAG_EOS: buffer flag indicating end of stream + * V4L2_BUF_FLAG_CDS_ENABLE: buffer flag to enable chroma down-sampling + */ +#define V4L2_BUF_FLAG_CDS_ENABLE 0x10000000 + +/* + * VPU uses multi-plane v4l2_buffer in the following manner: + * each plane can be a separate ION buffer, or all planes are from the + * same ION buffer (under this case all planes have the same fd, but different + * offset). + * + * For struct v4l2_plane + * fd: ION fd representing the ION buffer this plane is from + * reserved[0]: offset of this plane from the start of the ION buffer in + * bytes. Needed when all planes are from the same ION buffer. + */ +#define V4L2_PLANE_MEM_OFFSET 0 + +/* + * struct v4l2_format: + * always use v4l2_pix_format_mplane, even when there is only one plane + * + * v4l2_pix_format_mplane: + * + * VPU uses v4l2_pix_format_mplane for pixel format configuration + * The following members of this structure is either extended or changed: + * pixelformat: extended, a few more private formats added + * colorspace: possible values are enum vpu_colorspace + * field: when it is V4L2_FIELD_ALTERNATE, flags from vpu format extension + * specifies which field first. + * reserved[]: VPU format extension. struct v4l2_format_vpu_extension + */ +enum vpu_colorspace { + VPU_CS_MIN = 0, + /* RGB with full range*/ + VPU_CS_RGB_FULL = 1, + /* RGB with limited range*/ + VPU_CS_RGB_LIMITED = 2, + /* REC 601 with full range */ + VPU_CS_REC601_FULL = 3, + /* REC 601 with limited range */ + VPU_CS_REC601_LIMITED = 4, + /* REC 709 with full range */ + VPU_CS_REC709_FULL = 5, + /* REC 709 with limited range */ + VPU_CS_REC709_LIMITED = 6, + /* SMPTE 240 with full range */ + VPU_CS_SMPTE240_FULL = 7, + /* SMPTE 240 with limited range */ + VPU_CS_SMPTE240_LIMITED = 8, + VPU_CS_MAX = 9, +}; + + +#define VPU_FMT_EXT_FLAG_BT 1 /* bottom field first */ +#define VPU_FMT_EXT_FLAG_TB 2 /* top field first */ +#define VPU_FMT_EXT_FLAG_3D 4 /* 3D format */ +struct v4l2_format_vpu_extension { + __u8 flag; + __u8 gap_in_lines; +}; + +/* + * Supported pixel formats: + * + * VPU supported pixel format fourcc codes (use in s_fmt pixelformat field). + * Can be enumerated using VIDIOC_ENUM_FMT + * + * Standard V4L2 formats, defined in videodev2.h : + * + * V4L2_PIX_FMT_RGB24 24 bit RGB-8-8-8 + * V4L2_PIX_FMT_RGB32 32 bit XRGB-8-8-8-8 + * V4L2_PIX_FMT_BGR24 24 bit BGR-8-8-8 + * V4L2_PIX_FMT_BGR32 32 bit BGRX-8-8-8-8 + * + * V4L2_PIX_FMT_NV12 12 bit YUV 4:2:0 semi-planar NV12 + * V4L2_PIX_FMT_NV21 12 bit YUV 4:2:0 semi-planar NV21 + * V4L2_PIX_FMT_YUYV 16 bit YUYV 4:2:2 interleaved + * V4L2_PIX_FMT_YVYU 16 bit YVYU 4:2:2 interleaved + * V4L2_PIX_FMT_UYVY 16 bit UYVY 4:2:2 interleaved + * V4L2_PIX_FMT_VYUY 16 bit VYUY 4:2:2 interleaved + * + * + * Private VPU formats, defined here : + * + * V4L2_PIX_FMT_XRGB2 32 bit XRGB-2-10-10-10 + * V4L2_PIX_FMT_XBGR2 32 bit XBGR-2-10-10-10 + * + * V4L2_PIX_FMT_YUYV10 24 bit YUYV 4:2:2 10 bit per component loose + * V4L2_PIX_FMT_YUV8 24 bit YUV 4:4:4 8 bit per component + * V4L2_PIX_FMT_YUV10 32 bit YUV 4:4:4 10 bit per component loose + * V4L2_PIX_FMT_YUYV10BWC 10 bit YUYV 4:2:2 compressed, for output only + */ +#define V4L2_PIX_FMT_XRGB2 v4l2_fourcc('X', 'R', 'G', '2') +#define V4L2_PIX_FMT_XBGR2 v4l2_fourcc('X', 'B', 'G', '2') +#define V4L2_PIX_FMT_YUYV10 v4l2_fourcc('Y', 'U', 'Y', 'L') +#define V4L2_PIX_FMT_YUV8 v4l2_fourcc('Y', 'U', 'V', '8') +#define V4L2_PIX_FMT_YUV10 v4l2_fourcc('Y', 'U', 'V', 'L') +#define V4L2_PIX_FMT_YUYV10BWC v4l2_fourcc('Y', 'B', 'W', 'C') + +/* + * VIDIOC_S_INPUT/VIDIOC_S_OUTPUT + * + * The single integer passed by these commands specifies port type in the + * lower 16 bits, and pipe bit mask in the higher 16 bits. + */ +/* input / output types */ +#define VPU_INPUT_TYPE_HOST 0 +#define VPU_INPUT_TYPE_VCAP 1 +#define VPU_OUTPUT_TYPE_HOST 0 +#define VPU_OUTPUT_TYPE_DISPLAY 1 + +/* input / output pipe bit fields */ +#define VPU_PIPE_VCAP0 (1 << 16) +#define VPU_PIPE_VCAP1 (1 << 17) +#define VPU_PIPE_DISPLAY0 (1 << 18) +#define VPU_PIPE_DISPLAY1 (1 << 19) +#define VPU_PIPE_DISPLAY2 (1 << 20) +#define VPU_PIPE_DISPLAY3 (1 << 21) + +/* + * V P U E V E N T S : I D s A N D D A T A P A Y L O A D S + */ + +/* + * Event ID: set in type field of struct v4l2_event + * payload: returned in u.data array of struct v4l2_event + * + * + * VPU_EVENT_FLUSH_DONE: Done flushing buffers after VPU_FLUSH_BUFS ioctl + * payload data: enum v4l2_buf_type (buffer type of flushed port) + * + * VPU_EVENT_ACTIVE_REGION_CHANGED: New Active Region Detected + * payload data: struct v4l2_rect (new active region rectangle) + * + * VPU_EVENT_SESSION_TIMESTAMP: New Session timestamp + * payload data: vpu_frame_timestamp_info + * + * VPU_EVENT_SESSION_CREATED: New session has been created + * payload data: int (number of the attached session) + * + * VPU_EVENT_SESSION_FREED: Session is detached and free + * payload data: int (number of the detached session) + * + * VPU_EVENT_SESSION_CLIENT_EXITED: Indicates that clients of current + * session have exited. + * payload data: int (number of all remaining clients for this session) + * + * VPU_EVENT_HW_ERROR: a hardware error occurred in VPU + * payload data: NULL + * + * VPU_EVENT_INVALID_CONFIG: invalid VPU session configuration + * payload data: NULL + * + * VPU_EVENT_FAILED_SESSION_STREAMING: Failed to stream session + * payload data: NULL + */ +#define VPU_PRIVATE_EVENT_BASE (V4L2_EVENT_PRIVATE_START + 6 * 1000) +enum VPU_PRIVATE_EVENT { + VPU_EVENT_START = VPU_PRIVATE_EVENT_BASE, + + VPU_EVENT_FLUSH_DONE = VPU_EVENT_START + 1, + VPU_EVENT_ACTIVE_REGION_CHANGED = VPU_EVENT_START + 2, + VPU_EVENT_SESSION_TIMESTAMP = VPU_EVENT_START + 3, + VPU_EVENT_SESSION_CREATED = VPU_EVENT_START + 4, + VPU_EVENT_SESSION_FREED = VPU_EVENT_START + 5, + VPU_EVENT_SESSION_CLIENT_EXITED = VPU_EVENT_START + 6, + + VPU_EVENT_HW_ERROR = VPU_EVENT_START + 11, + VPU_EVENT_INVALID_CONFIG = VPU_EVENT_START + 12, + VPU_EVENT_FAILED_SESSION_STREAMING = VPU_EVENT_START + 13, + + VPU_EVENT_END +}; + + +/* + * V P U CO N T R O L S : S T R U C T S A N D I D s + * + * Controls are video processing parameters + */ + +/* + * Standard VPU Controls + */ +struct vpu_ctrl_standard { + __u32 enable; /* boolean: 0=disable, else=enable */ + __s32 value; +}; + +struct vpu_ctrl_auto_manual { + __u32 enable; /* boolean: 0=disable, else=enable */ + __u32 auto_mode; /* boolean: 0=manual, else=automatic */ + __s32 value; +}; + +struct vpu_ctrl_range_mapping { + __u32 enable; /* boolean: 0=disable, else=enable */ + __u32 y_range; /* the range mapping set for Y [0, 7] */ + __u32 uv_range; /* the range mapping set for UV [0, 7] */ +}; + +#define VPU_ACTIVE_REGION_N_EXCLUSIONS 1 +struct vpu_ctrl_active_region_param { + __u32 enable; /* boolean: 0=disable, else=enable */ + /* number of exclusion regions */ + __u32 num_exclusions; + /* roi where active region detection is applied */ + struct v4l2_rect detection_region; + /* roi(s) excluded from active region detection*/ + struct v4l2_rect excluded_regions[VPU_ACTIVE_REGION_N_EXCLUSIONS]; +}; + +struct vpu_ctrl_deinterlacing_mode { + __u32 field_polarity; + __u32 mvp_mode; +}; + +struct vpu_ctrl_hqv { + __u32 enable; + /* strength control of all sharpening features [0, 100] */ + __u32 sharpen_strength; + /* strength control of Auto NR feature [0, 100] */ + __u32 auto_nr_strength; +}; + +struct vpu_info_frame_timestamp { + /* presentation timestamp of the frame */ + __u32 pts_low; + __u32 pts_high; + /* qtimer snapshot */ + __u32 qtime_low; + __u32 qtime_high; +}; + +struct vpu_control { + __u32 control_id; + union control_data { + __s32 value; + struct vpu_ctrl_standard standard; + struct vpu_ctrl_auto_manual auto_manual; + struct vpu_ctrl_range_mapping range_mapping; + struct vpu_ctrl_active_region_param active_region_param; + struct v4l2_rect active_region_result; + struct vpu_ctrl_deinterlacing_mode deinterlacing_mode; + struct vpu_ctrl_hqv hqv; + struct vpu_info_frame_timestamp timestamp; + __u8 reserved[124]; + } data; +}; + +/* + * IDs for standard controls (use in control_id field of struct vpu_control) + * + * VPU_CTRL_NOISE_REDUCTION: noise reduction level, data: auto_manual, + * value: [0, 100] (step in increments of 25). + * + * VPU_CTRL_IMAGE_ENHANCEMENT: image enhancement level, data: auto_manual, + * value: [-100, 100] (step in increments of 1). + * + * VPU_CTRL_ANAMORPHIC_SCALING: anamorphic scaling config, data: standard, + * value: [0, 100] (step in increments of 1). + * + * VPU_CTRL_DIRECTIONAL_INTERPOLATION: directional interpolation config + * data: standard, value: [0, 100] (step in increments of 1). + * + * VPU_CTRL_BACKGROUND_COLOR: , data: value, + * value: red[0:7] green[8:15] blue[16:23] alpha[24:31] + * + * VPU_CTRL_RANGE_MAPPING: Y/UV range mapping, data: range_mapping, + * y_range: [0, 7], uv_range: [0, 7] (step in increments of 1). + * + * VPU_CTRL_DEINTERLACING_MODE: deinterlacing mode, data: deinterlacing_mode, + * field_polarity: [0, 2], mvp_mode: [0, 2] (step in increments of 1). + * + * VPU_CTRL_ACTIVE_REGION_PARAM: active region detection parameters (set only) + * data: active_region_param, + * + * VPU_CTRL_ACTIVE_REGION_RESULT: detected active region roi (get only) + * data: active_region_result + * + * VPU_CTRL_PRIORITY: Session priority, data: value, + * value: high 100, normal 50 + * + * VPU_CTRL_CONTENT_PROTECTION: input content protection status, data: value, + * value: secure 1, non-secure 0 + * + * VPU_CTRL_DISPLAY_REFRESH_RATE: display refresh rate (set only) + * data: value (set to __u32 16.16 format) + * + * VPU_CTRL_HQV: hqv block config, data: hqv, + * sharpen_strength: [0, 100] (step in increments of 25), + * auto_nr_strength: [0, 100] (step in increments of 1). + * + * VPU_CTRL_HQV_SHARPEN: , data: value, + * sharpen_strength: [0, 100] (step in increments of 1). + * + * VPU_CTRL_HQV_AUTONR: , data: value, + * auto_nr_strength: [0, 100] (step in increments of 1). + * + * VPU_CTRL_ACE: , data: value + * + * VPU_CTRL_ACE_BRIGHTNESS: , data: value, + * value: [-100, 100] (step in increments of 1). + * + * VPU_CTRL_ACE_CONTRAST: , data: value, + * value: [-100, 100] (step in increments of 1). + * + * VPU_CTRL_2D3D: , data: value, + * value: 1 enabled, 0 disabled + * + * VPU_CTRL_2D3D_DEPTH: , data: value, + * value: [0, 100] (step in increments of 1). + * + * VPU_CTRL_TIMESTAMP_INFO_MODE: timestamp reporting mode, + * data: value specifying how frequent a timestamp reporting info, value + * is in frames + * + * VPU_INFO_TIMESTAMP: timestamp information (get only) + * data: struct vpu_frame_timestamp_info + * + * VPU_CTRL_FRC: enable/disable FRC, data: value, + * value: 1 enable, 0 disable + * + * VPU_CTRL_FRC_MOTION_SMOOTHNESS: , data: value, + * value: [0, 100] (step in increments of 1). + * + * VPU_CTRL_FRC_MOTION_CLEAR: , data: value, + * value: [0, 100] (step in increments of 1). + * + * VPU_CTRL_LATENCY: session latency, data: value in us + * + * VPU_CTRL_LATENCY_MODE: data: value (ultra low, low, etc.) + * + * VPU_INFO_STATISTICS: frames dropped, etc (get only), + * data: reserved + */ +#define VPU_CTRL_ID_MIN 0 + +#define VPU_CTRL_NOISE_REDUCTION 1 +#define VPU_CTRL_IMAGE_ENHANCEMENT 2 +#define VPU_CTRL_ANAMORPHIC_SCALING 3 +#define VPU_CTRL_DIRECTIONAL_INTERPOLATION 4 +#define VPU_CTRL_BACKGROUND_COLOR 5 +#define VPU_CTRL_RANGE_MAPPING 6 +#define VPU_CTRL_DEINTERLACING_MODE 7 +#define VPU_CTRL_ACTIVE_REGION_PARAM 8 +#define VPU_CTRL_ACTIVE_REGION_RESULT 9 +#define VPU_CTRL_PRIORITY 10 +#define VPU_CTRL_CONTENT_PROTECTION 11 +#define VPU_CTRL_DISPLAY_REFRESH_RATE 12 + +#define VPU_CTRL_HQV 20 +#define VPU_CTRL_HQV_SHARPEN 21 +#define VPU_CTRL_HQV_AUTONR 22 +#define VPU_CTRL_ACE 23 +#define VPU_CTRL_ACE_BRIGHTNESS 24 +#define VPU_CTRL_ACE_CONTRAST 25 +#define VPU_CTRL_2D3D 26 +#define VPU_CTRL_2D3D_DEPTH 27 +#define VPU_CTRL_FRC 28 +#define VPU_CTRL_FRC_MOTION_SMOOTHNESS 29 +#define VPU_CTRL_FRC_MOTION_CLEAR 30 + +#define VPU_INFO_TIMESTAMP 35 +#define VPU_CTRL_TIMESTAMP_INFO_MODE 36 +#define VPU_INFO_STATISTICS 37 +#define VPU_CTRL_LATENCY 38 +#define VPU_CTRL_LATENCY_MODE 39 + +#define VPU_CTRL_ID_MAX 40 + + +/* + * Extended VPU Controls (large data payloads) + */ +#define VPU_MAX_EXT_DATA_SIZE 720 +struct vpu_control_extended { + /* + * extended control type + * 0: system + * 1: session + */ + __u32 type; + + /* + * size and ptr of the data to send + * maximum VPU_MAX_EXT_DATA_SIZE bytes + */ + __u32 data_len; + void __user *data_ptr; + + /* + * size and ptr of the buffer to recv data + * maximum VPU_MAX_EXT_DATA_SIZE bytes + */ + __u32 buf_size; + void __user *buf_ptr; +}; + +/* + * Port specific controls + */ +struct vpu_control_port { + __u32 control_id; + __u32 port; /* 0: INPUT, 1: OUTPUT */ + union control_port_data { + __u32 framerate; + } data; +}; + +/* + * IDs for port controls (use in control_id field of struct vpu_control_port) + * + * VPU_CTRL_FPS: set frame rate, data: __u32, 16.16 format + */ +#define VPU_CTRL_FPS 1000 + + +/* + * V P U D E V I C E P R I V A T E I O C T L C O D E S + */ + +/* VPU Session ioctls (deprecated) */ +#define VPU_ATTACH_TO_SESSION _IOW('V', (BASE_VIDIOC_PRIVATE + 1), int) + +/* VPU Session ioctls */ +#define VPU_QUERY_SESSIONS _IOR('V', (BASE_VIDIOC_PRIVATE + 0), int) +#define VPU_CREATE_SESSION _IOR('V', (BASE_VIDIOC_PRIVATE + 2), int) +#define VPU_JOIN_SESSION _IOW('V', (BASE_VIDIOC_PRIVATE + 3), int) + +/* Enable second VPU output port and use with current client */ +#define VPU_CREATE_OUTPUT2 _IO('V', (BASE_VIDIOC_PRIVATE + 5)) + +/* Explicit commit of session configuration */ +#define VPU_COMMIT_CONFIGURATION _IO('V', (BASE_VIDIOC_PRIVATE + 10)) + +/* Flush all buffers of given type (port) */ +#define VPU_FLUSH_BUFS _IOW('V', (BASE_VIDIOC_PRIVATE + 15), \ + enum v4l2_buf_type) + +/* VPU controls get/set ioctls (for most controls with small data) */ +#define VPU_G_CONTROL _IOWR('V', (BASE_VIDIOC_PRIVATE + 20), \ + struct vpu_control) +#define VPU_S_CONTROL _IOW('V', (BASE_VIDIOC_PRIVATE + 21), \ + struct vpu_control) + +/* extended control set/get ioctls (large data payloads) */ +#define VPU_G_CONTROL_EXTENDED _IOWR('V', (BASE_VIDIOC_PRIVATE + 22), \ + struct vpu_control_extended) +#define VPU_S_CONTROL_EXTENDED _IOW('V', (BASE_VIDIOC_PRIVATE + 23), \ + struct vpu_control_extended) + +/* VPU port (input/output) specific controls get/set ioctls */ +#define VPU_G_CONTROL_PORT _IOWR('V', (BASE_VIDIOC_PRIVATE + 24), \ + struct vpu_control_port) +#define VPU_S_CONTROL_PORT _IOW('V', (BASE_VIDIOC_PRIVATE + 25), \ + struct vpu_control_port) + +#endif /* _H_MSM_VPU_H_ */ + diff --git a/original-kernel-headers/media/msmb_camera.h b/original-kernel-headers/media/msmb_camera.h new file mode 100644 index 0000000..d053589 --- /dev/null +++ b/original-kernel-headers/media/msmb_camera.h @@ -0,0 +1,199 @@ +#ifndef __LINUX_MSMB_CAMERA_H +#define __LINUX_MSMB_CAMERA_H + +#include <linux/videodev2.h> +#include <linux/types.h> +#include <linux/ioctl.h> + +#define MSM_CAM_V4L2_IOCTL_NOTIFY \ + _IOW('V', BASE_VIDIOC_PRIVATE + 30, struct msm_v4l2_event_data) + +#define MSM_CAM_V4L2_IOCTL_NOTIFY_META \ + _IOW('V', BASE_VIDIOC_PRIVATE + 31, struct msm_v4l2_event_data) + +#define MSM_CAM_V4L2_IOCTL_CMD_ACK \ + _IOW('V', BASE_VIDIOC_PRIVATE + 32, struct msm_v4l2_event_data) + +#define MSM_CAM_V4L2_IOCTL_NOTIFY_ERROR \ + _IOW('V', BASE_VIDIOC_PRIVATE + 33, struct msm_v4l2_event_data) + + +#ifdef CONFIG_COMPAT +#define MSM_CAM_V4L2_IOCTL_NOTIFY32 \ + _IOW('V', BASE_VIDIOC_PRIVATE + 30, struct v4l2_event32) + +#define MSM_CAM_V4L2_IOCTL_NOTIFY_META32 \ + _IOW('V', BASE_VIDIOC_PRIVATE + 31, struct v4l2_event32) + +#define MSM_CAM_V4L2_IOCTL_CMD_ACK32 \ + _IOW('V', BASE_VIDIOC_PRIVATE + 32, struct v4l2_event32) + +#define MSM_CAM_V4L2_IOCTL_NOTIFY_ERROR32 \ + _IOW('V', BASE_VIDIOC_PRIVATE + 33, struct v4l2_event32) + +#endif + +#define QCAMERA_DEVICE_GROUP_ID 1 +#define QCAMERA_VNODE_GROUP_ID 2 +#define MSM_CAMERA_NAME "msm_camera" +#define MSM_CONFIGURATION_NAME "msm_config" + +#define MSM_CAMERA_SUBDEV_CSIPHY 0 +#define MSM_CAMERA_SUBDEV_CSID 1 +#define MSM_CAMERA_SUBDEV_ISPIF 2 +#define MSM_CAMERA_SUBDEV_VFE 3 +#define MSM_CAMERA_SUBDEV_AXI 4 +#define MSM_CAMERA_SUBDEV_VPE 5 +#define MSM_CAMERA_SUBDEV_SENSOR 6 +#define MSM_CAMERA_SUBDEV_ACTUATOR 7 +#define MSM_CAMERA_SUBDEV_EEPROM 8 +#define MSM_CAMERA_SUBDEV_CPP 9 +#define MSM_CAMERA_SUBDEV_CCI 10 +#define MSM_CAMERA_SUBDEV_LED_FLASH 11 +#define MSM_CAMERA_SUBDEV_STROBE_FLASH 12 +#define MSM_CAMERA_SUBDEV_BUF_MNGR 13 +#define MSM_CAMERA_SUBDEV_SENSOR_INIT 14 +#define MSM_CAMERA_SUBDEV_OIS 15 +#define MSM_CAMERA_SUBDEV_FLASH 16 + +#define MSM_MAX_CAMERA_SENSORS 5 + +/* The below macro is defined to put an upper limit on maximum + * number of buffer requested per stream. In case of extremely + * large value for number of buffer due to data structure corruption + * we return error to avoid integer overflow. This value may be + * configured in future*/ +#define MSM_CAMERA_MAX_STREAM_BUF 40 + +/* featur base */ +#define MSM_CAMERA_FEATURE_BASE 0x00010000 +#define MSM_CAMERA_FEATURE_SHUTDOWN (MSM_CAMERA_FEATURE_BASE + 1) + +#define MSM_CAMERA_STATUS_BASE 0x00020000 +#define MSM_CAMERA_STATUS_FAIL (MSM_CAMERA_STATUS_BASE + 1) +#define MSM_CAMERA_STATUS_SUCCESS (MSM_CAMERA_STATUS_BASE + 2) + +/* event type */ +#define MSM_CAMERA_V4L2_EVENT_TYPE (V4L2_EVENT_PRIVATE_START + 0x00002000) + +/* event id */ +#define MSM_CAMERA_EVENT_MIN 0 +#define MSM_CAMERA_NEW_SESSION (MSM_CAMERA_EVENT_MIN + 1) +#define MSM_CAMERA_DEL_SESSION (MSM_CAMERA_EVENT_MIN + 2) +#define MSM_CAMERA_SET_PARM (MSM_CAMERA_EVENT_MIN + 3) +#define MSM_CAMERA_GET_PARM (MSM_CAMERA_EVENT_MIN + 4) +#define MSM_CAMERA_MAPPING_CFG (MSM_CAMERA_EVENT_MIN + 5) +#define MSM_CAMERA_MAPPING_SES (MSM_CAMERA_EVENT_MIN + 6) +#define MSM_CAMERA_MSM_NOTIFY (MSM_CAMERA_EVENT_MIN + 7) +#define MSM_CAMERA_EVENT_MAX (MSM_CAMERA_EVENT_MIN + 8) + +/* data.command */ +#define MSM_CAMERA_PRIV_S_CROP (V4L2_CID_PRIVATE_BASE + 1) +#define MSM_CAMERA_PRIV_G_CROP (V4L2_CID_PRIVATE_BASE + 2) +#define MSM_CAMERA_PRIV_G_FMT (V4L2_CID_PRIVATE_BASE + 3) +#define MSM_CAMERA_PRIV_S_FMT (V4L2_CID_PRIVATE_BASE + 4) +#define MSM_CAMERA_PRIV_TRY_FMT (V4L2_CID_PRIVATE_BASE + 5) +#define MSM_CAMERA_PRIV_METADATA (V4L2_CID_PRIVATE_BASE + 6) +#define MSM_CAMERA_PRIV_QUERY_CAP (V4L2_CID_PRIVATE_BASE + 7) +#define MSM_CAMERA_PRIV_STREAM_ON (V4L2_CID_PRIVATE_BASE + 8) +#define MSM_CAMERA_PRIV_STREAM_OFF (V4L2_CID_PRIVATE_BASE + 9) +#define MSM_CAMERA_PRIV_NEW_STREAM (V4L2_CID_PRIVATE_BASE + 10) +#define MSM_CAMERA_PRIV_DEL_STREAM (V4L2_CID_PRIVATE_BASE + 11) +#define MSM_CAMERA_PRIV_SHUTDOWN (V4L2_CID_PRIVATE_BASE + 12) +#define MSM_CAMERA_PRIV_STREAM_INFO_SYNC \ + (V4L2_CID_PRIVATE_BASE + 13) + +/* data.status - success */ +#define MSM_CAMERA_CMD_SUCESS 0x00000001 +#define MSM_CAMERA_BUF_MAP_SUCESS 0x00000002 + +/* data.status - error */ +#define MSM_CAMERA_ERR_EVT_BASE 0x00010000 +#define MSM_CAMERA_ERR_CMD_FAIL (MSM_CAMERA_ERR_EVT_BASE + 1) +#define MSM_CAMERA_ERR_MAPPING (MSM_CAMERA_ERR_EVT_BASE + 2) + +/* The msm_v4l2_event_data structure should match the + * v4l2_event.u.data field. + * should not exceed 16 elements */ +struct msm_v4l2_event_data { + /*word 0*/ + unsigned int command; + /*word 1*/ + unsigned int status; + /*word 2*/ + unsigned int session_id; + /*word 3*/ + unsigned int stream_id; + /*word 4*/ + unsigned int map_op; + /*word 5*/ + unsigned int map_buf_idx; + /*word 6*/ + unsigned int notify; + /*word 7*/ + unsigned int arg_value; + /*word 8*/ + unsigned int ret_value; + /*word 9*/ + unsigned int v4l2_event_type; + /*word 10*/ + unsigned int v4l2_event_id; + /*word 11*/ + unsigned int nop5; + /*word 12*/ + unsigned int nop6; + /*word 13*/ + unsigned int nop7; + /*word 14*/ + unsigned int nop8; + /*word 15*/ + unsigned int nop9; +}; + +/* map to v4l2_format.fmt.raw_data */ +struct msm_v4l2_format_data { + enum v4l2_buf_type type; + unsigned int width; + unsigned int height; + unsigned int pixelformat; /* FOURCC */ + unsigned char num_planes; + unsigned int plane_sizes[VIDEO_MAX_PLANES]; +}; + +/* MSM Four-character-code (FOURCC) */ +#define msm_v4l2_fourcc(a, b, c, d)\ + ((__u32)(a) | ((__u32)(b) << 8) | ((__u32)(c) << 16) |\ + ((__u32)(d) << 24)) + +/* Composite stats */ +#define MSM_V4L2_PIX_FMT_STATS_COMB v4l2_fourcc('S', 'T', 'C', 'M') +/* AEC stats */ +#define MSM_V4L2_PIX_FMT_STATS_AE v4l2_fourcc('S', 'T', 'A', 'E') +/* AF stats */ +#define MSM_V4L2_PIX_FMT_STATS_AF v4l2_fourcc('S', 'T', 'A', 'F') +/* AWB stats */ +#define MSM_V4L2_PIX_FMT_STATS_AWB v4l2_fourcc('S', 'T', 'W', 'B') +/* IHIST stats */ +#define MSM_V4L2_PIX_FMT_STATS_IHST v4l2_fourcc('I', 'H', 'S', 'T') +/* Column count stats */ +#define MSM_V4L2_PIX_FMT_STATS_CS v4l2_fourcc('S', 'T', 'C', 'S') +/* Row count stats */ +#define MSM_V4L2_PIX_FMT_STATS_RS v4l2_fourcc('S', 'T', 'R', 'S') +/* Bayer Grid stats */ +#define MSM_V4L2_PIX_FMT_STATS_BG v4l2_fourcc('S', 'T', 'B', 'G') +/* Bayer focus stats */ +#define MSM_V4L2_PIX_FMT_STATS_BF v4l2_fourcc('S', 'T', 'B', 'F') +/* Bayer hist stats */ +#define MSM_V4L2_PIX_FMT_STATS_BHST v4l2_fourcc('B', 'H', 'S', 'T') + +enum smmu_attach_mode { + NON_SECURE_MODE, + SECURE_MODE, + MAX_PROTECTION_MODE, +}; + +struct msm_camera_smmu_attach_type { + enum smmu_attach_mode attach; +}; + +#endif /* __LINUX_MSMB_CAMERA_H */ diff --git a/original-kernel-headers/media/msmb_generic_buf_mgr.h b/original-kernel-headers/media/msmb_generic_buf_mgr.h new file mode 100644 index 0000000..a5823e6 --- /dev/null +++ b/original-kernel-headers/media/msmb_generic_buf_mgr.h @@ -0,0 +1,50 @@ +#ifndef __UAPI_MEDIA_MSMB_BUF_MNGR_H__ +#define __UAPI_MEDIA_MSMB_BUF_MNGR_H__ + +struct msm_buf_mngr_info { + uint32_t session_id; + uint32_t stream_id; + uint32_t frame_id; + struct timeval timestamp; + uint32_t index; + uint32_t reserved; +}; + +struct v4l2_subdev *msm_buf_mngr_get_subdev(void); + +#define VIDIOC_MSM_BUF_MNGR_GET_BUF \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 33, struct msm_buf_mngr_info) + +#define VIDIOC_MSM_BUF_MNGR_PUT_BUF \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 34, struct msm_buf_mngr_info) + +#define VIDIOC_MSM_BUF_MNGR_BUF_DONE \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 35, struct msm_buf_mngr_info) + +#define VIDIOC_MSM_BUF_MNGR_INIT \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 36, struct msm_buf_mngr_info) + +#define VIDIOC_MSM_BUF_MNGR_DEINIT \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 37, struct msm_buf_mngr_info) + +#ifdef CONFIG_COMPAT +struct msm_buf_mngr_info32_t { + uint32_t session_id; + uint32_t stream_id; + uint32_t frame_id; + struct compat_timeval timestamp; + uint32_t index; + uint32_t reserved; +}; + +#define VIDIOC_MSM_BUF_MNGR_GET_BUF32 \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 33, struct msm_buf_mngr_info32_t) + +#define VIDIOC_MSM_BUF_MNGR_PUT_BUF32 \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 34, struct msm_buf_mngr_info32_t) + +#define VIDIOC_MSM_BUF_MNGR_BUF_DONE32 \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 35, struct msm_buf_mngr_info32_t) +#endif + +#endif diff --git a/original-kernel-headers/media/msmb_isp.h b/original-kernel-headers/media/msmb_isp.h new file mode 100644 index 0000000..61eed72 --- /dev/null +++ b/original-kernel-headers/media/msmb_isp.h @@ -0,0 +1,637 @@ +/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#ifndef __MSMB_ISP__ +#define __MSMB_ISP__ + +#include <linux/videodev2.h> + +#define MAX_PLANES_PER_STREAM 3 +#define MAX_NUM_STREAM 7 + +#define ISP_VERSION_47 47 +#define ISP_VERSION_46 46 +#define ISP_VERSION_44 44 +#define ISP_VERSION_40 40 +#define ISP_VERSION_32 32 +#define ISP_NATIVE_BUF_BIT (0x10000 << 0) +#define ISP0_BIT (0x10000 << 1) +#define ISP1_BIT (0x10000 << 2) +#define ISP_META_CHANNEL_BIT (0x10000 << 3) +#define ISP_SCRATCH_BUF_BIT (0x10000 << 4) +#define ISP_STATS_STREAM_BIT 0x80000000 + +struct msm_vfe_cfg_cmd_list; + +enum ISP_START_PIXEL_PATTERN { + ISP_BAYER_RGRGRG, + ISP_BAYER_GRGRGR, + ISP_BAYER_BGBGBG, + ISP_BAYER_GBGBGB, + ISP_YUV_YCbYCr, + ISP_YUV_YCrYCb, + ISP_YUV_CbYCrY, + ISP_YUV_CrYCbY, + ISP_PIX_PATTERN_MAX +}; + +enum msm_vfe_plane_fmt { + Y_PLANE, + CB_PLANE, + CR_PLANE, + CRCB_PLANE, + CBCR_PLANE, + VFE_PLANE_FMT_MAX +}; + +enum msm_vfe_input_src { + VFE_PIX_0, + VFE_RAW_0, + VFE_RAW_1, + VFE_RAW_2, + VFE_SRC_MAX, +}; + +enum msm_vfe_axi_stream_src { + PIX_ENCODER, + PIX_VIEWFINDER, + PIX_VIDEO, + CAMIF_RAW, + IDEAL_RAW, + RDI_INTF_0, + RDI_INTF_1, + RDI_INTF_2, + VFE_AXI_SRC_MAX +}; + +enum msm_vfe_frame_skip_pattern { + NO_SKIP, + EVERY_2FRAME, + EVERY_3FRAME, + EVERY_4FRAME, + EVERY_5FRAME, + EVERY_6FRAME, + EVERY_7FRAME, + EVERY_8FRAME, + EVERY_16FRAME, + EVERY_32FRAME, + SKIP_ALL, + SKIP_RANGE, + MAX_SKIP, +}; + +enum msm_isp_stats_type { + MSM_ISP_STATS_AEC, /* legacy based AEC */ + MSM_ISP_STATS_AF, /* legacy based AF */ + MSM_ISP_STATS_AWB, /* legacy based AWB */ + MSM_ISP_STATS_RS, /* legacy based RS */ + MSM_ISP_STATS_CS, /* legacy based CS */ + MSM_ISP_STATS_IHIST, /* legacy based HIST */ + MSM_ISP_STATS_SKIN, /* legacy based SKIN */ + MSM_ISP_STATS_BG, /* Bayer Grids */ + MSM_ISP_STATS_BF, /* Bayer Focus */ + MSM_ISP_STATS_BE, /* Bayer Exposure*/ + MSM_ISP_STATS_BHIST, /* Bayer Hist */ + MSM_ISP_STATS_BF_SCALE, /* Bayer Focus scale */ + MSM_ISP_STATS_HDR_BE, /* HDR Bayer Exposure */ + MSM_ISP_STATS_HDR_BHIST, /* HDR Bayer Hist */ + MSM_ISP_STATS_MAX /* MAX */ +}; + +/* + * @stats_type_mask: Stats type mask (enum msm_isp_stats_type). + * @stream_src_mask: Stream src mask (enum msm_vfe_axi_stream_src) + * @skip_mode: skip pattern, if skip mode is range only then min/max is used + * @min_frame_id: minimum frame id (valid only if skip_mode = RANGE) + * @max_frame_id: maximum frame id (valid only if skip_mode = RANGE) +*/ +struct msm_isp_sw_framskip { + uint32_t stats_type_mask; + uint32_t stream_src_mask; + enum msm_vfe_frame_skip_pattern skip_mode; + uint32_t min_frame_id; + uint32_t max_frame_id; +}; + +enum msm_vfe_testgen_color_pattern { + COLOR_BAR_8_COLOR, + UNICOLOR_WHITE, + UNICOLOR_YELLOW, + UNICOLOR_CYAN, + UNICOLOR_GREEN, + UNICOLOR_MAGENTA, + UNICOLOR_RED, + UNICOLOR_BLUE, + UNICOLOR_BLACK, + MAX_COLOR, +}; + +enum msm_vfe_camif_input { + CAMIF_DISABLED, + CAMIF_PAD_REG_INPUT, + CAMIF_MIDDI_INPUT, + CAMIF_MIPI_INPUT, +}; + +struct msm_vfe_fetch_engine_cfg { + uint32_t input_format; + uint32_t buf_width; + uint32_t buf_height; + uint32_t fetch_width; + uint32_t fetch_height; + uint32_t x_offset; + uint32_t y_offset; + uint32_t buf_stride; +}; + +struct msm_vfe_camif_cfg { + uint32_t lines_per_frame; + uint32_t pixels_per_line; + uint32_t first_pixel; + uint32_t last_pixel; + uint32_t first_line; + uint32_t last_line; + uint32_t epoch_line0; + uint32_t epoch_line1; + enum msm_vfe_camif_input camif_input; +}; + +struct msm_vfe_testgen_cfg { + uint32_t lines_per_frame; + uint32_t pixels_per_line; + uint32_t v_blank; + uint32_t h_blank; + enum ISP_START_PIXEL_PATTERN pixel_bayer_pattern; + uint32_t rotate_period; + enum msm_vfe_testgen_color_pattern color_bar_pattern; + uint32_t burst_num_frame; +}; + +enum msm_vfe_inputmux { + CAMIF, + TESTGEN, + EXTERNAL_READ, +}; + +enum msm_vfe_stats_composite_group { + STATS_COMPOSITE_GRP_NONE, + STATS_COMPOSITE_GRP_1, + STATS_COMPOSITE_GRP_2, + STATS_COMPOSITE_GRP_MAX, +}; + +struct msm_vfe_pix_cfg { + struct msm_vfe_camif_cfg camif_cfg; + struct msm_vfe_testgen_cfg testgen_cfg; + struct msm_vfe_fetch_engine_cfg fetch_engine_cfg; + enum msm_vfe_inputmux input_mux; + enum ISP_START_PIXEL_PATTERN pixel_pattern; + uint32_t input_format; +}; + +struct msm_vfe_rdi_cfg { + uint8_t cid; + uint8_t frame_based; +}; + +struct msm_vfe_input_cfg { + union { + struct msm_vfe_pix_cfg pix_cfg; + struct msm_vfe_rdi_cfg rdi_cfg; + } d; + enum msm_vfe_input_src input_src; + uint32_t input_pix_clk; +}; + +struct msm_vfe_fetch_eng_start { + uint32_t session_id; + uint32_t stream_id; + uint32_t buf_idx; + uint32_t buf_addr; +}; + +struct msm_vfe_axi_plane_cfg { + uint32_t output_width; /*Include padding*/ + uint32_t output_height; + uint32_t output_stride; + uint32_t output_scan_lines; + uint32_t output_plane_format; /*Y/Cb/Cr/CbCr*/ + uint32_t plane_addr_offset; + uint8_t csid_src; /*RDI 0-2*/ + uint8_t rdi_cid;/*CID 1-16*/ +}; + +enum msm_stream_memory_input_t { + MEMORY_INPUT_DISABLED, + MEMORY_INPUT_ENABLED +}; + +struct msm_vfe_axi_stream_request_cmd { + uint32_t session_id; + uint32_t stream_id; + uint32_t vt_enable; + uint32_t output_format;/*Planar/RAW/Misc*/ + enum msm_vfe_axi_stream_src stream_src; /*CAMIF/IDEAL/RDIs*/ + struct msm_vfe_axi_plane_cfg plane_cfg[MAX_PLANES_PER_STREAM]; + + uint32_t burst_count; + uint32_t hfr_mode; + uint8_t frame_base; + + uint32_t init_frame_drop; /*MAX 31 Frames*/ + enum msm_vfe_frame_skip_pattern frame_skip_pattern; + uint8_t buf_divert; /* if TRUE no vb2 buf done. */ + /*Return values*/ + uint32_t axi_stream_handle; + uint32_t controllable_output; + uint32_t burst_len; + /* Flag indicating memory input stream */ + enum msm_stream_memory_input_t memory_input; +}; + +struct msm_vfe_axi_stream_release_cmd { + uint32_t stream_handle; +}; + +enum msm_vfe_axi_stream_cmd { + STOP_STREAM, + START_STREAM, + STOP_IMMEDIATELY, +}; + +struct msm_vfe_axi_stream_cfg_cmd { + uint8_t num_streams; + uint32_t stream_handle[MAX_NUM_STREAM]; + enum msm_vfe_axi_stream_cmd cmd; +}; + +enum msm_vfe_axi_stream_update_type { + ENABLE_STREAM_BUF_DIVERT, + DISABLE_STREAM_BUF_DIVERT, + UPDATE_STREAM_FRAMEDROP_PATTERN, + UPDATE_STREAM_STATS_FRAMEDROP_PATTERN, + UPDATE_STREAM_AXI_CONFIG, + UPDATE_STREAM_REQUEST_FRAMES, + UPDATE_STREAM_ADD_BUFQ, + UPDATE_STREAM_REMOVE_BUFQ, + UPDATE_STREAM_SW_FRAME_DROP, +}; + +enum msm_vfe_iommu_type { + IOMMU_ATTACH, + IOMMU_DETACH, +}; + +enum msm_vfe_buff_queue_id { + VFE_BUF_QUEUE_DEFAULT, + VFE_BUF_QUEUE_SHARED, + VFE_BUF_QUEUE_MAX, +}; + +struct msm_vfe_axi_stream_cfg_update_info { + uint32_t stream_handle; + uint32_t output_format; + uint32_t user_stream_id; + enum msm_vfe_frame_skip_pattern skip_pattern; + struct msm_vfe_axi_plane_cfg plane_cfg[MAX_PLANES_PER_STREAM]; + struct msm_isp_sw_framskip sw_skip_info; +}; + +struct msm_vfe_axi_halt_cmd { + uint32_t stop_camif; + uint32_t overflow_detected; +}; + +struct msm_vfe_axi_reset_cmd { + uint32_t blocking; + uint32_t frame_id; +}; + +struct msm_vfe_axi_restart_cmd { + uint32_t enable_camif; +}; + +struct msm_vfe_axi_stream_update_cmd { + uint32_t num_streams; + enum msm_vfe_axi_stream_update_type update_type; + struct msm_vfe_axi_stream_cfg_update_info + update_info[MSM_ISP_STATS_MAX]; +}; + +struct msm_vfe_smmu_attach_cmd { + uint32_t security_mode; + uint32_t iommu_attach_mode; +}; + +struct msm_vfe_stats_stream_request_cmd { + uint32_t session_id; + uint32_t stream_id; + enum msm_isp_stats_type stats_type; + uint32_t composite_flag; + uint32_t framedrop_pattern; + uint32_t init_frame_drop; /*MAX 31 Frames*/ + uint32_t irq_subsample_pattern; + uint32_t buffer_offset; + uint32_t stream_handle; +}; + +struct msm_vfe_stats_stream_release_cmd { + uint32_t stream_handle; +}; +struct msm_vfe_stats_stream_cfg_cmd { + uint8_t num_streams; + uint32_t stream_handle[MSM_ISP_STATS_MAX]; + uint8_t enable; + uint32_t stats_burst_len; +}; + +enum msm_vfe_reg_cfg_type { + VFE_WRITE, + VFE_WRITE_MB, + VFE_READ, + VFE_CFG_MASK, + VFE_WRITE_DMI_16BIT, + VFE_WRITE_DMI_32BIT, + VFE_WRITE_DMI_64BIT, + VFE_READ_DMI_16BIT, + VFE_READ_DMI_32BIT, + VFE_READ_DMI_64BIT, + GET_MAX_CLK_RATE, + GET_CLK_RATES, + GET_ISP_ID, + VFE_HW_UPDATE_LOCK, + VFE_HW_UPDATE_UNLOCK, + SET_WM_UB_SIZE, + SET_UB_POLICY, +}; + +struct msm_vfe_cfg_cmd2 { + uint16_t num_cfg; + uint16_t cmd_len; + void __user *cfg_data; + void __user *cfg_cmd; +}; + +struct msm_vfe_cfg_cmd_list { + struct msm_vfe_cfg_cmd2 cfg_cmd; + struct msm_vfe_cfg_cmd_list *next; + uint32_t next_size; +}; + +struct msm_vfe_reg_rw_info { + uint32_t reg_offset; + uint32_t cmd_data_offset; + uint32_t len; +}; + +struct msm_vfe_reg_mask_info { + uint32_t reg_offset; + uint32_t mask; + uint32_t val; +}; + +struct msm_vfe_reg_dmi_info { + uint32_t hi_tbl_offset; /*Optional*/ + uint32_t lo_tbl_offset; /*Required*/ + uint32_t len; +}; + +struct msm_vfe_reg_cfg_cmd { + union { + struct msm_vfe_reg_rw_info rw_info; + struct msm_vfe_reg_mask_info mask_info; + struct msm_vfe_reg_dmi_info dmi_info; + } u; + + enum msm_vfe_reg_cfg_type cmd_type; +}; + +enum msm_isp_buf_type { + ISP_PRIVATE_BUF, + ISP_SHARE_BUF, + MAX_ISP_BUF_TYPE, +}; + +struct msm_isp_buf_request { + uint32_t session_id; + uint32_t stream_id; + uint8_t num_buf; + uint32_t handle; + enum msm_isp_buf_type buf_type; +}; + +struct msm_isp_qbuf_plane { + uint32_t addr; + uint32_t offset; + uint32_t length; +}; + +struct msm_isp_qbuf_buffer { + struct msm_isp_qbuf_plane planes[MAX_PLANES_PER_STREAM]; + uint32_t num_planes; +}; + +struct msm_isp_qbuf_info { + uint32_t handle; + int32_t buf_idx; + /*Only used for prepare buffer*/ + struct msm_isp_qbuf_buffer buffer; + /*Only used for diverted buffer*/ + uint32_t dirty_buf; +}; + +struct msm_isp_clk_rates { + uint32_t nominal_rate; + uint32_t high_rate; +}; + +struct msm_vfe_axi_src_state { + enum msm_vfe_input_src input_src; + uint32_t src_active; + uint32_t src_frame_id; +}; + +enum msm_isp_event_idx { + ISP_REG_UPDATE = 0, + ISP_EPOCH_0 = 1, + ISP_EPOCH_1 = 2, + ISP_START_ACK = 3, + ISP_STOP_ACK = 4, + ISP_IRQ_VIOLATION = 5, + ISP_WM_BUS_OVERFLOW = 6, + ISP_STATS_OVERFLOW = 7, + ISP_CAMIF_ERROR = 8, + ISP_BUF_DONE = 9, + ISP_FE_RD_DONE = 10, + ISP_EVENT_MAX = 11 +}; + +#define ISP_EVENT_OFFSET 8 +#define ISP_EVENT_BASE (V4L2_EVENT_PRIVATE_START) +#define ISP_BUF_EVENT_BASE (ISP_EVENT_BASE + (1 << ISP_EVENT_OFFSET)) +#define ISP_STATS_EVENT_BASE (ISP_EVENT_BASE + (2 << ISP_EVENT_OFFSET)) +#define ISP_CAMIF_EVENT_BASE (ISP_EVENT_BASE + (3 << ISP_EVENT_OFFSET)) +#define ISP_STREAM_EVENT_BASE (ISP_EVENT_BASE + (4 << ISP_EVENT_OFFSET)) +#define ISP_EVENT_REG_UPDATE (ISP_EVENT_BASE + ISP_REG_UPDATE) +#define ISP_EVENT_EPOCH_0 (ISP_EVENT_BASE + ISP_EPOCH_0) +#define ISP_EVENT_EPOCH_1 (ISP_EVENT_BASE + ISP_EPOCH_1) +#define ISP_EVENT_START_ACK (ISP_EVENT_BASE + ISP_START_ACK) +#define ISP_EVENT_STOP_ACK (ISP_EVENT_BASE + ISP_STOP_ACK) +#define ISP_EVENT_IRQ_VIOLATION (ISP_EVENT_BASE + ISP_IRQ_VIOLATION) +#define ISP_EVENT_WM_BUS_OVERFLOW (ISP_EVENT_BASE + ISP_WM_BUS_OVERFLOW) +#define ISP_EVENT_STATS_OVERFLOW (ISP_EVENT_BASE + ISP_STATS_OVERFLOW) +#define ISP_EVENT_CAMIF_ERROR (ISP_EVENT_BASE + ISP_CAMIF_ERROR) +#define ISP_EVENT_SOF (ISP_CAMIF_EVENT_BASE) +#define ISP_EVENT_EOF (ISP_CAMIF_EVENT_BASE + 1) +#define ISP_EVENT_BUF_DONE (ISP_EVENT_BASE + ISP_BUF_DONE) +#define ISP_EVENT_BUF_DIVERT (ISP_BUF_EVENT_BASE) +#define ISP_EVENT_STATS_NOTIFY (ISP_STATS_EVENT_BASE) +#define ISP_EVENT_COMP_STATS_NOTIFY (ISP_EVENT_STATS_NOTIFY + MSM_ISP_STATS_MAX) +#define ISP_EVENT_FE_READ_DONE (ISP_EVENT_BASE + ISP_FE_RD_DONE) +#define ISP_EVENT_STREAM_UPDATE_DONE (ISP_STREAM_EVENT_BASE) + +/* The msm_v4l2_event_data structure should match the + * v4l2_event.u.data field. + * should not exceed 64 bytes */ + +struct msm_isp_buf_event { + uint32_t session_id; + uint32_t stream_id; + uint32_t handle; + uint32_t output_format; + int8_t buf_idx; +}; +struct msm_isp_stats_event { + uint32_t stats_mask; /* 4 bytes */ + uint8_t stats_buf_idxs[MSM_ISP_STATS_MAX]; /* 11 bytes */ +}; + +struct msm_isp_stream_ack { + uint32_t session_id; + uint32_t stream_id; + uint32_t handle; +}; + +struct msm_isp_error_info { + /* 1 << msm_isp_event_idx */ + uint32_t error_mask; +}; + +struct msm_isp_event_data { + /*Wall clock except for buffer divert events + *which use monotonic clock + */ + struct timeval timestamp; + /* Monotonic timestamp since bootup */ + struct timeval mono_timestamp; + enum msm_vfe_input_src input_intf; + uint32_t frame_id; + union { + struct msm_isp_stats_event stats; + struct msm_isp_buf_event buf_done; + struct msm_isp_error_info error_info; + } u; /* union can have max 52 bytes */ +}; + +#define V4L2_PIX_FMT_QBGGR8 v4l2_fourcc('Q', 'B', 'G', '8') +#define V4L2_PIX_FMT_QGBRG8 v4l2_fourcc('Q', 'G', 'B', '8') +#define V4L2_PIX_FMT_QGRBG8 v4l2_fourcc('Q', 'G', 'R', '8') +#define V4L2_PIX_FMT_QRGGB8 v4l2_fourcc('Q', 'R', 'G', '8') +#define V4L2_PIX_FMT_QBGGR10 v4l2_fourcc('Q', 'B', 'G', '0') +#define V4L2_PIX_FMT_QGBRG10 v4l2_fourcc('Q', 'G', 'B', '0') +#define V4L2_PIX_FMT_QGRBG10 v4l2_fourcc('Q', 'G', 'R', '0') +#define V4L2_PIX_FMT_QRGGB10 v4l2_fourcc('Q', 'R', 'G', '0') +#define V4L2_PIX_FMT_QBGGR12 v4l2_fourcc('Q', 'B', 'G', '2') +#define V4L2_PIX_FMT_QGBRG12 v4l2_fourcc('Q', 'G', 'B', '2') +#define V4L2_PIX_FMT_QGRBG12 v4l2_fourcc('Q', 'G', 'R', '2') +#define V4L2_PIX_FMT_QRGGB12 v4l2_fourcc('Q', 'R', 'G', '2') +#define V4L2_PIX_FMT_QBGGR14 v4l2_fourcc('Q', 'B', 'G', '4') +#define V4L2_PIX_FMT_QGBRG14 v4l2_fourcc('Q', 'G', 'B', '4') +#define V4L2_PIX_FMT_QGRBG14 v4l2_fourcc('Q', 'G', 'R', '4') +#define V4L2_PIX_FMT_QRGGB14 v4l2_fourcc('Q', 'R', 'G', '4') +#define V4L2_PIX_FMT_P16BGGR10 v4l2_fourcc('P', 'B', 'G', '0') +#define V4L2_PIX_FMT_P16GBRG10 v4l2_fourcc('P', 'G', 'B', '0') +#define V4L2_PIX_FMT_P16GRBG10 v4l2_fourcc('P', 'G', 'R', '0') +#define V4L2_PIX_FMT_P16RGGB10 v4l2_fourcc('P', 'R', 'G', '0') +#define V4L2_PIX_FMT_NV14 v4l2_fourcc('N', 'V', '1', '4') +#define V4L2_PIX_FMT_NV41 v4l2_fourcc('N', 'V', '4', '1') +#define V4L2_PIX_FMT_META v4l2_fourcc('Q', 'M', 'E', 'T') +#define V4L2_PIX_FMT_SBGGR14 v4l2_fourcc('B', 'G', '1', '4') /* 14 BGBG.GRGR.*/ +#define V4L2_PIX_FMT_SGBRG14 v4l2_fourcc('G', 'B', '1', '4') /* 14 GBGB.RGRG.*/ +#define V4L2_PIX_FMT_SGRBG14 v4l2_fourcc('B', 'A', '1', '4') /* 14 GRGR.BGBG.*/ +#define V4L2_PIX_FMT_SRGGB14 v4l2_fourcc('R', 'G', '1', '4') /* 14 RGRG.GBGB.*/ + +#define VIDIOC_MSM_VFE_REG_CFG \ + _IOWR('V', BASE_VIDIOC_PRIVATE, struct msm_vfe_cfg_cmd2) + +#define VIDIOC_MSM_ISP_REQUEST_BUF \ + _IOWR('V', BASE_VIDIOC_PRIVATE+1, struct msm_isp_buf_request) + +#define VIDIOC_MSM_ISP_ENQUEUE_BUF \ + _IOWR('V', BASE_VIDIOC_PRIVATE+2, struct msm_isp_qbuf_info) + +#define VIDIOC_MSM_ISP_RELEASE_BUF \ + _IOWR('V', BASE_VIDIOC_PRIVATE+3, struct msm_isp_buf_request) + +#define VIDIOC_MSM_ISP_REQUEST_STREAM \ + _IOWR('V', BASE_VIDIOC_PRIVATE+4, struct msm_vfe_axi_stream_request_cmd) + +#define VIDIOC_MSM_ISP_CFG_STREAM \ + _IOWR('V', BASE_VIDIOC_PRIVATE+5, struct msm_vfe_axi_stream_cfg_cmd) + +#define VIDIOC_MSM_ISP_RELEASE_STREAM \ + _IOWR('V', BASE_VIDIOC_PRIVATE+6, struct msm_vfe_axi_stream_release_cmd) + +#define VIDIOC_MSM_ISP_INPUT_CFG \ + _IOWR('V', BASE_VIDIOC_PRIVATE+7, struct msm_vfe_input_cfg) + +#define VIDIOC_MSM_ISP_SET_SRC_STATE \ + _IOWR('V', BASE_VIDIOC_PRIVATE+8, struct msm_vfe_axi_src_state) + +#define VIDIOC_MSM_ISP_REQUEST_STATS_STREAM \ + _IOWR('V', BASE_VIDIOC_PRIVATE+9, \ + struct msm_vfe_stats_stream_request_cmd) + +#define VIDIOC_MSM_ISP_CFG_STATS_STREAM \ + _IOWR('V', BASE_VIDIOC_PRIVATE+10, struct msm_vfe_stats_stream_cfg_cmd) + +#define VIDIOC_MSM_ISP_RELEASE_STATS_STREAM \ + _IOWR('V', BASE_VIDIOC_PRIVATE+11, \ + struct msm_vfe_stats_stream_release_cmd) + +#define VIDIOC_MSM_ISP_REG_UPDATE_CMD \ + _IOWR('V', BASE_VIDIOC_PRIVATE+12, enum msm_vfe_input_src) + +#define VIDIOC_MSM_ISP_UPDATE_STREAM \ + _IOWR('V', BASE_VIDIOC_PRIVATE+13, struct msm_vfe_axi_stream_update_cmd) + +#define VIDIOC_MSM_VFE_REG_LIST_CFG \ + _IOWR('V', BASE_VIDIOC_PRIVATE+14, struct msm_vfe_cfg_cmd_list) + +#define VIDIOC_MSM_ISP_SMMU_ATTACH \ + _IOWR('V', BASE_VIDIOC_PRIVATE+15, struct msm_vfe_smmu_attach_cmd) + +#define VIDIOC_MSM_ISP_UPDATE_STATS_STREAM \ + _IOWR('V', BASE_VIDIOC_PRIVATE+16, struct msm_vfe_axi_stream_update_cmd) + +#define VIDIOC_MSM_ISP_AXI_HALT \ + _IOWR('V', BASE_VIDIOC_PRIVATE+17, struct msm_vfe_axi_halt_cmd) + +#define VIDIOC_MSM_ISP_AXI_RESET \ + _IOWR('V', BASE_VIDIOC_PRIVATE+18, struct msm_vfe_axi_reset_cmd) + +#define VIDIOC_MSM_ISP_AXI_RESTART \ + _IOWR('V', BASE_VIDIOC_PRIVATE+19, struct msm_vfe_axi_restart_cmd) + +#define VIDIOC_MSM_ISP_FETCH_ENG_START \ + _IOWR('V', BASE_VIDIOC_PRIVATE+20, struct msm_vfe_fetch_eng_start) + +#endif /* __MSMB_ISP__ */ diff --git a/original-kernel-headers/media/msmb_ispif.h b/original-kernel-headers/media/msmb_ispif.h new file mode 100644 index 0000000..2564c33 --- /dev/null +++ b/original-kernel-headers/media/msmb_ispif.h @@ -0,0 +1,125 @@ +#ifndef MSM_CAM_ISPIF_H +#define MSM_CAM_ISPIF_H + +#define CSID_VERSION_V20 0x02000011 +#define CSID_VERSION_V22 0x02001000 +#define CSID_VERSION_V30 0x30000000 +#define CSID_VERSION_V3 0x30000000 + +enum msm_ispif_vfe_intf { + VFE0, + VFE1, + VFE_MAX +}; +#define VFE0_MASK (1 << VFE0) +#define VFE1_MASK (1 << VFE1) + +enum msm_ispif_intftype { + PIX0, + RDI0, + PIX1, + RDI1, + RDI2, + INTF_MAX +}; +#define MAX_PARAM_ENTRIES (INTF_MAX * 2) +#define MAX_CID_CH 8 + +#define PIX0_MASK (1 << PIX0) +#define PIX1_MASK (1 << PIX1) +#define RDI0_MASK (1 << RDI0) +#define RDI1_MASK (1 << RDI1) +#define RDI2_MASK (1 << RDI2) + + +enum msm_ispif_vc { + VC0, + VC1, + VC2, + VC3, + VC_MAX +}; + +enum msm_ispif_cid { + CID0, + CID1, + CID2, + CID3, + CID4, + CID5, + CID6, + CID7, + CID8, + CID9, + CID10, + CID11, + CID12, + CID13, + CID14, + CID15, + CID_MAX +}; + +enum msm_ispif_csid { + CSID0, + CSID1, + CSID2, + CSID3, + CSID_MAX +}; + +struct msm_ispif_params_entry { + enum msm_ispif_vfe_intf vfe_intf; + enum msm_ispif_intftype intftype; + int num_cids; + enum msm_ispif_cid cids[3]; + enum msm_ispif_csid csid; + int crop_enable; + uint16_t crop_start_pixel; + uint16_t crop_end_pixel; +}; + +struct msm_ispif_param_data { + uint32_t num; + struct msm_ispif_params_entry entries[MAX_PARAM_ENTRIES]; +}; + +struct msm_isp_info { + uint32_t max_resolution; + uint32_t id; + uint32_t ver; +}; + +struct msm_ispif_vfe_info { + int num_vfe; + struct msm_isp_info info[VFE_MAX]; +}; + +enum ispif_cfg_type_t { + ISPIF_CLK_ENABLE, + ISPIF_CLK_DISABLE, + ISPIF_INIT, + ISPIF_CFG, + ISPIF_START_FRAME_BOUNDARY, + ISPIF_RESTART_FRAME_BOUNDARY, + ISPIF_STOP_FRAME_BOUNDARY, + ISPIF_STOP_IMMEDIATELY, + ISPIF_RELEASE, + ISPIF_ENABLE_REG_DUMP, + ISPIF_SET_VFE_INFO, +}; + +struct ispif_cfg_data { + enum ispif_cfg_type_t cfg_type; + union { + int reg_dump; /* ISPIF_ENABLE_REG_DUMP */ + uint32_t csid_version; /* ISPIF_INIT */ + struct msm_ispif_vfe_info vfe_info; /* ISPIF_SET_VFE_INFO */ + struct msm_ispif_param_data params; /* CFG, START, STOP */ + }; +}; + +#define VIDIOC_MSM_ISPIF_CFG \ + _IOWR('V', BASE_VIDIOC_PRIVATE, struct ispif_cfg_data) + +#endif /* MSM_CAM_ISPIF_H */ diff --git a/original-kernel-headers/media/msmb_pproc.h b/original-kernel-headers/media/msmb_pproc.h new file mode 100644 index 0000000..4a575bb --- /dev/null +++ b/original-kernel-headers/media/msmb_pproc.h @@ -0,0 +1,471 @@ +#ifndef __MSMB_PPROC_H +#define __MSMB_PPROC_H + +#ifdef MSM_CAMERA_BIONIC +#include <sys/types.h> +#endif +#ifdef CONFIG_COMPAT +#include <linux/compat.h> +#endif +#include <linux/videodev2.h> +#include <linux/types.h> +#include <media/msmb_generic_buf_mgr.h> + +/* Should be same as VIDEO_MAX_PLANES in videodev2.h */ +#define MAX_PLANES VIDEO_MAX_PLANES + +#define MAX_NUM_CPP_STRIPS 8 +#define MSM_CPP_MAX_NUM_PLANES 3 +#define MSM_CPP_MIN_FRAME_LENGTH 13 +#define MSM_CPP_MAX_FRAME_LENGTH 2048 +#define MSM_CPP_MAX_FW_NAME_LEN 32 +#define MAX_FREQ_TBL 10 + +enum msm_cpp_frame_type { + MSM_CPP_OFFLINE_FRAME, + MSM_CPP_REALTIME_FRAME, +}; + +enum msm_vpe_frame_type { + MSM_VPE_OFFLINE_FRAME, + MSM_VPE_REALTIME_FRAME, +}; + +struct msm_cpp_frame_strip_info { + uint32_t scale_v_en; + uint32_t scale_h_en; + + uint32_t upscale_v_en; + uint32_t upscale_h_en; + + int32_t src_start_x; + uint32_t src_end_x; + int32_t src_start_y; + uint32_t src_end_y; + + /* extra 5th and 6th layer parameters */ + int32_t extra_src_start_x; + int32_t extra_src_end_x; + int32_t extra_src_start_y; + int32_t extra_src_end_y; + + int32_t extra_initial_vertical_count[2]; + int32_t extra_initial_horizontal_count[2]; + + /* crop downscale 32x pixels */ + int32_t extra_left_crop; + int32_t extra_top_crop; + + int32_t extra_pad_bottom; + int32_t extra_pad_top; + int32_t extra_pad_right; + int32_t extra_pad_left; + + int32_t extra_upscale_width; + int32_t extra_upscale_height; + + uint32_t temporal_pad_bottom; + uint32_t temporal_pad_top; + uint32_t temporal_pad_right; + uint32_t temporal_pad_left; + + int32_t temporal_src_start_x; + uint32_t temporal_src_end_x; + int32_t temporal_src_start_y; + uint32_t temporal_src_end_y; + + /* Padding is required for upscaler because it does not + * pad internally like other blocks, also needed for rotation + * rotation expects all the blocks in the stripe to be the same size + * Padding is done such that all the extra padded pixels + * are on the right and bottom + */ + uint32_t pad_bottom; + uint32_t pad_top; + uint32_t pad_right; + uint32_t pad_left; + + uint32_t v_init_phase; + uint32_t h_init_phase; + uint32_t h_phase_step; + uint32_t v_phase_step; + + uint32_t spatial_denoise_crop_width_first_pixel; + uint32_t spatial_denoise_crop_width_last_pixel; + uint32_t spatial_denoise_crop_height_first_line; + uint32_t spatial_denoise_crop_height_last_line; + + uint32_t sharpen_crop_height_first_line; + uint32_t sharpen_crop_height_last_line; + uint32_t sharpen_crop_width_first_pixel; + uint32_t sharpen_crop_width_last_pixel; + + uint32_t temporal_denoise_crop_width_first_pixel; + uint32_t temporal_denoise_crop_width_last_pixel; + uint32_t temporal_denoise_crop_height_first_line; + uint32_t temporal_denoise_crop_height_last_line; + + uint32_t prescaler_spatial_denoise_crop_width_first_pixel; + uint32_t prescaler_spatial_denoise_crop_width_last_pixel; + uint32_t prescaler_spatial_denoise_crop_height_first_line; + uint32_t prescaler_spatial_denoise_crop_height_last_line; + + uint32_t state_crop_width_first_pixel; + uint32_t state_crop_width_last_pixel; + uint32_t state_crop_height_first_line; + uint32_t state_crop_height_last_line; + + int32_t dst_start_x; + uint32_t dst_end_x; + int32_t dst_start_y; + uint32_t dst_end_y; + + int32_t temporal_dst_start_x; + uint32_t temporal_dst_end_x; + int32_t temporal_dst_start_y; + uint32_t temporal_dst_end_y; + + uint32_t input_bytes_per_pixel; + uint32_t output_bytes_per_pixel; + uint32_t temporal_bytes_per_pixel; + + uint32_t source_address[2]; + uint32_t extra_source_address[2]; + uint32_t destination_address[2]; + /* source_address[1] is used for CbCR planar + * to CbCr interleaved conversion + */ + uint32_t temporal_source_address[2]; + /* destination_address[1] is used for CbCr interleved + * to CbCr planar conversion + */ + uint32_t temporal_destination_address[2]; + uint32_t src_stride; + uint32_t dst_stride; + uint32_t rotate_270; + uint32_t horizontal_flip; + uint32_t vertical_flip; + uint32_t scale_output_width; + uint32_t scale_output_height; + uint32_t spatial_denoise_crop_en; + uint32_t sharpen_crop_en; + uint32_t temporal_denoise_crop_en; + uint32_t prescaler_spatial_denoise_crop_en; + uint32_t state_crop_en; + + int32_t we_h_init; + int32_t we_v_init; + int32_t we_h_step; + int32_t we_v_step; +}; + +struct msm_cpp_buffer_info_t { + int32_t fd; + uint32_t index; + uint32_t offset; + uint8_t native_buff; + uint8_t processed_divert; + uint32_t identity; +}; + +struct msm_cpp_stream_buff_info_t { + uint32_t identity; + uint32_t num_buffs; + struct msm_cpp_buffer_info_t *buffer_info; +}; + +struct msm_cpp_frame_info_t { + int32_t frame_id; + struct timeval timestamp; + uint32_t inst_id; + uint32_t identity; + uint32_t client_id; + enum msm_cpp_frame_type frame_type; + uint32_t num_strips; + struct msm_cpp_frame_strip_info __user *strip_info; + uint32_t msg_len; + uint32_t *cpp_cmd_msg; + int src_fd; + int dst_fd; + struct timeval in_time, out_time; + void __user *cookie; + int32_t *status; + int32_t duplicate_output; + uint32_t duplicate_identity; + uint8_t we_disable; + struct msm_cpp_buffer_info_t input_buffer_info; + struct msm_cpp_buffer_info_t output_buffer_info[2]; + struct msm_cpp_buffer_info_t tnr_scratch_buffer_info[2]; + uint32_t reserved; +}; + +struct msm_cpp_pop_stream_info_t { + int32_t frame_id; + uint32_t identity; +}; + +struct cpp_hw_info { + uint32_t cpp_hw_version; + uint32_t cpp_hw_caps; + unsigned long freq_tbl[MAX_FREQ_TBL]; + uint32_t freq_tbl_count; +}; + +struct msm_vpe_frame_strip_info { + uint32_t src_w; + uint32_t src_h; + uint32_t dst_w; + uint32_t dst_h; + uint32_t src_x; + uint32_t src_y; + uint32_t phase_step_x; + uint32_t phase_step_y; + uint32_t phase_init_x; + uint32_t phase_init_y; +}; + +struct msm_vpe_buffer_info_t { + int32_t fd; + uint32_t index; + uint32_t offset; + uint8_t native_buff; + uint8_t processed_divert; +}; + +struct msm_vpe_stream_buff_info_t { + uint32_t identity; + uint32_t num_buffs; + struct msm_vpe_buffer_info_t *buffer_info; +}; + +struct msm_vpe_frame_info_t { + int32_t frame_id; + struct timeval timestamp; + uint32_t inst_id; + uint32_t identity; + uint32_t client_id; + enum msm_vpe_frame_type frame_type; + struct msm_vpe_frame_strip_info strip_info; + unsigned long src_fd; + unsigned long dst_fd; + struct ion_handle *src_ion_handle; + struct ion_handle *dest_ion_handle; + unsigned long src_phyaddr; + unsigned long dest_phyaddr; + unsigned long src_chroma_plane_offset; + unsigned long dest_chroma_plane_offset; + struct timeval in_time, out_time; + void *cookie; + + struct msm_vpe_buffer_info_t input_buffer_info; + struct msm_vpe_buffer_info_t output_buffer_info; +}; + +struct msm_pproc_queue_buf_info { + struct msm_buf_mngr_info buff_mgr_info; + uint8_t is_buf_dirty; +}; + +struct msm_cpp_clock_settings_t { + unsigned long clock_rate; + uint64_t avg; + uint64_t inst; +}; + +#define VIDIOC_MSM_CPP_CFG \ + _IOWR('V', BASE_VIDIOC_PRIVATE, struct msm_camera_v4l2_ioctl_t) + +#define VIDIOC_MSM_CPP_GET_EVENTPAYLOAD \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 1, struct msm_camera_v4l2_ioctl_t) + +#define VIDIOC_MSM_CPP_GET_INST_INFO \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 2, struct msm_camera_v4l2_ioctl_t) + +#define VIDIOC_MSM_CPP_LOAD_FIRMWARE \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 3, struct msm_camera_v4l2_ioctl_t) + +#define VIDIOC_MSM_CPP_GET_HW_INFO \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 4, struct msm_camera_v4l2_ioctl_t) + +#define VIDIOC_MSM_CPP_FLUSH_QUEUE \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 5, struct msm_camera_v4l2_ioctl_t) + +#define VIDIOC_MSM_CPP_ENQUEUE_STREAM_BUFF_INFO \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 6, struct msm_camera_v4l2_ioctl_t) + +#define VIDIOC_MSM_CPP_DEQUEUE_STREAM_BUFF_INFO \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 7, struct msm_camera_v4l2_ioctl_t) + +#define VIDIOC_MSM_VPE_CFG \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 8, struct msm_camera_v4l2_ioctl_t) + +#define VIDIOC_MSM_VPE_TRANSACTION_SETUP \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 9, struct msm_camera_v4l2_ioctl_t) + +#define VIDIOC_MSM_VPE_GET_EVENTPAYLOAD \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 10, struct msm_camera_v4l2_ioctl_t) + +#define VIDIOC_MSM_VPE_GET_INST_INFO \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 11, struct msm_camera_v4l2_ioctl_t) + +#define VIDIOC_MSM_VPE_ENQUEUE_STREAM_BUFF_INFO \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 12, struct msm_camera_v4l2_ioctl_t) + +#define VIDIOC_MSM_VPE_DEQUEUE_STREAM_BUFF_INFO \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 13, struct msm_camera_v4l2_ioctl_t) + +#define VIDIOC_MSM_CPP_QUEUE_BUF \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 14, struct msm_camera_v4l2_ioctl_t) + +#define VIDIOC_MSM_CPP_APPEND_STREAM_BUFF_INFO \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 15, struct msm_camera_v4l2_ioctl_t) + +#define VIDIOC_MSM_CPP_SET_CLOCK \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 16, struct msm_camera_v4l2_ioctl_t) + +#define VIDIOC_MSM_CPP_POP_STREAM_BUFFER \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 17, struct msm_camera_v4l2_ioctl_t) + +#define VIDIOC_MSM_CPP_IOMMU_ATTACH \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 18, struct msm_camera_v4l2_ioctl_t) + +#define VIDIOC_MSM_CPP_IOMMU_DETACH \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 19, struct msm_camera_v4l2_ioctl_t) + +#define VIDIOC_MSM_CPP_DELETE_STREAM_BUFF\ + _IOWR('V', BASE_VIDIOC_PRIVATE + 20, struct msm_camera_v4l2_ioctl_t) + + +#define V4L2_EVENT_CPP_FRAME_DONE (V4L2_EVENT_PRIVATE_START + 0) +#define V4L2_EVENT_VPE_FRAME_DONE (V4L2_EVENT_PRIVATE_START + 1) + +struct msm_camera_v4l2_ioctl_t { + uint32_t id; + size_t len; + int32_t trans_code; + void __user *ioctl_ptr; +}; + +#ifdef CONFIG_COMPAT +struct msm_cpp_frame_info32_t { + int32_t frame_id; + struct compat_timeval timestamp; + uint32_t inst_id; + uint32_t identity; + uint32_t client_id; + enum msm_cpp_frame_type frame_type; + uint32_t num_strips; + compat_caddr_t strip_info; + uint32_t msg_len; + compat_uint_t cpp_cmd_msg; + int src_fd; + int dst_fd; + struct compat_timeval in_time, out_time; + compat_caddr_t cookie; + compat_int_t status; + int32_t duplicate_output; + uint32_t duplicate_identity; + uint8_t we_disable; + struct msm_cpp_buffer_info_t input_buffer_info; + struct msm_cpp_buffer_info_t output_buffer_info[2]; + struct msm_cpp_buffer_info_t tnr_scratch_buffer_info[2]; + uint32_t reserved; +}; + +struct msm_cpp_clock_settings32_t { + compat_long_t clock_rate; + uint64_t avg; + uint64_t inst; +}; + +struct msm_cpp_stream_buff_info32_t { + uint32_t identity; + uint32_t num_buffs; + compat_caddr_t buffer_info; +}; + +struct msm_pproc_queue_buf_info32_t { + struct msm_buf_mngr_info32_t buff_mgr_info; + uint8_t is_buf_dirty; +}; + +struct cpp_hw_info_32_t { + uint32_t cpp_hw_version; + uint32_t cpp_hw_caps; + compat_long_t freq_tbl[MAX_FREQ_TBL]; + uint32_t freq_tbl_count; +}; + + +#define VIDIOC_MSM_CPP_CFG32 \ + _IOWR('V', BASE_VIDIOC_PRIVATE, struct msm_camera_v4l2_ioctl32_t) + +#define VIDIOC_MSM_CPP_GET_EVENTPAYLOAD32 \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 1, struct msm_camera_v4l2_ioctl32_t) + +#define VIDIOC_MSM_CPP_GET_INST_INFO32 \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 2, struct msm_camera_v4l2_ioctl32_t) + +#define VIDIOC_MSM_CPP_LOAD_FIRMWARE32 \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 3, struct msm_camera_v4l2_ioctl32_t) + +#define VIDIOC_MSM_CPP_GET_HW_INFO32 \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 4, struct msm_camera_v4l2_ioctl32_t) + +#define VIDIOC_MSM_CPP_FLUSH_QUEUE32 \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 5, struct msm_camera_v4l2_ioctl32_t) + +#define VIDIOC_MSM_CPP_ENQUEUE_STREAM_BUFF_INFO32 \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 6, struct msm_camera_v4l2_ioctl32_t) + +#define VIDIOC_MSM_CPP_DEQUEUE_STREAM_BUFF_INFO32 \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 7, struct msm_camera_v4l2_ioctl32_t) + +#define VIDIOC_MSM_VPE_CFG32 \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 8, struct msm_camera_v4l2_ioctl32_t) + +#define VIDIOC_MSM_VPE_TRANSACTION_SETUP32 \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 9, struct msm_camera_v4l2_ioctl32_t) + +#define VIDIOC_MSM_VPE_GET_EVENTPAYLOAD32 \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 10, struct msm_camera_v4l2_ioctl32_t) + +#define VIDIOC_MSM_VPE_GET_INST_INFO32 \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 11, struct msm_camera_v4l2_ioctl32_t) + +#define VIDIOC_MSM_VPE_ENQUEUE_STREAM_BUFF_INFO32 \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 12, struct msm_camera_v4l2_ioctl32_t) + +#define VIDIOC_MSM_VPE_DEQUEUE_STREAM_BUFF_INFO32 \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 13, struct msm_camera_v4l2_ioctl32_t) + +#define VIDIOC_MSM_CPP_QUEUE_BUF32 \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 14, struct msm_camera_v4l2_ioctl32_t) + +#define VIDIOC_MSM_CPP_APPEND_STREAM_BUFF_INFO32 \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 15, struct msm_camera_v4l2_ioctl32_t) + +#define VIDIOC_MSM_CPP_SET_CLOCK32 \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 16, struct msm_camera_v4l2_ioctl32_t) + +#define VIDIOC_MSM_CPP_POP_STREAM_BUFFER32 \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 17, struct msm_camera_v4l2_ioctl32_t) + +#define VIDIOC_MSM_CPP_IOMMU_ATTACH32 \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 18, struct msm_camera_v4l2_ioctl32_t) + +#define VIDIOC_MSM_CPP_IOMMU_DETACH32 \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 19, struct msm_camera_v4l2_ioctl32_t) + +#define VIDIOC_MSM_CPP_DELETE_STREAM_BUFF32\ + _IOWR('V', BASE_VIDIOC_PRIVATE + 20, struct msm_camera_v4l2_ioctl32_t) + +struct msm_camera_v4l2_ioctl32_t { + uint32_t id; + uint32_t len; + int32_t trans_code; + compat_caddr_t ioctl_ptr; +}; +#endif + +#endif /* __MSMB_PPROC_H */ diff --git a/original-kernel-headers/sound/asound.h b/original-kernel-headers/sound/asound.h new file mode 100644 index 0000000..78efb06 --- /dev/null +++ b/original-kernel-headers/sound/asound.h @@ -0,0 +1,975 @@ +/* + * Advanced Linux Sound Architecture - ALSA - Driver + * Copyright (c) 1994-2003 by Jaroslav Kysela <perex@perex.cz>, + * Abramo Bagnara <abramo@alsa-project.org> + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#ifndef _UAPI__SOUND_ASOUND_H +#define _UAPI__SOUND_ASOUND_H + +#include <linux/types.h> + + +/* + * protocol version + */ + +#define SNDRV_PROTOCOL_VERSION(major, minor, subminor) (((major)<<16)|((minor)<<8)|(subminor)) +#define SNDRV_PROTOCOL_MAJOR(version) (((version)>>16)&0xffff) +#define SNDRV_PROTOCOL_MINOR(version) (((version)>>8)&0xff) +#define SNDRV_PROTOCOL_MICRO(version) ((version)&0xff) +#define SNDRV_PROTOCOL_INCOMPATIBLE(kversion, uversion) \ + (SNDRV_PROTOCOL_MAJOR(kversion) != SNDRV_PROTOCOL_MAJOR(uversion) || \ + (SNDRV_PROTOCOL_MAJOR(kversion) == SNDRV_PROTOCOL_MAJOR(uversion) && \ + SNDRV_PROTOCOL_MINOR(kversion) != SNDRV_PROTOCOL_MINOR(uversion))) + +/**************************************************************************** + * * + * Digital audio interface * + * * + ****************************************************************************/ + +struct snd_aes_iec958 { + unsigned char status[24]; /* AES/IEC958 channel status bits */ + unsigned char subcode[147]; /* AES/IEC958 subcode bits */ + unsigned char pad; /* nothing */ + unsigned char dig_subframe[4]; /* AES/IEC958 subframe bits */ +}; + +/**************************************************************************** + * * + * CEA-861 Audio InfoFrame. Used in HDMI and DisplayPort * + * * + ****************************************************************************/ + +struct snd_cea_861_aud_if { + unsigned char db1_ct_cc; /* coding type and channel count */ + unsigned char db2_sf_ss; /* sample frequency and size */ + unsigned char db3; /* not used, all zeros */ + unsigned char db4_ca; /* channel allocation code */ + unsigned char db5_dminh_lsv; /* downmix inhibit & level-shit values */ +}; + +/**************************************************************************** + * * + * Section for driver hardware dependent interface - /dev/snd/hw? * + * * + ****************************************************************************/ + +#define SNDRV_HWDEP_VERSION SNDRV_PROTOCOL_VERSION(1, 0, 1) + +enum { + SNDRV_HWDEP_IFACE_OPL2 = 0, + SNDRV_HWDEP_IFACE_OPL3, + SNDRV_HWDEP_IFACE_OPL4, + SNDRV_HWDEP_IFACE_SB16CSP, /* Creative Signal Processor */ + SNDRV_HWDEP_IFACE_EMU10K1, /* FX8010 processor in EMU10K1 chip */ + SNDRV_HWDEP_IFACE_YSS225, /* Yamaha FX processor */ + SNDRV_HWDEP_IFACE_ICS2115, /* Wavetable synth */ + SNDRV_HWDEP_IFACE_SSCAPE, /* Ensoniq SoundScape ISA card (MC68EC000) */ + SNDRV_HWDEP_IFACE_VX, /* Digigram VX cards */ + SNDRV_HWDEP_IFACE_MIXART, /* Digigram miXart cards */ + SNDRV_HWDEP_IFACE_USX2Y, /* Tascam US122, US224 & US428 usb */ + SNDRV_HWDEP_IFACE_EMUX_WAVETABLE, /* EmuX wavetable */ + SNDRV_HWDEP_IFACE_BLUETOOTH, /* Bluetooth audio */ + SNDRV_HWDEP_IFACE_USX2Y_PCM, /* Tascam US122, US224 & US428 rawusb pcm */ + SNDRV_HWDEP_IFACE_PCXHR, /* Digigram PCXHR */ + SNDRV_HWDEP_IFACE_SB_RC, /* SB Extigy/Audigy2NX remote control */ + SNDRV_HWDEP_IFACE_HDA, /* HD-audio */ + SNDRV_HWDEP_IFACE_USB_STREAM, /* direct access to usb stream */ + SNDRV_HWDEP_IFACE_AUDIO_BE, /* Backend Audio Control */ + SNDRV_HWDEP_IFACE_AUDIO_CODEC, /* codec Audio Control */ + + /* Don't forget to change the following: */ + SNDRV_HWDEP_IFACE_LAST = SNDRV_HWDEP_IFACE_AUDIO_CODEC +}; + +struct snd_hwdep_info { + unsigned int device; /* WR: device number */ + int card; /* R: card number */ + unsigned char id[64]; /* ID (user selectable) */ + unsigned char name[80]; /* hwdep name */ + int iface; /* hwdep interface */ + unsigned char reserved[64]; /* reserved for future */ +}; + +/* generic DSP loader */ +struct snd_hwdep_dsp_status { + unsigned int version; /* R: driver-specific version */ + unsigned char id[32]; /* R: driver-specific ID string */ + unsigned int num_dsps; /* R: number of DSP images to transfer */ + unsigned int dsp_loaded; /* R: bit flags indicating the loaded DSPs */ + unsigned int chip_ready; /* R: 1 = initialization finished */ + unsigned char reserved[16]; /* reserved for future use */ +}; + +struct snd_hwdep_dsp_image { + unsigned int index; /* W: DSP index */ + unsigned char name[64]; /* W: ID (e.g. file name) */ + unsigned char __user *image; /* W: binary image */ + size_t length; /* W: size of image in bytes */ + unsigned long driver_data; /* W: driver-specific data */ +}; + +#define SNDRV_HWDEP_IOCTL_PVERSION _IOR ('H', 0x00, int) +#define SNDRV_HWDEP_IOCTL_INFO _IOR ('H', 0x01, struct snd_hwdep_info) +#define SNDRV_HWDEP_IOCTL_DSP_STATUS _IOR('H', 0x02, struct snd_hwdep_dsp_status) +#define SNDRV_HWDEP_IOCTL_DSP_LOAD _IOW('H', 0x03, struct snd_hwdep_dsp_image) + +/***************************************************************************** + * * + * Digital Audio (PCM) interface - /dev/snd/pcm?? * + * * + *****************************************************************************/ + +#define SNDRV_PCM_VERSION SNDRV_PROTOCOL_VERSION(2, 0, 11) + +typedef unsigned long snd_pcm_uframes_t; +typedef signed long snd_pcm_sframes_t; + +enum { + SNDRV_PCM_CLASS_GENERIC = 0, /* standard mono or stereo device */ + SNDRV_PCM_CLASS_MULTI, /* multichannel device */ + SNDRV_PCM_CLASS_MODEM, /* software modem class */ + SNDRV_PCM_CLASS_DIGITIZER, /* digitizer class */ + /* Don't forget to change the following: */ + SNDRV_PCM_CLASS_LAST = SNDRV_PCM_CLASS_DIGITIZER, +}; + +enum { + SNDRV_PCM_SUBCLASS_GENERIC_MIX = 0, /* mono or stereo subdevices are mixed together */ + SNDRV_PCM_SUBCLASS_MULTI_MIX, /* multichannel subdevices are mixed together */ + /* Don't forget to change the following: */ + SNDRV_PCM_SUBCLASS_LAST = SNDRV_PCM_SUBCLASS_MULTI_MIX, +}; + +enum { + SNDRV_PCM_STREAM_PLAYBACK = 0, + SNDRV_PCM_STREAM_CAPTURE, + SNDRV_PCM_STREAM_LAST = SNDRV_PCM_STREAM_CAPTURE, +}; + +typedef int __bitwise snd_pcm_access_t; +#define SNDRV_PCM_ACCESS_MMAP_INTERLEAVED ((__force snd_pcm_access_t) 0) /* interleaved mmap */ +#define SNDRV_PCM_ACCESS_MMAP_NONINTERLEAVED ((__force snd_pcm_access_t) 1) /* noninterleaved mmap */ +#define SNDRV_PCM_ACCESS_MMAP_COMPLEX ((__force snd_pcm_access_t) 2) /* complex mmap */ +#define SNDRV_PCM_ACCESS_RW_INTERLEAVED ((__force snd_pcm_access_t) 3) /* readi/writei */ +#define SNDRV_PCM_ACCESS_RW_NONINTERLEAVED ((__force snd_pcm_access_t) 4) /* readn/writen */ +#define SNDRV_PCM_ACCESS_LAST SNDRV_PCM_ACCESS_RW_NONINTERLEAVED + +typedef int __bitwise snd_pcm_format_t; +#define SNDRV_PCM_FORMAT_S8 ((__force snd_pcm_format_t) 0) +#define SNDRV_PCM_FORMAT_U8 ((__force snd_pcm_format_t) 1) +#define SNDRV_PCM_FORMAT_S16_LE ((__force snd_pcm_format_t) 2) +#define SNDRV_PCM_FORMAT_S16_BE ((__force snd_pcm_format_t) 3) +#define SNDRV_PCM_FORMAT_U16_LE ((__force snd_pcm_format_t) 4) +#define SNDRV_PCM_FORMAT_U16_BE ((__force snd_pcm_format_t) 5) +#define SNDRV_PCM_FORMAT_S24_LE ((__force snd_pcm_format_t) 6) /* low three bytes */ +#define SNDRV_PCM_FORMAT_S24_BE ((__force snd_pcm_format_t) 7) /* low three bytes */ +#define SNDRV_PCM_FORMAT_U24_LE ((__force snd_pcm_format_t) 8) /* low three bytes */ +#define SNDRV_PCM_FORMAT_U24_BE ((__force snd_pcm_format_t) 9) /* low three bytes */ +#define SNDRV_PCM_FORMAT_S32_LE ((__force snd_pcm_format_t) 10) +#define SNDRV_PCM_FORMAT_S32_BE ((__force snd_pcm_format_t) 11) +#define SNDRV_PCM_FORMAT_U32_LE ((__force snd_pcm_format_t) 12) +#define SNDRV_PCM_FORMAT_U32_BE ((__force snd_pcm_format_t) 13) +#define SNDRV_PCM_FORMAT_FLOAT_LE ((__force snd_pcm_format_t) 14) /* 4-byte float, IEEE-754 32-bit, range -1.0 to 1.0 */ +#define SNDRV_PCM_FORMAT_FLOAT_BE ((__force snd_pcm_format_t) 15) /* 4-byte float, IEEE-754 32-bit, range -1.0 to 1.0 */ +#define SNDRV_PCM_FORMAT_FLOAT64_LE ((__force snd_pcm_format_t) 16) /* 8-byte float, IEEE-754 64-bit, range -1.0 to 1.0 */ +#define SNDRV_PCM_FORMAT_FLOAT64_BE ((__force snd_pcm_format_t) 17) /* 8-byte float, IEEE-754 64-bit, range -1.0 to 1.0 */ +#define SNDRV_PCM_FORMAT_IEC958_SUBFRAME_LE ((__force snd_pcm_format_t) 18) /* IEC-958 subframe, Little Endian */ +#define SNDRV_PCM_FORMAT_IEC958_SUBFRAME_BE ((__force snd_pcm_format_t) 19) /* IEC-958 subframe, Big Endian */ +#define SNDRV_PCM_FORMAT_MU_LAW ((__force snd_pcm_format_t) 20) +#define SNDRV_PCM_FORMAT_A_LAW ((__force snd_pcm_format_t) 21) +#define SNDRV_PCM_FORMAT_IMA_ADPCM ((__force snd_pcm_format_t) 22) +#define SNDRV_PCM_FORMAT_MPEG ((__force snd_pcm_format_t) 23) +#define SNDRV_PCM_FORMAT_GSM ((__force snd_pcm_format_t) 24) +#define SNDRV_PCM_FORMAT_SPECIAL ((__force snd_pcm_format_t) 31) +#define SNDRV_PCM_FORMAT_S24_3LE ((__force snd_pcm_format_t) 32) /* in three bytes */ +#define SNDRV_PCM_FORMAT_S24_3BE ((__force snd_pcm_format_t) 33) /* in three bytes */ +#define SNDRV_PCM_FORMAT_U24_3LE ((__force snd_pcm_format_t) 34) /* in three bytes */ +#define SNDRV_PCM_FORMAT_U24_3BE ((__force snd_pcm_format_t) 35) /* in three bytes */ +#define SNDRV_PCM_FORMAT_S20_3LE ((__force snd_pcm_format_t) 36) /* in three bytes */ +#define SNDRV_PCM_FORMAT_S20_3BE ((__force snd_pcm_format_t) 37) /* in three bytes */ +#define SNDRV_PCM_FORMAT_U20_3LE ((__force snd_pcm_format_t) 38) /* in three bytes */ +#define SNDRV_PCM_FORMAT_U20_3BE ((__force snd_pcm_format_t) 39) /* in three bytes */ +#define SNDRV_PCM_FORMAT_S18_3LE ((__force snd_pcm_format_t) 40) /* in three bytes */ +#define SNDRV_PCM_FORMAT_S18_3BE ((__force snd_pcm_format_t) 41) /* in three bytes */ +#define SNDRV_PCM_FORMAT_U18_3LE ((__force snd_pcm_format_t) 42) /* in three bytes */ +#define SNDRV_PCM_FORMAT_U18_3BE ((__force snd_pcm_format_t) 43) /* in three bytes */ +#define SNDRV_PCM_FORMAT_G723_24 ((__force snd_pcm_format_t) 44) /* 8 samples in 3 bytes */ +#define SNDRV_PCM_FORMAT_G723_24_1B ((__force snd_pcm_format_t) 45) /* 1 sample in 1 byte */ +#define SNDRV_PCM_FORMAT_G723_40 ((__force snd_pcm_format_t) 46) /* 8 Samples in 5 bytes */ +#define SNDRV_PCM_FORMAT_G723_40_1B ((__force snd_pcm_format_t) 47) /* 1 sample in 1 byte */ +#define SNDRV_PCM_FORMAT_DSD_U8 ((__force snd_pcm_format_t) 48) /* DSD, 1-byte samples DSD (x8) */ +#define SNDRV_PCM_FORMAT_DSD_U16_LE ((__force snd_pcm_format_t) 49) /* DSD, 2-byte samples DSD (x16), little endian */ +#define SNDRV_PCM_FORMAT_LAST SNDRV_PCM_FORMAT_DSD_U16_LE + +#ifdef SNDRV_LITTLE_ENDIAN +#define SNDRV_PCM_FORMAT_S16 SNDRV_PCM_FORMAT_S16_LE +#define SNDRV_PCM_FORMAT_U16 SNDRV_PCM_FORMAT_U16_LE +#define SNDRV_PCM_FORMAT_S24 SNDRV_PCM_FORMAT_S24_LE +#define SNDRV_PCM_FORMAT_U24 SNDRV_PCM_FORMAT_U24_LE +#define SNDRV_PCM_FORMAT_S32 SNDRV_PCM_FORMAT_S32_LE +#define SNDRV_PCM_FORMAT_U32 SNDRV_PCM_FORMAT_U32_LE +#define SNDRV_PCM_FORMAT_FLOAT SNDRV_PCM_FORMAT_FLOAT_LE +#define SNDRV_PCM_FORMAT_FLOAT64 SNDRV_PCM_FORMAT_FLOAT64_LE +#define SNDRV_PCM_FORMAT_IEC958_SUBFRAME SNDRV_PCM_FORMAT_IEC958_SUBFRAME_LE +#endif +#ifdef SNDRV_BIG_ENDIAN +#define SNDRV_PCM_FORMAT_S16 SNDRV_PCM_FORMAT_S16_BE +#define SNDRV_PCM_FORMAT_U16 SNDRV_PCM_FORMAT_U16_BE +#define SNDRV_PCM_FORMAT_S24 SNDRV_PCM_FORMAT_S24_BE +#define SNDRV_PCM_FORMAT_U24 SNDRV_PCM_FORMAT_U24_BE +#define SNDRV_PCM_FORMAT_S32 SNDRV_PCM_FORMAT_S32_BE +#define SNDRV_PCM_FORMAT_U32 SNDRV_PCM_FORMAT_U32_BE +#define SNDRV_PCM_FORMAT_FLOAT SNDRV_PCM_FORMAT_FLOAT_BE +#define SNDRV_PCM_FORMAT_FLOAT64 SNDRV_PCM_FORMAT_FLOAT64_BE +#define SNDRV_PCM_FORMAT_IEC958_SUBFRAME SNDRV_PCM_FORMAT_IEC958_SUBFRAME_BE +#endif + +typedef int __bitwise snd_pcm_subformat_t; +#define SNDRV_PCM_SUBFORMAT_STD ((__force snd_pcm_subformat_t) 0) +#define SNDRV_PCM_SUBFORMAT_LAST SNDRV_PCM_SUBFORMAT_STD + +#define SNDRV_PCM_INFO_MMAP 0x00000001 /* hardware supports mmap */ +#define SNDRV_PCM_INFO_MMAP_VALID 0x00000002 /* period data are valid during transfer */ +#define SNDRV_PCM_INFO_DOUBLE 0x00000004 /* Double buffering needed for PCM start/stop */ +#define SNDRV_PCM_INFO_BATCH 0x00000010 /* double buffering */ +#define SNDRV_PCM_INFO_INTERLEAVED 0x00000100 /* channels are interleaved */ +#define SNDRV_PCM_INFO_NONINTERLEAVED 0x00000200 /* channels are not interleaved */ +#define SNDRV_PCM_INFO_COMPLEX 0x00000400 /* complex frame organization (mmap only) */ +#define SNDRV_PCM_INFO_BLOCK_TRANSFER 0x00010000 /* hardware transfer block of samples */ +#define SNDRV_PCM_INFO_OVERRANGE 0x00020000 /* hardware supports ADC (capture) overrange detection */ +#define SNDRV_PCM_INFO_RESUME 0x00040000 /* hardware supports stream resume after suspend */ +#define SNDRV_PCM_INFO_PAUSE 0x00080000 /* pause ioctl is supported */ +#define SNDRV_PCM_INFO_HALF_DUPLEX 0x00100000 /* only half duplex */ +#define SNDRV_PCM_INFO_JOINT_DUPLEX 0x00200000 /* playback and capture stream are somewhat correlated */ +#define SNDRV_PCM_INFO_SYNC_START 0x00400000 /* pcm support some kind of sync go */ +#define SNDRV_PCM_INFO_NO_PERIOD_WAKEUP 0x00800000 /* period wakeup can be disabled */ +#define SNDRV_PCM_INFO_HAS_WALL_CLOCK 0x01000000 /* has audio wall clock for audio/system time sync */ +#define SNDRV_PCM_INFO_FIFO_IN_FRAMES 0x80000000 /* internal kernel flag - FIFO size is in frames */ + +typedef int __bitwise snd_pcm_state_t; +#define SNDRV_PCM_STATE_OPEN ((__force snd_pcm_state_t) 0) /* stream is open */ +#define SNDRV_PCM_STATE_SETUP ((__force snd_pcm_state_t) 1) /* stream has a setup */ +#define SNDRV_PCM_STATE_PREPARED ((__force snd_pcm_state_t) 2) /* stream is ready to start */ +#define SNDRV_PCM_STATE_RUNNING ((__force snd_pcm_state_t) 3) /* stream is running */ +#define SNDRV_PCM_STATE_XRUN ((__force snd_pcm_state_t) 4) /* stream reached an xrun */ +#define SNDRV_PCM_STATE_DRAINING ((__force snd_pcm_state_t) 5) /* stream is draining */ +#define SNDRV_PCM_STATE_PAUSED ((__force snd_pcm_state_t) 6) /* stream is paused */ +#define SNDRV_PCM_STATE_SUSPENDED ((__force snd_pcm_state_t) 7) /* hardware is suspended */ +#define SNDRV_PCM_STATE_DISCONNECTED ((__force snd_pcm_state_t) 8) /* hardware is disconnected */ +#define SNDRV_PCM_STATE_LAST SNDRV_PCM_STATE_DISCONNECTED + +enum { + SNDRV_PCM_MMAP_OFFSET_DATA = 0x00000000, + SNDRV_PCM_MMAP_OFFSET_STATUS = 0x80000000, + SNDRV_PCM_MMAP_OFFSET_CONTROL = 0x81000000, +}; + +union snd_pcm_sync_id { + unsigned char id[16]; + unsigned short id16[8]; + unsigned int id32[4]; +}; + +struct snd_pcm_info { + unsigned int device; /* RO/WR (control): device number */ + unsigned int subdevice; /* RO/WR (control): subdevice number */ + int stream; /* RO/WR (control): stream direction */ + int card; /* R: card number */ + unsigned char id[64]; /* ID (user selectable) */ + unsigned char name[80]; /* name of this device */ + unsigned char subname[32]; /* subdevice name */ + int dev_class; /* SNDRV_PCM_CLASS_* */ + int dev_subclass; /* SNDRV_PCM_SUBCLASS_* */ + unsigned int subdevices_count; + unsigned int subdevices_avail; + union snd_pcm_sync_id sync; /* hardware synchronization ID */ + unsigned char reserved[64]; /* reserved for future... */ +}; + +typedef int snd_pcm_hw_param_t; +#define SNDRV_PCM_HW_PARAM_ACCESS 0 /* Access type */ +#define SNDRV_PCM_HW_PARAM_FORMAT 1 /* Format */ +#define SNDRV_PCM_HW_PARAM_SUBFORMAT 2 /* Subformat */ +#define SNDRV_PCM_HW_PARAM_FIRST_MASK SNDRV_PCM_HW_PARAM_ACCESS +#define SNDRV_PCM_HW_PARAM_LAST_MASK SNDRV_PCM_HW_PARAM_SUBFORMAT + +#define SNDRV_PCM_HW_PARAM_SAMPLE_BITS 8 /* Bits per sample */ +#define SNDRV_PCM_HW_PARAM_FRAME_BITS 9 /* Bits per frame */ +#define SNDRV_PCM_HW_PARAM_CHANNELS 10 /* Channels */ +#define SNDRV_PCM_HW_PARAM_RATE 11 /* Approx rate */ +#define SNDRV_PCM_HW_PARAM_PERIOD_TIME 12 /* Approx distance between + * interrupts in us + */ +#define SNDRV_PCM_HW_PARAM_PERIOD_SIZE 13 /* Approx frames between + * interrupts + */ +#define SNDRV_PCM_HW_PARAM_PERIOD_BYTES 14 /* Approx bytes between + * interrupts + */ +#define SNDRV_PCM_HW_PARAM_PERIODS 15 /* Approx interrupts per + * buffer + */ +#define SNDRV_PCM_HW_PARAM_BUFFER_TIME 16 /* Approx duration of buffer + * in us + */ +#define SNDRV_PCM_HW_PARAM_BUFFER_SIZE 17 /* Size of buffer in frames */ +#define SNDRV_PCM_HW_PARAM_BUFFER_BYTES 18 /* Size of buffer in bytes */ +#define SNDRV_PCM_HW_PARAM_TICK_TIME 19 /* Approx tick duration in us */ +#define SNDRV_PCM_HW_PARAM_FIRST_INTERVAL SNDRV_PCM_HW_PARAM_SAMPLE_BITS +#define SNDRV_PCM_HW_PARAM_LAST_INTERVAL SNDRV_PCM_HW_PARAM_TICK_TIME + +#define SNDRV_PCM_HW_PARAMS_NORESAMPLE (1<<0) /* avoid rate resampling */ +#define SNDRV_PCM_HW_PARAMS_EXPORT_BUFFER (1<<1) /* export buffer */ +#define SNDRV_PCM_HW_PARAMS_NO_PERIOD_WAKEUP (1<<2) /* disable period wakeups */ + +struct snd_interval { + unsigned int min, max; + unsigned int openmin:1, + openmax:1, + integer:1, + empty:1; +}; + +#define SNDRV_MASK_MAX 256 + +struct snd_mask { + __u32 bits[(SNDRV_MASK_MAX+31)/32]; +}; + +struct snd_pcm_hw_params { + unsigned int flags; + struct snd_mask masks[SNDRV_PCM_HW_PARAM_LAST_MASK - + SNDRV_PCM_HW_PARAM_FIRST_MASK + 1]; + struct snd_mask mres[5]; /* reserved masks */ + struct snd_interval intervals[SNDRV_PCM_HW_PARAM_LAST_INTERVAL - + SNDRV_PCM_HW_PARAM_FIRST_INTERVAL + 1]; + struct snd_interval ires[9]; /* reserved intervals */ + unsigned int rmask; /* W: requested masks */ + unsigned int cmask; /* R: changed masks */ + unsigned int info; /* R: Info flags for returned setup */ + unsigned int msbits; /* R: used most significant bits */ + unsigned int rate_num; /* R: rate numerator */ + unsigned int rate_den; /* R: rate denominator */ + snd_pcm_uframes_t fifo_size; /* R: chip FIFO size in frames */ + unsigned char reserved[64]; /* reserved for future */ +}; + +enum { + SNDRV_PCM_TSTAMP_NONE = 0, + SNDRV_PCM_TSTAMP_ENABLE, + SNDRV_PCM_TSTAMP_LAST = SNDRV_PCM_TSTAMP_ENABLE, +}; + +struct snd_pcm_sw_params { + int tstamp_mode; /* timestamp mode */ + unsigned int period_step; + unsigned int sleep_min; /* min ticks to sleep */ + snd_pcm_uframes_t avail_min; /* min avail frames for wakeup */ + snd_pcm_uframes_t xfer_align; /* obsolete: xfer size need to be a multiple */ + snd_pcm_uframes_t start_threshold; /* min hw_avail frames for automatic start */ + snd_pcm_uframes_t stop_threshold; /* min avail frames for automatic stop */ + snd_pcm_uframes_t silence_threshold; /* min distance from noise for silence filling */ + snd_pcm_uframes_t silence_size; /* silence block size */ + snd_pcm_uframes_t boundary; /* pointers wrap point */ + unsigned char reserved[64]; /* reserved for future */ +}; + +struct snd_pcm_channel_info { + unsigned int channel; + __kernel_off_t offset; /* mmap offset */ + unsigned int first; /* offset to first sample in bits */ + unsigned int step; /* samples distance in bits */ +}; + +struct snd_pcm_status { + snd_pcm_state_t state; /* stream state */ + struct timespec trigger_tstamp; /* time when stream was started/stopped/paused */ + struct timespec tstamp; /* reference timestamp */ + snd_pcm_uframes_t appl_ptr; /* appl ptr */ + snd_pcm_uframes_t hw_ptr; /* hw ptr */ + snd_pcm_sframes_t delay; /* current delay in frames */ + snd_pcm_uframes_t avail; /* number of frames available */ + snd_pcm_uframes_t avail_max; /* max frames available on hw since last status */ + snd_pcm_uframes_t overrange; /* count of ADC (capture) overrange detections from last status */ + snd_pcm_state_t suspended_state; /* suspended stream state */ + __u32 reserved_alignment; /* must be filled with zero */ + struct timespec audio_tstamp; /* from sample counter or wall clock */ + unsigned char reserved[56-sizeof(struct timespec)]; /* must be filled with zero */ +}; + +struct snd_pcm_mmap_status { + snd_pcm_state_t state; /* RO: state - SNDRV_PCM_STATE_XXXX */ + int pad1; /* Needed for 64 bit alignment */ + snd_pcm_uframes_t hw_ptr; /* RO: hw ptr (0...boundary-1) */ + struct timespec tstamp; /* Timestamp */ + snd_pcm_state_t suspended_state; /* RO: suspended stream state */ + struct timespec audio_tstamp; /* from sample counter or wall clock */ +}; + +struct snd_pcm_mmap_control { + snd_pcm_uframes_t appl_ptr; /* RW: appl ptr (0...boundary-1) */ + snd_pcm_uframes_t avail_min; /* RW: min available frames for wakeup */ +}; + +#define SNDRV_PCM_SYNC_PTR_HWSYNC (1<<0) /* execute hwsync */ +#define SNDRV_PCM_SYNC_PTR_APPL (1<<1) /* get appl_ptr from driver (r/w op) */ +#define SNDRV_PCM_SYNC_PTR_AVAIL_MIN (1<<2) /* get avail_min from driver */ + +struct snd_pcm_sync_ptr { + unsigned int flags; + union { + struct snd_pcm_mmap_status status; + unsigned char reserved[64]; + } s; + union { + struct snd_pcm_mmap_control control; + unsigned char reserved[64]; + } c; +}; + +struct snd_xferi { + snd_pcm_sframes_t result; + void __user *buf; + snd_pcm_uframes_t frames; +}; + +struct snd_xfern { + snd_pcm_sframes_t result; + void __user * __user *bufs; + snd_pcm_uframes_t frames; +}; + +enum { + SNDRV_PCM_TSTAMP_TYPE_GETTIMEOFDAY = 0, /* gettimeofday equivalent */ + SNDRV_PCM_TSTAMP_TYPE_MONOTONIC, /* posix_clock_monotonic equivalent */ + SNDRV_PCM_TSTAMP_TYPE_LAST = SNDRV_PCM_TSTAMP_TYPE_MONOTONIC, +}; + +/* channel positions */ +enum { + SNDRV_CHMAP_UNKNOWN = 0, + SNDRV_CHMAP_NA, /* N/A, silent */ + SNDRV_CHMAP_MONO, /* mono stream */ + /* this follows the alsa-lib mixer channel value + 3 */ + SNDRV_CHMAP_FL, /* front left */ + SNDRV_CHMAP_FR, /* front right */ + SNDRV_CHMAP_RL, /* rear left */ + SNDRV_CHMAP_RR, /* rear right */ + SNDRV_CHMAP_FC, /* front center */ + SNDRV_CHMAP_LFE, /* LFE */ + SNDRV_CHMAP_SL, /* side left */ + SNDRV_CHMAP_SR, /* side right */ + SNDRV_CHMAP_RC, /* rear center */ + /* new definitions */ + SNDRV_CHMAP_FLC, /* front left center */ + SNDRV_CHMAP_FRC, /* front right center */ + SNDRV_CHMAP_RLC, /* rear left center */ + SNDRV_CHMAP_RRC, /* rear right center */ + SNDRV_CHMAP_FLW, /* front left wide */ + SNDRV_CHMAP_FRW, /* front right wide */ + SNDRV_CHMAP_FLH, /* front left high */ + SNDRV_CHMAP_FCH, /* front center high */ + SNDRV_CHMAP_FRH, /* front right high */ + SNDRV_CHMAP_TC, /* top center */ + SNDRV_CHMAP_TFL, /* top front left */ + SNDRV_CHMAP_TFR, /* top front right */ + SNDRV_CHMAP_TFC, /* top front center */ + SNDRV_CHMAP_TRL, /* top rear left */ + SNDRV_CHMAP_TRR, /* top rear right */ + SNDRV_CHMAP_TRC, /* top rear center */ + /* new definitions for UAC2 */ + SNDRV_CHMAP_TFLC, /* top front left center */ + SNDRV_CHMAP_TFRC, /* top front right center */ + SNDRV_CHMAP_TSL, /* top side left */ + SNDRV_CHMAP_TSR, /* top side right */ + SNDRV_CHMAP_LLFE, /* left LFE */ + SNDRV_CHMAP_RLFE, /* right LFE */ + SNDRV_CHMAP_BC, /* bottom center */ + SNDRV_CHMAP_BLC, /* bottom left center */ + SNDRV_CHMAP_BRC, /* bottom right center */ + SNDRV_CHMAP_LAST = SNDRV_CHMAP_BRC, +}; + +#define SNDRV_CHMAP_POSITION_MASK 0xffff +#define SNDRV_CHMAP_PHASE_INVERSE (0x01 << 16) +#define SNDRV_CHMAP_DRIVER_SPEC (0x02 << 16) + +#define SNDRV_PCM_IOCTL_PVERSION _IOR('A', 0x00, int) +#define SNDRV_PCM_IOCTL_INFO _IOR('A', 0x01, struct snd_pcm_info) +#define SNDRV_PCM_IOCTL_TSTAMP _IOW('A', 0x02, int) +#define SNDRV_PCM_IOCTL_TTSTAMP _IOW('A', 0x03, int) +#define SNDRV_PCM_IOCTL_HW_REFINE _IOWR('A', 0x10, struct snd_pcm_hw_params) +#define SNDRV_PCM_IOCTL_HW_PARAMS _IOWR('A', 0x11, struct snd_pcm_hw_params) +#define SNDRV_PCM_IOCTL_HW_FREE _IO('A', 0x12) +#define SNDRV_PCM_IOCTL_SW_PARAMS _IOWR('A', 0x13, struct snd_pcm_sw_params) +#define SNDRV_PCM_IOCTL_STATUS _IOR('A', 0x20, struct snd_pcm_status) +#define SNDRV_PCM_IOCTL_DELAY _IOR('A', 0x21, snd_pcm_sframes_t) +#define SNDRV_PCM_IOCTL_HWSYNC _IO('A', 0x22) +#define SNDRV_PCM_IOCTL_SYNC_PTR _IOWR('A', 0x23, struct snd_pcm_sync_ptr) +#define SNDRV_PCM_IOCTL_CHANNEL_INFO _IOR('A', 0x32, struct snd_pcm_channel_info) +#define SNDRV_PCM_IOCTL_PREPARE _IO('A', 0x40) +#define SNDRV_PCM_IOCTL_RESET _IO('A', 0x41) +#define SNDRV_PCM_IOCTL_START _IO('A', 0x42) +#define SNDRV_PCM_IOCTL_DROP _IO('A', 0x43) +#define SNDRV_PCM_IOCTL_DRAIN _IO('A', 0x44) +#define SNDRV_PCM_IOCTL_PAUSE _IOW('A', 0x45, int) +#define SNDRV_PCM_IOCTL_REWIND _IOW('A', 0x46, snd_pcm_uframes_t) +#define SNDRV_PCM_IOCTL_RESUME _IO('A', 0x47) +#define SNDRV_PCM_IOCTL_XRUN _IO('A', 0x48) +#define SNDRV_PCM_IOCTL_FORWARD _IOW('A', 0x49, snd_pcm_uframes_t) +#define SNDRV_PCM_IOCTL_WRITEI_FRAMES _IOW('A', 0x50, struct snd_xferi) +#define SNDRV_PCM_IOCTL_READI_FRAMES _IOR('A', 0x51, struct snd_xferi) +#define SNDRV_PCM_IOCTL_WRITEN_FRAMES _IOW('A', 0x52, struct snd_xfern) +#define SNDRV_PCM_IOCTL_READN_FRAMES _IOR('A', 0x53, struct snd_xfern) +#define SNDRV_PCM_IOCTL_LINK _IOW('A', 0x60, int) +#define SNDRV_PCM_IOCTL_UNLINK _IO('A', 0x61) + +/***************************************************************************** + * * + * MIDI v1.0 interface * + * * + *****************************************************************************/ + +/* + * Raw MIDI section - /dev/snd/midi?? + */ + +#define SNDRV_RAWMIDI_VERSION SNDRV_PROTOCOL_VERSION(2, 0, 0) + +enum { + SNDRV_RAWMIDI_STREAM_OUTPUT = 0, + SNDRV_RAWMIDI_STREAM_INPUT, + SNDRV_RAWMIDI_STREAM_LAST = SNDRV_RAWMIDI_STREAM_INPUT, +}; + +#define SNDRV_RAWMIDI_INFO_OUTPUT 0x00000001 +#define SNDRV_RAWMIDI_INFO_INPUT 0x00000002 +#define SNDRV_RAWMIDI_INFO_DUPLEX 0x00000004 + +struct snd_rawmidi_info { + unsigned int device; /* RO/WR (control): device number */ + unsigned int subdevice; /* RO/WR (control): subdevice number */ + int stream; /* WR: stream */ + int card; /* R: card number */ + unsigned int flags; /* SNDRV_RAWMIDI_INFO_XXXX */ + unsigned char id[64]; /* ID (user selectable) */ + unsigned char name[80]; /* name of device */ + unsigned char subname[32]; /* name of active or selected subdevice */ + unsigned int subdevices_count; + unsigned int subdevices_avail; + unsigned char reserved[64]; /* reserved for future use */ +}; + +struct snd_rawmidi_params { + int stream; + size_t buffer_size; /* queue size in bytes */ + size_t avail_min; /* minimum avail bytes for wakeup */ + unsigned int no_active_sensing: 1; /* do not send active sensing byte in close() */ + unsigned char reserved[16]; /* reserved for future use */ +}; + +struct snd_rawmidi_status { + int stream; + struct timespec tstamp; /* Timestamp */ + size_t avail; /* available bytes */ + size_t xruns; /* count of overruns since last status (in bytes) */ + unsigned char reserved[16]; /* reserved for future use */ +}; + +#define SNDRV_RAWMIDI_IOCTL_PVERSION _IOR('W', 0x00, int) +#define SNDRV_RAWMIDI_IOCTL_INFO _IOR('W', 0x01, struct snd_rawmidi_info) +#define SNDRV_RAWMIDI_IOCTL_PARAMS _IOWR('W', 0x10, struct snd_rawmidi_params) +#define SNDRV_RAWMIDI_IOCTL_STATUS _IOWR('W', 0x20, struct snd_rawmidi_status) +#define SNDRV_RAWMIDI_IOCTL_DROP _IOW('W', 0x30, int) +#define SNDRV_RAWMIDI_IOCTL_DRAIN _IOW('W', 0x31, int) + +/* + * Timer section - /dev/snd/timer + */ + +#define SNDRV_TIMER_VERSION SNDRV_PROTOCOL_VERSION(2, 0, 6) + +enum { + SNDRV_TIMER_CLASS_NONE = -1, + SNDRV_TIMER_CLASS_SLAVE = 0, + SNDRV_TIMER_CLASS_GLOBAL, + SNDRV_TIMER_CLASS_CARD, + SNDRV_TIMER_CLASS_PCM, + SNDRV_TIMER_CLASS_LAST = SNDRV_TIMER_CLASS_PCM, +}; + +/* slave timer classes */ +enum { + SNDRV_TIMER_SCLASS_NONE = 0, + SNDRV_TIMER_SCLASS_APPLICATION, + SNDRV_TIMER_SCLASS_SEQUENCER, /* alias */ + SNDRV_TIMER_SCLASS_OSS_SEQUENCER, /* alias */ + SNDRV_TIMER_SCLASS_LAST = SNDRV_TIMER_SCLASS_OSS_SEQUENCER, +}; + +/* global timers (device member) */ +#define SNDRV_TIMER_GLOBAL_SYSTEM 0 +#define SNDRV_TIMER_GLOBAL_RTC 1 +#define SNDRV_TIMER_GLOBAL_HPET 2 +#define SNDRV_TIMER_GLOBAL_HRTIMER 3 + +/* info flags */ +#define SNDRV_TIMER_FLG_SLAVE (1<<0) /* cannot be controlled */ + +struct snd_timer_id { + int dev_class; + int dev_sclass; + int card; + int device; + int subdevice; +}; + +struct snd_timer_ginfo { + struct snd_timer_id tid; /* requested timer ID */ + unsigned int flags; /* timer flags - SNDRV_TIMER_FLG_* */ + int card; /* card number */ + unsigned char id[64]; /* timer identification */ + unsigned char name[80]; /* timer name */ + unsigned long reserved0; /* reserved for future use */ + unsigned long resolution; /* average period resolution in ns */ + unsigned long resolution_min; /* minimal period resolution in ns */ + unsigned long resolution_max; /* maximal period resolution in ns */ + unsigned int clients; /* active timer clients */ + unsigned char reserved[32]; +}; + +struct snd_timer_gparams { + struct snd_timer_id tid; /* requested timer ID */ + unsigned long period_num; /* requested precise period duration (in seconds) - numerator */ + unsigned long period_den; /* requested precise period duration (in seconds) - denominator */ + unsigned char reserved[32]; +}; + +struct snd_timer_gstatus { + struct snd_timer_id tid; /* requested timer ID */ + unsigned long resolution; /* current period resolution in ns */ + unsigned long resolution_num; /* precise current period resolution (in seconds) - numerator */ + unsigned long resolution_den; /* precise current period resolution (in seconds) - denominator */ + unsigned char reserved[32]; +}; + +struct snd_timer_select { + struct snd_timer_id id; /* bind to timer ID */ + unsigned char reserved[32]; /* reserved */ +}; + +struct snd_timer_info { + unsigned int flags; /* timer flags - SNDRV_TIMER_FLG_* */ + int card; /* card number */ + unsigned char id[64]; /* timer identificator */ + unsigned char name[80]; /* timer name */ + unsigned long reserved0; /* reserved for future use */ + unsigned long resolution; /* average period resolution in ns */ + unsigned char reserved[64]; /* reserved */ +}; + +#define SNDRV_TIMER_PSFLG_AUTO (1<<0) /* auto start, otherwise one-shot */ +#define SNDRV_TIMER_PSFLG_EXCLUSIVE (1<<1) /* exclusive use, precise start/stop/pause/continue */ +#define SNDRV_TIMER_PSFLG_EARLY_EVENT (1<<2) /* write early event to the poll queue */ + +struct snd_timer_params { + unsigned int flags; /* flags - SNDRV_MIXER_PSFLG_* */ + unsigned int ticks; /* requested resolution in ticks */ + unsigned int queue_size; /* total size of queue (32-1024) */ + unsigned int reserved0; /* reserved, was: failure locations */ + unsigned int filter; /* event filter (bitmask of SNDRV_TIMER_EVENT_*) */ + unsigned char reserved[60]; /* reserved */ +}; + +struct snd_timer_status { + struct timespec tstamp; /* Timestamp - last update */ + unsigned int resolution; /* current period resolution in ns */ + unsigned int lost; /* counter of master tick lost */ + unsigned int overrun; /* count of read queue overruns */ + unsigned int queue; /* used queue size */ + unsigned char reserved[64]; /* reserved */ +}; + +#define SNDRV_TIMER_IOCTL_PVERSION _IOR('T', 0x00, int) +#define SNDRV_TIMER_IOCTL_NEXT_DEVICE _IOWR('T', 0x01, struct snd_timer_id) +#define SNDRV_TIMER_IOCTL_TREAD _IOW('T', 0x02, int) +#define SNDRV_TIMER_IOCTL_GINFO _IOWR('T', 0x03, struct snd_timer_ginfo) +#define SNDRV_TIMER_IOCTL_GPARAMS _IOW('T', 0x04, struct snd_timer_gparams) +#define SNDRV_TIMER_IOCTL_GSTATUS _IOWR('T', 0x05, struct snd_timer_gstatus) +#define SNDRV_TIMER_IOCTL_SELECT _IOW('T', 0x10, struct snd_timer_select) +#define SNDRV_TIMER_IOCTL_INFO _IOR('T', 0x11, struct snd_timer_info) +#define SNDRV_TIMER_IOCTL_PARAMS _IOW('T', 0x12, struct snd_timer_params) +#define SNDRV_TIMER_IOCTL_STATUS _IOR('T', 0x14, struct snd_timer_status) +/* The following four ioctls are changed since 1.0.9 due to confliction */ +#define SNDRV_TIMER_IOCTL_START _IO('T', 0xa0) +#define SNDRV_TIMER_IOCTL_STOP _IO('T', 0xa1) +#define SNDRV_TIMER_IOCTL_CONTINUE _IO('T', 0xa2) +#define SNDRV_TIMER_IOCTL_PAUSE _IO('T', 0xa3) + +struct snd_timer_read { + unsigned int resolution; + unsigned int ticks; +}; + +enum { + SNDRV_TIMER_EVENT_RESOLUTION = 0, /* val = resolution in ns */ + SNDRV_TIMER_EVENT_TICK, /* val = ticks */ + SNDRV_TIMER_EVENT_START, /* val = resolution in ns */ + SNDRV_TIMER_EVENT_STOP, /* val = 0 */ + SNDRV_TIMER_EVENT_CONTINUE, /* val = resolution in ns */ + SNDRV_TIMER_EVENT_PAUSE, /* val = 0 */ + SNDRV_TIMER_EVENT_EARLY, /* val = 0, early event */ + SNDRV_TIMER_EVENT_SUSPEND, /* val = 0 */ + SNDRV_TIMER_EVENT_RESUME, /* val = resolution in ns */ + /* master timer events for slave timer instances */ + SNDRV_TIMER_EVENT_MSTART = SNDRV_TIMER_EVENT_START + 10, + SNDRV_TIMER_EVENT_MSTOP = SNDRV_TIMER_EVENT_STOP + 10, + SNDRV_TIMER_EVENT_MCONTINUE = SNDRV_TIMER_EVENT_CONTINUE + 10, + SNDRV_TIMER_EVENT_MPAUSE = SNDRV_TIMER_EVENT_PAUSE + 10, + SNDRV_TIMER_EVENT_MSUSPEND = SNDRV_TIMER_EVENT_SUSPEND + 10, + SNDRV_TIMER_EVENT_MRESUME = SNDRV_TIMER_EVENT_RESUME + 10, +}; + +struct snd_timer_tread { + int event; + struct timespec tstamp; + unsigned int val; +}; + +/**************************************************************************** + * * + * Section for driver control interface - /dev/snd/control? * + * * + ****************************************************************************/ + +#define SNDRV_CTL_VERSION SNDRV_PROTOCOL_VERSION(2, 0, 7) + +struct snd_ctl_card_info { + int card; /* card number */ + int pad; /* reserved for future (was type) */ + unsigned char id[16]; /* ID of card (user selectable) */ + unsigned char driver[16]; /* Driver name */ + unsigned char name[32]; /* Short name of soundcard */ + unsigned char longname[80]; /* name + info text about soundcard */ + unsigned char reserved_[16]; /* reserved for future (was ID of mixer) */ + unsigned char mixername[80]; /* visual mixer identification */ + unsigned char components[128]; /* card components / fine identification, delimited with one space (AC97 etc..) */ +}; + +typedef int __bitwise snd_ctl_elem_type_t; +#define SNDRV_CTL_ELEM_TYPE_NONE ((__force snd_ctl_elem_type_t) 0) /* invalid */ +#define SNDRV_CTL_ELEM_TYPE_BOOLEAN ((__force snd_ctl_elem_type_t) 1) /* boolean type */ +#define SNDRV_CTL_ELEM_TYPE_INTEGER ((__force snd_ctl_elem_type_t) 2) /* integer type */ +#define SNDRV_CTL_ELEM_TYPE_ENUMERATED ((__force snd_ctl_elem_type_t) 3) /* enumerated type */ +#define SNDRV_CTL_ELEM_TYPE_BYTES ((__force snd_ctl_elem_type_t) 4) /* byte array */ +#define SNDRV_CTL_ELEM_TYPE_IEC958 ((__force snd_ctl_elem_type_t) 5) /* IEC958 (S/PDIF) setup */ +#define SNDRV_CTL_ELEM_TYPE_INTEGER64 ((__force snd_ctl_elem_type_t) 6) /* 64-bit integer type */ +#define SNDRV_CTL_ELEM_TYPE_LAST SNDRV_CTL_ELEM_TYPE_INTEGER64 + +typedef int __bitwise snd_ctl_elem_iface_t; +#define SNDRV_CTL_ELEM_IFACE_CARD ((__force snd_ctl_elem_iface_t) 0) /* global control */ +#define SNDRV_CTL_ELEM_IFACE_HWDEP ((__force snd_ctl_elem_iface_t) 1) /* hardware dependent device */ +#define SNDRV_CTL_ELEM_IFACE_MIXER ((__force snd_ctl_elem_iface_t) 2) /* virtual mixer device */ +#define SNDRV_CTL_ELEM_IFACE_PCM ((__force snd_ctl_elem_iface_t) 3) /* PCM device */ +#define SNDRV_CTL_ELEM_IFACE_RAWMIDI ((__force snd_ctl_elem_iface_t) 4) /* RawMidi device */ +#define SNDRV_CTL_ELEM_IFACE_TIMER ((__force snd_ctl_elem_iface_t) 5) /* timer device */ +#define SNDRV_CTL_ELEM_IFACE_SEQUENCER ((__force snd_ctl_elem_iface_t) 6) /* sequencer client */ +#define SNDRV_CTL_ELEM_IFACE_LAST SNDRV_CTL_ELEM_IFACE_SEQUENCER + +#define SNDRV_CTL_ELEM_ACCESS_READ (1<<0) +#define SNDRV_CTL_ELEM_ACCESS_WRITE (1<<1) +#define SNDRV_CTL_ELEM_ACCESS_READWRITE (SNDRV_CTL_ELEM_ACCESS_READ|SNDRV_CTL_ELEM_ACCESS_WRITE) +#define SNDRV_CTL_ELEM_ACCESS_VOLATILE (1<<2) /* control value may be changed without a notification */ +#define SNDRV_CTL_ELEM_ACCESS_TIMESTAMP (1<<3) /* when was control changed */ +#define SNDRV_CTL_ELEM_ACCESS_TLV_READ (1<<4) /* TLV read is possible */ +#define SNDRV_CTL_ELEM_ACCESS_TLV_WRITE (1<<5) /* TLV write is possible */ +#define SNDRV_CTL_ELEM_ACCESS_TLV_READWRITE (SNDRV_CTL_ELEM_ACCESS_TLV_READ|SNDRV_CTL_ELEM_ACCESS_TLV_WRITE) +#define SNDRV_CTL_ELEM_ACCESS_TLV_COMMAND (1<<6) /* TLV command is possible */ +#define SNDRV_CTL_ELEM_ACCESS_INACTIVE (1<<8) /* control does actually nothing, but may be updated */ +#define SNDRV_CTL_ELEM_ACCESS_LOCK (1<<9) /* write lock */ +#define SNDRV_CTL_ELEM_ACCESS_OWNER (1<<10) /* write lock owner */ +#define SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK (1<<28) /* kernel use a TLV callback */ +#define SNDRV_CTL_ELEM_ACCESS_USER (1<<29) /* user space element */ +/* bits 30 and 31 are obsoleted (for indirect access) */ + +/* for further details see the ACPI and PCI power management specification */ +#define SNDRV_CTL_POWER_D0 0x0000 /* full On */ +#define SNDRV_CTL_POWER_D1 0x0100 /* partial On */ +#define SNDRV_CTL_POWER_D2 0x0200 /* partial On */ +#define SNDRV_CTL_POWER_D3 0x0300 /* Off */ +#define SNDRV_CTL_POWER_D3hot (SNDRV_CTL_POWER_D3|0x0000) /* Off, with power */ +#define SNDRV_CTL_POWER_D3cold (SNDRV_CTL_POWER_D3|0x0001) /* Off, without power */ + +struct snd_ctl_elem_id { + unsigned int numid; /* numeric identifier, zero = invalid */ + snd_ctl_elem_iface_t iface; /* interface identifier */ + unsigned int device; /* device/client number */ + unsigned int subdevice; /* subdevice (substream) number */ + unsigned char name[44]; /* ASCII name of item */ + unsigned int index; /* index of item */ +}; + +struct snd_ctl_elem_list { + unsigned int offset; /* W: first element ID to get */ + unsigned int space; /* W: count of element IDs to get */ + unsigned int used; /* R: count of element IDs set */ + unsigned int count; /* R: count of all elements */ + struct snd_ctl_elem_id __user *pids; /* R: IDs */ + unsigned char reserved[50]; +}; + +struct snd_ctl_elem_info { + struct snd_ctl_elem_id id; /* W: element ID */ + snd_ctl_elem_type_t type; /* R: value type - SNDRV_CTL_ELEM_TYPE_* */ + unsigned int access; /* R: value access (bitmask) - SNDRV_CTL_ELEM_ACCESS_* */ + unsigned int count; /* count of values */ + __kernel_pid_t owner; /* owner's PID of this control */ + union { + struct { + long min; /* R: minimum value */ + long max; /* R: maximum value */ + long step; /* R: step (0 variable) */ + } integer; + struct { + long long min; /* R: minimum value */ + long long max; /* R: maximum value */ + long long step; /* R: step (0 variable) */ + } integer64; + struct { + unsigned int items; /* R: number of items */ + unsigned int item; /* W: item number */ + char name[64]; /* R: value name */ + __u64 names_ptr; /* W: names list (ELEM_ADD only) */ + unsigned int names_length; + } enumerated; + unsigned char reserved[128]; + } value; + union { + unsigned short d[4]; /* dimensions */ + unsigned short *d_ptr; /* indirect - obsoleted */ + } dimen; + unsigned char reserved[64-4*sizeof(unsigned short)]; +}; + +struct snd_ctl_elem_value { + struct snd_ctl_elem_id id; /* W: element ID */ + unsigned int indirect: 1; /* W: indirect access - obsoleted */ + union { + union { + long value[128]; + long *value_ptr; /* obsoleted */ + } integer; + union { + long long value[64]; + long long *value_ptr; /* obsoleted */ + } integer64; + union { + unsigned int item[128]; + unsigned int *item_ptr; /* obsoleted */ + } enumerated; + union { + unsigned char data[512]; + unsigned char *data_ptr; /* obsoleted */ + } bytes; + struct snd_aes_iec958 iec958; + } value; /* RO */ + struct timespec tstamp; + unsigned char reserved[128-sizeof(struct timespec)]; +}; + +struct snd_ctl_tlv { + unsigned int numid; /* control element numeric identification */ + unsigned int length; /* in bytes aligned to 4 */ + unsigned int tlv[0]; /* first TLV */ +}; + +#define SNDRV_CTL_IOCTL_PVERSION _IOR('U', 0x00, int) +#define SNDRV_CTL_IOCTL_CARD_INFO _IOR('U', 0x01, struct snd_ctl_card_info) +#define SNDRV_CTL_IOCTL_ELEM_LIST _IOWR('U', 0x10, struct snd_ctl_elem_list) +#define SNDRV_CTL_IOCTL_ELEM_INFO _IOWR('U', 0x11, struct snd_ctl_elem_info) +#define SNDRV_CTL_IOCTL_ELEM_READ _IOWR('U', 0x12, struct snd_ctl_elem_value) +#define SNDRV_CTL_IOCTL_ELEM_WRITE _IOWR('U', 0x13, struct snd_ctl_elem_value) +#define SNDRV_CTL_IOCTL_ELEM_LOCK _IOW('U', 0x14, struct snd_ctl_elem_id) +#define SNDRV_CTL_IOCTL_ELEM_UNLOCK _IOW('U', 0x15, struct snd_ctl_elem_id) +#define SNDRV_CTL_IOCTL_SUBSCRIBE_EVENTS _IOWR('U', 0x16, int) +#define SNDRV_CTL_IOCTL_ELEM_ADD _IOWR('U', 0x17, struct snd_ctl_elem_info) +#define SNDRV_CTL_IOCTL_ELEM_REPLACE _IOWR('U', 0x18, struct snd_ctl_elem_info) +#define SNDRV_CTL_IOCTL_ELEM_REMOVE _IOWR('U', 0x19, struct snd_ctl_elem_id) +#define SNDRV_CTL_IOCTL_TLV_READ _IOWR('U', 0x1a, struct snd_ctl_tlv) +#define SNDRV_CTL_IOCTL_TLV_WRITE _IOWR('U', 0x1b, struct snd_ctl_tlv) +#define SNDRV_CTL_IOCTL_TLV_COMMAND _IOWR('U', 0x1c, struct snd_ctl_tlv) +#define SNDRV_CTL_IOCTL_HWDEP_NEXT_DEVICE _IOWR('U', 0x20, int) +#define SNDRV_CTL_IOCTL_HWDEP_INFO _IOR('U', 0x21, struct snd_hwdep_info) +#define SNDRV_CTL_IOCTL_PCM_NEXT_DEVICE _IOR('U', 0x30, int) +#define SNDRV_CTL_IOCTL_PCM_INFO _IOWR('U', 0x31, struct snd_pcm_info) +#define SNDRV_CTL_IOCTL_PCM_PREFER_SUBDEVICE _IOW('U', 0x32, int) +#define SNDRV_CTL_IOCTL_RAWMIDI_NEXT_DEVICE _IOWR('U', 0x40, int) +#define SNDRV_CTL_IOCTL_RAWMIDI_INFO _IOWR('U', 0x41, struct snd_rawmidi_info) +#define SNDRV_CTL_IOCTL_RAWMIDI_PREFER_SUBDEVICE _IOW('U', 0x42, int) +#define SNDRV_CTL_IOCTL_POWER _IOWR('U', 0xd0, int) +#define SNDRV_CTL_IOCTL_POWER_STATE _IOR('U', 0xd1, int) + +/* + * Read interface. + */ + +enum sndrv_ctl_event_type { + SNDRV_CTL_EVENT_ELEM = 0, + SNDRV_CTL_EVENT_LAST = SNDRV_CTL_EVENT_ELEM, +}; + +#define SNDRV_CTL_EVENT_MASK_VALUE (1<<0) /* element value was changed */ +#define SNDRV_CTL_EVENT_MASK_INFO (1<<1) /* element info was changed */ +#define SNDRV_CTL_EVENT_MASK_ADD (1<<2) /* element was added */ +#define SNDRV_CTL_EVENT_MASK_TLV (1<<3) /* element TLV tree was changed */ +#define SNDRV_CTL_EVENT_MASK_REMOVE (~0U) /* element was removed */ + +struct snd_ctl_event { + int type; /* event type - SNDRV_CTL_EVENT_* */ + union { + struct { + unsigned int mask; + struct snd_ctl_elem_id id; + } elem; + unsigned char data8[60]; + } data; +}; + +/* + * Control names + */ + +#define SNDRV_CTL_NAME_NONE "" +#define SNDRV_CTL_NAME_PLAYBACK "Playback " +#define SNDRV_CTL_NAME_CAPTURE "Capture " + +#define SNDRV_CTL_NAME_IEC958_NONE "" +#define SNDRV_CTL_NAME_IEC958_SWITCH "Switch" +#define SNDRV_CTL_NAME_IEC958_VOLUME "Volume" +#define SNDRV_CTL_NAME_IEC958_DEFAULT "Default" +#define SNDRV_CTL_NAME_IEC958_MASK "Mask" +#define SNDRV_CTL_NAME_IEC958_CON_MASK "Con Mask" +#define SNDRV_CTL_NAME_IEC958_PRO_MASK "Pro Mask" +#define SNDRV_CTL_NAME_IEC958_PCM_STREAM "PCM Stream" +#define SNDRV_CTL_NAME_IEC958(expl,direction,what) "IEC958 " expl SNDRV_CTL_NAME_##direction SNDRV_CTL_NAME_IEC958_##what + +#endif /* _UAPI__SOUND_ASOUND_H */ diff --git a/original-kernel-headers/sound/audio_effects.h b/original-kernel-headers/sound/audio_effects.h new file mode 100644 index 0000000..e922ff7 --- /dev/null +++ b/original-kernel-headers/sound/audio_effects.h @@ -0,0 +1,321 @@ +/* + * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _AUDIO_EFFECTS_H +#define _AUDIO_EFFECTS_H + +/** AUDIO EFFECTS **/ + + +/* CONFIG GET/SET */ +#define CONFIG_CACHE 0 +#define CONFIG_SET 1 +#define CONFIG_GET 2 + +/* CONFIG HEADER */ +/* + + MODULE_ID, + DEVICE, + NUM_COMMANDS, + COMMAND_ID_1, + CONFIG_CACHE/SET/GET, + OFFSET_1, + LENGTH_1, + VALUES_1, + ..., + ..., + COMMAND_ID_2, + CONFIG_CACHE/SET/GET, + OFFSET_2, + LENGTH_2, + VALUES_2, + ..., + ..., + COMMAND_ID_3, + ... +*/ + + +/* CONFIG PARAM IDs */ +#define VIRTUALIZER_MODULE 0x00001000 +#define VIRTUALIZER_ENABLE 0x00001001 +#define VIRTUALIZER_STRENGTH 0x00001002 +#define VIRTUALIZER_OUT_TYPE 0x00001003 +#define VIRTUALIZER_GAIN_ADJUST 0x00001004 +#define VIRTUALIZER_ENABLE_PARAM_LEN 1 +#define VIRTUALIZER_STRENGTH_PARAM_LEN 1 +#define VIRTUALIZER_OUT_TYPE_PARAM_LEN 1 +#define VIRTUALIZER_GAIN_ADJUST_PARAM_LEN 1 + +#define REVERB_MODULE 0x00002000 +#define REVERB_ENABLE 0x00002001 +#define REVERB_MODE 0x00002002 +#define REVERB_PRESET 0x00002003 +#define REVERB_WET_MIX 0x00002004 +#define REVERB_GAIN_ADJUST 0x00002005 +#define REVERB_ROOM_LEVEL 0x00002006 +#define REVERB_ROOM_HF_LEVEL 0x00002007 +#define REVERB_DECAY_TIME 0x00002008 +#define REVERB_DECAY_HF_RATIO 0x00002009 +#define REVERB_REFLECTIONS_LEVEL 0x0000200a +#define REVERB_REFLECTIONS_DELAY 0x0000200b +#define REVERB_LEVEL 0x0000200c +#define REVERB_DELAY 0x0000200d +#define REVERB_DIFFUSION 0x0000200e +#define REVERB_DENSITY 0x0000200f +#define REVERB_ENABLE_PARAM_LEN 1 +#define REVERB_MODE_PARAM_LEN 1 +#define REVERB_PRESET_PARAM_LEN 1 +#define REVERB_WET_MIX_PARAM_LEN 1 +#define REVERB_GAIN_ADJUST_PARAM_LEN 1 +#define REVERB_ROOM_LEVEL_PARAM_LEN 1 +#define REVERB_ROOM_HF_LEVEL_PARAM_LEN 1 +#define REVERB_DECAY_TIME_PARAM_LEN 1 +#define REVERB_DECAY_HF_RATIO_PARAM_LEN 1 +#define REVERB_REFLECTIONS_LEVEL_PARAM_LEN 1 +#define REVERB_REFLECTIONS_DELAY_PARAM_LEN 1 +#define REVERB_LEVEL_PARAM_LEN 1 +#define REVERB_DELAY_PARAM_LEN 1 +#define REVERB_DIFFUSION_PARAM_LEN 1 +#define REVERB_DENSITY_PARAM_LEN 1 + +#define BASS_BOOST_MODULE 0x00003000 +#define BASS_BOOST_ENABLE 0x00003001 +#define BASS_BOOST_MODE 0x00003002 +#define BASS_BOOST_STRENGTH 0x00003003 +#define BASS_BOOST_ENABLE_PARAM_LEN 1 +#define BASS_BOOST_MODE_PARAM_LEN 1 +#define BASS_BOOST_STRENGTH_PARAM_LEN 1 + +#define EQ_MODULE 0x00004000 +#define EQ_ENABLE 0x00004001 +#define EQ_CONFIG 0x00004002 +#define EQ_NUM_BANDS 0x00004003 +#define EQ_BAND_LEVELS 0x00004004 +#define EQ_BAND_LEVEL_RANGE 0x00004005 +#define EQ_BAND_FREQS 0x00004006 +#define EQ_SINGLE_BAND_FREQ_RANGE 0x00004007 +#define EQ_SINGLE_BAND_FREQ 0x00004008 +#define EQ_BAND_INDEX 0x00004009 +#define EQ_PRESET_ID 0x0000400a +#define EQ_NUM_PRESETS 0x0000400b +#define EQ_PRESET_NAME 0x0000400c +#define EQ_ENABLE_PARAM_LEN 1 +#define EQ_CONFIG_PARAM_LEN 3 +#define EQ_CONFIG_PER_BAND_PARAM_LEN 5 +#define EQ_NUM_BANDS_PARAM_LEN 1 +#define EQ_BAND_LEVELS_PARAM_LEN 13 +#define EQ_BAND_LEVEL_RANGE_PARAM_LEN 2 +#define EQ_BAND_FREQS_PARAM_LEN 13 +#define EQ_SINGLE_BAND_FREQ_RANGE_PARAM_LEN 2 +#define EQ_SINGLE_BAND_FREQ_PARAM_LEN 1 +#define EQ_BAND_INDEX_PARAM_LEN 1 +#define EQ_PRESET_ID_PARAM_LEN 1 +#define EQ_NUM_PRESETS_PARAM_LEN 1 +#define EQ_PRESET_NAME_PARAM_LEN 32 + +#define EQ_TYPE_NONE 0 +#define EQ_BASS_BOOST 1 +#define EQ_BASS_CUT 2 +#define EQ_TREBLE_BOOST 3 +#define EQ_TREBLE_CUT 4 +#define EQ_BAND_BOOST 5 +#define EQ_BAND_CUT 6 + +#define SOFT_VOLUME_MODULE 0x00006000 +#define SOFT_VOLUME_ENABLE 0x00006001 +#define SOFT_VOLUME_GAIN_2CH 0x00006002 +#define SOFT_VOLUME_GAIN_MASTER 0x00006003 +#define SOFT_VOLUME_ENABLE_PARAM_LEN 1 +#define SOFT_VOLUME_GAIN_2CH_PARAM_LEN 2 +#define SOFT_VOLUME_GAIN_MASTER_PARAM_LEN 1 + +#define SOFT_VOLUME2_MODULE 0x00007000 +#define SOFT_VOLUME2_ENABLE 0x00007001 +#define SOFT_VOLUME2_GAIN_2CH 0x00007002 +#define SOFT_VOLUME2_GAIN_MASTER 0x00007003 +#define SOFT_VOLUME2_ENABLE_PARAM_LEN SOFT_VOLUME_ENABLE_PARAM_LEN +#define SOFT_VOLUME2_GAIN_2CH_PARAM_LEN SOFT_VOLUME_GAIN_2CH_PARAM_LEN +#define SOFT_VOLUME2_GAIN_MASTER_PARAM_LEN \ + SOFT_VOLUME_GAIN_MASTER_PARAM_LEN + +#define COMMAND_PAYLOAD_LEN 3 +#define COMMAND_PAYLOAD_SZ (COMMAND_PAYLOAD_LEN * sizeof(uint32_t)) +#define MAX_INBAND_PARAM_SZ 4096 +#define Q27_UNITY (1 << 27) +#define Q8_UNITY (1 << 8) +#define CUSTOM_OPENSL_PRESET 18 + +#define VIRTUALIZER_ENABLE_PARAM_SZ \ + (VIRTUALIZER_ENABLE_PARAM_LEN*sizeof(uint32_t)) +#define VIRTUALIZER_STRENGTH_PARAM_SZ \ + (VIRTUALIZER_STRENGTH_PARAM_LEN*sizeof(uint32_t)) +#define VIRTUALIZER_OUT_TYPE_PARAM_SZ \ + (VIRTUALIZER_OUT_TYPE_PARAM_LEN*sizeof(uint32_t)) +#define VIRTUALIZER_GAIN_ADJUST_PARAM_SZ \ + (VIRTUALIZER_GAIN_ADJUST_PARAM_LEN*sizeof(uint32_t)) +struct virtualizer_params { + uint32_t device; + uint32_t enable_flag; + uint32_t strength; + uint32_t out_type; + int32_t gain_adjust; +}; + +#define NUM_OSL_REVERB_PRESETS_SUPPORTED 6 +#define REVERB_ENABLE_PARAM_SZ \ + (REVERB_ENABLE_PARAM_LEN*sizeof(uint32_t)) +#define REVERB_MODE_PARAM_SZ \ + (REVERB_MODE_PARAM_LEN*sizeof(uint32_t)) +#define REVERB_PRESET_PARAM_SZ \ + (REVERB_PRESET_PARAM_LEN*sizeof(uint32_t)) +#define REVERB_WET_MIX_PARAM_SZ \ + (REVERB_WET_MIX_PARAM_LEN*sizeof(uint32_t)) +#define REVERB_GAIN_ADJUST_PARAM_SZ \ + (REVERB_GAIN_ADJUST_PARAM_LEN*sizeof(uint32_t)) +#define REVERB_ROOM_LEVEL_PARAM_SZ \ + (REVERB_ROOM_LEVEL_PARAM_LEN*sizeof(uint32_t)) +#define REVERB_ROOM_HF_LEVEL_PARAM_SZ \ + (REVERB_ROOM_HF_LEVEL_PARAM_LEN*sizeof(uint32_t)) +#define REVERB_DECAY_TIME_PARAM_SZ \ + (REVERB_DECAY_TIME_PARAM_LEN*sizeof(uint32_t)) +#define REVERB_DECAY_HF_RATIO_PARAM_SZ \ + (REVERB_DECAY_HF_RATIO_PARAM_LEN*sizeof(uint32_t)) +#define REVERB_REFLECTIONS_LEVEL_PARAM_SZ \ + (REVERB_REFLECTIONS_LEVEL_PARAM_LEN*sizeof(uint32_t)) +#define REVERB_REFLECTIONS_DELAY_PARAM_SZ \ + (REVERB_REFLECTIONS_DELAY_PARAM_LEN*sizeof(uint32_t)) +#define REVERB_LEVEL_PARAM_SZ \ + (REVERB_LEVEL_PARAM_LEN*sizeof(uint32_t)) +#define REVERB_DELAY_PARAM_SZ \ + (REVERB_DELAY_PARAM_LEN*sizeof(uint32_t)) +#define REVERB_DIFFUSION_PARAM_SZ \ + (REVERB_DIFFUSION_PARAM_LEN*sizeof(uint32_t)) +#define REVERB_DENSITY_PARAM_SZ \ + (REVERB_DENSITY_PARAM_LEN*sizeof(uint32_t)) +struct reverb_params { + uint32_t device; + uint32_t enable_flag; + uint32_t mode; + uint32_t preset; + uint32_t wet_mix; + int32_t gain_adjust; + int32_t room_level; + int32_t room_hf_level; + uint32_t decay_time; + uint32_t decay_hf_ratio; + int32_t reflections_level; + uint32_t reflections_delay; + int32_t level; + uint32_t delay; + uint32_t diffusion; + uint32_t density; +}; + +#define BASS_BOOST_ENABLE_PARAM_SZ \ + (BASS_BOOST_ENABLE_PARAM_LEN*sizeof(uint32_t)) +#define BASS_BOOST_MODE_PARAM_SZ \ + (BASS_BOOST_MODE_PARAM_LEN*sizeof(uint32_t)) +#define BASS_BOOST_STRENGTH_PARAM_SZ \ + (BASS_BOOST_STRENGTH_PARAM_LEN*sizeof(uint32_t)) +struct bass_boost_params { + uint32_t device; + uint32_t enable_flag; + uint32_t mode; + uint32_t strength; +}; + + +#define MAX_EQ_BANDS 12 +#define MAX_OSL_EQ_BANDS 5 +#define EQ_ENABLE_PARAM_SZ \ + (EQ_ENABLE_PARAM_LEN*sizeof(uint32_t)) +#define EQ_CONFIG_PARAM_SZ \ + (EQ_CONFIG_PARAM_LEN*sizeof(uint32_t)) +#define EQ_CONFIG_PER_BAND_PARAM_SZ \ + (EQ_CONFIG_PER_BAND_PARAM_LEN*sizeof(uint32_t)) +#define EQ_CONFIG_PARAM_MAX_LEN (EQ_CONFIG_PARAM_LEN+\ + MAX_EQ_BANDS*EQ_CONFIG_PER_BAND_PARAM_LEN) +#define EQ_CONFIG_PARAM_MAX_SZ \ + (EQ_CONFIG_PARAM_MAX_LEN*sizeof(uint32_t)) +#define EQ_NUM_BANDS_PARAM_SZ \ + (EQ_NUM_BANDS_PARAM_LEN*sizeof(uint32_t)) +#define EQ_BAND_LEVELS_PARAM_SZ \ + (EQ_BAND_LEVELS_PARAM_LEN*sizeof(uint32_t)) +#define EQ_BAND_LEVEL_RANGE_PARAM_SZ \ + (EQ_BAND_LEVEL_RANGE_PARAM_LEN*sizeof(uint32_t)) +#define EQ_BAND_FREQS_PARAM_SZ \ + (EQ_BAND_FREQS_PARAM_LEN*sizeof(uint32_t)) +#define EQ_SINGLE_BAND_FREQ_RANGE_PARAM_SZ \ + (EQ_SINGLE_BAND_FREQ_RANGE_PARAM_LEN*sizeof(uint32_t)) +#define EQ_SINGLE_BAND_FREQ_PARAM_SZ \ + (EQ_SINGLE_BAND_FREQ_PARAM_LEN*sizeof(uint32_t)) +#define EQ_BAND_INDEX_PARAM_SZ \ + (EQ_BAND_INDEX_PARAM_LEN*sizeof(uint32_t)) +#define EQ_PRESET_ID_PARAM_SZ \ + (EQ_PRESET_ID_PARAM_LEN*sizeof(uint32_t)) +#define EQ_NUM_PRESETS_PARAM_SZ \ + (EQ_NUM_PRESETS_PARAM_LEN*sizeof(uint8_t)) +struct eq_config_t { + int32_t eq_pregain; + int32_t preset_id; + uint32_t num_bands; +}; +struct eq_per_band_config_t { + int32_t band_idx; + uint32_t filter_type; + uint32_t freq_millihertz; + int32_t gain_millibels; + uint32_t quality_factor; +}; +struct eq_per_band_freq_range_t { + uint32_t band_index; + uint32_t min_freq_millihertz; + uint32_t max_freq_millihertz; +}; + +struct eq_params { + uint32_t device; + uint32_t enable_flag; + struct eq_config_t config; + struct eq_per_band_config_t per_band_cfg[MAX_EQ_BANDS]; + struct eq_per_band_freq_range_t per_band_freq_range[MAX_EQ_BANDS]; + uint32_t band_index; + uint32_t freq_millihertz; +}; + +#define SOFT_VOLUME_ENABLE_PARAM_SZ \ + (SOFT_VOLUME_ENABLE_PARAM_LEN*sizeof(uint32_t)) +#define SOFT_VOLUME_GAIN_MASTER_PARAM_SZ \ + (SOFT_VOLUME_GAIN_MASTER_PARAM_LEN*sizeof(uint32_t)) +#define SOFT_VOLUME_GAIN_2CH_PARAM_SZ \ + (SOFT_VOLUME_GAIN_2CH_PARAM_LEN*sizeof(uint16_t)) +struct soft_volume_params { + uint32_t device; + uint32_t enable_flag; + uint32_t master_gain; + uint32_t left_gain; + uint32_t right_gain; +}; + +struct msm_nt_eff_all_config { + struct bass_boost_params bass_boost; + struct virtualizer_params virtualizer; + struct reverb_params reverb; + struct eq_params equalizer; + struct soft_volume_params saplus_vol; + struct soft_volume_params topo_switch_vol; +}; + +#endif /*_MSM_AUDIO_EFFECTS_H*/ diff --git a/original-kernel-headers/sound/compress_offload.h b/original-kernel-headers/sound/compress_offload.h new file mode 100644 index 0000000..5d493a2 --- /dev/null +++ b/original-kernel-headers/sound/compress_offload.h @@ -0,0 +1,203 @@ +/* + * compress_offload.h - compress offload header definations + * + * Copyright (C) 2011 Intel Corporation + * Authors: Vinod Koul <vinod.koul@linux.intel.com> + * Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com> + * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. + * + * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + * + */ +#ifndef __COMPRESS_OFFLOAD_H +#define __COMPRESS_OFFLOAD_H + +#include <linux/types.h> +#include <sound/asound.h> +#include <sound/compress_params.h> + + +#define SNDRV_COMPRESS_VERSION SNDRV_PROTOCOL_VERSION(0, 1, 2) +/** + * struct snd_compressed_buffer: compressed buffer + * @fragment_size: size of buffer fragment in bytes + * @fragments: number of such fragments + */ +struct snd_compressed_buffer { + __u32 fragment_size; + __u32 fragments; +}; + +/** + * struct snd_compr_params: compressed stream params + * @buffer: buffer description + * @codec: codec parameters + * @no_wake_mode: dont wake on fragment elapsed + */ +struct snd_compr_params { + struct snd_compressed_buffer buffer; + struct snd_codec codec; + __u8 no_wake_mode; +}; + +/** + * struct snd_compr_tstamp: timestamp descriptor + * @byte_offset: Byte offset in ring buffer to DSP + * @copied_total: Total number of bytes copied from/to ring buffer to/by DSP + * @pcm_frames: Frames decoded or encoded by DSP. This field will evolve by + * large steps and should only be used to monitor encoding/decoding + * progress. It shall not be used for timing estimates. + * @pcm_io_frames: Frames rendered or received by DSP into a mixer or an audio + * output/input. This field should be used for A/V sync or time estimates. + * @sampling_rate: sampling rate of audio + */ +struct snd_compr_tstamp { + __u32 byte_offset; + __u32 copied_total; + __u32 pcm_frames; + __u32 pcm_io_frames; + __u32 sampling_rate; + uint64_t timestamp; +}; + +/** + * struct snd_compr_avail: avail descriptor + * @avail: Number of bytes available in ring buffer for writing/reading + * @tstamp: timestamp infomation + */ +struct snd_compr_avail { + __u64 avail; + struct snd_compr_tstamp tstamp; +} __attribute__((packed)); + +enum snd_compr_direction { + SND_COMPRESS_PLAYBACK = 0, + SND_COMPRESS_CAPTURE +}; + +/** + * struct snd_compr_caps: caps descriptor + * @codecs: pointer to array of codecs + * @direction: direction supported. Of type snd_compr_direction + * @min_fragment_size: minimum fragment supported by DSP + * @max_fragment_size: maximum fragment supported by DSP + * @min_fragments: min fragments supported by DSP + * @max_fragments: max fragments supported by DSP + * @num_codecs: number of codecs supported + * @reserved: reserved field + */ +struct snd_compr_caps { + __u32 num_codecs; + __u32 direction; + __u32 min_fragment_size; + __u32 max_fragment_size; + __u32 min_fragments; + __u32 max_fragments; + __u32 codecs[MAX_NUM_CODECS]; + __u32 reserved[11]; +}; + +/** + * struct snd_compr_codec_caps: query capability of codec + * @codec: codec for which capability is queried + * @num_descriptors: number of codec descriptors + * @descriptor: array of codec capability descriptor + */ +struct snd_compr_codec_caps { + __u32 codec; + __u32 num_descriptors; + struct snd_codec_desc descriptor[MAX_NUM_CODEC_DESCRIPTORS]; +}; + +/** + * struct snd_compr_audio_info: compressed input audio information + * @frame_size: legth of the encoded frame with valid data + * @reserved: reserved for furture use + */ +struct snd_compr_audio_info { + uint32_t frame_size; + uint32_t reserved[15]; +}; + +/** + * @SNDRV_COMPRESS_ENCODER_PADDING: no of samples appended by the encoder at the + * end of the track + * @SNDRV_COMPRESS_ENCODER_DELAY: no of samples inserted by the encoder at the + * beginning of the track + */ +enum { + SNDRV_COMPRESS_ENCODER_PADDING = 1, + SNDRV_COMPRESS_ENCODER_DELAY = 2, +}; + +/** + * struct snd_compr_metadata: compressed stream metadata + * @key: key id + * @value: key value + */ +struct snd_compr_metadata { + __u32 key; + __u32 value[8]; +}; + +/** + * compress path ioctl definitions + * SNDRV_COMPRESS_GET_CAPS: Query capability of DSP + * SNDRV_COMPRESS_GET_CODEC_CAPS: Query capability of a codec + * SNDRV_COMPRESS_SET_PARAMS: Set codec and stream parameters + * Note: only codec params can be changed runtime and stream params cant be + * SNDRV_COMPRESS_GET_PARAMS: Query codec params + * SNDRV_COMPRESS_TSTAMP: get the current timestamp value + * SNDRV_COMPRESS_AVAIL: get the current buffer avail value. + * This also queries the tstamp properties + * SNDRV_COMPRESS_PAUSE: Pause the running stream + * SNDRV_COMPRESS_RESUME: resume a paused stream + * SNDRV_COMPRESS_START: Start a stream + * SNDRV_COMPRESS_STOP: stop a running stream, discarding ring buffer content + * and the buffers currently with DSP + * SNDRV_COMPRESS_DRAIN: Play till end of buffers and stop after that + * SNDRV_COMPRESS_IOCTL_VERSION: Query the API version + */ +#define SNDRV_COMPRESS_IOCTL_VERSION _IOR('C', 0x00, int) +#define SNDRV_COMPRESS_GET_CAPS _IOWR('C', 0x10, struct snd_compr_caps) +#define SNDRV_COMPRESS_GET_CODEC_CAPS _IOWR('C', 0x11,\ + struct snd_compr_codec_caps) +#define SNDRV_COMPRESS_SET_PARAMS _IOW('C', 0x12, struct snd_compr_params) +#define SNDRV_COMPRESS_GET_PARAMS _IOR('C', 0x13, struct snd_codec) +#define SNDRV_COMPRESS_SET_METADATA _IOW('C', 0x14,\ + struct snd_compr_metadata) +#define SNDRV_COMPRESS_GET_METADATA _IOWR('C', 0x15,\ + struct snd_compr_metadata) +#define SNDRV_COMPRESS_TSTAMP _IOR('C', 0x20, struct snd_compr_tstamp) +#define SNDRV_COMPRESS_AVAIL _IOR('C', 0x21, struct snd_compr_avail) +#define SNDRV_COMPRESS_PAUSE _IO('C', 0x30) +#define SNDRV_COMPRESS_RESUME _IO('C', 0x31) +#define SNDRV_COMPRESS_START _IO('C', 0x32) +#define SNDRV_COMPRESS_STOP _IO('C', 0x33) +#define SNDRV_COMPRESS_DRAIN _IO('C', 0x34) +#define SNDRV_COMPRESS_NEXT_TRACK _IO('C', 0x35) +#define SNDRV_COMPRESS_PARTIAL_DRAIN _IO('C', 0x36) +/* + * TODO + * 1. add mmap support + * + */ +#define SND_COMPR_TRIGGER_DRAIN 7 /*FIXME move this to pcm.h */ +#define SND_COMPR_TRIGGER_NEXT_TRACK 8 +#define SND_COMPR_TRIGGER_PARTIAL_DRAIN 9 + +#define SNDRV_COMPRESS_METADATA_MODE _IOW('C', 0x99, bool) +#endif diff --git a/original-kernel-headers/sound/compress_params.h b/original-kernel-headers/sound/compress_params.h new file mode 100644 index 0000000..d249303 --- /dev/null +++ b/original-kernel-headers/sound/compress_params.h @@ -0,0 +1,438 @@ +/* + * compress_params.h - codec types and parameters for compressed data + * streaming interface + * + * Copyright (C) 2011 Intel Corporation + * Authors: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com> + * Vinod Koul <vinod.koul@linux.intel.com> + * + * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. + * + * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + * + * The definitions in this file are derived from the OpenMAX AL version 1.1 + * and OpenMAX IL v 1.1.2 header files which contain the copyright notice below. + * + * Copyright (c) 2007-2010 The Khronos Group Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and/or associated documentation files (the + * "Materials "), to deal in the Materials without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Materials, and to + * permit persons to whom the Materials are furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Materials. + * + * THE MATERIALS ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * MATERIALS OR THE USE OR OTHER DEALINGS IN THE MATERIALS. + * + */ +#ifndef __SND_COMPRESS_PARAMS_H +#define __SND_COMPRESS_PARAMS_H + +#include <linux/types.h> + +/* AUDIO CODECS SUPPORTED */ +#define MAX_NUM_CODECS 32 +#define MAX_NUM_CODEC_DESCRIPTORS 32 +#define MAX_NUM_BITRATES 32 + +/* compressed TX */ +#define MAX_NUM_FRAMES_PER_BUFFER 1 +#define COMPRESSED_META_DATA_MODE 0x10 +#define META_DATA_LEN_BYTES 36 +#define Q6_AC3_DECODER 0x00010BF6 +#define Q6_EAC3_DECODER 0x00010C3C +#define Q6_DTS 0x00010D88 +#define Q6_DTS_LBR 0x00010DBB + +/* Codecs are listed linearly to allow for extensibility */ +#define SND_AUDIOCODEC_PCM ((__u32) 0x00000001) +#define SND_AUDIOCODEC_MP3 ((__u32) 0x00000002) +#define SND_AUDIOCODEC_AMR ((__u32) 0x00000003) +#define SND_AUDIOCODEC_AMRWB ((__u32) 0x00000004) +#define SND_AUDIOCODEC_AMRWBPLUS ((__u32) 0x00000005) +#define SND_AUDIOCODEC_AAC ((__u32) 0x00000006) +#define SND_AUDIOCODEC_WMA ((__u32) 0x00000007) +#define SND_AUDIOCODEC_REAL ((__u32) 0x00000008) +#define SND_AUDIOCODEC_VORBIS ((__u32) 0x00000009) +#define SND_AUDIOCODEC_FLAC ((__u32) 0x0000000A) +#define SND_AUDIOCODEC_IEC61937 ((__u32) 0x0000000B) +#define SND_AUDIOCODEC_G723_1 ((__u32) 0x0000000C) +#define SND_AUDIOCODEC_G729 ((__u32) 0x0000000D) +#define SND_AUDIOCODEC_DTS_PASS_THROUGH ((__u32) 0x0000000E) +#define SND_AUDIOCODEC_DTS_LBR ((__u32) 0x0000000F) +#define SND_AUDIOCODEC_DTS_TRANSCODE_LOOPBACK ((__u32) 0x00000010) +#define SND_AUDIOCODEC_PASS_THROUGH ((__u32) 0x00000011) +#define SND_AUDIOCODEC_MP2 ((__u32) 0x00000012) +#define SND_AUDIOCODEC_DTS_LBR_PASS_THROUGH ((__u32) 0x00000013) +#define SND_AUDIOCODEC_AC3 ((__u32) 0x00000014) +#define SND_AUDIOCODEC_AC3_PASS_THROUGH ((__u32) 0x00000015) +#define SND_AUDIOCODEC_WMA_PRO ((__u32) 0x00000016) +#define SND_AUDIOCODEC_DTS ((__u32) 0x00000017) +#define SND_AUDIOCODEC_EAC3 ((__u32) 0x00000018) +#define SND_AUDIOCODEC_MAX SND_AUDIOCODEC_EAC3 +/* + * Profile and modes are listed with bit masks. This allows for a + * more compact representation of fields that will not evolve + * (in contrast to the list of codecs) + */ + +#define SND_AUDIOPROFILE_PCM ((__u32) 0x00000001) + +/* MP3 modes are only useful for encoders */ +#define SND_AUDIOCHANMODE_MP3_MONO ((__u32) 0x00000001) +#define SND_AUDIOCHANMODE_MP3_STEREO ((__u32) 0x00000002) +#define SND_AUDIOCHANMODE_MP3_JOINTSTEREO ((__u32) 0x00000004) +#define SND_AUDIOCHANMODE_MP3_DUAL ((__u32) 0x00000008) + +#define SND_AUDIOPROFILE_AMR ((__u32) 0x00000001) + +/* AMR modes are only useful for encoders */ +#define SND_AUDIOMODE_AMR_DTX_OFF ((__u32) 0x00000001) +#define SND_AUDIOMODE_AMR_VAD1 ((__u32) 0x00000002) +#define SND_AUDIOMODE_AMR_VAD2 ((__u32) 0x00000004) + +#define SND_AUDIOSTREAMFORMAT_UNDEFINED ((__u32) 0x00000000) +#define SND_AUDIOSTREAMFORMAT_CONFORMANCE ((__u32) 0x00000001) +#define SND_AUDIOSTREAMFORMAT_IF1 ((__u32) 0x00000002) +#define SND_AUDIOSTREAMFORMAT_IF2 ((__u32) 0x00000004) +#define SND_AUDIOSTREAMFORMAT_FSF ((__u32) 0x00000008) +#define SND_AUDIOSTREAMFORMAT_RTPPAYLOAD ((__u32) 0x00000010) +#define SND_AUDIOSTREAMFORMAT_ITU ((__u32) 0x00000020) + +#define SND_AUDIOPROFILE_AMRWB ((__u32) 0x00000001) + +/* AMRWB modes are only useful for encoders */ +#define SND_AUDIOMODE_AMRWB_DTX_OFF ((__u32) 0x00000001) +#define SND_AUDIOMODE_AMRWB_VAD1 ((__u32) 0x00000002) +#define SND_AUDIOMODE_AMRWB_VAD2 ((__u32) 0x00000004) + +#define SND_AUDIOPROFILE_AMRWBPLUS ((__u32) 0x00000001) + +#define SND_AUDIOPROFILE_AAC ((__u32) 0x00000001) + +/* AAC modes are required for encoders and decoders */ +#define SND_AUDIOMODE_AAC_MAIN ((__u32) 0x00000001) +#define SND_AUDIOMODE_AAC_LC ((__u32) 0x00000002) +#define SND_AUDIOMODE_AAC_SSR ((__u32) 0x00000004) +#define SND_AUDIOMODE_AAC_LTP ((__u32) 0x00000008) +#define SND_AUDIOMODE_AAC_HE ((__u32) 0x00000010) +#define SND_AUDIOMODE_AAC_SCALABLE ((__u32) 0x00000020) +#define SND_AUDIOMODE_AAC_ERLC ((__u32) 0x00000040) +#define SND_AUDIOMODE_AAC_LD ((__u32) 0x00000080) +#define SND_AUDIOMODE_AAC_HE_PS ((__u32) 0x00000100) +#define SND_AUDIOMODE_AAC_HE_MPS ((__u32) 0x00000200) + +/* AAC formats are required for encoders and decoders */ +#define SND_AUDIOSTREAMFORMAT_MP2ADTS ((__u32) 0x00000001) +#define SND_AUDIOSTREAMFORMAT_MP4ADTS ((__u32) 0x00000002) +#define SND_AUDIOSTREAMFORMAT_MP4LOAS ((__u32) 0x00000004) +#define SND_AUDIOSTREAMFORMAT_MP4LATM ((__u32) 0x00000008) +#define SND_AUDIOSTREAMFORMAT_ADIF ((__u32) 0x00000010) +#define SND_AUDIOSTREAMFORMAT_MP4FF ((__u32) 0x00000020) +#define SND_AUDIOSTREAMFORMAT_RAW ((__u32) 0x00000040) + +#define SND_AUDIOPROFILE_WMA7 ((__u32) 0x00000001) +#define SND_AUDIOPROFILE_WMA8 ((__u32) 0x00000002) +#define SND_AUDIOPROFILE_WMA9 ((__u32) 0x00000004) +#define SND_AUDIOPROFILE_WMA10 ((__u32) 0x00000008) + +#define SND_AUDIOMODE_WMA_LEVEL1 ((__u32) 0x00000001) +#define SND_AUDIOMODE_WMA_LEVEL2 ((__u32) 0x00000002) +#define SND_AUDIOMODE_WMA_LEVEL3 ((__u32) 0x00000004) +#define SND_AUDIOMODE_WMA_LEVEL4 ((__u32) 0x00000008) +#define SND_AUDIOMODE_WMAPRO_LEVELM0 ((__u32) 0x00000010) +#define SND_AUDIOMODE_WMAPRO_LEVELM1 ((__u32) 0x00000020) +#define SND_AUDIOMODE_WMAPRO_LEVELM2 ((__u32) 0x00000040) +#define SND_AUDIOMODE_WMAPRO_LEVELM3 ((__u32) 0x00000080) + +#define SND_AUDIOSTREAMFORMAT_WMA_ASF ((__u32) 0x00000001) +/* + * Some implementations strip the ASF header and only send ASF packets + * to the DSP + */ +#define SND_AUDIOSTREAMFORMAT_WMA_NOASF_HDR ((__u32) 0x00000002) + +#define SND_AUDIOPROFILE_REALAUDIO ((__u32) 0x00000001) + +#define SND_AUDIOMODE_REALAUDIO_G2 ((__u32) 0x00000001) +#define SND_AUDIOMODE_REALAUDIO_8 ((__u32) 0x00000002) +#define SND_AUDIOMODE_REALAUDIO_10 ((__u32) 0x00000004) +#define SND_AUDIOMODE_REALAUDIO_SURROUND ((__u32) 0x00000008) + +#define SND_AUDIOPROFILE_VORBIS ((__u32) 0x00000001) + +#define SND_AUDIOMODE_VORBIS ((__u32) 0x00000001) + +#define SND_AUDIOPROFILE_FLAC ((__u32) 0x00000001) + +/* + * Define quality levels for FLAC encoders, from LEVEL0 (fast) + * to LEVEL8 (best) + */ +#define SND_AUDIOMODE_FLAC_LEVEL0 ((__u32) 0x00000001) +#define SND_AUDIOMODE_FLAC_LEVEL1 ((__u32) 0x00000002) +#define SND_AUDIOMODE_FLAC_LEVEL2 ((__u32) 0x00000004) +#define SND_AUDIOMODE_FLAC_LEVEL3 ((__u32) 0x00000008) +#define SND_AUDIOMODE_FLAC_LEVEL4 ((__u32) 0x00000010) +#define SND_AUDIOMODE_FLAC_LEVEL5 ((__u32) 0x00000020) +#define SND_AUDIOMODE_FLAC_LEVEL6 ((__u32) 0x00000040) +#define SND_AUDIOMODE_FLAC_LEVEL7 ((__u32) 0x00000080) +#define SND_AUDIOMODE_FLAC_LEVEL8 ((__u32) 0x00000100) + +#define SND_AUDIOSTREAMFORMAT_FLAC ((__u32) 0x00000001) +#define SND_AUDIOSTREAMFORMAT_FLAC_OGG ((__u32) 0x00000002) + +/* IEC61937 payloads without CUVP and preambles */ +#define SND_AUDIOPROFILE_IEC61937 ((__u32) 0x00000001) +/* IEC61937 with S/PDIF preambles+CUVP bits in 32-bit containers */ +#define SND_AUDIOPROFILE_IEC61937_SPDIF ((__u32) 0x00000002) + +/* + * IEC modes are mandatory for decoders. Format autodetection + * will only happen on the DSP side with mode 0. The PCM mode should + * not be used, the PCM codec should be used instead. + */ +#define SND_AUDIOMODE_IEC_REF_STREAM_HEADER ((__u32) 0x00000000) +#define SND_AUDIOMODE_IEC_LPCM ((__u32) 0x00000001) +#define SND_AUDIOMODE_IEC_AC3 ((__u32) 0x00000002) +#define SND_AUDIOMODE_IEC_MPEG1 ((__u32) 0x00000004) +#define SND_AUDIOMODE_IEC_MP3 ((__u32) 0x00000008) +#define SND_AUDIOMODE_IEC_MPEG2 ((__u32) 0x00000010) +#define SND_AUDIOMODE_IEC_AACLC ((__u32) 0x00000020) +#define SND_AUDIOMODE_IEC_DTS ((__u32) 0x00000040) +#define SND_AUDIOMODE_IEC_ATRAC ((__u32) 0x00000080) +#define SND_AUDIOMODE_IEC_SACD ((__u32) 0x00000100) +#define SND_AUDIOMODE_IEC_EAC3 ((__u32) 0x00000200) +#define SND_AUDIOMODE_IEC_DTS_HD ((__u32) 0x00000400) +#define SND_AUDIOMODE_IEC_MLP ((__u32) 0x00000800) +#define SND_AUDIOMODE_IEC_DST ((__u32) 0x00001000) +#define SND_AUDIOMODE_IEC_WMAPRO ((__u32) 0x00002000) +#define SND_AUDIOMODE_IEC_REF_CXT ((__u32) 0x00004000) +#define SND_AUDIOMODE_IEC_HE_AAC ((__u32) 0x00008000) +#define SND_AUDIOMODE_IEC_HE_AAC2 ((__u32) 0x00010000) +#define SND_AUDIOMODE_IEC_MPEG_SURROUND ((__u32) 0x00020000) + +#define SND_AUDIOPROFILE_G723_1 ((__u32) 0x00000001) + +#define SND_AUDIOMODE_G723_1_ANNEX_A ((__u32) 0x00000001) +#define SND_AUDIOMODE_G723_1_ANNEX_B ((__u32) 0x00000002) +#define SND_AUDIOMODE_G723_1_ANNEX_C ((__u32) 0x00000004) + +#define SND_AUDIOPROFILE_G729 ((__u32) 0x00000001) + +#define SND_AUDIOMODE_G729_ANNEX_A ((__u32) 0x00000001) +#define SND_AUDIOMODE_G729_ANNEX_B ((__u32) 0x00000002) + +/* <FIXME: multichannel encoders aren't supported for now. Would need + an additional definition of channel arrangement> */ + +/* VBR/CBR definitions */ +#define SND_RATECONTROLMODE_CONSTANTBITRATE ((__u32) 0x00000001) +#define SND_RATECONTROLMODE_VARIABLEBITRATE ((__u32) 0x00000002) + +/* Encoder options */ + +struct snd_enc_wma { + __u32 super_block_align; /* WMA Type-specific data */ + __u32 bits_per_sample; + __u32 channelmask; + __u32 encodeopt; + __u32 encodeopt1; + __u32 encodeopt2; +}; + + +/** + * struct snd_enc_vorbis + * @quality: Sets encoding quality to n, between -1 (low) and 10 (high). + * In the default mode of operation, the quality level is 3. + * Normal quality range is 0 - 10. + * @managed: Boolean. Set bitrate management mode. This turns off the + * normal VBR encoding, but allows hard or soft bitrate constraints to be + * enforced by the encoder. This mode can be slower, and may also be + * lower quality. It is primarily useful for streaming. + * @max_bit_rate: Enabled only if managed is TRUE + * @min_bit_rate: Enabled only if managed is TRUE + * @downmix: Boolean. Downmix input from stereo to mono (has no effect on + * non-stereo streams). Useful for lower-bitrate encoding. + * + * These options were extracted from the OpenMAX IL spec and Gstreamer vorbisenc + * properties + * + * For best quality users should specify VBR mode and set quality levels. + */ + +struct snd_enc_vorbis { + __s32 quality; + __u32 managed; + __u32 max_bit_rate; + __u32 min_bit_rate; + __u32 downmix; +}; + + +/** + * struct snd_enc_real + * @quant_bits: number of coupling quantization bits in the stream + * @start_region: coupling start region in the stream + * @num_regions: number of regions value + * + * These options were extracted from the OpenMAX IL spec + */ + +struct snd_enc_real { + __u32 quant_bits; + __u32 start_region; + __u32 num_regions; +}; + +/** + * struct snd_enc_flac + * @num: serial number, valid only for OGG formats + * needs to be set by application + * @gain: Add replay gain tags + * + * These options were extracted from the FLAC online documentation + * at http://flac.sourceforge.net/documentation_tools_flac.html + * + * To make the API simpler, it is assumed that the user will select quality + * profiles. Additional options that affect encoding quality and speed can + * be added at a later stage if needed. + * + * By default the Subset format is used by encoders. + * + * TAGS such as pictures, etc, cannot be handled by an offloaded encoder and are + * not supported in this API. + */ + +struct snd_enc_flac { + __u32 num; + __u32 gain; +}; + +struct snd_enc_generic { + __u32 bw; /* encoder bandwidth */ + __s32 reserved[15]; +}; +struct snd_dec_ddp { + __u32 params_length; + __u32 params_id[18]; + __u32 params_value[18]; +}; +struct snd_dec_flac { + __u16 sample_size; + __u16 min_blk_size; + __u16 max_blk_size; + __u16 min_frame_size; + __u16 max_frame_size; +}; +union snd_codec_options { + struct snd_enc_wma wma; + struct snd_enc_vorbis vorbis; + struct snd_enc_real real; + struct snd_enc_flac flac; + struct snd_enc_generic generic; + struct snd_dec_ddp ddp; + struct snd_dec_flac flac_dec; +}; + +/** struct snd_codec_desc - description of codec capabilities + * @max_ch: Maximum number of audio channels + * @sample_rates: Sampling rates in Hz, use SNDRV_PCM_RATE_xxx for this + * @bit_rate: Indexed array containing supported bit rates + * @num_bitrates: Number of valid values in bit_rate array + * @rate_control: value is specified by SND_RATECONTROLMODE defines. + * @profiles: Supported profiles. See SND_AUDIOPROFILE defines. + * @modes: Supported modes. See SND_AUDIOMODE defines + * @formats: Supported formats. See SND_AUDIOSTREAMFORMAT defines + * @min_buffer: Minimum buffer size handled by codec implementation + * @reserved: reserved for future use + * + * This structure provides a scalar value for profiles, modes and stream + * format fields. + * If an implementation supports multiple combinations, they will be listed as + * codecs with different descriptors, for example there would be 2 descriptors + * for AAC-RAW and AAC-ADTS. + * This entails some redundancy but makes it easier to avoid invalid + * configurations. + * + */ + +struct snd_codec_desc { + __u32 max_ch; + __u32 sample_rates; + __u32 bit_rate[MAX_NUM_BITRATES]; + __u32 num_bitrates; + __u32 rate_control; + __u32 profiles; + __u32 modes; + __u32 formats; + __u32 min_buffer; + __u32 reserved[15]; +}; + +/** struct snd_codec + * @id: Identifies the supported audio encoder/decoder. + * See SND_AUDIOCODEC macros. + * @ch_in: Number of input audio channels + * @ch_out: Number of output channels. In case of contradiction between + * this field and the channelMode field, the channelMode field + * overrides. + * @sample_rate: Audio sample rate of input data + * @bit_rate: Bitrate of encoded data. May be ignored by decoders + * @rate_control: Encoding rate control. See SND_RATECONTROLMODE defines. + * Encoders may rely on profiles for quality levels. + * May be ignored by decoders. + * @profile: Mandatory for encoders, can be mandatory for specific + * decoders as well. See SND_AUDIOPROFILE defines. + * @level: Supported level (Only used by WMA at the moment) + * @ch_mode: Channel mode for encoder. See SND_AUDIOCHANMODE defines + * @format: Format of encoded bistream. Mandatory when defined. + * See SND_AUDIOSTREAMFORMAT defines. + * @align: Block alignment in bytes of an audio sample. + * Only required for PCM or IEC formats. + * @options: encoder-specific settings + * @reserved: reserved for future use + */ + +struct snd_codec { + __u32 id; + __u32 ch_in; + __u32 ch_out; + __u32 sample_rate; + __u32 bit_rate; + __u32 rate_control; + __u32 profile; + __u32 level; + __u32 ch_mode; + __u32 format; + __u32 align; + __u32 compr_passthr; + union snd_codec_options options; + __u32 reserved[3]; +}; + +#endif diff --git a/original-kernel-headers/sound/lsm_params.h b/original-kernel-headers/sound/lsm_params.h new file mode 100644 index 0000000..a7e8187 --- /dev/null +++ b/original-kernel-headers/sound/lsm_params.h @@ -0,0 +1,75 @@ +#ifndef _UAPI_LSM_PARAMS_H__ +#define _UAPI_LSM_PARAMS_H__ + +#include <linux/types.h> +#include <sound/asound.h> + +#define SNDRV_LSM_VERSION SNDRV_PROTOCOL_VERSION(0, 1, 0) + +enum lsm_app_id { + LSM_VOICE_WAKEUP_APP_ID = 1, + LSM_VOICE_WAKEUP_APP_ID_V2 = 2, +}; + +enum lsm_detection_mode { + LSM_MODE_KEYWORD_ONLY_DETECTION = 1, + LSM_MODE_USER_KEYWORD_DETECTION +}; + +enum lsm_vw_status { + LSM_VOICE_WAKEUP_STATUS_RUNNING = 1, + LSM_VOICE_WAKEUP_STATUS_DETECTED, + LSM_VOICE_WAKEUP_STATUS_END_SPEECH, + LSM_VOICE_WAKEUP_STATUS_REJECTED +}; + +struct snd_lsm_sound_model { + __u8 __user *data; + __u32 data_size; + enum lsm_detection_mode detection_mode; + __u16 min_keyw_confidence; + __u16 min_user_confidence; + bool detect_failure; +}; + +struct snd_lsm_sound_model_v2 { + __u8 __user *data; + __u8 *confidence_level; + __u32 data_size; + enum lsm_detection_mode detection_mode; + __u8 num_confidence_levels; + bool detect_failure; +}; + +struct snd_lsm_session_data { + enum lsm_app_id app_id; +}; + +struct snd_lsm_event_status { + __u16 status; + __u16 payload_size; + __u8 payload[0]; +}; + +struct snd_lsm_detection_params { + __u8 *conf_level; + enum lsm_detection_mode detect_mode; + __u8 num_confidence_levels; + bool detect_failure; +}; + +#define SNDRV_LSM_REG_SND_MODEL _IOW('U', 0x00, struct snd_lsm_sound_model) +#define SNDRV_LSM_DEREG_SND_MODEL _IOW('U', 0x01, int) +#define SNDRV_LSM_EVENT_STATUS _IOW('U', 0x02, struct snd_lsm_event_status) +#define SNDRV_LSM_ABORT_EVENT _IOW('U', 0x03, int) +#define SNDRV_LSM_START _IOW('U', 0x04, int) +#define SNDRV_LSM_STOP _IOW('U', 0x05, int) +#define SNDRV_LSM_SET_SESSION_DATA _IOW('U', 0x06, struct snd_lsm_session_data) +#define SNDRV_LSM_REG_SND_MODEL_V2 _IOW('U', 0x07,\ + struct snd_lsm_sound_model_v2) +#define SNDRV_LSM_LAB_CONTROL _IOW('U', 0x08, uint32_t) +#define SNDRV_LSM_STOP_LAB _IO('U', 0x09) +#define SNDRV_LSM_SET_PARAMS _IOW('U', 0x0A, \ + struct snd_lsm_detection_params) + +#endif diff --git a/original-kernel-headers/sound/msmcal-hwdep.h b/original-kernel-headers/sound/msmcal-hwdep.h new file mode 100644 index 0000000..324b497 --- /dev/null +++ b/original-kernel-headers/sound/msmcal-hwdep.h @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2014, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#ifndef _CALIB_HWDEP_H +#define _CALIB_HWDEP_H + +#define WCD9XXX_CODEC_HWDEP_NODE 1000 +enum wcd_cal_type { + WCD9XXX_MIN_CAL, + WCD9XXX_ANC_CAL = WCD9XXX_MIN_CAL, + WCD9XXX_MAD_CAL, + WCD9XXX_MBHC_CAL, + WCD9XXX_MAX_CAL, +}; + +struct wcdcal_ioctl_buffer { + __u32 size; + __u8 __user *buffer; + enum wcd_cal_type cal_type; +}; + +#define SNDRV_CTL_IOCTL_HWDEP_CAL_TYPE \ + _IOW('U', 0x1, struct wcdcal_ioctl_buffer) + +#endif /*_CALIB_HWDEP_H*/ diff --git a/original-kernel-headers/sound/voice_params.h b/original-kernel-headers/sound/voice_params.h new file mode 100644 index 0000000..43e3b9d --- /dev/null +++ b/original-kernel-headers/sound/voice_params.h @@ -0,0 +1,14 @@ +#ifndef __VOICE_PARAMS_H__ +#define __VOICE_PARAMS_H__ + +#include <linux/types.h> +#include <sound/asound.h> + +enum voice_lch_mode { + VOICE_LCH_START = 1, + VOICE_LCH_STOP +}; + +#define SNDRV_VOICE_IOCTL_LCH _IOW('U', 0x00, enum voice_lch_mode) + +#endif diff --git a/original-kernel-headers/video/msm_hdmi_modes.h b/original-kernel-headers/video/msm_hdmi_modes.h new file mode 100644 index 0000000..d443f00 --- /dev/null +++ b/original-kernel-headers/video/msm_hdmi_modes.h @@ -0,0 +1,404 @@ +#ifndef _UAPI_MSM_HDMI_MODES_H__ +#define _UAPI_MSM_HDMI_MODES_H__ +#include <linux/types.h> + +enum aspect_ratio { + HDMI_RES_AR_INVALID, + HDMI_RES_AR_4_3, + HDMI_RES_AR_5_4, + HDMI_RES_AR_16_9, + HDMI_RES_AR_16_10, + HDMI_RES_AR_MAX, +}; + +struct msm_hdmi_mode_timing_info { + uint32_t video_format; + uint32_t active_h; + uint32_t front_porch_h; + uint32_t pulse_width_h; + uint32_t back_porch_h; + uint32_t active_low_h; + uint32_t active_v; + uint32_t front_porch_v; + uint32_t pulse_width_v; + uint32_t back_porch_v; + uint32_t active_low_v; + /* Must divide by 1000 to get the actual frequency in MHZ */ + uint32_t pixel_freq; + /* Must divide by 1000 to get the actual frequency in HZ */ + uint32_t refresh_rate; + uint32_t interlaced; + uint32_t supported; + enum aspect_ratio ar; +}; + +#define MSM_HDMI_INIT_RES_PAGE 1 + +#define MSM_HDMI_MODES_CEA (1 << 0) +#define MSM_HDMI_MODES_XTND (1 << 1) +#define MSM_HDMI_MODES_DVI (1 << 2) +#define MSM_HDMI_MODES_ALL (MSM_HDMI_MODES_CEA |\ + MSM_HDMI_MODES_XTND |\ + MSM_HDMI_MODES_DVI) + +/* all video formats defined by CEA 861D */ +#define HDMI_VFRMT_UNKNOWN 0 +#define HDMI_VFRMT_640x480p60_4_3 1 +#define HDMI_VFRMT_720x480p60_4_3 2 +#define HDMI_VFRMT_720x480p60_16_9 3 +#define HDMI_VFRMT_1280x720p60_16_9 4 +#define HDMI_VFRMT_1920x1080i60_16_9 5 +#define HDMI_VFRMT_720x480i60_4_3 6 +#define HDMI_VFRMT_1440x480i60_4_3 HDMI_VFRMT_720x480i60_4_3 +#define HDMI_VFRMT_720x480i60_16_9 7 +#define HDMI_VFRMT_1440x480i60_16_9 HDMI_VFRMT_720x480i60_16_9 +#define HDMI_VFRMT_720x240p60_4_3 8 +#define HDMI_VFRMT_1440x240p60_4_3 HDMI_VFRMT_720x240p60_4_3 +#define HDMI_VFRMT_720x240p60_16_9 9 +#define HDMI_VFRMT_1440x240p60_16_9 HDMI_VFRMT_720x240p60_16_9 +#define HDMI_VFRMT_2880x480i60_4_3 10 +#define HDMI_VFRMT_2880x480i60_16_9 11 +#define HDMI_VFRMT_2880x240p60_4_3 12 +#define HDMI_VFRMT_2880x240p60_16_9 13 +#define HDMI_VFRMT_1440x480p60_4_3 14 +#define HDMI_VFRMT_1440x480p60_16_9 15 +#define HDMI_VFRMT_1920x1080p60_16_9 16 +#define HDMI_VFRMT_720x576p50_4_3 17 +#define HDMI_VFRMT_720x576p50_16_9 18 +#define HDMI_VFRMT_1280x720p50_16_9 19 +#define HDMI_VFRMT_1920x1080i50_16_9 20 +#define HDMI_VFRMT_720x576i50_4_3 21 +#define HDMI_VFRMT_1440x576i50_4_3 HDMI_VFRMT_720x576i50_4_3 +#define HDMI_VFRMT_720x576i50_16_9 22 +#define HDMI_VFRMT_1440x576i50_16_9 HDMI_VFRMT_720x576i50_16_9 +#define HDMI_VFRMT_720x288p50_4_3 23 +#define HDMI_VFRMT_1440x288p50_4_3 HDMI_VFRMT_720x288p50_4_3 +#define HDMI_VFRMT_720x288p50_16_9 24 +#define HDMI_VFRMT_1440x288p50_16_9 HDMI_VFRMT_720x288p50_16_9 +#define HDMI_VFRMT_2880x576i50_4_3 25 +#define HDMI_VFRMT_2880x576i50_16_9 26 +#define HDMI_VFRMT_2880x288p50_4_3 27 +#define HDMI_VFRMT_2880x288p50_16_9 28 +#define HDMI_VFRMT_1440x576p50_4_3 29 +#define HDMI_VFRMT_1440x576p50_16_9 30 +#define HDMI_VFRMT_1920x1080p50_16_9 31 +#define HDMI_VFRMT_1920x1080p24_16_9 32 +#define HDMI_VFRMT_1920x1080p25_16_9 33 +#define HDMI_VFRMT_1920x1080p30_16_9 34 +#define HDMI_VFRMT_2880x480p60_4_3 35 +#define HDMI_VFRMT_2880x480p60_16_9 36 +#define HDMI_VFRMT_2880x576p50_4_3 37 +#define HDMI_VFRMT_2880x576p50_16_9 38 +#define HDMI_VFRMT_1920x1250i50_16_9 39 +#define HDMI_VFRMT_1920x1080i100_16_9 40 +#define HDMI_VFRMT_1280x720p100_16_9 41 +#define HDMI_VFRMT_720x576p100_4_3 42 +#define HDMI_VFRMT_720x576p100_16_9 43 +#define HDMI_VFRMT_720x576i100_4_3 44 +#define HDMI_VFRMT_1440x576i100_4_3 HDMI_VFRMT_720x576i100_4_3 +#define HDMI_VFRMT_720x576i100_16_9 45 +#define HDMI_VFRMT_1440x576i100_16_9 HDMI_VFRMT_720x576i100_16_9 +#define HDMI_VFRMT_1920x1080i120_16_9 46 +#define HDMI_VFRMT_1280x720p120_16_9 47 +#define HDMI_VFRMT_720x480p120_4_3 48 +#define HDMI_VFRMT_720x480p120_16_9 49 +#define HDMI_VFRMT_720x480i120_4_3 50 +#define HDMI_VFRMT_1440x480i120_4_3 HDMI_VFRMT_720x480i120_4_3 +#define HDMI_VFRMT_720x480i120_16_9 51 +#define HDMI_VFRMT_1440x480i120_16_9 HDMI_VFRMT_720x480i120_16_9 +#define HDMI_VFRMT_720x576p200_4_3 52 +#define HDMI_VFRMT_720x576p200_16_9 53 +#define HDMI_VFRMT_720x576i200_4_3 54 +#define HDMI_VFRMT_1440x576i200_4_3 HDMI_VFRMT_720x576i200_4_3 +#define HDMI_VFRMT_720x576i200_16_9 55 +#define HDMI_VFRMT_1440x576i200_16_9 HDMI_VFRMT_720x576i200_16_9 +#define HDMI_VFRMT_720x480p240_4_3 56 +#define HDMI_VFRMT_720x480p240_16_9 57 +#define HDMI_VFRMT_720x480i240_4_3 58 +#define HDMI_VFRMT_1440x480i240_4_3 HDMI_VFRMT_720x480i240_4_3 +#define HDMI_VFRMT_720x480i240_16_9 59 +#define HDMI_VFRMT_1440x480i240_16_9 HDMI_VFRMT_720x480i240_16_9 +#define HDMI_VFRMT_1280x720p24_16_9 60 +#define HDMI_VFRMT_1280x720p25_16_9 61 +#define HDMI_VFRMT_1280x720p30_16_9 62 +#define HDMI_VFRMT_1920x1080p120_16_9 63 +#define HDMI_VFRMT_1920x1080p100_16_9 64 +/* Video Identification Codes from 65-127 are reserved for the future */ +#define HDMI_VFRMT_END 127 + +#define EVFRMT_OFF(x) (HDMI_VFRMT_END + x) + +/* extended video formats */ +#define HDMI_VFRMT_3840x2160p30_16_9 EVFRMT_OFF(1) +#define HDMI_VFRMT_3840x2160p25_16_9 EVFRMT_OFF(2) +#define HDMI_VFRMT_3840x2160p24_16_9 EVFRMT_OFF(3) +#define HDMI_VFRMT_4096x2160p24_16_9 EVFRMT_OFF(4) +#define HDMI_EVFRMT_END HDMI_VFRMT_4096x2160p24_16_9 + +#define WQXGA_OFF(x) (HDMI_EVFRMT_END + x) + +/* WQXGA */ +#define HDMI_VFRMT_2560x1600p60_16_9 WQXGA_OFF(1) +#define HDMI_WQXGAFRMT_END HDMI_VFRMT_2560x1600p60_16_9 + +#define WXGA_OFF(x) (HDMI_WQXGAFRMT_END + x) + +/* WXGA */ +#define HDMI_VFRMT_1280x800p60_16_10 WXGA_OFF(1) +#define HDMI_VFRMT_1366x768p60_16_10 WXGA_OFF(2) +#define HDMI_WXGAFRMT_END HDMI_VFRMT_1366x768p60_16_10 + +#define ETI_OFF(x) (HDMI_WXGAFRMT_END + x) + +/* ESTABLISHED TIMINGS I */ +#define HDMI_VFRMT_800x600p60_4_3 ETI_OFF(1) +#define ETI_VFRMT_END HDMI_VFRMT_800x600p60_4_3 + +#define ETII_OFF(x) (ETI_VFRMT_END + x) + +/* ESTABLISHED TIMINGS II */ +#define HDMI_VFRMT_1024x768p60_4_3 ETII_OFF(1) +#define HDMI_VFRMT_1280x1024p60_5_4 ETII_OFF(2) +#define ETII_VFRMT_END HDMI_VFRMT_1280x1024p60_5_4 + +#define ETIII_OFF(x) (ETII_VFRMT_END + x) + +/* ESTABLISHED TIMINGS III */ +#define HDMI_VFRMT_848x480p60_16_9 ETIII_OFF(1) +#define HDMI_VFRMT_1280x960p60_4_3 ETIII_OFF(2) +#define HDMI_VFRMT_1360x768p60_16_9 ETIII_OFF(3) +#define HDMI_VFRMT_1440x900p60_16_10 ETIII_OFF(4) +#define HDMI_VFRMT_1400x1050p60_4_3 ETIII_OFF(5) +#define HDMI_VFRMT_1680x1050p60_16_10 ETIII_OFF(6) +#define HDMI_VFRMT_1600x1200p60_4_3 ETIII_OFF(7) +#define HDMI_VFRMT_1920x1200p60_16_10 ETIII_OFF(8) +#define ETIII_VFRMT_END HDMI_VFRMT_1920x1200p60_16_10 + +#define RESERVE_OFF(x) (ETIII_VFRMT_END + x) + +#define HDMI_VFRMT_RESERVE1 RESERVE_OFF(1) +#define HDMI_VFRMT_RESERVE2 RESERVE_OFF(2) +#define HDMI_VFRMT_RESERVE3 RESERVE_OFF(3) +#define HDMI_VFRMT_RESERVE4 RESERVE_OFF(4) +#define HDMI_VFRMT_RESERVE5 RESERVE_OFF(5) +#define HDMI_VFRMT_RESERVE6 RESERVE_OFF(6) +#define HDMI_VFRMT_RESERVE7 RESERVE_OFF(7) +#define HDMI_VFRMT_RESERVE8 RESERVE_OFF(8) +#define RESERVE_VFRMT_END HDMI_VFRMT_RESERVE8 + +#define HDMI_VFRMT_MAX (RESERVE_VFRMT_END + 1) +#define HDMI_VFRMT_FORCE_32BIT 0x7FFFFFFF + +/* Timing information for supported modes */ +#define VFRMT_NOT_SUPPORTED(VFRMT) \ + {VFRMT, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, false, \ + HDMI_RES_AR_INVALID} + +#define HDMI_VFRMT_640x480p60_4_3_TIMING \ + {HDMI_VFRMT_640x480p60_4_3, 640, 16, 96, 48, true, \ + 480, 10, 2, 33, true, 25200, 60000, false, true, HDMI_RES_AR_4_3} +#define HDMI_VFRMT_720x480p60_4_3_TIMING \ + {HDMI_VFRMT_720x480p60_4_3, 720, 16, 62, 60, true, \ + 480, 9, 6, 30, true, 27027, 60000, false, true, HDMI_RES_AR_4_3} +#define HDMI_VFRMT_720x480p60_16_9_TIMING \ + {HDMI_VFRMT_720x480p60_16_9, 720, 16, 62, 60, true, \ + 480, 9, 6, 30, true, 27027, 60000, false, true, HDMI_RES_AR_16_9} +#define HDMI_VFRMT_1280x720p60_16_9_TIMING \ + {HDMI_VFRMT_1280x720p60_16_9, 1280, 110, 40, 220, false, \ + 720, 5, 5, 20, false, 74250, 60000, false, true, HDMI_RES_AR_16_9} +#define HDMI_VFRMT_1920x1080i60_16_9_TIMING \ + {HDMI_VFRMT_1920x1080i60_16_9, 1920, 88, 44, 148, false, \ + 540, 2, 5, 5, false, 74250, 60000, false, true, HDMI_RES_AR_16_9} +#define HDMI_VFRMT_1440x480i60_4_3_TIMING \ + {HDMI_VFRMT_1440x480i60_4_3, 1440, 38, 124, 114, true, \ + 240, 4, 3, 15, true, 27000, 60000, true, true, HDMI_RES_AR_4_3} +#define HDMI_VFRMT_1440x480i60_16_9_TIMING \ + {HDMI_VFRMT_1440x480i60_16_9, 1440, 38, 124, 114, true, \ + 240, 4, 3, 15, true, 27000, 60000, true, true, HDMI_RES_AR_16_9} +#define HDMI_VFRMT_1920x1080p60_16_9_TIMING \ + {HDMI_VFRMT_1920x1080p60_16_9, 1920, 88, 44, 148, false, \ + 1080, 4, 5, 36, false, 148500, 60000, false, true, HDMI_RES_AR_16_9} +#define HDMI_VFRMT_720x576p50_4_3_TIMING \ + {HDMI_VFRMT_720x576p50_4_3, 720, 12, 64, 68, true, \ + 576, 5, 5, 39, true, 27000, 50000, false, true, HDMI_RES_AR_4_3} +#define HDMI_VFRMT_720x576p50_16_9_TIMING \ + {HDMI_VFRMT_720x576p50_16_9, 720, 12, 64, 68, true, \ + 576, 5, 5, 39, true, 27000, 50000, false, true, HDMI_RES_AR_16_9} +#define HDMI_VFRMT_1280x720p50_16_9_TIMING \ + {HDMI_VFRMT_1280x720p50_16_9, 1280, 440, 40, 220, false, \ + 720, 5, 5, 20, false, 74250, 50000, false, true, HDMI_RES_AR_16_9} +#define HDMI_VFRMT_1440x576i50_4_3_TIMING \ + {HDMI_VFRMT_1440x576i50_4_3, 1440, 24, 126, 138, true, \ + 288, 2, 3, 19, true, 27000, 50000, true, true, HDMI_RES_AR_4_3} +#define HDMI_VFRMT_1440x576i50_16_9_TIMING \ + {HDMI_VFRMT_1440x576i50_16_9, 1440, 24, 126, 138, true, \ + 288, 2, 3, 19, true, 27000, 50000, true, true, HDMI_RES_AR_16_9} +#define HDMI_VFRMT_1920x1080p50_16_9_TIMING \ + {HDMI_VFRMT_1920x1080p50_16_9, 1920, 528, 44, 148, false, \ + 1080, 4, 5, 36, false, 148500, 50000, false, true, HDMI_RES_AR_16_9} +#define HDMI_VFRMT_1920x1080p24_16_9_TIMING \ + {HDMI_VFRMT_1920x1080p24_16_9, 1920, 638, 44, 148, false, \ + 1080, 4, 5, 36, false, 74250, 24000, false, true, HDMI_RES_AR_16_9} +#define HDMI_VFRMT_1920x1080p25_16_9_TIMING \ + {HDMI_VFRMT_1920x1080p25_16_9, 1920, 528, 44, 148, false, \ + 1080, 4, 5, 36, false, 74250, 25000, false, true, HDMI_RES_AR_16_9} +#define HDMI_VFRMT_1920x1080p30_16_9_TIMING \ + {HDMI_VFRMT_1920x1080p30_16_9, 1920, 88, 44, 148, false, \ + 1080, 4, 5, 36, false, 74250, 30000, false, true, HDMI_RES_AR_16_9} +#define HDMI_VFRMT_1024x768p60_4_3_TIMING \ + {HDMI_VFRMT_1024x768p60_4_3, 1024, 24, 136, 160, false, \ + 768, 2, 6, 29, false, 65000, 60000, false, true, HDMI_RES_AR_4_3} +#define HDMI_VFRMT_1280x1024p60_5_4_TIMING \ + {HDMI_VFRMT_1280x1024p60_5_4, 1280, 48, 112, 248, false, \ + 1024, 1, 3, 38, false, 108000, 60000, false, true, HDMI_RES_AR_5_4} +#define HDMI_VFRMT_2560x1600p60_16_9_TIMING \ + {HDMI_VFRMT_2560x1600p60_16_9, 2560, 48, 32, 80, false, \ + 1600, 3, 6, 37, false, 268500, 60000, false, true, HDMI_RES_AR_16_9} +#define HDMI_VFRMT_3840x2160p30_16_9_TIMING \ + {HDMI_VFRMT_3840x2160p30_16_9, 3840, 176, 88, 296, false, \ + 2160, 8, 10, 72, false, 297000, 30000, false, true, HDMI_RES_AR_16_9} +#define HDMI_VFRMT_3840x2160p25_16_9_TIMING \ + {HDMI_VFRMT_3840x2160p25_16_9, 3840, 1056, 88, 296, false, \ + 2160, 8, 10, 72, false, 297000, 25000, false, true, HDMI_RES_AR_16_9} +#define HDMI_VFRMT_3840x2160p24_16_9_TIMING \ + {HDMI_VFRMT_3840x2160p24_16_9, 3840, 1276, 88, 296, false, \ + 2160, 8, 10, 72, false, 297000, 24000, false, true, HDMI_RES_AR_16_9} +#define HDMI_VFRMT_4096x2160p24_16_9_TIMING \ + {HDMI_VFRMT_4096x2160p24_16_9, 4096, 1020, 88, 296, false, \ + 2160, 8, 10, 72, false, 297000, 24000, false, true, HDMI_RES_AR_16_9} + +#define HDMI_VFRMT_800x600p60_4_3_TIMING \ + {HDMI_VFRMT_800x600p60_4_3, 800, 40, 128, 88, false, \ + 600, 1, 4, 23, false, 40000, 60000, false, true, HDMI_RES_AR_4_3} +#define HDMI_VFRMT_848x480p60_16_9_TIMING \ + {HDMI_VFRMT_848x480p60_16_9, 848, 16, 112, 112, false, \ + 480, 6, 8, 23, false, 33750, 60000, false, true, HDMI_RES_AR_16_9} +#define HDMI_VFRMT_1280x960p60_4_3_TIMING\ + {HDMI_VFRMT_1280x960p60_4_3, 1280, 96, 112, 312, false, \ + 960, 1, 3, 36, false, 108000, 60000, false, true, HDMI_RES_AR_4_3} +#define HDMI_VFRMT_1360x768p60_16_9_TIMING\ + {HDMI_VFRMT_1360x768p60_16_9, 1360, 64, 112, 256, false, \ + 768, 3, 6, 18, false, 85500, 60000, false, true, HDMI_RES_AR_16_9} +#define HDMI_VFRMT_1440x900p60_16_10_TIMING\ + {HDMI_VFRMT_1440x900p60_16_10, 1440, 48, 32, 80, false, \ + 900, 3, 6, 17, true, 88750, 60000, false, true, HDMI_RES_AR_16_10} +#define HDMI_VFRMT_1400x1050p60_4_3_TIMING\ + {HDMI_VFRMT_1400x1050p60_4_3, 1400, 48, 32, 80, false, \ + 1050, 3, 4, 23, true, 101000, 60000, false, true, HDMI_RES_AR_4_3} +#define HDMI_VFRMT_1680x1050p60_16_10_TIMING\ + {HDMI_VFRMT_1680x1050p60_16_10, 1680, 48, 32, 80, false, \ + 1050, 3, 6, 21, true, 119000, 60000, false, true, HDMI_RES_AR_16_10} +#define HDMI_VFRMT_1600x1200p60_4_3_TIMING\ + {HDMI_VFRMT_1600x1200p60_4_3, 1600, 64, 192, 304, false, \ + 1200, 1, 3, 46, false, 162000, 60000, false, true, HDMI_RES_AR_4_3} +#define HDMI_VFRMT_1920x1200p60_16_10_TIMING\ + {HDMI_VFRMT_1920x1200p60_16_10, 1920, 48, 32, 80, false,\ + 1200, 3, 6, 26, true, 154000, 60000, false, true, HDMI_RES_AR_16_10} +#define HDMI_VFRMT_1366x768p60_16_10_TIMING\ + {HDMI_VFRMT_1366x768p60_16_10, 1366, 70, 143, 213, false,\ + 768, 3, 3, 24, false, 85500, 60000, false, true, HDMI_RES_AR_16_10} +#define HDMI_VFRMT_1280x800p60_16_10_TIMING\ + {HDMI_VFRMT_1280x800p60_16_10, 1280, 72, 128, 200, true,\ + 800, 3, 6, 22, false, 83500, 60000, false, true, HDMI_RES_AR_16_10} + +#define MSM_HDMI_MODES_SET_TIMING(LUT, MODE) do { \ + struct msm_hdmi_mode_timing_info mode = MODE##_TIMING; \ + LUT[MODE] = mode;\ + } while (0) + +#define MSM_HDMI_MODES_INIT_TIMINGS(__lut) \ +do { \ + unsigned int i; \ + for (i = 0; i < HDMI_VFRMT_MAX; i++) { \ + struct msm_hdmi_mode_timing_info mode = \ + VFRMT_NOT_SUPPORTED(i); \ + (__lut)[i] = mode; \ + } \ +} while (0) + +#define MSM_HDMI_MODES_SET_SUPP_TIMINGS(__lut, __type) \ +do { \ + if (__type & MSM_HDMI_MODES_CEA) { \ + MSM_HDMI_MODES_SET_TIMING(__lut, \ + HDMI_VFRMT_640x480p60_4_3); \ + MSM_HDMI_MODES_SET_TIMING(__lut, \ + HDMI_VFRMT_720x480p60_4_3); \ + MSM_HDMI_MODES_SET_TIMING(__lut, \ + HDMI_VFRMT_720x480p60_16_9); \ + MSM_HDMI_MODES_SET_TIMING(__lut, \ + HDMI_VFRMT_1280x720p60_16_9); \ + MSM_HDMI_MODES_SET_TIMING(__lut, \ + HDMI_VFRMT_1920x1080i60_16_9); \ + MSM_HDMI_MODES_SET_TIMING(__lut, \ + HDMI_VFRMT_1440x480i60_4_3); \ + MSM_HDMI_MODES_SET_TIMING(__lut, \ + HDMI_VFRMT_1440x480i60_16_9); \ + MSM_HDMI_MODES_SET_TIMING(__lut, \ + HDMI_VFRMT_1920x1080p60_16_9); \ + MSM_HDMI_MODES_SET_TIMING(__lut, \ + HDMI_VFRMT_720x576p50_4_3); \ + MSM_HDMI_MODES_SET_TIMING(__lut, \ + HDMI_VFRMT_720x576p50_16_9); \ + MSM_HDMI_MODES_SET_TIMING(__lut, \ + HDMI_VFRMT_1280x720p50_16_9); \ + MSM_HDMI_MODES_SET_TIMING(__lut, \ + HDMI_VFRMT_1440x576i50_4_3); \ + MSM_HDMI_MODES_SET_TIMING(__lut, \ + HDMI_VFRMT_1440x576i50_16_9); \ + MSM_HDMI_MODES_SET_TIMING(__lut, \ + HDMI_VFRMT_1920x1080p50_16_9); \ + MSM_HDMI_MODES_SET_TIMING(__lut, \ + HDMI_VFRMT_1920x1080p24_16_9); \ + MSM_HDMI_MODES_SET_TIMING(__lut, \ + HDMI_VFRMT_1920x1080p25_16_9); \ + MSM_HDMI_MODES_SET_TIMING(__lut, \ + HDMI_VFRMT_1920x1080p30_16_9); \ + } \ + if (__type & MSM_HDMI_MODES_XTND) { \ + MSM_HDMI_MODES_SET_TIMING(__lut, \ + HDMI_VFRMT_3840x2160p30_16_9); \ + MSM_HDMI_MODES_SET_TIMING(__lut, \ + HDMI_VFRMT_3840x2160p25_16_9); \ + MSM_HDMI_MODES_SET_TIMING(__lut, \ + HDMI_VFRMT_3840x2160p24_16_9); \ + MSM_HDMI_MODES_SET_TIMING(__lut, \ + HDMI_VFRMT_4096x2160p24_16_9); \ + } \ + if (__type & MSM_HDMI_MODES_DVI) { \ + MSM_HDMI_MODES_SET_TIMING(__lut, \ + HDMI_VFRMT_1024x768p60_4_3); \ + MSM_HDMI_MODES_SET_TIMING(__lut, \ + HDMI_VFRMT_1280x1024p60_5_4); \ + MSM_HDMI_MODES_SET_TIMING(__lut, \ + HDMI_VFRMT_2560x1600p60_16_9); \ + MSM_HDMI_MODES_SET_TIMING(__lut, \ + HDMI_VFRMT_800x600p60_4_3); \ + MSM_HDMI_MODES_SET_TIMING(__lut, \ + HDMI_VFRMT_848x480p60_16_9); \ + MSM_HDMI_MODES_SET_TIMING(__lut, \ + HDMI_VFRMT_1280x960p60_4_3); \ + MSM_HDMI_MODES_SET_TIMING(__lut, \ + HDMI_VFRMT_1360x768p60_16_9); \ + MSM_HDMI_MODES_SET_TIMING(__lut, \ + HDMI_VFRMT_1440x900p60_16_10); \ + MSM_HDMI_MODES_SET_TIMING(__lut, \ + HDMI_VFRMT_1400x1050p60_4_3); \ + MSM_HDMI_MODES_SET_TIMING(__lut, \ + HDMI_VFRMT_1680x1050p60_16_10); \ + MSM_HDMI_MODES_SET_TIMING(__lut, \ + HDMI_VFRMT_1600x1200p60_4_3); \ + MSM_HDMI_MODES_SET_TIMING(__lut, \ + HDMI_VFRMT_1920x1200p60_16_10); \ + MSM_HDMI_MODES_SET_TIMING(__lut, \ + HDMI_VFRMT_1366x768p60_16_10); \ + MSM_HDMI_MODES_SET_TIMING(__lut, \ + HDMI_VFRMT_1280x800p60_16_10); \ + } \ +} while (0) + +#define MSM_HDMI_MODES_GET_DETAILS(mode, MODE) do { \ + struct msm_hdmi_mode_timing_info info = MODE##_TIMING; \ + *mode = info; \ + } while (0) + +#endif /* _UAPI_MSM_HDMI_MODES_H__ */ |