diff options
author | Simon Wilson <simonwilson@google.com> | 2014-04-09 10:51:21 -0700 |
---|---|---|
committer | Simon Wilson <simonwilson@google.com> | 2014-04-09 10:51:21 -0700 |
commit | a1582f49b9f19a98dc22559814b7595c9a8e4488 (patch) | |
tree | 8e34fcb4be24a6c3bd797fb83a45fbf3dfa1772a | |
parent | 5491e9f18dd25f05f08d07c562fbd42745d5a6e3 (diff) | |
download | msm8x26-a1582f49b9f19a98dc22559814b7595c9a8e4488.tar.gz |
Revert "Revert "msm8x26: update headers""
This reverts commit 5491e9f18dd25f05f08d07c562fbd42745d5a6e3.
-rw-r--r-- | kernel-headers/linux/ion.h | 24 | ||||
-rw-r--r-- | kernel-headers/linux/msm_ion.h | 46 | ||||
-rw-r--r-- | kernel-headers/linux/msm_kgsl.h | 248 | ||||
-rw-r--r-- | kernel-headers/linux/msm_mdp.h | 311 | ||||
-rw-r--r-- | original-kernel-headers/linux/ion.h | 3 | ||||
-rw-r--r-- | original-kernel-headers/linux/msm_ion.h | 286 | ||||
-rw-r--r-- | original-kernel-headers/linux/msm_kgsl.h | 62 | ||||
-rw-r--r-- | original-kernel-headers/linux/msm_mdp.h | 54 | ||||
-rw-r--r-- | original-kernel-headers/media/msm_media_info.h | 188 | ||||
-rw-r--r-- | original-kernel-headers/video/msm_hdmi_modes.h | 360 |
10 files changed, 601 insertions, 981 deletions
diff --git a/kernel-headers/linux/ion.h b/kernel-headers/linux/ion.h index cc3270e..81ff1c1 100644 --- a/kernel-headers/linux/ion.h +++ b/kernel-headers/linux/ion.h @@ -21,59 +21,57 @@ #include <linux/ioctl.h> #include <linux/types.h> /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ -struct ion_handle; -typedef struct ion_handle *ion_user_handle_t; +typedef int ion_user_handle_t; enum ion_heap_type { ION_HEAP_TYPE_SYSTEM, -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ ION_HEAP_TYPE_SYSTEM_CONTIG, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ ION_HEAP_TYPE_CARVEOUT, ION_HEAP_TYPE_CHUNK, ION_HEAP_TYPE_CUSTOM, -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ ION_NUM_HEAPS, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ }; #define ION_HEAP_SYSTEM_MASK (1 << ION_HEAP_TYPE_SYSTEM) #define ION_HEAP_SYSTEM_CONTIG_MASK (1 << ION_HEAP_TYPE_SYSTEM_CONTIG) -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define ION_HEAP_CARVEOUT_MASK (1 << ION_HEAP_TYPE_CARVEOUT) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define ION_NUM_HEAP_IDS sizeof(unsigned int) * 8 #define ION_FLAG_CACHED 1 #define ION_FLAG_CACHED_NEEDS_SYNC 2 -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define ION_FLAG_FREED_FROM_SHRINKER 4 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct ion_allocation_data { size_t len; size_t align; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ unsigned int heap_mask; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ unsigned int flags; ion_user_handle_t handle; }; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct ion_fd_data { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ ion_user_handle_t handle; int fd; }; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct ion_handle_data { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ ion_user_handle_t handle; }; struct ion_custom_data { -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ unsigned int cmd; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ unsigned long arg; }; #define ION_IOC_MAGIC 'I' -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define ION_IOC_ALLOC _IOWR(ION_IOC_MAGIC, 0, struct ion_allocation_data) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define ION_IOC_FREE _IOWR(ION_IOC_MAGIC, 1, struct ion_handle_data) #define ION_IOC_MAP _IOWR(ION_IOC_MAGIC, 2, struct ion_fd_data) #define ION_IOC_SHARE _IOWR(ION_IOC_MAGIC, 4, struct ion_fd_data) -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define ION_IOC_IMPORT _IOWR(ION_IOC_MAGIC, 5, struct ion_fd_data) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define ION_IOC_SYNC _IOWR(ION_IOC_MAGIC, 7, struct ion_fd_data) #define ION_IOC_CUSTOM _IOWR(ION_IOC_MAGIC, 6, struct ion_custom_data) #endif -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ diff --git a/kernel-headers/linux/msm_ion.h b/kernel-headers/linux/msm_ion.h index dbdd802..169b58e 100644 --- a/kernel-headers/linux/msm_ion.h +++ b/kernel-headers/linux/msm_ion.h @@ -18,109 +18,107 @@ ****************************************************************************/ #ifndef _UAPI_MSM_ION_H #define _UAPI_MSM_ION_H -#include <linux/ion.h> +#include "ion.h" enum msm_ion_heap_types { /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ ION_HEAP_TYPE_MSM_START = ION_HEAP_TYPE_CUSTOM + 1, ION_HEAP_TYPE_DMA = ION_HEAP_TYPE_MSM_START, - ION_HEAP_TYPE_CP, ION_HEAP_TYPE_SECURE_DMA, -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ ION_HEAP_TYPE_REMOVED, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ }; enum ion_heap_ids { INVALID_HEAP_ID = -1, -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ ION_CP_MM_HEAP_ID = 8, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ ION_CP_MFC_HEAP_ID = 12, ION_CP_WB_HEAP_ID = 16, ION_CAMERA_HEAP_ID = 20, -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ ION_SYSTEM_CONTIG_HEAP_ID = 21, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ ION_ADSP_HEAP_ID = 22, ION_PIL1_HEAP_ID = 23, ION_SF_HEAP_ID = 24, -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ ION_SYSTEM_HEAP_ID = 25, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ ION_PIL2_HEAP_ID = 26, ION_QSECOM_HEAP_ID = 27, ION_AUDIO_HEAP_ID = 28, -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ ION_MM_FIRMWARE_HEAP_ID = 29, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ ION_HEAP_ID_RESERVED = 31 }; #define ION_IOMMU_HEAP_ID ION_SYSTEM_HEAP_ID -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define ION_HEAP_TYPE_IOMMU ION_HEAP_TYPE_SYSTEM +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ enum ion_fixed_position { NOT_FIXED, FIXED_LOW, -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ FIXED_MIDDLE, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ FIXED_HIGH, }; enum cp_mem_usage { -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ VIDEO_BITSTREAM = 0x1, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ VIDEO_PIXEL = 0x2, VIDEO_NONPIXEL = 0x3, MAX_USAGE = 0x4, -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ UNKNOWN = 0x7FFFFFFF, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ }; -#define ION_HEAP_CP_MASK (1 << ION_HEAP_TYPE_CP) #define ION_HEAP_TYPE_DMA_MASK (1 << ION_HEAP_TYPE_DMA) -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define ION_FLAG_SECURE (1 << ION_HEAP_ID_RESERVED) #define ION_FLAG_FORCE_CONTIGUOUS (1 << 30) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define ION_FLAG_POOL_FORCE_ALLOC (1 << 16) #define ION_SECURE ION_FLAG_SECURE -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define ION_FORCE_CONTIGUOUS ION_FLAG_FORCE_CONTIGUOUS #define ION_HEAP(bit) (1 << (bit)) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define ION_ADSP_HEAP_NAME "adsp" #define ION_SYSTEM_HEAP_NAME "system" -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define ION_VMALLOC_HEAP_NAME ION_SYSTEM_HEAP_NAME #define ION_KMALLOC_HEAP_NAME "kmalloc" +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define ION_AUDIO_HEAP_NAME "audio" #define ION_SF_HEAP_NAME "sf" -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define ION_MM_HEAP_NAME "mm" #define ION_CAMERA_HEAP_NAME "camera_preview" +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define ION_IOMMU_HEAP_NAME "iommu" #define ION_MFC_HEAP_NAME "mfc" -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define ION_WB_HEAP_NAME "wb" #define ION_MM_FIRMWARE_HEAP_NAME "mm_fw" +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define ION_PIL1_HEAP_NAME "pil_1" #define ION_PIL2_HEAP_NAME "pil_2" -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define ION_QSECOM_HEAP_NAME "qsecom" #define ION_SET_CACHED(__cache) (__cache | ION_FLAG_CACHED) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define ION_SET_UNCACHED(__cache) (__cache & ~ION_FLAG_CACHED) #define ION_IS_CACHED(__flags) ((__flags) & ION_FLAG_CACHED) -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct ion_flush_data { - struct ion_handle *handle; + ion_user_handle_t handle; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ int fd; void *vaddr; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ unsigned int offset; unsigned int length; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ }; struct ion_prefetch_data { -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ int heap_id; unsigned long len; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ }; #define ION_IOC_MSM_MAGIC 'M' -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define ION_IOC_CLEAN_CACHES _IOWR(ION_IOC_MSM_MAGIC, 0, struct ion_flush_data) #define ION_IOC_INV_CACHES _IOWR(ION_IOC_MSM_MAGIC, 1, struct ion_flush_data) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define ION_IOC_CLEAN_INV_CACHES _IOWR(ION_IOC_MSM_MAGIC, 2, struct ion_flush_data) #define ION_IOC_PREFETCH _IOWR(ION_IOC_MSM_MAGIC, 3, struct ion_prefetch_data) -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define ION_IOC_DRAIN _IOWR(ION_IOC_MSM_MAGIC, 4, struct ion_prefetch_data) #endif +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ diff --git a/kernel-headers/linux/msm_kgsl.h b/kernel-headers/linux/msm_kgsl.h index f54dfbd..715be75 100644 --- a/kernel-headers/linux/msm_kgsl.h +++ b/kernel-headers/linux/msm_kgsl.h @@ -34,64 +34,84 @@ #define KGSL_CONTEXT_END_OF_FRAME 0x00000100 #define KGSL_CONTEXT_NO_FAULT_TOLERANCE 0x00000200 #define KGSL_CONTEXT_SYNC 0x00000400 -#define KGSL_CONTEXT_PRIORITY_MASK 0x0000F000 +#define KGSL_CONTEXT_PWR_CONSTRAINT 0x00000800 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define KGSL_CONTEXT_PRIORITY_MASK 0x0000F000 #define KGSL_CONTEXT_PRIORITY_SHIFT 12 #define KGSL_CONTEXT_PRIORITY_UNDEF 0 #define KGSL_CONTEXT_TYPE_MASK 0x01F00000 -#define KGSL_CONTEXT_TYPE_SHIFT 20 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define KGSL_CONTEXT_TYPE_SHIFT 20 #define KGSL_CONTEXT_TYPE_ANY 0 #define KGSL_CONTEXT_TYPE_GL 1 #define KGSL_CONTEXT_TYPE_CL 2 -#define KGSL_CONTEXT_TYPE_C2D 3 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define KGSL_CONTEXT_TYPE_C2D 3 #define KGSL_CONTEXT_TYPE_RS 4 #define KGSL_CONTEXT_TYPE_UNKNOWN 0x1E #define KGSL_CONTEXT_INVALID 0xffffffff -#define KGSL_MEMFLAGS_GPUREADONLY 0x01000000 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define KGSL_MEMFLAGS_GPUREADONLY 0x01000000 #define KGSL_MEMFLAGS_USE_CPU_MAP 0x10000000 #define KGSL_CACHEMODE_MASK 0x0C000000 #define KGSL_CACHEMODE_SHIFT 26 -#define KGSL_CACHEMODE_WRITECOMBINE 0 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define KGSL_CACHEMODE_WRITECOMBINE 0 #define KGSL_CACHEMODE_UNCACHED 1 #define KGSL_CACHEMODE_WRITETHROUGH 2 #define KGSL_CACHEMODE_WRITEBACK 3 -#define KGSL_MEMTYPE_MASK 0x0000FF00 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define KGSL_MEMTYPE_MASK 0x0000FF00 #define KGSL_MEMTYPE_SHIFT 8 #define KGSL_MEMTYPE_OBJECTANY 0 #define KGSL_MEMTYPE_FRAMEBUFFER 1 -#define KGSL_MEMTYPE_RENDERBUFFER 2 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define KGSL_MEMTYPE_RENDERBUFFER 2 #define KGSL_MEMTYPE_ARRAYBUFFER 3 #define KGSL_MEMTYPE_ELEMENTARRAYBUFFER 4 #define KGSL_MEMTYPE_VERTEXARRAYBUFFER 5 -#define KGSL_MEMTYPE_TEXTURE 6 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define KGSL_MEMTYPE_TEXTURE 6 #define KGSL_MEMTYPE_SURFACE 7 #define KGSL_MEMTYPE_EGL_SURFACE 8 #define KGSL_MEMTYPE_GL 9 -#define KGSL_MEMTYPE_CL 10 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define KGSL_MEMTYPE_CL 10 #define KGSL_MEMTYPE_CL_BUFFER_MAP 11 #define KGSL_MEMTYPE_CL_BUFFER_NOMAP 12 #define KGSL_MEMTYPE_CL_IMAGE_MAP 13 -#define KGSL_MEMTYPE_CL_IMAGE_NOMAP 14 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define KGSL_MEMTYPE_CL_IMAGE_NOMAP 14 #define KGSL_MEMTYPE_CL_KERNEL_STACK 15 #define KGSL_MEMTYPE_COMMAND 16 #define KGSL_MEMTYPE_2D 17 -#define KGSL_MEMTYPE_EGL_IMAGE 18 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define KGSL_MEMTYPE_EGL_IMAGE 18 #define KGSL_MEMTYPE_EGL_SHADOW 19 #define KGSL_MEMTYPE_MULTISAMPLE 20 #define KGSL_MEMTYPE_KERNEL 255 -#define KGSL_MEMALIGN_MASK 0x00FF0000 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define KGSL_MEMALIGN_MASK 0x00FF0000 #define KGSL_MEMALIGN_SHIFT 16 +enum kgsl_user_mem_type { + KGSL_USER_MEM_TYPE_PMEM = 0x00000000, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + KGSL_USER_MEM_TYPE_ASHMEM = 0x00000001, + KGSL_USER_MEM_TYPE_ADDR = 0x00000002, + KGSL_USER_MEM_TYPE_ION = 0x00000003, + KGSL_USER_MEM_TYPE_MAX = 0x00000004, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +#define KGSL_MEMFLAGS_USERMEM_MASK 0x000000e0 +#define KGSL_MEMFLAGS_USERMEM_SHIFT 5 +#define KGSL_USERMEM_FLAG(x) (((x) + 1) << KGSL_MEMFLAGS_USERMEM_SHIFT) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define KGSL_MEMFLAGS_NOT_USERMEM 0 +#define KGSL_MEMFLAGS_USERMEM_PMEM KGSL_USERMEM_FLAG(KGSL_USER_MEM_TYPE_PMEM) +#define KGSL_MEMFLAGS_USERMEM_ASHMEM KGSL_USERMEM_FLAG(KGSL_USER_MEM_TYPE_ASHMEM) +#define KGSL_MEMFLAGS_USERMEM_ADDR KGSL_USERMEM_FLAG(KGSL_USER_MEM_TYPE_ADDR) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define KGSL_MEMFLAGS_USERMEM_ION KGSL_USERMEM_FLAG(KGSL_USER_MEM_TYPE_ION) #define KGSL_FLAGS_NORMALMODE 0x00000000 #define KGSL_FLAGS_SAFEMODE 0x00000001 #define KGSL_FLAGS_INITIALIZED0 0x00000002 @@ -131,459 +151,467 @@ enum kgsl_deviceid { KGSL_DEVICE_MAX = 0x00000003 }; /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ -enum kgsl_user_mem_type { - KGSL_USER_MEM_TYPE_PMEM = 0x00000000, - KGSL_USER_MEM_TYPE_ASHMEM = 0x00000001, - KGSL_USER_MEM_TYPE_ADDR = 0x00000002, -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ - KGSL_USER_MEM_TYPE_ION = 0x00000003, - KGSL_USER_MEM_TYPE_MAX = 0x00000004, -}; struct kgsl_devinfo { -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ unsigned int device_id; unsigned int chip_id; unsigned int mmu_enabled; - unsigned long gmem_gpubaseaddr; /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned long gmem_gpubaseaddr; unsigned int gpu_id; size_t gmem_sizebytes; }; -struct kgsl_devmemstore { /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct kgsl_devmemstore { volatile unsigned int soptimestamp; unsigned int sbz; volatile unsigned int eoptimestamp; - unsigned int sbz2; /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned int sbz2; volatile unsigned int ts_cmp_enable; unsigned int sbz3; volatile unsigned int ref_wait_ts; - unsigned int sbz4; /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned int sbz4; unsigned int current_context; unsigned int sbz5; }; -#define KGSL_MEMSTORE_OFFSET(ctxt_id, field) ((ctxt_id)*sizeof(struct kgsl_devmemstore) + offsetof(struct kgsl_devmemstore, field)) /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define KGSL_MEMSTORE_OFFSET(ctxt_id, field) ((ctxt_id)*sizeof(struct kgsl_devmemstore) + offsetof(struct kgsl_devmemstore, field)) enum kgsl_timestamp_type { KGSL_TIMESTAMP_CONSUMED = 0x00000001, KGSL_TIMESTAMP_RETIRED = 0x00000002, - KGSL_TIMESTAMP_QUEUED = 0x00000003, /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + KGSL_TIMESTAMP_QUEUED = 0x00000003, }; enum kgsl_property_type { KGSL_PROP_DEVICE_INFO = 0x00000001, - KGSL_PROP_DEVICE_SHADOW = 0x00000002, /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + KGSL_PROP_DEVICE_SHADOW = 0x00000002, KGSL_PROP_DEVICE_POWER = 0x00000003, KGSL_PROP_SHMEM = 0x00000004, KGSL_PROP_SHMEM_APERTURES = 0x00000005, - KGSL_PROP_MMU_ENABLE = 0x00000006, /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + KGSL_PROP_MMU_ENABLE = 0x00000006, KGSL_PROP_INTERRUPT_WAITS = 0x00000007, KGSL_PROP_VERSION = 0x00000008, KGSL_PROP_GPU_RESET_STAT = 0x00000009, - KGSL_PROP_PWRCTRL = 0x0000000E, /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + KGSL_PROP_PWRCTRL = 0x0000000E, + KGSL_PROP_PWR_CONSTRAINT = 0x00000012, }; struct kgsl_shadowprop { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ unsigned long gpuaddr; size_t size; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ unsigned int flags; }; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct kgsl_version { unsigned int drv_major; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ unsigned int drv_minor; unsigned int dev_major; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ unsigned int dev_minor; }; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define KGSL_PERFCOUNTER_GROUP_CP 0x0 #define KGSL_PERFCOUNTER_GROUP_RBBM 0x1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define KGSL_PERFCOUNTER_GROUP_PC 0x2 #define KGSL_PERFCOUNTER_GROUP_VFD 0x3 -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define KGSL_PERFCOUNTER_GROUP_HLSQ 0x4 #define KGSL_PERFCOUNTER_GROUP_VPC 0x5 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define KGSL_PERFCOUNTER_GROUP_TSE 0x6 #define KGSL_PERFCOUNTER_GROUP_RAS 0x7 -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define KGSL_PERFCOUNTER_GROUP_UCHE 0x8 #define KGSL_PERFCOUNTER_GROUP_TP 0x9 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define KGSL_PERFCOUNTER_GROUP_SP 0xA #define KGSL_PERFCOUNTER_GROUP_RB 0xB -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define KGSL_PERFCOUNTER_GROUP_PWR 0xC #define KGSL_PERFCOUNTER_GROUP_VBIF 0xD +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define KGSL_PERFCOUNTER_GROUP_VBIF_PWR 0xE #define KGSL_PERFCOUNTER_GROUP_MH 0xF -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define KGSL_PERFCOUNTER_GROUP_PA_SU 0x10 #define KGSL_PERFCOUNTER_GROUP_SQ 0x11 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define KGSL_PERFCOUNTER_GROUP_SX 0x12 #define KGSL_PERFCOUNTER_GROUP_TCF 0x13 -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define KGSL_PERFCOUNTER_GROUP_TCM 0x14 #define KGSL_PERFCOUNTER_GROUP_TCR 0x15 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define KGSL_PERFCOUNTER_GROUP_L2 0x16 #define KGSL_PERFCOUNTER_GROUP_VSC 0x17 -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define KGSL_PERFCOUNTER_GROUP_CCU 0x18 #define KGSL_PERFCOUNTER_GROUP_MAX 0x19 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define KGSL_PERFCOUNTER_NOT_USED 0xFFFFFFFF #define KGSL_PERFCOUNTER_BROKEN 0xFFFFFFFE -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct kgsl_ibdesc { unsigned long gpuaddr; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ unsigned long __pad; size_t sizedwords; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ unsigned int ctrl; }; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define KGSL_IOC_TYPE 0x09 struct kgsl_device_getproperty { -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ unsigned int type; void __user *value; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ size_t sizebytes; }; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define IOCTL_KGSL_DEVICE_GETPROPERTY _IOWR(KGSL_IOC_TYPE, 0x2, struct kgsl_device_getproperty) struct kgsl_device_waittimestamp { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ unsigned int timestamp; unsigned int timeout; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ }; #define IOCTL_KGSL_DEVICE_WAITTIMESTAMP _IOW(KGSL_IOC_TYPE, 0x6, struct kgsl_device_waittimestamp) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct kgsl_device_waittimestamp_ctxtid { unsigned int context_id; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ unsigned int timestamp; unsigned int timeout; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ }; #define IOCTL_KGSL_DEVICE_WAITTIMESTAMP_CTXTID _IOW(KGSL_IOC_TYPE, 0x7, struct kgsl_device_waittimestamp_ctxtid) -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct kgsl_ringbuffer_issueibcmds { unsigned int drawctxt_id; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ unsigned long ibdesc_addr; unsigned int numibs; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ unsigned int timestamp; unsigned int flags; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ }; #define IOCTL_KGSL_RINGBUFFER_ISSUEIBCMDS _IOWR(KGSL_IOC_TYPE, 0x10, struct kgsl_ringbuffer_issueibcmds) -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct kgsl_cmdstream_readtimestamp { unsigned int type; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ unsigned int timestamp; }; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define IOCTL_KGSL_CMDSTREAM_READTIMESTAMP_OLD _IOR(KGSL_IOC_TYPE, 0x11, struct kgsl_cmdstream_readtimestamp) #define IOCTL_KGSL_CMDSTREAM_READTIMESTAMP _IOWR(KGSL_IOC_TYPE, 0x11, struct kgsl_cmdstream_readtimestamp) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct kgsl_cmdstream_freememontimestamp { unsigned long gpuaddr; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ unsigned int type; unsigned int timestamp; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ }; #define IOCTL_KGSL_CMDSTREAM_FREEMEMONTIMESTAMP _IOW(KGSL_IOC_TYPE, 0x12, struct kgsl_cmdstream_freememontimestamp) -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define IOCTL_KGSL_CMDSTREAM_FREEMEMONTIMESTAMP_OLD _IOR(KGSL_IOC_TYPE, 0x12, struct kgsl_cmdstream_freememontimestamp) struct kgsl_drawctxt_create { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ unsigned int flags; unsigned int drawctxt_id; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ }; #define IOCTL_KGSL_DRAWCTXT_CREATE _IOWR(KGSL_IOC_TYPE, 0x13, struct kgsl_drawctxt_create) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct kgsl_drawctxt_destroy { unsigned int drawctxt_id; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ }; #define IOCTL_KGSL_DRAWCTXT_DESTROY _IOW(KGSL_IOC_TYPE, 0x14, struct kgsl_drawctxt_destroy) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct kgsl_map_user_mem { int fd; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ unsigned long gpuaddr; size_t len; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ size_t offset; unsigned long hostptr; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ enum kgsl_user_mem_type memtype; unsigned int flags; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ }; #define IOCTL_KGSL_MAP_USER_MEM _IOWR(KGSL_IOC_TYPE, 0x15, struct kgsl_map_user_mem) -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct kgsl_cmdstream_readtimestamp_ctxtid { unsigned int context_id; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ unsigned int type; unsigned int timestamp; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ }; #define IOCTL_KGSL_CMDSTREAM_READTIMESTAMP_CTXTID _IOWR(KGSL_IOC_TYPE, 0x16, struct kgsl_cmdstream_readtimestamp_ctxtid) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct kgsl_cmdstream_freememontimestamp_ctxtid { unsigned int context_id; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ unsigned long gpuaddr; unsigned int type; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ unsigned int timestamp; }; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define IOCTL_KGSL_CMDSTREAM_FREEMEMONTIMESTAMP_CTXTID _IOW(KGSL_IOC_TYPE, 0x17, struct kgsl_cmdstream_freememontimestamp_ctxtid) struct kgsl_sharedmem_from_pmem { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ int pmem_fd; unsigned long gpuaddr; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ unsigned int len; unsigned int offset; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ }; #define IOCTL_KGSL_SHAREDMEM_FROM_PMEM _IOWR(KGSL_IOC_TYPE, 0x20, struct kgsl_sharedmem_from_pmem) -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct kgsl_sharedmem_free { unsigned long gpuaddr; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ }; #define IOCTL_KGSL_SHAREDMEM_FREE _IOW(KGSL_IOC_TYPE, 0x21, struct kgsl_sharedmem_free) -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct kgsl_cff_user_event { unsigned char cff_opcode; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ unsigned int op1; unsigned int op2; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ unsigned int op3; unsigned int op4; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ unsigned int op5; unsigned int __pad[2]; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ }; #define IOCTL_KGSL_CFF_USER_EVENT _IOW(KGSL_IOC_TYPE, 0x31, struct kgsl_cff_user_event) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct kgsl_gmem_desc { unsigned int x; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ unsigned int y; unsigned int width; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ unsigned int height; unsigned int pitch; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ }; struct kgsl_buffer_desc { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ void *hostptr; unsigned long gpuaddr; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ int size; unsigned int format; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ unsigned int pitch; unsigned int enabled; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ }; struct kgsl_bind_gmem_shadow { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ unsigned int drawctxt_id; struct kgsl_gmem_desc gmem_desc; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ unsigned int shadow_x; unsigned int shadow_y; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct kgsl_buffer_desc shadow_buffer; unsigned int buffer_id; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ }; #define IOCTL_KGSL_DRAWCTXT_BIND_GMEM_SHADOW _IOW(KGSL_IOC_TYPE, 0x22, struct kgsl_bind_gmem_shadow) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct kgsl_sharedmem_from_vmalloc { unsigned long gpuaddr; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ unsigned int hostptr; unsigned int flags; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ }; #define IOCTL_KGSL_SHAREDMEM_FROM_VMALLOC _IOWR(KGSL_IOC_TYPE, 0x23, struct kgsl_sharedmem_from_vmalloc) -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define IOCTL_KGSL_SHAREDMEM_FLUSH_CACHE _IOW(KGSL_IOC_TYPE, 0x24, struct kgsl_sharedmem_free) struct kgsl_drawctxt_set_bin_base_offset { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ unsigned int drawctxt_id; unsigned int offset; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ }; #define IOCTL_KGSL_DRAWCTXT_SET_BIN_BASE_OFFSET _IOW(KGSL_IOC_TYPE, 0x25, struct kgsl_drawctxt_set_bin_base_offset) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ enum kgsl_cmdwindow_type { KGSL_CMDWINDOW_MIN = 0x00000000, -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ KGSL_CMDWINDOW_2D = 0x00000000, KGSL_CMDWINDOW_3D = 0x00000001, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ KGSL_CMDWINDOW_MMU = 0x00000002, KGSL_CMDWINDOW_ARBITER = 0x000000FF, -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ KGSL_CMDWINDOW_MAX = 0x000000FF, }; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct kgsl_cmdwindow_write { enum kgsl_cmdwindow_type target; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ unsigned int addr; unsigned int data; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ }; #define IOCTL_KGSL_CMDWINDOW_WRITE _IOW(KGSL_IOC_TYPE, 0x2e, struct kgsl_cmdwindow_write) -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct kgsl_gpumem_alloc { unsigned long gpuaddr; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ size_t size; unsigned int flags; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ }; #define IOCTL_KGSL_GPUMEM_ALLOC _IOWR(KGSL_IOC_TYPE, 0x2f, struct kgsl_gpumem_alloc) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct kgsl_cff_syncmem { unsigned long gpuaddr; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ size_t len; unsigned int __pad[2]; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ }; #define IOCTL_KGSL_CFF_SYNCMEM _IOW(KGSL_IOC_TYPE, 0x30, struct kgsl_cff_syncmem) -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct kgsl_timestamp_event { int type; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ unsigned int timestamp; unsigned int context_id; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ void __user *priv; size_t len; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ }; #define IOCTL_KGSL_TIMESTAMP_EVENT_OLD _IOW(KGSL_IOC_TYPE, 0x31, struct kgsl_timestamp_event) -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define KGSL_TIMESTAMP_EVENT_GENLOCK 1 struct kgsl_timestamp_event_genlock { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ int handle; }; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define KGSL_TIMESTAMP_EVENT_FENCE 2 struct kgsl_timestamp_event_fence { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ int fence_fd; }; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define IOCTL_KGSL_SETPROPERTY _IOW(KGSL_IOC_TYPE, 0x32, struct kgsl_device_getproperty) #define IOCTL_KGSL_TIMESTAMP_EVENT _IOWR(KGSL_IOC_TYPE, 0x33, struct kgsl_timestamp_event) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct kgsl_gpumem_alloc_id { unsigned int id; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ unsigned int flags; size_t size; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ size_t mmapsize; unsigned long gpuaddr; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ unsigned long __pad[2]; }; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define IOCTL_KGSL_GPUMEM_ALLOC_ID _IOWR(KGSL_IOC_TYPE, 0x34, struct kgsl_gpumem_alloc_id) struct kgsl_gpumem_free_id { -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ unsigned int id; unsigned int __pad; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ }; #define IOCTL_KGSL_GPUMEM_FREE_ID _IOWR(KGSL_IOC_TYPE, 0x35, struct kgsl_gpumem_free_id) -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct kgsl_gpumem_get_info { unsigned long gpuaddr; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ unsigned int id; unsigned int flags; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ size_t size; size_t mmapsize; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ unsigned long useraddr; unsigned long __pad[4]; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ }; #define IOCTL_KGSL_GPUMEM_GET_INFO _IOWR(KGSL_IOC_TYPE, 0x36, struct kgsl_gpumem_get_info) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct kgsl_gpumem_sync_cache { unsigned long gpuaddr; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ unsigned int id; unsigned int op; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ unsigned long __pad[2]; }; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define KGSL_GPUMEM_CACHE_CLEAN (1 << 0) #define KGSL_GPUMEM_CACHE_TO_GPU KGSL_GPUMEM_CACHE_CLEAN +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define KGSL_GPUMEM_CACHE_INV (1 << 1) #define KGSL_GPUMEM_CACHE_FROM_GPU KGSL_GPUMEM_CACHE_INV -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define KGSL_GPUMEM_CACHE_FLUSH (KGSL_GPUMEM_CACHE_CLEAN | KGSL_GPUMEM_CACHE_INV) #define IOCTL_KGSL_GPUMEM_SYNC_CACHE _IOW(KGSL_IOC_TYPE, 0x37, struct kgsl_gpumem_sync_cache) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct kgsl_perfcounter_get { unsigned int groupid; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ unsigned int countable; unsigned int offset; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ unsigned int offset_hi; unsigned int __pad; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ }; #define IOCTL_KGSL_PERFCOUNTER_GET _IOWR(KGSL_IOC_TYPE, 0x38, struct kgsl_perfcounter_get) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct kgsl_perfcounter_put { unsigned int groupid; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ unsigned int countable; unsigned int __pad[2]; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ }; #define IOCTL_KGSL_PERFCOUNTER_PUT _IOW(KGSL_IOC_TYPE, 0x39, struct kgsl_perfcounter_put) -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct kgsl_perfcounter_query { unsigned int groupid; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ unsigned int __user *countables; unsigned int count; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ unsigned int max_counters; unsigned int __pad[2]; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ }; #define IOCTL_KGSL_PERFCOUNTER_QUERY _IOWR(KGSL_IOC_TYPE, 0x3A, struct kgsl_perfcounter_query) -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct kgsl_perfcounter_read_group { unsigned int groupid; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ unsigned int countable; unsigned long long value; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ }; struct kgsl_perfcounter_read { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct kgsl_perfcounter_read_group __user *reads; unsigned int count; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ unsigned int __pad[2]; }; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define IOCTL_KGSL_PERFCOUNTER_READ _IOWR(KGSL_IOC_TYPE, 0x3B, struct kgsl_perfcounter_read) struct kgsl_gpumem_sync_cache_bulk { -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ unsigned int __user *id_list; unsigned int count; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ unsigned int op; unsigned int __pad[2]; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ }; #define IOCTL_KGSL_GPUMEM_SYNC_CACHE_BULK _IOWR(KGSL_IOC_TYPE, 0x3C, struct kgsl_gpumem_sync_cache_bulk) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct kgsl_cmd_syncpoint_timestamp { unsigned int context_id; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ unsigned int timestamp; }; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define KGSL_CMD_SYNCPOINT_TYPE_TIMESTAMP 0 struct kgsl_cmd_syncpoint_fence { -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ int fd; }; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define KGSL_CMD_SYNCPOINT_TYPE_FENCE 1 struct kgsl_cmd_syncpoint { -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ int type; void __user *priv; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ size_t size; }; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct kgsl_submit_commands { unsigned int context_id; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ unsigned int flags; struct kgsl_ibdesc __user *cmdlist; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ unsigned int numcmds; struct kgsl_cmd_syncpoint __user *synclist; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ unsigned int numsyncs; unsigned int timestamp; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ unsigned int __pad[4]; }; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define IOCTL_KGSL_SUBMIT_COMMANDS _IOWR(KGSL_IOC_TYPE, 0x3D, struct kgsl_submit_commands) -#endif +struct kgsl_device_constraint { + unsigned int type; + unsigned int context_id; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + void __user *data; + size_t size; +}; +#define KGSL_CONSTRAINT_NONE 0 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define KGSL_CONSTRAINT_PWRLEVEL 1 +#define KGSL_CONSTRAINT_PWR_MIN 0 +#define KGSL_CONSTRAINT_PWR_MAX 1 +struct kgsl_device_constraint_pwrlevel { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned int level; +}; +#endif diff --git a/kernel-headers/linux/msm_mdp.h b/kernel-headers/linux/msm_mdp.h index 345f504..3c227cc 100644 --- a/kernel-headers/linux/msm_mdp.h +++ b/kernel-headers/linux/msm_mdp.h @@ -73,10 +73,30 @@ /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define MSMFB_WRITEBACK_SET_MIRRORING_HINT _IOW(MSMFB_IOCTL_MAGIC, 167, unsigned int) #define MSMFB_ASYNC_BLIT _IOW(MSMFB_IOCTL_MAGIC, 168, unsigned int) +#define MSMFB_OVERLAY_PREPARE _IOWR(MSMFB_IOCTL_MAGIC, 169, struct mdp_overlay_list) #define FB_TYPE_3D_PANEL 0x10101010 -#define MDP_IMGTYPE2_START 0x10000 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define MDP_IMGTYPE2_START 0x10000 #define MSMFB_DRIVER_VERSION 0xF9E8D701 +#define MDSS_GET_MAJOR(rev) ((rev) >> 28) +#define MDSS_GET_MINOR(rev) (((rev) >> 16) & 0xFFF) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define MDSS_GET_STEP(rev) ((rev) & 0xFFFF) +#define MDSS_GET_MAJOR_MINOR(rev) ((rev) >> 16) +#define IS_MDSS_MAJOR_MINOR_SAME(rev1, rev2) (MDSS_GET_MAJOR_MINOR((rev1)) == MDSS_GET_MAJOR_MINOR((rev2))) +#define MDSS_MDP_REV(major, minor, step) ((((major) & 0x000F) << 28) | (((minor) & 0x0FFF) << 16) | ((step) & 0xFFFF)) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define MDSS_MDP_HW_REV_100 MDSS_MDP_REV(1, 0, 0) +#define MDSS_MDP_HW_REV_101 MDSS_MDP_REV(1, 1, 0) +#define MDSS_MDP_HW_REV_101_1 MDSS_MDP_REV(1, 1, 1) +#define MDSS_MDP_HW_REV_101_2 MDSS_MDP_REV(1, 1, 2) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define MDSS_MDP_HW_REV_102 MDSS_MDP_REV(1, 2, 0) +#define MDSS_MDP_HW_REV_102_1 MDSS_MDP_REV(1, 2, 1) +#define MDSS_MDP_HW_REV_103 MDSS_MDP_REV(1, 3, 0) +#define MDSS_MDP_HW_REV_103_1 MDSS_MDP_REV(1, 3, 1) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define MDSS_MDP_HW_REV_200 MDSS_MDP_REV(2, 0, 0) enum { NOTIFY_UPDATE_START, NOTIFY_UPDATE_STOP, @@ -138,626 +158,631 @@ enum { /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ MDP_BGRX_8888_TILE, MDP_YCBYCR_H2V1, + MDP_RGB_565_TILE, + MDP_BGR_565_TILE, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ MDP_IMGTYPE_LIMIT, MDP_RGB_BORDERFILL, -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ MDP_FB_FORMAT = MDP_IMGTYPE2_START, MDP_IMGTYPE_LIMIT2 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ }; enum { -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ PMEM_IMG, FB_IMG, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ }; enum { -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ HSIC_HUE = 0, HSIC_SAT, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ HSIC_INT, HSIC_CON, -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ NUM_HSIC_PARAM, }; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define MDSS_MDP_ROT_ONLY 0x80 #define MDSS_MDP_RIGHT_MIXER 0x100 -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define MDSS_MDP_DUAL_PIPE 0x200 #define MDP_ROT_NOP 0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define MDP_FLIP_LR 0x1 #define MDP_FLIP_UD 0x2 -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define MDP_ROT_90 0x4 #define MDP_ROT_180 (MDP_FLIP_UD|MDP_FLIP_LR) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define MDP_ROT_270 (MDP_ROT_90|MDP_FLIP_UD|MDP_FLIP_LR) #define MDP_DITHER 0x8 -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define MDP_BLUR 0x10 #define MDP_BLEND_FG_PREMULT 0x20000 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define MDP_IS_FG 0x40000 #define MDP_SOLID_FILL 0x00000020 -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define MDP_VPU_PIPE 0x00000040 #define MDP_DEINTERLACE 0x80000000 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define MDP_SHARPENING 0x40000000 #define MDP_NO_DMA_BARRIER_START 0x20000000 #define MDP_NO_DMA_BARRIER_END 0x10000000 -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define MDP_NO_BLIT 0x08000000 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define MDP_BLIT_WITH_DMA_BARRIERS 0x000 #define MDP_BLIT_WITH_NO_DMA_BARRIERS (MDP_NO_DMA_BARRIER_START | MDP_NO_DMA_BARRIER_END) #define MDP_BLIT_SRC_GEM 0x04000000 -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define MDP_BLIT_DST_GEM 0x02000000 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define MDP_BLIT_NON_CACHED 0x01000000 #define MDP_OV_PIPE_SHARE 0x00800000 #define MDP_DEINTERLACE_ODD 0x00400000 -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define MDP_OV_PLAY_NOWAIT 0x00200000 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define MDP_SOURCE_ROTATED_90 0x00100000 #define MDP_OVERLAY_PP_CFG_EN 0x00080000 #define MDP_BACKEND_COMPOSITION 0x00040000 -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define MDP_BORDERFILL_SUPPORTED 0x00010000 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define MDP_SECURE_OVERLAY_SESSION 0x00008000 #define MDP_SECURE_DISPLAY_OVERLAY_SESSION 0x00002000 #define MDP_OV_PIPE_FORCE_DMA 0x00004000 -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define MDP_MEMORY_ID_TYPE_FB 0x00001000 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define MDP_BWC_EN 0x00000400 #define MDP_DECIMATION_EN 0x00000800 #define MDP_TRANSP_NOP 0xffffffff -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define MDP_ALPHA_NOP 0xff +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define MDP_FB_PAGE_PROTECTION_NONCACHED (0) #define MDP_FB_PAGE_PROTECTION_WRITECOMBINE (1) #define MDP_FB_PAGE_PROTECTION_WRITETHROUGHCACHE (2) -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define MDP_FB_PAGE_PROTECTION_WRITEBACKCACHE (3) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define MDP_FB_PAGE_PROTECTION_WRITEBACKWACACHE (4) #define MDP_FB_PAGE_PROTECTION_INVALID (5) #define MDP_NUM_FB_PAGE_PROTECTION_VALUES (5) -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct mdp_rect { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint32_t x; uint32_t y; uint32_t w; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint32_t h; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ }; struct mdp_img { uint32_t width; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint32_t height; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint32_t format; uint32_t offset; int memory_id; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint32_t priv; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ }; #define MDP_CCS_RGB2YUV 0 #define MDP_CCS_YUV2RGB 1 -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define MDP_CCS_SIZE 9 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define MDP_BV_SIZE 3 struct mdp_ccs { int direction; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint16_t ccs[MDP_CCS_SIZE]; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint16_t bv[MDP_BV_SIZE]; }; struct mdp_csc { -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ int id; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint32_t csc_mv[9]; uint32_t csc_pre_bv[3]; uint32_t csc_post_bv[3]; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint32_t csc_pre_lv[6]; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint32_t csc_post_lv[6]; }; #define MDP_BLIT_REQ_VERSION 2 -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct color { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint32_t r; uint32_t g; uint32_t b; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint32_t alpha; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ }; struct mdp_blit_req { struct mdp_img src; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct mdp_img dst; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct mdp_rect src_rect; struct mdp_rect dst_rect; struct color const_color; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint32_t alpha; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint32_t transp_mask; uint32_t flags; int sharpening_strength; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ }; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct mdp_blit_req_list { uint32_t count; struct mdp_blit_req req[]; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ }; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define MSMFB_DATA_VERSION 2 struct msmfb_data { uint32_t offset; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ int memory_id; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ int id; uint32_t flags; uint32_t priv; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint32_t iova; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ }; #define MSMFB_NEW_REQUEST -1 struct msmfb_overlay_data { -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint32_t id; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct msmfb_data data; uint32_t version_key; struct msmfb_data plane1_data; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct msmfb_data plane2_data; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct msmfb_data dst_data; }; struct msmfb_img { -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint32_t width; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint32_t height; uint32_t format; }; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define MSMFB_WRITEBACK_DEQUEUE_BLOCKING 0x1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct msmfb_writeback_data { struct msmfb_data buf_info; struct msmfb_img img; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ }; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define MDP_PP_OPS_ENABLE 0x1 #define MDP_PP_OPS_READ 0x2 #define MDP_PP_OPS_WRITE 0x4 -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define MDP_PP_OPS_DISABLE 0x8 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define MDP_PP_IGC_FLAG_ROM0 0x10 #define MDP_PP_IGC_FLAG_ROM1 0x20 #define MDP_PP_PA_HUE_ENABLE 0x10 -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define MDP_PP_PA_SAT_ENABLE 0x20 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define MDP_PP_PA_VAL_ENABLE 0x40 #define MDP_PP_PA_CONT_ENABLE 0x80 #define MDP_PP_PA_SIX_ZONE_ENABLE 0x100 -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define MDP_PP_PA_SKIN_ENABLE 0x200 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define MDP_PP_PA_SKY_ENABLE 0x400 #define MDP_PP_PA_FOL_ENABLE 0x800 #define MDP_PP_PA_HUE_MASK 0x1000 -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define MDP_PP_PA_SAT_MASK 0x2000 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define MDP_PP_PA_VAL_MASK 0x4000 #define MDP_PP_PA_CONT_MASK 0x8000 #define MDP_PP_PA_SIX_ZONE_HUE_MASK 0x10000 -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define MDP_PP_PA_SIX_ZONE_SAT_MASK 0x20000 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define MDP_PP_PA_SIX_ZONE_VAL_MASK 0x40000 #define MDP_PP_PA_MEM_COL_SKIN_MASK 0x80000 #define MDP_PP_PA_MEM_COL_SKY_MASK 0x100000 -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define MDP_PP_PA_MEM_COL_FOL_MASK 0x200000 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define MDP_PP_PA_MEM_PROTECT_EN 0x400000 #define MDP_PP_PA_SAT_ZERO_EXP_EN 0x800000 #define MDSS_PP_DSPP_CFG 0x000 -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define MDSS_PP_SSPP_CFG 0x100 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define MDSS_PP_LM_CFG 0x200 #define MDSS_PP_WB_CFG 0x300 #define MDSS_PP_ARG_MASK 0x3C00 -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define MDSS_PP_ARG_NUM 4 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define MDSS_PP_ARG_SHIFT 10 #define MDSS_PP_LOCATION_MASK 0x0300 #define MDSS_PP_LOGICAL_MASK 0x00FF -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define MDSS_PP_ADD_ARG(var, arg) ((var) | (0x1 << (MDSS_PP_ARG_SHIFT + (arg)))) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define PP_ARG(x, var) ((var) & (0x1 << (MDSS_PP_ARG_SHIFT + (x)))) #define PP_LOCAT(var) ((var) & MDSS_PP_LOCATION_MASK) #define PP_BLOCK(var) ((var) & MDSS_PP_LOGICAL_MASK) -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct mdp_qseed_cfg { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint32_t table_num; uint32_t ops; uint32_t len; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint32_t *data; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ }; struct mdp_sharp_cfg { uint32_t flags; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint32_t strength; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint32_t edge_thr; uint32_t smooth_thr; uint32_t noise_thr; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ }; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct mdp_qseed_cfg_data { uint32_t block; struct mdp_qseed_cfg qseed_data; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ }; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define MDP_OVERLAY_PP_CSC_CFG 0x1 #define MDP_OVERLAY_PP_QSEED_CFG 0x2 #define MDP_OVERLAY_PP_PA_CFG 0x4 -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define MDP_OVERLAY_PP_IGC_CFG 0x8 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define MDP_OVERLAY_PP_SHARP_CFG 0x10 #define MDP_OVERLAY_PP_HIST_CFG 0x20 #define MDP_OVERLAY_PP_HIST_LUT_CFG 0x40 -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define MDP_OVERLAY_PP_PA_V2_CFG 0x80 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define MDP_CSC_FLAG_ENABLE 0x1 #define MDP_CSC_FLAG_YUV_IN 0x2 #define MDP_CSC_FLAG_YUV_OUT 0x4 -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct mdp_csc_cfg { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint32_t flags; uint32_t csc_mv[9]; uint32_t csc_pre_bv[3]; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint32_t csc_post_bv[3]; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint32_t csc_pre_lv[6]; uint32_t csc_post_lv[6]; }; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct mdp_csc_cfg_data { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint32_t block; struct mdp_csc_cfg csc_data; }; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct mdp_pa_cfg { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint32_t flags; uint32_t hue_adj; uint32_t sat_adj; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint32_t val_adj; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint32_t cont_adj; }; struct mdp_pa_mem_col_cfg { -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint32_t color_adjust_p0; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint32_t color_adjust_p1; uint32_t hue_region; uint32_t sat_region; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint32_t val_region; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ }; #define MDP_SIX_ZONE_LUT_SIZE 384 struct mdp_pa_v2_data { -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint32_t flags; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint32_t global_hue_adj; uint32_t global_sat_adj; uint32_t global_val_adj; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint32_t global_cont_adj; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct mdp_pa_mem_col_cfg skin_cfg; struct mdp_pa_mem_col_cfg sky_cfg; struct mdp_pa_mem_col_cfg fol_cfg; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint32_t six_zone_len; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint32_t six_zone_thresh; uint32_t *six_zone_curve_p0; uint32_t *six_zone_curve_p1; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ }; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct mdp_igc_lut_data { uint32_t block; uint32_t len, ops; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint32_t *c0_c1_data; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint32_t *c2_data; }; struct mdp_histogram_cfg { -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint32_t ops; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint32_t block; uint8_t frame_cnt; uint8_t bit_mask; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint16_t num_bins; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ }; struct mdp_hist_lut_data { uint32_t block; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint32_t ops; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint32_t len; uint32_t *data; }; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct mdp_overlay_pp_params { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint32_t config_ops; struct mdp_csc_cfg csc_cfg; struct mdp_qseed_cfg qseed_cfg[2]; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct mdp_pa_cfg pa_cfg; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct mdp_pa_v2_data pa_v2_cfg; struct mdp_igc_lut_data igc_cfg; struct mdp_sharp_cfg sharp_cfg; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct mdp_histogram_cfg hist_cfg; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct mdp_hist_lut_data hist_lut_cfg; }; enum mdss_mdp_blend_op { -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ BLEND_OP_NOT_DEFINED = 0, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ BLEND_OP_OPAQUE, BLEND_OP_PREMULTIPLIED, BLEND_OP_COVERAGE, -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ BLEND_OP_MAX, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ }; #define MAX_PLANES 4 struct mdp_scale_data { -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint8_t enable_pxl_ext; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ int init_phase_x[MAX_PLANES]; int phase_step_x[MAX_PLANES]; int init_phase_y[MAX_PLANES]; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ int phase_step_y[MAX_PLANES]; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ int num_ext_pxls_left[MAX_PLANES]; int num_ext_pxls_right[MAX_PLANES]; int num_ext_pxls_top[MAX_PLANES]; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ int num_ext_pxls_btm[MAX_PLANES]; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ int left_ftch[MAX_PLANES]; int left_rpt[MAX_PLANES]; int right_ftch[MAX_PLANES]; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ int right_rpt[MAX_PLANES]; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ int top_rpt[MAX_PLANES]; int btm_rpt[MAX_PLANES]; int top_ftch[MAX_PLANES]; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ int btm_ftch[MAX_PLANES]; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint32_t roi_w[MAX_PLANES]; }; struct mdp_overlay { -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct msmfb_img src; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct mdp_rect src_rect; struct mdp_rect dst_rect; uint32_t z_order; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint32_t is_fg; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint32_t alpha; uint32_t blend_op; uint32_t transp_mask; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint32_t flags; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint32_t id; uint32_t user_data[6]; uint32_t bg_color; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint8_t horz_deci; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint8_t vert_deci; struct mdp_overlay_pp_params overlay_pp_cfg; struct mdp_scale_data scale; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ }; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct msmfb_overlay_3d { uint32_t is_3d; uint32_t width; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint32_t height; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ }; struct msmfb_overlay_blt { uint32_t enable; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint32_t offset; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint32_t width; uint32_t height; uint32_t bpp; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ }; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct mdp_histogram { uint32_t frame_cnt; uint32_t bin_cnt; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint32_t *r; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint32_t *g; uint32_t *b; }; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define MISR_CRC_BATCH_SIZE 32 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ enum { DISPLAY_MISR_EDP, DISPLAY_MISR_DSI0, -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ DISPLAY_MISR_DSI1, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ DISPLAY_MISR_HDMI, DISPLAY_MISR_LCDC, DISPLAY_MISR_MDP, -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ DISPLAY_MISR_ATV, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ DISPLAY_MISR_DSI_CMD, DISPLAY_MISR_MAX }; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ enum { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ MISR_OP_NONE, MISR_OP_SFM, MISR_OP_MFM, -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ MISR_OP_BM, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ MISR_OP_MAX }; struct mdp_misr { -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint32_t block_id; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint32_t frame_count; uint32_t crc_op_mode; uint32_t crc_value[MISR_CRC_BATCH_SIZE]; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ }; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ enum { MDP_BLOCK_RESERVED = 0, MDP_BLOCK_OVERLAY_0, -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ MDP_BLOCK_OVERLAY_1, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ MDP_BLOCK_VG_1, MDP_BLOCK_VG_2, MDP_BLOCK_RGB_1, -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ MDP_BLOCK_RGB_2, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ MDP_BLOCK_DMA_P, MDP_BLOCK_DMA_S, MDP_BLOCK_DMA_E, -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ MDP_BLOCK_OVERLAY_2, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ MDP_LOGICAL_BLOCK_DISP_0 = 0x10, MDP_LOGICAL_BLOCK_DISP_1, MDP_LOGICAL_BLOCK_DISP_2, -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ MDP_BLOCK_MAX, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ }; struct mdp_histogram_start_req { uint32_t block; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint8_t frame_cnt; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint8_t bit_mask; uint16_t num_bins; }; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct mdp_histogram_data { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint32_t block; uint32_t bin_cnt; uint32_t *c0; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint32_t *c1; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint32_t *c2; uint32_t *extra_info; }; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct mdp_pcc_coeff { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint32_t c, r, g, b, rr, gg, bb, rg, gb, rb, rgb_0, rgb_1; }; struct mdp_pcc_cfg_data { -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint32_t block; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint32_t ops; struct mdp_pcc_coeff r, g, b; }; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define MDP_GAMUT_TABLE_NUM 8 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ enum { mdp_lut_igc, mdp_lut_pgc, -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ mdp_lut_hist, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ mdp_lut_max, }; struct mdp_ar_gc_lut_data { -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint32_t x_start; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint32_t slope; uint32_t offset; }; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct mdp_pgc_lut_data { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint32_t block; uint32_t flags; uint8_t num_r_stages; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint8_t num_g_stages; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint8_t num_b_stages; struct mdp_ar_gc_lut_data *r_data; struct mdp_ar_gc_lut_data *g_data; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct mdp_ar_gc_lut_data *b_data; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ }; struct mdp_lut_cfg_data { uint32_t lut_type; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ union { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct mdp_igc_lut_data igc_lut_data; struct mdp_pgc_lut_data pgc_lut_data; struct mdp_hist_lut_data hist_lut_data; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ } data; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ }; struct mdp_bl_scale_data { uint32_t min_lvl; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint32_t scale; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ }; struct mdp_pa_cfg_data { uint32_t block; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct mdp_pa_cfg pa_data; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ }; struct mdp_pa_v2_cfg_data { uint32_t block; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct mdp_pa_v2_data pa_v2_data; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ }; struct mdp_dither_cfg_data { uint32_t block; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint32_t flags; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint32_t g_y_depth; uint32_t r_cr_depth; uint32_t b_cb_depth; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ }; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct mdp_gamut_cfg_data { uint32_t block; uint32_t flags; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint32_t gamut_first; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint32_t tbl_size[MDP_GAMUT_TABLE_NUM]; uint16_t *r_tbl[MDP_GAMUT_TABLE_NUM]; uint16_t *g_tbl[MDP_GAMUT_TABLE_NUM]; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint16_t *b_tbl[MDP_GAMUT_TABLE_NUM]; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ }; struct mdp_calib_config_data { uint32_t ops; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint32_t addr; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint32_t data; }; struct mdp_calib_config_buffer { -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint32_t ops; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint32_t size; uint32_t *buffer; }; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct mdp_calib_dcm_state { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint32_t ops; uint32_t dcm_state; }; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ enum { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ DCM_UNINIT, DCM_UNBLANK, DCM_ENTER, -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ DCM_EXIT, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ DCM_BLANK, DTM_ENTER, DTM_EXIT, -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ }; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define MDSS_PP_SPLIT_LEFT_ONLY 0x10000000 #define MDSS_PP_SPLIT_RIGHT_ONLY 0x20000000 #define MDSS_PP_SPLIT_MASK 0x30000000 -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define MDSS_MAX_BL_BRIGHTNESS 255 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define AD_BL_LIN_LEN 256 +#define AD_BL_ATT_LUT_LEN 33 #define MDSS_AD_MODE_AUTO_BL 0x0 #define MDSS_AD_MODE_AUTO_STR 0x1 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ @@ -789,10 +814,15 @@ struct mdss_ad_init { uint16_t frame_h; uint8_t logo_v; uint8_t logo_h; - uint32_t bl_lin_len; + uint32_t alpha; /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t alpha_base; + uint32_t bl_lin_len; + uint32_t bl_att_len; uint32_t *bl_lin; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint32_t *bl_lin_inv; + uint32_t *bl_att_lut; }; #define MDSS_AD_BL_CTRL_MODE_EN 1 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ @@ -931,53 +961,63 @@ struct mdss_hw_caps { uint8_t vig_pipes; uint8_t dma_pipes; /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint8_t max_smp_cnt; + uint8_t smp_per_pipe; uint32_t features; }; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct msmfb_metadata { uint32_t op; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint32_t flags; union { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct mdp_misr misr_request; struct mdp_blend_cfg blend_cfg; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct mdp_mixer_cfg mixer_cfg; uint32_t panel_frame_rate; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint32_t video_info_code; struct mdss_hw_caps caps; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint8_t secure_en; } data; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ }; #define MDP_MAX_FENCE_FD 32 -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define MDP_BUF_SYNC_FLAG_WAIT 1 #define MDP_BUF_SYNC_FLAG_RETIRE_FENCE 0x10 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct mdp_buf_sync { uint32_t flags; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint32_t acq_fen_fd_cnt; uint32_t session_id; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ int *acq_fen_fd; int *rel_fen_fd; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ int *retire_fen_fd; }; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct mdp_async_blit_req_list { struct mdp_buf_sync sync; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint32_t count; struct mdp_blit_req req[]; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ }; #define MDP_DISPLAY_COMMIT_OVERLAY 1 -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct mdp_display_commit { uint32_t flags; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint32_t wait_for_finish; struct fb_var_screeninfo var; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct mdp_rect roi; }; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct mdp_overlay_list { + uint32_t num_overlays; + struct mdp_overlay **overlay_list; + uint32_t flags; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t processed_overlays; +}; struct mdp_page_protection { uint32_t page_protection; /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ @@ -1017,3 +1057,4 @@ enum { }; /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #endif + diff --git a/original-kernel-headers/linux/ion.h b/original-kernel-headers/linux/ion.h index 46451a0..19d57ec 100644 --- a/original-kernel-headers/linux/ion.h +++ b/original-kernel-headers/linux/ion.h @@ -20,8 +20,7 @@ #include <linux/ioctl.h> #include <linux/types.h> -struct ion_handle; -typedef struct ion_handle *ion_user_handle_t; +typedef int ion_user_handle_t; /** * enum ion_heap_types - list of all possible types of heaps diff --git a/original-kernel-headers/linux/msm_ion.h b/original-kernel-headers/linux/msm_ion.h index 60469dd..19d57ec 100644 --- a/original-kernel-headers/linux/msm_ion.h +++ b/original-kernel-headers/linux/msm_ion.h @@ -1,7 +1,7 @@ /* * include/linux/ion.h * - * Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. + * Copyright (C) 2011 Google, Inc. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and @@ -14,181 +14,185 @@ * */ -#ifndef _UAPI_MSM_ION_H -#define _UAPI_MSM_ION_H - -#include <linux/ion.h> - -enum msm_ion_heap_types { - ION_HEAP_TYPE_MSM_START = ION_HEAP_TYPE_CUSTOM + 1, - ION_HEAP_TYPE_DMA = ION_HEAP_TYPE_MSM_START, - ION_HEAP_TYPE_CP, - ION_HEAP_TYPE_SECURE_DMA, - ION_HEAP_TYPE_REMOVED, - /* - * if you add a heap type here you should also add it to - * heap_types_info[] in msm_ion.c - */ -}; +#ifndef _UAPI_ION_H +#define _UAPI_ION_H -/** - * These are the only ids that should be used for Ion heap ids. - * The ids listed are the order in which allocation will be attempted - * if specified. Don't swap the order of heap ids unless you know what - * you are doing! - * Id's are spaced by purpose to allow new Id's to be inserted in-between (for - * possible fallbacks) - */ +#include <linux/ioctl.h> +#include <linux/types.h> -enum ion_heap_ids { - INVALID_HEAP_ID = -1, - ION_CP_MM_HEAP_ID = 8, - ION_CP_MFC_HEAP_ID = 12, - ION_CP_WB_HEAP_ID = 16, /* 8660 only */ - ION_CAMERA_HEAP_ID = 20, /* 8660 only */ - ION_SYSTEM_CONTIG_HEAP_ID = 21, - ION_ADSP_HEAP_ID = 22, - ION_PIL1_HEAP_ID = 23, /* Currently used for other PIL images */ - ION_SF_HEAP_ID = 24, - ION_SYSTEM_HEAP_ID = 25, - ION_PIL2_HEAP_ID = 26, /* Currently used for modem firmware images */ - ION_QSECOM_HEAP_ID = 27, - ION_AUDIO_HEAP_ID = 28, - - ION_MM_FIRMWARE_HEAP_ID = 29, - - ION_HEAP_ID_RESERVED = 31 /** Bit reserved for ION_FLAG_SECURE flag */ -}; +typedef int ion_user_handle_t; -/* - * The IOMMU heap is deprecated! Here are some aliases for backwards - * compatibility: +/** + * enum ion_heap_types - list of all possible types of heaps + * @ION_HEAP_TYPE_SYSTEM: memory allocated via vmalloc + * @ION_HEAP_TYPE_SYSTEM_CONTIG: memory allocated via kmalloc + * @ION_HEAP_TYPE_CARVEOUT: memory allocated from a prereserved + * carveout heap, allocations are physically + * contiguous + * @ION_HEAP_END: helper for iterating over heaps */ -#define ION_IOMMU_HEAP_ID ION_SYSTEM_HEAP_ID -#define ION_HEAP_TYPE_IOMMU ION_HEAP_TYPE_SYSTEM - -enum ion_fixed_position { - NOT_FIXED, - FIXED_LOW, - FIXED_MIDDLE, - FIXED_HIGH, +enum ion_heap_type { + ION_HEAP_TYPE_SYSTEM, + ION_HEAP_TYPE_SYSTEM_CONTIG, + ION_HEAP_TYPE_CARVEOUT, + ION_HEAP_TYPE_CHUNK, + ION_HEAP_TYPE_CUSTOM, /* must be last so device specific heaps always + are at the end of this enum */ + ION_NUM_HEAPS, }; -enum cp_mem_usage { - VIDEO_BITSTREAM = 0x1, - VIDEO_PIXEL = 0x2, - VIDEO_NONPIXEL = 0x3, - MAX_USAGE = 0x4, - UNKNOWN = 0x7FFFFFFF, -}; +#define ION_HEAP_SYSTEM_MASK (1 << ION_HEAP_TYPE_SYSTEM) +#define ION_HEAP_SYSTEM_CONTIG_MASK (1 << ION_HEAP_TYPE_SYSTEM_CONTIG) +#define ION_HEAP_CARVEOUT_MASK (1 << ION_HEAP_TYPE_CARVEOUT) -#define ION_HEAP_CP_MASK (1 << ION_HEAP_TYPE_CP) -#define ION_HEAP_TYPE_DMA_MASK (1 << ION_HEAP_TYPE_DMA) +#define ION_NUM_HEAP_IDS sizeof(unsigned int) * 8 /** - * Flag to use when allocating to indicate that a heap is secure. + * allocation flags - the lower 16 bits are used by core ion, the upper 16 + * bits are reserved for use by the heaps themselves. */ -#define ION_FLAG_SECURE (1 << ION_HEAP_ID_RESERVED) +#define ION_FLAG_CACHED 1 /* mappings of this buffer should be + cached, ion will do cache + maintenance when the buffer is + mapped for dma */ +#define ION_FLAG_CACHED_NEEDS_SYNC 2 /* mappings of this buffer will created + at mmap time, if this is set + caches must be managed manually */ +#define ION_FLAG_FREED_FROM_SHRINKER 4 /* Skip any possible + heap-specific caching + mechanism (e.g. page + pools). Guarantees that any + buffer storage that came + from the system allocator + will be returned to the + system allocator. */ /** - * Flag for clients to force contiguous memort allocation + * DOC: Ion Userspace API + * + * create a client by opening /dev/ion + * most operations handled via following ioctls * - * Use of this flag is carefully monitored! - */ -#define ION_FLAG_FORCE_CONTIGUOUS (1 << 30) - -/* - * Used in conjunction with heap which pool memory to force an allocation - * to come from the page allocator directly instead of from the pool allocation */ -#define ION_FLAG_POOL_FORCE_ALLOC (1 << 16) /** -* Deprecated! Please use the corresponding ION_FLAG_* -*/ -#define ION_SECURE ION_FLAG_SECURE -#define ION_FORCE_CONTIGUOUS ION_FLAG_FORCE_CONTIGUOUS + * struct ion_allocation_data - metadata passed from userspace for allocations + * @len: size of the allocation + * @align: required alignment of the allocation + * @heap_id_mask: mask of heap ids to allocate from + * @flags: flags passed to heap + * @handle: pointer that will be populated with a cookie to use to + * refer to this allocation + * + * Provided by userspace as an argument to the ioctl + */ +struct ion_allocation_data { + size_t len; + size_t align; + unsigned int heap_mask; + unsigned int flags; + ion_user_handle_t handle; +}; /** - * Macro should be used with ion_heap_ids defined above. - */ -#define ION_HEAP(bit) (1 << (bit)) - -#define ION_ADSP_HEAP_NAME "adsp" -#define ION_SYSTEM_HEAP_NAME "system" -#define ION_VMALLOC_HEAP_NAME ION_SYSTEM_HEAP_NAME -#define ION_KMALLOC_HEAP_NAME "kmalloc" -#define ION_AUDIO_HEAP_NAME "audio" -#define ION_SF_HEAP_NAME "sf" -#define ION_MM_HEAP_NAME "mm" -#define ION_CAMERA_HEAP_NAME "camera_preview" -#define ION_IOMMU_HEAP_NAME "iommu" -#define ION_MFC_HEAP_NAME "mfc" -#define ION_WB_HEAP_NAME "wb" -#define ION_MM_FIRMWARE_HEAP_NAME "mm_fw" -#define ION_PIL1_HEAP_NAME "pil_1" -#define ION_PIL2_HEAP_NAME "pil_2" -#define ION_QSECOM_HEAP_NAME "qsecom" - -#define ION_SET_CACHED(__cache) (__cache | ION_FLAG_CACHED) -#define ION_SET_UNCACHED(__cache) (__cache & ~ION_FLAG_CACHED) - -#define ION_IS_CACHED(__flags) ((__flags) & ION_FLAG_CACHED) - -/* struct ion_flush_data - data passed to ion for flushing caches - * - * @handle: handle with data to flush - * @fd: fd to flush - * @vaddr: userspace virtual address mapped with mmap - * @offset: offset into the handle to flush - * @length: length of handle to flush - * - * Performs cache operations on the handle. If p is the start address - * of the handle, p + offset through p + offset + length will have - * the cache operations performed + * struct ion_fd_data - metadata passed to/from userspace for a handle/fd pair + * @handle: a handle + * @fd: a file descriptor representing that handle + * + * For ION_IOC_SHARE or ION_IOC_MAP userspace populates the handle field with + * the handle returned from ion alloc, and the kernel returns the file + * descriptor to share or map in the fd field. For ION_IOC_IMPORT, userspace + * provides the file descriptor and the kernel returns the handle. */ -struct ion_flush_data { - struct ion_handle *handle; +struct ion_fd_data { + ion_user_handle_t handle; int fd; - void *vaddr; - unsigned int offset; - unsigned int length; }; +/** + * struct ion_handle_data - a handle passed to/from the kernel + * @handle: a handle + */ +struct ion_handle_data { + ion_user_handle_t handle; +}; -struct ion_prefetch_data { - int heap_id; - unsigned long len; +/** + * struct ion_custom_data - metadata passed to/from userspace for a custom ioctl + * @cmd: the custom ioctl function to call + * @arg: additional data to pass to the custom ioctl, typically a user + * pointer to a predefined structure + * + * This works just like the regular cmd and arg fields of an ioctl. + */ +struct ion_custom_data { + unsigned int cmd; + unsigned long arg; }; +#define ION_IOC_MAGIC 'I' -#define ION_IOC_MSM_MAGIC 'M' +/** + * DOC: ION_IOC_ALLOC - allocate memory + * + * Takes an ion_allocation_data struct and returns it with the handle field + * populated with the opaque handle for the allocation. + */ +#define ION_IOC_ALLOC _IOWR(ION_IOC_MAGIC, 0, \ + struct ion_allocation_data) + +/** + * DOC: ION_IOC_FREE - free memory + * + * Takes an ion_handle_data struct and frees the handle. + */ +#define ION_IOC_FREE _IOWR(ION_IOC_MAGIC, 1, struct ion_handle_data) /** - * DOC: ION_IOC_CLEAN_CACHES - clean the caches + * DOC: ION_IOC_MAP - get a file descriptor to mmap * - * Clean the caches of the handle specified. + * Takes an ion_fd_data struct with the handle field populated with a valid + * opaque handle. Returns the struct with the fd field set to a file + * descriptor open in the current address space. This file descriptor + * can then be used as an argument to mmap. */ -#define ION_IOC_CLEAN_CACHES _IOWR(ION_IOC_MSM_MAGIC, 0, \ - struct ion_flush_data) +#define ION_IOC_MAP _IOWR(ION_IOC_MAGIC, 2, struct ion_fd_data) + /** - * DOC: ION_IOC_INV_CACHES - invalidate the caches + * DOC: ION_IOC_SHARE - creates a file descriptor to use to share an allocation * - * Invalidate the caches of the handle specified. + * Takes an ion_fd_data struct with the handle field populated with a valid + * opaque handle. Returns the struct with the fd field set to a file + * descriptor open in the current address space. This file descriptor + * can then be passed to another process. The corresponding opaque handle can + * be retrieved via ION_IOC_IMPORT. */ -#define ION_IOC_INV_CACHES _IOWR(ION_IOC_MSM_MAGIC, 1, \ - struct ion_flush_data) +#define ION_IOC_SHARE _IOWR(ION_IOC_MAGIC, 4, struct ion_fd_data) + /** - * DOC: ION_IOC_CLEAN_INV_CACHES - clean and invalidate the caches + * DOC: ION_IOC_IMPORT - imports a shared file descriptor * - * Clean and invalidate the caches of the handle specified. + * Takes an ion_fd_data struct with the fd field populated with a valid file + * descriptor obtained from ION_IOC_SHARE and returns the struct with the handle + * filed set to the corresponding opaque handle. */ -#define ION_IOC_CLEAN_INV_CACHES _IOWR(ION_IOC_MSM_MAGIC, 2, \ - struct ion_flush_data) +#define ION_IOC_IMPORT _IOWR(ION_IOC_MAGIC, 5, struct ion_fd_data) -#define ION_IOC_PREFETCH _IOWR(ION_IOC_MSM_MAGIC, 3, \ - struct ion_prefetch_data) +/** + * DOC: ION_IOC_SYNC - syncs a shared file descriptors to memory + * + * Deprecated in favor of using the dma_buf api's correctly (syncing + * will happend automatically when the buffer is mapped to a device). + * If necessary should be used after touching a cached buffer from the cpu, + * this will make the buffer in memory coherent. + */ +#define ION_IOC_SYNC _IOWR(ION_IOC_MAGIC, 7, struct ion_fd_data) -#define ION_IOC_DRAIN _IOWR(ION_IOC_MSM_MAGIC, 4, \ - struct ion_prefetch_data) +/** + * DOC: ION_IOC_CUSTOM - call architecture specific ion ioctl + * + * Takes the argument of the architecture specific ioctl to call and + * passes appropriate userdata for that ioctl + */ +#define ION_IOC_CUSTOM _IOWR(ION_IOC_MAGIC, 6, struct ion_custom_data) -#endif +#endif /* _UAPI_ION_H */ diff --git a/original-kernel-headers/linux/msm_kgsl.h b/original-kernel-headers/linux/msm_kgsl.h index cf6e60b..d731a33 100644 --- a/original-kernel-headers/linux/msm_kgsl.h +++ b/original-kernel-headers/linux/msm_kgsl.h @@ -24,6 +24,7 @@ #define KGSL_CONTEXT_NO_FAULT_TOLERANCE 0x00000200 #define KGSL_CONTEXT_SYNC 0x00000400 +#define KGSL_CONTEXT_PWR_CONSTRAINT 0x00000800 /* bits [12:15] are reserved for future use */ #define KGSL_CONTEXT_PRIORITY_MASK 0x0000F000 #define KGSL_CONTEXT_PRIORITY_SHIFT 12 @@ -90,6 +91,31 @@ #define KGSL_MEMALIGN_MASK 0x00FF0000 #define KGSL_MEMALIGN_SHIFT 16 +enum kgsl_user_mem_type { + KGSL_USER_MEM_TYPE_PMEM = 0x00000000, + KGSL_USER_MEM_TYPE_ASHMEM = 0x00000001, + KGSL_USER_MEM_TYPE_ADDR = 0x00000002, + KGSL_USER_MEM_TYPE_ION = 0x00000003, + KGSL_USER_MEM_TYPE_MAX = 0x00000004, +}; +#define KGSL_MEMFLAGS_USERMEM_MASK 0x000000e0 +#define KGSL_MEMFLAGS_USERMEM_SHIFT 5 + +/* + * Unfortunately, enum kgsl_user_mem_type starts at 0 which does not + * leave a good value for allocated memory. In the flags we use + * 0 to indicate allocated memory and thus need to add 1 to the enum + * values. + */ +#define KGSL_USERMEM_FLAG(x) (((x) + 1) << KGSL_MEMFLAGS_USERMEM_SHIFT) + +#define KGSL_MEMFLAGS_NOT_USERMEM 0 +#define KGSL_MEMFLAGS_USERMEM_PMEM KGSL_USERMEM_FLAG(KGSL_USER_MEM_TYPE_PMEM) +#define KGSL_MEMFLAGS_USERMEM_ASHMEM \ + KGSL_USERMEM_FLAG(KGSL_USER_MEM_TYPE_ASHMEM) +#define KGSL_MEMFLAGS_USERMEM_ADDR KGSL_USERMEM_FLAG(KGSL_USER_MEM_TYPE_ADDR) +#define KGSL_MEMFLAGS_USERMEM_ION KGSL_USERMEM_FLAG(KGSL_USER_MEM_TYPE_ION) + /* --- generic KGSL flag values --- */ #define KGSL_FLAGS_NORMALMODE 0x00000000 @@ -136,14 +162,6 @@ enum kgsl_deviceid { KGSL_DEVICE_MAX = 0x00000003 }; -enum kgsl_user_mem_type { - KGSL_USER_MEM_TYPE_PMEM = 0x00000000, - KGSL_USER_MEM_TYPE_ASHMEM = 0x00000001, - KGSL_USER_MEM_TYPE_ADDR = 0x00000002, - KGSL_USER_MEM_TYPE_ION = 0x00000003, - KGSL_USER_MEM_TYPE_MAX = 0x00000004, -}; - struct kgsl_devinfo { unsigned int device_id; @@ -201,6 +219,7 @@ enum kgsl_property_type { KGSL_PROP_VERSION = 0x00000008, KGSL_PROP_GPU_RESET_STAT = 0x00000009, KGSL_PROP_PWRCTRL = 0x0000000E, + KGSL_PROP_PWR_CONSTRAINT = 0x00000012, }; struct kgsl_shadowprop { @@ -899,4 +918,31 @@ struct kgsl_submit_commands { #define IOCTL_KGSL_SUBMIT_COMMANDS \ _IOWR(KGSL_IOC_TYPE, 0x3D, struct kgsl_submit_commands) +/** + * struct kgsl_device_constraint - device constraint argument + * @context_id: KGSL context ID + * @type: type of constraint i.e pwrlevel/none + * @data: constraint data + * @size: size of the constraint data + */ +struct kgsl_device_constraint { + unsigned int type; + unsigned int context_id; + void __user *data; + size_t size; +}; + +/* Constraint Type*/ +#define KGSL_CONSTRAINT_NONE 0 +#define KGSL_CONSTRAINT_PWRLEVEL 1 + +/* PWRLEVEL constraint level*/ +/* set to min frequency */ +#define KGSL_CONSTRAINT_PWR_MIN 0 +/* set to max frequency */ +#define KGSL_CONSTRAINT_PWR_MAX 1 + +struct kgsl_device_constraint_pwrlevel { + unsigned int level; +}; #endif /* _UAPI_MSM_KGSL_H */ diff --git a/original-kernel-headers/linux/msm_mdp.h b/original-kernel-headers/linux/msm_mdp.h index c1f7ca8..0b817d1 100644 --- a/original-kernel-headers/linux/msm_mdp.h +++ b/original-kernel-headers/linux/msm_mdp.h @@ -65,11 +65,37 @@ #define MSMFB_WRITEBACK_SET_MIRRORING_HINT _IOW(MSMFB_IOCTL_MAGIC, 167, \ unsigned int) #define MSMFB_ASYNC_BLIT _IOW(MSMFB_IOCTL_MAGIC, 168, unsigned int) +#define MSMFB_OVERLAY_PREPARE _IOWR(MSMFB_IOCTL_MAGIC, 169, \ + struct mdp_overlay_list) #define FB_TYPE_3D_PANEL 0x10101010 #define MDP_IMGTYPE2_START 0x10000 #define MSMFB_DRIVER_VERSION 0xF9E8D701 +/* HW Revisions for different MDSS targets */ +#define MDSS_GET_MAJOR(rev) ((rev) >> 28) +#define MDSS_GET_MINOR(rev) (((rev) >> 16) & 0xFFF) +#define MDSS_GET_STEP(rev) ((rev) & 0xFFFF) +#define MDSS_GET_MAJOR_MINOR(rev) ((rev) >> 16) + +#define IS_MDSS_MAJOR_MINOR_SAME(rev1, rev2) \ + (MDSS_GET_MAJOR_MINOR((rev1)) == MDSS_GET_MAJOR_MINOR((rev2))) + +#define MDSS_MDP_REV(major, minor, step) \ + ((((major) & 0x000F) << 28) | \ + (((minor) & 0x0FFF) << 16) | \ + ((step) & 0xFFFF)) + +#define MDSS_MDP_HW_REV_100 MDSS_MDP_REV(1, 0, 0) /* 8974 v1.0 */ +#define MDSS_MDP_HW_REV_101 MDSS_MDP_REV(1, 1, 0) /* 8x26 v1.0 */ +#define MDSS_MDP_HW_REV_101_1 MDSS_MDP_REV(1, 1, 1) /* 8x26 v2.0, 8926 v1.0 */ +#define MDSS_MDP_HW_REV_101_2 MDSS_MDP_REV(1, 1, 2) /* 8926 v2.0 */ +#define MDSS_MDP_HW_REV_102 MDSS_MDP_REV(1, 2, 0) /* 8974 v2.0 */ +#define MDSS_MDP_HW_REV_102_1 MDSS_MDP_REV(1, 2, 1) /* 8974 v3.0 (Pro) */ +#define MDSS_MDP_HW_REV_103 MDSS_MDP_REV(1, 3, 0) /* 8084 v1.0 */ +#define MDSS_MDP_HW_REV_103_1 MDSS_MDP_REV(1, 3, 1) /* 8084 v1.1 */ +#define MDSS_MDP_HW_REV_200 MDSS_MDP_REV(2, 0, 0) /* 8092 v1.0 */ + enum { NOTIFY_UPDATE_START, NOTIFY_UPDATE_STOP, @@ -121,6 +147,8 @@ enum { MDP_XBGR_8888_TILE, /* XBGR 8888 in tile format */ MDP_BGRX_8888_TILE, /* BGRX 8888 in tile format */ MDP_YCBYCR_H2V1, /* YCbYCr interleave */ + MDP_RGB_565_TILE, /* RGB 565 in tile format */ + MDP_BGR_565_TILE, /* BGR 565 in tile format */ MDP_IMGTYPE_LIMIT, MDP_RGB_BORDERFILL, /* border fill pipe */ MDP_FB_FORMAT = MDP_IMGTYPE2_START, /* framebuffer format */ @@ -156,6 +184,7 @@ enum { #define MDP_BLEND_FG_PREMULT 0x20000 #define MDP_IS_FG 0x40000 #define MDP_SOLID_FILL 0x00000020 +#define MDP_VPU_PIPE 0x00000040 #define MDP_DEINTERLACE 0x80000000 #define MDP_SHARPENING 0x40000000 #define MDP_NO_DMA_BARRIER_START 0x20000000 @@ -797,6 +826,7 @@ enum { #define MDSS_MAX_BL_BRIGHTNESS 255 #define AD_BL_LIN_LEN 256 +#define AD_BL_ATT_LUT_LEN 33 #define MDSS_AD_MODE_AUTO_BL 0x0 #define MDSS_AD_MODE_AUTO_STR 0x1 @@ -825,9 +855,13 @@ struct mdss_ad_init { uint16_t frame_h; uint8_t logo_v; uint8_t logo_h; + uint32_t alpha; + uint32_t alpha_base; uint32_t bl_lin_len; + uint32_t bl_att_len; uint32_t *bl_lin; uint32_t *bl_lin_inv; + uint32_t *bl_att_lut; }; #define MDSS_AD_BL_CTRL_MODE_EN 1 @@ -951,6 +985,8 @@ struct mdss_hw_caps { uint8_t rgb_pipes; uint8_t vig_pipes; uint8_t dma_pipes; + uint8_t max_smp_cnt; + uint8_t smp_per_pipe; uint32_t features; }; @@ -996,6 +1032,24 @@ struct mdp_display_commit { struct mdp_rect roi; }; +/** + * struct mdp_overlay_list - argument for ioctl MSMFB_OVERLAY_PREPARE + * @num_overlays: Number of overlay layers as part of the frame. + * @overlay_list: Pointer to a list of overlay structures identifying + * the layers as part of the frame + * @flags: Flags can be used to extend behavior. + * @processed_overlays: Output parameter indicating how many pipes were + * successful. If there are no errors this number should + * match num_overlays. Otherwise it will indicate the last + * successful index for overlay that couldn't be set. + */ +struct mdp_overlay_list { + uint32_t num_overlays; + struct mdp_overlay **overlay_list; + uint32_t flags; + uint32_t processed_overlays; +}; + struct mdp_page_protection { uint32_t page_protection; }; diff --git a/original-kernel-headers/media/msm_media_info.h b/original-kernel-headers/media/msm_media_info.h deleted file mode 100644 index ddf9c8e..0000000 --- a/original-kernel-headers/media/msm_media_info.h +++ /dev/null @@ -1,188 +0,0 @@ -#ifndef __MEDIA_INFO_H__ -#define __MEDIA_INFO_H__ - -#ifndef MSM_MEDIA_ALIGN -#define MSM_MEDIA_ALIGN(__sz, __align) (((__sz) + (__align-1)) & (~(__align-1))) -#endif - -enum color_fmts { - /* Venus NV12: - * YUV 4:2:0 image with a plane of 8 bit Y samples followed - * by an interleaved U/V plane containing 8 bit 2x2 subsampled - * colour difference samples. - * - * <-------- Y/UV_Stride --------> - * <------- Width -------> - * Y Y Y Y Y Y Y Y Y Y Y Y X X X X ^ ^ - * Y Y Y Y Y Y Y Y Y Y Y Y X X X X | | - * Y Y Y Y Y Y Y Y Y Y Y Y X X X X Height | - * Y Y Y Y Y Y Y Y Y Y Y Y X X X X | Y_Scanlines - * Y Y Y Y Y Y Y Y Y Y Y Y X X X X | | - * Y Y Y Y Y Y Y Y Y Y Y Y X X X X | | - * Y Y Y Y Y Y Y Y Y Y Y Y X X X X | | - * Y Y Y Y Y Y Y Y Y Y Y Y X X X X V | - * X X X X X X X X X X X X X X X X | - * X X X X X X X X X X X X X X X X | - * X X X X X X X X X X X X X X X X | - * X X X X X X X X X X X X X X X X V - * U V U V U V U V U V U V X X X X ^ - * U V U V U V U V U V U V X X X X | - * U V U V U V U V U V U V X X X X | - * U V U V U V U V U V U V X X X X UV_Scanlines - * X X X X X X X X X X X X X X X X | - * X X X X X X X X X X X X X X X X V - * X X X X X X X X X X X X X X X X --> Buffer size alignment - * - * Y_Stride : Width aligned to 128 - * UV_Stride : Width aligned to 128 - * Y_Scanlines: Height aligned to 32 - * UV_Scanlines: Height/2 aligned to 16 - * Total size = align((Y_Stride * Y_Scanlines - * + UV_Stride * UV_Scanlines + 4096), 4096) - */ - COLOR_FMT_NV12, - - /* Venus NV21: - * YUV 4:2:0 image with a plane of 8 bit Y samples followed - * by an interleaved V/U plane containing 8 bit 2x2 subsampled - * colour difference samples. - * - * <-------- Y/UV_Stride --------> - * <------- Width -------> - * Y Y Y Y Y Y Y Y Y Y Y Y X X X X ^ ^ - * Y Y Y Y Y Y Y Y Y Y Y Y X X X X | | - * Y Y Y Y Y Y Y Y Y Y Y Y X X X X Height | - * Y Y Y Y Y Y Y Y Y Y Y Y X X X X | Y_Scanlines - * Y Y Y Y Y Y Y Y Y Y Y Y X X X X | | - * Y Y Y Y Y Y Y Y Y Y Y Y X X X X | | - * Y Y Y Y Y Y Y Y Y Y Y Y X X X X | | - * Y Y Y Y Y Y Y Y Y Y Y Y X X X X V | - * X X X X X X X X X X X X X X X X | - * X X X X X X X X X X X X X X X X | - * X X X X X X X X X X X X X X X X | - * X X X X X X X X X X X X X X X X V - * V U V U V U V U V U V U X X X X ^ - * V U V U V U V U V U V U X X X X | - * V U V U V U V U V U V U X X X X | - * V U V U V U V U V U V U X X X X UV_Scanlines - * X X X X X X X X X X X X X X X X | - * X X X X X X X X X X X X X X X X V - * X X X X X X X X X X X X X X X X --> Padding & Buffer size alignment - * - * Y_Stride : Width aligned to 128 - * UV_Stride : Width aligned to 128 - * Y_Scanlines: Height aligned to 32 - * UV_Scanlines: Height/2 aligned to 16 - * Total size = align((Y_Stride * Y_Scanlines - * + UV_Stride * UV_Scanlines + 4096), 4096) - */ - COLOR_FMT_NV21, -}; - -static inline unsigned int VENUS_Y_STRIDE(int color_fmt, int width) -{ - unsigned int alignment, stride = 0; - if (!width) - goto invalid_input; - - switch (color_fmt) { - case COLOR_FMT_NV21: - case COLOR_FMT_NV12: - alignment = 128; - stride = MSM_MEDIA_ALIGN(width, alignment); - break; - default: - break; - } -invalid_input: - return stride; -} - -static inline unsigned int VENUS_UV_STRIDE(int color_fmt, int width) -{ - unsigned int alignment, stride = 0; - if (!width) - goto invalid_input; - - switch (color_fmt) { - case COLOR_FMT_NV21: - case COLOR_FMT_NV12: - alignment = 128; - stride = MSM_MEDIA_ALIGN(width, alignment); - break; - default: - break; - } -invalid_input: - return stride; -} - -static inline unsigned int VENUS_Y_SCANLINES(int color_fmt, int height) -{ - unsigned int alignment, sclines = 0; - if (!height) - goto invalid_input; - - switch (color_fmt) { - case COLOR_FMT_NV21: - case COLOR_FMT_NV12: - alignment = 32; - sclines = MSM_MEDIA_ALIGN(height, alignment); - break; - default: - break; - } -invalid_input: - return sclines; -} - -static inline unsigned int VENUS_UV_SCANLINES(int color_fmt, int height) -{ - unsigned int alignment, sclines = 0; - if (!height) - goto invalid_input; - - switch (color_fmt) { - case COLOR_FMT_NV21: - case COLOR_FMT_NV12: - alignment = 16; - sclines = MSM_MEDIA_ALIGN(((height + 1) >> 1), alignment); - break; - default: - break; - } -invalid_input: - return sclines; -} - -static inline unsigned int VENUS_BUFFER_SIZE( - int color_fmt, int width, int height) -{ - unsigned int uv_alignment; - unsigned int size = 0; - unsigned int y_plane, uv_plane, y_stride, - uv_stride, y_sclines, uv_sclines; - if (!width || !height) - goto invalid_input; - - y_stride = VENUS_Y_STRIDE(color_fmt, width); - uv_stride = VENUS_UV_STRIDE(color_fmt, width); - y_sclines = VENUS_Y_SCANLINES(color_fmt, height); - uv_sclines = VENUS_UV_SCANLINES(color_fmt, height); - switch (color_fmt) { - case COLOR_FMT_NV21: - case COLOR_FMT_NV12: - uv_alignment = 4096; - y_plane = y_stride * y_sclines; - uv_plane = uv_stride * uv_sclines + uv_alignment; - size = y_plane + uv_plane; - size = MSM_MEDIA_ALIGN(size, 4096); - break; - default: - break; - } -invalid_input: - return size; -} - -#endif diff --git a/original-kernel-headers/video/msm_hdmi_modes.h b/original-kernel-headers/video/msm_hdmi_modes.h deleted file mode 100644 index 87da941..0000000 --- a/original-kernel-headers/video/msm_hdmi_modes.h +++ /dev/null @@ -1,360 +0,0 @@ -#ifndef __MSM_HDMI_MODES_H__ -#define __MSM_HDMI_MODES_H__ -#include <linux/types.h> - -struct msm_hdmi_mode_timing_info { - uint32_t video_format; - uint32_t active_h; - uint32_t front_porch_h; - uint32_t pulse_width_h; - uint32_t back_porch_h; - uint32_t active_low_h; - uint32_t active_v; - uint32_t front_porch_v; - uint32_t pulse_width_v; - uint32_t back_porch_v; - uint32_t active_low_v; - /* Must divide by 1000 to get the actual frequency in MHZ */ - uint32_t pixel_freq; - /* Must divide by 1000 to get the actual frequency in HZ */ - uint32_t refresh_rate; - uint32_t interlaced; - uint32_t supported; -}; - -#define MSM_HDMI_MODES_CEA (1 << 0) -#define MSM_HDMI_MODES_XTND (1 << 1) -#define MSM_HDMI_MODES_DVI (1 << 2) -#define MSM_HDMI_MODES_ALL (MSM_HDMI_MODES_CEA |\ - MSM_HDMI_MODES_XTND |\ - MSM_HDMI_MODES_DVI) - -/* all video formats defined by CEA 861D */ -#define HDMI_VFRMT_UNKNOWN 0 -#define HDMI_VFRMT_640x480p60_4_3 1 -#define HDMI_VFRMT_720x480p60_4_3 2 -#define HDMI_VFRMT_720x480p60_16_9 3 -#define HDMI_VFRMT_1280x720p60_16_9 4 -#define HDMI_VFRMT_1920x1080i60_16_9 5 -#define HDMI_VFRMT_720x480i60_4_3 6 -#define HDMI_VFRMT_1440x480i60_4_3 HDMI_VFRMT_720x480i60_4_3 -#define HDMI_VFRMT_720x480i60_16_9 7 -#define HDMI_VFRMT_1440x480i60_16_9 HDMI_VFRMT_720x480i60_16_9 -#define HDMI_VFRMT_720x240p60_4_3 8 -#define HDMI_VFRMT_1440x240p60_4_3 HDMI_VFRMT_720x240p60_4_3 -#define HDMI_VFRMT_720x240p60_16_9 9 -#define HDMI_VFRMT_1440x240p60_16_9 HDMI_VFRMT_720x240p60_16_9 -#define HDMI_VFRMT_2880x480i60_4_3 10 -#define HDMI_VFRMT_2880x480i60_16_9 11 -#define HDMI_VFRMT_2880x240p60_4_3 12 -#define HDMI_VFRMT_2880x240p60_16_9 13 -#define HDMI_VFRMT_1440x480p60_4_3 14 -#define HDMI_VFRMT_1440x480p60_16_9 15 -#define HDMI_VFRMT_1920x1080p60_16_9 16 -#define HDMI_VFRMT_720x576p50_4_3 17 -#define HDMI_VFRMT_720x576p50_16_9 18 -#define HDMI_VFRMT_1280x720p50_16_9 19 -#define HDMI_VFRMT_1920x1080i50_16_9 20 -#define HDMI_VFRMT_720x576i50_4_3 21 -#define HDMI_VFRMT_1440x576i50_4_3 HDMI_VFRMT_720x576i50_4_3 -#define HDMI_VFRMT_720x576i50_16_9 22 -#define HDMI_VFRMT_1440x576i50_16_9 HDMI_VFRMT_720x576i50_16_9 -#define HDMI_VFRMT_720x288p50_4_3 23 -#define HDMI_VFRMT_1440x288p50_4_3 HDMI_VFRMT_720x288p50_4_3 -#define HDMI_VFRMT_720x288p50_16_9 24 -#define HDMI_VFRMT_1440x288p50_16_9 HDMI_VFRMT_720x288p50_16_9 -#define HDMI_VFRMT_2880x576i50_4_3 25 -#define HDMI_VFRMT_2880x576i50_16_9 26 -#define HDMI_VFRMT_2880x288p50_4_3 27 -#define HDMI_VFRMT_2880x288p50_16_9 28 -#define HDMI_VFRMT_1440x576p50_4_3 29 -#define HDMI_VFRMT_1440x576p50_16_9 30 -#define HDMI_VFRMT_1920x1080p50_16_9 31 -#define HDMI_VFRMT_1920x1080p24_16_9 32 -#define HDMI_VFRMT_1920x1080p25_16_9 33 -#define HDMI_VFRMT_1920x1080p30_16_9 34 -#define HDMI_VFRMT_2880x480p60_4_3 35 -#define HDMI_VFRMT_2880x480p60_16_9 36 -#define HDMI_VFRMT_2880x576p50_4_3 37 -#define HDMI_VFRMT_2880x576p50_16_9 38 -#define HDMI_VFRMT_1920x1250i50_16_9 39 -#define HDMI_VFRMT_1920x1080i100_16_9 40 -#define HDMI_VFRMT_1280x720p100_16_9 41 -#define HDMI_VFRMT_720x576p100_4_3 42 -#define HDMI_VFRMT_720x576p100_16_9 43 -#define HDMI_VFRMT_720x576i100_4_3 44 -#define HDMI_VFRMT_1440x576i100_4_3 HDMI_VFRMT_720x576i100_4_3 -#define HDMI_VFRMT_720x576i100_16_9 45 -#define HDMI_VFRMT_1440x576i100_16_9 HDMI_VFRMT_720x576i100_16_9 -#define HDMI_VFRMT_1920x1080i120_16_9 46 -#define HDMI_VFRMT_1280x720p120_16_9 47 -#define HDMI_VFRMT_720x480p120_4_3 48 -#define HDMI_VFRMT_720x480p120_16_9 49 -#define HDMI_VFRMT_720x480i120_4_3 50 -#define HDMI_VFRMT_1440x480i120_4_3 HDMI_VFRMT_720x480i120_4_3 -#define HDMI_VFRMT_720x480i120_16_9 51 -#define HDMI_VFRMT_1440x480i120_16_9 HDMI_VFRMT_720x480i120_16_9 -#define HDMI_VFRMT_720x576p200_4_3 52 -#define HDMI_VFRMT_720x576p200_16_9 53 -#define HDMI_VFRMT_720x576i200_4_3 54 -#define HDMI_VFRMT_1440x576i200_4_3 HDMI_VFRMT_720x576i200_4_3 -#define HDMI_VFRMT_720x576i200_16_9 55 -#define HDMI_VFRMT_1440x576i200_16_9 HDMI_VFRMT_720x576i200_16_9 -#define HDMI_VFRMT_720x480p240_4_3 56 -#define HDMI_VFRMT_720x480p240_16_9 57 -#define HDMI_VFRMT_720x480i240_4_3 58 -#define HDMI_VFRMT_1440x480i240_4_3 HDMI_VFRMT_720x480i240_4_3 -#define HDMI_VFRMT_720x480i240_16_9 59 -#define HDMI_VFRMT_1440x480i240_16_9 HDMI_VFRMT_720x480i240_16_9 -#define HDMI_VFRMT_1280x720p24_16_9 60 -#define HDMI_VFRMT_1280x720p25_16_9 61 -#define HDMI_VFRMT_1280x720p30_16_9 62 -#define HDMI_VFRMT_1920x1080p120_16_9 63 -#define HDMI_VFRMT_1920x1080p100_16_9 64 -/* Video Identification Codes from 65-127 are reserved for the future */ -#define HDMI_VFRMT_END 127 - -/* extended video formats */ -#define HDMI_VFRMT_3840x2160p30_16_9 (HDMI_VFRMT_END + 1) -#define HDMI_VFRMT_3840x2160p25_16_9 (HDMI_VFRMT_END + 2) -#define HDMI_VFRMT_3840x2160p24_16_9 (HDMI_VFRMT_END + 3) -#define HDMI_VFRMT_4096x2160p24_16_9 (HDMI_VFRMT_END + 4) -#define HDMI_EVFRMT_END HDMI_VFRMT_4096x2160p24_16_9 - -/* VESA DMT TIMINGS */ -#define HDMI_VFRMT_1024x768p60_4_3 (HDMI_EVFRMT_END + 1) -#define HDMI_VFRMT_1280x1024p60_5_4 (HDMI_EVFRMT_END + 2) -#define HDMI_VFRMT_2560x1600p60_16_9 (HDMI_EVFRMT_END + 3) -#define VESA_DMT_VFRMT_END HDMI_VFRMT_2560x1600p60_16_9 -#define HDMI_VFRMT_MAX (VESA_DMT_VFRMT_END + 1) -#define HDMI_VFRMT_FORCE_32BIT 0x7FFFFFFF - -/* Timing information for supported modes */ -#define VFRMT_NOT_SUPPORTED(VFRMT) \ - {VFRMT, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, false} - -#define HDMI_VFRMT_640x480p60_4_3_TIMING \ - {HDMI_VFRMT_640x480p60_4_3, 640, 16, 96, 48, true, \ - 480, 10, 2, 33, true, 25200, 60000, false, true} -#define HDMI_VFRMT_720x480p60_4_3_TIMING \ - {HDMI_VFRMT_720x480p60_4_3, 720, 16, 62, 60, true, \ - 480, 9, 6, 30, true, 27030, 60000, false, true} -#define HDMI_VFRMT_720x480p60_16_9_TIMING \ - {HDMI_VFRMT_720x480p60_16_9, 720, 16, 62, 60, true, \ - 480, 9, 6, 30, true, 27030, 60000, false, true} -#define HDMI_VFRMT_1280x720p60_16_9_TIMING \ - {HDMI_VFRMT_1280x720p60_16_9, 1280, 110, 40, 220, false, \ - 720, 5, 5, 20, false, 74250, 60000, false, true} -#define HDMI_VFRMT_1920x1080i60_16_9_TIMING \ - {HDMI_VFRMT_1920x1080i60_16_9, 1920, 88, 44, 148, false, \ - 540, 2, 5, 5, false, 74250, 60000, false, true} -#define HDMI_VFRMT_1440x480i60_4_3_TIMING \ - {HDMI_VFRMT_1440x480i60_4_3, 1440, 38, 124, 114, true, \ - 240, 4, 3, 15, true, 27000, 60000, true, true} -#define HDMI_VFRMT_1440x480i60_16_9_TIMING \ - {HDMI_VFRMT_1440x480i60_16_9, 1440, 38, 124, 114, true, \ - 240, 4, 3, 15, true, 27000, 60000, true, true} -#define HDMI_VFRMT_1920x1080p60_16_9_TIMING \ - {HDMI_VFRMT_1920x1080p60_16_9, 1920, 88, 44, 148, false, \ - 1080, 4, 5, 36, false, 148500, 60000, false, true} -#define HDMI_VFRMT_720x576p50_4_3_TIMING \ - {HDMI_VFRMT_720x576p50_4_3, 720, 12, 64, 68, true, \ - 576, 5, 5, 39, true, 27000, 50000, false, true} -#define HDMI_VFRMT_720x576p50_16_9_TIMING \ - {HDMI_VFRMT_720x576p50_16_9, 720, 12, 64, 68, true, \ - 576, 5, 5, 39, true, 27000, 50000, false, true} -#define HDMI_VFRMT_1280x720p50_16_9_TIMING \ - {HDMI_VFRMT_1280x720p50_16_9, 1280, 440, 40, 220, false, \ - 720, 5, 5, 20, false, 74250, 50000, false, true} -#define HDMI_VFRMT_1440x576i50_4_3_TIMING \ - {HDMI_VFRMT_1440x576i50_4_3, 1440, 24, 126, 138, true, \ - 288, 2, 3, 19, true, 27000, 50000, true, true} -#define HDMI_VFRMT_1440x576i50_16_9_TIMING \ - {HDMI_VFRMT_1440x576i50_16_9, 1440, 24, 126, 138, true, \ - 288, 2, 3, 19, true, 27000, 50000, true, true} -#define HDMI_VFRMT_1920x1080p50_16_9_TIMING \ - {HDMI_VFRMT_1920x1080p50_16_9, 1920, 528, 44, 148, false, \ - 1080, 4, 5, 36, false, 148500, 50000, false, true} -#define HDMI_VFRMT_1920x1080p24_16_9_TIMING \ - {HDMI_VFRMT_1920x1080p24_16_9, 1920, 638, 44, 148, false, \ - 1080, 4, 5, 36, false, 74250, 24000, false, true} -#define HDMI_VFRMT_1920x1080p25_16_9_TIMING \ - {HDMI_VFRMT_1920x1080p25_16_9, 1920, 528, 44, 148, false, \ - 1080, 4, 5, 36, false, 74250, 25000, false, true} -#define HDMI_VFRMT_1920x1080p30_16_9_TIMING \ - {HDMI_VFRMT_1920x1080p30_16_9, 1920, 88, 44, 148, false, \ - 1080, 4, 5, 36, false, 74250, 30000, false, true} -#define HDMI_VFRMT_1024x768p60_4_3_TIMING \ - {HDMI_VFRMT_1024x768p60_4_3, 1024, 24, 136, 160, false, \ - 768, 2, 6, 29, false, 65000, 60000, false, true} -#define HDMI_VFRMT_1280x1024p60_5_4_TIMING \ - {HDMI_VFRMT_1280x1024p60_5_4, 1280, 48, 112, 248, false, \ - 1024, 1, 3, 38, false, 108000, 60000, false, true} -#define HDMI_VFRMT_2560x1600p60_16_9_TIMING \ - {HDMI_VFRMT_2560x1600p60_16_9, 2560, 48, 32, 80, false, \ - 1600, 3, 6, 37, false, 268500, 60000, false, true} -#define HDMI_VFRMT_3840x2160p30_16_9_TIMING \ - {HDMI_VFRMT_3840x2160p30_16_9, 3840, 176, 88, 296, false, \ - 2160, 8, 10, 72, false, 297000, 30000, false, true} -#define HDMI_VFRMT_3840x2160p25_16_9_TIMING \ - {HDMI_VFRMT_3840x2160p25_16_9, 3840, 1056, 88, 296, false, \ - 2160, 8, 10, 72, false, 297000, 25000, false, true} -#define HDMI_VFRMT_3840x2160p24_16_9_TIMING \ - {HDMI_VFRMT_3840x2160p24_16_9, 3840, 1276, 88, 296, false, \ - 2160, 8, 10, 72, false, 297000, 24000, false, true} -#define HDMI_VFRMT_4096x2160p24_16_9_TIMING \ - {HDMI_VFRMT_4096x2160p24_16_9, 4096, 1020, 88, 296, false, \ - 2160, 8, 10, 72, false, 297000, 24000, false, true} - -#define MSM_HDMI_MODES_SET_TIMING(LUT, MODE) do { \ - struct msm_hdmi_mode_timing_info mode = MODE##_TIMING; \ - LUT[MODE] = mode;\ - } while (0) - -#define MSM_HDMI_MODES_INIT_TIMINGS(__lut) \ -do { \ - unsigned int i; \ - for (i = 0; i < HDMI_VFRMT_MAX; i++) { \ - struct msm_hdmi_mode_timing_info mode = \ - VFRMT_NOT_SUPPORTED(i); \ - (__lut)[i] = mode; \ - } \ -} while (0) - -#define MSM_HDMI_MODES_SET_SUPP_TIMINGS(__lut, __type) \ -do { \ - if (__type & MSM_HDMI_MODES_CEA) { \ - MSM_HDMI_MODES_SET_TIMING(__lut, \ - HDMI_VFRMT_640x480p60_4_3); \ - MSM_HDMI_MODES_SET_TIMING(__lut, \ - HDMI_VFRMT_720x480p60_4_3); \ - MSM_HDMI_MODES_SET_TIMING(__lut, \ - HDMI_VFRMT_720x480p60_16_9); \ - MSM_HDMI_MODES_SET_TIMING(__lut, \ - HDMI_VFRMT_1280x720p60_16_9); \ - MSM_HDMI_MODES_SET_TIMING(__lut, \ - HDMI_VFRMT_1920x1080i60_16_9); \ - MSM_HDMI_MODES_SET_TIMING(__lut, \ - HDMI_VFRMT_1440x480i60_4_3); \ - MSM_HDMI_MODES_SET_TIMING(__lut, \ - HDMI_VFRMT_1440x480i60_16_9); \ - MSM_HDMI_MODES_SET_TIMING(__lut, \ - HDMI_VFRMT_1920x1080p60_16_9); \ - MSM_HDMI_MODES_SET_TIMING(__lut, \ - HDMI_VFRMT_720x576p50_4_3); \ - MSM_HDMI_MODES_SET_TIMING(__lut, \ - HDMI_VFRMT_720x576p50_16_9); \ - MSM_HDMI_MODES_SET_TIMING(__lut, \ - HDMI_VFRMT_1280x720p50_16_9); \ - MSM_HDMI_MODES_SET_TIMING(__lut, \ - HDMI_VFRMT_1440x576i50_4_3); \ - MSM_HDMI_MODES_SET_TIMING(__lut, \ - HDMI_VFRMT_1440x576i50_16_9); \ - MSM_HDMI_MODES_SET_TIMING(__lut, \ - HDMI_VFRMT_1920x1080p50_16_9); \ - MSM_HDMI_MODES_SET_TIMING(__lut, \ - HDMI_VFRMT_1920x1080p24_16_9); \ - MSM_HDMI_MODES_SET_TIMING(__lut, \ - HDMI_VFRMT_1920x1080p25_16_9); \ - MSM_HDMI_MODES_SET_TIMING(__lut, \ - HDMI_VFRMT_1920x1080p30_16_9); \ - } \ - if (__type & MSM_HDMI_MODES_XTND) { \ - MSM_HDMI_MODES_SET_TIMING(__lut, \ - HDMI_VFRMT_3840x2160p30_16_9); \ - MSM_HDMI_MODES_SET_TIMING(__lut, \ - HDMI_VFRMT_3840x2160p25_16_9); \ - MSM_HDMI_MODES_SET_TIMING(__lut, \ - HDMI_VFRMT_3840x2160p24_16_9); \ - MSM_HDMI_MODES_SET_TIMING(__lut, \ - HDMI_VFRMT_4096x2160p24_16_9); \ - } \ - if (__type & MSM_HDMI_MODES_DVI) { \ - MSM_HDMI_MODES_SET_TIMING(__lut, \ - HDMI_VFRMT_1024x768p60_4_3); \ - MSM_HDMI_MODES_SET_TIMING(__lut, \ - HDMI_VFRMT_1280x1024p60_5_4); \ - MSM_HDMI_MODES_SET_TIMING(__lut, \ - HDMI_VFRMT_2560x1600p60_16_9); \ - } \ -} while (0) - -static inline const char *msm_hdmi_mode_2string(uint32_t mode) -{ - switch (mode) { - case HDMI_VFRMT_UNKNOWN: return "Unknown"; - case HDMI_VFRMT_640x480p60_4_3: return "640x480 p60 4/3"; - case HDMI_VFRMT_720x480p60_4_3: return "720x480 p60 4/3"; - case HDMI_VFRMT_720x480p60_16_9: return "720x480 p60 16/9"; - case HDMI_VFRMT_1280x720p60_16_9: return "1280x 720 p60 16/9"; - case HDMI_VFRMT_1920x1080i60_16_9: return "1920x1080 i60 16/9"; - case HDMI_VFRMT_1440x480i60_4_3: return "1440x480 i60 4/3"; - case HDMI_VFRMT_1440x480i60_16_9: return "1440x480 i60 16/9"; - case HDMI_VFRMT_1440x240p60_4_3: return "1440x240 p60 4/3"; - case HDMI_VFRMT_1440x240p60_16_9: return "1440x240 p60 16/9"; - case HDMI_VFRMT_2880x480i60_4_3: return "2880x480 i60 4/3"; - case HDMI_VFRMT_2880x480i60_16_9: return "2880x480 i60 16/9"; - case HDMI_VFRMT_2880x240p60_4_3: return "2880x240 p60 4/3"; - case HDMI_VFRMT_2880x240p60_16_9: return "2880x240 p60 16/9"; - case HDMI_VFRMT_1440x480p60_4_3: return "1440x480 p60 4/3"; - case HDMI_VFRMT_1440x480p60_16_9: return "1440x480 p60 16/9"; - case HDMI_VFRMT_1920x1080p60_16_9: return "1920x1080 p60 16/9"; - case HDMI_VFRMT_720x576p50_4_3: return "720x576 p50 4/3"; - case HDMI_VFRMT_720x576p50_16_9: return "720x576 p50 16/9"; - case HDMI_VFRMT_1280x720p50_16_9: return "1280x720 p50 16/9"; - case HDMI_VFRMT_1920x1080i50_16_9: return "1920x1080 i50 16/9"; - case HDMI_VFRMT_1440x576i50_4_3: return "1440x576 i50 4/3"; - case HDMI_VFRMT_1440x576i50_16_9: return "1440x576 i50 16/9"; - case HDMI_VFRMT_1440x288p50_4_3: return "1440x288 p50 4/3"; - case HDMI_VFRMT_1440x288p50_16_9: return "1440x288 p50 16/9"; - case HDMI_VFRMT_2880x576i50_4_3: return "2880x576 i50 4/3"; - case HDMI_VFRMT_2880x576i50_16_9: return "2880x576 i50 16/9"; - case HDMI_VFRMT_2880x288p50_4_3: return "2880x288 p50 4/3"; - case HDMI_VFRMT_2880x288p50_16_9: return "2880x288 p50 16/9"; - case HDMI_VFRMT_1440x576p50_4_3: return "1440x576 p50 4/3"; - case HDMI_VFRMT_1440x576p50_16_9: return "1440x576 p50 16/9"; - case HDMI_VFRMT_1920x1080p50_16_9: return "1920x1080 p50 16/9"; - case HDMI_VFRMT_1920x1080p24_16_9: return "1920x1080 p24 16/9"; - case HDMI_VFRMT_1920x1080p25_16_9: return "1920x1080 p25 16/9"; - case HDMI_VFRMT_1920x1080p30_16_9: return "1920x1080 p30 16/9"; - case HDMI_VFRMT_2880x480p60_4_3: return "2880x480 p60 4/3"; - case HDMI_VFRMT_2880x480p60_16_9: return "2880x480 p60 16/9"; - case HDMI_VFRMT_2880x576p50_4_3: return "2880x576 p50 4/3"; - case HDMI_VFRMT_2880x576p50_16_9: return "2880x576 p50 16/9"; - case HDMI_VFRMT_1920x1250i50_16_9: return "1920x1250 i50 16/9"; - case HDMI_VFRMT_1920x1080i100_16_9: return "1920x1080 i100 16/9"; - case HDMI_VFRMT_1280x720p100_16_9: return "1280x720 p100 16/9"; - case HDMI_VFRMT_720x576p100_4_3: return "720x576 p100 4/3"; - case HDMI_VFRMT_720x576p100_16_9: return "720x576 p100 16/9"; - case HDMI_VFRMT_1440x576i100_4_3: return "1440x576 i100 4/3"; - case HDMI_VFRMT_1440x576i100_16_9: return "1440x576 i100 16/9"; - case HDMI_VFRMT_1920x1080i120_16_9: return "1920x1080 i120 16/9"; - case HDMI_VFRMT_1280x720p120_16_9: return "1280x720 p120 16/9"; - case HDMI_VFRMT_720x480p120_4_3: return "720x480 p120 4/3"; - case HDMI_VFRMT_720x480p120_16_9: return "720x480 p120 16/9"; - case HDMI_VFRMT_1440x480i120_4_3: return "1440x480 i120 4/3"; - case HDMI_VFRMT_1440x480i120_16_9: return "1440x480 i120 16/9"; - case HDMI_VFRMT_720x576p200_4_3: return "720x576 p200 4/3"; - case HDMI_VFRMT_720x576p200_16_9: return "720x576 p200 16/9"; - case HDMI_VFRMT_1440x576i200_4_3: return "1440x576 i200 4/3"; - case HDMI_VFRMT_1440x576i200_16_9: return "1440x576 i200 16/9"; - case HDMI_VFRMT_720x480p240_4_3: return "720x480 p240 4/3"; - case HDMI_VFRMT_720x480p240_16_9: return "720x480 p240 16/9"; - case HDMI_VFRMT_1440x480i240_4_3: return "1440x480 i240 4/3"; - case HDMI_VFRMT_1440x480i240_16_9: return "1440x480 i240 16/9"; - case HDMI_VFRMT_1280x720p24_16_9: return "1280x720 p24 16/9"; - case HDMI_VFRMT_1280x720p25_16_9: return "1280x720 p25 16/9"; - case HDMI_VFRMT_1280x720p30_16_9: return "1280x720 p30 16/9"; - case HDMI_VFRMT_1920x1080p120_16_9: return "1920x1080 p120 16/9"; - case HDMI_VFRMT_1920x1080p100_16_9: return "1920x1080 p100 16/9"; - case HDMI_VFRMT_3840x2160p30_16_9: return "3840x2160 p30 16/9"; - case HDMI_VFRMT_3840x2160p25_16_9: return "3840x2160 p25 16/9"; - case HDMI_VFRMT_3840x2160p24_16_9: return "3840x2160 p24 16/9"; - case HDMI_VFRMT_4096x2160p24_16_9: return "4096x2160 p24 16/9"; - case HDMI_VFRMT_1024x768p60_4_3: return "1024x768 p60 4/3"; - case HDMI_VFRMT_1280x1024p60_5_4: return "1280x1024 p60 5/4"; - case HDMI_VFRMT_2560x1600p60_16_9: return "2560x1600 p60 16/9"; - default: return "???"; - } -} -#endif /* __MSM_HDMI_MODES_H__ */ |