diff options
Diffstat (limited to 'share/info/as.info')
| -rw-r--r-- | share/info/as.info | 18549 |
1 files changed, 9184 insertions, 9365 deletions
diff --git a/share/info/as.info b/share/info/as.info index 46f8db2..c5c5bf8 100644 --- a/share/info/as.info +++ b/share/info/as.info @@ -1,17 +1,8 @@ -This is as.info, produced by makeinfo version 4.13 from -/mnt/jenkins/workspace/linaro-android_toolchain64-4.9-2014.09/build/objdir/../build/../binutils/binutils-current/gas/doc/as.texinfo. +This is as.info, produced by makeinfo version 5.1 from as.texinfo. -INFO-DIR-SECTION Software development -START-INFO-DIR-ENTRY -* As: (as). The GNU assembler. -* Gas: (as). The GNU assembler. -END-INFO-DIR-ENTRY - - This file documents the GNU Assembler "as". +This file documents the GNU Assembler "as". - Copyright (C) 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, -2000, 2001, 2002, 2006, 2007, 2008, 2009, 2010, 2011 Free Software -Foundation, Inc. + Copyright (C) 1991-2013 Free Software Foundation, Inc. Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.3 or @@ -20,18 +11,24 @@ Invariant Sections, with no Front-Cover Texts, and with no Back-Cover Texts. A copy of the license is included in the section entitled "GNU Free Documentation License". +INFO-DIR-SECTION Software development +START-INFO-DIR-ENTRY +* As: (as). The GNU assembler. +* Gas: (as). The GNU assembler. +END-INFO-DIR-ENTRY + File: as.info, Node: Top, Next: Overview, Up: (dir) Using as ******** -This file is a user guide to the GNU assembler `as' (Linux/GNU Binutils) -version 2.23.52.0.2. +This file is a user guide to the GNU assembler 'as' (GNU Binutils) +version 2.24.0. This document is distributed under the terms of the GNU Free -Documentation License. A copy of the license is included in the -section entitled "GNU Free Documentation License". +Documentation License. A copy of the license is included in the section +entitled "GNU Free Documentation License". * Menu: @@ -42,7 +39,6 @@ section entitled "GNU Free Documentation License". * Symbols:: Symbols * Expressions:: Expressions * Pseudo Ops:: Assembler Directives - * Object Attributes:: Object Attributes * Machine Dependencies:: Machine Dependent Features * Reporting Bugs:: Reporting Bugs @@ -56,14 +52,15 @@ File: as.info, Node: Overview, Next: Invoking, Prev: Top, Up: Top 1 Overview ********** -Here is a brief summary of how to invoke `as'. For details, see *note +Here is a brief summary of how to invoke 'as'. For details, see *note Command-Line Options: Invoking. as [-a[cdghlns][=FILE]] [-alternate] [-D] [-compress-debug-sections] [-nocompress-debug-sections] [-debug-prefix-map OLD=NEW] [-defsym SYM=VAL] [-f] [-g] [-gstabs] - [-gstabs+] [-gdwarf-2] [-help] [-I DIR] [-J] + [-gstabs+] [-gdwarf-2] [-gdwarf-sections] + [-help] [-I DIR] [-J] [-K] [-L] [-listing-lhs-width=NUM] [-listing-lhs-width2=NUM] [-listing-rhs-width=NUM] [-listing-cont-lines=NUM] [-keep-locals] [-o @@ -76,6 +73,7 @@ Command-Line Options: Invoking. _Target AArch64 options:_ [-EB|-EL] + [-mabi=ABI] _Target Alpha options:_ [-mCPU] @@ -180,6 +178,7 @@ Command-Line Options: Invoking. [-mips3] [-mips4] [-mips5] [-mips32] [-mips32r2] [-mips64] [-mips64r2] [-construct-floats] [-no-construct-floats] + [-mnan=ENCODING] [-trap] [-no-break] [-break] [-no-trap] [-mips16] [-no-mips16] [-mmicromips] [-mno-micromips] @@ -190,6 +189,7 @@ Command-Line Options: Invoking. [-mdspr2] [-mno-dspr2] [-mmt] [-mno-mt] [-mmcu] [-mno-mcu] + [-minsn32] [-mno-insn32] [-mfix7000] [-mno-fix7000] [-mfix-vr4120] [-mno-fix-vr4120] [-mfix-vr4130] [-mno-fix-vr4130] @@ -285,96 +285,96 @@ Command-Line Options: Invoking. [ -forbid-undocumented-instructions] [-Fud] [ -forbid-unportable-instructions] [-Fup] -`@FILE' - Read command-line options from FILE. The options read are - inserted in place of the original @FILE option. If FILE does not - exist, or cannot be read, then the option will be treated - literally, and not removed. + +'@FILE' + Read command-line options from FILE. The options read are inserted + in place of the original @FILE option. If FILE does not exist, or + cannot be read, then the option will be treated literally, and not + removed. Options in FILE are separated by whitespace. A whitespace character may be included in an option by surrounding the entire - option in either single or double quotes. Any character - (including a backslash) may be included by prefixing the character - to be included with a backslash. The FILE may itself contain - additional @FILE options; any such options will be processed - recursively. + option in either single or double quotes. Any character (including + a backslash) may be included by prefixing the character to be + included with a backslash. The FILE may itself contain additional + @FILE options; any such options will be processed recursively. -`-a[cdghlmns]' +'-a[cdghlmns]' Turn on listings, in any of a variety of ways: - `-ac' + '-ac' omit false conditionals - `-ad' + '-ad' omit debugging directives - `-ag' + '-ag' include general information, like as version and options passed - `-ah' + '-ah' include high-level source - `-al' + '-al' include assembly - `-am' + '-am' include macro expansions - `-an' + '-an' omit forms processing - `-as' + '-as' include symbols - `=file' + '=file' set the name of the listing file - You may combine these options; for example, use `-aln' for assembly - listing without forms processing. The `=file' option, if used, - must be the last one. By itself, `-a' defaults to `-ahls'. + You may combine these options; for example, use '-aln' for assembly + listing without forms processing. The '=file' option, if used, + must be the last one. By itself, '-a' defaults to '-ahls'. -`--alternate' - Begin in alternate macro mode. *Note `.altmacro': Altmacro. +'--alternate' + Begin in alternate macro mode. *Note '.altmacro': Altmacro. -`--compress-debug-sections' +'--compress-debug-sections' Compress DWARF debug sections using zlib. The debug sections are - renamed to begin with `.zdebug', and the resulting object file may + renamed to begin with '.zdebug', and the resulting object file may not be compatible with older linkers and object file utilities. -`--nocompress-debug-sections' +'--nocompress-debug-sections' Do not compress DWARF debug sections. This is the default. -`-D' +'-D' Ignored. This option is accepted for script compatibility with calls to other assemblers. -`--debug-prefix-map OLD=NEW' - When assembling files in directory `OLD', record debugging - information describing them as in `NEW' instead. +'--debug-prefix-map OLD=NEW' + When assembling files in directory 'OLD', record debugging + information describing them as in 'NEW' instead. -`--defsym SYM=VALUE' +'--defsym SYM=VALUE' Define the symbol SYM to be VALUE before assembling the input file. - VALUE must be an integer constant. As in C, a leading `0x' - indicates a hexadecimal value, and a leading `0' indicates an octal + VALUE must be an integer constant. As in C, a leading '0x' + indicates a hexadecimal value, and a leading '0' indicates an octal value. The value of the symbol can be overridden inside a source - file via the use of a `.set' pseudo-op. + file via the use of a '.set' pseudo-op. -`-f' +'-f' "fast"--skip whitespace and comment preprocessing (assume source is compiler output). -`-g' -`--gen-debug' - Generate debugging information for each assembler source line - using whichever debug format is preferred by the target. This - currently means either STABS, ECOFF or DWARF2. +'-g' +'--gen-debug' + Generate debugging information for each assembler source line using + whichever debug format is preferred by the target. This currently + means either STABS, ECOFF or DWARF2. -`--gstabs' +'--gstabs' Generate stabs debugging information for each assembler line. This may help debugging assembler code, if the debugger can handle it. -`--gstabs+' +'--gstabs+' Generate stabs debugging information for each assembler line, with GNU extensions that probably only gdb can handle, and that could make other debuggers crash or refuse to read your program. This @@ -382,111 +382,119 @@ Command-Line Options: Invoking. extension is the location of the current working directory at assembling time. -`--gdwarf-2' +'--gdwarf-2' Generate DWARF2 debugging information for each assembler line. This may help debugging assembler code, if the debugger can handle it. Note--this option is only supported by some targets, not all of them. -`--size-check=error' -`--size-check=warning' +'--gdwarf-sections' + Instead of creating a .debug_line section, create a series of + .debug_line.FOO sections where FOO is the name of the corresponding + code section. For example a code section called .TEXT.FUNC will + have its dwarf line number information placed into a section called + .DEBUG_LINE.TEXT.FUNC. If the code section is just called .TEXT + then debug line section will still be called just .DEBUG_LINE + without any suffix. + +'--size-check=error' +'--size-check=warning' Issue an error or warning for invalid ELF .size directive. -`--help' +'--help' Print a summary of the command line options and exit. -`--target-help' +'--target-help' Print a summary of all target specific options and exit. -`-I DIR' - Add directory DIR to the search list for `.include' directives. +'-I DIR' + Add directory DIR to the search list for '.include' directives. -`-J' +'-J' Don't warn about signed overflow. -`-K' +'-K' Issue warnings when difference tables altered for long displacements. -`-L' -`--keep-locals' +'-L' +'--keep-locals' Keep (in the symbol table) local symbols. These symbols start with - system-specific local label prefixes, typically `.L' for ELF - systems or `L' for traditional a.out systems. *Note Symbol + system-specific local label prefixes, typically '.L' for ELF + systems or 'L' for traditional a.out systems. *Note Symbol Names::. -`--listing-lhs-width=NUMBER' +'--listing-lhs-width=NUMBER' Set the maximum width, in words, of the output data column for an assembler listing to NUMBER. -`--listing-lhs-width2=NUMBER' +'--listing-lhs-width2=NUMBER' Set the maximum width, in words, of the output data column for continuation lines in an assembler listing to NUMBER. -`--listing-rhs-width=NUMBER' +'--listing-rhs-width=NUMBER' Set the maximum width of an input source line, as displayed in a listing, to NUMBER bytes. -`--listing-cont-lines=NUMBER' +'--listing-cont-lines=NUMBER' Set the maximum number of lines printed in a listing for a single line of input to NUMBER + 1. -`-o OBJFILE' - Name the object-file output from `as' OBJFILE. +'-o OBJFILE' + Name the object-file output from 'as' OBJFILE. -`-R' +'-R' Fold the data section into the text section. Set the default size of GAS's hash tables to a prime number close to NUMBER. Increasing this value can reduce the length of time it takes the assembler to perform its tasks, at the expense of - increasing the assembler's memory requirements. Similarly - reducing this value can reduce the memory requirements at the - expense of speed. + increasing the assembler's memory requirements. Similarly reducing + this value can reduce the memory requirements at the expense of + speed. -`--reduce-memory-overheads' +'--reduce-memory-overheads' This option reduces GAS's memory requirements, at the expense of making the assembly processes slower. Currently this switch is a - synonym for `--hash-size=4051', but in the future it may have - other effects as well. + synonym for '--hash-size=4051', but in the future it may have other + effects as well. -`--statistics' - Print the maximum space (in bytes) and total time (in seconds) - used by assembly. +'--statistics' + Print the maximum space (in bytes) and total time (in seconds) used + by assembly. -`--strip-local-absolute' +'--strip-local-absolute' Remove local absolute symbols from the outgoing symbol table. -`-v' -`-version' - Print the `as' version. +'-v' +'-version' + Print the 'as' version. -`--version' - Print the `as' version and exit. +'--version' + Print the 'as' version and exit. -`-W' -`--no-warn' +'-W' +'--no-warn' Suppress warning messages. -`--fatal-warnings' +'--fatal-warnings' Treat warnings as errors. -`--warn' +'--warn' Don't suppress warning messages or treat them as errors. -`-w' +'-w' Ignored. -`-x' +'-x' Ignored. -`-Z' +'-Z' Generate an object file even after errors. -`-- | FILES ...' +'-- | FILES ...' Standard input, or source files to assemble. - *Note AArch64 Options::, for the options available when as is configured for the 64-bit mode of the ARM Architecture (AArch64). @@ -496,41 +504,32 @@ configured for an Alpha processor. The following options are available when as is configured for an ARC processor. -`-marc[5|6|7|8]' +'-marc[5|6|7|8]' This option selects the core processor variant. - -`-EB | -EL' +'-EB | -EL' Select either big-endian (-EB) or little-endian (-EL) output. The following options are available when as is configured for the ARM processor family. -`-mcpu=PROCESSOR[+EXTENSION...]' +'-mcpu=PROCESSOR[+EXTENSION...]' Specify which ARM processor variant is the target. - -`-march=ARCHITECTURE[+EXTENSION...]' +'-march=ARCHITECTURE[+EXTENSION...]' Specify which ARM architecture variant is used by the target. - -`-mfpu=FLOATING-POINT-FORMAT' +'-mfpu=FLOATING-POINT-FORMAT' Select which Floating Point architecture is the target. - -`-mfloat-abi=ABI' +'-mfloat-abi=ABI' Select which floating point ABI is in use. - -`-mthumb' +'-mthumb' Enable Thumb only instruction decoding. - -`-mapcs-32 | -mapcs-26 | -mapcs-float | -mapcs-reentrant' +'-mapcs-32 | -mapcs-26 | -mapcs-float | -mapcs-reentrant' Select which procedure calling convention is in use. - -`-EB | -EL' +'-EB | -EL' Select either big-endian (-EB) or little-endian (-EL) output. - -`-mthumb-interwork' +'-mthumb-interwork' Specify that the code has been generated with interworking between Thumb and ARM code in mind. - -`-k' +'-k' Specify that PIC code has been generated. *Note Blackfin Options::, for the options available when as is @@ -540,18 +539,18 @@ configured for the Blackfin processor family. The following options are available when as is configured for a D10V processor. -`-O' +'-O' Optimize output by parallelizing instructions. The following options are available when as is configured for a D30V processor. -`-O' +'-O' Optimize output by parallelizing instructions. -`-n' +'-n' Warn when nops are generated. -`-N' +'-N' Warn when a nop after a 32-bit multiply instruction is generated. The following options are available when as is configured for the @@ -560,82 +559,78 @@ Adapteva EPIPHANY series. *Note Epiphany Options::, for the options available when as is configured for an Epiphany processor. - *Note i386-Options::, for the options available when as is -configured for an i386 processor. + *Note i386-Options::, for the options available when as is configured +for an i386 processor. The following options are available when as is configured for the Intel 80960 processor. -`-ACA | -ACA_A | -ACB | -ACC | -AKA | -AKB | -AKC | -AMC' +'-ACA | -ACA_A | -ACB | -ACC | -AKA | -AKB | -AKC | -AMC' Specify which variant of the 960 architecture is the target. -`-b' +'-b' Add code to collect statistics about branches taken. -`-no-relax' +'-no-relax' Do not alter compare-and-branch instructions for long displacements; error if necessary. - The following options are available when as is configured for the Ubicom IP2K series. -`-mip2022ext' +'-mip2022ext' Specifies that the extended IP2022 instructions are allowed. -`-mip2022' +'-mip2022' Restores the default behaviour, which restricts the permitted instructions to just the basic IP2022 ones. - The following options are available when as is configured for the Renesas M32C and M16C processors. -`-m32c' +'-m32c' Assemble M32C instructions. -`-m16c' +'-m16c' Assemble M16C instructions (the default). -`-relax' +'-relax' Enable support for link-time relaxations. -`-h-tick-hex' +'-h-tick-hex' Support H'00 style hex constants in addition to 0x00 style. - The following options are available when as is configured for the Renesas M32R (formerly Mitsubishi M32R) series. -`--m32rx' +'--m32rx' Specify which processor in the M32R family is the target. The default is normally the M32R, but this option changes it to the M32RX. -`--warn-explicit-parallel-conflicts or --Wp' +'--warn-explicit-parallel-conflicts or --Wp' Produce warning messages when questionable parallel constructs are encountered. -`--no-warn-explicit-parallel-conflicts or --Wnp' +'--no-warn-explicit-parallel-conflicts or --Wnp' Do not produce warning messages when questionable parallel constructs are encountered. - The following options are available when as is configured for the Motorola 68000 series. -`-l' +'-l' Shorten references to undefined symbols, to one word instead of two. -`-m68000 | -m68008 | -m68010 | -m68020 | -m68030' -`| -m68040 | -m68060 | -m68302 | -m68331 | -m68332' -`| -m68333 | -m68340 | -mcpu32 | -m5200' +'-m68000 | -m68008 | -m68010 | -m68020 | -m68030' +'| -m68040 | -m68060 | -m68302 | -m68331 | -m68332' +'| -m68333 | -m68340 | -mcpu32 | -m5200' Specify what processor in the 68000 family is the target. The default is normally the 68020, but this can be changed at configuration time. -`-m68881 | -m68882 | -mno-68881 | -mno-68882' +'-m68881 | -m68882 | -mno-68881 | -mno-68882' The target machine does (or does not) have a floating-point coprocessor. The default is to assume a coprocessor for 68020, 68030, and cpu32. Although the basic 68000 is not compatible with @@ -643,11 +638,9 @@ Motorola 68000 series. possible to do emulation of the coprocessor instructions with the main processor. -`-m68851 | -mno-68851' - The target machine does (or does not) have a memory-management - unit coprocessor. The default is to assume an MMU for 68020 and - up. - +'-m68851 | -mno-68851' + The target machine does (or does not) have a memory-management unit + coprocessor. The default is to assume an MMU for 68020 and up. *Note Nios II Options::, for the options available when as is configured for an Altera Nios II processor. @@ -655,315 +648,318 @@ configured for an Altera Nios II processor. For details about the PDP-11 machine dependent features options, see *note PDP-11-Options::. -`-mpic | -mno-pic' +'-mpic | -mno-pic' Generate position-independent (or position-dependent) code. The - default is `-mpic'. + default is '-mpic'. -`-mall' -`-mall-extensions' +'-mall' +'-mall-extensions' Enable all instruction set extensions. This is the default. -`-mno-extensions' +'-mno-extensions' Disable all instruction set extensions. -`-mEXTENSION | -mno-EXTENSION' +'-mEXTENSION | -mno-EXTENSION' Enable (or disable) a particular instruction set extension. -`-mCPU' +'-mCPU' Enable the instruction set extensions supported by a particular CPU, and disable all other extensions. -`-mMACHINE' +'-mMACHINE' Enable the instruction set extensions supported by a particular machine model, and disable all other extensions. The following options are available when as is configured for a picoJava processor. -`-mb' +'-mb' Generate "big endian" format output. -`-ml' +'-ml' Generate "little endian" format output. - The following options are available when as is configured for the Motorola 68HC11 or 68HC12 series. -`-m68hc11 | -m68hc12 | -m68hcs12 | -mm9s12x | -mm9s12xg' +'-m68hc11 | -m68hc12 | -m68hcs12 | -mm9s12x | -mm9s12xg' Specify what processor is the target. The default is defined by the configuration option when building the assembler. -`--xgate-ramoffset' - Instruct the linker to offset RAM addresses from S12X address - space into XGATE address space. +'--xgate-ramoffset' + Instruct the linker to offset RAM addresses from S12X address space + into XGATE address space. -`-mshort' +'-mshort' Specify to use the 16-bit integer ABI. -`-mlong' +'-mlong' Specify to use the 32-bit integer ABI. -`-mshort-double' +'-mshort-double' Specify to use the 32-bit double ABI. -`-mlong-double' +'-mlong-double' Specify to use the 64-bit double ABI. -`--force-long-branches' - Relative branches are turned into absolute ones. This concerns +'--force-long-branches' + Relative branches are turned into absolute ones. This concerns conditional branches, unconditional branches and branches to a sub routine. -`-S | --short-branches' - Do not turn relative branches into absolute ones when the offset - is out of range. +'-S | --short-branches' + Do not turn relative branches into absolute ones when the offset is + out of range. -`--strict-direct-mode' +'--strict-direct-mode' Do not turn the direct addressing mode into extended addressing mode when the instruction does not support direct addressing mode. -`--print-insn-syntax' +'--print-insn-syntax' Print the syntax of instruction in case of error. -`--print-opcodes' +'--print-opcodes' Print the list of instructions with syntax and then exit. -`--generate-example' +'--generate-example' Print an example of instruction for each possible instruction and - then exit. This option is only useful for testing `as'. + then exit. This option is only useful for testing 'as'. - - The following options are available when `as' is configured for the + The following options are available when 'as' is configured for the SPARC architecture: -`-Av6 | -Av7 | -Av8 | -Asparclet | -Asparclite' -`-Av8plus | -Av8plusa | -Av9 | -Av9a' +'-Av6 | -Av7 | -Av8 | -Asparclet | -Asparclite' +'-Av8plus | -Av8plusa | -Av9 | -Av9a' Explicitly select a variant of the SPARC architecture. - `-Av8plus' and `-Av8plusa' select a 32 bit environment. `-Av9' - and `-Av9a' select a 64 bit environment. + '-Av8plus' and '-Av8plusa' select a 32 bit environment. '-Av9' and + '-Av9a' select a 64 bit environment. - `-Av8plusa' and `-Av9a' enable the SPARC V9 instruction set with + '-Av8plusa' and '-Av9a' enable the SPARC V9 instruction set with UltraSPARC extensions. -`-xarch=v8plus | -xarch=v8plusa' +'-xarch=v8plus | -xarch=v8plusa' For compatibility with the Solaris v9 assembler. These options are equivalent to -Av8plus and -Av8plusa, respectively. -`-bump' +'-bump' Warn when the assembler switches to another architecture. The following options are available when as is configured for the 'c54x architecture. -`-mfar-mode' +'-mfar-mode' Enable extended addressing mode. All addresses and relocations will assume extended addressing (usually 23 bits). - -`-mcpu=CPU_VERSION' +'-mcpu=CPU_VERSION' Sets the CPU version being compiled for. - -`-merrors-to-file FILENAME' +'-merrors-to-file FILENAME' Redirect error output to a file, for broken systems which don't support such behaviour in the shell. The following options are available when as is configured for a MIPS processor. -`-G NUM' +'-G NUM' This option sets the largest size of an object that can be - referenced implicitly with the `gp' register. It is only accepted + referenced implicitly with the 'gp' register. It is only accepted for targets that use ECOFF format, such as a DECstation running Ultrix. The default value is 8. -`-EB' +'-EB' Generate "big endian" format output. -`-EL' +'-EL' Generate "little endian" format output. -`-mips1' -`-mips2' -`-mips3' -`-mips4' -`-mips5' -`-mips32' -`-mips32r2' -`-mips64' -`-mips64r2' +'-mips1' +'-mips2' +'-mips3' +'-mips4' +'-mips5' +'-mips32' +'-mips32r2' +'-mips64' +'-mips64r2' Generate code for a particular MIPS Instruction Set Architecture - level. `-mips1' is an alias for `-march=r3000', `-mips2' is an - alias for `-march=r6000', `-mips3' is an alias for `-march=r4000' - and `-mips4' is an alias for `-march=r8000'. `-mips5', `-mips32', - `-mips32r2', `-mips64', and `-mips64r2' correspond to generic - `MIPS V', `MIPS32', `MIPS32 Release 2', `MIPS64', and `MIPS64 - Release 2' ISA processors, respectively. + level. '-mips1' is an alias for '-march=r3000', '-mips2' is an + alias for '-march=r6000', '-mips3' is an alias for '-march=r4000' + and '-mips4' is an alias for '-march=r8000'. '-mips5', '-mips32', + '-mips32r2', '-mips64', and '-mips64r2' correspond to generic MIPS + V, MIPS32, MIPS32 Release 2, MIPS64, and MIPS64 Release 2 ISA + processors, respectively. -`-march=CPU' - Generate code for a particular MIPS cpu. +'-march=CPU' + Generate code for a particular MIPS CPU. -`-mtune=CPU' - Schedule and tune for a particular MIPS cpu. +'-mtune=CPU' + Schedule and tune for a particular MIPS CPU. -`-mfix7000' -`-mno-fix7000' +'-mfix7000' +'-mno-fix7000' Cause nops to be inserted if the read of the destination register of an mfhi or mflo instruction occurs in the following two instructions. -`-mdebug' -`-no-mdebug' +'-mdebug' +'-no-mdebug' Cause stabs-style debugging output to go into an ECOFF-style .mdebug section instead of the standard ELF .stabs sections. -`-mpdr' -`-mno-pdr' - Control generation of `.pdr' sections. +'-mpdr' +'-mno-pdr' + Control generation of '.pdr' sections. -`-mgp32' -`-mfp32' +'-mgp32' +'-mfp32' The register sizes are normally inferred from the ISA and ABI, but these flags force a certain group of registers to be treated as 32 - bits wide at all times. `-mgp32' controls the size of - general-purpose registers and `-mfp32' controls the size of + bits wide at all times. '-mgp32' controls the size of + general-purpose registers and '-mfp32' controls the size of floating-point registers. -`-mips16' -`-no-mips16' +'-mips16' +'-no-mips16' Generate code for the MIPS 16 processor. This is equivalent to - putting `.set mips16' at the start of the assembly file. - `-no-mips16' turns off this option. + putting '.set mips16' at the start of the assembly file. + '-no-mips16' turns off this option. -`-mmicromips' -`-mno-micromips' +'-mmicromips' +'-mno-micromips' Generate code for the microMIPS processor. This is equivalent to - putting `.set micromips' at the start of the assembly file. - `-mno-micromips' turns off this option. This is equivalent to - putting `.set nomicromips' at the start of the assembly file. + putting '.set micromips' at the start of the assembly file. + '-mno-micromips' turns off this option. This is equivalent to + putting '.set nomicromips' at the start of the assembly file. -`-msmartmips' -`-mno-smartmips' +'-msmartmips' +'-mno-smartmips' Enables the SmartMIPS extension to the MIPS32 instruction set. - This is equivalent to putting `.set smartmips' at the start of the - assembly file. `-mno-smartmips' turns off this option. + This is equivalent to putting '.set smartmips' at the start of the + assembly file. '-mno-smartmips' turns off this option. -`-mips3d' -`-no-mips3d' - Generate code for the MIPS-3D Application Specific Extension. - This tells the assembler to accept MIPS-3D instructions. - `-no-mips3d' turns off this option. +'-mips3d' +'-no-mips3d' + Generate code for the MIPS-3D Application Specific Extension. This + tells the assembler to accept MIPS-3D instructions. '-no-mips3d' + turns off this option. -`-mdmx' -`-no-mdmx' +'-mdmx' +'-no-mdmx' Generate code for the MDMX Application Specific Extension. This - tells the assembler to accept MDMX instructions. `-no-mdmx' turns + tells the assembler to accept MDMX instructions. '-no-mdmx' turns off this option. -`-mdsp' -`-mno-dsp' +'-mdsp' +'-mno-dsp' Generate code for the DSP Release 1 Application Specific Extension. This tells the assembler to accept DSP Release 1 instructions. - `-mno-dsp' turns off this option. + '-mno-dsp' turns off this option. -`-mdspr2' -`-mno-dspr2' +'-mdspr2' +'-mno-dspr2' Generate code for the DSP Release 2 Application Specific Extension. This option implies -mdsp. This tells the assembler to accept DSP - Release 2 instructions. `-mno-dspr2' turns off this option. + Release 2 instructions. '-mno-dspr2' turns off this option. -`-mmt' -`-mno-mt' +'-mmt' +'-mno-mt' Generate code for the MT Application Specific Extension. This - tells the assembler to accept MT instructions. `-mno-mt' turns - off this option. + tells the assembler to accept MT instructions. '-mno-mt' turns off + this option. -`-mmcu' -`-mno-mcu' +'-mmcu' +'-mno-mcu' Generate code for the MCU Application Specific Extension. This - tells the assembler to accept MCU instructions. `-mno-mcu' turns + tells the assembler to accept MCU instructions. '-mno-mcu' turns off this option. -`--construct-floats' -`--no-construct-floats' - The `--no-construct-floats' option disables the construction of +'-minsn32' +'-mno-insn32' + Only use 32-bit instruction encodings when generating code for the + microMIPS processor. This option inhibits the use of any 16-bit + instructions. This is equivalent to putting '.set insn32' at the + start of the assembly file. '-mno-insn32' turns off this option. + This is equivalent to putting '.set noinsn32' at the start of the + assembly file. By default '-mno-insn32' is selected, allowing all + instructions to be used. + +'--construct-floats' +'--no-construct-floats' + The '--no-construct-floats' option disables the construction of double width floating point constants by loading the two halves of the value into the two single width floating point registers that - make up the double width register. By default - `--construct-floats' is selected, allowing construction of these - floating point constants. - -`--emulation=NAME' - This option causes `as' to emulate `as' configured for some other - target, in all respects, including output format (choosing between - ELF and ECOFF only), handling of pseudo-opcodes which may generate - debugging information or store symbol table information, and - default endianness. The available configuration names are: - `mipsecoff', `mipself', `mipslecoff', `mipsbecoff', `mipslelf', - `mipsbelf'. The first two do not alter the default endianness - from that of the primary target for which the assembler was - configured; the others change the default to little- or big-endian - as indicated by the `b' or `l' in the name. Using `-EB' or `-EL' - will override the endianness selection in any case. - - This option is currently supported only when the primary target - `as' is configured for is a MIPS ELF or ECOFF target. - Furthermore, the primary target or others specified with - `--enable-targets=...' at configuration time must include support - for the other format, if both are to be available. For example, - the Irix 5 configuration includes support for both. - - Eventually, this option will support more configurations, with more - fine-grained control over the assembler's behavior, and will be - supported for more processors. - -`-nocpp' - `as' ignores this option. It is accepted for compatibility with + make up the double width register. By default '--construct-floats' + is selected, allowing construction of these floating point + constants. + +'--relax-branch' +'--no-relax-branch' + The '--relax-branch' option enables the relaxation of out-of-range + branches. By default '--no-relax-branch' is selected, causing any + out-of-range branches to produce an error. + +'-mnan=ENCODING' + Select between the IEEE 754-2008 ('-mnan=2008') or the legacy + ('-mnan=legacy') NaN encoding format. The latter is the default. + +'--emulation=NAME' + This option was formerly used to switch between ELF and ECOFF + output on targets like IRIX 5 that supported both. MIPS ECOFF + support was removed in GAS 2.24, so the option now serves little + purpose. It is retained for backwards compatibility. + + The available configuration names are: 'mipself', 'mipslelf' and + 'mipsbelf'. Choosing 'mipself' now has no effect, since the output + is always ELF. 'mipslelf' and 'mipsbelf' select little- and + big-endian output respectively, but '-EL' and '-EB' are now the + preferred options instead. + +'-nocpp' + 'as' ignores this option. It is accepted for compatibility with the native tools. -`--trap' -`--no-trap' -`--break' -`--no-break' +'--trap' +'--no-trap' +'--break' +'--no-break' Control how to deal with multiplication overflow and division by - zero. `--trap' or `--no-break' (which are synonyms) take a trap + zero. '--trap' or '--no-break' (which are synonyms) take a trap exception (and only work for Instruction Set Architecture level 2 - and higher); `--break' or `--no-trap' (also synonyms, and the + and higher); '--break' or '--no-trap' (also synonyms, and the default) take a break exception. -`-n' - When this option is used, `as' will issue a warning every time it +'-n' + When this option is used, 'as' will issue a warning every time it generates a nop instruction from a macro. The following options are available when as is configured for an MCore processor. -`-jsri2bsr' -`-nojsri2bsr' +'-jsri2bsr' +'-nojsri2bsr' Enable or disable the JSRI to BSR transformation. By default this - is enabled. The command line option `-nojsri2bsr' can be used to + is enabled. The command line option '-nojsri2bsr' can be used to disable it. -`-sifilter' -`-nosifilter' - Enable or disable the silicon filter behaviour. By default this - is disabled. The default can be overridden by the `-sifilter' - command line option. +'-sifilter' +'-nosifilter' + Enable or disable the silicon filter behaviour. By default this is + disabled. The default can be overridden by the '-sifilter' command + line option. -`-relax' +'-relax' Alter jump instructions for long displacements. -`-mcpu=[210|340]' +'-mcpu=[210|340]' Select the cpu type on the target hardware. This controls which instructions can be assembled. -`-EB' +'-EB' Assemble for a big endian target. -`-EL' +'-EL' Assemble for a little endian target. - *Note Meta Options::, for the options available when as is configured for a Meta processor. @@ -977,25 +973,20 @@ for a PowerPC processor. The following options are available when as is configured for the s390 processor family. -`-m31' -`-m64' +'-m31' +'-m64' Select the word size, either 31/32 bits or 64 bits. - -`-mesa' - -`-mzarch' +'-mesa' +'-mzarch' Select the architecture mode, either the Enterprise System Architecture (esa) or the z/Architecture mode (zarch). - -`-march=PROCESSOR' - Specify which s390 processor variant is the target, `g6', `g6', - `z900', `z990', `z9-109', `z9-ec', `z10', `z196', or `zEC12'. - -`-mregnames' -`-mno-regnames' +'-march=PROCESSOR' + Specify which s390 processor variant is the target, 'g6', 'g6', + 'z900', 'z990', 'z9-109', 'z9-ec', 'z10', 'z196', or 'zEC12'. +'-mregnames' +'-mno-regnames' Allow or disallow symbolic names for registers. - -`-mwarn-areg-zero' +'-mwarn-areg-zero' Warn whenever the operand for a base or index register has been specified but evaluates to zero. @@ -1010,37 +1001,30 @@ configured for an Xtensa processor. The following options are available when as is configured for a Z80 family processor. -`-z80' +'-z80' Assemble for Z80 processor. - -`-r800' +'-r800' Assemble for R800 processor. - -`-ignore-undocumented-instructions' -`-Wnud' +'-ignore-undocumented-instructions' +'-Wnud' Assemble undocumented Z80 instructions that also work on R800 without warning. - -`-ignore-unportable-instructions' -`-Wnup' +'-ignore-unportable-instructions' +'-Wnup' Assemble all undocumented Z80 instructions without warning. - -`-warn-undocumented-instructions' -`-Wud' - Issue a warning for undocumented Z80 instructions that also work - on R800. - -`-warn-unportable-instructions' -`-Wup' +'-warn-undocumented-instructions' +'-Wud' + Issue a warning for undocumented Z80 instructions that also work on + R800. +'-warn-unportable-instructions' +'-Wup' Issue a warning for undocumented Z80 instructions that do not work on R800. - -`-forbid-undocumented-instructions' -`-Fud' +'-forbid-undocumented-instructions' +'-Fud' Treat all undocumented instructions as errors. - -`-forbid-unportable-instructions' -`-Fup' +'-forbid-unportable-instructions' +'-Fup' Treat undocumented Z80 instructions that do not work on R800 as errors. @@ -1061,9 +1045,9 @@ File: as.info, Node: Manual, Next: GNU Assembler, Up: Overview ============================ This manual is intended to describe what you need to know to use GNU -`as'. We cover the syntax expected in source files, including notation -for symbols, constants, and expressions; the directives that `as' -understands; and of course how to invoke `as'. +'as'. We cover the syntax expected in source files, including notation +for symbols, constants, and expressions; the directives that 'as' +understands; and of course how to invoke 'as'. This manual also describes some of the machine-dependent features of various flavors of the assembler. @@ -1082,24 +1066,24 @@ File: as.info, Node: GNU Assembler, Next: Object Formats, Prev: Manual, Up: 1.2 The GNU Assembler ===================== -GNU `as' is really a family of assemblers. If you use (or have used) +GNU 'as' is really a family of assemblers. If you use (or have used) the GNU assembler on one architecture, you should find a fairly similar environment when you use it on another architecture. Each version has much in common with the others, including object file formats, most assembler directives (often called "pseudo-ops") and assembler syntax. - `as' is primarily intended to assemble the output of the GNU C -compiler `gcc' for use by the linker `ld'. Nevertheless, we've tried -to make `as' assemble correctly everything that other assemblers for -the same machine would assemble. Any exceptions are documented -explicitly (*note Machine Dependencies::). This doesn't mean `as' -always uses the same syntax as another assembler for the same -architecture; for example, we know of several incompatible versions of -680x0 assembly language syntax. + 'as' is primarily intended to assemble the output of the GNU C +compiler 'gcc' for use by the linker 'ld'. Nevertheless, we've tried to +make 'as' assemble correctly everything that other assemblers for the +same machine would assemble. Any exceptions are documented explicitly +(*note Machine Dependencies::). This doesn't mean 'as' always uses the +same syntax as another assembler for the same architecture; for example, +we know of several incompatible versions of 680x0 assembly language +syntax. - Unlike older assemblers, `as' is designed to assemble a source + Unlike older assemblers, 'as' is designed to assemble a source program in one pass of the source file. This has a subtle impact on the -`.org' directive (*note `.org': Org.). +'.org' directive (*note '.org': Org.). File: as.info, Node: Object Formats, Next: Command Line, Prev: GNU Assembler, Up: Overview @@ -1119,23 +1103,23 @@ File: as.info, Node: Command Line, Next: Input Files, Prev: Object Formats, 1.4 Command Line ================ -After the program name `as', the command line may contain options and +After the program name 'as', the command line may contain options and file names. Options may appear in any order, and may be before, after, or between file names. The order of file names is significant. - `--' (two hyphens) by itself names the standard input file -explicitly, as one of the files for `as' to assemble. + '--' (two hyphens) by itself names the standard input file +explicitly, as one of the files for 'as' to assemble. - Except for `--' any command line argument that begins with a hyphen -(`-') is an option. Each option changes the behavior of `as'. No -option changes the way another option works. An option is a `-' + Except for '--' any command line argument that begins with a hyphen +('-') is an option. Each option changes the behavior of 'as'. No +option changes the way another option works. An option is a '-' followed by one or more letters; the case of the letter is important. All options are optional. Some options expect exactly one file name to follow them. The file name may either immediately follow the option's letter (compatible with -older assemblers) or it may be the next command argument (GNU -standard). These two command lines are equivalent: +older assemblers) or it may be the next command argument (GNU standard). +These two command lines are equivalent: as -o my-object-file.o mumble.s as -omy-object-file.o mumble.s @@ -1147,30 +1131,30 @@ File: as.info, Node: Input Files, Next: Object, Prev: Command Line, Up: Over =============== We use the phrase "source program", abbreviated "source", to describe -the program input to one run of `as'. The program may be in one or -more files; how the source is partitioned into files doesn't change the +the program input to one run of 'as'. The program may be in one or more +files; how the source is partitioned into files doesn't change the meaning of the source. The source program is a concatenation of the text in all the files, in the order specified. - Each time you run `as' it assembles exactly one source program. The + Each time you run 'as' it assembles exactly one source program. The source program is made up of one or more files. (The standard input is also a file.) - You give `as' a command line that has zero or more input file names. -The input files are read (from left file name to right). A command -line argument (in any position) that has no special meaning is taken to -be an input file name. + You give 'as' a command line that has zero or more input file names. +The input files are read (from left file name to right). A command line +argument (in any position) that has no special meaning is taken to be an +input file name. - If you give `as' no file names it attempts to read one input file -from the `as' standard input, which is normally your terminal. You may -have to type <ctl-D> to tell `as' there is no more program to assemble. + If you give 'as' no file names it attempts to read one input file +from the 'as' standard input, which is normally your terminal. You may +have to type <ctl-D> to tell 'as' there is no more program to assemble. - Use `--' if you need to explicitly name the standard input file in + Use '--' if you need to explicitly name the standard input file in your command line. - If the source is empty, `as' produces a small, empty object file. + If the source is empty, 'as' produces a small, empty object file. Filenames and Line-numbers -------------------------- @@ -1181,14 +1165,14 @@ line number in a physical file; the other refers to a line number in a "logical" file. *Note Error and Warning Messages: Errors. "Physical files" are those files named in the command line given to -`as'. +'as'. "Logical files" are simply names declared explicitly by assembler -directives; they bear no relation to physical files. Logical file -names help error messages reflect the original source file, when `as' -source is itself synthesized from other files. `as' understands the -`#' directives emitted by the `gcc' preprocessor. See also *note -`.file': File. +directives; they bear no relation to physical files. Logical file names +help error messages reflect the original source file, when 'as' source +is itself synthesized from other files. 'as' understands the '#' +directives emitted by the 'gcc' preprocessor. See also *note '.file': +File. File: as.info, Node: Object, Next: Errors, Prev: Input Files, Up: Overview @@ -1196,19 +1180,19 @@ File: as.info, Node: Object, Next: Errors, Prev: Input Files, Up: Overview 1.6 Output (Object) File ======================== -Every time you run `as' it produces an output file, which is your +Every time you run 'as' it produces an output file, which is your assembly language program translated into numbers. This file is the -object file. Its default name is `a.out'. You can give it another -name by using the `-o' option. Conventionally, object file names end -with `.o'. The default name is used for historical reasons: older -assemblers were capable of assembling self-contained programs directly -into a runnable program. (For some formats, this isn't currently -possible, but it can be done for the `a.out' format.) +object file. Its default name is 'a.out'. You can give it another name +by using the '-o' option. Conventionally, object file names end with +'.o'. The default name is used for historical reasons: older assemblers +were capable of assembling self-contained programs directly into a +runnable program. (For some formats, this isn't currently possible, but +it can be done for the 'a.out' format.) - The object file is meant for input to the linker `ld'. It contains -assembled program code, information to help `ld' integrate the -assembled program into a runnable file, and (optionally) symbolic -information for the debugger. + The object file is meant for input to the linker 'ld'. It contains +assembled program code, information to help 'ld' integrate the assembled +program into a runnable file, and (optionally) symbolic information for +the debugger. File: as.info, Node: Errors, Prev: Object, Up: Overview @@ -1216,9 +1200,9 @@ File: as.info, Node: Errors, Prev: Object, Up: Overview 1.7 Error and Warning Messages ============================== -`as' may write warnings and error messages to the standard error file -(usually your terminal). This should not happen when a compiler runs -`as' automatically. Warnings report an assumption made so that `as' +'as' may write warnings and error messages to the standard error file +(usually your terminal). This should not happen when a compiler runs +'as' automatically. Warnings report an assumption made so that 'as' could keep assembling a flawed program; errors report a grave problem that stops the assembly. @@ -1227,9 +1211,9 @@ that stops the assembly. file_name:NNN:Warning Message Text (where NNN is a line number). If a logical file name has been given -(*note `.file': File.) it is used for the filename, otherwise the name +(*note '.file': File.) it is used for the filename, otherwise the name of the current input file is used. If a logical line number was given -(*note `.line': Line.) then it is used to calculate the number printed, +(*note '.line': Line.) then it is used to calculate the number printed, otherwise the actual line in the current source file is printed. The message text is intended to be self explanatory (in the grand Unix tradition). @@ -1250,226 +1234,224 @@ This chapter describes command-line options available in _all_ versions of the GNU assembler; see *note Machine Dependencies::, for options specific to particular machine architectures. - If you are invoking `as' via the GNU C compiler, you can use the -`-Wa' option to pass arguments through to the assembler. The assembler -arguments must be separated from each other (and the `-Wa') by commas. + If you are invoking 'as' via the GNU C compiler, you can use the +'-Wa' option to pass arguments through to the assembler. The assembler +arguments must be separated from each other (and the '-Wa') by commas. For example: gcc -c -g -O -Wa,-alh,-L file.c -This passes two options to the assembler: `-alh' (emit a listing to -standard output with high-level and assembly source) and `-L' (retain +This passes two options to the assembler: '-alh' (emit a listing to +standard output with high-level and assembly source) and '-L' (retain local symbols in the symbol table). - Usually you do not need to use this `-Wa' mechanism, since many + Usually you do not need to use this '-Wa' mechanism, since many compiler command-line options are automatically passed to the assembler -by the compiler. (You can call the GNU compiler driver with the `-v' -option to see precisely what options it passes to each compilation -pass, including the assembler.) +by the compiler. (You can call the GNU compiler driver with the '-v' +option to see precisely what options it passes to each compilation pass, +including the assembler.) * Menu: * a:: -a[cdghlns] enable listings -* alternate:: --alternate enable alternate macro syntax +* alternate:: -alternate enable alternate macro syntax * D:: -D for compatibility * f:: -f to work faster * I:: -I for .include search path - * K:: -K for difference tables * L:: -L to retain local symbols -* listing:: --listing-XXX to configure listing output -* M:: -M or --mri to assemble in MRI compatibility mode -* MD:: --MD for dependency tracking +* listing:: -listing-XXX to configure listing output +* M:: -M or -mri to assemble in MRI compatibility mode +* MD:: -MD for dependency tracking * o:: -o to name the object file * R:: -R to join data and text sections -* statistics:: --statistics to see statistics about assembly -* traditional-format:: --traditional-format for compatible output +* statistics:: -statistics to see statistics about assembly +* traditional-format:: -traditional-format for compatible output * v:: -v to announce version -* W:: -W, --no-warn, --warn, --fatal-warnings to control warnings +* W:: -W, -no-warn, -warn, -fatal-warnings to control warnings * Z:: -Z to make object file even after errors File: as.info, Node: a, Next: alternate, Up: Invoking -2.1 Enable Listings: `-a[cdghlns]' +2.1 Enable Listings: '-a[cdghlns]' ================================== -These options enable listing output from the assembler. By itself, -`-a' requests high-level, assembly, and symbols listing. You can use -other letters to select specific options for the list: `-ah' requests a -high-level language listing, `-al' requests an output-program assembly -listing, and `-as' requests a symbol table listing. High-level -listings require that a compiler debugging option like `-g' be used, -and that assembly listings (`-al') be requested also. +These options enable listing output from the assembler. By itself, '-a' +requests high-level, assembly, and symbols listing. You can use other +letters to select specific options for the list: '-ah' requests a +high-level language listing, '-al' requests an output-program assembly +listing, and '-as' requests a symbol table listing. High-level listings +require that a compiler debugging option like '-g' be used, and that +assembly listings ('-al') be requested also. - Use the `-ag' option to print a first section with general assembly + Use the '-ag' option to print a first section with general assembly information, like as version, switches passed, or time stamp. - Use the `-ac' option to omit false conditionals from a listing. Any -lines which are not assembled because of a false `.if' (or `.ifdef', or -any other conditional), or a true `.if' followed by an `.else', will be + Use the '-ac' option to omit false conditionals from a listing. Any +lines which are not assembled because of a false '.if' (or '.ifdef', or +any other conditional), or a true '.if' followed by an '.else', will be omitted from the listing. - Use the `-ad' option to omit debugging directives from the listing. + Use the '-ad' option to omit debugging directives from the listing. Once you have specified one of these options, you can further control -listing output and its appearance using the directives `.list', -`.nolist', `.psize', `.eject', `.title', and `.sbttl'. The `-an' -option turns off all forms processing. If you do not request listing -output with one of the `-a' options, the listing-control directives -have no effect. +listing output and its appearance using the directives '.list', +'.nolist', '.psize', '.eject', '.title', and '.sbttl'. The '-an' option +turns off all forms processing. If you do not request listing output +with one of the '-a' options, the listing-control directives have no +effect. - The letters after `-a' may be combined into one option, _e.g._, -`-aln'. + The letters after '-a' may be combined into one option, _e.g._, +'-aln'. Note if the assembler source is coming from the standard input (e.g., -because it is being created by `gcc' and the `-pipe' command line switch +because it is being created by 'gcc' and the '-pipe' command line switch is being used) then the listing will not contain any comments or -preprocessor directives. This is because the listing code buffers -input source lines from stdin only after they have been preprocessed by -the assembler. This reduces memory usage and makes the code more -efficient. +preprocessor directives. This is because the listing code buffers input +source lines from stdin only after they have been preprocessed by the +assembler. This reduces memory usage and makes the code more efficient. File: as.info, Node: alternate, Next: D, Prev: a, Up: Invoking -2.2 `--alternate' +2.2 '--alternate' ================= -Begin in alternate macro mode, see *note `.altmacro': Altmacro. +Begin in alternate macro mode, see *note '.altmacro': Altmacro. File: as.info, Node: D, Next: f, Prev: alternate, Up: Invoking -2.3 `-D' +2.3 '-D' ======== This option has no effect whatsoever, but it is accepted to make it more -likely that scripts written for other assemblers also work with `as'. +likely that scripts written for other assemblers also work with 'as'. File: as.info, Node: f, Next: I, Prev: D, Up: Invoking -2.4 Work Faster: `-f' +2.4 Work Faster: '-f' ===================== -`-f' should only be used when assembling programs written by a -(trusted) compiler. `-f' stops the assembler from doing whitespace and -comment preprocessing on the input file(s) before assembling them. -*Note Preprocessing: Preprocessing. +'-f' should only be used when assembling programs written by a (trusted) +compiler. '-f' stops the assembler from doing whitespace and comment +preprocessing on the input file(s) before assembling them. *Note +Preprocessing: Preprocessing. - _Warning:_ if you use `-f' when the files actually need to be - preprocessed (if they contain comments, for example), `as' does - not work correctly. + _Warning:_ if you use '-f' when the files actually need to be + preprocessed (if they contain comments, for example), 'as' does not + work correctly. File: as.info, Node: I, Next: K, Prev: f, Up: Invoking -2.5 `.include' Search Path: `-I' PATH +2.5 '.include' Search Path: '-I' PATH ===================================== -Use this option to add a PATH to the list of directories `as' searches -for files specified in `.include' directives (*note `.include': -Include.). You may use `-I' as many times as necessary to include a +Use this option to add a PATH to the list of directories 'as' searches +for files specified in '.include' directives (*note '.include': +Include.). You may use '-I' as many times as necessary to include a variety of paths. The current working directory is always searched -first; after that, `as' searches any `-I' directories in the same order +first; after that, 'as' searches any '-I' directories in the same order as they were specified (left to right) on the command line. File: as.info, Node: K, Next: L, Prev: I, Up: Invoking -2.6 Difference Tables: `-K' +2.6 Difference Tables: '-K' =========================== -`as' sometimes alters the code emitted for directives of the form -`.word SYM1-SYM2'. *Note `.word': Word. You can use the `-K' option -if you want a warning issued when this is done. +'as' sometimes alters the code emitted for directives of the form '.word +SYM1-SYM2'. *Note '.word': Word. You can use the '-K' option if you +want a warning issued when this is done. File: as.info, Node: L, Next: listing, Prev: K, Up: Invoking -2.7 Include Local Symbols: `-L' +2.7 Include Local Symbols: '-L' =============================== Symbols beginning with system-specific local label prefixes, typically -`.L' for ELF systems or `L' for traditional a.out systems, are called +'.L' for ELF systems or 'L' for traditional a.out systems, are called "local symbols". *Note Symbol Names::. Normally you do not see such symbols when debugging, because they are intended for the use of programs (like compilers) that compose assembler programs, not for your -notice. Normally both `as' and `ld' discard such symbols, so you do -not normally debug with them. +notice. Normally both 'as' and 'ld' discard such symbols, so you do not +normally debug with them. - This option tells `as' to retain those local symbols in the object -file. Usually if you do this you also tell the linker `ld' to preserve + This option tells 'as' to retain those local symbols in the object +file. Usually if you do this you also tell the linker 'ld' to preserve those symbols. File: as.info, Node: listing, Next: M, Prev: L, Up: Invoking -2.8 Configuring listing output: `--listing' +2.8 Configuring listing output: '--listing' =========================================== -The listing feature of the assembler can be enabled via the command -line switch `-a' (*note a::). This feature combines the input source -file(s) with a hex dump of the corresponding locations in the output -object file, and displays them as a listing file. The format of this -listing can be controlled by directives inside the assembler source -(i.e., `.list' (*note List::), `.title' (*note Title::), `.sbttl' -(*note Sbttl::), `.psize' (*note Psize::), and `.eject' (*note Eject::) -and also by the following switches: - -`--listing-lhs-width=`number'' - Sets the maximum width, in words, of the first line of the hex - byte dump. This dump appears on the left hand side of the listing +The listing feature of the assembler can be enabled via the command line +switch '-a' (*note a::). This feature combines the input source file(s) +with a hex dump of the corresponding locations in the output object +file, and displays them as a listing file. The format of this listing +can be controlled by directives inside the assembler source (i.e., +'.list' (*note List::), '.title' (*note Title::), '.sbttl' (*note +Sbttl::), '.psize' (*note Psize::), and '.eject' (*note Eject::) and +also by the following switches: + +'--listing-lhs-width='number'' + Sets the maximum width, in words, of the first line of the hex byte + dump. This dump appears on the left hand side of the listing output. -`--listing-lhs-width2=`number'' +'--listing-lhs-width2='number'' Sets the maximum width, in words, of any further lines of the hex byte dump for a given input source line. If this value is not - specified, it defaults to being the same as the value specified - for `--listing-lhs-width'. If neither switch is used the default - is to one. + specified, it defaults to being the same as the value specified for + '--listing-lhs-width'. If neither switch is used the default is to + one. -`--listing-rhs-width=`number'' +'--listing-rhs-width='number'' Sets the maximum width, in characters, of the source line that is displayed alongside the hex dump. The default value for this parameter is 100. The source line is displayed on the right hand side of the listing output. -`--listing-cont-lines=`number'' - Sets the maximum number of continuation lines of hex dump that - will be displayed for a given single line of source input. The - default value is 4. +'--listing-cont-lines='number'' + Sets the maximum number of continuation lines of hex dump that will + be displayed for a given single line of source input. The default + value is 4. File: as.info, Node: M, Next: MD, Prev: listing, Up: Invoking -2.9 Assemble in MRI Compatibility Mode: `-M' +2.9 Assemble in MRI Compatibility Mode: '-M' ============================================ -The `-M' or `--mri' option selects MRI compatibility mode. This -changes the syntax and pseudo-op handling of `as' to make it compatible -with the `ASM68K' or the `ASM960' (depending upon the configured -target) assembler from Microtec Research. The exact nature of the MRI -syntax will not be documented here; see the MRI manuals for more -information. Note in particular that the handling of macros and macro -arguments is somewhat different. The purpose of this option is to -permit assembling existing MRI assembler code using `as'. +The '-M' or '--mri' option selects MRI compatibility mode. This changes +the syntax and pseudo-op handling of 'as' to make it compatible with the +'ASM68K' or the 'ASM960' (depending upon the configured target) +assembler from Microtec Research. The exact nature of the MRI syntax +will not be documented here; see the MRI manuals for more information. +Note in particular that the handling of macros and macro arguments is +somewhat different. The purpose of this option is to permit assembling +existing MRI assembler code using 'as'. - The MRI compatibility is not complete. Certain operations of the -MRI assembler depend upon its object file format, and can not be -supported using other object file formats. Supporting these would -require enhancing each object file format individually. These are: + The MRI compatibility is not complete. Certain operations of the MRI +assembler depend upon its object file format, and can not be supported +using other object file formats. Supporting these would require +enhancing each object file format individually. These are: * global symbols in common section - The m68k MRI assembler supports common sections which are merged - by the linker. Other object file formats do not support this. - `as' handles common sections by treating them as a single common - symbol. It permits local symbols to be defined within a common - section, but it can not support global symbols, since it has no - way to describe them. + The m68k MRI assembler supports common sections which are merged by + the linker. Other object file formats do not support this. 'as' + handles common sections by treating them as a single common symbol. + It permits local symbols to be defined within a common section, but + it can not support global symbols, since it has no way to describe + them. * complex relocations @@ -1478,31 +1460,31 @@ require enhancing each object file format individually. These are: or more sections. These are not support by other object file formats. - * `END' pseudo-op specifying start address + * 'END' pseudo-op specifying start address - The MRI `END' pseudo-op permits the specification of a start + The MRI 'END' pseudo-op permits the specification of a start address. This is not supported by other object file formats. The - start address may instead be specified using the `-e' option to - the linker, or in a linker script. + start address may instead be specified using the '-e' option to the + linker, or in a linker script. - * `IDNT', `.ident' and `NAME' pseudo-ops + * 'IDNT', '.ident' and 'NAME' pseudo-ops - The MRI `IDNT', `.ident' and `NAME' pseudo-ops assign a module - name to the output file. This is not supported by other object - file formats. + The MRI 'IDNT', '.ident' and 'NAME' pseudo-ops assign a module name + to the output file. This is not supported by other object file + formats. - * `ORG' pseudo-op + * 'ORG' pseudo-op - The m68k MRI `ORG' pseudo-op begins an absolute section at a given - address. This differs from the usual `as' `.org' pseudo-op, which - changes the location within the current section. Absolute - sections are not supported by other object file formats. The - address of a section may be assigned within a linker script. + The m68k MRI 'ORG' pseudo-op begins an absolute section at a given + address. This differs from the usual 'as' '.org' pseudo-op, which + changes the location within the current section. Absolute sections + are not supported by other object file formats. The address of a + section may be assigned within a linker script. There are some other features of the MRI assembler which are not -supported by `as', typically either because they are difficult or -because they seem of little consequence. Some of these may be -supported in future releases. +supported by 'as', typically either because they are difficult or +because they seem of little consequence. Some of these may be supported +in future releases. * EBCDIC strings @@ -1511,76 +1493,75 @@ supported in future releases. * packed binary coded decimal Packed binary coded decimal is not supported. This means that the - `DC.P' and `DCB.P' pseudo-ops are not supported. + 'DC.P' and 'DCB.P' pseudo-ops are not supported. - * `FEQU' pseudo-op + * 'FEQU' pseudo-op - The m68k `FEQU' pseudo-op is not supported. + The m68k 'FEQU' pseudo-op is not supported. - * `NOOBJ' pseudo-op + * 'NOOBJ' pseudo-op - The m68k `NOOBJ' pseudo-op is not supported. + The m68k 'NOOBJ' pseudo-op is not supported. - * `OPT' branch control options + * 'OPT' branch control options - The m68k `OPT' branch control options--`B', `BRS', `BRB', `BRL', - and `BRW'--are ignored. `as' automatically relaxes all branches, + The m68k 'OPT' branch control options--'B', 'BRS', 'BRB', 'BRL', + and 'BRW'--are ignored. 'as' automatically relaxes all branches, whether forward or backward, to an appropriate size, so these options serve no purpose. - * `OPT' list control options + * 'OPT' list control options - The following m68k `OPT' list control options are ignored: `C', - `CEX', `CL', `CRE', `E', `G', `I', `M', `MEX', `MC', `MD', `X'. + The following m68k 'OPT' list control options are ignored: 'C', + 'CEX', 'CL', 'CRE', 'E', 'G', 'I', 'M', 'MEX', 'MC', 'MD', 'X'. - * other `OPT' options + * other 'OPT' options - The following m68k `OPT' options are ignored: `NEST', `O', `OLD', - `OP', `P', `PCO', `PCR', `PCS', `R'. + The following m68k 'OPT' options are ignored: 'NEST', 'O', 'OLD', + 'OP', 'P', 'PCO', 'PCR', 'PCS', 'R'. - * `OPT' `D' option is default + * 'OPT' 'D' option is default - The m68k `OPT' `D' option is the default, unlike the MRI assembler. - `OPT NOD' may be used to turn it off. + The m68k 'OPT' 'D' option is the default, unlike the MRI assembler. + 'OPT NOD' may be used to turn it off. - * `XREF' pseudo-op. + * 'XREF' pseudo-op. - The m68k `XREF' pseudo-op is ignored. + The m68k 'XREF' pseudo-op is ignored. - * `.debug' pseudo-op + * '.debug' pseudo-op - The i960 `.debug' pseudo-op is not supported. + The i960 '.debug' pseudo-op is not supported. - * `.extended' pseudo-op + * '.extended' pseudo-op - The i960 `.extended' pseudo-op is not supported. + The i960 '.extended' pseudo-op is not supported. - * `.list' pseudo-op. + * '.list' pseudo-op. - The various options of the i960 `.list' pseudo-op are not + The various options of the i960 '.list' pseudo-op are not supported. - * `.optimize' pseudo-op - - The i960 `.optimize' pseudo-op is not supported. + * '.optimize' pseudo-op - * `.output' pseudo-op + The i960 '.optimize' pseudo-op is not supported. - The i960 `.output' pseudo-op is not supported. + * '.output' pseudo-op - * `.setreal' pseudo-op + The i960 '.output' pseudo-op is not supported. - The i960 `.setreal' pseudo-op is not supported. + * '.setreal' pseudo-op + The i960 '.setreal' pseudo-op is not supported. File: as.info, Node: MD, Next: o, Prev: M, Up: Invoking -2.10 Dependency Tracking: `--MD' +2.10 Dependency Tracking: '--MD' ================================ -`as' can generate a dependency file for the file it creates. This file -consists of a single rule suitable for `make' describing the +'as' can generate a dependency file for the file it creates. This file +consists of a single rule suitable for 'make' describing the dependencies of the main source file. The rule is written to the file named in its argument. @@ -1590,108 +1571,108 @@ dependencies of the main source file. File: as.info, Node: o, Next: R, Prev: MD, Up: Invoking -2.11 Name the Object File: `-o' +2.11 Name the Object File: '-o' =============================== -There is always one object file output when you run `as'. By default -it has the name `a.out' (or `b.out', for Intel 960 targets only). You -use this option (which takes exactly one filename) to give the object -file a different name. +There is always one object file output when you run 'as'. By default it +has the name 'a.out' (or 'b.out', for Intel 960 targets only). You use +this option (which takes exactly one filename) to give the object file a +different name. - Whatever the object file is called, `as' overwrites any existing -file of the same name. + Whatever the object file is called, 'as' overwrites any existing file +of the same name. File: as.info, Node: R, Next: statistics, Prev: o, Up: Invoking -2.12 Join Data and Text Sections: `-R' +2.12 Join Data and Text Sections: '-R' ====================================== -`-R' tells `as' to write the object file as if all data-section data +'-R' tells 'as' to write the object file as if all data-section data lives in the text section. This is only done at the very last moment: your binary data are the same, but data section parts are relocated differently. The data section part of your object file is zero bytes long because all its bytes are appended to the text section. (*Note Sections and Relocation: Sections.) - When you specify `-R' it would be possible to generate shorter + When you specify '-R' it would be possible to generate shorter address displacements (because we do not have to cross between text and data section). We refrain from doing this simply for compatibility with -older versions of `as'. In future, `-R' may work this way. +older versions of 'as'. In future, '-R' may work this way. - When `as' is configured for COFF or ELF output, this option is only -useful if you use sections named `.text' and `.data'. + When 'as' is configured for COFF or ELF output, this option is only +useful if you use sections named '.text' and '.data'. - `-R' is not supported for any of the HPPA targets. Using `-R' -generates a warning from `as'. + '-R' is not supported for any of the HPPA targets. Using '-R' +generates a warning from 'as'. File: as.info, Node: statistics, Next: traditional-format, Prev: R, Up: Invoking -2.13 Display Assembly Statistics: `--statistics' +2.13 Display Assembly Statistics: '--statistics' ================================================ -Use `--statistics' to display two statistics about the resources used by -`as': the maximum amount of space allocated during the assembly (in +Use '--statistics' to display two statistics about the resources used by +'as': the maximum amount of space allocated during the assembly (in bytes), and the total execution time taken for the assembly (in CPU seconds). File: as.info, Node: traditional-format, Next: v, Prev: statistics, Up: Invoking -2.14 Compatible Output: `--traditional-format' +2.14 Compatible Output: '--traditional-format' ============================================== -For some targets, the output of `as' is different in some ways from the -output of some existing assembler. This switch requests `as' to use -the traditional format instead. +For some targets, the output of 'as' is different in some ways from the +output of some existing assembler. This switch requests 'as' to use the +traditional format instead. - For example, it disables the exception frame optimizations which -`as' normally does by default on `gcc' output. + For example, it disables the exception frame optimizations which 'as' +normally does by default on 'gcc' output. File: as.info, Node: v, Next: W, Prev: traditional-format, Up: Invoking -2.15 Announce Version: `-v' +2.15 Announce Version: '-v' =========================== You can find out what version of as is running by including the option -`-v' (which you can also spell as `-version') on the command line. +'-v' (which you can also spell as '-version') on the command line. File: as.info, Node: W, Next: Z, Prev: v, Up: Invoking -2.16 Control Warnings: `-W', `--warn', `--no-warn', `--fatal-warnings' +2.16 Control Warnings: '-W', '--warn', '--no-warn', '--fatal-warnings' ====================================================================== -`as' should never give a warning or error message when assembling -compiler output. But programs written by people often cause `as' to -give a warning that a particular assumption was made. All such -warnings are directed to the standard error file. +'as' should never give a warning or error message when assembling +compiler output. But programs written by people often cause 'as' to +give a warning that a particular assumption was made. All such warnings +are directed to the standard error file. - If you use the `-W' and `--no-warn' options, no warnings are issued. + If you use the '-W' and '--no-warn' options, no warnings are issued. This only affects the warning messages: it does not change any -particular of how `as' assembles your file. Errors, which stop the +particular of how 'as' assembles your file. Errors, which stop the assembly, are still reported. - If you use the `--fatal-warnings' option, `as' considers files that + If you use the '--fatal-warnings' option, 'as' considers files that generate warnings to be in error. - You can switch these options off again by specifying `--warn', which + You can switch these options off again by specifying '--warn', which causes warnings to be output as usual. File: as.info, Node: Z, Prev: W, Up: Invoking -2.17 Generate Object File in Spite of Errors: `-Z' +2.17 Generate Object File in Spite of Errors: '-Z' ================================================== -After an error message, `as' normally produces no output. If for some -reason you are interested in object file output even after `as' gives -an error message on your program, use the `-Z' option. If there are -any errors, `as' continues anyways, and writes an object file after a -final warning message of the form `N errors, M warnings, generating bad -object file.' +After an error message, 'as' normally produces no output. If for some +reason you are interested in object file output even after 'as' gives an +error message on your program, use the '-Z' option. If there are any +errors, 'as' continues anyways, and writes an object file after a final +warning message of the form 'N errors, M warnings, generating bad object +file.' File: as.info, Node: Syntax, Next: Sections, Prev: Invoking, Up: Top @@ -1700,8 +1681,8 @@ File: as.info, Node: Syntax, Next: Sections, Prev: Invoking, Up: Top ******** This chapter describes the machine-independent syntax allowed in a -source file. `as' syntax is similar to what many other assemblers use; -it is inspired by the BSD 4.2 assembler, except that `as' does not +source file. 'as' syntax is similar to what many other assemblers use; +it is inspired by the BSD 4.2 assembler, except that 'as' does not assemble Vax bit-fields. * Menu: @@ -1719,7 +1700,7 @@ File: as.info, Node: Preprocessing, Next: Whitespace, Up: Syntax 3.1 Preprocessing ================= -The `as' internal preprocessor: +The 'as' internal preprocessor: * adjusts and removes extra whitespace. It leaves one space or tab before the keywords on a line, and turns any other whitespace on the line into a single space. @@ -1731,22 +1712,22 @@ The `as' internal preprocessor: It does not do macro processing, include file handling, or anything else you may get from your C compiler's preprocessor. You can do -include file processing with the `.include' directive (*note -`.include': Include.). You can use the GNU C compiler driver to get -other "CPP" style preprocessing by giving the input file a `.S' suffix. -*Note Options Controlling the Kind of Output: (gcc.info)Overall Options. +include file processing with the '.include' directive (*note '.include': +Include.). You can use the GNU C compiler driver to get other "CPP" +style preprocessing by giving the input file a '.S' suffix. *Note +Options Controlling the Kind of Output: (gcc.info)Overall Options. Excess whitespace, comments, and character constants cannot be used in the portions of the input text that are not preprocessed. - If the first line of an input file is `#NO_APP' or if you use the -`-f' option, whitespace and comments are not removed from the input + If the first line of an input file is '#NO_APP' or if you use the +'-f' option, whitespace and comments are not removed from the input file. Within an input file, you can ask for whitespace and comment -removal in specific portions of the by putting a line that says `#APP' +removal in specific portions of the by putting a line that says '#APP' before the text that may contain whitespace or comments, and putting a -line that says `#NO_APP' after this text. This feature is mainly -intend to support `asm' statements in compilers whose output is -otherwise free of comments and whitespace. +line that says '#NO_APP' after this text. This feature is mainly intend +to support 'asm' statements in compilers whose output is otherwise free +of comments and whitespace. File: as.info, Node: Whitespace, Next: Comments, Prev: Preprocessing, Up: Syntax @@ -1754,8 +1735,8 @@ File: as.info, Node: Whitespace, Next: Comments, Prev: Preprocessing, Up: Sy 3.2 Whitespace ============== -"Whitespace" is one or more blanks or tabs, in any order. Whitespace -is used to separate symbols, and to make programs neater for people to +"Whitespace" is one or more blanks or tabs, in any order. Whitespace is +used to separate symbols, and to make programs neater for people to read. Unless within character constants (*note Character Constants: Characters.), any whitespace means the same as exactly one space. @@ -1765,10 +1746,10 @@ File: as.info, Node: Comments, Next: Symbol Intro, Prev: Whitespace, Up: Syn 3.3 Comments ============ -There are two ways of rendering comments to `as'. In both cases the +There are two ways of rendering comments to 'as'. In both cases the comment is equivalent to one space. - Anything from `/*' through the next `*/' is a comment. This means + Anything from '/*' through the next '*/' is a comment. This means you may not nest these comments. /* @@ -1781,22 +1762,22 @@ you may not nest these comments. Anything from a "line comment" character up to the next newline is considered a comment and is ignored. The line comment character is target specific, and some targets multiple comment characters. Some -targets also have line comment characters that only work if they are -the first character on a line. Some targets use a sequence of two +targets also have line comment characters that only work if they are the +first character on a line. Some targets use a sequence of two characters to introduce a line comment. Some targets can also change their line comment characters depending upon command line options that have been used. For more details see the _Syntax_ section in the documentation for individual targets. - If the line comment character is the hash sign (`#') then it still + If the line comment character is the hash sign ('#') then it still has the special ability to enable and disable preprocessing (*note Preprocessing::) and to specify logical line numbers: - To be compatible with past assemblers, lines that begin with `#' -have a special interpretation. Following the `#' should be an absolute + To be compatible with past assemblers, lines that begin with '#' have +a special interpretation. Following the '#' should be an absolute expression (*note Expressions::): the logical line number of the _next_ -line. Then a string (*note Strings: Strings.) is allowed: if present -it is a new logical file name. The rest of the line, if any, should be +line. Then a string (*note Strings: Strings.) is allowed: if present it +is a new logical file name. The rest of the line, if any, should be whitespace. If the first non-whitespace characters on the line are not numeric, @@ -1805,8 +1786,8 @@ the line is ignored. (Just like a comment.) # This is an ordinary comment. # 42-6 "new_file_name" # New logical file name # This is logical line # 36. - This feature is deprecated, and may disappear from future versions -of `as'. + This feature is deprecated, and may disappear from future versions of +'as'. File: as.info, Node: Symbol Intro, Next: Statements, Prev: Comments, Up: Syntax @@ -1815,14 +1796,14 @@ File: as.info, Node: Symbol Intro, Next: Statements, Prev: Comments, Up: Syn =========== A "symbol" is one or more characters chosen from the set of all letters -(both upper and lower case), digits and the three characters `_.$'. On -most machines, you can also use `$' in symbol names; exceptions are +(both upper and lower case), digits and the three characters '_.$'. On +most machines, you can also use '$' in symbol names; exceptions are noted in *note Machine Dependencies::. No symbol may begin with a digit. Case is significant. There is no length limit: all characters are significant. Multibyte characters are supported. Symbols are delimited by characters not in that set, or by the beginning of a file (since the source program must end with a newline, the end of a file is -not a possible symbol delimiter). *Note Symbols::. +not a possible symbol delimiter). *Note Symbols::. File: as.info, Node: Statements, Next: Constants, Prev: Symbol Intro, Up: Syntax @@ -1830,15 +1811,15 @@ File: as.info, Node: Statements, Next: Constants, Prev: Symbol Intro, Up: Sy 3.5 Statements ============== -A "statement" ends at a newline character (`\n') or a "line separator +A "statement" ends at a newline character ('\n') or a "line separator character". The line separator character is target specific and described in the _Syntax_ section of each target's documentation. Not all targets support a line separator character. The newline or line -separator character is considered to be part of the preceding -statement. Newlines and separators within character constants are an -exception: they do not end statements. +separator character is considered to be part of the preceding statement. +Newlines and separators within character constants are an exception: +they do not end statements. - It is an error to end any statement with end-of-file: the last + It is an error to end any statement with end-of-file: the last character of any input file should be a newline. An empty statement is allowed, and may include whitespace. It is @@ -1847,21 +1828,21 @@ ignored. A statement begins with zero or more labels, optionally followed by a key symbol which determines what kind of statement it is. The key symbol determines the syntax of the rest of the statement. If the -symbol begins with a dot `.' then the statement is an assembler +symbol begins with a dot '.' then the statement is an assembler directive: typically valid for any computer. If the symbol begins with a letter the statement is an assembly language "instruction": it assembles into a machine language instruction. Different versions of -`as' for different computers recognize different instructions. In -fact, the same symbol may represent a different instruction in a -different computer's assembly language. +'as' for different computers recognize different instructions. In fact, +the same symbol may represent a different instruction in a different +computer's assembly language. - A label is a symbol immediately followed by a colon (`:'). + A label is a symbol immediately followed by a colon (':'). Whitespace before a label or after a colon is permitted, but you may not -have whitespace between a label's symbol and its colon. *Note Labels::. +have whitespace between a label's symbol and its colon. *Note Labels::. - For HPPA targets, labels need not be immediately followed by a -colon, but the definition of a label must begin in column zero. This -also implies that only one label may be defined on each line. + For HPPA targets, labels need not be immediately followed by a colon, +but the definition of a label must begin in column zero. This also +implies that only one label may be defined on each line. label: .directive followed by something another_label: # This is an empty statement. @@ -1912,51 +1893,51 @@ File: as.info, Node: Strings, Next: Chars, Up: Characters A "string" is written between double-quotes. It may contain double-quotes or null characters. The way to get special characters into a string is to "escape" these characters: precede them with a -backslash `\' character. For example `\\' represents one backslash: -the first `\' is an escape which tells `as' to interpret the second -character literally as a backslash (which prevents `as' from -recognizing the second `\' as an escape character). The complete list -of escapes follows. +backslash '\' character. For example '\\' represents one backslash: the +first '\' is an escape which tells 'as' to interpret the second +character literally as a backslash (which prevents 'as' from recognizing +the second '\' as an escape character). The complete list of escapes +follows. -`\b' +'\b' Mnemonic for backspace; for ASCII this is octal code 010. -`\f' +'\f' Mnemonic for FormFeed; for ASCII this is octal code 014. -`\n' +'\n' Mnemonic for newline; for ASCII this is octal code 012. -`\r' +'\r' Mnemonic for carriage-Return; for ASCII this is octal code 015. -`\t' +'\t' Mnemonic for horizontal Tab; for ASCII this is octal code 011. -`\ DIGIT DIGIT DIGIT' +'\ DIGIT DIGIT DIGIT' An octal character code. The numeric code is 3 octal digits. For compatibility with other Unix systems, 8 and 9 are accepted as - digits: for example, `\008' has the value 010, and `\009' the - value 011. + digits: for example, '\008' has the value 010, and '\009' the value + 011. -`\`x' HEX-DIGITS...' +'\x HEX-DIGITS...' A hex character code. All trailing hex digits are combined. - Either upper or lower case `x' works. + Either upper or lower case 'x' works. -`\\' - Represents one `\' character. +'\\' + Represents one '\' character. -`\"' - Represents one `"' character. Needed in strings to represent this - character, because an unescaped `"' would end the string. +'\"' + Represents one '"' character. Needed in strings to represent this + character, because an unescaped '"' would end the string. -`\ ANYTHING-ELSE' - Any other character when escaped by `\' gives a warning, but - assembles as if the `\' was not present. The idea is that if you +'\ ANYTHING-ELSE' + Any other character when escaped by '\' gives a warning, but + assembles as if the '\' was not present. The idea is that if you used an escape sequence you clearly didn't want the literal - interpretation of the following character. However `as' has no - other interpretation, so `as' knows it is giving you the wrong - code and warns you of the fact. + interpretation of the following character. However 'as' has no + other interpretation, so 'as' knows it is giving you the wrong code + and warns you of the fact. Which characters are escapable, and what those escapes represent, varies widely among assemblers. The current set is what we think the @@ -1969,16 +1950,16 @@ File: as.info, Node: Chars, Prev: Strings, Up: Characters 3.6.1.2 Characters .................. -A single character may be written as a single quote immediately -followed by that character. The same escapes apply to characters as to -strings. So if you want to write the character backslash, you must -write `'\\' where the first `\' escapes the second `\'. As you can -see, the quote is an acute accent, not a grave accent. A newline -immediately following an acute accent is taken as a literal character -and does not count as the end of a statement. The value of a character -constant in a numeric expression is the machine's byte-wide code for -that character. `as' assumes your character code is ASCII: `'A' means -65, `'B' means 66, and so on. +A single character may be written as a single quote immediately followed +by that character. The same escapes apply to characters as to strings. +So if you want to write the character backslash, you must write ''\\' +where the first '\' escapes the second '\'. As you can see, the quote +is an acute accent, not a grave accent. A newline immediately following +an acute accent is taken as a literal character and does not count as +the end of a statement. The value of a character constant in a numeric +expression is the machine's byte-wide code for that character. 'as' +assumes your character code is ASCII: ''A' means 65, ''B' means 66, and +so on. File: as.info, Node: Numbers, Prev: Characters, Up: Constants @@ -1986,9 +1967,9 @@ File: as.info, Node: Numbers, Prev: Characters, Up: Constants 3.6.2 Number Constants ---------------------- -`as' distinguishes three kinds of numbers according to how they are +'as' distinguishes three kinds of numbers according to how they are stored in the target machine. _Integers_ are numbers that would fit -into an `int' in the C language. _Bignums_ are integers, but they are +into an 'int' in the C language. _Bignums_ are integers, but they are stored in more than 32 bits. _Flonums_ are floating point numbers, described below. @@ -2004,20 +1985,20 @@ File: as.info, Node: Integers, Next: Bignums, Up: Numbers 3.6.2.1 Integers ................ -A binary integer is `0b' or `0B' followed by zero or more of the binary -digits `01'. +A binary integer is '0b' or '0B' followed by zero or more of the binary +digits '01'. - An octal integer is `0' followed by zero or more of the octal digits -(`01234567'). + An octal integer is '0' followed by zero or more of the octal digits +('01234567'). A decimal integer starts with a non-zero digit followed by zero or -more digits (`0123456789'). +more digits ('0123456789'). - A hexadecimal integer is `0x' or `0X' followed by one or more -hexadecimal digits chosen from `0123456789abcdefABCDEF'. + A hexadecimal integer is '0x' or '0X' followed by one or more +hexadecimal digits chosen from '0123456789abcdefABCDEF'. Integers have the usual values. To denote a negative integer, use -the prefix operator `-' discussed under expressions (*note Prefix +the prefix operator '-' discussed under expressions (*note Prefix Operators: Prefix Ops.). @@ -2039,51 +2020,48 @@ File: as.info, Node: Flonums, Prev: Bignums, Up: Numbers A "flonum" represents a floating point number. The translation is indirect: a decimal floating point number from the text is converted by -`as' to a generic binary floating point number of more than sufficient +'as' to a generic binary floating point number of more than sufficient precision. This generic floating point number is converted to a -particular computer's floating point format (or formats) by a portion -of `as' specialized to that computer. +particular computer's floating point format (or formats) by a portion of +'as' specialized to that computer. A flonum is written by writing (in order) - * The digit `0'. (`0' is optional on the HPPA.) + * The digit '0'. ('0' is optional on the HPPA.) - * A letter, to tell `as' the rest of the number is a flonum. `e' is + * A letter, to tell 'as' the rest of the number is a flonum. 'e' is recommended. Case is not important. On the H8/300, Renesas / SuperH SH, and AMD 29K architectures, the - letter must be one of the letters `DFPRSX' (in upper or lower + letter must be one of the letters 'DFPRSX' (in upper or lower case). - On the ARC, the letter must be one of the letters `DFRS' (in upper + On the ARC, the letter must be one of the letters 'DFRS' (in upper or lower case). On the Intel 960 architecture, the letter must be one of the - letters `DFT' (in upper or lower case). + letters 'DFT' (in upper or lower case). - On the HPPA architecture, the letter must be `E' (upper case only). + On the HPPA architecture, the letter must be 'E' (upper case only). - * An optional sign: either `+' or `-'. + * An optional sign: either '+' or '-'. * An optional "integer part": zero or more decimal digits. - * An optional "fractional part": `.' followed by zero or more - decimal digits. + * An optional "fractional part": '.' followed by zero or more decimal + digits. * An optional exponent, consisting of: - * An `E' or `e'. - - * Optional sign: either `+' or `-'. - + * An 'E' or 'e'. + * Optional sign: either '+' or '-'. * One or more decimal digits. - At least one of the integer part or the fractional part must be present. The floating point number has the usual base-10 value. - `as' does all processing using integers. Flonums are computed + 'as' does all processing using integers. Flonums are computed independently of any floating point hardware in the computer running -`as'. +'as'. File: as.info, Node: Sections, Next: Symbols, Prev: Syntax, Up: Top @@ -2109,82 +2087,79 @@ Roughly, a section is a range of addresses, with no gaps; all data "in" those addresses is treated the same for some particular purpose. For example there may be a "read only" section. - The linker `ld' reads many object files (partial programs) and -combines their contents to form a runnable program. When `as' emits an -object file, the partial program is assumed to start at address 0. -`ld' assigns the final addresses for the partial program, so that -different partial programs do not overlap. This is actually an -oversimplification, but it suffices to explain how `as' uses sections. + The linker 'ld' reads many object files (partial programs) and +combines their contents to form a runnable program. When 'as' emits an +object file, the partial program is assumed to start at address 0. 'ld' +assigns the final addresses for the partial program, so that different +partial programs do not overlap. This is actually an +oversimplification, but it suffices to explain how 'as' uses sections. - `ld' moves blocks of bytes of your program to their run-time + 'ld' moves blocks of bytes of your program to their run-time addresses. These blocks slide to their run-time addresses as rigid units; their length does not change and neither does the order of bytes within them. Such a rigid unit is called a _section_. Assigning run-time addresses to sections is called "relocation". It includes the -task of adjusting mentions of object-file addresses so they refer to -the proper run-time addresses. For the H8/300, and for the Renesas / -SuperH SH, `as' pads sections if needed to ensure they end on a word -(sixteen bit) boundary. +task of adjusting mentions of object-file addresses so they refer to the +proper run-time addresses. For the H8/300, and for the Renesas / SuperH +SH, 'as' pads sections if needed to ensure they end on a word (sixteen +bit) boundary. - An object file written by `as' has at least three sections, any of + An object file written by 'as' has at least three sections, any of which may be empty. These are named "text", "data" and "bss" sections. - When it generates COFF or ELF output, `as' can also generate -whatever other named sections you specify using the `.section' -directive (*note `.section': Section.). If you do not use any -directives that place output in the `.text' or `.data' sections, these -sections still exist, but are empty. + When it generates COFF or ELF output, 'as' can also generate whatever +other named sections you specify using the '.section' directive (*note +'.section': Section.). If you do not use any directives that place +output in the '.text' or '.data' sections, these sections still exist, +but are empty. - When `as' generates SOM or ELF output for the HPPA, `as' can also -generate whatever other named sections you specify using the `.space' -and `.subspace' directives. See `HP9000 Series 800 Assembly Language -Reference Manual' (HP 92432-90001) for details on the `.space' and -`.subspace' assembler directives. + When 'as' generates SOM or ELF output for the HPPA, 'as' can also +generate whatever other named sections you specify using the '.space' +and '.subspace' directives. See 'HP9000 Series 800 Assembly Language +Reference Manual' (HP 92432-90001) for details on the '.space' and +'.subspace' assembler directives. - Additionally, `as' uses different names for the standard text, data, + Additionally, 'as' uses different names for the standard text, data, and bss sections when generating SOM output. Program text is placed -into the `$CODE$' section, data into `$DATA$', and BSS into `$BSS$'. +into the '$CODE$' section, data into '$DATA$', and BSS into '$BSS$'. - Within the object file, the text section starts at address `0', the + Within the object file, the text section starts at address '0', the data section follows, and the bss section follows the data section. When generating either SOM or ELF output files on the HPPA, the text -section starts at address `0', the data section at address `0x4000000', +section starts at address '0', the data section at address '0x4000000', and the bss section follows the data section. - To let `ld' know which data changes when the sections are relocated, -and how to change that data, `as' also writes to the object file -details of the relocation needed. To perform relocation `ld' must -know, each time an address in the object file is mentioned: + To let 'ld' know which data changes when the sections are relocated, +and how to change that data, 'as' also writes to the object file details +of the relocation needed. To perform relocation 'ld' must know, each +time an address in the object file is mentioned: * Where in the object file is the beginning of this reference to an address? - * How long (in bytes) is this reference? - - * Which section does the address refer to? What is the numeric - value of + * Which section does the address refer to? What is the numeric value + of (ADDRESS) - (START-ADDRESS OF SECTION)? - * Is the reference to an address "Program-Counter relative"? - In fact, every address `as' ever uses is expressed as + In fact, every address 'as' ever uses is expressed as (SECTION) + (OFFSET INTO SECTION) - Further, most expressions `as' computes have this section-relative +Further, most expressions 'as' computes have this section-relative nature. (For some object formats, such as SOM for the HPPA, some expressions are symbol-relative instead.) - In this manual we use the notation {SECNAME N} to mean "offset N -into section SECNAME." + In this manual we use the notation {SECNAME N} to mean "offset N into +section SECNAME." Apart from text, data and bss sections you need to know about the -"absolute" section. When `ld' mixes partial programs, addresses in the -absolute section remain unchanged. For example, address `{absolute 0}' -is "relocated" to run-time address 0 by `ld'. Although the linker -never arranges two partial programs' data sections with overlapping -addresses after linking, _by definition_ their absolute sections must -overlap. Address `{absolute 239}' in one part of a program is always -the same address when the program is running as address `{absolute -239}' in any other part of the program. +"absolute" section. When 'ld' mixes partial programs, addresses in the +absolute section remain unchanged. For example, address '{absolute 0}' +is "relocated" to run-time address 0 by 'ld'. Although the linker never +arranges two partial programs' data sections with overlapping addresses +after linking, _by definition_ their absolute sections must overlap. +Address '{absolute 239}' in one part of a program is always the same +address when the program is running as address '{absolute 239}' in any +other part of the program. The idea of sections is extended to the "undefined" section. Any address whose section is unknown at assembly time is by definition @@ -2195,14 +2170,13 @@ be such a symbol: its value is unknown at assembly time so it has section _undefined_. By analogy the word _section_ is used to describe groups of sections -in the linked program. `ld' puts all partial programs' text sections -in contiguous addresses in the linked program. It is customary to -refer to the _text section_ of a program, meaning all the addresses of -all partial programs' text sections. Likewise for data and bss -sections. +in the linked program. 'ld' puts all partial programs' text sections in +contiguous addresses in the linked program. It is customary to refer to +the _text section_ of a program, meaning all the addresses of all +partial programs' text sections. Likewise for data and bss sections. - Some sections are manipulated by `ld'; others are invented for use -of `as' and have no meaning except during assembly. + Some sections are manipulated by 'ld'; others are invented for use of +'as' and have no meaning except during assembly. File: as.info, Node: Ld Sections, Next: As Sections, Prev: Secs Background, Up: Sections @@ -2210,16 +2184,16 @@ File: as.info, Node: Ld Sections, Next: As Sections, Prev: Secs Background, 4.2 Linker Sections =================== -`ld' deals with just four kinds of sections, summarized below. +'ld' deals with just four kinds of sections, summarized below. *named sections* *text section* *data section* - These sections hold your program. `as' and `ld' treat them as + These sections hold your program. 'as' and 'ld' treat them as separate but equal sections. Anything you can say of one section is true of another. When the program is running, however, it is - customary for the text section to be unalterable. The text - section is often shared among processes: it contains instructions, + customary for the text section to be unalterable. The text section + is often shared among processes: it contains instructions, constants and the like. The data section of a running program is usually alterable: for example, C variables would be stored in the data section. @@ -2235,17 +2209,17 @@ File: as.info, Node: Ld Sections, Next: As Sections, Prev: Secs Background, *absolute section* Address 0 of this section is always "relocated" to runtime address - 0. This is useful if you want to refer to an address that `ld' + 0. This is useful if you want to refer to an address that 'ld' must not change when relocating. In this sense we speak of - absolute addresses being "unrelocatable": they do not change - during relocation. + absolute addresses being "unrelocatable": they do not change during + relocation. *undefined section* - This "section" is a catch-all for address references to objects - not in the preceding sections. + This "section" is a catch-all for address references to objects not + in the preceding sections. An idealized example of three relocatable sections follows. The -example uses the traditional section names `.text' and `.data'. Memory +example uses the traditional section names '.text' and '.data'. Memory addresses are on the horizontal axis. +-----+----+--+ @@ -2271,16 +2245,16 @@ File: as.info, Node: As Sections, Next: Sub-Sections, Prev: Ld Sections, Up: 4.3 Assembler Internal Sections =============================== -These sections are meant only for the internal use of `as'. They have +These sections are meant only for the internal use of 'as'. They have no meaning at run-time. You do not really need to know about these -sections for most purposes; but they can be mentioned in `as' warning +sections for most purposes; but they can be mentioned in 'as' warning messages, so it might be helpful to have an idea of their meanings to -`as'. These sections are used to permit the value of every expression +'as'. These sections are used to permit the value of every expression in your assembly language program to be a section-relative address. ASSEMBLER-INTERNAL-LOGIC-ERROR! - An internal assembler logic error has been found. This means - there is a bug in the assembler. + An internal assembler logic error has been found. This means there + is a bug in the assembler. expr section The assembler stores complex expression internally as combinations @@ -2296,40 +2270,40 @@ File: as.info, Node: Sub-Sections, Next: bss, Prev: As Sections, Up: Section Assembled bytes conventionally fall into two sections: text and data. You may have separate groups of data in named sections that you want to end up near to each other in the object file, even though they are not -contiguous in the assembler source. `as' allows you to use +contiguous in the assembler source. 'as' allows you to use "subsections" for this purpose. Within each section, there can be -numbered subsections with values from 0 to 8192. Objects assembled -into the same subsection go into the object file together with other -objects in the same subsection. For example, a compiler might want to -store constants in the text section, but might not want to have them +numbered subsections with values from 0 to 8192. Objects assembled into +the same subsection go into the object file together with other objects +in the same subsection. For example, a compiler might want to store +constants in the text section, but might not want to have them interspersed with the program being assembled. In this case, the -compiler could issue a `.text 0' before each section of code being -output, and a `.text 1' before each group of constants being output. +compiler could issue a '.text 0' before each section of code being +output, and a '.text 1' before each group of constants being output. -Subsections are optional. If you do not use subsections, everything + Subsections are optional. If you do not use subsections, everything goes in subsection number zero. Each subsection is zero-padded up to a multiple of four bytes. (Subsections may be padded a different amount on different flavors of -`as'.) +'as'.) Subsections appear in your object file in numeric order, lowest numbered to highest. (All this to be compatible with other people's -assemblers.) The object file contains no representation of -subsections; `ld' and other programs that manipulate object files see -no trace of them. They just see all your text subsections as a text -section, and all your data subsections as a data section. +assemblers.) The object file contains no representation of subsections; +'ld' and other programs that manipulate object files see no trace of +them. They just see all your text subsections as a text section, and +all your data subsections as a data section. To specify which subsection you want subsequent statements assembled -into, use a numeric argument to specify it, in a `.text EXPRESSION' or -a `.data EXPRESSION' statement. When generating COFF output, you can -also use an extra subsection argument with arbitrary named sections: -`.section NAME, EXPRESSION'. When generating ELF output, you can also -use the `.subsection' directive (*note SubSection::) to specify a -subsection: `.subsection EXPRESSION'. EXPRESSION should be an absolute -expression (*note Expressions::). If you just say `.text' then `.text -0' is assumed. Likewise `.data' means `.data 0'. Assembly begins in -`text 0'. For instance: +into, use a numeric argument to specify it, in a '.text EXPRESSION' or a +'.data EXPRESSION' statement. When generating COFF output, you can also +use an extra subsection argument with arbitrary named sections: +'.section NAME, EXPRESSION'. When generating ELF output, you can also +use the '.subsection' directive (*note SubSection::) to specify a +subsection: '.subsection EXPRESSION'. EXPRESSION should be an absolute +expression (*note Expressions::). If you just say '.text' then '.text +0' is assumed. Likewise '.data' means '.data 0'. Assembly begins in +'text 0'. For instance: .text 0 # The default subsection is text 0 anyway. .ascii "This lives in the first text subsection. *" .text 1 @@ -2343,12 +2317,12 @@ expression (*note Expressions::). If you just say `.text' then `.text Each section has a "location counter" incremented by one for every byte assembled into that section. Because subsections are merely a -convenience restricted to `as' there is no concept of a subsection +convenience restricted to 'as' there is no concept of a subsection location counter. There is no way to directly manipulate a location -counter--but the `.align' directive changes it, and any label -definition captures its current value. The location counter of the -section where statements are being assembled is said to be the "active" -location counter. +counter--but the '.align' directive changes it, and any label definition +captures its current value. The location counter of the section where +statements are being assembled is said to be the "active" location +counter. File: as.info, Node: bss, Prev: Sub-Sections, Up: Sections @@ -2361,17 +2335,17 @@ allocate address space in the bss section, but you may not dictate data to load into it before your program executes. When your program starts running, all the contents of the bss section are zeroed bytes. - The `.lcomm' pseudo-op defines a symbol in the bss section; see -*note `.lcomm': Lcomm. + The '.lcomm' pseudo-op defines a symbol in the bss section; see *note +'.lcomm': Lcomm. - The `.comm' pseudo-op may be used to declare a common symbol, which -is another form of uninitialized symbol; see *note `.comm': Comm. + The '.comm' pseudo-op may be used to declare a common symbol, which +is another form of uninitialized symbol; see *note '.comm': Comm. When assembling for a target which supports multiple sections, such -as ELF or COFF, you may switch into the `.bss' section and define -symbols as usual; see *note `.section': Section. You may only assemble +as ELF or COFF, you may switch into the '.bss' section and define +symbols as usual; see *note '.section': Section. You may only assemble zero values into the section. Typically the section will only contain -symbol definitions and `.skip' directives (*note `.skip': Skip.). +symbol definitions and '.skip' directives (*note '.skip': Skip.). File: as.info, Node: Symbols, Next: Expressions, Prev: Sections, Up: Top @@ -2383,7 +2357,7 @@ Symbols are a central concept: the programmer uses symbols to name things, the linker uses symbols to link, and the debugger uses symbols to debug. - _Warning:_ `as' does not place symbols in the object file in the + _Warning:_ 'as' does not place symbols in the object file in the same order they were declared. This may break some debuggers. * Menu: @@ -2400,7 +2374,7 @@ File: as.info, Node: Labels, Next: Setting Symbols, Up: Symbols 5.1 Labels ========== -A "label" is written as a symbol immediately followed by a colon `:'. +A "label" is written as a symbol immediately followed by a colon ':'. The symbol then represents the current value of the active location counter, and is, for example, a suitable instruction operand. You are warned if you use the same symbol to represent two different locations: @@ -2409,7 +2383,7 @@ the first definition overrides any other definitions. On the HPPA, the usual form for a label need not be immediately followed by a colon, but instead must start in column zero. Only one label may be defined on a single line. To work around this, the HPPA -version of `as' also provides a special directive `.label' for defining +version of 'as' also provides a special directive '.label' for defining labels more flexibly. @@ -2419,12 +2393,12 @@ File: as.info, Node: Setting Symbols, Next: Symbol Names, Prev: Labels, Up: =============================== A symbol can be given an arbitrary value by writing a symbol, followed -by an equals sign `=', followed by an expression (*note Expressions::). -This is equivalent to using the `.set' directive. *Note `.set': Set. -In the same way, using a double equals sign `='`=' here represents an -equivalent of the `.eqv' directive. *Note `.eqv': Eqv. +by an equals sign '=', followed by an expression (*note Expressions::). +This is equivalent to using the '.set' directive. *Note '.set': Set. +In the same way, using a double equals sign '=''=' here represents an +equivalent of the '.eqv' directive. *Note '.eqv': Eqv. - Blackfin does not support symbol assignment with `='. + Blackfin does not support symbol assignment with '='. File: as.info, Node: Symbol Names, Next: Dot, Prev: Setting Symbols, Up: Symbols @@ -2432,18 +2406,18 @@ File: as.info, Node: Symbol Names, Next: Dot, Prev: Setting Symbols, Up: Sym 5.3 Symbol Names ================ -Symbol names begin with a letter or with one of `._'. On most -machines, you can also use `$' in symbol names; exceptions are noted in -*note Machine Dependencies::. That character may be followed by any -string of digits, letters, dollar signs (unless otherwise noted for a -particular target machine), and underscores. +Symbol names begin with a letter or with one of '._'. On most machines, +you can also use '$' in symbol names; exceptions are noted in *note +Machine Dependencies::. That character may be followed by any string of +digits, letters, dollar signs (unless otherwise noted for a particular +target machine), and underscores. -Case of letters is significant: `foo' is a different symbol name than -`Foo'. + Case of letters is significant: 'foo' is a different symbol name than +'Foo'. Multibyte characters are supported. To generate a symbol name containing multibyte characters enclose it within double quotes and use -escape codes. cf *Note Strings::. Generating a multibyte symbol name +escape codes. cf *Note Strings::. Generating a multibyte symbol name from a label is not currently supported. Each symbol has exactly one name. Each name in an assembly language @@ -2454,36 +2428,36 @@ Local Symbol Names ------------------ A local symbol is any symbol beginning with certain local label -prefixes. By default, the local label prefix is `.L' for ELF systems or -`L' for traditional a.out systems, but each target may have its own set -of local label prefixes. On the HPPA local symbols begin with `L$'. +prefixes. By default, the local label prefix is '.L' for ELF systems or +'L' for traditional a.out systems, but each target may have its own set +of local label prefixes. On the HPPA local symbols begin with 'L$'. Local symbols are defined and used within the assembler, but they are normally not saved in object files. Thus, they are not visible when -debugging. You may use the `-L' option (*note Include Local Symbols: -`-L': L.) to retain the local symbols in the object files. +debugging. You may use the '-L' option (*note Include Local Symbols: +'-L': L.) to retain the local symbols in the object files. Local Labels ------------ -Local labels help compilers and programmers use names temporarily. -They create symbols which are guaranteed to be unique over the entire -scope of the input source code and which can be referred to by a simple -notation. To define a local label, write a label of the form `N:' +Local labels help compilers and programmers use names temporarily. They +create symbols which are guaranteed to be unique over the entire scope +of the input source code and which can be referred to by a simple +notation. To define a local label, write a label of the form 'N:' (where N represents any positive integer). To refer to the most recent -previous definition of that label write `Nb', using the same number as +previous definition of that label write 'Nb', using the same number as when you defined the label. To refer to the next definition of a local -label, write `Nf'--the `b' stands for "backwards" and the `f' stands -for "forwards". +label, write 'Nf'--the 'b' stands for "backwards" and the 'f' stands for +"forwards". There is no restriction on how you can use these labels, and you can reuse them too. So that it is possible to repeatedly define the same -local label (using the same number `N'), although you can only refer to +local label (using the same number 'N'), although you can only refer to the most recently defined local label of that number (for a backwards reference) or the next definition of a specific local label for a forward reference. It is also worth noting that the first 10 local -labels (`0:'...`9:') are implemented in a slightly more efficient -manner than the others. +labels ('0:'...'9:') are implemented in a slightly more efficient manner +than the others. Here is an example: @@ -2505,52 +2479,51 @@ uses them. The symbol names are stored in the symbol table, appear in error messages, and are optionally emitted to the object file. The names are constructed using these parts: -`_local label prefix_' +'_local label prefix_' All local symbols begin with the system-specific local label - prefix. Normally both `as' and `ld' forget symbols that start - with the local label prefix. These labels are used for symbols - you are never intended to see. If you use the `-L' option then - `as' retains these symbols in the object file. If you also - instruct `ld' to retain these symbols, you may use them in - debugging. - -`NUMBER' - This is the number that was used in the local label definition. - So if the label is written `55:' then the number is `55'. - -`C-B' + prefix. Normally both 'as' and 'ld' forget symbols that start with + the local label prefix. These labels are used for symbols you are + never intended to see. If you use the '-L' option then 'as' + retains these symbols in the object file. If you also instruct + 'ld' to retain these symbols, you may use them in debugging. + +'NUMBER' + This is the number that was used in the local label definition. So + if the label is written '55:' then the number is '55'. + +'C-B' This unusual character is included so you do not accidentally - invent a symbol of the same name. The character has ASCII value - of `\002' (control-B). + invent a symbol of the same name. The character has ASCII value of + '\002' (control-B). -`_ordinal number_' +'_ordinal number_' This is a serial number to keep the labels distinct. The first - definition of `0:' gets the number `1'. The 15th definition of - `0:' gets the number `15', and so on. Likewise the first - definition of `1:' gets the number `1' and its 15th definition - gets `15' as well. + definition of '0:' gets the number '1'. The 15th definition of + '0:' gets the number '15', and so on. Likewise the first + definition of '1:' gets the number '1' and its 15th definition gets + '15' as well. - So for example, the first `1:' may be named `.L1C-B1', and the 44th -`3:' may be named `.L3C-B44'. + So for example, the first '1:' may be named '.L1C-B1', and the 44th +'3:' may be named '.L3C-B44'. Dollar Local Labels ------------------- -`as' also supports an even more local form of local labels called -dollar labels. These labels go out of scope (i.e., they become -undefined) as soon as a non-local label is defined. Thus they remain -valid for only a small region of the input source code. Normal local -labels, by contrast, remain in scope for the entire file, or until they -are redefined by another occurrence of the same local label. +'as' also supports an even more local form of local labels called dollar +labels. These labels go out of scope (i.e., they become undefined) as +soon as a non-local label is defined. Thus they remain valid for only a +small region of the input source code. Normal local labels, by +contrast, remain in scope for the entire file, or until they are +redefined by another occurrence of the same local label. Dollar labels are defined in exactly the same way as ordinary local labels, except that they have a dollar sign suffix to their numeric -value, e.g., `55$:'. +value, e.g., '55$:'. They can also be distinguished from ordinary local labels by their -transformed names which use ASCII character `\001' (control-A) as the +transformed names which use ASCII character '\001' (control-A) as the magic character to distinguish them from ordinary labels. For example, -the fifth definition of `6$' may be named `.L6C-A5'. +the fifth definition of '6$' may be named '.L6'C-A'5'. File: as.info, Node: Dot, Next: Symbol Attributes, Prev: Symbol Names, Up: Symbols @@ -2558,11 +2531,11 @@ File: as.info, Node: Dot, Next: Symbol Attributes, Prev: Symbol Names, Up: S 5.4 The Special Dot Symbol ========================== -The special symbol `.' refers to the current address that `as' is -assembling into. Thus, the expression `melvin: .long .' defines -`melvin' to contain its own address. Assigning a value to `.' is -treated the same as a `.org' directive. Thus, the expression `.=.+4' -is the same as saying `.space 4'. +The special symbol '.' refers to the current address that 'as' is +assembling into. Thus, the expression 'melvin: .long .' defines +'melvin' to contain its own address. Assigning a value to '.' is +treated the same as a '.org' directive. Thus, the expression '.=.+4' is +the same as saying '.space 4'. File: as.info, Node: Symbol Attributes, Prev: Dot, Up: Symbols @@ -2574,20 +2547,16 @@ Every symbol has, as well as its name, the attributes "Value" and "Type". Depending on output format, symbols can also have auxiliary attributes. - If you use a symbol without defining it, `as' assumes zero for all -these attributes, and probably won't warn you. This makes the symbol -an externally defined symbol, which is generally what you would want. + If you use a symbol without defining it, 'as' assumes zero for all +these attributes, and probably won't warn you. This makes the symbol an +externally defined symbol, which is generally what you would want. * Menu: * Symbol Value:: Value * Symbol Type:: Type - - -* a.out Symbols:: Symbol Attributes: `a.out' - +* a.out Symbols:: Symbol Attributes: 'a.out' * COFF Symbols:: Symbol Attributes for COFF - * SOM Symbols:: Symbol Attributes for SOM @@ -2600,15 +2569,15 @@ The value of a symbol is (usually) 32 bits. For a symbol which labels a location in the text, data, bss or absolute sections the value is the number of addresses from the start of that section to the label. Naturally for text, data and bss sections the value of a symbol changes -as `ld' changes section base addresses during linking. Absolute +as 'ld' changes section base addresses during linking. Absolute symbols' values do not change during linking: that is why they are called absolute. The value of an undefined symbol is treated in a special way. If it is 0 then the symbol is not defined in this assembler source file, and -`ld' tries to determine its value from other files linked into the same +'ld' tries to determine its value from other files linked into the same program. You make this kind of symbol simply by mentioning a symbol -name without defining it. A non-zero value represents a `.comm' common +name without defining it. A non-zero value represents a '.comm' common declaration. The value is how much common storage to reserve, in bytes (addresses). The symbol refers to the first address of the allocated storage. @@ -2627,7 +2596,7 @@ format depends on the object-code output format in use. File: as.info, Node: a.out Symbols, Next: COFF Symbols, Prev: Symbol Type, Up: Symbol Attributes -5.5.3 Symbol Attributes: `a.out' +5.5.3 Symbol Attributes: 'a.out' -------------------------------- * Menu: @@ -2642,8 +2611,8 @@ File: as.info, Node: Symbol Desc, Next: Symbol Other, Up: a.out Symbols .................. This is an arbitrary 16-bit value. You may establish a symbol's -descriptor value by using a `.desc' statement (*note `.desc': Desc.). -A descriptor value means nothing to `as'. +descriptor value by using a '.desc' statement (*note '.desc': Desc.). A +descriptor value means nothing to 'as'. File: as.info, Node: Symbol Other, Prev: Symbol Desc, Up: a.out Symbols @@ -2651,7 +2620,7 @@ File: as.info, Node: Symbol Other, Prev: Symbol Desc, Up: a.out Symbols 5.5.3.2 Other ............. -This is an arbitrary 8-bit value. It means nothing to `as'. +This is an arbitrary 8-bit value. It means nothing to 'as'. File: as.info, Node: COFF Symbols, Next: SOM Symbols, Prev: a.out Symbols, Up: Symbol Attributes @@ -2660,20 +2629,20 @@ File: as.info, Node: COFF Symbols, Next: SOM Symbols, Prev: a.out Symbols, U -------------------------------- The COFF format supports a multitude of auxiliary symbol attributes; -like the primary symbol attributes, they are set between `.def' and -`.endef' directives. +like the primary symbol attributes, they are set between '.def' and +'.endef' directives. 5.5.4.1 Primary Attributes .......................... -The symbol name is set with `.def'; the value and type, respectively, -with `.val' and `.type'. +The symbol name is set with '.def'; the value and type, respectively, +with '.val' and '.type'. 5.5.4.2 Auxiliary Attributes ............................ -The `as' directives `.dim', `.line', `.scl', `.size', `.tag', and -`.weak' can generate auxiliary symbol table information for COFF. +The 'as' directives '.dim', '.line', '.scl', '.size', '.tag', and +'.weak' can generate auxiliary symbol table information for COFF. File: as.info, Node: SOM Symbols, Prev: COFF Symbols, Up: Symbol Attributes @@ -2682,10 +2651,10 @@ File: as.info, Node: SOM Symbols, Prev: COFF Symbols, Up: Symbol Attributes ------------------------------- The SOM format for the HPPA supports a multitude of symbol attributes -set with the `.EXPORT' and `.IMPORT' directives. +set with the '.EXPORT' and '.IMPORT' directives. - The attributes are described in `HP9000 Series 800 Assembly Language -Reference Manual' (HP 92432-90001) under the `IMPORT' and `EXPORT' + The attributes are described in 'HP9000 Series 800 Assembly Language +Reference Manual' (HP 92432-90001) under the 'IMPORT' and 'EXPORT' assembler directive documentation. @@ -2698,11 +2667,11 @@ An "expression" specifies an address or numeric value. Whitespace may precede and/or follow an expression. The result of an expression must be an absolute number, or else an -offset into a particular section. If an expression is not absolute, -and there is not enough information when `as' sees the expression to -know its section, a second pass over the source program might be -necessary to interpret the expression--but the second pass is currently -not implemented. `as' aborts with an error message in this situation. +offset into a particular section. If an expression is not absolute, and +there is not enough information when 'as' sees the expression to know +its section, a second pass over the source program might be necessary to +interpret the expression--but the second pass is currently not +implemented. 'as' aborts with an error message in this situation. * Menu: @@ -2717,7 +2686,7 @@ File: as.info, Node: Empty Exprs, Next: Integer Exprs, Up: Expressions An empty expression has no value: it is just whitespace or null. Wherever an absolute expression is required, you may omit the -expression, and `as' assumes a value of (absolute) 0. This is +expression, and 'as' assumes a value of (absolute) 0. This is compatible with other assemblers. @@ -2756,12 +2725,12 @@ complement 32 bit integer. Numbers are usually integers. A number can be a flonum or bignum. In this case, you are warned -that only the low order 32 bits are used, and `as' pretends these 32 +that only the low order 32 bits are used, and 'as' pretends these 32 bits are an integer. You may write integer-manipulating instructions that act on exotic constants, compatible with other assemblers. - Subexpressions are a left parenthesis `(' followed by an integer -expression, followed by a right parenthesis `)'; or a prefix operator + Subexpressions are a left parenthesis '(' followed by an integer +expression, followed by a right parenthesis ')'; or a prefix operator followed by an argument. @@ -2770,10 +2739,9 @@ File: as.info, Node: Operators, Next: Prefix Ops, Prev: Arguments, Up: Integ 6.2.2 Operators --------------- -"Operators" are arithmetic functions, like `+' or `%'. Prefix -operators are followed by an argument. Infix operators appear between -their arguments. Operators may be preceded and/or followed by -whitespace. +"Operators" are arithmetic functions, like '+' or '%'. Prefix operators +are followed by an argument. Infix operators appear between their +arguments. Operators may be preceded and/or followed by whitespace. File: as.info, Node: Prefix Ops, Next: Infix Ops, Prev: Operators, Up: Integer Exprs @@ -2781,13 +2749,12 @@ File: as.info, Node: Prefix Ops, Next: Infix Ops, Prev: Operators, Up: Integ 6.2.3 Prefix Operator --------------------- -`as' has the following "prefix operators". They each take one -argument, which must be absolute. +'as' has the following "prefix operators". They each take one argument, +which must be absolute. -`-' +'-' "Negation". Two's complement negation. - -`~' +'~' "Complementation". Bitwise not. @@ -2798,83 +2765,78 @@ File: as.info, Node: Infix Ops, Prev: Prefix Ops, Up: Integer Exprs "Infix operators" take two arguments, one on either side. Operators have precedence, but operations with equal precedence are performed left -to right. Apart from `+' or `-', both arguments must be absolute, and +to right. Apart from '+' or '-', both arguments must be absolute, and the result is absolute. 1. Highest Precedence - `*' + '*' "Multiplication". - `/' - "Division". Truncation is the same as the C operator `/' + '/' + "Division". Truncation is the same as the C operator '/' - `%' + '%' "Remainder". - `<<' - "Shift Left". Same as the C operator `<<'. + '<<' + "Shift Left". Same as the C operator '<<'. - `>>' - "Shift Right". Same as the C operator `>>'. + '>>' + "Shift Right". Same as the C operator '>>'. 2. Intermediate precedence - `|' + '|' + "Bitwise Inclusive Or". - `&' + '&' "Bitwise And". - `^' + '^' "Bitwise Exclusive Or". - `!' + '!' "Bitwise Or Not". 3. Low Precedence - `+' + '+' "Addition". If either argument is absolute, the result has the section of the other argument. You may not add together arguments from different sections. - `-' + '-' "Subtraction". If the right argument is absolute, the result has the section of the left argument. If both arguments are in the same section, the result is absolute. You may not subtract arguments from different sections. - `==' + '==' "Is Equal To" - - `<>' - `!=' + '<>' + '!=' "Is Not Equal To" - - `<' + '<' "Is Less Than" - - `>' + '>' "Is Greater Than" - - `>=' + '>=' "Is Greater Than Or Equal To" - - `<=' + '<=' "Is Less Than Or Equal To" The comparison operators can be used as infix operators. A true results has a value of -1 whereas a false result has a - value of 0. Note, these operators perform signed - comparisons. + value of 0. Note, these operators perform signed comparisons. 4. Lowest Precedence - `&&' + '&&' "Logical And". - `||' + '||' "Logical Or". These two logical operations can be used to combine the @@ -2883,7 +2845,6 @@ the result is absolute. results does still return 0. Also note that the logical or operator has a slightly lower precedence than logical and. - In short, it's only meaningful to add or subtract the _offsets_ in an address; you can only have a defined section in one of the two arguments. @@ -2894,8 +2855,8 @@ File: as.info, Node: Pseudo Ops, Next: Object Attributes, Prev: Expressions, 7 Assembler Directives ********************** -All assembler directives have names that begin with a period (`.'). -The rest of the name is letters, usually in lower case. +All assembler directives have names that begin with a period ('.'). The +rest of the name is letters, usually in lower case. This chapter discusses directives that are available regardless of the target machine configuration for the GNU assembler. Some machine @@ -2904,179 +2865,155 @@ Dependencies::. * Menu: -* Abort:: `.abort' - -* ABORT (COFF):: `.ABORT' - -* Align:: `.align ABS-EXPR , ABS-EXPR' -* Altmacro:: `.altmacro' -* Ascii:: `.ascii "STRING"'... -* Asciz:: `.asciz "STRING"'... -* Balign:: `.balign ABS-EXPR , ABS-EXPR' -* Bundle directives:: `.bundle_align_mode ABS-EXPR', `.bundle_lock', `.bundle_unlock' -* Byte:: `.byte EXPRESSIONS' -* CFI directives:: `.cfi_startproc [simple]', `.cfi_endproc', etc. -* Comm:: `.comm SYMBOL , LENGTH ' -* Data:: `.data SUBSECTION' - -* Def:: `.def NAME' - -* Desc:: `.desc SYMBOL, ABS-EXPRESSION' - -* Dim:: `.dim' - -* Double:: `.double FLONUMS' -* Eject:: `.eject' -* Else:: `.else' -* Elseif:: `.elseif' -* End:: `.end' - -* Endef:: `.endef' - -* Endfunc:: `.endfunc' -* Endif:: `.endif' -* Equ:: `.equ SYMBOL, EXPRESSION' -* Equiv:: `.equiv SYMBOL, EXPRESSION' -* Eqv:: `.eqv SYMBOL, EXPRESSION' -* Err:: `.err' -* Error:: `.error STRING' -* Exitm:: `.exitm' -* Extern:: `.extern' -* Fail:: `.fail' -* File:: `.file' -* Fill:: `.fill REPEAT , SIZE , VALUE' -* Float:: `.float FLONUMS' -* Func:: `.func' -* Global:: `.global SYMBOL', `.globl SYMBOL' - -* Gnu_attribute:: `.gnu_attribute TAG,VALUE' -* Hidden:: `.hidden NAMES' - -* hword:: `.hword EXPRESSIONS' -* Ident:: `.ident' -* If:: `.if ABSOLUTE EXPRESSION' -* Incbin:: `.incbin "FILE"[,SKIP[,COUNT]]' -* Include:: `.include "FILE"' -* Int:: `.int EXPRESSIONS' - -* Internal:: `.internal NAMES' - -* Irp:: `.irp SYMBOL,VALUES'... -* Irpc:: `.irpc SYMBOL,VALUES'... -* Lcomm:: `.lcomm SYMBOL , LENGTH' -* Lflags:: `.lflags' - -* Line:: `.line LINE-NUMBER' - -* Linkonce:: `.linkonce [TYPE]' -* List:: `.list' -* Ln:: `.ln LINE-NUMBER' -* Loc:: `.loc FILENO LINENO' -* Loc_mark_labels:: `.loc_mark_labels ENABLE' - -* Local:: `.local NAMES' - -* Long:: `.long EXPRESSIONS' - -* Macro:: `.macro NAME ARGS'... -* MRI:: `.mri VAL' -* Noaltmacro:: `.noaltmacro' -* Nolist:: `.nolist' -* Octa:: `.octa BIGNUMS' -* Offset:: `.offset LOC' -* Org:: `.org NEW-LC, FILL' -* P2align:: `.p2align ABS-EXPR, ABS-EXPR, ABS-EXPR' - -* PopSection:: `.popsection' -* Previous:: `.previous' - -* Print:: `.print STRING' - -* Protected:: `.protected NAMES' -* Secondary:: `.secondary NAMES' - -* Psize:: `.psize LINES, COLUMNS' -* Purgem:: `.purgem NAME' - -* PushSection:: `.pushsection NAME' - -* Quad:: `.quad BIGNUMS' -* Reloc:: `.reloc OFFSET, RELOC_NAME[, EXPRESSION]' -* Rept:: `.rept COUNT' -* Sbttl:: `.sbttl "SUBHEADING"' - -* Scl:: `.scl CLASS' - -* Section:: `.section NAME[, FLAGS]' - -* Set:: `.set SYMBOL, EXPRESSION' -* Short:: `.short EXPRESSIONS' -* Single:: `.single FLONUMS' - -* Size:: `.size [NAME , EXPRESSION]' - -* Skip:: `.skip SIZE , FILL' - -* Sleb128:: `.sleb128 EXPRESSIONS' - -* Space:: `.space SIZE , FILL' - -* Stab:: `.stabd, .stabn, .stabs' - -* String:: `.string "STR"', `.string8 "STR"', `.string16 "STR"', `.string32 "STR"', `.string64 "STR"' -* Struct:: `.struct EXPRESSION' - -* SubSection:: `.subsection' -* Symver:: `.symver NAME,NAME2@NODENAME' - - -* Tag:: `.tag STRUCTNAME' - -* Text:: `.text SUBSECTION' -* Title:: `.title "HEADING"' - -* Type:: `.type <INT | NAME , TYPE DESCRIPTION>' - -* Uleb128:: `.uleb128 EXPRESSIONS' - -* Val:: `.val ADDR' - - -* Version:: `.version "STRING"' -* VTableEntry:: `.vtable_entry TABLE, OFFSET' -* VTableInherit:: `.vtable_inherit CHILD, PARENT' - -* Warning:: `.warning STRING' -* Weak:: `.weak NAMES' -* Weakref:: `.weakref ALIAS, SYMBOL' -* Word:: `.word EXPRESSIONS' +* Abort:: '.abort' +* ABORT (COFF):: '.ABORT' + +* Align:: '.align ABS-EXPR , ABS-EXPR' +* Altmacro:: '.altmacro' +* Ascii:: '.ascii "STRING"'... +* Asciz:: '.asciz "STRING"'... +* Balign:: '.balign ABS-EXPR , ABS-EXPR' +* Bundle directives:: '.bundle_align_mode ABS-EXPR', '.bundle_lock', '.bundle_unlock' +* Byte:: '.byte EXPRESSIONS' +* CFI directives:: '.cfi_startproc [simple]', '.cfi_endproc', etc. +* Comm:: '.comm SYMBOL , LENGTH ' +* Data:: '.data SUBSECTION' +* Def:: '.def NAME' +* Desc:: '.desc SYMBOL, ABS-EXPRESSION' +* Dim:: '.dim' + +* Double:: '.double FLONUMS' +* Eject:: '.eject' +* Else:: '.else' +* Elseif:: '.elseif' +* End:: '.end' +* Endef:: '.endef' + +* Endfunc:: '.endfunc' +* Endif:: '.endif' +* Equ:: '.equ SYMBOL, EXPRESSION' +* Equiv:: '.equiv SYMBOL, EXPRESSION' +* Eqv:: '.eqv SYMBOL, EXPRESSION' +* Err:: '.err' +* Error:: '.error STRING' +* Exitm:: '.exitm' +* Extern:: '.extern' +* Fail:: '.fail' +* File:: '.file' +* Fill:: '.fill REPEAT , SIZE , VALUE' +* Float:: '.float FLONUMS' +* Func:: '.func' +* Global:: '.global SYMBOL', '.globl SYMBOL' +* Gnu_attribute:: '.gnu_attribute TAG,VALUE' +* Hidden:: '.hidden NAMES' + +* hword:: '.hword EXPRESSIONS' +* Ident:: '.ident' +* If:: '.if ABSOLUTE EXPRESSION' +* Incbin:: '.incbin "FILE"[,SKIP[,COUNT]]' +* Include:: '.include "FILE"' +* Int:: '.int EXPRESSIONS' +* Internal:: '.internal NAMES' + +* Irp:: '.irp SYMBOL,VALUES'... +* Irpc:: '.irpc SYMBOL,VALUES'... +* Lcomm:: '.lcomm SYMBOL , LENGTH' +* Lflags:: '.lflags' +* Line:: '.line LINE-NUMBER' + +* Linkonce:: '.linkonce [TYPE]' +* List:: '.list' +* Ln:: '.ln LINE-NUMBER' +* Loc:: '.loc FILENO LINENO' +* Loc_mark_labels:: '.loc_mark_labels ENABLE' +* Local:: '.local NAMES' + +* Long:: '.long EXPRESSIONS' + +* Macro:: '.macro NAME ARGS'... +* MRI:: '.mri VAL' +* Noaltmacro:: '.noaltmacro' +* Nolist:: '.nolist' +* Octa:: '.octa BIGNUMS' +* Offset:: '.offset LOC' +* Org:: '.org NEW-LC, FILL' +* P2align:: '.p2align ABS-EXPR, ABS-EXPR, ABS-EXPR' +* PopSection:: '.popsection' +* Previous:: '.previous' + +* Print:: '.print STRING' +* Protected:: '.protected NAMES' + +* Psize:: '.psize LINES, COLUMNS' +* Purgem:: '.purgem NAME' +* PushSection:: '.pushsection NAME' + +* Quad:: '.quad BIGNUMS' +* Reloc:: '.reloc OFFSET, RELOC_NAME[, EXPRESSION]' +* Rept:: '.rept COUNT' +* Sbttl:: '.sbttl "SUBHEADING"' +* Scl:: '.scl CLASS' +* Section:: '.section NAME[, FLAGS]' + +* Set:: '.set SYMBOL, EXPRESSION' +* Short:: '.short EXPRESSIONS' +* Single:: '.single FLONUMS' +* Size:: '.size [NAME , EXPRESSION]' +* Skip:: '.skip SIZE , FILL' + +* Sleb128:: '.sleb128 EXPRESSIONS' +* Space:: '.space SIZE , FILL' +* Stab:: '.stabd, .stabn, .stabs' + +* String:: '.string "STR"', '.string8 "STR"', '.string16 "STR"', '.string32 "STR"', '.string64 "STR"' +* Struct:: '.struct EXPRESSION' +* SubSection:: '.subsection' +* Symver:: '.symver NAME,NAME2@NODENAME' + +* Tag:: '.tag STRUCTNAME' + +* Text:: '.text SUBSECTION' +* Title:: '.title "HEADING"' +* Type:: '.type <INT | NAME , TYPE DESCRIPTION>' + +* Uleb128:: '.uleb128 EXPRESSIONS' +* Val:: '.val ADDR' + +* Version:: '.version "STRING"' +* VTableEntry:: '.vtable_entry TABLE, OFFSET' +* VTableInherit:: '.vtable_inherit CHILD, PARENT' + +* Warning:: '.warning STRING' +* Weak:: '.weak NAMES' +* Weakref:: '.weakref ALIAS, SYMBOL' +* Word:: '.word EXPRESSIONS' * Deprecated:: Deprecated Directives File: as.info, Node: Abort, Next: ABORT (COFF), Up: Pseudo Ops -7.1 `.abort' +7.1 '.abort' ============ This directive stops the assembly immediately. It is for compatibility -with other assemblers. The original idea was that the assembly -language source would be piped into the assembler. If the sender of -the source quit, it could use this directive tells `as' to quit also. -One day `.abort' will not be supported. +with other assemblers. The original idea was that the assembly language +source would be piped into the assembler. If the sender of the source +quit, it could use this directive tells 'as' to quit also. One day +'.abort' will not be supported. File: as.info, Node: ABORT (COFF), Next: Align, Prev: Abort, Up: Pseudo Ops -7.2 `.ABORT' (COFF) +7.2 '.ABORT' (COFF) =================== -When producing COFF output, `as' accepts this directive as a synonym -for `.abort'. +When producing COFF output, 'as' accepts this directive as a synonym for +'.abort'. File: as.info, Node: Align, Next: Altmacro, Prev: ABORT (COFF), Up: Pseudo Ops -7.3 `.align ABS-EXPR, ABS-EXPR, ABS-EXPR' +7.3 '.align ABS-EXPR, ABS-EXPR, ABS-EXPR' ========================================= Pad the location counter (in the current subsection) to a particular @@ -3091,99 +3028,99 @@ is omitted, the space is filled with no-op instructions. The third expression is also absolute, and is also optional. If it is present, it is the maximum number of bytes that should be skipped by -this alignment directive. If doing the alignment would require -skipping more bytes than the specified maximum, then the alignment is -not done at all. You can omit the fill value (the second argument) -entirely by simply using two commas after the required alignment; this -can be useful if you want the alignment to be filled with no-op -instructions when appropriate. +this alignment directive. If doing the alignment would require skipping +more bytes than the specified maximum, then the alignment is not done at +all. You can omit the fill value (the second argument) entirely by +simply using two commas after the required alignment; this can be useful +if you want the alignment to be filled with no-op instructions when +appropriate. The way the required alignment is specified varies from system to system. For the arc, hppa, i386 using ELF, i860, iq2000, m68k, or32, s390, sparc, tic4x, tic80 and xtensa, the first expression is the -alignment request in bytes. For example `.align 8' advances the +alignment request in bytes. For example '.align 8' advances the location counter until it is a multiple of 8. If the location counter is already a multiple of 8, no change is needed. For the tic54x, the first expression is the alignment request in words. For other systems, including ppc, i386 using a.out format, arm and strongarm, it is the number of low-order zero bits the location counter -must have after advancement. For example `.align 3' advances the +must have after advancement. For example '.align 3' advances the location counter until it a multiple of 8. If the location counter is already a multiple of 8, no change is needed. This inconsistency is due to the different behaviors of the various native assemblers for these systems which GAS must emulate. GAS also -provides `.balign' and `.p2align' directives, described later, which -have a consistent behavior across all architectures (but are specific -to GAS). +provides '.balign' and '.p2align' directives, described later, which +have a consistent behavior across all architectures (but are specific to +GAS). File: as.info, Node: Altmacro, Next: Ascii, Prev: Align, Up: Pseudo Ops -7.4 `.altmacro' +7.4 '.altmacro' =============== Enable alternate macro mode, enabling: -`LOCAL NAME [ , ... ]' - One additional directive, `LOCAL', is available. It is used to +'LOCAL NAME [ , ... ]' + One additional directive, 'LOCAL', is available. It is used to generate a string replacement for each of the NAME arguments, and replace any instances of NAME in each macro expansion. The replacement string is unique in the assembly, and different for - each separate macro expansion. `LOCAL' allows you to write macros + each separate macro expansion. 'LOCAL' allows you to write macros that define symbols, without fear of conflict between separate macro expansions. -`String delimiters' +'String delimiters' You can write strings delimited in these other ways besides - `"STRING"': + '"STRING"': - `'STRING'' + ''STRING'' You can delimit strings with single-quote characters. - `<STRING>' + '<STRING>' You can delimit strings with matching angle brackets. -`single-character string escape' +'single-character string escape' To include any single character literally in a string (even if the character would otherwise have some special meaning), you can - prefix the character with `!' (an exclamation mark). For example, - you can write `<4.3 !> 5.4!!>' to get the literal text `4.3 > + prefix the character with '!' (an exclamation mark). For example, + you can write '<4.3 !> 5.4!!>' to get the literal text '4.3 > 5.4!'. -`Expression results as strings' - You can write `%EXPR' to evaluate the expression EXPR and use the +'Expression results as strings' + You can write '%EXPR' to evaluate the expression EXPR and use the result as a string. File: as.info, Node: Ascii, Next: Asciz, Prev: Altmacro, Up: Pseudo Ops -7.5 `.ascii "STRING"'... +7.5 '.ascii "STRING"'... ======================== -`.ascii' expects zero or more string literals (*note Strings::) +'.ascii' expects zero or more string literals (*note Strings::) separated by commas. It assembles each string (with no automatic trailing zero byte) into consecutive addresses. File: as.info, Node: Asciz, Next: Balign, Prev: Ascii, Up: Pseudo Ops -7.6 `.asciz "STRING"'... +7.6 '.asciz "STRING"'... ======================== -`.asciz' is just like `.ascii', but each string is followed by a zero -byte. The "z" in `.asciz' stands for "zero". +'.asciz' is just like '.ascii', but each string is followed by a zero +byte. The "z" in '.asciz' stands for "zero". File: as.info, Node: Balign, Next: Bundle directives, Prev: Asciz, Up: Pseudo Ops -7.7 `.balign[wl] ABS-EXPR, ABS-EXPR, ABS-EXPR' +7.7 '.balign[wl] ABS-EXPR, ABS-EXPR, ABS-EXPR' ============================================== Pad the location counter (in the current subsection) to a particular storage boundary. The first expression (which must be absolute) is the -alignment request in bytes. For example `.balign 8' advances the +alignment request in bytes. For example '.balign 8' advances the location counter until it is a multiple of 8. If the location counter is already a multiple of 8, no change is needed. @@ -3195,234 +3132,234 @@ is omitted, the space is filled with no-op instructions. The third expression is also absolute, and is also optional. If it is present, it is the maximum number of bytes that should be skipped by -this alignment directive. If doing the alignment would require -skipping more bytes than the specified maximum, then the alignment is -not done at all. You can omit the fill value (the second argument) -entirely by simply using two commas after the required alignment; this -can be useful if you want the alignment to be filled with no-op -instructions when appropriate. - - The `.balignw' and `.balignl' directives are variants of the -`.balign' directive. The `.balignw' directive treats the fill pattern -as a two byte word value. The `.balignl' directives treats the fill -pattern as a four byte longword value. For example, `.balignw -4,0x368d' will align to a multiple of 4. If it skips two bytes, they -will be filled in with the value 0x368d (the exact placement of the -bytes depends upon the endianness of the processor). If it skips 1 or -3 bytes, the fill value is undefined. +this alignment directive. If doing the alignment would require skipping +more bytes than the specified maximum, then the alignment is not done at +all. You can omit the fill value (the second argument) entirely by +simply using two commas after the required alignment; this can be useful +if you want the alignment to be filled with no-op instructions when +appropriate. + + The '.balignw' and '.balignl' directives are variants of the +'.balign' directive. The '.balignw' directive treats the fill pattern +as a two byte word value. The '.balignl' directives treats the fill +pattern as a four byte longword value. For example, '.balignw 4,0x368d' +will align to a multiple of 4. If it skips two bytes, they will be +filled in with the value 0x368d (the exact placement of the bytes +depends upon the endianness of the processor). If it skips 1 or 3 +bytes, the fill value is undefined. File: as.info, Node: Bundle directives, Next: Byte, Prev: Balign, Up: Pseudo Ops -7.8 `.bundle_align_mode ABS-EXPR' +7.8 '.bundle_align_mode ABS-EXPR' ================================= -`.bundle_align_mode' enables or disables "aligned instruction bundle" -mode. In this mode, sequences of adjacent instructions are grouped -into fixed-sized "bundles". If the argument is zero, this mode is -disabled (which is the default state). If the argument it not zero, it -gives the size of an instruction bundle as a power of two (as for the -`.p2align' directive, *note P2align::). +'.bundle_align_mode' enables or disables "aligned instruction bundle" +mode. In this mode, sequences of adjacent instructions are grouped into +fixed-sized "bundles". If the argument is zero, this mode is disabled +(which is the default state). If the argument it not zero, it gives the +size of an instruction bundle as a power of two (as for the '.p2align' +directive, *note P2align::). For some targets, it's an ABI requirement that no instruction may span a certain aligned boundary. A "bundle" is simply a sequence of instructions that starts on an aligned boundary. For example, if -ABS-EXPR is `5' then the bundle size is 32, so each aligned chunk of 32 +ABS-EXPR is '5' then the bundle size is 32, so each aligned chunk of 32 bytes is a bundle. When aligned instruction bundle mode is in effect, no single instruction may span a boundary between bundles. If an instruction would start too close to the end of a bundle for the length of that particular instruction to fit within the bundle, then the space at the end of that bundle is filled with no-op instructions so the -instruction starts in the next bundle. As a corollary, it's an error -if any single instruction's encoding is longer than the bundle size. +instruction starts in the next bundle. As a corollary, it's an error if +any single instruction's encoding is longer than the bundle size. -7.9 `.bundle_lock' and `.bundle_unlock' +7.9 '.bundle_lock' and '.bundle_unlock' ======================================= -The `.bundle_lock' and directive `.bundle_unlock' directives allow +The '.bundle_lock' and directive '.bundle_unlock' directives allow explicit control over instruction bundle padding. These directives are -only valid when `.bundle_align_mode' has been used to enable aligned +only valid when '.bundle_align_mode' has been used to enable aligned instruction bundle mode. It's an error if they appear when -`.bundle_align_mode' has not been used at all, or when the last -directive was `.bundle_align_mode 0'. +'.bundle_align_mode' has not been used at all, or when the last +directive was '.bundle_align_mode 0'. For some targets, it's an ABI requirement that certain instructions may appear only as part of specified permissible sequences of multiple -instructions, all within the same bundle. A pair of `.bundle_lock' and -`.bundle_unlock' directives define a "bundle-locked" instruction +instructions, all within the same bundle. A pair of '.bundle_lock' and +'.bundle_unlock' directives define a "bundle-locked" instruction sequence. For purposes of aligned instruction bundle mode, a sequence -starting with `.bundle_lock' and ending with `.bundle_unlock' is -treated as a single instruction. That is, the entire sequence must fit -into a single bundle and may not span a bundle boundary. If necessary, -no-op instructions will be inserted before the first instruction of the +starting with '.bundle_lock' and ending with '.bundle_unlock' is treated +as a single instruction. That is, the entire sequence must fit into a +single bundle and may not span a bundle boundary. If necessary, no-op +instructions will be inserted before the first instruction of the sequence so that the whole sequence starts on an aligned bundle boundary. It's an error if the sequence is longer than the bundle size. - For convenience when using `.bundle_lock' and `.bundle_unlock' -inside assembler macros (*note Macro::), bundle-locked sequences may be -nested. That is, a second `.bundle_lock' directive before the next -`.bundle_unlock' directive has no effect except that it must be matched -by another closing `.bundle_unlock' so that there is the same number of -`.bundle_lock' and `.bundle_unlock' directives. + For convenience when using '.bundle_lock' and '.bundle_unlock' inside +assembler macros (*note Macro::), bundle-locked sequences may be nested. +That is, a second '.bundle_lock' directive before the next +'.bundle_unlock' directive has no effect except that it must be matched +by another closing '.bundle_unlock' so that there is the same number of +'.bundle_lock' and '.bundle_unlock' directives. File: as.info, Node: Byte, Next: CFI directives, Prev: Bundle directives, Up: Pseudo Ops -7.10 `.byte EXPRESSIONS' +7.10 '.byte EXPRESSIONS' ======================== -`.byte' expects zero or more expressions, separated by commas. Each +'.byte' expects zero or more expressions, separated by commas. Each expression is assembled into the next byte. File: as.info, Node: CFI directives, Next: Comm, Prev: Byte, Up: Pseudo Ops -7.11 `.cfi_sections SECTION_LIST' +7.11 '.cfi_sections SECTION_LIST' ================================= -`.cfi_sections' may be used to specify whether CFI directives should -emit `.eh_frame' section and/or `.debug_frame' section. If -SECTION_LIST is `.eh_frame', `.eh_frame' is emitted, if SECTION_LIST is -`.debug_frame', `.debug_frame' is emitted. To emit both use -`.eh_frame, .debug_frame'. The default if this directive is not used -is `.cfi_sections .eh_frame'. +'.cfi_sections' may be used to specify whether CFI directives should +emit '.eh_frame' section and/or '.debug_frame' section. If SECTION_LIST +is '.eh_frame', '.eh_frame' is emitted, if SECTION_LIST is +'.debug_frame', '.debug_frame' is emitted. To emit both use '.eh_frame, +.debug_frame'. The default if this directive is not used is +'.cfi_sections .eh_frame'. -7.12 `.cfi_startproc [simple]' +7.12 '.cfi_startproc [simple]' ============================== -`.cfi_startproc' is used at the beginning of each function that should -have an entry in `.eh_frame'. It initializes some internal data -structures. Don't forget to close the function by `.cfi_endproc'. +'.cfi_startproc' is used at the beginning of each function that should +have an entry in '.eh_frame'. It initializes some internal data +structures. Don't forget to close the function by '.cfi_endproc'. - Unless `.cfi_startproc' is used along with parameter `simple' it -also emits some architecture dependent initial CFI instructions. + Unless '.cfi_startproc' is used along with parameter 'simple' it also +emits some architecture dependent initial CFI instructions. -7.13 `.cfi_endproc' +7.13 '.cfi_endproc' =================== -`.cfi_endproc' is used at the end of a function where it closes its -unwind entry previously opened by `.cfi_startproc', and emits it to -`.eh_frame'. +'.cfi_endproc' is used at the end of a function where it closes its +unwind entry previously opened by '.cfi_startproc', and emits it to +'.eh_frame'. -7.14 `.cfi_personality ENCODING [, EXP]' +7.14 '.cfi_personality ENCODING [, EXP]' ======================================== -`.cfi_personality' defines personality routine and its encoding. +'.cfi_personality' defines personality routine and its encoding. ENCODING must be a constant determining how the personality should be -encoded. If it is 255 (`DW_EH_PE_omit'), second argument is not +encoded. If it is 255 ('DW_EH_PE_omit'), second argument is not present, otherwise second argument should be a constant or a symbol name. When using indirect encodings, the symbol provided should be the location where personality can be loaded from, not the personality -routine itself. The default after `.cfi_startproc' is -`.cfi_personality 0xff', no personality routine. +routine itself. The default after '.cfi_startproc' is '.cfi_personality +0xff', no personality routine. -7.15 `.cfi_lsda ENCODING [, EXP]' +7.15 '.cfi_lsda ENCODING [, EXP]' ================================= -`.cfi_lsda' defines LSDA and its encoding. ENCODING must be a constant +'.cfi_lsda' defines LSDA and its encoding. ENCODING must be a constant determining how the LSDA should be encoded. If it is 255 -(`DW_EH_PE_omit'), second argument is not present, otherwise second +('DW_EH_PE_omit'), second argument is not present, otherwise second argument should be a constant or a symbol name. The default after -`.cfi_startproc' is `.cfi_lsda 0xff', no LSDA. +'.cfi_startproc' is '.cfi_lsda 0xff', no LSDA. -7.16 `.cfi_def_cfa REGISTER, OFFSET' +7.16 '.cfi_def_cfa REGISTER, OFFSET' ==================================== -`.cfi_def_cfa' defines a rule for computing CFA as: take address from +'.cfi_def_cfa' defines a rule for computing CFA as: take address from REGISTER and add OFFSET to it. -7.17 `.cfi_def_cfa_register REGISTER' +7.17 '.cfi_def_cfa_register REGISTER' ===================================== -`.cfi_def_cfa_register' modifies a rule for computing CFA. From now on -REGISTER will be used instead of the old one. Offset remains the same. +'.cfi_def_cfa_register' modifies a rule for computing CFA. From now on +REGISTER will be used instead of the old one. Offset remains the same. -7.18 `.cfi_def_cfa_offset OFFSET' +7.18 '.cfi_def_cfa_offset OFFSET' ================================= -`.cfi_def_cfa_offset' modifies a rule for computing CFA. Register -remains the same, but OFFSET is new. Note that it is the absolute +'.cfi_def_cfa_offset' modifies a rule for computing CFA. Register +remains the same, but OFFSET is new. Note that it is the absolute offset that will be added to a defined register to compute CFA address. -7.19 `.cfi_adjust_cfa_offset OFFSET' +7.19 '.cfi_adjust_cfa_offset OFFSET' ==================================== -Same as `.cfi_def_cfa_offset' but OFFSET is a relative value that is +Same as '.cfi_def_cfa_offset' but OFFSET is a relative value that is added/substracted from the previous offset. -7.20 `.cfi_offset REGISTER, OFFSET' +7.20 '.cfi_offset REGISTER, OFFSET' =================================== Previous value of REGISTER is saved at offset OFFSET from CFA. -7.21 `.cfi_rel_offset REGISTER, OFFSET' +7.21 '.cfi_rel_offset REGISTER, OFFSET' ======================================= Previous value of REGISTER is saved at offset OFFSET from the current -CFA register. This is transformed to `.cfi_offset' using the known -displacement of the CFA register from the CFA. This is often easier to +CFA register. This is transformed to '.cfi_offset' using the known +displacement of the CFA register from the CFA. This is often easier to use, because the number will match the code it's annotating. -7.22 `.cfi_register REGISTER1, REGISTER2' +7.22 '.cfi_register REGISTER1, REGISTER2' ========================================= Previous value of REGISTER1 is saved in register REGISTER2. -7.23 `.cfi_restore REGISTER' +7.23 '.cfi_restore REGISTER' ============================ -`.cfi_restore' says that the rule for REGISTER is now the same as it -was at the beginning of the function, after all initial instruction -added by `.cfi_startproc' were executed. +'.cfi_restore' says that the rule for REGISTER is now the same as it was +at the beginning of the function, after all initial instruction added by +'.cfi_startproc' were executed. -7.24 `.cfi_undefined REGISTER' +7.24 '.cfi_undefined REGISTER' ============================== From now on the previous value of REGISTER can't be restored anymore. -7.25 `.cfi_same_value REGISTER' +7.25 '.cfi_same_value REGISTER' =============================== Current value of REGISTER is the same like in the previous frame, i.e. no restoration needed. -7.26 `.cfi_remember_state', +7.26 '.cfi_remember_state', =========================== -First save all current rules for all registers by `.cfi_remember_state', -then totally screw them up by subsequent `.cfi_*' directives and when -everything is hopelessly bad, use `.cfi_restore_state' to restore the +First save all current rules for all registers by '.cfi_remember_state', +then totally screw them up by subsequent '.cfi_*' directives and when +everything is hopelessly bad, use '.cfi_restore_state' to restore the previous saved state. -7.27 `.cfi_return_column REGISTER' +7.27 '.cfi_return_column REGISTER' ================================== -Change return column REGISTER, i.e. the return address is either +Change return column REGISTER, i.e. the return address is either directly in REGISTER or can be accessed by rules for REGISTER. -7.28 `.cfi_signal_frame' +7.28 '.cfi_signal_frame' ======================== Mark current function as signal trampoline. -7.29 `.cfi_window_save' +7.29 '.cfi_window_save' ======================= SPARC register window has been saved. -7.30 `.cfi_escape' EXPRESSION[, ...] +7.30 '.cfi_escape' EXPRESSION[, ...] ==================================== Allows the user to add arbitrary bytes to the unwind info. One might -use this to add OS-specific CFI opcodes, or generic CFI opcodes that -GAS does not yet support. +use this to add OS-specific CFI opcodes, or generic CFI opcodes that GAS +does not yet support. -7.31 `.cfi_val_encoded_addr REGISTER, ENCODING, LABEL' +7.31 '.cfi_val_encoded_addr REGISTER, ENCODING, LABEL' ====================================================== The current value of REGISTER is LABEL. The value of LABEL will be -encoded in the output file according to ENCODING; see the description -of `.cfi_personality' for details on this encoding. +encoded in the output file according to ENCODING; see the description of +'.cfi_personality' for details on this encoding. The usefulness of equating a register to a fixed label is probably limited to the return address register. Here, it can be useful to mark @@ -3433,101 +3370,101 @@ another register. File: as.info, Node: Comm, Next: Data, Prev: CFI directives, Up: Pseudo Ops -7.32 `.comm SYMBOL , LENGTH ' +7.32 '.comm SYMBOL , LENGTH ' ============================= -`.comm' declares a common symbol named SYMBOL. When linking, a common +'.comm' declares a common symbol named SYMBOL. When linking, a common symbol in one object file may be merged with a defined or common symbol -of the same name in another object file. If `ld' does not see a +of the same name in another object file. If 'ld' does not see a definition for the symbol-just one or more common symbols-then it will allocate LENGTH bytes of uninitialized memory. LENGTH must be an -absolute expression. If `ld' sees multiple common symbols with the -same name, and they do not all have the same size, it will allocate -space using the largest size. +absolute expression. If 'ld' sees multiple common symbols with the same +name, and they do not all have the same size, it will allocate space +using the largest size. - When using ELF or (as a GNU extension) PE, the `.comm' directive + When using ELF or (as a GNU extension) PE, the '.comm' directive takes an optional third argument. This is the desired alignment of the symbol, specified for ELF as a byte boundary (for example, an alignment of 16 means that the least significant 4 bits of the address should be zero), and for PE as a power of two (for example, an alignment of 5 -means aligned to a 32-byte boundary). The alignment must be an -absolute expression, and it must be a power of two. If `ld' allocates +means aligned to a 32-byte boundary). The alignment must be an absolute +expression, and it must be a power of two. If 'ld' allocates uninitialized memory for the common symbol, it will use the alignment -when placing the symbol. If no alignment is specified, `as' will set -the alignment to the largest power of two less than or equal to the -size of the symbol, up to a maximum of 16 on ELF, or the default -section alignment of 4 on PE(1). +when placing the symbol. If no alignment is specified, 'as' will set +the alignment to the largest power of two less than or equal to the size +of the symbol, up to a maximum of 16 on ELF, or the default section +alignment of 4 on PE(1). - The syntax for `.comm' differs slightly on the HPPA. The syntax is -`SYMBOL .comm, LENGTH'; SYMBOL is optional. + The syntax for '.comm' differs slightly on the HPPA. The syntax is +'SYMBOL .comm, LENGTH'; SYMBOL is optional. ---------- Footnotes ---------- (1) This is not the same as the executable image file alignment -controlled by `ld''s `--section-alignment' option; image file sections +controlled by 'ld''s '--section-alignment' option; image file sections in PE are aligned to multiples of 4096, which is far too large an alignment for ordinary variables. It is rather the default alignment -for (non-debug) sections within object (`*.o') files, which are less +for (non-debug) sections within object ('*.o') files, which are less strictly aligned. File: as.info, Node: Data, Next: Def, Prev: Comm, Up: Pseudo Ops -7.33 `.data SUBSECTION' +7.33 '.data SUBSECTION' ======================= -`.data' tells `as' to assemble the following statements onto the end of +'.data' tells 'as' to assemble the following statements onto the end of the data subsection numbered SUBSECTION (which is an absolute expression). If SUBSECTION is omitted, it defaults to zero. File: as.info, Node: Def, Next: Desc, Prev: Data, Up: Pseudo Ops -7.34 `.def NAME' +7.34 '.def NAME' ================ Begin defining debugging information for a symbol NAME; the definition -extends until the `.endef' directive is encountered. +extends until the '.endef' directive is encountered. File: as.info, Node: Desc, Next: Dim, Prev: Def, Up: Pseudo Ops -7.35 `.desc SYMBOL, ABS-EXPRESSION' +7.35 '.desc SYMBOL, ABS-EXPRESSION' =================================== This directive sets the descriptor of the symbol (*note Symbol Attributes::) to the low 16 bits of an absolute expression. - The `.desc' directive is not available when `as' is configured for -COFF output; it is only for `a.out' or `b.out' object format. For the -sake of compatibility, `as' accepts it, but produces no output, when + The '.desc' directive is not available when 'as' is configured for +COFF output; it is only for 'a.out' or 'b.out' object format. For the +sake of compatibility, 'as' accepts it, but produces no output, when configured for COFF. File: as.info, Node: Dim, Next: Double, Prev: Desc, Up: Pseudo Ops -7.36 `.dim' +7.36 '.dim' =========== This directive is generated by compilers to include auxiliary debugging information in the symbol table. It is only permitted inside -`.def'/`.endef' pairs. +'.def'/'.endef' pairs. File: as.info, Node: Double, Next: Eject, Prev: Dim, Up: Pseudo Ops -7.37 `.double FLONUMS' +7.37 '.double FLONUMS' ====================== -`.double' expects zero or more flonums, separated by commas. It +'.double' expects zero or more flonums, separated by commas. It assembles floating point numbers. The exact kind of floating point -numbers emitted depends on how `as' is configured. *Note Machine +numbers emitted depends on how 'as' is configured. *Note Machine Dependencies::. File: as.info, Node: Eject, Next: Else, Prev: Double, Up: Pseudo Ops -7.38 `.eject' +7.38 '.eject' ============= Force a page break at this point, when generating assembly listings. @@ -3535,80 +3472,80 @@ Force a page break at this point, when generating assembly listings. File: as.info, Node: Else, Next: Elseif, Prev: Eject, Up: Pseudo Ops -7.39 `.else' +7.39 '.else' ============ -`.else' is part of the `as' support for conditional assembly; see *note -`.if': If. It marks the beginning of a section of code to be assembled -if the condition for the preceding `.if' was false. +'.else' is part of the 'as' support for conditional assembly; see *note +'.if': If. It marks the beginning of a section of code to be assembled +if the condition for the preceding '.if' was false. File: as.info, Node: Elseif, Next: End, Prev: Else, Up: Pseudo Ops -7.40 `.elseif' +7.40 '.elseif' ============== -`.elseif' is part of the `as' support for conditional assembly; see -*note `.if': If. It is shorthand for beginning a new `.if' block that -would otherwise fill the entire `.else' section. +'.elseif' is part of the 'as' support for conditional assembly; see +*note '.if': If. It is shorthand for beginning a new '.if' block that +would otherwise fill the entire '.else' section. File: as.info, Node: End, Next: Endef, Prev: Elseif, Up: Pseudo Ops -7.41 `.end' +7.41 '.end' =========== -`.end' marks the end of the assembly file. `as' does not process -anything in the file past the `.end' directive. +'.end' marks the end of the assembly file. 'as' does not process +anything in the file past the '.end' directive. File: as.info, Node: Endef, Next: Endfunc, Prev: End, Up: Pseudo Ops -7.42 `.endef' +7.42 '.endef' ============= -This directive flags the end of a symbol definition begun with `.def'. +This directive flags the end of a symbol definition begun with '.def'. File: as.info, Node: Endfunc, Next: Endif, Prev: Endef, Up: Pseudo Ops -7.43 `.endfunc' +7.43 '.endfunc' =============== -`.endfunc' marks the end of a function specified with `.func'. +'.endfunc' marks the end of a function specified with '.func'. File: as.info, Node: Endif, Next: Equ, Prev: Endfunc, Up: Pseudo Ops -7.44 `.endif' +7.44 '.endif' ============= -`.endif' is part of the `as' support for conditional assembly; it marks +'.endif' is part of the 'as' support for conditional assembly; it marks the end of a block of code that is only assembled conditionally. *Note -`.if': If. +'.if': If. File: as.info, Node: Equ, Next: Equiv, Prev: Endif, Up: Pseudo Ops -7.45 `.equ SYMBOL, EXPRESSION' +7.45 '.equ SYMBOL, EXPRESSION' ============================== -This directive sets the value of SYMBOL to EXPRESSION. It is -synonymous with `.set'; see *note `.set': Set. +This directive sets the value of SYMBOL to EXPRESSION. It is synonymous +with '.set'; see *note '.set': Set. - The syntax for `equ' on the HPPA is `SYMBOL .equ EXPRESSION'. + The syntax for 'equ' on the HPPA is 'SYMBOL .equ EXPRESSION'. - The syntax for `equ' on the Z80 is `SYMBOL equ EXPRESSION'. On the + The syntax for 'equ' on the Z80 is 'SYMBOL equ EXPRESSION'. On the Z80 it is an eror if SYMBOL is already defined, but the symbol is not protected from later redefinition. Compare *note Equiv::. File: as.info, Node: Equiv, Next: Eqv, Prev: Equ, Up: Pseudo Ops -7.46 `.equiv SYMBOL, EXPRESSION' +7.46 '.equiv SYMBOL, EXPRESSION' ================================ -The `.equiv' directive is like `.equ' and `.set', except that the +The '.equiv' directive is like '.equ' and '.set', except that the assembler will signal an error if SYMBOL is already defined. Note a symbol which has been referenced but not actually defined is considered to be undefined. @@ -3624,10 +3561,10 @@ equivalent to File: as.info, Node: Eqv, Next: Err, Prev: Equiv, Up: Pseudo Ops -7.47 `.eqv SYMBOL, EXPRESSION' +7.47 '.eqv SYMBOL, EXPRESSION' ============================== -The `.eqv' directive is like `.equiv', but no attempt is made to +The '.eqv' directive is like '.equiv', but no attempt is made to evaluate the expression or any part of it immediately. Instead each time the resulting symbol is used in an expression, a snapshot of its current value is taken. @@ -3635,31 +3572,31 @@ current value is taken. File: as.info, Node: Err, Next: Error, Prev: Eqv, Up: Pseudo Ops -7.48 `.err' +7.48 '.err' =========== -If `as' assembles a `.err' directive, it will print an error message -and, unless the `-Z' option was used, it will not generate an object +If 'as' assembles a '.err' directive, it will print an error message +and, unless the '-Z' option was used, it will not generate an object file. This can be used to signal an error in conditionally compiled code. File: as.info, Node: Error, Next: Exitm, Prev: Err, Up: Pseudo Ops -7.49 `.error "STRING"' +7.49 '.error "STRING"' ====================== -Similarly to `.err', this directive emits an error, but you can specify +Similarly to '.err', this directive emits an error, but you can specify a string that will be emitted as the error message. If you don't -specify the message, it defaults to `".error directive invoked in -source file"'. *Note Error and Warning Messages: Errors. +specify the message, it defaults to '".error directive invoked in source +file"'. *Note Error and Warning Messages: Errors. .error "This code has not been assembled and tested." File: as.info, Node: Exitm, Next: Extern, Prev: Error, Up: Pseudo Ops -7.50 `.exitm' +7.50 '.exitm' ============= Exit early from the current macro definition. *Note Macro::. @@ -3667,54 +3604,54 @@ Exit early from the current macro definition. *Note Macro::. File: as.info, Node: Extern, Next: Fail, Prev: Exitm, Up: Pseudo Ops -7.51 `.extern' +7.51 '.extern' ============== -`.extern' is accepted in the source program--for compatibility with -other assemblers--but it is ignored. `as' treats all undefined symbols +'.extern' is accepted in the source program--for compatibility with +other assemblers--but it is ignored. 'as' treats all undefined symbols as external. File: as.info, Node: Fail, Next: File, Prev: Extern, Up: Pseudo Ops -7.52 `.fail EXPRESSION' +7.52 '.fail EXPRESSION' ======================= Generates an error or a warning. If the value of the EXPRESSION is 500 -or more, `as' will print a warning message. If the value is less than -500, `as' will print an error message. The message will include the +or more, 'as' will print a warning message. If the value is less than +500, 'as' will print an error message. The message will include the value of EXPRESSION. This can occasionally be useful inside complex nested macros or conditional assembly. File: as.info, Node: File, Next: Fill, Prev: Fail, Up: Pseudo Ops -7.53 `.file' +7.53 '.file' ============ -There are two different versions of the `.file' directive. Targets -that support DWARF2 line number information use the DWARF2 version of -`.file'. Other targets use the default version. +There are two different versions of the '.file' directive. Targets that +support DWARF2 line number information use the DWARF2 version of +'.file'. Other targets use the default version. Default Version --------------- -This version of the `.file' directive tells `as' that we are about to +This version of the '.file' directive tells 'as' that we are about to start a new logical file. The syntax is: .file STRING STRING is the new file name. In general, the filename is recognized -whether or not it is surrounded by quotes `"'; but if you wish to -specify an empty file name, you must give the quotes-`""'. This +whether or not it is surrounded by quotes '"'; but if you wish to +specify an empty file name, you must give the quotes-'""'. This statement may go away in future: it is only recognized to be compatible -with old `as' programs. +with old 'as' programs. DWARF2 Version -------------- -When emitting DWARF2 line number information, `.file' assigns filenames -to the `.debug_line' file name table. The syntax is: +When emitting DWARF2 line number information, '.file' assigns filenames +to the '.debug_line' file name table. The syntax is: .file FILENO FILENAME @@ -3723,14 +3660,14 @@ index of the entry in the table. The FILENAME operand is a C string literal. The detail of filename indices is exposed to the user because the -filename table is shared with the `.debug_info' section of the DWARF2 +filename table is shared with the '.debug_info' section of the DWARF2 debugging information, and thus the user must know the exact indices that table entries will have. File: as.info, Node: Fill, Next: Float, Prev: File, Up: Pseudo Ops -7.54 `.fill REPEAT , SIZE , VALUE' +7.54 '.fill REPEAT , SIZE , VALUE' ================================== REPEAT, SIZE and VALUE are absolute expressions. This emits REPEAT @@ -3739,8 +3676,8 @@ more, but if it is more than 8, then it is deemed to have the value 8, compatible with other people's assemblers. The contents of each REPEAT bytes is taken from an 8-byte number. The highest order 4 bytes are zero. The lowest order 4 bytes are VALUE rendered in the byte-order of -an integer on the computer `as' is assembling for. Each SIZE bytes in -a repetition is taken from the lowest order SIZE bytes of this number. +an integer on the computer 'as' is assembling for. Each SIZE bytes in a +repetition is taken from the lowest order SIZE bytes of this number. Again, this bizarre behavior is compatible with other people's assemblers. @@ -3751,51 +3688,51 @@ are absent, SIZE is assumed to be 1. File: as.info, Node: Float, Next: Func, Prev: Fill, Up: Pseudo Ops -7.55 `.float FLONUMS' +7.55 '.float FLONUMS' ===================== This directive assembles zero or more flonums, separated by commas. It -has the same effect as `.single'. The exact kind of floating point -numbers emitted depends on how `as' is configured. *Note Machine +has the same effect as '.single'. The exact kind of floating point +numbers emitted depends on how 'as' is configured. *Note Machine Dependencies::. File: as.info, Node: Func, Next: Global, Prev: Float, Up: Pseudo Ops -7.56 `.func NAME[,LABEL]' +7.56 '.func NAME[,LABEL]' ========================= -`.func' emits debugging information to denote function NAME, and is +'.func' emits debugging information to denote function NAME, and is ignored unless the file is assembled with debugging enabled. Only -`--gstabs[+]' is currently supported. LABEL is the entry point of the -function and if omitted NAME prepended with the `leading char' is used. -`leading char' is usually `_' or nothing, depending on the target. All -functions are currently defined to have `void' return type. The -function must be terminated with `.endfunc'. +'--gstabs[+]' is currently supported. LABEL is the entry point of the +function and if omitted NAME prepended with the 'leading char' is used. +'leading char' is usually '_' or nothing, depending on the target. All +functions are currently defined to have 'void' return type. The +function must be terminated with '.endfunc'. File: as.info, Node: Global, Next: Gnu_attribute, Prev: Func, Up: Pseudo Ops -7.57 `.global SYMBOL', `.globl SYMBOL' +7.57 '.global SYMBOL', '.globl SYMBOL' ====================================== -`.global' makes the symbol visible to `ld'. If you define SYMBOL in +'.global' makes the symbol visible to 'ld'. If you define SYMBOL in your partial program, its value is made available to other partial programs that are linked with it. Otherwise, SYMBOL takes its attributes from a symbol of the same name from another file linked into the same program. - Both spellings (`.globl' and `.global') are accepted, for + Both spellings ('.globl' and '.global') are accepted, for compatibility with other assemblers. - On the HPPA, `.global' is not always enough to make it accessible to -other partial programs. You may need the HPPA-only `.EXPORT' directive + On the HPPA, '.global' is not always enough to make it accessible to +other partial programs. You may need the HPPA-only '.EXPORT' directive as well. *Note HPPA Assembler Directives: HPPA Directives. File: as.info, Node: Gnu_attribute, Next: Hidden, Prev: Global, Up: Pseudo Ops -7.58 `.gnu_attribute TAG,VALUE' +7.58 '.gnu_attribute TAG,VALUE' =============================== Record a GNU object attribute for this file. *Note Object Attributes::. @@ -3803,161 +3740,161 @@ Record a GNU object attribute for this file. *Note Object Attributes::. File: as.info, Node: Hidden, Next: hword, Prev: Gnu_attribute, Up: Pseudo Ops -7.59 `.hidden NAMES' +7.59 '.hidden NAMES' ==================== This is one of the ELF visibility directives. The other two are -`.internal' (*note `.internal': Internal.) and `.protected' (*note -`.protected': Protected.). +'.internal' (*note '.internal': Internal.) and '.protected' (*note +'.protected': Protected.). This directive overrides the named symbols default visibility (which -is set by their binding: local, global or weak). The directive sets -the visibility to `hidden' which means that the symbols are not visible -to other components. Such symbols are always considered to be -`protected' as well. +is set by their binding: local, global or weak). The directive sets the +visibility to 'hidden' which means that the symbols are not visible to +other components. Such symbols are always considered to be 'protected' +as well. File: as.info, Node: hword, Next: Ident, Prev: Hidden, Up: Pseudo Ops -7.60 `.hword EXPRESSIONS' +7.60 '.hword EXPRESSIONS' ========================= This expects zero or more EXPRESSIONS, and emits a 16 bit number for each. - This directive is a synonym for `.short'; depending on the target -architecture, it may also be a synonym for `.word'. + This directive is a synonym for '.short'; depending on the target +architecture, it may also be a synonym for '.word'. File: as.info, Node: Ident, Next: If, Prev: hword, Up: Pseudo Ops -7.61 `.ident' +7.61 '.ident' ============= -This directive is used by some assemblers to place tags in object -files. The behavior of this directive varies depending on the target. -When using the a.out object file format, `as' simply accepts the -directive for source-file compatibility with existing assemblers, but -does not emit anything for it. When using COFF, comments are emitted -to the `.comment' or `.rdata' section, depending on the target. When -using ELF, comments are emitted to the `.comment' section. +This directive is used by some assemblers to place tags in object files. +The behavior of this directive varies depending on the target. When +using the a.out object file format, 'as' simply accepts the directive +for source-file compatibility with existing assemblers, but does not +emit anything for it. When using COFF, comments are emitted to the +'.comment' or '.rdata' section, depending on the target. When using +ELF, comments are emitted to the '.comment' section. File: as.info, Node: If, Next: Incbin, Prev: Ident, Up: Pseudo Ops -7.62 `.if ABSOLUTE EXPRESSION' +7.62 '.if ABSOLUTE EXPRESSION' ============================== -`.if' marks the beginning of a section of code which is only considered +'.if' marks the beginning of a section of code which is only considered part of the source program being assembled if the argument (which must be an ABSOLUTE EXPRESSION) is non-zero. The end of the conditional -section of code must be marked by `.endif' (*note `.endif': Endif.); +section of code must be marked by '.endif' (*note '.endif': Endif.); optionally, you may include code for the alternative condition, flagged -by `.else' (*note `.else': Else.). If you have several conditions to -check, `.elseif' may be used to avoid nesting blocks if/else within -each subsequent `.else' block. +by '.else' (*note '.else': Else.). If you have several conditions to +check, '.elseif' may be used to avoid nesting blocks if/else within each +subsequent '.else' block. - The following variants of `.if' are also supported: -`.ifdef SYMBOL' - Assembles the following section of code if the specified SYMBOL - has been defined. Note a symbol which has been referenced but not - yet defined is considered to be undefined. + The following variants of '.if' are also supported: +'.ifdef SYMBOL' + Assembles the following section of code if the specified SYMBOL has + been defined. Note a symbol which has been referenced but not yet + defined is considered to be undefined. -`.ifb TEXT' +'.ifb TEXT' Assembles the following section of code if the operand is blank (empty). -`.ifc STRING1,STRING2' +'.ifc STRING1,STRING2' Assembles the following section of code if the two strings are the - same. The strings may be optionally quoted with single quotes. - If they are not quoted, the first string stops at the first comma, - and the second string stops at the end of the line. Strings which - contain whitespace should be quoted. The string comparison is - case sensitive. + same. The strings may be optionally quoted with single quotes. If + they are not quoted, the first string stops at the first comma, and + the second string stops at the end of the line. Strings which + contain whitespace should be quoted. The string comparison is case + sensitive. -`.ifeq ABSOLUTE EXPRESSION' +'.ifeq ABSOLUTE EXPRESSION' Assembles the following section of code if the argument is zero. -`.ifeqs STRING1,STRING2' - Another form of `.ifc'. The strings must be quoted using double +'.ifeqs STRING1,STRING2' + Another form of '.ifc'. The strings must be quoted using double quotes. -`.ifge ABSOLUTE EXPRESSION' +'.ifge ABSOLUTE EXPRESSION' Assembles the following section of code if the argument is greater than or equal to zero. -`.ifgt ABSOLUTE EXPRESSION' +'.ifgt ABSOLUTE EXPRESSION' Assembles the following section of code if the argument is greater than zero. -`.ifle ABSOLUTE EXPRESSION' +'.ifle ABSOLUTE EXPRESSION' Assembles the following section of code if the argument is less than or equal to zero. -`.iflt ABSOLUTE EXPRESSION' +'.iflt ABSOLUTE EXPRESSION' Assembles the following section of code if the argument is less than zero. -`.ifnb TEXT' - Like `.ifb', but the sense of the test is reversed: this assembles +'.ifnb TEXT' + Like '.ifb', but the sense of the test is reversed: this assembles the following section of code if the operand is non-blank (non-empty). -`.ifnc STRING1,STRING2.' - Like `.ifc', but the sense of the test is reversed: this assembles +'.ifnc STRING1,STRING2.' + Like '.ifc', but the sense of the test is reversed: this assembles the following section of code if the two strings are not the same. -`.ifndef SYMBOL' -`.ifnotdef SYMBOL' - Assembles the following section of code if the specified SYMBOL - has not been defined. Both spelling variants are equivalent. - Note a symbol which has been referenced but not yet defined is - considered to be undefined. +'.ifndef SYMBOL' +'.ifnotdef SYMBOL' + Assembles the following section of code if the specified SYMBOL has + not been defined. Both spelling variants are equivalent. Note a + symbol which has been referenced but not yet defined is considered + to be undefined. -`.ifne ABSOLUTE EXPRESSION' +'.ifne ABSOLUTE EXPRESSION' Assembles the following section of code if the argument is not - equal to zero (in other words, this is equivalent to `.if'). + equal to zero (in other words, this is equivalent to '.if'). -`.ifnes STRING1,STRING2' - Like `.ifeqs', but the sense of the test is reversed: this +'.ifnes STRING1,STRING2' + Like '.ifeqs', but the sense of the test is reversed: this assembles the following section of code if the two strings are not the same. File: as.info, Node: Incbin, Next: Include, Prev: If, Up: Pseudo Ops -7.63 `.incbin "FILE"[,SKIP[,COUNT]]' +7.63 '.incbin "FILE"[,SKIP[,COUNT]]' ==================================== -The `incbin' directive includes FILE verbatim at the current location. -You can control the search paths used with the `-I' command-line option +The 'incbin' directive includes FILE verbatim at the current location. +You can control the search paths used with the '-I' command-line option (*note Command-Line Options: Invoking.). Quotation marks are required around FILE. - The SKIP argument skips a number of bytes from the start of the -FILE. The COUNT argument indicates the maximum number of bytes to -read. Note that the data is not aligned in any way, so it is the user's + The SKIP argument skips a number of bytes from the start of the FILE. +The COUNT argument indicates the maximum number of bytes to read. Note +that the data is not aligned in any way, so it is the user's responsibility to make sure that proper alignment is provided both -before and after the `incbin' directive. +before and after the 'incbin' directive. File: as.info, Node: Include, Next: Int, Prev: Incbin, Up: Pseudo Ops -7.64 `.include "FILE"' +7.64 '.include "FILE"' ====================== This directive provides a way to include supporting files at specified -points in your source program. The code from FILE is assembled as if -it followed the point of the `.include'; when the end of the included -file is reached, assembly of the original file continues. You can -control the search paths used with the `-I' command-line option (*note +points in your source program. The code from FILE is assembled as if it +followed the point of the '.include'; when the end of the included file +is reached, assembly of the original file continues. You can control +the search paths used with the '-I' command-line option (*note Command-Line Options: Invoking.). Quotation marks are required around FILE. File: as.info, Node: Int, Next: Internal, Prev: Include, Up: Pseudo Ops -7.65 `.int EXPRESSIONS' +7.65 '.int EXPRESSIONS' ======================= Expect zero or more EXPRESSIONS, of any section, separated by commas. @@ -3968,33 +3905,33 @@ what kind of target the assembly is for. File: as.info, Node: Internal, Next: Irp, Prev: Int, Up: Pseudo Ops -7.66 `.internal NAMES' +7.66 '.internal NAMES' ====================== This is one of the ELF visibility directives. The other two are -`.hidden' (*note `.hidden': Hidden.) and `.protected' (*note -`.protected': Protected.). +'.hidden' (*note '.hidden': Hidden.) and '.protected' (*note +'.protected': Protected.). This directive overrides the named symbols default visibility (which -is set by their binding: local, global or weak). The directive sets -the visibility to `internal' which means that the symbols are -considered to be `hidden' (i.e., not visible to other components), and -that some extra, processor specific processing must also be performed -upon the symbols as well. +is set by their binding: local, global or weak). The directive sets the +visibility to 'internal' which means that the symbols are considered to +be 'hidden' (i.e., not visible to other components), and that some +extra, processor specific processing must also be performed upon the +symbols as well. File: as.info, Node: Irp, Next: Irpc, Prev: Internal, Up: Pseudo Ops -7.67 `.irp SYMBOL,VALUES'... +7.67 '.irp SYMBOL,VALUES'... ============================ Evaluate a sequence of statements assigning different values to SYMBOL. -The sequence of statements starts at the `.irp' directive, and is -terminated by an `.endr' directive. For each VALUE, SYMBOL is set to +The sequence of statements starts at the '.irp' directive, and is +terminated by an '.endr' directive. For each VALUE, SYMBOL is set to VALUE, and the sequence of statements is assembled. If no VALUE is -listed, the sequence of statements is assembled once, with SYMBOL set -to the null string. To refer to SYMBOL within the sequence of -statements, use \SYMBOL. +listed, the sequence of statements is assembled once, with SYMBOL set to +the null string. To refer to SYMBOL within the sequence of statements, +use \SYMBOL. For example, assembling @@ -4013,16 +3950,16 @@ statements, use \SYMBOL. File: as.info, Node: Irpc, Next: Lcomm, Prev: Irp, Up: Pseudo Ops -7.68 `.irpc SYMBOL,VALUES'... +7.68 '.irpc SYMBOL,VALUES'... ============================= Evaluate a sequence of statements assigning different values to SYMBOL. -The sequence of statements starts at the `.irpc' directive, and is -terminated by an `.endr' directive. For each character in VALUE, -SYMBOL is set to the character, and the sequence of statements is -assembled. If no VALUE is listed, the sequence of statements is -assembled once, with SYMBOL set to the null string. To refer to SYMBOL -within the sequence of statements, use \SYMBOL. +The sequence of statements starts at the '.irpc' directive, and is +terminated by an '.endr' directive. For each character in VALUE, SYMBOL +is set to the character, and the sequence of statements is assembled. +If no VALUE is listed, the sequence of statements is assembled once, +with SYMBOL set to the null string. To refer to SYMBOL within the +sequence of statements, use \SYMBOL. For example, assembling @@ -4042,64 +3979,64 @@ at *Note Macro::. File: as.info, Node: Lcomm, Next: Lflags, Prev: Irpc, Up: Pseudo Ops -7.69 `.lcomm SYMBOL , LENGTH' +7.69 '.lcomm SYMBOL , LENGTH' ============================= -Reserve LENGTH (an absolute expression) bytes for a local common -denoted by SYMBOL. The section and value of SYMBOL are those of the -new local common. The addresses are allocated in the bss section, so -that at run-time the bytes start off zeroed. SYMBOL is not declared -global (*note `.global': Global.), so is normally not visible to `ld'. +Reserve LENGTH (an absolute expression) bytes for a local common denoted +by SYMBOL. The section and value of SYMBOL are those of the new local +common. The addresses are allocated in the bss section, so that at +run-time the bytes start off zeroed. SYMBOL is not declared global +(*note '.global': Global.), so is normally not visible to 'ld'. - Some targets permit a third argument to be used with `.lcomm'. This + Some targets permit a third argument to be used with '.lcomm'. This argument specifies the desired alignment of the symbol in the bss section. - The syntax for `.lcomm' differs slightly on the HPPA. The syntax is -`SYMBOL .lcomm, LENGTH'; SYMBOL is optional. + The syntax for '.lcomm' differs slightly on the HPPA. The syntax is +'SYMBOL .lcomm, LENGTH'; SYMBOL is optional. File: as.info, Node: Lflags, Next: Line, Prev: Lcomm, Up: Pseudo Ops -7.70 `.lflags' +7.70 '.lflags' ============== -`as' accepts this directive, for compatibility with other assemblers, +'as' accepts this directive, for compatibility with other assemblers, but ignores it. File: as.info, Node: Line, Next: Linkonce, Prev: Lflags, Up: Pseudo Ops -7.71 `.line LINE-NUMBER' +7.71 '.line LINE-NUMBER' ======================== Change the logical line number. LINE-NUMBER must be an absolute expression. The next line has that logical line number. Therefore any other statements on the current line (after a statement separator character) are reported as on logical line number LINE-NUMBER - 1. One -day `as' will no longer support this directive: it is recognized only +day 'as' will no longer support this directive: it is recognized only for compatibility with existing assembler programs. -Even though this is a directive associated with the `a.out' or `b.out' -object-code formats, `as' still recognizes it when producing COFF -output, and treats `.line' as though it were the COFF `.ln' _if_ it is -found outside a `.def'/`.endef' pair. + Even though this is a directive associated with the 'a.out' or +'b.out' object-code formats, 'as' still recognizes it when producing +COFF output, and treats '.line' as though it were the COFF '.ln' _if_ it +is found outside a '.def'/'.endef' pair. - Inside a `.def', `.line' is, instead, one of the directives used by + Inside a '.def', '.line' is, instead, one of the directives used by compilers to generate auxiliary symbol information for debugging. File: as.info, Node: Linkonce, Next: List, Prev: Line, Up: Pseudo Ops -7.72 `.linkonce [TYPE]' +7.72 '.linkonce [TYPE]' ======================= Mark the current section so that the linker only includes a single copy of it. This may be used to include the same section in several different object files, but ensure that the linker will only include it -once in the final output file. The `.linkonce' pseudo-op must be used -for each instance of the section. Duplicate sections are detected -based on the section name, so it should be unique. +once in the final output file. The '.linkonce' pseudo-op must be used +for each instance of the section. Duplicate sections are detected based +on the section name, so it should be unique. This directive is only supported by a few object file formats; as of this writing, the only object file format which supports it is the @@ -4110,128 +4047,127 @@ following strings. For example: .linkonce same_size Not all types may be supported on all object file formats. -`discard' +'discard' Silently discard duplicate sections. This is the default. -`one_only' +'one_only' Warn if there are duplicate sections, but still keep only one copy. -`same_size' +'same_size' Warn if any of the duplicates have different sizes. -`same_contents' +'same_contents' Warn if any of the duplicates do not have exactly the same contents. File: as.info, Node: List, Next: Ln, Prev: Linkonce, Up: Pseudo Ops -7.73 `.list' +7.73 '.list' ============ -Control (in conjunction with the `.nolist' directive) whether or not +Control (in conjunction with the '.nolist' directive) whether or not assembly listings are generated. These two directives maintain an -internal counter (which is zero initially). `.list' increments the -counter, and `.nolist' decrements it. Assembly listings are generated +internal counter (which is zero initially). '.list' increments the +counter, and '.nolist' decrements it. Assembly listings are generated whenever the counter is greater than zero. By default, listings are disabled. When you enable them (with the -`-a' command line option; *note Command-Line Options: Invoking.), the +'-a' command line option; *note Command-Line Options: Invoking.), the initial value of the listing counter is one. File: as.info, Node: Ln, Next: Loc, Prev: List, Up: Pseudo Ops -7.74 `.ln LINE-NUMBER' +7.74 '.ln LINE-NUMBER' ====================== -`.ln' is a synonym for `.line'. +'.ln' is a synonym for '.line'. File: as.info, Node: Loc, Next: Loc_mark_labels, Prev: Ln, Up: Pseudo Ops -7.75 `.loc FILENO LINENO [COLUMN] [OPTIONS]' +7.75 '.loc FILENO LINENO [COLUMN] [OPTIONS]' ============================================ -When emitting DWARF2 line number information, the `.loc' directive will -add a row to the `.debug_line' line number matrix corresponding to the +When emitting DWARF2 line number information, the '.loc' directive will +add a row to the '.debug_line' line number matrix corresponding to the immediately following assembly instruction. The FILENO, LINENO, and -optional COLUMN arguments will be applied to the `.debug_line' state +optional COLUMN arguments will be applied to the '.debug_line' state machine before the row is added. The OPTIONS are a sequence of the following tokens in any order: -`basic_block' - This option will set the `basic_block' register in the - `.debug_line' state machine to `true'. +'basic_block' + This option will set the 'basic_block' register in the + '.debug_line' state machine to 'true'. -`prologue_end' - This option will set the `prologue_end' register in the - `.debug_line' state machine to `true'. +'prologue_end' + This option will set the 'prologue_end' register in the + '.debug_line' state machine to 'true'. -`epilogue_begin' - This option will set the `epilogue_begin' register in the - `.debug_line' state machine to `true'. +'epilogue_begin' + This option will set the 'epilogue_begin' register in the + '.debug_line' state machine to 'true'. -`is_stmt VALUE' - This option will set the `is_stmt' register in the `.debug_line' - state machine to `value', which must be either 0 or 1. +'is_stmt VALUE' + This option will set the 'is_stmt' register in the '.debug_line' + state machine to 'value', which must be either 0 or 1. -`isa VALUE' - This directive will set the `isa' register in the `.debug_line' +'isa VALUE' + This directive will set the 'isa' register in the '.debug_line' state machine to VALUE, which must be an unsigned integer. -`discriminator VALUE' - This directive will set the `discriminator' register in the - `.debug_line' state machine to VALUE, which must be an unsigned +'discriminator VALUE' + This directive will set the 'discriminator' register in the + '.debug_line' state machine to VALUE, which must be an unsigned integer. - File: as.info, Node: Loc_mark_labels, Next: Local, Prev: Loc, Up: Pseudo Ops -7.76 `.loc_mark_labels ENABLE' +7.76 '.loc_mark_labels ENABLE' ============================== -When emitting DWARF2 line number information, the `.loc_mark_labels' -directive makes the assembler emit an entry to the `.debug_line' line -number matrix with the `basic_block' register in the state machine set +When emitting DWARF2 line number information, the '.loc_mark_labels' +directive makes the assembler emit an entry to the '.debug_line' line +number matrix with the 'basic_block' register in the state machine set whenever a code label is seen. The ENABLE argument should be either 1 or 0, to enable or disable this function respectively. File: as.info, Node: Local, Next: Long, Prev: Loc_mark_labels, Up: Pseudo Ops -7.77 `.local NAMES' +7.77 '.local NAMES' =================== This directive, which is available for ELF targets, marks each symbol in -the comma-separated list of `names' as a local symbol so that it will +the comma-separated list of 'names' as a local symbol so that it will not be externally visible. If the symbols do not already exist, they will be created. - For targets where the `.lcomm' directive (*note Lcomm::) does not + For targets where the '.lcomm' directive (*note Lcomm::) does not accept an alignment argument, which is the case for most ELF targets, -the `.local' directive can be used in combination with `.comm' (*note +the '.local' directive can be used in combination with '.comm' (*note Comm::) to define aligned local common data. File: as.info, Node: Long, Next: Macro, Prev: Local, Up: Pseudo Ops -7.78 `.long EXPRESSIONS' +7.78 '.long EXPRESSIONS' ======================== -`.long' is the same as `.int'. *Note `.int': Int. +'.long' is the same as '.int'. *Note '.int': Int. File: as.info, Node: Macro, Next: MRI, Prev: Long, Up: Pseudo Ops -7.79 `.macro' +7.79 '.macro' ============= -The commands `.macro' and `.endm' allow you to define macros that +The commands '.macro' and '.endm' allow you to define macros that generate assembly output. For example, this definition specifies a -macro `sum' that puts a sequence of numbers into memory: +macro 'sum' that puts a sequence of numbers into memory: .macro sum from=0, to=5 .long \from @@ -4240,7 +4176,7 @@ macro `sum' that puts a sequence of numbers into memory: .endif .endm -With that definition, `SUM 0,5' is equivalent to this assembly input: +With that definition, 'SUM 0,5' is equivalent to this assembly input: .long 0 .long 1 @@ -4249,56 +4185,55 @@ With that definition, `SUM 0,5' is equivalent to this assembly input: .long 4 .long 5 -`.macro MACNAME' -`.macro MACNAME MACARGS ...' +'.macro MACNAME' +'.macro MACNAME MACARGS ...' Begin the definition of a macro called MACNAME. If your macro definition requires arguments, specify their names after the macro name, separated by commas or spaces. You can qualify the macro argument to indicate whether all invocations must specify a - non-blank value (through `:`req''), or whether it takes all of the - remaining arguments (through `:`vararg''). You can supply a + non-blank value (through ':'req''), or whether it takes all of the + remaining arguments (through ':'vararg''). You can supply a default value for any macro argument by following the name with - `=DEFLT'. You cannot define two macros with the same MACNAME - unless it has been subject to the `.purgem' directive (*note + '=DEFLT'. You cannot define two macros with the same MACNAME + unless it has been subject to the '.purgem' directive (*note Purgem::) between the two definitions. For example, these are all - valid `.macro' statements: + valid '.macro' statements: - `.macro comm' - Begin the definition of a macro called `comm', which takes no + '.macro comm' + Begin the definition of a macro called 'comm', which takes no arguments. - `.macro plus1 p, p1' - `.macro plus1 p p1' + '.macro plus1 p, p1' + '.macro plus1 p p1' Either statement begins the definition of a macro called - `plus1', which takes two arguments; within the macro - definition, write `\p' or `\p1' to evaluate the arguments. + 'plus1', which takes two arguments; within the macro + definition, write '\p' or '\p1' to evaluate the arguments. - `.macro reserve_str p1=0 p2' - Begin the definition of a macro called `reserve_str', with two + '.macro reserve_str p1=0 p2' + Begin the definition of a macro called 'reserve_str', with two arguments. The first argument has a default value, but not the second. After the definition is complete, you can call - the macro either as `reserve_str A,B' (with `\p1' evaluating - to A and `\p2' evaluating to B), or as `reserve_str ,B' (with - `\p1' evaluating as the default, in this case `0', and `\p2' + the macro either as 'reserve_str A,B' (with '\p1' evaluating + to A and '\p2' evaluating to B), or as 'reserve_str ,B' (with + '\p1' evaluating as the default, in this case '0', and '\p2' evaluating to B). - `.macro m p1:req, p2=0, p3:vararg' - Begin the definition of a macro called `m', with at least + '.macro m p1:req, p2=0, p3:vararg' + Begin the definition of a macro called 'm', with at least three arguments. The first argument must always have a value specified, but not the second, which instead has a default - value. The third formal will get assigned all remaining + value. The third formal will get assigned all remaining arguments specified at invocation time. When you call a macro, you can specify the argument values - either by position, or by keyword. For example, `sum 9,17' - is equivalent to `sum to=17, from=9'. - + either by position, or by keyword. For example, 'sum 9,17' is + equivalent to 'sum to=17, from=9'. - Note that since each of the MACARGS can be an identifier exactly - as any other one permitted by the target architecture, there may be + Note that since each of the MACARGS can be an identifier exactly as + any other one permitted by the target architecture, there may be occasional problems if the target hand-crafts special meanings to certain characters when they occur in a special position. For - example, if the colon (`:') is generally permitted to be part of a + example, if the colon (':') is generally permitted to be part of a symbol name, but the architecture specific code special-cases it when occurring as the final character of a symbol (to denote a label), then the macro parameter replacement code will have no way @@ -4311,12 +4246,12 @@ With that definition, `SUM 0,5' is equivalent to this assembly input: \l: .endm - might not work as expected. Invoking `label foo' might not create - a label called `foo' but instead just insert the text `\l:' into + might not work as expected. Invoking 'label foo' might not create + a label called 'foo' but instead just insert the text '\l:' into the assembler source, probably generating an error about an unrecognised identifier. - Similarly problems might occur with the period character (`.') + Similarly problems might occur with the period character ('.') which is often allowed inside opcode names (and hence identifier names). So for example constructing a macro to build an opcode from a base name and a length specifier like this: @@ -4325,13 +4260,13 @@ With that definition, `SUM 0,5' is equivalent to this assembly input: \base.\length .endm - and invoking it as `opcode store l' will not create a `store.l' + and invoking it as 'opcode store l' will not create a 'store.l' instruction but instead generate some kind of error as the - assembler tries to interpret the text `\base.\length'. + assembler tries to interpret the text '\base.\length'. There are several possible ways around this problem: - `Insert white space' + 'Insert white space' If it is possible to use white space characters then this is the simplest solution. eg: @@ -4339,17 +4274,17 @@ With that definition, `SUM 0,5' is equivalent to this assembly input: \l : .endm - `Use `\()'' - The string `\()' can be used to separate the end of a macro + 'Use '\()'' + The string '\()' can be used to separate the end of a macro argument from the following text. eg: .macro opcode base length \base\().\length .endm - `Use the alternate macro syntax mode' + 'Use the alternate macro syntax mode' In the alternative macro syntax mode the ampersand character - (`&') can be used as a separator. eg: + ('&') can be used as a separator. eg: .altmacro .macro label l @@ -4357,40 +4292,40 @@ With that definition, `SUM 0,5' is equivalent to this assembly input: .endm Note: this problem of correctly identifying string parameters to - pseudo ops also applies to the identifiers used in `.irp' (*note - Irp::) and `.irpc' (*note Irpc::) as well. + pseudo ops also applies to the identifiers used in '.irp' (*note + Irp::) and '.irpc' (*note Irpc::) as well. -`.endm' +'.endm' Mark the end of a macro definition. -`.exitm' +'.exitm' Exit early from the current macro definition. -`\@' - `as' maintains a counter of how many macros it has executed in - this pseudo-variable; you can copy that number to your output with - `\@', but _only within a macro definition_. +'\@' + 'as' maintains a counter of how many macros it has executed in this + pseudo-variable; you can copy that number to your output with '\@', + but _only within a macro definition_. -`LOCAL NAME [ , ... ]' - _Warning: `LOCAL' is only available if you select "alternate macro - syntax" with `--alternate' or `.altmacro'._ *Note `.altmacro': +'LOCAL NAME [ , ... ]' + _Warning: 'LOCAL' is only available if you select "alternate macro + syntax" with '--alternate' or '.altmacro'._ *Note '.altmacro': Altmacro. File: as.info, Node: MRI, Next: Noaltmacro, Prev: Macro, Up: Pseudo Ops -7.80 `.mri VAL' +7.80 '.mri VAL' =============== -If VAL is non-zero, this tells `as' to enter MRI mode. If VAL is zero, -this tells `as' to exit MRI mode. This change affects code assembled -until the next `.mri' directive, or until the end of the file. *Note +If VAL is non-zero, this tells 'as' to enter MRI mode. If VAL is zero, +this tells 'as' to exit MRI mode. This change affects code assembled +until the next '.mri' directive, or until the end of the file. *Note MRI mode: M. File: as.info, Node: Noaltmacro, Next: Nolist, Prev: MRI, Up: Pseudo Ops -7.81 `.noaltmacro' +7.81 '.noaltmacro' ================== Disable alternate macro mode. *Note Altmacro::. @@ -4398,19 +4333,19 @@ Disable alternate macro mode. *Note Altmacro::. File: as.info, Node: Nolist, Next: Octa, Prev: Noaltmacro, Up: Pseudo Ops -7.82 `.nolist' +7.82 '.nolist' ============== -Control (in conjunction with the `.list' directive) whether or not +Control (in conjunction with the '.list' directive) whether or not assembly listings are generated. These two directives maintain an -internal counter (which is zero initially). `.list' increments the -counter, and `.nolist' decrements it. Assembly listings are generated +internal counter (which is zero initially). '.list' increments the +counter, and '.nolist' decrements it. Assembly listings are generated whenever the counter is greater than zero. File: as.info, Node: Octa, Next: Offset, Prev: Nolist, Up: Pseudo Ops -7.83 `.octa BIGNUMS' +7.83 '.octa BIGNUMS' ==================== This directive expects zero or more bignums, separated by commas. For @@ -4422,32 +4357,31 @@ hence _octa_-word for 16 bytes. File: as.info, Node: Offset, Next: Org, Prev: Octa, Up: Pseudo Ops -7.84 `.offset LOC' +7.84 '.offset LOC' ================== -Set the location counter to LOC in the absolute section. LOC must be -an absolute expression. This directive may be useful for defining -symbols with absolute values. Do not confuse it with the `.org' -directive. +Set the location counter to LOC in the absolute section. LOC must be an +absolute expression. This directive may be useful for defining symbols +with absolute values. Do not confuse it with the '.org' directive. File: as.info, Node: Org, Next: P2align, Prev: Offset, Up: Pseudo Ops -7.85 `.org NEW-LC , FILL' +7.85 '.org NEW-LC , FILL' ========================= Advance the location counter of the current section to NEW-LC. NEW-LC is either an absolute expression or an expression with the same section -as the current subsection. That is, you can't use `.org' to cross -sections: if NEW-LC has the wrong section, the `.org' directive is +as the current subsection. That is, you can't use '.org' to cross +sections: if NEW-LC has the wrong section, the '.org' directive is ignored. To be compatible with former assemblers, if the section of -NEW-LC is absolute, `as' issues a warning, then pretends the section of +NEW-LC is absolute, 'as' issues a warning, then pretends the section of NEW-LC is the same as the current subsection. - `.org' may only increase the location counter, or leave it -unchanged; you cannot use `.org' to move the location counter backwards. + '.org' may only increase the location counter, or leave it unchanged; +you cannot use '.org' to move the location counter backwards. - Because `as' tries to assemble programs in one pass, NEW-LC may not + Because 'as' tries to assemble programs in one pass, NEW-LC may not be undefined. If you really detest this restriction we eagerly await a chance to share your improved assembler. @@ -4462,15 +4396,15 @@ expression. If the comma and FILL are omitted, FILL defaults to zero. File: as.info, Node: P2align, Next: PopSection, Prev: Org, Up: Pseudo Ops -7.86 `.p2align[wl] ABS-EXPR, ABS-EXPR, ABS-EXPR' +7.86 '.p2align[wl] ABS-EXPR, ABS-EXPR, ABS-EXPR' ================================================ Pad the location counter (in the current subsection) to a particular storage boundary. The first expression (which must be absolute) is the number of low-order zero bits the location counter must have after -advancement. For example `.p2align 3' advances the location counter -until it a multiple of 8. If the location counter is already a -multiple of 8, no change is needed. +advancement. For example '.p2align 3' advances the location counter +until it a multiple of 8. If the location counter is already a multiple +of 8, no change is needed. The second expression (also absolute) gives the fill value to be stored in the padding bytes. It (and the comma) may be omitted. If it @@ -4480,51 +4414,51 @@ is omitted, the space is filled with no-op instructions. The third expression is also absolute, and is also optional. If it is present, it is the maximum number of bytes that should be skipped by -this alignment directive. If doing the alignment would require -skipping more bytes than the specified maximum, then the alignment is -not done at all. You can omit the fill value (the second argument) -entirely by simply using two commas after the required alignment; this -can be useful if you want the alignment to be filled with no-op -instructions when appropriate. - - The `.p2alignw' and `.p2alignl' directives are variants of the -`.p2align' directive. The `.p2alignw' directive treats the fill -pattern as a two byte word value. The `.p2alignl' directives treats the -fill pattern as a four byte longword value. For example, `.p2alignw +this alignment directive. If doing the alignment would require skipping +more bytes than the specified maximum, then the alignment is not done at +all. You can omit the fill value (the second argument) entirely by +simply using two commas after the required alignment; this can be useful +if you want the alignment to be filled with no-op instructions when +appropriate. + + The '.p2alignw' and '.p2alignl' directives are variants of the +'.p2align' directive. The '.p2alignw' directive treats the fill pattern +as a two byte word value. The '.p2alignl' directives treats the fill +pattern as a four byte longword value. For example, '.p2alignw 2,0x368d' will align to a multiple of 4. If it skips two bytes, they will be filled in with the value 0x368d (the exact placement of the -bytes depends upon the endianness of the processor). If it skips 1 or -3 bytes, the fill value is undefined. +bytes depends upon the endianness of the processor). If it skips 1 or 3 +bytes, the fill value is undefined. File: as.info, Node: PopSection, Next: Previous, Prev: P2align, Up: Pseudo Ops -7.87 `.popsection' +7.87 '.popsection' ================== This is one of the ELF section stack manipulation directives. The -others are `.section' (*note Section::), `.subsection' (*note -SubSection::), `.pushsection' (*note PushSection::), and `.previous' +others are '.section' (*note Section::), '.subsection' (*note +SubSection::), '.pushsection' (*note PushSection::), and '.previous' (*note Previous::). - This directive replaces the current section (and subsection) with -the top section (and subsection) on the section stack. This section is + This directive replaces the current section (and subsection) with the +top section (and subsection) on the section stack. This section is popped off the stack. File: as.info, Node: Previous, Next: Print, Prev: PopSection, Up: Pseudo Ops -7.88 `.previous' +7.88 '.previous' ================ This is one of the ELF section stack manipulation directives. The -others are `.section' (*note Section::), `.subsection' (*note -SubSection::), `.pushsection' (*note PushSection::), and `.popsection' +others are '.section' (*note Section::), '.subsection' (*note +SubSection::), '.pushsection' (*note PushSection::), and '.popsection' (*note PopSection::). This directive swaps the current section (and subsection) with most recently referenced section/subsection pair prior to this one. Multiple -`.previous' directives in a row will flip between two sections (and +'.previous' directives in a row will flip between two sections (and their subsections). For example: .section A @@ -4536,7 +4470,7 @@ their subsections). For example: .word 0x9abc Will place 0x1234 and 0x9abc into subsection 1 and 0x5678 into -subsection 2 of section A. Whilst: +subsection 2 of section A. Whilst: .section A .subsection 1 @@ -4553,8 +4487,8 @@ subsection 2 of section A. Whilst: # Now in section B subsection 0 .word 0xdef0 - Will place 0x1234 into section A, 0x5678 and 0xdef0 into subsection -0 of section B and 0x9abc into subsection 1 of section B. + Will place 0x1234 into section A, 0x5678 and 0xdef0 into subsection 0 +of section B and 0x9abc into subsection 1 of section B. In terms of the section stack, this directive swaps the current section with the top section on the section stack. @@ -4562,61 +4496,51 @@ section with the top section on the section stack. File: as.info, Node: Print, Next: Protected, Prev: Previous, Up: Pseudo Ops -7.89 `.print STRING' +7.89 '.print STRING' ==================== -`as' will print STRING on the standard output during assembly. You -must put STRING in double quotes. +'as' will print STRING on the standard output during assembly. You must +put STRING in double quotes. -File: as.info, Node: Protected, Next: Secondary, Prev: Print, Up: Pseudo Ops +File: as.info, Node: Protected, Next: Psize, Prev: Print, Up: Pseudo Ops -7.90 `.protected NAMES' +7.90 '.protected NAMES' ======================= This is one of the ELF visibility directives. The other two are -`.hidden' (*note Hidden::) and `.internal' (*note Internal::). +'.hidden' (*note Hidden::) and '.internal' (*note Internal::). This directive overrides the named symbols default visibility (which -is set by their binding: local, global or weak). The directive sets -the visibility to `protected' which means that any references to the -symbols from within the components that defines them must be resolved -to the definition in that component, even if a definition in another -component would normally preempt this. +is set by their binding: local, global or weak). The directive sets the +visibility to 'protected' which means that any references to the symbols +from within the components that defines them must be resolved to the +definition in that component, even if a definition in another component +would normally preempt this. -File: as.info, Node: Secondary, Next: Psize, Prev: Protected, Up: Pseudo Ops +File: as.info, Node: Psize, Next: Purgem, Prev: Protected, Up: Pseudo Ops -7.91 `.secondary NAMES' -======================= - -This directive sets the secondary attribute on the comma separated list -of symbol `names'. If the symbols do not already exist, they will be -created. - - -File: as.info, Node: Psize, Next: Purgem, Prev: Secondary, Up: Pseudo Ops - -7.92 `.psize LINES , COLUMNS' +7.91 '.psize LINES , COLUMNS' ============================= Use this directive to declare the number of lines--and, optionally, the number of columns--to use for each page, when generating listings. - If you do not use `.psize', listings use a default line-count of 60. + If you do not use '.psize', listings use a default line-count of 60. You may omit the comma and COLUMNS specification; the default width is 200 columns. - `as' generates formfeeds whenever the specified number of lines is -exceeded (or whenever you explicitly request one, using `.eject'). + 'as' generates formfeeds whenever the specified number of lines is +exceeded (or whenever you explicitly request one, using '.eject'). - If you specify LINES as `0', no formfeeds are generated save those -explicitly specified with `.eject'. + If you specify LINES as '0', no formfeeds are generated save those +explicitly specified with '.eject'. File: as.info, Node: Purgem, Next: PushSection, Prev: Psize, Up: Pseudo Ops -7.93 `.purgem NAME' +7.92 '.purgem NAME' =================== Undefine the macro NAME, so that later uses of the string will not be @@ -4625,30 +4549,30 @@ expanded. *Note Macro::. File: as.info, Node: PushSection, Next: Quad, Prev: Purgem, Up: Pseudo Ops -7.94 `.pushsection NAME [, SUBSECTION] [, "FLAGS"[, @TYPE[,ARGUMENTS]]]' +7.93 '.pushsection NAME [, SUBSECTION] [, "FLAGS"[, @TYPE[,ARGUMENTS]]]' ======================================================================== This is one of the ELF section stack manipulation directives. The -others are `.section' (*note Section::), `.subsection' (*note -SubSection::), `.popsection' (*note PopSection::), and `.previous' +others are '.section' (*note Section::), '.subsection' (*note +SubSection::), '.popsection' (*note PopSection::), and '.previous' (*note Previous::). This directive pushes the current section (and subsection) onto the top of the section stack, and then replaces the current section and -subsection with `name' and `subsection'. The optional `flags', `type' -and `arguments' are treated the same as in the `.section' (*note +subsection with 'name' and 'subsection'. The optional 'flags', 'type' +and 'arguments' are treated the same as in the '.section' (*note Section::) directive. File: as.info, Node: Quad, Next: Reloc, Prev: PushSection, Up: Pseudo Ops -7.95 `.quad BIGNUMS' +7.94 '.quad BIGNUMS' ==================== -`.quad' expects zero or more bignums, separated by commas. For each -bignum, it emits an 8-byte integer. If the bignum won't fit in 8 -bytes, it prints a warning message; and just takes the lowest order 8 -bytes of the bignum. +'.quad' expects zero or more bignums, separated by commas. For each +bignum, it emits an 8-byte integer. If the bignum won't fit in 8 bytes, +it prints a warning message; and just takes the lowest order 8 bytes of +the bignum. The term "quad" comes from contexts in which a "word" is two bytes; hence _quad_-word for 8 bytes. @@ -4656,7 +4580,7 @@ hence _quad_-word for 8 bytes. File: as.info, Node: Reloc, Next: Rept, Prev: Quad, Up: Pseudo Ops -7.96 `.reloc OFFSET, RELOC_NAME[, EXPRESSION]' +7.95 '.reloc OFFSET, RELOC_NAME[, EXPRESSION]' ============================================== Generate a relocation at OFFSET of type RELOC_NAME with value @@ -4672,11 +4596,11 @@ support addends stored in the section. File: as.info, Node: Rept, Next: Sbttl, Prev: Reloc, Up: Pseudo Ops -7.97 `.rept COUNT' +7.96 '.rept COUNT' ================== -Repeat the sequence of lines between the `.rept' directive and the next -`.endr' directive COUNT times. +Repeat the sequence of lines between the '.rept' directive and the next +'.endr' directive COUNT times. For example, assembling @@ -4693,7 +4617,7 @@ Repeat the sequence of lines between the `.rept' directive and the next File: as.info, Node: Sbttl, Next: Scl, Prev: Rept, Up: Pseudo Ops -7.98 `.sbttl "SUBHEADING"' +7.97 '.sbttl "SUBHEADING"' ========================== Use SUBHEADING as the title (third line, immediately after the title @@ -4705,31 +4629,31 @@ if it appears within ten lines of the top of a page. File: as.info, Node: Scl, Next: Section, Prev: Sbttl, Up: Pseudo Ops -7.99 `.scl CLASS' +7.98 '.scl CLASS' ================= Set the storage-class value for a symbol. This directive may only be -used inside a `.def'/`.endef' pair. Storage class may flag whether a +used inside a '.def'/'.endef' pair. Storage class may flag whether a symbol is static or external, or it may record further symbolic debugging information. File: as.info, Node: Section, Next: Set, Prev: Scl, Up: Pseudo Ops -7.100 `.section NAME' -===================== +7.99 '.section NAME' +==================== -Use the `.section' directive to assemble the following code into a +Use the '.section' directive to assemble the following code into a section named NAME. This directive is only supported for targets that actually support -arbitrarily named sections; on `a.out' targets, for example, it is not -accepted, even with a standard `a.out' section name. +arbitrarily named sections; on 'a.out' targets, for example, it is not +accepted, even with a standard 'a.out' section name. COFF Version ------------ - For COFF targets, the `.section' directive is used in one of the +For COFF targets, the '.section' directive is used in one of the following ways: .section NAME[, "FLAGS"] @@ -4738,134 +4662,111 @@ following ways: If the optional argument is quoted, it is taken as flags to use for the section. Each flag is a single character. The following flags are recognized: -`b' +'b' bss section (uninitialized data) - -`n' +'n' section is not loaded - -`w' +'w' writable section - -`d' +'d' data section - -`e' +'e' exclude section from linking - -`r' +'r' read-only section - -`x' +'x' executable section - -`s' +'s' shared section (meaningful for PE targets) - -`a' +'a' ignored. (For compatibility with the ELF version) - -`y' +'y' section is not readable (meaningful for PE targets) - -`0-9' +'0-9' single-digit power-of-two section alignment (GNU extension) If no flags are specified, the default flags depend upon the section name. If the section name is not recognized, the default will be for -the section to be loaded and writable. Note the `n' and `w' flags +the section to be loaded and writable. Note the 'n' and 'w' flags remove attributes from the section, rather than adding them, so if they are used on their own it will be as if no flags had been specified at all. - If the optional argument to the `.section' directive is not quoted, + If the optional argument to the '.section' directive is not quoted, it is taken as a subsection number (*note Sub-Sections::). ELF Version ----------- - This is one of the ELF section stack manipulation directives. The -others are `.subsection' (*note SubSection::), `.pushsection' (*note -PushSection::), `.popsection' (*note PopSection::), and `.previous' +This is one of the ELF section stack manipulation directives. The +others are '.subsection' (*note SubSection::), '.pushsection' (*note +PushSection::), '.popsection' (*note PopSection::), and '.previous' (*note Previous::). - For ELF targets, the `.section' directive is used like this: + For ELF targets, the '.section' directive is used like this: .section NAME [, "FLAGS"[, @TYPE[,FLAG_SPECIFIC_ARGUMENTS]]] The optional FLAGS argument is a quoted string which may contain any combination of the following characters: -`a' +'a' section is allocatable - -`e' +'e' section is excluded from executable and shared library. - -`w' +'w' section is writable - -`x' +'x' section is executable - -`M' +'M' section is mergeable - -`S' +'S' section contains zero terminated strings - -`G' +'G' section is a member of a section group - -`T' +'T' section is used for thread-local-storage - -`?' +'?' section is a member of the previously-current section's group, if any The optional TYPE argument may contain one of the following constants: -`@progbits' +'@progbits' section contains data - -`@nobits' +'@nobits' section does not contain data (i.e., section only occupies space) - -`@note' +'@note' section contains data which is used by things other than the program - -`@init_array' +'@init_array' section contains an array of pointers to init functions - -`@fini_array' +'@fini_array' section contains an array of pointers to finish functions - -`@preinit_array' +'@preinit_array' section contains an array of pointers to pre-init functions Many targets only support the first three section types. - Note on targets where the `@' character is the start of a comment (eg + Note on targets where the '@' character is the start of a comment (eg ARM) then another character is used instead. For example the ARM port -uses the `%' character. +uses the '%' character. - If FLAGS contains the `M' symbol then the TYPE argument must be + If FLAGS contains the 'M' symbol then the TYPE argument must be specified as well as an extra argument--ENTSIZE--like this: .section NAME , "FLAGS"M, @TYPE, ENTSIZE - Sections with the `M' flag but not `S' flag must contain fixed size -constants, each ENTSIZE octets long. Sections with both `M' and `S' + Sections with the 'M' flag but not 'S' flag must contain fixed size +constants, each ENTSIZE octets long. Sections with both 'M' and 'S' must contain zero terminated strings where each character is ENTSIZE -bytes long. The linker may remove duplicates within sections with the -same name, same entity size and same flags. ENTSIZE must be an -absolute expression. For sections with both `M' and `S', a string -which is a suffix of a larger string is considered a duplicate. Thus -`"def"' will be merged with `"abcdef"'; A reference to the first -`"def"' will be changed to a reference to `"abcdef"+3'. - - If FLAGS contains the `G' symbol then the TYPE argument must be +bytes long. The linker may remove duplicates within sections with the +same name, same entity size and same flags. ENTSIZE must be an absolute +expression. For sections with both 'M' and 'S', a string which is a +suffix of a larger string is considered a duplicate. Thus '"def"' will +be merged with '"abcdef"'; A reference to the first '"def"' will be +changed to a reference to '"abcdef"+3'. + + If FLAGS contains the 'G' symbol then the TYPE argument must be present along with an additional field like this: .section NAME , "FLAGS"G, @TYPE, GROUPNAME[, LINKAGE] @@ -4873,10 +4774,9 @@ present along with an additional field like this: The GROUPNAME field specifies the name of the section group to which this particular section belongs. The optional linkage field can contain: -`comdat' +'comdat' indicates that only one copy of this section should be retained - -`.gnu.linkonce' +'.gnu.linkonce' an alias for comdat Note: if both the M and G flags are present then the fields for the @@ -4884,89 +4784,85 @@ Merge flag should come first, like this: .section NAME , "FLAGS"MG, @TYPE, ENTSIZE, GROUPNAME[, LINKAGE] - If FLAGS contains the `?' symbol then it may not also contain the -`G' symbol and the GROUPNAME or LINKAGE fields should not be present. -Instead, `?' says to consider the section that's current before this -directive. If that section used `G', then the new section will use `G' + If FLAGS contains the '?' symbol then it may not also contain the 'G' +symbol and the GROUPNAME or LINKAGE fields should not be present. +Instead, '?' says to consider the section that's current before this +directive. If that section used 'G', then the new section will use 'G' with those same GROUPNAME and LINKAGE fields implicitly. If not, then -the `?' symbol has no effect. +the '?' symbol has no effect. If no flags are specified, the default flags depend upon the section name. If the section name is not recognized, the default will be for -the section to have none of the above flags: it will not be allocated -in memory, nor writable, nor executable. The section will contain data. +the section to have none of the above flags: it will not be allocated in +memory, nor writable, nor executable. The section will contain data. - For ELF targets, the assembler supports another type of `.section' + For ELF targets, the assembler supports another type of '.section' directive for compatibility with the Solaris assembler: .section "NAME"[, FLAGS...] Note that the section name is quoted. There may be a sequence of comma separated flags: -`#alloc' +'#alloc' section is allocatable - -`#write' +'#write' section is writable - -`#execinstr' +'#execinstr' section is executable - -`#exclude' +'#exclude' section is excluded from executable and shared library. - -`#tls' +'#tls' section is used for thread local storage This directive replaces the current section and subsection. See the -contents of the gas testsuite directory `gas/testsuite/gas/elf' for -some examples of how this directive and the other section stack -directives work. +contents of the gas testsuite directory 'gas/testsuite/gas/elf' for some +examples of how this directive and the other section stack directives +work. File: as.info, Node: Set, Next: Short, Prev: Section, Up: Pseudo Ops -7.101 `.set SYMBOL, EXPRESSION' +7.100 '.set SYMBOL, EXPRESSION' =============================== Set the value of SYMBOL to EXPRESSION. This changes SYMBOL's value and type to conform to EXPRESSION. If SYMBOL was flagged as external, it remains flagged (*note Symbol Attributes::). - You may `.set' a symbol many times in the same assembly. + You may '.set' a symbol many times in the same assembly. - If you `.set' a global symbol, the value stored in the object file -is the last value stored into it. + If you '.set' a global symbol, the value stored in the object file is +the last value stored into it. - On Z80 `set' is a real instruction, use `SYMBOL defl EXPRESSION' + On Z80 'set' is a real instruction, use 'SYMBOL defl EXPRESSION' instead. File: as.info, Node: Short, Next: Single, Prev: Set, Up: Pseudo Ops -7.102 `.short EXPRESSIONS' +7.101 '.short EXPRESSIONS' ========================== -`.short' is normally the same as `.word'. *Note `.word': Word. +'.short' is normally the same as '.word'. *Note '.word': Word. - In some configurations, however, `.short' and `.word' generate + In some configurations, however, '.short' and '.word' generate numbers of different lengths. *Note Machine Dependencies::. File: as.info, Node: Single, Next: Size, Prev: Short, Up: Pseudo Ops -7.103 `.single FLONUMS' +7.102 '.single FLONUMS' ======================= This directive assembles zero or more flonums, separated by commas. It -has the same effect as `.float'. The exact kind of floating point -numbers emitted depends on how `as' is configured. *Note Machine +has the same effect as '.float'. The exact kind of floating point +numbers emitted depends on how 'as' is configured. *Note Machine Dependencies::. File: as.info, Node: Size, Next: Skip, Prev: Single, Up: Pseudo Ops -7.104 `.size' +7.103 '.size' ============= This directive is used to set the size associated with a symbol. @@ -4974,80 +4870,80 @@ This directive is used to set the size associated with a symbol. COFF Version ------------ - For COFF targets, the `.size' directive is only permitted inside -`.def'/`.endef' pairs. It is used like this: +For COFF targets, the '.size' directive is only permitted inside +'.def'/'.endef' pairs. It is used like this: .size EXPRESSION ELF Version ----------- - For ELF targets, the `.size' directive is used like this: +For ELF targets, the '.size' directive is used like this: .size NAME , EXPRESSION - This directive sets the size associated with a symbol NAME. The -size in bytes is computed from EXPRESSION which can make use of label + This directive sets the size associated with a symbol NAME. The size +in bytes is computed from EXPRESSION which can make use of label arithmetic. This directive is typically used to set the size of function symbols. File: as.info, Node: Skip, Next: Sleb128, Prev: Size, Up: Pseudo Ops -7.105 `.skip SIZE , FILL' +7.104 '.skip SIZE , FILL' ========================= -This directive emits SIZE bytes, each of value FILL. Both SIZE and -FILL are absolute expressions. If the comma and FILL are omitted, FILL -is assumed to be zero. This is the same as `.space'. +This directive emits SIZE bytes, each of value FILL. Both SIZE and FILL +are absolute expressions. If the comma and FILL are omitted, FILL is +assumed to be zero. This is the same as '.space'. File: as.info, Node: Sleb128, Next: Space, Prev: Skip, Up: Pseudo Ops -7.106 `.sleb128 EXPRESSIONS' +7.105 '.sleb128 EXPRESSIONS' ============================ SLEB128 stands for "signed little endian base 128." This is a compact, variable length representation of numbers used by the DWARF symbolic -debugging format. *Note `.uleb128': Uleb128. +debugging format. *Note '.uleb128': Uleb128. File: as.info, Node: Space, Next: Stab, Prev: Sleb128, Up: Pseudo Ops -7.107 `.space SIZE , FILL' +7.106 '.space SIZE , FILL' ========================== -This directive emits SIZE bytes, each of value FILL. Both SIZE and -FILL are absolute expressions. If the comma and FILL are omitted, FILL -is assumed to be zero. This is the same as `.skip'. +This directive emits SIZE bytes, each of value FILL. Both SIZE and FILL +are absolute expressions. If the comma and FILL are omitted, FILL is +assumed to be zero. This is the same as '.skip'. - _Warning:_ `.space' has a completely different meaning for HPPA - targets; use `.block' as a substitute. See `HP9000 Series 800 + _Warning:_ '.space' has a completely different meaning for HPPA + targets; use '.block' as a substitute. See 'HP9000 Series 800 Assembly Language Reference Manual' (HP 92432-90001) for the - meaning of the `.space' directive. *Note HPPA Assembler + meaning of the '.space' directive. *Note HPPA Assembler Directives: HPPA Directives, for a summary. File: as.info, Node: Stab, Next: String, Prev: Space, Up: Pseudo Ops -7.108 `.stabd, .stabn, .stabs' +7.107 '.stabd, .stabn, .stabs' ============================== -There are three directives that begin `.stab'. All emit symbols (*note +There are three directives that begin '.stab'. All emit symbols (*note Symbols::), for use by symbolic debuggers. The symbols are not entered -in the `as' hash table: they cannot be referenced elsewhere in the +in the 'as' hash table: they cannot be referenced elsewhere in the source file. Up to five fields are required: STRING This is the symbol's name. It may contain any character except - `\000', so is more general than ordinary symbol names. Some + '\000', so is more general than ordinary symbol names. Some debuggers used to code arbitrarily complex structures into symbol names using this field. TYPE - An absolute expression. The symbol's type is set to the low 8 - bits of this expression. Any bit pattern is permitted, but `ld' - and debuggers choke on silly bit patterns. + An absolute expression. The symbol's type is set to the low 8 bits + of this expression. Any bit pattern is permitted, but 'ld' and + debuggers choke on silly bit patterns. OTHER An absolute expression. The symbol's "other" attribute is set to @@ -5060,43 +4956,44 @@ DESC VALUE An absolute expression which becomes the symbol's value. - If a warning is detected while reading a `.stabd', `.stabn', or -`.stabs' statement, the symbol has probably already been created; you + If a warning is detected while reading a '.stabd', '.stabn', or +'.stabs' statement, the symbol has probably already been created; you get a half-formed symbol in your object file. This is compatible with earlier assemblers! -`.stabd TYPE , OTHER , DESC' - The "name" of the symbol generated is not even an empty string. - It is a null pointer, for compatibility. Older assemblers used a - null pointer so they didn't waste space in object files with empty +'.stabd TYPE , OTHER , DESC' + + The "name" of the symbol generated is not even an empty string. It + is a null pointer, for compatibility. Older assemblers used a null + pointer so they didn't waste space in object files with empty strings. The symbol's value is set to the location counter, relocatably. When your program is linked, the value of this symbol is the - address of the location counter when the `.stabd' was assembled. + address of the location counter when the '.stabd' was assembled. -`.stabn TYPE , OTHER , DESC , VALUE' - The name of the symbol is set to the empty string `""'. +'.stabn TYPE , OTHER , DESC , VALUE' + The name of the symbol is set to the empty string '""'. -`.stabs STRING , TYPE , OTHER , DESC , VALUE' +'.stabs STRING , TYPE , OTHER , DESC , VALUE' All five fields are specified. File: as.info, Node: String, Next: Struct, Prev: Stab, Up: Pseudo Ops -7.109 `.string' "STR", `.string8' "STR", `.string16' +7.108 '.string' "STR", '.string8' "STR", '.string16' ==================================================== -"STR", `.string32' "STR", `.string64' "STR" +"STR", '.string32' "STR", '.string64' "STR" Copy the characters in STR to the object file. You may specify more than one string to copy, separated by commas. Unless otherwise specified for a particular machine, the assembler marks the end of each -string with a 0 byte. You can use any of the escape sequences -described in *note Strings: Strings. +string with a 0 byte. You can use any of the escape sequences described +in *note Strings: Strings. - The variants `string16', `string32' and `string64' differ from the -`string' pseudo opcode in that each 8-bit character from STR is copied + The variants 'string16', 'string32' and 'string64' differ from the +'string' pseudo opcode in that each 8-bit character from STR is copied and expanded to 16, 32 or 64 bits respectively. The expanded characters are stored in target endianness byte order. @@ -5109,117 +5006,116 @@ are stored in target endianness byte order. File: as.info, Node: Struct, Next: SubSection, Prev: String, Up: Pseudo Ops -7.110 `.struct EXPRESSION' +7.109 '.struct EXPRESSION' ========================== Switch to the absolute section, and set the section offset to -EXPRESSION, which must be an absolute expression. You might use this -as follows: +EXPRESSION, which must be an absolute expression. You might use this as +follows: .struct 0 field1: .struct field1 + 4 field2: .struct field2 + 4 field3: - This would define the symbol `field1' to have the value 0, the symbol -`field2' to have the value 4, and the symbol `field3' to have the value + This would define the symbol 'field1' to have the value 0, the symbol +'field2' to have the value 4, and the symbol 'field3' to have the value 8. Assembly would be left in the absolute section, and you would need -to use a `.section' directive of some sort to change to some other +to use a '.section' directive of some sort to change to some other section before further assembly. File: as.info, Node: SubSection, Next: Symver, Prev: Struct, Up: Pseudo Ops -7.111 `.subsection NAME' +7.110 '.subsection NAME' ======================== This is one of the ELF section stack manipulation directives. The -others are `.section' (*note Section::), `.pushsection' (*note -PushSection::), `.popsection' (*note PopSection::), and `.previous' +others are '.section' (*note Section::), '.pushsection' (*note +PushSection::), '.popsection' (*note PopSection::), and '.previous' (*note Previous::). - This directive replaces the current subsection with `name'. The -current section is not changed. The replaced subsection is put onto -the section stack in place of the then current top of stack subsection. + This directive replaces the current subsection with 'name'. The +current section is not changed. The replaced subsection is put onto the +section stack in place of the then current top of stack subsection. File: as.info, Node: Symver, Next: Tag, Prev: SubSection, Up: Pseudo Ops -7.112 `.symver' +7.111 '.symver' =============== -Use the `.symver' directive to bind symbols to specific version nodes +Use the '.symver' directive to bind symbols to specific version nodes within a source file. This is only supported on ELF platforms, and is typically used when assembling files to be linked into a shared library. There are cases where it may make sense to use this in objects to be bound into an application itself so as to override a versioned symbol from a shared library. - For ELF targets, the `.symver' directive can be used like this: + For ELF targets, the '.symver' directive can be used like this: .symver NAME, NAME2@NODENAME If the symbol NAME is defined within the file being assembled, the -`.symver' directive effectively creates a symbol alias with the name +'.symver' directive effectively creates a symbol alias with the name NAME2@NODENAME, and in fact the main reason that we just don't try and -create a regular alias is that the @ character isn't permitted in -symbol names. The NAME2 part of the name is the actual name of the -symbol by which it will be externally referenced. The name NAME itself -is merely a name of convenience that is used so that it is possible to -have definitions for multiple versions of a function within a single -source file, and so that the compiler can unambiguously know which -version of a function is being mentioned. The NODENAME portion of the -alias should be the name of a node specified in the version script -supplied to the linker when building a shared library. If you are -attempting to override a versioned symbol from a shared library, then -NODENAME should correspond to the nodename of the symbol you are trying -to override. +create a regular alias is that the @ character isn't permitted in symbol +names. The NAME2 part of the name is the actual name of the symbol by +which it will be externally referenced. The name NAME itself is merely +a name of convenience that is used so that it is possible to have +definitions for multiple versions of a function within a single source +file, and so that the compiler can unambiguously know which version of a +function is being mentioned. The NODENAME portion of the alias should +be the name of a node specified in the version script supplied to the +linker when building a shared library. If you are attempting to +override a versioned symbol from a shared library, then NODENAME should +correspond to the nodename of the symbol you are trying to override. If the symbol NAME is not defined within the file being assembled, all references to NAME will be changed to NAME2@NODENAME. If no reference to NAME is made, NAME2@NODENAME will be removed from the symbol table. - Another usage of the `.symver' directive is: + Another usage of the '.symver' directive is: .symver NAME, NAME2@@NODENAME In this case, the symbol NAME must exist and be defined within the -file being assembled. It is similar to NAME2@NODENAME. The difference +file being assembled. It is similar to NAME2@NODENAME. The difference is NAME2@@NODENAME will also be used to resolve references to NAME2 by the linker. - The third usage of the `.symver' directive is: + The third usage of the '.symver' directive is: .symver NAME, NAME2@@@NODENAME When NAME is not defined within the file being assembled, it is -treated as NAME2@NODENAME. When NAME is defined within the file being +treated as NAME2@NODENAME. When NAME is defined within the file being assembled, the symbol name, NAME, will be changed to NAME2@@NODENAME. File: as.info, Node: Tag, Next: Text, Prev: Symver, Up: Pseudo Ops -7.113 `.tag STRUCTNAME' +7.112 '.tag STRUCTNAME' ======================= This directive is generated by compilers to include auxiliary debugging information in the symbol table. It is only permitted inside -`.def'/`.endef' pairs. Tags are used to link structure definitions in +'.def'/'.endef' pairs. Tags are used to link structure definitions in the symbol table with instances of those structures. File: as.info, Node: Text, Next: Title, Prev: Tag, Up: Pseudo Ops -7.114 `.text SUBSECTION' +7.113 '.text SUBSECTION' ======================== -Tells `as' to assemble the following statements onto the end of the -text subsection numbered SUBSECTION, which is an absolute expression. -If SUBSECTION is omitted, subsection number zero is used. +Tells 'as' to assemble the following statements onto the end of the text +subsection numbered SUBSECTION, which is an absolute expression. If +SUBSECTION is omitted, subsection number zero is used. File: as.info, Node: Title, Next: Type, Prev: Text, Up: Pseudo Ops -7.115 `.title "HEADING"' +7.114 '.title "HEADING"' ======================== -Use HEADING as the title (second line, immediately after the source -file name and pagenumber) when generating assembly listings. +Use HEADING as the title (second line, immediately after the source file +name and pagenumber) when generating assembly listings. This directive affects subsequent pages, as well as the current page if it appears within ten lines of the top of a page. @@ -5227,7 +5123,7 @@ if it appears within ten lines of the top of a page. File: as.info, Node: Type, Next: Uleb128, Prev: Title, Up: Pseudo Ops -7.116 `.type' +7.115 '.type' ============= This directive is used to set the type of a symbol. @@ -5235,8 +5131,8 @@ This directive is used to set the type of a symbol. COFF Version ------------ - For COFF targets, this directive is permitted only within -`.def'/`.endef' pairs. It is used like this: +For COFF targets, this directive is permitted only within +'.def'/'.endef' pairs. It is used like this: .type INT @@ -5246,7 +5142,7 @@ entry. ELF Version ----------- - For ELF targets, the `.type' directive is used like this: +For ELF targets, the '.type' directive is used like this: .type NAME , TYPE DESCRIPTION @@ -5255,12 +5151,12 @@ an object symbol. There are five different syntaxes supported for the TYPE DESCRIPTION field, in order to provide compatibility with various other assemblers. - Because some of the characters used in these syntaxes (such as `@' -and `#') are comment characters for some architectures, some of the -syntaxes below do not work on all architectures. The first variant -will be accepted by the GNU assembler on all architectures so that -variant should be used for maximum portability, if you do not need to -assemble your code with other assemblers. + Because some of the characters used in these syntaxes (such as '@' +and '#') are comment characters for some architectures, some of the +syntaxes below do not work on all architectures. The first variant will +be accepted by the GNU assembler on all architectures so that variant +should be used for maximum portability, if you do not need to assemble +your code with other assemblers. The syntaxes supported are: @@ -5272,113 +5168,112 @@ assemble your code with other assemblers. The types supported are: -`STT_FUNC' -`function' +'STT_FUNC' +'function' Mark the symbol as being a function name. -`STT_GNU_IFUNC' -`gnu_indirect_function' +'STT_GNU_IFUNC' +'gnu_indirect_function' Mark the symbol as an indirect function when evaluated during reloc processing. (This is only supported on assemblers targeting GNU systems). -`STT_OBJECT' -`object' +'STT_OBJECT' +'object' Mark the symbol as being a data object. -`STT_TLS' -`tls_object' +'STT_TLS' +'tls_object' Mark the symbol as being a thead-local data object. -`STT_COMMON' -`common' +'STT_COMMON' +'common' Mark the symbol as being a common data object. -`STT_NOTYPE' -`notype' +'STT_NOTYPE' +'notype' Does not mark the symbol in any way. It is supported just for completeness. -`gnu_unique_object' +'gnu_unique_object' Marks the symbol as being a globally unique data object. The dynamic linker will make sure that in the entire process there is just one symbol with this name and type in use. (This is only supported on assemblers targeting GNU systems). - Note: Some targets support extra types in addition to those listed above. File: as.info, Node: Uleb128, Next: Val, Prev: Type, Up: Pseudo Ops -7.117 `.uleb128 EXPRESSIONS' +7.116 '.uleb128 EXPRESSIONS' ============================ ULEB128 stands for "unsigned little endian base 128." This is a compact, variable length representation of numbers used by the DWARF -symbolic debugging format. *Note `.sleb128': Sleb128. +symbolic debugging format. *Note '.sleb128': Sleb128. File: as.info, Node: Val, Next: Version, Prev: Uleb128, Up: Pseudo Ops -7.118 `.val ADDR' +7.117 '.val ADDR' ================= -This directive, permitted only within `.def'/`.endef' pairs, records -the address ADDR as the value attribute of a symbol table entry. +This directive, permitted only within '.def'/'.endef' pairs, records the +address ADDR as the value attribute of a symbol table entry. File: as.info, Node: Version, Next: VTableEntry, Prev: Val, Up: Pseudo Ops -7.119 `.version "STRING"' +7.118 '.version "STRING"' ========================= -This directive creates a `.note' section and places into it an ELF -formatted note of type NT_VERSION. The note's name is set to `string'. +This directive creates a '.note' section and places into it an ELF +formatted note of type NT_VERSION. The note's name is set to 'string'. File: as.info, Node: VTableEntry, Next: VTableInherit, Prev: Version, Up: Pseudo Ops -7.120 `.vtable_entry TABLE, OFFSET' +7.119 '.vtable_entry TABLE, OFFSET' =================================== -This directive finds or creates a symbol `table' and creates a -`VTABLE_ENTRY' relocation for it with an addend of `offset'. +This directive finds or creates a symbol 'table' and creates a +'VTABLE_ENTRY' relocation for it with an addend of 'offset'. File: as.info, Node: VTableInherit, Next: Warning, Prev: VTableEntry, Up: Pseudo Ops -7.121 `.vtable_inherit CHILD, PARENT' +7.120 '.vtable_inherit CHILD, PARENT' ===================================== -This directive finds the symbol `child' and finds or creates the symbol -`parent' and then creates a `VTABLE_INHERIT' relocation for the parent +This directive finds the symbol 'child' and finds or creates the symbol +'parent' and then creates a 'VTABLE_INHERIT' relocation for the parent whose addend is the value of the child symbol. As a special case the -parent name of `0' is treated as referring to the `*ABS*' section. +parent name of '0' is treated as referring to the '*ABS*' section. File: as.info, Node: Warning, Next: Weak, Prev: VTableInherit, Up: Pseudo Ops -7.122 `.warning "STRING"' +7.121 '.warning "STRING"' ========================= -Similar to the directive `.error' (*note `.error "STRING"': Error.), -but just emits a warning. +Similar to the directive '.error' (*note '.error "STRING"': Error.), but +just emits a warning. File: as.info, Node: Weak, Next: Weakref, Prev: Warning, Up: Pseudo Ops -7.123 `.weak NAMES' +7.122 '.weak NAMES' =================== This directive sets the weak attribute on the comma separated list of -symbol `names'. If the symbols do not already exist, they will be +symbol 'names'. If the symbols do not already exist, they will be created. On COFF targets other than PE, weak symbols are a GNU extension. This directive sets the weak attribute on the comma separated list of -symbol `names'. If the symbols do not already exist, they will be +symbol 'names'. If the symbols do not already exist, they will be created. On the PE target, weak symbols are supported natively as weak @@ -5388,15 +5283,15 @@ creates an alternate symbol to hold the default value. File: as.info, Node: Weakref, Next: Word, Prev: Weak, Up: Pseudo Ops -7.124 `.weakref ALIAS, TARGET' +7.123 '.weakref ALIAS, TARGET' ============================== This directive creates an alias to the target symbol that enables the -symbol to be referenced with weak-symbol semantics, but without -actually making it weak. If direct references or definitions of the -symbol are present, then the symbol will not be weak, but if all -references to it are through weak references, the symbol will be marked -as weak in the symbol table. +symbol to be referenced with weak-symbol semantics, but without actually +making it weak. If direct references or definitions of the symbol are +present, then the symbol will not be weak, but if all references to it +are through weak references, the symbol will be marked as weak in the +symbol table. The effect is equivalent to moving all references to the alias to a separate assembly source file, renaming the alias to the symbol in it, @@ -5411,7 +5306,7 @@ handled within the assembler. File: as.info, Node: Word, Next: Deprecated, Prev: Weakref, Up: Pseudo Ops -7.125 `.word EXPRESSIONS' +7.124 '.word EXPRESSIONS' ========================= This directive expects zero or more EXPRESSIONS, of any section, @@ -5427,37 +5322,34 @@ addressing, require the following special treatment. If the machine of interest to you does 32-bit addressing (or doesn't require it; *note Machine Dependencies::), you can ignore this issue. - In order to assemble compiler output into something that works, `as' -occasionally does strange things to `.word' directives. Directives of -the form `.word sym1-sym2' are often emitted by compilers as part of -jump tables. Therefore, when `as' assembles a directive of the form -`.word sym1-sym2', and the difference between `sym1' and `sym2' does -not fit in 16 bits, `as' creates a "secondary jump table", immediately + In order to assemble compiler output into something that works, 'as' +occasionally does strange things to '.word' directives. Directives of +the form '.word sym1-sym2' are often emitted by compilers as part of +jump tables. Therefore, when 'as' assembles a directive of the form +'.word sym1-sym2', and the difference between 'sym1' and 'sym2' does not +fit in 16 bits, 'as' creates a "secondary jump table", immediately before the next label. This secondary jump table is preceded by a -short-jump to the first byte after the secondary table. This -short-jump prevents the flow of control from accidentally falling into -the new table. Inside the table is a long-jump to `sym2'. The -original `.word' contains `sym1' minus the address of the long-jump to -`sym2'. +short-jump to the first byte after the secondary table. This short-jump +prevents the flow of control from accidentally falling into the new +table. Inside the table is a long-jump to 'sym2'. The original '.word' +contains 'sym1' minus the address of the long-jump to 'sym2'. - If there were several occurrences of `.word sym1-sym2' before the -secondary jump table, all of them are adjusted. If there was a `.word -sym3-sym4', that also did not fit in sixteen bits, a long-jump to -`sym4' is included in the secondary jump table, and the `.word' -directives are adjusted to contain `sym3' minus the address of the -long-jump to `sym4'; and so on, for as many entries in the original -jump table as necessary. + If there were several occurrences of '.word sym1-sym2' before the +secondary jump table, all of them are adjusted. If there was a '.word +sym3-sym4', that also did not fit in sixteen bits, a long-jump to 'sym4' +is included in the secondary jump table, and the '.word' directives are +adjusted to contain 'sym3' minus the address of the long-jump to 'sym4'; +and so on, for as many entries in the original jump table as necessary. File: as.info, Node: Deprecated, Prev: Word, Up: Pseudo Ops -7.126 Deprecated Directives +7.125 Deprecated Directives =========================== One day these directives won't work. They are included for compatibility with older assemblers. .abort - .line @@ -5466,7 +5358,7 @@ File: as.info, Node: Object Attributes, Next: Machine Dependencies, Prev: Pse 8 Object Attributes ******************* -`as' assembles source files written for a specific architecture into +'as' assembles source files written for a specific architecture into object files for that architecture. But not all object files are alike. Many architectures support incompatible variations. For instance, floating point arguments might be passed in floating point registers if @@ -5477,19 +5369,19 @@ objects are built for different generations of the same architecture, the combination may require the newer generation at run-time. This information is useful during and after linking. At link time, -`ld' can warn about incompatible object files. After link time, tools -like `gdb' can use it to process the linked file correctly. +'ld' can warn about incompatible object files. After link time, tools +like 'gdb' can use it to process the linked file correctly. Compatibility information is recorded as a series of object attributes. Each attribute has a "vendor", "tag", and "value". The vendor is a string, and indicates who sets the meaning of the tag. The tag is an integer, and indicates what property the attribute describes. The value may be a string or an integer, and indicates how the property -affects this object. Missing attributes are the same as attributes -with a zero value or empty string value. +affects this object. Missing attributes are the same as attributes with +a zero value or empty string value. Object attributes were developed as part of the ABI for the ARM -Architecture. The file format is documented in `ELF for the ARM +Architecture. The file format is documented in 'ELF for the ARM Architecture'. * Menu: @@ -5503,14 +5395,14 @@ File: as.info, Node: GNU Object Attributes, Next: Defining New Object Attribut 8.1 GNU Object Attributes ========================= -The `.gnu_attribute' directive records an object attribute with vendor -`gnu'. +The '.gnu_attribute' directive records an object attribute with vendor +'gnu'. - Except for `Tag_compatibility', which has both an integer and a + Except for 'Tag_compatibility', which has both an integer and a string for its value, GNU attributes have a string value if the tag number is odd and an integer value if the tag number is even. The -second bit (`TAG & 2' is set for architecture-independent attributes -and clear for architecture-dependent ones. +second bit ('TAG & 2' is set for architecture-independent attributes and +clear for architecture-dependent ones. 8.1.1 Common GNU attributes --------------------------- @@ -5533,18 +5425,14 @@ Tag_GNU_MIPS_ABI_FP (4) be: * 0 for files not affected by the floating-point ABI. - * 1 for files using the hardware floating-point with a standard double-precision FPU. - * 2 for files using the hardware floating-point ABI with a single-precision FPU. - * 3 for files using the software floating-point ABI. - * 4 for files using the hardware floating-point ABI with 64-bit - wide double-precision floating-point registers and 32-bit - wide general purpose registers. + wide double-precision floating-point registers and 32-bit wide + general purpose registers. 8.1.3 PowerPC Attributes ------------------------ @@ -5554,12 +5442,9 @@ Tag_GNU_Power_ABI_FP (4) be: * 0 for files not affected by the floating-point ABI. - * 1 for files using double-precision hardware floating-point ABI. - * 2 for files using the software floating-point ABI. - * 3 for files using single-precision hardware floating-point ABI. @@ -5567,11 +5452,8 @@ Tag_GNU_Power_ABI_Vector (8) The vector ABI used by this object file. The value will be: * 0 for files not affected by the vector ABI. - * 1 for files using general purpose registers to pass vectors. - * 2 for files using AltiVec registers to pass vectors. - * 3 for files using SPE registers to pass vectors. @@ -5582,19 +5464,14 @@ File: as.info, Node: Defining New Object Attributes, Prev: GNU Object Attribut If you want to define a new GNU object attribute, here are the places you will need to modify. New attributes should be discussed on the -`binutils' mailing list. +'binutils' mailing list. * This manual, which is the official register of attributes. - - * The header for your architecture `include/elf', to define the tag. - - * The `bfd' support file for your architecture, to merge the + * The header for your architecture 'include/elf', to define the tag. + * The 'bfd' support file for your architecture, to merge the attribute and issue any appropriate link warnings. - - * Test cases in `ld/testsuite' for merging and link warnings. - - * `binutils/readelf.c' to display your attribute. - + * Test cases in 'ld/testsuite' for merging and link warnings. + * 'binutils/readelf.c' to display your attribute. * GCC, if you want the compiler to mark the attribute automatically. @@ -5604,10 +5481,10 @@ File: as.info, Node: Machine Dependencies, Next: Reporting Bugs, Prev: Object **************************** The machine instruction sets are (almost by definition) different on -each machine where `as' runs. Floating point representations vary as -well, and `as' often supports a few additional directives or +each machine where 'as' runs. Floating point representations vary as +well, and 'as' often supports a few additional directives or command-line options for compatibility with other assemblers on a -particular platform. Finally, some versions of `as' support special +particular platform. Finally, some versions of 'as' support special pseudo-instructions for branch optimization. This chapter discusses most of these differences, though it does not @@ -5616,108 +5493,57 @@ subject, see the hardware manufacturer's manual. * Menu: - * AArch64-Dependent:: AArch64 Dependent Features - * Alpha-Dependent:: Alpha Dependent Features - * ARC-Dependent:: ARC Dependent Features - * ARM-Dependent:: ARM Dependent Features - * AVR-Dependent:: AVR Dependent Features - * Blackfin-Dependent:: Blackfin Dependent Features - * CR16-Dependent:: CR16 Dependent Features - * CRIS-Dependent:: CRIS Dependent Features - * D10V-Dependent:: D10V Dependent Features - * D30V-Dependent:: D30V Dependent Features - * Epiphany-Dependent:: EPIPHANY Dependent Features - * H8/300-Dependent:: Renesas H8/300 Dependent Features - * HPPA-Dependent:: HPPA Dependent Features - * ESA/390-Dependent:: IBM ESA/390 Dependent Features - * i386-Dependent:: Intel 80386 and AMD x86-64 Dependent Features - * i860-Dependent:: Intel 80860 Dependent Features - * i960-Dependent:: Intel 80960 Dependent Features - * IA-64-Dependent:: Intel IA-64 Dependent Features - * IP2K-Dependent:: IP2K Dependent Features - * LM32-Dependent:: LM32 Dependent Features - * M32C-Dependent:: M32C Dependent Features - * M32R-Dependent:: M32R Dependent Features - * M68K-Dependent:: M680x0 Dependent Features - * M68HC11-Dependent:: M68HC11 and 68HC12 Dependent Features - * Meta-Dependent :: Meta Dependent Features - * MicroBlaze-Dependent:: MICROBLAZE Dependent Features - * MIPS-Dependent:: MIPS Dependent Features - * MMIX-Dependent:: MMIX Dependent Features - * MSP430-Dependent:: MSP430 Dependent Features - * NiosII-Dependent:: Altera Nios II Dependent Features - * NS32K-Dependent:: NS32K Dependent Features - * SH-Dependent:: Renesas / SuperH SH Dependent Features * SH64-Dependent:: SuperH SH64 Dependent Features - * PDP-11-Dependent:: PDP-11 Dependent Features - * PJ-Dependent:: picoJava Dependent Features - * PPC-Dependent:: PowerPC Dependent Features - * RL78-Dependent:: RL78 Dependent Features - * RX-Dependent:: RX Dependent Features - * S/390-Dependent:: IBM S/390 Dependent Features - * SCORE-Dependent:: SCORE Dependent Features - * Sparc-Dependent:: SPARC Dependent Features - * TIC54X-Dependent:: TI TMS320C54x Dependent Features - * TIC6X-Dependent :: TI TMS320C6x Dependent Features - * TILE-Gx-Dependent :: Tilera TILE-Gx Dependent Features - * TILEPro-Dependent :: Tilera TILEPro Dependent Features - * V850-Dependent:: V850 Dependent Features - * XGATE-Dependent:: XGATE Features - * XSTORMY16-Dependent:: XStormy16 Dependent Features - * Xtensa-Dependent:: Xtensa Dependent Features - * Z80-Dependent:: Z80 Dependent Features - * Z8000-Dependent:: Z8000 Dependent Features - * Vax-Dependent:: VAX Dependent Features @@ -5741,14 +5567,18 @@ File: as.info, Node: AArch64 Options, Next: AArch64 Syntax, Up: AArch64-Depen 9.1.1 Options ------------- -`-EB' +'-EB' This option specifies that the output generated by the assembler should be marked as being encoded for a big-endian processor. -`-EL' +'-EL' This option specifies that the output generated by the assembler should be marked as being encoded for a little-endian processor. +'-mabi=ABI' + Specify which ABI the source code uses. The recognized arguments + are: 'ilp32' and 'lp64', which decides the generated object file in + ELF32 and ELF64 format respectively. The default is 'lp64'. File: as.info, Node: AArch64 Syntax, Next: AArch64 Floating Point, Prev: AArch64 Options, Up: AArch64-Dependent @@ -5768,14 +5598,14 @@ File: as.info, Node: AArch64-Chars, Next: AArch64-Regs, Up: AArch64 Syntax 9.1.2.1 Special Characters .......................... -The presence of a `//' on a line indicates the start of a comment that -extends to the end of the current line. If a `#' appears as the first +The presence of a '//' on a line indicates the start of a comment that +extends to the end of the current line. If a '#' appears as the first character of a line, the whole line is treated as a comment. - The `;' character can be used instead of a newline to separate + The ';' character can be used instead of a newline to separate statements. - The `#' can be optionally used to indicate immediate operands. + The '#' can be optionally used to indicate immediate operands. File: as.info, Node: AArch64-Regs, Next: AArch64-Relocations, Prev: AArch64-Chars, Up: AArch64 Syntax @@ -5783,8 +5613,8 @@ File: as.info, Node: AArch64-Regs, Next: AArch64-Relocations, Prev: AArch64-C 9.1.2.2 Register Names ...................... -Please refer to the section `4.4 Register Names' of `ARMv8 Instruction -Set Overview', which is available at `http://infocenter.arm.com'. +Please refer to the section '4.4 Register Names' of 'ARMv8 Instruction +Set Overview', which is available at <http://infocenter.arm.com>. File: as.info, Node: AArch64-Relocations, Prev: AArch64-Regs, Up: AArch64 Syntax @@ -5792,20 +5622,20 @@ File: as.info, Node: AArch64-Relocations, Prev: AArch64-Regs, Up: AArch64 Syn 9.1.2.3 Relocations ................... -Relocations for `MOVZ' and `MOVK' instructions can be generated by -prefixing the label with `#:abs_g2:' etc. For example to load the +Relocations for 'MOVZ' and 'MOVK' instructions can be generated by +prefixing the label with '#:abs_g2:' etc. For example to load the 48-bit absolute address of FOO into x0: movz x0, #:abs_g2:foo // bits 32-47, overflow check movk x0, #:abs_g1_nc:foo // bits 16-31, no overflow check movk x0, #:abs_g0_nc:foo // bits 0-15, no overflow check - Relocations for `ADRP', and `ADD', `LDR' or `STR' instructions can -be generated by prefixing the label with `#:pg_hi21:' and `#:lo12:' + Relocations for 'ADRP', and 'ADD', 'LDR' or 'STR' instructions can be +generated by prefixing the label with '#:pg_hi21:' and '#:lo12:' respectively. - For example to use 33-bit (+/-4GB) pc-relative addressing to load -the address of FOO into x0: + For example to use 33-bit (+/-4GB) pc-relative addressing to load the +address of FOO into x0: adrp x0, #:pg_hi21:foo add x0, x0, #:lo12:foo @@ -5815,7 +5645,7 @@ the address of FOO into x0: adrp x0, #:pg_hi21:foo ldr x0, [x0, #:lo12:foo] - Note that `#:pg_hi21:' is optional. + Note that '#:pg_hi21:' is optional. adrp x0, foo @@ -5837,34 +5667,34 @@ File: as.info, Node: AArch64 Directives, Next: AArch64 Opcodes, Prev: AArch64 9.1.4 AArch64 Machine Directives -------------------------------- -`.bss' - This directive switches to the `.bss' section. +'.bss' + This directive switches to the '.bss' section. -`.ltorg' +'.ltorg' This directive causes the current contents of the literal pool to be dumped into the current section (which is assumed to be the .text section) at the current location (aligned to a word - boundary). `GAS' maintains a separate literal pool for each - section and each sub-section. The `.ltorg' directive will only - affect the literal pool of the current section and sub-section. - At the end of assembly all remaining, un-empty literal pools will + boundary). 'GAS' maintains a separate literal pool for each + section and each sub-section. The '.ltorg' directive will only + affect the literal pool of the current section and sub-section. At + the end of assembly all remaining, un-empty literal pools will automatically be dumped. - Note - older versions of `GAS' would dump the current literal pool + Note - older versions of 'GAS' would dump the current literal pool any time a section change occurred. This is no longer done, since it prevents accurate control of the placement of literal pools. -`.pool' +'.pool' This is a synonym for .ltorg. -`NAME .req REGISTER NAME' +'NAME .req REGISTER NAME' This creates an alias for REGISTER NAME called NAME. For example: foo .req w0 -`.unreq ALIAS-NAME' +'.unreq ALIAS-NAME' This undefines a register alias which was previously defined using - the `req' directive. For example: + the 'req' directive. For example: foo .req w0 .unreq foo @@ -5873,27 +5703,25 @@ File: as.info, Node: AArch64 Directives, Next: AArch64 Opcodes, Prev: AArch64 can be used to delete builtin in register name aliases (eg 'w0'). This should only be done if it is really necessary. - File: as.info, Node: AArch64 Opcodes, Next: AArch64 Mapping Symbols, Prev: AArch64 Directives, Up: AArch64-Dependent 9.1.5 Opcodes ------------- -`as' implements all the standard AArch64 opcodes. It also implements +'as' implements all the standard AArch64 opcodes. It also implements several pseudo opcodes, including several synthetic load instructions. -`LDR =' +'LDR =' ldr <register> , =<expression> The constant expression will be placed into the nearest literal pool (if it not already there) and a PC-relative LDR instruction will be generated. - For more information on the AArch64 instruction set and assembly -language notation, see `ARMv8 Instruction Set Overview' available at -`http://infocenter.arm.com'. +language notation, see 'ARMv8 Instruction Set Overview' available at +<http://infocenter.arm.com>. File: as.info, Node: AArch64 Mapping Symbols, Prev: AArch64 Opcodes, Up: AArch64-Dependent @@ -5904,13 +5732,12 @@ File: as.info, Node: AArch64 Mapping Symbols, Prev: AArch64 Opcodes, Up: AArc The AArch64 ELF specification requires that special symbols be inserted into object files to mark certain features: -`$x' +'$x' At the start of a region of code containing AArch64 instructions. -`$d' +'$d' At the start of a region of data. - File: as.info, Node: Alpha-Dependent, Next: ARC-Dependent, Prev: AArch64-Dependent, Up: Machine Dependencies @@ -5932,9 +5759,9 @@ File: as.info, Node: Alpha Notes, Next: Alpha Options, Up: Alpha-Dependent 9.2.1 Notes ----------- -The documentation here is primarily for the ELF object format. `as' -also supports the ECOFF and EVAX formats, but features specific to -these formats are not yet documented. +The documentation here is primarily for the ELF object format. 'as' +also supports the ECOFF and EVAX formats, but features specific to these +formats are not yet documented. File: as.info, Node: Alpha Options, Next: Alpha Syntax, Prev: Alpha Notes, Up: Alpha-Dependent @@ -5942,33 +5769,33 @@ File: as.info, Node: Alpha Options, Next: Alpha Syntax, Prev: Alpha Notes, U 9.2.2 Options ------------- -`-mCPU' +'-mCPU' This option specifies the target processor. If an attempt is made to assemble an instruction which will not execute on the target processor, the assembler may either expand the instruction as a macro or issue an error message. This option is equivalent to the - `.arch' directive. + '.arch' directive. - The following processor names are recognized: `21064', `21064a', - `21066', `21068', `21164', `21164a', `21164pc', `21264', `21264a', - `21264b', `ev4', `ev5', `lca45', `ev5', `ev56', `pca56', `ev6', - `ev67', `ev68'. The special name `all' may be used to allow the + The following processor names are recognized: '21064', '21064a', + '21066', '21068', '21164', '21164a', '21164pc', '21264', '21264a', + '21264b', 'ev4', 'ev5', 'lca45', 'ev5', 'ev56', 'pca56', 'ev6', + 'ev67', 'ev68'. The special name 'all' may be used to allow the assembler to accept instructions valid for any Alpha processor. In order to support existing practice in OSF/1 with respect to - `.arch', and existing practice within `MILO' (the Linux ARC + '.arch', and existing practice within 'MILO' (the Linux ARC bootloader), the numbered processor names (e.g. 21064) enable the - processor-specific PALcode instructions, while the - "electro-vlasic" names (e.g. `ev4') do not. + processor-specific PALcode instructions, while the "electro-vlasic" + names (e.g. 'ev4') do not. -`-mdebug' -`-no-mdebug' - Enables or disables the generation of `.mdebug' encapsulation for +'-mdebug' +'-no-mdebug' + Enables or disables the generation of '.mdebug' encapsulation for stabs directives and procedure descriptors. The default is to - automatically enable `.mdebug' when the first stabs directive is + automatically enable '.mdebug' when the first stabs directive is seen. -`-relax' +'-relax' This option forces all relocations to be put into the object file, instead of saving space and resolving some relocations at assembly time. Note that this option does not propagate all symbol @@ -5976,25 +5803,25 @@ File: as.info, Node: Alpha Options, Next: Alpha Syntax, Prev: Alpha Notes, U can be represented. However, the option can still be useful in specific applications. -`-replace' -`-noreplace' +'-replace' +'-noreplace' Enables or disables the optimization of procedure calls, both at assemblage and at link time. These options are only available for - VMS targets and `-replace' is the default. See section 1.4.1 of + VMS targets and '-replace' is the default. See section 1.4.1 of the OpenVMS Linker Utility Manual. -`-g' +'-g' This option is used when the compiler generates debug information. - When `gcc' is using `mips-tfile' to generate debug information for + When 'gcc' is using 'mips-tfile' to generate debug information for ECOFF, local labels must be passed through to the object file. Otherwise this option has no effect. -`-GSIZE' - A local common symbol larger than SIZE is placed in `.bss', while - smaller symbols are placed in `.sbss'. +'-GSIZE' + A local common symbol larger than SIZE is placed in '.bss', while + smaller symbols are placed in '.sbss'. -`-F' -`-32addr' +'-F' +'-32addr' These options are ignored for backward compatibility. @@ -6019,12 +5846,12 @@ File: as.info, Node: Alpha-Chars, Next: Alpha-Regs, Up: Alpha Syntax 9.2.3.1 Special Characters .......................... -`#' is the line comment character. Note that if `#' is the first +'#' is the line comment character. Note that if '#' is the first character on a line then it can also be a logical line number directive (*note Comments::) or a preprocessor control command (*note Preprocessing::). - `;' can be used instead of a newline to separate statements. + ';' can be used instead of a newline to separate statements. File: as.info, Node: Alpha-Regs, Next: Alpha-Relocs, Prev: Alpha-Chars, Up: Alpha Syntax @@ -6032,11 +5859,11 @@ File: as.info, Node: Alpha-Regs, Next: Alpha-Relocs, Prev: Alpha-Chars, Up: 9.2.3.2 Register Names ...................... -The 32 integer registers are referred to as `$N' or `$rN'. In -addition, registers 15, 28, 29, and 30 may be referred to by the -symbols `$fp', `$at', `$gp', and `$sp' respectively. +The 32 integer registers are referred to as '$N' or '$rN'. In addition, +registers 15, 28, 29, and 30 may be referred to by the symbols '$fp', +'$at', '$gp', and '$sp' respectively. - The 32 floating-point registers are referred to as `$fN'. + The 32 floating-point registers are referred to as '$fN'. File: as.info, Node: Alpha-Relocs, Prev: Alpha-Regs, Up: Alpha Syntax @@ -6045,10 +5872,10 @@ File: as.info, Node: Alpha-Relocs, Prev: Alpha-Regs, Up: Alpha Syntax ................... Some of these relocations are available for ECOFF, but mostly only for -ELF. They are modeled after the relocation format introduced in -Digital Unix 4.0, but there are additions. +ELF. They are modeled after the relocation format introduced in Digital +Unix 4.0, but there are additions. - The format is `!TAG' or `!TAG!NUMBER' where TAG is the name of the + The format is '!TAG' or '!TAG!NUMBER' where TAG is the name of the relocation. In some cases NUMBER is used to relate specific instructions. @@ -6059,147 +5886,145 @@ instructions. ldq $1,b($29) !literal!100 ldl $2,0($1) !lituse_base!100 -`!literal' -`!literal!N' - Used with an `ldq' instruction to load the address of a symbol - from the GOT. +'!literal' +'!literal!N' + Used with an 'ldq' instruction to load the address of a symbol from + the GOT. A sequence number N is optional, and if present is used to pair - `lituse' relocations with this `literal' relocation. The `lituse' + 'lituse' relocations with this 'literal' relocation. The 'lituse' relocations are used by the linker to optimize the code based on the final location of the symbol. Note that these optimizations are dependent on the data flow of the - program. Therefore, if _any_ `lituse' is paired with a `literal' - relocation, then _all_ uses of the register set by the `literal' - instruction must also be marked with `lituse' relocations. This - is because the original `literal' instruction may be deleted or + program. Therefore, if _any_ 'lituse' is paired with a 'literal' + relocation, then _all_ uses of the register set by the 'literal' + instruction must also be marked with 'lituse' relocations. This is + because the original 'literal' instruction may be deleted or transformed into another instruction. Also note that there may be a one-to-many relationship between - `literal' and `lituse', but not a many-to-one. That is, if there - are two code paths that load up the same address and feed the - value to a single use, then the use may not use a `lituse' - relocation. + 'literal' and 'lituse', but not a many-to-one. That is, if there + are two code paths that load up the same address and feed the value + to a single use, then the use may not use a 'lituse' relocation. -`!lituse_base!N' - Used with any memory format instruction (e.g. `ldl') to indicate +'!lituse_base!N' + Used with any memory format instruction (e.g. 'ldl') to indicate that the literal is used for an address load. The offset field of the instruction must be zero. During relaxation, the code may be altered to use a gp-relative load. -`!lituse_jsr!N' - Used with a register branch format instruction (e.g. `jsr') to +'!lituse_jsr!N' + Used with a register branch format instruction (e.g. 'jsr') to indicate that the literal is used for a call. During relaxation, - the code may be altered to use a direct branch (e.g. `bsr'). + the code may be altered to use a direct branch (e.g. 'bsr'). -`!lituse_jsrdirect!N' - Similar to `lituse_jsr', but also that this call cannot be vectored +'!lituse_jsrdirect!N' + Similar to 'lituse_jsr', but also that this call cannot be vectored through a PLT entry. This is useful for functions with special calling conventions which do not allow the normal call-clobbered registers to be clobbered. -`!lituse_bytoff!N' - Used with a byte mask instruction (e.g. `extbl') to indicate that +'!lituse_bytoff!N' + Used with a byte mask instruction (e.g. 'extbl') to indicate that only the low 3 bits of the address are relevant. During relaxation, the code may be altered to use an immediate instead of a register shift. -`!lituse_addr!N' +'!lituse_addr!N' Used with any other instruction to indicate that the original - address is in fact used, and the original `ldq' instruction may - not be altered or deleted. This is useful in conjunction with - `lituse_jsr' to test whether a weak symbol is defined. + address is in fact used, and the original 'ldq' instruction may not + be altered or deleted. This is useful in conjunction with + 'lituse_jsr' to test whether a weak symbol is defined. ldq $27,foo($29) !literal!1 beq $27,is_undef !lituse_addr!1 jsr $26,($27),foo !lituse_jsr!1 -`!lituse_tlsgd!N' +'!lituse_tlsgd!N' Used with a register branch format instruction to indicate that the - literal is the call to `__tls_get_addr' used to compute the - address of the thread-local storage variable whose descriptor was - loaded with `!tlsgd!N'. + literal is the call to '__tls_get_addr' used to compute the address + of the thread-local storage variable whose descriptor was loaded + with '!tlsgd!N'. -`!lituse_tlsldm!N' +'!lituse_tlsldm!N' Used with a register branch format instruction to indicate that the - literal is the call to `__tls_get_addr' used to compute the - address of the base of the thread-local storage block for the - current module. The descriptor for the module must have been - loaded with `!tlsldm!N'. - -`!gpdisp!N' - Used with `ldah' and `lda' to load the GP from the current - address, a-la the `ldgp' macro. The source register for the - `ldah' instruction must contain the address of the `ldah' - instruction. There must be exactly one `lda' instruction paired - with the `ldah' instruction, though it may appear anywhere in the - instruction stream. The immediate operands must be zero. + literal is the call to '__tls_get_addr' used to compute the address + of the base of the thread-local storage block for the current + module. The descriptor for the module must have been loaded with + '!tlsldm!N'. + +'!gpdisp!N' + Used with 'ldah' and 'lda' to load the GP from the current address, + a-la the 'ldgp' macro. The source register for the 'ldah' + instruction must contain the address of the 'ldah' instruction. + There must be exactly one 'lda' instruction paired with the 'ldah' + instruction, though it may appear anywhere in the instruction + stream. The immediate operands must be zero. bsr $26,foo ldah $29,0($26) !gpdisp!1 lda $29,0($29) !gpdisp!1 -`!gprelhigh' - Used with an `ldah' instruction to add the high 16 bits of a - 32-bit displacement from the GP. +'!gprelhigh' + Used with an 'ldah' instruction to add the high 16 bits of a 32-bit + displacement from the GP. -`!gprellow' +'!gprellow' Used with any memory format instruction to add the low 16 bits of a 32-bit displacement from the GP. -`!gprel' +'!gprel' Used with any memory format instruction to add a 16-bit displacement from the GP. -`!samegp' +'!samegp' Used with any branch format instruction to skip the GP load at the target address. The referenced symbol must have the same GP as the - source object file, and it must be declared to either not use `$27' + source object file, and it must be declared to either not use '$27' or perform a standard GP load in the first two instructions via the - `.prologue' directive. + '.prologue' directive. -`!tlsgd' -`!tlsgd!N' - Used with an `lda' instruction to load the address of a TLS +'!tlsgd' +'!tlsgd!N' + Used with an 'lda' instruction to load the address of a TLS descriptor for a symbol in the GOT. The sequence number N is optional, and if present it used to pair - the descriptor load with both the `literal' loading the address of - the `__tls_get_addr' function and the `lituse_tlsgd' marking the + the descriptor load with both the 'literal' loading the address of + the '__tls_get_addr' function and the 'lituse_tlsgd' marking the call to that function. - For proper relaxation, both the `tlsgd', `literal' and `lituse' - relocations must be in the same extended basic block. That is, - the relocation with the lowest address must be executed first at + For proper relaxation, both the 'tlsgd', 'literal' and 'lituse' + relocations must be in the same extended basic block. That is, the + relocation with the lowest address must be executed first at runtime. -`!tlsldm' -`!tlsldm!N' - Used with an `lda' instruction to load the address of a TLS +'!tlsldm' +'!tlsldm!N' + Used with an 'lda' instruction to load the address of a TLS descriptor for the current module in the GOT. - Similar in other respects to `tlsgd'. + Similar in other respects to 'tlsgd'. -`!gotdtprel' - Used with an `ldq' instruction to load the offset of the TLS - symbol within its module's thread-local storage block. Also known - as the dynamic thread pointer offset or dtp-relative offset. +'!gotdtprel' + Used with an 'ldq' instruction to load the offset of the TLS symbol + within its module's thread-local storage block. Also known as the + dynamic thread pointer offset or dtp-relative offset. -`!dtprelhi' -`!dtprello' -`!dtprel' - Like `gprel' relocations except they compute dtp-relative offsets. +'!dtprelhi' +'!dtprello' +'!dtprel' + Like 'gprel' relocations except they compute dtp-relative offsets. -`!gottprel' - Used with an `ldq' instruction to load the offset of the TLS - symbol from the thread pointer. Also known as the tp-relative - offset. +'!gottprel' + Used with an 'ldq' instruction to load the offset of the TLS symbol + from the thread pointer. Also known as the tp-relative offset. -`!tprelhi' -`!tprello' -`!tprel' - Like `gprel' relocations except they compute tp-relative offsets. +'!tprelhi' +'!tprello' +'!tprel' + Like 'gprel' relocations except they compute tp-relative offsets. File: as.info, Node: Alpha Floating Point, Next: Alpha Directives, Prev: Alpha Syntax, Up: Alpha-Dependent @@ -6215,122 +6040,121 @@ File: as.info, Node: Alpha Directives, Next: Alpha Opcodes, Prev: Alpha Float 9.2.5 Alpha Assembler Directives -------------------------------- -`as' for the Alpha supports many additional directives for -compatibility with the native assembler. This section describes them -only briefly. +'as' for the Alpha supports many additional directives for compatibility +with the native assembler. This section describes them only briefly. - These are the additional directives in `as' for the Alpha: + These are the additional directives in 'as' for the Alpha: -`.arch CPU' - Specifies the target processor. This is equivalent to the `-mCPU' +'.arch CPU' + Specifies the target processor. This is equivalent to the '-mCPU' command-line option. *Note Options: Alpha Options, for a list of values for CPU. -`.ent FUNCTION[, N]' +'.ent FUNCTION[, N]' Mark the beginning of FUNCTION. An optional number may follow for compatibility with the OSF/1 assembler, but is ignored. When - generating `.mdebug' information, this will create a procedure + generating '.mdebug' information, this will create a procedure descriptor for the function. In ELF, it will mark the symbol as a - function a-la the generic `.type' directive. + function a-la the generic '.type' directive. -`.end FUNCTION' +'.end FUNCTION' Mark the end of FUNCTION. In ELF, it will set the size of the - symbol a-la the generic `.size' directive. + symbol a-la the generic '.size' directive. -`.mask MASK, OFFSET' +'.mask MASK, OFFSET' Indicate which of the integer registers are saved in the current function's stack frame. MASK is interpreted a bit mask in which bit N set indicates that register N is saved. The registers are saved in a block located OFFSET bytes from the "canonical frame address" (CFA) which is the value of the stack pointer on entry to the function. The registers are saved sequentially, except that - the return address register (normally `$26') is saved first. + the return address register (normally '$26') is saved first. This and the other directives that describe the stack frame are - currently only used when generating `.mdebug' information. They - may in the future be used to generate DWARF2 `.debug_frame' unwind + currently only used when generating '.mdebug' information. They + may in the future be used to generate DWARF2 '.debug_frame' unwind information for hand written assembly. -`.fmask MASK, OFFSET' +'.fmask MASK, OFFSET' Indicate which of the floating-point registers are saved in the current stack frame. The MASK and OFFSET parameters are - interpreted as with `.mask'. + interpreted as with '.mask'. -`.frame FRAMEREG, FRAMEOFFSET, RETREG[, ARGOFFSET]' +'.frame FRAMEREG, FRAMEOFFSET, RETREG[, ARGOFFSET]' Describes the shape of the stack frame. The frame pointer in use - is FRAMEREG; normally this is either `$fp' or `$sp'. The frame - pointer is FRAMEOFFSET bytes below the CFA. The return address is + is FRAMEREG; normally this is either '$fp' or '$sp'. The frame + pointer is FRAMEOFFSET bytes below the CFA. The return address is initially located in RETREG until it is saved as indicated in - `.mask'. For compatibility with OSF/1 an optional ARGOFFSET + '.mask'. For compatibility with OSF/1 an optional ARGOFFSET parameter is accepted and ignored. It is believed to indicate the offset from the CFA to the saved argument registers. -`.prologue N' +'.prologue N' Indicate that the stack frame is set up and all registers have been spilled. The argument N indicates whether and how the function uses the incoming "procedure vector" (the address of the called - function) in `$27'. 0 indicates that `$27' is not used; 1 - indicates that the first two instructions of the function use `$27' - to perform a load of the GP register; 2 indicates that `$27' is + function) in '$27'. 0 indicates that '$27' is not used; 1 + indicates that the first two instructions of the function use '$27' + to perform a load of the GP register; 2 indicates that '$27' is used in some non-standard way and so the linker cannot elide the load of the procedure vector during relaxation. -`.usepv FUNCTION, WHICH' - Used to indicate the use of the `$27' register, similar to - `.prologue', but without the other semantics of needing to be - inside an open `.ent'/`.end' block. +'.usepv FUNCTION, WHICH' + Used to indicate the use of the '$27' register, similar to + '.prologue', but without the other semantics of needing to be + inside an open '.ent'/'.end' block. - The WHICH argument should be either `no', indicating that `$27' is - not used, or `std', indicating that the first two instructions of + The WHICH argument should be either 'no', indicating that '$27' is + not used, or 'std', indicating that the first two instructions of the function perform a GP load. - One might use this directive instead of `.prologue' if you are - also using dwarf2 CFI directives. + One might use this directive instead of '.prologue' if you are also + using dwarf2 CFI directives. -`.gprel32 EXPRESSION' +'.gprel32 EXPRESSION' Computes the difference between the address in EXPRESSION and the GP for the current object file, and stores it in 4 bytes. In addition to being smaller than a full 8 byte address, this also does not require a dynamic relocation when used in a shared library. -`.t_floating EXPRESSION' +'.t_floating EXPRESSION' Stores EXPRESSION as an IEEE double precision value. -`.s_floating EXPRESSION' +'.s_floating EXPRESSION' Stores EXPRESSION as an IEEE single precision value. -`.f_floating EXPRESSION' +'.f_floating EXPRESSION' Stores EXPRESSION as a VAX F format value. -`.g_floating EXPRESSION' +'.g_floating EXPRESSION' Stores EXPRESSION as a VAX G format value. -`.d_floating EXPRESSION' +'.d_floating EXPRESSION' Stores EXPRESSION as a VAX D format value. -`.set FEATURE' +'.set FEATURE' Enables or disables various assembler features. Using the positive - name of the feature enables while using `noFEATURE' disables. + name of the feature enables while using 'noFEATURE' disables. - `at' + 'at' Indicates that macro expansions may clobber the "assembler - temporary" (`$at' or `$28') register. Some macros may not be + temporary" ('$at' or '$28') register. Some macros may not be expanded without this and will generate an error message if - `noat' is in effect. When `at' is in effect, a warning will - be generated if `$at' is used by the programmer. + 'noat' is in effect. When 'at' is in effect, a warning will + be generated if '$at' is used by the programmer. - `macro' + 'macro' Enables the expansion of macro instructions. Note that - variants of real instructions, such as `br label' vs `br + variants of real instructions, such as 'br label' vs 'br $31,label' are considered alternate forms and not macros. - `move' - `reorder' - `volatile' + 'move' + 'reorder' + 'volatile' These control whether and how the assembler may re-order instructions. Accepted for compatibility with the OSF/1 - assembler, but `as' does not do instruction scheduling, so + assembler, but 'as' does not do instruction scheduling, so these features are ignored. The following directives are recognized for compatibility with the @@ -6372,14 +6196,14 @@ File: as.info, Node: ARC Options, Next: ARC Syntax, Up: ARC-Dependent 9.3.1 Options ------------- -`-marc[5|6|7|8]' - This option selects the core processor variant. Using `-marc' is - the same as `-marc6', which is also the default. +'-marc[5|6|7|8]' + This option selects the core processor variant. Using '-marc' is + the same as '-marc6', which is also the default. - `arc5' + 'arc5' Base instruction set. - `arc6' + 'arc6' Jump-and-link (jl) instruction. No requirement of an instruction between setting flags and conditional jump. For example: @@ -6387,26 +6211,24 @@ File: as.info, Node: ARC Options, Next: ARC Syntax, Up: ARC-Dependent mov.f r0,r1 beq foo - `arc7' + 'arc7' Break (brk) and sleep (sleep) instructions. - `arc8' + 'arc8' Software interrupt (swi) instruction. - - Note: the `.option' directive can to be used to select a core + Note: the '.option' directive can to be used to select a core variant from within assembly code. -`-EB' +'-EB' This option specifies that the output generated by the assembler should be marked as being encoded for a big-endian processor. -`-EL' +'-EL' This option specifies that the output generated by the assembler should be marked as being encoded for a little-endian processor - this is the default. - File: as.info, Node: ARC Syntax, Next: ARC Floating Point, Prev: ARC Options, Up: ARC-Dependent @@ -6424,10 +6246,10 @@ File: as.info, Node: ARC-Chars, Next: ARC-Regs, Up: ARC Syntax 9.3.2.1 Special Characters .......................... -The presence of a `#' on a line indicates the start of a comment that -extends to the end of the current line. Note that if a line starts -with a `#' character then it can also be a logical line number -directive (*note Comments::) or a preprocessor control command (*note +The presence of a '#' on a line indicates the start of a comment that +extends to the end of the current line. Note that if a line starts with +a '#' character then it can also be a logical line number directive +(*note Comments::) or a preprocessor control command (*note Preprocessing::). The ARC assembler does not support a line separator character. @@ -6447,7 +6269,7 @@ File: as.info, Node: ARC Floating Point, Next: ARC Directives, Prev: ARC Synt -------------------- The ARC core does not currently have hardware floating point support. -Software floating point support is provided by `GCC' and uses IEEE +Software floating point support is provided by 'GCC' and uses IEEE floating-point numbers. @@ -6456,42 +6278,39 @@ File: as.info, Node: ARC Directives, Next: ARC Opcodes, Prev: ARC Floating Po 9.3.4 ARC Machine Directives ---------------------------- -The ARC version of `as' supports the following additional machine +The ARC version of 'as' supports the following additional machine directives: -`.2byte EXPRESSIONS' +'.2byte EXPRESSIONS' *TODO* -`.3byte EXPRESSIONS' +'.3byte EXPRESSIONS' *TODO* -`.4byte EXPRESSIONS' +'.4byte EXPRESSIONS' *TODO* -`.extAuxRegister NAME,ADDRESS,MODE' +'.extAuxRegister NAME,ADDRESS,MODE' The ARCtangent A4 has extensible auxiliary register space. The auxiliary registers can be defined in the assembler source code by using this directive. The first parameter is the NAME of the new auxiallry register. The second parameter is the ADDRESS of the register in the auxiliary register memory map for the variant of - the ARC. The third parameter specifies the MODE in which the + the ARC. The third parameter specifies the MODE in which the register can be operated is and it can be one of: - `r (readonly)' - - `w (write only)' - - `r|w (read or write)' + 'r (readonly)' + 'w (write only)' + 'r|w (read or write)' For example: .extAuxRegister mulhi,0x12,w - This specifies an extension auxiliary register called _mulhi_ - which is at address 0x12 in the memory space and which is only - writable. + This specifies an extension auxiliary register called _mulhi_ which + is at address 0x12 in the memory space and which is only writable. -`.extCondCode SUFFIX,VALUE' +'.extCondCode SUFFIX,VALUE' The condition codes on the ARCtangent A4 are extensible and can be specified by means of this assembler directive. They are specified by the suffix and the value for the condition code. They can be @@ -6503,23 +6322,20 @@ directives: add.is_busy r1,r2,r3 bis_busy _main -`.extCoreRegister NAME,REGNUM,MODE,SHORTCUT' +'.extCoreRegister NAME,REGNUM,MODE,SHORTCUT' Specifies an extension core register NAME for the application. This allows a register NAME with a valid REGNUM between 0 and 60, with the following as valid values for MODE - `_r_ (readonly)' - - `_w_ (write only)' - - `_r|w_ (read or write)' + '_r_ (readonly)' + '_w_ (write only)' + '_r|w_ (read or write)' The other parameter gives a description of the register having a SHORTCUT in the pipeline. The valid values are: - `can_shortcut' - - `cannot_shortcut' + 'can_shortcut' + 'cannot_shortcut' For example: @@ -6528,15 +6344,15 @@ directives: This defines an extension core register mlo with the value 57 which can shortcut the pipeline. -`.extInstruction NAME,OPCODE,SUBOPCODE,SUFFIXCLASS,SYNTAXCLASS' +'.extInstruction NAME,OPCODE,SUBOPCODE,SUFFIXCLASS,SYNTAXCLASS' The ARCtangent A4 allows the user to specify extension instructions. The extension instructions are not macros. The - assembler creates encodings for use of these instructions - according to the specification by the user. The parameters are: + assembler creates encodings for use of these instructions according + to the specification by the user. The parameters are: * NAME Name of the extension instruction - * OPCODE Opcode to be used. (Bits 27:31 in the encoding). + * OPCODE Opcode to be used. (Bits 27:31 in the encoding). Valid values 0x10-0x1f or 0x03 * SUBOPCODE Subopcode to be used. Valid values are from @@ -6544,20 +6360,18 @@ directives: SYNTAXCLASS * SUFFIXCLASS Determines the kinds of suffixes to be allowed. - Valid values are `SUFFIX_NONE', `SUFFIX_COND', `SUFFIX_FLAG' + Valid values are 'SUFFIX_NONE', 'SUFFIX_COND', 'SUFFIX_FLAG' which indicates the absence or presence of conditional - suffixes and flag setting by the extension instruction. It - is also possible to specify that an instruction sets the - flags and is conditional by using `SUFFIX_CODE' | - `SUFFIX_FLAG'. + suffixes and flag setting by the extension instruction. It is + also possible to specify that an instruction sets the flags + and is conditional by using 'SUFFIX_CODE' | 'SUFFIX_FLAG'. * SYNTAXCLASS Determines the syntax class for the instruction. It can have the following values: - ``SYNTAX_2OP':' + 'SYNTAX_2OP:' 2 Operand Instruction - - ``SYNTAX_3OP':' + 'SYNTAX_3OP:' 3 Operand Instruction In addition there could be modifiers for the syntax class as @@ -6565,7 +6379,7 @@ directives: Syntax Class Modifiers are: - - `OP1_MUST_BE_IMM': Modifies syntax class SYNTAX_3OP, + - 'OP1_MUST_BE_IMM': Modifies syntax class SYNTAX_3OP, specifying that the first operand of a three-operand instruction must be an immediate (i.e., the result is discarded). OP1_MUST_BE_IMM is used by bitwise ORing it @@ -6573,7 +6387,7 @@ directives: could usually be used to set the flags using specific instructions and not retain results. - - `OP1_IMM_IMPLIED': Modifies syntax class SYNTAX_20P, it + - 'OP1_IMM_IMPLIED': Modifies syntax class SYNTAX_20P, it specifies that there is an implied immediate destination operand which does not appear in the syntax. For example, if the source code contains an instruction like: @@ -6586,7 +6400,6 @@ directives: You use OP1_IMM_IMPLIED by bitwise ORing it with SYNTAX_20P. - For example, defining 64-bit multiplier with immediate operands: .extInstruction mp64,0x14,0x0,SUFFIX_COND | SUFFIX_FLAG , @@ -6594,8 +6407,8 @@ directives: The above specifies an extension instruction called mp64 which has 3 operands, sets the flags, can be used with a condition code, for - which the first operand is an immediate. (Equivalent to - discarding the result of the operation). + which the first operand is an immediate. (Equivalent to discarding + the result of the operation). .extInstruction mul64,0x14,0x00,SUFFIX_COND, SYNTAX_2OP|OP1_IMM_IMPLIED @@ -6603,35 +6416,34 @@ directives: immediate operand. The result of this operation would be discarded. -`.half EXPRESSIONS' +'.half EXPRESSIONS' *TODO* -`.long EXPRESSIONS' +'.long EXPRESSIONS' *TODO* -`.option ARC|ARC5|ARC6|ARC7|ARC8' - The `.option' directive must be followed by the desired core - version. Again `arc' is an alias for `arc6'. +'.option ARC|ARC5|ARC6|ARC7|ARC8' + The '.option' directive must be followed by the desired core + version. Again 'arc' is an alias for 'arc6'. - Note: the `.option' directive overrides the command line option - `-marc'; a warning is emitted when the version is not consistent + Note: the '.option' directive overrides the command line option + '-marc'; a warning is emitted when the version is not consistent between the two - even for the implicit default core version (arc6). -`.short EXPRESSIONS' +'.short EXPRESSIONS' *TODO* -`.word EXPRESSIONS' +'.word EXPRESSIONS' *TODO* - File: as.info, Node: ARC Opcodes, Prev: ARC Directives, Up: ARC-Dependent 9.3.5 Opcodes ------------- -For information on the ARC instruction set, see `ARC Programmers +For information on the ARC instruction set, see 'ARC Programmers Reference Manual', ARC International (www.arc.com) @@ -6656,96 +6468,97 @@ File: as.info, Node: ARM Options, Next: ARM Syntax, Up: ARM-Dependent 9.4.1 Options ------------- -`-mcpu=PROCESSOR[+EXTENSION...]' +'-mcpu=PROCESSOR[+EXTENSION...]' This option specifies the target processor. The assembler will issue an error message if an attempt is made to assemble an instruction which will not execute on the target processor. The - following processor names are recognized: `arm1', `arm2', `arm250', - `arm3', `arm6', `arm60', `arm600', `arm610', `arm620', `arm7', - `arm7m', `arm7d', `arm7dm', `arm7di', `arm7dmi', `arm70', `arm700', - `arm700i', `arm710', `arm710t', `arm720', `arm720t', `arm740t', - `arm710c', `arm7100', `arm7500', `arm7500fe', `arm7t', `arm7tdmi', - `arm7tdmi-s', `arm8', `arm810', `strongarm', `strongarm1', - `strongarm110', `strongarm1100', `strongarm1110', `arm9', `arm920', - `arm920t', `arm922t', `arm940t', `arm9tdmi', `fa526' (Faraday - FA526 processor), `fa626' (Faraday FA626 processor), `arm9e', - `arm926e', `arm926ej-s', `arm946e-r0', `arm946e', `arm946e-s', - `arm966e-r0', `arm966e', `arm966e-s', `arm968e-s', `arm10t', - `arm10tdmi', `arm10e', `arm1020', `arm1020t', `arm1020e', - `arm1022e', `arm1026ej-s', `fa606te' (Faraday FA606TE processor), - `fa616te' (Faraday FA616TE processor), `fa626te' (Faraday FA626TE - processor), `fmp626' (Faraday FMP626 processor), `fa726te' - (Faraday FA726TE processor), `arm1136j-s', `arm1136jf-s', - `arm1156t2-s', `arm1156t2f-s', `arm1176jz-s', `arm1176jzf-s', - `mpcore', `mpcorenovfp', `cortex-a5', `cortex-a7', `cortex-a8', - `cortex-a9', `cortex-a15', `cortex-r4', `cortex-r4f', `cortex-r5', - `cortex-r7', `cortex-m4', `cortex-m3', `cortex-m1', `cortex-m0', - `cortex-m0plus', `ep9312' (ARM920 with Cirrus Maverick - coprocessor), `i80200' (Intel XScale processor) `iwmmxt' (Intel(r) + following processor names are recognized: 'arm1', 'arm2', 'arm250', + 'arm3', 'arm6', 'arm60', 'arm600', 'arm610', 'arm620', 'arm7', + 'arm7m', 'arm7d', 'arm7dm', 'arm7di', 'arm7dmi', 'arm70', 'arm700', + 'arm700i', 'arm710', 'arm710t', 'arm720', 'arm720t', 'arm740t', + 'arm710c', 'arm7100', 'arm7500', 'arm7500fe', 'arm7t', 'arm7tdmi', + 'arm7tdmi-s', 'arm8', 'arm810', 'strongarm', 'strongarm1', + 'strongarm110', 'strongarm1100', 'strongarm1110', 'arm9', 'arm920', + 'arm920t', 'arm922t', 'arm940t', 'arm9tdmi', 'fa526' (Faraday FA526 + processor), 'fa626' (Faraday FA626 processor), 'arm9e', 'arm926e', + 'arm926ej-s', 'arm946e-r0', 'arm946e', 'arm946e-s', 'arm966e-r0', + 'arm966e', 'arm966e-s', 'arm968e-s', 'arm10t', 'arm10tdmi', + 'arm10e', 'arm1020', 'arm1020t', 'arm1020e', 'arm1022e', + 'arm1026ej-s', 'fa606te' (Faraday FA606TE processor), 'fa616te' + (Faraday FA616TE processor), 'fa626te' (Faraday FA626TE processor), + 'fmp626' (Faraday FMP626 processor), 'fa726te' (Faraday FA726TE + processor), 'arm1136j-s', 'arm1136jf-s', 'arm1156t2-s', + 'arm1156t2f-s', 'arm1176jz-s', 'arm1176jzf-s', 'mpcore', + 'mpcorenovfp', 'cortex-a5', 'cortex-a7', 'cortex-a8', 'cortex-a9', + 'cortex-a15', 'cortex-r4', 'cortex-r4f', 'cortex-r5', 'cortex-r7', + 'cortex-m4', 'cortex-m3', 'cortex-m1', 'cortex-m0', + 'cortex-m0plus', 'ep9312' (ARM920 with Cirrus Maverick + coprocessor), 'i80200' (Intel XScale processor) 'iwmmxt' (Intel(r) XScale processor with Wireless MMX(tm) technology coprocessor) and - `xscale'. The special name `all' may be used to allow the + 'xscale'. The special name 'all' may be used to allow the assembler to accept instructions valid for any ARM processor. - In addition to the basic instruction set, the assembler can be - told to accept various extension mnemonics that extend the - processor using the co-processor instruction space. For example, - `-mcpu=arm920+maverick' is equivalent to specifying `-mcpu=ep9312'. + In addition to the basic instruction set, the assembler can be told + to accept various extension mnemonics that extend the processor + using the co-processor instruction space. For example, + '-mcpu=arm920+maverick' is equivalent to specifying '-mcpu=ep9312'. - Multiple extensions may be specified, separated by a `+'. The + Multiple extensions may be specified, separated by a '+'. The extensions should be specified in ascending alphabetical order. - Some extensions may be restricted to particular architectures; - this is documented in the list of extensions below. + Some extensions may be restricted to particular architectures; this + is documented in the list of extensions below. Extension mnemonics may also be removed from those the assembler - accepts. This is done be prepending `no' to the option that adds + accepts. This is done be prepending 'no' to the option that adds the extension. Extensions that are removed should be listed after all extensions which have been added, again in ascending - alphabetical order. For example, `-mcpu=ep9312+nomaverick' is - equivalent to specifying `-mcpu=arm920'. + alphabetical order. For example, '-mcpu=ep9312+nomaverick' is + equivalent to specifying '-mcpu=arm920'. - The following extensions are currently supported: `crypto' - (Cryptography Extensions for v8-A architecture, implies `fp+simd'), - `fp' (Floating Point Extensions for v8-A architecture), `idiv' + The following extensions are currently supported: 'crypto' + (Cryptography Extensions for v8-A architecture, implies 'fp+simd'), + 'fp' (Floating Point Extensions for v8-A architecture), 'idiv' (Integer Divide Extensions for v7-A and v7-R architectures), - `iwmmxt', `iwmmxt2', `maverick', `mp' (Multiprocessing Extensions - for v7-A and v7-R architectures), `os' (Operating System for v6M - architecture), `sec' (Security Extensions for v6K and v7-A - architectures), `simd' (Advanced SIMD Extensions for v8-A - architecture, implies `fp'), `virt' (Virtualization Extensions for - v7-A architecture, implies `idiv'), and `xscale'. - -`-march=ARCHITECTURE[+EXTENSION...]' + 'iwmmxt', 'iwmmxt2', 'maverick', 'mp' (Multiprocessing Extensions + for v7-A and v7-R architectures), 'os' (Operating System for v6M + architecture), 'sec' (Security Extensions for v6K and v7-A + architectures), 'simd' (Advanced SIMD Extensions for v8-A + architecture, implies 'fp'), 'virt' (Virtualization Extensions for + v7-A architecture, implies 'idiv'), and 'xscale'. + +'-march=ARCHITECTURE[+EXTENSION...]' This option specifies the target architecture. The assembler will issue an error message if an attempt is made to assemble an - instruction which will not execute on the target architecture. - The following architecture names are recognized: `armv1', `armv2', - `armv2a', `armv2s', `armv3', `armv3m', `armv4', `armv4xm', - `armv4t', `armv4txm', `armv5', `armv5t', `armv5txm', `armv5te', - `armv5texp', `armv6', `armv6j', `armv6k', `armv6z', `armv6zk', - `armv6-m', `armv6s-m', `armv7', `armv7-a', `armv7-r', `armv7-m', - `armv7e-m', `armv8-a', `iwmmxt' and `xscale'. If both `-mcpu' and - `-march' are specified, the assembler will use the setting for - `-mcpu'. + instruction which will not execute on the target architecture. The + following architecture names are recognized: 'armv1', 'armv2', + 'armv2a', 'armv2s', 'armv3', 'armv3m', 'armv4', 'armv4xm', + 'armv4t', 'armv4txm', 'armv5', 'armv5t', 'armv5txm', 'armv5te', + 'armv5texp', 'armv6', 'armv6j', 'armv6k', 'armv6z', 'armv6zk', + 'armv6-m', 'armv6s-m', 'armv7', 'armv7-a', 'armv7ve', 'armv7-r', + 'armv7-m', 'armv7e-m', 'armv8-a', 'iwmmxt' and 'xscale'. If both + '-mcpu' and '-march' are specified, the assembler will use the + setting for '-mcpu'. The architecture option can be extended with the same instruction - set extension options as the `-mcpu' option. + set extension options as the '-mcpu' option. + +'-mfpu=FLOATING-POINT-FORMAT' -`-mfpu=FLOATING-POINT-FORMAT' This option specifies the floating point format to assemble for. The assembler will issue an error message if an attempt is made to assemble an instruction which will not execute on the target floating point unit. The following format options are recognized: - `softfpa', `fpe', `fpe2', `fpe3', `fpa', `fpa10', `fpa11', - `arm7500fe', `softvfp', `softvfp+vfp', `vfp', `vfp10', `vfp10-r0', - `vfp9', `vfpxd', `vfpv2', `vfpv3', `vfpv3-fp16', `vfpv3-d16', - `vfpv3-d16-fp16', `vfpv3xd', `vfpv3xd-d16', `vfpv4', `vfpv4-d16', - `fpv4-sp-d16', `fp-armv8', `arm1020t', `arm1020e', `arm1136jf-s', - `maverick', `neon', `neon-vfpv4', `neon-fp-armv8', and - `crypto-neon-fp-armv8'. + 'softfpa', 'fpe', 'fpe2', 'fpe3', 'fpa', 'fpa10', 'fpa11', + 'arm7500fe', 'softvfp', 'softvfp+vfp', 'vfp', 'vfp10', 'vfp10-r0', + 'vfp9', 'vfpxd', 'vfpv2', 'vfpv3', 'vfpv3-fp16', 'vfpv3-d16', + 'vfpv3-d16-fp16', 'vfpv3xd', 'vfpv3xd-d16', 'vfpv4', 'vfpv4-d16', + 'fpv4-sp-d16', 'fp-armv8', 'arm1020t', 'arm1020e', 'arm1136jf-s', + 'maverick', 'neon', 'neon-vfpv4', 'neon-fp-armv8', and + 'crypto-neon-fp-armv8'. In addition to determining which instructions are assembled, this - option also affects the way in which the `.double' assembler + option also affects the way in which the '.double' assembler directive behaves when assembling little-endian code. The default is dependent on the processor selected. For @@ -6753,86 +6566,85 @@ File: as.info, Node: ARM Options, Next: ARM Syntax, Up: ARM-Dependent instructions; for earlier architectures the default is to assemble for FPA instructions. -`-mthumb' +'-mthumb' This option specifies that the assembler should start assembling Thumb instructions; that is, it should behave as though the file - starts with a `.code 16' directive. + starts with a '.code 16' directive. -`-mthumb-interwork' +'-mthumb-interwork' This option specifies that the output generated by the assembler should be marked as supporting interworking. -`-mimplicit-it=never' -`-mimplicit-it=always' -`-mimplicit-it=arm' -`-mimplicit-it=thumb' - The `-mimplicit-it' option controls the behavior of the assembler - when conditional instructions are not enclosed in IT blocks. - There are four possible behaviors. If `never' is specified, such +'-mimplicit-it=never' +'-mimplicit-it=always' +'-mimplicit-it=arm' +'-mimplicit-it=thumb' + The '-mimplicit-it' option controls the behavior of the assembler + when conditional instructions are not enclosed in IT blocks. There + are four possible behaviors. If 'never' is specified, such constructs cause a warning in ARM code and an error in Thumb-2 - code. If `always' is specified, such constructs are accepted in + code. If 'always' is specified, such constructs are accepted in both ARM and Thumb-2 code, where the IT instruction is added - implicitly. If `arm' is specified, such constructs are accepted - in ARM code and cause an error in Thumb-2 code. If `thumb' is + implicitly. If 'arm' is specified, such constructs are accepted in + ARM code and cause an error in Thumb-2 code. If 'thumb' is specified, such constructs cause a warning in ARM code and are - accepted in Thumb-2 code. If you omit this option, the behavior - is equivalent to `-mimplicit-it=arm'. + accepted in Thumb-2 code. If you omit this option, the behavior is + equivalent to '-mimplicit-it=arm'. -`-mapcs-26' -`-mapcs-32' +'-mapcs-26' +'-mapcs-32' These options specify that the output generated by the assembler should be marked as supporting the indicated version of the Arm Procedure. Calling Standard. -`-matpcs' +'-matpcs' This option specifies that the output generated by the assembler should be marked as supporting the Arm/Thumb Procedure Calling Standard. If enabled this option will cause the assembler to create an empty debugging section in the object file called - .arm.atpcs. Debuggers can use this to determine the ABI being - used by. + .arm.atpcs. Debuggers can use this to determine the ABI being used + by. -`-mapcs-float' +'-mapcs-float' This indicates the floating point variant of the APCS should be used. In this variant floating point arguments are passed in FP registers rather than integer registers. -`-mapcs-reentrant' +'-mapcs-reentrant' This indicates that the reentrant variant of the APCS should be used. This variant supports position independent code. -`-mfloat-abi=ABI' +'-mfloat-abi=ABI' This option specifies that the output generated by the assembler - should be marked as using specified floating point ABI. The - following values are recognized: `soft', `softfp' and `hard'. + should be marked as using specified floating point ABI. The + following values are recognized: 'soft', 'softfp' and 'hard'. -`-meabi=VER' +'-meabi=VER' This option specifies which EABI version the produced object files - should conform to. The following values are recognized: `gnu', `4' - and `5'. + should conform to. The following values are recognized: 'gnu', '4' + and '5'. -`-EB' +'-EB' This option specifies that the output generated by the assembler should be marked as being encoded for a big-endian processor. -`-EL' +'-EL' This option specifies that the output generated by the assembler should be marked as being encoded for a little-endian processor. -`-k' +'-k' This option specifies that the output of the assembler should be marked as position-independent code (PIC). -`--fix-v4bx' - Allow `BX' instructions in ARMv4 code. This is intended for use +'--fix-v4bx' + Allow 'BX' instructions in ARMv4 code. This is intended for use with the linker option of the same name. -`-mwarn-deprecated' -`-mno-warn-deprecated' +'-mwarn-deprecated' +'-mno-warn-deprecated' Enable or disable warnings about using deprecated options or features. The default is to warn. - File: as.info, Node: ARM Syntax, Next: ARM Floating Point, Prev: ARM Options, Up: ARM-Dependent @@ -6854,29 +6666,28 @@ File: as.info, Node: ARM-Instruction-Set, Next: ARM-Chars, Up: ARM Syntax .............................. Two slightly different syntaxes are support for ARM and THUMB -instructions. The default, `divided', uses the old style where ARM and -THUMB instructions had their own, separate syntaxes. The new, -`unified' syntax, which can be selected via the `.syntax' directive, -and has the following main features: +instructions. The default, 'divided', uses the old style where ARM and +THUMB instructions had their own, separate syntaxes. The new, 'unified' +syntax, which can be selected via the '.syntax' directive, and has the +following main features: - * Immediate operands do not require a `#' prefix. + * Immediate operands do not require a '#' prefix. - * The `IT' instruction may appear, and if it does it is validated + * The 'IT' instruction may appear, and if it does it is validated against subsequent conditional affixes. In ARM mode it does not generate machine code, in THUMB mode it does. * For ARM instructions the conditional affixes always appear at the - end of the instruction. For THUMB instructions conditional - affixes can be used, but only inside the scope of an `IT' - instruction. + end of the instruction. For THUMB instructions conditional affixes + can be used, but only inside the scope of an 'IT' instruction. * All of the instructions new to the V6T2 architecture (and later) are available. (Only a few such instructions can be written in the - `divided' syntax). + 'divided' syntax). - * The `.N' and `.W' suffixes are recognized and honored. + * The '.N' and '.W' suffixes are recognized and honored. - * All instructions set the flags if and only if they have an `s' + * All instructions set the flags if and only if they have an 's' affix. @@ -6885,18 +6696,18 @@ File: as.info, Node: ARM-Chars, Next: ARM-Regs, Prev: ARM-Instruction-Set, U 9.4.2.2 Special Characters .......................... -The presence of a `@' anywhere on a line indicates the start of a +The presence of a '@' anywhere on a line indicates the start of a comment that extends to the end of that line. - If a `#' appears as the first character of a line then the whole -line is treated as a comment, but in this case the line could also be a + If a '#' appears as the first character of a line then the whole line +is treated as a comment, but in this case the line could also be a logical line number directive (*note Comments::) or a preprocessor control command (*note Preprocessing::). - The `;' character can be used instead of a newline to separate + The ';' character can be used instead of a newline to separate statements. - Either `#' or `$' can be used to indicate immediate operands. + Either '#' or '$' can be used to indicate immediate operands. *TODO* Explain about /data modifier on symbols. @@ -6919,19 +6730,19 @@ name in parentheses after the symbol name. For example: .word foo(TARGET1) - This will generate an `R_ARM_TARGET1' relocation against the symbol -FOO. The following relocations are supported: `GOT', `GOTOFF', -`TARGET1', `TARGET2', `SBREL', `TLSGD', `TLSLDM', `TLSLDO', `TLSDESC', -`TLSCALL', `GOTTPOFF', `GOT_PREL' and `TPOFF'. + This will generate an 'R_ARM_TARGET1' relocation against the symbol +FOO. The following relocations are supported: 'GOT', 'GOTOFF', +'TARGET1', 'TARGET2', 'SBREL', 'TLSGD', 'TLSLDM', 'TLSLDO', 'TLSDESC', +'TLSCALL', 'GOTTPOFF', 'GOT_PREL' and 'TPOFF'. For compatibility with older toolchains the assembler also accepts -`(PLT)' after branch targets. On legacy targets this will generate the -deprecated `R_ARM_PLT32' relocation. On EABI targets it will encode -either the `R_ARM_CALL' or `R_ARM_JUMP24' relocation, as appropriate. +'(PLT)' after branch targets. On legacy targets this will generate the +deprecated 'R_ARM_PLT32' relocation. On EABI targets it will encode +either the 'R_ARM_CALL' or 'R_ARM_JUMP24' relocation, as appropriate. - Relocations for `MOVW' and `MOVT' instructions can be generated by -prefixing the value with `#:lower16:' and `#:upper16' respectively. -For example to load the 32-bit address of foo into r0: + Relocations for 'MOVW' and 'MOVT' instructions can be generated by +prefixing the value with '#:lower16:' and '#:upper16' respectively. For +example to load the 32-bit address of foo into r0: MOVW r0, #:lower16:foo MOVT r0, #:upper16:foo @@ -6943,9 +6754,9 @@ File: as.info, Node: ARM-Neon-Alignment, Prev: ARM-Relocations, Up: ARM Synta ................................. Some NEON load/store instructions allow an optional address alignment -qualifier. The ARM documentation specifies that this is indicated by -`@ ALIGN'. However GAS already interprets the `@' character as a "line -comment" start, so `: ALIGN' is used instead. For example: +qualifier. The ARM documentation specifies that this is indicated by '@ +ALIGN'. However GAS already interprets the '@' character as a "line +comment" start, so ': ALIGN' is used instead. For example: vld1.8 {q0}, [r0, :128] @@ -6963,71 +6774,71 @@ File: as.info, Node: ARM Directives, Next: ARM Opcodes, Prev: ARM Floating Po 9.4.4 ARM Machine Directives ---------------------------- -`.2byte EXPRESSION [, EXPRESSION]*' -`.4byte EXPRESSION [, EXPRESSION]*' -`.8byte EXPRESSION [, EXPRESSION]*' +'.2byte EXPRESSION [, EXPRESSION]*' +'.4byte EXPRESSION [, EXPRESSION]*' +'.8byte EXPRESSION [, EXPRESSION]*' These directives write 2, 4 or 8 byte values to the output section. -`.align EXPRESSION [, EXPRESSION]' +'.align EXPRESSION [, EXPRESSION]' This is the generic .ALIGN directive. For the ARM however if the first argument is zero (ie no alignment is needed) the assembler will behave as if the argument had been 2 (ie pad to the next four byte boundary). This is for compatibility with ARM's own assembler. -`.arch NAME' - Select the target architecture. Valid values for NAME are the - same as for the `-march' commandline option. +'.arch NAME' + Select the target architecture. Valid values for NAME are the same + as for the '-march' commandline option. - Specifying `.arch' clears any previously selected architecture + Specifying '.arch' clears any previously selected architecture extensions. -`.arch_extension NAME' - Add or remove an architecture extension to the target - architecture. Valid values for NAME are the same as those - accepted as architectural extensions by the `-mcpu' commandline - option. +'.arch_extension NAME' + Add or remove an architecture extension to the target architecture. + Valid values for NAME are the same as those accepted as + architectural extensions by the '-mcpu' commandline option. - `.arch_extension' may be used multiple times to add or remove + '.arch_extension' may be used multiple times to add or remove extensions incrementally to the architecture being compiled for. -`.arm' +'.arm' This performs the same action as .CODE 32. -`.pad #COUNT' +'.pad #COUNT' Generate unwinder annotations for a stack adjustment of COUNT bytes. A positive value indicates the function prologue allocated stack space by decrementing the stack pointer. -`.bss' - This directive switches to the `.bss' section. +'.bss' + This directive switches to the '.bss' section. -`.cantunwind' +'.cantunwind' Prevents unwinding through the current function. No personality routine or exception table data is required or permitted. -`.code `[16|32]'' - This directive selects the instruction set being generated. The +'.code [16|32]' + This directive selects the instruction set being generated. The value 16 selects Thumb, with the value 32 selecting ARM. -`.cpu NAME' +'.cpu NAME' Select the target processor. Valid values for NAME are the same as - for the `-mcpu' commandline option. + for the '-mcpu' commandline option. - Specifying `.cpu' clears any previously selected architecture + Specifying '.cpu' clears any previously selected architecture extensions. -`NAME .dn REGISTER NAME [.TYPE] [[INDEX]]' -`NAME .qn REGISTER NAME [.TYPE] [[INDEX]]' - The `dn' and `qn' directives are used to create typed and/or +'NAME .dn REGISTER NAME [.TYPE] [[INDEX]]' +'NAME .qn REGISTER NAME [.TYPE] [[INDEX]]' + + The 'dn' and 'qn' directives are used to create typed and/or indexed register aliases for use in Advanced SIMD Extension (Neon) instructions. The former should be used to create aliases of double-precision registers, and the latter to create aliases of quad-precision registers. - If these directives are used to create typed aliases, those - aliases can be used in Neon instructions instead of writing types - after the mnemonic or after each operand. For example: + If these directives are used to create typed aliases, those aliases + can be used in Neon instructions instead of writing types after the + mnemonic or after each operand. For example: x .dn d2.f32 y .dn d3.f32 @@ -7038,135 +6849,134 @@ File: as.info, Node: ARM Directives, Next: ARM Opcodes, Prev: ARM Floating Po vmul.f32 d2,d3,d4[1] - Aliases created using `dn' or `qn' can be destroyed using `unreq'. + Aliases created using 'dn' or 'qn' can be destroyed using 'unreq'. -`.eabi_attribute TAG, VALUE' +'.eabi_attribute TAG, VALUE' Set the EABI object attribute TAG to VALUE. The TAG is either an attribute number, or one of the following: - `Tag_CPU_raw_name', `Tag_CPU_name', `Tag_CPU_arch', - `Tag_CPU_arch_profile', `Tag_ARM_ISA_use', `Tag_THUMB_ISA_use', - `Tag_FP_arch', `Tag_WMMX_arch', `Tag_Advanced_SIMD_arch', - `Tag_PCS_config', `Tag_ABI_PCS_R9_use', `Tag_ABI_PCS_RW_data', - `Tag_ABI_PCS_RO_data', `Tag_ABI_PCS_GOT_use', - `Tag_ABI_PCS_wchar_t', `Tag_ABI_FP_rounding', - `Tag_ABI_FP_denormal', `Tag_ABI_FP_exceptions', - `Tag_ABI_FP_user_exceptions', `Tag_ABI_FP_number_model', - `Tag_ABI_align_needed', `Tag_ABI_align_preserved', - `Tag_ABI_enum_size', `Tag_ABI_HardFP_use', `Tag_ABI_VFP_args', - `Tag_ABI_WMMX_args', `Tag_ABI_optimization_goals', - `Tag_ABI_FP_optimization_goals', `Tag_compatibility', - `Tag_CPU_unaligned_access', `Tag_FP_HP_extension', - `Tag_ABI_FP_16bit_format', `Tag_MPextension_use', `Tag_DIV_use', - `Tag_nodefaults', `Tag_also_compatible_with', `Tag_conformance', - `Tag_T2EE_use', `Tag_Virtualization_use' - - The VALUE is either a `number', `"string"', or `number, "string"' + 'Tag_CPU_raw_name', 'Tag_CPU_name', 'Tag_CPU_arch', + 'Tag_CPU_arch_profile', 'Tag_ARM_ISA_use', 'Tag_THUMB_ISA_use', + 'Tag_FP_arch', 'Tag_WMMX_arch', 'Tag_Advanced_SIMD_arch', + 'Tag_PCS_config', 'Tag_ABI_PCS_R9_use', 'Tag_ABI_PCS_RW_data', + 'Tag_ABI_PCS_RO_data', 'Tag_ABI_PCS_GOT_use', + 'Tag_ABI_PCS_wchar_t', 'Tag_ABI_FP_rounding', + 'Tag_ABI_FP_denormal', 'Tag_ABI_FP_exceptions', + 'Tag_ABI_FP_user_exceptions', 'Tag_ABI_FP_number_model', + 'Tag_ABI_align_needed', 'Tag_ABI_align_preserved', + 'Tag_ABI_enum_size', 'Tag_ABI_HardFP_use', 'Tag_ABI_VFP_args', + 'Tag_ABI_WMMX_args', 'Tag_ABI_optimization_goals', + 'Tag_ABI_FP_optimization_goals', 'Tag_compatibility', + 'Tag_CPU_unaligned_access', 'Tag_FP_HP_extension', + 'Tag_ABI_FP_16bit_format', 'Tag_MPextension_use', 'Tag_DIV_use', + 'Tag_nodefaults', 'Tag_also_compatible_with', 'Tag_conformance', + 'Tag_T2EE_use', 'Tag_Virtualization_use' + + The VALUE is either a 'number', '"string"', or 'number, "string"' depending on the tag. Note - the following legacy values are also accepted by TAG: - `Tag_VFP_arch', `Tag_ABI_align8_needed', - `Tag_ABI_align8_preserved', `Tag_VFP_HP_extension', + 'Tag_VFP_arch', 'Tag_ABI_align8_needed', + 'Tag_ABI_align8_preserved', 'Tag_VFP_HP_extension', -`.even' +'.even' This directive aligns to an even-numbered address. -`.extend EXPRESSION [, EXPRESSION]*' -`.ldouble EXPRESSION [, EXPRESSION]*' +'.extend EXPRESSION [, EXPRESSION]*' +'.ldouble EXPRESSION [, EXPRESSION]*' These directives write 12byte long double floating-point values to the output section. These are not compatible with current ARM processors or ABIs. -`.fnend' - Marks the end of a function with an unwind table entry. The - unwind index table entry is created when this directive is - processed. +'.fnend' + Marks the end of a function with an unwind table entry. The unwind + index table entry is created when this directive is processed. If no personality routine has been specified then standard - personality routine 0 or 1 will be used, depending on the number - of unwind opcodes required. + personality routine 0 or 1 will be used, depending on the number of + unwind opcodes required. -`.fnstart' +'.fnstart' Marks the start of a function with an unwind table entry. -`.force_thumb' +'.force_thumb' This directive forces the selection of Thumb instructions, even if the target processor does not support those instructions -`.fpu NAME' +'.fpu NAME' Select the floating-point unit to assemble for. Valid values for - NAME are the same as for the `-mfpu' commandline option. + NAME are the same as for the '-mfpu' commandline option. -`.handlerdata' +'.handlerdata' Marks the end of the current function, and the start of the exception table entry for that function. Anything between this - directive and the `.fnend' directive will be added to the - exception table entry. + directive and the '.fnend' directive will be added to the exception + table entry. - Must be preceded by a `.personality' or `.personalityindex' + Must be preceded by a '.personality' or '.personalityindex' directive. -`.inst OPCODE [ , ... ]' -`.inst.n OPCODE [ , ... ]' -`.inst.w OPCODE [ , ... ]' +'.inst OPCODE [ , ... ]' +'.inst.n OPCODE [ , ... ]' +'.inst.w OPCODE [ , ... ]' Generates the instruction corresponding to the numerical value - OPCODE. `.inst.n' and `.inst.w' allow the Thumb instruction size + OPCODE. '.inst.n' and '.inst.w' allow the Thumb instruction size to be specified explicitly, overriding the normal encoding rules. -`.ldouble EXPRESSION [, EXPRESSION]*' - See `.extend'. +'.ldouble EXPRESSION [, EXPRESSION]*' + See '.extend'. -`.ltorg' +'.ltorg' This directive causes the current contents of the literal pool to be dumped into the current section (which is assumed to be the .text section) at the current location (aligned to a word - boundary). `GAS' maintains a separate literal pool for each - section and each sub-section. The `.ltorg' directive will only - affect the literal pool of the current section and sub-section. - At the end of assembly all remaining, un-empty literal pools will + boundary). 'GAS' maintains a separate literal pool for each + section and each sub-section. The '.ltorg' directive will only + affect the literal pool of the current section and sub-section. At + the end of assembly all remaining, un-empty literal pools will automatically be dumped. - Note - older versions of `GAS' would dump the current literal pool + Note - older versions of 'GAS' would dump the current literal pool any time a section change occurred. This is no longer done, since it prevents accurate control of the placement of literal pools. -`.movsp REG [, #OFFSET]' +'.movsp REG [, #OFFSET]' Tell the unwinder that REG contains an offset from the current stack pointer. If OFFSET is not specified then it is assumed to be zero. -`.object_arch NAME' +'.object_arch NAME' Override the architecture recorded in the EABI object attribute - section. Valid values for NAME are the same as for the `.arch' + section. Valid values for NAME are the same as for the '.arch' directive. Typically this is useful when code uses runtime detection of CPU features. -`.packed EXPRESSION [, EXPRESSION]*' +'.packed EXPRESSION [, EXPRESSION]*' This directive writes 12-byte packed floating-point values to the output section. These are not compatible with current ARM processors or ABIs. -`.pad #COUNT' +'.pad #COUNT' Generate unwinder annotations for a stack adjustment of COUNT bytes. A positive value indicates the function prologue allocated stack space by decrementing the stack pointer. -`.personality NAME' +'.personality NAME' Sets the personality routine for the current function to NAME. -`.personalityindex INDEX' +'.personalityindex INDEX' Sets the personality routine for the current function to the EABI standard routine number INDEX -`.pool' +'.pool' This is a synonym for .ltorg. -`NAME .req REGISTER NAME' +'NAME .req REGISTER NAME' This creates an alias for REGISTER NAME called NAME. For example: foo .req r0 -`.save REGLIST' +'.save REGLIST' Generate unwinder annotations to restore the registers in REGLIST. The format of REGLIST is the same as the corresponding store-multiple instruction. @@ -7190,13 +7000,13 @@ File: as.info, Node: ARM Directives, Next: ARM Opcodes, Prev: ARM Floating Po .save wr10 wstrd wr10, [sp, #-8]! -`.setfp FPREG, SPREG [, #OFFSET]' - Make all unwinder annotations relative to a frame pointer. - Without this the unwinder will use offsets from the stack pointer. +'.setfp FPREG, SPREG [, #OFFSET]' + Make all unwinder annotations relative to a frame pointer. Without + this the unwinder will use offsets from the stack pointer. - The syntax of this directive is the same as the `add' or `mov' + The syntax of this directive is the same as the 'add' or 'mov' instruction used to set the frame pointer. SPREG must be either - `sp' or mentioned in a previous `.movsp' directive. + 'sp' or mentioned in a previous '.movsp' directive. .movsp ip mov ip, sp @@ -7204,44 +7014,44 @@ File: as.info, Node: ARM Directives, Next: ARM Opcodes, Prev: ARM Floating Po .setfp fp, ip, #4 add fp, ip, #4 -`.secrel32 EXPRESSION [, EXPRESSION]*' +'.secrel32 EXPRESSION [, EXPRESSION]*' This directive emits relocations that evaluate to the section-relative offset of each expression's symbol. This directive is only supported for PE targets. -`.syntax [`unified' | `divided']' +'.syntax [unified | divided]' This directive sets the Instruction Set Syntax as described in the *note ARM-Instruction-Set:: section. -`.thumb' +'.thumb' This performs the same action as .CODE 16. -`.thumb_func' +'.thumb_func' This directive specifies that the following symbol is the name of a Thumb encoded function. This information is necessary in order to allow the assembler and linker to generate correct code for interworking between Arm and Thumb instructions and should be used - even if interworking is not going to be performed. The presence - of this directive also implies `.thumb' + even if interworking is not going to be performed. The presence of + this directive also implies '.thumb' This directive is not neccessary when generating EABI objects. On these targets the encoding is implicit when generating Thumb code. -`.thumb_set' - This performs the equivalent of a `.set' directive in that it - creates a symbol which is an alias for another symbol (possibly - not yet defined). This directive also has the added property in - that it marks the aliased symbol as being a thumb function entry - point, in the same way that the `.thumb_func' directive does. +'.thumb_set' + This performs the equivalent of a '.set' directive in that it + creates a symbol which is an alias for another symbol (possibly not + yet defined). This directive also has the added property in that + it marks the aliased symbol as being a thumb function entry point, + in the same way that the '.thumb_func' directive does. -`.tlsdescseq TLS-VARIABLE' +'.tlsdescseq TLS-VARIABLE' This directive is used to annotate parts of an inlined TLS descriptor trampoline. Normally the trampoline is provided by the linker, and this directive is not needed. -`.unreq ALIAS-NAME' +'.unreq ALIAS-NAME' This undefines a register alias which was previously defined using - the `req', `dn' or `qn' directives. For example: + the 'req', 'dn' or 'qn' directives. For example: foo .req r0 .unreq foo @@ -7250,18 +7060,18 @@ File: as.info, Node: ARM Directives, Next: ARM Opcodes, Prev: ARM Floating Po can be used to delete builtin in register name aliases (eg 'r0'). This should only be done if it is really necessary. -`.unwind_raw OFFSET, BYTE1, ...' - Insert one of more arbitary unwind opcode bytes, which are known - to adjust the stack pointer by OFFSET bytes. +'.unwind_raw OFFSET, BYTE1, ...' + Insert one of more arbitary unwind opcode bytes, which are known to + adjust the stack pointer by OFFSET bytes. - For example `.unwind_raw 4, 0xb1, 0x01' is equivalent to `.save + For example '.unwind_raw 4, 0xb1, 0x01' is equivalent to '.save {r0}' -`.vsave VFP-REGLIST' +'.vsave VFP-REGLIST' Generate unwinder annotations to restore the VFP registers in - VFP-REGLIST using FLDMD. Also works for VFPv3 registers that are - to be restored using VLDM. The format of VFP-REGLIST is the same - as the corresponding store-multiple instruction. + VFP-REGLIST using FLDMD. Also works for VFPv3 registers that are to + be restored using VLDM. The format of VFP-REGLIST is the same as + the corresponding store-multiple instruction. _VFP registers_ .vsave {d8, d9, d10} @@ -7271,36 +7081,35 @@ File: as.info, Node: ARM Directives, Next: ARM Opcodes, Prev: ARM Floating Po vstm sp!, {d15, d16, d17} Since FLDMX and FSTMX are now deprecated, this directive should be - used in favour of `.save' for saving VFP registers for ARMv6 and + used in favour of '.save' for saving VFP registers for ARMv6 and above. - File: as.info, Node: ARM Opcodes, Next: ARM Mapping Symbols, Prev: ARM Directives, Up: ARM-Dependent 9.4.5 Opcodes ------------- -`as' implements all the standard ARM opcodes. It also implements +'as' implements all the standard ARM opcodes. It also implements several pseudo opcodes, including several synthetic load instructions. -`NOP' +'NOP' nop - This pseudo op will always evaluate to a legal ARM instruction - that does nothing. Currently it will evaluate to MOV r0, r0. + This pseudo op will always evaluate to a legal ARM instruction that + does nothing. Currently it will evaluate to MOV r0, r0. -`LDR' +'LDR' ldr <register> , = <expression> If expression evaluates to a numeric constant then a MOV or MVN instruction will be used in place of the LDR instruction, if the constant can be generated by either of these instructions. - Otherwise the constant will be placed into the nearest literal - pool (if it not already there) and a PC relative LDR instruction - will be generated. + Otherwise the constant will be placed into the nearest literal pool + (if it not already there) and a PC relative LDR instruction will be + generated. -`ADR' +'ADR' adr <register> <label> This instruction will load the address of LABEL into the indicated @@ -7310,7 +7119,7 @@ several pseudo opcodes, including several synthetic load instructions. (and section) as the ADR instruction, then an error will be generated. This instruction will not make use of the literal pool. -`ADRL' +'ADRL' adrl <register> <label> This instruction will load the address of LABEL into the indicated @@ -7324,8 +7133,7 @@ several pseudo opcodes, including several synthetic load instructions. file (and section) as the ADRL instruction, then an error will be generated. This instruction will not make use of the literal pool. - - For information on the ARM or Thumb instruction sets, see `ARM + For information on the ARM or Thumb instruction sets, see 'ARM Software Development Toolkit Reference Manual', Advanced RISC Machines Ltd. @@ -7335,24 +7143,23 @@ File: as.info, Node: ARM Mapping Symbols, Next: ARM Unwinding Tutorial, Prev: 9.4.6 Mapping Symbols --------------------- -The ARM ELF specification requires that special symbols be inserted -into object files to mark certain features: +The ARM ELF specification requires that special symbols be inserted into +object files to mark certain features: -`$a' +'$a' At the start of a region of code containing ARM instructions. -`$t' +'$t' At the start of a region of code containing THUMB instructions. -`$d' +'$d' At the start of a region of data. - The assembler will automatically insert these symbols for you - there is no need to code them yourself. Support for tagging symbols ($b, $f, $p and $m) which is also mentioned in the current ARM ELF specification -is not implemented. This is because they have been dropped from the -new EABI and so tools cannot rely upon their presence. +is not implemented. This is because they have been dropped from the new +EABI and so tools cannot rely upon their presence. File: as.info, Node: ARM Unwinding Tutorial, Prev: ARM Mapping Symbols, Up: ARM-Dependent @@ -7366,12 +7173,12 @@ exception is thrown to determine where control should be transferred. In particular, the unwind information is used to determine which function called the function that threw the exception, and which function called that one, and so forth. This information is also used -to restore the values of callee-saved registers in the function -catching the exception. +to restore the values of callee-saved registers in the function catching +the exception. If you are writing functions in assembly code, and those functions -call other functions that throw exceptions, you must use assembly -pseudo ops to ensure that appropriate exception unwind information is +call other functions that throw exceptions, you must use assembly pseudo +ops to ensure that appropriate exception unwind information is generated. Otherwise, if one of the functions called by your assembly code throws an exception, the run-time library will be unable to unwind the stack through your assembly code and your program will not behave @@ -7431,64 +7238,63 @@ that are used to generate unwind information. An important assumption made by the unwinder is that the stack frame does not change during the body of the function. In particular, since -we assume that the assembly code does not itself throw an exception, -the only point where an exception can be thrown is from a call, such as -the `bl' instruction above. At each call site, the same saved -registers (including `lr', which indicates the return address) must be -located in the same locations relative to the frame pointer. +we assume that the assembly code does not itself throw an exception, the +only point where an exception can be thrown is from a call, such as the +'bl' instruction above. At each call site, the same saved registers +(including 'lr', which indicates the return address) must be located in +the same locations relative to the frame pointer. - The `.fnstart' (*note .fnstart pseudo op: arm_fnstart.) pseudo op + The '.fnstart' (*note .fnstart pseudo op: arm_fnstart.) pseudo op appears immediately before the first instruction of the function while -the `.fnend' (*note .fnend pseudo op: arm_fnend.) pseudo op appears +the '.fnend' (*note .fnend pseudo op: arm_fnend.) pseudo op appears immediately after the last instruction of the function. These pseudo ops specify the range of the function. - Only the order of the other pseudos ops (e.g., `.setfp' or `.pad') + Only the order of the other pseudos ops (e.g., '.setfp' or '.pad') matters; their exact locations are irrelevant. In the example above, the compiler emits the pseudo ops with particular instructions. That makes it easier to understand the code, but it is not required for correctness. It would work just as well to emit all of the pseudo ops -other than `.fnend' in the same order, but immediately after `.fnstart'. - - The `.save' (*note .save pseudo op: arm_save.) pseudo op indicates -registers that have been saved to the stack so that they can be -restored before the function returns. The argument to the `.save' -pseudo op is a list of registers to save. If a register is -"callee-saved" (as specified by the ABI) and is modified by the -function you are writing, then your code must save the value before it -is modified and restore the original value before the function returns. -If an exception is thrown, the run-time library restores the values of -these registers from their locations on the stack before returning -control to the exception handler. (Of course, if an exception is not -thrown, the function that contains the `.save' pseudo op restores these -registers in the function epilogue, as is done with the `ldmfd' -instruction above.) +other than '.fnend' in the same order, but immediately after '.fnstart'. + + The '.save' (*note .save pseudo op: arm_save.) pseudo op indicates +registers that have been saved to the stack so that they can be restored +before the function returns. The argument to the '.save' pseudo op is a +list of registers to save. If a register is "callee-saved" (as +specified by the ABI) and is modified by the function you are writing, +then your code must save the value before it is modified and restore the +original value before the function returns. If an exception is thrown, +the run-time library restores the values of these registers from their +locations on the stack before returning control to the exception +handler. (Of course, if an exception is not thrown, the function that +contains the '.save' pseudo op restores these registers in the function +epilogue, as is done with the 'ldmfd' instruction above.) You do not have to save callee-saved registers at the very beginning -of the function and you do not need to use the `.save' pseudo op +of the function and you do not need to use the '.save' pseudo op immediately following the point at which the registers are saved. However, if you modify a callee-saved register, you must save it on the stack before modifying it and before calling any functions which might -throw an exception. And, you must use the `.save' pseudo op to -indicate that you have done so. +throw an exception. And, you must use the '.save' pseudo op to indicate +that you have done so. - The `.pad' (*note .pad: arm_pad.) pseudo op indicates a modification + The '.pad' (*note .pad: arm_pad.) pseudo op indicates a modification of the stack pointer that does not save any registers. The argument is the number of bytes (in decimal) that are subtracted from the stack pointer. (On ARM CPUs, the stack grows downwards, so subtracting from the stack pointer increases the size of the stack.) - The `.setfp' (*note .setfp pseudo op: arm_setfp.) pseudo op -indicates the register that contains the frame pointer. The first -argument is the register that is set, which is typically `fp'. The -second argument indicates the register from which the frame pointer -takes its value. The third argument, if present, is the value (in -decimal) added to the register specified by the second argument to -compute the value of the frame pointer. You should not modify the -frame pointer in the body of the function. + The '.setfp' (*note .setfp pseudo op: arm_setfp.) pseudo op indicates +the register that contains the frame pointer. The first argument is the +register that is set, which is typically 'fp'. The second argument +indicates the register from which the frame pointer takes its value. +The third argument, if present, is the value (in decimal) added to the +register specified by the second argument to compute the value of the +frame pointer. You should not modify the frame pointer in the body of +the function. If you do not use a frame pointer, then you should not use the -`.setfp' pseudo op. If you do not use a frame pointer, then you should +'.setfp' pseudo op. If you do not use a frame pointer, then you should avoid modifying the stack pointer outside of the function prologue. Otherwise, the run-time library will be unable to find saved registers when it is unwinding the stack. @@ -7496,8 +7302,8 @@ when it is unwinding the stack. The pseudo ops described above are sufficient for writing assembly code that calls functions which may throw exceptions. If you need to know more about the object-file format used to represent unwind -information, you may consult the `Exception Handling ABI for the ARM -Architecture' available from `http://infocenter.arm.com'. +information, you may consult the 'Exception Handling ABI for the ARM +Architecture' available from <http://infocenter.arm.com>. File: as.info, Node: AVR-Dependent, Next: Blackfin-Dependent, Prev: ARM-Dependent, Up: Machine Dependencies @@ -7517,7 +7323,7 @@ File: as.info, Node: AVR Options, Next: AVR Syntax, Up: AVR-Dependent 9.5.1 Options ------------- -`-mmcu=MCU' +'-mmcu=MCU' Specify ATMEL AVR instruction set or MCU type. Instruction set avr1 is for the minimal AVR core, not supported by @@ -7535,13 +7341,13 @@ File: as.info, Node: AVR Options, Next: AVR Syntax, Up: AVR-Dependent attiny4313, attiny44, attiny44a, attiny84, attiny84a, attiny25, attiny45, attiny85, attiny261, attiny261a, attiny461, attiny461a, attiny861, attiny861a, attiny87, attiny43u, attiny48, attiny88, - at86rf401, ata6289). + at86rf401). Instruction set avr3 is for the classic AVR core with up to 128K program memory space (MCU types: at43usb355, at76c711). - Instruction set avr31 is for the classic AVR core with exactly - 128K program memory space (MCU types: atmega103, at43usb320). + Instruction set avr31 is for the classic AVR core with exactly 128K + program memory space (MCU types: atmega103, at43usb320). Instruction set avr35 is for classic AVR core plus MOVW, CALL, and JMP instructions (MCU types: attiny167, at90usb82, at90usb162, @@ -7551,7 +7357,7 @@ File: as.info, Node: AVR Options, Next: AVR Syntax, Up: AVR-Dependent program memory space (MCU types: atmega48, atmega48a, atmega48p, atmega8, atmega88, atmega88a, atmega88p, atmega88pa, atmega8515, atmega8535, atmega8hva, at90pwm1, at90pwm2, at90pwm2b, at90pwm3, - at90pwm3b, at90pwm81). + at90pwm3b, at90pwm81, ata6289). Instruction set avr5 is for the enhanced AVR core with up to 128K program memory space (MCU types: atmega16, atmega16a, atmega161, @@ -7598,25 +7404,24 @@ File: as.info, Node: AVR Options, Next: AVR Syntax, Up: AVR-Dependent program memory space and greater than 64K data space (MCU types: atxmega64a1, atxmega64a1u). - Instruction set avrxmega6 is for the XMEGA AVR core with up to - 256K program memory space and less than 64K data space (MCU types: + Instruction set avrxmega6 is for the XMEGA AVR core with up to 256K + program memory space and less than 64K data space (MCU types: atxmega128a3, atxmega128d3, atxmega192a3, atxmega128b1, atxmega192d3, atxmega256a3, atxmega256a3b, atxmega256a3bu, atxmega192d3). - Instruction set avrxmega7 is for the XMEGA AVR core with up to - 256K program memory space and greater than 64K data space (MCU - types: atxmega128a1, atxmega128a1u). + Instruction set avrxmega7 is for the XMEGA AVR core with up to 256K + program memory space and greater than 64K data space (MCU types: + atxmega128a1, atxmega128a1u). -`-mall-opcodes' - Accept all AVR opcodes, even if not supported by `-mmcu'. +'-mall-opcodes' + Accept all AVR opcodes, even if not supported by '-mmcu'. -`-mno-skip-bug' +'-mno-skip-bug' This option disable warnings for skipping two-word instructions. -`-mno-wrap' - This option reject `rjmp/rcall' instructions with 8K wrap-around. - +'-mno-wrap' + This option reject 'rjmp/rcall' instructions with 8K wrap-around. File: as.info, Node: AVR Syntax, Next: AVR Opcodes, Prev: AVR Options, Up: AVR-Dependent @@ -7636,15 +7441,15 @@ File: as.info, Node: AVR-Chars, Next: AVR-Regs, Up: AVR Syntax 9.5.2.1 Special Characters .......................... -The presence of a `;' anywhere on a line indicates the start of a +The presence of a ';' anywhere on a line indicates the start of a comment that extends to the end of that line. - If a `#' appears as the first character of a line, the whole line is + If a '#' appears as the first character of a line, the whole line is treated as a comment, but in this case the line can also be a logical line number directive (*note Comments::) or a preprocessor control command (*note Preprocessing::). - The `$' character can be used instead of a newline to separate + The '$' character can be used instead of a newline to separate statements. @@ -7653,12 +7458,12 @@ File: as.info, Node: AVR-Regs, Next: AVR-Modifiers, Prev: AVR-Chars, Up: AVR 9.5.2.2 Register Names ...................... -The AVR has 32 x 8-bit general purpose working registers `r0', `r1', -... `r31'. Six of the 32 registers can be used as three 16-bit -indirect address register pointers for Data Space addressing. One of -the these address pointers can also be used as an address pointer for -look up tables in Flash program memory. These added function registers -are the 16-bit `X', `Y' and `Z' - registers. +The AVR has 32 x 8-bit general purpose working registers 'r0', 'r1', ... +'r31'. Six of the 32 registers can be used as three 16-bit indirect +address register pointers for Data Space addressing. One of the these +address pointers can also be used as an address pointer for look up +tables in Flash program memory. These added function registers are the +16-bit 'X', 'Y' and 'Z' - registers. X = r26:r27 Y = r28:r29 @@ -7676,33 +7481,37 @@ following: modifier(relocatable-expression) -`lo8' +'lo8' + This modifier allows you to use bits 0 through 7 of an address expression as 8 bit relocatable expression. -`hi8' +'hi8' + This modifier allows you to use bits 7 through 15 of an address expression as 8 bit relocatable expression. This is useful with, - for example, the AVR `ldi' instruction and `lo8' modifier. + for example, the AVR 'ldi' instruction and 'lo8' modifier. For example ldi r26, lo8(sym+10) ldi r27, hi8(sym+10) -`hh8' +'hh8' + This modifier allows you to use bits 16 through 23 of an address expression as 8 bit relocatable expression. Also, can be useful for loading 32 bit constants. -`hlo8' - Synonym of `hh8'. +'hlo8' + + Synonym of 'hh8'. -`hhi8' - This modifier allows you to use bits 24 through 31 of an - expression as 8 bit expression. This is useful with, for example, - the AVR `ldi' instruction and `lo8', `hi8', `hlo8', `hhi8', - modifier. +'hhi8' + + This modifier allows you to use bits 24 through 31 of an expression + as 8 bit expression. This is useful with, for example, the AVR + 'ldi' instruction and 'lo8', 'hi8', 'hlo8', 'hhi8', modifier. For example @@ -7712,23 +7521,25 @@ following: ldi r29, hhi8(285774925) ; r29,r28,r27,r26 = 285774925 -`pm_lo8' +'pm_lo8' + This modifier allows you to use bits 0 through 7 of an address expression as 8 bit relocatable expression. This modifier useful - for addressing data or code from Flash/Program memory. The using - of `pm_lo8' similar to `lo8'. + for addressing data or code from Flash/Program memory. The using + of 'pm_lo8' similar to 'lo8'. + +'pm_hi8' -`pm_hi8' This modifier allows you to use bits 8 through 15 of an address expression as 8 bit relocatable expression. This modifier useful for addressing data or code from Flash/Program memory. -`pm_hh8' +'pm_hh8' + This modifier allows you to use bits 15 through 23 of an address expression as 8 bit relocatable expression. This modifier useful for addressing data or code from Flash/Program memory. - File: as.info, Node: AVR Opcodes, Prev: AVR Syntax, Up: AVR-Dependent @@ -7736,17 +7547,17 @@ File: as.info, Node: AVR Opcodes, Prev: AVR Syntax, Up: AVR-Dependent ------------- For detailed information on the AVR machine instruction set, see -`www.atmel.com/products/AVR'. +<www.atmel.com/products/AVR>. - `as' implements all the standard AVR opcodes. The following table + 'as' implements all the standard AVR opcodes. The following table summarizes the AVR opcodes, and their arguments. Legend: r any register - d `ldi' register (r16-r31) - v `movw' even register (r0, r2, ..., r28, r30) - a `fmul' register (r16-r23) - w `adiw' register (r24,r26,r28,r30) + d 'ldi' register (r16-r31) + v 'movw' even register (r0, r2, ..., r28, r30) + a 'fmul' register (r16-r23) + w 'adiw' register (r24,r26,r28,r30) e pointer registers (X,Y,Z) b base pointer register and displacement ([YZ]+disp) z Z pointer register (for [e]lpm Rd,Z[+]) @@ -7755,7 +7566,7 @@ summarizes the AVR opcodes, and their arguments. s immediate value from 0 to 7 P Port address value from 0 to 63. (in, out) p Port address value from 0 to 31. (cbi, sbi, sbic, sbis) - K immediate value from 0 to 63 (used in `adiw', `sbiw') + K immediate value from 0 to 63 (used in 'adiw', 'sbiw') i immediate value l signed pc relative offset from -64 to 63 L signed pc relative offset from -2048 to 2047 @@ -7898,24 +7709,24 @@ File: as.info, Node: Blackfin Options, Next: Blackfin Syntax, Up: Blackfin-De 9.6.1 Options ------------- -`-mcpu=PROCESSOR[-SIREVISION]' +'-mcpu=PROCESSOR[-SIREVISION]' This option specifies the target processor. The optional SIREVISION is not used in assembler. It's here such that GCC can - easily pass down its `-mcpu=' option. The assembler will issue an + easily pass down its '-mcpu=' option. The assembler will issue an error message if an attempt is made to assemble an instruction which will not execute on the target processor. The following - processor names are recognized: `bf504', `bf506', `bf512', `bf514', - `bf516', `bf518', `bf522', `bf523', `bf524', `bf525', `bf526', - `bf527', `bf531', `bf532', `bf533', `bf534', `bf535' (not - implemented yet), `bf536', `bf537', `bf538', `bf539', `bf542', - `bf542m', `bf544', `bf544m', `bf547', `bf547m', `bf548', `bf548m', - `bf549', `bf549m', `bf561', and `bf592'. - -`-mfdpic' + processor names are recognized: 'bf504', 'bf506', 'bf512', 'bf514', + 'bf516', 'bf518', 'bf522', 'bf523', 'bf524', 'bf525', 'bf526', + 'bf527', 'bf531', 'bf532', 'bf533', 'bf534', 'bf535' (not + implemented yet), 'bf536', 'bf537', 'bf538', 'bf539', 'bf542', + 'bf542m', 'bf544', 'bf544m', 'bf547', 'bf547m', 'bf548', 'bf548m', + 'bf549', 'bf549m', 'bf561', and 'bf592'. + +'-mfdpic' Assemble for the FDPIC ABI. -`-mno-fdpic' -`-mnopic' +'-mno-fdpic' +'-mnopic' Disable -mfdpic. @@ -7924,7 +7735,7 @@ File: as.info, Node: Blackfin Syntax, Next: Blackfin Directives, Prev: Blackf 9.6.2 Syntax ------------ -`Special Characters' +'Special Characters' Assembler input is free format and may appear anywhere on the line. One instruction may extend across multiple lines or more than one instruction may appear on the same line. White space (space, tab, @@ -7933,14 +7744,14 @@ File: as.info, Node: Blackfin Syntax, Next: Blackfin Directives, Prev: Blackf names, keywords, user identifiers, and also some multicharacter special symbols like "+=", "/*" or "||". - Comments are introduced by the `#' character and extend to the end - of the current line. If the `#' appears as the first character of + Comments are introduced by the '#' character and extend to the end + of the current line. If the '#' appears as the first character of a line, the whole line is treated as a comment, but in this case the line can also be a logical line number directive (*note Comments::) or a preprocessor control command (*note Preprocessing::). -`Instruction Delimiting' +'Instruction Delimiting' A semicolon must terminate every instruction. Sometimes a complete instruction will consist of more than one operation. There are two cases where this occurs. The first is when two general operations @@ -7958,7 +7769,8 @@ File: as.info, Node: Blackfin Syntax, Next: Blackfin Directives, Prev: Blackf Multiple instructions can occur on the same line. Each must be terminated by a semicolon character. -`Register Names' +'Register Names' + The assembler treats register names and instruction keywords in a case insensitive manner. User identifiers are case sensitive. Thus, R3.l, R3.L, r3.l and r3.L are all equivalent input to the @@ -7975,104 +7787,100 @@ File: as.info, Node: Blackfin Syntax, Next: Blackfin Directives, Prev: Blackf Some instructions (such as -SP (Push Multiple)) require a group of adjacent registers. Adjacent registers are denoted in the syntax - by the range enclosed in parentheses and separated by a colon, - eg., (R7:3). Again, the larger number appears first. + by the range enclosed in parentheses and separated by a colon, eg., + (R7:3). Again, the larger number appears first. Portions of a particular register may be individually specified. - This is written with a dot (".") following the register name and + This is written with a dot (".") following the register name and then a letter denoting the desired portion. For 32-bit registers, ".H" denotes the most significant ("High") portion. ".L" denotes the least-significant portion. The subdivisions of the 40-bit registers are described later. -`Accumulators' +'Accumulators' The set of 40-bit registers A1 and A0 that normally contain data that is being manipulated. Each accumulator can be accessed in four ways. - `one 40-bit register' + 'one 40-bit register' The register will be referred to as A1 or A0. - - `one 32-bit register' + 'one 32-bit register' The registers are designated as A1.W or A0.W. - - `two 16-bit registers' + 'two 16-bit registers' The registers are designated as A1.H, A1.L, A0.H or A0.L. - - `one 8-bit register' + 'one 8-bit register' The registers are designated as A1.X or A0.X for the bits that extend beyond bit 31. -`Data Registers' +'Data Registers' The set of 32-bit registers (R0, R1, R2, R3, R4, R5, R6 and R7) - that normally contain data for manipulation. These are - abbreviated as D-register or Dreg. Data registers can be accessed - as 32-bit registers or as two independent 16-bit registers. The - least significant 16 bits of each register is called the "low" - half and is designated with ".L" following the register name. The - most significant 16 bits are called the "high" half and is - designated with ".H" following the name. + that normally contain data for manipulation. These are abbreviated + as D-register or Dreg. Data registers can be accessed as 32-bit + registers or as two independent 16-bit registers. The least + significant 16 bits of each register is called the "low" half and + is designated with ".L" following the register name. The most + significant 16 bits are called the "high" half and is designated + with ".H" following the name. R7.L, r2.h, r4.L, R0.H -`Pointer Registers' +'Pointer Registers' The set of 32-bit registers (P0, P1, P2, P3, P4, P5, SP and FP) that normally contain byte addresses of data structures. These are abbreviated as P-register or Preg. p2, p5, fp, sp -`Stack Pointer SP' +'Stack Pointer SP' The stack pointer contains the 32-bit address of the last occupied byte location in the stack. The stack grows by decrementing the stack pointer. -`Frame Pointer FP' +'Frame Pointer FP' The frame pointer contains the 32-bit address of the previous frame pointer in the stack. It is located at the top of a frame. -`Loop Top' - LT0 and LT1. These registers contain the 32-bit address of the - top of a zero overhead loop. +'Loop Top' + LT0 and LT1. These registers contain the 32-bit address of the top + of a zero overhead loop. -`Loop Count' +'Loop Count' LC0 and LC1. These registers contain the 32-bit counter of the zero overhead loop executions. -`Loop Bottom' +'Loop Bottom' LB0 and LB1. These registers contain the 32-bit address of the bottom of a zero overhead loop. -`Index Registers' +'Index Registers' The set of 32-bit registers (I0, I1, I2, I3) that normally contain byte addresses of data structures. Abbreviated I-register or Ireg. -`Modify Registers' +'Modify Registers' The set of 32-bit registers (M0, M1, M2, M3) that normally contain offset values that are added and subtracted to one of the index registers. Abbreviated as Mreg. -`Length Registers' +'Length Registers' The set of 32-bit registers (L0, L1, L2, L3) that normally contain the length in bytes of the circular buffer. Abbreviated as Lreg. - Clear the Lreg to disable circular addressing for the - corresponding Ireg. + Clear the Lreg to disable circular addressing for the corresponding + Ireg. -`Base Registers' +'Base Registers' The set of 32-bit registers (B0, B1, B2, B3) that normally contain the base address in bytes of the circular buffer. Abbreviated as Breg. -`Floating Point' +'Floating Point' The Blackfin family has no hardware floating point but the .float directive generates ieee floating point numbers for use with software floating point libraries. -`Blackfin Opcodes' +'Blackfin Opcodes' For detailed information on the Blackfin machine instruction set, see the Blackfin(r) Processor Instruction Set Reference. - File: as.info, Node: Blackfin Directives, Prev: Blackfin Syntax, Up: Blackfin-Dependent @@ -8082,32 +7890,27 @@ File: as.info, Node: Blackfin Directives, Prev: Blackfin Syntax, Up: Blackfin The following directives are provided for compatibility with the VDSP assembler. -`.byte2' +'.byte2' Initializes a two byte data object. - This maps to the `.short' directive. - -`.byte4' + This maps to the '.short' directive. +'.byte4' Initializes a four byte data object. - This maps to the `.int' directive. - -`.db' + This maps to the '.int' directive. +'.db' Initializes a single byte data object. - This directive is a synonym for `.byte'. - -`.dw' + This directive is a synonym for '.byte'. +'.dw' Initializes a two byte data object. - This directive is a synonym for `.byte2'. - -`.dd' + This directive is a synonym for '.byte2'. +'.dd' Initializes a four byte data object. - This directive is a synonym for `.byte4'. - -`.var' + This directive is a synonym for '.byte4'. +'.var' Define and initialize a 32 bit data object. @@ -8127,91 +7930,85 @@ File: as.info, Node: CR16 Operand Qualifiers, Next: CR16 Syntax, Up: CR16-Dep 9.7.1 CR16 Operand Qualifiers ----------------------------- -The National Semiconductor CR16 target of `as' has a few machine +The National Semiconductor CR16 target of 'as' has a few machine dependent operand qualifiers. Operand expression type qualifier is an optional field in the instruction operand, to determines the type of the expression field of -an operand. The `@' is required. CR16 architecture uses one of the +an operand. The '@' is required. CR16 architecture uses one of the following expression qualifiers: -`s' - - `Specifies expression operand type as small' - -`m' - - `Specifies expression operand type as medium' - -`l' - - `Specifies expression operand type as large' - -`c' - - `Specifies the CR16 Assembler generates a relocation entry for +'s' + - 'Specifies expression operand type as small' +'m' + - 'Specifies expression operand type as medium' +'l' + - 'Specifies expression operand type as large' +'c' + - 'Specifies the CR16 Assembler generates a relocation entry for the operand, where pc has implied bit, the expression is adjusted accordingly. The linker uses the relocation entry to update the operand address at link time.' - -`got/GOT' - - `Specifies the CR16 Assembler generates a relocation entry for +'got/GOT' + - 'Specifies the CR16 Assembler generates a relocation entry for the operand, offset from Global Offset Table. The linker uses this relocation entry to update the operand address at link time' - -`cgot/cGOT' - - `Specifies the CompactRISC Assembler generates a relocation - entry for the operand, where pc has implied bit, the expression is +'cgot/cGOT' + - 'Specifies the CompactRISC Assembler generates a relocation entry + for the operand, where pc has implied bit, the expression is adjusted accordingly. The linker uses the relocation entry to update the operand address at link time.' CR16 target operand qualifiers and its size (in bits): -`Immediate Operand: s' +'Immediate Operand: s' 4 bits. -`Immediate Operand: m' +'Immediate Operand: m' 16 bits, for movb and movw instructions. -`Immediate Operand: m' +'Immediate Operand: m' 20 bits, movd instructions. -`Immediate Operand: l' +'Immediate Operand: l' 32 bits. -`Absolute Operand: s' +'Absolute Operand: s' Illegal specifier for this operand. -`Absolute Operand: m' +'Absolute Operand: m' 20 bits, movd instructions. -`Displacement Operand: s' +'Displacement Operand: s' 8 bits. -`Displacement Operand: m' +'Displacement Operand: m' 16 bits. -`Displacement Operand: l' +'Displacement Operand: l' 24 bits. - For example: - 1 `movw $_myfun@c,r1' + 1 movw $_myfun@c,r1 This loads the address of _myfun, shifted right by 1, into r1. - 2 `movd $_myfun@c,(r2,r1)' + 2 movd $_myfun@c,(r2,r1) This loads the address of _myfun, shifted right by 1, into register-pair r2-r1. - 3 `_myfun_ptr:' - `.long _myfun@c' - `loadd _myfun_ptr, (r1,r0)' - `jal (r1,r0)' + 3 _myfun_ptr: + .long _myfun@c + loadd _myfun_ptr, (r1,r0) + jal (r1,r0) This .long directive, the address of _myfunc, shifted right by 1 at link time. - 4 `loadd _data1@GOT(r12), (r1,r0)' + 4 loadd _data1@GOT(r12), (r1,r0) This loads the address of _data1, into global offset table (ie GOT) and its offset value from GOT loads into register-pair r2-r1. - 5 `loadd _myfunc@cGOT(r12), (r1,r0)' + 5 loadd _myfunc@cGOT(r12), (r1,r0) This loads the address of _myfun, shifted right by 1, into global offset table (ie GOT) and its offset value from GOT loads into register-pair r1-r0. @@ -8231,14 +8028,13 @@ File: as.info, Node: CR16-Chars, Up: CR16 Syntax 9.7.2.1 Special Characters .......................... -The presence of a `#' on a line indicates the start of a comment that -extends to the end of the current line. If the `#' appears as the -first character of a line, the whole line is treated as a comment, but -in this case the line can also be a logical line number directive -(*note Comments::) or a preprocessor control command (*note -Preprocessing::). +The presence of a '#' on a line indicates the start of a comment that +extends to the end of the current line. If the '#' appears as the first +character of a line, the whole line is treated as a comment, but in this +case the line can also be a logical line number directive (*note +Comments::) or a preprocessor control command (*note Preprocessing::). - The `;' character can be used to separate statements on the same + The ';' character can be used to separate statements on the same line. @@ -8260,72 +8056,73 @@ File: as.info, Node: CRIS-Opts, Next: CRIS-Expand, Up: CRIS-Dependent 9.8.1 Command-line Options -------------------------- -The CRIS version of `as' has these machine-dependent command-line +The CRIS version of 'as' has these machine-dependent command-line options. The format of the generated object files can be either ELF or a.out, -specified by the command-line options `--emulation=crisaout' and -`--emulation=criself'. The default is ELF (criself), unless `as' has +specified by the command-line options '--emulation=crisaout' and +'--emulation=criself'. The default is ELF (criself), unless 'as' has been configured specifically for a.out by using the configuration name -`cris-axis-aout'. +'cris-axis-aout'. There are two different link-incompatible ELF object file variants for CRIS, for use in environments where symbols are expected to be -prefixed by a leading `_' character and for environments without such a +prefixed by a leading '_' character and for environments without such a symbol prefix. The variant used for GNU/Linux port has no symbol prefix. Which variant to produce is specified by either of the options -`--underscore' and `--no-underscore'. The default is `--underscore'. -Since symbols in CRIS a.out objects are expected to have a `_' prefix, -specifying `--no-underscore' when generating a.out objects is an error. +'--underscore' and '--no-underscore'. The default is '--underscore'. +Since symbols in CRIS a.out objects are expected to have a '_' prefix, +specifying '--no-underscore' when generating a.out objects is an error. Besides the object format difference, the effect of this option is to parse register names differently (*note crisnous::). The -`--no-underscore' option makes a `$' register prefix mandatory. +'--no-underscore' option makes a '$' register prefix mandatory. - The option `--pic' must be passed to `as' in order to recognize the + The option '--pic' must be passed to 'as' in order to recognize the symbol syntax used for ELF (SVR4 PIC) position-independent-code (*note crispic::). This will also affect expansion of instructions. The -expansion with `--pic' will use PC-relative rather than (slightly +expansion with '--pic' will use PC-relative rather than (slightly faster) absolute addresses in those expansions. This option is only valid when generating ELF format object files. - The option `--march=ARCHITECTURE' specifies the recognized + The option '--march=ARCHITECTURE' specifies the recognized instruction set and recognized register names. It also controls the architecture type of the object file. Valid values for ARCHITECTURE are: -`v0_v10' - All instructions and register names for any architecture variant - in the set v0...v10 are recognized. This is the default if the - target is configured as cris-*. -`v10' +'v0_v10' + All instructions and register names for any architecture variant in + the set v0...v10 are recognized. This is the default if the target + is configured as cris-*. + +'v10' Only instructions and register names for CRIS v10 (as found in - ETRAX 100 LX) are recognized. This is the default if the target - is configured as crisv10-*. + ETRAX 100 LX) are recognized. This is the default if the target is + configured as crisv10-*. -`v32' +'v32' Only instructions and register names for CRIS v32 (code name Guinness) are recognized. This is the default if the target is - configured as crisv32-*. This value implies `--no-mul-bug-abort'. - (A subsequent `--mul-bug-abort' will turn it back on.) + configured as crisv32-*. This value implies '--no-mul-bug-abort'. + (A subsequent '--mul-bug-abort' will turn it back on.) -`common_v10_v32' +'common_v10_v32' Only instructions with register names and addressing modes with opcodes common to the v10 and v32 are recognized. - When `-N' is specified, `as' will emit a warning when a 16-bit -branch instruction is expanded into a 32-bit multiple-instruction -construct (*note CRIS-Expand::). + When '-N' is specified, 'as' will emit a warning when a 16-bit branch +instruction is expanded into a 32-bit multiple-instruction construct +(*note CRIS-Expand::). Some versions of the CRIS v10, for example in the Etrax 100 LX, contain a bug that causes destabilizing memory accesses when a multiply instruction is executed with certain values in the first operand just -before a cache-miss. When the `--mul-bug-abort' command line option is -active (the default value), `as' will refuse to assemble a file +before a cache-miss. When the '--mul-bug-abort' command line option is +active (the default value), 'as' will refuse to assemble a file containing a multiply instruction at a dangerous offset, one that could be the last on a cache-line, or is in a section with insufficient alignment. This placement checking does not catch any case where the multiply instruction is dangerously placed because it is located in a -delay-slot. The `--mul-bug-abort' command line option turns off the +delay-slot. The '--mul-bug-abort' command line option turns off the checking. @@ -8334,25 +8131,25 @@ File: as.info, Node: CRIS-Expand, Next: CRIS-Symbols, Prev: CRIS-Opts, Up: C 9.8.2 Instruction expansion --------------------------- -`as' will silently choose an instruction that fits the operand size for -`[register+constant]' operands. For example, the offset `127' in -`move.d [r3+127],r4' fits in an instruction using a signed-byte offset. -Similarly, `move.d [r2+32767],r1' will generate an instruction using a +'as' will silently choose an instruction that fits the operand size for +'[register+constant]' operands. For example, the offset '127' in +'move.d [r3+127],r4' fits in an instruction using a signed-byte offset. +Similarly, 'move.d [r2+32767],r1' will generate an instruction using a 16-bit offset. For symbolic expressions and constants that do not fit in 16 bits including the sign bit, a 32-bit offset is generated. - For branches, `as' will expand from a 16-bit branch instruction into + For branches, 'as' will expand from a 16-bit branch instruction into a sequence of instructions that can reach a full 32-bit address. Since this does not correspond to a single instruction, such expansions can optionally be warned about. *Note CRIS-Opts::. - If the operand is found to fit the range, a `lapc' mnemonic will -translate to a `lapcq' instruction. Use `lapc.d' to force the 32-bit -`lapc' instruction. + If the operand is found to fit the range, a 'lapc' mnemonic will +translate to a 'lapcq' instruction. Use 'lapc.d' to force the 32-bit +'lapc' instruction. - Similarly, the `addo' mnemonic will translate to the shortest -fitting instruction of `addoq', `addo.w' and `addo.d', when used with a -operand that is a constant known at assembly time. + Similarly, the 'addo' mnemonic will translate to the shortest fitting +instruction of 'addoq', 'addo.w' and 'addo.d', when used with a operand +that is a constant known at assembly time. File: as.info, Node: CRIS-Symbols, Next: CRIS-Syntax, Prev: CRIS-Expand, Up: CRIS-Dependent @@ -8373,23 +8170,24 @@ in conditional assembly, for example: .endif These symbols are defined in the assembler, reflecting command-line -options, either when specified or the default. They are always -defined, to 0 or 1. -`..asm.arch.cris.any_v0_v10' - This symbol is non-zero when `--march=v0_v10' is specified or the +options, either when specified or the default. They are always defined, +to 0 or 1. + +'..asm.arch.cris.any_v0_v10' + This symbol is non-zero when '--march=v0_v10' is specified or the default. -`..asm.arch.cris.common_v10_v32' - Set according to the option `--march=common_v10_v32'. +'..asm.arch.cris.common_v10_v32' + Set according to the option '--march=common_v10_v32'. -`..asm.arch.cris.v10' - Reflects the option `--march=v10'. +'..asm.arch.cris.v10' + Reflects the option '--march=v10'. -`..asm.arch.cris.v32' - Corresponds to `--march=v10'. +'..asm.arch.cris.v32' + Corresponds to '--march=v10'. Speaking of symbols, when a symbol is used in code, it can have a -suffix modifying its value for use in position-independent code. *Note +suffix modifying its value for use in position-independent code. *Note CRIS-Pic::. @@ -8413,13 +8211,13 @@ File: as.info, Node: CRIS-Chars, Next: CRIS-Pic, Up: CRIS-Syntax 9.8.4.1 Special Characters .......................... -The character `#' is a line comment character. It starts a comment if +The character '#' is a line comment character. It starts a comment if and only if it is placed at the beginning of a line. - A `;' character starts a comment anywhere on the line, causing all + A ';' character starts a comment anywhere on the line, causing all characters up to the end of the line to be ignored. - A `@' character is handled as a line separator equivalent to a + A '@' character is handled as a line separator equivalent to a logical new-line character (except in a comment), so separate instructions can be specified on a single line. @@ -8431,71 +8229,78 @@ File: as.info, Node: CRIS-Pic, Next: CRIS-Regs, Prev: CRIS-Chars, Up: CRIS-S When generating position-independent code (SVR4 PIC) for use in cris-axis-linux-gnu or crisv32-axis-linux-gnu shared libraries, symbol -suffixes are used to specify what kind of run-time symbol lookup will -be used, expressed in the object as different _relocation types_. -Usually, all absolute symbol values must be located in a table, the -_global offset table_, leaving the code position-independent; -independent of values of global symbols and independent of the address -of the code. The suffix modifies the value of the symbol, into for -example an index into the global offset table where the real symbol -value is entered, or a PC-relative value, or a value relative to the -start of the global offset table. All symbol suffixes start with the -character `:' (omitted in the list below). Every symbol use in code or -a read-only section must therefore have a PIC suffix to enable a useful -shared library to be created. Usually, these constructs must not be -used with an additive constant offset as is usually allowed, i.e. no 4 -as in `symbol + 4' is allowed. This restriction is checked at -link-time, not at assembly-time. - -`GOT' +suffixes are used to specify what kind of run-time symbol lookup will be +used, expressed in the object as different _relocation types_. Usually, +all absolute symbol values must be located in a table, the _global +offset table_, leaving the code position-independent; independent of +values of global symbols and independent of the address of the code. +The suffix modifies the value of the symbol, into for example an index +into the global offset table where the real symbol value is entered, or +a PC-relative value, or a value relative to the start of the global +offset table. All symbol suffixes start with the character ':' (omitted +in the list below). Every symbol use in code or a read-only section +must therefore have a PIC suffix to enable a useful shared library to be +created. Usually, these constructs must not be used with an additive +constant offset as is usually allowed, i.e. no 4 as in 'symbol + 4' is +allowed. This restriction is checked at link-time, not at +assembly-time. + +'GOT' + Attaching this suffix to a symbol in an instruction causes the symbol to be entered into the global offset table. The value is a 32-bit index for that symbol into the global offset table. The - name of the corresponding relocation is `R_CRIS_32_GOT'. Example: - `move.d [$r0+extsym:GOT],$r9' + name of the corresponding relocation is 'R_CRIS_32_GOT'. Example: + 'move.d [$r0+extsym:GOT],$r9' -`GOT16' - Same as for `GOT', but the value is a 16-bit index into the global - offset table. The corresponding relocation is `R_CRIS_16_GOT'. - Example: `move.d [$r0+asymbol:GOT16],$r10' +'GOT16' + + Same as for 'GOT', but the value is a 16-bit index into the global + offset table. The corresponding relocation is 'R_CRIS_16_GOT'. + Example: 'move.d [$r0+asymbol:GOT16],$r10' + +'PLT' -`PLT' This suffix is used for function symbols. It causes a _procedure linkage table_, an array of code stubs, to be created at the time the shared object is created or linked against, together with a global offset table entry. The value is a pc-relative offset to the corresponding stub code in the procedure linkage table. This arrangement causes the run-time symbol resolver to be called to - look up and set the value of the symbol the first time the - function is called (at latest; depending environment variables). - It is only safe to leave the symbol unresolved this way if all - references are function calls. The name of the relocation is - `R_CRIS_32_PLT_PCREL'. Example: `add.d fnname:PLT,$pc' + look up and set the value of the symbol the first time the function + is called (at latest; depending environment variables). It is only + safe to leave the symbol unresolved this way if all references are + function calls. The name of the relocation is + 'R_CRIS_32_PLT_PCREL'. Example: 'add.d fnname:PLT,$pc' + +'PLTG' -`PLTG' Like PLT, but the value is relative to the beginning of the global - offset table. The relocation is `R_CRIS_32_PLT_GOTREL'. Example: - `move.d fnname:PLTG,$r3' + offset table. The relocation is 'R_CRIS_32_PLT_GOTREL'. Example: + 'move.d fnname:PLTG,$r3' -`GOTPLT' - Similar to `PLT', but the value of the symbol is a 32-bit index +'GOTPLT' + + Similar to 'PLT', but the value of the symbol is a 32-bit index into the global offset table. This is somewhat of a mix between - the effect of the `GOT' and the `PLT' suffix; the difference to - `GOT' is that there will be a procedure linkage table entry + the effect of the 'GOT' and the 'PLT' suffix; the difference to + 'GOT' is that there will be a procedure linkage table entry created, and that the symbol is assumed to be a function entry and - will be resolved by the run-time resolver as with `PLT'. The - relocation is `R_CRIS_32_GOTPLT'. Example: `jsr + will be resolved by the run-time resolver as with 'PLT'. The + relocation is 'R_CRIS_32_GOTPLT'. Example: 'jsr [$r0+fnname:GOTPLT]' -`GOTPLT16' - A variant of `GOTPLT' giving a 16-bit value. Its relocation name - is `R_CRIS_16_GOTPLT'. Example: `jsr [$r0+fnname:GOTPLT16]' +'GOTPLT16' + + A variant of 'GOTPLT' giving a 16-bit value. Its relocation name + is 'R_CRIS_16_GOTPLT'. Example: 'jsr [$r0+fnname:GOTPLT16]' + +'GOTOFF' -`GOTOFF' This suffix must only be attached to a local symbol, but may be used in an expression adding an offset. The value is the address of the symbol relative to the start of the global offset table. - The relocation name is `R_CRIS_32_GOTREL'. Example: `move.d + The relocation name is 'R_CRIS_32_GOTREL'. Example: 'move.d [$r0+localsym:GOTOFF],r3' @@ -8504,9 +8309,9 @@ File: as.info, Node: CRIS-Regs, Next: CRIS-Pseudos, Prev: CRIS-Pic, Up: CRIS 9.8.4.3 Register names ...................... -A `$' character may always prefix a general or special register name in +A '$' character may always prefix a general or special register name in an instruction operand but is mandatory when the option -`--no-underscore' is specified or when the `.syntax register_prefix' +'--no-underscore' is specified or when the '.syntax register_prefix' directive is in effect (*note crisnous::). Register names are case-insensitive. @@ -8518,47 +8323,51 @@ File: as.info, Node: CRIS-Pseudos, Prev: CRIS-Regs, Up: CRIS-Syntax There are a few CRIS-specific pseudo-directives in addition to the generic ones. *Note Pseudo Ops::. Constants emitted by -pseudo-directives are in little-endian order for CRIS. There is no +pseudo-directives are in little-endian order for CRIS. There is no support for floating-point-specific directives for CRIS. -`.dword EXPRESSIONS' - The `.dword' directive is a synonym for `.int', expecting zero or +'.dword EXPRESSIONS' + + The '.dword' directive is a synonym for '.int', expecting zero or more EXPRESSIONS, separated by commas. For each expression, a 32-bit little-endian constant is emitted. -`.syntax ARGUMENT' - The `.syntax' directive takes as ARGUMENT one of the following +'.syntax ARGUMENT' + The '.syntax' directive takes as ARGUMENT one of the following case-sensitive choices. - `no_register_prefix' - The `.syntax no_register_prefix' directive makes a `$' + 'no_register_prefix' + + The '.syntax no_register_prefix' directive makes a '$' character prefix on all registers optional. It overrides a previous setting, including the corresponding effect of the - option `--no-underscore'. If this directive is used when - ordinary symbols do not have a `_' character prefix, care - must be taken to avoid ambiguities whether an operand is a - register or a symbol; using symbols with names the same as - general or special registers then invoke undefined behavior. - - `register_prefix' - This directive makes a `$' character prefix on all registers + option '--no-underscore'. If this directive is used when + ordinary symbols do not have a '_' character prefix, care must + be taken to avoid ambiguities whether an operand is a register + or a symbol; using symbols with names the same as general or + special registers then invoke undefined behavior. + + 'register_prefix' + + This directive makes a '$' character prefix on all registers mandatory. It overrides a previous setting, including the - corresponding effect of the option `--underscore'. + corresponding effect of the option '--underscore'. + + 'leading_underscore' - `leading_underscore' This is an assertion directive, emitting an error if the - `--no-underscore' option is in effect. + '--no-underscore' option is in effect. + + 'no_leading_underscore' - `no_leading_underscore' - This is the opposite of the `.syntax leading_underscore' - directive and emits an error if the option `--underscore' is + This is the opposite of the '.syntax leading_underscore' + directive and emits an error if the option '--underscore' is in effect. -`.arch ARGUMENT' +'.arch ARGUMENT' This is an assertion directive, giving an error if the specified ARGUMENT is not the same as the specified or default value for the - `--march=ARCHITECTURE' option (*note march-option::). - + '--march=ARCHITECTURE' option (*note march-option::). File: as.info, Node: D10V-Dependent, Next: D30V-Dependent, Prev: CRIS-Dependent, Up: Machine Dependencies @@ -8579,25 +8388,24 @@ File: as.info, Node: D10V-Opts, Next: D10V-Syntax, Up: D10V-Dependent 9.9.1 D10V Options ------------------ -The Mitsubishi D10V version of `as' has a few machine dependent options. +The Mitsubishi D10V version of 'as' has a few machine dependent options. -`-O' - The D10V can often execute two sub-instructions in parallel. When - this option is used, `as' will attempt to optimize its output by +'-O' + The D10V can often execute two sub-instructions in parallel. When + this option is used, 'as' will attempt to optimize its output by detecting when instructions can be executed in parallel. - -`--nowarnswap' - To optimize execution performance, `as' will sometimes swap the - order of instructions. Normally this generates a warning. When - this option is used, no warning will be generated when - instructions are swapped. - -`--gstabs-packing' -`--no-gstabs-packing' - `as' packs adjacent short instructions into a single packed - instruction. `--no-gstabs-packing' turns instruction packing off if - `--gstabs' is specified as well; `--gstabs-packing' (the default) - turns instruction packing on even when `--gstabs' is specified. +'--nowarnswap' + To optimize execution performance, 'as' will sometimes swap the + order of instructions. Normally this generates a warning. When + this option is used, no warning will be generated when instructions + are swapped. +'--gstabs-packing' +'--no-gstabs-packing' + 'as' packs adjacent short instructions into a single packed + instruction. '--no-gstabs-packing' turns instruction packing off + if '--gstabs' is specified as well; '--gstabs-packing' (the + default) turns instruction packing on even when '--gstabs' is + specified. File: as.info, Node: D10V-Syntax, Next: D10V-Float, Prev: D10V-Opts, Up: D10V-Dependent @@ -8605,8 +8413,8 @@ File: as.info, Node: D10V-Syntax, Next: D10V-Float, Prev: D10V-Opts, Up: D10 9.9.2 Syntax ------------ -The D10V syntax is based on the syntax in Mitsubishi's D10V -architecture manual. The differences are detailed below. +The D10V syntax is based on the syntax in Mitsubishi's D10V architecture +manual. The differences are detailed below. * Menu: @@ -8623,19 +8431,19 @@ File: as.info, Node: D10V-Size, Next: D10V-Subs, Up: D10V-Syntax 9.9.2.1 Size Modifiers ...................... -The D10V version of `as' uses the instruction names in the D10V +The D10V version of 'as' uses the instruction names in the D10V Architecture Manual. However, the names in the manual are sometimes ambiguous. There are instruction names that can assemble to a short or -long form opcode. How does the assembler pick the correct form? `as' +long form opcode. How does the assembler pick the correct form? 'as' will always pick the smallest form if it can. When dealing with a symbol that is not defined yet when a line is being assembled, it will always use the long form. If you need to force the assembler to use either the short or long form of the instruction, you can append either -`.s' (short) or `.l' (long) to it. For example, if you are writing an -assembly program and you want to do a branch to a symbol that is -defined later in your program, you can write `bra.s foo'. Objdump -and GDB will always append `.s' or `.l' to instructions which have both -short and long forms. +'.s' (short) or '.l' (long) to it. For example, if you are writing an +assembly program and you want to do a branch to a symbol that is defined +later in your program, you can write 'bra.s foo'. Objdump and GDB will +always append '.s' or '.l' to instructions which have both short and +long forms. File: as.info, Node: D10V-Subs, Next: D10V-Chars, Prev: D10V-Size, Up: D10V-Syntax @@ -8650,13 +8458,13 @@ sub-instructions. These sub-instructions can be packed into a single instruction. The assembler will do this automatically. It will also detect when it should not pack instructions. For example, when a label is defined, the next instruction will never be packaged with the -previous one. Whenever a branch and link instruction is called, it -will not be packaged with the next instruction so the return address -will be valid. Nops are automatically inserted when necessary. +previous one. Whenever a branch and link instruction is called, it will +not be packaged with the next instruction so the return address will be +valid. Nops are automatically inserted when necessary. If you do not want the assembler automatically making these -decisions, you can control the packaging and execution type (parallel -or sequential) with the special execution symbols described in the next +decisions, you can control the packaging and execution type (parallel or +sequential) with the special execution symbols described in the next section. @@ -8665,10 +8473,10 @@ File: as.info, Node: D10V-Chars, Next: D10V-Regs, Prev: D10V-Subs, Up: D10V- 9.9.2.3 Special Characters .......................... -A semicolon (`;') can be used anywhere on a line to start a comment -that extends to the end of the line. +A semicolon (';') can be used anywhere on a line to start a comment that +extends to the end of the line. - If a `#' appears as the first character of a line, the whole line is + If a '#' appears as the first character of a line, the whole line is treated as a comment, but in this case the line could also be a logical line number directive (*note Comments::) or a preprocessor control command (*note Preprocessing::). @@ -8677,42 +8485,35 @@ command (*note Preprocessing::). parallel. Instructions listed in the standard one-per-line format will be executed sequentially. To specify the executing order, use the following symbols: -`->' +'->' Sequential with instruction on the left first. - -`<-' +'<-' Sequential with instruction on the right first. - -`||' +'||' Parallel The D10V syntax allows either one instruction per line, one instruction per line with the execution symbol, or two instructions per line. For example -`abs a1 -> abs r0' - Execute these sequentially. The instruction on the right is in - the right container and is executed second. - -`abs r0 <- abs a1' +'abs a1 -> abs r0' + Execute these sequentially. The instruction on the right is in the + right container and is executed second. +'abs r0 <- abs a1' Execute these reverse-sequentially. The instruction on the right is in the right container, and is executed first. - -`ld2w r2,@r8+ || mac a0,r0,r7' +'ld2w r2,@r8+ || mac a0,r0,r7' Execute these in parallel. - -`ld2w r2,@r8+ ||' -`mac a0,r0,r7' - Two-line format. Execute these in parallel. - -`ld2w r2,@r8+' -`mac a0,r0,r7' - Two-line format. Execute these sequentially. Assembler will put +'ld2w r2,@r8+ ||' +'mac a0,r0,r7' + Two-line format. Execute these in parallel. +'ld2w r2,@r8+' +'mac a0,r0,r7' + Two-line format. Execute these sequentially. Assembler will put them in the proper containers. - -`ld2w r2,@r8+ ->' -`mac a0,r0,r7' - Two-line format. Execute these sequentially. Same as above but +'ld2w r2,@r8+ ->' +'mac a0,r0,r7' + Two-line format. Execute these sequentially. Same as above but second instruction will always go into right container. - Since `$' has no special meaning, you may use it in symbol names. + Since '$' has no special meaning, you may use it in symbol names. File: as.info, Node: D10V-Regs, Next: D10V-Addressing, Prev: D10V-Chars, Up: D10V-Syntax @@ -8720,68 +8521,49 @@ File: as.info, Node: D10V-Regs, Next: D10V-Addressing, Prev: D10V-Chars, Up: 9.9.2.4 Register Names ...................... -You can use the predefined symbols `r0' through `r15' to refer to the -D10V registers. You can also use `sp' as an alias for `r15'. The -accumulators are `a0' and `a1'. There are special register-pair names +You can use the predefined symbols 'r0' through 'r15' to refer to the +D10V registers. You can also use 'sp' as an alias for 'r15'. The +accumulators are 'a0' and 'a1'. There are special register-pair names that may optionally be used in opcodes that require even-numbered -registers. Register names are not case sensitive. +registers. Register names are not case sensitive. Register Pairs -`r0-r1' - -`r2-r3' - -`r4-r5' - -`r6-r7' - -`r8-r9' - -`r10-r11' - -`r12-r13' - -`r14-r15' +'r0-r1' +'r2-r3' +'r4-r5' +'r6-r7' +'r8-r9' +'r10-r11' +'r12-r13' +'r14-r15' The D10V also has predefined symbols for these control registers and status bits: -`psw' +'psw' Processor Status Word - -`bpsw' +'bpsw' Backup Processor Status Word - -`pc' +'pc' Program Counter - -`bpc' +'bpc' Backup Program Counter - -`rpt_c' +'rpt_c' Repeat Count - -`rpt_s' +'rpt_s' Repeat Start address - -`rpt_e' +'rpt_e' Repeat End address - -`mod_s' +'mod_s' Modulo Start address - -`mod_e' +'mod_e' Modulo End address - -`iba' +'iba' Instruction Break Address - -`f0' +'f0' Flag 0 - -`f1' +'f1' Flag 1 - -`c' +'c' Carry flag @@ -8790,32 +8572,25 @@ File: as.info, Node: D10V-Addressing, Next: D10V-Word, Prev: D10V-Regs, Up: 9.9.2.5 Addressing Modes ........................ -`as' understands the following addressing modes for the D10V. `RN' in +'as' understands the following addressing modes for the D10V. 'RN' in the following refers to any of the numbered registers, but _not_ the control registers. -`RN' +'RN' Register direct - -`@RN' +'@RN' Register indirect - -`@RN+' +'@RN+' Register indirect with post-increment - -`@RN-' +'@RN-' Register indirect with post-decrement - -`@-SP' +'@-SP' Register indirect with pre-decrement - -`@(DISP, RN)' +'@(DISP, RN)' Register indirect with displacement - -`ADDR' +'ADDR' PC relative address (for branch or rep). - -`#IMM' - Immediate data (the `#' is optional and ignored) +'#IMM' + Immediate data (the '#' is optional and ignored) File: as.info, Node: D10V-Word, Prev: D10V-Addressing, Up: D10V-Syntax @@ -8823,11 +8598,11 @@ File: as.info, Node: D10V-Word, Prev: D10V-Addressing, Up: D10V-Syntax 9.9.2.6 @WORD Modifier ...................... -Any symbol followed by `@word' will be replaced by the symbol's value +Any symbol followed by '@word' will be replaced by the symbol's value shifted right by 2. This is used in situations such as loading a register with the address of a function (or any other code fragment). For example, if you want to load a register with the location of the -function `main' then jump to that function, you could do it as follows: +function 'main' then jump to that function, you could do it as follows: ldi r2, main@word jmp r2 @@ -8837,7 +8612,7 @@ File: as.info, Node: D10V-Float, Next: D10V-Opcodes, Prev: D10V-Syntax, Up: 9.9.3 Floating Point -------------------- -The D10V has no hardware floating point, but the `.float' and `.double' +The D10V has no hardware floating point, but the '.float' and '.double' directives generates IEEE floating-point numbers for compatibility with other development tools. @@ -8847,9 +8622,9 @@ File: as.info, Node: D10V-Opcodes, Prev: D10V-Float, Up: D10V-Dependent 9.9.4 Opcodes ------------- -For detailed information on the D10V machine instruction set, see `D10V +For detailed information on the D10V machine instruction set, see 'D10V Architecture: A VLIW Microprocessor for Multimedia Applications' -(Mitsubishi Electric Corp.). `as' implements all the standard D10V +(Mitsubishi Electric Corp.). 'as' implements all the standard D10V opcodes. The only changes are those described in the section on size modifiers @@ -8872,19 +8647,19 @@ File: as.info, Node: D30V-Opts, Next: D30V-Syntax, Up: D30V-Dependent 9.10.1 D30V Options ------------------- -The Mitsubishi D30V version of `as' has a few machine dependent options. +The Mitsubishi D30V version of 'as' has a few machine dependent options. -`-O' - The D30V can often execute two sub-instructions in parallel. When - this option is used, `as' will attempt to optimize its output by +'-O' + The D30V can often execute two sub-instructions in parallel. When + this option is used, 'as' will attempt to optimize its output by detecting when instructions can be executed in parallel. -`-n' - When this option is used, `as' will issue a warning every time it +'-n' + When this option is used, 'as' will issue a warning every time it adds a nop instruction. -`-N' - When this option is used, `as' will issue a warning if it needs to +'-N' + When this option is used, 'as' will issue a warning if it needs to insert a nop after a 32-bit multiply before a load or 16-bit multiply instruction. @@ -8894,8 +8669,8 @@ File: as.info, Node: D30V-Syntax, Next: D30V-Float, Prev: D30V-Opts, Up: D30 9.10.2 Syntax ------------- -The D30V syntax is based on the syntax in Mitsubishi's D30V -architecture manual. The differences are detailed below. +The D30V syntax is based on the syntax in Mitsubishi's D30V architecture +manual. The differences are detailed below. * Menu: @@ -8912,19 +8687,19 @@ File: as.info, Node: D30V-Size, Next: D30V-Subs, Up: D30V-Syntax 9.10.2.1 Size Modifiers ....................... -The D30V version of `as' uses the instruction names in the D30V +The D30V version of 'as' uses the instruction names in the D30V Architecture Manual. However, the names in the manual are sometimes ambiguous. There are instruction names that can assemble to a short or -long form opcode. How does the assembler pick the correct form? `as' +long form opcode. How does the assembler pick the correct form? 'as' will always pick the smallest form if it can. When dealing with a symbol that is not defined yet when a line is being assembled, it will always use the long form. If you need to force the assembler to use either the short or long form of the instruction, you can append either -`.s' (short) or `.l' (long) to it. For example, if you are writing an -assembly program and you want to do a branch to a symbol that is -defined later in your program, you can write `bra.s foo'. Objdump and -GDB will always append `.s' or `.l' to instructions which have both -short and long forms. +'.s' (short) or '.l' (long) to it. For example, if you are writing an +assembly program and you want to do a branch to a symbol that is defined +later in your program, you can write 'bra.s foo'. Objdump and GDB will +always append '.s' or '.l' to instructions which have both short and +long forms. File: as.info, Node: D30V-Subs, Next: D30V-Chars, Prev: D30V-Size, Up: D30V-Syntax @@ -8939,13 +8714,13 @@ sub-instructions. These sub-instructions can be packed into a single instruction. The assembler will do this automatically. It will also detect when it should not pack instructions. For example, when a label is defined, the next instruction will never be packaged with the -previous one. Whenever a branch and link instruction is called, it -will not be packaged with the next instruction so the return address -will be valid. Nops are automatically inserted when necessary. +previous one. Whenever a branch and link instruction is called, it will +not be packaged with the next instruction so the return address will be +valid. Nops are automatically inserted when necessary. If you do not want the assembler automatically making these -decisions, you can control the packaging and execution type (parallel -or sequential) with the special execution symbols described in the next +decisions, you can control the packaging and execution type (parallel or +sequential) with the special execution symbols described in the next section. @@ -8954,71 +8729,71 @@ File: as.info, Node: D30V-Chars, Next: D30V-Guarded, Prev: D30V-Subs, Up: D3 9.10.2.3 Special Characters ........................... -A semicolon (`;') can be used anywhere on a line to start a comment -that extends to the end of the line. +A semicolon (';') can be used anywhere on a line to start a comment that +extends to the end of the line. - If a `#' appears as the first character of a line, the whole line is + If a '#' appears as the first character of a line, the whole line is treated as a comment, but in this case the line could also be a logical line number directive (*note Comments::) or a preprocessor control command (*note Preprocessing::). Sub-instructions may be executed in order, in reverse-order, or in parallel. Instructions listed in the standard one-per-line format will -be executed sequentially unless you use the `-O' option. +be executed sequentially unless you use the '-O' option. To specify the executing order, use the following symbols: -`->' +'->' Sequential with instruction on the left first. -`<-' +'<-' Sequential with instruction on the right first. -`||' +'||' Parallel The D30V syntax allows either one instruction per line, one instruction per line with the execution symbol, or two instructions per line. For example -`abs r2,r3 -> abs r4,r5' - Execute these sequentially. The instruction on the right is in - the right container and is executed second. +'abs r2,r3 -> abs r4,r5' + Execute these sequentially. The instruction on the right is in the + right container and is executed second. -`abs r2,r3 <- abs r4,r5' +'abs r2,r3 <- abs r4,r5' Execute these reverse-sequentially. The instruction on the right is in the right container, and is executed first. -`abs r2,r3 || abs r4,r5' +'abs r2,r3 || abs r4,r5' Execute these in parallel. -`ldw r2,@(r3,r4) ||' -`mulx r6,r8,r9' - Two-line format. Execute these in parallel. +'ldw r2,@(r3,r4) ||' +'mulx r6,r8,r9' + Two-line format. Execute these in parallel. -`mulx a0,r8,r9' -`stw r2,@(r3,r4)' - Two-line format. Execute these sequentially unless `-O' option is - used. If the `-O' option is used, the assembler will determine if +'mulx a0,r8,r9' +'stw r2,@(r3,r4)' + Two-line format. Execute these sequentially unless '-O' option is + used. If the '-O' option is used, the assembler will determine if the instructions could be done in parallel (the above two instructions can be done in parallel), and if so, emit them as parallel instructions. The assembler will put them in the proper - containers. In the above example, the assembler will put the - `stw' instruction in left container and the `mulx' instruction in - the right container. - -`stw r2,@(r3,r4) ->' -`mulx a0,r8,r9' - Two-line format. Execute the `stw' instruction followed by the - `mulx' instruction sequentially. The first instruction goes in the + containers. In the above example, the assembler will put the 'stw' + instruction in left container and the 'mulx' instruction in the + right container. + +'stw r2,@(r3,r4) ->' +'mulx a0,r8,r9' + Two-line format. Execute the 'stw' instruction followed by the + 'mulx' instruction sequentially. The first instruction goes in the left container and the second instruction goes into right container. The assembler will give an error if the machine ordering constraints are violated. -`stw r2,@(r3,r4) <-' -`mulx a0,r8,r9' - Same as previous example, except that the `mulx' instruction is - executed before the `stw' instruction. +'stw r2,@(r3,r4) <-' +'mulx a0,r8,r9' + Same as previous example, except that the 'mulx' instruction is + executed before the 'stw' instruction. - Since `$' has no special meaning, you may use it in symbol names. + Since '$' has no special meaning, you may use it in symbol names. File: as.info, Node: D30V-Guarded, Next: D30V-Regs, Prev: D30V-Chars, Up: D30V-Syntax @@ -9026,26 +8801,21 @@ File: as.info, Node: D30V-Guarded, Next: D30V-Regs, Prev: D30V-Chars, Up: D3 9.10.2.4 Guarded Execution .......................... -`as' supports the full range of guarded execution directives for each +'as' supports the full range of guarded execution directives for each instruction. Just append the directive after the instruction proper. The directives are: -`/tx' +'/tx' Execute the instruction if flag f0 is true. - -`/fx' +'/fx' Execute the instruction if flag f0 is false. - -`/xt' +'/xt' Execute the instruction if flag f1 is true. - -`/xf' +'/xf' Execute the instruction if flag f1 is false. - -`/tt' +'/tt' Execute the instruction if both flags f0 and f1 are true. - -`/tf' +'/tf' Execute the instruction if flag f0 is true and flag f1 is false. @@ -9054,79 +8824,57 @@ File: as.info, Node: D30V-Regs, Next: D30V-Addressing, Prev: D30V-Guarded, U 9.10.2.5 Register Names ....................... -You can use the predefined symbols `r0' through `r63' to refer to the -D30V registers. You can also use `sp' as an alias for `r63' and `link' -as an alias for `r62'. The accumulators are `a0' and `a1'. +You can use the predefined symbols 'r0' through 'r63' to refer to the +D30V registers. You can also use 'sp' as an alias for 'r63' and 'link' +as an alias for 'r62'. The accumulators are 'a0' and 'a1'. The D30V also has predefined symbols for these control registers and status bits: -`psw' +'psw' Processor Status Word - -`bpsw' +'bpsw' Backup Processor Status Word - -`pc' +'pc' Program Counter - -`bpc' +'bpc' Backup Program Counter - -`rpt_c' +'rpt_c' Repeat Count - -`rpt_s' +'rpt_s' Repeat Start address - -`rpt_e' +'rpt_e' Repeat End address - -`mod_s' +'mod_s' Modulo Start address - -`mod_e' +'mod_e' Modulo End address - -`iba' +'iba' Instruction Break Address - -`f0' +'f0' Flag 0 - -`f1' +'f1' Flag 1 - -`f2' +'f2' Flag 2 - -`f3' +'f3' Flag 3 - -`f4' +'f4' Flag 4 - -`f5' +'f5' Flag 5 - -`f6' +'f6' Flag 6 - -`f7' +'f7' Flag 7 - -`s' +'s' Same as flag 4 (saturation flag) - -`v' +'v' Same as flag 5 (overflow flag) - -`va' +'va' Same as flag 6 (sticky overflow flag) - -`c' +'c' Same as flag 7 (carry/borrow flag) - -`b' +'b' Same as flag 7 (carry/borrow flag) @@ -9135,32 +8883,25 @@ File: as.info, Node: D30V-Addressing, Prev: D30V-Regs, Up: D30V-Syntax 9.10.2.6 Addressing Modes ......................... -`as' understands the following addressing modes for the D30V. `RN' in +'as' understands the following addressing modes for the D30V. 'RN' in the following refers to any of the numbered registers, but _not_ the control registers. -`RN' +'RN' Register direct - -`@RN' +'@RN' Register indirect - -`@RN+' +'@RN+' Register indirect with post-increment - -`@RN-' +'@RN-' Register indirect with post-decrement - -`@-SP' +'@-SP' Register indirect with pre-decrement - -`@(DISP, RN)' +'@(DISP, RN)' Register indirect with displacement - -`ADDR' +'ADDR' PC relative address (for branch or rep). - -`#IMM' - Immediate data (the `#' is optional and ignored) +'#IMM' + Immediate data (the '#' is optional and ignored) File: as.info, Node: D30V-Float, Next: D30V-Opcodes, Prev: D30V-Syntax, Up: D30V-Dependent @@ -9168,7 +8909,7 @@ File: as.info, Node: D30V-Float, Next: D30V-Opcodes, Prev: D30V-Syntax, Up: 9.10.3 Floating Point --------------------- -The D30V has no hardware floating point, but the `.float' and `.double' +The D30V has no hardware floating point, but the '.float' and '.double' directives generates IEEE floating-point numbers for compatibility with other development tools. @@ -9178,9 +8919,9 @@ File: as.info, Node: D30V-Opcodes, Prev: D30V-Float, Up: D30V-Dependent 9.10.4 Opcodes -------------- -For detailed information on the D30V machine instruction set, see `D30V +For detailed information on the D30V machine instruction set, see 'D30V Architecture: A VLIW Microprocessor for Multimedia Applications' -(Mitsubishi Electric Corp.). `as' implements all the standard D30V +(Mitsubishi Electric Corp.). 'as' implements all the standard D30V opcodes. The only changes are those described in the section on size modifiers @@ -9201,14 +8942,14 @@ File: as.info, Node: Epiphany Options, Next: Epiphany Syntax, Up: Epiphany-De 9.11.1 Options -------------- -`as' has two additional command-line options for the Epiphany +'as' has two additional command-line options for the Epiphany architecture. -`-mepiphany' +'-mepiphany' Specifies that the both 32 and 16 bit instructions are allowed. This is the default behavior. -`-mepiphany16' +'-mepiphany16' Restricts the permitted instructions to just the 16 bit set. @@ -9227,15 +8968,15 @@ File: as.info, Node: Epiphany-Chars, Up: Epiphany Syntax 9.11.2.1 Special Characters ........................... -The presence of a `;' on a line indicates the start of a comment that +The presence of a ';' on a line indicates the start of a comment that extends to the end of the current line. - If a `#' appears as the first character of a line then the whole -line is treated as a comment, but in this case the line could also be a + If a '#' appears as the first character of a line then the whole line +is treated as a comment, but in this case the line could also be a logical line number directive (*note Comments::) or a preprocessor control command (*note Preprocessing::). - The ``' character can be used to separate statements on the same + The '`' character can be used to separate statements on the same line. @@ -9258,12 +8999,11 @@ File: as.info, Node: H8/300 Options, Next: H8/300 Syntax, Up: H8/300-Dependen 9.12.1 Options -------------- -The Renesas H8/300 version of `as' has one machine-dependent option: +The Renesas H8/300 version of 'as' has one machine-dependent option: -`-h-tick-hex' +'-h-tick-hex' Support H'00 style hex constants in addition to 0x00 style. - File: as.info, Node: H8/300 Syntax, Next: H8/300 Floating Point, Prev: H8/300 Options, Up: H8/300-Dependent @@ -9282,10 +9022,10 @@ File: as.info, Node: H8/300-Chars, Next: H8/300-Regs, Up: H8/300 Syntax 9.12.2.1 Special Characters ........................... -`;' is the line comment character. +';' is the line comment character. - `$' can be used instead of a newline to separate statements. -Therefore _you may not use `$' in symbol names_ on the H8/300. + '$' can be used instead of a newline to separate statements. +Therefore _you may not use '$' in symbol names_ on the H8/300. File: as.info, Node: H8/300-Regs, Next: H8/300-Addressing, Prev: H8/300-Chars, Up: H8/300 Syntax @@ -9293,22 +9033,22 @@ File: as.info, Node: H8/300-Regs, Next: H8/300-Addressing, Prev: H8/300-Chars 9.12.2.2 Register Names ....................... -You can use predefined symbols of the form `rNh' and `rNl' to refer to -the H8/300 registers as sixteen 8-bit general-purpose registers. N is -a digit from `0' to `7'); for instance, both `r0h' and `r7l' are valid +You can use predefined symbols of the form 'rNh' and 'rNl' to refer to +the H8/300 registers as sixteen 8-bit general-purpose registers. N is a +digit from '0' to '7'); for instance, both 'r0h' and 'r7l' are valid register names. - You can also use the eight predefined symbols `rN' to refer to the + You can also use the eight predefined symbols 'rN' to refer to the H8/300 registers as 16-bit registers (you must use this form for addressing). - On the H8/300H, you can also use the eight predefined symbols `erN' -(`er0' ... `er7') to refer to the 32-bit general purpose registers. + On the H8/300H, you can also use the eight predefined symbols 'erN' +('er0' ... 'er7') to refer to the 32-bit general purpose registers. - The two control registers are called `pc' (program counter; a 16-bit -register, except on the H8/300H where it is 24 bits) and `ccr' -(condition code register; an 8-bit register). `r7' is used as the -stack pointer, and can also be called `sp'. + The two control registers are called 'pc' (program counter; a 16-bit +register, except on the H8/300H where it is 24 bits) and 'ccr' +(condition code register; an 8-bit register). 'r7' is used as the stack +pointer, and can also be called 'sp'. File: as.info, Node: H8/300-Addressing, Prev: H8/300-Regs, Up: H8/300 Syntax @@ -9317,43 +9057,43 @@ File: as.info, Node: H8/300-Addressing, Prev: H8/300-Regs, Up: H8/300 Syntax ......................... as understands the following addressing modes for the H8/300: -`rN' +'rN' Register direct -`@rN' +'@rN' Register indirect -`@(D, rN)' -`@(D:16, rN)' -`@(D:24, rN)' - Register indirect: 16-bit or 24-bit displacement D from register - N. (24-bit displacements are only meaningful on the H8/300H.) +'@(D, rN)' +'@(D:16, rN)' +'@(D:24, rN)' + Register indirect: 16-bit or 24-bit displacement D from register N. + (24-bit displacements are only meaningful on the H8/300H.) -`@rN+' +'@rN+' Register indirect with post-increment -`@-rN' +'@-rN' Register indirect with pre-decrement -``@'AA' -``@'AA:8' -``@'AA:16' -``@'AA:24' - Absolute address `aa'. (The address size `:24' only makes sense - on the H8/300H.) - -`#XX' -`#XX:8' -`#XX:16' -`#XX:32' - Immediate data XX. You may specify the `:8', `:16', or `:32' for - clarity, if you wish; but `as' neither requires this nor uses +'@AA' +'@AA:8' +'@AA:16' +'@AA:24' + Absolute address 'aa'. (The address size ':24' only makes sense on + the H8/300H.) + +'#XX' +'#XX:8' +'#XX:16' +'#XX:32' + Immediate data XX. You may specify the ':8', ':16', or ':32' for + clarity, if you wish; but 'as' neither requires this nor uses it--the data size required is taken from context. -``@'`@'AA' -``@'`@'AA:8' - Memory indirect. You may specify the `:8' for clarity, if you - wish; but `as' neither requires this nor uses it. +'@@AA' +'@@AA:8' + Memory indirect. You may specify the ':8' for clarity, if you + wish; but 'as' neither requires this nor uses it. File: as.info, Node: H8/300 Floating Point, Next: H8/300 Directives, Prev: H8/300 Syntax, Up: H8/300-Dependent @@ -9361,7 +9101,7 @@ File: as.info, Node: H8/300 Floating Point, Next: H8/300 Directives, Prev: H8 9.12.3 Floating Point --------------------- -The H8/300 family has no hardware floating point, but the `.float' +The H8/300 family has no hardware floating point, but the '.float' directive generates IEEE floating-point numbers for compatibility with other development tools. @@ -9371,29 +9111,29 @@ File: as.info, Node: H8/300 Directives, Next: H8/300 Opcodes, Prev: H8/300 Fl 9.12.4 H8/300 Machine Directives -------------------------------- -`as' has the following machine-dependent directives for the H8/300: +'as' has the following machine-dependent directives for the H8/300: -`.h8300h' - Recognize and emit additional instructions for the H8/300H - variant, and also make `.int' emit 32-bit numbers rather than the - usual (16-bit) for the H8/300 family. +'.h8300h' + Recognize and emit additional instructions for the H8/300H variant, + and also make '.int' emit 32-bit numbers rather than the usual + (16-bit) for the H8/300 family. -`.h8300s' +'.h8300s' Recognize and emit additional instructions for the H8S variant, and - also make `.int' emit 32-bit numbers rather than the usual (16-bit) + also make '.int' emit 32-bit numbers rather than the usual (16-bit) for the H8/300 family. -`.h8300hn' +'.h8300hn' Recognize and emit additional instructions for the H8/300H variant - in normal mode, and also make `.int' emit 32-bit numbers rather + in normal mode, and also make '.int' emit 32-bit numbers rather than the usual (16-bit) for the H8/300 family. -`.h8300sn' +'.h8300sn' Recognize and emit additional instructions for the H8S variant in - normal mode, and also make `.int' emit 32-bit numbers rather than + normal mode, and also make '.int' emit 32-bit numbers rather than the usual (16-bit) for the H8/300 family. - On the H8/300 family (including the H8/300H) `.word' directives + On the H8/300 family (including the H8/300H) '.word' directives generate 16-bit numbers. @@ -9403,14 +9143,14 @@ File: as.info, Node: H8/300 Opcodes, Prev: H8/300 Directives, Up: H8/300-Depe -------------- For detailed information on the H8/300 machine instruction set, see -`H8/300 Series Programming Manual'. For information specific to the -H8/300H, see `H8/300H Series Programming Manual' (Renesas). +'H8/300 Series Programming Manual'. For information specific to the +H8/300H, see 'H8/300H Series Programming Manual' (Renesas). - `as' implements all the standard H8/300 opcodes. No additional + 'as' implements all the standard H8/300 opcodes. No additional pseudo-instructions are needed on this family. The following table summarizes the H8/300 opcodes, and their -arguments. Entries marked `*' are opcodes used only on the H8/300H. +arguments. Entries marked '*' are opcodes used only on the H8/300H. Legend: Rs source register @@ -9435,7 +9175,6 @@ arguments. Entries marked `*' are opcodes used only on the H8/300H. * and.w #imm,rd bhi pcrel:8 * and.l #imm,rd * bhi pcrel:16 * and.l rs,rd bls pcrel:8 - * bls pcrel:16 bld #imm,rd bcc pcrel:8 bld #imm,@rd * bcc pcrel:16 bld #imm,@abs:8 @@ -9486,7 +9225,6 @@ arguments. Entries marked `*' are opcodes used only on the H8/300H. bixor #imm,rd * divxs.w rs,rd bixor #imm,@rd eepmov bixor #imm,@abs:8 * eepmovw - * exts.w rd mov.w rs,@abs:16 * exts.l rd * mov.l #imm,rd * extu.w rd * mov.l rs,rd @@ -9537,7 +9275,6 @@ arguments. Entries marked `*' are opcodes used only on the H8/300H. mov.w @abs:16,rd * rotxl.l rs mov.w rs,@(disp:16,rd) rotxr.b rs mov.w rs,@-rd * rotxr.w rs - * rotxr.l rs * stc ccr,@(disp:24,rd) bpt * stc ccr,@-rd rte * stc ccr,@abs:16 @@ -9559,18 +9296,18 @@ arguments. Entries marked `*' are opcodes used only on the H8/300H. * stc ccr,@rs * xor.l rs,rd * stc ccr,@(disp:16,rd) xorc #imm,ccr - Four H8/300 instructions (`add', `cmp', `mov', `sub') are defined -with variants using the suffixes `.b', `.w', and `.l' to specify the -size of a memory operand. `as' supports these suffixes, but does not -require them; since one of the operands is always a register, `as' can + Four H8/300 instructions ('add', 'cmp', 'mov', 'sub') are defined +with variants using the suffixes '.b', '.w', and '.l' to specify the +size of a memory operand. 'as' supports these suffixes, but does not +require them; since one of the operands is always a register, 'as' can deduce the correct size. - For example, since `r0' refers to a 16-bit register, + For example, since 'r0' refers to a 16-bit register, mov r0,@foo is equivalent to mov.w r0,@foo - If you use the size suffixes, `as' issues a warning when the suffix + If you use the size suffixes, 'as' issues a warning when the suffix and the register size do not match. @@ -9594,17 +9331,17 @@ File: as.info, Node: HPPA Notes, Next: HPPA Options, Up: HPPA-Dependent 9.13.1 Notes ------------ -As a back end for GNU CC `as' has been throughly tested and should work +As a back end for GNU CC 'as' has been throughly tested and should work extremely well. We have tested it only minimally on hand written assembly code and no one has tested it much on the assembly output from the HP compilers. The format of the debugging sections has changed since the original -`as' port (version 1.3X) was released; therefore, you must rebuild all +'as' port (version 1.3X) was released; therefore, you must rebuild all HPPA objects and libraries with the new assembler so that you can debug the final executable. - The HPPA `as' port generates a small subset of the relocations + The HPPA 'as' port generates a small subset of the relocations available in the SOM and ELF object file formats. Additional relocation support will be added as it becomes necessary. @@ -9614,7 +9351,7 @@ File: as.info, Node: HPPA Options, Next: HPPA Syntax, Prev: HPPA Notes, Up: 9.13.2 Options -------------- -`as' has no machine-dependent command-line options for the HPPA. +'as' has no machine-dependent command-line options for the HPPA. File: as.info, Node: HPPA Syntax, Next: HPPA Floating Point, Prev: HPPA Options, Up: HPPA-Dependent @@ -9630,25 +9367,25 @@ assembly language reference manual, with a few noteworthy differences. simply for compatibility with how most assembly language programmers write code. - Some obscure expression parsing problems may affect hand written -code which uses the `spop' instructions, or code which makes significant -use of the `!' line separator. + Some obscure expression parsing problems may affect hand written code +which uses the 'spop' instructions, or code which makes significant use +of the '!' line separator. - `as' is much less forgiving about missing arguments and other -similar oversights than the HP assembler. `as' notifies you of missing + 'as' is much less forgiving about missing arguments and other similar +oversights than the HP assembler. 'as' notifies you of missing arguments as syntax errors; this is regarded as a feature, not a bug. - Finally, `as' allows you to use an external symbol without -explicitly importing the symbol. _Warning:_ in the future this will be -an error for HPPA targets. + Finally, 'as' allows you to use an external symbol without explicitly +importing the symbol. _Warning:_ in the future this will be an error +for HPPA targets. Special characters for HPPA targets include: - `;' is the line comment character. + ';' is the line comment character. - `!' can be used instead of a newline to separate statements. + '!' can be used instead of a newline to separate statements. - Since `$' has no special meaning, you may use it in symbol names. + Since '$' has no special meaning, you may use it in symbol names. File: as.info, Node: HPPA Floating Point, Next: HPPA Directives, Prev: HPPA Syntax, Up: HPPA-Dependent @@ -9664,12 +9401,12 @@ File: as.info, Node: HPPA Directives, Next: HPPA Opcodes, Prev: HPPA Floating 9.13.5 HPPA Assembler Directives -------------------------------- -`as' for the HPPA supports many additional directives for compatibility +'as' for the HPPA supports many additional directives for compatibility with the native assembler. This section describes them only briefly. For detailed information on HPPA-specific assembler directives, see -`HP9000 Series 800 Assembly Language Reference Manual' (HP 92432-90001). +'HP9000 Series 800 Assembly Language Reference Manual' (HP 92432-90001). - `as' does _not_ support the following assembler directives described + 'as' does _not_ support the following assembler directives described in the HP manual: .endm .liston @@ -9677,195 +9414,194 @@ in the HP manual: .leave .macro .listoff - Beyond those implemented for compatibility, `as' supports one -additional assembler directive for the HPPA: `.param'. It conveys + Beyond those implemented for compatibility, 'as' supports one +additional assembler directive for the HPPA: '.param'. It conveys register argument locations for static functions. Its syntax closely -follows the `.export' directive. +follows the '.export' directive. - These are the additional directives in `as' for the HPPA: + These are the additional directives in 'as' for the HPPA: -`.block N' -`.blockz N' +'.block N' +'.blockz N' Reserve N bytes of storage, and initialize them to zero. -`.call' - Mark the beginning of a procedure call. Only the special case - with _no arguments_ is allowed. +'.call' + Mark the beginning of a procedure call. Only the special case with + _no arguments_ is allowed. -`.callinfo [ PARAM=VALUE, ... ] [ FLAG, ... ]' +'.callinfo [ PARAM=VALUE, ... ] [ FLAG, ... ]' Specify a number of parameters and flags that define the environment for a procedure. - PARAM may be any of `frame' (frame size), `entry_gr' (end of - general register range), `entry_fr' (end of float register range), - `entry_sr' (end of space register range). + PARAM may be any of 'frame' (frame size), 'entry_gr' (end of + general register range), 'entry_fr' (end of float register range), + 'entry_sr' (end of space register range). - The values for FLAG are `calls' or `caller' (proc has - subroutines), `no_calls' (proc does not call subroutines), - `save_rp' (preserve return pointer), `save_sp' (proc preserves - stack pointer), `no_unwind' (do not unwind this proc), `hpux_int' - (proc is interrupt routine). + The values for FLAG are 'calls' or 'caller' (proc has subroutines), + 'no_calls' (proc does not call subroutines), 'save_rp' (preserve + return pointer), 'save_sp' (proc preserves stack pointer), + 'no_unwind' (do not unwind this proc), 'hpux_int' (proc is + interrupt routine). -`.code' - Assemble into the standard section called `$TEXT$', subsection - `$CODE$'. +'.code' + Assemble into the standard section called '$TEXT$', subsection + '$CODE$'. -`.copyright "STRING"' +'.copyright "STRING"' In the SOM object format, insert STRING into the object code, marked as a copyright string. -`.copyright "STRING"' +'.copyright "STRING"' In the ELF object format, insert STRING into the object code, marked as a version string. -`.enter' +'.enter' Not yet supported; the assembler rejects programs containing this directive. -`.entry' +'.entry' Mark the beginning of a procedure. -`.exit' +'.exit' Mark the end of a procedure. -`.export NAME [ ,TYP ] [ ,PARAM=R ]' +'.export NAME [ ,TYP ] [ ,PARAM=R ]' Make a procedure NAME available to callers. TYP, if present, must - be one of `absolute', `code' (ELF only, not SOM), `data', `entry', - `data', `entry', `millicode', `plabel', `pri_prog', or `sec_prog'. + be one of 'absolute', 'code' (ELF only, not SOM), 'data', 'entry', + 'data', 'entry', 'millicode', 'plabel', 'pri_prog', or 'sec_prog'. PARAM, if present, provides either relocation information for the procedure arguments and result, or a privilege level. PARAM may be - `argwN' (where N ranges from `0' to `3', and indicates one of four - one-word arguments); `rtnval' (the procedure's result); or - `priv_lev' (privilege level). For arguments or the result, R - specifies how to relocate, and must be one of `no' (not - relocatable), `gr' (argument is in general register), `fr' (in - floating point register), or `fu' (upper half of float register). - For `priv_lev', R is an integer. - -`.half N' - Define a two-byte integer constant N; synonym for the portable - `as' directive `.short'. - -`.import NAME [ ,TYP ]' - Converse of `.export'; make a procedure available to call. The + 'argwN' (where N ranges from '0' to '3', and indicates one of four + one-word arguments); 'rtnval' (the procedure's result); or + 'priv_lev' (privilege level). For arguments or the result, R + specifies how to relocate, and must be one of 'no' (not + relocatable), 'gr' (argument is in general register), 'fr' (in + floating point register), or 'fu' (upper half of float register). + For 'priv_lev', R is an integer. + +'.half N' + Define a two-byte integer constant N; synonym for the portable 'as' + directive '.short'. + +'.import NAME [ ,TYP ]' + Converse of '.export'; make a procedure available to call. The arguments use the same conventions as the first two arguments for - `.export'. + '.export'. -`.label NAME' +'.label NAME' Define NAME as a label for the current assembly location. -`.leave' +'.leave' Not yet supported; the assembler rejects programs containing this directive. -`.origin LC' - Advance location counter to LC. Synonym for the `as' portable - directive `.org'. +'.origin LC' + Advance location counter to LC. Synonym for the 'as' portable + directive '.org'. -`.param NAME [ ,TYP ] [ ,PARAM=R ]' - Similar to `.export', but used for static procedures. +'.param NAME [ ,TYP ] [ ,PARAM=R ]' + Similar to '.export', but used for static procedures. -`.proc' +'.proc' Use preceding the first statement of a procedure. -`.procend' +'.procend' Use following the last statement of a procedure. -`LABEL .reg EXPR' - Synonym for `.equ'; define LABEL with the absolute expression EXPR +'LABEL .reg EXPR' + Synonym for '.equ'; define LABEL with the absolute expression EXPR as its value. -`.space SECNAME [ ,PARAMS ]' +'.space SECNAME [ ,PARAMS ]' Switch to section SECNAME, creating a new section by that name if necessary. You may only use PARAMS when creating a new section, not when switching to an existing one. SECNAME may identify a section by number rather than by name. If specified, the list PARAMS declares attributes of the section, - identified by keywords. The keywords recognized are `spnum=EXP' + identified by keywords. The keywords recognized are 'spnum=EXP' (identify this section by the number EXP, an absolute expression), - `sort=EXP' (order sections according to this sort key when linking; - EXP is an absolute expression), `unloadable' (section contains no - loadable data), `notdefined' (this section defined elsewhere), and - `private' (data in this section not available to other programs). + 'sort=EXP' (order sections according to this sort key when linking; + EXP is an absolute expression), 'unloadable' (section contains no + loadable data), 'notdefined' (this section defined elsewhere), and + 'private' (data in this section not available to other programs). -`.spnum SECNAM' +'.spnum SECNAM' Allocate four bytes of storage, and initialize them with the section number of the section named SECNAM. (You can define the - section number with the HPPA `.space' directive.) + section number with the HPPA '.space' directive.) -`.string "STR"' +'.string "STR"' Copy the characters in the string STR to the object file. *Note Strings: Strings, for information on escape sequences you can use - in `as' strings. + in 'as' strings. - _Warning!_ The HPPA version of `.string' differs from the usual - `as' definition: it does _not_ write a zero byte after copying STR. + _Warning!_ The HPPA version of '.string' differs from the usual + 'as' definition: it does _not_ write a zero byte after copying STR. -`.stringz "STR"' - Like `.string', but appends a zero byte after copying STR to object +'.stringz "STR"' + Like '.string', but appends a zero byte after copying STR to object file. -`.subspa NAME [ ,PARAMS ]' -`.nsubspa NAME [ ,PARAMS ]' - Similar to `.space', but selects a subsection NAME within the +'.subspa NAME [ ,PARAMS ]' +'.nsubspa NAME [ ,PARAMS ]' + Similar to '.space', but selects a subsection NAME within the current section. You may only specify PARAMS when you create a - subsection (in the first instance of `.subspa' for this NAME). + subsection (in the first instance of '.subspa' for this NAME). If specified, the list PARAMS declares attributes of the subsection, identified by keywords. The keywords recognized are - `quad=EXPR' ("quadrant" for this subsection), `align=EXPR' + 'quad=EXPR' ("quadrant" for this subsection), 'align=EXPR' (alignment for beginning of this subsection; a power of two), - `access=EXPR' (value for "access rights" field), `sort=EXPR' - (sorting order for this subspace in link), `code_only' (subsection - contains only code), `unloadable' (subsection cannot be loaded - into memory), `comdat' (subsection is comdat), `common' - (subsection is common block), `dup_comm' (subsection may have - duplicate names), or `zero' (subsection is all zeros, do not write - in object file). - - `.nsubspa' always creates a new subspace with the given name, even + 'access=EXPR' (value for "access rights" field), 'sort=EXPR' + (sorting order for this subspace in link), 'code_only' (subsection + contains only code), 'unloadable' (subsection cannot be loaded into + memory), 'comdat' (subsection is comdat), 'common' (subsection is + common block), 'dup_comm' (subsection may have duplicate names), or + 'zero' (subsection is all zeros, do not write in object file). + + '.nsubspa' always creates a new subspace with the given name, even if one with the same name already exists. - `comdat', `common' and `dup_comm' can be used to implement various + 'comdat', 'common' and 'dup_comm' can be used to implement various flavors of one-only support when using the SOM linker. The SOM linker only supports specific combinations of these flags. The details are not documented. A brief description is provided here. - `comdat' provides a form of linkonce support. It is useful for - both code and data subspaces. A `comdat' subspace has a key symbol - marked by the `is_comdat' flag or `ST_COMDAT'. Only the first + 'comdat' provides a form of linkonce support. It is useful for + both code and data subspaces. A 'comdat' subspace has a key symbol + marked by the 'is_comdat' flag or 'ST_COMDAT'. Only the first subspace for any given key is selected. The key symbol becomes universal in shared links. This is similar to the behavior of - `secondary_def' symbols. + 'secondary_def' symbols. - `common' provides Fortran named common support. It is only useful - for data subspaces. Symbols with the flag `is_common' retain this - flag in shared links. Referencing a `is_common' symbol in a shared - library from outside the library doesn't work. Thus, `is_common' + 'common' provides Fortran named common support. It is only useful + for data subspaces. Symbols with the flag 'is_common' retain this + flag in shared links. Referencing a 'is_common' symbol in a shared + library from outside the library doesn't work. Thus, 'is_common' symbols must be output whenever they are needed. - `common' and `dup_comm' together provide Cobol common support. - The subspaces in this case must all be the same length. - Otherwise, this support is similar to the Fortran common support. + 'common' and 'dup_comm' together provide Cobol common support. The + subspaces in this case must all be the same length. Otherwise, + this support is similar to the Fortran common support. - `dup_comm' by itself provides a type of one-only support for code. - Only the first `dup_comm' subspace is selected. There is a rather + 'dup_comm' by itself provides a type of one-only support for code. + Only the first 'dup_comm' subspace is selected. There is a rather complex algorithm to compare subspaces. Code symbols marked with - the `dup_common' flag are hidden. This support was intended for + the 'dup_common' flag are hidden. This support was intended for "C++ duplicate inlines". A simplified technique is used to mark the flags of symbols based on the flags of their subspace. A symbol with the scope SS_UNIVERSAL and type ST_ENTRY, ST_CODE or ST_DATA is marked with - the corresponding settings of `comdat', `common' and `dup_comm' + the corresponding settings of 'comdat', 'common' and 'dup_comm' from the subspace, respectively. This avoids having to introduce - additional directives to mark these symbols. The HP assembler - sets `is_common' from `common'. However, it doesn't set the - `dup_common' from `dup_comm'. It doesn't have `comdat' support. + additional directives to mark these symbols. The HP assembler sets + 'is_common' from 'common'. However, it doesn't set the + 'dup_common' from 'dup_comm'. It doesn't have 'comdat' support. -`.version "STR"' +'.version "STR"' Write STR as version identifier in object code. @@ -9875,7 +9611,7 @@ File: as.info, Node: HPPA Opcodes, Prev: HPPA Directives, Up: HPPA-Dependent -------------- For detailed information on the HPPA machine instruction set, see -`PA-RISC Architecture and Instruction Set Reference Manual' (HP +'PA-RISC Architecture and Instruction Set Reference Manual' (HP 09740-90039). @@ -9899,13 +9635,13 @@ File: as.info, Node: ESA/390 Notes, Next: ESA/390 Options, Up: ESA/390-Depend 9.14.1 Notes ------------ -The ESA/390 `as' port is currently intended to be a back-end for the -GNU CC compiler. It is not HLASM compatible, although it does support -a subset of some of the HLASM directives. The only supported binary -file format is ELF; none of the usual MVS/VM/OE/USS object file -formats, such as ESD or XSD, are supported. +The ESA/390 'as' port is currently intended to be a back-end for the GNU +CC compiler. It is not HLASM compatible, although it does support a +subset of some of the HLASM directives. The only supported binary file +format is ELF; none of the usual MVS/VM/OE/USS object file formats, such +as ESD or XSD, are supported. - When used with the GNU CC compiler, the ESA/390 `as' will produce + When used with the GNU CC compiler, the ESA/390 'as' will produce correct, fully relocated, functional binaries, and has been used to compile and execute large projects. However, many aspects should still be considered experimental; these include shared library support, @@ -9918,7 +9654,7 @@ File: as.info, Node: ESA/390 Options, Next: ESA/390 Syntax, Prev: ESA/390 Not 9.14.2 Options -------------- -`as' has no machine-dependent command-line options for the ESA/390. +'as' has no machine-dependent command-line options for the ESA/390. File: as.info, Node: ESA/390 Syntax, Next: ESA/390 Floating Point, Prev: ESA/390 Options, Up: ESA/390-Dependent @@ -9940,24 +9676,24 @@ effect. for compatibility with how most assembly language programmers write code. - `#' is the line comment character. + '#' is the line comment character. - `;' can be used instead of a newline to separate statements. + ';' can be used instead of a newline to separate statements. - Since `$' has no special meaning, you may use it in symbol names. + Since '$' has no special meaning, you may use it in symbol names. Registers can be given the symbolic names r0..r15, fp0, fp2, fp4, -fp6. By using thesse symbolic names, `as' can detect simple syntax -errors. The name rarg or r.arg is a synonym for r11, rtca or r.tca for +fp6. By using thesse symbolic names, 'as' can detect simple syntax +errors. The name rarg or r.arg is a synonym for r11, rtca or r.tca for r12, sp, r.sp, dsa r.dsa for r13, lr or r.lr for r14, rbase or r.base for r3 and rpgt or r.pgt for r4. - `*' is the current location counter. Unlike `.' it is always + '*' is the current location counter. Unlike '.' it is always relative to the last USING directive. Note that this means that -expressions cannot use multiplication, as any occurrence of `*' will be +expressions cannot use multiplication, as any occurrence of '*' will be interpreted as a location counter. - All labels are relative to the last USING. Thus, branches to a label + All labels are relative to the last USING. Thus, branches to a label always imply the use of base+displacement. Many of the usual forms of address constants / address literals are @@ -9974,7 +9710,7 @@ supported. Thus, should all behave as expected: that is, an entry in the literal pool will be created (or reused if it already exists), and the instruction operands will be the displacement into the literal pool using the -current base register (as last declared with the `.using' directive). +current base register (as last declared with the '.using' directive). File: as.info, Node: ESA/390 Floating Point, Next: ESA/390 Directives, Prev: ESA/390 Syntax, Up: ESA/390-Dependent @@ -9991,59 +9727,59 @@ File: as.info, Node: ESA/390 Directives, Next: ESA/390 Opcodes, Prev: ESA/390 9.14.5 ESA/390 Assembler Directives ----------------------------------- -`as' for the ESA/390 supports all of the standard ELF/SVR4 assembler +'as' for the ESA/390 supports all of the standard ELF/SVR4 assembler directives that are documented in the main part of this documentation. Several additional directives are supported in order to implement the -ESA/390 addressing model. The most important of these are `.using' and -`.ltorg' +ESA/390 addressing model. The most important of these are '.using' and +'.ltorg' - These are the additional directives in `as' for the ESA/390: + These are the additional directives in 'as' for the ESA/390: -`.dc' +'.dc' A small subset of the usual DC directive is supported. -`.drop REGNO' +'.drop REGNO' Stop using REGNO as the base register. The REGNO must have been - previously declared with a `.using' directive in the same section + previously declared with a '.using' directive in the same section as the current section. -`.ebcdic STRING' +'.ebcdic STRING' Emit the EBCDIC equivalent of the indicated string. The emitted - string will be null terminated. Note that the directives - `.string' etc. emit ascii strings by default. + string will be null terminated. Note that the directives '.string' + etc. emit ascii strings by default. -`EQU' +'EQU' The standard HLASM-style EQU directive is not supported; however, - the standard `as' directive .equ can be used to the same effect. + the standard 'as' directive .equ can be used to the same effect. -`.ltorg' +'.ltorg' Dump the literal pool accumulated so far; begin a new literal pool. The literal pool will be written in the current section; in order - to generate correct assembly, a `.using' must have been previously + to generate correct assembly, a '.using' must have been previously specified in the same section. -`.using EXPR,REGNO' +'.using EXPR,REGNO' Use REGNO as the base register for all subsequent RX, RS, and SS - form instructions. The EXPR will be evaluated to obtain the base - address; usually, EXPR will merely be `*'. + form instructions. The EXPR will be evaluated to obtain the base + address; usually, EXPR will merely be '*'. - This assembler allows two `.using' directives to be simultaneously - outstanding, one in the `.text' section, and one in another section - (typically, the `.data' section). This feature allows dynamically + This assembler allows two '.using' directives to be simultaneously + outstanding, one in the '.text' section, and one in another section + (typically, the '.data' section). This feature allows dynamically loaded objects to be implemented in a relatively straightforward - way. A `.using' directive must always be specified in the `.text' + way. A '.using' directive must always be specified in the '.text' section; this will specify the base register that will be used for - branches in the `.text' section. A second `.using' may be + branches in the '.text' section. A second '.using' may be specified in another section; this will specify the base register that is used for non-label address literals. When a second - `.using' is specified, then the subsequent `.ltorg' must be put in + '.using' is specified, then the subsequent '.ltorg' must be put in the same section; otherwise an error will result. - Thus, for example, the following code uses `r3' to address branch - targets and `r4' to address the literal pool, which has been - written to the `.data' section. The is, the constants - `=A(some_routine)', `=H'42'' and `=E'3.1416'' will all appear in - the `.data' section. + Thus, for example, the following code uses 'r3' to address branch + targets and 'r4' to address the literal pool, which has been + written to the '.data' section. The is, the constants + '=A(some_routine)', '=H'42'' and '=E'3.1416'' will all appear in + the '.data' section. .data .using LITPOOL,r4 @@ -10064,11 +9800,10 @@ ESA/390 addressing model. The most important of these are `.using' and LITPOOL: .ltorg - Note that this dual-`.using' directive semantics extends and is - not compatible with HLASM semantics. Note that this assembler + Note that this dual-'.using' directive semantics extends and is not + compatible with HLASM semantics. Note that this assembler directive does not support the full range of HLASM semantics. - File: as.info, Node: ESA/390 Opcodes, Prev: ESA/390 Directives, Up: ESA/390-Dependent @@ -10076,7 +9811,7 @@ File: as.info, Node: ESA/390 Opcodes, Prev: ESA/390 Directives, Up: ESA/390-D -------------- For detailed information on the ESA/390 machine instruction set, see -`ESA/390 Principles of Operation' (IBM Publication Number DZ9AR004). +'ESA/390 Principles of Operation' (IBM Publication Number DZ9AR004). File: as.info, Node: i386-Dependent, Next: i860-Dependent, Prev: ESA/390-Dependent, Up: Machine Dependencies @@ -10084,9 +9819,9 @@ File: as.info, Node: i386-Dependent, Next: i860-Dependent, Prev: ESA/390-Depe 9.15 80386 Dependent Features ============================= - The i386 version `as' supports both the original Intel 386 -architecture in both 16 and 32-bit mode as well as AMD x86-64 -architecture extending the Intel architecture to 64-bits. +The i386 version 'as' supports both the original Intel 386 architecture +in both 16 and 32-bit mode as well as AMD x86-64 architecture extending +the Intel architecture to 64-bits. * Menu: @@ -10114,11 +9849,11 @@ File: as.info, Node: i386-Options, Next: i386-Directives, Up: i386-Dependent 9.15.1 Options -------------- -The i386 version of `as' has a few machine dependent options: +The i386 version of 'as' has a few machine dependent options: -`--32 | --x32 | --64' - Select the word size, either 32 bits or 64 bits. `--32' implies - Intel i386 architecture, while `--x32' and `--64' imply AMD x86-64 +'--32 | --x32 | --64' + Select the word size, either 32 bits or 64 bits. '--32' implies + Intel i386 architecture, while '--x32' and '--64' imply AMD x86-64 architecture with 32-bit or 64-bit word-size respectively. These options are only available with the ELF object file format, @@ -10126,94 +9861,116 @@ The i386 version of `as' has a few machine dependent options: 32-bit platform you have to add -enable-64-bit-bfd to configure enable 64-bit usage and use x86-64 as target platform). -`-n' +'-n' By default, x86 GAS replaces multiple nop instructions used for alignment within code sections with multi-byte nop instructions such as leal 0(%esi,1),%esi. This switch disables the optimization. -`--divide' - On SVR4-derived platforms, the character `/' is treated as a +'--divide' + On SVR4-derived platforms, the character '/' is treated as a comment character, which means that it cannot be used in - expressions. The `--divide' option turns `/' into a normal - character. This does not disable `/' at the beginning of a line - starting a comment, or affect using `#' for starting a comment. + expressions. The '--divide' option turns '/' into a normal + character. This does not disable '/' at the beginning of a line + starting a comment, or affect using '#' for starting a comment. -`-march=CPU[+EXTENSION...]' +'-march=CPU[+EXTENSION...]' This option specifies the target processor. The assembler will issue an error message if an attempt is made to assemble an instruction which will not execute on the target processor. The - following processor names are recognized: `i8086', `i186', `i286', - `i386', `i486', `i586', `i686', `pentium', `pentiumpro', - `pentiumii', `pentiumiii', `pentium4', `prescott', `nocona', - `core', `core2', `corei7', `l1om', `k1om', `k6', `k6_2', `athlon', - `opteron', `k8', `amdfam10', `bdver1', `bdver2', `bdver3', - `btver1', `btver2', `generic32' and `generic64'. - - In addition to the basic instruction set, the assembler can be - told to accept various extension mnemonics. For example, - `-march=i686+sse4+vmx' extends I686 with SSE4 and VMX. The - following extensions are currently supported: `8087', `287', `387', - `no87', `mmx', `nommx', `sse', `sse2', `sse3', `ssse3', `sse4.1', - `sse4.2', `sse4', `nosse', `avx', `avx2', `adx', `rdseed', - `prfchw', `smap', `noavx', `vmx', `vmfunc', `smx', `xsave', - `xsaveopt', `aes', `pclmul', `fsgsbase', `rdrnd', `f16c', `bmi2', - `fma', `movbe', `ept', `lzcnt', `hle', `rtm', `invpcid', `clflush', - `lwp', `fma4', `xop', `cx16', `syscall', `rdtscp', `3dnow', - `3dnowa', `sse4a', `sse5', `svme', `abm' and `padlock'. Note that - rather than extending a basic instruction set, the extension - mnemonics starting with `no' revoke the respective functionality. - - When the `.arch' directive is used with `-march', the `.arch' + following processor names are recognized: 'i8086', 'i186', 'i286', + 'i386', 'i486', 'i586', 'i686', 'pentium', 'pentiumpro', + 'pentiumii', 'pentiumiii', 'pentium4', 'prescott', 'nocona', + 'core', 'core2', 'corei7', 'l1om', 'k1om', 'k6', 'k6_2', 'athlon', + 'opteron', 'k8', 'amdfam10', 'bdver1', 'bdver2', 'bdver3', + 'btver1', 'btver2', 'generic32' and 'generic64'. + + In addition to the basic instruction set, the assembler can be told + to accept various extension mnemonics. For example, + '-march=i686+sse4+vmx' extends I686 with SSE4 and VMX. The + following extensions are currently supported: '8087', '287', '387', + 'no87', 'mmx', 'nommx', 'sse', 'sse2', 'sse3', 'ssse3', 'sse4.1', + 'sse4.2', 'sse4', 'nosse', 'avx', 'avx2', 'adx', 'rdseed', + 'prfchw', 'smap', 'mpx', 'sha', 'avx512f', 'avx512cd', 'avx512er', + 'avx512pf', 'noavx', 'vmx', 'vmfunc', 'smx', 'xsave', 'xsaveopt', + 'aes', 'pclmul', 'fsgsbase', 'rdrnd', 'f16c', 'bmi2', 'fma', + 'movbe', 'ept', 'lzcnt', 'hle', 'rtm', 'invpcid', 'clflush', 'lwp', + 'fma4', 'xop', 'cx16', 'syscall', 'rdtscp', '3dnow', '3dnowa', + 'sse4a', 'sse5', 'svme', 'abm' and 'padlock'. Note that rather + than extending a basic instruction set, the extension mnemonics + starting with 'no' revoke the respective functionality. + + When the '.arch' directive is used with '-march', the '.arch' directive will take precedent. -`-mtune=CPU' - This option specifies a processor to optimize for. When used in - conjunction with the `-march' option, only instructions of the - processor specified by the `-march' option will be generated. +'-mtune=CPU' + This option specifies a processor to optimize for. When used in + conjunction with the '-march' option, only instructions of the + processor specified by the '-march' option will be generated. Valid CPU values are identical to the processor list of - `-march=CPU'. + '-march=CPU'. -`-msse2avx' +'-msse2avx' This option specifies that the assembler should encode SSE instructions with VEX prefix. -`-msse-check=NONE' -`-msse-check=WARNING' -`-msse-check=ERROR' +'-msse-check=NONE' +'-msse-check=WARNING' +'-msse-check=ERROR' These options control if the assembler should check SSE - intructions. `-msse-check=NONE' will make the assembler not to - check SSE instructions, which is the default. - `-msse-check=WARNING' will make the assembler issue a warning for - any SSE intruction. `-msse-check=ERROR' will make the assembler - issue an error for any SSE intruction. - -`-mavxscalar=128' -`-mavxscalar=256' + instructions. '-msse-check=NONE' will make the assembler not to + check SSE instructions, which is the default. + '-msse-check=WARNING' will make the assembler issue a warning for + any SSE instruction. '-msse-check=ERROR' will make the assembler + issue an error for any SSE instruction. + +'-mavxscalar=128' +'-mavxscalar=256' These options control how the assembler should encode scalar AVX - instructions. `-mavxscalar=128' will encode scalar AVX + instructions. '-mavxscalar=128' will encode scalar AVX instructions with 128bit vector length, which is the default. - `-mavxscalar=256' will encode scalar AVX instructions with 256bit + '-mavxscalar=256' will encode scalar AVX instructions with 256bit vector length. -`-mmnemonic=ATT' -`-mmnemonic=INTEL' +'-mevexlig=128' +'-mevexlig=256' +'-mevexlig=512' + These options control how the assembler should encode + length-ignored (LIG) EVEX instructions. '-mevexlig=128' will + encode LIG EVEX instructions with 128bit vector length, which is + the default. '-mevexlig=256' and '-mevexlig=512' will encode LIG + EVEX instructions with 256bit and 512bit vector length, + respectively. + +'-mevexwig=0' +'-mevexwig=1' + These options control how the assembler should encode w-ignored + (WIG) EVEX instructions. '-mevexwig=0' will encode WIG EVEX + instructions with evex.w = 0, which is the default. '-mevexwig=1' + will encode WIG EVEX instructions with evex.w = 1. + +'-mmnemonic=ATT' +'-mmnemonic=INTEL' This option specifies instruction mnemonic for matching - instructions. The `.att_mnemonic' and `.intel_mnemonic' - directives will take precedent. + instructions. The '.att_mnemonic' and '.intel_mnemonic' directives + will take precedent. -`-msyntax=ATT' -`-msyntax=INTEL' +'-msyntax=ATT' +'-msyntax=INTEL' This option specifies instruction syntax when processing - instructions. The `.att_syntax' and `.intel_syntax' directives + instructions. The '.att_syntax' and '.intel_syntax' directives will take precedent. -`-mnaked-reg' - This opetion specifies that registers don't require a `%' prefix. - The `.att_syntax' and `.intel_syntax' directives will take +'-mnaked-reg' + This opetion specifies that registers don't require a '%' prefix. + The '.att_syntax' and '.intel_syntax' directives will take precedent. +'-madd-bnd-prefix' + This option forces the assembler to add BND prefix to all branches, + even if such prefix was not explicitly specified in the source + code. File: as.info, Node: i386-Directives, Next: i386-Syntax, Prev: i386-Options, Up: i386-Dependent @@ -10221,18 +9978,17 @@ File: as.info, Node: i386-Directives, Next: i386-Syntax, Prev: i386-Options, 9.15.2 x86 specific Directives ------------------------------ -`.lcomm SYMBOL , LENGTH[, ALIGNMENT]' +'.lcomm SYMBOL , LENGTH[, ALIGNMENT]' Reserve LENGTH (an absolute expression) bytes for a local common denoted by SYMBOL. The section and value of SYMBOL are those of the new local common. The addresses are allocated in the bss section, so that at run-time the bytes start off zeroed. Since - SYMBOL is not declared global, it is normally not visible to `ld'. + SYMBOL is not declared global, it is normally not visible to 'ld'. The optional third parameter, ALIGNMENT, specifies the desired alignment of the symbol in the bss section. This directive is only available for COFF based x86 targets. - File: as.info, Node: i386-Syntax, Next: i386-Mnemonics, Prev: i386-Directives, Up: i386-Dependent @@ -10250,45 +10006,44 @@ File: as.info, Node: i386-Variations, Next: i386-Chars, Up: i386-Syntax 9.15.3.1 AT&T Syntax versus Intel Syntax ........................................ -`as' now supports assembly using Intel assembler syntax. -`.intel_syntax' selects Intel mode, and `.att_syntax' switches back to -the usual AT&T mode for compatibility with the output of `gcc'. Either -of these directives may have an optional argument, `prefix', or -`noprefix' specifying whether registers require a `%' prefix. AT&T +'as' now supports assembly using Intel assembler syntax. +'.intel_syntax' selects Intel mode, and '.att_syntax' switches back to +the usual AT&T mode for compatibility with the output of 'gcc'. Either +of these directives may have an optional argument, 'prefix', or +'noprefix' specifying whether registers require a '%' prefix. AT&T System V/386 assembler syntax is quite different from Intel syntax. We mention these differences because almost all 80386 documents use Intel syntax. Notable differences between the two syntaxes are: - * AT&T immediate operands are preceded by `$'; Intel immediate - operands are undelimited (Intel `push 4' is AT&T `pushl $4'). - AT&T register operands are preceded by `%'; Intel register operands - are undelimited. AT&T absolute (as opposed to PC relative) - jump/call operands are prefixed by `*'; they are undelimited in - Intel syntax. + * AT&T immediate operands are preceded by '$'; Intel immediate + operands are undelimited (Intel 'push 4' is AT&T 'pushl $4'). AT&T + register operands are preceded by '%'; Intel register operands are + undelimited. AT&T absolute (as opposed to PC relative) jump/call + operands are prefixed by '*'; they are undelimited in Intel syntax. * AT&T and Intel syntax use the opposite order for source and - destination operands. Intel `add eax, 4' is `addl $4, %eax'. The - `source, dest' convention is maintained for compatibility with - previous Unix assemblers. Note that `bound', `invlpga', and - instructions with 2 immediate operands, such as the `enter' + destination operands. Intel 'add eax, 4' is 'addl $4, %eax'. The + 'source, dest' convention is maintained for compatibility with + previous Unix assemblers. Note that 'bound', 'invlpga', and + instructions with 2 immediate operands, such as the 'enter' instruction, do _not_ have reversed order. *note i386-Bugs::. * In AT&T syntax the size of memory operands is determined from the last character of the instruction mnemonic. Mnemonic suffixes of - `b', `w', `l' and `q' specify byte (8-bit), word (16-bit), long + 'b', 'w', 'l' and 'q' specify byte (8-bit), word (16-bit), long (32-bit) and quadruple word (64-bit) memory references. Intel syntax accomplishes this by prefixing memory operands (_not_ the - instruction mnemonics) with `byte ptr', `word ptr', `dword ptr' - and `qword ptr'. Thus, Intel `mov al, byte ptr FOO' is `movb FOO, - %al' in AT&T syntax. + instruction mnemonics) with 'byte ptr', 'word ptr', 'dword ptr' and + 'qword ptr'. Thus, Intel 'mov al, byte ptr FOO' is 'movb FOO, %al' + in AT&T syntax. - In 64-bit code, `movabs' can be used to encode the `mov' + In 64-bit code, 'movabs' can be used to encode the 'mov' instruction with the 64-bit displacement or immediate operand. - * Immediate form long jumps and calls are `lcall/ljmp $SECTION, - $OFFSET' in AT&T syntax; the Intel syntax is `call/jmp far - SECTION:OFFSET'. Also, the far return instruction is `lret - $STACK-ADJUST' in AT&T syntax; Intel syntax is `ret far + * Immediate form long jumps and calls are 'lcall/ljmp $SECTION, + $OFFSET' in AT&T syntax; the Intel syntax is 'call/jmp far + SECTION:OFFSET'. Also, the far return instruction is 'lret + $STACK-ADJUST' in AT&T syntax; Intel syntax is 'ret far STACK-ADJUST'. * The AT&T assembler does not provide support for multiple section @@ -10301,19 +10056,19 @@ File: as.info, Node: i386-Chars, Prev: i386-Variations, Up: i386-Syntax 9.15.3.2 Special Characters ........................... -The presence of a `#' appearing anywhere on a line indicates the start +The presence of a '#' appearing anywhere on a line indicates the start of a comment that extends to the end of that line. - If a `#' appears as the first character of a line then the whole -line is treated as a comment, but in this case the line can also be a -logical line number directive (*note Comments::) or a preprocessor -control command (*note Preprocessing::). + If a '#' appears as the first character of a line then the whole line +is treated as a comment, but in this case the line can also be a logical +line number directive (*note Comments::) or a preprocessor control +command (*note Preprocessing::). - If the `--divide' command line option has not been specified then -the `/' character appearing anywhere on a line also introduces a line + If the '--divide' command line option has not been specified then the +'/' character appearing anywhere on a line also introduces a line comment. - The `;' character can be used to separate statements on the same + The ';' character can be used to separate statements on the same line. @@ -10323,69 +10078,68 @@ File: as.info, Node: i386-Mnemonics, Next: i386-Regs, Prev: i386-Syntax, Up: ------------------------- Instruction mnemonics are suffixed with one character modifiers which -specify the size of operands. The letters `b', `w', `l' and `q' -specify byte, word, long and quadruple word operands. If no suffix is -specified by an instruction then `as' tries to fill in the missing -suffix based on the destination register operand (the last one by -convention). Thus, `mov %ax, %bx' is equivalent to `movw %ax, %bx'; -also, `mov $1, %bx' is equivalent to `movw $1, bx'. Note that this is -incompatible with the AT&T Unix assembler which assumes that a missing -mnemonic suffix implies long operand size. (This incompatibility does -not affect compiler output since compilers always explicitly specify -the mnemonic suffix.) +specify the size of operands. The letters 'b', 'w', 'l' and 'q' specify +byte, word, long and quadruple word operands. If no suffix is specified +by an instruction then 'as' tries to fill in the missing suffix based on +the destination register operand (the last one by convention). Thus, +'mov %ax, %bx' is equivalent to 'movw %ax, %bx'; also, 'mov $1, %bx' is +equivalent to 'movw $1, bx'. Note that this is incompatible with the +AT&T Unix assembler which assumes that a missing mnemonic suffix implies +long operand size. (This incompatibility does not affect compiler +output since compilers always explicitly specify the mnemonic suffix.) Almost all instructions have the same names in AT&T and Intel format. There are a few exceptions. The sign extend and zero extend instructions need two sizes to specify them. They need a size to sign/zero extend _from_ and a size to zero extend _to_. This is accomplished by using two instruction mnemonic suffixes in AT&T syntax. -Base names for sign extend and zero extend are `movs...' and `movz...' -in AT&T syntax (`movsx' and `movzx' in Intel syntax). The instruction +Base names for sign extend and zero extend are 'movs...' and 'movz...' +in AT&T syntax ('movsx' and 'movzx' in Intel syntax). The instruction mnemonic suffixes are tacked on to this base name, the _from_ suffix -before the _to_ suffix. Thus, `movsbl %al, %edx' is AT&T syntax for +before the _to_ suffix. Thus, 'movsbl %al, %edx' is AT&T syntax for "move sign extend _from_ %al _to_ %edx." Possible suffixes, thus, are -`bl' (from byte to long), `bw' (from byte to word), `wl' (from word to -long), `bq' (from byte to quadruple word), `wq' (from word to quadruple -word), and `lq' (from long to quadruple word). +'bl' (from byte to long), 'bw' (from byte to word), 'wl' (from word to +long), 'bq' (from byte to quadruple word), 'wq' (from word to quadruple +word), and 'lq' (from long to quadruple word). Different encoding options can be specified via optional mnemonic -suffix. `.s' suffix swaps 2 register operands in encoding when moving -from one register to another. `.d8' or `.d32' suffix prefers 8bit or +suffix. '.s' suffix swaps 2 register operands in encoding when moving +from one register to another. '.d8' or '.d32' suffix prefers 8bit or 32bit displacement in encoding. The Intel-syntax conversion instructions - * `cbw' -- sign-extend byte in `%al' to word in `%ax', + * 'cbw' -- sign-extend byte in '%al' to word in '%ax', - * `cwde' -- sign-extend word in `%ax' to long in `%eax', + * 'cwde' -- sign-extend word in '%ax' to long in '%eax', - * `cwd' -- sign-extend word in `%ax' to long in `%dx:%ax', + * 'cwd' -- sign-extend word in '%ax' to long in '%dx:%ax', - * `cdq' -- sign-extend dword in `%eax' to quad in `%edx:%eax', + * 'cdq' -- sign-extend dword in '%eax' to quad in '%edx:%eax', - * `cdqe' -- sign-extend dword in `%eax' to quad in `%rax' (x86-64 + * 'cdqe' -- sign-extend dword in '%eax' to quad in '%rax' (x86-64 only), - * `cqo' -- sign-extend quad in `%rax' to octuple in `%rdx:%rax' + * 'cqo' -- sign-extend quad in '%rax' to octuple in '%rdx:%rax' (x86-64 only), -are called `cbtw', `cwtl', `cwtd', `cltd', `cltq', and `cqto' in AT&T -naming. `as' accepts either naming for these instructions. +are called 'cbtw', 'cwtl', 'cwtd', 'cltd', 'cltq', and 'cqto' in AT&T +naming. 'as' accepts either naming for these instructions. - Far call/jump instructions are `lcall' and `ljmp' in AT&T syntax, -but are `call far' and `jump far' in Intel convention. + Far call/jump instructions are 'lcall' and 'ljmp' in AT&T syntax, but +are 'call far' and 'jump far' in Intel convention. 9.15.5 AT&T Mnemonic versus Intel Mnemonic ------------------------------------------ -`as' supports assembly using Intel mnemonic. `.intel_mnemonic' selects -Intel mnemonic with Intel syntax, and `.att_mnemonic' switches back to +'as' supports assembly using Intel mnemonic. '.intel_mnemonic' selects +Intel mnemonic with Intel syntax, and '.att_mnemonic' switches back to the usual AT&T mnemonic with AT&T syntax for compatibility with the -output of `gcc'. Several x87 instructions, `fadd', `fdiv', `fdivp', -`fdivr', `fdivrp', `fmul', `fsub', `fsubp', `fsubr' and `fsubrp', are -implemented in AT&T System V/386 assembler with different mnemonics -from those in Intel IA32 specification. `gcc' generates those -instructions with AT&T mnemonic. +output of 'gcc'. Several x87 instructions, 'fadd', 'fdiv', 'fdivp', +'fdivr', 'fdivrp', 'fmul', 'fsub', 'fsubp', 'fsubr' and 'fsubrp', are +implemented in AT&T System V/386 assembler with different mnemonics from +those in Intel IA32 specification. 'gcc' generates those instructions +with AT&T mnemonic. File: as.info, Node: i386-Regs, Next: i386-Prefixes, Prev: i386-Mnemonics, Up: i386-Dependent @@ -10393,58 +10147,57 @@ File: as.info, Node: i386-Regs, Next: i386-Prefixes, Prev: i386-Mnemonics, U 9.15.6 Register Naming ---------------------- -Register operands are always prefixed with `%'. The 80386 registers +Register operands are always prefixed with '%'. The 80386 registers consist of - * the 8 32-bit registers `%eax' (the accumulator), `%ebx', `%ecx', - `%edx', `%edi', `%esi', `%ebp' (the frame pointer), and `%esp' - (the stack pointer). + * the 8 32-bit registers '%eax' (the accumulator), '%ebx', '%ecx', + '%edx', '%edi', '%esi', '%ebp' (the frame pointer), and '%esp' (the + stack pointer). - * the 8 16-bit low-ends of these: `%ax', `%bx', `%cx', `%dx', `%di', - `%si', `%bp', and `%sp'. + * the 8 16-bit low-ends of these: '%ax', '%bx', '%cx', '%dx', '%di', + '%si', '%bp', and '%sp'. - * the 8 8-bit registers: `%ah', `%al', `%bh', `%bl', `%ch', `%cl', - `%dh', and `%dl' (These are the high-bytes and low-bytes of `%ax', - `%bx', `%cx', and `%dx') + * the 8 8-bit registers: '%ah', '%al', '%bh', '%bl', '%ch', '%cl', + '%dh', and '%dl' (These are the high-bytes and low-bytes of '%ax', + '%bx', '%cx', and '%dx') - * the 6 section registers `%cs' (code section), `%ds' (data - section), `%ss' (stack section), `%es', `%fs', and `%gs'. + * the 6 section registers '%cs' (code section), '%ds' (data section), + '%ss' (stack section), '%es', '%fs', and '%gs'. - * the 3 processor control registers `%cr0', `%cr2', and `%cr3'. + * the 3 processor control registers '%cr0', '%cr2', and '%cr3'. - * the 6 debug registers `%db0', `%db1', `%db2', `%db3', `%db6', and - `%db7'. + * the 6 debug registers '%db0', '%db1', '%db2', '%db3', '%db6', and + '%db7'. - * the 2 test registers `%tr6' and `%tr7'. + * the 2 test registers '%tr6' and '%tr7'. - * the 8 floating point register stack `%st' or equivalently - `%st(0)', `%st(1)', `%st(2)', `%st(3)', `%st(4)', `%st(5)', - `%st(6)', and `%st(7)'. These registers are overloaded by 8 MMX - registers `%mm0', `%mm1', `%mm2', `%mm3', `%mm4', `%mm5', `%mm6' - and `%mm7'. + * the 8 floating point register stack '%st' or equivalently '%st(0)', + '%st(1)', '%st(2)', '%st(3)', '%st(4)', '%st(5)', '%st(6)', and + '%st(7)'. These registers are overloaded by 8 MMX registers + '%mm0', '%mm1', '%mm2', '%mm3', '%mm4', '%mm5', '%mm6' and '%mm7'. - * the 8 SSE registers registers `%xmm0', `%xmm1', `%xmm2', `%xmm3', - `%xmm4', `%xmm5', `%xmm6' and `%xmm7'. + * the 8 SSE registers registers '%xmm0', '%xmm1', '%xmm2', '%xmm3', + '%xmm4', '%xmm5', '%xmm6' and '%xmm7'. The AMD x86-64 architecture extends the register set by: - * enhancing the 8 32-bit registers to 64-bit: `%rax' (the - accumulator), `%rbx', `%rcx', `%rdx', `%rdi', `%rsi', `%rbp' (the - frame pointer), `%rsp' (the stack pointer) + * enhancing the 8 32-bit registers to 64-bit: '%rax' (the + accumulator), '%rbx', '%rcx', '%rdx', '%rdi', '%rsi', '%rbp' (the + frame pointer), '%rsp' (the stack pointer) - * the 8 extended registers `%r8'-`%r15'. + * the 8 extended registers '%r8'-'%r15'. - * the 8 32-bit low ends of the extended registers: `%r8d'-`%r15d' + * the 8 32-bit low ends of the extended registers: '%r8d'-'%r15d' - * the 8 16-bit low ends of the extended registers: `%r8w'-`%r15w' + * the 8 16-bit low ends of the extended registers: '%r8w'-'%r15w' - * the 8 8-bit low ends of the extended registers: `%r8b'-`%r15b' + * the 8 8-bit low ends of the extended registers: '%r8b'-'%r15b' - * the 4 8-bit registers: `%sil', `%dil', `%bpl', `%spl'. + * the 4 8-bit registers: '%sil', '%dil', '%bpl', '%spl'. - * the 8 debug registers: `%db8'-`%db15'. + * the 8 debug registers: '%db8'-'%db15'. - * the 8 SSE registers: `%xmm8'-`%xmm15'. + * the 8 SSE registers: '%xmm8'-'%xmm15'. File: as.info, Node: i386-Prefixes, Next: i386-Memory, Prev: i386-Regs, Up: i386-Dependent @@ -10458,51 +10211,50 @@ perform bus lock operations, and to change operand and address sizes. (Most instructions that normally operate on 32-bit operands will use 16-bit operands if the instruction has an "operand size" prefix.) Instruction prefixes are best written on the same line as the -instruction they act upon. For example, the `scas' (scan string) +instruction they act upon. For example, the 'scas' (scan string) instruction is repeated with: repne scas %es:(%edi),%al You may also place prefixes on the lines immediately preceding the -instruction, but this circumvents checks that `as' does with prefixes, +instruction, but this circumvents checks that 'as' does with prefixes, and will not work with all prefixes. Here is a list of instruction prefixes: - * Section override prefixes `cs', `ds', `ss', `es', `fs', `gs'. + * Section override prefixes 'cs', 'ds', 'ss', 'es', 'fs', 'gs'. These are automatically added by specifying using the SECTION:MEMORY-OPERAND form for memory references. - * Operand/Address size prefixes `data16' and `addr16' change 32-bit - operands/addresses into 16-bit operands/addresses, while `data32' - and `addr32' change 16-bit ones (in a `.code16' section) into + * Operand/Address size prefixes 'data16' and 'addr16' change 32-bit + operands/addresses into 16-bit operands/addresses, while 'data32' + and 'addr32' change 16-bit ones (in a '.code16' section) into 32-bit operands/addresses. These prefixes _must_ appear on the - same line of code as the instruction they modify. For example, in - a 16-bit `.code16' section, you might write: + same line of code as the instruction they modify. For example, in + a 16-bit '.code16' section, you might write: addr32 jmpl *(%ebx) - * The bus lock prefix `lock' inhibits interrupts during execution of + * The bus lock prefix 'lock' inhibits interrupts during execution of the instruction it precedes. (This is only valid with certain instructions; see a 80386 manual for details). - * The wait for coprocessor prefix `wait' waits for the coprocessor to + * The wait for coprocessor prefix 'wait' waits for the coprocessor to complete the current instruction. This should never be needed for the 80386/80387 combination. - * The `rep', `repe', and `repne' prefixes are added to string - instructions to make them repeat `%ecx' times (`%cx' times if the - current address size is 16-bits). - - * The `rex' family of prefixes is used by x86-64 to encode - extensions to i386 instruction set. The `rex' prefix has four - bits -- an operand size overwrite (`64') used to change operand - size from 32-bit to 64-bit and X, Y and Z extensions bits used to - extend the register set. - - You may write the `rex' prefixes directly. The `rex64xyz' - instruction emits `rex' prefix with all the bits set. By omitting - the `64', `x', `y' or `z' you may write other prefixes as well. + * The 'rep', 'repe', and 'repne' prefixes are added to string + instructions to make them repeat '%ecx' times ('%cx' times if the + current address size is 16-bits). + * The 'rex' family of prefixes is used by x86-64 to encode extensions + to i386 instruction set. The 'rex' prefix has four bits -- an + operand size overwrite ('64') used to change operand size from + 32-bit to 64-bit and X, Y and Z extensions bits used to extend the + register set. + + You may write the 'rex' prefixes directly. The 'rex64xyz' + instruction emits 'rex' prefix with all the bits set. By omitting + the '64', 'x', 'y' or 'z' you may write other prefixes as well. Normally, there is no need to write the prefixes explicitly, since gas will automatically generate them based on the instruction operands. @@ -10522,56 +10274,56 @@ is translated into the AT&T syntax SECTION:DISP(BASE, INDEX, SCALE) where BASE and INDEX are the optional 32-bit base and index registers, -DISP is the optional displacement, and SCALE, taking the values 1, 2, -4, and 8, multiplies INDEX to calculate the address of the operand. If -no SCALE is specified, SCALE is taken to be 1. SECTION specifies the +DISP is the optional displacement, and SCALE, taking the values 1, 2, 4, +and 8, multiplies INDEX to calculate the address of the operand. If no +SCALE is specified, SCALE is taken to be 1. SECTION specifies the optional section register for the memory operand, and may override the default section register (see a 80386 manual for section register -defaults). Note that section overrides in AT&T syntax _must_ be -preceded by a `%'. If you specify a section override which coincides -with the default section register, `as' does _not_ output any section +defaults). Note that section overrides in AT&T syntax _must_ be +preceded by a '%'. If you specify a section override which coincides +with the default section register, 'as' does _not_ output any section register override prefixes to assemble the given instruction. Thus, section overrides can be specified to emphasize which section register is used for a given memory operand. Here are some examples of Intel and AT&T style memory references: -AT&T: `-4(%ebp)', Intel: `[ebp - 4]' - BASE is `%ebp'; DISP is `-4'. SECTION is missing, and the default - section is used (`%ss' for addressing with `%ebp' as the base +AT&T: '-4(%ebp)', Intel: '[ebp - 4]' + BASE is '%ebp'; DISP is '-4'. SECTION is missing, and the default + section is used ('%ss' for addressing with '%ebp' as the base register). INDEX, SCALE are both missing. -AT&T: `foo(,%eax,4)', Intel: `[foo + eax*4]' - INDEX is `%eax' (scaled by a SCALE 4); DISP is `foo'. All other - fields are missing. The section register here defaults to `%ds'. +AT&T: 'foo(,%eax,4)', Intel: '[foo + eax*4]' + INDEX is '%eax' (scaled by a SCALE 4); DISP is 'foo'. All other + fields are missing. The section register here defaults to '%ds'. -AT&T: `foo(,1)'; Intel `[foo]' - This uses the value pointed to by `foo' as a memory operand. Note - that BASE and INDEX are both missing, but there is only _one_ `,'. +AT&T: 'foo(,1)'; Intel '[foo]' + This uses the value pointed to by 'foo' as a memory operand. Note + that BASE and INDEX are both missing, but there is only _one_ ','. This is a syntactic exception. -AT&T: `%gs:foo'; Intel `gs:foo' - This selects the contents of the variable `foo' with section - register SECTION being `%gs'. +AT&T: '%gs:foo'; Intel 'gs:foo' + This selects the contents of the variable 'foo' with section + register SECTION being '%gs'. Absolute (as opposed to PC relative) call and jump operands must be -prefixed with `*'. If no `*' is specified, `as' always chooses PC +prefixed with '*'. If no '*' is specified, 'as' always chooses PC relative addressing for jump/call labels. Any instruction that has a memory operand, but no register operand, _must_ specify its size (byte, word, long, or quadruple) with an -instruction mnemonic suffix (`b', `w', `l' or `q', respectively). +instruction mnemonic suffix ('b', 'w', 'l' or 'q', respectively). The x86-64 architecture adds an RIP (instruction pointer relative) -addressing. This addressing mode is specified by using `rip' as a base -register. Only constant offsets are valid. For example: +addressing. This addressing mode is specified by using 'rip' as a base +register. Only constant offsets are valid. For example: -AT&T: `1234(%rip)', Intel: `[rip + 1234]' +AT&T: '1234(%rip)', Intel: '[rip + 1234]' Points to the address 1234 bytes past the end of the current instruction. -AT&T: `symbol(%rip)', Intel: `[rip + symbol]' - Points to the `symbol' in RIP relative way, this is shorter than +AT&T: 'symbol(%rip)', Intel: '[rip + symbol]' + Points to the 'symbol' in RIP relative way, this is shorter than the default absolute addressing. Other addressing modes remain unchanged in x86-64 architecture, @@ -10587,16 +10339,16 @@ Jump instructions are always optimized to use the smallest possible displacements. This is accomplished by using byte (8-bit) displacement jumps whenever the target is sufficiently close. If a byte displacement is insufficient a long displacement is used. We do not support word -(16-bit) displacement jumps in 32-bit mode (i.e. prefixing the jump -instruction with the `data16' instruction prefix), since the 80386 -insists upon masking `%eip' to 16 bits after the word displacement is -added. (See also *note i386-Arch::) +(16-bit) displacement jumps in 32-bit mode (i.e. prefixing the jump +instruction with the 'data16' instruction prefix), since the 80386 +insists upon masking '%eip' to 16 bits after the word displacement is +added. (See also *note i386-Arch::) - Note that the `jcxz', `jecxz', `loop', `loopz', `loope', `loopnz' -and `loopne' instructions only come in byte displacements, so that if -you use these instructions (`gcc' does not use them) you may get an -error message (and incorrect code). The AT&T 80386 assembler tries to -get around this problem by expanding `jcxz foo' to + Note that the 'jcxz', 'jecxz', 'loop', 'loopz', 'loope', 'loopnz' and +'loopne' instructions only come in byte displacements, so that if you +use these instructions ('gcc' does not use them) you may get an error +message (and incorrect code). The AT&T 80386 assembler tries to get +around this problem by expanding 'jcxz foo' to jcxz cx_zero jmp cx_nonzero @@ -10612,31 +10364,31 @@ File: as.info, Node: i386-Float, Next: i386-SIMD, Prev: i386-Jumps, Up: i386 All 80387 floating point types except packed BCD are supported. (BCD support may be added without much difficulty). These data types are 16-, 32-, and 64- bit integers, and single (32-bit), double (64-bit), -and extended (80-bit) precision floating point. Each supported type -has an instruction mnemonic suffix and a constructor associated with -it. Instruction mnemonic suffixes specify the operand's data type. +and extended (80-bit) precision floating point. Each supported type has +an instruction mnemonic suffix and a constructor associated with it. +Instruction mnemonic suffixes specify the operand's data type. Constructors build these data types into memory. - * Floating point constructors are `.float' or `.single', `.double', - and `.tfloat' for 32-, 64-, and 80-bit formats. These correspond - to instruction mnemonic suffixes `s', `l', and `t'. `t' stands for + * Floating point constructors are '.float' or '.single', '.double', + and '.tfloat' for 32-, 64-, and 80-bit formats. These correspond + to instruction mnemonic suffixes 's', 'l', and 't'. 't' stands for 80-bit (ten byte) real. The 80387 only supports this format via - the `fldt' (load 80-bit real to stack top) and `fstpt' (store + the 'fldt' (load 80-bit real to stack top) and 'fstpt' (store 80-bit real and pop stack) instructions. - * Integer constructors are `.word', `.long' or `.int', and `.quad' + * Integer constructors are '.word', '.long' or '.int', and '.quad' for the 16-, 32-, and 64-bit integer formats. The corresponding - instruction mnemonic suffixes are `s' (single), `l' (long), and - `q' (quad). As with the 80-bit real format, the 64-bit `q' format - is only present in the `fildq' (load quad integer to stack top) - and `fistpq' (store quad integer and pop stack) instructions. + instruction mnemonic suffixes are 's' (single), 'l' (long), and 'q' + (quad). As with the 80-bit real format, the 64-bit 'q' format is + only present in the 'fildq' (load quad integer to stack top) and + 'fistpq' (store quad integer and pop stack) instructions. Register to register operations should not use instruction mnemonic -suffixes. `fstl %st, %st(1)' will give a warning, and be assembled as -if you wrote `fst %st, %st(1)', since all register to register -operations use 80-bit floating point operands. (Contrast this with -`fstl %st, mem', which converts `%st' from 80-bit to 64-bit floating -point format, then stores the result in the 4 byte location `mem') +suffixes. 'fstl %st, %st(1)' will give a warning, and be assembled as +if you wrote 'fst %st, %st(1)', since all register to register +operations use 80-bit floating point operands. (Contrast this with +'fstl %st, mem', which converts '%st' from 80-bit to 64-bit floating +point format, then stores the result in the 4 byte location 'mem') File: as.info, Node: i386-SIMD, Next: i386-LWP, Prev: i386-Float, Up: i386-Dependent @@ -10644,18 +10396,18 @@ File: as.info, Node: i386-SIMD, Next: i386-LWP, Prev: i386-Float, Up: i386-D 9.15.11 Intel's MMX and AMD's 3DNow! SIMD Operations ---------------------------------------------------- -`as' supports Intel's MMX instruction set (SIMD instructions for -integer data), available on Intel's Pentium MMX processors and Pentium -II processors, AMD's K6 and K6-2 processors, Cyrix' M2 processor, and -probably others. It also supports AMD's 3DNow! instruction set (SIMD +'as' supports Intel's MMX instruction set (SIMD instructions for integer +data), available on Intel's Pentium MMX processors and Pentium II +processors, AMD's K6 and K6-2 processors, Cyrix' M2 processor, and +probably others. It also supports AMD's 3DNow! instruction set (SIMD instructions for 32-bit floating point data) available on AMD's K6-2 processor and possibly others in the future. - Currently, `as' does not support Intel's floating point SIMD, Katmai + Currently, 'as' does not support Intel's floating point SIMD, Katmai (KNI). The eight 64-bit MMX operands, also used by 3DNow!, are called -`%mm0', `%mm1', ... `%mm7'. They contain eight 8-bit integers, four +'%mm0', '%mm1', ... '%mm7'. They contain eight 8-bit integers, four 16-bit integers, two 32-bit integers, one 64-bit integer, or two 32-bit floating point values. The MMX registers cannot be used at the same time as the floating point stack. @@ -10669,7 +10421,7 @@ File: as.info, Node: i386-LWP, Next: i386-BMI, Prev: i386-SIMD, Up: i386-Dep 9.15.12 AMD's Lightweight Profiling Instructions ------------------------------------------------ -`as' supports AMD's Lightweight Profiling (LWP) instruction set, +'as' supports AMD's Lightweight Profiling (LWP) instruction set, available on AMD's Family 15h (Orochi) processors. LWP enables applications to collect and manage performance data, and @@ -10678,7 +10430,7 @@ requires no context switches. LWP runs in the context of a thread and so several counters can be used independently across multiple threads. LWP can be used in both 64-bit and legacy 32-bit modes. - For detailed information on the LWP instruction set, see the `AMD + For detailed information on the LWP instruction set, see the 'AMD Lightweight Profiling Specification' available at Lightweight Profiling Specification (http://developer.amd.com/cpu/LWP). @@ -10688,7 +10440,7 @@ File: as.info, Node: i386-BMI, Next: i386-TBM, Prev: i386-LWP, Up: i386-Depe 9.15.13 Bit Manipulation Instructions ------------------------------------- -`as' supports the Bit Manipulation (BMI) instruction set. +'as' supports the Bit Manipulation (BMI) instruction set. BMI instructions provide several instructions implementing individual bit manipulation operations such as isolation, masking, setting, or @@ -10700,7 +10452,7 @@ File: as.info, Node: i386-TBM, Next: i386-16bit, Prev: i386-BMI, Up: i386-De 9.15.14 AMD's Trailing Bit Manipulation Instructions ---------------------------------------------------- -`as' supports AMD's Trailing Bit Manipulation (TBM) instruction set, +'as' supports AMD's Trailing Bit Manipulation (TBM) instruction set, available on AMD's BDVER2 processors (Trinity and Viperfish). TBM instructions provide instructions implementing individual bit @@ -10708,49 +10460,49 @@ manipulation operations such as isolating, masking, setting, resetting, complementing, and operations on trailing zeros and ones. -File: as.info, Node: i386-16bit, Next: i386-Arch, Prev: i386-TBM, Up: i386-Dependent +File: as.info, Node: i386-16bit, Next: i386-Bugs, Prev: i386-TBM, Up: i386-Dependent 9.15.15 Writing 16-bit Code --------------------------- -While `as' normally writes only "pure" 32-bit i386 code or 64-bit -x86-64 code depending on the default configuration, it also supports -writing code to run in real mode or in 16-bit protected mode code -segments. To do this, put a `.code16' or `.code16gcc' directive before -the assembly language instructions to be run in 16-bit mode. You can -switch `as' to writing 32-bit code with the `.code32' directive or -64-bit code with the `.code64' directive. - - `.code16gcc' provides experimental support for generating 16-bit -code from gcc, and differs from `.code16' in that `call', `ret', -`enter', `leave', `push', `pop', `pusha', `popa', `pushf', and `popf' +While 'as' normally writes only "pure" 32-bit i386 code or 64-bit x86-64 +code depending on the default configuration, it also supports writing +code to run in real mode or in 16-bit protected mode code segments. To +do this, put a '.code16' or '.code16gcc' directive before the assembly +language instructions to be run in 16-bit mode. You can switch 'as' to +writing 32-bit code with the '.code32' directive or 64-bit code with the +'.code64' directive. + + '.code16gcc' provides experimental support for generating 16-bit code +from gcc, and differs from '.code16' in that 'call', 'ret', 'enter', +'leave', 'push', 'pop', 'pusha', 'popa', 'pushf', and 'popf' instructions default to 32-bit size. This is so that the stack pointer is manipulated in the same way over function calls, allowing access to function parameters at the same stack offsets as in 32-bit mode. -`.code16gcc' also automatically adds address size prefixes where +'.code16gcc' also automatically adds address size prefixes where necessary to use the 32-bit addressing modes that gcc generates. - The code which `as' generates in 16-bit mode will not necessarily -run on a 16-bit pre-80386 processor. To write code that runs on such a + The code which 'as' generates in 16-bit mode will not necessarily run +on a 16-bit pre-80386 processor. To write code that runs on such a processor, you must refrain from using _any_ 32-bit constructs which -require `as' to output address or operand size prefixes. +require 'as' to output address or operand size prefixes. Note that writing 16-bit code instructions by explicitly specifying a prefix or an instruction mnemonic suffix within a 32-bit code section generates different machine instructions than those generated for a 16-bit code segment. In a 32-bit code section, the following code -generates the machine opcode bytes `66 6a 04', which pushes the value -`4' onto the stack, decrementing `%esp' by 2. +generates the machine opcode bytes '66 6a 04', which pushes the value +'4' onto the stack, decrementing '%esp' by 2. pushw $4 The same code in a 16-bit code section would generate the machine -opcode bytes `6a 04' (i.e., without the operand size prefix), which is +opcode bytes '6a 04' (i.e., without the operand size prefix), which is correct since the processor default operand size is assumed to be 16 bits in a 16-bit code section. -File: as.info, Node: i386-Bugs, Next: i386-Notes, Prev: i386-Arch, Up: i386-Dependent +File: as.info, Node: i386-Bugs, Next: i386-Arch, Prev: i386-16bit, Up: i386-Dependent 9.15.16 AT&T Syntax bugs ------------------------ @@ -10764,89 +10516,96 @@ with it. For example fsub %st,%st(3) - results in `%st(3)' being updated to `%st - %st(3)' rather than the -expected `%st(3) - %st'. This happens with all the non-commutative +results in '%st(3)' being updated to '%st - %st(3)' rather than the +expected '%st(3) - %st'. This happens with all the non-commutative arithmetic floating point operations with two register operands where -the source register is `%st' and the destination register is `%st(i)'. +the source register is '%st' and the destination register is '%st(i)'. -File: as.info, Node: i386-Arch, Next: i386-Bugs, Prev: i386-16bit, Up: i386-Dependent +File: as.info, Node: i386-Arch, Next: i386-Notes, Prev: i386-Bugs, Up: i386-Dependent 9.15.17 Specifying CPU Architecture ----------------------------------- -`as' may be told to assemble for a particular CPU (sub-)architecture -with the `.arch CPU_TYPE' directive. This directive enables a warning +'as' may be told to assemble for a particular CPU (sub-)architecture +with the '.arch CPU_TYPE' directive. This directive enables a warning when gas detects an instruction that is not supported on the CPU specified. The choices for CPU_TYPE are: -`i8086' `i186' `i286' `i386' -`i486' `i586' `i686' `pentium' -`pentiumpro' `pentiumii' `pentiumiii' `pentium4' -`prescott' `nocona' `core' `core2' -`corei7' `l1om' `k1om' -`k6' `k6_2' `athlon' `k8' -`amdfam10' `bdver1' `bdver2' `bdver3' -`btver1' `btver2' -`generic32' `generic64' -`.mmx' `.sse' `.sse2' `.sse3' -`.ssse3' `.sse4.1' `.sse4.2' `.sse4' -`.avx' `.vmx' `.smx' `.ept' -`.clflush' `.movbe' `.xsave' `.xsaveopt' -`.aes' `.pclmul' `.fma' `.fsgsbase' -`.rdrnd' `.f16c' `.avx2' `.bmi2' -`.lzcnt' `.invpcid' `.vmfunc' `.hle' -`.rtm' `.adx' `.rdseed' `.prfchw' -`.smap' -`.3dnow' `.3dnowa' `.sse4a' `.sse5' -`.syscall' `.rdtscp' `.svme' `.abm' -`.lwp' `.fma4' `.xop' `.cx16' -`.padlock' - - Apart from the warning, there are only two other effects on `as' -operation; Firstly, if you specify a CPU other than `i486', then shift -by one instructions such as `sarl $1, %eax' will automatically use a -two byte opcode sequence. The larger three byte opcode sequence is -used on the 486 (and when no architecture is specified) because it -executes faster on the 486. Note that you can explicitly request the -two byte opcode by writing `sarl %eax'. Secondly, if you specify -`i8086', `i186', or `i286', _and_ `.code16' or `.code16gcc' then byte -offset conditional jumps will be promoted when necessary to a two -instruction sequence consisting of a conditional jump of the opposite -sense around an unconditional jump to the target. - - Following the CPU architecture (but not a sub-architecture, which -are those starting with a dot), you may specify `jumps' or `nojumps' to -control automatic promotion of conditional jumps. `jumps' is the -default, and enables jump promotion; All external jumps will be of the +'i8086' 'i186' 'i286' 'i386' +'i486' 'i586' 'i686' 'pentium' +'pentiumpro' 'pentiumii' 'pentiumiii' 'pentium4' +'prescott' 'nocona' 'core' 'core2' +'corei7' 'l1om' 'k1om' +'k6' 'k6_2' 'athlon' 'k8' +'amdfam10' 'bdver1' 'bdver2' 'bdver3' +'btver1' 'btver2' +'generic32' 'generic64' +'.mmx' '.sse' '.sse2' '.sse3' +'.ssse3' '.sse4.1' '.sse4.2' '.sse4' +'.avx' '.vmx' '.smx' '.ept' +'.clflush' '.movbe' '.xsave' '.xsaveopt' +'.aes' '.pclmul' '.fma' '.fsgsbase' +'.rdrnd' '.f16c' '.avx2' '.bmi2' +'.lzcnt' '.invpcid' '.vmfunc' '.hle' +'.rtm' '.adx' '.rdseed' '.prfchw' +'.smap' '.mpx' +'.smap' '.sha' +'.smap' '.clflushopt' '.xsavec' '.xsaves' +'.smap' '.prefetchwt1' +'.3dnow' '.3dnowa' '.sse4a' '.sse5' +'.syscall' '.rdtscp' '.svme' '.abm' +'.lwp' '.fma4' '.xop' '.cx16' +'.padlock' +'.smap' '.avx512f' '.avx512cd' '.avx512er' +'.avx512pf' '.3dnow' '.3dnowa' '.sse4a' +'.sse5' '.syscall' '.rdtscp' '.svme' +'.abm' '.lwp' '.fma4' '.xop' +'.cx16' '.padlock' + + Apart from the warning, there are only two other effects on 'as' +operation; Firstly, if you specify a CPU other than 'i486', then shift +by one instructions such as 'sarl $1, %eax' will automatically use a two +byte opcode sequence. The larger three byte opcode sequence is used on +the 486 (and when no architecture is specified) because it executes +faster on the 486. Note that you can explicitly request the two byte +opcode by writing 'sarl %eax'. Secondly, if you specify 'i8086', +'i186', or 'i286', _and_ '.code16' or '.code16gcc' then byte offset +conditional jumps will be promoted when necessary to a two instruction +sequence consisting of a conditional jump of the opposite sense around +an unconditional jump to the target. + + Following the CPU architecture (but not a sub-architecture, which are +those starting with a dot), you may specify 'jumps' or 'nojumps' to +control automatic promotion of conditional jumps. 'jumps' is the +default, and enables jump promotion; All external jumps will be of the long variety, and file-local jumps will be promoted as necessary. -(*note i386-Jumps::) `nojumps' leaves external conditional jumps as -byte offset jumps, and warns about file-local conditional jumps that -`as' promotes. Unconditional jumps are treated as for `jumps'. +(*note i386-Jumps::) 'nojumps' leaves external conditional jumps as byte +offset jumps, and warns about file-local conditional jumps that 'as' +promotes. Unconditional jumps are treated as for 'jumps'. For example .arch i8086,nojumps -File: as.info, Node: i386-Notes, Prev: i386-Bugs, Up: i386-Dependent +File: as.info, Node: i386-Notes, Prev: i386-Arch, Up: i386-Dependent 9.15.18 Notes ------------- -There is some trickery concerning the `mul' and `imul' instructions -that deserves mention. The 16-, 32-, 64- and 128-bit expanding -multiplies (base opcode `0xf6'; extension 4 for `mul' and 5 for `imul') -can be output only in the one operand form. Thus, `imul %ebx, %eax' -does _not_ select the expanding multiply; the expanding multiply would -clobber the `%edx' register, and this would confuse `gcc' output. Use -`imul %ebx' to get the 64-bit product in `%edx:%eax'. +There is some trickery concerning the 'mul' and 'imul' instructions that +deserves mention. The 16-, 32-, 64- and 128-bit expanding multiplies +(base opcode '0xf6'; extension 4 for 'mul' and 5 for 'imul') can be +output only in the one operand form. Thus, 'imul %ebx, %eax' does _not_ +select the expanding multiply; the expanding multiply would clobber the +'%edx' register, and this would confuse 'gcc' output. Use 'imul %ebx' +to get the 64-bit product in '%edx:%eax'. - We have added a two operand form of `imul' when the first operand is -an immediate mode expression and the second operand is a register. -This is just a shorthand, so that, multiplying `%eax' by 69, for -example, can be done with `imul $69, %eax' rather than `imul $69, %eax, -%eax'. + We have added a two operand form of 'imul' when the first operand is +an immediate mode expression and the second operand is a register. This +is just a shorthand, so that, multiplying '%eax' by 69, for example, can +be done with 'imul $69, %eax' rather than 'imul $69, %eax, %eax'. File: as.info, Node: i860-Dependent, Next: i960-Dependent, Prev: i386-Dependent, Up: Machine Dependencies @@ -10869,19 +10628,19 @@ File: as.info, Node: Notes-i860, Next: Options-i860, Up: i860-Dependent ----------------- This is a fairly complete i860 assembler which is compatible with the -UNIX System V/860 Release 4 assembler. However, it does not currently -support SVR4 PIC (i.e., `@GOT, @GOTOFF, @PLT'). +UNIX System V/860 Release 4 assembler. However, it does not currently +support SVR4 PIC (i.e., '@GOT, @GOTOFF, @PLT'). Like the SVR4/860 assembler, the output object format is ELF32. -Currently, this is the only supported object format. If there is +Currently, this is the only supported object format. If there is sufficient interest, other formats such as COFF may be implemented. Both the Intel and AT&T/SVR4 syntaxes are supported, with the latter being the default. One difference is that AT&T syntax requires the '%' prefix on register names while Intel syntax does not. Another difference is in the specification of relocatable expressions. The -Intel syntax is `ha%expression' whereas the SVR4 syntax is -`[expression]@ha' (and similarly for the "l" and "h" selectors). +Intel syntax is 'ha%expression' whereas the SVR4 syntax is +'[expression]@ha' (and similarly for the "l" and "h" selectors). File: as.info, Node: Options-i860, Next: Directives-i860, Prev: Notes-i860, Up: i860-Dependent @@ -10892,41 +10651,35 @@ File: as.info, Node: Options-i860, Next: Directives-i860, Prev: Notes-i860, 9.16.2.1 SVR4 compatibility options ................................... -`-V' +'-V' Print assembler version. - -`-Qy' +'-Qy' Ignored. - -`-Qn' +'-Qn' Ignored. 9.16.2.2 Other options ...................... -`-EL' +'-EL' Select little endian output (this is the default). - -`-EB' - Select big endian output. Note that the i860 always reads +'-EB' + Select big endian output. Note that the i860 always reads instructions as little endian data, so this option only effects data and not instructions. - -`-mwarn-expand' +'-mwarn-expand' Emit a warning message if any pseudo-instruction expansions - occurred. For example, a `or' instruction with an immediate - larger than 16-bits will be expanded into two instructions. This - is a very undesirable feature to rely on, so this flag can help - detect any code where it happens. One use of it, for instance, has - been to find and eliminate any place where `gcc' may emit these + occurred. For example, a 'or' instruction with an immediate larger + than 16-bits will be expanded into two instructions. This is a + very undesirable feature to rely on, so this flag can help detect + any code where it happens. One use of it, for instance, has been + to find and eliminate any place where 'gcc' may emit these pseudo-instructions. - -`-mxp' +'-mxp' Enable support for the i860XP instructions and control registers. By default, this option is disabled so that only the base instruction set (i.e., i860XR) is supported. - -`-mintel-syntax' +'-mintel-syntax' The i860 assembler defaults to AT&T/SVR4 syntax. This option enables the Intel syntax. @@ -10936,27 +10689,27 @@ File: as.info, Node: Directives-i860, Next: Opcodes for i860, Prev: Options-i 9.16.3 i860 Machine Directives ------------------------------ -`.dual' - Enter dual instruction mode. While this directive is supported, the - preferred way to use dual instruction mode is to explicitly code - the dual bit with the `d.' prefix. +'.dual' + Enter dual instruction mode. While this directive is supported, + the preferred way to use dual instruction mode is to explicitly + code the dual bit with the 'd.' prefix. -`.enddual' - Exit dual instruction mode. While this directive is supported, the +'.enddual' + Exit dual instruction mode. While this directive is supported, the preferred way to use dual instruction mode is to explicitly code - the dual bit with the `d.' prefix. + the dual bit with the 'd.' prefix. -`.atmp' +'.atmp' Change the temporary register used when expanding pseudo - operations. The default register is `r31'. + operations. The default register is 'r31'. - The `.dual', `.enddual', and `.atmp' directives are available only -in the Intel syntax mode. + The '.dual', '.enddual', and '.atmp' directives are available only in +the Intel syntax mode. - Both syntaxes allow for the standard `.align' directive. However, + Both syntaxes allow for the standard '.align' directive. However, the Intel syntax additionally allows keywords for the alignment -parameter: "`.align type'", where `type' is one of `.short', `.long', -`.quad', `.single', `.double' representing alignments of 2, 4, 16, 4, +parameter: "'.align type'", where 'type' is one of '.short', '.long', +'.quad', '.single', '.double' representing alignments of 2, 4, 16, 4, and 8, respectively. @@ -10966,53 +10719,50 @@ File: as.info, Node: Opcodes for i860, Next: Syntax of i860, Prev: Directives ------------------- All of the Intel i860XR and i860XP machine instructions are supported. -Please see either _i860 Microprocessor Programmer's Reference Manual_ -or _i860 Microprocessor Architecture_ for more information. +Please see either _i860 Microprocessor Programmer's Reference Manual_ or +_i860 Microprocessor Architecture_ for more information. 9.16.4.1 Other instruction support (pseudo-instructions) ........................................................ For compatibility with some other i860 assemblers, a number of -pseudo-instructions are supported. While these are supported, they are +pseudo-instructions are supported. While these are supported, they are a very undesirable feature that should be avoided - in particular, when -they result in an expansion to multiple actual i860 instructions. Below +they result in an expansion to multiple actual i860 instructions. Below are the pseudo-instructions that result in expansions. * Load large immediate into general register: - The pseudo-instruction `mov imm,%rn' (where the immediate does not + The pseudo-instruction 'mov imm,%rn' (where the immediate does not fit within a signed 16-bit field) will be expanded into: orh large_imm@h,%r0,%rn or large_imm@l,%rn,%rn - * Load/store with relocatable address expression: - For example, the pseudo-instruction `ld.b addr_exp(%rx),%rn' will + For example, the pseudo-instruction 'ld.b addr_exp(%rx),%rn' will be expanded into: orh addr_exp@ha,%rx,%r31 ld.l addr_exp@l(%r31),%rn - The analogous expansions apply to `ld.x, st.x, fld.x, pfld.x, - fst.x', and `pst.x' as well. - + The analogous expansions apply to 'ld.x, st.x, fld.x, pfld.x, + fst.x', and 'pst.x' as well. * Signed large immediate with add/subtract: - If any of the arithmetic operations `adds, addu, subs, subu' are - used with an immediate larger than 16-bits (signed), then they - will be expanded. For instance, the pseudo-instruction `adds + If any of the arithmetic operations 'adds, addu, subs, subu' are + used with an immediate larger than 16-bits (signed), then they will + be expanded. For instance, the pseudo-instruction 'adds large_imm,%rx,%rn' expands to: orh large_imm@h,%r0,%r31 or large_imm@l,%r31,%r31 adds %r31,%rx,%rn - * Unsigned large immediate with logical operations: - Logical operations (`or, andnot, or, xor') also result in - expansions. The pseudo-instruction `or large_imm,%rx,%rn' results + Logical operations ('or, andnot, or, xor') also result in + expansions. The pseudo-instruction 'or large_imm,%rx,%rn' results in: orh large_imm@h,%rx,%r31 or large_imm@l,%r31,%rn - Similarly for the others, except for `and' which expands to: + Similarly for the others, except for 'and' which expands to: andnot (-1 - large_imm)@h,%rx,%r31 andnot (-1 - large_imm)@l,%r31,%rn @@ -11032,15 +10782,15 @@ File: as.info, Node: i860-Chars, Up: Syntax of i860 9.16.5.1 Special Characters ........................... -The presence of a `#' appearing anywhere on a line indicates the start +The presence of a '#' appearing anywhere on a line indicates the start of a comment that extends to the end of that line. - If a `#' appears as the first character of a line then the whole -line is treated as a comment, but in this case the line can also be a -logical line number directive (*note Comments::) or a preprocessor -control command (*note Preprocessing::). + If a '#' appears as the first character of a line then the whole line +is treated as a comment, but in this case the line can also be a logical +line number directive (*note Comments::) or a preprocessor control +command (*note Preprocessing::). - The `;' character can be used to separate statements on the same + The ';' character can be used to separate statements on the same line. @@ -11063,29 +10813,29 @@ File: as.info, Node: Options-i960, Next: Floating Point-i960, Up: i960-Depend 9.17.1 i960 Command-line Options -------------------------------- -`-ACA | -ACA_A | -ACB | -ACC | -AKA | -AKB | -AKC | -AMC' +'-ACA | -ACA_A | -ACB | -ACC | -AKA | -AKB | -AKC | -AMC' Select the 80960 architecture. Instructions or features not supported by the selected architecture cause fatal errors. - `-ACA' is equivalent to `-ACA_A'; `-AKC' is equivalent to `-AMC'. + '-ACA' is equivalent to '-ACA_A'; '-AKC' is equivalent to '-AMC'. Synonyms are provided for compatibility with other tools. - If you do not specify any of these options, `as' generates code - for any instruction or feature that is supported by _some_ version - of the 960 (even if this means mixing architectures!). In - principle, `as' attempts to deduce the minimal sufficient - processor type if none is specified; depending on the object code - format, the processor type may be recorded in the object file. If - it is critical that the `as' output match a specific architecture, + If you do not specify any of these options, 'as' generates code for + any instruction or feature that is supported by _some_ version of + the 960 (even if this means mixing architectures!). In principle, + 'as' attempts to deduce the minimal sufficient processor type if + none is specified; depending on the object code format, the + processor type may be recorded in the object file. If it is + critical that the 'as' output match a specific architecture, specify that architecture explicitly. -`-b' +'-b' Add code to collect information about conditional branches taken, for later optimization using branch prediction bits. (The conditional branch instructions have branch prediction bits in the CA, CB, and CC architectures.) If BR represents a conditional branch instruction, the following represents the code generated by - the assembler when `-b' is specified: + the assembler when '-b' is specified: call INCREMENT ROUTINE .word 0 # pre-counter @@ -11097,9 +10847,9 @@ File: as.info, Node: Options-i960, Next: Floating Point-i960, Up: i960-Depend branch was _not_ taken; the difference between the two counters is the number of times the branch _was_ taken. - A table of every such `Label' is also generated, so that the - external postprocessor `gbr960' (supplied by Intel) can locate all - the counters. This table is always labeled `__BRANCH_TABLE__'; + A table of every such 'Label' is also generated, so that the + external postprocessor 'gbr960' (supplied by Intel) can locate all + the counters. This table is always labeled '__BRANCH_TABLE__'; this is a local symbol to permit collecting statistics for many separate object files. The table is word aligned, and begins with a two-word header. The first word, initialized to 0, is used in @@ -11117,24 +10867,24 @@ File: as.info, Node: Options-i960, Next: Floating Point-i960, Up: i960-Depend __BRANCH_TABLE__ layout The first word of the header is used to locate multiple branch - tables, since each object file may contain one. Normally the links + tables, since each object file may contain one. Normally the links are maintained with a call to an initialization routine, placed at the beginning of each function in the file. The GNU C compiler - generates these calls automatically when you give it a `-b' option. - For further details, see the documentation of `gbr960'. + generates these calls automatically when you give it a '-b' option. + For further details, see the documentation of 'gbr960'. -`-no-relax' +'-no-relax' Normally, Compare-and-Branch instructions with targets that require displacements greater than 13 bits (or that have external targets) - are replaced with the corresponding compare (or `chkbit') and - branch instructions. You can use the `-no-relax' option to - specify that `as' should generate errors instead, if the target + are replaced with the corresponding compare (or 'chkbit') and + branch instructions. You can use the '-no-relax' option to specify + that 'as' should generate errors instead, if the target displacement is larger than 13 bits. This option does not affect the Compare-and-Jump instructions; the code emitted for them is _always_ adjusted when necessary (depending on displacement size), regardless of whether you use - `-no-relax'. + '-no-relax'. File: as.info, Node: Floating Point-i960, Next: Directives-i960, Prev: Options-i960, Up: i960-Dependent @@ -11142,8 +10892,8 @@ File: as.info, Node: Floating Point-i960, Next: Directives-i960, Prev: Option 9.17.2 Floating Point --------------------- -`as' generates IEEE floating-point numbers for the directives `.float', -`.double', `.extended', and `.single'. +'as' generates IEEE floating-point numbers for the directives '.float', +'.double', '.extended', and '.single'. File: as.info, Node: Directives-i960, Next: Opcodes for i960, Prev: Floating Point-i960, Up: i960-Dependent @@ -11151,42 +10901,42 @@ File: as.info, Node: Directives-i960, Next: Opcodes for i960, Prev: Floating 9.17.3 i960 Machine Directives ------------------------------ -`.bss SYMBOL, LENGTH, ALIGN' - Reserve LENGTH bytes in the bss section for a local SYMBOL, - aligned to the power of two specified by ALIGN. LENGTH and ALIGN - must be positive absolute expressions. This directive differs - from `.lcomm' only in that it permits you to specify an alignment. - *Note `.lcomm': Lcomm. +'.bss SYMBOL, LENGTH, ALIGN' + Reserve LENGTH bytes in the bss section for a local SYMBOL, aligned + to the power of two specified by ALIGN. LENGTH and ALIGN must be + positive absolute expressions. This directive differs from + '.lcomm' only in that it permits you to specify an alignment. + *Note '.lcomm': Lcomm. -`.extended FLONUMS' - `.extended' expects zero or more flonums, separated by commas; for - each flonum, `.extended' emits an IEEE extended-format (80-bit) +'.extended FLONUMS' + '.extended' expects zero or more flonums, separated by commas; for + each flonum, '.extended' emits an IEEE extended-format (80-bit) floating-point number. -`.leafproc CALL-LAB, BAL-LAB' - You can use the `.leafproc' directive in conjunction with the - optimized `callj' instruction to enable faster calls of leaf +'.leafproc CALL-LAB, BAL-LAB' + You can use the '.leafproc' directive in conjunction with the + optimized 'callj' instruction to enable faster calls of leaf procedures. If a procedure is known to call no other procedures, - you may define an entry point that skips procedure prolog code - (and that does not depend on system-supplied saved context), and - declare it as the BAL-LAB using `.leafproc'. If the procedure - also has an entry point that goes through the normal prolog, you - can specify that entry point as CALL-LAB. + you may define an entry point that skips procedure prolog code (and + that does not depend on system-supplied saved context), and declare + it as the BAL-LAB using '.leafproc'. If the procedure also has an + entry point that goes through the normal prolog, you can specify + that entry point as CALL-LAB. - A `.leafproc' declaration is meant for use in conjunction with the - optimized call instruction `callj'; the directive records the data - needed later to choose between converting the `callj' into a `bal' - or a `call'. + A '.leafproc' declaration is meant for use in conjunction with the + optimized call instruction 'callj'; the directive records the data + needed later to choose between converting the 'callj' into a 'bal' + or a 'call'. CALL-LAB is optional; if only one argument is present, or if the two arguments are identical, the single argument is assumed to be - the `bal' entry point. + the 'bal' entry point. -`.sysproc NAME, INDEX' - The `.sysproc' directive defines a name for a system procedure. - After you define it using `.sysproc', you can use NAME to refer to +'.sysproc NAME, INDEX' + The '.sysproc' directive defines a name for a system procedure. + After you define it using '.sysproc', you can use NAME to refer to the system procedure identified by INDEX when calling procedures - with the optimized call instruction `callj'. + with the optimized call instruction 'callj'. Both arguments are required; INDEX must be between 0 and 31 (inclusive). @@ -11202,26 +10952,26 @@ Command-line Options: Options-i960. for a discussion of selecting the instruction subset for a particular 960 architecture. Some opcodes are processed beyond simply emitting a single -corresponding instruction: `callj', and Compare-and-Branch or +corresponding instruction: 'callj', and Compare-and-Branch or Compare-and-Jump instructions with target displacements larger than 13 bits. * Menu: -* callj-i960:: `callj' +* callj-i960:: 'callj' * Compare-and-branch-i960:: Compare-and-Branch File: as.info, Node: callj-i960, Next: Compare-and-branch-i960, Up: Opcodes for i960 -9.17.4.1 `callj' +9.17.4.1 'callj' ................ -You can write `callj' to have the assembler or the linker determine the -most appropriate form of subroutine call: `call', `bal', or `calls'. -If the assembly source contains enough information--a `.leafproc' or -`.sysproc' directive defining the operand--then `as' translates the -`callj'; if not, it simply emits the `callj', leaving it for the linker +You can write 'callj' to have the assembler or the linker determine the +most appropriate form of subroutine call: 'call', 'bal', or 'calls'. If +the assembly source contains enough information--a '.leafproc' or +'.sysproc' directive defining the operand--then 'as' translates the +'callj'; if not, it simply emits the 'callj', leaving it for the linker to resolve. @@ -11237,12 +10987,12 @@ enough away that its address won't fit in 13 bits, the assembler can either issue an error, or convert your Compare-and-Branch instruction into separate instructions to do the compare and the branch. - Whether `as' gives an error or expands the instruction depends on -two choices you can make: whether you use the `-no-relax' option, and + Whether 'as' gives an error or expands the instruction depends on two +choices you can make: whether you use the '-no-relax' option, and whether you use a "Compare and Branch" instruction or a "Compare and Jump" instruction. The "Jump" instructions are _always_ expanded if necessary; the "Branch" instructions are expanded when necessary -_unless_ you specify `-no-relax'--in which case `as' gives an error +_unless_ you specify '-no-relax'--in which case 'as' gives an error instead. These are the Compare-and-Branch instructions, their "Jump" variants, @@ -11284,15 +11034,15 @@ File: as.info, Node: i960-Chars, Up: Syntax of i960 9.17.5.1 Special Characters ........................... -The presence of a `#' on a line indicates the start of a comment that +The presence of a '#' on a line indicates the start of a comment that extends to the end of the current line. - If a `#' appears as the first character of a line, the whole line is + If a '#' appears as the first character of a line, the whole line is treated as a comment, but in this case the line can also be a logical line number directive (*note Comments::) or a preprocessor control command (*note Preprocessing::). - The `;' character can be used to separate statements on the same + The ';' character can be used to separate statements on the same line. @@ -11313,7 +11063,7 @@ File: as.info, Node: IA-64 Options, Next: IA-64 Syntax, Up: IA-64-Dependent 9.18.1 Options -------------- -`-mconstant-gp' +'-mconstant-gp' This option instructs the assembler to mark the resulting object file as using the "constant GP" model. With this model, it is assumed that the entire program uses a single global pointer (GP) @@ -11321,79 +11071,78 @@ File: as.info, Node: IA-64 Options, Next: IA-64 Syntax, Up: IA-64-Dependent machine code emitted by the assembler. All it does is turn on the EF_IA_64_CONS_GP flag in the ELF file header. -`-mauto-pic' +'-mauto-pic' This option instructs the assembler to mark the resulting object file as using the "constant GP without function descriptor" data model. This model is like the "constant GP" model, except that it additionally does away with function descriptors. What this means - is that the address of a function refers directly to the - function's code entry-point. Normally, such an address would - refer to a function descriptor, which contains both the code - entry-point and the GP-value needed by the function. Note that - this option does not in any fashion affect the machine code - emitted by the assembler. All it does is turn on the - EF_IA_64_NOFUNCDESC_CONS_GP flag in the ELF file header. - -`-milp32' -`-milp64' -`-mlp64' -`-mp64' + is that the address of a function refers directly to the function's + code entry-point. Normally, such an address would refer to a + function descriptor, which contains both the code entry-point and + the GP-value needed by the function. Note that this option does + not in any fashion affect the machine code emitted by the + assembler. All it does is turn on the EF_IA_64_NOFUNCDESC_CONS_GP + flag in the ELF file header. + +'-milp32' +'-milp64' +'-mlp64' +'-mp64' These options select the data model. The assembler defaults to - `-mlp64' (LP64 data model). - -`-mle' -`-mbe' - These options select the byte order. The `-mle' option selects - little-endian byte order (default) and `-mbe' selects big-endian - byte order. Note that IA-64 machine code always uses - little-endian byte order. - -`-mtune=itanium1' -`-mtune=itanium2' - Tune for a particular IA-64 CPU, ITANIUM1 or ITANIUM2. The default + '-mlp64' (LP64 data model). + +'-mle' +'-mbe' + These options select the byte order. The '-mle' option selects + little-endian byte order (default) and '-mbe' selects big-endian + byte order. Note that IA-64 machine code always uses little-endian + byte order. + +'-mtune=itanium1' +'-mtune=itanium2' + Tune for a particular IA-64 CPU, ITANIUM1 or ITANIUM2. The default is ITANIUM2. -`-munwind-check=warning' -`-munwind-check=error' +'-munwind-check=warning' +'-munwind-check=error' These options control what the assembler will do when performing - consistency checks on unwind directives. `-munwind-check=warning' + consistency checks on unwind directives. '-munwind-check=warning' will make the assembler issue a warning when an unwind directive - check fails. This is the default. `-munwind-check=error' will + check fails. This is the default. '-munwind-check=error' will make the assembler issue an error when an unwind directive check fails. -`-mhint.b=ok' -`-mhint.b=warning' -`-mhint.b=error' - These options control what the assembler will do when the `hint.b' - instruction is used. `-mhint.b=ok' will make the assembler accept - `hint.b'. `-mint.b=warning' will make the assembler issue a - warning when `hint.b' is used. `-mhint.b=error' will make the - assembler treat `hint.b' as an error, which is the default. - -`-x' -`-xexplicit' +'-mhint.b=ok' +'-mhint.b=warning' +'-mhint.b=error' + These options control what the assembler will do when the 'hint.b' + instruction is used. '-mhint.b=ok' will make the assembler accept + 'hint.b'. '-mint.b=warning' will make the assembler issue a + warning when 'hint.b' is used. '-mhint.b=error' will make the + assembler treat 'hint.b' as an error, which is the default. + +'-x' +'-xexplicit' These options turn on dependency violation checking. -`-xauto' +'-xauto' This option instructs the assembler to automatically insert stop bits where necessary to remove dependency violations. This is the default mode. -`-xnone' +'-xnone' This option turns off dependency violation checking. -`-xdebug' +'-xdebug' This turns on debug output intended to help tracking down bugs in the dependency violation checker. -`-xdebugn' +'-xdebugn' This is a shortcut for -xnone -xdebug. -`-xdebugx' +'-xdebugx' This is a shortcut for -xexplicit -xdebug. - File: as.info, Node: IA-64 Syntax, Next: IA-64 Opcodes, Prev: IA-64 Options, Up: IA-64-Dependent @@ -11416,9 +11165,9 @@ File: as.info, Node: IA-64-Chars, Next: IA-64-Regs, Up: IA-64 Syntax 9.18.2.1 Special Characters ........................... -`//' is the line comment token. +'//' is the line comment token. - `;' can be used instead of a newline to separate statements. + ';' can be used instead of a newline to separate statements. File: as.info, Node: IA-64-Regs, Next: IA-64-Bits, Prev: IA-64-Chars, Up: IA-64 Syntax @@ -11426,19 +11175,19 @@ File: as.info, Node: IA-64-Regs, Next: IA-64-Bits, Prev: IA-64-Chars, Up: IA 9.18.2.2 Register Names ....................... -The 128 integer registers are referred to as `rN'. The 128 -floating-point registers are referred to as `fN'. The 128 application -registers are referred to as `arN'. The 128 control registers are -referred to as `crN'. The 64 one-bit predicate registers are referred -to as `pN'. The 8 branch registers are referred to as `bN'. In -addition, the assembler defines a number of aliases: `gp' (`r1'), `sp' -(`r12'), `rp' (`b0'), `ret0' (`r8'), `ret1' (`r9'), `ret2' (`r10'), -`ret3' (`r9'), `fargN' (`f8+N'), and `fretN' (`f8+N'). +The 128 integer registers are referred to as 'rN'. The 128 +floating-point registers are referred to as 'fN'. The 128 application +registers are referred to as 'arN'. The 128 control registers are +referred to as 'crN'. The 64 one-bit predicate registers are referred +to as 'pN'. The 8 branch registers are referred to as 'bN'. In +addition, the assembler defines a number of aliases: 'gp' ('r1'), 'sp' +('r12'), 'rp' ('b0'), 'ret0' ('r8'), 'ret1' ('r9'), 'ret2' ('r10'), +'ret3' ('r9'), 'fargN' ('f8+N'), and 'fretN' ('f8+N'). For convenience, the assembler also defines aliases for all named -application and control registers. For example, `ar.bsp' refers to the -register backing store pointer (`ar17'). Similarly, `cr.eoi' refers to -the end-of-interrupt register (`cr67'). +application and control registers. For example, 'ar.bsp' refers to the +register backing store pointer ('ar17'). Similarly, 'cr.eoi' refers to +the end-of-interrupt register ('cr67'). File: as.info, Node: IA-64-Bits, Next: IA-64-Relocs, Prev: IA-64-Regs, Up: IA-64 Syntax @@ -11447,9 +11196,9 @@ File: as.info, Node: IA-64-Bits, Next: IA-64-Relocs, Prev: IA-64-Regs, Up: I ........................................................ The assembler defines bit masks for each of the bits in the IA-64 -processor status register. For example, `psr.ic' corresponds to a -value of 0x2000. These masks are primarily intended for use with the -`ssm'/`sum' and `rsm'/`rum' instructions, but they can be used anywhere +processor status register. For example, 'psr.ic' corresponds to a value +of 0x2000. These masks are primarily intended for use with the +'ssm'/'sum' and 'rsm'/'rum' instructions, but they can be used anywhere else where an integer constant is expected. @@ -11458,12 +11207,12 @@ File: as.info, Node: IA-64-Relocs, Prev: IA-64-Bits, Up: IA-64 Syntax 9.18.2.4 Relocations .................... -In addition to the standard IA-64 relocations, the following -relocations are implemented by `as': +In addition to the standard IA-64 relocations, the following relocations +are implemented by 'as': -`@slotcount(V)' +'@slotcount(V)' Convert the address offset V into a slot count. This pseudo - function is available only on VMS. The expression V must be known + function is available only on VMS. The expression V must be known at assembly time: it can't reference undefined symbols or symbols in different sections. @@ -11494,18 +11243,17 @@ File: as.info, Node: IP2K-Opts, Next: IP2K-Syntax, Up: IP2K-Dependent 9.19.1 IP2K Options ------------------- -The Ubicom IP2K version of `as' has a few machine dependent options: +The Ubicom IP2K version of 'as' has a few machine dependent options: -`-mip2022ext' - `as' can assemble the extended IP2022 instructions, but it will +'-mip2022ext' + 'as' can assemble the extended IP2022 instructions, but it will only do so if this is specifically allowed via this command line option. -`-mip2022' +'-mip2022' This option restores the assembler's default behaviour of not permitting the extended IP2022 instructions to be assembled. - File: as.info, Node: IP2K-Syntax, Prev: IP2K-Opts, Up: IP2K-Dependent @@ -11522,10 +11270,10 @@ File: as.info, Node: IP2K-Chars, Up: IP2K-Syntax 9.19.2.1 Special Characters ........................... -The presence of a `;' on a line indicates the start of a comment that +The presence of a ';' on a line indicates the start of a comment that extends to the end of the current line. - If a `#' appears as the first character of a line, the whole line is + If a '#' appears as the first character of a line, the whole line is treated as a comment, but in this case the line can also be a logical line number directive (*note Comments::) or a preprocessor control command (*note Preprocessing::). @@ -11551,34 +11299,33 @@ File: as.info, Node: LM32 Options, Next: LM32 Syntax, Up: LM32-Dependent 9.20.1 Options -------------- -`-mmultiply-enabled' +'-mmultiply-enabled' Enable multiply instructions. -`-mdivide-enabled' +'-mdivide-enabled' Enable divide instructions. -`-mbarrel-shift-enabled' +'-mbarrel-shift-enabled' Enable barrel-shift instructions. -`-msign-extend-enabled' +'-msign-extend-enabled' Enable sign extend instructions. -`-muser-enabled' +'-muser-enabled' Enable user defined instructions. -`-micache-enabled' +'-micache-enabled' Enable instruction cache related CSRs. -`-mdcache-enabled' +'-mdcache-enabled' Enable data cache related CSRs. -`-mbreak-enabled' +'-mbreak-enabled' Enable break instructions. -`-mall-enabled' +'-mall-enabled' Enable all instructions and CSRs. - File: as.info, Node: LM32 Syntax, Next: LM32 Opcodes, Prev: LM32 Options, Up: LM32-Dependent @@ -11597,71 +11344,52 @@ File: as.info, Node: LM32-Regs, Next: LM32-Modifiers, Up: LM32 Syntax 9.20.2.1 Register Names ....................... -LM32 has 32 x 32-bit general purpose registers `r0', `r1', ... `r31'. +LM32 has 32 x 32-bit general purpose registers 'r0', 'r1', ... 'r31'. - The following aliases are defined: `gp' - `r26', `fp' - `r27', `sp' -- `r28', `ra' - `r29', `ea' - `r30', `ba' - `r31'. + The following aliases are defined: 'gp' - 'r26', 'fp' - 'r27', 'sp' - +'r28', 'ra' - 'r29', 'ea' - 'r30', 'ba' - 'r31'. LM32 has the following Control and Status Registers (CSRs). -`IE' +'IE' Interrupt enable. - -`IM' +'IM' Interrupt mask. - -`IP' +'IP' Interrupt pending. - -`ICC' +'ICC' Instruction cache control. - -`DCC' +'DCC' Data cache control. - -`CC' +'CC' Cycle counter. - -`CFG' +'CFG' Configuration. - -`EBA' +'EBA' Exception base address. - -`DC' +'DC' Debug control. - -`DEBA' +'DEBA' Debug exception base address. - -`JTX' +'JTX' JTAG transmit. - -`JRX' +'JRX' JTAG receive. - -`BP0' +'BP0' Breakpoint 0. - -`BP1' +'BP1' Breakpoint 1. - -`BP2' +'BP2' Breakpoint 2. - -`BP3' +'BP3' Breakpoint 3. - -`WP0' +'WP0' Watchpoint 0. - -`WP1' +'WP1' Watchpoint 1. - -`WP2' +'WP2' Watchpoint 2. - -`WP3' +'WP3' Watchpoint 3. @@ -11676,11 +11404,13 @@ following: modifier(relocatable-expression) -`lo' +'lo' + This modifier allows you to use bits 0 through 15 of an address expression as 16 bit relocatable expression. -`hi' +'hi' + This modifier allows you to use bits 16 through 23 of an address expression as 16 bit relocatable expression. @@ -11689,44 +11419,47 @@ following: ori r4, r4, lo(sym+10) orhi r4, r4, hi(sym+10) -`gp' +'gp' + This modified creates a 16-bit relocatable expression that is the offset of the symbol from the global pointer. mva r4, gp(sym) -`got' +'got' + This modifier places a symbol in the GOT and creates a 16-bit relocatable expression that is the offset into the GOT of this symbol. lw r4, (gp+got(sym)) -`gotofflo16' - This modifier allows you to use the bits 0 through 15 of an - address which is an offset from the GOT. +'gotofflo16' + + This modifier allows you to use the bits 0 through 15 of an address + which is an offset from the GOT. + +'gotoffhi16' -`gotoffhi16' This modifier allows you to use the bits 16 through 31 of an address which is an offset from the GOT. orhi r4, r4, gotoffhi16(lsym) addi r4, r4, gotofflo16(lsym) - File: as.info, Node: LM32-Chars, Prev: LM32-Modifiers, Up: LM32 Syntax 9.20.2.3 Special Characters ........................... -The presence of a `#' on a line indicates the start of a comment that -extends to the end of the current line. Note that if a line starts -with a `#' character then it can also be a logical line number -directive (*note Comments::) or a preprocessor control command (*note +The presence of a '#' on a line indicates the start of a comment that +extends to the end of the current line. Note that if a line starts with +a '#' character then it can also be a logical line number directive +(*note Comments::) or a preprocessor control command (*note Preprocessing::). - A semicolon (`;') can be used to separate multiple statements on the + A semicolon (';') can be used to separate multiple statements on the same line. @@ -11736,9 +11469,9 @@ File: as.info, Node: LM32 Opcodes, Prev: LM32 Syntax, Up: LM32-Dependent -------------- For detailed information on the LM32 machine instruction set, see -`http://www.latticesemi.com/products/intellectualproperty/ipcores/mico32/'. +<http://www.latticesemi.com/products/intellectualproperty/ipcores/mico32/>. - `as' implements all the standard LM32 opcodes. + 'as' implements all the standard LM32 opcodes. File: as.info, Node: M32C-Dependent, Next: M32R-Dependent, Prev: LM32-Dependent, Up: Machine Dependencies @@ -11746,10 +11479,10 @@ File: as.info, Node: M32C-Dependent, Next: M32R-Dependent, Prev: LM32-Depende 9.21 M32C Dependent Features ============================ - `as' can assemble code for several different members of the Renesas -M32C family. Normally the default is to assemble code for the M16C -microprocessor. The `-m32c' option may be used to change the default -to the M32C microprocessor. +'as' can assemble code for several different members of the Renesas M32C +family. Normally the default is to assemble code for the M16C +microprocessor. The '-m32c' option may be used to change the default to +the M32C microprocessor. * Menu: @@ -11762,21 +11495,20 @@ File: as.info, Node: M32C-Opts, Next: M32C-Syntax, Up: M32C-Dependent 9.21.1 M32C Options ------------------- -The Renesas M32C version of `as' has these machine-dependent options: +The Renesas M32C version of 'as' has these machine-dependent options: -`-m32c' +'-m32c' Assemble M32C instructions. -`-m16c' +'-m16c' Assemble M16C instructions (default). -`-relax' +'-relax' Enable support for link-time relaxations. -`-h-tick-hex' +'-h-tick-hex' Support H'00 style hex constants in addition to 0x00 style. - File: as.info, Node: M32C-Syntax, Prev: M32C-Opts, Up: M32C-Dependent @@ -11799,12 +11531,13 @@ M32C instruction operands. The general syntax is the following: %modifier(symbol) -`%dsp8' -`%dsp16' +'%dsp8' +'%dsp16' + These modifiers override the assembler's assumptions about how big a symbol's address is. Normally, when it sees an operand like - `sym[a0]' it assumes `sym' may require the widest displacement - field (16 bits for `-m16c', 24 bits for `-m32c'). These modifiers + 'sym[a0]' it assumes 'sym' may require the widest displacement + field (16 bits for '-m16c', 24 bits for '-m32c'). These modifiers tell it to assume the address will fit in an 8 or 16 bit (respectively) unsigned displacement. Note that, of course, if it doesn't actually fit you will get linker errors. Example: @@ -11812,25 +11545,28 @@ M32C instruction operands. The general syntax is the following: mov.w %dsp8(sym)[a0],r1 mov.b #0,%dsp8(sym)[a0] -`%hi8' +'%hi8' + This modifier allows you to load bits 16 through 23 of a 24 bit address into an 8 bit register. This is useful with, for example, - the M16C `smovf' instruction, which expects a 20 bit address in - `r1h' and `a0'. Example: + the M16C 'smovf' instruction, which expects a 20 bit address in + 'r1h' and 'a0'. Example: mov.b #%hi8(sym),r1h mov.w #%lo16(sym),a0 smovf.b -`%lo16' +'%lo16' + Likewise, this modifier allows you to load bits 0 through 15 of a 24 bit address into a 16 bit register. -`%hi16' +'%hi16' + This modifier allows you to load bits 16 through 31 of a 32 bit address into a 16 bit register. While the M32C family only has 24 bits of address space, it does support addresses in pairs of 16 bit - registers (like `a1a0' for the `lde' instruction). This modifier + registers (like 'a1a0' for the 'lde' instruction). This modifier is for loading the upper half in such cases. Example: mov.w #%hi16(sym),a1 @@ -11838,22 +11574,21 @@ M32C instruction operands. The general syntax is the following: ... lde.w [a1a0],r1 - File: as.info, Node: M32C-Chars, Prev: M32C-Modifiers, Up: M32C-Syntax 9.21.2.2 Special Characters ........................... -The presence of a `;' character on a line indicates the start of a +The presence of a ';' character on a line indicates the start of a comment that extends to the end of that line. - If a `#' appears as the first character of a line, the whole line is + If a '#' appears as the first character of a line, the whole line is treated as a comment, but in this case the line can also be a logical line number directive (*note Comments::) or a preprocessor control command (*note Preprocessing::). - The `|' character can be used to separate statements on the same + The '|' character can be used to separate statements on the same line. @@ -11874,153 +11609,152 @@ File: as.info, Node: M32R-Opts, Next: M32R-Directives, Up: M32R-Dependent 9.22.1 M32R Options ------------------- -The Renease M32R version of `as' has a few machine dependent options: +The Renease M32R version of 'as' has a few machine dependent options: -`-m32rx' - `as' can assemble code for several different members of the - Renesas M32R family. Normally the default is to assemble code for - the M32R microprocessor. This option may be used to change the - default to the M32RX microprocessor, which adds some more - instructions to the basic M32R instruction set, and some - additional parameters to some of the original instructions. +'-m32rx' + 'as' can assemble code for several different members of the Renesas + M32R family. Normally the default is to assemble code for the M32R + microprocessor. This option may be used to change the default to + the M32RX microprocessor, which adds some more instructions to the + basic M32R instruction set, and some additional parameters to some + of the original instructions. -`-m32r2' - This option changes the target processor to the the M32R2 +'-m32r2' + This option changes the target processor to the M32R2 microprocessor. -`-m32r' +'-m32r' This option can be used to restore the assembler's default behaviour of assembling for the M32R microprocessor. This can be useful if the default has been changed by a previous command line option. -`-little' +'-little' This option tells the assembler to produce little-endian code and data. The default is dependent upon how the toolchain was configured. -`-EL' +'-EL' This is a synonym for _-little_. -`-big' +'-big' This option tells the assembler to produce big-endian code and data. -`-EB' +'-EB' This is a synonum for _-big_. -`-KPIC' +'-KPIC' This option specifies that the output of the assembler should be marked as position-independent code (PIC). -`-parallel' +'-parallel' This option tells the assembler to attempts to combine two sequential instructions into a single, parallel instruction, where it is legal to do so. -`-no-parallel' +'-no-parallel' This option disables a previously enabled _-parallel_ option. -`-no-bitinst' +'-no-bitinst' This option disables the support for the extended bit-field instructions provided by the M32R2. If this support needs to be re-enabled the _-bitinst_ switch can be used to restore it. -`-O' +'-O' This option tells the assembler to attempt to optimize the instructions that it produces. This includes filling delay slots and converting sequential instructions into parallel ones. This option implies _-parallel_. -`-warn-explicit-parallel-conflicts' - Instructs `as' to produce warning messages when questionable +'-warn-explicit-parallel-conflicts' + Instructs 'as' to produce warning messages when questionable parallel instructions are encountered. This option is enabled by - default, but `gcc' disables it when it invokes `as' directly. + default, but 'gcc' disables it when it invokes 'as' directly. Questionable instructions are those whose behaviour would be - different if they were executed sequentially. For example the - code fragment `mv r1, r2 || mv r3, r1' produces a different result - from `mv r1, r2 \n mv r3, r1' since the former moves r1 into r3 - and then r2 into r1, whereas the later moves r2 into r1 and r3. + different if they were executed sequentially. For example the code + fragment 'mv r1, r2 || mv r3, r1' produces a different result from + 'mv r1, r2 \n mv r3, r1' since the former moves r1 into r3 and then + r2 into r1, whereas the later moves r2 into r1 and r3. -`-Wp' +'-Wp' This is a shorter synonym for the _-warn-explicit-parallel-conflicts_ option. -`-no-warn-explicit-parallel-conflicts' - Instructs `as' not to produce warning messages when questionable +'-no-warn-explicit-parallel-conflicts' + Instructs 'as' not to produce warning messages when questionable parallel instructions are encountered. -`-Wnp' +'-Wnp' This is a shorter synonym for the _-no-warn-explicit-parallel-conflicts_ option. -`-ignore-parallel-conflicts' +'-ignore-parallel-conflicts' This option tells the assembler's to stop checking parallel instructions for constraint violations. This ability is provided for hardware vendors testing chip designs and should not be used under normal circumstances. -`-no-ignore-parallel-conflicts' +'-no-ignore-parallel-conflicts' This option restores the assembler's default behaviour of checking parallel instructions to detect constraint violations. -`-Ip' +'-Ip' This is a shorter synonym for the _-ignore-parallel-conflicts_ option. -`-nIp' +'-nIp' This is a shorter synonym for the _-no-ignore-parallel-conflicts_ option. -`-warn-unmatched-high' +'-warn-unmatched-high' This option tells the assembler to produce a warning message if a - `.high' pseudo op is encountered without a matching `.low' pseudo + '.high' pseudo op is encountered without a matching '.low' pseudo op. The presence of such an unmatched pseudo op usually indicates a programming error. -`-no-warn-unmatched-high' +'-no-warn-unmatched-high' Disables a previously enabled _-warn-unmatched-high_ option. -`-Wuh' +'-Wuh' This is a shorter synonym for the _-warn-unmatched-high_ option. -`-Wnuh' +'-Wnuh' This is a shorter synonym for the _-no-warn-unmatched-high_ option. - File: as.info, Node: M32R-Directives, Next: M32R-Warnings, Prev: M32R-Opts, Up: M32R-Dependent 9.22.2 M32R Directives ---------------------- -The Renease M32R version of `as' has a few architecture specific +The Renease M32R version of 'as' has a few architecture specific directives: -`low EXPRESSION' - The `low' directive computes the value of its expression and - places the lower 16-bits of the result into the immediate-field of - the instruction. For example: +'low EXPRESSION' + The 'low' directive computes the value of its expression and places + the lower 16-bits of the result into the immediate-field of the + instruction. For example: or3 r0, r0, #low(0x12345678) ; compute r0 = r0 | 0x5678 add3, r0, r0, #low(fred) ; compute r0 = r0 + low 16-bits of address of fred -`high EXPRESSION' - The `high' directive computes the value of its expression and +'high EXPRESSION' + The 'high' directive computes the value of its expression and places the upper 16-bits of the result into the immediate-field of the instruction. For example: seth r0, #high(0x12345678) ; compute r0 = 0x12340000 seth, r0, #high(fred) ; compute r0 = upper 16-bits of address of fred -`shigh EXPRESSION' - The `shigh' directive is very similar to the `high' directive. It +'shigh EXPRESSION' + The 'shigh' directive is very similar to the 'high' directive. It also computes the value of its expression and places the upper 16-bits of the result into the immediate-field of the instruction. - The difference is that `shigh' also checks to see if the lower + The difference is that 'shigh' also checks to see if the lower 16-bits could be interpreted as a signed number, and if so it assumes that a borrow will occur from the upper-16 bits. To - compensate for this the `shigh' directive pre-biases the upper 16 + compensate for this the 'shigh' directive pre-biases the upper 16 bit value by adding one to it. For example: For example: @@ -12033,10 +11767,10 @@ directives: value becomes 0xffff8000. If this value is then added to 0x00010000 then the result is 0x00008000. - This behaviour is to allow for the different semantics of the - `or3' and `add3' instructions. The `or3' instruction treats its - 16-bit immediate argument as unsigned whereas the `add3' treats - its 16-bit immediate as a signed value. So for example: + This behaviour is to allow for the different semantics of the 'or3' + and 'add3' instructions. The 'or3' instruction treats its 16-bit + immediate argument as unsigned whereas the 'add3' treats its 16-bit + immediate as a signed value. So for example: seth r0, #shigh(0x00008000) add3 r0, r0, #low(0x00008000) @@ -12048,41 +11782,40 @@ directives: Stores 0xffff8000 into r0. - Note - the `shigh' directive does not know where in the assembly + Note - the 'shigh' directive does not know where in the assembly source code the lower 16-bits of the value are going set, so it - cannot check to make sure that an `or3' instruction is being used - rather than an `add3' instruction. It is up to the programmer to + cannot check to make sure that an 'or3' instruction is being used + rather than an 'add3' instruction. It is up to the programmer to make sure that correct directives are used. -`.m32r' +'.m32r' The directive performs a similar thing as the _-m32r_ command line option. It tells the assembler to only accept M32R instructions from now on. An instructions from later M32R architectures are refused. -`.m32rx' - The directive performs a similar thing as the _-m32rx_ command - line option. It tells the assembler to start accepting the extra +'.m32rx' + The directive performs a similar thing as the _-m32rx_ command line + option. It tells the assembler to start accepting the extra instructions in the M32RX ISA as well as the ordinary M32R ISA. -`.m32r2' - The directive performs a similar thing as the _-m32r2_ command - line option. It tells the assembler to start accepting the extra +'.m32r2' + The directive performs a similar thing as the _-m32r2_ command line + option. It tells the assembler to start accepting the extra instructions in the M32R2 ISA as well as the ordinary M32R ISA. -`.little' +'.little' The directive performs a similar thing as the _-little_ command line option. It tells the assembler to start producing little-endian code and data. This option should be used with care as producing mixed-endian binary files is fraught with danger. -`.big' +'.big' The directive performs a similar thing as the _-big_ command line option. It tells the assembler to start producing big-endian code and data. This option should be used with care as producing mixed-endian binary files is fraught with danger. - File: as.info, Node: M32R-Warnings, Prev: M32R-Directives, Up: M32R-Dependent @@ -12090,60 +11823,59 @@ File: as.info, Node: M32R-Warnings, Prev: M32R-Directives, Up: M32R-Dependent -------------------- There are several warning and error messages that can be produced by -`as' which are specific to the M32R: +'as' which are specific to the M32R: -`output of 1st instruction is the same as an input to 2nd instruction - is this intentional ?' +'output of 1st instruction is the same as an input to 2nd instruction - is this intentional ?' This message is only produced if warnings for explicit parallel conflicts have been enabled. It indicates that the assembler has encountered a parallel instruction in which the destination register of the left hand instruction is used as an input register in the right hand instruction. For example in this code fragment - `mv r1, r2 || neg r3, r1' register r1 is the destination of the + 'mv r1, r2 || neg r3, r1' register r1 is the destination of the move instruction and the input to the neg instruction. -`output of 2nd instruction is the same as an input to 1st instruction - is this intentional ?' +'output of 2nd instruction is the same as an input to 1st instruction - is this intentional ?' This message is only produced if warnings for explicit parallel conflicts have been enabled. It indicates that the assembler has encountered a parallel instruction in which the destination - register of the right hand instruction is used as an input - register in the left hand instruction. For example in this code - fragment `mv r1, r2 || neg r2, r3' register r2 is the destination - of the neg instruction and the input to the move instruction. + register of the right hand instruction is used as an input register + in the left hand instruction. For example in this code fragment + 'mv r1, r2 || neg r2, r3' register r2 is the destination of the neg + instruction and the input to the move instruction. -`instruction `...' is for the M32RX only' +'instruction '...' is for the M32RX only' This message is produced when the assembler encounters an - instruction which is only supported by the M32Rx processor, and - the `-m32rx' command line flag has not been specified to allow - assembly of such instructions. + instruction which is only supported by the M32Rx processor, and the + '-m32rx' command line flag has not been specified to allow assembly + of such instructions. -`unknown instruction `...'' +'unknown instruction '...'' This message is produced when the assembler encounters an instruction which it does not recognize. -`only the NOP instruction can be issued in parallel on the m32r' +'only the NOP instruction can be issued in parallel on the m32r' This message is produced when the assembler encounters a parallel instruction which does not involve a NOP instruction and the - `-m32rx' command line flag has not been specified. Only the M32Rx + '-m32rx' command line flag has not been specified. Only the M32Rx processor is able to execute two instructions in parallel. -`instruction `...' cannot be executed in parallel.' +'instruction '...' cannot be executed in parallel.' This message is produced when the assembler encounters a parallel instruction which is made up of one or two instructions which cannot be executed in parallel. -`Instructions share the same execution pipeline' +'Instructions share the same execution pipeline' This message is produced when the assembler encounters a parallel instruction whoes components both use the same execution pipeline. -`Instructions write to the same destination register.' +'Instructions write to the same destination register.' This message is produced when the assembler encounters a parallel instruction where both components attempt to modify the same register. For example these code fragments will produce this - message: `mv r1, r2 || neg r1, r3' `jl r0 || mv r14, r1' `st r2, - @-r1 || mv r1, r3' `mv r1, r2 || ld r0, @r1+' `cmp r1, r2 || addx + message: 'mv r1, r2 || neg r1, r3' 'jl r0 || mv r14, r1' 'st r2, + @-r1 || mv r1, r3' 'mv r1, r2 || ld r0, @r1+' 'cmp r1, r2 || addx r3, r4' (Both write to the condition bit) - File: as.info, Node: M68K-Dependent, Next: M68HC11-Dependent, Prev: M32R-Dependent, Up: Machine Dependencies @@ -12165,90 +11897,91 @@ File: as.info, Node: M68K-Opts, Next: M68K-Syntax, Up: M68K-Dependent 9.23.1 M680x0 Options --------------------- -The Motorola 680x0 version of `as' has a few machine dependent options: +The Motorola 680x0 version of 'as' has a few machine dependent options: -`-march=ARCHITECTURE' +'-march=ARCHITECTURE' This option specifies a target architecture. The following - architectures are recognized: `68000', `68010', `68020', `68030', - `68040', `68060', `cpu32', `isaa', `isaaplus', `isab', `isac' and - `cfv4e'. + architectures are recognized: '68000', '68010', '68020', '68030', + '68040', '68060', 'cpu32', 'isaa', 'isaaplus', 'isab', 'isac' and + 'cfv4e'. -`-mcpu=CPU' +'-mcpu=CPU' This option specifies a target cpu. When used in conjunction with - the `-march' option, the cpu must be within the specified + the '-march' option, the cpu must be within the specified architecture. Also, the generic features of the architecture are used for instruction generation, rather than those of the specific chip. -`-m[no-]68851' -`-m[no-]68881' -`-m[no-]div' -`-m[no-]usp' -`-m[no-]float' -`-m[no-]mac' -`-m[no-]emac' +'-m[no-]68851' +'-m[no-]68881' +'-m[no-]div' +'-m[no-]usp' +'-m[no-]float' +'-m[no-]mac' +'-m[no-]emac' + Enable or disable various architecture specific features. If a chip or architecture by default supports an option (for instance - `-march=isaaplus' includes the `-mdiv' option), explicitly + '-march=isaaplus' includes the '-mdiv' option), explicitly disabling the option will override the default. -`-l' - You can use the `-l' option to shorten the size of references to - undefined symbols. If you do not use the `-l' option, references - to undefined symbols are wide enough for a full `long' (32 bits). - (Since `as' cannot know where these symbols end up, `as' can only - allocate space for the linker to fill in later. Since `as' does - not know how far away these symbols are, it allocates as much - space as it can.) If you use this option, the references are only - one word wide (16 bits). This may be useful if you want the - object file to be as small as possible, and you know that the - relevant symbols are always less than 17 bits away. - -`--register-prefix-optional' +'-l' + You can use the '-l' option to shorten the size of references to + undefined symbols. If you do not use the '-l' option, references + to undefined symbols are wide enough for a full 'long' (32 bits). + (Since 'as' cannot know where these symbols end up, 'as' can only + allocate space for the linker to fill in later. Since 'as' does + not know how far away these symbols are, it allocates as much space + as it can.) If you use this option, the references are only one + word wide (16 bits). This may be useful if you want the object + file to be as small as possible, and you know that the relevant + symbols are always less than 17 bits away. + +'--register-prefix-optional' For some configurations, especially those where the compiler normally does not prepend an underscore to the names of user - variables, the assembler requires a `%' before any use of a + variables, the assembler requires a '%' before any use of a register name. This is intended to let the assembler distinguish - between C variables and functions named `a0' through `a7', and so - on. The `%' is always accepted, but is not required for certain - configurations, notably `sun3'. The `--register-prefix-optional' - option may be used to permit omitting the `%' even for - configurations for which it is normally required. If this is - done, it will generally be impossible to refer to C variables and + between C variables and functions named 'a0' through 'a7', and so + on. The '%' is always accepted, but is not required for certain + configurations, notably 'sun3'. The '--register-prefix-optional' + option may be used to permit omitting the '%' even for + configurations for which it is normally required. If this is done, + it will generally be impossible to refer to C variables and functions with the same names as register names. -`--bitwise-or' - Normally the character `|' is treated as a comment character, which - means that it can not be used in expressions. The `--bitwise-or' - option turns `|' into a normal character. In this mode, you must - either use C style comments, or start comments with a `#' character +'--bitwise-or' + Normally the character '|' is treated as a comment character, which + means that it can not be used in expressions. The '--bitwise-or' + option turns '|' into a normal character. In this mode, you must + either use C style comments, or start comments with a '#' character at the beginning of a line. -`--base-size-default-16 --base-size-default-32' +'--base-size-default-16 --base-size-default-32' If you use an addressing mode with a base register without - specifying the size, `as' will normally use the full 32 bit value. - For example, the addressing mode `%a0@(%d0)' is equivalent to - `%a0@(%d0:l)'. You may use the `--base-size-default-16' option to - tell `as' to default to using the 16 bit value. In this case, - `%a0@(%d0)' is equivalent to `%a0@(%d0:w)'. You may use the - `--base-size-default-32' option to restore the default behaviour. - -`--disp-size-default-16 --disp-size-default-32' - If you use an addressing mode with a displacement, and the value - of the displacement is not known, `as' will normally assume that - the value is 32 bits. For example, if the symbol `disp' has not - been defined, `as' will assemble the addressing mode - `%a0@(disp,%d0)' as though `disp' is a 32 bit value. You may use - the `--disp-size-default-16' option to tell `as' to instead assume - that the displacement is 16 bits. In this case, `as' will - assemble `%a0@(disp,%d0)' as though `disp' is a 16 bit value. You - may use the `--disp-size-default-32' option to restore the default + specifying the size, 'as' will normally use the full 32 bit value. + For example, the addressing mode '%a0@(%d0)' is equivalent to + '%a0@(%d0:l)'. You may use the '--base-size-default-16' option to + tell 'as' to default to using the 16 bit value. In this case, + '%a0@(%d0)' is equivalent to '%a0@(%d0:w)'. You may use the + '--base-size-default-32' option to restore the default behaviour. + +'--disp-size-default-16 --disp-size-default-32' + If you use an addressing mode with a displacement, and the value of + the displacement is not known, 'as' will normally assume that the + value is 32 bits. For example, if the symbol 'disp' has not been + defined, 'as' will assemble the addressing mode '%a0@(disp,%d0)' as + though 'disp' is a 32 bit value. You may use the + '--disp-size-default-16' option to tell 'as' to instead assume that + the displacement is 16 bits. In this case, 'as' will assemble + '%a0@(disp,%d0)' as though 'disp' is a 16 bit value. You may use + the '--disp-size-default-32' option to restore the default behaviour. -`--pcrel' +'--pcrel' Always keep branches PC-relative. In the M680x0 architecture all branches are defined as PC-relative. However, on some processors - they are limited to word displacements maximum. When `as' needs a + they are limited to word displacements maximum. When 'as' needs a long branch that is not available, it normally emits an absolute jump instead. This option disables this substitution. When this option is given and no long branches are available, only word @@ -12257,9 +11990,9 @@ The Motorola 680x0 version of `as' has a few machine dependent options: 68020 and other processors that have long branches. *note Branch Improvement: M68K-Branch. -`-m68000' - `as' can assemble code for several different members of the - Motorola 680x0 family. The default depends upon how `as' was +'-m68000' + 'as' can assemble code for several different members of the + Motorola 680x0 family. The default depends upon how 'as' was configured when it was built; normally, the default is to assemble code for the 68020 microprocessor. The following options may be used to change the default. These options control which @@ -12267,87 +12000,87 @@ The Motorola 680x0 version of `as' has a few machine dependent options: the 680x0 family are very similar. For detailed information about the differences, see the Motorola manuals. - `-m68000' - `-m68ec000' - `-m68hc000' - `-m68hc001' - `-m68008' - `-m68302' - `-m68306' - `-m68307' - `-m68322' - `-m68356' - Assemble for the 68000. `-m68008', `-m68302', and so on are - synonyms for `-m68000', since the chips are the same from the + '-m68000' + '-m68ec000' + '-m68hc000' + '-m68hc001' + '-m68008' + '-m68302' + '-m68306' + '-m68307' + '-m68322' + '-m68356' + Assemble for the 68000. '-m68008', '-m68302', and so on are + synonyms for '-m68000', since the chips are the same from the point of view of the assembler. - `-m68010' + '-m68010' Assemble for the 68010. - `-m68020' - `-m68ec020' + '-m68020' + '-m68ec020' Assemble for the 68020. This is normally the default. - `-m68030' - `-m68ec030' + '-m68030' + '-m68ec030' Assemble for the 68030. - `-m68040' - `-m68ec040' + '-m68040' + '-m68ec040' Assemble for the 68040. - `-m68060' - `-m68ec060' + '-m68060' + '-m68ec060' Assemble for the 68060. - `-mcpu32' - `-m68330' - `-m68331' - `-m68332' - `-m68333' - `-m68334' - `-m68336' - `-m68340' - `-m68341' - `-m68349' - `-m68360' + '-mcpu32' + '-m68330' + '-m68331' + '-m68332' + '-m68333' + '-m68334' + '-m68336' + '-m68340' + '-m68341' + '-m68349' + '-m68360' Assemble for the CPU32 family of chips. - `-m5200' - `-m5202' - `-m5204' - `-m5206' - `-m5206e' - `-m521x' - `-m5249' - `-m528x' - `-m5307' - `-m5407' - `-m547x' - `-m548x' - `-mcfv4' - `-mcfv4e' + '-m5200' + '-m5202' + '-m5204' + '-m5206' + '-m5206e' + '-m521x' + '-m5249' + '-m528x' + '-m5307' + '-m5407' + '-m547x' + '-m548x' + '-mcfv4' + '-mcfv4e' Assemble for the ColdFire family of chips. - `-m68881' - `-m68882' + '-m68881' + '-m68882' Assemble 68881 floating point instructions. This is the default for the 68020, 68030, and the CPU32. The 68040 and 68060 always support floating point instructions. - `-mno-68881' + '-mno-68881' Do not assemble 68881 floating point instructions. This is the default for 68000 and the 68010. The 68040 and 68060 always support floating point instructions, even if this option is used. - `-m68851' + '-m68851' Assemble 68851 MMU instructions. This is the default for the 68020, 68030, and 68060. The 68040 accepts a somewhat - different set of MMU instructions; `-m68851' and `-m68040' + different set of MMU instructions; '-m68851' and '-m68040' should not be used together. - `-mno-68851' + '-mno-68851' Do not assemble 68851 MMU instructions. This is the default for the 68000, 68010, and the CPU32. The 68040 accepts a somewhat different set of MMU instructions. @@ -12360,61 +12093,61 @@ File: as.info, Node: M68K-Syntax, Next: M68K-Moto-Syntax, Prev: M68K-Opts, U This syntax for the Motorola 680x0 was developed at MIT. - The 680x0 version of `as' uses instructions names and syntax -compatible with the Sun assembler. Intervening periods are ignored; -for example, `movl' is equivalent to `mov.l'. + The 680x0 version of 'as' uses instructions names and syntax +compatible with the Sun assembler. Intervening periods are ignored; for +example, 'movl' is equivalent to 'mov.l'. In the following table APC stands for any of the address registers -(`%a0' through `%a7'), the program counter (`%pc'), the zero-address -relative to the program counter (`%zpc'), a suppressed address register -(`%za0' through `%za7'), or it may be omitted entirely. The use of -SIZE means one of `w' or `l', and it may be omitted, along with the -leading colon, unless a scale is also specified. The use of SCALE -means one of `1', `2', `4', or `8', and it may always be omitted along -with the leading colon. +('%a0' through '%a7'), the program counter ('%pc'), the zero-address +relative to the program counter ('%zpc'), a suppressed address register +('%za0' through '%za7'), or it may be omitted entirely. The use of SIZE +means one of 'w' or 'l', and it may be omitted, along with the leading +colon, unless a scale is also specified. The use of SCALE means one of +'1', '2', '4', or '8', and it may always be omitted along with the +leading colon. The following addressing modes are understood: "Immediate" - `#NUMBER' + '#NUMBER' "Data Register" - `%d0' through `%d7' + '%d0' through '%d7' "Address Register" - `%a0' through `%a7' - `%a7' is also known as `%sp', i.e., the Stack Pointer. `%a6' is - also known as `%fp', the Frame Pointer. + '%a0' through '%a7' + '%a7' is also known as '%sp', i.e., the Stack Pointer. '%a6' is + also known as '%fp', the Frame Pointer. "Address Register Indirect" - `%a0@' through `%a7@' + '%a0@' through '%a7@' "Address Register Postincrement" - `%a0@+' through `%a7@+' + '%a0@+' through '%a7@+' "Address Register Predecrement" - `%a0@-' through `%a7@-' + '%a0@-' through '%a7@-' "Indirect Plus Offset" - `APC@(NUMBER)' + 'APC@(NUMBER)' "Index" - `APC@(NUMBER,REGISTER:SIZE:SCALE)' + 'APC@(NUMBER,REGISTER:SIZE:SCALE)' The NUMBER may be omitted. "Postindex" - `APC@(NUMBER)@(ONUMBER,REGISTER:SIZE:SCALE)' + 'APC@(NUMBER)@(ONUMBER,REGISTER:SIZE:SCALE)' The ONUMBER or the REGISTER, but not both, may be omitted. "Preindex" - `APC@(NUMBER,REGISTER:SIZE:SCALE)@(ONUMBER)' + 'APC@(NUMBER,REGISTER:SIZE:SCALE)@(ONUMBER)' The NUMBER may be omitted. Omitting the REGISTER produces the Postindex addressing mode. "Absolute" - `SYMBOL', or `DIGITS', optionally followed by `:b', `:w', or `:l'. + 'SYMBOL', or 'DIGITS', optionally followed by ':b', ':w', or ':l'. File: as.info, Node: M68K-Moto-Syntax, Next: M68K-Float, Prev: M68K-Syntax, Up: M68K-Dependent @@ -12423,65 +12156,64 @@ File: as.info, Node: M68K-Moto-Syntax, Next: M68K-Float, Prev: M68K-Syntax, ---------------------- The standard Motorola syntax for this chip differs from the syntax -already discussed (*note Syntax: M68K-Syntax.). `as' can accept +already discussed (*note Syntax: M68K-Syntax.). 'as' can accept Motorola syntax for operands, even if MIT syntax is used for other operands in the same instruction. The two kinds of syntax are fully compatible. In the following table APC stands for any of the address registers -(`%a0' through `%a7'), the program counter (`%pc'), the zero-address -relative to the program counter (`%zpc'), or a suppressed address -register (`%za0' through `%za7'). The use of SIZE means one of `w' or -`l', and it may always be omitted along with the leading dot. The use -of SCALE means one of `1', `2', `4', or `8', and it may always be +('%a0' through '%a7'), the program counter ('%pc'), the zero-address +relative to the program counter ('%zpc'), or a suppressed address +register ('%za0' through '%za7'). The use of SIZE means one of 'w' or +'l', and it may always be omitted along with the leading dot. The use +of SCALE means one of '1', '2', '4', or '8', and it may always be omitted along with the leading asterisk. The following additional addressing modes are understood: "Address Register Indirect" - `(%a0)' through `(%a7)' - `%a7' is also known as `%sp', i.e., the Stack Pointer. `%a6' is - also known as `%fp', the Frame Pointer. + '(%a0)' through '(%a7)' + '%a7' is also known as '%sp', i.e., the Stack Pointer. '%a6' is + also known as '%fp', the Frame Pointer. "Address Register Postincrement" - `(%a0)+' through `(%a7)+' + '(%a0)+' through '(%a7)+' "Address Register Predecrement" - `-(%a0)' through `-(%a7)' + '-(%a0)' through '-(%a7)' "Indirect Plus Offset" - `NUMBER(%A0)' through `NUMBER(%A7)', or `NUMBER(%PC)'. + 'NUMBER(%A0)' through 'NUMBER(%A7)', or 'NUMBER(%PC)'. The NUMBER may also appear within the parentheses, as in - `(NUMBER,%A0)'. When used with the PC, the NUMBER may be omitted + '(NUMBER,%A0)'. When used with the PC, the NUMBER may be omitted (with an address register, omitting the NUMBER produces Address Register Indirect mode). "Index" - `NUMBER(APC,REGISTER.SIZE*SCALE)' + 'NUMBER(APC,REGISTER.SIZE*SCALE)' - The NUMBER may be omitted, or it may appear within the - parentheses. The APC may be omitted. The REGISTER and the APC - may appear in either order. If both APC and REGISTER are address - registers, and the SIZE and SCALE are omitted, then the first - register is taken as the base register, and the second as the - index register. + The NUMBER may be omitted, or it may appear within the parentheses. + The APC may be omitted. The REGISTER and the APC may appear in + either order. If both APC and REGISTER are address registers, and + the SIZE and SCALE are omitted, then the first register is taken as + the base register, and the second as the index register. "Postindex" - `([NUMBER,APC],REGISTER.SIZE*SCALE,ONUMBER)' + '([NUMBER,APC],REGISTER.SIZE*SCALE,ONUMBER)' The ONUMBER, or the REGISTER, or both, may be omitted. Either the NUMBER or the APC may be omitted, but not both. "Preindex" - `([NUMBER,APC,REGISTER.SIZE*SCALE],ONUMBER)' + '([NUMBER,APC,REGISTER.SIZE*SCALE],ONUMBER)' - The NUMBER, or the APC, or the REGISTER, or any two of them, may - be omitted. The ONUMBER may be omitted. The REGISTER and the APC - may appear in either order. If both APC and REGISTER are address + The NUMBER, or the APC, or the REGISTER, or any two of them, may be + omitted. The ONUMBER may be omitted. The REGISTER and the APC may + appear in either order. If both APC and REGISTER are address registers, and the SIZE and SCALE are omitted, then the first - register is taken as the base register, and the second as the - index register. + register is taken as the base register, and the second as the index + register. File: as.info, Node: M68K-Float, Next: M68K-Directives, Prev: M68K-Moto-Syntax, Up: M68K-Dependent @@ -12494,15 +12226,15 @@ free to add the code! The floating point formats generated by directives are these. -`.float' - `Single' precision floating point constants. +'.float' + 'Single' precision floating point constants. -`.double' - `Double' precision floating point constants. +'.double' + 'Double' precision floating point constants. -`.extend' -`.ldouble' - `Extended' precision (`long double') floating point constants. +'.extend' +'.ldouble' + 'Extended' precision ('long double') floating point constants. File: as.info, Node: M68K-Directives, Next: M68K-opcodes, Prev: M68K-Float, Up: M68K-Dependent @@ -12513,35 +12245,34 @@ File: as.info, Node: M68K-Directives, Next: M68K-opcodes, Prev: M68K-Float, In order to be compatible with the Sun assembler the 680x0 assembler understands the following directives. -`.data1' - This directive is identical to a `.data 1' directive. +'.data1' + This directive is identical to a '.data 1' directive. -`.data2' - This directive is identical to a `.data 2' directive. +'.data2' + This directive is identical to a '.data 2' directive. -`.even' - This directive is a special case of the `.align' directive; it +'.even' + This directive is a special case of the '.align' directive; it aligns the output to an even byte boundary. -`.skip' - This directive is identical to a `.space' directive. +'.skip' + This directive is identical to a '.space' directive. -`.arch NAME' +'.arch NAME' Select the target architecture and extension features. Valid - values for NAME are the same as for the `-march' command line + values for NAME are the same as for the '-march' command line option. This directive cannot be specified after any instructions have been assembled. If it is given multiple times, or in - conjunction with the `-march' option, all uses must be for the - same architecture and extension set. + conjunction with the '-march' option, all uses must be for the same + architecture and extension set. -`.cpu NAME' +'.cpu NAME' Select the target cpu. Valid valuse for NAME are the same as for - the `-mcpu' command line option. This directive cannot be + the '-mcpu' command line option. This directive cannot be specified after any instructions have been assembled. If it is - given multiple times, or in conjunction with the `-mopt' option, + given multiple times, or in conjunction with the '-mopt' option, all uses must be for the same cpu. - File: as.info, Node: M68K-opcodes, Prev: M68K-Directives, Up: M68K-Dependent @@ -12561,10 +12292,10 @@ File: as.info, Node: M68K-Branch, Next: M68K-Chars, Up: M68K-opcodes Certain pseudo opcodes are permitted for branch instructions. They expand to the shortest branch instruction that reach the target. -Generally these mnemonics are made by substituting `j' for `b' at the +Generally these mnemonics are made by substituting 'j' for 'b' at the start of a Motorola mnemonic. - The following table summarizes the pseudo-operations. A `*' flags + The following table summarizes the pseudo-operations. A '*' flags cases that are more fully described after the table: Displacement @@ -12580,36 +12311,37 @@ cases that are more fully described after the table: XX: condition NX: negative of condition XX - `*'--see full description below - `**'--this expansion mode is disallowed by `--pcrel' -`jbsr' -`jra' + '*'--see full description below + '**'--this expansion mode is disallowed by '--pcrel' + +'jbsr' +'jra' These are the simplest jump pseudo-operations; they always map to one particular machine instruction, depending on the displacement to the branch target. This instruction will be a byte or word branch is that is sufficient. Otherwise, a long branch will be emitted if available. If no long branches are available and the - `--pcrel' option is not given, an absolute long jump will be - emitted instead. If no long branches are available, the `--pcrel' + '--pcrel' option is not given, an absolute long jump will be + emitted instead. If no long branches are available, the '--pcrel' option is given, and a word branch cannot reach the target, an error message is generated. - In addition to standard branch operands, `as' allows these - pseudo-operations to have all operands that are allowed for jsr - and jmp, substituting these instructions if the operand given is - not valid for a branch instruction. + In addition to standard branch operands, 'as' allows these + pseudo-operations to have all operands that are allowed for jsr and + jmp, substituting these instructions if the operand given is not + valid for a branch instruction. -`jXX' - Here, `jXX' stands for an entire family of pseudo-operations, - where XX is a conditional branch or condition-code test. The full - list of pseudo-ops in this family is: +'jXX' + Here, 'jXX' stands for an entire family of pseudo-operations, where + XX is a conditional branch or condition-code test. The full list + of pseudo-ops in this family is: jhi jls jcc jcs jne jeq jvc jvs jpl jmi jge jlt jgt jle Usually, each of these pseudo-operations expands to a single branch instruction. However, if a word branch is not sufficient, no long - branches are available, and the `--pcrel' option is not given, `as' + branches are available, and the '--pcrel' option is not given, 'as' issues a longer code fragment in terms of NX, the opposite condition to XX. For example, under these conditions: jXX foo @@ -12618,30 +12350,30 @@ cases that are more fully described after the table: jmp foo oof: -`dbXX' +'dbXX' The full family of pseudo-operations covered here is dbhi dbls dbcc dbcs dbne dbeq dbvc dbvs dbpl dbmi dbge dblt dbgt dble dbf dbra dbt - Motorola `dbXX' instructions allow word displacements only. When - a word displacement is sufficient, each of these pseudo-operations + Motorola 'dbXX' instructions allow word displacements only. When a + word displacement is sufficient, each of these pseudo-operations expands to the corresponding Motorola instruction. When a word displacement is not sufficient and long branches are available, - when the source reads `dbXX foo', `as' emits + when the source reads 'dbXX foo', 'as' emits dbXX oo1 bras oo2 oo1:bral foo oo2: - If, however, long branches are not available and the `--pcrel' - option is not given, `as' emits + If, however, long branches are not available and the '--pcrel' + option is not given, 'as' emits dbXX oo1 bras oo2 oo1:jmp foo oo2: -`fjXX' +'fjXX' This family includes fjne fjeq fjge fjlt fjgt fjle fjf fjt fjgl fjgle fjnge fjngl fjngle fjngt @@ -12654,29 +12386,28 @@ cases that are more fully described after the table: coprocessor branch instructions allow both word and long displacements. - File: as.info, Node: M68K-Chars, Prev: M68K-Branch, Up: M68K-opcodes 9.23.6.2 Special Characters ........................... -Line comments are introduced by the `|' character appearing anywhere on -a line, unless the `--bitwise-or' command line option has been +Line comments are introduced by the '|' character appearing anywhere on +a line, unless the '--bitwise-or' command line option has been specified. - An asterisk (`*') as the first character on a line marks the start -of a line comment as well. + An asterisk ('*') as the first character on a line marks the start of +a line comment as well. - A hash character (`#') as the first character on a line also marks -the start of a line comment, but in this case it could also be a -logical line number directive (*note Comments::) or a preprocessor -control command (*note Preprocessing::). If the hash character appears + A hash character ('#') as the first character on a line also marks +the start of a line comment, but in this case it could also be a logical +line number directive (*note Comments::) or a preprocessor control +command (*note Preprocessing::). If the hash character appears elsewhere on a line it is used to introduce an immediate value. (This is for compatibility with Sun's assembler). Multiple statements on the same line can appear if they are separated -by the `;' character. +by the ';' character. File: as.info, Node: M68HC11-Dependent, Next: Meta-Dependent, Prev: M68K-Dependent, Up: Machine Dependencies @@ -12699,102 +12430,101 @@ File: as.info, Node: M68HC11-Opts, Next: M68HC11-Syntax, Up: M68HC11-Dependen 9.24.1 M68HC11 and M68HC12 Options ---------------------------------- -The Motorola 68HC11 and 68HC12 version of `as' have a few machine +The Motorola 68HC11 and 68HC12 version of 'as' have a few machine dependent options. -`-m68hc11' - This option switches the assembler into the M68HC11 mode. In this - mode, the assembler only accepts 68HC11 operands and mnemonics. It +'-m68hc11' + This option switches the assembler into the M68HC11 mode. In this + mode, the assembler only accepts 68HC11 operands and mnemonics. It produces code for the 68HC11. -`-m68hc12' - This option switches the assembler into the M68HC12 mode. In this - mode, the assembler also accepts 68HC12 operands and mnemonics. It - produces code for the 68HC12. A few 68HC11 instructions are +'-m68hc12' + This option switches the assembler into the M68HC12 mode. In this + mode, the assembler also accepts 68HC12 operands and mnemonics. It + produces code for the 68HC12. A few 68HC11 instructions are replaced by some 68HC12 instructions as recommended by Motorola specifications. -`-m68hcs12' +'-m68hcs12' This option switches the assembler into the M68HCS12 mode. This - mode is similar to `-m68hc12' but specifies to assemble for the + mode is similar to '-m68hc12' but specifies to assemble for the 68HCS12 series. The only difference is on the assembling of the - `movb' and `movw' instruction when a PC-relative operand is used. + 'movb' and 'movw' instruction when a PC-relative operand is used. -`-mm9s12x' - This option switches the assembler into the M9S12X mode. This - mode is similar to `-m68hc12' but specifies to assemble for the - S12X series which is a superset of the HCS12. +'-mm9s12x' + This option switches the assembler into the M9S12X mode. This mode + is similar to '-m68hc12' but specifies to assemble for the S12X + series which is a superset of the HCS12. -`-mm9s12xg' +'-mm9s12xg' This option switches the assembler into the XGATE mode for the RISC co-processor featured on some S12X-family chips. -`--xgate-ramoffset' +'--xgate-ramoffset' This option instructs the linker to offset RAM addresses from S12X address space into XGATE address space. -`-mshort' +'-mshort' This option controls the ABI and indicates to use a 16-bit integer - ABI. It has no effect on the assembled instructions. This is the + ABI. It has no effect on the assembled instructions. This is the default. -`-mlong' +'-mlong' This option controls the ABI and indicates to use a 32-bit integer ABI. -`-mshort-double' +'-mshort-double' This option controls the ABI and indicates to use a 32-bit float - ABI. This is the default. + ABI. This is the default. -`-mlong-double' +'-mlong-double' This option controls the ABI and indicates to use a 64-bit float ABI. -`--strict-direct-mode' - You can use the `--strict-direct-mode' option to disable the +'--strict-direct-mode' + You can use the '--strict-direct-mode' option to disable the automatic translation of direct page mode addressing into extended mode when the instruction does not support direct mode. For - example, the `clr' instruction does not support direct page mode - addressing. When it is used with the direct page mode, `as' will + example, the 'clr' instruction does not support direct page mode + addressing. When it is used with the direct page mode, 'as' will ignore it and generate an absolute addressing. This option - prevents `as' from doing this, and the wrong usage of the direct + prevents 'as' from doing this, and the wrong usage of the direct page mode will raise an error. -`--short-branches' - The `--short-branches' option turns off the translation of - relative branches into absolute branches when the branch offset is - out of range. By default `as' transforms the relative branch - (`bsr', `bgt', `bge', `beq', `bne', `ble', `blt', `bhi', `bcc', - `bls', `bcs', `bmi', `bvs', `bvs', `bra') into an absolute branch - when the offset is out of the -128 .. 127 range. In that case, - the `bsr' instruction is translated into a `jsr', the `bra' - instruction is translated into a `jmp' and the conditional - branches instructions are inverted and followed by a `jmp'. This - option disables these translations and `as' will generate an error - if a relative branch is out of range. This option does not affect - the optimization associated to the `jbra', `jbsr' and `jbXX' +'--short-branches' + The '--short-branches' option turns off the translation of relative + branches into absolute branches when the branch offset is out of + range. By default 'as' transforms the relative branch ('bsr', + 'bgt', 'bge', 'beq', 'bne', 'ble', 'blt', 'bhi', 'bcc', 'bls', + 'bcs', 'bmi', 'bvs', 'bvs', 'bra') into an absolute branch when the + offset is out of the -128 .. 127 range. In that case, the 'bsr' + instruction is translated into a 'jsr', the 'bra' instruction is + translated into a 'jmp' and the conditional branches instructions + are inverted and followed by a 'jmp'. This option disables these + translations and 'as' will generate an error if a relative branch + is out of range. This option does not affect the optimization + associated to the 'jbra', 'jbsr' and 'jbXX' pseudo opcodes. + +'--force-long-branches' + The '--force-long-branches' option forces the translation of + relative branches into absolute branches. This option does not + affect the optimization associated to the 'jbra', 'jbsr' and 'jbXX' pseudo opcodes. -`--force-long-branches' - The `--force-long-branches' option forces the translation of - relative branches into absolute branches. This option does not - affect the optimization associated to the `jbra', `jbsr' and - `jbXX' pseudo opcodes. - -`--print-insn-syntax' - You can use the `--print-insn-syntax' option to obtain the syntax +'--print-insn-syntax' + You can use the '--print-insn-syntax' option to obtain the syntax description of the instruction when an error is detected. -`--print-opcodes' - The `--print-opcodes' option prints the list of all the - instructions with their syntax. The first item of each line +'--print-opcodes' + The '--print-opcodes' option prints the list of all the + instructions with their syntax. The first item of each line represents the instruction name and the rest of the line indicates - the possible operands for that instruction. The list is printed in - alphabetical order. Once the list is printed `as' exits. + the possible operands for that instruction. The list is printed in + alphabetical order. Once the list is printed 'as' exits. -`--generate-example' - The `--generate-example' option is similar to `--print-opcodes' - but it generates an example for each instruction instead. +'--generate-example' + The '--generate-example' option is similar to '--print-opcodes' but + it generates an example for each instruction instead. File: as.info, Node: M68HC11-Syntax, Next: M68HC11-Modifiers, Prev: M68HC11-Opts, Up: M68HC11-Dependent @@ -12803,23 +12533,22 @@ File: as.info, Node: M68HC11-Syntax, Next: M68HC11-Modifiers, Prev: M68HC11-O ------------- In the M68HC11 syntax, the instruction name comes first and it may be -followed by one or several operands (up to three). Operands are -separated by comma (`,'). In the normal mode, `as' will complain if too -many operands are specified for a given instruction. In the MRI mode -(turned on with `-M' option), it will treat them as comments. Example: +followed by one or several operands (up to three). Operands are +separated by comma (','). In the normal mode, 'as' will complain if too +many operands are specified for a given instruction. In the MRI mode +(turned on with '-M' option), it will treat them as comments. Example: inx lda #23 bset 2,x #4 brclr *bot #8 foo - The presence of a `;' character or a `!' character anywhere on a -line indicates the start of a comment that extends to the end of that -line. + The presence of a ';' character or a '!' character anywhere on a line +indicates the start of a comment that extends to the end of that line. - A `*' or a `#' character at the start of a line also introduces a + A '*' or a '#' character at the start of a line also introduces a line comment, but these characters do not work elsewhere on the line. -If the first character of the line is a `#' then as well as starting a +If the first character of the line is a '#' then as well as starting a comment, the line could also be logical line number directive (*note Comments::) or a preprocessor control command (*note Preprocessing::). @@ -12828,55 +12557,54 @@ character. The following addressing modes are understood for 68HC11 and 68HC12: "Immediate" - `#NUMBER' + '#NUMBER' "Address Register" - `NUMBER,X', `NUMBER,Y' + 'NUMBER,X', 'NUMBER,Y' The NUMBER may be omitted in which case 0 is assumed. "Direct Addressing mode" - `*SYMBOL', or `*DIGITS' + '*SYMBOL', or '*DIGITS' "Absolute" - `SYMBOL', or `DIGITS' + 'SYMBOL', or 'DIGITS' - The M68HC12 has other more complex addressing modes. All of them are + The M68HC12 has other more complex addressing modes. All of them are supported and they are represented below: "Constant Offset Indexed Addressing Mode" - `NUMBER,REG' + 'NUMBER,REG' - The NUMBER may be omitted in which case 0 is assumed. The - register can be either `X', `Y', `SP' or `PC'. The assembler will - use the smaller post-byte definition according to the constant - value (5-bit constant offset, 9-bit constant offset or 16-bit - constant offset). If the constant is not known by the assembler - it will use the 16-bit constant offset post-byte and the value - will be resolved at link time. + The NUMBER may be omitted in which case 0 is assumed. The register + can be either 'X', 'Y', 'SP' or 'PC'. The assembler will use the + smaller post-byte definition according to the constant value (5-bit + constant offset, 9-bit constant offset or 16-bit constant offset). + If the constant is not known by the assembler it will use the + 16-bit constant offset post-byte and the value will be resolved at + link time. "Offset Indexed Indirect" - `[NUMBER,REG]' + '[NUMBER,REG]' - The register can be either `X', `Y', `SP' or `PC'. + The register can be either 'X', 'Y', 'SP' or 'PC'. "Auto Pre-Increment/Pre-Decrement/Post-Increment/Post-Decrement" - `NUMBER,-REG' `NUMBER,+REG' `NUMBER,REG-' `NUMBER,REG+' + 'NUMBER,-REG' 'NUMBER,+REG' 'NUMBER,REG-' 'NUMBER,REG+' - The number must be in the range `-8'..`+8' and must not be 0. The - register can be either `X', `Y', `SP' or `PC'. + The number must be in the range '-8'..'+8' and must not be 0. The + register can be either 'X', 'Y', 'SP' or 'PC'. "Accumulator Offset" - `ACC,REG' + 'ACC,REG' - The accumulator register can be either `A', `B' or `D'. The - register can be either `X', `Y', `SP' or `PC'. + The accumulator register can be either 'A', 'B' or 'D'. The + register can be either 'X', 'Y', 'SP' or 'PC'. "Accumulator D offset indexed-indirect" - `[D,REG]' - - The register can be either `X', `Y', `SP' or `PC'. + '[D,REG]' + The register can be either 'X', 'Y', 'SP' or 'PC'. For example: @@ -12899,33 +12627,32 @@ following: %modifier(symbol) -`%addr' +'%addr' This modifier indicates to the assembler and linker to use the 16-bit physical address corresponding to the symbol. This is - intended to be used on memory window systems to map a symbol in - the memory bank window. If the symbol is in a memory expansion - part, the physical address corresponds to the symbol address - within the memory bank window. If the symbol is not in a memory - expansion part, this is the symbol address (using or not using the - %addr modifier has no effect in that case). - -`%page' + intended to be used on memory window systems to map a symbol in the + memory bank window. If the symbol is in a memory expansion part, + the physical address corresponds to the symbol address within the + memory bank window. If the symbol is not in a memory expansion + part, this is the symbol address (using or not using the %addr + modifier has no effect in that case). + +'%page' This modifier indicates to use the memory page number corresponding to the symbol. If the symbol is in a memory expansion part, its page number is computed by the linker as a number used to map the page containing the symbol in the memory bank window. If the symbol is not in a memory expansion part, the page number is 0. -`%hi' +'%hi' This modifier indicates to use the 8-bit high part of the physical address of the symbol. -`%lo' +'%lo' This modifier indicates to use the 8-bit low part of the physical address of the symbol. - - For example a 68HC12 call to a function `foo_example' stored in + For example a 68HC12 call to a function 'foo_example' stored in memory expansion part could be written as follows: call %addr(foo_example),%page(foo_example) @@ -12946,35 +12673,34 @@ File: as.info, Node: M68HC11-Directives, Next: M68HC11-Float, Prev: M68HC11-M 9.24.4 Assembler Directives --------------------------- -The 68HC11 and 68HC12 version of `as' have the following specific +The 68HC11 and 68HC12 version of 'as' have the following specific assembler directives: -`.relax' - The relax directive is used by the `GNU Compiler' to emit a +'.relax' + The relax directive is used by the 'GNU Compiler' to emit a specific relocation to mark a group of instructions for linker relaxation. The sequence of instructions within the group must be known to the linker so that relaxation can be performed. -`.mode [mshort|mlong|mshort-double|mlong-double]' - This directive specifies the ABI. It overrides the `-mshort', - `-mlong', `-mshort-double' and `-mlong-double' options. +'.mode [mshort|mlong|mshort-double|mlong-double]' + This directive specifies the ABI. It overrides the '-mshort', + '-mlong', '-mshort-double' and '-mlong-double' options. -`.far SYMBOL' - This directive marks the symbol as a `far' symbol meaning that it - uses a `call/rtc' calling convention as opposed to `jsr/rts'. +'.far SYMBOL' + This directive marks the symbol as a 'far' symbol meaning that it + uses a 'call/rtc' calling convention as opposed to 'jsr/rts'. During a final link, the linker will identify references to the - `far' symbol and will verify the proper calling convention. + 'far' symbol and will verify the proper calling convention. -`.interrupt SYMBOL' +'.interrupt SYMBOL' This directive marks the symbol as an interrupt entry point. This information is then used by the debugger to correctly unwind the frame across interrupts. -`.xrefb SYMBOL' - This directive is defined for compatibility with the - `Specification for Motorola 8 and 16-Bit Assembly Language Input - Standard' and is ignored. - +'.xrefb SYMBOL' + This directive is defined for compatibility with the 'Specification + for Motorola 8 and 16-Bit Assembly Language Input Standard' and is + ignored. File: as.info, Node: M68HC11-Float, Next: M68HC11-opcodes, Prev: M68HC11-Directives, Up: M68HC11-Dependent @@ -12987,15 +12713,15 @@ free to add the code! The floating point formats generated by directives are these. -`.float' - `Single' precision floating point constants. +'.float' + 'Single' precision floating point constants. -`.double' - `Double' precision floating point constants. +'.double' + 'Double' precision floating point constants. -`.extend' -`.ldouble' - `Extended' precision (`long double') floating point constants. +'.extend' +'.ldouble' + 'Extended' precision ('long double') floating point constants. File: as.info, Node: M68HC11-opcodes, Prev: M68HC11-Float, Up: M68HC11-Dependent @@ -13015,9 +12741,9 @@ File: as.info, Node: M68HC11-Branch, Up: M68HC11-opcodes Certain pseudo opcodes are permitted for branch instructions. They expand to the shortest branch instruction that reach the target. -Generally these mnemonics are made by prepending `j' to the start of -Motorola mnemonic. These pseudo opcodes are not affected by the -`--short-branches' or `--force-long-branches' options. +Generally these mnemonics are made by prepending 'j' to the start of +Motorola mnemonic. These pseudo opcodes are not affected by the +'--short-branches' or '--force-long-branches' options. The following table summarizes the pseudo-operations. @@ -13039,30 +12765,29 @@ Motorola mnemonic. These pseudo opcodes are not affected by the XX: condition NX: negative of condition XX -`jbsr' -`jbra' +'jbsr' +'jbra' These are the simplest jump pseudo-operations; they always map to one particular machine instruction, depending on the displacement to the branch target. -`jbXX' - Here, `jbXX' stands for an entire family of pseudo-operations, +'jbXX' + Here, 'jbXX' stands for an entire family of pseudo-operations, where XX is a conditional branch or condition-code test. The full list of pseudo-ops in this family is: jbcc jbeq jbge jbgt jbhi jbvs jbpl jblo jbcs jbne jblt jble jbls jbvc jbmi For the cases of non-PC relative displacements and long - displacements, `as' issues a longer code fragment in terms of NX, - the opposite condition to XX. For example, for the non-PC - relative case: + displacements, 'as' issues a longer code fragment in terms of NX, + the opposite condition to XX. For example, for the non-PC relative + case: jbXX foo gives bNXs oof jmp foo oof: - File: as.info, Node: Meta-Dependent, Next: MicroBlaze-Dependent, Prev: M68HC11-Dependent, Up: Machine Dependencies @@ -13082,24 +12807,23 @@ File: as.info, Node: Meta Options, Next: Meta Syntax, Up: Meta-Dependent The Imagination Technologies Meta architecture is implemented in a number of versions, with each new version adding new features such as -instructions and registers. For precise details of what instructions +instructions and registers. For precise details of what instructions each core supports, please see the chip's technical reference manual. The following table lists all available Meta options. -`-mcpu=metac11' +'-mcpu=metac11' Generate code for Meta 1.1. -`-mcpu=metac12' +'-mcpu=metac12' Generate code for Meta 1.2. -`-mcpu=metac21' +'-mcpu=metac21' Generate code for Meta 2.1. -`-mfpu=metac21' +'-mfpu=metac21' Allow code to use FPU hardware of Meta 2.1. - File: as.info, Node: Meta Syntax, Prev: Meta Options, Up: Meta-Dependent @@ -13117,11 +12841,11 @@ File: as.info, Node: Meta-Chars, Next: Meta-Regs, Up: Meta Syntax 9.25.2.1 Special Characters ........................... -`!' is the line comment character. +'!' is the line comment character. - You can use `;' instead of a newline to separate statements. + You can use ';' instead of a newline to separate statements. - Since `$' has no special meaning, you may use it in symbol names. + Since '$' has no special meaning, you may use it in symbol names. File: as.info, Node: Meta-Regs, Prev: Meta-Chars, Up: Meta Syntax @@ -13130,8 +12854,8 @@ File: as.info, Node: Meta-Regs, Prev: Meta-Chars, Up: Meta Syntax ....................... Registers can be specified either using their mnemonic names, such as -`D0Re0', or using the unit plus register number separated by a `.', -such as `D0.0'. +'D0Re0', or using the unit plus register number separated by a '.', such +as 'D0.0'. File: as.info, Node: MicroBlaze-Dependent, Next: MIPS-Dependent, Prev: Meta-Dependent, Up: Machine Dependencies @@ -13139,12 +12863,11 @@ File: as.info, Node: MicroBlaze-Dependent, Next: MIPS-Dependent, Prev: Meta-D 9.26 MicroBlaze Dependent Features ================================== - The Xilinx MicroBlaze processor family includes several variants, -all using the same core instruction set. This chapter covers features -of the GNU assembler that are specific to the MicroBlaze architecture. -For details about the MicroBlaze instruction set, please see the -`MicroBlaze Processor Reference Guide (UG081)' available at -www.xilinx.com. +The Xilinx MicroBlaze processor family includes several variants, all +using the same core instruction set. This chapter covers features of +the GNU assembler that are specific to the MicroBlaze architecture. For +details about the MicroBlaze instruction set, please see the 'MicroBlaze +Processor Reference Guide (UG081)' available at www.xilinx.com. * Menu: @@ -13159,47 +12882,47 @@ File: as.info, Node: MicroBlaze Directives, Next: MicroBlaze Syntax, Up: Micr A number of assembler directives are available for MicroBlaze. -`.data8 EXPRESSION,...' - This directive is an alias for `.byte'. Each expression is +'.data8 EXPRESSION,...' + This directive is an alias for '.byte'. Each expression is assembled into an eight-bit value. -`.data16 EXPRESSION,...' - This directive is an alias for `.hword'. Each expression is +'.data16 EXPRESSION,...' + This directive is an alias for '.hword'. Each expression is assembled into an 16-bit value. -`.data32 EXPRESSION,...' - This directive is an alias for `.word'. Each expression is +'.data32 EXPRESSION,...' + This directive is an alias for '.word'. Each expression is assembled into an 32-bit value. -`.ent NAME[,LABEL]' - This directive is an alias for `.func' denoting the start of +'.ent NAME[,LABEL]' + This directive is an alias for '.func' denoting the start of function NAME at (optional) LABEL. -`.end NAME[,LABEL]' - This directive is an alias for `.endfunc' denoting the end of +'.end NAME[,LABEL]' + This directive is an alias for '.endfunc' denoting the end of function NAME. -`.gpword LABEL,...' - This directive is an alias for `.rva'. The resolved address of +'.gpword LABEL,...' + This directive is an alias for '.rva'. The resolved address of LABEL is stored in the data section. -`.weakext LABEL' +'.weakext LABEL' Declare that LABEL is a weak external symbol. -`.rodata' - Switch to .rodata section. Equivalent to `.section .rodata' +'.rodata' + Switch to .rodata section. Equivalent to '.section .rodata' -`.sdata2' - Switch to .sdata2 section. Equivalent to `.section .sdata2' +'.sdata2' + Switch to .sdata2 section. Equivalent to '.section .sdata2' -`.sdata' - Switch to .sdata section. Equivalent to `.section .sdata' +'.sdata' + Switch to .sdata section. Equivalent to '.section .sdata' -`.bss' - Switch to .bss section. Equivalent to `.section .bss' +'.bss' + Switch to .bss section. Equivalent to '.section .bss' -`.sbss' - Switch to .sbss section. Equivalent to `.section .sbss' +'.sbss' + Switch to .sbss section. Equivalent to '.section .sbss' File: as.info, Node: MicroBlaze Syntax, Prev: MicroBlaze Directives, Up: MicroBlaze-Dependent @@ -13217,15 +12940,15 @@ File: as.info, Node: MicroBlaze-Chars, Up: MicroBlaze Syntax 9.26.2.1 Special Characters ........................... -The presence of a `#' on a line indicates the start of a comment that +The presence of a '#' on a line indicates the start of a comment that extends to the end of the current line. - If a `#' appears as the first character of a line, the whole line is + If a '#' appears as the first character of a line, the whole line is treated as a comment, but in this case the line can also be a logical line number directive (*note Comments::) or a preprocessor control command (*note Preprocessing::). - The `;' character can be used to separate statements on the same + The ';' character can be used to separate statements on the same line. @@ -13234,224 +12957,242 @@ File: as.info, Node: MIPS-Dependent, Next: MMIX-Dependent, Prev: MicroBlaze-D 9.27 MIPS Dependent Features ============================ - GNU `as' for MIPS architectures supports several different MIPS +GNU 'as' for MIPS architectures supports several different MIPS processors, and MIPS ISA levels I through V, MIPS32, and MIPS64. For -information about the MIPS instruction set, see `MIPS RISC +information about the MIPS instruction set, see 'MIPS RISC Architecture', by Kane and Heindrich (Prentice-Hall). For an overview of MIPS assembly conventions, see "Appendix D: Assembly Language Programming" in the same work. * Menu: -* MIPS Opts:: Assembler options -* MIPS Object:: ECOFF object code -* MIPS Stabs:: Directives for debugging information +* MIPS Options:: Assembler options +* MIPS Macros:: High-level assembly macros +* MIPS Symbol Sizes:: Directives to override the size of symbols +* MIPS Small Data:: Controlling the use of small data accesses * MIPS ISA:: Directives to override the ISA level -* MIPS symbol sizes:: Directives to override the size of symbols +* MIPS assembly options:: Directives to control code generation * MIPS autoextend:: Directives for extending MIPS 16 bit instructions * MIPS insn:: Directive to mark data as an instruction -* MIPS option stack:: Directives to save and restore options -* MIPS ASE instruction generation overrides:: Directives to control +* MIPS NaN Encodings:: Directives to record which NaN encoding is being used +* MIPS Option Stack:: Directives to save and restore options +* MIPS ASE Instruction Generation Overrides:: Directives to control generation of MIPS ASE instructions -* MIPS floating-point:: Directives to override floating-point options +* MIPS Floating-Point:: Directives to override floating-point options * MIPS Syntax:: MIPS specific syntactical considerations -File: as.info, Node: MIPS Opts, Next: MIPS Object, Up: MIPS-Dependent +File: as.info, Node: MIPS Options, Next: MIPS Macros, Up: MIPS-Dependent 9.27.1 Assembler options ------------------------ -The MIPS configurations of GNU `as' support these special options: +The MIPS configurations of GNU 'as' support these special options: -`-G NUM' - This option sets the largest size of an object that can be - referenced implicitly with the `gp' register. It is only accepted - for targets that use ECOFF format. The default value is 8. +'-G NUM' + Set the "small data" limit to N bytes. The default limit is 8 + bytes. *Note Controlling the use of small data accesses: MIPS + Small Data. -`-EB' -`-EL' - Any MIPS configuration of `as' can select big-endian or +'-EB' +'-EL' + Any MIPS configuration of 'as' can select big-endian or little-endian output at run time (unlike the other GNU development - tools, which must be configured for one or the other). Use `-EB' - to select big-endian output, and `-EL' for little-endian. + tools, which must be configured for one or the other). Use '-EB' + to select big-endian output, and '-EL' for little-endian. -`-KPIC' - Generate SVR4-style PIC. This option tells the assembler to - generate SVR4-style position-independent macro expansions. It - also tells the assembler to mark the output file as PIC. +'-KPIC' + Generate SVR4-style PIC. This option tells the assembler to + generate SVR4-style position-independent macro expansions. It also + tells the assembler to mark the output file as PIC. -`-mvxworks-pic' - Generate VxWorks PIC. This option tells the assembler to generate +'-mvxworks-pic' + Generate VxWorks PIC. This option tells the assembler to generate VxWorks-style position-independent macro expansions. -`-mips1' -`-mips2' -`-mips3' -`-mips4' -`-mips5' -`-mips32' -`-mips32r2' -`-mips64' -`-mips64r2' +'-mips1' +'-mips2' +'-mips3' +'-mips4' +'-mips5' +'-mips32' +'-mips32r2' +'-mips64' +'-mips64r2' Generate code for a particular MIPS Instruction Set Architecture - level. `-mips1' corresponds to the R2000 and R3000 processors, - `-mips2' to the R6000 processor, `-mips3' to the R4000 processor, - and `-mips4' to the R8000 and R10000 processors. `-mips5', - `-mips32', `-mips32r2', `-mips64', and `-mips64r2' correspond to - generic MIPS V, MIPS32, MIPS32 RELEASE 2, MIPS64, and MIPS64 - RELEASE 2 ISA processors, respectively. You can also switch + level. '-mips1' corresponds to the R2000 and R3000 processors, + '-mips2' to the R6000 processor, '-mips3' to the R4000 processor, + and '-mips4' to the R8000 and R10000 processors. '-mips5', + '-mips32', '-mips32r2', '-mips64', and '-mips64r2' correspond to + generic MIPS V, MIPS32, MIPS32 Release 2, MIPS64, and MIPS64 + Release 2 ISA processors, respectively. You can also switch instruction sets during the assembly; see *note Directives to override the ISA level: MIPS ISA. -`-mgp32' -`-mfp32' +'-mgp32' +'-mfp32' Some macros have different expansions for 32-bit and 64-bit registers. The register sizes are normally inferred from the ISA and ABI, but these flags force a certain group of registers to be - treated as 32 bits wide at all times. `-mgp32' controls the size - of general-purpose registers and `-mfp32' controls the size of + treated as 32 bits wide at all times. '-mgp32' controls the size + of general-purpose registers and '-mfp32' controls the size of floating-point registers. - The `.set gp=32' and `.set fp=32' directives allow the size of - registers to be changed for parts of an object. The default value - is restored by `.set gp=default' and `.set fp=default'. + The '.set gp=32' and '.set fp=32' directives allow the size of + registers to be changed for parts of an object. The default value + is restored by '.set gp=default' and '.set fp=default'. On some MIPS variants there is a 32-bit mode flag; when this flag is set, 64-bit instructions generate a trap. Also, some 32-bit OSes only save the 32-bit registers on a context switch, so it is essential never to use the 64-bit registers. -`-mgp64' -`-mfp64' +'-mgp64' +'-mfp64' Assume that 64-bit registers are available. This is provided in - the interests of symmetry with `-mgp32' and `-mfp32'. + the interests of symmetry with '-mgp32' and '-mfp32'. - The `.set gp=64' and `.set fp=64' directives allow the size of - registers to be changed for parts of an object. The default value - is restored by `.set gp=default' and `.set fp=default'. + The '.set gp=64' and '.set fp=64' directives allow the size of + registers to be changed for parts of an object. The default value + is restored by '.set gp=default' and '.set fp=default'. -`-mips16' -`-no-mips16' +'-mips16' +'-no-mips16' Generate code for the MIPS 16 processor. This is equivalent to - putting `.set mips16' at the start of the assembly file. - `-no-mips16' turns off this option. + putting '.set mips16' at the start of the assembly file. + '-no-mips16' turns off this option. -`-mmicromips' -`-mno-micromips' +'-mmicromips' +'-mno-micromips' Generate code for the microMIPS processor. This is equivalent to - putting `.set micromips' at the start of the assembly file. - `-mno-micromips' turns off this option. This is equivalent to - putting `.set nomicromips' at the start of the assembly file. + putting '.set micromips' at the start of the assembly file. + '-mno-micromips' turns off this option. This is equivalent to + putting '.set nomicromips' at the start of the assembly file. -`-msmartmips' -`-mno-smartmips' +'-msmartmips' +'-mno-smartmips' Enables the SmartMIPS extensions to the MIPS32 instruction set, which provides a number of new instructions which target smartcard and cryptographic applications. This is equivalent to putting - `.set smartmips' at the start of the assembly file. - `-mno-smartmips' turns off this option. + '.set smartmips' at the start of the assembly file. + '-mno-smartmips' turns off this option. -`-mips3d' -`-no-mips3d' - Generate code for the MIPS-3D Application Specific Extension. - This tells the assembler to accept MIPS-3D instructions. - `-no-mips3d' turns off this option. +'-mips3d' +'-no-mips3d' + Generate code for the MIPS-3D Application Specific Extension. This + tells the assembler to accept MIPS-3D instructions. '-no-mips3d' + turns off this option. -`-mdmx' -`-no-mdmx' +'-mdmx' +'-no-mdmx' Generate code for the MDMX Application Specific Extension. This - tells the assembler to accept MDMX instructions. `-no-mdmx' turns + tells the assembler to accept MDMX instructions. '-no-mdmx' turns off this option. -`-mdsp' -`-mno-dsp' +'-mdsp' +'-mno-dsp' Generate code for the DSP Release 1 Application Specific Extension. This tells the assembler to accept DSP Release 1 instructions. - `-mno-dsp' turns off this option. + '-mno-dsp' turns off this option. -`-mdspr2' -`-mno-dspr2' +'-mdspr2' +'-mno-dspr2' Generate code for the DSP Release 2 Application Specific Extension. This option implies -mdsp. This tells the assembler to accept DSP - Release 2 instructions. `-mno-dspr2' turns off this option. + Release 2 instructions. '-mno-dspr2' turns off this option. -`-mmt' -`-mno-mt' +'-mmt' +'-mno-mt' Generate code for the MT Application Specific Extension. This - tells the assembler to accept MT instructions. `-mno-mt' turns - off this option. + tells the assembler to accept MT instructions. '-mno-mt' turns off + this option. -`-mmcu' -`-mno-mcu' +'-mmcu' +'-mno-mcu' Generate code for the MCU Application Specific Extension. This - tells the assembler to accept MCU instructions. `-mno-mcu' turns + tells the assembler to accept MCU instructions. '-mno-mcu' turns off this option. -`-mfix7000' -`-mno-fix7000' +'-mvirt' +'-mno-virt' + Generate code for the Virtualization Application Specific + Extension. This tells the assembler to accept Virtualization + instructions. '-mno-virt' turns off this option. + +'-minsn32' +'-mno-insn32' + Only use 32-bit instruction encodings when generating code for the + microMIPS processor. This option inhibits the use of any 16-bit + instructions. This is equivalent to putting '.set insn32' at the + start of the assembly file. '-mno-insn32' turns off this option. + This is equivalent to putting '.set noinsn32' at the start of the + assembly file. By default '-mno-insn32' is selected, allowing all + instructions to be used. + +'-mfix7000' +'-mno-fix7000' Cause nops to be inserted if the read of the destination register of an mfhi or mflo instruction occurs in the following two instructions. -`-mfix-loongson2f-jump' -`-mno-fix-loongson2f-jump' - Eliminate instruction fetch from outside 256M region to work - around the Loongson2F `jump' instructions. Without it, under - extreme cases, the kernel may crash. The issue has been solved in - latest processor batches, but this fix has no side effect to them. - -`-mfix-loongson2f-nop' -`-mno-fix-loongson2f-nop' - Replace nops by `or at,at,zero' to work around the Loongson2F - `nop' errata. Without it, under extreme cases, cpu might - deadlock. The issue has been solved in latest loongson2f batches, - but this fix has no side effect to them. - -`-mfix-vr4120' -`-mno-fix-vr4120' +'-mfix-loongson2f-jump' +'-mno-fix-loongson2f-jump' + Eliminate instruction fetch from outside 256M region to work around + the Loongson2F 'jump' instructions. Without it, under extreme + cases, the kernel may crash. The issue has been solved in latest + processor batches, but this fix has no side effect to them. + +'-mfix-loongson2f-nop' +'-mno-fix-loongson2f-nop' + Replace nops by 'or at,at,zero' to work around the Loongson2F 'nop' + errata. Without it, under extreme cases, the CPU might deadlock. + The issue has been solved in later Loongson2F batches, but this fix + has no side effect to them. + +'-mfix-vr4120' +'-mno-fix-vr4120' Insert nops to work around certain VR4120 errata. This option is intended to be used on GCC-generated code: it is not designed to catch all problems in hand-written assembler code. -`-mfix-vr4130' -`-mno-fix-vr4130' - Insert nops to work around the VR4130 `mflo'/`mfhi' errata. +'-mfix-vr4130' +'-mno-fix-vr4130' + Insert nops to work around the VR4130 'mflo'/'mfhi' errata. -`-mfix-24k' -`-mno-fix-24k' - Insert nops to work around the 24K `eret'/`deret' errata. +'-mfix-24k' +'-mno-fix-24k' + Insert nops to work around the 24K 'eret'/'deret' errata. -`-mfix-cn63xxp1' -`-mno-fix-cn63xxp1' - Replace `pref' hints 0 - 4 and 6 - 24 with hint 28 to work around +'-mfix-cn63xxp1' +'-mno-fix-cn63xxp1' + Replace 'pref' hints 0 - 4 and 6 - 24 with hint 28 to work around certain CN63XXP1 errata. -`-m4010' -`-no-m4010' +'-m4010' +'-no-m4010' Generate code for the LSI R4010 chip. This tells the assembler to - accept the R4010 specific instructions (`addciu', `ffc', etc.), - and to not schedule `nop' instructions around accesses to the `HI' - and `LO' registers. `-no-m4010' turns off this option. - -`-m4650' -`-no-m4650' - Generate code for the MIPS R4650 chip. This tells the assembler - to accept the `mad' and `madu' instruction, and to not schedule - `nop' instructions around accesses to the `HI' and `LO' registers. - `-no-m4650' turns off this option. - -`-m3900' -`-no-m3900' -`-m4100' -`-no-m4100' - For each option `-mNNNN', generate code for the MIPS RNNNN chip. + accept the R4010-specific instructions ('addciu', 'ffc', etc.), and + to not schedule 'nop' instructions around accesses to the 'HI' and + 'LO' registers. '-no-m4010' turns off this option. + +'-m4650' +'-no-m4650' + Generate code for the MIPS R4650 chip. This tells the assembler to + accept the 'mad' and 'madu' instruction, and to not schedule 'nop' + instructions around accesses to the 'HI' and 'LO' registers. + '-no-m4650' turns off this option. + +'-m3900' +'-no-m3900' +'-m4100' +'-no-m4100' + For each option '-mNNNN', generate code for the MIPS RNNNN chip. This tells the assembler to accept instructions specific to that chip, and to schedule for that chip's hazards. -`-march=CPU' - Generate code for a particular MIPS cpu. It is exactly equivalent - to `-mCPU', except that there are more value of CPU understood. +'-march=CPU' + Generate code for a particular MIPS CPU. It is exactly equivalent + to '-mCPU', except that there are more value of CPU understood. Valid CPU value are: 2000, 3000, 3900, 4000, 4010, 4100, 4111, vr4120, vr4130, @@ -13465,142 +13206,183 @@ The MIPS configurations of GNU `as' support these special options: 5kf, 20kc, 25kf, sb1, sb1a, loongson2e, loongson2f, loongson3a, octeon, octeon+, octeon2, xlr, xlp - For compatibility reasons, `Nx' and `Bfx' are accepted as synonyms - for `Nf1_1'. These values are deprecated. + For compatibility reasons, 'Nx' and 'Bfx' are accepted as synonyms + for 'Nf1_1'. These values are deprecated. -`-mtune=CPU' - Schedule and tune for a particular MIPS cpu. Valid CPU values are - identical to `-march=CPU'. +'-mtune=CPU' + Schedule and tune for a particular MIPS CPU. Valid CPU values are + identical to '-march=CPU'. -`-mabi=ABI' +'-mabi=ABI' Record which ABI the source code uses. The recognized arguments - are: `32', `n32', `o64', `64' and `eabi'. + are: '32', 'n32', 'o64', '64' and 'eabi'. -`-msym32' -`-mno-sym32' - Equivalent to adding `.set sym32' or `.set nosym32' to the - beginning of the assembler input. *Note MIPS symbol sizes::. +'-msym32' +'-mno-sym32' + Equivalent to adding '.set sym32' or '.set nosym32' to the + beginning of the assembler input. *Note MIPS Symbol Sizes::. -`-nocpp' +'-nocpp' This option is ignored. It is accepted for command-line compatibility with other assemblers, which use it to turn off C - style preprocessing. With GNU `as', there is no need for - `-nocpp', because the GNU assembler itself never runs the C - preprocessor. + style preprocessing. With GNU 'as', there is no need for '-nocpp', + because the GNU assembler itself never runs the C preprocessor. -`-msoft-float' -`-mhard-float' +'-msoft-float' +'-mhard-float' Disable or enable floating-point instructions. Note that by default floating-point instructions are always allowed even with CPU targets that don't have support for these instructions. -`-msingle-float' -`-mdouble-float' +'-msingle-float' +'-mdouble-float' Disable or enable double-precision floating-point operations. Note that by default double-precision floating-point operations are always allowed even with CPU targets that don't have support for these operations. -`--construct-floats' -`--no-construct-floats' - The `--no-construct-floats' option disables the construction of +'--construct-floats' +'--no-construct-floats' + The '--no-construct-floats' option disables the construction of double width floating point constants by loading the two halves of the value into the two single width floating point registers that make up the double width register. This feature is useful if the - processor support the FR bit in its status register, and this bit + processor support the FR bit in its status register, and this bit is known (by the programmer) to be set. This bit prevents the aliasing of the double width register by the single width registers. - By default `--construct-floats' is selected, allowing construction + By default '--construct-floats' is selected, allowing construction of these floating point constants. -`--trap' -`--no-break' - `as' automatically macro expands certain division and +'--relax-branch' +'--no-relax-branch' + The '--relax-branch' option enables the relaxation of out-of-range + branches. Any branches whose target cannot be reached directly are + converted to a small instruction sequence including an + inverse-condition branch to the physically next instruction, and a + jump to the original target is inserted between the two + instructions. In PIC code the jump will involve further + instructions for address calculation. + + The 'BC1ANY2F', 'BC1ANY2T', 'BC1ANY4F', 'BC1ANY4T', 'BPOSGE32' and + 'BPOSGE64' instructions are excluded from relaxation, because they + have no complementing counterparts. They could be relaxed with the + use of a longer sequence involving another branch, however this has + not been implemented and if their target turns out of reach, they + produce an error even if branch relaxation is enabled. + + Also no MIPS16 branches are ever relaxed. + + By default '--no-relax-branch' is selected, causing any + out-of-range branches to produce an error. + +'-mnan=ENCODING' + This option indicates whether the source code uses the IEEE 2008 + NaN encoding ('-mnan=2008') or the original MIPS encoding + ('-mnan=legacy'). It is equivalent to adding a '.nan' directive to + the beginning of the source file. *Note MIPS NaN Encodings::. + + '-mnan=legacy' is the default if no '-mnan' option or '.nan' + directive is used. + +'--trap' +'--no-break' + 'as' automatically macro expands certain division and multiplication instructions to check for overflow and division by - zero. This option causes `as' to generate code to take a trap + zero. This option causes 'as' to generate code to take a trap exception rather than a break exception when an error is detected. The trap instructions are only supported at Instruction Set Architecture level 2 and higher. -`--break' -`--no-trap' +'--break' +'--no-trap' Generate code to take a break exception rather than a trap exception when an error is detected. This is the default. -`-mpdr' -`-mno-pdr' - Control generation of `.pdr' sections. Off by default on IRIX, on +'-mpdr' +'-mno-pdr' + Control generation of '.pdr' sections. Off by default on IRIX, on elsewhere. -`-mshared' -`-mno-shared' +'-mshared' +'-mno-shared' When generating code using the Unix calling conventions (selected - by `-KPIC' or `-mcall_shared'), gas will normally generate code - which can go into a shared library. The `-mno-shared' option - tells gas to generate code which uses the calling convention, but - can not go into a shared library. The resulting code is slightly - more efficient. This option only affects the handling of the - `.cpload' and `.cpsetup' pseudo-ops. + by '-KPIC' or '-mcall_shared'), gas will normally generate code + which can go into a shared library. The '-mno-shared' option tells + gas to generate code which uses the calling convention, but can not + go into a shared library. The resulting code is slightly more + efficient. This option only affects the handling of the '.cpload' + and '.cpsetup' pseudo-ops. -File: as.info, Node: MIPS Object, Next: MIPS Stabs, Prev: MIPS Opts, Up: MIPS-Dependent +File: as.info, Node: MIPS Macros, Next: MIPS Symbol Sizes, Prev: MIPS Options, Up: MIPS-Dependent -9.27.2 MIPS ECOFF object code ------------------------------ +9.27.2 High-level assembly macros +--------------------------------- -Assembling for a MIPS ECOFF target supports some additional sections -besides the usual `.text', `.data' and `.bss'. The additional sections -are `.rdata', used for read-only data, `.sdata', used for small data, -and `.sbss', used for small common objects. - - When assembling for ECOFF, the assembler uses the `$gp' (`$28') -register to form the address of a "small object". Any object in the -`.sdata' or `.sbss' sections is considered "small" in this sense. For -external objects, or for objects in the `.bss' section, you can use the -`gcc' `-G' option to control the size of objects addressed via `$gp'; -the default value is 8, meaning that a reference to any object eight -bytes or smaller uses `$gp'. Passing `-G 0' to `as' prevents it from -using the `$gp' register on the basis of object size (but the assembler -uses `$gp' for objects in `.sdata' or `sbss' in any case). The size of -an object in the `.bss' section is set by the `.comm' or `.lcomm' -directive that defines it. The size of an external object may be set -with the `.extern' directive. For example, `.extern sym,4' declares -that the object at `sym' is 4 bytes in length, whie leaving `sym' -otherwise undefined. - - Using small ECOFF objects requires linker support, and assumes that -the `$gp' register is correctly initialized (normally done -automatically by the startup code). MIPS ECOFF assembly code must not -modify the `$gp' register. - - -File: as.info, Node: MIPS Stabs, Next: MIPS ISA, Prev: MIPS Object, Up: MIPS-Dependent - -9.27.3 Directives for debugging information -------------------------------------------- +MIPS assemblers have traditionally provided a wider range of +instructions than the MIPS architecture itself. These extra +instructions are usually referred to as "macro" instructions (1). + + Some MIPS macro instructions extend an underlying architectural +instruction while others are entirely new. An example of the former +type is 'and', which allows the third operand to be either a register or +an arbitrary immediate value. Examples of the latter type include +'bgt', which branches to the third operand when the first operand is +greater than the second operand, and 'ulh', which implements an +unaligned 2-byte load. + + One of the most common extensions provided by macros is to expand +memory offsets to the full address range (32 or 64 bits) and to allow +symbolic offsets such as 'my_data + 4' to be used in place of integer +constants. For example, the architectural instruction 'lbu' allows only +a signed 16-bit offset, whereas the macro 'lbu' allows code such as 'lbu +$4,array+32769($5)'. The implementation of these symbolic offsets +depends on several factors, such as whether the assembler is generating +SVR4-style PIC (selected by '-KPIC', *note Assembler options: MIPS +Options.), the size of symbols (*note Directives to override the size of +symbols: MIPS Symbol Sizes.), and the small data limit (*note +Controlling the use of small data accesses: MIPS Small Data.). + + Sometimes it is undesirable to have one assembly instruction expand +to several machine instructions. The directive '.set nomacro' tells the +assembler to warn when this happens. '.set macro' restores the default +behavior. + + Some macro instructions need a temporary register to store +intermediate results. This register is usually '$1', also known as +'$at', but it can be changed to any core register REG using '.set +at=REG'. Note that '$at' always refers to '$1' regardless of which +register is being used as the temporary register. + + Implicit uses of the temporary register in macros could interfere +with explicit uses in the assembly code. The assembler therefore warns +whenever it sees an explicit use of the temporary register. The +directive '.set noat' silences this warning while '.set at' restores the +default behavior. It is safe to use '.set noat' while '.set nomacro' is +in effect since single-instruction macros never need a temporary +register. + + Note that while the GNU assembler provides these macros for +compatibility, it does not make any attempt to optimize them with the +surrounding code. + + ---------- Footnotes ---------- -MIPS ECOFF `as' supports several directives used for generating -debugging information which are not support by traditional MIPS -assemblers. These are `.def', `.endef', `.dim', `.file', `.scl', -`.size', `.tag', `.type', `.val', `.stabd', `.stabn', and `.stabs'. -The debugging information generated by the three `.stab' directives can -only be read by GDB, not by traditional MIPS debuggers (this -enhancement is required to fully support C++ debugging). These -directives are primarily used by compilers, not assembly language -programmers! + (1) The term "macro" is somewhat overloaded here, since these macros +have no relation to those defined by '.macro', *note '.macro': Macro. -File: as.info, Node: MIPS symbol sizes, Next: MIPS autoextend, Prev: MIPS ISA, Up: MIPS-Dependent +File: as.info, Node: MIPS Symbol Sizes, Next: MIPS Small Data, Prev: MIPS Macros, Up: MIPS-Dependent -9.27.4 Directives to override the size of symbols +9.27.3 Directives to override the size of symbols ------------------------------------------------- The n64 ABI allows symbols to have any 64-bit value. Although this provides a great deal of flexibility, it means that some macros have -much longer expansions than their 32-bit counterparts. For example, -the non-PIC expansion of `dla $4,sym' is usually: +much longer expansions than their 32-bit counterparts. For example, the +non-PIC expansion of 'dla $4,sym' is usually: lui $4,%highest(sym) lui $1,%hi(sym) @@ -13618,8 +13400,8 @@ the non-PIC expansion of `dla $4,sym' is usually: constants are known to have 32-bit values, and in such cases, it's preferable to use the 32-bit expansion instead of the 64-bit expansion. - You can use the `.set sym32' directive to tell the assembler that, -from this point on, all expressions of the form `SYMBOL' or `SYMBOL + + You can use the '.set sym32' directive to tell the assembler that, +from this point on, all expressions of the form 'SYMBOL' or 'SYMBOL + OFFSET' have 32-bit values. For example: .set sym32 @@ -13627,91 +13409,153 @@ OFFSET' have 32-bit values. For example: lw $4,sym+16 sw $4,sym+0x8000($4) - will cause the assembler to treat `sym', `sym+16' and `sym+0x8000' -as 32-bit values. The handling of non-symbolic addresses is not -affected. + will cause the assembler to treat 'sym', 'sym+16' and 'sym+0x8000' as +32-bit values. The handling of non-symbolic addresses is not affected. - The directive `.set nosym32' ends a `.set sym32' block and reverts -to the normal behavior. It is also possible to change the symbol size -using the command-line options `-msym32' and `-mno-sym32'. + The directive '.set nosym32' ends a '.set sym32' block and reverts to +the normal behavior. It is also possible to change the symbol size +using the command-line options '-msym32' and '-mno-sym32'. These options and directives are always accepted, but at present, they have no effect for anything other than n64. -File: as.info, Node: MIPS ISA, Next: MIPS symbol sizes, Prev: MIPS Stabs, Up: MIPS-Dependent +File: as.info, Node: MIPS Small Data, Next: MIPS ISA, Prev: MIPS Symbol Sizes, Up: MIPS-Dependent + +9.27.4 Controlling the use of small data accesses +------------------------------------------------- + +It often takes several instructions to load the address of a symbol. +For example, when 'addr' is a 32-bit symbol, the non-PIC expansion of +'dla $4,addr' is usually: + + lui $4,%hi(addr) + daddiu $4,$4,%lo(addr) + + The sequence is much longer when 'addr' is a 64-bit symbol. *Note +Directives to override the size of symbols: MIPS Symbol Sizes. + + In order to cut down on this overhead, most embedded MIPS systems set +aside a 64-kilobyte "small data" area and guarantee that all data of +size N and smaller will be placed in that area. The limit N is passed +to both the assembler and the linker using the command-line option '-G +N', *note Assembler options: MIPS Options. Note that the same value of +N must be used when linking and when assembling all input files to the +link; any inconsistency could cause a relocation overflow error. + + The size of an object in the '.bss' section is set by the '.comm' or +'.lcomm' directive that defines it. The size of an external object may +be set with the '.extern' directive. For example, '.extern sym,4' +declares that the object at 'sym' is 4 bytes in length, while leaving +'sym' otherwise undefined. + + When no '-G' option is given, the default limit is 8 bytes. The +option '-G 0' prevents any data from being automatically classified as +small. + + It is also possible to mark specific objects as small by putting them +in the special sections '.sdata' and '.sbss', which are "small" +counterparts of '.data' and '.bss' respectively. The toolchain will +treat such data as small regardless of the '-G' setting. + + On startup, systems that support a small data area are expected to +initialize register '$28', also known as '$gp', in such a way that small +data can be accessed using a 16-bit offset from that register. For +example, when 'addr' is small data, the 'dla $4,addr' instruction above +is equivalent to: + + daddiu $4,$28,%gp_rel(addr) + + Small data is not supported for SVR4-style PIC. + + +File: as.info, Node: MIPS ISA, Next: MIPS assembly options, Prev: MIPS Small Data, Up: MIPS-Dependent 9.27.5 Directives to override the ISA level ------------------------------------------- -GNU `as' supports an additional directive to change the MIPS -Instruction Set Architecture level on the fly: `.set mipsN'. N should -be a number from 0 to 5, or 32, 32r2, 64 or 64r2. The values other -than 0 make the assembler accept instructions for the corresponding ISA -level, from that point on in the assembly. `.set mipsN' affects not -only which instructions are permitted, but also how certain macros are -expanded. `.set mips0' restores the ISA level to its original level: -either the level you selected with command line options, or the default -for your configuration. You can use this feature to permit specific -MIPS3 instructions while assembling in 32 bit mode. Use this directive -with care! - - The `.set arch=CPU' directive provides even finer control. It +GNU 'as' supports an additional directive to change the MIPS Instruction +Set Architecture level on the fly: '.set mipsN'. N should be a number +from 0 to 5, or 32, 32r2, 64 or 64r2. The values other than 0 make the +assembler accept instructions for the corresponding ISA level, from that +point on in the assembly. '.set mipsN' affects not only which +instructions are permitted, but also how certain macros are expanded. +'.set mips0' restores the ISA level to its original level: either the +level you selected with command line options, or the default for your +configuration. You can use this feature to permit specific MIPS III +instructions while assembling in 32 bit mode. Use this directive with +care! + + The '.set arch=CPU' directive provides even finer control. It changes the effective CPU target and allows the assembler to use -instructions specific to a particular CPU. All CPUs supported by the -`-march' command line option are also selectable by this directive. -The original value is restored by `.set arch=default'. +instructions specific to a particular CPU. All CPUs supported by the +'-march' command line option are also selectable by this directive. The +original value is restored by '.set arch=default'. - The directive `.set mips16' puts the assembler into MIPS 16 mode, in + The directive '.set mips16' puts the assembler into MIPS 16 mode, in which it will assemble instructions for the MIPS 16 processor. Use -`.set nomips16' to return to normal 32 bit mode. +'.set nomips16' to return to normal 32 bit mode. Traditional MIPS assemblers do not support this directive. - The directive `.set micromips' puts the assembler into microMIPS + The directive '.set micromips' puts the assembler into microMIPS mode, in which it will assemble instructions for the microMIPS -processor. Use `.set nomicromips' to return to normal 32 bit mode. +processor. Use '.set nomicromips' to return to normal 32 bit mode. Traditional MIPS assemblers do not support this directive. -File: as.info, Node: MIPS autoextend, Next: MIPS insn, Prev: MIPS symbol sizes, Up: MIPS-Dependent +File: as.info, Node: MIPS assembly options, Next: MIPS autoextend, Prev: MIPS ISA, Up: MIPS-Dependent + +9.27.6 Directives to control code generation +-------------------------------------------- + +The directive '.set insn32' makes the assembler only use 32-bit +instruction encodings when generating code for the microMIPS processor. +This directive inhibits the use of any 16-bit instructions from that +point on in the assembly. The '.set noinsn32' directive allows 16-bit +instructions to be accepted. -9.27.6 Directives for extending MIPS 16 bit instructions + Traditional MIPS assemblers do not support this directive. + + +File: as.info, Node: MIPS autoextend, Next: MIPS insn, Prev: MIPS assembly options, Up: MIPS-Dependent + +9.27.7 Directives for extending MIPS 16 bit instructions -------------------------------------------------------- By default, MIPS 16 instructions are automatically extended to 32 bits -when necessary. The directive `.set noautoextend' will turn this off. -When `.set noautoextend' is in effect, any 32 bit instruction must be -explicitly extended with the `.e' modifier (e.g., `li.e $4,1000'). The -directive `.set autoextend' may be used to once again automatically +when necessary. The directive '.set noautoextend' will turn this off. +When '.set noautoextend' is in effect, any 32 bit instruction must be +explicitly extended with the '.e' modifier (e.g., 'li.e $4,1000'). The +directive '.set autoextend' may be used to once again automatically extend instructions when necessary. This directive is only meaningful when in MIPS 16 mode. Traditional MIPS assemblers do not support this directive. -File: as.info, Node: MIPS insn, Next: MIPS option stack, Prev: MIPS autoextend, Up: MIPS-Dependent +File: as.info, Node: MIPS insn, Next: MIPS NaN Encodings, Prev: MIPS autoextend, Up: MIPS-Dependent -9.27.7 Directive to mark data as an instruction +9.27.8 Directive to mark data as an instruction ----------------------------------------------- -The `.insn' directive tells `as' that the following data is actually +The '.insn' directive tells 'as' that the following data is actually instructions. This makes a difference in MIPS 16 and microMIPS modes: -when loading the address of a label which precedes instructions, `as' -automatically adds 1 to the value, so that jumping to the loaded -address will do the right thing. +when loading the address of a label which precedes instructions, 'as' +automatically adds 1 to the value, so that jumping to the loaded address +will do the right thing. - The `.global' and `.globl' directives supported by `as' will by + The '.global' and '.globl' directives supported by 'as' will by default mark the symbol as pointing to a region of data not code. This means that, for example, any instructions following such a symbol will -not be disassembled by `objdump' as it will regard them as data. To +not be disassembled by 'objdump' as it will regard them as data. To change this behaviour an optional section name can be placed after the -symbol name in the `.global' directive. If this section exists and is +symbol name in the '.global' directive. If this section exists and is known to be a code section, then the symbol will be marked as poiting at code not data. Ie the syntax for the directive is: - `.global SYMBOL[ SECTION][, SYMBOL[ SECTION]] ...', + '.global SYMBOL[ SECTION][, SYMBOL[ SECTION]] ...', Here is a short example: @@ -13724,15 +13568,56 @@ code not data. Ie the syntax for the directive is: .word 0x1 -File: as.info, Node: MIPS option stack, Next: MIPS ASE instruction generation overrides, Prev: MIPS insn, Up: MIPS-Dependent +File: as.info, Node: MIPS NaN Encodings, Next: MIPS Option Stack, Prev: MIPS insn, Up: MIPS-Dependent + +9.27.9 Directives to record which NaN encoding is being used +------------------------------------------------------------ + +The IEEE 754 floating-point standard defines two types of not-a-number +(NaN) data: "signalling" NaNs and "quiet" NaNs. The original version of +the standard did not specify how these two types should be +distinguished. Most implementations followed the i387 model, in which +the first bit of the significand is set for quiet NaNs and clear for +signalling NaNs. However, the original MIPS implementation assigned the +opposite meaning to the bit, so that it was set for signalling NaNs and +clear for quiet NaNs. + + The 2008 revision of the standard formally suggested the i387 choice +and as from Sep 2012 the current release of the MIPS architecture +therefore optionally supports that form. Code that uses one NaN +encoding would usually be incompatible with code that uses the other NaN +encoding, so MIPS ELF objects have a flag ('EF_MIPS_NAN2008') to record +which encoding is being used. + + Assembly files can use the '.nan' directive to select between the two +encodings. '.nan 2008' says that the assembly file uses the IEEE +754-2008 encoding while '.nan legacy' says that the file uses the +original MIPS encoding. If several '.nan' directives are given, the +final setting is the one that is used. + + The command-line options '-mnan=legacy' and '-mnan=2008' can be used +instead of '.nan legacy' and '.nan 2008' respectively. However, any +'.nan' directive overrides the command-line setting. + + '.nan legacy' is the default if no '.nan' directive or '-mnan' option +is given. + + Note that GNU 'as' does not produce NaNs itself and therefore these +directives do not affect code generation. They simply control the +setting of the 'EF_MIPS_NAN2008' flag. + + Traditional MIPS assemblers do not support these directives. + + +File: as.info, Node: MIPS Option Stack, Next: MIPS ASE Instruction Generation Overrides, Prev: MIPS NaN Encodings, Up: MIPS-Dependent -9.27.8 Directives to save and restore options ---------------------------------------------- +9.27.10 Directives to save and restore options +---------------------------------------------- -The directives `.set push' and `.set pop' may be used to save and -restore the current settings for all the options which are controlled -by `.set'. The `.set push' directive saves the current settings on a -stack. The `.set pop' directive pops the stack and restores the +The directives '.set push' and '.set pop' may be used to save and +restore the current settings for all the options which are controlled by +'.set'. The '.set push' directive saves the current settings on a +stack. The '.set pop' directive pops the stack and restores the settings. These directives can be useful inside an macro which must change an @@ -13742,73 +13627,77 @@ to change the state of the code which invoked the macro. Traditional MIPS assemblers do not support these directives. -File: as.info, Node: MIPS ASE instruction generation overrides, Next: MIPS floating-point, Prev: MIPS option stack, Up: MIPS-Dependent +File: as.info, Node: MIPS ASE Instruction Generation Overrides, Next: MIPS Floating-Point, Prev: MIPS Option Stack, Up: MIPS-Dependent -9.27.9 Directives to control generation of MIPS ASE instructions ----------------------------------------------------------------- +9.27.11 Directives to control generation of MIPS ASE instructions +----------------------------------------------------------------- -The directive `.set mips3d' makes the assembler accept instructions -from the MIPS-3D Application Specific Extension from that point on in -the assembly. The `.set nomips3d' directive prevents MIPS-3D -instructions from being accepted. +The directive '.set mips3d' makes the assembler accept instructions from +the MIPS-3D Application Specific Extension from that point on in the +assembly. The '.set nomips3d' directive prevents MIPS-3D instructions +from being accepted. - The directive `.set smartmips' makes the assembler accept + The directive '.set smartmips' makes the assembler accept instructions from the SmartMIPS Application Specific Extension to the -MIPS32 ISA from that point on in the assembly. The `.set nosmartmips' +MIPS32 ISA from that point on in the assembly. The '.set nosmartmips' directive prevents SmartMIPS instructions from being accepted. - The directive `.set mdmx' makes the assembler accept instructions + The directive '.set mdmx' makes the assembler accept instructions from the MDMX Application Specific Extension from that point on in the -assembly. The `.set nomdmx' directive prevents MDMX instructions from +assembly. The '.set nomdmx' directive prevents MDMX instructions from being accepted. - The directive `.set dsp' makes the assembler accept instructions -from the DSP Release 1 Application Specific Extension from that point -on in the assembly. The `.set nodsp' directive prevents DSP Release 1 + The directive '.set dsp' makes the assembler accept instructions from +the DSP Release 1 Application Specific Extension from that point on in +the assembly. The '.set nodsp' directive prevents DSP Release 1 instructions from being accepted. - The directive `.set dspr2' makes the assembler accept instructions -from the DSP Release 2 Application Specific Extension from that point -on in the assembly. This dirctive implies `.set dsp'. The `.set -nodspr2' directive prevents DSP Release 2 instructions from being -accepted. + The directive '.set dspr2' makes the assembler accept instructions +from the DSP Release 2 Application Specific Extension from that point on +in the assembly. This dirctive implies '.set dsp'. The '.set nodspr2' +directive prevents DSP Release 2 instructions from being accepted. - The directive `.set mt' makes the assembler accept instructions from + The directive '.set mt' makes the assembler accept instructions from the MT Application Specific Extension from that point on in the -assembly. The `.set nomt' directive prevents MT instructions from -being accepted. +assembly. The '.set nomt' directive prevents MT instructions from being +accepted. - The directive `.set mcu' makes the assembler accept instructions -from the MCU Application Specific Extension from that point on in the -assembly. The `.set nomcu' directive prevents MCU instructions from + The directive '.set mcu' makes the assembler accept instructions from +the MCU Application Specific Extension from that point on in the +assembly. The '.set nomcu' directive prevents MCU instructions from being accepted. + The directive '.set virt' makes the assembler accept instructions +from the Virtualization Application Specific Extension from that point +on in the assembly. The '.set novirt' directive prevents Virtualization +instructions from being accepted. + Traditional MIPS assemblers do not support these directives. -File: as.info, Node: MIPS floating-point, Next: MIPS Syntax, Prev: MIPS ASE instruction generation overrides, Up: MIPS-Dependent +File: as.info, Node: MIPS Floating-Point, Next: MIPS Syntax, Prev: MIPS ASE Instruction Generation Overrides, Up: MIPS-Dependent -9.27.10 Directives to override floating-point options +9.27.12 Directives to override floating-point options ----------------------------------------------------- -The directives `.set softfloat' and `.set hardfloat' provide finer +The directives '.set softfloat' and '.set hardfloat' provide finer control of disabling and enabling float-point instructions. These -directives always override the default (that hard-float instructions -are accepted) or the command-line options (`-msoft-float' and -`-mhard-float'). +directives always override the default (that hard-float instructions are +accepted) or the command-line options ('-msoft-float' and +'-mhard-float'). - The directives `.set singlefloat' and `.set doublefloat' provide + The directives '.set singlefloat' and '.set doublefloat' provide finer control of disabling and enabling double-precision float-point operations. These directives always override the default (that double-precision operations are accepted) or the command-line options -(`-msingle-float' and `-mdouble-float'). +('-msingle-float' and '-mdouble-float'). Traditional MIPS assemblers do not support these directives. -File: as.info, Node: MIPS Syntax, Prev: MIPS floating-point, Up: MIPS-Dependent +File: as.info, Node: MIPS Syntax, Prev: MIPS Floating-Point, Up: MIPS-Dependent -9.27.11 Syntactical considerations for the MIPS assembler +9.27.13 Syntactical considerations for the MIPS assembler --------------------------------------------------------- * Menu: @@ -13818,18 +13707,18 @@ File: as.info, Node: MIPS Syntax, Prev: MIPS floating-point, Up: MIPS-Depende File: as.info, Node: MIPS-Chars, Up: MIPS Syntax -9.27.11.1 Special Characters +9.27.13.1 Special Characters ............................ -The presence of a `#' on a line indicates the start of a comment that +The presence of a '#' on a line indicates the start of a comment that extends to the end of the current line. - If a `#' appears as the first character of a line, the whole line is + If a '#' appears as the first character of a line, the whole line is treated as a comment, but in this case the line can also be a logical line number directive (*note Comments::) or a preprocessor control command (*note Preprocessing::). - The `;' character can be used to separate statements on the same + The ';' character can be used to separate statements on the same line. @@ -13843,7 +13732,7 @@ File: as.info, Node: MMIX-Dependent, Next: MSP430-Dependent, Prev: MIPS-Depen * MMIX-Opts:: Command-line Options * MMIX-Expand:: Instruction expansion * MMIX-Syntax:: Syntax -* MMIX-mmixal:: Differences to `mmixal' syntax and semantics +* MMIX-mmixal:: Differences to 'mmixal' syntax and semantics File: as.info, Node: MMIX-Opts, Next: MMIX-Expand, Up: MMIX-Dependent @@ -13851,70 +13740,70 @@ File: as.info, Node: MMIX-Opts, Next: MMIX-Expand, Up: MMIX-Dependent 9.28.1 Command-line Options --------------------------- -The MMIX version of `as' has some machine-dependent options. +The MMIX version of 'as' has some machine-dependent options. - When `--fixed-special-register-names' is specified, only the register + When '--fixed-special-register-names' is specified, only the register names specified in *note MMIX-Regs:: are recognized in the instructions -`PUT' and `GET'. +'PUT' and 'GET'. - You can use the `--globalize-symbols' to make all symbols global. -This option is useful when splitting up a `mmixal' program into several + You can use the '--globalize-symbols' to make all symbols global. +This option is useful when splitting up a 'mmixal' program into several files. - The `--gnu-syntax' turns off most syntax compatibility with -`mmixal'. Its usability is currently doubtful. + The '--gnu-syntax' turns off most syntax compatibility with 'mmixal'. +Its usability is currently doubtful. - The `--relax' option is not fully supported, but will eventually make + The '--relax' option is not fully supported, but will eventually make the object file prepared for linker relaxation. If you want to avoid inadvertently calling a predefined symbol and -would rather get an error, for example when using `as' with a compiler -or other machine-generated code, specify `--no-predefined-syms'. This -turns off built-in predefined definitions of all such symbols, -including rounding-mode symbols, segment symbols, `BIT' symbols, and -`TRAP' symbols used in `mmix' "system calls". It also turns off -predefined special-register names, except when used in `PUT' and `GET' +would rather get an error, for example when using 'as' with a compiler +or other machine-generated code, specify '--no-predefined-syms'. This +turns off built-in predefined definitions of all such symbols, including +rounding-mode symbols, segment symbols, 'BIT' symbols, and 'TRAP' +symbols used in 'mmix' "system calls". It also turns off predefined +special-register names, except when used in 'PUT' and 'GET' instructions. By default, some instructions are expanded to fit the size of the operand or an external symbol (*note MMIX-Expand::). By passing -`--no-expand', no such expansion will be done, instead causing errors -at link time if the operand does not fit. +'--no-expand', no such expansion will be done, instead causing errors at +link time if the operand does not fit. - The `mmixal' documentation (*note mmixsite::) specifies that global -registers allocated with the `GREG' directive (*note MMIX-greg::) and + The 'mmixal' documentation (*note mmixsite::) specifies that global +registers allocated with the 'GREG' directive (*note MMIX-greg::) and initialized to the same non-zero value, will refer to the same global -register. This isn't strictly enforceable in `as' since the final +register. This isn't strictly enforceable in 'as' since the final addresses aren't known until link-time, but it will do an effort unless -the `--no-merge-gregs' option is specified. (Register merging isn't -yet implemented in `ld'.) - - `as' will warn every time it expands an instruction to fit an -operand unless the option `-x' is specified. It is believed that this -behaviour is more useful than just mimicking `mmixal''s behaviour, in -which instructions are only expanded if the `-x' option is specified, -and assembly fails otherwise, when an instruction needs to be expanded. -It needs to be kept in mind that `mmixal' is both an assembler and -linker, while `as' will expand instructions that at link stage can be -contracted. (Though linker relaxation isn't yet implemented in `ld'.) -The option `-x' also imples `--linker-allocated-gregs'. - - If instruction expansion is enabled, `as' can expand a `PUSHJ' -instruction into a series of instructions. The shortest expansion is -to not expand it, but just mark the call as redirectable to a stub, -which `ld' creates at link-time, but only if the original `PUSHJ' -instruction is found not to reach the target. The stub consists of the -necessary instructions to form a jump to the target. This happens if -`as' can assert that the `PUSHJ' instruction can reach such a stub. -The option `--no-pushj-stubs' disables this shorter expansion, and the -longer series of instructions is then created at assembly-time. The -option `--no-stubs' is a synonym, intended for compatibility with -future releases, where generation of stubs for other instructions may -be implemented. +the '--no-merge-gregs' option is specified. (Register merging isn't yet +implemented in 'ld'.) + + 'as' will warn every time it expands an instruction to fit an operand +unless the option '-x' is specified. It is believed that this behaviour +is more useful than just mimicking 'mmixal''s behaviour, in which +instructions are only expanded if the '-x' option is specified, and +assembly fails otherwise, when an instruction needs to be expanded. It +needs to be kept in mind that 'mmixal' is both an assembler and linker, +while 'as' will expand instructions that at link stage can be +contracted. (Though linker relaxation isn't yet implemented in 'ld'.) +The option '-x' also imples '--linker-allocated-gregs'. + + If instruction expansion is enabled, 'as' can expand a 'PUSHJ' +instruction into a series of instructions. The shortest expansion is to +not expand it, but just mark the call as redirectable to a stub, which +'ld' creates at link-time, but only if the original 'PUSHJ' instruction +is found not to reach the target. The stub consists of the necessary +instructions to form a jump to the target. This happens if 'as' can +assert that the 'PUSHJ' instruction can reach such a stub. The option +'--no-pushj-stubs' disables this shorter expansion, and the longer +series of instructions is then created at assembly-time. The option +'--no-stubs' is a synonym, intended for compatibility with future +releases, where generation of stubs for other instructions may be +implemented. Usually a two-operand-expression (*note GREG-base::) without a -matching `GREG' directive is treated as an error by `as'. When the -option `--linker-allocated-gregs' is in effect, they are instead passed +matching 'GREG' directive is treated as an error by 'as'. When the +option '--linker-allocated-gregs' is in effect, they are instead passed through to the linker, which will allocate as many global registers as is needed. @@ -13924,33 +13813,30 @@ File: as.info, Node: MMIX-Expand, Next: MMIX-Syntax, Prev: MMIX-Opts, Up: MM 9.28.2 Instruction expansion ---------------------------- -When `as' encounters an instruction with an operand that is either not -known or does not fit the operand size of the instruction, `as' (and -`ld') will expand the instruction into a sequence of instructions +When 'as' encounters an instruction with an operand that is either not +known or does not fit the operand size of the instruction, 'as' (and +'ld') will expand the instruction into a sequence of instructions semantically equivalent to the operand fitting the instruction. Expansion will take place for the following instructions: -`GETA' - Expands to a sequence of four instructions: `SETL', `INCML', - `INCMH' and `INCH'. The operand must be a multiple of four. - +'GETA' + Expands to a sequence of four instructions: 'SETL', 'INCML', + 'INCMH' and 'INCH'. The operand must be a multiple of four. Conditional branches A branch instruction is turned into a branch with the complemented condition and prediction bit over five instructions; four - instructions setting `$255' to the operand value, which like with - `GETA' must be a multiple of four, and a final `GO $255,$255,0'. - -`PUSHJ' + instructions setting '$255' to the operand value, which like with + 'GETA' must be a multiple of four, and a final 'GO $255,$255,0'. +'PUSHJ' Similar to expansion for conditional branches; four instructions - set `$255' to the operand value, followed by a `PUSHGO + set '$255' to the operand value, followed by a 'PUSHGO $255,$255,0'. +'JMP' + Similar to conditional branches and 'PUSHJ'. The final instruction + is 'GO $255,$255,0'. -`JMP' - Similar to conditional branches and `PUSHJ'. The final instruction - is `GO $255,$255,0'. - - The linker `ld' is expected to shrink these expansions for code -assembled with `--relax' (though not currently implemented). + The linker 'ld' is expected to shrink these expansions for code +assembled with '--relax' (though not currently implemented). File: as.info, Node: MMIX-Syntax, Next: MMIX-mmixal, Prev: MMIX-Expand, Up: MMIX-Dependent @@ -13959,10 +13845,10 @@ File: as.info, Node: MMIX-Syntax, Next: MMIX-mmixal, Prev: MMIX-Expand, Up: ------------- The assembly syntax is supposed to be upward compatible with that -described in Sections 1.3 and 1.4 of `The Art of Computer Programming, +described in Sections 1.3 and 1.4 of 'The Art of Computer Programming, Volume 1'. Draft versions of those chapters as well as other MMIX information is located at -`http://www-cs-faculty.stanford.edu/~knuth/mmix-news.html'. Most code +<http://www-cs-faculty.stanford.edu/~knuth/mmix-news.html>. Most code examples from the mmixal package located there should work unmodified when assembled and linked as single files, with a few noteworthy exceptions (*note MMIX-mmixal::). @@ -13971,8 +13857,8 @@ exceptions (*note MMIX-mmixal::). the next four-byte boundary. If a label is defined at the beginning of the line, its value will be the aligned value. - In addition to the traditional hex-prefix `0x', a hexadecimal number -can also be specified by the prefix character `#'. + In addition to the traditional hex-prefix '0x', a hexadecimal number +can also be specified by the prefix character '#'. After all operands to an MMIX instruction or directive have been specified, the rest of the line is ignored, treated as a comment. @@ -13990,19 +13876,19 @@ File: as.info, Node: MMIX-Chars, Next: MMIX-Symbols, Up: MMIX-Syntax 9.28.3.1 Special Characters ........................... -The characters `*' and `#' are line comment characters; each start a -comment at the beginning of a line, but only at the beginning of a -line. A `#' prefixes a hexadecimal number if found elsewhere on a -line. If a `#' appears at the start of a line the whole line is -treated as a comment, but the line can also act as a logical line -number directive (*note Comments::) or a preprocessor control command -(*note Preprocessing::). +The characters '*' and '#' are line comment characters; each start a +comment at the beginning of a line, but only at the beginning of a line. +A '#' prefixes a hexadecimal number if found elsewhere on a line. If a +'#' appears at the start of a line the whole line is treated as a +comment, but the line can also act as a logical line number directive +(*note Comments::) or a preprocessor control command (*note +Preprocessing::). - Two other characters, `%' and `!', each start a comment anywhere on -the line. Thus you can't use the `modulus' and `not' operators in + Two other characters, '%' and '!', each start a comment anywhere on +the line. Thus you can't use the 'modulus' and 'not' operators in expressions normally associated with these two characters. - A `;' is a line separator, treated as a new-line, so separate + A ';' is a line separator, treated as a new-line, so separate instructions can be specified on a single line. @@ -14011,40 +13897,39 @@ File: as.info, Node: MMIX-Symbols, Next: MMIX-Regs, Prev: MMIX-Chars, Up: MM 9.28.3.2 Symbols ................ -The character `:' is permitted in identifiers. There are two -exceptions to it being treated as any other symbol character: if a -symbol begins with `:', it means that the symbol is in the global -namespace and that the current prefix should not be prepended to that -symbol (*note MMIX-prefix::). The `:' is then not considered part of -the symbol. For a symbol in the label position (first on a line), a `:' -at the end of a symbol is silently stripped off. A label is permitted, -but not required, to be followed by a `:', as with many other assembly -formats. +The character ':' is permitted in identifiers. There are two exceptions +to it being treated as any other symbol character: if a symbol begins +with ':', it means that the symbol is in the global namespace and that +the current prefix should not be prepended to that symbol (*note +MMIX-prefix::). The ':' is then not considered part of the symbol. For +a symbol in the label position (first on a line), a ':' at the end of a +symbol is silently stripped off. A label is permitted, but not +required, to be followed by a ':', as with many other assembly formats. - The character `@' in an expression, is a synonym for `.', the -current location. + The character '@' in an expression, is a synonym for '.', the current +location. In addition to the common forward and backward local symbol formats -(*note Symbol Names::), they can be specified with upper-case `B' and -`F', as in `8B' and `9F'. A local label defined for the current -position is written with a `H' appended to the number: +(*note Symbol Names::), they can be specified with upper-case 'B' and +'F', as in '8B' and '9F'. A local label defined for the current +position is written with a 'H' appended to the number: 3H LDB $0,$1,2 This and traditional local-label formats cannot be mixed: a label must be defined and referred to using the same format. There's a minor caveat: just as for the ordinary local symbols, the local symbols are translated into ordinary symbols using control -characters are to hide the ordinal number of the symbol. -Unfortunately, these symbols are not translated back in error messages. -Thus you may see confusing error messages when local symbols are used. -Control characters `\003' (control-C) and `\004' (control-D) are used -for the MMIX-specific local-symbol syntax. +characters are to hide the ordinal number of the symbol. Unfortunately, +these symbols are not translated back in error messages. Thus you may +see confusing error messages when local symbols are used. Control +characters '\003' (control-C) and '\004' (control-D) are used for the +MMIX-specific local-symbol syntax. - The symbol `Main' is handled specially; it is always global. + The symbol 'Main' is handled specially; it is always global. - By defining the symbols `__.MMIX.start..text' and -`__.MMIX.start..data', the address of respectively the `.text' and -`.data' segments of the final program can be defined, though when + By defining the symbols '__.MMIX.start..text' and +'__.MMIX.start..data', the address of respectively the '.text' and +'.data' segments of the final program can be defined, though when linking more than one object file, the code or data in the object file containing the symbol is not guaranteed to be start at that position; just the final executable. *Note MMIX-loc::. @@ -14055,11 +13940,11 @@ File: as.info, Node: MMIX-Regs, Next: MMIX-Pseudos, Prev: MMIX-Symbols, Up: 9.28.3.3 Register names ....................... -Local and global registers are specified as `$0' to `$255'. The -recognized special register names are `rJ', `rA', `rB', `rC', `rD', -`rE', `rF', `rG', `rH', `rI', `rK', `rL', `rM', `rN', `rO', `rP', `rQ', -`rR', `rS', `rT', `rU', `rV', `rW', `rX', `rY', `rZ', `rBB', `rTT', -`rWW', `rXX', `rYY' and `rZZ'. A leading `:' is optional for special +Local and global registers are specified as '$0' to '$255'. The +recognized special register names are 'rJ', 'rA', 'rB', 'rC', 'rD', +'rE', 'rF', 'rG', 'rH', 'rI', 'rK', 'rL', 'rM', 'rN', 'rO', 'rP', 'rQ', +'rR', 'rS', 'rT', 'rU', 'rV', 'rW', 'rX', 'rY', 'rZ', 'rBB', 'rTT', +'rWW', 'rXX', 'rYY' and 'rZZ'. A leading ':' is optional for special register names. Local and global symbols can be equated to register names and used in @@ -14068,9 +13953,9 @@ place of ordinary registers. Similarly for special registers, local and global symbols can be used. Also, symbols equated from numbers and constant expressions are allowed in place of a special register, except when either of the -options `--no-predefined-syms' and `--fixed-special-register-names' are +options '--no-predefined-syms' and '--fixed-special-register-names' are specified. Then only the special register names above are allowed for -the instructions having a special register operand; `GET' and `PUT'. +the instructions having a special register operand; 'GET' and 'PUT'. File: as.info, Node: MMIX-Pseudos, Prev: MMIX-Regs, Up: MMIX-Syntax @@ -14078,12 +13963,13 @@ File: as.info, Node: MMIX-Pseudos, Prev: MMIX-Regs, Up: MMIX-Syntax 9.28.3.4 Assembler Directives ............................. -`LOC' - The `LOC' directive sets the current location to the value of the - operand field, which may include changing sections. If the - operand is a constant, the section is set to either `.data' if the - value is `0x2000000000000000' or larger, else it is set to `.text'. - Within a section, the current location may only be changed to +'LOC' + + The 'LOC' directive sets the current location to the value of the + operand field, which may include changing sections. If the operand + is a constant, the section is set to either '.data' if the value is + '0x2000000000000000' or larger, else it is set to '.text'. Within + a section, the current location may only be changed to monotonically higher addresses. A LOC expression must be a previously defined symbol or a "pure" constant. @@ -14092,14 +13978,15 @@ File: as.info, Node: MMIX-Pseudos, Prev: MMIX-Regs, Up: MMIX-Syntax prev LOC @+8 When a LOC has a constant as its operand, a symbol - `__.MMIX.start..text' or `__.MMIX.start..data' is defined - depending on the address as mentioned above. Each such symbol is - interpreted as special by the linker, locating the section at that - address. Note that if multiple files are linked, the first object - file with that section will be mapped to that address (not - necessarily the file with the LOC definition). - -`LOCAL' + '__.MMIX.start..text' or '__.MMIX.start..data' is defined depending + on the address as mentioned above. Each such symbol is interpreted + as special by the linker, locating the section at that address. + Note that if multiple files are linked, the first object file with + that section will be mapped to that address (not necessarily the + file with the LOC definition). + +'LOCAL' + Example: LOCAL external_symbol LOCAL 42 @@ -14110,18 +13997,20 @@ File: as.info, Node: MMIX-Pseudos, Prev: MMIX-Regs, Up: MMIX-Syntax an expression that at link-time resolves to a register symbol or a number. A number is treated as the register having that number. There is one restriction on the use of this directive: the - pseudo-directive must be placed in a section with contents, code - or data. + pseudo-directive must be placed in a section with contents, code or + data. -`IS' - The `IS' directive: +'IS' + + The 'IS' directive: asymbol IS an_expression - sets the symbol `asymbol' to `an_expression'. A symbol may not be + sets the symbol 'asymbol' to 'an_expression'. A symbol may not be set more than once using this directive. Local labels may be set using this directive, for example: 5H IS @+4 -`GREG' +'GREG' + This directive reserves a global register, gives it an initial value and optionally gives it a symbolic name. Some examples: @@ -14132,26 +14021,26 @@ File: as.info, Node: MMIX-Pseudos, Prev: MMIX-Regs, Up: MMIX-Syntax The symbolic register name can be used in place of a (non-special) register. If a value isn't provided, it defaults to zero. Unless - the option `--no-merge-gregs' is specified, non-zero registers - allocated with this directive may be eliminated by `as'; another + the option '--no-merge-gregs' is specified, non-zero registers + allocated with this directive may be eliminated by 'as'; another register with the same value used in its place. Any of the - instructions `CSWAP', `GO', `LDA', `LDBU', `LDB', `LDHT', `LDOU', - `LDO', `LDSF', `LDTU', `LDT', `LDUNC', `LDVTS', `LDWU', `LDW', - `PREGO', `PRELD', `PREST', `PUSHGO', `STBU', `STB', `STCO', `STHT', - `STOU', `STSF', `STTU', `STT', `STUNC', `SYNCD', `SYNCID', can - have a value nearby an initial value in place of its second and - third operands. Here, "nearby" is defined as within the range - 0...255 from the initial value of such an allocated register. + instructions 'CSWAP', 'GO', 'LDA', 'LDBU', 'LDB', 'LDHT', 'LDOU', + 'LDO', 'LDSF', 'LDTU', 'LDT', 'LDUNC', 'LDVTS', 'LDWU', 'LDW', + 'PREGO', 'PRELD', 'PREST', 'PUSHGO', 'STBU', 'STB', 'STCO', 'STHT', + 'STOU', 'STSF', 'STTU', 'STT', 'STUNC', 'SYNCD', 'SYNCID', can have + a value nearby an initial value in place of its second and third + operands. Here, "nearby" is defined as within the range 0...255 + from the initial value of such an allocated register. buffer1 BYTE 0,0,0,0,0 buffer2 BYTE 0,0,0,0,0 ... GREG buffer1 LDOU $42,buffer2 - In the example above, the `Y' field of the `LDOUI' instruction + In the example above, the 'Y' field of the 'LDOUI' instruction (LDOU with a constant Z) will be replaced with the global register - allocated for `buffer1', and the `Z' field will have the value 5, - the offset from `buffer1' to `buffer2'. The result is equivalent + allocated for 'buffer1', and the 'Z' field will have the value 5, + the offset from 'buffer1' to 'buffer2'. The result is equivalent to this code: buffer1 BYTE 0,0,0,0,0 buffer2 BYTE 0,0,0,0,0 @@ -14163,72 +14052,75 @@ File: as.info, Node: MMIX-Pseudos, Prev: MMIX-Regs, Up: MMIX-Syntax order higher-to-lower within a file. Other than that, the exact order of register allocation and elimination is undefined. For example, the order is undefined when more than one file with such - directives are linked together. With the options `-x' and - `--linker-allocated-gregs', `GREG' directives for two-operand - cases like the one mentioned above can be omitted. Sufficient - global registers will then be allocated by the linker. - -`BYTE' - The `BYTE' directive takes a series of operands separated by a - comma. If an operand is a string (*note Strings::), each - character of that string is emitted as a byte. Other operands - must be constant expressions without forward references, in the - range 0...255. If you need operands having expressions with - forward references, use `.byte' (*note Byte::). An operand can be - omitted, defaulting to a zero value. - -`WYDE' -`TETRA' -`OCTA' - The directives `WYDE', `TETRA' and `OCTA' emit constants of two, + directives are linked together. With the options '-x' and + '--linker-allocated-gregs', 'GREG' directives for two-operand cases + like the one mentioned above can be omitted. Sufficient global + registers will then be allocated by the linker. + +'BYTE' + + The 'BYTE' directive takes a series of operands separated by a + comma. If an operand is a string (*note Strings::), each character + of that string is emitted as a byte. Other operands must be + constant expressions without forward references, in the range + 0...255. If you need operands having expressions with forward + references, use '.byte' (*note Byte::). An operand can be omitted, + defaulting to a zero value. + +'WYDE' +'TETRA' +'OCTA' + + The directives 'WYDE', 'TETRA' and 'OCTA' emit constants of two, four and eight bytes size respectively. Before anything else happens for the directive, the current location is aligned to the respective constant-size boundary. If a label is defined at the beginning of the line, its value will be that after the alignment. - A single operand can be omitted, defaulting to a zero value - emitted for the directive. Operands can be expressed as strings - (*note Strings::), in which case each character in the string is - emitted as a separate constant of the size indicated by the - directive. + A single operand can be omitted, defaulting to a zero value emitted + for the directive. Operands can be expressed as strings (*note + Strings::), in which case each character in the string is emitted + as a separate constant of the size indicated by the directive. + +'PREFIX' -`PREFIX' - The `PREFIX' directive sets a symbol name prefix to be prepended to + The 'PREFIX' directive sets a symbol name prefix to be prepended to all symbols (except local symbols, *note MMIX-Symbols::), that are - not prefixed with `:', until the next `PREFIX' directive. Such + not prefixed with ':', until the next 'PREFIX' directive. Such prefixes accumulate. For example, PREFIX a PREFIX b c IS 0 - defines a symbol `abc' with the value 0. + defines a symbol 'abc' with the value 0. -`BSPEC' -`ESPEC' - A pair of `BSPEC' and `ESPEC' directives delimit a section of +'BSPEC' +'ESPEC' + + A pair of 'BSPEC' and 'ESPEC' directives delimit a section of special contents (without specified semantics). Example: BSPEC 42 TETRA 1,2,3 ESPEC - The single operand to `BSPEC' must be number in the range 0...255. - The `BSPEC' number 80 is used by the GNU binutils implementation. + The single operand to 'BSPEC' must be number in the range 0...255. + The 'BSPEC' number 80 is used by the GNU binutils implementation. File: as.info, Node: MMIX-mmixal, Prev: MMIX-Syntax, Up: MMIX-Dependent -9.28.4 Differences to `mmixal' +9.28.4 Differences to 'mmixal' ------------------------------ -The binutils `as' and `ld' combination has a few differences in -function compared to `mmixal' (*note mmixsite::). +The binutils 'as' and 'ld' combination has a few differences in function +compared to 'mmixal' (*note mmixsite::). The replacement of a symbol with a GREG-allocated register (*note -GREG-base::) is not handled the exactly same way in `as' as in -`mmixal'. This is apparent in the `mmixal' example file `inout.mms', -where different registers with different offsets, eventually yielding -the same address, are used in the first instruction. This type of -difference should however not affect the function of any program unless -it has specific assumptions about the allocated register number. - - Line numbers (in the `mmo' object format) are currently not +GREG-base::) is not handled the exactly same way in 'as' as in 'mmixal'. +This is apparent in the 'mmixal' example file 'inout.mms', where +different registers with different offsets, eventually yielding the same +address, are used in the first instruction. This type of difference +should however not affect the function of any program unless it has +specific assumptions about the allocated register number. + + Line numbers (in the 'mmo' object format) are currently not supported. Expression operator precedence is not that of mmixal: operator @@ -14236,16 +14128,16 @@ precedence is that of the C programming language. It's recommended to use parentheses to explicitly specify wanted operator precedence whenever more than one type of operators are used. - The serialize unary operator `&', the fractional division operator -`//', the logical not operator `!' and the modulus operator `%' are not + The serialize unary operator '&', the fractional division operator +'//', the logical not operator '!' and the modulus operator '%' are not available. Symbols are not global by default, unless the option -`--globalize-symbols' is passed. Use the `.global' directive to +'--globalize-symbols' is passed. Use the '.global' directive to globalize symbols (*note Global::). - Operand syntax is a bit stricter with `as' than `mmixal'. For -example, you can't say `addu 1,2,3', instead you must write `addu + Operand syntax is a bit stricter with 'as' than 'mmixal'. For +example, you can't say 'addu 1,2,3', instead you must write 'addu $1,$2,3'. You can't LOC to a lower address than those already visited (i.e., @@ -14259,9 +14151,9 @@ symbol.) Some mapping of constant expressions to sections in LOC expressions is attempted, but that functionality is easily confused and should be -avoided unless compatibility with `mmixal' is required. A LOC -expression to `0x2000000000000000' or higher, maps to the `.data' -section and lower addresses map to the `.text' section (*note +avoided unless compatibility with 'mmixal' is required. A LOC +expression to '0x2000000000000000' or higher, maps to the '.data' +section and lower addresses map to the '.text' section (*note MMIX-loc::). The code and data areas are each contiguous. Sparse programs with @@ -14270,38 +14162,36 @@ contiguous program with zeros filled in the gaps between the LOC directives. If you need sparse programs, you might try and get the wanted effect with a linker script and splitting up the code parts into sections (*note Section::). Assembly code for this, to be compatible -with `mmixal', would look something like: +with 'mmixal', would look something like: .if 0 LOC away_expression .else .section away,"ax" .fi - `as' will not execute the LOC directive and `mmixal' ignores the -lines with `.'. This construct can be used generally to help + 'as' will not execute the LOC directive and 'mmixal' ignores the +lines with '.'. This construct can be used generally to help compatibility. Symbols can't be defined twice-not even to the same value. Instruction mnemonics are recognized case-insensitive, though the -`IS' and `GREG' pseudo-operations must be specified in upper-case +'IS' and 'GREG' pseudo-operations must be specified in upper-case characters. There's no unicode support. - The following is a list of programs in `mmix.tar.gz', available at -`http://www-cs-faculty.stanford.edu/~knuth/mmix-news.html', last -checked with the version dated 2001-08-25 (md5sum -c393470cfc86fac040487d22d2bf0172) that assemble with `mmixal' but do -not assemble with `as': + The following is a list of programs in 'mmix.tar.gz', available at +<http://www-cs-faculty.stanford.edu/~knuth/mmix-news.html>, last checked +with the version dated 2001-08-25 (md5sum +c393470cfc86fac040487d22d2bf0172) that assemble with 'mmixal' but do not +assemble with 'as': -`silly.mms' +'silly.mms' LOC to a previous address. - -`sim.mms' - Redefines symbol `Done'. - -`test.mms' - Uses the serial operator `&'. +'sim.mms' + Redefines symbol 'Done'. +'test.mms' + Uses the serial operator '&'. File: as.info, Node: MSP430-Dependent, Next: NiosII-Dependent, Prev: MMIX-Dependent, Up: Machine Dependencies @@ -14324,15 +14214,38 @@ File: as.info, Node: MSP430 Options, Next: MSP430 Syntax, Up: MSP430-Dependen 9.29.1 Options -------------- -`-m' - select the mpu arch. Currently has no effect. +'-mmcu' + selects the mpu arch. If the architecture is 430Xv2 then this also + enables NOP generation unless the '-mN' is also specified. -`-mP' +'-mcpu' + selects the cpu architecture. If the architecture is 430Xv2 then + this also enables NOP generation unless the '-mN' is also + specified. + +'-mP' enables polymorph instructions handler. -`-mQ' - enables relaxation at assembly time. DANGEROUS! +'-mQ' + enables relaxation at assembly time. DANGEROUS! + +'-ml' + indicates that the input uses the large code model. +'-mN' + disables the generation of a NOP instruction following any + instruction that might change the interrupts enabled/disabled + state. For the 430Xv2 architecture the instructions: 'EINT', + 'DINT', 'BIC #8, SR', 'BIS #8, SR' and 'MOV.W <>, SR' must be + followed by a NOP instruction in order to ensure the correct + processing of interrupts. By default generation of the NOP + instruction happens automatically, but this command line option + disables this behaviour. It is then up to the programmer to ensure + that interrupts are enabled and disabled correctly. + +'-md' + mark the object file as one that requires data to copied from ROM + to RAM at execution startup. Disabled by default. File: as.info, Node: MSP430 Syntax, Next: MSP430 Floating Point, Prev: MSP430 Options, Up: MSP430-Dependent @@ -14354,24 +14267,23 @@ File: as.info, Node: MSP430-Macros, Next: MSP430-Chars, Up: MSP430 Syntax ............... The macro syntax used on the MSP 430 is like that described in the MSP -430 Family Assembler Specification. Normal `as' macros should still +430 Family Assembler Specification. Normal 'as' macros should still work. Additional built-in macros are: -`llo(exp)' +'llo(exp)' Extracts least significant word from 32-bit expression 'exp'. -`lhi(exp)' +'lhi(exp)' Extracts most significant word from 32-bit expression 'exp'. -`hlo(exp)' +'hlo(exp)' Extracts 3rd word from 64-bit expression 'exp'. -`hhi(exp)' +'hhi(exp)' Extracts 4rd word from 64-bit expression 'exp'. - They normally being used as an immediate source operand. mov #llo(1), r10 ; == mov #1, r10 mov #lhi(1), r10 ; == mov #0, r10 @@ -14382,18 +14294,18 @@ File: as.info, Node: MSP430-Chars, Next: MSP430-Regs, Prev: MSP430-Macros, U 9.29.2.2 Special Characters ........................... -A semicolon (`;') appearing anywhere on a line starts a comment that +A semicolon (';') appearing anywhere on a line starts a comment that extends to the end of that line. - If a `#' appears as the first character of a line then the whole -line is treated as a comment, but it can also be a logical line number + If a '#' appears as the first character of a line then the whole line +is treated as a comment, but it can also be a logical line number directive (*note Comments::) or a preprocessor control command (*note Preprocessing::). Multiple statements can appear on the same line provided that they -are separated by the `{' character. +are separated by the '{' character. - The character `$' in jump instructions indicates current location and + The character '$' in jump instructions indicates current location and implemented only for TI syntax compatibility. @@ -14403,12 +14315,12 @@ File: as.info, Node: MSP430-Regs, Next: MSP430-Ext, Prev: MSP430-Chars, Up: ....................... General-purpose registers are represented by predefined symbols of the -form `rN' (for global registers), where N represents a number between -`0' and `15'. The leading letters may be in either upper or lower -case; for example, `r13' and `R7' are both valid register names. +form 'rN' (for global registers), where N represents a number between +'0' and '15'. The leading letters may be in either upper or lower case; +for example, 'r13' and 'R7' are both valid register names. - Register names `PC', `SP' and `SR' cannot be used as register names -and will be treated as variables. Use `r0', `r1', and `r2' instead. + Register names 'PC', 'SP' and 'SR' cannot be used as register names +and will be treated as variables. Use 'r0', 'r1', and 'r2' instead. File: as.info, Node: MSP430-Ext, Prev: MSP430-Regs, Up: MSP430 Syntax @@ -14416,65 +14328,64 @@ File: as.info, Node: MSP430-Ext, Prev: MSP430-Regs, Up: MSP430 Syntax 9.29.2.4 Assembler Extensions ............................. -`@rN' - As destination operand being treated as `0(rn)' +'@rN' + As destination operand being treated as '0(rn)' -`0(rN)' - As source operand being treated as `@rn' +'0(rN)' + As source operand being treated as '@rn' -`jCOND +N' +'jCOND +N' Skips next N bytes followed by jump instruction and equivalent to - `jCOND $+N+2' - + 'jCOND $+N+2' Also, there are some instructions, which cannot be found in other assemblers. These are branch instructions, which has different opcodes upon jump distance. They all got PC relative addressing mode. -`beq label' - A polymorph instruction which is `jeq label' in case if jump - distance within allowed range for cpu's jump instruction. If not, +'beq label' + A polymorph instruction which is 'jeq label' in case if jump + distance within allowed range for cpu's jump instruction. If not, this unrolls into a sequence of jne $+6 br label -`bne label' - A polymorph instruction which is `jne label' or `jeq +4; br label' +'bne label' + A polymorph instruction which is 'jne label' or 'jeq +4; br label' -`blt label' - A polymorph instruction which is `jl label' or `jge +4; br label' +'blt label' + A polymorph instruction which is 'jl label' or 'jge +4; br label' -`bltn label' - A polymorph instruction which is `jn label' or `jn +2; jmp +4; br +'bltn label' + A polymorph instruction which is 'jn label' or 'jn +2; jmp +4; br label' -`bltu label' - A polymorph instruction which is `jlo label' or `jhs +2; br label' +'bltu label' + A polymorph instruction which is 'jlo label' or 'jhs +2; br label' -`bge label' - A polymorph instruction which is `jge label' or `jl +4; br label' +'bge label' + A polymorph instruction which is 'jge label' or 'jl +4; br label' -`bgeu label' - A polymorph instruction which is `jhs label' or `jlo +4; br label' +'bgeu label' + A polymorph instruction which is 'jhs label' or 'jlo +4; br label' -`bgt label' - A polymorph instruction which is `jeq +2; jge label' or `jeq +6; - jl +4; br label' +'bgt label' + A polymorph instruction which is 'jeq +2; jge label' or 'jeq +6; jl + +4; br label' -`bgtu label' - A polymorph instruction which is `jeq +2; jhs label' or `jeq +6; +'bgtu label' + A polymorph instruction which is 'jeq +2; jhs label' or 'jeq +6; jlo +4; br label' -`bleu label' - A polymorph instruction which is `jeq label; jlo label' or `jeq - +2; jhs +4; br label' +'bleu label' + A polymorph instruction which is 'jeq label; jlo label' or 'jeq +2; + jhs +4; br label' -`ble label' - A polymorph instruction which is `jeq label; jl label' or `jeq - +2; jge +4; br label' +'ble label' + A polymorph instruction which is 'jeq label; jl label' or 'jeq +2; + jge +4; br label' -`jump label' - A polymorph instruction which is `jmp label' or `br label' +'jump label' + A polymorph instruction which is 'jmp label' or 'br label' File: as.info, Node: MSP430 Floating Point, Next: MSP430 Directives, Prev: MSP430 Syntax, Up: MSP430-Dependent @@ -14490,37 +14401,40 @@ File: as.info, Node: MSP430 Directives, Next: MSP430 Opcodes, Prev: MSP430 Fl 9.29.4 MSP 430 Machine Directives --------------------------------- -`.file' +'.file' This directive is ignored; it is accepted for compatibility with other MSP 430 assemblers. - _Warning:_ in other versions of the GNU assembler, `.file' is - used for the directive called `.app-file' in the MSP 430 + _Warning:_ in other versions of the GNU assembler, '.file' is + used for the directive called '.app-file' in the MSP 430 support. -`.line' +'.line' This directive is ignored; it is accepted for compatibility with other MSP 430 assemblers. -`.arch' - Currently this directive is ignored; it is accepted for - compatibility with other MSP 430 assemblers. +'.arch' + Sets the target microcontroller in the same way as the '-mmcu' + command line option. + +'.cpu' + Sets the target architecture in the same way as the '-mcpu' command + line option. -`.profiler' +'.profiler' This directive instructs assembler to add new profile entry to the object file. - File: as.info, Node: MSP430 Opcodes, Next: MSP430 Profiling Capability, Prev: MSP430 Directives, Up: MSP430-Dependent 9.29.5 Opcodes -------------- -`as' implements all the standard MSP 430 opcodes. No additional +'as' implements all the standard MSP 430 opcodes. No additional pseudo-instructions are needed on this family. - For information on the 430 machine instruction set, see `MSP430 + For information on the 430 machine instruction set, see 'MSP430 User's Manual, document slau049d', Texas Instrument, Inc. @@ -14534,75 +14448,58 @@ target. Even more - jtag hardware facility does not perform any profiling functions. However we've got gdb's built-in simulator where we can do anything. - We define new section `.profiler' which holds all profiling -information. We define new pseudo operation `.profiler' which will -instruct assembler to add new profile entry to the object file. Profile + We define new section '.profiler' which holds all profiling +information. We define new pseudo operation '.profiler' which will +instruct assembler to add new profile entry to the object file. Profile should take place at the present address. Pseudo operation format: - `.profiler flags,function_to_profile [, cycle_corrector, extra]' + '.profiler flags,function_to_profile [, cycle_corrector, extra]' where: - `flags' is a combination of the following characters: + 'flags' is a combination of the following characters: - `s' + 's' function entry - - `x' + 'x' function exit - - `i' + 'i' function is in init section - - `f' + 'f' function is in fini section - - `l' + 'l' library call - - `c' + 'c' libc standard call - - `d' + 'd' stack value demand - - `I' + 'I' interrupt service routine - - `P' + 'P' prologue start - - `p' + 'p' prologue end - - `E' + 'E' epilogue start - - `e' + 'e' epilogue end - - `j' + 'j' long jump / sjlj unwind - - `a' + 'a' an arbitrary code fragment - - `t' + 't' extra parameter saved (a constant value like frame size) -`function_to_profile' +'function_to_profile' a function address - -`cycle_corrector' +'cycle_corrector' a value which should be added to the cycle counter, zero if omitted. - -`extra' +'extra' any extra parameter, zero if omitted. - For example: .global fxx .type fxx,@function @@ -14648,30 +14545,28 @@ File: as.info, Node: Nios II Options, Next: Nios II Syntax, Up: NiosII-Depend 9.30.1 Options -------------- -`-relax-section' - Replace identified out-of-range branches with PC-relative `jmp' +'-relax-section' + Replace identified out-of-range branches with PC-relative 'jmp' sequences when possible. The generated code sequences are suitable for use in position-independent code, but there is a practical limit on the extended branch range because of the length of the sequences. This option is the default. -`-relax-all' - Replace branch instructions not determinable to be in range and - all call instructions with `jmp' and `callr' sequences - (respectively). This option generates absolute relocations - against the target symbols and is not appropriate for - position-independent code. +'-relax-all' + Replace branch instructions not determinable to be in range and all + call instructions with 'jmp' and 'callr' sequences (respectively). + This option generates absolute relocations against the target + symbols and is not appropriate for position-independent code. -`-no-relax' +'-no-relax' Do not replace any branches or calls. -`-EB' +'-EB' Generate big-endian output. -`-EL' +'-EL' Generate little-endian output. This is the default. - File: as.info, Node: Nios II Syntax, Next: Nios II Relocations, Prev: Nios II Options, Up: NiosII-Dependent @@ -14688,7 +14583,7 @@ File: as.info, Node: Nios II Chars, Up: Nios II Syntax 9.30.2.1 Special Characters ........................... -`#' is the line comment character. `;' is the line separator character. +'#' is the line comment character. ';' is the line separator character. File: as.info, Node: Nios II Relocations, Next: Nios II Directives, Prev: Nios II Syntax, Up: NiosII-Dependent @@ -14696,30 +14591,30 @@ File: as.info, Node: Nios II Relocations, Next: Nios II Directives, Prev: Nio 9.30.3 Nios II Machine Relocations ---------------------------------- -`%hiadj(EXPRESSION)' - Extract the upper 16 bits of EXPRESSION and add one if the 15th - bit is set. +'%hiadj(EXPRESSION)' + Extract the upper 16 bits of EXPRESSION and add one if the 15th bit + is set. - The value of `%hiadj(EXPRESSION)' is: + The value of '%hiadj(EXPRESSION)' is: ((EXPRESSION >> 16) & 0xffff) + ((EXPRESSION >> 15) & 0x01) - The `%hiadj' relocation is intended to be used with the `addi', - `ld' or `st' instructions along with a `%lo', in order to load a + The '%hiadj' relocation is intended to be used with the 'addi', + 'ld' or 'st' instructions along with a '%lo', in order to load a 32-bit constant. movhi r2, %hiadj(symbol) addi r2, r2, %lo(symbol) -`%hi(EXPRESSION)' +'%hi(EXPRESSION)' Extract the upper 16 bits of EXPRESSION. -`%lo(EXPRESSION)' +'%lo(EXPRESSION)' Extract the lower 16 bits of EXPRESSION. -`%gprel(EXPRESSION)' - Subtract the value of the symbol `_gp' from EXPRESSION. +'%gprel(EXPRESSION)' + Subtract the value of the symbol '_gp' from EXPRESSION. - The intention of the `%gprel' relocation is to have a fast small + The intention of the '%gprel' relocation is to have a fast small area of memory which only takes a 16-bit immediate to access. .section .sdata @@ -14728,18 +14623,19 @@ File: as.info, Node: Nios II Relocations, Next: Nios II Directives, Prev: Nio .section .text ldw r4, %gprel(fastint)(gp) -`%call(EXPRESSION)' -`%got(EXPRESSION)' -`%gotoff(EXPRESSION)' -`%gotoff_lo(EXPRESSION)' -`%gotoff_hiadj(EXPRESSION)' -`%tls_gd(EXPRESSION)' -`%tls_ie(EXPRESSION)' -`%tls_le(EXPRESSION)' -`%tls_ldm(EXPRESSION)' -`%tls_ldo(EXPRESSION)' +'%call(EXPRESSION)' +'%got(EXPRESSION)' +'%gotoff(EXPRESSION)' +'%gotoff_lo(EXPRESSION)' +'%gotoff_hiadj(EXPRESSION)' +'%tls_gd(EXPRESSION)' +'%tls_ie(EXPRESSION)' +'%tls_le(EXPRESSION)' +'%tls_ldm(EXPRESSION)' +'%tls_ldo(EXPRESSION)' + These relocations support the ABI for Linux Systems documented in - the `Nios II Processor Reference Handbook'. + the 'Nios II Processor Reference Handbook'. File: as.info, Node: Nios II Directives, Next: Nios II Opcodes, Prev: Nios II Relocations, Up: NiosII-Dependent @@ -14747,60 +14643,59 @@ File: as.info, Node: Nios II Directives, Next: Nios II Opcodes, Prev: Nios II 9.30.4 Nios II Machine Directives --------------------------------- -`.align EXPRESSION [, EXPRESSION]' - This is the generic `.align' directive, however this aligns to a +'.align EXPRESSION [, EXPRESSION]' + This is the generic '.align' directive, however this aligns to a power of two. -`.half EXPRESSION' +'.half EXPRESSION' Create an aligned constant 2 bytes in size. -`.word EXPRESSION' +'.word EXPRESSION' Create an aligned constant 4 bytes in size. -`.dword EXPRESSION' +'.dword EXPRESSION' Create an aligned constant 8 bytes in size. -`.2byte EXPRESSION' +'.2byte EXPRESSION' Create an unaligned constant 2 bytes in size. -`.4byte EXPRESSION' +'.4byte EXPRESSION' Create an unaligned constant 4 bytes in size. -`.8byte EXPRESSION' +'.8byte EXPRESSION' Create an unaligned constant 8 bytes in size. -`.16byte EXPRESSION' +'.16byte EXPRESSION' Create an unaligned constant 16 bytes in size. -`.set noat' - Allows assembly code to use `at' register without warning. Macro +'.set noat' + Allows assembly code to use 'at' register without warning. Macro or relaxation expansions generate warnings. -`.set at' - Assembly code using `at' register generates warnings, and macro +'.set at' + Assembly code using 'at' register generates warnings, and macro expansion and relaxation are enabled. -`.set nobreak' - Allows assembly code to use `ba' and `bt' registers without +'.set nobreak' + Allows assembly code to use 'ba' and 'bt' registers without warning. -`.set break' - Turns warnings back on for using `ba' and `bt' registers. +'.set break' + Turns warnings back on for using 'ba' and 'bt' registers. -`.set norelax' +'.set norelax' Do not replace any branches or calls. -`.set relaxsection' - Replace identified out-of-range branches with `jmp' sequences +'.set relaxsection' + Replace identified out-of-range branches with 'jmp' sequences (default). -`.set relaxsection' - Replace all branch and call instructions with `jmp' and `callr' +'.set relaxsection' + Replace all branch and call instructions with 'jmp' and 'callr' sequences. -`.set ...' - All other `.set' are the normal use. - +'.set ...' + All other '.set' are the normal use. File: as.info, Node: Nios II Opcodes, Prev: Nios II Directives, Up: NiosII-Dependent @@ -14808,12 +14703,12 @@ File: as.info, Node: Nios II Opcodes, Prev: Nios II Directives, Up: NiosII-De 9.30.5 Opcodes -------------- -`as' implements all the standard Nios II opcodes documented in the -`Nios II Processor Reference Handbook', including the assembler +'as' implements all the standard Nios II opcodes documented in the 'Nios +II Processor Reference Handbook', including the assembler pseudo-instructions. -File: as.info, Node: NS32K-Dependent, Next: SH-Dependent, Prev: NiosII-Dependent, Up: Machine Dependencies +File: as.info, Node: NS32K-Dependent, Next: PDP-11-Dependent, Prev: NiosII-Dependent, Up: Machine Dependencies 9.31 NS32K Dependent Features ============================= @@ -14838,23 +14733,23 @@ File: as.info, Node: NS32K-Chars, Up: NS32K Syntax 9.31.1.1 Special Characters ........................... -The presence of a `#' appearing anywhere on a line indicates the start +The presence of a '#' appearing anywhere on a line indicates the start of a comment that extends to the end of that line. - If a `#' appears as the first character of a line then the whole -line is treated as a comment, but in this case the line can also be a -logical line number directive (*note Comments::) or a preprocessor -control command (*note Preprocessing::). + If a '#' appears as the first character of a line then the whole line +is treated as a comment, but in this case the line can also be a logical +line number directive (*note Comments::) or a preprocessor control +command (*note Preprocessing::). If Sequent compatibility has been configured into the assembler then -the `|' character appearing as the first character on a line will also +the '|' character appearing as the first character on a line will also indicate the start of a line comment. - The `;' character can be used to separate statements on the same + The ';' character can be used to separate statements on the same line. -File: as.info, Node: PDP-11-Dependent, Next: PJ-Dependent, Prev: SH64-Dependent, Up: Machine Dependencies +File: as.info, Node: PDP-11-Dependent, Next: PJ-Dependent, Prev: NS32K-Dependent, Up: Machine Dependencies 9.32 PDP-11 Dependent Features ============================== @@ -14873,12 +14768,12 @@ File: as.info, Node: PDP-11-Options, Next: PDP-11-Pseudos, Up: PDP-11-Depende 9.32.1 Options -------------- -The PDP-11 version of `as' has a rich set of machine dependent options. +The PDP-11 version of 'as' has a rich set of machine dependent options. 9.32.1.1 Code Generation Options ................................ -`-mpic | -mno-pic' +'-mpic | -mno-pic' Generate position-independent (or position-dependent) code. The default is to generate position-independent code. @@ -14888,70 +14783,70 @@ The PDP-11 version of `as' has a rich set of machine dependent options. These options enables or disables the use of extensions over the base line instruction set as introduced by the first PDP-11 CPU: the KA11. -Most options come in two variants: a `-m'EXTENSION that enables -EXTENSION, and a `-mno-'EXTENSION that disables EXTENSION. +Most options come in two variants: a '-m'EXTENSION that enables +EXTENSION, and a '-mno-'EXTENSION that disables EXTENSION. The default is to enable all extensions. -`-mall | -mall-extensions' +'-mall | -mall-extensions' Enable all instruction set extensions. -`-mno-extensions' +'-mno-extensions' Disable all instruction set extensions. -`-mcis | -mno-cis' +'-mcis | -mno-cis' Enable (or disable) the use of the commercial instruction set, - which consists of these instructions: `ADDNI', `ADDN', `ADDPI', - `ADDP', `ASHNI', `ASHN', `ASHPI', `ASHP', `CMPCI', `CMPC', - `CMPNI', `CMPN', `CMPPI', `CMPP', `CVTLNI', `CVTLN', `CVTLPI', - `CVTLP', `CVTNLI', `CVTNL', `CVTNPI', `CVTNP', `CVTPLI', `CVTPL', - `CVTPNI', `CVTPN', `DIVPI', `DIVP', `L2DR', `L3DR', `LOCCI', - `LOCC', `MATCI', `MATC', `MOVCI', `MOVC', `MOVRCI', `MOVRC', - `MOVTCI', `MOVTC', `MULPI', `MULP', `SCANCI', `SCANC', `SKPCI', - `SKPC', `SPANCI', `SPANC', `SUBNI', `SUBN', `SUBPI', and `SUBP'. - -`-mcsm | -mno-csm' - Enable (or disable) the use of the `CSM' instruction. - -`-meis | -mno-eis' + which consists of these instructions: 'ADDNI', 'ADDN', 'ADDPI', + 'ADDP', 'ASHNI', 'ASHN', 'ASHPI', 'ASHP', 'CMPCI', 'CMPC', 'CMPNI', + 'CMPN', 'CMPPI', 'CMPP', 'CVTLNI', 'CVTLN', 'CVTLPI', 'CVTLP', + 'CVTNLI', 'CVTNL', 'CVTNPI', 'CVTNP', 'CVTPLI', 'CVTPL', 'CVTPNI', + 'CVTPN', 'DIVPI', 'DIVP', 'L2DR', 'L3DR', 'LOCCI', 'LOCC', 'MATCI', + 'MATC', 'MOVCI', 'MOVC', 'MOVRCI', 'MOVRC', 'MOVTCI', 'MOVTC', + 'MULPI', 'MULP', 'SCANCI', 'SCANC', 'SKPCI', 'SKPC', 'SPANCI', + 'SPANC', 'SUBNI', 'SUBN', 'SUBPI', and 'SUBP'. + +'-mcsm | -mno-csm' + Enable (or disable) the use of the 'CSM' instruction. + +'-meis | -mno-eis' Enable (or disable) the use of the extended instruction set, which - consists of these instructions: `ASHC', `ASH', `DIV', `MARK', - `MUL', `RTT', `SOB' `SXT', and `XOR'. + consists of these instructions: 'ASHC', 'ASH', 'DIV', 'MARK', + 'MUL', 'RTT', 'SOB' 'SXT', and 'XOR'. -`-mfis | -mkev11' -`-mno-fis | -mno-kev11' +'-mfis | -mkev11' +'-mno-fis | -mno-kev11' Enable (or disable) the use of the KEV11 floating-point - instructions: `FADD', `FDIV', `FMUL', and `FSUB'. + instructions: 'FADD', 'FDIV', 'FMUL', and 'FSUB'. -`-mfpp | -mfpu | -mfp-11' -`-mno-fpp | -mno-fpu | -mno-fp-11' +'-mfpp | -mfpu | -mfp-11' +'-mno-fpp | -mno-fpu | -mno-fp-11' Enable (or disable) the use of FP-11 floating-point instructions: - `ABSF', `ADDF', `CFCC', `CLRF', `CMPF', `DIVF', `LDCFF', `LDCIF', - `LDEXP', `LDF', `LDFPS', `MODF', `MULF', `NEGF', `SETD', `SETF', - `SETI', `SETL', `STCFF', `STCFI', `STEXP', `STF', `STFPS', `STST', - `SUBF', and `TSTF'. + 'ABSF', 'ADDF', 'CFCC', 'CLRF', 'CMPF', 'DIVF', 'LDCFF', 'LDCIF', + 'LDEXP', 'LDF', 'LDFPS', 'MODF', 'MULF', 'NEGF', 'SETD', 'SETF', + 'SETI', 'SETL', 'STCFF', 'STCFI', 'STEXP', 'STF', 'STFPS', 'STST', + 'SUBF', and 'TSTF'. -`-mlimited-eis | -mno-limited-eis' +'-mlimited-eis | -mno-limited-eis' Enable (or disable) the use of the limited extended instruction - set: `MARK', `RTT', `SOB', `SXT', and `XOR'. + set: 'MARK', 'RTT', 'SOB', 'SXT', and 'XOR'. The -mno-limited-eis options also implies -mno-eis. -`-mmfpt | -mno-mfpt' - Enable (or disable) the use of the `MFPT' instruction. +'-mmfpt | -mno-mfpt' + Enable (or disable) the use of the 'MFPT' instruction. -`-mmultiproc | -mno-multiproc' +'-mmultiproc | -mno-multiproc' Enable (or disable) the use of multiprocessor instructions: - `TSTSET' and `WRTLCK'. + 'TSTSET' and 'WRTLCK'. -`-mmxps | -mno-mxps' - Enable (or disable) the use of the `MFPS' and `MTPS' instructions. +'-mmxps | -mno-mxps' + Enable (or disable) the use of the 'MFPS' and 'MTPS' instructions. -`-mspl | -mno-spl' - Enable (or disable) the use of the `SPL' instruction. +'-mspl | -mno-spl' + Enable (or disable) the use of the 'SPL' instruction. - Enable (or disable) the use of the microcode instructions: `LDUB', - `MED', and `XFC'. + Enable (or disable) the use of the microcode instructions: 'LDUB', + 'MED', and 'XFC'. 9.32.1.3 CPU Model Options .......................... @@ -14959,47 +14854,47 @@ EXTENSION, and a `-mno-'EXTENSION that disables EXTENSION. These options enable the instruction set extensions supported by a particular CPU, and disables all other extensions. -`-mka11' - KA11 CPU. Base line instruction set only. +'-mka11' + KA11 CPU. Base line instruction set only. -`-mkb11' - KB11 CPU. Enable extended instruction set and `SPL'. +'-mkb11' + KB11 CPU. Enable extended instruction set and 'SPL'. -`-mkd11a' - KD11-A CPU. Enable limited extended instruction set. +'-mkd11a' + KD11-A CPU. Enable limited extended instruction set. -`-mkd11b' - KD11-B CPU. Base line instruction set only. +'-mkd11b' + KD11-B CPU. Base line instruction set only. -`-mkd11d' - KD11-D CPU. Base line instruction set only. +'-mkd11d' + KD11-D CPU. Base line instruction set only. -`-mkd11e' - KD11-E CPU. Enable extended instruction set, `MFPS', and `MTPS'. +'-mkd11e' + KD11-E CPU. Enable extended instruction set, 'MFPS', and 'MTPS'. -`-mkd11f | -mkd11h | -mkd11q' - KD11-F, KD11-H, or KD11-Q CPU. Enable limited extended - instruction set, `MFPS', and `MTPS'. +'-mkd11f | -mkd11h | -mkd11q' + KD11-F, KD11-H, or KD11-Q CPU. Enable limited extended instruction + set, 'MFPS', and 'MTPS'. -`-mkd11k' - KD11-K CPU. Enable extended instruction set, `LDUB', `MED', - `MFPS', `MFPT', `MTPS', and `XFC'. +'-mkd11k' + KD11-K CPU. Enable extended instruction set, 'LDUB', 'MED', 'MFPS', + 'MFPT', 'MTPS', and 'XFC'. -`-mkd11z' - KD11-Z CPU. Enable extended instruction set, `CSM', `MFPS', - `MFPT', `MTPS', and `SPL'. +'-mkd11z' + KD11-Z CPU. Enable extended instruction set, 'CSM', 'MFPS', 'MFPT', + 'MTPS', and 'SPL'. -`-mf11' - F11 CPU. Enable extended instruction set, `MFPS', `MFPT', and - `MTPS'. +'-mf11' + F11 CPU. Enable extended instruction set, 'MFPS', 'MFPT', and + 'MTPS'. -`-mj11' - J11 CPU. Enable extended instruction set, `CSM', `MFPS', `MFPT', - `MTPS', `SPL', `TSTSET', and `WRTLCK'. +'-mj11' + J11 CPU. Enable extended instruction set, 'CSM', 'MFPS', 'MFPT', + 'MTPS', 'SPL', 'TSTSET', and 'WRTLCK'. -`-mt11' - T11 CPU. Enable limited extended instruction set, `MFPS', and - `MTPS'. +'-mt11' + T11 CPU. Enable limited extended instruction set, 'MFPS', and + 'MTPS'. 9.32.1.4 Machine Model Options .............................. @@ -15007,44 +14902,44 @@ particular CPU, and disables all other extensions. These options enable the instruction set extensions supported by a particular machine model, and disables all other extensions. -`-m11/03' - Same as `-mkd11f'. +'-m11/03' + Same as '-mkd11f'. -`-m11/04' - Same as `-mkd11d'. +'-m11/04' + Same as '-mkd11d'. -`-m11/05 | -m11/10' - Same as `-mkd11b'. +'-m11/05 | -m11/10' + Same as '-mkd11b'. -`-m11/15 | -m11/20' - Same as `-mka11'. +'-m11/15 | -m11/20' + Same as '-mka11'. -`-m11/21' - Same as `-mt11'. +'-m11/21' + Same as '-mt11'. -`-m11/23 | -m11/24' - Same as `-mf11'. +'-m11/23 | -m11/24' + Same as '-mf11'. -`-m11/34' - Same as `-mkd11e'. +'-m11/34' + Same as '-mkd11e'. -`-m11/34a' - Ame as `-mkd11e' `-mfpp'. +'-m11/34a' + Ame as '-mkd11e' '-mfpp'. -`-m11/35 | -m11/40' - Same as `-mkd11a'. +'-m11/35 | -m11/40' + Same as '-mkd11a'. -`-m11/44' - Same as `-mkd11z'. +'-m11/44' + Same as '-mkd11z'. -`-m11/45 | -m11/50 | -m11/55 | -m11/70' - Same as `-mkb11'. +'-m11/45 | -m11/50 | -m11/55 | -m11/70' + Same as '-mkb11'. -`-m11/53 | -m11/73 | -m11/83 | -m11/84 | -m11/93 | -m11/94' - Same as `-mj11'. +'-m11/53 | -m11/73 | -m11/83 | -m11/84 | -m11/93 | -m11/94' + Same as '-mj11'. -`-m11/60' - Same as `-mkd11k'. +'-m11/60' + Same as '-mkd11k'. File: as.info, Node: PDP-11-Pseudos, Next: PDP-11-Syntax, Prev: PDP-11-Options, Up: PDP-11-Dependent @@ -15052,13 +14947,13 @@ File: as.info, Node: PDP-11-Pseudos, Next: PDP-11-Syntax, Prev: PDP-11-Option 9.32.2 Assembler Directives --------------------------- -The PDP-11 version of `as' has a few machine dependent assembler +The PDP-11 version of 'as' has a few machine dependent assembler directives. -`.bss' - Switch to the `bss' section. +'.bss' + Switch to the 'bss' section. -`.even' +'.even' Align the location counter to an even number. @@ -15067,20 +14962,20 @@ File: as.info, Node: PDP-11-Syntax, Next: PDP-11-Mnemonics, Prev: PDP-11-Pseu 9.32.3 PDP-11 Assembly Language Syntax -------------------------------------- -`as' supports both DEC syntax and BSD syntax. The only difference is -that in DEC syntax, a `#' character is used to denote an immediate -constants, while in BSD syntax the character for this purpose is `$'. +'as' supports both DEC syntax and BSD syntax. The only difference is +that in DEC syntax, a '#' character is used to denote an immediate +constants, while in BSD syntax the character for this purpose is '$'. - general-purpose registers are named `r0' through `r7'. Mnemonic -alternatives for `r6' and `r7' are `sp' and `pc', respectively. + general-purpose registers are named 'r0' through 'r7'. Mnemonic +alternatives for 'r6' and 'r7' are 'sp' and 'pc', respectively. - Floating-point registers are named `ac0' through `ac3', or -alternatively `fr0' through `fr3'. + Floating-point registers are named 'ac0' through 'ac3', or +alternatively 'fr0' through 'fr3'. - Comments are started with a `#' or a `/' character, and extend to -the end of the line. (FIXME: clash with immediates?) + Comments are started with a '#' or a '/' character, and extend to the +end of the line. (FIXME: clash with immediates?) - Multiple statements on the same line can be separated by the `;' + Multiple statements on the same line can be separated by the ';' character. @@ -15091,20 +14986,20 @@ File: as.info, Node: PDP-11-Mnemonics, Next: PDP-11-Synthetic, Prev: PDP-11-S Some instructions have alternative names. -`BCC' - `BHIS' +'BCC' + 'BHIS' -`BCS' - `BLO' +'BCS' + 'BLO' -`L2DR' - `L2D' +'L2DR' + 'L2D' -`L3DR' - `L3D' +'L3DR' + 'L3D' -`SYS' - `TRAP' +'SYS' + 'TRAP' File: as.info, Node: PDP-11-Synthetic, Prev: PDP-11-Mnemonics, Up: PDP-11-Dependent @@ -15112,7 +15007,7 @@ File: as.info, Node: PDP-11-Synthetic, Prev: PDP-11-Mnemonics, Up: PDP-11-Dep 9.32.5 Synthetic Instructions ----------------------------- -The `JBR' and `J'CC synthetic instructions are not supported yet. +The 'JBR' and 'J'CC synthetic instructions are not supported yet. File: as.info, Node: PJ-Dependent, Next: PPC-Dependent, Prev: PDP-11-Dependent, Up: Machine Dependencies @@ -15131,12 +15026,12 @@ File: as.info, Node: PJ Options, Next: PJ Syntax, Up: PJ-Dependent 9.33.1 Options -------------- -`as' has two additional command-line options for the picoJava +'as' has two additional command-line options for the picoJava architecture. -`-ml' +'-ml' This option selects little endian data output. -`-mb' +'-mb' This option selects big endian data output. @@ -15155,15 +15050,15 @@ File: as.info, Node: PJ-Chars, Up: PJ Syntax 9.33.2.1 Special Characters ........................... -The presence of a `!' or `/' on a line indicates the start of a comment +The presence of a '!' or '/' on a line indicates the start of a comment that extends to the end of the current line. - If a `#' appears as the first character of a line then the whole -line is treated as a comment, but in this case the line could also be a + If a '#' appears as the first character of a line then the whole line +is treated as a comment, but in this case the line could also be a logical line number directive (*note Comments::) or a preprocessor control command (*note Preprocessing::). - The `;' character can be used to separate statements on the same + The ';' character can be used to separate statements on the same line. @@ -15192,148 +15087,147 @@ architecture reference manual. The following table lists all available PowerPC options. -`-a32' +'-a32' Generate ELF32 or XCOFF32. -`-a64' +'-a64' Generate ELF64 or XCOFF64. -`-K PIC' +'-K PIC' Set EF_PPC_RELOCATABLE_LIB in ELF flags. -`-mpwrx | -mpwr2' +'-mpwrx | -mpwr2' Generate code for POWER/2 (RIOS2). -`-mpwr' +'-mpwr' Generate code for POWER (RIOS1) -`-m601' +'-m601' Generate code for PowerPC 601. -`-mppc, -mppc32, -m603, -m604' +'-mppc, -mppc32, -m603, -m604' Generate code for PowerPC 603/604. -`-m403, -m405' +'-m403, -m405' Generate code for PowerPC 403/405. -`-m440' +'-m440' Generate code for PowerPC 440. BookE and some 405 instructions. -`-m464' +'-m464' Generate code for PowerPC 464. -`-m476' +'-m476' Generate code for PowerPC 476. -`-m7400, -m7410, -m7450, -m7455' +'-m7400, -m7410, -m7450, -m7455' Generate code for PowerPC 7400/7410/7450/7455. -`-m750cl' +'-m750cl' Generate code for PowerPC 750CL. -`-mppc64, -m620' +'-mppc64, -m620' Generate code for PowerPC 620/625/630. -`-me500, -me500x2' +'-me500, -me500x2' Generate code for Motorola e500 core complex. -`-me500mc' +'-me500mc' Generate code for Freescale e500mc core complex. -`-me500mc64' +'-me500mc64' Generate code for Freescale e500mc64 core complex. -`-me5500' +'-me5500' Generate code for Freescale e5500 core complex. -`-me6500' +'-me6500' Generate code for Freescale e6500 core complex. -`-mspe' +'-mspe' Generate code for Motorola SPE instructions. -`-mtitan' +'-mtitan' Generate code for AppliedMicro Titan core complex. -`-mppc64bridge' +'-mppc64bridge' Generate code for PowerPC 64, including bridge insns. -`-mbooke' +'-mbooke' Generate code for 32-bit BookE. -`-ma2' +'-ma2' Generate code for A2 architecture. -`-me300' +'-me300' Generate code for PowerPC e300 family. -`-maltivec' +'-maltivec' Generate code for processors with AltiVec instructions. -`-mvle' +'-mvle' Generate code for Freescale PowerPC VLE instructions. -`-mvsx' +'-mvsx' Generate code for processors with Vector-Scalar (VSX) instructions. -`-mhtm' +'-mhtm' Generate code for processors with Hardware Transactional Memory instructions. -`-mpower4, -mpwr4' +'-mpower4, -mpwr4' Generate code for Power4 architecture. -`-mpower5, -mpwr5, -mpwr5x' +'-mpower5, -mpwr5, -mpwr5x' Generate code for Power5 architecture. -`-mpower6, -mpwr6' +'-mpower6, -mpwr6' Generate code for Power6 architecture. -`-mpower7, -mpwr7' +'-mpower7, -mpwr7' Generate code for Power7 architecture. -`-mpower8, -mpwr8' +'-mpower8, -mpwr8' Generate code for Power8 architecture. -`-mcell' - -`-mcell' +'-mcell' +'-mcell' Generate code for Cell Broadband Engine architecture. -`-mcom' +'-mcom' Generate code Power/PowerPC common instructions. -`-many' +'-many' Generate code for any architecture (PWR/PWRX/PPC). -`-mregnames' +'-mregnames' Allow symbolic names for registers. -`-mno-regnames' +'-mno-regnames' Do not allow symbolic names for registers. -`-mrelocatable' +'-mrelocatable' Support for GCC's -mrelocatable option. -`-mrelocatable-lib' +'-mrelocatable-lib' Support for GCC's -mrelocatable-lib option. -`-memb' +'-memb' Set PPC_EMB bit in ELF flags. -`-mlittle, -mlittle-endian, -le' +'-mlittle, -mlittle-endian, -le' Generate code for a little endian machine. -`-mbig, -mbig-endian, -be' +'-mbig, -mbig-endian, -be' Generate code for a big endian machine. -`-msolaris' +'-msolaris' Generate code for Solaris. -`-mno-solaris' +'-mno-solaris' Do not generate code for Solaris. -`-nops=COUNT' +'-nops=COUNT' If an alignment directive inserts more than COUNT nops, put a branch at the beginning to skip execution of the nops. @@ -15343,15 +15237,15 @@ File: as.info, Node: PowerPC-Pseudo, Next: PowerPC-Syntax, Prev: PowerPC-Opts 9.34.2 PowerPC Assembler Directives ----------------------------------- -A number of assembler directives are available for PowerPC. The +A number of assembler directives are available for PowerPC. The following table is far from complete. -`.machine "string"' +'.machine "string"' This directive allows you to change the machine for which code is - generated. `"string"' may be any of the -m cpu selection options - (without the -m) enclosed in double quotes, `"push"', or `"pop"'. - `.machine "push"' saves the currently selected cpu, which may be - restored with `.machine "pop"'. + generated. '"string"' may be any of the -m cpu selection options + (without the -m) enclosed in double quotes, '"push"', or '"pop"'. + '.machine "push"' saves the currently selected cpu, which may be + restored with '.machine "pop"'. File: as.info, Node: PowerPC-Syntax, Prev: PowerPC-Pseudo, Up: PPC-Dependent @@ -15369,19 +15263,19 @@ File: as.info, Node: PowerPC-Chars, Up: PowerPC-Syntax 9.34.3.1 Special Characters ........................... -The presence of a `#' on a line indicates the start of a comment that +The presence of a '#' on a line indicates the start of a comment that extends to the end of the current line. - If a `#' appears as the first character of a line then the whole -line is treated as a comment, but in this case the line could also be a + If a '#' appears as the first character of a line then the whole line +is treated as a comment, but in this case the line could also be a logical line number directive (*note Comments::) or a preprocessor control command (*note Preprocessing::). If the assembler has been configured for the ppc-*-solaris* target -then the `!' character also acts as a line comment character. This can -be disabled via the `-mno-solaris' command line option. +then the '!' character also acts as a line comment character. This can +be disabled via the '-mno-solaris' command line option. - The `;' character can be used to separate statements on the same + The ';' character can be used to separate statements on the same line. @@ -15403,7 +15297,12 @@ File: as.info, Node: RL78-Opts, Next: RL78-Modifiers, Up: RL78-Dependent 9.35.1 RL78 Options ------------------- -The Renesas RL78 port of `as' has no target-specific options. +'relax' + Enable support for link-time relaxation. + +'mg10' + Mark the generated binary as targeting the G10 variant of the RL78 + architecture. File: as.info, Node: RL78-Modifiers, Next: RL78-Directives, Prev: RL78-Opts, Up: RL78-Dependent @@ -15414,26 +15313,28 @@ File: as.info, Node: RL78-Modifiers, Next: RL78-Directives, Prev: RL78-Opts, The RL78 has three modifiers that adjust the relocations used by the linker: -`%lo16()' +'%lo16()' + When loading a 20-bit (or wider) address into registers, this modifier selects the 16 least significant bits. movw ax,#%lo16(_sym) -`%hi16()' +'%hi16()' + When loading a 20-bit (or wider) address into registers, this modifier selects the 16 most significant bits. movw ax,#%hi16(_sym) -`%hi8()' +'%hi8()' + When loading a 20-bit (or wider) address into registers, this - modifier selects the 8 bits that would go into CS or ES (i.e. bits + modifier selects the 8 bits that would go into CS or ES (i.e. bits 23..16). mov es, #%hi8(_sym) - File: as.info, Node: RL78-Directives, Next: RL78-Syntax, Prev: RL78-Modifiers, Up: RL78-Dependent @@ -15442,21 +15343,20 @@ File: as.info, Node: RL78-Directives, Next: RL78-Syntax, Prev: RL78-Modifiers In addition to the common directives, the RL78 adds these: -`.double' +'.double' Output a constant in "double" format, which is a 32-bit floating point value on RL78. -`.bss' +'.bss' Select the BSS section. -`.3byte' +'.3byte' Output a constant value in a three byte format. -`.int' -`.word' +'.int' +'.word' Output a constant value in a four byte format. - File: as.info, Node: RL78-Syntax, Prev: RL78-Directives, Up: RL78-Dependent @@ -15473,15 +15373,15 @@ File: as.info, Node: RL78-Chars, Up: RL78-Syntax 9.35.4.1 Special Characters ........................... -The presence of a `;' appearing anywhere on a line indicates the start +The presence of a ';' appearing anywhere on a line indicates the start of a comment that extends to the end of that line. - If a `#' appears as the first character of a line then the whole -line is treated as a comment, but in this case the line can also be a -logical line number directive (*note Comments::) or a preprocessor -control command (*note Preprocessing::). + If a '#' appears as the first character of a line then the whole line +is treated as a comment, but in this case the line can also be a logical +line number directive (*note Comments::) or a preprocessor control +command (*note Preprocessing::). - The `|' character can be used to separate statements on the same + The '|' character can be used to separate statements on the same line. @@ -15504,75 +15404,80 @@ File: as.info, Node: RX-Opts, Next: RX-Modifiers, Up: RX-Dependent 9.36.1 RX Options ----------------- -The Renesas RX port of `as' has a few target specfic command line +The Renesas RX port of 'as' has a few target specfic command line options: -`-m32bit-doubles' +'-m32bit-doubles' This option controls the ABI and indicates to use a 32-bit float - ABI. It has no effect on the assembled instructions, but it does - influence the behaviour of the `.double' pseudo-op. This is the + ABI. It has no effect on the assembled instructions, but it does + influence the behaviour of the '.double' pseudo-op. This is the default. -`-m64bit-doubles' +'-m64bit-doubles' This option controls the ABI and indicates to use a 64-bit float - ABI. It has no effect on the assembled instructions, but it does - influence the behaviour of the `.double' pseudo-op. + ABI. It has no effect on the assembled instructions, but it does + influence the behaviour of the '.double' pseudo-op. -`-mbig-endian' +'-mbig-endian' This option controls the ABI and indicates to use a big-endian data - ABI. It has no effect on the assembled instructions, but it does - influence the behaviour of the `.short', `.hword', `.int', - `.word', `.long', `.quad' and `.octa' pseudo-ops. + ABI. It has no effect on the assembled instructions, but it does + influence the behaviour of the '.short', '.hword', '.int', '.word', + '.long', '.quad' and '.octa' pseudo-ops. -`-mlittle-endian' +'-mlittle-endian' This option controls the ABI and indicates to use a little-endian - data ABI. It has no effect on the assembled instructions, but it - does influence the behaviour of the `.short', `.hword', `.int', - `.word', `.long', `.quad' and `.octa' pseudo-ops. This is the + data ABI. It has no effect on the assembled instructions, but it + does influence the behaviour of the '.short', '.hword', '.int', + '.word', '.long', '.quad' and '.octa' pseudo-ops. This is the default. -`-muse-conventional-section-names' +'-muse-conventional-section-names' This option controls the default names given to the code (.text), initialised data (.data) and uninitialised data sections (.bss). -`-muse-renesas-section-names' +'-muse-renesas-section-names' This option controls the default names given to the code (.P), initialised data (.D_1) and uninitialised data sections (.B_1). This is the default. -`-msmall-data-limit' +'-msmall-data-limit' This option tells the assembler that the small data limit feature of the RX port of GCC is being used. This results in the assembler - generating an undefined reference to a symbol called `__gp' for - use by the relocations that are needed to support the small data - limit feature. This option is not enabled by default as it would + generating an undefined reference to a symbol called '__gp' for use + by the relocations that are needed to support the small data limit + feature. This option is not enabled by default as it would otherwise pollute the symbol table. -`-mpid' +'-mpid' This option tells the assembler that the position independent data of the RX port of GCC is being used. This results in the assembler - generating an undefined reference to a symbol called `__pid_base', + generating an undefined reference to a symbol called '__pid_base', and also setting the RX_PID flag bit in the e_flags field of the ELF header of the object file. -`-mint-register=NUM' +'-mint-register=NUM' This option tells the assembler how many registers have been - reserved for use by interrupt handlers. This is needed in order - to compute the correct values for the `%gpreg' and `%pidreg' meta + reserved for use by interrupt handlers. This is needed in order to + compute the correct values for the '%gpreg' and '%pidreg' meta registers. -`-mgcc-abi' +'-mgcc-abi' This option tells the assembler that the old GCC ABI is being used by the assembled code. With this version of the ABI function arguments that are passed on the stack are aligned to a 32-bit boundary. -`-mrx-abi' +'-mrx-abi' This option tells the assembler that the official RX ABI is being used by the assembled code. With this version of the ABI function arguments that are passed on the stack are aligned to their natural alignments. This option is the default. +'-mcpu=NAME' + This option tells the assembler the target CPU type. Currently the + 'rx200', 'rx600' and 'rx610' are recognised as valid cpu names. + Attempting to assemble an instruction not supported by the + indicated cpu type will result in an error message being generated. File: as.info, Node: RX-Modifiers, Next: RX-Directives, Prev: RX-Opts, Up: RX-Dependent @@ -15585,10 +15490,10 @@ instruction operands. The general syntax is the following: %gp(symbol) - The modifier returns the offset from the __GP symbol to the -specified symbol as a 16-bit value. The intent is that this offset -should be used in a register+offset move instruction when generating -references to small data. Ie, like this: + The modifier returns the offset from the __GP symbol to the specified +symbol as a 16-bit value. The intent is that this offset should be used +in a register+offset move instruction when generating references to +small data. Ie, like this: mov.W %gp(_foo)[%gpreg], r1 @@ -15596,13 +15501,12 @@ references to small data. Ie, like this: to refer to registers whose values may not be known to the programmer. These meta register names are: -`%gpreg' +'%gpreg' The small data address register. -`%pidreg' +'%pidreg' The PID base address register. - Both registers normally have the value r13, but this can change if some registers have been reserved for use by interrupt handlers or if both the small data limit and position independent data features are @@ -15614,13 +15518,13 @@ File: as.info, Node: RX-Directives, Next: RX-Float, Prev: RX-Modifiers, Up: 9.36.3 Assembler Directives --------------------------- -The RX version of `as' has the following specific assembler directives: +The RX version of 'as' has the following specific assembler directives: -`.3byte' +'.3byte' Inserts a 3-byte value into the output file at the current location. -`.fetchalign' +'.fetchalign' If the next opcode following this directive spans a fetch line boundary (8 byte boundary), the opcode is aligned to that boundary. If the next opcode does not span a fetch line, this directive has @@ -15628,7 +15532,6 @@ The RX version of `as' has the following specific assembler directives: directive and the opcode; those labels are aligned as well. Any inserted bytes due to alignment will form a NOP opcode. - File: as.info, Node: RX-Float, Next: RX-Syntax, Prev: RX-Directives, Up: RX-Dependent @@ -15637,17 +15540,15 @@ File: as.info, Node: RX-Float, Next: RX-Syntax, Prev: RX-Directives, Up: RX- The floating point formats generated by directives are these. -`.float' - `Single' precision (32-bit) floating point constants. - -`.double' - If the `-m64bit-doubles' command line option has been specified - then then `double' directive generates `double' precision (64-bit) - floating point constants, otherwise it generates `single' - precision (32-bit) floating point constants. To force the - generation of 64-bit floating point constants used the `dc.d' - directive instead. +'.float' + 'Single' precision (32-bit) floating point constants. +'.double' + If the '-m64bit-doubles' command line option has been specified + then then 'double' directive generates 'double' precision (64-bit) + floating point constants, otherwise it generates 'single' precision + (32-bit) floating point constants. To force the generation of + 64-bit floating point constants used the 'dc.d' directive instead. File: as.info, Node: RX-Syntax, Prev: RX-Float, Up: RX-Dependent @@ -15665,15 +15566,15 @@ File: as.info, Node: RX-Chars, Up: RX-Syntax 9.36.5.1 Special Characters ........................... -The presence of a `;' appearing anywhere on a line indicates the start +The presence of a ';' appearing anywhere on a line indicates the start of a comment that extends to the end of that line. - If a `#' appears as the first character of a line then the whole -line is treated as a comment, but in this case the line can also be a -logical line number directive (*note Comments::) or a preprocessor -control command (*note Preprocessing::). + If a '#' appears as the first character of a line then the whole line +is treated as a comment, but in this case the line can also be a logical +line number directive (*note Comments::) or a preprocessor control +command (*note Preprocessing::). - The `!' character can be used to separate statements on the same + The '!' character can be used to separate statements on the same line. @@ -15682,10 +15583,10 @@ File: as.info, Node: S/390-Dependent, Next: SCORE-Dependent, Prev: RX-Depende 9.37 IBM S/390 Dependent Features ================================= - The s390 version of `as' supports two architectures modes and seven -chip levels. The architecture modes are the Enterprise System -Architecture (ESA) and the newer z/Architecture mode. The chip levels -are g5, g6, z900, z990, z9-109, z9-ec, z10, z196, and zEC12. +The s390 version of 'as' supports two architectures modes and seven chip +levels. The architecture modes are the Enterprise System Architecture +(ESA) and the newer z/Architecture mode. The chip levels are g5, g6, +z900, z990, z9-109, z9-ec, z10, z196, and zEC12. * Menu: @@ -15703,7 +15604,7 @@ File: as.info, Node: s390 Options, Next: s390 Characters, Up: S/390-Dependent The following table lists all available s390 specific options: -`-m31 | -m64' +'-m31 | -m64' Select 31- or 64-bit ABI implying a word size of 32- or 64-bit. These options are only available with the ELF object file format, @@ -15712,47 +15613,46 @@ The following table lists all available s390 specific options: configure script to enable 64-bit usage and use s390x as target platform). -`-mesa | -mzarch' +'-mesa | -mzarch' Select the architecture mode, either the Enterprise System Architecture (esa) mode or the z/Architecture mode (zarch). The 64-bit instructions are only available with the z/Architecture - mode. The combination of `-m64' and `-mesa' results in a warning + mode. The combination of '-m64' and '-mesa' results in a warning message. -`-march=CPU' - This option specifies the target processor. The following - processor names are recognized: `g5', `g6', `z900', `z990', - `z9-109', `z9-ec', `z10' and `z196'. Assembling an instruction +'-march=CPU' + This option specifies the target processor. The following + processor names are recognized: 'g5', 'g6', 'z900', 'z990', + 'z9-109', 'z9-ec', 'z10' and 'z196'. Assembling an instruction that is not supported on the target processor results in an error - message. Do not specify `g5' or `g6' with `-mzarch'. + message. Do not specify 'g5' or 'g6' with '-mzarch'. -`-mregnames' +'-mregnames' Allow symbolic names for registers. -`-mno-regnames' +'-mno-regnames' Do not allow symbolic names for registers. -`-mwarn-areg-zero' +'-mwarn-areg-zero' Warn whenever the operand for a base or index register has been - specified but evaluates to zero. This can indicate the misuse of + specified but evaluates to zero. This can indicate the misuse of general purpose register 0 as an address register. - File: as.info, Node: s390 Characters, Next: s390 Syntax, Prev: s390 Options, Up: S/390-Dependent 9.37.2 Special Characters ------------------------- -`#' is the line comment character. +'#' is the line comment character. - If a `#' appears as the first character of a line then the whole -line is treated as a comment, but in this case the line could also be a + If a '#' appears as the first character of a line then the whole line +is treated as a comment, but in this case the line could also be a logical line number directive (*note Comments::) or a preprocessor control command (*note Preprocessing::). - The `;' character can be used instead of a newline to separate + The ';' character can be used instead of a newline to separate statements. @@ -15766,7 +15666,7 @@ Systems Architecture/390 Principles of Operation (SA22-7201) and the z/Architecture Principles of Operation (SA22-7832). Each instruction has two major parts, the instruction mnemonic and -the instruction operands. The instruction format varies. +the instruction operands. The instruction format varies. * Menu: @@ -15785,12 +15685,12 @@ File: as.info, Node: s390 Register, Next: s390 Mnemonics, Up: s390 Syntax 9.37.3.1 Register naming ........................ -The `as' recognizes a number of predefined symbols for the various -processor registers. A register specification in one of the instruction -formats is an unsigned integer between 0 and 15. The specific +The 'as' recognizes a number of predefined symbols for the various +processor registers. A register specification in one of the instruction +formats is an unsigned integer between 0 and 15. The specific instruction and the position of the register in the instruction format -denotes the type of the register. The register symbols are prefixed with -`%': +denotes the type of the register. The register symbols are prefixed +with '%': %rN the 16 general purpose registers, 0 <= N <= 15 %fN the 16 floating point registers, 0 <= N <= 15 @@ -15808,32 +15708,32 @@ File: as.info, Node: s390 Mnemonics, Next: s390 Operands, Prev: s390 Register All instructions documented in the Principles of Operation are supported with the mnemonic and order of operands as described. The instruction mnemonic identifies the instruction format (*note s390 Formats::) and -the specific operation code for the instruction. For example, the `lr' -mnemonic denotes the instruction format `RR' with the operation code -`0x18'. +the specific operation code for the instruction. For example, the 'lr' +mnemonic denotes the instruction format 'RR' with the operation code +'0x18'. The definition of the various mnemonics follows a scheme, where the first character usually hint at the type of the instruction: - a add instruction, for example `al' for add logical 32-bit - b branch instruction, for example `bc' for branch on condition - c compare or convert instruction, for example `cr' for compare + a add instruction, for example 'al' for add logical 32-bit + b branch instruction, for example 'bc' for branch on condition + c compare or convert instruction, for example 'cr' for compare register 32-bit - d divide instruction, for example `dlr' devide logical register + d divide instruction, for example 'dlr' devide logical register 64-bit to 32-bit - i insert instruction, for example `ic' insert character - l load instruction, for example `ltr' load and test register - mv move instruction, for example `mvc' move character - m multiply instruction, for example `mh' multiply halfword - n and instruction, for example `ni' and immediate - o or instruction, for example `oc' or character + i insert instruction, for example 'ic' insert character + l load instruction, for example 'ltr' load and test register + mv move instruction, for example 'mvc' move character + m multiply instruction, for example 'mh' multiply halfword + n and instruction, for example 'ni' and immediate + o or instruction, for example 'oc' or character sla, sll shift left single instruction sra, srl shift right single instruction - st store instruction, for example `stm' store multiple - s subtract instruction, for example `slr' subtract + st store instruction, for example 'stm' store multiple + s subtract instruction, for example 'slr' subtract logical 32-bit - t test or translate instruction, of example `tm' test under mask - x exclusive or instruction, for example `xc' exclusive or + t test or translate instruction, of example 'tm' test under mask + x exclusive or instruction, for example 'xc' exclusive or character Certain characters at the end of the mnemonic may describe a property @@ -15850,13 +15750,13 @@ of the instruction: y the instruction uses 20-bit displacements There are many exceptions to the scheme outlined in the above lists, -in particular for the priviledged instructions. For non-priviledged -instruction it works quite well, for example the instruction `clgfr' c: -compare instruction, l: unsigned operands, g: 64-bit operands, f: 32- -to 64-bit extension, r: register operands. The instruction compares an +in particular for the priviledged instructions. For non-priviledged +instruction it works quite well, for example the instruction 'clgfr' c: +compare instruction, l: unsigned operands, g: 64-bit operands, f: 32- to +64-bit extension, r: register operands. The instruction compares an 64-bit value in a register with the zero extended 32-bit value from a -second register. For a complete list of all mnemonics see appendix B -in the Principles of Operation. +second register. For a complete list of all mnemonics see appendix B in +the Principles of Operation. File: as.info, Node: s390 Operands, Next: s390 Formats, Prev: s390 Mnemonics, Up: s390 Syntax @@ -15868,68 +15768,60 @@ Instruction operands can be grouped into three classes, operands located in registers, immediate operands, and operands in storage. A register operand can be located in general, floating-point, access, -or control register. The register is identified by a four-bit field. +or control register. The register is identified by a four-bit field. The field containing the register operand is called the R field. Immediate operands are contained within the instruction and can have -8, 16 or 32 bits. The field containing the immediate operand is called -the I field. Dependent on the instruction the I field is either signed +8, 16 or 32 bits. The field containing the immediate operand is called +the I field. Dependent on the instruction the I field is either signed or unsigned. - A storage operand consists of an address and a length. The address + A storage operand consists of an address and a length. The address of a storage operands can be specified in any of these ways: * The content of a single general R - * The sum of the content of a general register called the base register B plus the content of a displacement field D - * The sum of the contents of two general registers called the index register X and the base register B plus the content of a displacement field - * The sum of the current instruction address and a 32-bit signed immediate field multiplied by two. The length of a storage operand can be: * Implied by the instruction - * Specified by a bitmask - * Specified by a four-bit or eight-bit length field L - * Specified by the content of a general register The notation for storage operand addresses formed from multiple fields is as follows: -`Dn(Bn)' +'Dn(Bn)' the address for operand number n is formed from the content of general register Bn called the base register and the displacement field Dn. - -`Dn(Xn,Bn)' +'Dn(Xn,Bn)' the address for operand number n is formed from the content of general register Xn called the index register, general register Bn called the base register and the displacement field Dn. - -`Dn(Ln,Bn)' +'Dn(Ln,Bn)' the address for operand number n is formed from the content of general regiser Bn called the base register and the displacement field Dn. The length of the operand n is specified by the field Ln. - The base registers Bn and the index registers Xn of a storage -operand can be skipped. If Bn and Xn are skipped, a zero will be stored -to the operand field. The notation changes as follows: + The base registers Bn and the index registers Xn of a storage operand +can be skipped. If Bn and Xn are skipped, a zero will be stored to the +operand field. The notation changes as follows: - full notation short notation - ------------------------------------------ - Dn(0,Bn) Dn(Bn) - Dn(0,0) Dn - Dn(0) Dn - Dn(Ln,0) Dn(Ln) + full notation short notation + ---------------------------------------------- + Dn(0,Bn) Dn(Bn) + Dn(0,0) Dn + Dn(0) Dn + Dn(Ln,0) Dn(Ln) File: as.info, Node: s390 Formats, Next: s390 Aliases, Prev: s390 Operands, Up: s390 Syntax @@ -15938,9 +15830,9 @@ File: as.info, Node: s390 Formats, Next: s390 Aliases, Prev: s390 Operands, ............................ The Principles of Operation manuals lists 26 instruction formats where -some of the formats have multiple variants. For the `.insn' pseudo +some of the formats have multiple variants. For the '.insn' pseudo directive the assembler recognizes some of the formats. Typically, the -most general variant of the instruction format is used by the `.insn' +most general variant of the instruction format is used by the '.insn' directive. The following table lists the abbreviations used in the table of @@ -15957,165 +15849,164 @@ instruction formats: Ux Unsigned immediate for operand x. An instruction is two, four, or six bytes in length and must be -aligned on a 2 byte boundary. The first two bits of the instruction +aligned on a 2 byte boundary. The first two bits of the instruction specify the length of the instruction, 00 indicates a two byte instruction, 01 and 10 indicates a four byte instruction, and 11 indicates a six byte instruction. The following table lists the s390 instruction formats that are -available with the `.insn' pseudo directive: +available with the '.insn' pseudo directive: -`E format' +'E format' +-------------+ | OpCode | +-------------+ 0 15 -`RI format: <insn> R1,I2' +'RI format: <insn> R1,I2' +--------+----+----+------------------+ | OpCode | R1 |OpCd| I2 | +--------+----+----+------------------+ 0 8 12 16 31 -`RIE format: <insn> R1,R3,I2' +'RIE format: <insn> R1,R3,I2' +--------+----+----+------------------+--------+--------+ | OpCode | R1 | R3 | I2 |////////| OpCode | +--------+----+----+------------------+--------+--------+ 0 8 12 16 32 40 47 -`RIL format: <insn> R1,I2' +'RIL format: <insn> R1,I2' +--------+----+----+------------------------------------+ | OpCode | R1 |OpCd| I2 | +--------+----+----+------------------------------------+ 0 8 12 16 47 -`RILU format: <insn> R1,U2' +'RILU format: <insn> R1,U2' +--------+----+----+------------------------------------+ | OpCode | R1 |OpCd| U2 | +--------+----+----+------------------------------------+ 0 8 12 16 47 -`RIS format: <insn> R1,I2,M3,D4(B4)' +'RIS format: <insn> R1,I2,M3,D4(B4)' +--------+----+----+----+-------------+--------+--------+ | OpCode | R1 | M3 | B4 | D4 | I2 | Opcode | +--------+----+----+----+-------------+--------+--------+ 0 8 12 16 20 32 36 47 -`RR format: <insn> R1,R2' +'RR format: <insn> R1,R2' +--------+----+----+ | OpCode | R1 | R2 | +--------+----+----+ 0 8 12 15 -`RRE format: <insn> R1,R2' +'RRE format: <insn> R1,R2' +------------------+--------+----+----+ | OpCode |////////| R1 | R2 | +------------------+--------+----+----+ 0 16 24 28 31 -`RRF format: <insn> R1,R2,R3,M4' +'RRF format: <insn> R1,R2,R3,M4' +------------------+----+----+----+----+ | OpCode | R3 | M4 | R1 | R2 | +------------------+----+----+----+----+ 0 16 20 24 28 31 -`RRS format: <insn> R1,R2,M3,D4(B4)' +'RRS format: <insn> R1,R2,M3,D4(B4)' +--------+----+----+----+-------------+----+----+--------+ | OpCode | R1 | R3 | B4 | D4 | M3 |////| OpCode | +--------+----+----+----+-------------+----+----+--------+ 0 8 12 16 20 32 36 40 47 -`RS format: <insn> R1,R3,D2(B2)' +'RS format: <insn> R1,R3,D2(B2)' +--------+----+----+----+-------------+ | OpCode | R1 | R3 | B2 | D2 | +--------+----+----+----+-------------+ 0 8 12 16 20 31 -`RSE format: <insn> R1,R3,D2(B2)' +'RSE format: <insn> R1,R3,D2(B2)' +--------+----+----+----+-------------+--------+--------+ | OpCode | R1 | R3 | B2 | D2 |////////| OpCode | +--------+----+----+----+-------------+--------+--------+ 0 8 12 16 20 32 40 47 -`RSI format: <insn> R1,R3,I2' +'RSI format: <insn> R1,R3,I2' +--------+----+----+------------------------------------+ | OpCode | R1 | R3 | I2 | +--------+----+----+------------------------------------+ 0 8 12 16 47 -`RSY format: <insn> R1,R3,D2(B2)' +'RSY format: <insn> R1,R3,D2(B2)' +--------+----+----+----+-------------+--------+--------+ | OpCode | R1 | R3 | B2 | DL2 | DH2 | OpCode | +--------+----+----+----+-------------+--------+--------+ 0 8 12 16 20 32 40 47 -`RX format: <insn> R1,D2(X2,B2)' +'RX format: <insn> R1,D2(X2,B2)' +--------+----+----+----+-------------+ | OpCode | R1 | X2 | B2 | D2 | +--------+----+----+----+-------------+ 0 8 12 16 20 31 -`RXE format: <insn> R1,D2(X2,B2)' +'RXE format: <insn> R1,D2(X2,B2)' +--------+----+----+----+-------------+--------+--------+ | OpCode | R1 | X2 | B2 | D2 |////////| OpCode | +--------+----+----+----+-------------+--------+--------+ 0 8 12 16 20 32 40 47 -`RXF format: <insn> R1,R3,D2(X2,B2)' +'RXF format: <insn> R1,R3,D2(X2,B2)' +--------+----+----+----+-------------+----+---+--------+ | OpCode | R3 | X2 | B2 | D2 | R1 |///| OpCode | +--------+----+----+----+-------------+----+---+--------+ 0 8 12 16 20 32 36 40 47 -`RXY format: <insn> R1,D2(X2,B2)' +'RXY format: <insn> R1,D2(X2,B2)' +--------+----+----+----+-------------+--------+--------+ | OpCode | R1 | X2 | B2 | DL2 | DH2 | OpCode | +--------+----+----+----+-------------+--------+--------+ 0 8 12 16 20 32 36 40 47 -`S format: <insn> D2(B2)' +'S format: <insn> D2(B2)' +------------------+----+-------------+ | OpCode | B2 | D2 | +------------------+----+-------------+ 0 16 20 31 -`SI format: <insn> D1(B1),I2' +'SI format: <insn> D1(B1),I2' +--------+---------+----+-------------+ | OpCode | I2 | B1 | D1 | +--------+---------+----+-------------+ 0 8 16 20 31 -`SIY format: <insn> D1(B1),U2' +'SIY format: <insn> D1(B1),U2' +--------+---------+----+-------------+--------+--------+ | OpCode | I2 | B1 | DL1 | DH1 | OpCode | +--------+---------+----+-------------+--------+--------+ 0 8 16 20 32 36 40 47 -`SIL format: <insn> D1(B1),I2' +'SIL format: <insn> D1(B1),I2' +------------------+----+-------------+-----------------+ | OpCode | B1 | D1 | I2 | +------------------+----+-------------+-----------------+ 0 16 20 32 47 -`SS format: <insn> D1(R1,B1),D2(B3),R3' +'SS format: <insn> D1(R1,B1),D2(B3),R3' +--------+----+----+----+-------------+----+------------+ | OpCode | R1 | R3 | B1 | D1 | B2 | D2 | +--------+----+----+----+-------------+----+------------+ 0 8 12 16 20 32 36 47 -`SSE format: <insn> D1(B1),D2(B2)' +'SSE format: <insn> D1(B1),D2(B2)' +------------------+----+-------------+----+------------+ | OpCode | B1 | D1 | B2 | D2 | +------------------+----+-------------+----+------------+ 0 8 12 16 20 32 36 47 -`SSF format: <insn> D1(B1),D2(B2),R3' +'SSF format: <insn> D1(B1),D2(B2),R3' +--------+----+----+----+-------------+----+------------+ | OpCode | R3 |OpCd| B1 | D1 | B2 | D2 | +--------+----+----+----+-------------+----+------------+ 0 8 12 16 20 32 36 47 - For the complete list of all instruction format variants see the Principles of Operation manuals. @@ -16126,23 +16017,23 @@ File: as.info, Node: s390 Aliases, Next: s390 Operand Modifier, Prev: s390 Fo ............................ A specific bit pattern can have multiple mnemonics, for example the bit -pattern `0xa7000000' has the mnemonics `tmh' and `tmlh'. In addition, -there are a number of mnemonics recognized by `as' that are not present -in the Principles of Operation. These are the short forms of the -branch instructions, where the condition code mask operand is encoded -in the mnemonic. This is relevant for the branch instructions, the -compare and branch instructions, and the compare and trap instructions. +pattern '0xa7000000' has the mnemonics 'tmh' and 'tmlh'. In addition, +there are a number of mnemonics recognized by 'as' that are not present +in the Principles of Operation. These are the short forms of the branch +instructions, where the condition code mask operand is encoded in the +mnemonic. This is relevant for the branch instructions, the compare and +branch instructions, and the compare and trap instructions. For the branch instructions there are 20 condition code strings that can be used as part of the mnemonic in place of a mask operand in the instruction format: - instruction short form - ------------------------------------------ - bcr M1,R2 b<m>r R2 - bc M1,D2(X2,B2) b<m> D2(X2,B2) - brc M1,I2 j<m> I2 - brcl M1,I2 jg<m> I2 + instruction short form + ---------------------------------------------- + bcr M1,R2 b<m>r R2 + bc M1,D2(X2,B2) b<m> D2(X2,B2) + brc M1,I2 j<m> I2 + brcl M1,I2 jg<m> I2 In the mnemonic for a branch instruction the condition code string <m> can be any of the following: @@ -16172,32 +16063,32 @@ instruction format: are 12 condition code strings that can be used as part of the mnemonic in place of a mask operand in the instruction format: - instruction short form - -------------------------------------------------------- - crb R1,R2,M3,D4(B4) crb<m> R1,R2,D4(B4) - cgrb R1,R2,M3,D4(B4) cgrb<m> R1,R2,D4(B4) - crj R1,R2,M3,I4 crj<m> R1,R2,I4 - cgrj R1,R2,M3,I4 cgrj<m> R1,R2,I4 - cib R1,I2,M3,D4(B4) cib<m> R1,I2,D4(B4) - cgib R1,I2,M3,D4(B4) cgib<m> R1,I2,D4(B4) - cij R1,I2,M3,I4 cij<m> R1,I2,I4 - cgij R1,I2,M3,I4 cgij<m> R1,I2,I4 - crt R1,R2,M3 crt<m> R1,R2 - cgrt R1,R2,M3 cgrt<m> R1,R2 - cit R1,I2,M3 cit<m> R1,I2 - cgit R1,I2,M3 cgit<m> R1,I2 - clrb R1,R2,M3,D4(B4) clrb<m> R1,R2,D4(B4) - clgrb R1,R2,M3,D4(B4) clgrb<m> R1,R2,D4(B4) - clrj R1,R2,M3,I4 clrj<m> R1,R2,I4 - clgrj R1,R2,M3,I4 clgrj<m> R1,R2,I4 - clib R1,I2,M3,D4(B4) clib<m> R1,I2,D4(B4) - clgib R1,I2,M3,D4(B4) clgib<m> R1,I2,D4(B4) - clij R1,I2,M3,I4 clij<m> R1,I2,I4 - clgij R1,I2,M3,I4 clgij<m> R1,I2,I4 - clrt R1,R2,M3 clrt<m> R1,R2 - clgrt R1,R2,M3 clgrt<m> R1,R2 - clfit R1,I2,M3 clfit<m> R1,I2 - clgit R1,I2,M3 clgit<m> R1,I2 + instruction short form + ------------------------------------------------------------ + crb R1,R2,M3,D4(B4) crb<m> R1,R2,D4(B4) + cgrb R1,R2,M3,D4(B4) cgrb<m> R1,R2,D4(B4) + crj R1,R2,M3,I4 crj<m> R1,R2,I4 + cgrj R1,R2,M3,I4 cgrj<m> R1,R2,I4 + cib R1,I2,M3,D4(B4) cib<m> R1,I2,D4(B4) + cgib R1,I2,M3,D4(B4) cgib<m> R1,I2,D4(B4) + cij R1,I2,M3,I4 cij<m> R1,I2,I4 + cgij R1,I2,M3,I4 cgij<m> R1,I2,I4 + crt R1,R2,M3 crt<m> R1,R2 + cgrt R1,R2,M3 cgrt<m> R1,R2 + cit R1,I2,M3 cit<m> R1,I2 + cgit R1,I2,M3 cgit<m> R1,I2 + clrb R1,R2,M3,D4(B4) clrb<m> R1,R2,D4(B4) + clgrb R1,R2,M3,D4(B4) clgrb<m> R1,R2,D4(B4) + clrj R1,R2,M3,I4 clrj<m> R1,R2,I4 + clgrj R1,R2,M3,I4 clgrj<m> R1,R2,I4 + clib R1,I2,M3,D4(B4) clib<m> R1,I2,D4(B4) + clgib R1,I2,M3,D4(B4) clgib<m> R1,I2,D4(B4) + clij R1,I2,M3,I4 clij<m> R1,I2,I4 + clgij R1,I2,M3,I4 clgij<m> R1,I2,I4 + clrt R1,R2,M3 clrt<m> R1,R2 + clgrt R1,R2,M3 clgrt<m> R1,R2 + clfit R1,I2,M3 clfit<m> R1,I2 + clgit R1,I2,M3 clgit<m> R1,I2 In the mnemonic for a compare and branch and compare and trap instruction the condition code string <m> can be any of the following: @@ -16224,76 +16115,69 @@ File: as.info, Node: s390 Operand Modifier, Next: s390 Instruction Marker, Pr If a symbol modifier is attached to a symbol in an expression for an instruction operand field, the symbol term is replaced with a reference to an object in the global offset table (GOT) or the procedure linkage -table (PLT). The following expressions are allowed: `symbol@modifier + -constant', `symbol@modifier + label + constant', and `symbol@modifier - -label + constant'. The term `symbol' is the symbol that will be -entered into the GOT or PLT, `label' is a local label, and `constant' -is an arbitrary expression that the assembler can evaluate to a -constant value. - - The term `(symbol + constant1)@modifier +/- label + constant2' is -also accepted but a warning message is printed and the term is -converted to `symbol@modifier +/- label + constant1 + constant2'. - -`@got' -`@got12' +table (PLT). The following expressions are allowed: 'symbol@modifier + +constant', 'symbol@modifier + label + constant', and 'symbol@modifier - +label + constant'. The term 'symbol' is the symbol that will be entered +into the GOT or PLT, 'label' is a local label, and 'constant' is an +arbitrary expression that the assembler can evaluate to a constant +value. + + The term '(symbol + constant1)@modifier +/- label + constant2' is +also accepted but a warning message is printed and the term is converted +to 'symbol@modifier +/- label + constant1 + constant2'. + +'@got' +'@got12' The @got modifier can be used for displacement fields, 16-bit - immediate fields and 32-bit pc-relative immediate fields. The - @got12 modifier is synonym to @got. The symbol is added to the - GOT. For displacement fields and 16-bit immediate fields the - symbol term is replaced with the offset from the start of the GOT - to the GOT slot for the symbol. For a 32-bit pc-relative field - the pc-relative offset to the GOT slot from the current - instruction address is used. - -`@gotent' + immediate fields and 32-bit pc-relative immediate fields. The + @got12 modifier is synonym to @got. The symbol is added to the + GOT. For displacement fields and 16-bit immediate fields the symbol + term is replaced with the offset from the start of the GOT to the + GOT slot for the symbol. For a 32-bit pc-relative field the + pc-relative offset to the GOT slot from the current instruction + address is used. +'@gotent' The @gotent modifier can be used for 32-bit pc-relative immediate fields. The symbol is added to the GOT and the symbol term is replaced with the pc-relative offset from the current instruction to the GOT slot for the symbol. - -`@gotoff' - The @gotoff modifier can be used for 16-bit immediate fields. The +'@gotoff' + The @gotoff modifier can be used for 16-bit immediate fields. The symbol term is replaced with the offset from the start of the GOT to the address of the symbol. - -`@gotplt' +'@gotplt' The @gotplt modifier can be used for displacement fields, 16-bit - immediate fields, and 32-bit pc-relative immediate fields. A + immediate fields, and 32-bit pc-relative immediate fields. A procedure linkage table entry is generated for the symbol and a jump slot for the symbol is added to the GOT. For displacement - fields and 16-bit immediate fields the symbol term is replaced - with the offset from the start of the GOT to the jump slot for the - symbol. For a 32-bit pc-relative field the pc-relative offset to + fields and 16-bit immediate fields the symbol term is replaced with + the offset from the start of the GOT to the jump slot for the + symbol. For a 32-bit pc-relative field the pc-relative offset to the jump slot from the current instruction address is used. - -`@plt' +'@plt' The @plt modifier can be used for 16-bit and 32-bit pc-relative - immediate fields. A procedure linkage table entry is generated for + immediate fields. A procedure linkage table entry is generated for the symbol. The symbol term is replaced with the relative offset from the current instruction to the PLT entry for the symbol. - -`@pltoff' - The @pltoff modifier can be used for 16-bit immediate fields. The +'@pltoff' + The @pltoff modifier can be used for 16-bit immediate fields. The symbol term is replaced with the offset from the start of the PLT to the address of the symbol. - -`@gotntpoff' - The @gotntpoff modifier can be used for displacement fields. The +'@gotntpoff' + The @gotntpoff modifier can be used for displacement fields. The symbol is added to the static TLS block and the negated offset to the symbol in the static TLS block is added to the GOT. The symbol term is replaced with the offset to the GOT slot from the start of the GOT. - -`@indntpoff' +'@indntpoff' The @indntpoff modifier can be used for 32-bit pc-relative - immediate fields. The symbol is added to the static TLS block and + immediate fields. The symbol is added to the static TLS block and the negated offset to the symbol in the static TLS block is added - to the GOT. The symbol term is replaced with the pc-relative - offset to the GOT slot from the current instruction address. + to the GOT. The symbol term is replaced with the pc-relative offset + to the GOT slot from the current instruction address. For more information about the thread local storage modifiers -`gotntpoff' and `indntpoff' see the ELF extension documentation `ELF +'gotntpoff' and 'indntpoff' see the ELF extension documentation 'ELF Handling For Thread-Local Storage'. @@ -16305,24 +16189,22 @@ File: as.info, Node: s390 Instruction Marker, Next: s390 Literal Pool Entries, The thread local storage instruction markers are used by the linker to perform code optimization. -`:tls_load' +':tls_load' The :tls_load marker is used to flag the load instruction in the initial exec TLS model that retrieves the offset from the thread pointer to a thread local storage variable from the GOT. - -`:tls_gdcall' +':tls_gdcall' The :tls_gdcall marker is used to flag the branch-and-save instruction to the __tls_get_offset function in the global dynamic TLS model. - -`:tls_ldcall' +':tls_ldcall' The :tls_ldcall marker is used to flag the branch-and-save instruction to the __tls_get_offset function in the local dynamic TLS model. For more information about the thread local storage instruction marker and the linker optimizations see the ELF extension documentation -`ELF Handling For Thread-Local Storage'. +'ELF Handling For Thread-Local Storage'. File: as.info, Node: s390 Literal Pool Entries, Prev: s390 Instruction Marker, Up: s390 Syntax @@ -16330,41 +16212,39 @@ File: as.info, Node: s390 Literal Pool Entries, Prev: s390 Instruction Marker, 9.37.3.8 Literal Pool Entries ............................. -A literal pool is a collection of values. To access the values a pointer -to the literal pool is loaded to a register, the literal pool register. -Usually, register %r13 is used as the literal pool register (*note s390 -Register::). Literal pool entries are created by adding the suffix -:lit1, :lit2, :lit4, or :lit8 to the end of an expression for an -instruction operand. The expression is added to the literal pool and the -operand is replaced with the offset to the literal in the literal pool. +A literal pool is a collection of values. To access the values a +pointer to the literal pool is loaded to a register, the literal pool +register. Usually, register %r13 is used as the literal pool register +(*note s390 Register::). Literal pool entries are created by adding the +suffix :lit1, :lit2, :lit4, or :lit8 to the end of an expression for an +instruction operand. The expression is added to the literal pool and +the operand is replaced with the offset to the literal in the literal +pool. -`:lit1' - The literal pool entry is created as an 8-bit value. An operand +':lit1' + The literal pool entry is created as an 8-bit value. An operand modifier must not be used for the original expression. - -`:lit2' - The literal pool entry is created as a 16 bit value. The operand - modifier @got may be used in the original expression. The term - `x@got:lit2' will put the got offset for the global symbol x to - the literal pool as 16 bit value. - -`:lit4' - The literal pool entry is created as a 32-bit value. The operand - modifier @got and @plt may be used in the original expression. The - term `x@got:lit4' will put the got offset for the global symbol x - to the literal pool as a 32-bit value. The term `x@plt:lit4' will - put the plt offset for the global symbol x to the literal pool as - a 32-bit value. - -`:lit8' - The literal pool entry is created as a 64-bit value. The operand - modifier @got and @plt may be used in the original expression. The - term `x@got:lit8' will put the got offset for the global symbol x - to the literal pool as a 64-bit value. The term `x@plt:lit8' will - put the plt offset for the global symbol x to the literal pool as - a 64-bit value. - - The assembler directive `.ltorg' is used to emit all literal pool +':lit2' + The literal pool entry is created as a 16 bit value. The operand + modifier @got may be used in the original expression. The term + 'x@got:lit2' will put the got offset for the global symbol x to the + literal pool as 16 bit value. +':lit4' + The literal pool entry is created as a 32-bit value. The operand + modifier @got and @plt may be used in the original expression. The + term 'x@got:lit4' will put the got offset for the global symbol x + to the literal pool as a 32-bit value. The term 'x@plt:lit4' will + put the plt offset for the global symbol x to the literal pool as a + 32-bit value. +':lit8' + The literal pool entry is created as a 64-bit value. The operand + modifier @got and @plt may be used in the original expression. The + term 'x@got:lit8' will put the got offset for the global symbol x + to the literal pool as a 64-bit value. The term 'x@plt:lit8' will + put the plt offset for the global symbol x to the literal pool as a + 64-bit value. + + The assembler directive '.ltorg' is used to emit all literal pool entries to the current position. @@ -16373,113 +16253,103 @@ File: as.info, Node: s390 Directives, Next: s390 Floating Point, Prev: s390 S 9.37.4 Assembler Directives --------------------------- -`as' for s390 supports all of the standard ELF assembler directives as +'as' for s390 supports all of the standard ELF assembler directives as outlined in the main part of this document. Some directives have been extended and there are some additional directives, which are only -available for the s390 `as'. +available for the s390 'as'. -`.insn' +'.insn' This directive permits the numeric representation of an instructions and makes the assembler insert the operands according - to one of the instructions formats for `.insn' (*note s390 - Formats::). For example, the instruction `l %r1,24(%r15)' could - be written as `.insn rx,0x58000000,%r1,24(%r15)'. - -`.short' -`.long' -`.quad' + to one of the instructions formats for '.insn' (*note s390 + Formats::). For example, the instruction 'l %r1,24(%r15)' could be + written as '.insn rx,0x58000000,%r1,24(%r15)'. +'.short' +'.long' +'.quad' This directive places one or more 16-bit (.short), 32-bit (.long), - or 64-bit (.quad) values into the current section. If an ELF or + or 64-bit (.quad) values into the current section. If an ELF or TLS modifier is used only the following expressions are allowed: - `symbol@modifier + constant', `symbol@modifier + label + - constant', and `symbol@modifier - label + constant'. The - following modifiers are available: - `@got' - `@got12' + 'symbol@modifier + constant', 'symbol@modifier + label + constant', + and 'symbol@modifier - label + constant'. The following modifiers + are available: + '@got' + '@got12' The @got modifier can be used for .short, .long and .quad. - The @got12 modifier is synonym to @got. The symbol is added + The @got12 modifier is synonym to @got. The symbol is added to the GOT. The symbol term is replaced with offset from the start of the GOT to the GOT slot for the symbol. - - `@gotoff' + '@gotoff' The @gotoff modifier can be used for .short, .long and .quad. The symbol term is replaced with the offset from the start of the GOT to the address of the symbol. - - `@gotplt' - The @gotplt modifier can be used for .long and .quad. A + '@gotplt' + The @gotplt modifier can be used for .long and .quad. A procedure linkage table entry is generated for the symbol and a jump slot for the symbol is added to the GOT. The symbol term is replaced with the offset from the start of the GOT to the jump slot for the symbol. - - `@plt' - The @plt modifier can be used for .long and .quad. A + '@plt' + The @plt modifier can be used for .long and .quad. A procedure linkage table entry us generated for the symbol. The symbol term is replaced with the address of the PLT entry for the symbol. - - `@pltoff' + '@pltoff' The @pltoff modifier can be used for .short, .long and .quad. The symbol term is replaced with the offset from the start of the PLT to the address of the symbol. - - `@tlsgd' - `@tlsldm' + '@tlsgd' + '@tlsldm' The @tlsgd and @tlsldm modifier can be used for .long and - .quad. A tls_index structure for the symbol is added to the + .quad. A tls_index structure for the symbol is added to the GOT. The symbol term is replaced with the offset from the start of the GOT to the tls_index structure. - - `@gotntpoff' - `@indntpoff' + '@gotntpoff' + '@indntpoff' The @gotntpoff and @indntpoff modifier can be used for .long and .quad. The symbol is added to the static TLS block and the negated offset to the symbol in the static TLS block is added to the GOT. For @gotntpoff the symbol term is replaced - with the offset from the start of the GOT to the GOT slot, - for @indntpoff the symbol term is replaced with the address - of the GOT slot. - - `@dtpoff' - The @dtpoff modifier can be used for .long and .quad. The - symbol term is replaced with the offset of the symbol - relative to the start of the TLS block it is contained in. - - `@ntpoff' - The @ntpoff modifier can be used for .long and .quad. The - symbol term is replaced with the offset of the symbol - relative to the TCB pointer. + with the offset from the start of the GOT to the GOT slot, for + @indntpoff the symbol term is replaced with the address of the + GOT slot. + '@dtpoff' + The @dtpoff modifier can be used for .long and .quad. The + symbol term is replaced with the offset of the symbol relative + to the start of the TLS block it is contained in. + '@ntpoff' + The @ntpoff modifier can be used for .long and .quad. The + symbol term is replaced with the offset of the symbol relative + to the TCB pointer. For more information about the thread local storage modifiers see - the ELF extension documentation `ELF Handling For Thread-Local + the ELF extension documentation 'ELF Handling For Thread-Local Storage'. -`.ltorg' +'.ltorg' This directive causes the current contents of the literal pool to be dumped to the current location (*note s390 Literal Pool Entries::). -`.machine string' +'.machine string' This directive allows you to change the machine for which code is - generated. `string' may be any of the `-march=' selection options - (without the -march=), `push', or `pop'. `.machine push' saves - the currently selected cpu, which may be restored with `.machine - pop'. Be aware that the cpu string has to be put into double - quotes in case it contains characters not appropriate for - identifiers. So you have to write `"z9-109"' instead of just - `z9-109'. - -`.machinemode string' + generated. 'string' may be any of the '-march=' selection options + (without the -march=), 'push', or 'pop'. '.machine push' saves the + currently selected cpu, which may be restored with '.machine pop'. + Be aware that the cpu string has to be put into double quotes in + case it contains characters not appropriate for identifiers. So + you have to write '"z9-109"' instead of just 'z9-109'. + +'.machinemode string' This directive allows to change the architecture mode for which - code is being generated. `string' may be `esa', `zarch', - `zarch_nohighgprs', `push', or `pop'. `.machinemode - zarch_nohighgprs' can be used to prevent the `highgprs' flag from + code is being generated. 'string' may be 'esa', 'zarch', + 'zarch_nohighgprs', 'push', or 'pop'. '.machinemode + zarch_nohighgprs' can be used to prevent the 'highgprs' flag from being set in the ELF header of the output file. This is useful in - situations where the code is gated with a runtime check which - makes sure that the code is only executed on kernels providing the - `highgprs' feature. `.machinemode push' saves the currently - selected mode, which may be restored with `.machinemode pop'. + situations where the code is gated with a runtime check which makes + sure that the code is only executed on kernels providing the + 'highgprs' feature. '.machinemode push' saves the currently + selected mode, which may be restored with '.machinemode pop'. File: as.info, Node: s390 Floating Point, Prev: s390 Directives, Up: S/390-Dependent @@ -16488,13 +16358,13 @@ File: as.info, Node: s390 Floating Point, Prev: s390 Directives, Up: S/390-De --------------------- The assembler recognizes both the IEEE floating-point instruction and -the hexadecimal floating-point instructions. The floating-point -constructors `.float', `.single', and `.double' always emit the IEEE -format. To assemble hexadecimal floating-point constants the `.long' -and `.quad' directives must be used. +the hexadecimal floating-point instructions. The floating-point +constructors '.float', '.single', and '.double' always emit the IEEE +format. To assemble hexadecimal floating-point constants the '.long' +and '.quad' directives must be used. -File: as.info, Node: SCORE-Dependent, Next: Sparc-Dependent, Prev: S/390-Dependent, Up: Machine Dependencies +File: as.info, Node: SCORE-Dependent, Next: SH-Dependent, Prev: S/390-Dependent, Up: Machine Dependencies 9.38 SCORE Dependent Features ============================= @@ -16513,117 +16383,115 @@ File: as.info, Node: SCORE-Opts, Next: SCORE-Pseudo, Up: SCORE-Dependent The following table lists all available SCORE options. -`-G NUM' +'-G NUM' This option sets the largest size of an object that can be - referenced implicitly with the `gp' register. The default value is + referenced implicitly with the 'gp' register. The default value is 8. -`-EB' +'-EB' Assemble code for a big-endian cpu -`-EL' +'-EL' Assemble code for a little-endian cpu -`-FIXDD' +'-FIXDD' Assemble code for fix data dependency -`-NWARN' +'-NWARN' Assemble code for no warning message for fix data dependency -`-SCORE5' +'-SCORE5' Assemble code for target is SCORE5 -`-SCORE5U' +'-SCORE5U' Assemble code for target is SCORE5U -`-SCORE7' +'-SCORE7' Assemble code for target is SCORE7, this is default setting -`-SCORE3' +'-SCORE3' Assemble code for target is SCORE3 -`-march=score7' +'-march=score7' Assemble code for target is SCORE7, this is default setting -`-march=score3' +'-march=score3' Assemble code for target is SCORE3 -`-USE_R1' +'-USE_R1' Assemble code for no warning message when using temp register r1 -`-KPIC' - Generate code for PIC. This option tells the assembler to generate +'-KPIC' + Generate code for PIC. This option tells the assembler to generate score position-independent macro expansions. It also tells the assembler to mark the output file as PIC. -`-O0' +'-O0' Assembler will not perform any optimizations -`-V' +'-V' Sunplus release version - File: as.info, Node: SCORE-Pseudo, Next: SCORE-Syntax, Prev: SCORE-Opts, Up: SCORE-Dependent 9.38.2 SCORE Assembler Directives --------------------------------- -A number of assembler directives are available for SCORE. The -following table is far from complete. +A number of assembler directives are available for SCORE. The following +table is far from complete. -`.set nwarn' +'.set nwarn' Let the assembler not to generate warnings if the source machine language instructions happen data dependency. -`.set fixdd' +'.set fixdd' Let the assembler to insert bubbles (32 bit nop instruction / 16 - bit nop! Instruction) if the source machine language instructions + bit nop! Instruction) if the source machine language instructions happen data dependency. -`.set nofixdd' +'.set nofixdd' Let the assembler to generate warnings if the source machine - language instructions happen data dependency. (Default) + language instructions happen data dependency. (Default) -`.set r1' +'.set r1' Let the assembler not to generate warnings if the source program - uses r1. allow user to use r1 + uses r1. allow user to use r1 -`set nor1' +'set nor1' Let the assembler to generate warnings if the source program uses - r1. (Default) + r1. (Default) -`.sdata' +'.sdata' Tell the assembler to add subsequent data into the sdata section -`.rdata' +'.rdata' Tell the assembler to add subsequent data into the rdata section -`.frame "frame-register", "offset", "return-pc-register"' - Describe a stack frame. "frame-register" is the frame register, +'.frame "frame-register", "offset", "return-pc-register"' + Describe a stack frame. "frame-register" is the frame register, "offset" is the distance from the frame register to the virtual frame pointer, "return-pc-register" is the return program register. You must use ".ent" before ".frame" and only one ".frame" can be used per ".ent". -`.mask "bitmask", "frameoffset"' +'.mask "bitmask", "frameoffset"' Indicate which of the integer registers are saved in the current function's stack frame, this is for the debugger to explain the frame chain. -`.ent "proc-name"' - Set the beginning of the procedure "proc_name". Use this directive +'.ent "proc-name"' + Set the beginning of the procedure "proc_name". Use this directive when you want to generate information for the debugger. -`.end proc-name' - Set the end of a procedure. Use this directive to generate +'.end proc-name' + Set the end of a procedure. Use this directive to generate information for the debugger. -`.bss' +'.bss' Switch the destination of following statements into the bss section, which is used for data that is uninitialized anywhere. - File: as.info, Node: SCORE-Syntax, Prev: SCORE-Pseudo, Up: SCORE-Dependent @@ -16640,19 +16508,19 @@ File: as.info, Node: SCORE-Chars, Up: SCORE-Syntax 9.38.3.1 Special Characters ........................... -The presence of a `#' appearing anywhere on a line indicates the start +The presence of a '#' appearing anywhere on a line indicates the start of a comment that extends to the end of that line. - If a `#' appears as the first character of a line then the whole -line is treated as a comment, but in this case the line can also be a -logical line number directive (*note Comments::) or a preprocessor -control command (*note Preprocessing::). + If a '#' appears as the first character of a line then the whole line +is treated as a comment, but in this case the line can also be a logical +line number directive (*note Comments::) or a preprocessor control +command (*note Preprocessing::). - The `;' character can be used to separate statements on the same + The ';' character can be used to separate statements on the same line. -File: as.info, Node: SH-Dependent, Next: SH64-Dependent, Prev: NS32K-Dependent, Up: Machine Dependencies +File: as.info, Node: SH-Dependent, Next: SH64-Dependent, Prev: SCORE-Dependent, Up: Machine Dependencies 9.39 Renesas / SuperH SH Dependent Features =========================================== @@ -16671,50 +16539,46 @@ File: as.info, Node: SH Options, Next: SH Syntax, Up: SH-Dependent 9.39.1 Options -------------- -`as' has following command-line options for the Renesas (formerly +'as' has following command-line options for the Renesas (formerly Hitachi) / SuperH SH family. -`--little' +'--little' Generate little endian code. -`--big' +'--big' Generate big endian code. -`--relax' +'--relax' Alter jump instructions for long displacements. -`--small' +'--small' Align sections to 4 byte boundaries, not 16. -`--dsp' +'--dsp' Enable sh-dsp insns, and disable sh3e / sh4 insns. -`--renesas' +'--renesas' Disable optimization with section symbol for compatibility with Renesas assembler. -`--allow-reg-prefix' +'--allow-reg-prefix' Allow '$' as a register name prefix. -`--fdpic' +'--fdpic' Generate an FDPIC object file. -`--isa=sh4 | sh4a' +'--isa=sh4 | sh4a' Specify the sh4 or sh4a instruction set. - -`--isa=dsp' +'--isa=dsp' Enable sh-dsp insns, and disable sh3e / sh4 insns. - -`--isa=fp' +'--isa=fp' Enable sh2e, sh3e, sh4, and sh4a insn sets. - -`--isa=all' +'--isa=all' Enable sh1, sh2, sh2e, sh3, sh3e, sh4, sh4a, and sh-dsp insn sets. -`-h-tick-hex' +'-h-tick-hex' Support H'00 style hex constants in addition to 0x00 style. - File: as.info, Node: SH Syntax, Next: SH Floating Point, Prev: SH Options, Up: SH-Dependent @@ -16733,16 +16597,16 @@ File: as.info, Node: SH-Chars, Next: SH-Regs, Up: SH Syntax 9.39.2.1 Special Characters ........................... -`!' is the line comment character. +'!' is the line comment character. - You can use `;' instead of a newline to separate statements. + You can use ';' instead of a newline to separate statements. - If a `#' appears as the first character of a line then the whole -line is treated as a comment, but in this case the line could also be a + If a '#' appears as the first character of a line then the whole line +is treated as a comment, but in this case the line could also be a logical line number directive (*note Comments::) or a preprocessor control command (*note Preprocessing::). - Since `$' has no special meaning, you may use it in symbol names. + Since '$' has no special meaning, you may use it in symbol names. File: as.info, Node: SH-Regs, Next: SH-Addressing, Prev: SH-Chars, Up: SH Syntax @@ -16750,29 +16614,29 @@ File: as.info, Node: SH-Regs, Next: SH-Addressing, Prev: SH-Chars, Up: SH Sy 9.39.2.2 Register Names ....................... -You can use the predefined symbols `r0', `r1', `r2', `r3', `r4', `r5', -`r6', `r7', `r8', `r9', `r10', `r11', `r12', `r13', `r14', and `r15' to +You can use the predefined symbols 'r0', 'r1', 'r2', 'r3', 'r4', 'r5', +'r6', 'r7', 'r8', 'r9', 'r10', 'r11', 'r12', 'r13', 'r14', and 'r15' to refer to the SH registers. The SH also has these control registers: -`pr' +'pr' procedure register (holds return address) -`pc' +'pc' program counter -`mach' -`macl' +'mach' +'macl' high and low multiply accumulator registers -`sr' +'sr' status register -`gbr' +'gbr' global base register -`vbr' +'vbr' vector base register (for interrupt vectors) @@ -16781,42 +16645,42 @@ File: as.info, Node: SH-Addressing, Prev: SH-Regs, Up: SH Syntax 9.39.2.3 Addressing Modes ......................... -`as' understands the following addressing modes for the SH. `RN' in -the following refers to any of the numbered registers, but _not_ the -control registers. +'as' understands the following addressing modes for the SH. 'RN' in the +following refers to any of the numbered registers, but _not_ the control +registers. -`RN' +'RN' Register direct -`@RN' +'@RN' Register indirect -`@-RN' +'@-RN' Register indirect with pre-decrement -`@RN+' +'@RN+' Register indirect with post-increment -`@(DISP, RN)' +'@(DISP, RN)' Register indirect with displacement -`@(R0, RN)' +'@(R0, RN)' Register indexed -`@(DISP, GBR)' - `GBR' offset +'@(DISP, GBR)' + 'GBR' offset -`@(R0, GBR)' +'@(R0, GBR)' GBR indexed -`ADDR' -`@(DISP, PC)' +'ADDR' +'@(DISP, PC)' PC relative address (for branch or for addressing memory). The - `as' implementation allows you to use the simpler form ADDR - anywhere a PC relative address is called for; the alternate form - is supported for compatibility with other assemblers. + 'as' implementation allows you to use the simpler form ADDR + anywhere a PC relative address is called for; the alternate form is + supported for compatibility with other assemblers. -`#IMM' +'#IMM' Immediate data @@ -16826,22 +16690,22 @@ File: as.info, Node: SH Floating Point, Next: SH Directives, Prev: SH Syntax, --------------------- SH2E, SH3E and SH4 groups have on-chip floating-point unit (FPU). Other -SH groups can use `.float' directive to generate IEEE floating-point +SH groups can use '.float' directive to generate IEEE floating-point numbers. SH2E and SH3E support single-precision floating point calculations as -well as entirely PCAPI compatible emulation of double-precision -floating point calculations. SH2E and SH3E instructions are a subset of -the floating point calculations conforming to the IEEE754 standard. +well as entirely PCAPI compatible emulation of double-precision floating +point calculations. SH2E and SH3E instructions are a subset of the +floating point calculations conforming to the IEEE754 standard. In addition to single-precision and double-precision floating-point operation capability, the on-chip FPU of SH4 has a 128-bit graphic engine that enables 32-bit floating-point data to be processed 128 bits -at a time. It also supports 4 * 4 array operations and inner product -operations. Also, a superscalar architecture is employed that enables -simultaneous execution of two instructions (including FPU -instructions), providing performance of up to twice that of -conventional architectures at the same frequency. +at a time. It also supports 4 * 4 array operations and inner product +operations. Also, a superscalar architecture is employed that enables +simultaneous execution of two instructions (including FPU instructions), +providing performance of up to twice that of conventional architectures +at the same frequency. File: as.info, Node: SH Directives, Next: SH Opcodes, Prev: SH Floating Point, Up: SH-Dependent @@ -16849,12 +16713,12 @@ File: as.info, Node: SH Directives, Next: SH Opcodes, Prev: SH Floating Point 9.39.4 SH Machine Directives ---------------------------- -`uaword' -`ualong' -`uaquad' - `as' will issue a warning when a misaligned `.word', `.long', or - `.quad' directive is used. You may use `.uaword', `.ualong', or - `.uaquad' to indicate that the value is intentionally misaligned. +'uaword' +'ualong' +'uaquad' + 'as' will issue a warning when a misaligned '.word', '.long', or + '.quad' directive is used. You may use '.uaword', '.ualong', or + '.uaquad' to indicate that the value is intentionally misaligned. File: as.info, Node: SH Opcodes, Prev: SH Directives, Up: SH-Dependent @@ -16863,17 +16727,17 @@ File: as.info, Node: SH Opcodes, Prev: SH Directives, Up: SH-Dependent -------------- For detailed information on the SH machine instruction set, see -`SH-Microcomputer User's Manual' (Renesas) or `SH-4 32-bit CPU Core -Architecture' (SuperH) and `SuperH (SH) 64-Bit RISC Series' (SuperH). +'SH-Microcomputer User's Manual' (Renesas) or 'SH-4 32-bit CPU Core +Architecture' (SuperH) and 'SuperH (SH) 64-Bit RISC Series' (SuperH). - `as' implements all the standard SH opcodes. No additional + 'as' implements all the standard SH opcodes. No additional pseudo-instructions are needed on this family. Note, however, that -because `as' supports a simpler form of PC-relative addressing, you may +because 'as' supports a simpler form of PC-relative addressing, you may simply write (for example) mov.l bar,r0 -where other assemblers might require an explicit displacement to `bar' +where other assemblers might require an explicit displacement to 'bar' from the program counter: mov.l @(DISP, PC) @@ -16930,7 +16794,6 @@ from the program counter: lds Rn,PR mulu Rm,Rn lds.l @Rn+,MACH neg Rm,Rn lds.l @Rn+,MACL negc Rm,Rn - nop stc VBR,Rn not Rm,Rn stc.l GBR,@-Rn or #imm,R0 stc.l SR,@-Rn @@ -16958,7 +16821,7 @@ from the program counter: stc SR,Rn -File: as.info, Node: SH64-Dependent, Next: PDP-11-Dependent, Prev: SH-Dependent, Up: Machine Dependencies +File: as.info, Node: SH64-Dependent, Next: Sparc-Dependent, Prev: SH-Dependent, Up: Machine Dependencies 9.40 SuperH SH64 Dependent Features =================================== @@ -16976,56 +16839,51 @@ File: as.info, Node: SH64 Options, Next: SH64 Syntax, Up: SH64-Dependent 9.40.1 Options -------------- -`-isa=sh4 | sh4a' +'-isa=sh4 | sh4a' Specify the sh4 or sh4a instruction set. - -`-isa=dsp' +'-isa=dsp' Enable sh-dsp insns, and disable sh3e / sh4 insns. - -`-isa=fp' +'-isa=fp' Enable sh2e, sh3e, sh4, and sh4a insn sets. - -`-isa=all' +'-isa=all' Enable sh1, sh2, sh2e, sh3, sh3e, sh4, sh4a, and sh-dsp insn sets. - -`-isa=shmedia | -isa=shcompact' - Specify the default instruction set. `SHmedia' specifies the - 32-bit opcodes, and `SHcompact' specifies the 16-bit opcodes +'-isa=shmedia | -isa=shcompact' + Specify the default instruction set. 'SHmedia' specifies the + 32-bit opcodes, and 'SHcompact' specifies the 16-bit opcodes compatible with previous SH families. The default depends on the ABI selected; the default for the 64-bit ABI is SHmedia, and the default for the 32-bit ABI is SHcompact. If neither the ABI nor the ISA is specified, the default is 32-bit SHcompact. - Note that the `.mode' pseudo-op is not permitted if the ISA is not + Note that the '.mode' pseudo-op is not permitted if the ISA is not specified on the command line. -`-abi=32 | -abi=64' - Specify the default ABI. If the ISA is specified and the ABI is - not, the default ABI depends on the ISA, with SHmedia defaulting - to 64-bit and SHcompact defaulting to 32-bit. +'-abi=32 | -abi=64' + Specify the default ABI. If the ISA is specified and the ABI is + not, the default ABI depends on the ISA, with SHmedia defaulting to + 64-bit and SHcompact defaulting to 32-bit. - Note that the `.abi' pseudo-op is not permitted if the ABI is not + Note that the '.abi' pseudo-op is not permitted if the ABI is not specified on the command line. When the ABI is specified on the - command line, any `.abi' pseudo-ops in the source must match it. + command line, any '.abi' pseudo-ops in the source must match it. -`-shcompact-const-crange' +'-shcompact-const-crange' Emit code-range descriptors for constants in SHcompact code sections. -`-no-mix' +'-no-mix' Disallow SHmedia code in the same section as constants and SHcompact code. -`-no-expand' +'-no-expand' Do not expand MOVI, PT, PTA or PTB instructions. -`-expand-pt32' +'-expand-pt32' With -abi=64, expand PT, PTA and PTB instructions to 32 bits only. -`-h-tick-hex' +'-h-tick-hex' Support H'00 style hex constants in addition to 0x00 style. - File: as.info, Node: SH64 Syntax, Next: SH64 Directives, Prev: SH64 Options, Up: SH64-Dependent @@ -17044,16 +16902,16 @@ File: as.info, Node: SH64-Chars, Next: SH64-Regs, Up: SH64 Syntax 9.40.2.1 Special Characters ........................... -`!' is the line comment character. +'!' is the line comment character. - If a `#' appears as the first character of a line then the whole -line is treated as a comment, but in this case the line could also be a + If a '#' appears as the first character of a line then the whole line +is treated as a comment, but in this case the line could also be a logical line number directive (*note Comments::) or a preprocessor control command (*note Preprocessing::). - You can use `;' instead of a newline to separate statements. + You can use ';' instead of a newline to separate statements. - Since `$' has no special meaning, you may use it in symbol names. + Since '$' has no special meaning, you may use it in symbol names. File: as.info, Node: SH64-Regs, Next: SH64-Addressing, Prev: SH64-Chars, Up: SH64 Syntax @@ -17061,21 +16919,21 @@ File: as.info, Node: SH64-Regs, Next: SH64-Addressing, Prev: SH64-Chars, Up: 9.40.2.2 Register Names ....................... -You can use the predefined symbols `r0' through `r63' to refer to the -SH64 general registers, `cr0' through `cr63' for control registers, -`tr0' through `tr7' for target address registers, `fr0' through `fr63' -for single-precision floating point registers, `dr0' through `dr62' +You can use the predefined symbols 'r0' through 'r63' to refer to the +SH64 general registers, 'cr0' through 'cr63' for control registers, +'tr0' through 'tr7' for target address registers, 'fr0' through 'fr63' +for single-precision floating point registers, 'dr0' through 'dr62' (even numbered registers only) for double-precision floating point -registers, `fv0' through `fv60' (multiples of four only) for -single-precision floating point vectors, `fp0' through `fp62' (even +registers, 'fv0' through 'fv60' (multiples of four only) for +single-precision floating point vectors, 'fp0' through 'fp62' (even numbered registers only) for single-precision floating point pairs, -`mtrx0' through `mtrx48' (multiples of 16 only) for 4x4 matrices of -single-precision floating point registers, `pc' for the program -counter, and `fpscr' for the floating point status and control register. +'mtrx0' through 'mtrx48' (multiples of 16 only) for 4x4 matrices of +single-precision floating point registers, 'pc' for the program counter, +and 'fpscr' for the floating point status and control register. - You can also refer to the control registers by the mnemonics `sr', -`ssr', `pssr', `intevt', `expevt', `pexpevt', `tra', `spc', `pspc', -`resvec', `vbr', `tea', `dcr', `kcr0', `kcr1', `ctc', and `usr'. + You can also refer to the control registers by the mnemonics 'sr', +'ssr', 'pssr', 'intevt', 'expevt', 'pexpevt', 'tra', 'spc', 'pspc', +'resvec', 'vbr', 'tea', 'dcr', 'kcr0', 'kcr1', 'ctc', and 'usr'. File: as.info, Node: SH64-Addressing, Prev: SH64-Regs, Up: SH64 Syntax @@ -17095,10 +16953,10 @@ label reference), as in this example: Instruction label references can reference labels in either SHmedia or SHcompact. To differentiate between the two, labels in SHmedia -sections will always have the least significant bit set (i.e. they will +sections will always have the least significant bit set (i.e. they will be odd), which SHcompact labels will have the least significant bit -reset (i.e. they will be even). If you need to reference the actual -address of a label, you can use the `datalabel' modifier, as in this +reset (i.e. they will be even). If you need to reference the actual +address of a label, you can use the 'datalabel' modifier, as in this example: .long function @@ -17118,22 +16976,21 @@ File: as.info, Node: SH64 Directives, Next: SH64 Opcodes, Prev: SH64 Syntax, In addition to the SH directives, the SH64 provides the following directives: -`.mode [shmedia|shcompact]' -`.isa [shmedia|shcompact]' +'.mode [shmedia|shcompact]' +'.isa [shmedia|shcompact]' Specify the ISA for the following instructions (the two directives - are equivalent). Note that programs such as `objdump' rely on + are equivalent). Note that programs such as 'objdump' rely on symbolic labels to determine when such mode switches occur (by - checking the least significant bit of the label's address), so - such mode/isa changes should always be followed by a label (in - practice, this is true anyway). Note that you cannot use these - directives if you didn't specify an ISA on the command line. + checking the least significant bit of the label's address), so such + mode/isa changes should always be followed by a label (in practice, + this is true anyway). Note that you cannot use these directives if + you didn't specify an ISA on the command line. -`.abi [32|64]' +'.abi [32|64]' Specify the ABI for the following instructions. Note that you cannot use this directive unless you specified an ABI on the command line, and the ABIs specified must match. - File: as.info, Node: SH64 Opcodes, Prev: SH64 Directives, Up: SH64-Dependent @@ -17141,24 +16998,23 @@ File: as.info, Node: SH64 Opcodes, Prev: SH64 Directives, Up: SH64-Dependent -------------- For detailed information on the SH64 machine instruction set, see -`SuperH 64 bit RISC Series Architecture Manual' (SuperH, Inc.). +'SuperH 64 bit RISC Series Architecture Manual' (SuperH, Inc.). - `as' implements all the standard SH64 opcodes. In addition, the + 'as' implements all the standard SH64 opcodes. In addition, the following pseudo-opcodes may be expanded into one or more alternate opcodes: -`movi' - If the value doesn't fit into a standard `movi' opcode, `as' will - replace the `movi' with a sequence of `movi' and `shori' opcodes. +'movi' + If the value doesn't fit into a standard 'movi' opcode, 'as' will + replace the 'movi' with a sequence of 'movi' and 'shori' opcodes. -`pt' - This expands to a sequence of `movi' and `shori' opcode, followed - by a `ptrel' opcode, or to a `pta' or `ptb' opcode, depending on +'pt' + This expands to a sequence of 'movi' and 'shori' opcode, followed + by a 'ptrel' opcode, or to a 'pta' or 'ptb' opcode, depending on the label referenced. - -File: as.info, Node: Sparc-Dependent, Next: TIC54X-Dependent, Prev: SCORE-Dependent, Up: Machine Dependencies +File: as.info, Node: Sparc-Dependent, Next: TIC54X-Dependent, Prev: SH64-Dependent, Up: Machine Dependencies 9.41 SPARC Dependent Features ============================= @@ -17183,98 +17039,98 @@ at each version. There are exceptions to this however. For details on what instructions each variant supports, please see the chip's architecture reference manual. - By default, `as' assumes the core instruction set (SPARC v6), but + By default, 'as' assumes the core instruction set (SPARC v6), but "bumps" the architecture level as needed: it switches to successively higher architectures as it encounters instructions that only exist in the higher levels. - If not configured for SPARC v9 (`sparc64-*-*') GAS will not bump -past sparclite by default, an option must be passed to enable the v9 + If not configured for SPARC v9 ('sparc64-*-*') GAS will not bump past +sparclite by default, an option must be passed to enable the v9 instructions. GAS treats sparclite as being compatible with v8, unless an architecture is explicitly requested. SPARC v9 is always incompatible with sparclite. -`-Av6 | -Av7 | -Av8 | -Asparclet | -Asparclite' -`-Av8plus | -Av8plusa | -Av8plusb | -Av8plusc | -Av8plusd | -Av8plusv' -`-Av9 | -Av9a | -Av9b | -Av9c | -Av9d | -Av9v' -`-Asparc | -Asparcvis | -Asparcvis2 | -Asparcfmaf | -Asparcima' -`-Asparcvis3 | -Asparcvis3r' - Use one of the `-A' options to select one of the SPARC +'-Av6 | -Av7 | -Av8 | -Aleon | -Asparclet | -Asparclite' +'-Av8plus | -Av8plusa | -Av8plusb | -Av8plusc | -Av8plusd | -Av8plusv' +'-Av9 | -Av9a | -Av9b | -Av9c | -Av9d | -Av9v' +'-Asparc | -Asparcvis | -Asparcvis2 | -Asparcfmaf | -Asparcima' +'-Asparcvis3 | -Asparcvis3r' + Use one of the '-A' options to select one of the SPARC architectures explicitly. If you select an architecture - explicitly, `as' reports a fatal error if it encounters an + explicitly, 'as' reports a fatal error if it encounters an instruction or feature requiring an incompatible or higher level. - `-Av8plus', `-Av8plusa', `-Av8plusb', `-Av8plusc', `-Av8plusd', - and `-Av8plusv' select a 32 bit environment. + '-Av8plus', '-Av8plusa', '-Av8plusb', '-Av8plusc', '-Av8plusd', and + '-Av8plusv' select a 32 bit environment. - `-Av9', `-Av9a', `-Av9b', `-Av9c', `-Av9d', and `-Av9v' select a - 64 bit environment and are not available unless GAS is explicitly + '-Av9', '-Av9a', '-Av9b', '-Av9c', '-Av9d', and '-Av9v' select a 64 + bit environment and are not available unless GAS is explicitly configured with 64 bit environment support. - `-Av8plusa' and `-Av9a' enable the SPARC V9 instruction set with + '-Av8plusa' and '-Av9a' enable the SPARC V9 instruction set with UltraSPARC VIS 1.0 extensions. - `-Av8plusb' and `-Av9b' enable the UltraSPARC VIS 2.0 instructions, - as well as the instructions enabled by `-Av8plusa' and `-Av9a'. + '-Av8plusb' and '-Av9b' enable the UltraSPARC VIS 2.0 instructions, + as well as the instructions enabled by '-Av8plusa' and '-Av9a'. - `-Av8plusc' and `-Av9c' enable the UltraSPARC Niagara instructions, - as well as the instructions enabled by `-Av8plusb' and `-Av9b'. + '-Av8plusc' and '-Av9c' enable the UltraSPARC Niagara instructions, + as well as the instructions enabled by '-Av8plusb' and '-Av9b'. - `-Av8plusd' and `-Av9d' enable the floating point fused + '-Av8plusd' and '-Av9d' enable the floating point fused multiply-add, VIS 3.0, and HPC extension instructions, as well as - the instructions enabled by `-Av8plusc' and `-Av9c'. + the instructions enabled by '-Av8plusc' and '-Av9c'. - `-Av8plusv' and `-Av9v' enable the 'random', transactional memory, + '-Av8plusv' and '-Av9v' enable the 'random', transactional memory, floating point unfused multiply-add, integer multiply-add, and cache sparing store instructions, as well as the instructions - enabled by `-Av8plusd' and `-Av9d'. + enabled by '-Av8plusd' and '-Av9d'. - `-Asparc' specifies a v9 environment. It is equivalent to `-Av9' - if the word size is 64-bit, and `-Av8plus' otherwise. + '-Asparc' specifies a v9 environment. It is equivalent to '-Av9' + if the word size is 64-bit, and '-Av8plus' otherwise. - `-Asparcvis' specifies a v9a environment. It is equivalent to - `-Av9a' if the word size is 64-bit, and `-Av8plusa' otherwise. + '-Asparcvis' specifies a v9a environment. It is equivalent to + '-Av9a' if the word size is 64-bit, and '-Av8plusa' otherwise. - `-Asparcvis2' specifies a v9b environment. It is equivalent to - `-Av9b' if the word size is 64-bit, and `-Av8plusb' otherwise. + '-Asparcvis2' specifies a v9b environment. It is equivalent to + '-Av9b' if the word size is 64-bit, and '-Av8plusb' otherwise. - `-Asparcfmaf' specifies a v9b environment with the floating point + '-Asparcfmaf' specifies a v9b environment with the floating point fused multiply-add instructions enabled. - `-Asparcima' specifies a v9b environment with the integer + '-Asparcima' specifies a v9b environment with the integer multiply-add instructions enabled. - `-Asparcvis3' specifies a v9b environment with the VIS 3.0, HPC , + '-Asparcvis3' specifies a v9b environment with the VIS 3.0, HPC , and floating point fused multiply-add instructions enabled. - `-Asparcvis3r' specifies a v9b environment with the VIS 3.0, HPC, + '-Asparcvis3r' specifies a v9b environment with the VIS 3.0, HPC, transactional memory, random, and floating point unfused multiply-add instructions enabled. -`-xarch=v8plus | -xarch=v8plusa | -xarch=v8plusb | -xarch=v8plusc' -`-xarch=v8plusd | -xarch=v8plusv | -xarch=v9 | -xarch=v9a' -`-xarch=v9b | -xarch=v9c | -xarch=v9d | -xarch=v9v' -`-xarch=sparc | -xarch=sparcvis | -xarch=sparcvis2' -`-xarch=sparcfmaf | -xarch=sparcima | -xarch=sparcvis3' -`-xarch=sparcvis3r' +'-xarch=v8plus | -xarch=v8plusa | -xarch=v8plusb | -xarch=v8plusc' +'-xarch=v8plusd | -xarch=v8plusv | -xarch=v9 | -xarch=v9a' +'-xarch=v9b | -xarch=v9c | -xarch=v9d | -xarch=v9v' +'-xarch=sparc | -xarch=sparcvis | -xarch=sparcvis2' +'-xarch=sparcfmaf | -xarch=sparcima | -xarch=sparcvis3' +'-xarch=sparcvis3r' For compatibility with the SunOS v9 assembler. These options are equivalent to -Av8plus, -Av8plusa, -Av8plusb, -Av8plusc, -Av8plusd, -Av8plusv, -Av9, -Av9a, -Av9b, -Av9c, -Av9d, -Av9v, -Asparc, -Asparcvis, -Asparcvis2, -Asparcfmaf, -Asparcima, -Asparcvis3, and -Asparcvis3r, respectively. -`-bump' +'-bump' Warn whenever it is necessary to switch to another level. If an architecture level is explicitly requested, GAS will not issue warnings until that level is reached, and will then bump the level as required (except between incompatible levels). -`-32 | -64' - Select the word size, either 32 bits or 64 bits. These options - are only available with the ELF object file format, and require - that the necessary BFD support has been included. +'-32 | -64' + Select the word size, either 32 bits or 64 bits. These options are + only available with the ELF object file format, and require that + the necessary BFD support has been included. File: as.info, Node: Sparc-Aligned-Data, Next: Sparc-Syntax, Prev: Sparc-Opts, Up: Sparc-Dependent @@ -17283,17 +17139,17 @@ File: as.info, Node: Sparc-Aligned-Data, Next: Sparc-Syntax, Prev: Sparc-Opts ----------------------------- SPARC GAS normally permits data to be misaligned. For example, it -permits the `.long' pseudo-op to be used on a byte boundary. However, +permits the '.long' pseudo-op to be used on a byte boundary. However, the native SunOS assemblers issue an error when they see misaligned data. - You can use the `--enforce-aligned-data' option to make SPARC GAS + You can use the '--enforce-aligned-data' option to make SPARC GAS also issue an error about misaligned data, just as the SunOS assemblers do. - The `--enforce-aligned-data' option is not the default because gcc + The '--enforce-aligned-data' option is not the default because gcc issues misaligned data pseudo-ops when it initializes certain packed -data structures (structures defined using the `packed' attribute). You +data structures (structures defined using the 'packed' attribute). You may have to assemble with GAS in order to initialize packed data structures in your own code. @@ -17321,15 +17177,15 @@ File: as.info, Node: Sparc-Chars, Next: Sparc-Regs, Up: Sparc-Syntax 9.41.3.1 Special Characters ........................... -A `!' character appearing anywhere on a line indicates the start of a +A '!' character appearing anywhere on a line indicates the start of a comment that extends to the end of that line. - If a `#' appears as the first character of a line then the whole -line is treated as a comment, but in this case the line could also be a + If a '#' appears as the first character of a line then the whole line +is treated as a comment, but in this case the line could also be a logical line number directive (*note Comments::) or a preprocessor control command (*note Preprocessing::). - `;' can be used instead of a newline to separate statements. + ';' can be used instead of a newline to separate statements. File: as.info, Node: Sparc-Regs, Next: Sparc-Constants, Prev: Sparc-Chars, Up: Sparc-Syntax @@ -17340,147 +17196,146 @@ File: as.info, Node: Sparc-Regs, Next: Sparc-Constants, Prev: Sparc-Chars, U The Sparc integer register file is broken down into global, outgoing, local, and incoming. - * The 8 global registers are referred to as `%gN'. + * The 8 global registers are referred to as '%gN'. - * The 8 outgoing registers are referred to as `%oN'. + * The 8 outgoing registers are referred to as '%oN'. - * The 8 local registers are referred to as `%lN'. + * The 8 local registers are referred to as '%lN'. - * The 8 incoming registers are referred to as `%iN'. + * The 8 incoming registers are referred to as '%iN'. - * The frame pointer register `%i6' can be referenced using the alias - `%fp'. + * The frame pointer register '%i6' can be referenced using the alias + '%fp'. - * The stack pointer register `%o6' can be referenced using the alias - `%sp'. + * The stack pointer register '%o6' can be referenced using the alias + '%sp'. - Floating point registers are simply referred to as `%fN'. When + Floating point registers are simply referred to as '%fN'. When assembling for pre-V9, only 32 floating point registers are available. For V9 and later there are 64, but there are restrictions when -referencing the upper 32 registers. They can only be accessed as -double or quad, and thus only even or quad numbered accesses are -allowed. For example, `%f34' is a legal floating point register, but -`%f35' is not. +referencing the upper 32 registers. They can only be accessed as double +or quad, and thus only even or quad numbered accesses are allowed. For +example, '%f34' is a legal floating point register, but '%f35' is not. Certain V9 instructions allow access to ancillary state registers. -Most simply they can be referred to as `%asrN' where N can be from 16 -to 31. However, there are some aliases defined to reference ASR -registers defined for various UltraSPARC processors: +Most simply they can be referred to as '%asrN' where N can be from 16 to +31. However, there are some aliases defined to reference ASR registers +defined for various UltraSPARC processors: - * The tick compare register is referred to as `%tick_cmpr'. + * The tick compare register is referred to as '%tick_cmpr'. - * The system tick register is referred to as `%stick'. An alias, - `%sys_tick', exists but is deprecated and should not be used by - new software. + * The system tick register is referred to as '%stick'. An alias, + '%sys_tick', exists but is deprecated and should not be used by new + software. - * The system tick compare register is referred to as `%stick_cmpr'. - An alias, `%sys_tick_cmpr', exists but is deprecated and should - not be used by new software. + * The system tick compare register is referred to as '%stick_cmpr'. + An alias, '%sys_tick_cmpr', exists but is deprecated and should not + be used by new software. - * The software interrupt register is referred to as `%softint'. + * The software interrupt register is referred to as '%softint'. * The set software interrupt register is referred to as - `%set_softint'. The mnemonic `%softint_set' is provided as an + '%set_softint'. The mnemonic '%softint_set' is provided as an alias. * The clear software interrupt register is referred to as - `%clear_softint'. The mnemonic `%softint_clear' is provided as an + '%clear_softint'. The mnemonic '%softint_clear' is provided as an alias. * The performance instrumentation counters register is referred to as - `%pic'. + '%pic'. - * The performance control register is referred to as `%pcr'. + * The performance control register is referred to as '%pcr'. - * The graphics status register is referred to as `%gsr'. + * The graphics status register is referred to as '%gsr'. - * The V9 dispatch control register is referred to as `%dcr'. + * The V9 dispatch control register is referred to as '%dcr'. Various V9 branch and conditional move instructions allow specification of which set of integer condition codes to test. These -are referred to as `%xcc' and `%icc'. +are referred to as '%xcc' and '%icc'. In V9, there are 4 sets of floating point condition codes which are -referred to as `%fccN'. +referred to as '%fccN'. Several special privileged and non-privileged registers exist: - * The V9 address space identifier register is referred to as `%asi'. + * The V9 address space identifier register is referred to as '%asi'. - * The V9 restorable windows register is referred to as `%canrestore'. + * The V9 restorable windows register is referred to as '%canrestore'. - * The V9 savable windows register is referred to as `%cansave'. + * The V9 savable windows register is referred to as '%cansave'. - * The V9 clean windows register is referred to as `%cleanwin'. + * The V9 clean windows register is referred to as '%cleanwin'. - * The V9 current window pointer register is referred to as `%cwp'. + * The V9 current window pointer register is referred to as '%cwp'. - * The floating-point queue register is referred to as `%fq'. + * The floating-point queue register is referred to as '%fq'. - * The V8 co-processor queue register is referred to as `%cq'. + * The V8 co-processor queue register is referred to as '%cq'. - * The floating point status register is referred to as `%fsr'. + * The floating point status register is referred to as '%fsr'. - * The other windows register is referred to as `%otherwin'. + * The other windows register is referred to as '%otherwin'. - * The V9 program counter register is referred to as `%pc'. + * The V9 program counter register is referred to as '%pc'. - * The V9 next program counter register is referred to as `%npc'. + * The V9 next program counter register is referred to as '%npc'. - * The V9 processor interrupt level register is referred to as `%pil'. + * The V9 processor interrupt level register is referred to as '%pil'. - * The V9 processor state register is referred to as `%pstate'. + * The V9 processor state register is referred to as '%pstate'. - * The trap base address register is referred to as `%tba'. + * The trap base address register is referred to as '%tba'. - * The V9 tick register is referred to as `%tick'. + * The V9 tick register is referred to as '%tick'. - * The V9 trap level is referred to as `%tl'. + * The V9 trap level is referred to as '%tl'. - * The V9 trap program counter is referred to as `%tpc'. + * The V9 trap program counter is referred to as '%tpc'. - * The V9 trap next program counter is referred to as `%tnpc'. + * The V9 trap next program counter is referred to as '%tnpc'. - * The V9 trap state is referred to as `%tstate'. + * The V9 trap state is referred to as '%tstate'. - * The V9 trap type is referred to as `%tt'. + * The V9 trap type is referred to as '%tt'. - * The V9 condition codes is referred to as `%ccr'. + * The V9 condition codes is referred to as '%ccr'. - * The V9 floating-point registers state is referred to as `%fprs'. + * The V9 floating-point registers state is referred to as '%fprs'. - * The V9 version register is referred to as `%ver'. + * The V9 version register is referred to as '%ver'. - * The V9 window state register is referred to as `%wstate'. + * The V9 window state register is referred to as '%wstate'. - * The Y register is referred to as `%y'. + * The Y register is referred to as '%y'. - * The V8 window invalid mask register is referred to as `%wim'. + * The V8 window invalid mask register is referred to as '%wim'. - * The V8 processor state register is referred to as `%psr'. + * The V8 processor state register is referred to as '%psr'. - * The V9 global register level register is referred to as `%gl'. + * The V9 global register level register is referred to as '%gl'. Several special register names exist for hypervisor mode code: * The hyperprivileged processor state register is referred to as - `%hpstate'. + '%hpstate'. * The hyperprivileged trap state register is referred to as - `%htstate'. + '%htstate'. * The hyperprivileged interrupt pending register is referred to as - `%hintp'. + '%hintp'. * The hyperprivileged trap base address register is referred to as - `%htba'. + '%htba'. * The hyperprivileged implementation version register is referred to - as `%hver'. + as '%hver'. * The hyperprivileged system tick compare register is referred to as - `%hstick_cmpr'. Note that there is no `%hstick' register, the - normal `%stick' is used. + '%hstick_cmpr'. Note that there is no '%hstick' register, the + normal '%stick' is used. File: as.info, Node: Sparc-Constants, Next: Sparc-Relocs, Prev: Sparc-Regs, Up: Sparc-Syntax @@ -17489,93 +17344,92 @@ File: as.info, Node: Sparc-Constants, Next: Sparc-Relocs, Prev: Sparc-Regs, .................. Several Sparc instructions take an immediate operand field for which -mnemonic names exist. Two such examples are `membar' and `prefetch'. +mnemonic names exist. Two such examples are 'membar' and 'prefetch'. Another example are the set of V9 memory access instruction that allow specification of an address space identifier. - The `membar' instruction specifies a memory barrier that is the -defined by the operand which is a bitmask. The supported mask -mnemonics are: + The 'membar' instruction specifies a memory barrier that is the +defined by the operand which is a bitmask. The supported mask mnemonics +are: - * `#Sync' requests that all operations (including nonmemory - reference operations) appearing prior to the `membar' must have - been performed and the effects of any exceptions become visible - before any instructions after the `membar' may be initiated. This - corresponds to `membar' cmask field bit 2. + * '#Sync' requests that all operations (including nonmemory reference + operations) appearing prior to the 'membar' must have been + performed and the effects of any exceptions become visible before + any instructions after the 'membar' may be initiated. This + corresponds to 'membar' cmask field bit 2. - * `#MemIssue' requests that all memory reference operations - appearing prior to the `membar' must have been performed before - any memory operation after the `membar' may be initiated. This - corresponds to `membar' cmask field bit 1. + * '#MemIssue' requests that all memory reference operations appearing + prior to the 'membar' must have been performed before any memory + operation after the 'membar' may be initiated. This corresponds to + 'membar' cmask field bit 1. - * `#Lookaside' requests that a store appearing prior to the `membar' - must complete before any load following the `membar' referencing - the same address can be initiated. This corresponds to `membar' + * '#Lookaside' requests that a store appearing prior to the 'membar' + must complete before any load following the 'membar' referencing + the same address can be initiated. This corresponds to 'membar' cmask field bit 0. - * `#StoreStore' defines that the effects of all stores appearing - prior to the `membar' instruction must be visible to all - processors before the effect of any stores following the `membar'. - Equivalent to the deprecated `stbar' instruction. This - corresponds to `membar' mmask field bit 3. + * '#StoreStore' defines that the effects of all stores appearing + prior to the 'membar' instruction must be visible to all processors + before the effect of any stores following the 'membar'. Equivalent + to the deprecated 'stbar' instruction. This corresponds to + 'membar' mmask field bit 3. - * `#LoadStore' defines all loads appearing prior to the `membar' + * '#LoadStore' defines all loads appearing prior to the 'membar' instruction must have been performed before the effect of any - stores following the `membar' is visible to any other processor. - This corresponds to `membar' mmask field bit 2. + stores following the 'membar' is visible to any other processor. + This corresponds to 'membar' mmask field bit 2. - * `#StoreLoad' defines that the effects of all stores appearing - prior to the `membar' instruction must be visible to all - processors before loads following the `membar' may be performed. - This corresponds to `membar' mmask field bit 1. + * '#StoreLoad' defines that the effects of all stores appearing prior + to the 'membar' instruction must be visible to all processors + before loads following the 'membar' may be performed. This + corresponds to 'membar' mmask field bit 1. - * `#LoadLoad' defines that all loads appearing prior to the `membar' - instruction must have been performed before any loads following - the `membar' may be performed. This corresponds to `membar' mmask + * '#LoadLoad' defines that all loads appearing prior to the 'membar' + instruction must have been performed before any loads following the + 'membar' may be performed. This corresponds to 'membar' mmask field bit 0. - These values can be ored together, for example: membar #Sync membar #StoreLoad | #LoadLoad membar #StoreLoad | #StoreStore - The `prefetch' and `prefetcha' instructions take a prefetch function + The 'prefetch' and 'prefetcha' instructions take a prefetch function code. The following prefetch function code constant mnemonics are available: - * `#n_reads' requests a prefetch for several reads, and corresponds + * '#n_reads' requests a prefetch for several reads, and corresponds to a prefetch function code of 0. - `#one_read' requests a prefetch for one read, and corresponds to a + '#one_read' requests a prefetch for one read, and corresponds to a prefetch function code of 1. - `#n_writes' requests a prefetch for several writes (and possibly + '#n_writes' requests a prefetch for several writes (and possibly reads), and corresponds to a prefetch function code of 2. - `#one_write' requests a prefetch for one write, and corresponds to + '#one_write' requests a prefetch for one write, and corresponds to a prefetch function code of 3. - `#page' requests a prefetch page, and corresponds to a prefetch + '#page' requests a prefetch page, and corresponds to a prefetch function code of 4. - `#invalidate' requests a prefetch invalidate, and corresponds to a + '#invalidate' requests a prefetch invalidate, and corresponds to a prefetch function code of 16. - `#unified' requests a prefetch to the nearest unified cache, and + '#unified' requests a prefetch to the nearest unified cache, and corresponds to a prefetch function code of 17. - `#n_reads_strong' requests a strong prefetch for several reads, - and corresponds to a prefetch function code of 20. + '#n_reads_strong' requests a strong prefetch for several reads, and + corresponds to a prefetch function code of 20. - `#one_read_strong' requests a strong prefetch for one read, and + '#one_read_strong' requests a strong prefetch for one read, and corresponds to a prefetch function code of 21. - `#n_writes_strong' requests a strong prefetch for several writes, + '#n_writes_strong' requests a strong prefetch for several writes, and corresponds to a prefetch function code of 22. - `#one_write_strong' requests a strong prefetch for one write, and + '#one_write_strong' requests a strong prefetch for one write, and corresponds to a prefetch function code of 23. Onle one prefetch code may be specified. Here are some examples: @@ -17590,11 +17444,10 @@ available: function code, it will treat the prefetch instruction as a nop. For instructions that accept an immediate address space identifier, - `as' provides many mnemonics corresponding to V9 defined as well - as UltraSPARC and Niagara extended values. For example, `#ASI_P' - and `#ASI_BLK_INIT_QUAD_LDD_AIUS'. See the V9 and processor - specific manuals for details. - + 'as' provides many mnemonics corresponding to V9 defined as well as + UltraSPARC and Niagara extended values. For example, '#ASI_P' and + '#ASI_BLK_INIT_QUAD_LDD_AIUS'. See the V9 and processor specific + manuals for details. File: as.info, Node: Sparc-Relocs, Next: Sparc-Size-Translations, Prev: Sparc-Constants, Up: Sparc-Syntax @@ -17605,9 +17458,9 @@ File: as.info, Node: Sparc-Relocs, Next: Sparc-Size-Translations, Prev: Sparc ELF relocations are available as defined in the 32-bit and 64-bit Sparc ELF specifications. - `R_SPARC_HI22' is obtained using `%hi' and `R_SPARC_LO10' is -obtained using `%lo'. Likewise `R_SPARC_HIX22' is obtained from `%hix' -and `R_SPARC_LOX10' is obtained using `%lox'. For example: + 'R_SPARC_HI22' is obtained using '%hi' and 'R_SPARC_LO10' is obtained +using '%lo'. Likewise 'R_SPARC_HIX22' is obtained from '%hix' and +'R_SPARC_LOX10' is obtained using '%lox'. For example: sethi %hi(symbol), %g1 or %g1, %lo(symbol), %g1 @@ -17620,94 +17473,75 @@ and `R_SPARC_LOX10' is obtained using `%lox'. For example: V9 code model relocations can be requested as follows: - * `R_SPARC_HH22' is requested using `%hh'. It can also be generated - using `%uhi'. - - * `R_SPARC_HM10' is requested using `%hm'. It can also be generated - using `%ulo'. - - * `R_SPARC_LM22' is requested using `%lm'. - - * `R_SPARC_H44' is requested using `%h44'. + * 'R_SPARC_HH22' is requested using '%hh'. It can also be generated + using '%uhi'. + * 'R_SPARC_HM10' is requested using '%hm'. It can also be generated + using '%ulo'. + * 'R_SPARC_LM22' is requested using '%lm'. - * `R_SPARC_M44' is requested using `%m44'. + * 'R_SPARC_H44' is requested using '%h44'. + * 'R_SPARC_M44' is requested using '%m44'. + * 'R_SPARC_L44' is requested using '%l44' or '%l34'. + * 'R_SPARC_H34' is requested using '%h34'. - * `R_SPARC_L44' is requested using `%l44' or `%l34'. + The '%l34' generates a 'R_SPARC_L44' relocation because it calculates +the necessary value, and therefore no explicit 'R_SPARC_L34' relocation +needed to be created for this purpose. - * `R_SPARC_H34' is requested using `%h34'. - - The `%l34' generates a `R_SPARC_L44' relocation because it -calculates the necessary value, and therefore no explicit `R_SPARC_L34' -relocation needed to be created for this purpose. - - The `%h34' and `%l34' relocations are used for the abs34 code model. + The '%h34' and '%l34' relocations are used for the abs34 code model. Here is an example abs34 address generation sequence: sethi %h34(symbol), %g1 sllx %g1, 2, %g1 or %g1, %l34(symbol), %g1 - The PC relative relocation `R_SPARC_PC22' can be obtained by -enclosing an operand inside of `%pc22'. Likewise, the `R_SPARC_PC10' -relocation can be obtained using `%pc10'. These are mostly used when -assembling PIC code. For example, the standard PIC sequence on Sparc -to get the base of the global offset table, PC relative, into a -register, can be performed as: + The PC relative relocation 'R_SPARC_PC22' can be obtained by +enclosing an operand inside of '%pc22'. Likewise, the 'R_SPARC_PC10' +relocation can be obtained using '%pc10'. These are mostly used when +assembling PIC code. For example, the standard PIC sequence on Sparc to +get the base of the global offset table, PC relative, into a register, +can be performed as: sethi %pc22(_GLOBAL_OFFSET_TABLE_-4), %l7 add %l7, %pc10(_GLOBAL_OFFSET_TABLE_+4), %l7 Several relocations exist to allow the link editor to potentially -optimize GOT data references. The `R_SPARC_GOTDATA_OP_HIX22' -relocation can obtained by enclosing an operand inside of -`%gdop_hix22'. The `R_SPARC_GOTDATA_OP_LOX10' relocation can obtained -by enclosing an operand inside of `%gdop_lox10'. Likewise, -`R_SPARC_GOTDATA_OP' can be obtained by enclosing an operand inside of -`%gdop'. For example, assuming the GOT base is in register `%l7': +optimize GOT data references. The 'R_SPARC_GOTDATA_OP_HIX22' relocation +can obtained by enclosing an operand inside of '%gdop_hix22'. The +'R_SPARC_GOTDATA_OP_LOX10' relocation can obtained by enclosing an +operand inside of '%gdop_lox10'. Likewise, 'R_SPARC_GOTDATA_OP' can be +obtained by enclosing an operand inside of '%gdop'. For example, +assuming the GOT base is in register '%l7': sethi %gdop_hix22(symbol), %l1 xor %l1, %gdop_lox10(symbol), %l1 ld [%l7 + %l1], %l2, %gdop(symbol) - There are many relocations that can be requested for access to -thread local storage variables. All of the Sparc TLS mnemonics are -supported: - - * `R_SPARC_TLS_GD_HI22' is requested using `%tgd_hi22'. - - * `R_SPARC_TLS_GD_LO10' is requested using `%tgd_lo10'. - - * `R_SPARC_TLS_GD_ADD' is requested using `%tgd_add'. - - * `R_SPARC_TLS_GD_CALL' is requested using `%tgd_call'. - - * `R_SPARC_TLS_LDM_HI22' is requested using `%tldm_hi22'. + There are many relocations that can be requested for access to thread +local storage variables. All of the Sparc TLS mnemonics are supported: - * `R_SPARC_TLS_LDM_LO10' is requested using `%tldm_lo10'. + * 'R_SPARC_TLS_GD_HI22' is requested using '%tgd_hi22'. + * 'R_SPARC_TLS_GD_LO10' is requested using '%tgd_lo10'. + * 'R_SPARC_TLS_GD_ADD' is requested using '%tgd_add'. + * 'R_SPARC_TLS_GD_CALL' is requested using '%tgd_call'. - * `R_SPARC_TLS_LDM_ADD' is requested using `%tldm_add'. + * 'R_SPARC_TLS_LDM_HI22' is requested using '%tldm_hi22'. + * 'R_SPARC_TLS_LDM_LO10' is requested using '%tldm_lo10'. + * 'R_SPARC_TLS_LDM_ADD' is requested using '%tldm_add'. + * 'R_SPARC_TLS_LDM_CALL' is requested using '%tldm_call'. - * `R_SPARC_TLS_LDM_CALL' is requested using `%tldm_call'. + * 'R_SPARC_TLS_LDO_HIX22' is requested using '%tldo_hix22'. + * 'R_SPARC_TLS_LDO_LOX10' is requested using '%tldo_lox10'. + * 'R_SPARC_TLS_LDO_ADD' is requested using '%tldo_add'. - * `R_SPARC_TLS_LDO_HIX22' is requested using `%tldo_hix22'. + * 'R_SPARC_TLS_IE_HI22' is requested using '%tie_hi22'. + * 'R_SPARC_TLS_IE_LO10' is requested using '%tie_lo10'. + * 'R_SPARC_TLS_IE_LD' is requested using '%tie_ld'. + * 'R_SPARC_TLS_IE_LDX' is requested using '%tie_ldx'. + * 'R_SPARC_TLS_IE_ADD' is requested using '%tie_add'. - * `R_SPARC_TLS_LDO_LOX10' is requested using `%tldo_lox10'. - - * `R_SPARC_TLS_LDO_ADD' is requested using `%tldo_add'. - - * `R_SPARC_TLS_IE_HI22' is requested using `%tie_hi22'. - - * `R_SPARC_TLS_IE_LO10' is requested using `%tie_lo10'. - - * `R_SPARC_TLS_IE_LD' is requested using `%tie_ld'. - - * `R_SPARC_TLS_IE_LDX' is requested using `%tie_ldx'. - - * `R_SPARC_TLS_IE_ADD' is requested using `%tie_add'. - - * `R_SPARC_TLS_LE_HIX22' is requested using `%tle_hix22'. - - * `R_SPARC_TLS_LE_LOX10' is requested using `%tle_lox10'. + * 'R_SPARC_TLS_LE_HIX22' is requested using '%tle_hix22'. + * 'R_SPARC_TLS_LE_LOX10' is requested using '%tle_lox10'. Here are some example TLS model sequences. @@ -17751,7 +17585,7 @@ supported: When assembling for 64-bit, and a secondary constant addend is specified in an address expression that would normally generate an -`R_SPARC_LO10' relocation, the assembler will emit an `R_SPARC_OLO10' +'R_SPARC_LO10' relocation, the assembler will emit an 'R_SPARC_OLO10' instead. @@ -17761,14 +17595,14 @@ File: as.info, Node: Sparc-Size-Translations, Prev: Sparc-Relocs, Up: Sparc-S .......................... Often it is desirable to write code in an operand size agnostic manner. -`as' provides support for this via operand size opcode translations. +'as' provides support for this via operand size opcode translations. Translations are supported for loads, stores, shifts, compare-and-swap -atomics, and the `clr' synthetic instruction. +atomics, and the 'clr' synthetic instruction. - If generating 32-bit code, `as' will generate the 32-bit opcode. + If generating 32-bit code, 'as' will generate the 32-bit opcode. Whereas if 64-bit code is being generated, the 64-bit opcode will be -emitted. For example `ldn' will be transformed into `ld' for 32-bit -code and `ldx' for 64-bit code. +emitted. For example 'ldn' will be transformed into 'ld' for 32-bit +code and 'ldx' for 64-bit code. Here is an example meant to demonstrate all the supported opcode translations: @@ -17784,7 +17618,7 @@ translations: casna [%o0] %asi, %o1, %o2 clrn %g1 - In 32-bit mode `as' will emit: + In 32-bit mode 'as' will emit: ld [%o0], %o1 lda [%o0] %asi, %o2 @@ -17797,7 +17631,7 @@ translations: casa [%o0] %asi, %o1, %o2 clr %g1 - And in 64-bit mode `as' will emit: + And in 64-bit mode 'as' will emit: ldx [%o0], %o1 ldxa [%o0] %asi, %o2 @@ -17810,8 +17644,8 @@ translations: casxa [%o0] %asi, %o1, %o2 clrx %g1 - Finally, the `.nword' translating directive is supported as well. -It is documented in the section on Sparc machine directives. + Finally, the '.nword' translating directive is supported as well. It +is documented in the section on Sparc machine directives. File: as.info, Node: Sparc-Float, Next: Sparc-Directives, Prev: Sparc-Syntax, Up: Sparc-Dependent @@ -17827,57 +17661,57 @@ File: as.info, Node: Sparc-Directives, Prev: Sparc-Float, Up: Sparc-Dependent 9.41.5 Sparc Machine Directives ------------------------------- -The Sparc version of `as' supports the following additional machine +The Sparc version of 'as' supports the following additional machine directives: -`.align' +'.align' This must be followed by the desired alignment in bytes. -`.common' +'.common' This must be followed by a symbol name, a positive number, and - `"bss"'. This behaves somewhat like `.comm', but the syntax is + '"bss"'. This behaves somewhat like '.comm', but the syntax is different. -`.half' - This is functionally identical to `.short'. +'.half' + This is functionally identical to '.short'. -`.nword' - On the Sparc, the `.nword' directive produces native word sized - value, ie. if assembling with -32 it is equivalent to `.word', if - assembling with -64 it is equivalent to `.xword'. +'.nword' + On the Sparc, the '.nword' directive produces native word sized + value, ie. if assembling with -32 it is equivalent to '.word', if + assembling with -64 it is equivalent to '.xword'. -`.proc' +'.proc' This directive is ignored. Any text following it on the same line is also ignored. -`.register' +'.register' This directive declares use of a global application or system register. It must be followed by a register name %g2, %g3, %g6 or %g7, comma and the symbol name for that register. If symbol name - is `#scratch', it is a scratch register, if it is `#ignore', it + is '#scratch', it is a scratch register, if it is '#ignore', it just suppresses any errors about using undeclared global register, but does not emit any information about it into the object file. - This can be useful e.g. if you save the register before use and + This can be useful e.g. if you save the register before use and restore it after. -`.reserve' +'.reserve' This must be followed by a symbol name, a positive number, and - `"bss"'. This behaves somewhat like `.lcomm', but the syntax is + '"bss"'. This behaves somewhat like '.lcomm', but the syntax is different. -`.seg' - This must be followed by `"text"', `"data"', or `"data1"'. It - behaves like `.text', `.data', or `.data 1'. +'.seg' + This must be followed by '"text"', '"data"', or '"data1"'. It + behaves like '.text', '.data', or '.data 1'. -`.skip' - This is functionally identical to the `.space' directive. +'.skip' + This is functionally identical to the '.space' directive. -`.word' - On the Sparc, the `.word' directive produces 32 bit values, - instead of the 16 bit values it produces on many other machines. +'.word' + On the Sparc, the '.word' directive produces 32 bit values, instead + of the 16 bit values it produces on many other machines. -`.xword' - On the Sparc V9 processor, the `.xword' directive produces 64 bit +'.xword' + On the Sparc V9 processor, the '.xword' directive produces 64 bit values. @@ -17907,24 +17741,24 @@ File: as.info, Node: TIC54X-Opts, Next: TIC54X-Block, Up: TIC54X-Dependent 9.42.1 Options -------------- -The TMS320C54X version of `as' has a few machine-dependent options. +The TMS320C54X version of 'as' has a few machine-dependent options. - You can use the `-mfar-mode' option to enable extended addressing + You can use the '-mfar-mode' option to enable extended addressing mode. All addresses will be assumed to be > 16 bits, and the -appropriate relocation types will be used. This option is equivalent -to using the `.far_mode' directive in the assembly code. If you do not -use the `-mfar-mode' option, all references will be assumed to be 16 -bits. This option may be abbreviated to `-mf'. - - You can use the `-mcpu' option to specify a particular CPU. This -option is equivalent to using the `.version' directive in the assembly -code. For recognized CPU codes, see *Note `.version': -TIC54X-Directives. The default CPU version is `542'. - - You can use the `-merrors-to-file' option to redirect error output -to a file (this provided for those deficient environments which don't +appropriate relocation types will be used. This option is equivalent to +using the '.far_mode' directive in the assembly code. If you do not use +the '-mfar-mode' option, all references will be assumed to be 16 bits. +This option may be abbreviated to '-mf'. + + You can use the '-mcpu' option to specify a particular CPU. This +option is equivalent to using the '.version' directive in the assembly +code. For recognized CPU codes, see *Note '.version': +TIC54X-Directives. The default CPU version is '542'. + + You can use the '-merrors-to-file' option to redirect error output to +a file (this provided for those deficient environments which don't provide adequate output redirection). This option may be abbreviated to -`-me'. +'-me'. File: as.info, Node: TIC54X-Block, Next: TIC54X-Env, Prev: TIC54X-Opts, Up: TIC54X-Dependent @@ -17943,9 +17777,9 @@ File: as.info, Node: TIC54X-Env, Next: TIC54X-Constants, Prev: TIC54X-Block, 9.42.3 Environment Settings --------------------------- -`C54XDSP_DIR' and `A_DIR' are semicolon-separated paths which are added +'C54XDSP_DIR' and 'A_DIR' are semicolon-separated paths which are added to the list of directories normally searched for source and include -files. `C54XDSP_DIR' will override `A_DIR'. +files. 'C54XDSP_DIR' will override 'A_DIR'. File: as.info, Node: TIC54X-Constants, Next: TIC54X-Subsyms, Prev: TIC54X-Env, Up: TIC54X-Dependent @@ -17953,12 +17787,12 @@ File: as.info, Node: TIC54X-Constants, Next: TIC54X-Subsyms, Prev: TIC54X-Env 9.42.4 Constants Syntax ----------------------- -The TIC54X version of `as' allows the following additional constant +The TIC54X version of 'as' allows the following additional constant formats, using a suffix to indicate the radix: - Binary `000000B, 011000b' - Octal `10Q, 224q' - Hexadecimal `45h, 0FH' + Binary 000000B, 011000b + Octal 10Q, 224q + Hexadecimal 45h, 0FH File: as.info, Node: TIC54X-Subsyms, Next: TIC54X-Locals, Prev: TIC54X-Constants, Up: TIC54X-Dependent @@ -17968,18 +17802,18 @@ File: as.info, Node: TIC54X-Subsyms, Next: TIC54X-Locals, Prev: TIC54X-Consta A subset of allowable symbols (which we'll call subsyms) may be assigned arbitrary string values. This is roughly equivalent to C preprocessor -#define macros. When `as' encounters one of these symbols, the symbol +#define macros. When 'as' encounters one of these symbols, the symbol is replaced in the input stream by its string value. Subsym names *must* begin with a letter. - Subsyms may be defined using the `.asg' and `.eval' directives -(*Note `.asg': TIC54X-Directives, *Note `.eval': TIC54X-Directives. + Subsyms may be defined using the '.asg' and '.eval' directives (*Note +'.asg': TIC54X-Directives, *Note '.eval': TIC54X-Directives. - Expansion is recursive until a previously encountered symbol is -seen, at which point substitution stops. + Expansion is recursive until a previously encountered symbol is seen, +at which point substitution stops. - In this example, x is replaced with SYM2; SYM2 is replaced with -SYM1, and SYM1 is replaced with x. At this point, x has already been + In this example, x is replaced with SYM2; SYM2 is replaced with SYM1, +and SYM1 is replaced with x. At this point, x has already been encountered and the substitution stops. .asg "x",SYM1 @@ -17988,10 +17822,10 @@ encountered and the substitution stops. add x,a ; final code assembled is "add x, a" Macro parameters are converted to subsyms; a side effect of this is -the normal `as' '\ARG' dereferencing syntax is unnecessary. Subsyms -defined within a macro will have global scope, unless the `.var' -directive is used to identify the subsym as a local macro variable -*note `.var': TIC54X-Directives. +the normal 'as' '\ARG' dereferencing syntax is unnecessary. Subsyms +defined within a macro will have global scope, unless the '.var' +directive is used to identify the subsym as a local macro variable *note +'.var': TIC54X-Directives. Substitution may be forced in situations where replacement might be ambiguous by placing colons on either side of the subsym. The following @@ -18007,11 +17841,10 @@ code: Smaller parts of the string assigned to a subsym may be accessed with the following syntax: -``:SYMBOL(CHAR_INDEX):'' +':SYMBOL(CHAR_INDEX):' Evaluates to a single-character string, the character at CHAR_INDEX. - -``:SYMBOL(START,LENGTH):'' +':SYMBOL(START,LENGTH):' Evaluates to a substring of SYMBOL beginning at START with length LENGTH. @@ -18024,7 +17857,6 @@ File: as.info, Node: TIC54X-Locals, Next: TIC54X-Builtins, Prev: TIC54X-Subsy Local labels may be defined in two ways: * $N, where N is a decimal number between 0 and 9 - * LABEL?, where LABEL is any legal symbol name. Local labels thus defined may be redefined or automatically @@ -18032,12 +17864,9 @@ generated. The scope of a local label is based on when it may be undefined or reset. This happens when one of the following situations is encountered: - * .newblock directive *note `.newblock': TIC54X-Directives. - + * .newblock directive *note '.newblock': TIC54X-Directives. * The current section is changed (.sect, .text, or .data) - * Entering or leaving an included file - * The macro scope where the label was defined is exited @@ -18047,105 +17876,104 @@ File: as.info, Node: TIC54X-Builtins, Next: TIC54X-Ext, Prev: TIC54X-Locals, -------------------- The following built-in functions may be used to generate a -floating-point value. All return a floating-point value except `$cvi', -`$int', and `$sgn', which return an integer value. +floating-point value. All return a floating-point value except '$cvi', +'$int', and '$sgn', which return an integer value. -``$acos(EXPR)'' +'$acos(EXPR)' Returns the floating point arccosine of EXPR. -``$asin(EXPR)'' +'$asin(EXPR)' Returns the floating point arcsine of EXPR. -``$atan(EXPR)'' +'$atan(EXPR)' Returns the floating point arctangent of EXPR. -``$atan2(EXPR1,EXPR2)'' +'$atan2(EXPR1,EXPR2)' Returns the floating point arctangent of EXPR1 / EXPR2. -``$ceil(EXPR)'' +'$ceil(EXPR)' Returns the smallest integer not less than EXPR as floating point. -``$cosh(EXPR)'' +'$cosh(EXPR)' Returns the floating point hyperbolic cosine of EXPR. -``$cos(EXPR)'' +'$cos(EXPR)' Returns the floating point cosine of EXPR. -``$cvf(EXPR)'' +'$cvf(EXPR)' Returns the integer value EXPR converted to floating-point. -``$cvi(EXPR)'' +'$cvi(EXPR)' Returns the floating point value EXPR converted to integer. -``$exp(EXPR)'' +'$exp(EXPR)' Returns the floating point value e ^ EXPR. -``$fabs(EXPR)'' +'$fabs(EXPR)' Returns the floating point absolute value of EXPR. -``$floor(EXPR)'' +'$floor(EXPR)' Returns the largest integer that is not greater than EXPR as floating point. -``$fmod(EXPR1,EXPR2)'' +'$fmod(EXPR1,EXPR2)' Returns the floating point remainder of EXPR1 / EXPR2. -``$int(EXPR)'' +'$int(EXPR)' Returns 1 if EXPR evaluates to an integer, zero otherwise. -``$ldexp(EXPR1,EXPR2)'' +'$ldexp(EXPR1,EXPR2)' Returns the floating point value EXPR1 * 2 ^ EXPR2. -``$log10(EXPR)'' +'$log10(EXPR)' Returns the base 10 logarithm of EXPR. -``$log(EXPR)'' +'$log(EXPR)' Returns the natural logarithm of EXPR. -``$max(EXPR1,EXPR2)'' +'$max(EXPR1,EXPR2)' Returns the floating point maximum of EXPR1 and EXPR2. -``$min(EXPR1,EXPR2)'' +'$min(EXPR1,EXPR2)' Returns the floating point minimum of EXPR1 and EXPR2. -``$pow(EXPR1,EXPR2)'' +'$pow(EXPR1,EXPR2)' Returns the floating point value EXPR1 ^ EXPR2. -``$round(EXPR)'' +'$round(EXPR)' Returns the nearest integer to EXPR as a floating point number. -``$sgn(EXPR)'' +'$sgn(EXPR)' Returns -1, 0, or 1 based on the sign of EXPR. -``$sin(EXPR)'' +'$sin(EXPR)' Returns the floating point sine of EXPR. -``$sinh(EXPR)'' +'$sinh(EXPR)' Returns the floating point hyperbolic sine of EXPR. -``$sqrt(EXPR)'' +'$sqrt(EXPR)' Returns the floating point square root of EXPR. -``$tan(EXPR)'' +'$tan(EXPR)' Returns the floating point tangent of EXPR. -``$tanh(EXPR)'' +'$tanh(EXPR)' Returns the floating point hyperbolic tangent of EXPR. -``$trunc(EXPR)'' +'$trunc(EXPR)' Returns the integer value of EXPR truncated towards zero as floating point. - File: as.info, Node: TIC54X-Ext, Next: TIC54X-Directives, Prev: TIC54X-Builtins, Up: TIC54X-Dependent 9.42.8 Extended Addressing -------------------------- -The `LDX' pseudo-op is provided for loading the extended addressing bits -of a label or address. For example, if an address `_label' resides in -extended program memory, the value of `_label' may be loaded as follows: +The 'LDX' pseudo-op is provided for loading the extended addressing bits +of a label or address. For example, if an address '_label' resides in +extended program memory, the value of '_label' may be loaded as follows: ldx #_label,16,a ; loads extended bits of _label or #_label,a ; loads lower 16 bits of _label bacc a ; full address is in accumulator A @@ -18156,224 +17984,222 @@ File: as.info, Node: TIC54X-Directives, Next: TIC54X-Macros, Prev: TIC54X-Ext 9.42.9 Directives ----------------- -`.align [SIZE]' -`.even' +'.align [SIZE]' +'.even' Align the section program counter on the next boundary, based on - SIZE. SIZE may be any power of 2. `.even' is equivalent to - `.align' with a SIZE of 2. - `1' + SIZE. SIZE may be any power of 2. '.even' is equivalent to + '.align' with a SIZE of 2. + '1' Align SPC to word boundary - - `2' + '2' Align SPC to longword boundary (same as .even) - - `128' + '128' Align SPC to page boundary -`.asg STRING, NAME' +'.asg STRING, NAME' Assign NAME the string STRING. String replacement is performed on STRING before assignment. -`.eval STRING, NAME' +'.eval STRING, NAME' Evaluate the contents of string STRING and assign the result as a string to the subsym NAME. String replacement is performed on STRING before assignment. -`.bss SYMBOL, SIZE [, [BLOCKING_FLAG] [,ALIGNMENT_FLAG]]' +'.bss SYMBOL, SIZE [, [BLOCKING_FLAG] [,ALIGNMENT_FLAG]]' Reserve space for SYMBOL in the .bss section. SIZE is in words. If present, BLOCKING_FLAG indicates the allocated space should be aligned on a page boundary if it would otherwise cross a page boundary. If present, ALIGNMENT_FLAG causes the assembler to allocate SIZE on a long word boundary. -`.byte VALUE [,...,VALUE_N]' -`.ubyte VALUE [,...,VALUE_N]' -`.char VALUE [,...,VALUE_N]' -`.uchar VALUE [,...,VALUE_N]' +'.byte VALUE [,...,VALUE_N]' +'.ubyte VALUE [,...,VALUE_N]' +'.char VALUE [,...,VALUE_N]' +'.uchar VALUE [,...,VALUE_N]' Place one or more bytes into consecutive words of the current - section. The upper 8 bits of each word is zero-filled. If a - label is used, it points to the word allocated for the first byte + section. The upper 8 bits of each word is zero-filled. If a label + is used, it points to the word allocated for the first byte encountered. -`.clink ["SECTION_NAME"]' - Set STYP_CLINK flag for this section, which indicates to the - linker that if no symbols from this section are referenced, the - section should not be included in the link. If SECTION_NAME is - omitted, the current section is used. +'.clink ["SECTION_NAME"]' + Set STYP_CLINK flag for this section, which indicates to the linker + that if no symbols from this section are referenced, the section + should not be included in the link. If SECTION_NAME is omitted, + the current section is used. -`.c_mode' +'.c_mode' TBD. -`.copy "FILENAME" | FILENAME' -`.include "FILENAME" | FILENAME' +'.copy "FILENAME" | FILENAME' +'.include "FILENAME" | FILENAME' Read source statements from FILENAME. The normal include search path is used. Normally .copy will cause statements from the included file to be printed in the assembly listing and .include will not, but this distinction is not currently implemented. -`.data' +'.data' Begin assembling code into the .data section. -`.double VALUE [,...,VALUE_N]' -`.ldouble VALUE [,...,VALUE_N]' -`.float VALUE [,...,VALUE_N]' -`.xfloat VALUE [,...,VALUE_N]' - Place an IEEE single-precision floating-point representation of - one or more floating-point values into the current section. All - but `.xfloat' align the result on a longword boundary. Values are +'.double VALUE [,...,VALUE_N]' +'.ldouble VALUE [,...,VALUE_N]' +'.float VALUE [,...,VALUE_N]' +'.xfloat VALUE [,...,VALUE_N]' + Place an IEEE single-precision floating-point representation of one + or more floating-point values into the current section. All but + '.xfloat' align the result on a longword boundary. Values are stored most-significant word first. -`.drlist' -`.drnolist' +'.drlist' +'.drnolist' Control printing of directives to the listing file. Ignored. -`.emsg STRING' -`.mmsg STRING' -`.wmsg STRING' +'.emsg STRING' +'.mmsg STRING' +'.wmsg STRING' Emit a user-defined error, message, or warning, respectively. -`.far_mode' +'.far_mode' Use extended addressing when assembling statements. This should appear only once per file, and is equivalent to the -mfar-mode - option *note `-mfar-mode': TIC54X-Opts. + option *note '-mfar-mode': TIC54X-Opts. -`.fclist' -`.fcnolist' +'.fclist' +'.fcnolist' Control printing of false conditional blocks to the listing file. -`.field VALUE [,SIZE]' +'.field VALUE [,SIZE]' Initialize a bitfield of SIZE bits in the current section. If VALUE is relocatable, then SIZE must be 16. SIZE defaults to 16 bits. If VALUE does not fit into SIZE bits, the value will be - truncated. Successive `.field' directives will pack starting at + truncated. Successive '.field' directives will pack starting at the current word, filling the most significant bits first, and aligning to the start of the next word if the field size does not - fit into the space remaining in the current word. A `.align' - directive with an operand of 1 will force the next `.field' + fit into the space remaining in the current word. A '.align' + directive with an operand of 1 will force the next '.field' directive to begin packing into a new word. If a label is used, it points to the word that contains the specified field. -`.global SYMBOL [,...,SYMBOL_N]' -`.def SYMBOL [,...,SYMBOL_N]' -`.ref SYMBOL [,...,SYMBOL_N]' - `.def' nominally identifies a symbol defined in the current file - and available to other files. `.ref' identifies a symbol used in +'.global SYMBOL [,...,SYMBOL_N]' +'.def SYMBOL [,...,SYMBOL_N]' +'.ref SYMBOL [,...,SYMBOL_N]' + '.def' nominally identifies a symbol defined in the current file + and available to other files. '.ref' identifies a symbol used in the current file but defined elsewhere. Both map to the standard - `.global' directive. - -`.half VALUE [,...,VALUE_N]' -`.uhalf VALUE [,...,VALUE_N]' -`.short VALUE [,...,VALUE_N]' -`.ushort VALUE [,...,VALUE_N]' -`.int VALUE [,...,VALUE_N]' -`.uint VALUE [,...,VALUE_N]' -`.word VALUE [,...,VALUE_N]' -`.uword VALUE [,...,VALUE_N]' + '.global' directive. + +'.half VALUE [,...,VALUE_N]' +'.uhalf VALUE [,...,VALUE_N]' +'.short VALUE [,...,VALUE_N]' +'.ushort VALUE [,...,VALUE_N]' +'.int VALUE [,...,VALUE_N]' +'.uint VALUE [,...,VALUE_N]' +'.word VALUE [,...,VALUE_N]' +'.uword VALUE [,...,VALUE_N]' Place one or more values into consecutive words of the current section. If a label is used, it points to the word allocated for the first value encountered. -`.label SYMBOL' +'.label SYMBOL' Define a special SYMBOL to refer to the load time address of the current section program counter. -`.length' -`.width' +'.length' +'.width' Set the page length and width of the output listing file. Ignored. -`.list' -`.nolist' +'.list' +'.nolist' Control whether the source listing is printed. Ignored. -`.long VALUE [,...,VALUE_N]' -`.ulong VALUE [,...,VALUE_N]' -`.xlong VALUE [,...,VALUE_N]' +'.long VALUE [,...,VALUE_N]' +'.ulong VALUE [,...,VALUE_N]' +'.xlong VALUE [,...,VALUE_N]' Place one or more 32-bit values into consecutive words in the current section. The most significant word is stored first. - `.long' and `.ulong' align the result on a longword boundary; - `xlong' does not. - -`.loop [COUNT]' -`.break [CONDITION]' -`.endloop' - Repeatedly assemble a block of code. `.loop' begins the block, and - `.endloop' marks its termination. COUNT defaults to 1024, and + '.long' and '.ulong' align the result on a longword boundary; + 'xlong' does not. + +'.loop [COUNT]' +'.break [CONDITION]' +'.endloop' + Repeatedly assemble a block of code. '.loop' begins the block, and + '.endloop' marks its termination. COUNT defaults to 1024, and indicates the number of times the block should be repeated. - `.break' terminates the loop so that assembly begins after the - `.endloop' directive. The optional CONDITION will cause the loop + '.break' terminates the loop so that assembly begins after the + '.endloop' directive. The optional CONDITION will cause the loop to terminate only if it evaluates to zero. -`MACRO_NAME .macro [PARAM1][,...PARAM_N]' -`[.mexit]' -`.endm' +'MACRO_NAME .macro [PARAM1][,...PARAM_N]' +'[.mexit]' +'.endm' See the section on macros for more explanation (*Note TIC54X-Macros::. -`.mlib "FILENAME" | FILENAME' +'.mlib "FILENAME" | FILENAME' Load the macro library FILENAME. FILENAME must be an archived - library (BFD ar-compatible) of text files, expected to contain - only macro definitions. The standard include search path is used. + library (BFD ar-compatible) of text files, expected to contain only + macro definitions. The standard include search path is used. -`.mlist' -`.mnolist' +'.mlist' +'.mnolist' Control whether to include macro and loop block expansions in the listing output. Ignored. -`.mmregs' +'.mmregs' Define global symbolic names for the 'c54x registers. Supposedly - equivalent to executing `.set' directives for each register with + equivalent to executing '.set' directives for each register with its memory-mapped value, but in reality is provided only for compatibility and does nothing. -`.newblock' +'.newblock' This directive resets any TIC54X local labels currently defined. - Normal `as' local labels are unaffected. + Normal 'as' local labels are unaffected. -`.option OPTION_LIST' +'.option OPTION_LIST' Set listing options. Ignored. -`.sblock "SECTION_NAME" | SECTION_NAME [,"NAME_N" | NAME_N]' +'.sblock "SECTION_NAME" | SECTION_NAME [,"NAME_N" | NAME_N]' Designate SECTION_NAME for blocking. Blocking guarantees that a section will start on a page boundary (128 words) if it would otherwise cross a page boundary. Only initialized sections may be designated with this directive. See also *Note TIC54X-Block::. -`.sect "SECTION_NAME"' +'.sect "SECTION_NAME"' Define a named initialized section and make it the current section. -`SYMBOL .set "VALUE"' -`SYMBOL .equ "VALUE"' +'SYMBOL .set "VALUE"' +'SYMBOL .equ "VALUE"' Equate a constant VALUE to a SYMBOL, which is placed in the symbol table. SYMBOL may not be previously defined. -`.space SIZE_IN_BITS' -`.bes SIZE_IN_BITS' +'.space SIZE_IN_BITS' +'.bes SIZE_IN_BITS' Reserve the given number of bits in the current section and - zero-fill them. If a label is used with `.space', it points to the - *first* word reserved. With `.bes', the label points to the - *last* word reserved. + zero-fill them. If a label is used with '.space', it points to the + *first* word reserved. With '.bes', the label points to the *last* + word reserved. -`.sslist' -`.ssnolist' - Controls the inclusion of subsym replacement in the listing - output. Ignored. +'.sslist' +'.ssnolist' + Controls the inclusion of subsym replacement in the listing output. + Ignored. -`.string "STRING" [,...,"STRING_N"]' -`.pstring "STRING" [,...,"STRING_N"]' +'.string "STRING" [,...,"STRING_N"]' +'.pstring "STRING" [,...,"STRING_N"]' Place 8-bit characters from STRING into the current section. - `.string' zero-fills the upper 8 bits of each word, while - `.pstring' puts two characters into each word, filling the + '.string' zero-fills the upper 8 bits of each word, while + '.pstring' puts two characters into each word, filling the most-significant bits first. Unused space is zero-filled. If a label is used, it points to the first word initialized. -`[STAG] .struct [OFFSET]' -`[NAME_1] element [COUNT_1]' -`[NAME_2] element [COUNT_2]' -`[TNAME] .tag STAGX [TCOUNT]' -`...' -`[NAME_N] element [COUNT_N]' -`[SSIZE] .endstruct' -`LABEL .tag [STAG]' +'[STAG] .struct [OFFSET]' +'[NAME_1] element [COUNT_1]' +'[NAME_2] element [COUNT_2]' +'[TNAME] .tag STAGX [TCOUNT]' +'...' +'[NAME_N] element [COUNT_N]' +'[SSIZE] .endstruct' +'LABEL .tag [STAG]' Assign symbolic offsets to the elements of a structure. STAG defines a symbol to use to reference the structure. OFFSET indicates a starting value to use for the first element @@ -18381,62 +18207,62 @@ File: as.info, Node: TIC54X-Directives, Next: TIC54X-Macros, Prev: TIC54X-Ext a named offset, NAME, which is a symbol assigned the value of the element's offset into the structure. If STAG is missing, these become global symbols. COUNT adjusts the offset that many times, - as if `element' were an array. `element' may be one of `.byte', - `.word', `.long', `.float', or any equivalent of those, and the - structure offset is adjusted accordingly. `.field' and `.string' - are also allowed; the size of `.field' is one bit, and `.string' - is considered to be one word in size. Only element descriptors, - structure/union tags, `.align' and conditional assembly directives - are allowed within `.struct'/`.endstruct'. `.align' aligns member + as if 'element' were an array. 'element' may be one of '.byte', + '.word', '.long', '.float', or any equivalent of those, and the + structure offset is adjusted accordingly. '.field' and '.string' + are also allowed; the size of '.field' is one bit, and '.string' is + considered to be one word in size. Only element descriptors, + structure/union tags, '.align' and conditional assembly directives + are allowed within '.struct'/'.endstruct'. '.align' aligns member offsets to word boundaries only. SSIZE, if provided, will always be assigned the size of the structure. - The `.tag' directive, in addition to being used to define a + The '.tag' directive, in addition to being used to define a structure/union element within a structure, may be used to apply a structure to a symbol. Once applied to LABEL, the individual structure elements may be applied to LABEL to produce the desired offsets using LABEL as the structure base. -`.tab' +'.tab' Set the tab size in the output listing. Ignored. -`[UTAG] .union' -`[NAME_1] element [COUNT_1]' -`[NAME_2] element [COUNT_2]' -`[TNAME] .tag UTAGX[,TCOUNT]' -`...' -`[NAME_N] element [COUNT_N]' -`[USIZE] .endstruct' -`LABEL .tag [UTAG]' - Similar to `.struct', but the offset after each element is reset to +'[UTAG] .union' +'[NAME_1] element [COUNT_1]' +'[NAME_2] element [COUNT_2]' +'[TNAME] .tag UTAGX[,TCOUNT]' +'...' +'[NAME_N] element [COUNT_N]' +'[USIZE] .endstruct' +'LABEL .tag [UTAG]' + Similar to '.struct', but the offset after each element is reset to zero, and the USIZE is set to the maximum of all defined elements. Starting offset for the union is always zero. -`[SYMBOL] .usect "SECTION_NAME", SIZE, [,[BLOCKING_FLAG] [,ALIGNMENT_FLAG]]' +'[SYMBOL] .usect "SECTION_NAME", SIZE, [,[BLOCKING_FLAG] [,ALIGNMENT_FLAG]]' Reserve space for variables in a named, uninitialized section - (similar to .bss). `.usect' allows definitions sections + (similar to .bss). '.usect' allows definitions sections independent of .bss. SYMBOL points to the first location reserved by this allocation. The symbol may be used as a variable name. SIZE is the allocated size in words. BLOCKING_FLAG indicates - whether to block this section on a page boundary (128 words) - (*note TIC54X-Block::). ALIGNMENT FLAG indicates whether the - section should be longword-aligned. + whether to block this section on a page boundary (128 words) (*note + TIC54X-Block::). ALIGNMENT FLAG indicates whether the section + should be longword-aligned. -`.var SYM[,..., SYM_N]' +'.var SYM[,..., SYM_N]' Define a subsym to be a local variable within a macro. See *Note TIC54X-Macros::. -`.version VERSION' +'.version VERSION' Set which processor to build instructions for. Though the following values are accepted, the op is ignored. - `541' - `542' - `543' - `545' - `545LP' - `546LP' - `548' - `549' + '541' + '542' + '543' + '545' + '545LP' + '546LP' + '548' + '549' File: as.info, Node: TIC54X-Macros, Next: TIC54X-MMRegs, Prev: TIC54X-Directives, Up: TIC54X-Dependent @@ -18447,58 +18273,57 @@ File: as.info, Node: TIC54X-Macros, Next: TIC54X-MMRegs, Prev: TIC54X-Directi Macros do not require explicit dereferencing of arguments (i.e., \ARG). During macro expansion, the macro parameters are converted to -subsyms. If the number of arguments passed the macro invocation -exceeds the number of parameters defined, the last parameter is -assigned the string equivalent of all remaining arguments. If fewer -arguments are given than parameters, the missing parameters are -assigned empty strings. To include a comma in an argument, you must -enclose the argument in quotes. +subsyms. If the number of arguments passed the macro invocation exceeds +the number of parameters defined, the last parameter is assigned the +string equivalent of all remaining arguments. If fewer arguments are +given than parameters, the missing parameters are assigned empty +strings. To include a comma in an argument, you must enclose the +argument in quotes. The following built-in subsym functions allow examination of the string value of subsyms (or ordinary strings). The arguments are strings unless otherwise indicated (subsyms passed as args will be replaced by the strings they represent). -``$symlen(STR)'' +'$symlen(STR)' Returns the length of STR. -``$symcmp(STR1,STR2)'' +'$symcmp(STR1,STR2)' Returns 0 if STR1 == STR2, non-zero otherwise. -``$firstch(STR,CH)'' +'$firstch(STR,CH)' Returns index of the first occurrence of character constant CH in STR. -``$lastch(STR,CH)'' +'$lastch(STR,CH)' Returns index of the last occurrence of character constant CH in STR. -``$isdefed(SYMBOL)'' +'$isdefed(SYMBOL)' Returns zero if the symbol SYMBOL is not in the symbol table, non-zero otherwise. -``$ismember(SYMBOL,LIST)'' +'$ismember(SYMBOL,LIST)' Assign the first member of comma-separated string LIST to SYMBOL; - LIST is reassigned the remainder of the list. Returns zero if - LIST is a null string. Both arguments must be subsyms. + LIST is reassigned the remainder of the list. Returns zero if LIST + is a null string. Both arguments must be subsyms. -``$iscons(EXPR)'' - Returns 1 if string EXPR is binary, 2 if octal, 3 if hexadecimal, - 4 if a character, 5 if decimal, and zero if not an integer. +'$iscons(EXPR)' + Returns 1 if string EXPR is binary, 2 if octal, 3 if hexadecimal, 4 + if a character, 5 if decimal, and zero if not an integer. -``$isname(NAME)'' +'$isname(NAME)' Returns 1 if NAME is a valid symbol name, zero otherwise. -``$isreg(REG)'' +'$isreg(REG)' Returns 1 if REG is a valid predefined register name (AR0-AR7 only). -``$structsz(STAG)'' +'$structsz(STAG)' Returns the size of the structure or union represented by STAG. -``$structacc(STAG)'' +'$structacc(STAG)' Returns the reference point of the structure or union represented - by STAG. Always returns zero. - + by STAG. Always returns zero. File: as.info, Node: TIC54X-MMRegs, Next: TIC54X-Syntax, Prev: TIC54X-Macros, Up: TIC54X-Dependent @@ -18508,7 +18333,6 @@ File: as.info, Node: TIC54X-MMRegs, Next: TIC54X-Syntax, Prev: TIC54X-Macros, The following symbols are recognized as memory-mapped registers: - File: as.info, Node: TIC54X-Syntax, Prev: TIC54X-MMRegs, Up: TIC54X-Dependent @@ -18525,15 +18349,15 @@ File: as.info, Node: TIC54X-Chars, Up: TIC54X-Syntax 9.42.12.1 Special Characters ............................ -The presence of a `;' appearing anywhere on a line indicates the start +The presence of a ';' appearing anywhere on a line indicates the start of a comment that extends to the end of that line. - If a `#' appears as the first character of a line then the whole -line is treated as a comment, but in this case the line can also be a -logical line number directive (*note Comments::) or a preprocessor -control command (*note Preprocessing::). + If a '#' appears as the first character of a line then the whole line +is treated as a comment, but in this case the line can also be a logical +line number directive (*note Comments::) or a preprocessor control +command (*note Preprocessing::). - The presence of an asterisk (`*') at the start of a line also + The presence of an asterisk ('*') at the start of a line also indicates a comment that extends to the end of that line. The TIC54X assembler does not currently support a line separator @@ -18557,71 +18381,70 @@ File: as.info, Node: TIC6X Options, Next: TIC6X Syntax, Up: TIC6X-Dependent 9.43.1 TIC6X Options -------------------- -`-march=ARCH' - Enable (only) instructions from architecture ARCH. By default, - all instructions are permitted. +'-march=ARCH' + Enable (only) instructions from architecture ARCH. By default, all + instructions are permitted. - The following values of ARCH are accepted: `c62x', `c64x', - `c64x+', `c67x', `c67x+', `c674x'. + The following values of ARCH are accepted: 'c62x', 'c64x', 'c64x+', + 'c67x', 'c67x+', 'c674x'. -`-mdsbt' -`-mno-dsbt' - The `-mdsbt' option causes the assembler to generate the - `Tag_ABI_DSBT' attribute with a value of 1, indicating that the - code is using DSBT addressing. The `-mno-dsbt' option, the +'-mdsbt' +'-mno-dsbt' + The '-mdsbt' option causes the assembler to generate the + 'Tag_ABI_DSBT' attribute with a value of 1, indicating that the + code is using DSBT addressing. The '-mno-dsbt' option, the default, causes the tag to have a value of 0, indicating that the code does not use DSBT addressing. The linker will emit a warning if objects of different type (DSBT and non-DSBT) are linked together. -`-mpid=no' -`-mpid=near' -`-mpid=far' - The `-mpid=' option causes the assembler to generate the - `Tag_ABI_PID' attribute with a value indicating the form of data - addressing used by the code. `-mpid=no', the default, indicates - position-dependent data addressing, `-mpid=near' indicates +'-mpid=no' +'-mpid=near' +'-mpid=far' + The '-mpid=' option causes the assembler to generate the + 'Tag_ABI_PID' attribute with a value indicating the form of data + addressing used by the code. '-mpid=no', the default, indicates + position-dependent data addressing, '-mpid=near' indicates position-independent addressing with GOT accesses using near DP - addressing, and `-mpid=far' indicates position-independent + addressing, and '-mpid=far' indicates position-independent addressing with GOT accesses using far DP addressing. The linker will emit a warning if objects built with different settings of this option are linked together. -`-mpic' -`-mno-pic' - The `-mpic' option causes the assembler to generate the - `Tag_ABI_PIC' attribute with a value of 1, indicating that the - code is using position-independent code addressing, The - `-mno-pic' option, the default, causes the tag to have a value of - 0, indicating position-dependent code addressing. The linker will +'-mpic' +'-mno-pic' + The '-mpic' option causes the assembler to generate the + 'Tag_ABI_PIC' attribute with a value of 1, indicating that the code + is using position-independent code addressing, The '-mno-pic' + option, the default, causes the tag to have a value of 0, + indicating position-dependent code addressing. The linker will emit a warning if objects of different type (position-dependent and position-independent) are linked together. -`-mbig-endian' -`-mlittle-endian' +'-mbig-endian' +'-mlittle-endian' Generate code for the specified endianness. The default is little-endian. - File: as.info, Node: TIC6X Syntax, Next: TIC6X Directives, Prev: TIC6X Options, Up: TIC6X-Dependent 9.43.2 TIC6X Syntax ------------------- -The presence of a `;' on a line indicates the start of a comment that -extends to the end of the current line. If a `#' or `*' appears as the -first character of a line, the whole line is treated as a comment. -Note that if a line starts with a `#' character then it can also be a -logical line number directive (*note Comments::) or a preprocessor -control command (*note Preprocessing::). +The presence of a ';' on a line indicates the start of a comment that +extends to the end of the current line. If a '#' or '*' appears as the +first character of a line, the whole line is treated as a comment. Note +that if a line starts with a '#' character then it can also be a logical +line number directive (*note Comments::) or a preprocessor control +command (*note Preprocessing::). - The `@' character can be used instead of a newline to separate + The '@' character can be used instead of a newline to separate statements. Instruction, register and functional unit names are case-insensitive. -`as' requires fully-specified functional unit names, such as `.S1', -`.L1X' or `.D1T2', on all instructions using a functional unit. +'as' requires fully-specified functional unit names, such as '.S1', +'.L1X' or '.D1T2', on all instructions using a functional unit. For some instructions, there may be syntactic ambiguity between register or functional unit names and the names of labels or other @@ -18635,63 +18458,62 @@ File: as.info, Node: TIC6X Directives, Prev: TIC6X Syntax, Up: TIC6X-Dependen 9.43.3 TIC6X Directives ----------------------- -Directives controlling the set of instructions accepted by the -assembler have effect for instructions between the directive and any -subsequent directive overriding it. +Directives controlling the set of instructions accepted by the assembler +have effect for instructions between the directive and any subsequent +directive overriding it. -`.arch ARCH' - This has the same effect as `-march=ARCH'. +'.arch ARCH' + This has the same effect as '-march=ARCH'. -`.cantunwind' +'.cantunwind' Prevents unwinding through the current function. No personality routine or exception table data is required or permitted. If this is not specified then frame unwinding information will be - constructed from CFI directives. *note CFI directives::. + constructed from CFI directives. *note CFI directives::. -`.c6xabi_attribute TAG, VALUE' +'.c6xabi_attribute TAG, VALUE' Set the C6000 EABI build attribute TAG to VALUE. - The TAG is either an attribute number or one of `Tag_ISA', - `Tag_ABI_wchar_t', `Tag_ABI_stack_align_needed', - `Tag_ABI_stack_align_preserved', `Tag_ABI_DSBT', `Tag_ABI_PID', - `Tag_ABI_PIC', `TAG_ABI_array_object_alignment', - `TAG_ABI_array_object_align_expected', `Tag_ABI_compatibility' and - `Tag_ABI_conformance'. The VALUE is either a `number', - `"string"', or `number, "string"' depending on the tag. + The TAG is either an attribute number or one of 'Tag_ISA', + 'Tag_ABI_wchar_t', 'Tag_ABI_stack_align_needed', + 'Tag_ABI_stack_align_preserved', 'Tag_ABI_DSBT', 'Tag_ABI_PID', + 'Tag_ABI_PIC', 'TAG_ABI_array_object_alignment', + 'TAG_ABI_array_object_align_expected', 'Tag_ABI_compatibility' and + 'Tag_ABI_conformance'. The VALUE is either a 'number', '"string"', + or 'number, "string"' depending on the tag. -`.ehtype SYMBOL' +'.ehtype SYMBOL' Output an exception type table reference to SYMBOL. -`.endp' +'.endp' Marks the end of and exception table or function. If preceeded by - a `.handlerdata' directive then this also switched back to the + a '.handlerdata' directive then this also switched back to the previous text section. -`.handlerdata' +'.handlerdata' Marks the end of the current function, and the start of the exception table entry for that function. Anything between this - directive and the `.endp' directive will be added to the exception + directive and the '.endp' directive will be added to the exception table entry. - Must be preceded by a CFI block containing a `.cfi_lsda' directive. + Must be preceded by a CFI block containing a '.cfi_lsda' directive. -`.nocmp' +'.nocmp' Disallow use of C64x+ compact instructions in the current text section. -`.personalityindex INDEX' +'.personalityindex INDEX' Sets the personality routine for the current function to the ABI specified compact routine number INDEX -`.personality NAME' +'.personality NAME' Sets the personality routine for the current function to NAME. -`.scomm SYMBOL, SIZE, ALIGN' - Like `.comm', creating a common symbol SYMBOL with size SIZE and - alignment ALIGN, but unlike when using `.comm', this symbol will - be placed into the small BSS section by the linker. - +'.scomm SYMBOL, SIZE, ALIGN' + Like '.comm', creating a common symbol SYMBOL with size SIZE and + alignment ALIGN, but unlike when using '.comm', this symbol will be + placed into the small BSS section by the linker. File: as.info, Node: TILE-Gx-Dependent, Next: TILEPro-Dependent, Prev: TIC6X-Dependent, Up: Machine Dependencies @@ -18713,22 +18535,21 @@ File: as.info, Node: TILE-Gx Options, Next: TILE-Gx Syntax, Up: TILE-Gx-Depen The following table lists all available TILE-Gx specific options: -`-m32 | -m64' +'-m32 | -m64' Select the word size, either 32 bits or 64 bits. -`-EB | -EL' +'-EB | -EL' Select the endianness, either big-endian (-EB) or little-endian (-EL). - File: as.info, Node: TILE-Gx Syntax, Next: TILE-Gx Directives, Prev: TILE-Gx Options, Up: TILE-Gx-Dependent 9.44.2 Syntax ------------- -Block comments are delimited by `/*' and `*/'. End of line comments -may be introduced by `#'. +Block comments are delimited by '/*' and '*/'. End of line comments may +be introduced by '#'. Instructions consist of a leading opcode or macro name followed by whitespace and an optional comma-separated list of operands: @@ -18738,26 +18559,26 @@ whitespace and an optional comma-separated list of operands: Instructions must be separated by a newline or semicolon. There are two ways to write code: either write naked instructions, -which the assembler is free to combine into VLIW bundles, or specify -the VLIW bundles explicitly. +which the assembler is free to combine into VLIW bundles, or specify the +VLIW bundles explicitly. Bundles are specified using curly braces: { ADD r3,r4,r5 ; ADD r7,r8,r9 ; LW r10,r11 } - A bundle can span multiple lines. If you want to put multiple -instructions on a line, whether in a bundle or not, you need to -separate them with semicolons as in this example. + A bundle can span multiple lines. If you want to put multiple +instructions on a line, whether in a bundle or not, you need to separate +them with semicolons as in this example. A bundle may contain one or more instructions, up to the limit -specified by the ISA (currently three). If fewer instructions are +specified by the ISA (currently three). If fewer instructions are specified than the hardware supports in a bundle, the assembler inserts -`fnop' instructions automatically. +'fnop' instructions automatically. The assembler will prefer to preserve the ordering of instructions within the bundle, putting the first instruction in a lower-numbered pipeline than the next one, etc. This fact, combined with the optional -use of explicit `fnop' or `nop' instructions, allows precise control +use of explicit 'fnop' or 'nop' instructions, allows precise control over which pipeline executes each instruction. If the instructions cannot be bundled in the listed order, the @@ -18767,9 +18588,9 @@ reports an error. The assembler does not yet auto-bundle (automatically combine multiple instructions into one bundle), but it reserves the right to do -so in the future. If you want to force an instruction to run by -itself, put it in a bundle explicitly with curly braces and use `nop' -instructions (not `fnop') to fill the remaining pipeline slots in that +so in the future. If you want to force an instruction to run by itself, +put it in a bundle explicitly with curly braces and use 'nop' +instructions (not 'fnop') to fill the remaining pipeline slots in that bundle. * Menu: @@ -18785,7 +18606,7 @@ File: as.info, Node: TILE-Gx Opcodes, Next: TILE-Gx Registers, Up: TILE-Gx Sy ..................... For a complete list of opcodes and descriptions of their semantics, see -`TILE-Gx Instruction Set Architecture', available upon request at +'TILE-Gx Instruction Set Architecture', available upon request at www.tilera.com. @@ -18795,44 +18616,43 @@ File: as.info, Node: TILE-Gx Registers, Next: TILE-Gx Modifiers, Prev: TILE-G ....................... General-purpose registers are represented by predefined symbols of the -form `rN', where N represents a number between `0' and `63'. However, +form 'rN', where N represents a number between '0' and '63'. However, the following registers have canonical names that must be used instead: -`r54' +'r54' sp -`r55' +'r55' lr -`r56' +'r56' sn -`r57' +'r57' idn0 -`r58' +'r58' idn1 -`r59' +'r59' udn0 -`r60' +'r60' udn1 -`r61' +'r61' udn2 -`r62' +'r62' udn3 -`r63' +'r63' zero - The assembler will emit a warning if a numeric name is used instead -of the non-numeric name. The `.no_require_canonical_reg_names' +of the non-numeric name. The '.no_require_canonical_reg_names' assembler pseudo-op turns off this warning. -`.require_canonical_reg_names' turns it back on. +'.require_canonical_reg_names' turns it back on. File: as.info, Node: TILE-Gx Modifiers, Prev: TILE-Gx Registers, Up: TILE-Gx Syntax @@ -18847,28 +18667,35 @@ TILE-Gx instruction operands. The general syntax is the following: The following modifiers are supported: -`hw0' +'hw0' + This modifier is used to load bits 0-15 of the symbol's address. -`hw1' +'hw1' + This modifier is used to load bits 16-31 of the symbol's address. -`hw2' +'hw2' + This modifier is used to load bits 32-47 of the symbol's address. -`hw3' +'hw3' + This modifier is used to load bits 48-63 of the symbol's address. -`hw0_last' - This modifier yields the same value as `hw0', but it also checks +'hw0_last' + + This modifier yields the same value as 'hw0', but it also checks that the value does not overflow. -`hw1_last' - This modifier yields the same value as `hw1', but it also checks +'hw1_last' + + This modifier yields the same value as 'hw1', but it also checks that the value does not overflow. -`hw2_last' - This modifier yields the same value as `hw2', but it also checks +'hw2_last' + + This modifier yields the same value as 'hw2', but it also checks that the value does not overflow. A 48-bit symbolic value is constructed by using the following @@ -18878,135 +18705,153 @@ TILE-Gx instruction operands. The general syntax is the following: shl16insli r0, r0, hw1(sym) shl16insli r0, r0, hw0(sym) -`hw0_got' +'hw0_got' + This modifier is used to load bits 0-15 of the symbol's offset in the GOT entry corresponding to the symbol. -`hw0_last_got' - This modifier yields the same value as `hw0_got', but it also +'hw0_last_got' + + This modifier yields the same value as 'hw0_got', but it also checks that the value does not overflow. -`hw1_last_got' +'hw1_last_got' + This modifier is used to load bits 16-31 of the symbol's offset in the GOT entry corresponding to the symbol, and it also checks that the value does not overflow. -`plt' - This modifier is used for function symbols. It causes a - _procedure linkage table_, an array of code stubs, to be created - at the time the shared object is created or linked against, - together with a global offset table entry. The value is a - pc-relative offset to the corresponding stub code in the procedure - linkage table. This arrangement causes the run-time symbol - resolver to be called to look up and set the value of the symbol - the first time the function is called (at latest; depending - environment variables). It is only safe to leave the symbol - unresolved this way if all references are function calls. - -`hw0_plt' +'plt' + + This modifier is used for function symbols. It causes a _procedure + linkage table_, an array of code stubs, to be created at the time + the shared object is created or linked against, together with a + global offset table entry. The value is a pc-relative offset to + the corresponding stub code in the procedure linkage table. This + arrangement causes the run-time symbol resolver to be called to + look up and set the value of the symbol the first time the function + is called (at latest; depending environment variables). It is only + safe to leave the symbol unresolved this way if all references are + function calls. + +'hw0_plt' + This modifier is used to load bits 0-15 of the pc-relative address of a plt entry. -`hw1_plt' - This modifier is used to load bits 16-31 of the pc-relative - address of a plt entry. +'hw1_plt' + + This modifier is used to load bits 16-31 of the pc-relative address + of a plt entry. + +'hw1_last_plt' -`hw1_last_plt' - This modifier yields the same value as `hw1_plt', but it also + This modifier yields the same value as 'hw1_plt', but it also checks that the value does not overflow. -`hw2_last_plt' - This modifier is used to load bits 32-47 of the pc-relative - address of a plt entry, and it also checks that the value does not +'hw2_last_plt' + + This modifier is used to load bits 32-47 of the pc-relative address + of a plt entry, and it also checks that the value does not overflow. -`hw0_tls_gd' +'hw0_tls_gd' + This modifier is used to load bits 0-15 of the offset of the GOT entry of the symbol's TLS descriptor, to be used for general-dynamic TLS accesses. -`hw0_last_tls_gd' - This modifier yields the same value as `hw0_tls_gd', but it also +'hw0_last_tls_gd' + + This modifier yields the same value as 'hw0_tls_gd', but it also checks that the value does not overflow. -`hw1_last_tls_gd' +'hw1_last_tls_gd' + This modifier is used to load bits 16-31 of the offset of the GOT entry of the symbol's TLS descriptor, to be used for general-dynamic TLS accesses. It also checks that the value does not overflow. -`hw0_tls_ie' +'hw0_tls_ie' + This modifier is used to load bits 0-15 of the offset of the GOT entry containing the offset of the symbol's address from the TCB, to be used for initial-exec TLS accesses. -`hw0_last_tls_ie' - This modifier yields the same value as `hw0_tls_ie', but it also +'hw0_last_tls_ie' + + This modifier yields the same value as 'hw0_tls_ie', but it also checks that the value does not overflow. -`hw1_last_tls_ie' +'hw1_last_tls_ie' + This modifier is used to load bits 16-31 of the offset of the GOT entry containing the offset of the symbol's address from the TCB, to be used for initial-exec TLS accesses. It also checks that the value does not overflow. -`hw0_tls_le' +'hw0_tls_le' + This modifier is used to load bits 0-15 of the offset of the symbol's address from the TCB, to be used for local-exec TLS accesses. -`hw0_last_tls_le' - This modifier yields the same value as `hw0_tls_le', but it also +'hw0_last_tls_le' + + This modifier yields the same value as 'hw0_tls_le', but it also checks that the value does not overflow. -`hw1_last_tls_le' +'hw1_last_tls_le' + This modifier is used to load bits 16-31 of the offset of the symbol's address from the TCB, to be used for local-exec TLS accesses. It also checks that the value does not overflow. -`tls_gd_call' +'tls_gd_call' + This modifier is used to tag an instrution as the "call" part of a calling sequence for a TLS GD reference of its operand. -`tls_gd_add' +'tls_gd_add' + This modifier is used to tag an instruction as the "add" part of a calling sequence for a TLS GD reference of its operand. -`tls_ie_load' +'tls_ie_load' + This modifier is used to tag an instruction as the "load" part of a calling sequence for a TLS IE reference of its operand. - File: as.info, Node: TILE-Gx Directives, Prev: TILE-Gx Syntax, Up: TILE-Gx-Dependent 9.44.3 TILE-Gx Directives ------------------------- -`.align EXPRESSION [, EXPRESSION]' +'.align EXPRESSION [, EXPRESSION]' This is the generic .ALIGN directive. The first argument is the requested alignment in bytes. -`.allow_suspicious_bundles' +'.allow_suspicious_bundles' Turns on error checking for combinations of instructions in a bundle that probably indicate a programming error. This is on by default. -`.no_allow_suspicious_bundles' +'.no_allow_suspicious_bundles' Turns off error checking for combinations of instructions in a bundle that probably indicate a programming error. -`.require_canonical_reg_names' +'.require_canonical_reg_names' Require that canonical register names be used, and emit a warning if the numeric names are used. This is on by default. -`.no_require_canonical_reg_names' +'.no_require_canonical_reg_names' Permit the use of numeric names for registers that have canonical names. - -File: as.info, Node: TILEPro-Dependent, Next: V850-Dependent, Prev: TILE-Gx-Dependent, Up: Machine Dependencies +File: as.info, Node: TILEPro-Dependent, Next: Z80-Dependent, Prev: TILE-Gx-Dependent, Up: Machine Dependencies 9.45 TILEPro Dependent Features =============================== @@ -19023,7 +18868,7 @@ File: as.info, Node: TILEPro Options, Next: TILEPro Syntax, Up: TILEPro-Depen 9.45.1 Options -------------- -`as' has no machine-dependent command-line options for TILEPro. +'as' has no machine-dependent command-line options for TILEPro. File: as.info, Node: TILEPro Syntax, Next: TILEPro Directives, Prev: TILEPro Options, Up: TILEPro-Dependent @@ -19031,8 +18876,8 @@ File: as.info, Node: TILEPro Syntax, Next: TILEPro Directives, Prev: TILEPro 9.45.2 Syntax ------------- -Block comments are delimited by `/*' and `*/'. End of line comments -may be introduced by `#'. +Block comments are delimited by '/*' and '*/'. End of line comments may +be introduced by '#'. Instructions consist of a leading opcode or macro name followed by whitespace and an optional comma-separated list of operands: @@ -19042,26 +18887,26 @@ whitespace and an optional comma-separated list of operands: Instructions must be separated by a newline or semicolon. There are two ways to write code: either write naked instructions, -which the assembler is free to combine into VLIW bundles, or specify -the VLIW bundles explicitly. +which the assembler is free to combine into VLIW bundles, or specify the +VLIW bundles explicitly. Bundles are specified using curly braces: { ADD r3,r4,r5 ; ADD r7,r8,r9 ; LW r10,r11 } - A bundle can span multiple lines. If you want to put multiple -instructions on a line, whether in a bundle or not, you need to -separate them with semicolons as in this example. + A bundle can span multiple lines. If you want to put multiple +instructions on a line, whether in a bundle or not, you need to separate +them with semicolons as in this example. A bundle may contain one or more instructions, up to the limit -specified by the ISA (currently three). If fewer instructions are +specified by the ISA (currently three). If fewer instructions are specified than the hardware supports in a bundle, the assembler inserts -`fnop' instructions automatically. +'fnop' instructions automatically. The assembler will prefer to preserve the ordering of instructions within the bundle, putting the first instruction in a lower-numbered pipeline than the next one, etc. This fact, combined with the optional -use of explicit `fnop' or `nop' instructions, allows precise control +use of explicit 'fnop' or 'nop' instructions, allows precise control over which pipeline executes each instruction. If the instructions cannot be bundled in the listed order, the @@ -19071,9 +18916,9 @@ reports an error. The assembler does not yet auto-bundle (automatically combine multiple instructions into one bundle), but it reserves the right to do -so in the future. If you want to force an instruction to run by -itself, put it in a bundle explicitly with curly braces and use `nop' -instructions (not `fnop') to fill the remaining pipeline slots in that +so in the future. If you want to force an instruction to run by itself, +put it in a bundle explicitly with curly braces and use 'nop' +instructions (not 'fnop') to fill the remaining pipeline slots in that bundle. * Menu: @@ -19089,7 +18934,7 @@ File: as.info, Node: TILEPro Opcodes, Next: TILEPro Registers, Up: TILEPro Sy ..................... For a complete list of opcodes and descriptions of their semantics, see -`TILE Processor User Architecture Manual', available upon request at +'TILE Processor User Architecture Manual', available upon request at www.tilera.com. @@ -19099,43 +18944,42 @@ File: as.info, Node: TILEPro Registers, Next: TILEPro Modifiers, Prev: TILEPr ....................... General-purpose registers are represented by predefined symbols of the -form `rN', where N represents a number between `0' and `63'. However, +form 'rN', where N represents a number between '0' and '63'. However, the following registers have canonical names that must be used instead: -`r54' +'r54' sp -`r55' +'r55' lr -`r56' +'r56' sn -`r57' +'r57' idn0 -`r58' +'r58' idn1 -`r59' +'r59' udn0 -`r60' +'r60' udn1 -`r61' +'r61' udn2 -`r62' +'r62' udn3 -`r63' +'r63' zero - The assembler will emit a warning if a numeric name is used instead -of the canonical name. The `.no_require_canonical_reg_names' assembler -pseudo-op turns off this warning. `.require_canonical_reg_names' turns +of the canonical name. The '.no_require_canonical_reg_names' assembler +pseudo-op turns off this warning. '.require_canonical_reg_names' turns it back on. @@ -19151,152 +18995,173 @@ TILEPro instruction operands. The general syntax is the following: The following modifiers are supported: -`lo16' +'lo16' + This modifier is used to load the low 16 bits of the symbol's address, sign-extended to a 32-bit value (sign-extension allows it to be range-checked against signed 16 bit immediate operands without complaint). -`hi16' +'hi16' + This modifier is used to load the high 16 bits of the symbol's address, also sign-extended to a 32-bit value. -`ha16' - `ha16(N)' is identical to `hi16(N)', except if `lo16(N)' is - negative it adds one to the `hi16(N)' value. This way `lo16' and - `ha16' can be added to create any 32-bit value using `auli'. For +'ha16' + + 'ha16(N)' is identical to 'hi16(N)', except if 'lo16(N)' is + negative it adds one to the 'hi16(N)' value. This way 'lo16' and + 'ha16' can be added to create any 32-bit value using 'auli'. For example, here is how you move an arbitrary 32-bit address into r3: moveli r3, lo16(sym) auli r3, r3, ha16(sym) -`got' +'got' + This modifier is used to load the offset of the GOT entry corresponding to the symbol. -`got_lo16' +'got_lo16' + This modifier is used to load the sign-extended low 16 bits of the offset of the GOT entry corresponding to the symbol. -`got_hi16' +'got_hi16' + This modifier is used to load the sign-extended high 16 bits of the offset of the GOT entry corresponding to the symbol. -`got_ha16' - This modifier is like `got_hi16', but it adds one if `got_lo16' of +'got_ha16' + + This modifier is like 'got_hi16', but it adds one if 'got_lo16' of the input value is negative. -`plt' - This modifier is used for function symbols. It causes a - _procedure linkage table_, an array of code stubs, to be created - at the time the shared object is created or linked against, - together with a global offset table entry. The value is a - pc-relative offset to the corresponding stub code in the procedure - linkage table. This arrangement causes the run-time symbol - resolver to be called to look up and set the value of the symbol - the first time the function is called (at latest; depending - environment variables). It is only safe to leave the symbol - unresolved this way if all references are function calls. - -`tls_gd' +'plt' + + This modifier is used for function symbols. It causes a _procedure + linkage table_, an array of code stubs, to be created at the time + the shared object is created or linked against, together with a + global offset table entry. The value is a pc-relative offset to + the corresponding stub code in the procedure linkage table. This + arrangement causes the run-time symbol resolver to be called to + look up and set the value of the symbol the first time the function + is called (at latest; depending environment variables). It is only + safe to leave the symbol unresolved this way if all references are + function calls. + +'tls_gd' + This modifier is used to load the offset of the GOT entry of the symbol's TLS descriptor, to be used for general-dynamic TLS accesses. -`tls_gd_lo16' +'tls_gd_lo16' + This modifier is used to load the sign-extended low 16 bits of the offset of the GOT entry of the symbol's TLS descriptor, to be used for general dynamic TLS accesses. -`tls_gd_hi16' +'tls_gd_hi16' + This modifier is used to load the sign-extended high 16 bits of the offset of the GOT entry of the symbol's TLS descriptor, to be used for general dynamic TLS accesses. -`tls_gd_ha16' - This modifier is like `tls_gd_hi16', but it adds one to the value - if `tls_gd_lo16' of the input value is negative. +'tls_gd_ha16' + + This modifier is like 'tls_gd_hi16', but it adds one to the value + if 'tls_gd_lo16' of the input value is negative. + +'tls_ie' -`tls_ie' This modifier is used to load the offset of the GOT entry containing the offset of the symbol's address from the TCB, to be used for initial-exec TLS accesses. -`tls_ie_lo16' +'tls_ie_lo16' + This modifier is used to load the low 16 bits of the offset of the GOT entry containing the offset of the symbol's address from the TCB, to be used for initial-exec TLS accesses. -`tls_ie_hi16' +'tls_ie_hi16' + This modifier is used to load the high 16 bits of the offset of the GOT entry containing the offset of the symbol's address from the TCB, to be used for initial-exec TLS accesses. -`tls_ie_ha16' - This modifier is like `tls_ie_hi16', but it adds one to the value - if `tls_ie_lo16' of the input value is negative. +'tls_ie_ha16' + + This modifier is like 'tls_ie_hi16', but it adds one to the value + if 'tls_ie_lo16' of the input value is negative. + +'tls_le' -`tls_le' This modifier is used to load the offset of the symbol's address from the TCB, to be used for local-exec TLS accesses. -`tls_le_lo16' +'tls_le_lo16' + This modifier is used to load the low 16 bits of the offset of the symbol's address from the TCB, to be used for local-exec TLS accesses. -`tls_le_hi16' +'tls_le_hi16' + This modifier is used to load the high 16 bits of the offset of the symbol's address from the TCB, to be used for local-exec TLS accesses. -`tls_le_ha16' - This modifier is like `tls_le_hi16', but it adds one to the value - if `tls_le_lo16' of the input value is negative. +'tls_le_ha16' + + This modifier is like 'tls_le_hi16', but it adds one to the value + if 'tls_le_lo16' of the input value is negative. + +'tls_gd_call' -`tls_gd_call' This modifier is used to tag an instrution as the "call" part of a calling sequence for a TLS GD reference of its operand. -`tls_gd_add' +'tls_gd_add' + This modifier is used to tag an instruction as the "add" part of a calling sequence for a TLS GD reference of its operand. -`tls_ie_load' +'tls_ie_load' + This modifier is used to tag an instruction as the "load" part of a calling sequence for a TLS IE reference of its operand. - File: as.info, Node: TILEPro Directives, Prev: TILEPro Syntax, Up: TILEPro-Dependent 9.45.3 TILEPro Directives ------------------------- -`.align EXPRESSION [, EXPRESSION]' +'.align EXPRESSION [, EXPRESSION]' This is the generic .ALIGN directive. The first argument is the requested alignment in bytes. -`.allow_suspicious_bundles' +'.allow_suspicious_bundles' Turns on error checking for combinations of instructions in a bundle that probably indicate a programming error. This is on by default. -`.no_allow_suspicious_bundles' +'.no_allow_suspicious_bundles' Turns off error checking for combinations of instructions in a bundle that probably indicate a programming error. -`.require_canonical_reg_names' +'.require_canonical_reg_names' Require that canonical register names be used, and emit a warning if the numeric names are used. This is on by default. -`.no_require_canonical_reg_names' +'.no_require_canonical_reg_names' Permit the use of numeric names for registers that have canonical names. - -File: as.info, Node: Z80-Dependent, Next: Z8000-Dependent, Prev: Xtensa-Dependent, Up: Machine Dependencies +File: as.info, Node: Z80-Dependent, Next: Z8000-Dependent, Prev: TILEPro-Dependent, Up: Machine Dependencies 9.46 Z80 Dependent Features =========================== @@ -19315,46 +19180,40 @@ File: as.info, Node: Z80 Options, Next: Z80 Syntax, Up: Z80-Dependent 9.46.1 Options -------------- -The Zilog Z80 and Ascii R800 version of `as' have a few machine +The Zilog Z80 and Ascii R800 version of 'as' have a few machine dependent options. -`-z80' - Produce code for the Z80 processor. There are additional options to - request warnings and error messages for undocumented instructions. - -`-ignore-undocumented-instructions' -`-Wnud' +'-z80' + Produce code for the Z80 processor. There are additional options + to request warnings and error messages for undocumented + instructions. +'-ignore-undocumented-instructions' +'-Wnud' Silently assemble undocumented Z80-instructions that have been adopted as documented R800-instructions. - -`-ignore-unportable-instructions' -`-Wnup' +'-ignore-unportable-instructions' +'-Wnup' Silently assemble all undocumented Z80-instructions. - -`-warn-undocumented-instructions' -`-Wud' - Issue warnings for undocumented Z80-instructions that work on - R800, do not assemble other undocumented instructions without - warning. - -`-warn-unportable-instructions' -`-Wup' +'-warn-undocumented-instructions' +'-Wud' + Issue warnings for undocumented Z80-instructions that work on R800, + do not assemble other undocumented instructions without warning. +'-warn-unportable-instructions' +'-Wup' Issue warnings for other undocumented Z80-instructions, do not treat any undocumented instructions as errors. - -`-forbid-undocumented-instructions' -`-Fud' +'-forbid-undocumented-instructions' +'-Fud' Treat all undocumented z80-instructions as errors. - -`-forbid-unportable-instructions' -`-Fup' +'-forbid-unportable-instructions' +'-Fup' Treat undocumented z80-instructions that do not work on R800 as errors. -`-r800' - Produce code for the R800 processor. The assembler does not support - undocumented instructions for the R800. In line with common - practice, `as' uses Z80 instruction names for the R800 processor, - as far as they exist. +'-r800' + Produce code for the R800 processor. The assembler does not + support undocumented instructions for the R800. In line with + common practice, 'as' uses Z80 instruction names for the R800 + processor, as far as they exist. File: as.info, Node: Z80 Syntax, Next: Z80 Floating Point, Prev: Z80 Options, Up: Z80-Dependent @@ -19363,14 +19222,14 @@ File: as.info, Node: Z80 Syntax, Next: Z80 Floating Point, Prev: Z80 Options, ------------- The assembler syntax closely follows the 'Z80 family CPU User Manual' by -Zilog. In expressions a single `=' may be used as "is equal to" +Zilog. In expressions a single '=' may be used as "is equal to" comparison operator. - Suffices can be used to indicate the radix of integer constants; `H' -or `h' for hexadecimal, `D' or `d' for decimal, `Q', `O', `q' or `o' -for octal, and `B' for binary. + Suffices can be used to indicate the radix of integer constants; 'H' +or 'h' for hexadecimal, 'D' or 'd' for decimal, 'Q', 'O', 'q' or 'o' for +octal, and 'B' for binary. - The suffix `b' denotes a backreference to local label. + The suffix 'b' denotes a backreference to local label. * Menu: @@ -19384,21 +19243,21 @@ File: as.info, Node: Z80-Chars, Next: Z80-Regs, Up: Z80 Syntax 9.46.2.1 Special Characters ........................... -The semicolon `;' is the line comment character; +The semicolon ';' is the line comment character; - If a `#' appears as the first character of a line then the whole -line is treated as a comment, but in this case the line could also be a + If a '#' appears as the first character of a line then the whole line +is treated as a comment, but in this case the line could also be a logical line number directive (*note Comments::) or a preprocessor control command (*note Preprocessing::). The Z80 assembler does not support a line separator character. - The dollar sign `$' can be used as a prefix for hexadecimal numbers + The dollar sign '$' can be used as a prefix for hexadecimal numbers and as a symbol denoting the current location counter. - A backslash `\' is an ordinary character for the Z80 assembler. + A backslash '\' is an ordinary character for the Z80 assembler. - The single quote `'' must be followed by a closing quote. If there + The single quote ''' must be followed by a closing quote. If there is one character in between, it is a character constant, otherwise it is a string constant. @@ -19409,9 +19268,9 @@ File: as.info, Node: Z80-Regs, Next: Z80-Case, Prev: Z80-Chars, Up: Z80 Synt ....................... The registers are referred to with the letters assigned to them by -Zilog. In addition `as' recognizes `ixl' and `ixh' as the least and -most significant octet in `ix', and similarly `iyl' and `iyh' as parts -of `iy'. +Zilog. In addition 'as' recognizes 'ixl' and 'ixh' as the least and +most significant octet in 'ix', and similarly 'iyl' and 'iyh' as parts +of 'iy'. File: as.info, Node: Z80-Case, Prev: Z80-Regs, Up: Z80 Syntax @@ -19420,10 +19279,10 @@ File: as.info, Node: Z80-Case, Prev: Z80-Regs, Up: Z80 Syntax ......................... Upper and lower case are equivalent in register names, opcodes, -condition codes and assembler directives. The case of letters is -significant in labels and symbol names. The case is also important to -distinguish the suffix `b' for a backward reference to a local label -from the suffix `B' for a number in binary notation. +condition codes and assembler directives. The case of letters is +significant in labels and symbol names. The case is also important to +distinguish the suffix 'b' for a backward reference to a local label +from the suffix 'B' for a number in binary notation. File: as.info, Node: Z80 Floating Point, Next: Z80 Directives, Prev: Z80 Syntax, Up: Z80-Dependent @@ -19439,51 +19298,50 @@ File: as.info, Node: Z80 Directives, Next: Z80 Opcodes, Prev: Z80 Floating Po 9.46.4 Z80 Assembler Directives ------------------------------- -`as' for the Z80 supports some additional directives for compatibility +'as' for the Z80 supports some additional directives for compatibility with other assemblers. - These are the additional directives in `as' for the Z80: + These are the additional directives in 'as' for the Z80: -`db EXPRESSION|STRING[,EXPRESSION|STRING...]' -`defb EXPRESSION|STRING[,EXPRESSION|STRING...]' +'db EXPRESSION|STRING[,EXPRESSION|STRING...]' +'defb EXPRESSION|STRING[,EXPRESSION|STRING...]' For each STRING the characters are copied to the object file, for each other EXPRESSION the value is stored in one byte. A warning is issued in case of an overflow. -`dw EXPRESSION[,EXPRESSION...]' -`defw EXPRESSION[,EXPRESSION...]' +'dw EXPRESSION[,EXPRESSION...]' +'defw EXPRESSION[,EXPRESSION...]' For each EXPRESSION the value is stored in two bytes, ignoring overflow. -`d24 EXPRESSION[,EXPRESSION...]' -`def24 EXPRESSION[,EXPRESSION...]' +'d24 EXPRESSION[,EXPRESSION...]' +'def24 EXPRESSION[,EXPRESSION...]' For each EXPRESSION the value is stored in three bytes, ignoring overflow. -`d32 EXPRESSION[,EXPRESSION...]' -`def32 EXPRESSION[,EXPRESSION...]' +'d32 EXPRESSION[,EXPRESSION...]' +'def32 EXPRESSION[,EXPRESSION...]' For each EXPRESSION the value is stored in four bytes, ignoring overflow. -`ds COUNT[, VALUE]' -`defs COUNT[, VALUE]' - Fill COUNT bytes in the object file with VALUE, if VALUE is - omitted it defaults to zero. +'ds COUNT[, VALUE]' +'defs COUNT[, VALUE]' + Fill COUNT bytes in the object file with VALUE, if VALUE is omitted + it defaults to zero. -`SYMBOL equ EXPRESSION' -`SYMBOL defl EXPRESSION' - These directives set the value of SYMBOL to EXPRESSION. If `equ' +'SYMBOL equ EXPRESSION' +'SYMBOL defl EXPRESSION' + These directives set the value of SYMBOL to EXPRESSION. If 'equ' is used, it is an error if SYMBOL is already defined. Symbols - defined with `equ' are not protected from redefinition. + defined with 'equ' are not protected from redefinition. -`set' +'set' This is a normal instruction on Z80, and not an assembler directive. -`psect NAME' +'psect NAME' A synonym for *Note Section::, no second argument should be given. - File: as.info, Node: Z80 Opcodes, Prev: Z80 Directives, Up: Z80-Dependent @@ -19494,36 +19352,36 @@ In line with common practice, Z80 mnemonics are used for both the Z80 and the R800. In many instructions it is possible to use one of the half index -registers (`ixl',`ixh',`iyl',`iyh') in stead of an 8-bit general -purpose register. This yields instructions that are documented on the -R800 and undocumented on the Z80. Similarly `in f,(c)' is documented -on the R800 and undocumented on the Z80. +registers ('ixl','ixh','iyl','iyh') in stead of an 8-bit general purpose +register. This yields instructions that are documented on the R800 and +undocumented on the Z80. Similarly 'in f,(c)' is documented on the R800 +and undocumented on the Z80. The assembler also supports the following undocumented Z80-instructions, that have not been adopted in the R800 instruction set: -`out (c),0' +'out (c),0' Sends zero to the port pointed to by register c. -`sli M' - Equivalent to `M = (M<<1)+1', the operand M can be any operand - that is valid for `sla'. One can use `sll' as a synonym for `sli'. +'sli M' + Equivalent to 'M = (M<<1)+1', the operand M can be any operand that + is valid for 'sla'. One can use 'sll' as a synonym for 'sli'. -`OP (ix+D), R' +'OP (ix+D), R' This is equivalent to ld R, (ix+D) OPC R ld (ix+D), R - The operation `OPC' may be any of `res B,', `set B,', `rl', `rlc', - `rr', `rrc', `sla', `sli', `sra' and `srl', and the register `R' - may be any of `a', `b', `c', `d', `e', `h' and `l'. + The operation 'OPC' may be any of 'res B,', 'set B,', 'rl', 'rlc', + 'rr', 'rrc', 'sla', 'sli', 'sra' and 'srl', and the register 'R' + may be any of 'a', 'b', 'c', 'd', 'e', 'h' and 'l'. -`OPC (iy+D), R' - As above, but with `iy' instead of `ix'. +'OPC (iy+D), R' + As above, but with 'iy' instead of 'ix'. - The web site at `http://www.z80.info' is a good starting place to + The web site at <http://www.z80.info> is a good starting place to find more information on programming the Z80. @@ -19532,14 +19390,14 @@ File: as.info, Node: Z8000-Dependent, Next: Vax-Dependent, Prev: Z80-Dependen 9.47 Z8000 Dependent Features ============================= - The Z8000 as supports both members of the Z8000 family: the -unsegmented Z8002, with 16 bit addresses, and the segmented Z8001 with -24 bit addresses. +The Z8000 as supports both members of the Z8000 family: the unsegmented +Z8002, with 16 bit addresses, and the segmented Z8001 with 24 bit +addresses. When the assembler is in unsegmented mode (specified with the -`unsegm' directive), an address takes up one word (16 bit) sized +'unsegm' directive), an address takes up one word (16 bit) sized register. When the assembler is in segmented mode (specified with the -`segm' directive), a 24-bit address takes up a long (32 bit) register. +'segm' directive), a 24-bit address takes up a long (32 bit) register. *Note Assembler Directives for the Z8000: Z8000 Directives, for a list of other Z8000 specific assembler directives. @@ -19556,10 +19414,10 @@ File: as.info, Node: Z8000 Options, Next: Z8000 Syntax, Up: Z8000-Dependent 9.47.1 Options -------------- -`-z8001' +'-z8001' Generate segmented code by default. -`-z8002' +'-z8002' Generate unsegmented code by default. @@ -19580,14 +19438,14 @@ File: as.info, Node: Z8000-Chars, Next: Z8000-Regs, Up: Z8000 Syntax 9.47.2.1 Special Characters ........................... -`!' is the line comment character. +'!' is the line comment character. - If a `#' appears as the first character of a line then the whole -line is treated as a comment, but in this case the line could also be a + If a '#' appears as the first character of a line then the whole line +is treated as a comment, but in this case the line could also be a logical line number directive (*note Comments::) or a preprocessor control command (*note Preprocessing::). - You can use `;' instead of a newline to separate statements. + You can use ';' instead of a newline to separate statements. File: as.info, Node: Z8000-Regs, Next: Z8000-Addressing, Prev: Z8000-Chars, Up: Z8000 Syntax @@ -19597,10 +19455,10 @@ File: as.info, Node: Z8000-Regs, Next: Z8000-Addressing, Prev: Z8000-Chars, The Z8000 has sixteen 16 bit registers, numbered 0 to 15. You can refer to different sized groups of registers by register number, with the -prefix `r' for 16 bit registers, `rr' for 32 bit registers and `rq' for -64 bit registers. You can also refer to the contents of the first -eight (of the sixteen 16 bit registers) by bytes. They are named `rlN' -and `rhN'. +prefix 'r' for 16 bit registers, 'rr' for 32 bit registers and 'rq' for +64 bit registers. You can also refer to the contents of the first eight +(of the sixteen 16 bit registers) by bytes. They are named 'rlN' and +'rhN'. _byte registers_ rl0 rh0 rl1 rh1 rl2 rh2 rl3 rh3 @@ -19623,40 +19481,39 @@ File: as.info, Node: Z8000-Addressing, Prev: Z8000-Regs, Up: Z8000 Syntax as understands the following addressing modes for the Z8000: -`rlN' -`rhN' -`rN' -`rrN' -`rqN' - Register direct: 8bit, 16bit, 32bit, and 64bit registers. +'rlN' +'rhN' +'rN' +'rrN' +'rqN' + Register direct: 8bit, 16bit, 32bit, and 64bit registers. -`@rN' -`@rrN' - Indirect register: @rrN in segmented mode, @rN in unsegmented - mode. +'@rN' +'@rrN' + Indirect register: @rrN in segmented mode, @rN in unsegmented mode. -`ADDR' +'ADDR' Direct: the 16 bit or 24 bit address (depending on whether the - assembler is in segmented or unsegmented mode) of the operand is - in the instruction. + assembler is in segmented or unsegmented mode) of the operand is in + the instruction. -`address(rN)' +'address(rN)' Indexed: the 16 or 24 bit address is added to the 16 bit register to produce the final address in memory of the operand. -`rN(#IMM)' -`rrN(#IMM)' +'rN(#IMM)' +'rrN(#IMM)' Base Address: the 16 or 24 bit register is added to the 16 bit sign extended immediate displacement to produce the final address in memory of the operand. -`rN(rM)' -`rrN(rM)' +'rN(rM)' +'rrN(rM)' Base Index: the 16 or 24 bit register rN or rrN is added to the - sign extended 16 bit index register rM to produce the final - address in memory of the operand. + sign extended 16 bit index register rM to produce the final address + in memory of the operand. -`#XX' +'#XX' Immediate data XX. @@ -19666,43 +19523,42 @@ File: as.info, Node: Z8000 Directives, Next: Z8000 Opcodes, Prev: Z8000 Synta ----------------------------------------- The Z8000 port of as includes additional assembler directives, for -compatibility with other Z8000 assemblers. These do not begin with `.' +compatibility with other Z8000 assemblers. These do not begin with '.' (unlike the ordinary as directives). -`segm' -`.z8001' +'segm' +'.z8001' Generate code for the segmented Z8001. -`unsegm' -`.z8002' +'unsegm' +'.z8002' Generate code for the unsegmented Z8002. -`name' - Synonym for `.file' +'name' + Synonym for '.file' -`global' - Synonym for `.global' +'global' + Synonym for '.global' -`wval' - Synonym for `.word' +'wval' + Synonym for '.word' -`lval' - Synonym for `.long' +'lval' + Synonym for '.long' -`bval' - Synonym for `.byte' +'bval' + Synonym for '.byte' -`sval' - Assemble a string. `sval' expects one string literal, delimited by +'sval' + Assemble a string. 'sval' expects one string literal, delimited by single quotes. It assembles each byte of the string into - consecutive addresses. You can use the escape sequence `%XX' + consecutive addresses. You can use the escape sequence '%XX' (where XX represents a two-digit hexadecimal number) to represent the character whose ASCII value is XX. Use this feature to describe single quote and other characters that may not appear in - string literals as themselves. For example, the C statement - `char *a = "he said \"it's 50% off\"";' is represented in Z8000 - assembly language (shown with the assembler output in hex at the - left) as + string literals as themselves. For example, the C statement 'char *a = "he said \"it's 50% off\"";' + is represented in Z8000 assembly language (shown with the assembler + output in hex at the left) as 68652073 sval 'he said %22it%27s 50%25 off%22%00' 61696420 @@ -19711,14 +19567,14 @@ compatibility with other Z8000 assemblers. These do not begin with `.' 25206F66 662200 -`rsect' - synonym for `.section' +'rsect' + synonym for '.section' -`block' - synonym for `.space' +'block' + synonym for '.space' -`even' - special case of `.align'; aligns output to even byte boundary. +'even' + special case of '.align'; aligns output to even byte boundary. File: as.info, Node: Z8000 Opcodes, Prev: Z8000 Directives, Up: Z8000-Dependent @@ -19727,7 +19583,7 @@ File: as.info, Node: Z8000 Opcodes, Prev: Z8000 Directives, Up: Z8000-Depende -------------- For detailed information on the Z8000 machine instruction set, see -`Z8000 Technical Manual'. +'Z8000 Technical Manual'. The following table summarizes the opcodes and their arguments: @@ -19884,7 +19740,7 @@ For detailed information on the Z8000 machine instruction set, see set addr(rd),imm4 subl rrd,addr(rs) -File: as.info, Node: Vax-Dependent, Prev: Z8000-Dependent, Up: Machine Dependencies +File: as.info, Node: Vax-Dependent, Next: V850-Dependent, Prev: Z8000-Dependent, Up: Machine Dependencies 9.48 VAX Dependent Features =========================== @@ -19906,84 +19762,84 @@ File: as.info, Node: VAX-Opts, Next: VAX-float, Up: Vax-Dependent 9.48.1 VAX Command-Line Options ------------------------------- -The Vax version of `as' accepts any of the following options, gives a -warning message that the option was ignored and proceeds. These -options are for compatibility with scripts designed for other people's +The Vax version of 'as' accepts any of the following options, gives a +warning message that the option was ignored and proceeds. These options +are for compatibility with scripts designed for other people's assemblers. -``-D' (Debug)' -``-S' (Symbol Table)' -``-T' (Token Trace)' +'-D (Debug)' +'-S (Symbol Table)' +'-T (Token Trace)' These are obsolete options used to debug old assemblers. -``-d' (Displacement size for JUMPs)' - This option expects a number following the `-d'. Like options - that expect filenames, the number may immediately follow the `-d' - (old standard) or constitute the whole of the command line - argument that follows `-d' (GNU standard). +'-d (Displacement size for JUMPs)' + This option expects a number following the '-d'. Like options that + expect filenames, the number may immediately follow the '-d' (old + standard) or constitute the whole of the command line argument that + follows '-d' (GNU standard). -``-V' (Virtualize Interpass Temporary File)' +'-V (Virtualize Interpass Temporary File)' Some other assemblers use a temporary file. This option commanded - them to keep the information in active memory rather than in a - disk file. `as' always does this, so this option is redundant. - -``-J' (JUMPify Longer Branches)' - Many 32-bit computers permit a variety of branch instructions to - do the same job. Some of these instructions are short (and fast) - but have a limited range; others are long (and slow) but can - branch anywhere in virtual memory. Often there are 3 flavors of - branch: short, medium and long. Some other assemblers would emit - short and medium branches, unless told by this option to emit - short and long branches. - -``-t' (Temporary File Directory)' + them to keep the information in active memory rather than in a disk + file. 'as' always does this, so this option is redundant. + +'-J (JUMPify Longer Branches)' + Many 32-bit computers permit a variety of branch instructions to do + the same job. Some of these instructions are short (and fast) but + have a limited range; others are long (and slow) but can branch + anywhere in virtual memory. Often there are 3 flavors of branch: + short, medium and long. Some other assemblers would emit short and + medium branches, unless told by this option to emit short and long + branches. + +'-t (Temporary File Directory)' Some other assemblers may use a temporary file, and this option takes a filename being the directory to site the temporary file. - Since `as' does not use a temporary disk file, this option makes - no difference. `-t' needs exactly one filename. + Since 'as' does not use a temporary disk file, this option makes no + difference. '-t' needs exactly one filename. The Vax version of the assembler accepts additional options when compiled for VMS: -`-h N' +'-h N' External symbol or section (used for global variables) names are not case sensitive on VAX/VMS and always mapped to upper case. This is contrary to the C language definition which explicitly distinguishes upper and lower case. To implement a standard conforming C compiler, names must be changed (mapped) to preserve the case information. The default mapping is to convert all lower - case characters to uppercase and adding an underscore followed by - a 6 digit hex value, representing a 24 digit binary value. The - one digits in the binary value represent which characters are - uppercase in the original symbol name. - - The `-h N' option determines how we map names. This takes several - values. No `-h' switch at all allows case hacking as described - above. A value of zero (`-h0') implies names should be upper - case, and inhibits the case hack. A value of 2 (`-h2') implies - names should be all lower case, with no case hack. A value of 3 - (`-h3') implies that case should be preserved. The value 1 is - unused. The `-H' option directs `as' to display every mapped - symbol during assembly. - - Symbols whose names include a dollar sign `$' are exceptions to the + case characters to uppercase and adding an underscore followed by a + 6 digit hex value, representing a 24 digit binary value. The one + digits in the binary value represent which characters are uppercase + in the original symbol name. + + The '-h N' option determines how we map names. This takes several + values. No '-h' switch at all allows case hacking as described + above. A value of zero ('-h0') implies names should be upper case, + and inhibits the case hack. A value of 2 ('-h2') implies names + should be all lower case, with no case hack. A value of 3 ('-h3') + implies that case should be preserved. The value 1 is unused. The + '-H' option directs 'as' to display every mapped symbol during + assembly. + + Symbols whose names include a dollar sign '$' are exceptions to the general name mapping. These symbols are normally only used to reference VMS library names. Such symbols are always mapped to upper case. -`-+' - The `-+' option causes `as' to truncate any symbol name larger - than 31 characters. The `-+' option also prevents some code - following the `_main' symbol normally added to make the object - file compatible with Vax-11 "C". +'-+' + The '-+' option causes 'as' to truncate any symbol name larger than + 31 characters. The '-+' option also prevents some code following + the '_main' symbol normally added to make the object file + compatible with Vax-11 "C". -`-1' - This option is ignored for backward compatibility with `as' - version 1.x. +'-1' + This option is ignored for backward compatibility with 'as' version + 1.x. -`-H' - The `-H' option causes `as' to print every symbol which was - changed by case mapping. +'-H' + The '-H' option causes 'as' to print every symbol which was changed + by case mapping. File: as.info, Node: VAX-float, Next: VAX-directives, Prev: VAX-Opts, Up: Vax-Dependent @@ -19995,13 +19851,13 @@ Conversion of flonums to floating point is correct, and compatible with previous assemblers. Rounding is towards zero if the remainder is exactly half the least significant bit. - `D', `F', `G' and `H' floating point formats are understood. + 'D', 'F', 'G' and 'H' floating point formats are understood. - Immediate floating literals (_e.g._ `S`$6.9') are rendered + Immediate floating literals (_e.g._ 'S`$6.9') are rendered correctly. Again, rounding is towards zero in the boundary case. - The `.float' directive produces `f' format numbers. The `.double' -directive produces `d' format numbers. + The '.float' directive produces 'f' format numbers. The '.double' +directive produces 'd' format numbers. File: as.info, Node: VAX-directives, Next: VAX-opcodes, Prev: VAX-float, Up: Vax-Dependent @@ -20009,26 +19865,24 @@ File: as.info, Node: VAX-directives, Next: VAX-opcodes, Prev: VAX-float, Up: 9.48.3 Vax Machine Directives ----------------------------- -The Vax version of the assembler supports four directives for -generating Vax floating point constants. They are described in the -table below. +The Vax version of the assembler supports four directives for generating +Vax floating point constants. They are described in the table below. -`.dfloat' +'.dfloat' This expects zero or more flonums, separated by commas, and - assembles Vax `d' format 64-bit floating point constants. + assembles Vax 'd' format 64-bit floating point constants. -`.ffloat' +'.ffloat' This expects zero or more flonums, separated by commas, and - assembles Vax `f' format 32-bit floating point constants. + assembles Vax 'f' format 32-bit floating point constants. -`.gfloat' +'.gfloat' This expects zero or more flonums, separated by commas, and - assembles Vax `g' format 64-bit floating point constants. + assembles Vax 'g' format 64-bit floating point constants. -`.hfloat' +'.hfloat' This expects zero or more flonums, separated by commas, and - assembles Vax `h' format 128-bit floating point constants. - + assembles Vax 'h' format 128-bit floating point constants. File: as.info, Node: VAX-opcodes, Next: VAX-branch, Prev: VAX-directives, Up: Vax-Dependent @@ -20036,9 +19890,9 @@ File: as.info, Node: VAX-opcodes, Next: VAX-branch, Prev: VAX-directives, Up 9.48.4 VAX Opcodes ------------------ -All DEC mnemonics are supported. Beware that `case...' instructions -have exactly 3 operands. The dispatch table that follows the `case...' -instruction should be made with `.word' statements. This is compatible +All DEC mnemonics are supported. Beware that 'case...' instructions +have exactly 3 operands. The dispatch table that follows the 'case...' +instruction should be made with '.word' statements. This is compatible with all unix assemblers we know of. @@ -20047,98 +19901,80 @@ File: as.info, Node: VAX-branch, Next: VAX-operands, Prev: VAX-opcodes, Up: 9.48.5 VAX Branch Improvement ----------------------------- -Certain pseudo opcodes are permitted. They are for branch -instructions. They expand to the shortest branch instruction that -reaches the target. Generally these mnemonics are made by substituting -`j' for `b' at the start of a DEC mnemonic. This feature is included -both for compatibility and to help compilers. If you do not need this -feature, avoid these opcodes. Here are the mnemonics, and the code -they can expand into. - -`jbsb' - `Jsb' is already an instruction mnemonic, so we chose `jbsb'. - (byte displacement) - `bsbb ...' - - (word displacement) - `bsbw ...' - - (long displacement) - `jsb ...' - -`jbr' -`jr' +Certain pseudo opcodes are permitted. They are for branch instructions. +They expand to the shortest branch instruction that reaches the target. +Generally these mnemonics are made by substituting 'j' for 'b' at the +start of a DEC mnemonic. This feature is included both for +compatibility and to help compilers. If you do not need this feature, +avoid these opcodes. Here are the mnemonics, and the code they can +expand into. + +'jbsb' + 'Jsb' is already an instruction mnemonic, so we chose 'jbsb'. + (byte displacement) + 'bsbb ...' + (word displacement) + 'bsbw ...' + (long displacement) + 'jsb ...' +'jbr' +'jr' Unconditional branch. - (byte displacement) - `brb ...' - - (word displacement) - `brw ...' - - (long displacement) - `jmp ...' - -`jCOND' - COND may be any one of the conditional branches `neq', `nequ', - `eql', `eqlu', `gtr', `geq', `lss', `gtru', `lequ', `vc', `vs', - `gequ', `cc', `lssu', `cs'. COND may also be one of the bit tests - `bs', `bc', `bss', `bcs', `bsc', `bcc', `bssi', `bcci', `lbs', - `lbc'. NOTCOND is the opposite condition to COND. - (byte displacement) - `bCOND ...' - - (word displacement) - `bNOTCOND foo ; brw ... ; foo:' - - (long displacement) - `bNOTCOND foo ; jmp ... ; foo:' - -`jacbX' - X may be one of `b d f g h l w'. - (word displacement) - `OPCODE ...' - - (long displacement) + (byte displacement) + 'brb ...' + (word displacement) + 'brw ...' + (long displacement) + 'jmp ...' +'jCOND' + COND may be any one of the conditional branches 'neq', 'nequ', + 'eql', 'eqlu', 'gtr', 'geq', 'lss', 'gtru', 'lequ', 'vc', 'vs', + 'gequ', 'cc', 'lssu', 'cs'. COND may also be one of the bit tests + 'bs', 'bc', 'bss', 'bcs', 'bsc', 'bcc', 'bssi', 'bcci', 'lbs', + 'lbc'. NOTCOND is the opposite condition to COND. + (byte displacement) + 'bCOND ...' + (word displacement) + 'bNOTCOND foo ; brw ... ; foo:' + (long displacement) + 'bNOTCOND foo ; jmp ... ; foo:' +'jacbX' + X may be one of 'b d f g h l w'. + (word displacement) + 'OPCODE ...' + (long displacement) OPCODE ..., foo ; brb bar ; foo: jmp ... ; bar: - -`jaobYYY' - YYY may be one of `lss leq'. - -`jsobZZZ' - ZZZ may be one of `geq gtr'. - (byte displacement) - `OPCODE ...' - - (word displacement) +'jaobYYY' + YYY may be one of 'lss leq'. +'jsobZZZ' + ZZZ may be one of 'geq gtr'. + (byte displacement) + 'OPCODE ...' + (word displacement) OPCODE ..., foo ; brb bar ; foo: brw DESTINATION ; bar: - - (long displacement) + (long displacement) OPCODE ..., foo ; brb bar ; foo: jmp DESTINATION ; bar: - -`aobleq' -`aoblss' -`sobgeq' -`sobgtr' - - (byte displacement) - `OPCODE ...' - - (word displacement) +'aobleq' +'aoblss' +'sobgeq' +'sobgtr' + (byte displacement) + 'OPCODE ...' + (word displacement) OPCODE ..., foo ; brb bar ; foo: brw DESTINATION ; bar: - - (long displacement) + (long displacement) OPCODE ..., foo ; brb bar ; foo: jmp DESTINATION ; @@ -20150,18 +19986,18 @@ File: as.info, Node: VAX-operands, Next: VAX-no, Prev: VAX-branch, Up: Vax-D 9.48.6 VAX Operands ------------------- -The immediate character is `$' for Unix compatibility, not `#' as DEC +The immediate character is '$' for Unix compatibility, not '#' as DEC writes it. - The indirect character is `*' for Unix compatibility, not `@' as DEC + The indirect character is '*' for Unix compatibility, not '@' as DEC writes it. - The displacement sizing character is ``' (an accent grave) for Unix -compatibility, not `^' as DEC writes it. The letter preceding ``' may -have either case. `G' is not understood, but all other letters (`b i l + The displacement sizing character is '`' (an accent grave) for Unix +compatibility, not '^' as DEC writes it. The letter preceding '`' may +have either case. 'G' is not understood, but all other letters ('b i l s w') are understood. - Register names understood are `r0 r1 r2 ... r15 ap fp sp pc'. Upper + Register names understood are 'r0 r1 r2 ... r15 ap fp sp pc'. Upper and lower case letters are equivalent. For instance @@ -20176,7 +20012,7 @@ File: as.info, Node: VAX-no, Next: VAX-Syntax, Prev: VAX-operands, Up: Vax-D 9.48.7 Not Supported on VAX --------------------------- -Vax bit fields can not be assembled with `as'. Someone can add the +Vax bit fields can not be assembled with 'as'. Someone can add the required code if they really need it. @@ -20195,19 +20031,19 @@ File: as.info, Node: VAX-Chars, Up: VAX-Syntax 9.48.8.1 Special Characters ........................... -The presence of a `#' appearing anywhere on a line indicates the start +The presence of a '#' appearing anywhere on a line indicates the start of a comment that extends to the end of that line. - If a `#' appears as the first character of a line then the whole -line is treated as a comment, but in this case the line can also be a -logical line number directive (*note Comments::) or a preprocessor -control command (*note Preprocessing::). + If a '#' appears as the first character of a line then the whole line +is treated as a comment, but in this case the line can also be a logical +line number directive (*note Comments::) or a preprocessor control +command (*note Preprocessing::). - The `;' character can be used to separate statements on the same + The ';' character can be used to separate statements on the same line. -File: as.info, Node: V850-Dependent, Next: XGATE-Dependent, Prev: TILEPro-Dependent, Up: Machine Dependencies +File: as.info, Node: V850-Dependent, Next: XGATE-Dependent, Prev: Vax-Dependent, Up: Machine Dependencies 9.49 v850 Dependent Features ============================ @@ -20226,96 +20062,95 @@ File: as.info, Node: V850 Options, Next: V850 Syntax, Up: V850-Dependent 9.49.1 Options -------------- -`as' supports the following additional command-line options for the -V850 processor family: +'as' supports the following additional command-line options for the V850 +processor family: -`-wsigned_overflow' +'-wsigned_overflow' Causes warnings to be produced when signed immediate values overflow the space available for then within their opcodes. By default this option is disabled as it is possible to receive spurious warnings due to using exact bit patterns as immediate constants. -`-wunsigned_overflow' +'-wunsigned_overflow' Causes warnings to be produced when unsigned immediate values overflow the space available for then within their opcodes. By default this option is disabled as it is possible to receive spurious warnings due to using exact bit patterns as immediate constants. -`-mv850' +'-mv850' Specifies that the assembled code should be marked as being targeted at the V850 processor. This allows the linker to detect attempts to link such code with code assembled for other processors. -`-mv850e' +'-mv850e' Specifies that the assembled code should be marked as being targeted at the V850E processor. This allows the linker to detect attempts to link such code with code assembled for other processors. -`-mv850e1' +'-mv850e1' Specifies that the assembled code should be marked as being - targeted at the V850E1 processor. This allows the linker to - detect attempts to link such code with code assembled for other + targeted at the V850E1 processor. This allows the linker to detect + attempts to link such code with code assembled for other processors. -`-mv850any' +'-mv850any' Specifies that the assembled code should be marked as being targeted at the V850 processor but support instructions that are specific to the extended variants of the process. This allows the - production of binaries that contain target specific code, but - which are also intended to be used in a generic fashion. For - example libgcc.a contains generic routines used by the code - produced by GCC for all versions of the v850 architecture, - together with support routines only used by the V850E architecture. + production of binaries that contain target specific code, but which + are also intended to be used in a generic fashion. For example + libgcc.a contains generic routines used by the code produced by GCC + for all versions of the v850 architecture, together with support + routines only used by the V850E architecture. -`-mv850e2' +'-mv850e2' Specifies that the assembled code should be marked as being - targeted at the V850E2 processor. This allows the linker to - detect attempts to link such code with code assembled for other + targeted at the V850E2 processor. This allows the linker to detect + attempts to link such code with code assembled for other processors. -`-mv850e2v3' +'-mv850e2v3' Specifies that the assembled code should be marked as being targeted at the V850E2V3 processor. This allows the linker to detect attempts to link such code with code assembled for other processors. -`-mv850e2v4' - This is an alias for `-mv850e3v5'. +'-mv850e2v4' + This is an alias for '-mv850e3v5'. -`-mv850e3v5' +'-mv850e3v5' Specifies that the assembled code should be marked as being targeted at the V850E3V5 processor. This allows the linker to detect attempts to link such code with code assembled for other processors. -`-mrelax' +'-mrelax' Enables relaxation. This allows the .longcall and .longjump pseudo ops to be used in the assembler source code. These ops label sections of code which are either a long function call or a long branch. The assembler will then flag these sections of code and the linker will attempt to relax them. -`-mgcc-abi' +'-mgcc-abi' Marks the generated objecy file as supporting the old GCC ABI. -`-mrh850-abi' - Marks the generated objecy file as supporting the RH850 ABI. This +'-mrh850-abi' + Marks the generated objecy file as supporting the RH850 ABI. This is the default. -`-m8byte-align' +'-m8byte-align' Marks the generated objecy file as supporting a maximum 64-bits of alignment for variables defined in the source code. -`-m4byte-align' +'-m4byte-align' Marks the generated objecy file as supporting a maximum 32-bits of alignment for variables defined in the source code. This is the default. - File: as.info, Node: V850 Syntax, Next: V850 Floating Point, Prev: V850 Options, Up: V850-Dependent @@ -20333,14 +20168,14 @@ File: as.info, Node: V850-Chars, Next: V850-Regs, Up: V850 Syntax 9.49.2.1 Special Characters ........................... -`#' is the line comment character. If a `#' appears as the first -character of a line, the whole line is treated as a comment, but in -this case the line can also be a logical line number directive (*note +'#' is the line comment character. If a '#' appears as the first +character of a line, the whole line is treated as a comment, but in this +case the line can also be a logical line number directive (*note Comments::) or a preprocessor control command (*note Preprocessing::). - Two dashes (`--') can also be used to start a line comment. + Two dashes ('--') can also be used to start a line comment. - The `;' character can be used to separate statements on the same + The ';' character can be used to separate statements on the same line. @@ -20349,134 +20184,92 @@ File: as.info, Node: V850-Regs, Prev: V850-Chars, Up: V850 Syntax 9.49.2.2 Register Names ....................... -`as' supports the following names for registers: -`general register 0' +'as' supports the following names for registers: +'general register 0' r0, zero - -`general register 1' +'general register 1' r1 - -`general register 2' - r2, hp - -`general register 3' - r3, sp - -`general register 4' - r4, gp - -`general register 5' +'general register 2' + r2, hp +'general register 3' + r3, sp +'general register 4' + r4, gp +'general register 5' r5, tp - -`general register 6' +'general register 6' r6 - -`general register 7' +'general register 7' r7 - -`general register 8' +'general register 8' r8 - -`general register 9' +'general register 9' r9 - -`general register 10' +'general register 10' r10 - -`general register 11' +'general register 11' r11 - -`general register 12' +'general register 12' r12 - -`general register 13' +'general register 13' r13 - -`general register 14' +'general register 14' r14 - -`general register 15' +'general register 15' r15 - -`general register 16' +'general register 16' r16 - -`general register 17' +'general register 17' r17 - -`general register 18' +'general register 18' r18 - -`general register 19' +'general register 19' r19 - -`general register 20' +'general register 20' r20 - -`general register 21' +'general register 21' r21 - -`general register 22' +'general register 22' r22 - -`general register 23' +'general register 23' r23 - -`general register 24' +'general register 24' r24 - -`general register 25' +'general register 25' r25 - -`general register 26' +'general register 26' r26 - -`general register 27' +'general register 27' r27 - -`general register 28' +'general register 28' r28 - -`general register 29' - r29 - -`general register 30' - r30, ep - -`general register 31' - r31, lp - -`system register 0' - eipc - -`system register 1' - eipsw - -`system register 2' - fepc - -`system register 3' - fepsw - -`system register 4' - ecr - -`system register 5' - psw - -`system register 16' - ctpc - -`system register 17' - ctpsw - -`system register 18' - dbpc - -`system register 19' - dbpsw - -`system register 20' +'general register 29' + r29 +'general register 30' + r30, ep +'general register 31' + r31, lp +'system register 0' + eipc +'system register 1' + eipsw +'system register 2' + fepc +'system register 3' + fepsw +'system register 4' + ecr +'system register 5' + psw +'system register 16' + ctpc +'system register 17' + ctpsw +'system register 18' + dbpc +'system register 19' + dbpsw +'system register 20' ctbp @@ -20493,91 +20286,90 @@ File: as.info, Node: V850 Directives, Next: V850 Opcodes, Prev: V850 Floating 9.49.4 V850 Machine Directives ------------------------------ -`.offset <EXPRESSION>' +'.offset <EXPRESSION>' Moves the offset into the current section to the specified amount. -`.section "name", <type>' +'.section "name", <type>' This is an extension to the standard .section directive. It sets the current section to be <type> and creates an alias for this section called "name". -`.v850' +'.v850' Specifies that the assembled code should be marked as being targeted at the V850 processor. This allows the linker to detect attempts to link such code with code assembled for other processors. -`.v850e' +'.v850e' Specifies that the assembled code should be marked as being targeted at the V850E processor. This allows the linker to detect attempts to link such code with code assembled for other processors. -`.v850e1' +'.v850e1' Specifies that the assembled code should be marked as being - targeted at the V850E1 processor. This allows the linker to - detect attempts to link such code with code assembled for other + targeted at the V850E1 processor. This allows the linker to detect + attempts to link such code with code assembled for other processors. -`.v850e2' +'.v850e2' Specifies that the assembled code should be marked as being - targeted at the V850E2 processor. This allows the linker to - detect attempts to link such code with code assembled for other + targeted at the V850E2 processor. This allows the linker to detect + attempts to link such code with code assembled for other processors. -`.v850e2v3' +'.v850e2v3' Specifies that the assembled code should be marked as being targeted at the V850E2V3 processor. This allows the linker to detect attempts to link such code with code assembled for other processors. -`.v850e2v4' +'.v850e2v4' Specifies that the assembled code should be marked as being targeted at the V850E3V5 processor. This allows the linker to detect attempts to link such code with code assembled for other processors. -`.v850e3v5' +'.v850e3v5' Specifies that the assembled code should be marked as being targeted at the V850E3V5 processor. This allows the linker to detect attempts to link such code with code assembled for other processors. - File: as.info, Node: V850 Opcodes, Prev: V850 Directives, Up: V850-Dependent 9.49.5 Opcodes -------------- -`as' implements all the standard V850 opcodes. +'as' implements all the standard V850 opcodes. - `as' also implements the following pseudo ops: + 'as' also implements the following pseudo ops: -`hi0()' +'hi0()' Computes the higher 16 bits of the given expression and stores it into the immediate operand field of the given instruction. For example: - `mulhi hi0(here - there), r5, r6' + 'mulhi hi0(here - there), r5, r6' computes the difference between the address of labels 'here' and - 'there', takes the upper 16 bits of this difference, shifts it - down 16 bits and then multiplies it by the lower 16 bits in - register 5, putting the result into register 6. + 'there', takes the upper 16 bits of this difference, shifts it down + 16 bits and then multiplies it by the lower 16 bits in register 5, + putting the result into register 6. -`lo()' +'lo()' Computes the lower 16 bits of the given expression and stores it into the immediate operand field of the given instruction. For example: - `addi lo(here - there), r5, r6' + 'addi lo(here - there), r5, r6' computes the difference between the address of labels 'here' and 'there', takes the lower 16 bits of this difference and adds it to register 5, putting the result into register 6. -`hi()' +'hi()' Computes the higher 16 bits of the given expression and then adds the value of the most significant bit of the lower 16 bits of the expression and stores the result into the immediate operand field @@ -20585,37 +20377,37 @@ File: as.info, Node: V850 Opcodes, Prev: V850 Directives, Up: V850-Dependent used to compute the address of the label 'here' and store it into register 6: - `movhi hi(here), r0, r6' `movea lo(here), r6, r6' + 'movhi hi(here), r0, r6' 'movea lo(here), r6, r6' The reason for this special behaviour is that movea performs a sign extension on its immediate operand. So for example if the address of 'here' was 0xFFFFFFFF then without the special behaviour of the hi() pseudo-op the movhi instruction would put 0xFFFF0000 into r6, then the movea instruction would takes its immediate operand, - 0xFFFF, sign extend it to 32 bits, 0xFFFFFFFF, and then add it - into r6 giving 0xFFFEFFFF which is wrong (the fifth nibble is E). - With the hi() pseudo op adding in the top bit of the lo() pseudo - op, the movhi instruction actually stores 0 into r6 (0xFFFF + 1 = - 0x0000), so that the movea instruction stores 0xFFFFFFFF into r6 - - the right value. - -`hilo()' + 0xFFFF, sign extend it to 32 bits, 0xFFFFFFFF, and then add it into + r6 giving 0xFFFEFFFF which is wrong (the fifth nibble is E). With + the hi() pseudo op adding in the top bit of the lo() pseudo op, the + movhi instruction actually stores 0 into r6 (0xFFFF + 1 = 0x0000), + so that the movea instruction stores 0xFFFFFFFF into r6 - the right + value. + +'hilo()' Computes the 32 bit value of the given expression and stores it into the immediate operand field of the given instruction (which must be a mov instruction). For example: - `mov hilo(here), r6' + 'mov hilo(here), r6' computes the absolute address of label 'here' and puts the result into register 6. -`sdaoff()' +'sdaoff()' Computes the offset of the named variable from the start of the Small Data Area (whoes address is held in register 4, the GP register) and stores the result as a 16 bit signed value in the immediate operand field of the given instruction. For example: - `ld.w sdaoff(_a_variable)[gp],r6' + 'ld.w sdaoff(_a_variable)[gp],r6' loads the contents of the location pointed to by the label '_a_variable' into register 6, provided that the label is located @@ -20623,64 +20415,62 @@ File: as.info, Node: V850 Opcodes, Prev: V850 Directives, Up: V850-Dependent [Note the linker assumes that the GP register contains a fixed address set to the address of the label called '__gp'. This can either be set up automatically by the linker, or specifically set - by using the `--defsym __gp=<value>' command line option]. + by using the '--defsym __gp=<value>' command line option]. -`tdaoff()' +'tdaoff()' Computes the offset of the named variable from the start of the Tiny Data Area (whoes address is held in register 30, the EP - register) and stores the result as a 4,5, 7 or 8 bit unsigned - value in the immediate operand field of the given instruction. - For example: + register) and stores the result as a 4,5, 7 or 8 bit unsigned value + in the immediate operand field of the given instruction. For + example: - `sld.w tdaoff(_a_variable)[ep],r6' + 'sld.w tdaoff(_a_variable)[ep],r6' loads the contents of the location pointed to by the label '_a_variable' into register 6, provided that the label is located - somewhere within +256 bytes of the address held in the EP - register. [Note the linker assumes that the EP register contains - a fixed address set to the address of the label called '__ep'. - This can either be set up automatically by the linker, or - specifically set by using the `--defsym __ep=<value>' command line - option]. + somewhere within +256 bytes of the address held in the EP register. + [Note the linker assumes that the EP register contains a fixed + address set to the address of the label called '__ep'. This can + either be set up automatically by the linker, or specifically set + by using the '--defsym __ep=<value>' command line option]. -`zdaoff()' - Computes the offset of the named variable from address 0 and - stores the result as a 16 bit signed value in the immediate - operand field of the given instruction. For example: +'zdaoff()' + Computes the offset of the named variable from address 0 and stores + the result as a 16 bit signed value in the immediate operand field + of the given instruction. For example: - `movea zdaoff(_a_variable),zero,r6' + 'movea zdaoff(_a_variable),zero,r6' puts the address of the label '_a_variable' into register 6, assuming that the label is somewhere within the first 32K of - memory. (Strictly speaking it also possible to access the last - 32K of memory as well, as the offsets are signed). + memory. (Strictly speaking it also possible to access the last 32K + of memory as well, as the offsets are signed). -`ctoff()' +'ctoff()' Computes the offset of the named variable from the start of the Call Table Area (whoes address is helg in system register 20, the CTBP register) and stores the result a 6 or 16 bit unsigned value in the immediate field of then given instruction or piece of data. For example: - `callt ctoff(table_func1)' + 'callt ctoff(table_func1)' will put the call the function whoes address is held in the call table at the location labeled 'table_func1'. -`.longcall `name'' +'.longcall name' Indicates that the following sequence of instructions is a long - call to function `name'. The linker will attempt to shorten this - call sequence if `name' is within a 22bit offset of the call. Only - valid if the `-mrelax' command line switch has been enabled. + call to function 'name'. The linker will attempt to shorten this + call sequence if 'name' is within a 22bit offset of the call. Only + valid if the '-mrelax' command line switch has been enabled. -`.longjump `name'' +'.longjump name' Indicates that the following sequence of instructions is a long - jump to label `name'. The linker will attempt to shorten this code - sequence if `name' is within a 22bit offset of the jump. Only - valid if the `-mrelax' command line switch has been enabled. - + jump to label 'name'. The linker will attempt to shorten this code + sequence if 'name' is within a 22bit offset of the jump. Only + valid if the '-mrelax' command line switch has been enabled. - For information on the V850 instruction set, see `V850 Family + For information on the V850 instruction set, see 'V850 Family 32-/16-Bit single-Chip Microcontroller Architecture Manual' from NEC. Ltd. @@ -20704,35 +20494,34 @@ File: as.info, Node: XGATE-Opts, Next: XGATE-Syntax, Up: XGATE-Dependent 9.50.1 XGATE Options -------------------- -The Freescale XGATE version of `as' has a few machine dependent options. +The Freescale XGATE version of 'as' has a few machine dependent options. -`-mshort' +'-mshort' This option controls the ABI and indicates to use a 16-bit integer - ABI. It has no effect on the assembled instructions. This is the + ABI. It has no effect on the assembled instructions. This is the default. -`-mlong' +'-mlong' This option controls the ABI and indicates to use a 32-bit integer ABI. -`-mshort-double' +'-mshort-double' This option controls the ABI and indicates to use a 32-bit float - ABI. This is the default. + ABI. This is the default. -`-mlong-double' +'-mlong-double' This option controls the ABI and indicates to use a 64-bit float ABI. -`--print-insn-syntax' - You can use the `--print-insn-syntax' option to obtain the syntax +'--print-insn-syntax' + You can use the '--print-insn-syntax' option to obtain the syntax description of the instruction when an error is detected. -`--print-opcodes' - The `--print-opcodes' option prints the list of all the - instructions with their syntax. Once the list is printed `as' +'--print-opcodes' + The '--print-opcodes' option prints the list of all the + instructions with their syntax. Once the list is printed 'as' exits. - File: as.info, Node: XGATE-Syntax, Next: XGATE-Directives, Prev: XGATE-Opts, Up: XGATE-Dependent @@ -20740,22 +20529,21 @@ File: as.info, Node: XGATE-Syntax, Next: XGATE-Directives, Prev: XGATE-Opts, ------------- In XGATE RISC syntax, the instruction name comes first and it may be -followed by up to three operands. Operands are separated by commas -(`,'). `as' will complain if too many operands are specified for a -given instruction. The same will happen if you specified too few +followed by up to three operands. Operands are separated by commas +(','). 'as' will complain if too many operands are specified for a +given instruction. The same will happen if you specified too few operands. nop ldl #23 CMP R1, R2 - The presence of a `;' character or a `!' character anywhere on a -line indicates the start of a comment that extends to the end of that -line. + The presence of a ';' character or a '!' character anywhere on a line +indicates the start of a comment that extends to the end of that line. - A `*' or a `#' character at the start of a line also introduces a + A '*' or a '#' character at the start of a line also introduces a line comment, but these characters do not work elsewhere on the line. -If the first character of the line is a `#' then as well as starting a +If the first character of the line is a '#' then as well as starting a comment, the line could also be logical line number directive (*note Comments::) or a preprocessor control command (*note Preprocessing::). @@ -20764,52 +20552,51 @@ character. The following addressing modes are understood for XGATE: "Inherent" - `' + '' "Immediate 3 Bit Wide" - `#NUMBER' + '#NUMBER' "Immediate 4 Bit Wide" - `#NUMBER' + '#NUMBER' "Immediate 8 Bit Wide" - `#NUMBER' + '#NUMBER' "Monadic Addressing" - `REG' + 'REG' "Dyadic Addressing" - `REG, REG' + 'REG, REG' "Triadic Addressing" - `REG, REG, REG' + 'REG, REG, REG' "Relative Addressing 9 Bit Wide" - `*SYMBOL' + '*SYMBOL' "Relative Addressing 10 Bit Wide" - `*SYMBOL' + '*SYMBOL' "Index Register plus Immediate Offset" - `REG, (REG, #NUMBER)' + 'REG, (REG, #NUMBER)' "Index Register plus Register Offset" - `REG, REG, REG' + 'REG, REG, REG' "Index Register plus Register Offset with Post-increment" - `REG, REG, REG+' + 'REG, REG, REG+' "Index Register plus Register Offset with Pre-decrement" - `REG, REG, -REG' - - The register can be either `R0', `R1', `R2', `R3', `R4', `R5', - `R6' or `R7'. + 'REG, REG, -REG' + The register can be either 'R0', 'R1', 'R2', 'R3', 'R4', 'R5', 'R6' + or 'R7'. Convience macro opcodes to deal with 16-bit values have been added. "Immediate 16 Bit Wide" - `#NUMBER', or `*SYMBOL' + '#NUMBER', or '*SYMBOL' For example: @@ -20825,7 +20612,7 @@ File: as.info, Node: XGATE-Directives, Next: XGATE-Float, Prev: XGATE-Syntax, 9.50.3 Assembler Directives --------------------------- -The XGATE version of `as' have the following specific assembler +The XGATE version of 'as' have the following specific assembler directives: @@ -20838,15 +20625,15 @@ Packed decimal (P) format floating literals are not supported(yet). The floating point formats generated by directives are these. -`.float' - `Single' precision floating point constants. +'.float' + 'Single' precision floating point constants. -`.double' - `Double' precision floating point constants. +'.double' + 'Double' precision floating point constants. -`.extend' -`.ldouble' - `Extended' precision (`long double') floating point constants. +'.extend' +'.ldouble' + 'Extended' precision ('long double') floating point constants. File: as.info, Node: XGATE-opcodes, Prev: XGATE-Float, Up: XGATE-Dependent @@ -20882,15 +20669,15 @@ File: as.info, Node: XStormy16-Chars, Up: XStormy16 Syntax 9.51.1.1 Special Characters ........................... -`#' is the line comment character. If a `#' appears as the first -character of a line, the whole line is treated as a comment, but in -this case the line can also be a logical line number directive (*note +'#' is the line comment character. If a '#' appears as the first +character of a line, the whole line is treated as a comment, but in this +case the line can also be a logical line number directive (*note Comments::) or a preprocessor control command (*note Preprocessing::). - A semicolon (`;') can be used to start a comment that extends from + A semicolon (';') can be used to start a comment that extends from wherever the character appears on the line up to the end of the line. - The `|' character can be used to separate statements on the same + The '|' character can be used to separate statements on the same line. @@ -20899,52 +20686,50 @@ File: as.info, Node: XStormy16 Directives, Next: XStormy16 Opcodes, Prev: XSt 9.51.2 XStormy16 Machine Directives ----------------------------------- -`.16bit_pointers' - Like the `--16bit-pointers' command line option this directive +'.16bit_pointers' + Like the '--16bit-pointers' command line option this directive indicates that the assembly code makes use of 16-bit pointers. -`.32bit_pointers' - Like the `--32bit-pointers' command line option this directive +'.32bit_pointers' + Like the '--32bit-pointers' command line option this directive indicates that the assembly code makes use of 32-bit pointers. -`.no_pointers' - Like the `--no-pointers' command line option this directive +'.no_pointers' + Like the '--no-pointers' command line option this directive indicates that the assembly code does not makes use pointers. - File: as.info, Node: XStormy16 Opcodes, Prev: XStormy16 Directives, Up: XSTORMY16-Dependent 9.51.3 XStormy16 Pseudo-Opcodes ------------------------------- -`as' implements all the standard XStormy16 opcodes. +'as' implements all the standard XStormy16 opcodes. - `as' also implements the following pseudo ops: + 'as' also implements the following pseudo ops: -`@lo()' +'@lo()' Computes the lower 16 bits of the given expression and stores it into the immediate operand field of the given instruction. For example: - `add r6, @lo(here - there)' + 'add r6, @lo(here - there)' computes the difference between the address of labels 'here' and 'there', takes the lower 16 bits of this difference and adds it to register 6. -`@hi()' +'@hi()' Computes the higher 16 bits of the given expression and stores it into the immediate operand field of the given instruction. For example: - `addc r7, @hi(here - there)' + 'addc r7, @hi(here - there)' computes the difference between the address of labels 'here' and - 'there', takes the upper 16 bits of this difference, shifts it - down 16 bits and then adds it, along with the carry bit, to the - value in register 7. - + 'there', takes the upper 16 bits of this difference, shifts it down + 16 bits and then adds it, along with the carry bit, to the value in + register 7. File: as.info, Node: Xtensa-Dependent, Next: Z80-Dependent, Prev: XSTORMY16-Dependent, Up: Machine Dependencies @@ -20952,10 +20737,10 @@ File: as.info, Node: Xtensa-Dependent, Next: Z80-Dependent, Prev: XSTORMY16-D 9.52 Xtensa Dependent Features ============================== - This chapter covers features of the GNU assembler that are specific -to the Xtensa architecture. For details about the Xtensa instruction -set, please consult the `Xtensa Instruction Set Architecture (ISA) -Reference Manual'. +This chapter covers features of the GNU assembler that are specific to +the Xtensa architecture. For details about the Xtensa instruction set, +please consult the 'Xtensa Instruction Set Architecture (ISA) Reference +Manual'. * Menu: @@ -20971,52 +20756,51 @@ File: as.info, Node: Xtensa Options, Next: Xtensa Syntax, Up: Xtensa-Dependen 9.52.1 Command Line Options --------------------------- -`--text-section-literals | --no-text-section-literals' +'--text-section-literals | --no-text-section-literals' Control the treatment of literal pools. The default is - `--no-text-section-literals', which places literals in separate + '--no-text-section-literals', which places literals in separate sections in the output file. This allows the literal pool to be - placed in a data RAM/ROM. With `--text-section-literals', the - literals are interspersed in the text section in order to keep - them as close as possible to their references. This may be - necessary for large assembly files, where the literals would - otherwise be out of range of the `L32R' instructions in the text - section. These options only affect literals referenced via - PC-relative `L32R' instructions; literals for absolute mode `L32R' - instructions are handled separately. *Note literal: Literal - Directive. - -`--absolute-literals | --no-absolute-literals' - Indicate to the assembler whether `L32R' instructions use absolute + placed in a data RAM/ROM. With '--text-section-literals', the + literals are interspersed in the text section in order to keep them + as close as possible to their references. This may be necessary + for large assembly files, where the literals would otherwise be out + of range of the 'L32R' instructions in the text section. These + options only affect literals referenced via PC-relative 'L32R' + instructions; literals for absolute mode 'L32R' instructions are + handled separately. *Note literal: Literal Directive. + +'--absolute-literals | --no-absolute-literals' + Indicate to the assembler whether 'L32R' instructions use absolute or PC-relative addressing. If the processor includes the absolute - addressing option, the default is to use absolute `L32R' - relocations. Otherwise, only the PC-relative `L32R' relocations + addressing option, the default is to use absolute 'L32R' + relocations. Otherwise, only the PC-relative 'L32R' relocations can be used. -`--target-align | --no-target-align' - Enable or disable automatic alignment to reduce branch penalties - at some expense in code size. *Note Automatic Instruction - Alignment: Xtensa Automatic Alignment. This optimization is - enabled by default. Note that the assembler will always align - instructions like `LOOP' that have fixed alignment requirements. +'--target-align | --no-target-align' + Enable or disable automatic alignment to reduce branch penalties at + some expense in code size. *Note Automatic Instruction Alignment: + Xtensa Automatic Alignment. This optimization is enabled by + default. Note that the assembler will always align instructions + like 'LOOP' that have fixed alignment requirements. -`--longcalls | --no-longcalls' +'--longcalls | --no-longcalls' Enable or disable transformation of call instructions to allow calls across a greater range of addresses. *Note Function Call Relaxation: Xtensa Call Relaxation. This option should be used when call targets can potentially be out of range. It may degrade both code size and performance, but the linker can generally optimize away the unnecessary overhead when a call ends up within - range. The default is `--no-longcalls'. + range. The default is '--no-longcalls'. -`--transform | --no-transform' +'--transform | --no-transform' Enable or disable all assembler transformations of Xtensa instructions, including both relaxation and optimization. The - default is `--transform'; `--no-transform' should only be used in + default is '--transform'; '--no-transform' should only be used in the rare cases when the instructions must be exactly as specified - in the assembly source. Using `--no-transform' causes out of range + in the assembly source. Using '--no-transform' causes out of range instruction operands to be errors. -`--rename-section OLDNAME=NEWNAME' +'--rename-section OLDNAME=NEWNAME' Rename the OLDNAME section to NEWNAME. This option can be used multiple times to rename multiple sections. @@ -21026,11 +20810,11 @@ File: as.info, Node: Xtensa Syntax, Next: Xtensa Optimizations, Prev: Xtensa 9.52.2 Assembler Syntax ----------------------- -Block comments are delimited by `/*' and `*/'. End of line comments -may be introduced with either `#' or `//'. +Block comments are delimited by '/*' and '*/'. End of line comments may +be introduced with either '#' or '//'. - If a `#' appears as the first character of a line then the whole -line is treated as a comment, but in this case the line could also be a + If a '#' appears as the first character of a line then the whole line +is treated as a comment, but in this case the line could also be a logical line number directive (*note Comments::) or a preprocessor control command (*note Preprocessing::). @@ -21039,7 +20823,7 @@ whitespace and an optional comma-separated list of operands: OPCODE [OPERAND, ...] - Instructions must be separated by a newline or semicolon (`;'). + Instructions must be separated by a newline or semicolon (';'). FLIX instructions, which bundle multiple opcodes together in a single instruction, are specified by enclosing the bundled opcodes inside @@ -21082,11 +20866,11 @@ File: as.info, Node: Xtensa Opcodes, Next: Xtensa Registers, Up: Xtensa Synta 9.52.2.1 Opcode Names ..................... -See the `Xtensa Instruction Set Architecture (ISA) Reference Manual' -for a complete list of opcodes and descriptions of their semantics. +See the 'Xtensa Instruction Set Architecture (ISA) Reference Manual' for +a complete list of opcodes and descriptions of their semantics. - If an opcode name is prefixed with an underscore character (`_'), -`as' will not transform that instruction in any way. The underscore + If an opcode name is prefixed with an underscore character ('_'), +'as' will not transform that instruction in any way. The underscore prefix disables both optimization (*note Xtensa Optimizations: Xtensa Optimizations.) and relaxation (*note Xtensa Relaxation: Xtensa Relaxation.) for that particular instruction. Only use the underscore @@ -21097,19 +20881,19 @@ disabling relaxation. Note that this special handling of underscore prefixes only applies to Xtensa opcodes, not to either built-in macros or user-defined macros. -When an underscore prefix is used with a macro (e.g., `_MOV'), it -refers to a different macro. The assembler generally provides built-in -macros both with and without the underscore prefix, where the underscore +When an underscore prefix is used with a macro (e.g., '_MOV'), it refers +to a different macro. The assembler generally provides built-in macros +both with and without the underscore prefix, where the underscore versions behave as if the underscore carries through to the instructions -in the macros. For example, `_MOV' may expand to `_MOV.N'. +in the macros. For example, '_MOV' may expand to '_MOV.N'. The underscore prefix only applies to individual instructions, not to series of instructions. For example, if a series of instructions have underscore prefixes, the assembler will not transform the individual instructions, but it may insert other instructions between them (e.g., -to align a `LOOP' instruction). To prevent the assembler from -modifying a series of instructions as a whole, use the `no-transform' -directive. *Note transform: Transform Directive. +to align a 'LOOP' instruction). To prevent the assembler from modifying +a series of instructions as a whole, use the 'no-transform' directive. +*Note transform: Transform Directive. File: as.info, Node: Xtensa Registers, Prev: Xtensa Opcodes, Up: Xtensa Syntax @@ -21119,11 +20903,11 @@ File: as.info, Node: Xtensa Registers, Prev: Xtensa Opcodes, Up: Xtensa Synta The assembly syntax for a register file entry is the "short" name for a TIE register file followed by the index into that register file. For -example, the general-purpose `AR' register file has a short name of -`a', so these registers are named `a0'...`a15'. As a special feature, -`sp' is also supported as a synonym for `a1'. Additional registers may -be added by processor configuration options and by designer-defined TIE -extensions. An initial `$' character is optional in all register names. +example, the general-purpose 'AR' register file has a short name of 'a', +so these registers are named 'a0'...'a15'. As a special feature, 'sp' +is also supported as a synonym for 'a1'. Additional registers may be +added by processor configuration options and by designer-defined TIE +extensions. An initial '$' character is optional in all register names. File: as.info, Node: Xtensa Optimizations, Next: Xtensa Relaxation, Prev: Xtensa Syntax, Up: Xtensa-Dependent @@ -21131,7 +20915,7 @@ File: as.info, Node: Xtensa Optimizations, Next: Xtensa Relaxation, Prev: Xte 9.52.3 Xtensa Optimizations --------------------------- -The optimizations currently supported by `as' are generation of density +The optimizations currently supported by 'as' are generation of density instructions where appropriate and automatic branch target alignment. * Menu: @@ -21152,9 +20936,9 @@ assembler automatically translates instructions from the core Xtensa instruction set into equivalent instructions from the Xtensa code density option. This translation can be disabled by using underscore prefixes (*note Opcode Names: Xtensa Opcodes.), by using the -`--no-transform' command-line option (*note Command Line Options: -Xtensa Options.), or by using the `no-transform' directive (*note -transform: Transform Directive.). +'--no-transform' command-line option (*note Command Line Options: Xtensa +Options.), or by using the 'no-transform' directive (*note transform: +Transform Directive.). It is a good idea _not_ to use the density instructions directly. The assembler will automatically select dense instructions where @@ -21177,10 +20961,9 @@ align branch targets so they do not cross instruction fetch boundaries. instruction fetch widths.) An instruction immediately following a call is treated as a branch target in this context, because it will be the target of a return from the call. This alignment has the potential to -reduce branch penalties at some expense in code size. This -optimization is enabled by default. You can disable it with the -`--no-target-align' command-line option (*note Command Line Options: -Xtensa Options.). +reduce branch penalties at some expense in code size. This optimization +is enabled by default. You can disable it with the '--no-target-align' +command-line option (*note Command Line Options: Xtensa Options.). The target alignment optimization is done without adding instructions that could increase the execution time of the program. If there are @@ -21188,23 +20971,23 @@ density instructions in the code preceding a target, the assembler can change the target alignment by widening some of those instructions to the equivalent 24-bit instructions. Extra bytes of padding can be inserted immediately following unconditional jump and return -instructions. This approach is usually successful in aligning many, -but not all, branch targets. - - The `LOOP' family of instructions must be aligned such that the -first instruction in the loop body does not cross an instruction fetch -boundary (e.g., with a 32-bit fetch width, a `LOOP' instruction must be -on either a 1 or 2 mod 4 byte boundary). The assembler knows about -this restriction and inserts the minimal number of 2 or 3 byte no-op +instructions. This approach is usually successful in aligning many, but +not all, branch targets. + + The 'LOOP' family of instructions must be aligned such that the first +instruction in the loop body does not cross an instruction fetch +boundary (e.g., with a 32-bit fetch width, a 'LOOP' instruction must be +on either a 1 or 2 mod 4 byte boundary). The assembler knows about this +restriction and inserts the minimal number of 2 or 3 byte no-op instructions to satisfy it. When no-op instructions are added, any label immediately preceding the original loop will be moved in order to refer to the loop instruction, not the newly generated no-op instruction. To preserve binary compatibility across processors with different fetch widths, the assembler conservatively assumes a 32-bit -fetch width when aligning `LOOP' instructions (except if the first +fetch width when aligning 'LOOP' instructions (except if the first instruction in the loop is a 64-bit instruction). - Previous versions of the assembler automatically aligned `ENTRY' + Previous versions of the assembler automatically aligned 'ENTRY' instructions to 4-byte boundaries, but that alignment is now the programmer's responsibility. @@ -21215,12 +20998,12 @@ File: as.info, Node: Xtensa Relaxation, Next: Xtensa Directives, Prev: Xtensa ------------------------ When an instruction operand is outside the range allowed for that -particular instruction field, `as' can transform the code to use a +particular instruction field, 'as' can transform the code to use a functionally-equivalent instruction or sequence of instructions. This process is known as "relaxation". This is typically done for branch instructions because the distance of the branch targets is not known until assembly-time. The Xtensa assembler offers branch relaxation and -also extends this concept to function calls, `MOVI' instructions and +also extends this concept to function calls, 'MOVI' instructions and other instructions with immediate fields. * Menu: @@ -21248,21 +21031,21 @@ replace the branch with a branch around a jump. For example, j L M: - (The `BNEZ.N' instruction would be used in this example only if the -density option is available. Otherwise, `BNEZ' would be used.) + (The 'BNEZ.N' instruction would be used in this example only if the +density option is available. Otherwise, 'BNEZ' would be used.) This relaxation works well because the unconditional jump instruction has a much larger offset range than the various conditional branches. However, an error will occur if a branch target is beyond the range of a -jump instruction. `as' cannot relax unconditional jumps. Similarly, -an error will occur if the original input contains an unconditional -jump to a target that is out of range. +jump instruction. 'as' cannot relax unconditional jumps. Similarly, an +error will occur if the original input contains an unconditional jump to +a target that is out of range. Branch relaxation is enabled by default. It can be disabled by using underscore prefixes (*note Opcode Names: Xtensa Opcodes.), the -`--no-transform' command-line option (*note Command Line Options: -Xtensa Options.), or the `no-transform' directive (*note transform: -Transform Directive.). +'--no-transform' command-line option (*note Command Line Options: Xtensa +Options.), or the 'no-transform' directive (*note transform: Transform +Directive.). File: as.info, Node: Xtensa Call Relaxation, Next: Xtensa Immediate Relaxation, Prev: Xtensa Branch Relaxation, Up: Xtensa Relaxation @@ -21271,15 +21054,14 @@ File: as.info, Node: Xtensa Call Relaxation, Next: Xtensa Immediate Relaxation ................................. Function calls may require relaxation because the Xtensa immediate call -instructions (`CALL0', `CALL4', `CALL8' and `CALL12') provide a +instructions ('CALL0', 'CALL4', 'CALL8' and 'CALL12') provide a PC-relative offset of only 512 Kbytes in either direction. For larger -programs, it may be necessary to use indirect calls (`CALLX0', -`CALLX4', `CALLX8' and `CALLX12') where the target address is specified -in a register. The Xtensa assembler can automatically relax immediate -call instructions into indirect call instructions. This relaxation is -done by loading the address of the called function into the callee's -return address register and then using a `CALLX' instruction. So, for -example: +programs, it may be necessary to use indirect calls ('CALLX0', 'CALLX4', +'CALLX8' and 'CALLX12') where the target address is specified in a +register. The Xtensa assembler can automatically relax immediate call +instructions into indirect call instructions. This relaxation is done +by loading the address of the called function into the callee's return +address register and then using a 'CALLX' instruction. So, for example: call8 func @@ -21300,7 +21082,7 @@ assembler for those cases where direct calls are sufficient. effect on both code size and performance, although the linker can usually eliminate the unnecessary overhead. If a program is too large and some of the calls are out of range, function call relaxation can be -enabled using the `--longcalls' command-line option or the `longcalls' +enabled using the '--longcalls' command-line option or the 'longcalls' directive (*note longcalls: Longcalls Directive.). @@ -21310,14 +21092,14 @@ File: as.info, Node: Xtensa Immediate Relaxation, Prev: Xtensa Call Relaxation ......................................... The assembler normally performs the following other relaxations. They -can be disabled by using underscore prefixes (*note Opcode Names: -Xtensa Opcodes.), the `--no-transform' command-line option (*note -Command Line Options: Xtensa Options.), or the `no-transform' directive -(*note transform: Transform Directive.). +can be disabled by using underscore prefixes (*note Opcode Names: Xtensa +Opcodes.), the '--no-transform' command-line option (*note Command Line +Options: Xtensa Options.), or the 'no-transform' directive (*note +transform: Transform Directive.). - The `MOVI' machine instruction can only materialize values in the + The 'MOVI' machine instruction can only materialize values in the range from -2048 to 2047. Values outside this range are best -materialized with `L32R' instructions. Thus: +materialized with 'L32R' instructions. Thus: movi a0, 100000 @@ -21326,11 +21108,11 @@ materialized with `L32R' instructions. Thus: .literal .L1, 100000 l32r a0, .L1 - The `L8UI' machine instruction can only be used with immediate -offsets in the range from 0 to 255. The `L16SI' and `L16UI' machine -instructions can only be used with offsets from 0 to 510. The `L32I' + The 'L8UI' machine instruction can only be used with immediate +offsets in the range from 0 to 255. The 'L16SI' and 'L16UI' machine +instructions can only be used with offsets from 0 to 510. The 'L32I' machine instruction can only be used with offsets from 0 to 1020. A -load offset outside these ranges can be materialized with an `L32R' +load offset outside these ranges can be materialized with an 'L32R' instruction if the destination register of the load is different than the source address register. For example: @@ -21346,16 +21128,16 @@ the source address register. For example: If the load destination and source address register are the same, an out-of-range offset causes an error. - The Xtensa `ADDI' instruction only allows immediate operands in the + The Xtensa 'ADDI' instruction only allows immediate operands in the range from -128 to 127. There are a number of alternate instruction -sequences for the `ADDI' operation. First, if the immediate is 0, the -`ADDI' will be turned into a `MOV.N' instruction (or the equivalent -`OR' instruction if the code density option is not available). If the -`ADDI' immediate is outside of the range -128 to 127, but inside the -range -32896 to 32639, an `ADDMI' instruction or `ADDMI'/`ADDI' -sequence will be used. Finally, if the immediate is outside of this -range and a free register is available, an `L32R'/`ADD' sequence will -be used with a literal allocated from the literal pool. +sequences for the 'ADDI' operation. First, if the immediate is 0, the +'ADDI' will be turned into a 'MOV.N' instruction (or the equivalent 'OR' +instruction if the code density option is not available). If the 'ADDI' +immediate is outside of the range -128 to 127, but inside the range +-32896 to 32639, an 'ADDMI' instruction or 'ADDMI'/'ADDI' sequence will +be used. Finally, if the immediate is outside of this range and a free +register is available, an 'L32R'/'ADD' sequence will be used with a +literal allocated from the literal pool. For example: @@ -21389,9 +21171,9 @@ The Xtensa assembler supports a region-based directive syntax: All the Xtensa-specific directives that apply to a region of code use this syntax. - The directive applies to code between the `.begin' and the `.end'. -The state of the option after the `.end' reverts to what it was before -the `.begin'. A nested `.begin'/`.end' region can further change the + The directive applies to code between the '.begin' and the '.end'. +The state of the option after the '.end' reverts to what it was before +the '.begin'. A nested '.begin'/'.end' region can further change the state of the directive without having to be aware of its outer state. For example, consider: @@ -21403,16 +21185,15 @@ For example, consider: N: add a0, a1, a2 .end no-transform - The `ADD' opcodes at `L' and `N' in the outer `no-transform' region -both result in `ADD' machine instructions, but the assembler selects an -`ADD.N' instruction for the `ADD' at `M' in the inner `transform' + The 'ADD' opcodes at 'L' and 'N' in the outer 'no-transform' region +both result in 'ADD' machine instructions, but the assembler selects an +'ADD.N' instruction for the 'ADD' at 'M' in the inner 'transform' region. - The advantage of this style is that it works well inside macros -which can preserve the context of their callers. + The advantage of this style is that it works well inside macros which +can preserve the context of their callers. The following directives are available: - * Menu: * Schedule Directive:: Enable instruction scheduling. @@ -21429,13 +21210,13 @@ File: as.info, Node: Schedule Directive, Next: Longcalls Directive, Up: Xtens 9.52.5.1 schedule ................. -The `schedule' directive is recognized only for compatibility with +The 'schedule' directive is recognized only for compatibility with Tensilica's assembler. .begin [no-]schedule .end [no-]schedule - This directive is ignored and has no effect on `as'. + This directive is ignored and has no effect on 'as'. File: as.info, Node: Longcalls Directive, Next: Transform Directive, Prev: Schedule Directive, Up: Xtensa Directives @@ -21443,14 +21224,14 @@ File: as.info, Node: Longcalls Directive, Next: Transform Directive, Prev: Sc 9.52.5.2 longcalls .................. -The `longcalls' directive enables or disables function call relaxation. +The 'longcalls' directive enables or disables function call relaxation. *Note Function Call Relaxation: Xtensa Call Relaxation. .begin [no-]longcalls .end [no-]longcalls - Call relaxation is disabled by default unless the `--longcalls' -command-line option is specified. The `longcalls' directive overrides + Call relaxation is disabled by default unless the '--longcalls' +command-line option is specified. The 'longcalls' directive overrides the default determined by the command-line options. @@ -21466,8 +21247,8 @@ optimization (*note Xtensa Optimizations: Xtensa Optimizations.). .begin [no-]transform .end [no-]transform - Transformations are enabled by default unless the `--no-transform' -option is used. The `transform' directive overrides the default + Transformations are enabled by default unless the '--no-transform' +option is used. The 'transform' directive overrides the default determined by the command-line options. An underscore opcode prefix, disabling transformation of that opcode, always takes precedence over both directives and command-line flags. @@ -21478,14 +21259,14 @@ File: as.info, Node: Literal Directive, Next: Literal Position Directive, Pre 9.52.5.4 literal ................ -The `.literal' directive is used to define literal pool data, i.e., -read-only 32-bit data accessed via `L32R' instructions. +The '.literal' directive is used to define literal pool data, i.e., +read-only 32-bit data accessed via 'L32R' instructions. .literal LABEL, VALUE[, VALUE...] - This directive is similar to the standard `.word' directive, except + This directive is similar to the standard '.word' directive, except that the actual location of the literal data is determined by the -assembler and linker, not by the position of the `.literal' directive. +assembler and linker, not by the position of the '.literal' directive. Using this directive gives the assembler freedom to locate the literal data in the most appropriate place and possibly to combine identical literals. For example, the code: @@ -21494,59 +21275,58 @@ literals. For example, the code: .literal .L1, sym l32r a4, .L1 - can be used to load a pointer to the symbol `sym' into register -`a4'. The value of `sym' will not be placed between the `ENTRY' and -`L32R' instructions; instead, the assembler puts the data in a literal -pool. + can be used to load a pointer to the symbol 'sym' into register 'a4'. +The value of 'sym' will not be placed between the 'ENTRY' and 'L32R' +instructions; instead, the assembler puts the data in a literal pool. Literal pools are placed by default in separate literal sections; -however, when using the `--text-section-literals' option (*note Command +however, when using the '--text-section-literals' option (*note Command Line Options: Xtensa Options.), the literal pools for PC-relative mode -`L32R' instructions are placed in the current section.(1) These text -section literal pools are created automatically before `ENTRY' -instructions and manually after `.literal_position' directives (*note +'L32R' instructions are placed in the current section.(1) These text +section literal pools are created automatically before 'ENTRY' +instructions and manually after '.literal_position' directives (*note literal_position: Literal Position Directive.). If there are no -preceding `ENTRY' instructions, explicit `.literal_position' directives -must be used to place the text section literal pools; otherwise, `as' +preceding 'ENTRY' instructions, explicit '.literal_position' directives +must be used to place the text section literal pools; otherwise, 'as' will report an error. When literals are placed in separate sections, the literal section names are derived from the names of the sections where the literals are -defined. The base literal section names are `.literal' for PC-relative -mode `L32R' instructions and `.lit4' for absolute mode `L32R' +defined. The base literal section names are '.literal' for PC-relative +mode 'L32R' instructions and '.lit4' for absolute mode 'L32R' instructions (*note absolute-literals: Absolute Literals Directive.). -These base names are used for literals defined in the default `.text' +These base names are used for literals defined in the default '.text' section. For literals defined in other sections or within the scope of -a `literal_prefix' directive (*note literal_prefix: Literal Prefix +a 'literal_prefix' directive (*note literal_prefix: Literal Prefix Directive.), the following rules determine the literal section name: 1. If the current section is a member of a section group, the literal section name includes the group name as a suffix to the base - `.literal' or `.lit4' name, with a period to separate the base - name and group name. The literal section is also made a member of - the group. + '.literal' or '.lit4' name, with a period to separate the base name + and group name. The literal section is also made a member of the + group. - 2. If the current section name (or `literal_prefix' value) begins with - "`.gnu.linkonce.KIND.'", the literal section name is formed by - replacing "`.KIND'" with the base `.literal' or `.lit4' name. For + 2. If the current section name (or 'literal_prefix' value) begins with + "'.gnu.linkonce.KIND.'", the literal section name is formed by + replacing "'.KIND'" with the base '.literal' or '.lit4' name. For example, for literals defined in a section named - `.gnu.linkonce.t.func', the literal section will be - `.gnu.linkonce.literal.func' or `.gnu.linkonce.lit4.func'. + '.gnu.linkonce.t.func', the literal section will be + '.gnu.linkonce.literal.func' or '.gnu.linkonce.lit4.func'. - 3. If the current section name (or `literal_prefix' value) ends with - `.text', the literal section name is formed by replacing that - suffix with the base `.literal' or `.lit4' name. For example, for - literals defined in a section named `.iram0.text', the literal - section will be `.iram0.literal' or `.iram0.lit4'. + 3. If the current section name (or 'literal_prefix' value) ends with + '.text', the literal section name is formed by replacing that + suffix with the base '.literal' or '.lit4' name. For example, for + literals defined in a section named '.iram0.text', the literal + section will be '.iram0.literal' or '.iram0.lit4'. - 4. If none of the preceding conditions apply, the literal section - name is formed by adding the base `.literal' or `.lit4' name as a - suffix to the current section name (or `literal_prefix' value). + 4. If none of the preceding conditions apply, the literal section name + is formed by adding the base '.literal' or '.lit4' name as a suffix + to the current section name (or 'literal_prefix' value). ---------- Footnotes ---------- - (1) Literals for the `.init' and `.fini' sections are always placed -in separate sections, even when `--text-section-literals' is enabled. + (1) Literals for the '.init' and '.fini' sections are always placed +in separate sections, even when '--text-section-literals' is enabled. File: as.info, Node: Literal Position Directive, Next: Literal Prefix Directive, Prev: Literal Directive, Up: Xtensa Directives @@ -21554,33 +21334,33 @@ File: as.info, Node: Literal Position Directive, Next: Literal Prefix Directiv 9.52.5.5 literal_position ......................... -When using `--text-section-literals' to place literals inline in the -section being assembled, the `.literal_position' directive can be used +When using '--text-section-literals' to place literals inline in the +section being assembled, the '.literal_position' directive can be used to mark a potential location for a literal pool. .literal_position - The `.literal_position' directive is ignored when the -`--text-section-literals' option is not used or when `L32R' -instructions use the absolute addressing mode. + The '.literal_position' directive is ignored when the +'--text-section-literals' option is not used or when 'L32R' instructions +use the absolute addressing mode. The assembler will automatically place text section literal pools -before `ENTRY' instructions, so the `.literal_position' directive is +before 'ENTRY' instructions, so the '.literal_position' directive is only needed to specify some other location for a literal pool. You may need to add an explicit jump instruction to skip over an inline literal pool. - For example, an interrupt vector does not begin with an `ENTRY' + For example, an interrupt vector does not begin with an 'ENTRY' instruction so the assembler will be unable to automatically find a good place to put a literal pool. Moreover, the code for the interrupt vector must be at a specific starting address, so the literal pool cannot come before the start of the code. The literal pool for the vector must be explicitly positioned in the middle of the vector (before any uses of the literals, due to the negative offsets used by -PC-relative `L32R' instructions). The `.literal_position' directive -can be used to do this. In the following code, the literal for `M' -will automatically be aligned correctly and is placed after the -unconditional jump. +PC-relative 'L32R' instructions). The '.literal_position' directive can +be used to do this. In the following code, the literal for 'M' will +automatically be aligned correctly and is placed after the unconditional +jump. .global M code_start: @@ -21596,7 +21376,7 @@ File: as.info, Node: Literal Prefix Directive, Next: Absolute Literals Directi 9.52.5.6 literal_prefix ....................... -The `literal_prefix' directive allows you to override the default +The 'literal_prefix' directive allows you to override the default literal section names, which are derived from the names of the sections where the literals are defined. @@ -21608,7 +21388,7 @@ names are derived from the NAME argument instead of the name of the current section. The rules used to derive the literal section names do not change. *Note literal: Literal Directive. If the NAME argument is omitted, the literal sections revert to the defaults. This directive -has no effect when using the `--text-section-literals' option (*note +has no effect when using the '--text-section-literals' option (*note Command Line Options: Xtensa Options.). @@ -21617,27 +21397,27 @@ File: as.info, Node: Absolute Literals Directive, Prev: Literal Prefix Directi 9.52.5.7 absolute-literals .......................... -The `absolute-literals' and `no-absolute-literals' directives control -the absolute vs. PC-relative mode for `L32R' instructions. These are +The 'absolute-literals' and 'no-absolute-literals' directives control +the absolute vs. PC-relative mode for 'L32R' instructions. These are relevant only for Xtensa configurations that include the absolute -addressing option for `L32R' instructions. +addressing option for 'L32R' instructions. .begin [no-]absolute-literals .end [no-]absolute-literals - These directives do not change the `L32R' mode--they only cause the -assembler to emit the appropriate kind of relocation for `L32R' + These directives do not change the 'L32R' mode--they only cause the +assembler to emit the appropriate kind of relocation for 'L32R' instructions and to place the literal values in the appropriate section. -To change the `L32R' mode, the program must write the `LITBASE' special +To change the 'L32R' mode, the program must write the 'LITBASE' special register. It is the programmer's responsibility to keep track of the mode and indicate to the assembler which mode is used in each region of code. - If the Xtensa configuration includes the absolute `L32R' addressing -option, the default is to assume absolute `L32R' addressing unless the -`--no-absolute-literals' command-line option is specified. Otherwise, -the default is to assume PC-relative `L32R' addressing. The -`absolute-literals' directive can then be used to override the default + If the Xtensa configuration includes the absolute 'L32R' addressing +option, the default is to assume absolute 'L32R' addressing unless the +'--no-absolute-literals' command-line option is specified. Otherwise, +the default is to assume PC-relative 'L32R' addressing. The +'absolute-literals' directive can then be used to override the default determined by the command-line options. @@ -21646,12 +21426,12 @@ File: as.info, Node: Reporting Bugs, Next: Acknowledgements, Prev: Machine De 10 Reporting Bugs ***************** -Your bug reports play an essential role in making `as' reliable. +Your bug reports play an essential role in making 'as' reliable. Reporting a bug may help you by bringing a solution to your problem, or it may not. But in any case the principal function of a bug report -is to help the entire community by making the next version of `as' work -better. Bug reports are your contribution to the maintenance of `as'. +is to help the entire community by making the next version of 'as' work +better. Bug reports are your contribution to the maintenance of 'as'. In order for a bug report to serve its purpose, you must include the information that enables us to fix the bug. @@ -21671,17 +21451,17 @@ If you are not sure whether you have found a bug, here are some guidelines: * If the assembler gets a fatal signal, for any input whatever, that - is a `as' bug. Reliable assemblers never crash. + is a 'as' bug. Reliable assemblers never crash. - * If `as' produces an error message for valid input, that is a bug. + * If 'as' produces an error message for valid input, that is a bug. - * If `as' does not produce an error message for invalid input, that + * If 'as' does not produce an error message for invalid input, that is a bug. However, you should note that your idea of "invalid input" might be our idea of "an extension" or "support for traditional practice". * If you are an experienced user of assemblers, your suggestions for - improvement of `as' are welcome in any case. + improvement of 'as' are welcome in any case. File: as.info, Node: Bug Reporting, Prev: Bug Criteria, Up: Reporting Bugs @@ -21690,18 +21470,18 @@ File: as.info, Node: Bug Reporting, Prev: Bug Criteria, Up: Reporting Bugs ======================= A number of companies and individuals offer support for GNU products. -If you obtained `as' from a support organization, we recommend you +If you obtained 'as' from a support organization, we recommend you contact that organization first. You can find contact information for many support companies and -individuals in the file `etc/SERVICE' in the GNU Emacs distribution. +individuals in the file 'etc/SERVICE' in the GNU Emacs distribution. - In any event, we also recommend that you send bug reports for `as' -to `http://www.sourceware.org/bugzilla/ and mailto:hjl.tools@gmail.com'. + In any event, we also recommend that you send bug reports for 'as' to +<http://www.sourceware.org/bugzilla/>. - The fundamental principle of reporting bugs usefully is this: -*report all the facts*. If you are not sure whether to state a fact or -leave it out, state it! + The fundamental principle of reporting bugs usefully is this: *report +all the facts*. If you are not sure whether to state a fact or leave it +out, state it! Often people omit facts because they think they know what causes the problem and assume that some details do not matter. Thus, you might @@ -21714,8 +21494,8 @@ thing despite the bug. Play it safe and give a specific, complete example. That is the easiest thing for you to do, and the most helpful. Keep in mind that the purpose of a bug report is to enable us to fix -the bug if it is new to us. Therefore, always write your bug reports -on the assumption that the bug has not been reported previously. +the bug if it is new to us. Therefore, always write your bug reports on +the assumption that the bug has not been reported previously. Sometimes people give a few sketchy facts and ask, "Does this ring a bell?" This cannot help us fix a bug, so it is basically useless. We @@ -21724,24 +21504,24 @@ might as well expedite matters by sending them to begin with. To enable us to fix the bug, you should include all these things: - * The version of `as'. `as' announces it if you start it with the - `--version' argument. + * The version of 'as'. 'as' announces it if you start it with the + '--version' argument. Without this, we will not know whether there is any point in - looking for the bug in the current version of `as'. + looking for the bug in the current version of 'as'. - * Any patches you may have applied to the `as' source. + * Any patches you may have applied to the 'as' source. * The type of machine you are using, and the operating system name and version number. - * What compiler (and its version) was used to compile `as'--e.g. - "`gcc-2.7'". + * What compiler (and its version) was used to compile 'as'--e.g. + "'gcc-2.7'". * The command arguments you gave the assembler to assemble your example and observe the bug. To guarantee you will not omit - something important, list them all. A copy of the Makefile (or - the output from make) is sufficient. + something important, list them all. A copy of the Makefile (or the + output from make) is sufficient. If we were to try to guess the arguments, we would probably guess wrong and then we might not encounter the bug. @@ -21749,23 +21529,22 @@ might as well expedite matters by sending them to begin with. * A complete input file that will reproduce the bug. If the bug is observed when the assembler is invoked via a compiler, send the assembler source, not the high level language source. Most - compilers will produce the assembler source when run with the `-S' - option. If you are using `gcc', use the options `-v - --save-temps'; this will save the assembler source in a file with - an extension of `.s', and also show you exactly how `as' is being - run. + compilers will produce the assembler source when run with the '-S' + option. If you are using 'gcc', use the options '-v --save-temps'; + this will save the assembler source in a file with an extension of + '.s', and also show you exactly how 'as' is being run. * A description of what behavior you observe that you believe is incorrect. For example, "It gets a fatal signal." - Of course, if the bug is that `as' gets a fatal signal, then we + Of course, if the bug is that 'as' gets a fatal signal, then we will certainly notice it. But if the bug is incorrect output, we might not notice unless it is glaringly wrong. You might as well not give us a chance to make a mistake. Even if the problem you experience is a fatal signal, you should still say so explicitly. Suppose something strange is going on, - such as, your copy of `as' is out of sync, or you have encountered + such as, your copy of 'as' is out of sync, or you have encountered a bug in the C library on your system. (This has happened!) Your copy might crash and ours would not. If you told us to expect a crash, then when ours fails to crash, we would know that the bug @@ -21773,15 +21552,15 @@ might as well expedite matters by sending them to begin with. crash, then we would not be able to draw any conclusion from our observations. - * If you wish to suggest changes to the `as' source, send us context - diffs, as generated by `diff' with the `-u', `-c', or `-p' option. + * If you wish to suggest changes to the 'as' source, send us context + diffs, as generated by 'diff' with the '-u', '-c', or '-p' option. Always send diffs from the old file to the new file. If you even - discuss something in the `as' source, refer to it by context, not + discuss something in the 'as' source, refer to it by context, not by line number. - The line numbers in our development sources will not match those - in your sources. Your line numbers would convey no useful - information to us. + The line numbers in our development sources will not match those in + your sources. Your line numbers would convey no useful information + to us. Here are some things that are not necessary: @@ -21796,8 +21575,8 @@ might as well expedite matters by sending them to begin with. debugger with breakpoints, not by pure deduction from a series of examples. We recommend that you save your time for something else. - Of course, if you can find a simpler example to report _instead_ - of the original one, that is a convenience for us. Errors in the + Of course, if you can find a simpler example to report _instead_ of + the original one, that is a convenience for us. Errors in the output will be easier to spot, running under the debugger will take less time, and so on. @@ -21809,15 +21588,15 @@ might as well expedite matters by sending them to begin with. A patch for the bug does help us if it is a good one. But do not omit the necessary information, such as the test case, on the - assumption that a patch is all we need. We might see problems - with your patch and decide to fix the problem another way, or we - might not understand it at all. + assumption that a patch is all we need. We might see problems with + your patch and decide to fix the problem another way, or we might + not understand it at all. - Sometimes with a program as complicated as `as' it is very hard to + Sometimes with a program as complicated as 'as' it is very hard to construct an example that will make the program follow a certain path through the code. If you do not send us the example, we will - not be able to construct one, so we will not be able to verify - that the bug is fixed. + not be able to construct one, so we will not be able to verify that + the bug is fixed. And if we cannot understand what bug you are trying to fix, or why your patch should be an improvement, we will not install it. A @@ -21837,27 +21616,27 @@ File: as.info, Node: Acknowledgements, Next: GNU Free Documentation License, If you have contributed to GAS and your name isn't listed here, it is not meant as a slight. We just don't know about it. Send mail to the maintainer, and we'll correct the situation. Currently the maintainer -is Nick Clifton (email address `nickc@redhat.com'). +is Nick Clifton (email address 'nickc@redhat.com'). Dean Elsner wrote the original GNU assembler for the VAX.(1) Jay Fenlason maintained GAS for a while, adding support for GDB-specific debug information and the 68k series machines, most of the -preprocessing pass, and extensive changes in `messages.c', -`input-file.c', `write.c'. +preprocessing pass, and extensive changes in 'messages.c', +'input-file.c', 'write.c'. K. Richard Pixley maintained GAS for a while, adding various enhancements and many bug fixes, including merging support for several processors, breaking GAS up to handle multiple object file format back ends (including heavy rewrite, testing, an integration of the coff and b.out back ends), adding configuration including heavy testing and -verification of cross assemblers and file splits and renaming, -converted GAS to strictly ANSI C including full prototypes, added -support for m680[34]0 and cpu32, did considerable work on i960 -including a COFF port (including considerable amounts of reverse -engineering), a SPARC opcode file rewrite, DECstation, rs6000, and -hp300hpux host ports, updated "know" assertions and made them work, -much other reorganization, cleanup, and lint. +verification of cross assemblers and file splits and renaming, converted +GAS to strictly ANSI C including full prototypes, added support for +m680[34]0 and cpu32, did considerable work on i960 including a COFF port +(including considerable amounts of reverse engineering), a SPARC opcode +file rewrite, DECstation, rs6000, and hp300hpux host ports, updated +"know" assertions and made them work, much other reorganization, +cleanup, and lint. Ken Raeburn wrote the high-level BFD interface code to replace most of the code in format-specific I/O modules. @@ -21873,10 +21652,10 @@ Youngdale has done much work with it since. of Buffalo University and Torbjorn Granlund of the Swedish Institute of Computer Science. - Keith Knowles at the Open Software Foundation wrote the original -MIPS back end (`tc-mips.c', `tc-mips.h'), and contributed Rose format -support (which hasn't been merged in yet). Ralph Campbell worked with -the MIPS code to support a.out format. + Keith Knowles at the Open Software Foundation wrote the original MIPS +back end ('tc-mips.c', 'tc-mips.h'), and contributed Rose format support +(which hasn't been merged in yet). Ralph Campbell worked with the MIPS +code to support a.out format. Support for the Zilog Z8k and Renesas H8/300 processors (tc-z8k, tc-h8300), and IEEE 695 object file format (obj-ieee), was written by @@ -21884,39 +21663,39 @@ Steve Chamberlain of Cygnus Support. Steve also modified the COFF back end to use BFD for some low-level operations, for use with the H8/300 and AMD 29k targets. - John Gilmore built the AMD 29000 support, added `.include' support, + John Gilmore built the AMD 29000 support, added '.include' support, and simplified the configuration of which versions accept which directives. He updated the 68k machine description so that Motorola's -opcodes always produced fixed-size instructions (e.g., `jsr'), while -synthetic instructions remained shrinkable (`jbsr'). John fixed many +opcodes always produced fixed-size instructions (e.g., 'jsr'), while +synthetic instructions remained shrinkable ('jbsr'). John fixed many bugs, including true tested cross-compilation support, and one bug in relaxation that took a week and required the proverbial one-bit fix. - Ian Lance Taylor of Cygnus Support merged the Motorola and MIT -syntax for the 68k, completed support for some COFF targets (68k, i386 -SVR3, and SCO Unix), added support for MIPS ECOFF and ELF targets, -wrote the initial RS/6000 and PowerPC assembler, and made a few other -minor patches. + Ian Lance Taylor of Cygnus Support merged the Motorola and MIT syntax +for the 68k, completed support for some COFF targets (68k, i386 SVR3, +and SCO Unix), added support for MIPS ECOFF and ELF targets, wrote the +initial RS/6000 and PowerPC assembler, and made a few other minor +patches. Steve Chamberlain made GAS able to generate listings. Hewlett-Packard contributed support for the HP9000/300. Jeff Law wrote GAS and BFD support for the native HPPA object format -(SOM) along with a fairly extensive HPPA testsuite (for both SOM and -ELF object formats). This work was supported by both the Center for +(SOM) along with a fairly extensive HPPA testsuite (for both SOM and ELF +object formats). This work was supported by both the Center for Software Science at the University of Utah and Cygnus Support. Support for ELF format files has been worked on by Mark Eichin of Cygnus Support (original, incomplete implementation for SPARC), Pete -Hoogenboom and Jeff Law at the University of Utah (HPPA mainly), -Michael Meissner of the Open Software Foundation (i386 mainly), and Ken -Raeburn of Cygnus Support (sparc, and some initial 64-bit support). +Hoogenboom and Jeff Law at the University of Utah (HPPA mainly), Michael +Meissner of the Open Software Foundation (i386 mainly), and Ken Raeburn +of Cygnus Support (sparc, and some initial 64-bit support). Linas Vepstas added GAS support for the ESA/390 "IBM 370" architecture. - Richard Henderson rewrote the Alpha assembler. Klaus Kaempf wrote + Richard Henderson rewrote the Alpha assembler. Klaus Kaempf wrote GAS and BFD support for openVMS/Alpha. Timothy Wall, Michael Hayes, and Greg Smart contributed to the @@ -21925,8 +21704,8 @@ various tic* flavors. David Heine, Sterling Augustine, Bob Wilson and John Ruttenberg from Tensilica, Inc. added support for Xtensa processors. - Several engineers at Cygnus Support have also provided many small -bug fixes and configuration enhancements. + Several engineers at Cygnus Support have also provided many small bug +fixes and configuration enhancements. Jon Beniston added support for the Lattice Mico32 architecture. @@ -21948,7 +21727,7 @@ Appendix A GNU Free Documentation License Version 1.3, 3 November 2008 Copyright (C) 2000, 2001, 2002, 2007, 2008 Free Software Foundation, Inc. - `http://fsf.org/' + <http://fsf.org/> Everyone is permitted to copy and distribute verbatim copies of this license document, but changing it is not allowed. @@ -21973,21 +21752,21 @@ Appendix A GNU Free Documentation License free program should come with manuals providing the same freedoms that the software does. But this License is not limited to software manuals; it can be used for any textual work, regardless - of subject matter or whether it is published as a printed book. - We recommend this License principally for works whose purpose is + of subject matter or whether it is published as a printed book. We + recommend this License principally for works whose purpose is instruction or reference. 1. APPLICABILITY AND DEFINITIONS This License applies to any manual or other work, in any medium, - that contains a notice placed by the copyright holder saying it - can be distributed under the terms of this License. Such a notice + that contains a notice placed by the copyright holder saying it can + be distributed under the terms of this License. Such a notice grants a world-wide, royalty-free license, unlimited in duration, to use that work under the conditions stated herein. The "Document", below, refers to any such manual or work. Any member - of the public is a licensee, and is addressed as "you". You - accept the license if you copy, modify or distribute the work in a - way requiring permission under copyright law. + of the public is a licensee, and is addressed as "you". You accept + the license if you copy, modify or distribute the work in a way + requiring permission under copyright law. A "Modified Version" of the Document means any work containing the Document or a portion of it, either copied verbatim, or with @@ -22005,12 +21784,12 @@ Appendix A GNU Free Documentation License regarding them. The "Invariant Sections" are certain Secondary Sections whose - titles are designated, as being those of Invariant Sections, in - the notice that says that the Document is released under this - License. If a section does not fit the above definition of - Secondary then it is not allowed to be designated as Invariant. - The Document may contain zero Invariant Sections. If the Document - does not identify any Invariant Sections then there are none. + titles are designated, as being those of Invariant Sections, in the + notice that says that the Document is released under this License. + If a section does not fit the above definition of Secondary then it + is not allowed to be designated as Invariant. The Document may + contain zero Invariant Sections. If the Document does not identify + any Invariant Sections then there are none. The "Cover Texts" are certain short passages of text that are listed, as Front-Cover Texts or Back-Cover Texts, in the notice @@ -22021,27 +21800,27 @@ Appendix A GNU Free Documentation License A "Transparent" copy of the Document means a machine-readable copy, represented in a format whose specification is available to the general public, that is suitable for revising the document - straightforwardly with generic text editors or (for images - composed of pixels) generic paint programs or (for drawings) some - widely available drawing editor, and that is suitable for input to - text formatters or for automatic translation to a variety of - formats suitable for input to text formatters. A copy made in an - otherwise Transparent file format whose markup, or absence of - markup, has been arranged to thwart or discourage subsequent - modification by readers is not Transparent. An image format is - not Transparent if used for any substantial amount of text. A - copy that is not "Transparent" is called "Opaque". + straightforwardly with generic text editors or (for images composed + of pixels) generic paint programs or (for drawings) some widely + available drawing editor, and that is suitable for input to text + formatters or for automatic translation to a variety of formats + suitable for input to text formatters. A copy made in an otherwise + Transparent file format whose markup, or absence of markup, has + been arranged to thwart or discourage subsequent modification by + readers is not Transparent. An image format is not Transparent if + used for any substantial amount of text. A copy that is not + "Transparent" is called "Opaque". Examples of suitable formats for Transparent copies include plain ASCII without markup, Texinfo input format, LaTeX input format, - SGML or XML using a publicly available DTD, and - standard-conforming simple HTML, PostScript or PDF designed for - human modification. Examples of transparent image formats include - PNG, XCF and JPG. Opaque formats include proprietary formats that - can be read and edited only by proprietary word processors, SGML or - XML for which the DTD and/or processing tools are not generally - available, and the machine-generated HTML, PostScript or PDF - produced by some word processors for output purposes only. + SGML or XML using a publicly available DTD, and standard-conforming + simple HTML, PostScript or PDF designed for human modification. + Examples of transparent image formats include PNG, XCF and JPG. + Opaque formats include proprietary formats that can be read and + edited only by proprietary word processors, SGML or XML for which + the DTD and/or processing tools are not generally available, and + the machine-generated HTML, PostScript or PDF produced by some word + processors for output purposes only. The "Title Page" means, for a printed book, the title page itself, plus such following pages as are needed to hold, legibly, the @@ -22079,8 +21858,8 @@ Appendix A GNU Free Documentation License may not use technical measures to obstruct or control the reading or further copying of the copies you make or distribute. However, you may accept compensation in exchange for copies. If you - distribute a large enough number of copies you must also follow - the conditions in section 3. + distribute a large enough number of copies you must also follow the + conditions in section 3. You may also lend copies, under the same conditions stated above, and you may publicly display copies. @@ -22094,12 +21873,11 @@ Appendix A GNU Free Documentation License these Cover Texts: Front-Cover Texts on the front cover, and Back-Cover Texts on the back cover. Both covers must also clearly and legibly identify you as the publisher of these copies. The - front cover must present the full title with all words of the - title equally prominent and visible. You may add other material - on the covers in addition. Copying with changes limited to the - covers, as long as they preserve the title of the Document and - satisfy these conditions, can be treated as verbatim copying in - other respects. + front cover must present the full title with all words of the title + equally prominent and visible. You may add other material on the + covers in addition. Copying with changes limited to the covers, as + long as they preserve the title of the Document and satisfy these + conditions, can be treated as verbatim copying in other respects. If the required texts for either cover are too voluminous to fit legibly, you should put the first ones listed (as many as fit @@ -22107,40 +21885,39 @@ Appendix A GNU Free Documentation License adjacent pages. If you publish or distribute Opaque copies of the Document - numbering more than 100, you must either include a - machine-readable Transparent copy along with each Opaque copy, or - state in or with each Opaque copy a computer-network location from - which the general network-using public has access to download - using public-standard network protocols a complete Transparent - copy of the Document, free of added material. If you use the - latter option, you must take reasonably prudent steps, when you - begin distribution of Opaque copies in quantity, to ensure that - this Transparent copy will remain thus accessible at the stated - location until at least one year after the last time you - distribute an Opaque copy (directly or through your agents or - retailers) of that edition to the public. + numbering more than 100, you must either include a machine-readable + Transparent copy along with each Opaque copy, or state in or with + each Opaque copy a computer-network location from which the general + network-using public has access to download using public-standard + network protocols a complete Transparent copy of the Document, free + of added material. If you use the latter option, you must take + reasonably prudent steps, when you begin distribution of Opaque + copies in quantity, to ensure that this Transparent copy will + remain thus accessible at the stated location until at least one + year after the last time you distribute an Opaque copy (directly or + through your agents or retailers) of that edition to the public. It is requested, but not required, that you contact the authors of - the Document well before redistributing any large number of - copies, to give them a chance to provide you with an updated - version of the Document. + the Document well before redistributing any large number of copies, + to give them a chance to provide you with an updated version of the + Document. 4. MODIFICATIONS You may copy and distribute a Modified Version of the Document under the conditions of sections 2 and 3 above, provided that you - release the Modified Version under precisely this License, with - the Modified Version filling the role of the Document, thus - licensing distribution and modification of the Modified Version to - whoever possesses a copy of it. In addition, you must do these - things in the Modified Version: + release the Modified Version under precisely this License, with the + Modified Version filling the role of the Document, thus licensing + distribution and modification of the Modified Version to whoever + possesses a copy of it. In addition, you must do these things in + the Modified Version: A. Use in the Title Page (and on the covers, if any) a title - distinct from that of the Document, and from those of - previous versions (which should, if there were any, be listed - in the History section of the Document). You may use the - same title as a previous version if the original publisher of - that version gives permission. + distinct from that of the Document, and from those of previous + versions (which should, if there were any, be listed in the + History section of the Document). You may use the same title + as a previous version if the original publisher of that + version gives permission. B. List on the Title Page, as authors, one or more persons or entities responsible for authorship of the modifications in @@ -22170,31 +21947,30 @@ Appendix A GNU Free Documentation License I. Preserve the section Entitled "History", Preserve its Title, and add to it an item stating at least the title, year, new - authors, and publisher of the Modified Version as given on - the Title Page. If there is no section Entitled "History" in - the Document, create one stating the title, year, authors, - and publisher of the Document as given on its Title Page, - then add an item describing the Modified Version as stated in - the previous sentence. + authors, and publisher of the Modified Version as given on the + Title Page. If there is no section Entitled "History" in the + Document, create one stating the title, year, authors, and + publisher of the Document as given on its Title Page, then add + an item describing the Modified Version as stated in the + previous sentence. J. Preserve the network location, if any, given in the Document for public access to a Transparent copy of the Document, and likewise the network locations given in the Document for - previous versions it was based on. These may be placed in - the "History" section. You may omit a network location for a - work that was published at least four years before the - Document itself, or if the original publisher of the version - it refers to gives permission. + previous versions it was based on. These may be placed in the + "History" section. You may omit a network location for a work + that was published at least four years before the Document + itself, or if the original publisher of the version it refers + to gives permission. K. For any section Entitled "Acknowledgements" or "Dedications", - Preserve the Title of the section, and preserve in the - section all the substance and tone of each of the contributor + Preserve the Title of the section, and preserve in the section + all the substance and tone of each of the contributor acknowledgements and/or dedications given therein. - L. Preserve all the Invariant Sections of the Document, - unaltered in their text and in their titles. Section numbers - or the equivalent are not considered part of the section - titles. + L. Preserve all the Invariant Sections of the Document, unaltered + in their text and in their titles. Section numbers or the + equivalent are not considered part of the section titles. M. Delete any section Entitled "Endorsements". Such a section may not be included in the Modified Version. @@ -22207,11 +21983,11 @@ Appendix A GNU Free Documentation License If the Modified Version includes new front-matter sections or appendices that qualify as Secondary Sections and contain no - material copied from the Document, you may at your option - designate some or all of these sections as invariant. To do this, - add their titles to the list of Invariant Sections in the Modified - Version's license notice. These titles must be distinct from any - other section titles. + material copied from the Document, you may at your option designate + some or all of these sections as invariant. To do this, add their + titles to the list of Invariant Sections in the Modified Version's + license notice. These titles must be distinct from any other + section titles. You may add a section Entitled "Endorsements", provided it contains nothing but endorsements of your Modified Version by various @@ -22220,15 +21996,15 @@ Appendix A GNU Free Documentation License definition of a standard. You may add a passage of up to five words as a Front-Cover Text, - and a passage of up to 25 words as a Back-Cover Text, to the end - of the list of Cover Texts in the Modified Version. Only one - passage of Front-Cover Text and one of Back-Cover Text may be - added by (or through arrangements made by) any one entity. If the - Document already includes a cover text for the same cover, - previously added by you or by arrangement made by the same entity - you are acting on behalf of, you may not add another; but you may - replace the old one, on explicit permission from the previous - publisher that added the old one. + and a passage of up to 25 words as a Back-Cover Text, to the end of + the list of Cover Texts in the Modified Version. Only one passage + of Front-Cover Text and one of Back-Cover Text may be added by (or + through arrangements made by) any one entity. If the Document + already includes a cover text for the same cover, previously added + by you or by arrangement made by the same entity you are acting on + behalf of, you may not add another; but you may replace the old + one, on explicit permission from the previous publisher that added + the old one. The author(s) and publisher(s) of the Document do not by this License give permission to use their names for publicity for or to @@ -22238,8 +22014,8 @@ Appendix A GNU Free Documentation License You may combine the Document with other documents released under this License, under the terms defined in section 4 above for - modified versions, provided that you include in the combination - all of the Invariant Sections of all of the original documents, + modified versions, provided that you include in the combination all + of the Invariant Sections of all of the original documents, unmodified, and list them all as Invariant Sections of your combined work in its license notice, and that you preserve all their Warranty Disclaimers. @@ -22266,20 +22042,20 @@ Appendix A GNU Free Documentation License documents released under this License, and replace the individual copies of this License in the various documents with a single copy that is included in the collection, provided that you follow the - rules of this License for verbatim copying of each of the - documents in all other respects. + rules of this License for verbatim copying of each of the documents + in all other respects. You may extract a single document from such a collection, and distribute it individually under this License, provided you insert - a copy of this License into the extracted document, and follow - this License in all other respects regarding verbatim copying of - that document. + a copy of this License into the extracted document, and follow this + License in all other respects regarding verbatim copying of that + document. 7. AGGREGATION WITH INDEPENDENT WORKS A compilation of the Document or its derivatives with other - separate and independent documents or works, in or on a volume of - a storage or distribution medium, is called an "aggregate" if the + separate and independent documents or works, in or on a volume of a + storage or distribution medium, is called an "aggregate" if the copyright resulting from the compilation is not used to limit the legal rights of the compilation's users beyond what the individual works permit. When the Document is included in an aggregate, this @@ -22324,8 +22100,8 @@ Appendix A GNU Free Documentation License However, if you cease all violation of this License, then your license from a particular copyright holder is reinstated (a) - provisionally, unless and until the copyright holder explicitly - and finally terminates your license, and (b) permanently, if the + provisionally, unless and until the copyright holder explicitly and + finally terminates your license, and (b) permanently, if the copyright holder fails to notify you of the violation by some reasonable means prior to 60 days after the cessation. @@ -22337,33 +22113,33 @@ Appendix A GNU Free Documentation License after your receipt of the notice. Termination of your rights under this section does not terminate - the licenses of parties who have received copies or rights from - you under this License. If your rights have been terminated and - not permanently reinstated, receipt of a copy of some or all of - the same material does not give you any rights to use it. + the licenses of parties who have received copies or rights from you + under this License. If your rights have been terminated and not + permanently reinstated, receipt of a copy of some or all of the + same material does not give you any rights to use it. - 10. FUTURE REVISIONS OF THIS LICENSE + 10. FUTURE REVISIONS OF THIS LICENSE The Free Software Foundation may publish new, revised versions of the GNU Free Documentation License from time to time. Such new versions will be similar in spirit to the present version, but may differ in detail to address new problems or concerns. See - `http://www.gnu.org/copyleft/'. + <http://www.gnu.org/copyleft/>. Each version of the License is given a distinguishing version number. If the Document specifies that a particular numbered version of this License "or any later version" applies to it, you have the option of following the terms and conditions either of that specified version or of any later version that has been - published (not as a draft) by the Free Software Foundation. If - the Document does not specify a version number of this License, - you may choose any version ever published (not as a draft) by the - Free Software Foundation. If the Document specifies that a proxy - can decide which future versions of this License can be used, that + published (not as a draft) by the Free Software Foundation. If the + Document does not specify a version number of this License, you may + choose any version ever published (not as a draft) by the Free + Software Foundation. If the Document specifies that a proxy can + decide which future versions of this License can be used, that proxy's public statement of acceptance of a version permanently authorizes you to choose that version for the Document. - 11. RELICENSING + 11. RELICENSING "Massive Multiauthor Collaboration Site" (or "MMC Site") means any World Wide Web server that publishes copyrightable works and also @@ -22393,7 +22169,6 @@ Appendix A GNU Free Documentation License site under CC-BY-SA on the same site at any time before August 1, 2009, provided the MMC is eligible for relicensing. - ADDENDUM: How to use this License for your documents ==================================================== @@ -22410,7 +22185,7 @@ notices just after the title page: Free Documentation License''. If you have Invariant Sections, Front-Cover Texts and Back-Cover -Texts, replace the "with...Texts." line with this: +Texts, replace the "with...Texts." line with this: with the Invariant Sections being LIST THEIR TITLES, with the Front-Cover Texts being LIST, and with the Back-Cover Texts @@ -22421,9 +22196,9 @@ combination of the three, merge those two alternatives to suit the situation. If your document contains nontrivial examples of program code, we -recommend releasing these examples in parallel under your choice of -free software license, such as the GNU General Public License, to -permit their use in free software. +recommend releasing these examples in parallel under your choice of free +software license, such as the GNU General Public License, to permit +their use in free software. File: as.info, Node: AS Index, Prev: GNU Free Documentation License, Up: Top @@ -22437,147 +22212,151 @@ AS Index * #: Comments. (line 33) * #APP: Preprocessing. (line 26) * #NO_APP: Preprocessing. (line 26) -* $ in symbol names <1>: SH64-Chars. (line 15) -* $ in symbol names <2>: SH-Chars. (line 15) -* $ in symbol names <3>: Meta-Chars. (line 10) -* $ in symbol names <4>: D30V-Chars. (line 70) -* $ in symbol names: D10V-Chars. (line 53) -* $a: ARM Mapping Symbols. (line 9) -* $acos math builtin, TIC54X: TIC54X-Builtins. (line 10) -* $asin math builtin, TIC54X: TIC54X-Builtins. (line 13) -* $atan math builtin, TIC54X: TIC54X-Builtins. (line 16) -* $atan2 math builtin, TIC54X: TIC54X-Builtins. (line 19) -* $ceil math builtin, TIC54X: TIC54X-Builtins. (line 22) -* $cos math builtin, TIC54X: TIC54X-Builtins. (line 28) -* $cosh math builtin, TIC54X: TIC54X-Builtins. (line 25) -* $cvf math builtin, TIC54X: TIC54X-Builtins. (line 31) -* $cvi math builtin, TIC54X: TIC54X-Builtins. (line 34) -* $d <1>: ARM Mapping Symbols. (line 15) -* $d: AArch64 Mapping Symbols. +* '$' in symbol names: D10V-Chars. (line 46) +* '$' in symbol names <1>: D30V-Chars. (line 70) +* '$' in symbol names <2>: Meta-Chars. (line 10) +* '$' in symbol names <3>: SH-Chars. (line 15) +* '$' in symbol names <4>: SH64-Chars. (line 15) +* '$a': ARM Mapping Symbols. (line 9) +* '$acos' math builtin, TIC54X: TIC54X-Builtins. (line 10) +* '$asin' math builtin, TIC54X: TIC54X-Builtins. (line 13) +* '$atan' math builtin, TIC54X: TIC54X-Builtins. (line 16) +* '$atan2' math builtin, TIC54X: TIC54X-Builtins. (line 19) +* '$ceil' math builtin, TIC54X: TIC54X-Builtins. (line 22) +* '$cos' math builtin, TIC54X: TIC54X-Builtins. (line 28) +* '$cosh' math builtin, TIC54X: TIC54X-Builtins. (line 25) +* '$cvf' math builtin, TIC54X: TIC54X-Builtins. (line 31) +* '$cvi' math builtin, TIC54X: TIC54X-Builtins. (line 34) +* '$d': AArch64 Mapping Symbols. (line 12) -* $exp math builtin, TIC54X: TIC54X-Builtins. (line 37) -* $fabs math builtin, TIC54X: TIC54X-Builtins. (line 40) -* $firstch subsym builtin, TIC54X: TIC54X-Macros. (line 26) -* $floor math builtin, TIC54X: TIC54X-Builtins. (line 43) -* $fmod math builtin, TIC54X: TIC54X-Builtins. (line 47) -* $int math builtin, TIC54X: TIC54X-Builtins. (line 50) -* $iscons subsym builtin, TIC54X: TIC54X-Macros. (line 43) -* $isdefed subsym builtin, TIC54X: TIC54X-Macros. (line 34) -* $ismember subsym builtin, TIC54X: TIC54X-Macros. (line 38) -* $isname subsym builtin, TIC54X: TIC54X-Macros. (line 47) -* $isreg subsym builtin, TIC54X: TIC54X-Macros. (line 50) -* $lastch subsym builtin, TIC54X: TIC54X-Macros. (line 30) -* $ldexp math builtin, TIC54X: TIC54X-Builtins. (line 53) -* $log math builtin, TIC54X: TIC54X-Builtins. (line 59) -* $log10 math builtin, TIC54X: TIC54X-Builtins. (line 56) -* $max math builtin, TIC54X: TIC54X-Builtins. (line 62) -* $min math builtin, TIC54X: TIC54X-Builtins. (line 65) -* $pow math builtin, TIC54X: TIC54X-Builtins. (line 68) -* $round math builtin, TIC54X: TIC54X-Builtins. (line 71) -* $sgn math builtin, TIC54X: TIC54X-Builtins. (line 74) -* $sin math builtin, TIC54X: TIC54X-Builtins. (line 77) -* $sinh math builtin, TIC54X: TIC54X-Builtins. (line 80) -* $sqrt math builtin, TIC54X: TIC54X-Builtins. (line 83) -* $structacc subsym builtin, TIC54X: TIC54X-Macros. (line 57) -* $structsz subsym builtin, TIC54X: TIC54X-Macros. (line 54) -* $symcmp subsym builtin, TIC54X: TIC54X-Macros. (line 23) -* $symlen subsym builtin, TIC54X: TIC54X-Macros. (line 20) -* $t: ARM Mapping Symbols. (line 12) -* $tan math builtin, TIC54X: TIC54X-Builtins. (line 86) -* $tanh math builtin, TIC54X: TIC54X-Builtins. (line 89) -* $trunc math builtin, TIC54X: TIC54X-Builtins. (line 92) -* $x: AArch64 Mapping Symbols. +* '$d' <1>: ARM Mapping Symbols. (line 15) +* '$exp' math builtin, TIC54X: TIC54X-Builtins. (line 37) +* '$fabs' math builtin, TIC54X: TIC54X-Builtins. (line 40) +* '$firstch' subsym builtin, TIC54X: TIC54X-Macros. (line 26) +* '$floor' math builtin, TIC54X: TIC54X-Builtins. (line 43) +* '$fmod' math builtin, TIC54X: TIC54X-Builtins. (line 47) +* '$int' math builtin, TIC54X: TIC54X-Builtins. (line 50) +* '$iscons' subsym builtin, TIC54X: TIC54X-Macros. (line 43) +* '$isdefed' subsym builtin, TIC54X: TIC54X-Macros. (line 34) +* '$ismember' subsym builtin, TIC54X: TIC54X-Macros. (line 38) +* '$isname' subsym builtin, TIC54X: TIC54X-Macros. (line 47) +* '$isreg' subsym builtin, TIC54X: TIC54X-Macros. (line 50) +* '$lastch' subsym builtin, TIC54X: TIC54X-Macros. (line 30) +* '$ldexp' math builtin, TIC54X: TIC54X-Builtins. (line 53) +* '$log' math builtin, TIC54X: TIC54X-Builtins. (line 59) +* '$log10' math builtin, TIC54X: TIC54X-Builtins. (line 56) +* '$max' math builtin, TIC54X: TIC54X-Builtins. (line 62) +* '$min' math builtin, TIC54X: TIC54X-Builtins. (line 65) +* '$pow' math builtin, TIC54X: TIC54X-Builtins. (line 68) +* '$round' math builtin, TIC54X: TIC54X-Builtins. (line 71) +* '$sgn' math builtin, TIC54X: TIC54X-Builtins. (line 74) +* '$sin' math builtin, TIC54X: TIC54X-Builtins. (line 77) +* '$sinh' math builtin, TIC54X: TIC54X-Builtins. (line 80) +* '$sqrt' math builtin, TIC54X: TIC54X-Builtins. (line 83) +* '$structacc' subsym builtin, TIC54X: TIC54X-Macros. (line 57) +* '$structsz' subsym builtin, TIC54X: TIC54X-Macros. (line 54) +* '$symcmp' subsym builtin, TIC54X: TIC54X-Macros. (line 23) +* '$symlen' subsym builtin, TIC54X: TIC54X-Macros. (line 20) +* '$t': ARM Mapping Symbols. (line 12) +* '$tan' math builtin, TIC54X: TIC54X-Builtins. (line 86) +* '$tanh' math builtin, TIC54X: TIC54X-Builtins. (line 89) +* '$trunc' math builtin, TIC54X: TIC54X-Builtins. (line 92) +* '$x': AArch64 Mapping Symbols. (line 9) * %gp: RX-Modifiers. (line 6) -* %gpreg: RX-Modifiers. (line 22) -* %pidreg: RX-Modifiers. (line 25) -* -+ option, VAX/VMS: VAX-Opts. (line 71) +* '%gpreg': RX-Modifiers. (line 22) +* '%pidreg': RX-Modifiers. (line 25) +* '-+' option, VAX/VMS: VAX-Opts. (line 71) * --: Command Line. (line 10) -* --32 option, i386: i386-Options. (line 8) -* --32 option, x86-64: i386-Options. (line 8) -* --64 option, i386: i386-Options. (line 8) -* --64 option, x86-64: i386-Options. (line 8) -* --absolute-literals: Xtensa Options. (line 21) +* '--32' option, i386: i386-Options. (line 8) +* '--32' option, x86-64: i386-Options. (line 8) +* '--64' option, i386: i386-Options. (line 8) +* '--64' option, x86-64: i386-Options. (line 8) +* --absolute-literals: Xtensa Options. (line 20) * --allow-reg-prefix: SH Options. (line 9) * --alternate: alternate. (line 6) -* --base-size-default-16: M68K-Opts. (line 65) -* --base-size-default-32: M68K-Opts. (line 65) +* '--base-size-default-16': M68K-Opts. (line 66) +* '--base-size-default-32': M68K-Opts. (line 66) * --big: SH Options. (line 9) -* --bitwise-or option, M680x0: M68K-Opts. (line 58) -* --disp-size-default-16: M68K-Opts. (line 74) -* --disp-size-default-32: M68K-Opts. (line 74) -* --divide option, i386: i386-Options. (line 24) +* '--bitwise-or' option, M680x0: M68K-Opts. (line 59) +* '--disp-size-default-16': M68K-Opts. (line 75) +* '--disp-size-default-32': M68K-Opts. (line 75) +* '--divide' option, i386: i386-Options. (line 24) * --dsp: SH Options. (line 9) -* --emulation=crisaout command line option, CRIS: CRIS-Opts. (line 9) -* --emulation=criself command line option, CRIS: CRIS-Opts. (line 9) +* '--emulation=crisaout' command line option, CRIS: CRIS-Opts. + (line 9) +* '--emulation=criself' command line option, CRIS: CRIS-Opts. (line 9) * --enforce-aligned-data: Sparc-Aligned-Data. (line 11) * --fatal-warnings: W. (line 16) * --fdpic: SH Options. (line 31) -* --fix-v4bx command line option, ARM: ARM Options. (line 173) -* --fixed-special-register-names command line option, MMIX: MMIX-Opts. +* '--fix-v4bx' command line option, ARM: ARM Options. (line 174) +* '--fixed-special-register-names' command line option, MMIX: MMIX-Opts. (line 8) -* --force-long-branches: M68HC11-Opts. (line 82) -* --generate-example: M68HC11-Opts. (line 99) -* --globalize-symbols command line option, MMIX: MMIX-Opts. (line 12) -* --gnu-syntax command line option, MMIX: MMIX-Opts. (line 16) -* --hash-size=NUMBER: Overview. (line 387) -* --linker-allocated-gregs command line option, MMIX: MMIX-Opts. +* '--force-long-branches': M68HC11-Opts. (line 81) +* '--generate-example': M68HC11-Opts. (line 98) +* '--globalize-symbols' command line option, MMIX: MMIX-Opts. (line 12) +* '--gnu-syntax' command line option, MMIX: MMIX-Opts. (line 16) +* --hash-size=NUMBER: Overview. (line 400) +* '--linker-allocated-gregs' command line option, MMIX: MMIX-Opts. (line 67) * --listing-cont-lines: listing. (line 34) * --listing-lhs-width: listing. (line 16) * --listing-lhs-width2: listing. (line 21) * --listing-rhs-width: listing. (line 28) * --little: SH Options. (line 9) -* --longcalls: Xtensa Options. (line 35) -* --march=ARCHITECTURE command line option, CRIS: CRIS-Opts. (line 34) +* --longcalls: Xtensa Options. (line 34) +* '--march=ARCHITECTURE' command line option, CRIS: CRIS-Opts. + (line 34) * --MD: MD. (line 6) -* --mul-bug-abort command line option, CRIS: CRIS-Opts. (line 62) -* --no-absolute-literals: Xtensa Options. (line 21) -* --no-expand command line option, MMIX: MMIX-Opts. (line 31) -* --no-longcalls: Xtensa Options. (line 35) -* --no-merge-gregs command line option, MMIX: MMIX-Opts. (line 36) -* --no-mul-bug-abort command line option, CRIS: CRIS-Opts. (line 62) -* --no-predefined-syms command line option, MMIX: MMIX-Opts. (line 22) -* --no-pushj-stubs command line option, MMIX: MMIX-Opts. (line 54) -* --no-stubs command line option, MMIX: MMIX-Opts. (line 54) -* --no-target-align: Xtensa Options. (line 28) +* '--mul-bug-abort' command line option, CRIS: CRIS-Opts. (line 63) +* --no-absolute-literals: Xtensa Options. (line 20) +* '--no-expand' command line option, MMIX: MMIX-Opts. (line 31) +* --no-longcalls: Xtensa Options. (line 34) +* '--no-merge-gregs' command line option, MMIX: MMIX-Opts. (line 36) +* '--no-mul-bug-abort' command line option, CRIS: CRIS-Opts. (line 63) +* '--no-predefined-syms' command line option, MMIX: MMIX-Opts. + (line 22) +* '--no-pushj-stubs' command line option, MMIX: MMIX-Opts. (line 54) +* '--no-stubs' command line option, MMIX: MMIX-Opts. (line 54) +* --no-target-align: Xtensa Options. (line 27) * --no-text-section-literals: Xtensa Options. (line 7) -* --no-transform: Xtensa Options. (line 44) -* --no-underscore command line option, CRIS: CRIS-Opts. (line 15) +* --no-transform: Xtensa Options. (line 43) +* '--no-underscore' command line option, CRIS: CRIS-Opts. (line 15) * --no-warn: W. (line 11) -* --pcrel: M68K-Opts. (line 86) -* --pic command line option, CRIS: CRIS-Opts. (line 27) -* --print-insn-syntax <1>: XGATE-Opts. (line 25) -* --print-insn-syntax: M68HC11-Opts. (line 88) -* --print-opcodes <1>: XGATE-Opts. (line 29) -* --print-opcodes: M68HC11-Opts. (line 92) -* --register-prefix-optional option, M680x0: M68K-Opts. (line 45) +* '--pcrel': M68K-Opts. (line 87) +* '--pic' command line option, CRIS: CRIS-Opts. (line 27) +* '--print-insn-syntax': M68HC11-Opts. (line 87) +* '--print-insn-syntax' <1>: XGATE-Opts. (line 25) +* '--print-opcodes': M68HC11-Opts. (line 91) +* '--print-opcodes' <1>: XGATE-Opts. (line 29) +* '--register-prefix-optional' option, M680x0: M68K-Opts. (line 46) * --relax: SH Options. (line 9) -* --relax command line option, MMIX: MMIX-Opts. (line 19) -* --rename-section: Xtensa Options. (line 52) +* '--relax' command line option, MMIX: MMIX-Opts. (line 19) +* --rename-section: Xtensa Options. (line 51) * --renesas: SH Options. (line 9) -* --short-branches: M68HC11-Opts. (line 67) +* '--short-branches': M68HC11-Opts. (line 67) * --small: SH Options. (line 9) * --statistics: statistics. (line 6) -* --strict-direct-mode: M68HC11-Opts. (line 57) -* --target-align: Xtensa Options. (line 28) +* '--strict-direct-mode': M68HC11-Opts. (line 57) +* --target-align: Xtensa Options. (line 27) * --text-section-literals: Xtensa Options. (line 7) * --traditional-format: traditional-format. (line 6) -* --transform: Xtensa Options. (line 44) -* --underscore command line option, CRIS: CRIS-Opts. (line 15) +* --transform: Xtensa Options. (line 43) +* '--underscore' command line option, CRIS: CRIS-Opts. (line 15) * --warn: W. (line 19) -* --x32 option, i386: i386-Options. (line 8) -* --x32 option, x86-64: i386-Options. (line 8) -* --xgate-ramoffset: M68HC11-Opts. (line 36) -* -1 option, VAX/VMS: VAX-Opts. (line 77) -* -32addr command line option, Alpha: Alpha Options. (line 57) +* '--x32' option, i386: i386-Options. (line 8) +* '--x32' option, x86-64: i386-Options. (line 8) +* '--xgate-ramoffset': M68HC11-Opts. (line 36) +* '-1' option, VAX/VMS: VAX-Opts. (line 77) +* '-32addr' command line option, Alpha: Alpha Options. (line 57) * -a: a. (line 6) -* -A options, i960: Options-i960. (line 6) +* '-A' options, i960: Options-i960. (line 6) * -ac: a. (line 6) * -ad: a. (line 6) * -ag: a. (line 6) * -ah: a. (line 6) * -al: a. (line 6) +* -Aleon: Sparc-Opts. (line 25) * -an: a. (line 6) * -as: a. (line 6) * -Asparc: Sparc-Opts. (line 25) @@ -22598,42 +22377,42 @@ AS Index * -Av9c: Sparc-Opts. (line 25) * -Av9d: Sparc-Opts. (line 25) * -Av9v: Sparc-Opts. (line 25) -* -b option, i960: Options-i960. (line 22) -* -big option, M32R: M32R-Opts. (line 35) +* '-b' option, i960: Options-i960. (line 22) +* '-big' option, M32R: M32R-Opts. (line 35) * -D: D. (line 6) -* -D, ignored on VAX: VAX-Opts. (line 11) -* -d, VAX option: VAX-Opts. (line 16) -* -eabi= command line option, ARM: ARM Options. (line 156) -* -EB command line option, AArch64: AArch64 Options. (line 6) -* -EB command line option, ARC: ARC Options. (line 31) -* -EB command line option, ARM: ARM Options. (line 161) -* -EB option (MIPS): MIPS Opts. (line 13) -* -EB option, M32R: M32R-Opts. (line 39) -* -EB option, TILE-Gx: TILE-Gx Options. (line 11) -* -EL command line option, AArch64: AArch64 Options. (line 10) -* -EL command line option, ARC: ARC Options. (line 35) -* -EL command line option, ARM: ARM Options. (line 165) -* -EL option (MIPS): MIPS Opts. (line 13) -* -EL option, M32R: M32R-Opts. (line 32) -* -EL option, TILE-Gx: TILE-Gx Options. (line 11) +* '-D', ignored on VAX: VAX-Opts. (line 11) +* '-d', VAX option: VAX-Opts. (line 16) +* '-eabi=' command line option, ARM: ARM Options. (line 157) +* '-EB' command line option, AArch64: AArch64 Options. (line 6) +* '-EB' command line option, ARC: ARC Options. (line 30) +* '-EB' command line option, ARM: ARM Options. (line 162) +* '-EB' option (MIPS): MIPS Options. (line 13) +* '-EB' option, M32R: M32R-Opts. (line 39) +* '-EB' option, TILE-Gx: TILE-Gx Options. (line 11) +* '-EL' command line option, AArch64: AArch64 Options. (line 10) +* '-EL' command line option, ARC: ARC Options. (line 34) +* '-EL' command line option, ARM: ARM Options. (line 166) +* '-EL' option (MIPS): MIPS Options. (line 13) +* '-EL' option, M32R: M32R-Opts. (line 32) +* '-EL' option, TILE-Gx: TILE-Gx Options. (line 11) * -f: f. (line 6) -* -F command line option, Alpha: Alpha Options. (line 57) -* -G command line option, Alpha: Alpha Options. (line 53) -* -g command line option, Alpha: Alpha Options. (line 47) -* -G option (MIPS): MIPS Opts. (line 8) -* -H option, VAX/VMS: VAX-Opts. (line 81) -* -h option, VAX/VMS: VAX-Opts. (line 45) +* '-F' command line option, Alpha: Alpha Options. (line 57) +* '-g' command line option, Alpha: Alpha Options. (line 47) +* '-G' command line option, Alpha: Alpha Options. (line 53) +* '-G' option (MIPS): MIPS Options. (line 8) +* '-h' option, VAX/VMS: VAX-Opts. (line 45) +* '-H' option, VAX/VMS: VAX-Opts. (line 81) * -I PATH: I. (line 6) -* -ignore-parallel-conflicts option, M32RX: M32R-Opts. (line 87) -* -Ip option, M32RX: M32R-Opts. (line 97) -* -J, ignored on VAX: VAX-Opts. (line 27) +* '-ignore-parallel-conflicts' option, M32RX: M32R-Opts. (line 87) +* '-Ip' option, M32RX: M32R-Opts. (line 97) +* '-J', ignored on VAX: VAX-Opts. (line 27) * -K: K. (line 6) -* -k command line option, ARM: ARM Options. (line 169) -* -KPIC option, M32R: M32R-Opts. (line 42) -* -KPIC option, MIPS: MIPS Opts. (line 21) +* '-k' command line option, ARM: ARM Options. (line 170) +* '-KPIC' option, M32R: M32R-Opts. (line 42) +* '-KPIC' option, MIPS: MIPS Options. (line 21) * -L: L. (line 6) -* -l option, M680x0: M68K-Opts. (line 33) -* -little option, M32R: M32R-Opts. (line 27) +* '-l' option, M680x0: M68K-Opts. (line 34) +* '-little' option, M32R: M32R-Opts. (line 27) * -M: M. (line 6) * -m11/03: PDP-11-Options. (line 140) * -m11/04: PDP-11-Options. (line 143) @@ -22660,88 +22439,90 @@ AS Index * -m11/84: PDP-11-Options. (line 173) * -m11/93: PDP-11-Options. (line 173) * -m11/94: PDP-11-Options. (line 173) -* -m16c option, M16C: M32C-Opts. (line 12) -* -m31 option, s390: s390 Options. (line 8) -* -m32 option, TILE-Gx: TILE-Gx Options. (line 8) -* -m32bit-doubles: RX-Opts. (line 9) -* -m32c option, M32C: M32C-Opts. (line 9) -* -m32r option, M32R: M32R-Opts. (line 21) -* -m32rx option, M32R2: M32R-Opts. (line 17) -* -m32rx option, M32RX: M32R-Opts. (line 9) -* -m4byte-align command line option, V850: V850 Options. (line 90) -* -m64 option, s390: s390 Options. (line 8) -* -m64 option, TILE-Gx: TILE-Gx Options. (line 8) -* -m64bit-doubles: RX-Opts. (line 15) -* -m68000 and related options: M68K-Opts. (line 98) -* -m68hc11: M68HC11-Opts. (line 9) -* -m68hc12: M68HC11-Opts. (line 14) -* -m68hcs12: M68HC11-Opts. (line 21) -* -m8byte-align command line option, V850: V850 Options. (line 86) -* -m[no-]68851 command line option, M680x0: M68K-Opts. (line 21) -* -m[no-]68881 command line option, M680x0: M68K-Opts. (line 21) -* -m[no-]div command line option, M680x0: M68K-Opts. (line 21) -* -m[no-]emac command line option, M680x0: M68K-Opts. (line 21) -* -m[no-]float command line option, M680x0: M68K-Opts. (line 21) -* -m[no-]mac command line option, M680x0: M68K-Opts. (line 21) -* -m[no-]usp command line option, M680x0: M68K-Opts. (line 21) +* '-m16c' option, M16C: M32C-Opts. (line 12) +* '-m31' option, s390: s390 Options. (line 8) +* '-m32' option, TILE-Gx: TILE-Gx Options. (line 8) +* '-m32bit-doubles': RX-Opts. (line 9) +* '-m32c' option, M32C: M32C-Opts. (line 9) +* '-m32r' option, M32R: M32R-Opts. (line 21) +* '-m32rx' option, M32R2: M32R-Opts. (line 17) +* '-m32rx' option, M32RX: M32R-Opts. (line 9) +* '-m4byte-align' command line option, V850: V850 Options. (line 90) +* '-m64' option, s390: s390 Options. (line 8) +* '-m64' option, TILE-Gx: TILE-Gx Options. (line 8) +* '-m64bit-doubles': RX-Opts. (line 15) +* '-m68000' and related options: M68K-Opts. (line 99) +* '-m68hc11': M68HC11-Opts. (line 9) +* '-m68hc12': M68HC11-Opts. (line 14) +* '-m68hcs12': M68HC11-Opts. (line 21) +* '-m8byte-align' command line option, V850: V850 Options. (line 86) +* '-mabi=' command line option, AArch64: AArch64 Options. (line 14) +* '-madd-bnd-prefix' option, i386: i386-Options. (line 124) +* '-madd-bnd-prefix' option, x86-64: i386-Options. (line 124) * -mall: PDP-11-Options. (line 26) -* -mall-enabled command line option, LM32: LM32 Options. (line 30) +* '-mall-enabled' command line option, LM32: LM32 Options. (line 30) * -mall-extensions: PDP-11-Options. (line 26) -* -mall-opcodes command line option, AVR: AVR Options. (line 97) -* -mapcs-26 command line option, ARM: ARM Options. (line 128) -* -mapcs-32 command line option, ARM: ARM Options. (line 128) -* -mapcs-float command line option, ARM: ARM Options. (line 142) -* -mapcs-reentrant command line option, ARM: ARM Options. (line 147) -* -marc[5|6|7|8] command line option, ARC: ARC Options. (line 6) -* -march= command line option, ARM: ARM Options. (line 65) -* -march= command line option, M680x0: M68K-Opts. (line 8) -* -march= command line option, TIC6X: TIC6X Options. (line 6) -* -march= option, i386: i386-Options. (line 31) -* -march= option, s390: s390 Options. (line 25) -* -march= option, x86-64: i386-Options. (line 31) -* -matpcs command line option, ARM: ARM Options. (line 134) -* -mavxscalar= option, i386: i386-Options. (line 81) -* -mavxscalar= option, x86-64: i386-Options. (line 81) -* -mbarrel-shift-enabled command line option, LM32: LM32 Options. +* '-mall-opcodes' command line option, AVR: AVR Options. (line 97) +* '-mapcs-26' command line option, ARM: ARM Options. (line 129) +* '-mapcs-32' command line option, ARM: ARM Options. (line 129) +* '-mapcs-float' command line option, ARM: ARM Options. (line 143) +* '-mapcs-reentrant' command line option, ARM: ARM Options. (line 148) +* '-march=' command line option, ARM: ARM Options. (line 65) +* '-march=' command line option, M680x0: M68K-Opts. (line 8) +* '-march=' command line option, TIC6X: TIC6X Options. (line 6) +* '-march=' option, i386: i386-Options. (line 31) +* '-march=' option, s390: s390 Options. (line 25) +* '-march=' option, x86-64: i386-Options. (line 31) +* '-marc[5|6|7|8]' command line option, ARC: ARC Options. (line 6) +* '-matpcs' command line option, ARM: ARM Options. (line 135) +* '-mavxscalar=' option, i386: i386-Options. (line 82) +* '-mavxscalar=' option, x86-64: i386-Options. (line 82) +* '-mbarrel-shift-enabled' command line option, LM32: LM32 Options. (line 12) -* -mbig-endian: RX-Opts. (line 20) -* -mbreak-enabled command line option, LM32: LM32 Options. (line 27) +* '-mbig-endian': RX-Opts. (line 20) +* '-mbreak-enabled' command line option, LM32: LM32 Options. (line 27) * -mcis: PDP-11-Options. (line 32) -* -mconstant-gp command line option, IA-64: IA-64 Options. (line 6) -* -mCPU command line option, Alpha: Alpha Options. (line 6) -* -mcpu option, cpu: TIC54X-Opts. (line 15) -* -mcpu= command line option, ARM: ARM Options. (line 6) -* -mcpu= command line option, Blackfin: Blackfin Options. (line 6) -* -mcpu= command line option, M680x0: M68K-Opts. (line 14) +* '-mconstant-gp' command line option, IA-64: IA-64 Options. (line 6) +* '-mCPU' command line option, Alpha: Alpha Options. (line 6) +* '-mcpu' option, cpu: TIC54X-Opts. (line 15) +* '-mcpu=': RX-Opts. (line 75) +* '-mcpu=' command line option, ARM: ARM Options. (line 6) +* '-mcpu=' command line option, Blackfin: Blackfin Options. (line 6) +* '-mcpu=' command line option, M680x0: M68K-Opts. (line 14) * -mcsm: PDP-11-Options. (line 43) -* -mdcache-enabled command line option, LM32: LM32 Options. (line 24) -* -mdebug command line option, Alpha: Alpha Options. (line 25) -* -mdivide-enabled command line option, LM32: LM32 Options. (line 9) -* -mdsbt command line option, TIC6X: TIC6X Options. (line 13) -* -me option, stderr redirect: TIC54X-Opts. (line 20) +* '-mdcache-enabled' command line option, LM32: LM32 Options. (line 24) +* '-mdebug' command line option, Alpha: Alpha Options. (line 25) +* '-mdivide-enabled' command line option, LM32: LM32 Options. (line 9) +* '-mdsbt' command line option, TIC6X: TIC6X Options. (line 13) +* '-me' option, stderr redirect: TIC54X-Opts. (line 20) * -meis: PDP-11-Options. (line 46) -* -mepiphany command line option, Epiphany: Epiphany Options. (line 9) -* -mepiphany16 command line option, Epiphany: Epiphany Options. +* '-mepiphany' command line option, Epiphany: Epiphany Options. + (line 9) +* '-mepiphany16' command line option, Epiphany: Epiphany Options. (line 13) -* -merrors-to-file option, stderr redirect: TIC54X-Opts. (line 20) -* -mesa option, s390: s390 Options. (line 17) -* -mf option, far-mode: TIC54X-Opts. (line 8) +* '-merrors-to-file' option, stderr redirect: TIC54X-Opts. (line 20) +* '-mesa' option, s390: s390 Options. (line 17) +* '-mevexlig=' option, i386: i386-Options. (line 90) +* '-mevexlig=' option, x86-64: i386-Options. (line 90) +* '-mevexwig=' option, i386: i386-Options. (line 100) +* '-mevexwig=' option, x86-64: i386-Options. (line 100) +* '-mf' option, far-mode: TIC54X-Opts. (line 8) * -mf11: PDP-11-Options. (line 122) -* -mfar-mode option, far-mode: TIC54X-Opts. (line 8) -* -mfdpic command line option, Blackfin: Blackfin Options. (line 19) +* '-mfar-mode' option, far-mode: TIC54X-Opts. (line 8) +* '-mfdpic' command line option, Blackfin: Blackfin Options. (line 19) * -mfis: PDP-11-Options. (line 51) -* -mfloat-abi= command line option, ARM: ARM Options. (line 151) +* '-mfloat-abi=' command line option, ARM: ARM Options. (line 152) * -mfp-11: PDP-11-Options. (line 56) * -mfpp: PDP-11-Options. (line 56) * -mfpu: PDP-11-Options. (line 56) -* -mfpu= command line option, ARM: ARM Options. (line 81) -* -mgcc-abi: RX-Opts. (line 63) -* -mgcc-abi command line option, V850: V850 Options. (line 79) -* -micache-enabled command line option, LM32: LM32 Options. (line 21) -* -mimplicit-it command line option, ARM: ARM Options. (line 112) -* -mint-register: RX-Opts. (line 57) -* -mip2022 option, IP2K: IP2K-Opts. (line 14) -* -mip2022ext option, IP2022: IP2K-Opts. (line 9) +* '-mfpu=' command line option, ARM: ARM Options. (line 81) +* '-mgcc-abi': RX-Opts. (line 63) +* '-mgcc-abi' command line option, V850: V850 Options. (line 79) +* '-micache-enabled' command line option, LM32: LM32 Options. (line 21) +* '-mimplicit-it' command line option, ARM: ARM Options. (line 113) +* '-mint-register': RX-Opts. (line 57) +* '-mip2022' option, IP2K: IP2K-Opts. (line 14) +* '-mip2022ext' option, IP2022: IP2K-Opts. (line 9) * -mj11: PDP-11-Options. (line 126) * -mka11: PDP-11-Options. (line 92) * -mkb11: PDP-11-Options. (line 95) @@ -22755,30 +22536,34 @@ AS Index * -mkd11q: PDP-11-Options. (line 110) * -mkd11z: PDP-11-Options. (line 118) * -mkev11: PDP-11-Options. (line 51) +* -mkev11 <1>: PDP-11-Options. (line 51) * -mlimited-eis: PDP-11-Options. (line 64) -* -mlittle-endian: RX-Opts. (line 26) -* -mlong <1>: XGATE-Opts. (line 13) -* -mlong: M68HC11-Opts. (line 45) -* -mlong-double <1>: XGATE-Opts. (line 21) -* -mlong-double: M68HC11-Opts. (line 53) -* -mm9s12x: M68HC11-Opts. (line 27) -* -mm9s12xg: M68HC11-Opts. (line 32) -* -mmcu= command line option, AVR: AVR Options. (line 6) +* '-mlittle-endian': RX-Opts. (line 26) +* '-mlong': M68HC11-Opts. (line 45) +* '-mlong' <1>: XGATE-Opts. (line 13) +* '-mlong-double': M68HC11-Opts. (line 53) +* '-mlong-double' <1>: XGATE-Opts. (line 21) +* '-mm9s12x': M68HC11-Opts. (line 27) +* '-mm9s12xg': M68HC11-Opts. (line 32) +* '-mmcu=' command line option, AVR: AVR Options. (line 6) * -mmfpt: PDP-11-Options. (line 70) * -mmicrocode: PDP-11-Options. (line 83) -* -mmnemonic= option, i386: i386-Options. (line 89) -* -mmnemonic= option, x86-64: i386-Options. (line 89) -* -mmultiply-enabled command line option, LM32: LM32 Options. (line 6) +* '-mmnemonic=' option, i386: i386-Options. (line 107) +* '-mmnemonic=' option, x86-64: i386-Options. (line 107) +* '-mmultiply-enabled' command line option, LM32: LM32 Options. + (line 6) * -mmutiproc: PDP-11-Options. (line 73) * -mmxps: PDP-11-Options. (line 77) -* -mnaked-reg option, i386: i386-Options. (line 101) -* -mnaked-reg option, x86-64: i386-Options. (line 101) +* '-mnaked-reg' option, i386: i386-Options. (line 119) +* '-mnaked-reg' option, x86-64: i386-Options. (line 119) +* '-mnan=' command line option, MIPS: MIPS Options. (line 296) * -mno-cis: PDP-11-Options. (line 32) * -mno-csm: PDP-11-Options. (line 43) -* -mno-dsbt command line option, TIC6X: TIC6X Options. (line 13) +* '-mno-dsbt' command line option, TIC6X: TIC6X Options. (line 13) * -mno-eis: PDP-11-Options. (line 46) * -mno-extensions: PDP-11-Options. (line 29) -* -mno-fdpic command line option, Blackfin: Blackfin Options. (line 22) +* '-mno-fdpic' command line option, Blackfin: Blackfin Options. + (line 22) * -mno-fis: PDP-11-Options. (line 51) * -mno-fp-11: PDP-11-Options. (line 56) * -mno-fpp: PDP-11-Options. (line 56) @@ -22790,262 +22575,285 @@ AS Index * -mno-mutiproc: PDP-11-Options. (line 73) * -mno-mxps: PDP-11-Options. (line 77) * -mno-pic: PDP-11-Options. (line 11) -* -mno-pic command line option, TIC6X: TIC6X Options. (line 36) -* -mno-regnames option, s390: s390 Options. (line 35) -* -mno-skip-bug command line option, AVR: AVR Options. (line 100) +* '-mno-pic' command line option, TIC6X: TIC6X Options. (line 36) +* '-mno-regnames' option, s390: s390 Options. (line 35) +* '-mno-skip-bug' command line option, AVR: AVR Options. (line 100) * -mno-spl: PDP-11-Options. (line 80) -* -mno-sym32: MIPS Opts. (line 222) -* -mno-wrap command line option, AVR: AVR Options. (line 103) -* -mnopic command line option, Blackfin: Blackfin Options. (line 22) +* -mno-sym32: MIPS Options. (line 238) +* '-mno-wrap' command line option, AVR: AVR Options. (line 103) +* '-mnopic' command line option, Blackfin: Blackfin Options. (line 22) * -mpic: PDP-11-Options. (line 11) -* -mpic command line option, TIC6X: TIC6X Options. (line 36) -* -mpid: RX-Opts. (line 50) -* -mpid= command line option, TIC6X: TIC6X Options. (line 23) -* -mregnames option, s390: s390 Options. (line 32) -* -mrelax command line option, V850: V850 Options. (line 72) -* -mrh850-abi command line option, V850: V850 Options. (line 82) -* -mrx-abi: RX-Opts. (line 69) -* -mshort <1>: XGATE-Opts. (line 8) -* -mshort: M68HC11-Opts. (line 40) -* -mshort-double <1>: XGATE-Opts. (line 17) -* -mshort-double: M68HC11-Opts. (line 49) -* -msign-extend-enabled command line option, LM32: LM32 Options. +* '-mpic' command line option, TIC6X: TIC6X Options. (line 36) +* '-mpid': RX-Opts. (line 50) +* '-mpid=' command line option, TIC6X: TIC6X Options. (line 23) +* '-mregnames' option, s390: s390 Options. (line 32) +* '-mrelax' command line option, V850: V850 Options. (line 72) +* '-mrh850-abi' command line option, V850: V850 Options. (line 82) +* '-mrx-abi': RX-Opts. (line 69) +* '-mshort': M68HC11-Opts. (line 40) +* '-mshort' <1>: XGATE-Opts. (line 8) +* '-mshort-double': M68HC11-Opts. (line 49) +* '-mshort-double' <1>: XGATE-Opts. (line 17) +* '-msign-extend-enabled' command line option, LM32: LM32 Options. (line 15) -* -msmall-data-limit: RX-Opts. (line 42) +* '-msmall-data-limit': RX-Opts. (line 42) * -mspl: PDP-11-Options. (line 80) -* -msse-check= option, i386: i386-Options. (line 71) -* -msse-check= option, x86-64: i386-Options. (line 71) -* -msse2avx option, i386: i386-Options. (line 67) -* -msse2avx option, x86-64: i386-Options. (line 67) -* -msym32: MIPS Opts. (line 222) -* -msyntax= option, i386: i386-Options. (line 95) -* -msyntax= option, x86-64: i386-Options. (line 95) +* '-msse-check=' option, i386: i386-Options. (line 72) +* '-msse-check=' option, x86-64: i386-Options. (line 72) +* '-msse2avx' option, i386: i386-Options. (line 68) +* '-msse2avx' option, x86-64: i386-Options. (line 68) +* -msym32: MIPS Options. (line 238) +* '-msyntax=' option, i386: i386-Options. (line 113) +* '-msyntax=' option, x86-64: i386-Options. (line 113) * -mt11: PDP-11-Options. (line 130) -* -mthumb command line option, ARM: ARM Options. (line 103) -* -mthumb-interwork command line option, ARM: ARM Options. (line 108) -* -mtune= option, i386: i386-Options. (line 59) -* -mtune= option, x86-64: i386-Options. (line 59) -* -muse-conventional-section-names: RX-Opts. (line 33) -* -muse-renesas-section-names: RX-Opts. (line 37) -* -muser-enabled command line option, LM32: LM32 Options. (line 18) -* -mv850 command line option, V850: V850 Options. (line 23) -* -mv850any command line option, V850: V850 Options. (line 41) -* -mv850e command line option, V850: V850 Options. (line 29) -* -mv850e1 command line option, V850: V850 Options. (line 35) -* -mv850e2 command line option, V850: V850 Options. (line 51) -* -mv850e2v3 command line option, V850: V850 Options. (line 57) -* -mv850e2v4 command line option, V850: V850 Options. (line 63) -* -mv850e3v5 command line option, V850: V850 Options. (line 66) -* -mvxworks-pic option, MIPS: MIPS Opts. (line 26) -* -mwarn-areg-zero option, s390: s390 Options. (line 38) -* -mwarn-deprecated command line option, ARM: ARM Options. (line 177) -* -mzarch option, s390: s390 Options. (line 17) -* -N command line option, CRIS: CRIS-Opts. (line 58) -* -nIp option, M32RX: M32R-Opts. (line 101) -* -no-bitinst, M32R2: M32R-Opts. (line 54) -* -no-ignore-parallel-conflicts option, M32RX: M32R-Opts. (line 93) -* -no-mdebug command line option, Alpha: Alpha Options. (line 25) -* -no-parallel option, M32RX: M32R-Opts. (line 51) -* -no-relax option, i960: Options-i960. (line 66) -* -no-warn-explicit-parallel-conflicts option, M32RX: M32R-Opts. +* '-mthumb' command line option, ARM: ARM Options. (line 104) +* '-mthumb-interwork' command line option, ARM: ARM Options. (line 109) +* '-mtune=' option, i386: i386-Options. (line 60) +* '-mtune=' option, x86-64: i386-Options. (line 60) +* '-muse-conventional-section-names': RX-Opts. (line 33) +* '-muse-renesas-section-names': RX-Opts. (line 37) +* '-muser-enabled' command line option, LM32: LM32 Options. (line 18) +* '-mv850' command line option, V850: V850 Options. (line 23) +* '-mv850any' command line option, V850: V850 Options. (line 41) +* '-mv850e' command line option, V850: V850 Options. (line 29) +* '-mv850e1' command line option, V850: V850 Options. (line 35) +* '-mv850e2' command line option, V850: V850 Options. (line 51) +* '-mv850e2v3' command line option, V850: V850 Options. (line 57) +* '-mv850e2v4' command line option, V850: V850 Options. (line 63) +* '-mv850e3v5' command line option, V850: V850 Options. (line 66) +* '-mvxworks-pic' option, MIPS: MIPS Options. (line 26) +* '-mwarn-areg-zero' option, s390: s390 Options. (line 38) +* '-mwarn-deprecated' command line option, ARM: ARM Options. (line 178) +* '-mzarch' option, s390: s390 Options. (line 17) +* '-m[no-]68851' command line option, M680x0: M68K-Opts. (line 21) +* '-m[no-]68881' command line option, M680x0: M68K-Opts. (line 21) +* '-m[no-]div' command line option, M680x0: M68K-Opts. (line 21) +* '-m[no-]emac' command line option, M680x0: M68K-Opts. (line 21) +* '-m[no-]float' command line option, M680x0: M68K-Opts. (line 21) +* '-m[no-]mac' command line option, M680x0: M68K-Opts. (line 21) +* '-m[no-]usp' command line option, M680x0: M68K-Opts. (line 21) +* '-N' command line option, CRIS: CRIS-Opts. (line 59) +* '-nIp' option, M32RX: M32R-Opts. (line 101) +* '-no-bitinst', M32R2: M32R-Opts. (line 54) +* '-no-ignore-parallel-conflicts' option, M32RX: M32R-Opts. (line 93) +* '-no-mdebug' command line option, Alpha: Alpha Options. (line 25) +* '-no-parallel' option, M32RX: M32R-Opts. (line 51) +* '-no-relax' option, i960: Options-i960. (line 66) +* '-no-warn-explicit-parallel-conflicts' option, M32RX: M32R-Opts. (line 79) -* -no-warn-unmatched-high option, M32R: M32R-Opts. (line 111) -* -nocpp ignored (MIPS): MIPS Opts. (line 225) -* -noreplace command line option, Alpha: Alpha Options. (line 40) +* '-no-warn-unmatched-high' option, M32R: M32R-Opts. (line 111) +* '-nocpp' ignored (MIPS): MIPS Options. (line 241) +* '-noreplace' command line option, Alpha: Alpha Options. (line 40) * -o: o. (line 6) -* -O option, M32RX: M32R-Opts. (line 59) -* -parallel option, M32RX: M32R-Opts. (line 46) +* '-O' option, M32RX: M32R-Opts. (line 59) +* '-parallel' option, M32RX: M32R-Opts. (line 46) * -R: R. (line 6) -* -r800 command line option, Z80: Z80 Options. (line 41) -* -relax command line option, Alpha: Alpha Options. (line 32) -* -replace command line option, Alpha: Alpha Options. (line 40) -* -S, ignored on VAX: VAX-Opts. (line 11) -* -t, ignored on VAX: VAX-Opts. (line 36) -* -T, ignored on VAX: VAX-Opts. (line 11) +* '-r800' command line option, Z80: Z80 Options. (line 35) +* '-relax' command line option, Alpha: Alpha Options. (line 32) +* '-replace' command line option, Alpha: Alpha Options. (line 40) +* '-S', ignored on VAX: VAX-Opts. (line 11) +* '-T', ignored on VAX: VAX-Opts. (line 11) +* '-t', ignored on VAX: VAX-Opts. (line 36) * -v: v. (line 6) -* -V, redundant on VAX: VAX-Opts. (line 22) +* '-V', redundant on VAX: VAX-Opts. (line 22) * -version: v. (line 6) * -W: W. (line 11) -* -warn-explicit-parallel-conflicts option, M32RX: M32R-Opts. (line 65) -* -warn-unmatched-high option, M32R: M32R-Opts. (line 105) -* -Wnp option, M32RX: M32R-Opts. (line 83) -* -Wnuh option, M32RX: M32R-Opts. (line 117) -* -Wp option, M32RX: M32R-Opts. (line 75) -* -wsigned_overflow command line option, V850: V850 Options. (line 9) -* -Wuh option, M32RX: M32R-Opts. (line 114) -* -wunsigned_overflow command line option, V850: V850 Options. +* '-warn-explicit-parallel-conflicts' option, M32RX: M32R-Opts. + (line 65) +* '-warn-unmatched-high' option, M32R: M32R-Opts. (line 105) +* '-Wnp' option, M32RX: M32R-Opts. (line 83) +* '-Wnuh' option, M32RX: M32R-Opts. (line 117) +* '-Wp' option, M32RX: M32R-Opts. (line 75) +* '-wsigned_overflow' command line option, V850: V850 Options. + (line 9) +* '-Wuh' option, M32RX: M32R-Opts. (line 114) +* '-wunsigned_overflow' command line option, V850: V850 Options. (line 16) -* -x command line option, MMIX: MMIX-Opts. (line 44) -* -z80 command line option, Z80: Z80 Options. (line 8) -* -z8001 command line option, Z8000: Z8000 Options. (line 6) -* -z8002 command line option, Z8000: Z8000 Options. (line 9) -* . (symbol): Dot. (line 6) -* .2byte directive, ARM: ARM Directives. (line 6) -* .4byte directive, ARM: ARM Directives. (line 6) -* .8byte directive, ARM: ARM Directives. (line 6) -* .align directive, ARM: ARM Directives. (line 11) -* .align directive, TILE-Gx: TILE-Gx Directives. (line 6) -* .align directive, TILEPro: TILEPro Directives. (line 6) -* .allow_suspicious_bundles directive, TILE-Gx: TILE-Gx Directives. +* '-x' command line option, MMIX: MMIX-Opts. (line 44) +* '-z80' command line option, Z80: Z80 Options. (line 8) +* '-z8001' command line option, Z8000: Z8000 Options. (line 6) +* '-z8002' command line option, Z8000: Z8000 Options. (line 9) +* '.' (symbol): Dot. (line 6) +* '.2byte' directive, ARM: ARM Directives. (line 6) +* '.4byte' directive, ARM: ARM Directives. (line 6) +* '.8byte' directive, ARM: ARM Directives. (line 6) +* '.align' directive, ARM: ARM Directives. (line 11) +* '.align' directive, TILE-Gx: TILE-Gx Directives. (line 6) +* '.align' directive, TILEPro: TILEPro Directives. (line 6) +* '.allow_suspicious_bundles' directive, TILE-Gx: TILE-Gx Directives. (line 10) -* .allow_suspicious_bundles directive, TILEPro: TILEPro Directives. +* '.allow_suspicious_bundles' directive, TILEPro: TILEPro Directives. (line 10) -* .arch directive, ARM: ARM Directives. (line 18) -* .arch directive, TIC6X: TIC6X Directives. (line 10) -* .arch_extension directive, ARM: ARM Directives. (line 25) -* .arm directive, ARM: ARM Directives. (line 34) -* .big directive, M32RX: M32R-Directives. (line 88) -* .bss directive, AArch64: AArch64 Directives. (line 6) -* .bss directive, ARM: ARM Directives. (line 42) -* .c6xabi_attribute directive, TIC6X: TIC6X Directives. (line 20) -* .cantunwind directive, ARM: ARM Directives. (line 45) -* .cantunwind directive, TIC6X: TIC6X Directives. (line 13) -* .code directive, ARM: ARM Directives. (line 49) -* .cpu directive, ARM: ARM Directives. (line 53) -* .dn and .qn directives, ARM: ARM Directives. (line 60) -* .eabi_attribute directive, ARM: ARM Directives. (line 83) -* .ehtype directive, TIC6X: TIC6X Directives. (line 31) -* .endp directive, TIC6X: TIC6X Directives. (line 34) -* .even directive, ARM: ARM Directives. (line 111) -* .extend directive, ARM: ARM Directives. (line 114) -* .fnend directive, ARM: ARM Directives. (line 120) -* .fnstart directive, ARM: ARM Directives. (line 129) -* .force_thumb directive, ARM: ARM Directives. (line 132) -* .fpu directive, ARM: ARM Directives. (line 136) -* .global: MIPS insn. (line 12) -* .handlerdata directive, ARM: ARM Directives. (line 140) -* .handlerdata directive, TIC6X: TIC6X Directives. (line 39) -* .insn: MIPS insn. (line 6) -* .insn directive, s390: s390 Directives. (line 11) -* .inst directive, ARM: ARM Directives. (line 149) -* .ldouble directive, ARM: ARM Directives. (line 114) -* .little directive, M32RX: M32R-Directives. (line 82) -* .long directive, s390: s390 Directives. (line 16) -* .ltorg directive, AArch64: AArch64 Directives. (line 9) -* .ltorg directive, ARM: ARM Directives. (line 159) -* .ltorg directive, s390: s390 Directives. (line 88) -* .m32r directive, M32R: M32R-Directives. (line 66) -* .m32r2 directive, M32R2: M32R-Directives. (line 77) -* .m32rx directive, M32RX: M32R-Directives. (line 72) -* .machine directive, s390: s390 Directives. (line 93) -* .machinemode directive, s390: s390 Directives. (line 103) -* .movsp directive, ARM: ARM Directives. (line 173) -* .no_pointers directive, XStormy16: XStormy16 Directives. +* '.arch' directive, ARM: ARM Directives. (line 18) +* '.arch' directive, TIC6X: TIC6X Directives. (line 10) +* '.arch_extension' directive, ARM: ARM Directives. (line 25) +* '.arm' directive, ARM: ARM Directives. (line 33) +* '.big' directive, M32RX: M32R-Directives. (line 88) +* '.bss' directive, AArch64: AArch64 Directives. (line 6) +* '.bss' directive, ARM: ARM Directives. (line 41) +* '.c6xabi_attribute' directive, TIC6X: TIC6X Directives. (line 20) +* '.cantunwind' directive, ARM: ARM Directives. (line 44) +* '.cantunwind' directive, TIC6X: TIC6X Directives. (line 13) +* '.code' directive, ARM: ARM Directives. (line 48) +* '.cpu' directive, ARM: ARM Directives. (line 52) +* '.dn' and '.qn' directives, ARM: ARM Directives. (line 59) +* '.eabi_attribute' directive, ARM: ARM Directives. (line 83) +* '.ehtype' directive, TIC6X: TIC6X Directives. (line 31) +* '.endp' directive, TIC6X: TIC6X Directives. (line 34) +* '.even' directive, ARM: ARM Directives. (line 111) +* '.extend' directive, ARM: ARM Directives. (line 114) +* '.fnend' directive, ARM: ARM Directives. (line 120) +* '.fnstart' directive, ARM: ARM Directives. (line 128) +* '.force_thumb' directive, ARM: ARM Directives. (line 131) +* '.fpu' directive, ARM: ARM Directives. (line 135) +* '.global': MIPS insn. (line 12) +* '.handlerdata' directive, ARM: ARM Directives. (line 139) +* '.handlerdata' directive, TIC6X: TIC6X Directives. (line 39) +* '.insn': MIPS insn. (line 6) +* '.insn' directive, s390: s390 Directives. (line 11) +* '.inst' directive, ARM: ARM Directives. (line 148) +* '.ldouble' directive, ARM: ARM Directives. (line 114) +* '.little' directive, M32RX: M32R-Directives. (line 82) +* '.long' directive, s390: s390 Directives. (line 16) +* '.ltorg' directive, AArch64: AArch64 Directives. (line 9) +* '.ltorg' directive, ARM: ARM Directives. (line 158) +* '.ltorg' directive, s390: s390 Directives. (line 79) +* '.m32r' directive, M32R: M32R-Directives. (line 66) +* '.m32r2' directive, M32R2: M32R-Directives. (line 77) +* '.m32rx' directive, M32RX: M32R-Directives. (line 72) +* '.machine' directive, s390: s390 Directives. (line 84) +* '.machinemode' directive, s390: s390 Directives. (line 93) +* '.movsp' directive, ARM: ARM Directives. (line 172) +* '.nan' directive, MIPS: MIPS NaN Encodings. (line 6) +* '.nocmp' directive, TIC6X: TIC6X Directives. (line 47) +* '.no_pointers' directive, XStormy16: XStormy16 Directives. (line 14) -* .nocmp directive, TIC6X: TIC6X Directives. (line 47) * .o: Object. (line 6) -* .object_arch directive, ARM: ARM Directives. (line 178) -* .packed directive, ARM: ARM Directives. (line 184) -* .pad directive, ARM: ARM Directives. (line 37) -* .param on HPPA: HPPA Directives. (line 19) -* .personality directive, ARM: ARM Directives. (line 194) -* .personality directive, TIC6X: TIC6X Directives. (line 55) -* .personalityindex directive, ARM: ARM Directives. (line 197) -* .personalityindex directive, TIC6X: TIC6X Directives. (line 51) -* .pool directive, AArch64: AArch64 Directives. (line 23) -* .pool directive, ARM: ARM Directives. (line 201) -* .quad directive, s390: s390 Directives. (line 16) -* .req directive, AArch64: AArch64 Directives. (line 26) -* .req directive, ARM: ARM Directives. (line 204) -* .require_canonical_reg_names directive, TILE-Gx: TILE-Gx Directives. +* '.object_arch' directive, ARM: ARM Directives. (line 177) +* '.packed' directive, ARM: ARM Directives. (line 183) +* '.pad' directive, ARM: ARM Directives. (line 36) +* '.pad' directive, ARM <1>: ARM Directives. (line 188) +* '.param' on HPPA: HPPA Directives. (line 19) +* '.personality' directive, ARM: ARM Directives. (line 193) +* '.personality' directive, TIC6X: TIC6X Directives. (line 55) +* '.personalityindex' directive, ARM: ARM Directives. (line 196) +* '.personalityindex' directive, TIC6X: TIC6X Directives. (line 51) +* '.pool' directive, AArch64: AArch64 Directives. (line 23) +* '.pool' directive, ARM: ARM Directives. (line 200) +* '.quad' directive, s390: s390 Directives. (line 16) +* '.req' directive, AArch64: AArch64 Directives. (line 26) +* '.req' directive, ARM: ARM Directives. (line 203) +* '.require_canonical_reg_names' directive, TILE-Gx: TILE-Gx Directives. (line 19) -* .require_canonical_reg_names directive, TILEPro: TILEPro Directives. +* '.require_canonical_reg_names' directive, TILEPro: TILEPro Directives. (line 19) -* .save directive, ARM: ARM Directives. (line 209) -* .scomm directive, TIC6X: TIC6X Directives. (line 58) -* .secrel32 directive, ARM: ARM Directives. (line 247) -* .set arch=CPU: MIPS ISA. (line 18) -* .set autoextend: MIPS autoextend. (line 6) -* .set doublefloat: MIPS floating-point. (line 12) -* .set dsp: MIPS ASE instruction generation overrides. +* '.save' directive, ARM: ARM Directives. (line 208) +* '.scomm' directive, TIC6X: TIC6X Directives. (line 58) +* '.secrel32' directive, ARM: ARM Directives. (line 246) +* '.set arch=CPU': MIPS ISA. (line 18) +* '.set at': MIPS Macros. (line 41) +* '.set at=REG': MIPS Macros. (line 35) +* '.set autoextend': MIPS autoextend. (line 6) +* '.set doublefloat': MIPS Floating-Point. (line 12) +* '.set dsp': MIPS ASE Instruction Generation Overrides. (line 21) -* .set dspr2: MIPS ASE instruction generation overrides. +* '.set dspr2': MIPS ASE Instruction Generation Overrides. (line 26) -* .set hardfloat: MIPS floating-point. (line 6) -* .set mcu: MIPS ASE instruction generation overrides. - (line 37) -* .set mdmx: MIPS ASE instruction generation overrides. +* '.set hardfloat': MIPS Floating-Point. (line 6) +* '.set insn32': MIPS assembly options. + (line 6) +* '.set macro': MIPS Macros. (line 30) +* '.set mcu': MIPS ASE Instruction Generation Overrides. + (line 36) +* '.set mdmx': MIPS ASE Instruction Generation Overrides. (line 16) -* .set mips3d: MIPS ASE instruction generation overrides. +* '.set mips3d': MIPS ASE Instruction Generation Overrides. (line 6) -* .set mipsN: MIPS ISA. (line 6) -* .set mt: MIPS ASE instruction generation overrides. - (line 32) -* .set noautoextend: MIPS autoextend. (line 6) -* .set nodsp: MIPS ASE instruction generation overrides. +* '.set mipsN': MIPS ISA. (line 6) +* '.set mt': MIPS ASE Instruction Generation Overrides. + (line 31) +* '.set noat': MIPS Macros. (line 41) +* '.set noautoextend': MIPS autoextend. (line 6) +* '.set nodsp': MIPS ASE Instruction Generation Overrides. (line 21) -* .set nodspr2: MIPS ASE instruction generation overrides. +* '.set nodspr2': MIPS ASE Instruction Generation Overrides. (line 26) -* .set nomcu: MIPS ASE instruction generation overrides. - (line 37) -* .set nomdmx: MIPS ASE instruction generation overrides. +* '.set noinsn32': MIPS assembly options. + (line 6) +* '.set nomacro': MIPS Macros. (line 30) +* '.set nomcu': MIPS ASE Instruction Generation Overrides. + (line 36) +* '.set nomdmx': MIPS ASE Instruction Generation Overrides. (line 16) -* .set nomips3d: MIPS ASE instruction generation overrides. +* '.set nomips3d': MIPS ASE Instruction Generation Overrides. (line 6) -* .set nomt: MIPS ASE instruction generation overrides. - (line 32) -* .set nosmartmips: MIPS ASE instruction generation overrides. +* '.set nomt': MIPS ASE Instruction Generation Overrides. + (line 31) +* '.set nosmartmips': MIPS ASE Instruction Generation Overrides. (line 11) -* .set nosym32: MIPS symbol sizes. (line 6) -* .set pop: MIPS option stack. (line 6) -* .set push: MIPS option stack. (line 6) -* .set singlefloat: MIPS floating-point. (line 12) -* .set smartmips: MIPS ASE instruction generation overrides. +* '.set nosym32': MIPS Symbol Sizes. (line 6) +* '.set novirt': MIPS ASE Instruction Generation Overrides. + (line 41) +* '.set pop': MIPS Option Stack. (line 6) +* '.set push': MIPS Option Stack. (line 6) +* '.set singlefloat': MIPS Floating-Point. (line 12) +* '.set smartmips': MIPS ASE Instruction Generation Overrides. (line 11) -* .set softfloat: MIPS floating-point. (line 6) -* .set sym32: MIPS symbol sizes. (line 6) -* .setfp directive, ARM: ARM Directives. (line 233) -* .short directive, s390: s390 Directives. (line 16) -* .syntax directive, ARM: ARM Directives. (line 252) -* .thumb directive, ARM: ARM Directives. (line 256) -* .thumb_func directive, ARM: ARM Directives. (line 259) -* .thumb_set directive, ARM: ARM Directives. (line 270) -* .tlsdescseq directive, ARM: ARM Directives. (line 277) -* .unreq directive, AArch64: AArch64 Directives. (line 31) -* .unreq directive, ARM: ARM Directives. (line 282) -* .unwind_raw directive, ARM: ARM Directives. (line 293) -* .v850 directive, V850: V850 Directives. (line 14) -* .v850e directive, V850: V850 Directives. (line 20) -* .v850e1 directive, V850: V850 Directives. (line 26) -* .v850e2 directive, V850: V850 Directives. (line 32) -* .v850e2v3 directive, V850: V850 Directives. (line 38) -* .v850e2v4 directive, V850: V850 Directives. (line 44) -* .v850e3v5 directive, V850: V850 Directives. (line 50) -* .vsave directive, ARM: ARM Directives. (line 300) +* '.set softfloat': MIPS Floating-Point. (line 6) +* '.set sym32': MIPS Symbol Sizes. (line 6) +* '.set virt': MIPS ASE Instruction Generation Overrides. + (line 41) +* '.setfp' directive, ARM: ARM Directives. (line 232) +* '.short' directive, s390: s390 Directives. (line 16) +* '.syntax' directive, ARM: ARM Directives. (line 251) +* '.thumb' directive, ARM: ARM Directives. (line 255) +* '.thumb_func' directive, ARM: ARM Directives. (line 258) +* '.thumb_set' directive, ARM: ARM Directives. (line 269) +* '.tlsdescseq' directive, ARM: ARM Directives. (line 276) +* '.unreq' directive, AArch64: AArch64 Directives. (line 31) +* '.unreq' directive, ARM: ARM Directives. (line 281) +* '.unwind_raw' directive, ARM: ARM Directives. (line 292) +* '.v850' directive, V850: V850 Directives. (line 14) +* '.v850e' directive, V850: V850 Directives. (line 20) +* '.v850e1' directive, V850: V850 Directives. (line 26) +* '.v850e2' directive, V850: V850 Directives. (line 32) +* '.v850e2v3' directive, V850: V850 Directives. (line 38) +* '.v850e2v4' directive, V850: V850 Directives. (line 44) +* '.v850e3v5' directive, V850: V850 Directives. (line 50) +* '.vsave' directive, ARM: ARM Directives. (line 299) * .z8001: Z8000 Directives. (line 11) * .z8002: Z8000 Directives. (line 15) * 16-bit code, i386: i386-16bit. (line 6) -* 16bit_pointers directive, XStormy16: XStormy16 Directives. +* '16bit_pointers' directive, XStormy16: XStormy16 Directives. (line 6) -* 16byte directive, Nios II: Nios II Directives. (line 28) -* 2byte directive, ARC: ARC Directives. (line 9) -* 2byte directive, Nios II: Nios II Directives. (line 19) -* 32bit_pointers directive, XStormy16: XStormy16 Directives. +* '16byte' directive, Nios II: Nios II Directives. (line 28) +* '2byte' directive, ARC: ARC Directives. (line 9) +* '2byte' directive, Nios II: Nios II Directives. (line 19) +* '32bit_pointers' directive, XStormy16: XStormy16 Directives. (line 10) -* 3byte directive, ARC: ARC Directives. (line 12) +* '3byte' directive, ARC: ARC Directives. (line 12) * 3DNow!, i386: i386-SIMD. (line 6) * 3DNow!, x86-64: i386-SIMD. (line 6) * 430 support: MSP430-Dependent. (line 6) -* 4byte directive, ARC: ARC Directives. (line 15) -* 4byte directive, Nios II: Nios II Directives. (line 22) -* 8byte directive, Nios II: Nios II Directives. (line 25) -* : (label): Statements. (line 31) -* @hi pseudo-op, XStormy16: XStormy16 Opcodes. (line 21) -* @lo pseudo-op, XStormy16: XStormy16 Opcodes. (line 10) +* '4byte' directive, ARC: ARC Directives. (line 15) +* '4byte' directive, Nios II: Nios II Directives. (line 22) +* '8byte' directive, Nios II: Nios II Directives. (line 25) +* ':' (label): Statements. (line 31) +* '@hi' pseudo-op, XStormy16: XStormy16 Opcodes. (line 21) +* '@lo' pseudo-op, XStormy16: XStormy16 Opcodes. (line 10) * @word modifier, D10V: D10V-Word. (line 6) -* \" (doublequote character): Strings. (line 43) -* \\ (\ character): Strings. (line 40) -* \b (backspace character): Strings. (line 15) -* \DDD (octal character code): Strings. (line 30) -* \f (formfeed character): Strings. (line 18) -* \n (newline character): Strings. (line 21) -* \r (carriage return character): Strings. (line 24) -* \t (tab): Strings. (line 27) -* \XD... (hex character code): Strings. (line 36) +* '\"' (doublequote character): Strings. (line 43) +* '\b' (backspace character): Strings. (line 15) +* '\DDD' (octal character code): Strings. (line 30) +* '\f' (formfeed character): Strings. (line 18) +* '\n' (newline character): Strings. (line 21) +* '\r' (carriage return character): Strings. (line 24) +* '\t' (tab): Strings. (line 27) +* '\XD...' (hex character code): Strings. (line 36) +* '\\' ('\' character): Strings. (line 40) * _ opcode prefix: Xtensa Opcodes. (line 9) * a.out: Object. (line 6) -* a.out symbol attributes: a.out Symbols. (line 6) -* A_DIR environment variable, TIC54X: TIC54X-Env. (line 6) +* 'a.out' symbol attributes: a.out Symbols. (line 6) * AArch64 floating point (IEEE): AArch64 Floating Point. (line 6) * AArch64 immediate character: AArch64-Chars. (line 13) @@ -23057,40 +22865,40 @@ AS Index * AArch64 register names: AArch64-Regs. (line 6) * AArch64 relocations: AArch64-Relocations. (line 6) * AArch64 support: AArch64-Dependent. (line 6) -* ABI options, SH64: SH64 Options. (line 29) -* ABORT directive: ABORT (COFF). (line 6) -* abort directive: Abort. (line 6) +* ABI options, SH64: SH64 Options. (line 25) +* 'abort' directive: Abort. (line 6) +* 'ABORT' directive: ABORT (COFF). (line 6) * absolute section: Ld Sections. (line 29) -* absolute-literals directive: Absolute Literals Directive. +* 'absolute-literals' directive: Absolute Literals Directive. (line 6) -* ADDI instructions, relaxation: Xtensa Immediate Relaxation. +* 'ADDI' instructions, relaxation: Xtensa Immediate Relaxation. (line 43) -* addition, permitted arguments: Infix Ops. (line 44) +* addition, permitted arguments: Infix Ops. (line 45) * addresses: Expressions. (line 6) -* addresses, format of: Secs Background. (line 68) +* addresses, format of: Secs Background. (line 65) * addressing modes, D10V: D10V-Addressing. (line 6) * addressing modes, D30V: D30V-Addressing. (line 6) * addressing modes, H8/300: H8/300-Addressing. (line 6) * addressing modes, M680x0: M68K-Syntax. (line 21) -* addressing modes, M68HC11: M68HC11-Syntax. (line 30) +* addressing modes, M68HC11: M68HC11-Syntax. (line 29) * addressing modes, SH: SH-Addressing. (line 6) * addressing modes, SH64: SH64-Addressing. (line 6) -* addressing modes, XGATE: XGATE-Syntax. (line 29) +* addressing modes, XGATE: XGATE-Syntax. (line 28) * addressing modes, Z8000: Z8000-Addressing. (line 6) -* ADR reg,<label> pseudo op, ARM: ARM Opcodes. (line 25) -* ADRL reg,<label> pseudo op, ARM: ARM Opcodes. (line 35) +* 'ADR reg,<label>' pseudo op, ARM: ARM Opcodes. (line 25) +* 'ADRL reg,<label>' pseudo op, ARM: ARM Opcodes. (line 35) * ADRP, ADD, LDR/STR group relocations, AArch64: AArch64-Relocations. (line 14) * advancing location counter: Org. (line 6) -* align directive: Align. (line 6) -* align directive, Nios II: Nios II Directives. (line 6) -* align directive, SPARC: Sparc-Directives. (line 9) -* align directive, TIC54X: TIC54X-Directives. (line 6) +* 'align' directive: Align. (line 6) +* 'align' directive, Nios II: Nios II Directives. (line 6) +* 'align' directive, SPARC: Sparc-Directives. (line 9) +* 'align' directive, TIC54X: TIC54X-Directives. (line 6) * aligned instruction bundle: Bundle directives. (line 6) * alignment for NEON instructions: ARM-Neon-Alignment. (line 6) * alignment of branch targets: Xtensa Automatic Alignment. (line 6) -* alignment of LOOP instructions: Xtensa Automatic Alignment. +* alignment of 'LOOP' instructions: Xtensa Automatic Alignment. (line 6) * Alpha floating point (IEEE): Alpha Floating Point. (line 6) @@ -23101,8 +22909,8 @@ AS Index * Alpha registers: Alpha-Regs. (line 6) * Alpha relocations: Alpha-Relocs. (line 6) * Alpha support: Alpha-Dependent. (line 6) -* Alpha Syntax: Alpha Options. (line 61) -* Alpha-only directives: Alpha Directives. (line 10) +* Alpha Syntax: Alpha Options. (line 60) +* Alpha-only directives: Alpha Directives. (line 9) * Altera Nios II support: NiosII-Dependent. (line 6) * altered difference tables: Word. (line 12) * alternate syntax for the 680x0: M68K-Moto-Syntax. (line 6) @@ -23114,12 +22922,13 @@ AS Index * ARC options (none): ARC Options. (line 6) * ARC register names: ARC-Regs. (line 6) * ARC support: ARC-Dependent. (line 6) -* arc5 arc5, ARC: ARC Options. (line 10) -* arc6 arc6, ARC: ARC Options. (line 13) -* arc7 arc7, ARC: ARC Options. (line 21) -* arc8 arc8, ARC: ARC Options. (line 24) +* 'arc5' arc5, ARC: ARC Options. (line 10) +* 'arc6' arc6, ARC: ARC Options. (line 13) +* 'arc7' arc7, ARC: ARC Options. (line 21) +* 'arc8' arc8, ARC: ARC Options. (line 24) * arch directive, i386: i386-Arch. (line 6) -* arch directive, M680x0: M68K-Directives. (line 22) +* 'arch' directive, M680x0: M68K-Directives. (line 22) +* 'arch' directive, MSP 430: MSP430 Directives. (line 18) * arch directive, x86-64: i386-Arch. (line 6) * architecture options, i960: Options-i960. (line 6) * architecture options, IP2022: IP2K-Opts. (line 9) @@ -23129,14 +22938,14 @@ AS Index * architecture options, M32R: M32R-Opts. (line 21) * architecture options, M32R2: M32R-Opts. (line 17) * architecture options, M32RX: M32R-Opts. (line 9) -* architecture options, M680x0: M68K-Opts. (line 98) +* architecture options, M680x0: M68K-Opts. (line 99) * Architecture variant option, CRIS: CRIS-Opts. (line 34) * architectures, Meta: Meta Options. (line 6) * architectures, PowerPC: PowerPC-Opts. (line 6) * architectures, SCORE: SCORE-Opts. (line 6) * architectures, SPARC: Sparc-Opts. (line 6) -* arguments for addition: Infix Ops. (line 44) -* arguments for subtraction: Infix Ops. (line 49) +* arguments for addition: Infix Ops. (line 45) +* arguments for subtraction: Infix Ops. (line 50) * arguments in expressions: Arguments. (line 6) * arithmetic functions: Operators. (line 6) * arithmetic operands: Arguments. (line 6) @@ -23151,13 +22960,13 @@ AS Index * ARM options (none): ARM Options. (line 6) * ARM register names: ARM-Regs. (line 6) * ARM support: ARM-Dependent. (line 6) -* ascii directive: Ascii. (line 6) -* asciz directive: Asciz. (line 6) -* asg directive, TIC54X: TIC54X-Directives. (line 20) +* 'ascii' directive: Ascii. (line 6) +* 'asciz' directive: Asciz. (line 6) +* 'asg' directive, TIC54X: TIC54X-Directives. (line 18) * assembler bugs, reporting: Bug Reporting. (line 6) * assembler crash: Bug Criteria. (line 9) * assembler directive .3byte, RX: RX-Directives. (line 9) -* assembler directive .arch, CRIS: CRIS-Pseudos. (line 45) +* assembler directive .arch, CRIS: CRIS-Pseudos. (line 50) * assembler directive .dword, CRIS: CRIS-Pseudos. (line 12) * assembler directive .far, M68HC11: M68HC11-Directives. (line 20) * assembler directive .fetchalign, RX: RX-Directives. (line 13) @@ -23165,19 +22974,19 @@ AS Index (line 26) * assembler directive .mode, M68HC11: M68HC11-Directives. (line 16) * assembler directive .relax, M68HC11: M68HC11-Directives. (line 10) -* assembler directive .syntax, CRIS: CRIS-Pseudos. (line 17) +* assembler directive .syntax, CRIS: CRIS-Pseudos. (line 18) * assembler directive .xrefb, M68HC11: M68HC11-Directives. (line 31) -* assembler directive BSPEC, MMIX: MMIX-Pseudos. (line 131) -* assembler directive BYTE, MMIX: MMIX-Pseudos. (line 97) -* assembler directive ESPEC, MMIX: MMIX-Pseudos. (line 131) -* assembler directive GREG, MMIX: MMIX-Pseudos. (line 50) -* assembler directive IS, MMIX: MMIX-Pseudos. (line 42) +* assembler directive BSPEC, MMIX: MMIX-Pseudos. (line 137) +* assembler directive BYTE, MMIX: MMIX-Pseudos. (line 101) +* assembler directive ESPEC, MMIX: MMIX-Pseudos. (line 137) +* assembler directive GREG, MMIX: MMIX-Pseudos. (line 53) +* assembler directive IS, MMIX: MMIX-Pseudos. (line 44) * assembler directive LOC, MMIX: MMIX-Pseudos. (line 7) -* assembler directive LOCAL, MMIX: MMIX-Pseudos. (line 28) -* assembler directive OCTA, MMIX: MMIX-Pseudos. (line 108) -* assembler directive PREFIX, MMIX: MMIX-Pseudos. (line 120) -* assembler directive TETRA, MMIX: MMIX-Pseudos. (line 108) -* assembler directive WYDE, MMIX: MMIX-Pseudos. (line 108) +* assembler directive LOCAL, MMIX: MMIX-Pseudos. (line 29) +* assembler directive OCTA, MMIX: MMIX-Pseudos. (line 113) +* assembler directive PREFIX, MMIX: MMIX-Pseudos. (line 125) +* assembler directive TETRA, MMIX: MMIX-Pseudos. (line 113) +* assembler directive WYDE, MMIX: MMIX-Pseudos. (line 113) * assembler directives, CRIS: CRIS-Pseudos. (line 6) * assembler directives, M68HC11: M68HC11-Directives. (line 6) * assembler directives, M68HC12: M68HC11-Directives. (line 6) @@ -23189,12 +22998,13 @@ AS Index * assembler version: v. (line 6) * assembler, and linker: Secs Background. (line 10) * assembly listings, enabling: a. (line 6) -* assigning values to symbols <1>: Equ. (line 6) * assigning values to symbols: Setting Symbols. (line 6) -* atmp directive, i860: Directives-i860. (line 16) +* assigning values to symbols <1>: Equ. (line 6) +* 'at' register, MIPS: MIPS Macros. (line 35) +* 'atmp' directive, i860: Directives-i860. (line 16) +* attributes, symbol: Symbol Attributes. (line 6) * att_syntax pseudo op, i386: i386-Variations. (line 6) * att_syntax pseudo op, x86-64: i386-Variations. (line 6) -* attributes, symbol: Symbol Attributes. (line 6) * auxiliary attributes, COFF symbols: COFF Symbols. (line 19) * auxiliary symbol information, COFF: Dim. (line 6) * AVR line comment character: AVR-Chars. (line 6) @@ -23204,15 +23014,16 @@ AS Index * AVR options (none): AVR Options. (line 6) * AVR register names: AVR-Regs. (line 6) * AVR support: AVR-Dependent. (line 6) -* backslash (\\): Strings. (line 40) -* backspace (\b): Strings. (line 15) -* balign directive: Balign. (line 6) -* balignl directive: Balign. (line 27) -* balignw directive: Balign. (line 27) -* bes directive, TIC54X: TIC54X-Directives. (line 196) -* big endian output, MIPS: Overview. (line 727) -* big endian output, PJ: Overview. (line 630) -* big-endian output, MIPS: MIPS Opts. (line 13) +* 'A_DIR' environment variable, TIC54X: TIC54X-Env. (line 6) +* backslash ('\\'): Strings. (line 40) +* backspace ('\b'): Strings. (line 15) +* 'balign' directive: Balign. (line 6) +* 'balignl' directive: Balign. (line 27) +* 'balignw' directive: Balign. (line 27) +* 'bes' directive, TIC54X: TIC54X-Directives. (line 194) +* big endian output, MIPS: Overview. (line 720) +* big endian output, PJ: Overview. (line 627) +* big-endian output, MIPS: MIPS Options. (line 13) * big-endian output, TIC6X: TIC6X Options. (line 46) * bignums: Bignums. (line 6) * binary constants, TIC54X: TIC54X-Constants. (line 8) @@ -23224,7 +23035,7 @@ AS Index * Blackfin options (none): Blackfin Options. (line 6) * Blackfin support: Blackfin-Dependent. (line 6) * Blackfin syntax: Blackfin Syntax. (line 6) -* block: Z8000 Directives. (line 55) +* block: Z8000 Directives. (line 54) * BMI, i386: i386-BMI. (line 6) * BMI, x86-64: i386-BMI. (line 6) * branch improvement, M680x0: M68K-Branch. (line 6) @@ -23236,12 +23047,12 @@ AS Index * branch statistics table, i960: Options-i960. (line 40) * branch target alignment: Xtensa Automatic Alignment. (line 6) -* break directive, TIC54X: TIC54X-Directives. (line 143) +* 'break' directive, TIC54X: TIC54X-Directives. (line 141) * BSD syntax: PDP-11-Syntax. (line 6) -* bss directive, i960: Directives-i960. (line 6) -* bss directive, TIC54X: TIC54X-Directives. (line 29) -* bss section <1>: bss. (line 6) +* 'bss' directive, i960: Directives-i960. (line 6) +* 'bss' directive, TIC54X: TIC54X-Directives. (line 27) * bss section: Ld Sections. (line 20) +* bss section <1>: bss. (line 6) * bug criteria: Bug Criteria. (line 6) * bug reports: Bug Reporting. (line 6) * bugs in assembler: Reporting Bugs. (line 6) @@ -23249,40 +23060,39 @@ AS Index * builtin math functions, TIC54X: TIC54X-Builtins. (line 6) * builtin subsym functions, TIC54X: TIC54X-Macros. (line 16) * bundle: Bundle directives. (line 6) -* bundle-locked: Bundle directives. (line 35) -* bundle_align_mode directive: Bundle directives. (line 6) -* bundle_lock directive: Bundle directives. (line 28) -* bundle_unlock directive: Bundle directives. (line 28) +* bundle-locked: Bundle directives. (line 36) +* 'bundle_align_mode' directive: Bundle directives. (line 6) +* 'bundle_lock' directive: Bundle directives. (line 28) +* 'bundle_unlock' directive: Bundle directives. (line 28) * bus lock prefixes, i386: i386-Prefixes. (line 36) * bval: Z8000 Directives. (line 30) -* byte directive: Byte. (line 6) -* byte directive, TIC54X: TIC54X-Directives. (line 36) -* C54XDSP_DIR environment variable, TIC54X: TIC54X-Env. (line 6) -* c_mode directive, TIC54X: TIC54X-Directives. (line 51) -* call directive, Nios II: Nios II Relocations. (line 38) -* call instructions, i386: i386-Mnemonics. (line 56) +* 'byte' directive: Byte. (line 6) +* 'byte' directive, TIC54X: TIC54X-Directives. (line 34) +* 'C54XDSP_DIR' environment variable, TIC54X: TIC54X-Env. (line 6) +* 'call' directive, Nios II: Nios II Relocations. (line 38) +* call instructions, i386: i386-Mnemonics. (line 55) * call instructions, relaxation: Xtensa Call Relaxation. (line 6) -* call instructions, x86-64: i386-Mnemonics. (line 56) -* callj, i960 pseudo-opcode: callj-i960. (line 6) -* carriage return (\r): Strings. (line 24) +* call instructions, x86-64: i386-Mnemonics. (line 55) +* 'callj', i960 pseudo-opcode: callj-i960. (line 6) +* carriage return ('\r'): Strings. (line 24) * case sensitivity, Z80: Z80-Case. (line 6) -* cfi_endproc directive: CFI directives. (line 26) -* cfi_sections directive: CFI directives. (line 6) -* cfi_startproc directive: CFI directives. (line 16) -* char directive, TIC54X: TIC54X-Directives. (line 36) +* 'cfi_endproc' directive: CFI directives. (line 26) +* 'cfi_sections' directive: CFI directives. (line 6) +* 'cfi_startproc' directive: CFI directives. (line 16) +* 'char' directive, TIC54X: TIC54X-Directives. (line 34) * character constant, Z80: Z80-Chars. (line 20) * character constants: Characters. (line 6) * character escape codes: Strings. (line 15) * character escapes, Z80: Z80-Chars. (line 18) * character, single: Chars. (line 6) * characters used in symbols: Symbol Intro. (line 6) -* clink directive, TIC54X: TIC54X-Directives. (line 45) -* code16 directive, i386: i386-16bit. (line 6) -* code16gcc directive, i386: i386-16bit. (line 6) -* code32 directive, i386: i386-16bit. (line 6) -* code64 directive, i386: i386-16bit. (line 6) -* code64 directive, x86-64: i386-16bit. (line 6) +* 'clink' directive, TIC54X: TIC54X-Directives. (line 43) +* 'code16' directive, i386: i386-16bit. (line 6) +* 'code16gcc' directive, i386: i386-16bit. (line 6) +* 'code32' directive, i386: i386-16bit. (line 6) +* 'code64' directive, i386: i386-16bit. (line 6) +* 'code64' directive, x86-64: i386-16bit. (line 6) * COFF auxiliary symbol information: Dim. (line 6) * COFF structure debugging: Tag. (line 6) * COFF symbol attributes: COFF Symbols. (line 6) @@ -23292,7 +23102,7 @@ AS Index * COFF symbols, debugging: Def. (line 6) * COFF value attribute: Val. (line 6) * COMDAT: Linkonce. (line 6) -* comm directive: Comm. (line 6) +* 'comm' directive: Comm. (line 6) * command line conventions: Command Line. (line 6) * command line options, V850: V850 Options. (line 9) * command-line options ignored, VAX: VAX-Opts. (line 6) @@ -23300,14 +23110,14 @@ AS Index * comments: Comments. (line 6) * comments, M680x0: M68K-Chars. (line 6) * comments, removed by preprocessor: Preprocessing. (line 11) -* common directive, SPARC: Sparc-Directives. (line 12) +* 'common' directive, SPARC: Sparc-Directives. (line 12) * common sections: Linkonce. (line 6) * common variable storage: bss. (line 6) * compare and jump expansions, i960: Compare-and-branch-i960. (line 13) * compare/branch instructions, i960: Compare-and-branch-i960. (line 6) -* comparison expressions: Infix Ops. (line 55) +* comparison expressions: Infix Ops. (line 56) * conditional assembly: If. (line 6) * constant, single character: Chars. (line 6) * constants: Constants. (line 6) @@ -23320,55 +23130,57 @@ AS Index * constants, Sparc: Sparc-Constants. (line 6) * constants, string: Strings. (line 6) * constants, TIC54X: TIC54X-Constants. (line 6) -* conversion instructions, i386: i386-Mnemonics. (line 37) -* conversion instructions, x86-64: i386-Mnemonics. (line 37) +* conversion instructions, i386: i386-Mnemonics. (line 36) +* conversion instructions, x86-64: i386-Mnemonics. (line 36) * coprocessor wait, i386: i386-Prefixes. (line 40) -* copy directive, TIC54X: TIC54X-Directives. (line 54) -* cpu directive, M680x0: M68K-Directives. (line 30) +* 'copy' directive, TIC54X: TIC54X-Directives. (line 52) +* 'cpu' directive, M680x0: M68K-Directives. (line 30) +* 'cpu' directive, MSP 430: MSP430 Directives. (line 22) * CR16 line comment character: CR16-Chars. (line 6) -* CR16 line separator: CR16-Chars. (line 13) +* CR16 line separator: CR16-Chars. (line 12) * CR16 Operand Qualifiers: CR16 Operand Qualifiers. (line 6) * CR16 support: CR16-Dependent. (line 6) * crash of assembler: Bug Criteria. (line 9) -* CRIS --emulation=crisaout command line option: CRIS-Opts. (line 9) -* CRIS --emulation=criself command line option: CRIS-Opts. (line 9) -* CRIS --march=ARCHITECTURE command line option: CRIS-Opts. (line 34) -* CRIS --mul-bug-abort command line option: CRIS-Opts. (line 62) -* CRIS --no-mul-bug-abort command line option: CRIS-Opts. (line 62) -* CRIS --no-underscore command line option: CRIS-Opts. (line 15) -* CRIS --pic command line option: CRIS-Opts. (line 27) -* CRIS --underscore command line option: CRIS-Opts. (line 15) -* CRIS -N command line option: CRIS-Opts. (line 58) +* CRIS '--emulation=crisaout' command line option: CRIS-Opts. (line 9) +* CRIS '--emulation=criself' command line option: CRIS-Opts. (line 9) +* CRIS '--march=ARCHITECTURE' command line option: CRIS-Opts. (line 34) +* CRIS '--mul-bug-abort' command line option: CRIS-Opts. (line 63) +* CRIS '--no-mul-bug-abort' command line option: CRIS-Opts. (line 63) +* CRIS '--no-underscore' command line option: CRIS-Opts. (line 15) +* CRIS '--pic' command line option: CRIS-Opts. (line 27) +* CRIS '--underscore' command line option: CRIS-Opts. (line 15) +* CRIS '-N' command line option: CRIS-Opts. (line 59) * CRIS architecture variant option: CRIS-Opts. (line 34) -* CRIS assembler directive .arch: CRIS-Pseudos. (line 45) +* CRIS assembler directive .arch: CRIS-Pseudos. (line 50) * CRIS assembler directive .dword: CRIS-Pseudos. (line 12) -* CRIS assembler directive .syntax: CRIS-Pseudos. (line 17) +* CRIS assembler directive .syntax: CRIS-Pseudos. (line 18) * CRIS assembler directives: CRIS-Pseudos. (line 6) * CRIS built-in symbols: CRIS-Symbols. (line 6) * CRIS instruction expansion: CRIS-Expand. (line 6) * CRIS line comment characters: CRIS-Chars. (line 6) * CRIS options: CRIS-Opts. (line 6) * CRIS position-independent code: CRIS-Opts. (line 27) -* CRIS pseudo-op .arch: CRIS-Pseudos. (line 45) +* CRIS pseudo-op .arch: CRIS-Pseudos. (line 50) * CRIS pseudo-op .dword: CRIS-Pseudos. (line 12) -* CRIS pseudo-op .syntax: CRIS-Pseudos. (line 17) +* CRIS pseudo-op .syntax: CRIS-Pseudos. (line 18) * CRIS pseudo-ops: CRIS-Pseudos. (line 6) * CRIS register names: CRIS-Regs. (line 6) * CRIS support: CRIS-Dependent. (line 6) * CRIS symbols in position-independent code: CRIS-Pic. (line 6) -* ctbp register, V850: V850-Regs. (line 131) -* ctoff pseudo-op, V850: V850 Opcodes. (line 111) -* ctpc register, V850: V850-Regs. (line 119) -* ctpsw register, V850: V850-Regs. (line 122) +* 'ctbp' register, V850: V850-Regs. (line 90) +* 'ctoff' pseudo-op, V850: V850 Opcodes. (line 110) +* 'ctpc' register, V850: V850-Regs. (line 82) +* 'ctpsw' register, V850: V850-Regs. (line 84) * current address: Dot. (line 6) * current address, advancing: Org. (line 6) +* 'c_mode' directive, TIC54X: TIC54X-Directives. (line 49) * D10V @word modifier: D10V-Word. (line 6) * D10V addressing modes: D10V-Addressing. (line 6) * D10V floating point: D10V-Float. (line 6) * D10V line comment character: D10V-Chars. (line 6) * D10V opcode summary: D10V-Opcodes. (line 6) -* D10V optimization: Overview. (line 490) +* D10V optimization: Overview. (line 493) * D10V options: D10V-Opts. (line 6) * D10V registers: D10V-Regs. (line 6) * D10V size modifiers: D10V-Size. (line 6) @@ -23380,10 +23192,10 @@ AS Index * D30V floating point: D30V-Float. (line 6) * D30V Guarded Execution: D30V-Guarded. (line 6) * D30V line comment character: D30V-Chars. (line 6) -* D30V nops: Overview. (line 498) -* D30V nops after 32-bit multiply: Overview. (line 501) +* D30V nops: Overview. (line 501) +* D30V nops after 32-bit multiply: Overview. (line 504) * D30V opcode summary: D30V-Opcodes. (line 6) -* D30V optimization: Overview. (line 495) +* D30V optimization: Overview. (line 498) * D30V options: D30V-Opts. (line 6) * D30V registers: D30V-Regs. (line 6) * D30V size modifiers: D30V-Size. (line 6) @@ -23393,32 +23205,32 @@ AS Index * D30V syntax: D30V-Syntax. (line 6) * data alignment on SPARC: Sparc-Aligned-Data. (line 6) * data and text sections, joining: R. (line 6) -* data directive: Data. (line 6) -* data directive, TIC54X: TIC54X-Directives. (line 61) +* 'data' directive: Data. (line 6) +* 'data' directive, TIC54X: TIC54X-Directives. (line 59) * data relocations, ARM: ARM-Relocations. (line 6) * data section: Ld Sections. (line 9) -* data1 directive, M680x0: M68K-Directives. (line 9) -* data2 directive, M680x0: M68K-Directives. (line 12) +* 'data1' directive, M680x0: M68K-Directives. (line 9) +* 'data2' directive, M680x0: M68K-Directives. (line 12) * datalabel, SH64: SH64-Addressing. (line 16) -* dbpc register, V850: V850-Regs. (line 125) -* dbpsw register, V850: V850-Regs. (line 128) +* 'dbpc' register, V850: V850-Regs. (line 86) +* 'dbpsw' register, V850: V850-Regs. (line 88) * debuggers, and symbol order: Symbols. (line 10) * debugging COFF symbols: Def. (line 6) * DEC syntax: PDP-11-Syntax. (line 6) * decimal integers: Integers. (line 12) -* def directive: Def. (line 6) -* def directive, TIC54X: TIC54X-Directives. (line 103) +* 'def' directive: Def. (line 6) +* 'def' directive, TIC54X: TIC54X-Directives. (line 101) * density instructions: Density Instructions. (line 6) * dependency tracking: MD. (line 6) * deprecated directives: Deprecated. (line 6) -* desc directive: Desc. (line 6) -* descriptor, of a.out symbol: Symbol Desc. (line 6) -* dfloat directive, VAX: VAX-directives. (line 10) +* 'desc' directive: Desc. (line 6) +* descriptor, of 'a.out' symbol: Symbol Desc. (line 6) +* 'dfloat' directive, VAX: VAX-directives. (line 9) * difference tables altered: Word. (line 12) * difference tables, warning: K. (line 6) * differences, mmixal: MMIX-mmixal. (line 6) -* dim directive: Dim. (line 6) +* 'dim' directive: Dim. (line 6) * directives and instructions: Statements. (line 20) * directives for PowerPC: PowerPC-Pseudo. (line 6) * directives for SCORE: SCORE-Pseudo. (line 6) @@ -23428,66 +23240,65 @@ AS Index * directives, machine independent: Pseudo Ops. (line 6) * directives, Xtensa: Xtensa Directives. (line 6) * directives, Z8000: Z8000 Directives. (line 6) -* Disable floating-point instructions: MIPS floating-point. (line 6) -* Disable single-precision floating-point operations: MIPS floating-point. +* Disable floating-point instructions: MIPS Floating-Point. (line 6) +* Disable single-precision floating-point operations: MIPS Floating-Point. (line 12) * displacement sizing character, VAX: VAX-operands. (line 12) -* dollar local symbols: Symbol Names. (line 110) +* dollar local symbols: Symbol Names. (line 109) * dot (symbol): Dot. (line 6) -* double directive: Double. (line 6) -* double directive, i386: i386-Float. (line 14) -* double directive, M680x0: M68K-Float. (line 14) -* double directive, M68HC11: M68HC11-Float. (line 14) -* double directive, RX: RX-Float. (line 11) -* double directive, TIC54X: TIC54X-Directives. (line 64) -* double directive, VAX: VAX-float. (line 15) -* double directive, x86-64: i386-Float. (line 14) -* double directive, XGATE: XGATE-Float. (line 13) -* doublequote (\"): Strings. (line 43) -* drlist directive, TIC54X: TIC54X-Directives. (line 73) -* drnolist directive, TIC54X: TIC54X-Directives. (line 73) -* dual directive, i860: Directives-i860. (line 6) -* dword directive, Nios II: Nios II Directives. (line 16) -* EB command line option, Nios II: Nios II Options. (line 23) -* ECOFF sections: MIPS Object. (line 6) -* ecr register, V850: V850-Regs. (line 113) +* 'double' directive: Double. (line 6) +* 'double' directive, i386: i386-Float. (line 14) +* 'double' directive, M680x0: M68K-Float. (line 14) +* 'double' directive, M68HC11: M68HC11-Float. (line 14) +* 'double' directive, RX: RX-Float. (line 11) +* 'double' directive, TIC54X: TIC54X-Directives. (line 62) +* 'double' directive, VAX: VAX-float. (line 15) +* 'double' directive, x86-64: i386-Float. (line 14) +* 'double' directive, XGATE: XGATE-Float. (line 13) +* doublequote ('\"'): Strings. (line 43) +* 'drlist' directive, TIC54X: TIC54X-Directives. (line 71) +* 'drnolist' directive, TIC54X: TIC54X-Directives. (line 71) +* 'dual' directive, i860: Directives-i860. (line 6) +* 'dword' directive, Nios II: Nios II Directives. (line 16) +* 'EB' command line option, Nios II: Nios II Options. (line 22) +* 'ecr' register, V850: V850-Regs. (line 78) * eight-byte integer: Quad. (line 9) -* eipc register, V850: V850-Regs. (line 101) -* eipsw register, V850: V850-Regs. (line 104) -* eject directive: Eject. (line 6) -* EL command line option, Nios II: Nios II Options. (line 26) +* 'eipc' register, V850: V850-Regs. (line 70) +* 'eipsw' register, V850: V850-Regs. (line 72) +* 'eject' directive: Eject. (line 6) +* 'EL' command line option, Nios II: Nios II Options. (line 25) * ELF symbol type: Type. (line 22) -* else directive: Else. (line 6) -* elseif directive: Elseif. (line 6) +* 'else' directive: Else. (line 6) +* 'elseif' directive: Elseif. (line 6) * empty expressions: Empty Exprs. (line 6) -* emsg directive, TIC54X: TIC54X-Directives. (line 77) -* emulation: Overview. (line 843) -* encoding options, i386: i386-Mnemonics. (line 32) -* encoding options, x86-64: i386-Mnemonics. (line 32) -* end directive: End. (line 6) -* enddual directive, i860: Directives-i860. (line 11) -* endef directive: Endef. (line 6) -* endfunc directive: Endfunc. (line 6) -* endianness, MIPS: Overview. (line 727) -* endianness, PJ: Overview. (line 630) -* endif directive: Endif. (line 6) -* endloop directive, TIC54X: TIC54X-Directives. (line 143) -* endm directive: Macro. (line 138) -* endm directive, TIC54X: TIC54X-Directives. (line 153) -* endstruct directive, TIC54X: TIC54X-Directives. (line 216) -* endunion directive, TIC54X: TIC54X-Directives. (line 250) +* 'emsg' directive, TIC54X: TIC54X-Directives. (line 75) +* emulation: Overview. (line 856) +* encoding options, i386: i386-Mnemonics. (line 31) +* encoding options, x86-64: i386-Mnemonics. (line 31) +* 'end' directive: End. (line 6) +* 'enddual' directive, i860: Directives-i860. (line 11) +* 'endef' directive: Endef. (line 6) +* 'endfunc' directive: Endfunc. (line 6) +* endianness, MIPS: Overview. (line 720) +* endianness, PJ: Overview. (line 627) +* 'endif' directive: Endif. (line 6) +* 'endloop' directive, TIC54X: TIC54X-Directives. (line 141) +* 'endm' directive: Macro. (line 137) +* 'endm' directive, TIC54X: TIC54X-Directives. (line 151) +* 'endstruct' directive, TIC54X: TIC54X-Directives. (line 214) +* 'endunion' directive, TIC54X: TIC54X-Directives. (line 248) * environment settings, TIC54X: TIC54X-Env. (line 6) * EOF, newline must precede: Statements. (line 14) -* ep register, V850: V850-Regs. (line 95) +* 'ep' register, V850: V850-Regs. (line 66) * Epiphany line comment character: Epiphany-Chars. (line 6) * Epiphany line separator: Epiphany-Chars. (line 14) * Epiphany options: Epiphany Options. (line 6) * Epiphany support: Epiphany-Dependent. (line 6) -* equ directive: Equ. (line 6) -* equ directive, TIC54X: TIC54X-Directives. (line 191) -* equiv directive: Equiv. (line 6) -* eqv directive: Eqv. (line 6) -* err directive: Err. (line 6) +* 'equ' directive: Equ. (line 6) +* 'equ' directive, TIC54X: TIC54X-Directives. (line 189) +* 'equiv' directive: Equiv. (line 6) +* 'eqv' directive: Eqv. (line 6) +* 'err' directive: Err. (line 6) * error directive: Error. (line 6) * error messages: Errors. (line 6) * error on valid input: Bug Criteria. (line 12) @@ -23496,61 +23307,61 @@ AS Index * ESA/390 floating point (IEEE): ESA/390 Floating Point. (line 6) * ESA/390 support: ESA/390-Dependent. (line 6) -* ESA/390 Syntax: ESA/390 Options. (line 8) +* ESA/390 Syntax: ESA/390 Options. (line 7) * ESA/390-only directives: ESA/390 Directives. (line 12) * escape codes, character: Strings. (line 15) -* eval directive, TIC54X: TIC54X-Directives. (line 24) -* even: Z8000 Directives. (line 58) -* even directive, M680x0: M68K-Directives. (line 15) -* even directive, TIC54X: TIC54X-Directives. (line 6) -* exitm directive: Macro. (line 141) +* 'eval' directive, TIC54X: TIC54X-Directives. (line 22) +* even: Z8000 Directives. (line 57) +* 'even' directive, M680x0: M68K-Directives. (line 15) +* 'even' directive, TIC54X: TIC54X-Directives. (line 6) +* 'exitm' directive: Macro. (line 140) * expr (internal section): As Sections. (line 17) * expression arguments: Arguments. (line 6) * expressions: Expressions. (line 6) -* expressions, comparison: Infix Ops. (line 55) +* expressions, comparison: Infix Ops. (line 56) * expressions, empty: Empty Exprs. (line 6) * expressions, integer: Integer Exprs. (line 6) -* extAuxRegister directive, ARC: ARC Directives. (line 18) -* extCondCode directive, ARC: ARC Directives. (line 41) -* extCoreRegister directive, ARC: ARC Directives. (line 53) -* extend directive M680x0: M68K-Float. (line 17) -* extend directive M68HC11: M68HC11-Float. (line 17) -* extend directive XGATE: XGATE-Float. (line 16) -* extended directive, i960: Directives-i960. (line 13) -* extern directive: Extern. (line 6) -* extInstruction directive, ARC: ARC Directives. (line 78) -* fail directive: Fail. (line 6) -* far_mode directive, TIC54X: TIC54X-Directives. (line 82) -* faster processing (-f): f. (line 6) +* 'extAuxRegister' directive, ARC: ARC Directives. (line 18) +* 'extCondCode' directive, ARC: ARC Directives. (line 38) +* 'extCoreRegister' directive, ARC: ARC Directives. (line 50) +* 'extend' directive M680x0: M68K-Float. (line 17) +* 'extend' directive M68HC11: M68HC11-Float. (line 17) +* 'extend' directive XGATE: XGATE-Float. (line 16) +* 'extended' directive, i960: Directives-i960. (line 13) +* 'extern' directive: Extern. (line 6) +* 'extInstruction' directive, ARC: ARC Directives. (line 72) +* 'fail' directive: Fail. (line 6) +* 'far_mode' directive, TIC54X: TIC54X-Directives. (line 80) +* faster processing ('-f'): f. (line 6) * fatal signal: Bug Criteria. (line 9) -* fclist directive, TIC54X: TIC54X-Directives. (line 87) -* fcnolist directive, TIC54X: TIC54X-Directives. (line 87) -* fepc register, V850: V850-Regs. (line 107) -* fepsw register, V850: V850-Regs. (line 110) -* ffloat directive, VAX: VAX-directives. (line 14) -* field directive, TIC54X: TIC54X-Directives. (line 91) -* file directive: File. (line 6) -* file directive, MSP 430: MSP430 Directives. (line 6) +* 'fclist' directive, TIC54X: TIC54X-Directives. (line 85) +* 'fcnolist' directive, TIC54X: TIC54X-Directives. (line 85) +* 'fepc' register, V850: V850-Regs. (line 74) +* 'fepsw' register, V850: V850-Regs. (line 76) +* 'ffloat' directive, VAX: VAX-directives. (line 13) +* 'field' directive, TIC54X: TIC54X-Directives. (line 89) +* 'file' directive: File. (line 6) +* 'file' directive, MSP 430: MSP430 Directives. (line 6) * file name, logical: File. (line 13) * files, including: Include. (line 6) * files, input: Input Files. (line 6) -* fill directive: Fill. (line 6) -* filling memory <1>: Space. (line 6) +* 'fill' directive: Fill. (line 6) * filling memory: Skip. (line 6) +* filling memory <1>: Space. (line 6) * FLIX syntax: Xtensa Syntax. (line 6) -* float directive: Float. (line 6) -* float directive, i386: i386-Float. (line 14) -* float directive, M680x0: M68K-Float. (line 11) -* float directive, M68HC11: M68HC11-Float. (line 11) -* float directive, RX: RX-Float. (line 8) -* float directive, TIC54X: TIC54X-Directives. (line 64) -* float directive, VAX: VAX-float. (line 15) -* float directive, x86-64: i386-Float. (line 14) -* float directive, XGATE: XGATE-Float. (line 10) +* 'float' directive: Float. (line 6) +* 'float' directive, i386: i386-Float. (line 14) +* 'float' directive, M680x0: M68K-Float. (line 11) +* 'float' directive, M68HC11: M68HC11-Float. (line 11) +* 'float' directive, RX: RX-Float. (line 8) +* 'float' directive, TIC54X: TIC54X-Directives. (line 62) +* 'float' directive, VAX: VAX-float. (line 15) +* 'float' directive, x86-64: i386-Float. (line 14) +* 'float' directive, XGATE: XGATE-Float. (line 10) * floating point numbers: Flonums. (line 6) * floating point numbers (double): Double. (line 6) -* floating point numbers (single) <1>: Single. (line 6) * floating point numbers (single): Float. (line 6) +* floating point numbers (single) <1>: Single. (line 6) * floating point, AArch64 (IEEE): AArch64 Floating Point. (line 6) * floating point, Alpha (IEEE): Alpha Floating Point. @@ -23582,21 +23393,21 @@ AS Index * flonums: Flonums. (line 6) * format of error messages: Errors. (line 24) * format of warning messages: Errors. (line 12) -* formfeed (\f): Strings. (line 18) -* func directive: Func. (line 6) +* formfeed ('\f'): Strings. (line 18) +* 'func' directive: Func. (line 6) * functions, in expressions: Operators. (line 6) -* gbr960, i960 postprocessor: Options-i960. (line 40) -* gfloat directive, VAX: VAX-directives. (line 18) +* 'gbr960', i960 postprocessor: Options-i960. (line 40) +* 'gfloat' directive, VAX: VAX-directives. (line 17) * global: Z8000 Directives. (line 21) -* global directive: Global. (line 6) -* global directive, TIC54X: TIC54X-Directives. (line 103) -* got directive, Nios II: Nios II Relocations. (line 38) -* gotoff directive, Nios II: Nios II Relocations. (line 38) -* gotoff_hiadj directive, Nios II: Nios II Relocations. (line 38) -* gotoff_lo directive, Nios II: Nios II Relocations. (line 38) -* gp register, MIPS: MIPS Object. (line 11) -* gp register, V850: V850-Regs. (line 17) -* gprel directive, Nios II: Nios II Relocations. (line 26) +* 'global' directive: Global. (line 6) +* 'global' directive, TIC54X: TIC54X-Directives. (line 101) +* 'got' directive, Nios II: Nios II Relocations. (line 38) +* 'gotoff' directive, Nios II: Nios II Relocations. (line 38) +* 'gotoff_hiadj' directive, Nios II: Nios II Relocations. (line 38) +* 'gotoff_lo' directive, Nios II: Nios II Relocations. (line 38) +* 'gp' register, MIPS: MIPS Small Data. (line 6) +* 'gp' register, V850: V850-Regs. (line 14) +* 'gprel' directive, Nios II: Nios II Relocations. (line 26) * grouping data: Sub-Sections. (line 6) * H8/300 addressing modes: H8/300-Addressing. (line 6) * H8/300 floating point (IEEE): H8/300 Floating Point. @@ -23607,53 +23418,53 @@ AS Index * H8/300 opcode summary: H8/300 Opcodes. (line 6) * H8/300 options: H8/300 Options. (line 6) * H8/300 registers: H8/300-Regs. (line 6) -* H8/300 size suffixes: H8/300 Opcodes. (line 163) +* H8/300 size suffixes: H8/300 Opcodes. (line 160) * H8/300 support: H8/300-Dependent. (line 6) * H8/300H, assembling for: H8/300 Directives. (line 8) -* half directive, ARC: ARC Directives. (line 153) -* half directive, Nios II: Nios II Directives. (line 10) -* half directive, SPARC: Sparc-Directives. (line 17) -* half directive, TIC54X: TIC54X-Directives. (line 111) -* hex character code (\XD...): Strings. (line 36) +* 'half' directive, ARC: ARC Directives. (line 144) +* 'half' directive, Nios II: Nios II Directives. (line 10) +* 'half' directive, SPARC: Sparc-Directives. (line 17) +* 'half' directive, TIC54X: TIC54X-Directives. (line 109) +* hex character code ('\XD...'): Strings. (line 36) * hexadecimal integers: Integers. (line 15) * hexadecimal prefix, Z80: Z80-Chars. (line 15) -* hfloat directive, VAX: VAX-directives. (line 22) -* hi directive, Nios II: Nios II Relocations. (line 20) -* hi pseudo-op, V850: V850 Opcodes. (line 33) -* hi0 pseudo-op, V850: V850 Opcodes. (line 10) -* hiadj directive, Nios II: Nios II Relocations. (line 6) -* hidden directive: Hidden. (line 6) -* high directive, M32R: M32R-Directives. (line 18) -* hilo pseudo-op, V850: V850 Opcodes. (line 55) +* 'hfloat' directive, VAX: VAX-directives. (line 21) +* 'hi' directive, Nios II: Nios II Relocations. (line 20) +* 'hi' pseudo-op, V850: V850 Opcodes. (line 33) +* 'hi0' pseudo-op, V850: V850 Opcodes. (line 10) +* 'hiadj' directive, Nios II: Nios II Relocations. (line 6) +* 'hidden' directive: Hidden. (line 6) +* 'high' directive, M32R: M32R-Directives. (line 18) +* 'hilo' pseudo-op, V850: V850 Opcodes. (line 55) * HPPA directives not supported: HPPA Directives. (line 11) * HPPA floating point (IEEE): HPPA Floating Point. (line 6) -* HPPA Syntax: HPPA Options. (line 8) +* HPPA Syntax: HPPA Options. (line 7) * HPPA-only directives: HPPA Directives. (line 24) -* hword directive: hword. (line 6) +* 'hword' directive: hword. (line 6) * i370 support: ESA/390-Dependent. (line 6) * i386 16-bit code: i386-16bit. (line 6) * i386 arch directive: i386-Arch. (line 6) * i386 att_syntax pseudo op: i386-Variations. (line 6) -* i386 conversion instructions: i386-Mnemonics. (line 37) +* i386 conversion instructions: i386-Mnemonics. (line 36) * i386 floating point: i386-Float. (line 6) * i386 immediate operands: i386-Variations. (line 15) * i386 instruction naming: i386-Mnemonics. (line 6) * i386 instruction prefixes: i386-Prefixes. (line 6) * i386 intel_syntax pseudo op: i386-Variations. (line 6) * i386 jump optimization: i386-Jumps. (line 6) -* i386 jump, call, return: i386-Variations. (line 41) +* i386 jump, call, return: i386-Variations. (line 40) * i386 jump/call operands: i386-Variations. (line 15) * i386 line comment character: i386-Chars. (line 6) * i386 line separator: i386-Chars. (line 18) * i386 memory references: i386-Memory. (line 6) -* i386 mnemonic compatibility: i386-Mnemonics. (line 62) -* i386 mul, imul instructions: i386-Notes. (line 6) +* i386 mnemonic compatibility: i386-Mnemonics. (line 61) +* i386 'mul', 'imul' instructions: i386-Notes. (line 6) * i386 options: i386-Options. (line 6) * i386 register operands: i386-Variations. (line 15) * i386 registers: i386-Regs. (line 6) -* i386 sections: i386-Variations. (line 47) -* i386 size suffixes: i386-Variations. (line 29) -* i386 source, destination operands: i386-Variations. (line 22) +* i386 sections: i386-Variations. (line 46) +* i386 size suffixes: i386-Variations. (line 28) +* i386 source, destination operands: i386-Variations. (line 21) * i386 support: i386-Dependent. (line 6) * i386 syntax compatibility: i386-Variations. (line 6) * i80386 support: i386-Dependent. (line 6) @@ -23664,7 +23475,7 @@ AS Index * i860 support: i860-Dependent. (line 6) * i960 architecture options: Options-i960. (line 6) * i960 branch recording: Options-i960. (line 22) -* i960 callj pseudo-opcode: callj-i960. (line 6) +* i960 'callj' pseudo-opcode: callj-i960. (line 6) * i960 compare and jump expansions: Compare-and-branch-i960. (line 13) * i960 compare/branch instructions: Compare-and-branch-i960. @@ -23683,26 +23494,26 @@ AS Index * IA-64 registers: IA-64-Regs. (line 6) * IA-64 relocations: IA-64-Relocs. (line 6) * IA-64 support: IA-64-Dependent. (line 6) -* IA-64 Syntax: IA-64 Options. (line 87) -* ident directive: Ident. (line 6) +* IA-64 Syntax: IA-64 Options. (line 85) +* 'ident' directive: Ident. (line 6) * identifiers, ARM: ARM-Chars. (line 19) * identifiers, MSP 430: MSP430-Chars. (line 17) -* if directive: If. (line 6) -* ifb directive: If. (line 21) -* ifc directive: If. (line 25) -* ifdef directive: If. (line 16) -* ifeq directive: If. (line 33) -* ifeqs directive: If. (line 36) -* ifge directive: If. (line 40) -* ifgt directive: If. (line 44) -* ifle directive: If. (line 48) -* iflt directive: If. (line 52) -* ifnb directive: If. (line 56) -* ifnc directive: If. (line 61) -* ifndef directive: If. (line 65) -* ifne directive: If. (line 72) -* ifnes directive: If. (line 76) -* ifnotdef directive: If. (line 65) +* 'if' directive: If. (line 6) +* 'ifb' directive: If. (line 21) +* 'ifc' directive: If. (line 25) +* 'ifdef' directive: If. (line 16) +* 'ifeq' directive: If. (line 33) +* 'ifeqs' directive: If. (line 36) +* 'ifge' directive: If. (line 40) +* 'ifgt' directive: If. (line 44) +* 'ifle' directive: If. (line 48) +* 'iflt' directive: If. (line 52) +* 'ifnb' directive: If. (line 56) +* 'ifnc' directive: If. (line 61) +* 'ifndef' directive: If. (line 65) +* 'ifne' directive: If. (line 72) +* 'ifnes' directive: If. (line 76) +* 'ifnotdef' directive: If. (line 65) * immediate character, AArch64: AArch64-Chars. (line 13) * immediate character, ARM: ARM-Chars. (line 17) * immediate character, M680x0: M68K-Chars. (line 13) @@ -23711,11 +23522,11 @@ AS Index (line 6) * immediate operands, i386: i386-Variations. (line 15) * immediate operands, x86-64: i386-Variations. (line 15) -* imul instruction, i386: i386-Notes. (line 6) -* imul instruction, x86-64: i386-Notes. (line 6) -* incbin directive: Incbin. (line 6) -* include directive: Include. (line 6) -* include directive search path: I. (line 6) +* 'imul' instruction, i386: i386-Notes. (line 6) +* 'imul' instruction, x86-64: i386-Notes. (line 6) +* 'incbin' directive: Incbin. (line 6) +* 'include' directive: Include. (line 6) +* 'include' directive search path: I. (line 6) * indirect character, VAX: VAX-operands. (line 9) * infix operators: Infix Ops. (line 6) * inhibiting interrupts, i386: i386-Prefixes. (line 36) @@ -23737,7 +23548,7 @@ AS Index * instruction prefixes, i386: i386-Prefixes. (line 6) * instruction set, M680x0: M68K-opcodes. (line 6) * instruction set, M68HC11: M68HC11-opcodes. (line 6) -* instruction set, XGATE: XGATE-opcodes. (line 6) +* instruction set, XGATE: XGATE-opcodes. (line 5) * instruction summary, AVR: AVR Opcodes. (line 6) * instruction summary, D10V: D10V-Opcodes. (line 6) * instruction summary, D30V: D30V-Opcodes. (line 6) @@ -23748,11 +23559,11 @@ AS Index * instruction summary, Z8000: Z8000 Opcodes. (line 6) * instruction syntax, s390: s390 Syntax. (line 6) * instructions and directives: Statements. (line 20) -* int directive: Int. (line 6) -* int directive, H8/300: H8/300 Directives. (line 6) -* int directive, i386: i386-Float. (line 21) -* int directive, TIC54X: TIC54X-Directives. (line 111) -* int directive, x86-64: i386-Float. (line 21) +* 'int' directive: Int. (line 6) +* 'int' directive, H8/300: H8/300 Directives. (line 6) +* 'int' directive, i386: i386-Float. (line 21) +* 'int' directive, TIC54X: TIC54X-Directives. (line 109) +* 'int' directive, x86-64: i386-Float. (line 21) * integer expressions: Integer Exprs. (line 6) * integer, 16-byte: Octa. (line 6) * integer, 8-byte: Quad. (line 9) @@ -23767,48 +23578,49 @@ AS Index * intel_syntax pseudo op, i386: i386-Variations. (line 6) * intel_syntax pseudo op, x86-64: i386-Variations. (line 6) * internal assembler sections: As Sections. (line 6) -* internal directive: Internal. (line 6) +* 'internal' directive: Internal. (line 6) * invalid input: Bug Criteria. (line 14) * invocation summary: Overview. (line 6) * IP2K architecture options: IP2K-Opts. (line 9) +* IP2K architecture options <1>: IP2K-Opts. (line 14) * IP2K line comment character: IP2K-Chars. (line 6) * IP2K line separator: IP2K-Chars. (line 14) * IP2K options: IP2K-Opts. (line 6) * IP2K support: IP2K-Dependent. (line 6) -* irp directive: Irp. (line 6) -* irpc directive: Irpc. (line 6) +* 'irp' directive: Irp. (line 6) +* 'irpc' directive: Irpc. (line 6) * ISA options, SH64: SH64 Options. (line 6) * joining text and data sections: R. (line 6) -* jump instructions, i386: i386-Mnemonics. (line 56) -* jump instructions, x86-64: i386-Mnemonics. (line 56) +* jump instructions, i386: i386-Mnemonics. (line 55) +* jump instructions, x86-64: i386-Mnemonics. (line 55) * jump optimization, i386: i386-Jumps. (line 6) * jump optimization, x86-64: i386-Jumps. (line 6) * jump/call operands, i386: i386-Variations. (line 15) * jump/call operands, x86-64: i386-Variations. (line 15) -* L16SI instructions, relaxation: Xtensa Immediate Relaxation. +* 'L16SI' instructions, relaxation: Xtensa Immediate Relaxation. (line 23) -* L16UI instructions, relaxation: Xtensa Immediate Relaxation. +* 'L16UI' instructions, relaxation: Xtensa Immediate Relaxation. (line 23) -* L32I instructions, relaxation: Xtensa Immediate Relaxation. +* 'L32I' instructions, relaxation: Xtensa Immediate Relaxation. (line 23) -* L8UI instructions, relaxation: Xtensa Immediate Relaxation. +* 'L8UI' instructions, relaxation: Xtensa Immediate Relaxation. (line 23) -* label (:): Statements. (line 31) -* label directive, TIC54X: TIC54X-Directives. (line 123) +* label (':'): Statements. (line 31) +* 'label' directive, TIC54X: TIC54X-Directives. (line 121) * labels: Labels. (line 6) -* lcomm directive: Lcomm. (line 6) -* lcomm directive, COFF: i386-Directives. (line 6) +* 'lcomm' directive: Lcomm. (line 6) +* 'lcomm' directive, COFF: i386-Directives. (line 6) * ld: Object. (line 15) -* ldouble directive M680x0: M68K-Float. (line 17) -* ldouble directive M68HC11: M68HC11-Float. (line 17) -* ldouble directive XGATE: XGATE-Float. (line 16) -* ldouble directive, TIC54X: TIC54X-Directives. (line 64) -* LDR reg,=<expr> pseudo op, AArch64: AArch64 Opcodes. (line 9) -* LDR reg,=<label> pseudo op, ARM: ARM Opcodes. (line 15) -* leafproc directive, i960: Directives-i960. (line 18) -* length directive, TIC54X: TIC54X-Directives. (line 127) +* 'ldouble' directive M680x0: M68K-Float. (line 17) +* 'ldouble' directive M68HC11: M68HC11-Float. (line 17) +* 'ldouble' directive XGATE: XGATE-Float. (line 16) +* 'ldouble' directive, TIC54X: TIC54X-Directives. (line 62) +* 'LDR reg,=<expr>' pseudo op, AArch64: AArch64 Opcodes. (line 9) +* 'LDR reg,=<label>' pseudo op, ARM: ARM Opcodes. (line 15) +* 'leafproc' directive, i960: Directives-i960. (line 18) +* 'length' directive, TIC54X: TIC54X-Directives. (line 125) * length of symbols: Symbol Intro. (line 14) -* lflags directive (ignored): Lflags. (line 6) +* 'lflags' directive (ignored): Lflags. (line 6) * line comment character: Comments. (line 19) * line comment character, AArch64: AArch64-Chars. (line 6) * line comment character, Alpha: Alpha-Chars. (line 6) @@ -23854,8 +23666,8 @@ AS Index * line comment character, Z8000: Z8000-Chars. (line 6) * line comment characters, CRIS: CRIS-Chars. (line 6) * line comment characters, MMIX: MMIX-Chars. (line 6) -* line directive: Line. (line 6) -* line directive, MSP 430: MSP430 Directives. (line 14) +* 'line' directive: Line. (line 6) +* 'line' directive, MSP 430: MSP430 Directives. (line 14) * line numbers, in input files: Input Files. (line 35) * line numbers, in warnings/errors: Errors. (line 16) * line separator character: Statements. (line 6) @@ -23865,7 +23677,7 @@ AS Index * line separator, ARC: ARC-Chars. (line 12) * line separator, ARM: ARM-Chars. (line 14) * line separator, AVR: AVR-Chars. (line 14) -* line separator, CR16: CR16-Chars. (line 13) +* line separator, CR16: CR16-Chars. (line 12) * line separator, Epiphany: Epiphany-Chars. (line 14) * line separator, H8/300: H8/300-Chars. (line 8) * line separator, i386: i386-Chars. (line 18) @@ -23876,7 +23688,7 @@ AS Index * line separator, LM32: LM32-Chars. (line 12) * line separator, M32C: M32C-Chars. (line 14) * line separator, M680x0: M68K-Chars. (line 20) -* line separator, M68HC11: M68HC11-Syntax. (line 27) +* line separator, M68HC11: M68HC11-Syntax. (line 26) * line separator, Meta: Meta-Chars. (line 8) * line separator, MicroBlaze: MicroBlaze-Chars. (line 14) * line separator, MIPS: MIPS-Chars. (line 14) @@ -23895,16 +23707,16 @@ AS Index * line separator, TIC6X: TIC6X Syntax. (line 13) * line separator, V850: V850-Chars. (line 13) * line separator, VAX: VAX-Chars. (line 14) -* line separator, XGATE: XGATE-Syntax. (line 26) +* line separator, XGATE: XGATE-Syntax. (line 25) * line separator, XStormy16: XStormy16-Chars. (line 14) * line separator, Z80: Z80-Chars. (line 13) * line separator, Z8000: Z8000-Chars. (line 13) -* lines starting with #: Comments. (line 33) +* lines starting with '#': Comments. (line 33) * linker: Object. (line 15) * linker, and assembler: Secs Background. (line 10) -* linkonce directive: Linkonce. (line 6) -* list directive: List. (line 6) -* list directive, TIC54X: TIC54X-Directives. (line 131) +* 'linkonce' directive: Linkonce. (line 6) +* 'list' directive: List. (line 6) +* 'list' directive, TIC54X: TIC54X-Directives. (line 129) * listing control, turning off: Nolist. (line 6) * listing control, turning on: List. (line 6) * listing control: new page: Eject. (line 6) @@ -23912,16 +23724,16 @@ AS Index * listing control: subtitle: Sbttl. (line 6) * listing control: title line: Title. (line 6) * listings, enabling: a. (line 6) -* literal directive: Literal Directive. (line 6) +* 'literal' directive: Literal Directive. (line 6) * literal pool entries, s390: s390 Literal Pool Entries. (line 6) -* literal_position directive: Literal Position Directive. +* 'literal_position' directive: Literal Position Directive. (line 6) -* literal_prefix directive: Literal Prefix Directive. +* 'literal_prefix' directive: Literal Prefix Directive. (line 6) -* little endian output, MIPS: Overview. (line 730) -* little endian output, PJ: Overview. (line 633) -* little-endian output, MIPS: MIPS Opts. (line 13) +* little endian output, MIPS: Overview. (line 723) +* little endian output, PJ: Overview. (line 630) +* little-endian output, MIPS: MIPS Options. (line 13) * little-endian output, TIC6X: TIC6X Options. (line 46) * LM32 line comment character: LM32-Chars. (line 6) * LM32 line separator: LM32-Chars. (line 12) @@ -23930,35 +23742,35 @@ AS Index * LM32 options (none): LM32 Options. (line 6) * LM32 register names: LM32-Regs. (line 6) * LM32 support: LM32-Dependent. (line 6) -* ln directive: Ln. (line 6) -* lo directive, Nios II: Nios II Relocations. (line 23) -* lo pseudo-op, V850: V850 Opcodes. (line 22) -* loc directive: Loc. (line 6) -* loc_mark_labels directive: Loc_mark_labels. (line 6) +* 'ln' directive: Ln. (line 6) +* 'lo' directive, Nios II: Nios II Relocations. (line 23) +* 'lo' pseudo-op, V850: V850 Opcodes. (line 22) +* 'loc' directive: Loc. (line 6) * local common symbols: Lcomm. (line 6) -* local directive: Local. (line 6) +* 'local' directive: Local. (line 6) * local labels: Symbol Names. (line 40) * local symbol names: Symbol Names. (line 27) * local symbols, retaining in output: L. (line 6) * location counter: Dot. (line 6) * location counter, advancing: Org. (line 6) * location counter, Z80: Z80-Chars. (line 15) +* 'loc_mark_labels' directive: Loc_mark_labels. (line 6) * logical file name: File. (line 13) * logical line number: Line. (line 6) * logical line numbers: Comments. (line 33) -* long directive: Long. (line 6) -* long directive, ARC: ARC Directives. (line 156) -* long directive, i386: i386-Float. (line 21) -* long directive, TIC54X: TIC54X-Directives. (line 135) -* long directive, x86-64: i386-Float. (line 21) -* longcall pseudo-op, V850: V850 Opcodes. (line 123) -* longcalls directive: Longcalls Directive. (line 6) -* longjump pseudo-op, V850: V850 Opcodes. (line 129) -* loop directive, TIC54X: TIC54X-Directives. (line 143) -* LOOP instructions, alignment: Xtensa Automatic Alignment. +* 'long' directive: Long. (line 6) +* 'long' directive, ARC: ARC Directives. (line 147) +* 'long' directive, i386: i386-Float. (line 21) +* 'long' directive, TIC54X: TIC54X-Directives. (line 133) +* 'long' directive, x86-64: i386-Float. (line 21) +* 'longcall' pseudo-op, V850: V850 Opcodes. (line 122) +* 'longcalls' directive: Longcalls Directive. (line 6) +* 'longjump' pseudo-op, V850: V850 Opcodes. (line 128) +* 'loop' directive, TIC54X: TIC54X-Directives. (line 141) +* 'LOOP' instructions, alignment: Xtensa Automatic Alignment. (line 6) -* low directive, M32R: M32R-Directives. (line 9) -* lp register, V850: V850-Regs. (line 98) +* 'low' directive, M32R: M32R-Directives. (line 9) +* 'lp' register, V850: V850-Regs. (line 68) * lval: Z8000 Directives. (line 27) * LWP, i386: i386-LWP. (line 6) * LWP, x86-64: i386-LWP. (line 6) @@ -23970,12 +23782,14 @@ AS Index * M32C options: M32C-Opts. (line 6) * M32C support: M32C-Dependent. (line 6) * M32R architecture options: M32R-Opts. (line 9) +* M32R architecture options <1>: M32R-Opts. (line 17) +* M32R architecture options <2>: M32R-Opts. (line 21) * M32R directives: M32R-Directives. (line 6) * M32R options: M32R-Opts. (line 6) * M32R support: M32R-Dependent. (line 6) * M32R warnings: M32R-Warnings. (line 6) * M680x0 addressing modes: M68K-Syntax. (line 21) -* M680x0 architecture options: M68K-Opts. (line 98) +* M680x0 architecture options: M68K-Opts. (line 99) * M680x0 branch improvement: M68K-Branch. (line 6) * M680x0 directives: M68K-Directives. (line 6) * M680x0 floating point: M68K-Float. (line 6) @@ -23988,7 +23802,7 @@ AS Index * M680x0 size modifiers: M68K-Syntax. (line 8) * M680x0 support: M68K-Dependent. (line 6) * M680x0 syntax: M68K-Syntax. (line 8) -* M68HC11 addressing modes: M68HC11-Syntax. (line 30) +* M68HC11 addressing modes: M68HC11-Syntax. (line 29) * M68HC11 and M68HC12 support: M68HC11-Dependent. (line 6) * M68HC11 assembler directive .far: M68HC11-Directives. (line 20) * M68HC11 assembler directive .interrupt: M68HC11-Directives. (line 26) @@ -23999,7 +23813,7 @@ AS Index * M68HC11 branch improvement: M68HC11-Branch. (line 6) * M68HC11 floating point: M68HC11-Float. (line 6) * M68HC11 line comment character: M68HC11-Syntax. (line 17) -* M68HC11 line separator: M68HC11-Syntax. (line 27) +* M68HC11 line separator: M68HC11-Syntax. (line 26) * M68HC11 modifiers: M68HC11-Modifiers. (line 6) * M68HC11 opcodes: M68HC11-opcodes. (line 6) * M68HC11 options: M68HC11-Opts. (line 6) @@ -24032,10 +23846,10 @@ AS Index * machine instructions (not covered): Manual. (line 14) * machine relocations, Nios II: Nios II Relocations. (line 6) * machine-independent syntax: Syntax. (line 6) -* macro directive: Macro. (line 28) -* macro directive, TIC54X: TIC54X-Directives. (line 153) +* 'macro' directive: Macro. (line 28) +* 'macro' directive, TIC54X: TIC54X-Directives. (line 151) * macros: Macro. (line 6) -* macros, count executed: Macro. (line 143) +* macros, count executed: Macro. (line 142) * Macros, MSP 430: MSP430-Macros. (line 6) * macros, TIC54X: TIC54X-Macros. (line 6) * make rules: MD. (line 6) @@ -24060,72 +23874,74 @@ AS Index * MicroBlaze line comment character: MicroBlaze-Chars. (line 6) * MicroBlaze line separator: MicroBlaze-Chars. (line 14) * MicroBlaze support: MicroBlaze-Dependent. - (line 13) -* minus, permitted arguments: Infix Ops. (line 49) -* MIPS architecture options: MIPS Opts. (line 29) -* MIPS big-endian output: MIPS Opts. (line 13) + (line 12) +* minus, permitted arguments: Infix Ops. (line 50) +* MIPS 32-bit microMIPS instruction generation override: MIPS assembly options. + (line 6) +* MIPS architecture options: MIPS Options. (line 29) +* MIPS big-endian output: MIPS Options. (line 13) * MIPS CPU override: MIPS ISA. (line 18) -* MIPS debugging directives: MIPS Stabs. (line 6) -* MIPS DSP Release 1 instruction generation override: MIPS ASE instruction generation overrides. +* MIPS DSP Release 1 instruction generation override: MIPS ASE Instruction Generation Overrides. (line 21) -* MIPS DSP Release 2 instruction generation override: MIPS ASE instruction generation overrides. +* MIPS DSP Release 2 instruction generation override: MIPS ASE Instruction Generation Overrides. (line 26) -* MIPS ECOFF sections: MIPS Object. (line 6) -* MIPS endianness: Overview. (line 727) -* MIPS ISA: Overview. (line 733) +* MIPS endianness: Overview. (line 720) +* MIPS IEEE 754 NaN data encoding selection: MIPS NaN Encodings. + (line 6) +* MIPS ISA: Overview. (line 726) * MIPS ISA override: MIPS ISA. (line 6) * MIPS line comment character: MIPS-Chars. (line 6) * MIPS line separator: MIPS-Chars. (line 14) -* MIPS little-endian output: MIPS Opts. (line 13) -* MIPS MCU instruction generation override: MIPS ASE instruction generation overrides. - (line 37) -* MIPS MDMX instruction generation override: MIPS ASE instruction generation overrides. +* MIPS little-endian output: MIPS Options. (line 13) +* MIPS MCU instruction generation override: MIPS ASE Instruction Generation Overrides. + (line 36) +* MIPS MDMX instruction generation override: MIPS ASE Instruction Generation Overrides. (line 16) -* MIPS MIPS-3D instruction generation override: MIPS ASE instruction generation overrides. +* MIPS MIPS-3D instruction generation override: MIPS ASE Instruction Generation Overrides. (line 6) -* MIPS MT instruction generation override: MIPS ASE instruction generation overrides. - (line 32) -* MIPS option stack: MIPS option stack. (line 6) +* MIPS MT instruction generation override: MIPS ASE Instruction Generation Overrides. + (line 31) +* MIPS option stack: MIPS Option Stack. (line 6) * MIPS processor: MIPS-Dependent. (line 6) * MIT: M68K-Syntax. (line 6) -* mlib directive, TIC54X: TIC54X-Directives. (line 159) -* mlist directive, TIC54X: TIC54X-Directives. (line 164) -* MMIX assembler directive BSPEC: MMIX-Pseudos. (line 131) -* MMIX assembler directive BYTE: MMIX-Pseudos. (line 97) -* MMIX assembler directive ESPEC: MMIX-Pseudos. (line 131) -* MMIX assembler directive GREG: MMIX-Pseudos. (line 50) -* MMIX assembler directive IS: MMIX-Pseudos. (line 42) +* 'mlib' directive, TIC54X: TIC54X-Directives. (line 157) +* 'mlist' directive, TIC54X: TIC54X-Directives. (line 162) +* MMIX assembler directive BSPEC: MMIX-Pseudos. (line 137) +* MMIX assembler directive BYTE: MMIX-Pseudos. (line 101) +* MMIX assembler directive ESPEC: MMIX-Pseudos. (line 137) +* MMIX assembler directive GREG: MMIX-Pseudos. (line 53) +* MMIX assembler directive IS: MMIX-Pseudos. (line 44) * MMIX assembler directive LOC: MMIX-Pseudos. (line 7) -* MMIX assembler directive LOCAL: MMIX-Pseudos. (line 28) -* MMIX assembler directive OCTA: MMIX-Pseudos. (line 108) -* MMIX assembler directive PREFIX: MMIX-Pseudos. (line 120) -* MMIX assembler directive TETRA: MMIX-Pseudos. (line 108) -* MMIX assembler directive WYDE: MMIX-Pseudos. (line 108) +* MMIX assembler directive LOCAL: MMIX-Pseudos. (line 29) +* MMIX assembler directive OCTA: MMIX-Pseudos. (line 113) +* MMIX assembler directive PREFIX: MMIX-Pseudos. (line 125) +* MMIX assembler directive TETRA: MMIX-Pseudos. (line 113) +* MMIX assembler directive WYDE: MMIX-Pseudos. (line 113) * MMIX assembler directives: MMIX-Pseudos. (line 6) * MMIX line comment characters: MMIX-Chars. (line 6) * MMIX options: MMIX-Opts. (line 6) -* MMIX pseudo-op BSPEC: MMIX-Pseudos. (line 131) -* MMIX pseudo-op BYTE: MMIX-Pseudos. (line 97) -* MMIX pseudo-op ESPEC: MMIX-Pseudos. (line 131) -* MMIX pseudo-op GREG: MMIX-Pseudos. (line 50) -* MMIX pseudo-op IS: MMIX-Pseudos. (line 42) +* MMIX pseudo-op BSPEC: MMIX-Pseudos. (line 137) +* MMIX pseudo-op BYTE: MMIX-Pseudos. (line 101) +* MMIX pseudo-op ESPEC: MMIX-Pseudos. (line 137) +* MMIX pseudo-op GREG: MMIX-Pseudos. (line 53) +* MMIX pseudo-op IS: MMIX-Pseudos. (line 44) * MMIX pseudo-op LOC: MMIX-Pseudos. (line 7) -* MMIX pseudo-op LOCAL: MMIX-Pseudos. (line 28) -* MMIX pseudo-op OCTA: MMIX-Pseudos. (line 108) -* MMIX pseudo-op PREFIX: MMIX-Pseudos. (line 120) -* MMIX pseudo-op TETRA: MMIX-Pseudos. (line 108) -* MMIX pseudo-op WYDE: MMIX-Pseudos. (line 108) +* MMIX pseudo-op LOCAL: MMIX-Pseudos. (line 29) +* MMIX pseudo-op OCTA: MMIX-Pseudos. (line 113) +* MMIX pseudo-op PREFIX: MMIX-Pseudos. (line 125) +* MMIX pseudo-op TETRA: MMIX-Pseudos. (line 113) +* MMIX pseudo-op WYDE: MMIX-Pseudos. (line 113) * MMIX pseudo-ops: MMIX-Pseudos. (line 6) * MMIX register names: MMIX-Regs. (line 6) * MMIX support: MMIX-Dependent. (line 6) * mmixal differences: MMIX-mmixal. (line 6) -* mmregs directive, TIC54X: TIC54X-Directives. (line 169) -* mmsg directive, TIC54X: TIC54X-Directives. (line 77) +* 'mmregs' directive, TIC54X: TIC54X-Directives. (line 167) +* 'mmsg' directive, TIC54X: TIC54X-Directives. (line 75) * MMX, i386: i386-SIMD. (line 6) * MMX, x86-64: i386-SIMD. (line 6) -* mnemonic compatibility, i386: i386-Mnemonics. (line 62) -* mnemonic suffixes, i386: i386-Variations. (line 29) -* mnemonic suffixes, x86-64: i386-Variations. (line 29) +* mnemonic compatibility, i386: i386-Mnemonics. (line 61) +* mnemonic suffixes, i386: i386-Variations. (line 28) +* mnemonic suffixes, x86-64: i386-Variations. (line 28) * mnemonics for opcodes, VAX: VAX-opcodes. (line 6) * mnemonics, AVR: AVR Opcodes. (line 6) * mnemonics, D10V: D10V-Opcodes. (line 6) @@ -24135,16 +23951,16 @@ AS Index * mnemonics, SH: SH Opcodes. (line 6) * mnemonics, SH64: SH64 Opcodes. (line 6) * mnemonics, Z8000: Z8000 Opcodes. (line 6) -* mnolist directive, TIC54X: TIC54X-Directives. (line 164) +* 'mnolist' directive, TIC54X: TIC54X-Directives. (line 162) * modifiers, M32C: M32C-Modifiers. (line 6) * Motorola syntax for the 680x0: M68K-Moto-Syntax. (line 6) -* MOVI instructions, relaxation: Xtensa Immediate Relaxation. +* 'MOVI' instructions, relaxation: Xtensa Immediate Relaxation. (line 12) * MOVN, MOVZ and MOVK group relocations, AArch64: AArch64-Relocations. (line 6) * MOVW and MOVT relocations, ARM: ARM-Relocations. (line 21) * MRI compatibility mode: M. (line 6) -* mri directive: MRI. (line 6) +* 'mri' directive: MRI. (line 6) * MRI mode, temporarily: MRI. (line 6) * MSP 430 floating point (IEEE): MSP430 Floating Point. (line 6) @@ -24160,8 +23976,8 @@ AS Index * MSP 430 register names: MSP430-Regs. (line 6) * MSP 430 support: MSP430-Dependent. (line 6) * MSP430 Assembler Extensions: MSP430-Ext. (line 6) -* mul instruction, i386: i386-Notes. (line 6) -* mul instruction, x86-64: i386-Notes. (line 6) +* 'mul' instruction, i386: i386-Notes. (line 6) +* 'mul' instruction, x86-64: i386-Notes. (line 6) * N32K support: NS32K-Dependent. (line 6) * name: Z8000 Directives. (line 18) * named section: Section. (line 6) @@ -24169,8 +23985,8 @@ AS Index * names, symbol: Symbol Names. (line 6) * naming object file: o. (line 6) * new page, in listings: Eject. (line 6) -* newblock directive, TIC54X: TIC54X-Directives. (line 175) -* newline (\n): Strings. (line 21) +* 'newblock' directive, TIC54X: TIC54X-Directives. (line 173) +* newline ('\n'): Strings. (line 21) * newline, required at file end: Statements. (line 14) * Nios II line comment character: Nios II Chars. (line 6) * Nios II line separator character: Nios II Chars. (line 6) @@ -24180,36 +23996,36 @@ AS Index * Nios II options: Nios II Options. (line 6) * Nios II support: NiosII-Dependent. (line 6) * Nios support: NiosII-Dependent. (line 6) -* no-absolute-literals directive: Absolute Literals Directive. +* 'no-absolute-literals' directive: Absolute Literals Directive. (line 6) -* no-longcalls directive: Longcalls Directive. (line 6) -* no-relax command line option, Nios II: Nios II Options. (line 20) -* no-schedule directive: Schedule Directive. (line 6) -* no-transform directive: Transform Directive. (line 6) -* nolist directive: Nolist. (line 6) -* nolist directive, TIC54X: TIC54X-Directives. (line 131) -* NOP pseudo op, ARM: ARM Opcodes. (line 9) +* 'no-longcalls' directive: Longcalls Directive. (line 6) +* 'no-relax' command line option, Nios II: Nios II Options. (line 19) +* 'no-schedule' directive: Schedule Directive. (line 6) +* 'no-transform' directive: Transform Directive. (line 6) +* 'nolist' directive: Nolist. (line 6) +* 'nolist' directive, TIC54X: TIC54X-Directives. (line 129) +* 'NOP' pseudo op, ARM: ARM Opcodes. (line 9) * notes for Alpha: Alpha Notes. (line 6) * NS32K line comment character: NS32K-Chars. (line 6) * NS32K line separator: NS32K-Chars. (line 18) * null-terminated strings: Asciz. (line 6) * number constants: Numbers. (line 6) -* number of macros executed: Macro. (line 143) +* number of macros executed: Macro. (line 142) * numbered subsections: Sub-Sections. (line 6) * numbers, 16-bit: hword. (line 6) * numeric values: Expressions. (line 6) -* nword directive, SPARC: Sparc-Directives. (line 20) +* 'nword' directive, SPARC: Sparc-Directives. (line 20) * object attributes: Object Attributes. (line 6) * object file: Object. (line 6) * object file format: Object Formats. (line 6) * object file name: o. (line 6) * object file, after errors: Z. (line 6) * obsolescent directives: Deprecated. (line 6) -* octa directive: Octa. (line 6) -* octal character code (\DDD): Strings. (line 30) +* 'octa' directive: Octa. (line 6) +* octal character code ('\DDD'): Strings. (line 30) * octal integers: Integers. (line 9) -* offset directive: Offset. (line 6) -* offset directive, V850: V850 Directives. (line 6) +* 'offset' directive: Offset. (line 6) +* 'offset' directive, V850: V850 Directives. (line 6) * opcode mnemonics, VAX: VAX-opcodes. (line 6) * opcode names, TILE-Gx: TILE-Gx Opcodes. (line 6) * opcode names, TILEPro: TILEPro Opcodes. (line 6) @@ -24239,12 +24055,12 @@ AS Index * operator precedence: Infix Ops. (line 11) * operators, in expressions: Operators. (line 6) * operators, permitted arguments: Infix Ops. (line 6) -* optimization, D10V: Overview. (line 490) -* optimization, D30V: Overview. (line 495) +* optimization, D10V: Overview. (line 493) +* optimization, D30V: Overview. (line 498) * optimizations: Xtensa Optimizations. (line 6) -* option directive, ARC: ARC Directives. (line 159) -* option directive, TIC54X: TIC54X-Directives. (line 179) +* 'option' directive, ARC: ARC Directives. (line 150) +* 'option' directive, TIC54X: TIC54X-Directives. (line 177) * option summary: Overview. (line 6) * options for AArch64 (none): AArch64 Options. (line 6) * options for Alpha: Alpha Options. (line 6) @@ -24290,18 +24106,18 @@ AS Index * options, TIC54X: TIC54X-Opts. (line 6) * options, XGATE: XGATE-Opts. (line 6) * options, Z8000: Z8000 Options. (line 6) -* org directive: Org. (line 6) -* other attribute, of a.out symbol: Symbol Other. (line 6) +* 'org' directive: Org. (line 6) +* other attribute, of 'a.out' symbol: Symbol Other. (line 6) * output file: Object. (line 6) -* p2align directive: P2align. (line 6) -* p2alignl directive: P2align. (line 28) -* p2alignw directive: P2align. (line 28) +* 'p2align' directive: P2align. (line 6) +* 'p2alignl' directive: P2align. (line 28) +* 'p2alignw' directive: P2align. (line 28) * padding the location counter: Align. (line 6) * padding the location counter given a power of two: P2align. (line 6) * padding the location counter given number of bytes: Balign. (line 6) * page, in listings: Eject. (line 6) * paper size, for listings: Psize. (line 6) -* paths for .include: I. (line 6) +* paths for '.include': I. (line 6) * patterns, writing in memory: Fill. (line 6) * PDP-11 comments: PDP-11-Syntax. (line 16) * PDP-11 floating-point register syntax: PDP-11-Syntax. (line 13) @@ -24310,16 +24126,16 @@ AS Index * PDP-11 line separator: PDP-11-Syntax. (line 19) * PDP-11 support: PDP-11-Dependent. (line 6) * PDP-11 syntax: PDP-11-Syntax. (line 6) -* PIC code generation for ARM: ARM Options. (line 169) +* PIC code generation for ARM: ARM Options. (line 170) * PIC code generation for M32R: M32R-Opts. (line 42) -* PIC selection, MIPS: MIPS Opts. (line 21) -* PJ endianness: Overview. (line 630) +* PIC selection, MIPS: MIPS Options. (line 21) +* PJ endianness: Overview. (line 627) * PJ line comment character: PJ-Chars. (line 6) * PJ line separator: PJ-Chars. (line 14) * PJ options: PJ Options. (line 6) * PJ support: PJ-Dependent. (line 6) -* plus, permitted arguments: Infix Ops. (line 44) -* popsection directive: PopSection. (line 6) +* plus, permitted arguments: Infix Ops. (line 45) +* 'popsection' directive: PopSection. (line 6) * Position-independent code, CRIS: CRIS-Opts. (line 27) * Position-independent code, symbols in, CRIS: CRIS-Pic. (line 6) * PowerPC architectures: PowerPC-Opts. (line 6) @@ -24334,28 +24150,28 @@ AS Index * prefixes, i386: i386-Prefixes. (line 6) * preprocessing: Preprocessing. (line 6) * preprocessing, turning on and off: Preprocessing. (line 26) -* previous directive: Previous. (line 6) +* 'previous' directive: Previous. (line 6) * primary attributes, COFF symbols: COFF Symbols. (line 13) -* print directive: Print. (line 6) -* proc directive, SPARC: Sparc-Directives. (line 25) -* profiler directive, MSP 430: MSP430 Directives. (line 22) +* 'print' directive: Print. (line 6) +* 'proc' directive, SPARC: Sparc-Directives. (line 25) +* 'profiler' directive, MSP 430: MSP430 Directives. (line 26) * profiling capability for MSP 430: MSP430 Profiling Capability. (line 6) -* protected directive: Protected. (line 6) -* pseudo-op .arch, CRIS: CRIS-Pseudos. (line 45) +* 'protected' directive: Protected. (line 6) +* pseudo-op .arch, CRIS: CRIS-Pseudos. (line 50) * pseudo-op .dword, CRIS: CRIS-Pseudos. (line 12) -* pseudo-op .syntax, CRIS: CRIS-Pseudos. (line 17) -* pseudo-op BSPEC, MMIX: MMIX-Pseudos. (line 131) -* pseudo-op BYTE, MMIX: MMIX-Pseudos. (line 97) -* pseudo-op ESPEC, MMIX: MMIX-Pseudos. (line 131) -* pseudo-op GREG, MMIX: MMIX-Pseudos. (line 50) -* pseudo-op IS, MMIX: MMIX-Pseudos. (line 42) +* pseudo-op .syntax, CRIS: CRIS-Pseudos. (line 18) +* pseudo-op BSPEC, MMIX: MMIX-Pseudos. (line 137) +* pseudo-op BYTE, MMIX: MMIX-Pseudos. (line 101) +* pseudo-op ESPEC, MMIX: MMIX-Pseudos. (line 137) +* pseudo-op GREG, MMIX: MMIX-Pseudos. (line 53) +* pseudo-op IS, MMIX: MMIX-Pseudos. (line 44) * pseudo-op LOC, MMIX: MMIX-Pseudos. (line 7) -* pseudo-op LOCAL, MMIX: MMIX-Pseudos. (line 28) -* pseudo-op OCTA, MMIX: MMIX-Pseudos. (line 108) -* pseudo-op PREFIX, MMIX: MMIX-Pseudos. (line 120) -* pseudo-op TETRA, MMIX: MMIX-Pseudos. (line 108) -* pseudo-op WYDE, MMIX: MMIX-Pseudos. (line 108) +* pseudo-op LOCAL, MMIX: MMIX-Pseudos. (line 29) +* pseudo-op OCTA, MMIX: MMIX-Pseudos. (line 113) +* pseudo-op PREFIX, MMIX: MMIX-Pseudos. (line 125) +* pseudo-op TETRA, MMIX: MMIX-Pseudos. (line 113) +* pseudo-op WYDE, MMIX: MMIX-Pseudos. (line 113) * pseudo-opcodes for XStormy16: XStormy16 Opcodes. (line 6) * pseudo-opcodes, M680x0: M68K-Branch. (line 6) * pseudo-opcodes, M68HC11: M68HC11-Branch. (line 6) @@ -24363,19 +24179,19 @@ AS Index * pseudo-ops, CRIS: CRIS-Pseudos. (line 6) * pseudo-ops, machine independent: Pseudo Ops. (line 6) * pseudo-ops, MMIX: MMIX-Pseudos. (line 6) -* psize directive: Psize. (line 6) +* 'psize' directive: Psize. (line 6) * PSR bits: IA-64-Bits. (line 6) -* pstring directive, TIC54X: TIC54X-Directives. (line 208) -* psw register, V850: V850-Regs. (line 116) -* purgem directive: Purgem. (line 6) +* 'pstring' directive, TIC54X: TIC54X-Directives. (line 206) +* 'psw' register, V850: V850-Regs. (line 80) +* 'purgem' directive: Purgem. (line 6) * purpose of GNU assembler: GNU Assembler. (line 12) -* pushsection directive: PushSection. (line 6) -* quad directive: Quad. (line 6) -* quad directive, i386: i386-Float. (line 21) -* quad directive, x86-64: i386-Float. (line 21) +* 'pushsection' directive: PushSection. (line 6) +* 'quad' directive: Quad. (line 6) +* 'quad' directive, i386: i386-Float. (line 21) +* 'quad' directive, x86-64: i386-Float. (line 21) * real-mode code, i386: i386-16bit. (line 6) -* ref directive, TIC54X: TIC54X-Directives. (line 103) -* register directive, SPARC: Sparc-Directives. (line 29) +* 'ref' directive, TIC54X: TIC54X-Directives. (line 101) +* 'register' directive, SPARC: Sparc-Directives. (line 29) * register names, AArch64: AArch64-Regs. (line 6) * register names, Alpha: Alpha-Regs. (line 6) * register names, ARC: ARC-Regs. (line 6) @@ -24406,11 +24222,11 @@ AS Index * registers, TIC54X memory-mapped: TIC54X-MMRegs. (line 6) * registers, x86-64: i386-Regs. (line 6) * registers, Z8000: Z8000-Regs. (line 6) -* relax-all command line option, Nios II: Nios II Options. (line 13) -* relax-section command line option, Nios II: Nios II Options. +* 'relax-all' command line option, Nios II: Nios II Options. (line 13) +* 'relax-section' command line option, Nios II: Nios II Options. (line 6) * relaxation: Xtensa Relaxation. (line 6) -* relaxation of ADDI instructions: Xtensa Immediate Relaxation. +* relaxation of 'ADDI' instructions: Xtensa Immediate Relaxation. (line 43) * relaxation of branch instructions: Xtensa Branch Relaxation. (line 6) @@ -24418,17 +24234,17 @@ AS Index (line 6) * relaxation of immediate fields: Xtensa Immediate Relaxation. (line 6) -* relaxation of L16SI instructions: Xtensa Immediate Relaxation. +* relaxation of 'L16SI' instructions: Xtensa Immediate Relaxation. (line 23) -* relaxation of L16UI instructions: Xtensa Immediate Relaxation. +* relaxation of 'L16UI' instructions: Xtensa Immediate Relaxation. (line 23) -* relaxation of L32I instructions: Xtensa Immediate Relaxation. +* relaxation of 'L32I' instructions: Xtensa Immediate Relaxation. (line 23) -* relaxation of L8UI instructions: Xtensa Immediate Relaxation. +* relaxation of 'L8UI' instructions: Xtensa Immediate Relaxation. (line 23) -* relaxation of MOVI instructions: Xtensa Immediate Relaxation. +* relaxation of 'MOVI' instructions: Xtensa Immediate Relaxation. (line 12) -* reloc directive: Reloc. (line 6) +* 'reloc' directive: Reloc. (line 6) * relocation: Sections. (line 6) * relocation example: Ld Sections. (line 40) * relocations, AArch64: AArch64-Relocations. (line 6) @@ -24436,10 +24252,10 @@ AS Index * relocations, Sparc: Sparc-Relocs. (line 6) * repeat prefixes, i386: i386-Prefixes. (line 44) * reporting bugs in assembler: Reporting Bugs. (line 6) -* rept directive: Rept. (line 6) -* reserve directive, SPARC: Sparc-Directives. (line 39) -* return instructions, i386: i386-Variations. (line 41) -* return instructions, x86-64: i386-Variations. (line 41) +* 'rept' directive: Rept. (line 6) +* 'reserve' directive, SPARC: Sparc-Directives. (line 39) +* return instructions, i386: i386-Variations. (line 40) +* return instructions, x86-64: i386-Variations. (line 40) * REX prefixes, i386: i386-Prefixes. (line 46) * RL78 assembler directives: RL78-Directives. (line 6) * RL78 line comment character: RL78-Chars. (line 6) @@ -24447,7 +24263,7 @@ AS Index * RL78 modifiers: RL78-Modifiers. (line 6) * RL78 options: RL78-Opts. (line 6) * RL78 support: RL78-Dependent. (line 6) -* rsect: Z8000 Directives. (line 52) +* rsect: Z8000 Directives. (line 51) * RX assembler directive .3byte: RX-Directives. (line 9) * RX assembler directive .fetchalign: RX-Directives. (line 13) * RX assembler directives: RX-Directives. (line 6) @@ -24474,48 +24290,46 @@ AS Index * s390 options: s390 Options. (line 6) * s390 register naming: s390 Register. (line 6) * s390 support: S/390-Dependent. (line 6) -* sblock directive, TIC54X: TIC54X-Directives. (line 182) -* sbttl directive: Sbttl. (line 6) -* schedule directive: Schedule Directive. (line 6) -* scl directive: Scl. (line 6) +* 'sblock' directive, TIC54X: TIC54X-Directives. (line 180) +* 'sbttl' directive: Sbttl. (line 6) +* 'schedule' directive: Schedule Directive. (line 6) +* 'scl' directive: Scl. (line 6) * SCORE architectures: SCORE-Opts. (line 6) * SCORE directives: SCORE-Pseudo. (line 6) * SCORE line comment character: SCORE-Chars. (line 6) * SCORE line separator: SCORE-Chars. (line 14) * SCORE options: SCORE-Opts. (line 6) * SCORE processor: SCORE-Dependent. (line 6) -* sdaoff pseudo-op, V850: V850 Opcodes. (line 65) -* search path for .include: I. (line 6) -* secondary directive: Secondary. (line 6) -* sect directive, MSP 430: MSP430 Directives. (line 18) -* sect directive, TIC54X: TIC54X-Directives. (line 188) -* section directive (COFF version): Section. (line 16) -* section directive (ELF version): Section. (line 76) -* section directive, V850: V850 Directives. (line 9) +* 'sdaoff' pseudo-op, V850: V850 Opcodes. (line 65) +* search path for '.include': I. (line 6) +* 'sect' directive, TIC54X: TIC54X-Directives. (line 186) +* 'section' directive (COFF version): Section. (line 16) +* 'section' directive (ELF version): Section. (line 66) +* 'section' directive, V850: V850 Directives. (line 9) * section override prefixes, i386: i386-Prefixes. (line 23) -* Section Stack <1>: SubSection. (line 6) -* Section Stack <2>: Section. (line 71) -* Section Stack <3>: PushSection. (line 6) -* Section Stack <4>: Previous. (line 6) * Section Stack: PopSection. (line 6) -* section-relative addressing: Secs Background. (line 68) +* Section Stack <1>: Previous. (line 6) +* Section Stack <2>: PushSection. (line 6) +* Section Stack <3>: Section. (line 61) +* Section Stack <4>: SubSection. (line 6) +* section-relative addressing: Secs Background. (line 65) * sections: Sections. (line 6) * sections in messages, internal: As Sections. (line 6) -* sections, i386: i386-Variations. (line 47) +* sections, i386: i386-Variations. (line 46) * sections, named: Ld Sections. (line 8) -* sections, x86-64: i386-Variations. (line 47) -* seg directive, SPARC: Sparc-Directives. (line 44) +* sections, x86-64: i386-Variations. (line 46) +* 'seg' directive, SPARC: Sparc-Directives. (line 44) * segm: Z8000 Directives. (line 10) -* set at directive, Nios II: Nios II Directives. (line 35) -* set break directive, Nios II: Nios II Directives. (line 43) -* set directive: Set. (line 6) -* set directive, Nios II: Nios II Directives. (line 57) -* set directive, TIC54X: TIC54X-Directives. (line 191) -* set noat directive, Nios II: Nios II Directives. (line 31) -* set nobreak directive, Nios II: Nios II Directives. (line 39) -* set norelax directive, Nios II: Nios II Directives. (line 46) -* set relaxall directive, Nios II: Nios II Directives. (line 53) -* set relaxsection directive, Nios II: Nios II Directives. (line 49) +* 'set at' directive, Nios II: Nios II Directives. (line 35) +* 'set break' directive, Nios II: Nios II Directives. (line 43) +* 'set' directive: Set. (line 6) +* 'set' directive, Nios II: Nios II Directives. (line 57) +* 'set' directive, TIC54X: TIC54X-Directives. (line 189) +* 'set noat' directive, Nios II: Nios II Directives. (line 31) +* 'set nobreak' directive, Nios II: Nios II Directives. (line 39) +* 'set norelax' directive, Nios II: Nios II Directives. (line 46) +* 'set relaxall' directive, Nios II: Nios II Directives. (line 53) +* 'set relaxsection' directive, Nios II: Nios II Directives. (line 49) * SH addressing modes: SH-Addressing. (line 6) * SH floating point (IEEE): SH Floating Point. (line 6) * SH line comment character: SH-Chars. (line 6) @@ -24525,7 +24339,7 @@ AS Index * SH options: SH Options. (line 6) * SH registers: SH-Regs. (line 6) * SH support: SH-Dependent. (line 6) -* SH64 ABI options: SH64 Options. (line 29) +* SH64 ABI options: SH64 Options. (line 25) * SH64 addressing modes: SH64-Addressing. (line 6) * SH64 ISA options: SH64 Options. (line 6) * SH64 line comment character: SH64-Chars. (line 6) @@ -24535,45 +24349,45 @@ AS Index * SH64 options: SH64 Options. (line 6) * SH64 registers: SH64-Regs. (line 6) * SH64 support: SH64-Dependent. (line 6) -* shigh directive, M32R: M32R-Directives. (line 26) -* short directive: Short. (line 6) -* short directive, ARC: ARC Directives. (line 168) -* short directive, TIC54X: TIC54X-Directives. (line 111) +* 'shigh' directive, M32R: M32R-Directives. (line 26) +* 'short' directive: Short. (line 6) +* 'short' directive, ARC: ARC Directives. (line 159) +* 'short' directive, TIC54X: TIC54X-Directives. (line 109) * SIMD, i386: i386-SIMD. (line 6) * SIMD, x86-64: i386-SIMD. (line 6) * single character constant: Chars. (line 6) -* single directive: Single. (line 6) -* single directive, i386: i386-Float. (line 14) -* single directive, x86-64: i386-Float. (line 14) +* 'single' directive: Single. (line 6) +* 'single' directive, i386: i386-Float. (line 14) +* 'single' directive, x86-64: i386-Float. (line 14) * single quote, Z80: Z80-Chars. (line 20) * sixteen bit integers: hword. (line 6) * sixteen byte integer: Octa. (line 6) -* size directive (COFF version): Size. (line 11) -* size directive (ELF version): Size. (line 19) +* 'size' directive (COFF version): Size. (line 11) +* 'size' directive (ELF version): Size. (line 19) * size modifiers, D10V: D10V-Size. (line 6) * size modifiers, D30V: D30V-Size. (line 6) * size modifiers, M680x0: M68K-Syntax. (line 8) * size prefixes, i386: i386-Prefixes. (line 27) -* size suffixes, H8/300: H8/300 Opcodes. (line 163) +* size suffixes, H8/300: H8/300 Opcodes. (line 160) * size, translations, Sparc: Sparc-Size-Translations. (line 6) -* sizes operands, i386: i386-Variations. (line 29) -* sizes operands, x86-64: i386-Variations. (line 29) -* skip directive: Skip. (line 6) -* skip directive, M680x0: M68K-Directives. (line 19) -* skip directive, SPARC: Sparc-Directives. (line 48) -* sleb128 directive: Sleb128. (line 6) -* small objects, MIPS ECOFF: MIPS Object. (line 11) -* SmartMIPS instruction generation override: MIPS ASE instruction generation overrides. +* sizes operands, i386: i386-Variations. (line 28) +* sizes operands, x86-64: i386-Variations. (line 28) +* 'skip' directive: Skip. (line 6) +* 'skip' directive, M680x0: M68K-Directives. (line 19) +* 'skip' directive, SPARC: Sparc-Directives. (line 48) +* 'sleb128' directive: Sleb128. (line 6) +* small data, MIPS: MIPS Small Data. (line 6) +* SmartMIPS instruction generation override: MIPS ASE Instruction Generation Overrides. (line 11) * SOM symbol attributes: SOM Symbols. (line 6) * source program: Input Files. (line 6) -* source, destination operands; i386: i386-Variations. (line 22) -* source, destination operands; x86-64: i386-Variations. (line 22) +* source, destination operands; i386: i386-Variations. (line 21) +* source, destination operands; x86-64: i386-Variations. (line 21) * sp register: Xtensa Registers. (line 6) -* sp register, V850: V850-Regs. (line 14) -* space directive: Space. (line 6) -* space directive, TIC54X: TIC54X-Directives. (line 196) +* 'sp' register, V850: V850-Regs. (line 12) +* 'space' directive: Space. (line 6) +* 'space' directive, TIC54X: TIC54X-Directives. (line 194) * space used, maximum for assembly: statistics. (line 6) * SPARC architectures: Sparc-Opts. (line 6) * Sparc constants: Sparc-Constants. (line 6) @@ -24591,12 +24405,12 @@ AS Index * SPARC syntax: Sparc-Aligned-Data. (line 21) * special characters, M680x0: M68K-Chars. (line 6) * special purpose registers, MSP 430: MSP430-Regs. (line 11) -* sslist directive, TIC54X: TIC54X-Directives. (line 203) -* ssnolist directive, TIC54X: TIC54X-Directives. (line 203) -* stabd directive: Stab. (line 38) -* stabn directive: Stab. (line 48) -* stabs directive: Stab. (line 51) -* stabX directives: Stab. (line 6) +* 'sslist' directive, TIC54X: TIC54X-Directives. (line 201) +* 'ssnolist' directive, TIC54X: TIC54X-Directives. (line 201) +* 'stabd' directive: Stab. (line 38) +* 'stabn' directive: Stab. (line 49) +* 'stabs' directive: Stab. (line 52) +* 'stabX' directives: Stab. (line 6) * standard assembler sections: Secs Background. (line 27) * standard input, as input file: Command Line. (line 10) * statement separator character: Statements. (line 6) @@ -24605,7 +24419,7 @@ AS Index * statement separator, ARC: ARC-Chars. (line 12) * statement separator, ARM: ARM-Chars. (line 14) * statement separator, AVR: AVR-Chars. (line 14) -* statement separator, CR16: CR16-Chars. (line 13) +* statement separator, CR16: CR16-Chars. (line 12) * statement separator, Epiphany: Epiphany-Chars. (line 14) * statement separator, H8/300: H8/300-Chars. (line 8) * statement separator, i386: i386-Chars. (line 18) @@ -24615,7 +24429,7 @@ AS Index * statement separator, IP2K: IP2K-Chars. (line 14) * statement separator, LM32: LM32-Chars. (line 12) * statement separator, M32C: M32C-Chars. (line 14) -* statement separator, M68HC11: M68HC11-Syntax. (line 27) +* statement separator, M68HC11: M68HC11-Syntax. (line 26) * statement separator, Meta: Meta-Chars. (line 8) * statement separator, MicroBlaze: MicroBlaze-Chars. (line 14) * statement separator, MIPS: MIPS-Chars. (line 14) @@ -24634,7 +24448,7 @@ AS Index * statement separator, TIC6X: TIC6X Syntax. (line 13) * statement separator, V850: V850-Chars. (line 13) * statement separator, VAX: VAX-Chars. (line 14) -* statement separator, XGATE: XGATE-Syntax. (line 26) +* statement separator, XGATE: XGATE-Syntax. (line 25) * statement separator, XStormy16: XStormy16-Chars. (line 14) * statement separator, Z80: Z80-Chars. (line 13) * statement separator, Z8000: Z8000-Chars. (line 13) @@ -24642,53 +24456,53 @@ AS Index * statistics, about assembly: statistics. (line 6) * stopping the assembly: Abort. (line 6) * string constants: Strings. (line 6) -* string directive: String. (line 8) -* string directive on HPPA: HPPA Directives. (line 137) -* string directive, TIC54X: TIC54X-Directives. (line 208) +* 'string' directive: String. (line 8) +* 'string' directive on HPPA: HPPA Directives. (line 137) +* 'string' directive, TIC54X: TIC54X-Directives. (line 206) * string literals: Ascii. (line 6) * string, copying to object file: String. (line 8) -* string16 directive: String. (line 8) +* 'string16' directive: String. (line 8) * string16, copying to object file: String. (line 8) -* string32 directive: String. (line 8) +* 'string32' directive: String. (line 8) * string32, copying to object file: String. (line 8) -* string64 directive: String. (line 8) +* 'string64' directive: String. (line 8) * string64, copying to object file: String. (line 8) -* string8 directive: String. (line 8) +* 'string8' directive: String. (line 8) * string8, copying to object file: String. (line 8) -* struct directive: Struct. (line 6) -* struct directive, TIC54X: TIC54X-Directives. (line 216) +* 'struct' directive: Struct. (line 6) +* 'struct' directive, TIC54X: TIC54X-Directives. (line 214) * structure debugging, COFF: Tag. (line 6) * sub-instruction ordering, D10V: D10V-Chars. (line 14) * sub-instruction ordering, D30V: D30V-Chars. (line 14) * sub-instructions, D10V: D10V-Subs. (line 6) * sub-instructions, D30V: D30V-Subs. (line 6) * subexpressions: Arguments. (line 24) -* subsection directive: SubSection. (line 6) +* 'subsection' directive: SubSection. (line 6) * subsym builtins, TIC54X: TIC54X-Macros. (line 16) * subtitles for listings: Sbttl. (line 6) -* subtraction, permitted arguments: Infix Ops. (line 49) +* subtraction, permitted arguments: Infix Ops. (line 50) * summary of options: Overview. (line 6) * support: HPPA-Dependent. (line 6) * supporting files, including: Include. (line 6) * suppressing warnings: W. (line 11) * sval: Z8000 Directives. (line 33) * symbol attributes: Symbol Attributes. (line 6) -* symbol attributes, a.out: a.out Symbols. (line 6) +* symbol attributes, 'a.out': a.out Symbols. (line 6) * symbol attributes, COFF: COFF Symbols. (line 6) * symbol attributes, SOM: SOM Symbols. (line 6) * symbol descriptor, COFF: Desc. (line 6) -* symbol modifiers <1>: M68HC11-Modifiers. (line 12) -* symbol modifiers <2>: M32C-Modifiers. (line 11) -* symbol modifiers <3>: LM32-Modifiers. (line 12) * symbol modifiers: AVR-Modifiers. (line 12) +* symbol modifiers <1>: LM32-Modifiers. (line 12) +* symbol modifiers <2>: M32C-Modifiers. (line 11) +* symbol modifiers <3>: M68HC11-Modifiers. (line 12) * symbol modifiers, TILE-Gx: TILE-Gx Modifiers. (line 6) * symbol modifiers, TILEPro: TILEPro Modifiers. (line 6) * symbol names: Symbol Names. (line 6) -* symbol names, $ in <1>: SH64-Chars. (line 15) -* symbol names, $ in <2>: SH-Chars. (line 15) -* symbol names, $ in <3>: Meta-Chars. (line 10) -* symbol names, $ in <4>: D30V-Chars. (line 70) -* symbol names, $ in: D10V-Chars. (line 53) +* symbol names, '$' in: D10V-Chars. (line 46) +* symbol names, '$' in <1>: D30V-Chars. (line 70) +* symbol names, '$' in <2>: Meta-Chars. (line 10) +* symbol names, '$' in <3>: SH-Chars. (line 15) +* symbol names, '$' in <4>: SH64-Chars. (line 15) * symbol names, local: Symbol Names. (line 27) * symbol names, temporary: Symbol Names. (line 40) * symbol storage class (COFF): Scl. (line 6) @@ -24709,7 +24523,7 @@ AS Index * Symbols, built-in, CRIS: CRIS-Symbols. (line 6) * Symbols, CRIS, built-in: CRIS-Symbols. (line 6) * symbols, local common: Lcomm. (line 6) -* symver directive: Symver. (line 6) +* 'symver' directive: Symver. (line 6) * syntax compatibility, i386: i386-Variations. (line 6) * syntax compatibility, x86-64: i386-Variations. (line 6) * syntax, AVR: AVR-Modifiers. (line 6) @@ -24718,32 +24532,33 @@ AS Index * syntax, D30V: D30V-Syntax. (line 6) * syntax, LM32: LM32-Modifiers. (line 6) * syntax, M680x0: M68K-Syntax. (line 8) -* syntax, M68HC11 <1>: M68HC11-Modifiers. (line 6) * syntax, M68HC11: M68HC11-Syntax. (line 6) +* syntax, M68HC11 <1>: M68HC11-Modifiers. (line 6) * syntax, machine-independent: Syntax. (line 6) * syntax, RL78: RL78-Modifiers. (line 6) * syntax, RX: RX-Modifiers. (line 6) -* syntax, SPARC: Sparc-Aligned-Data. (line 21) +* syntax, SPARC: Sparc-Aligned-Data. (line 20) * syntax, TILE-Gx: TILE-Gx Syntax. (line 6) * syntax, TILEPro: TILEPro Syntax. (line 6) * syntax, XGATE: XGATE-Syntax. (line 6) * syntax, Xtensa assembler: Xtensa Syntax. (line 6) -* sysproc directive, i960: Directives-i960. (line 37) -* tab (\t): Strings. (line 27) -* tab directive, TIC54X: TIC54X-Directives. (line 247) -* tag directive: Tag. (line 6) -* tag directive, TIC54X: TIC54X-Directives. (line 216) +* 'sysproc' directive, i960: Directives-i960. (line 37) +* tab ('\t'): Strings. (line 27) +* 'tab' directive, TIC54X: TIC54X-Directives. (line 245) +* 'tag' directive: Tag. (line 6) +* 'tag' directive, TIC54X: TIC54X-Directives. (line 214) +* 'tag' directive, TIC54X <1>: TIC54X-Directives. (line 248) * TBM, i386: i386-TBM. (line 6) * TBM, x86-64: i386-TBM. (line 6) -* tdaoff pseudo-op, V850: V850 Opcodes. (line 81) +* 'tdaoff' pseudo-op, V850: V850 Opcodes. (line 81) * temporary symbol names: Symbol Names. (line 40) * text and data sections, joining: R. (line 6) -* text directive: Text. (line 6) +* 'text' directive: Text. (line 6) * text section: Ld Sections. (line 9) -* tfloat directive, i386: i386-Float. (line 14) -* tfloat directive, x86-64: i386-Float. (line 14) -* Thumb support <1>: ARM-Dependent. (line 6) +* 'tfloat' directive, i386: i386-Float. (line 14) +* 'tfloat' directive, x86-64: i386-Float. (line 14) * Thumb support: AArch64-Dependent. (line 6) +* Thumb support <1>: ARM-Dependent. (line 6) * TIC54X builtin math functions: TIC54X-Builtins. (line 6) * TIC54X line comment character: TIC54X-Chars. (line 6) * TIC54X line separator: TIC54X-Chars. (line 17) @@ -24773,35 +24588,35 @@ AS Index * TILEPro support: TILEPro-Dependent. (line 6) * TILEPro syntax: TILEPro Syntax. (line 6) * time, total for assembly: statistics. (line 6) -* title directive: Title. (line 6) -* tls_gd directive, Nios II: Nios II Relocations. (line 38) -* tls_ie directive, Nios II: Nios II Relocations. (line 38) -* tls_ldm directive, Nios II: Nios II Relocations. (line 38) -* tls_ldo directive, Nios II: Nios II Relocations. (line 38) -* tls_le directive, Nios II: Nios II Relocations. (line 38) +* 'title' directive: Title. (line 6) +* 'tls_gd' directive, Nios II: Nios II Relocations. (line 38) +* 'tls_ie' directive, Nios II: Nios II Relocations. (line 38) +* 'tls_ldm' directive, Nios II: Nios II Relocations. (line 38) +* 'tls_ldo' directive, Nios II: Nios II Relocations. (line 38) +* 'tls_le' directive, Nios II: Nios II Relocations. (line 38) * TMS320C6X support: TIC6X-Dependent. (line 6) -* tp register, V850: V850-Regs. (line 20) -* transform directive: Transform Directive. (line 6) +* 'tp' register, V850: V850-Regs. (line 16) +* 'transform' directive: Transform Directive. (line 6) * trusted compiler: f. (line 6) * turning preprocessing on and off: Preprocessing. (line 26) -* type directive (COFF version): Type. (line 11) -* type directive (ELF version): Type. (line 22) +* 'type' directive (COFF version): Type. (line 11) +* 'type' directive (ELF version): Type. (line 22) * type of a symbol: Symbol Type. (line 6) -* ualong directive, SH: SH Directives. (line 6) -* uaquad directive, SH: SH Directives. (line 6) -* uaword directive, SH: SH Directives. (line 6) -* ubyte directive, TIC54X: TIC54X-Directives. (line 36) -* uchar directive, TIC54X: TIC54X-Directives. (line 36) -* uhalf directive, TIC54X: TIC54X-Directives. (line 111) -* uint directive, TIC54X: TIC54X-Directives. (line 111) -* uleb128 directive: Uleb128. (line 6) -* ulong directive, TIC54X: TIC54X-Directives. (line 135) +* 'ualong' directive, SH: SH Directives. (line 6) +* 'uaquad' directive, SH: SH Directives. (line 6) +* 'uaword' directive, SH: SH Directives. (line 6) +* 'ubyte' directive, TIC54X: TIC54X-Directives. (line 34) +* 'uchar' directive, TIC54X: TIC54X-Directives. (line 34) +* 'uhalf' directive, TIC54X: TIC54X-Directives. (line 109) +* 'uint' directive, TIC54X: TIC54X-Directives. (line 109) +* 'uleb128' directive: Uleb128. (line 6) +* 'ulong' directive, TIC54X: TIC54X-Directives. (line 133) * undefined section: Ld Sections. (line 36) -* union directive, TIC54X: TIC54X-Directives. (line 250) +* 'union' directive, TIC54X: TIC54X-Directives. (line 248) * unsegm: Z8000 Directives. (line 14) -* usect directive, TIC54X: TIC54X-Directives. (line 262) -* ushort directive, TIC54X: TIC54X-Directives. (line 111) -* uword directive, TIC54X: TIC54X-Directives. (line 111) +* 'usect' directive, TIC54X: TIC54X-Directives. (line 260) +* 'ushort' directive, TIC54X: TIC54X-Directives. (line 109) +* 'uword' directive, TIC54X: TIC54X-Directives. (line 109) * V850 command line options: V850 Options. (line 9) * V850 floating point (IEEE): V850 Floating Point. (line 6) * V850 line comment character: V850-Chars. (line 6) @@ -24811,10 +24626,10 @@ AS Index * V850 options (none): V850 Options. (line 6) * V850 register names: V850-Regs. (line 6) * V850 support: V850-Dependent. (line 6) -* val directive: Val. (line 6) +* 'val' directive: Val. (line 6) * value attribute, COFF: Val. (line 6) * value of a symbol: Symbol Value. (line 6) -* var directive, TIC54X: TIC54X-Directives. (line 272) +* 'var' directive, TIC54X: TIC54X-Directives. (line 270) * VAX bitfields not supported: VAX-no. (line 6) * VAX branch improvement: VAX-branch. (line 6) * VAX command-line options ignored: VAX-Opts. (line 6) @@ -24831,16 +24646,18 @@ AS Index * VAX support: Vax-Dependent. (line 6) * Vax-11 C compatibility: VAX-Opts. (line 42) * VAX/VMS options: VAX-Opts. (line 42) -* version directive: Version. (line 6) -* version directive, TIC54X: TIC54X-Directives. (line 276) +* 'version' directive: Version. (line 6) +* 'version' directive, TIC54X: TIC54X-Directives. (line 274) * version of assembler: v. (line 6) * versions of symbols: Symver. (line 6) -* visibility <1>: Protected. (line 6) -* visibility <2>: Internal. (line 6) +* Virtualization instruction generation override: MIPS ASE Instruction Generation Overrides. + (line 41) * visibility: Hidden. (line 6) +* visibility <1>: Internal. (line 6) +* visibility <2>: Protected. (line 6) * VMS (VAX) options: VAX-Opts. (line 42) -* vtable_entry directive: VTableEntry. (line 6) -* vtable_inherit directive: VTableInherit. (line 6) +* 'vtable_entry' directive: VTableEntry. (line 6) +* 'vtable_inherit' directive: VTableInherit. (line 6) * warning directive: Warning. (line 6) * warning for altered difference tables: K. (line 6) * warning messages: Errors. (line 6) @@ -24848,57 +24665,57 @@ AS Index * warnings, M32R: M32R-Warnings. (line 6) * warnings, suppressing: W. (line 11) * warnings, switching on: W. (line 19) -* weak directive: Weak. (line 6) -* weakref directive: Weakref. (line 6) +* 'weak' directive: Weak. (line 6) +* 'weakref' directive: Weakref. (line 6) * whitespace: Whitespace. (line 6) * whitespace, removed by preprocessor: Preprocessing. (line 7) -* wide floating point directives, VAX: VAX-directives. (line 10) -* width directive, TIC54X: TIC54X-Directives. (line 127) +* wide floating point directives, VAX: VAX-directives. (line 9) +* 'width' directive, TIC54X: TIC54X-Directives. (line 125) * Width of continuation lines of disassembly output: listing. (line 21) * Width of first line disassembly output: listing. (line 16) * Width of source line output: listing. (line 28) -* wmsg directive, TIC54X: TIC54X-Directives. (line 77) -* word directive: Word. (line 6) -* word directive, ARC: ARC Directives. (line 171) -* word directive, H8/300: H8/300 Directives. (line 6) -* word directive, i386: i386-Float. (line 21) -* word directive, Nios II: Nios II Directives. (line 13) -* word directive, SPARC: Sparc-Directives. (line 51) -* word directive, TIC54X: TIC54X-Directives. (line 111) -* word directive, x86-64: i386-Float. (line 21) +* 'wmsg' directive, TIC54X: TIC54X-Directives. (line 75) +* 'word' directive: Word. (line 6) +* 'word' directive, ARC: ARC Directives. (line 162) +* 'word' directive, H8/300: H8/300 Directives. (line 6) +* 'word' directive, i386: i386-Float. (line 21) +* 'word' directive, Nios II: Nios II Directives. (line 13) +* 'word' directive, SPARC: Sparc-Directives. (line 51) +* 'word' directive, TIC54X: TIC54X-Directives. (line 109) +* 'word' directive, x86-64: i386-Float. (line 21) * writing patterns in memory: Fill. (line 6) * wval: Z8000 Directives. (line 24) * x86 machine directives: i386-Directives. (line 6) * x86-64 arch directive: i386-Arch. (line 6) * x86-64 att_syntax pseudo op: i386-Variations. (line 6) -* x86-64 conversion instructions: i386-Mnemonics. (line 37) +* x86-64 conversion instructions: i386-Mnemonics. (line 36) * x86-64 floating point: i386-Float. (line 6) * x86-64 immediate operands: i386-Variations. (line 15) * x86-64 instruction naming: i386-Mnemonics. (line 6) * x86-64 intel_syntax pseudo op: i386-Variations. (line 6) * x86-64 jump optimization: i386-Jumps. (line 6) -* x86-64 jump, call, return: i386-Variations. (line 41) +* x86-64 jump, call, return: i386-Variations. (line 40) * x86-64 jump/call operands: i386-Variations. (line 15) * x86-64 memory references: i386-Memory. (line 6) * x86-64 options: i386-Options. (line 6) * x86-64 register operands: i386-Variations. (line 15) * x86-64 registers: i386-Regs. (line 6) -* x86-64 sections: i386-Variations. (line 47) -* x86-64 size suffixes: i386-Variations. (line 29) -* x86-64 source, destination operands: i386-Variations. (line 22) +* x86-64 sections: i386-Variations. (line 46) +* x86-64 size suffixes: i386-Variations. (line 28) +* x86-64 source, destination operands: i386-Variations. (line 21) * x86-64 support: i386-Dependent. (line 6) * x86-64 syntax compatibility: i386-Variations. (line 6) -* xfloat directive, TIC54X: TIC54X-Directives. (line 64) -* XGATE addressing modes: XGATE-Syntax. (line 29) +* 'xfloat' directive, TIC54X: TIC54X-Directives. (line 62) +* XGATE addressing modes: XGATE-Syntax. (line 28) * XGATE assembler directives: XGATE-Directives. (line 6) * XGATE floating point: XGATE-Float. (line 6) * XGATE line comment character: XGATE-Syntax. (line 16) -* XGATE line separator: XGATE-Syntax. (line 26) +* XGATE line separator: XGATE-Syntax. (line 25) * XGATE opcodes: XGATE-opcodes. (line 6) * XGATE options: XGATE-Opts. (line 6) * XGATE support: XGATE-Dependent. (line 6) * XGATE syntax: XGATE-Syntax. (line 6) -* xlong directive, TIC54X: TIC54X-Directives. (line 135) +* 'xlong' directive, TIC54X: TIC54X-Directives. (line 133) * XStormy16 comment character: XStormy16-Chars. (line 11) * XStormy16 line comment character: XStormy16-Chars. (line 6) * XStormy16 line separator: XStormy16-Chars. (line 14) @@ -24911,7 +24728,7 @@ AS Index * Xtensa directives: Xtensa Directives. (line 6) * Xtensa opcode names: Xtensa Opcodes. (line 6) * Xtensa register names: Xtensa Registers. (line 6) -* xword directive, SPARC: Sparc-Directives. (line 55) +* 'xword' directive, SPARC: Sparc-Directives. (line 55) * Z80 $: Z80-Chars. (line 15) * Z80 ': Z80-Chars. (line 20) * Z80 floating point: Z80 Floating Point. (line 6) @@ -24920,9 +24737,9 @@ AS Index * Z80 options: Z80 Options. (line 6) * Z80 registers: Z80-Regs. (line 6) * Z80 support: Z80-Dependent. (line 6) -* Z80 Syntax: Z80 Options. (line 47) -* Z80, \: Z80-Chars. (line 18) +* Z80 Syntax: Z80 Options. (line 40) * Z80, case sensitivity: Z80-Case. (line 6) +* Z80, \: Z80-Chars. (line 18) * Z80-only directives: Z80 Directives. (line 9) * Z800 addressing modes: Z8000-Addressing. (line 6) * Z8000 directives: Z8000 Directives. (line 6) @@ -24932,636 +24749,638 @@ AS Index * Z8000 options: Z8000 Options. (line 6) * Z8000 registers: Z8000-Regs. (line 6) * Z8000 support: Z8000-Dependent. (line 6) -* zdaoff pseudo-op, V850: V850 Opcodes. (line 99) -* zero register, V850: V850-Regs. (line 7) +* 'zdaoff' pseudo-op, V850: V850 Opcodes. (line 98) +* 'zero' register, V850: V850-Regs. (line 7) * zero-terminated strings: Asciz. (line 6) Tag Table: -Node: Top958 -Node: Overview1957 -Node: Manual33174 -Node: GNU Assembler34118 -Node: Object Formats35289 -Node: Command Line35741 -Node: Input Files36828 -Node: Object38809 -Node: Errors39705 -Node: Invoking40900 -Node: a42855 -Node: alternate44766 -Node: D44938 -Node: f45171 -Node: I45679 -Node: K46223 -Node: L46527 -Node: listing47266 -Node: M48925 -Node: MD53326 -Node: o53752 -Node: R54207 -Node: statistics55237 -Node: traditional-format55644 -Node: v56117 -Node: W56392 -Node: Z57299 -Node: Syntax57821 -Node: Preprocessing58413 -Node: Whitespace59976 -Node: Comments60372 -Node: Symbol Intro62383 -Node: Statements63110 -Node: Constants65099 -Node: Characters65730 -Node: Strings66232 -Node: Chars68398 -Node: Numbers69152 -Node: Integers69692 -Node: Bignums70348 -Node: Flonums70704 -Node: Sections72451 -Node: Secs Background72829 -Node: Ld Sections77868 -Node: As Sections80252 -Node: Sub-Sections81162 -Node: bss84307 -Node: Symbols85257 -Node: Labels85905 -Node: Setting Symbols86636 -Node: Symbol Names87190 -Node: Dot92481 -Node: Symbol Attributes92928 -Node: Symbol Value93665 -Node: Symbol Type94710 -Node: a.out Symbols95098 -Node: Symbol Desc95360 -Node: Symbol Other95655 -Node: COFF Symbols95824 -Node: SOM Symbols96497 -Node: Expressions96939 -Node: Empty Exprs97688 -Node: Integer Exprs98035 -Node: Arguments98430 -Node: Operators99536 -Node: Prefix Ops99871 -Node: Infix Ops100199 -Node: Pseudo Ops102589 -Node: Abort108264 -Node: ABORT (COFF)108676 -Node: Align108884 -Node: Altmacro111166 -Node: Ascii112495 -Node: Asciz112804 -Node: Balign113049 -Node: Bundle directives114925 -Node: Byte117854 -Node: CFI directives118115 -Node: Comm123744 -Ref: Comm-Footnote-1125345 -Node: Data125707 -Node: Def126024 -Node: Desc126256 -Node: Dim126756 -Node: Double127013 -Node: Eject127351 -Node: Else127526 -Node: Elseif127826 -Node: End128120 -Node: Endef128335 -Node: Endfunc128512 -Node: Endif128687 -Node: Equ128948 -Node: Equiv129462 -Node: Eqv130018 -Node: Err130382 -Node: Error130693 -Node: Exitm131138 -Node: Extern131307 -Node: Fail131568 -Node: File132013 -Node: Fill133342 -Node: Float134306 -Node: Func134648 -Node: Global135238 -Node: Gnu_attribute135995 -Node: Hidden136220 -Node: hword136806 -Node: Ident137134 -Node: If137708 -Node: Incbin140767 -Node: Include141462 -Node: Int142013 -Node: Internal142394 -Node: Irp143042 -Node: Irpc143921 -Node: Lcomm144838 -Node: Lflags145586 -Node: Line145780 -Node: Linkonce146693 -Node: List147922 -Node: Ln148530 -Node: Loc148680 -Node: Loc_mark_labels150066 -Node: Local150550 -Node: Long151162 -Node: Macro151340 -Node: MRI157262 -Node: Noaltmacro157600 -Node: Nolist157769 -Node: Octa158199 -Node: Offset158536 -Node: Org158863 -Node: P2align160148 -Node: PopSection162076 -Node: Previous162584 -Node: Print163997 -Node: Protected164226 -Node: Secondary164877 -Node: Psize165162 -Node: Purgem165846 -Node: PushSection166067 -Node: Quad166810 -Node: Reloc167266 -Node: Rept168027 -Node: Sbttl168441 -Node: Scl168806 -Node: Section169147 -Node: Set175303 -Node: Short175876 -Node: Single176199 -Node: Size176546 -Node: Skip177220 -Node: Sleb128177544 -Node: Space177868 -Node: Stab178509 -Node: String180513 -Node: Struct181507 -Node: SubSection182232 -Node: Symver182795 -Node: Tag185188 -Node: Text185570 -Node: Title185891 -Node: Type186272 -Node: Uleb128188585 -Node: Val188909 -Node: Version189159 -Node: VTableEntry189434 -Node: VTableInherit189724 -Node: Warning190174 -Node: Weak190408 -Node: Weakref191077 -Node: Word192042 -Node: Deprecated193888 -Node: Object Attributes194123 -Node: GNU Object Attributes195843 -Node: Defining New Object Attributes198396 -Node: Machine Dependencies199193 -Node: AArch64-Dependent203022 -Node: AArch64 Options203468 -Node: AArch64 Syntax203877 -Node: AArch64-Chars204174 -Node: AArch64-Regs204660 -Node: AArch64-Relocations204954 -Node: AArch64 Floating Point206033 -Node: AArch64 Directives206258 -Node: AArch64 Opcodes207806 -Node: AArch64 Mapping Symbols208485 -Node: Alpha-Dependent208867 -Node: Alpha Notes209307 -Node: Alpha Options209588 -Node: Alpha Syntax212063 -Node: Alpha-Chars212532 -Node: Alpha-Regs212944 -Node: Alpha-Relocs213331 -Node: Alpha Floating Point219589 -Node: Alpha Directives219811 -Node: Alpha Opcodes225334 -Node: ARC-Dependent225629 -Node: ARC Options226012 -Node: ARC Syntax227081 -Node: ARC-Chars227313 -Node: ARC-Regs227794 -Node: ARC Floating Point227918 -Node: ARC Directives228229 -Node: ARC Opcodes234194 -Node: ARM-Dependent234420 -Node: ARM Options234885 -Node: ARM Syntax243719 -Node: ARM-Instruction-Set244087 -Node: ARM-Chars245307 -Node: ARM-Regs246018 -Node: ARM-Relocations246227 -Node: ARM-Neon-Alignment247361 -Node: ARM Floating Point247825 -Node: ARM Directives248024 -Ref: arm_pad249341 -Ref: arm_fnend252678 -Ref: arm_fnstart253002 -Ref: arm_save256012 -Ref: arm_setfp256713 -Node: ARM Opcodes260005 -Node: ARM Mapping Symbols262093 -Node: ARM Unwinding Tutorial262903 -Node: AVR-Dependent269103 -Node: AVR Options269393 -Node: AVR Syntax274281 -Node: AVR-Chars274568 -Node: AVR-Regs275127 -Node: AVR-Modifiers275706 -Node: AVR Opcodes277766 -Node: Blackfin-Dependent283012 -Node: Blackfin Options283324 -Node: Blackfin Syntax284298 -Node: Blackfin Directives290505 -Node: CR16-Dependent291251 -Node: CR16 Operand Qualifiers291551 -Node: CR16 Syntax294280 -Node: CR16-Chars294466 -Node: CRIS-Dependent295003 -Node: CRIS-Opts295349 -Ref: march-option297035 -Node: CRIS-Expand298852 -Node: CRIS-Symbols300035 -Node: CRIS-Syntax301204 -Node: CRIS-Chars301540 -Node: CRIS-Pic302091 -Ref: crispic302287 -Node: CRIS-Regs305827 -Node: CRIS-Pseudos306244 -Ref: crisnous307020 -Node: D10V-Dependent308302 -Node: D10V-Opts308653 -Node: D10V-Syntax309615 -Node: D10V-Size310144 -Node: D10V-Subs311117 -Node: D10V-Chars312152 -Node: D10V-Regs314064 -Node: D10V-Addressing315109 -Node: D10V-Word315795 -Node: D10V-Float316310 -Node: D10V-Opcodes316621 -Node: D30V-Dependent317014 -Node: D30V-Opts317371 -Node: D30V-Syntax318048 -Node: D30V-Size318582 -Node: D30V-Subs319555 -Node: D30V-Chars320592 -Node: D30V-Guarded323200 -Node: D30V-Regs323882 -Node: D30V-Addressing325023 -Node: D30V-Float325693 -Node: D30V-Opcodes326006 -Node: Epiphany-Dependent326401 -Node: Epiphany Options326689 -Node: Epiphany Syntax327088 -Node: Epiphany-Chars327289 -Node: H8/300-Dependent327843 -Node: H8/300 Options328259 -Node: H8/300 Syntax328526 -Node: H8/300-Chars328827 -Node: H8/300-Regs329126 -Node: H8/300-Addressing330045 -Node: H8/300 Floating Point331086 -Node: H8/300 Directives331413 -Node: H8/300 Opcodes332541 -Node: HPPA-Dependent340863 -Node: HPPA Notes341298 -Node: HPPA Options342056 -Node: HPPA Syntax342251 -Node: HPPA Floating Point343521 -Node: HPPA Directives343727 -Node: HPPA Opcodes352413 -Node: ESA/390-Dependent352672 -Node: ESA/390 Notes353132 -Node: ESA/390 Options353923 -Node: ESA/390 Syntax354133 -Node: ESA/390 Floating Point356306 -Node: ESA/390 Directives356585 -Node: ESA/390 Opcodes359874 -Node: i386-Dependent360136 -Node: i386-Options361466 -Node: i386-Directives366048 -Node: i386-Syntax366786 -Node: i386-Variations367091 -Node: i386-Chars369632 -Node: i386-Mnemonics370361 -Node: i386-Regs373672 -Node: i386-Prefixes375717 -Node: i386-Memory378477 -Node: i386-Jumps381414 -Node: i386-Float382535 -Node: i386-SIMD384366 -Node: i386-LWP385475 -Node: i386-BMI386309 -Node: i386-TBM386687 -Node: i386-16bit387217 -Node: i386-Bugs389288 -Node: i386-Arch390042 -Node: i386-Notes392924 -Node: i860-Dependent393782 -Node: Notes-i860394222 -Node: Options-i860395127 -Node: Directives-i860396490 -Node: Opcodes for i860397559 -Node: Syntax of i860399749 -Node: i860-Chars399933 -Node: i960-Dependent400492 -Node: Options-i960400939 -Node: Floating Point-i960404824 -Node: Directives-i960405092 -Node: Opcodes for i960407126 -Node: callj-i960407766 -Node: Compare-and-branch-i960408255 -Node: Syntax of i960410159 -Node: i960-Chars410359 -Node: IA-64-Dependent410902 -Node: IA-64 Options411203 -Node: IA-64 Syntax414354 -Node: IA-64-Chars414760 -Node: IA-64-Regs414990 -Node: IA-64-Bits415916 -Node: IA-64-Relocs416446 -Node: IA-64 Opcodes416918 -Node: IP2K-Dependent417190 -Node: IP2K-Opts417462 -Node: IP2K-Syntax417962 -Node: IP2K-Chars418136 -Node: LM32-Dependent418679 -Node: LM32 Options418974 -Node: LM32 Syntax419608 -Node: LM32-Regs419904 -Node: LM32-Modifiers420863 -Node: LM32-Chars422238 -Node: LM32 Opcodes422746 -Node: M32C-Dependent423050 -Node: M32C-Opts423559 -Node: M32C-Syntax423979 -Node: M32C-Modifiers424214 -Node: M32C-Chars426003 -Node: M32R-Dependent426569 -Node: M32R-Opts426890 -Node: M32R-Directives431057 -Node: M32R-Warnings435032 -Node: M68K-Dependent438038 -Node: M68K-Opts438505 -Node: M68K-Syntax445878 -Node: M68K-Moto-Syntax447718 -Node: M68K-Float450308 -Node: M68K-Directives450828 -Node: M68K-opcodes452156 -Node: M68K-Branch452382 -Node: M68K-Chars456580 -Node: M68HC11-Dependent457443 -Node: M68HC11-Opts457974 -Node: M68HC11-Syntax462279 -Node: M68HC11-Modifiers465070 -Node: M68HC11-Directives466898 -Node: M68HC11-Float468274 -Node: M68HC11-opcodes468802 -Node: M68HC11-Branch468984 -Node: Meta-Dependent471433 -Node: Meta Options471718 -Node: Meta Syntax472380 -Node: Meta-Chars472592 -Node: Meta-Regs472892 -Node: MicroBlaze-Dependent473168 -Node: MicroBlaze Directives473857 -Node: MicroBlaze Syntax475240 -Node: MicroBlaze-Chars475472 -Node: MIPS-Dependent476024 -Node: MIPS Opts477252 -Node: MIPS Object488326 -Node: MIPS Stabs489892 -Node: MIPS symbol sizes490614 -Node: MIPS ISA492283 -Node: MIPS autoextend494020 -Node: MIPS insn494750 -Node: MIPS option stack496035 -Node: MIPS ASE instruction generation overrides496809 -Node: MIPS floating-point498847 -Node: MIPS Syntax499753 -Node: MIPS-Chars500015 -Node: MMIX-Dependent500557 -Node: MMIX-Opts500937 -Node: MMIX-Expand504541 -Node: MMIX-Syntax505856 -Ref: mmixsite506213 -Node: MMIX-Chars507054 -Node: MMIX-Symbols507928 -Node: MMIX-Regs509996 -Node: MMIX-Pseudos511021 -Ref: MMIX-loc511162 -Ref: MMIX-local512242 -Ref: MMIX-is512774 -Ref: MMIX-greg513045 -Ref: GREG-base513964 -Ref: MMIX-byte515281 -Ref: MMIX-constants515752 -Ref: MMIX-prefix516398 -Ref: MMIX-spec516772 -Node: MMIX-mmixal517106 -Node: MSP430-Dependent520604 -Node: MSP430 Options521074 -Node: MSP430 Syntax521360 -Node: MSP430-Macros521676 -Node: MSP430-Chars522407 -Node: MSP430-Regs523122 -Node: MSP430-Ext523682 -Node: MSP430 Floating Point525503 -Node: MSP430 Directives525727 -Node: MSP430 Opcodes526518 -Node: MSP430 Profiling Capability526913 -Node: NiosII-Dependent529242 -Node: Nios II Options529662 -Node: Nios II Syntax530583 -Node: Nios II Chars530789 -Node: Nios II Relocations530980 -Node: Nios II Directives532454 -Node: Nios II Opcodes534017 -Node: NS32K-Dependent534292 -Node: NS32K Syntax534515 -Node: NS32K-Chars534664 -Node: PDP-11-Dependent535404 -Node: PDP-11-Options535793 -Node: PDP-11-Pseudos540864 -Node: PDP-11-Syntax541209 -Node: PDP-11-Mnemonics542041 -Node: PDP-11-Synthetic542343 -Node: PJ-Dependent542561 -Node: PJ Options542824 -Node: PJ Syntax543119 -Node: PJ-Chars543284 -Node: PPC-Dependent543833 -Node: PowerPC-Opts544166 -Node: PowerPC-Pseudo547662 -Node: PowerPC-Syntax548284 -Node: PowerPC-Chars548474 -Node: RL78-Dependent549225 -Node: RL78-Opts549623 -Node: RL78-Modifiers549806 -Node: RL78-Directives550582 -Node: RL78-Syntax551080 -Node: RL78-Chars551276 -Node: RX-Dependent551832 -Node: RX-Opts552263 -Node: RX-Modifiers555377 -Node: RX-Directives556481 -Node: RX-Float557221 -Node: RX-Syntax557862 -Node: RX-Chars558041 -Node: S/390-Dependent558593 -Node: s390 Options559309 -Node: s390 Characters560855 -Node: s390 Syntax561376 -Node: s390 Register562277 -Node: s390 Mnemonics563090 -Node: s390 Operands566110 -Node: s390 Formats568729 -Node: s390 Aliases576575 -Node: s390 Operand Modifier580472 -Node: s390 Instruction Marker584273 -Node: s390 Literal Pool Entries585289 -Node: s390 Directives587212 -Node: s390 Floating Point592268 -Node: SCORE-Dependent592714 -Node: SCORE-Opts593019 -Node: SCORE-Pseudo594307 -Node: SCORE-Syntax596384 -Node: SCORE-Chars596566 -Node: SH-Dependent597124 -Node: SH Options597535 -Node: SH Syntax598590 -Node: SH-Chars598863 -Node: SH-Regs599406 -Node: SH-Addressing600020 -Node: SH Floating Point600929 -Node: SH Directives602023 -Node: SH Opcodes602424 -Node: SH64-Dependent606746 -Node: SH64 Options607109 -Node: SH64 Syntax608906 -Node: SH64-Chars609189 -Node: SH64-Regs609738 -Node: SH64-Addressing610834 -Node: SH64 Directives612017 -Node: SH64 Opcodes613002 -Node: Sparc-Dependent613718 -Node: Sparc-Opts614130 -Node: Sparc-Aligned-Data618788 -Node: Sparc-Syntax619620 -Node: Sparc-Chars620194 -Node: Sparc-Regs620757 -Node: Sparc-Constants625868 -Node: Sparc-Relocs630628 -Node: Sparc-Size-Translations635764 -Node: Sparc-Float637413 -Node: Sparc-Directives637608 -Node: TIC54X-Dependent639568 -Node: TIC54X-Opts640331 -Node: TIC54X-Block641374 -Node: TIC54X-Env641734 -Node: TIC54X-Constants642082 -Node: TIC54X-Subsyms642484 -Node: TIC54X-Locals644393 -Node: TIC54X-Builtins645137 -Node: TIC54X-Ext647608 -Node: TIC54X-Directives648179 -Node: TIC54X-Macros659080 -Node: TIC54X-MMRegs661191 -Node: TIC54X-Syntax661429 -Node: TIC54X-Chars661619 -Node: TIC6X-Dependent662310 -Node: TIC6X Options662613 -Node: TIC6X Syntax664614 -Node: TIC6X Directives665716 -Node: TILE-Gx-Dependent668001 -Node: TILE-Gx Options668311 -Node: TILE-Gx Syntax668661 -Node: TILE-Gx Opcodes670895 -Node: TILE-Gx Registers671183 -Node: TILE-Gx Modifiers671955 -Node: TILE-Gx Directives676927 -Node: TILEPro-Dependent677831 -Node: TILEPro Options678140 -Node: TILEPro Syntax678324 -Node: TILEPro Opcodes680558 -Node: TILEPro Registers680849 -Node: TILEPro Modifiers681619 -Node: TILEPro Directives686384 -Node: Z80-Dependent687288 -Node: Z80 Options687676 -Node: Z80 Syntax689099 -Node: Z80-Chars689771 -Node: Z80-Regs690621 -Node: Z80-Case690973 -Node: Z80 Floating Point691418 -Node: Z80 Directives691612 -Node: Z80 Opcodes693237 -Node: Z8000-Dependent694581 -Node: Z8000 Options695542 -Node: Z8000 Syntax695759 -Node: Z8000-Chars696049 -Node: Z8000-Regs696531 -Node: Z8000-Addressing697321 -Node: Z8000 Directives698438 -Node: Z8000 Opcodes700047 -Node: Vax-Dependent709989 -Node: VAX-Opts710549 -Node: VAX-float714284 -Node: VAX-directives714916 -Node: VAX-opcodes715777 -Node: VAX-branch716166 -Node: VAX-operands718673 -Node: VAX-no719436 -Node: VAX-Syntax719692 -Node: VAX-Chars719858 -Node: V850-Dependent720412 -Node: V850 Options720810 -Node: V850 Syntax724456 -Node: V850-Chars724696 -Node: V850-Regs725240 -Node: V850 Floating Point726808 -Node: V850 Directives727014 -Node: V850 Opcodes729081 -Node: XGATE-Dependent734973 -Node: XGATE-Opts735393 -Node: XGATE-Syntax736384 -Node: XGATE-Directives738463 -Node: XGATE-Float738702 -Node: XGATE-opcodes739199 -Node: XSTORMY16-Dependent739311 -Node: XStormy16 Syntax739657 -Node: XStormy16-Chars739847 -Node: XStormy16 Directives740460 -Node: XStormy16 Opcodes741115 -Node: Xtensa-Dependent742171 -Node: Xtensa Options742905 -Node: Xtensa Syntax745642 -Node: Xtensa Opcodes747786 -Node: Xtensa Registers749580 -Node: Xtensa Optimizations750213 -Node: Density Instructions750665 -Node: Xtensa Automatic Alignment751767 -Node: Xtensa Relaxation754214 -Node: Xtensa Branch Relaxation755122 -Node: Xtensa Call Relaxation756494 -Node: Xtensa Immediate Relaxation758280 -Node: Xtensa Directives760854 -Node: Schedule Directive762563 -Node: Longcalls Directive762903 -Node: Transform Directive763447 -Node: Literal Directive764189 -Ref: Literal Directive-Footnote-1767728 -Node: Literal Position Directive767870 -Node: Literal Prefix Directive769569 -Node: Absolute Literals Directive770467 -Node: Reporting Bugs771774 -Node: Bug Criteria772500 -Node: Bug Reporting773267 -Node: Acknowledgements779947 -Ref: Acknowledgements-Footnote-1784912 -Node: GNU Free Documentation License784938 -Node: AS Index810107 +Node: Top736 +Node: Overview1723 +Node: Manual33597 +Node: GNU Assembler34541 +Node: Object Formats35712 +Node: Command Line36164 +Node: Input Files37250 +Node: Object39231 +Node: Errors40127 +Node: Invoking41320 +Node: a43265 +Node: alternate45176 +Node: D45348 +Node: f45581 +Node: I46090 +Node: K46634 +Node: L46938 +Node: listing47677 +Node: M49336 +Node: MD53735 +Node: o54161 +Node: R54616 +Node: statistics55646 +Node: traditional-format56053 +Node: v56526 +Node: W56801 +Node: Z57708 +Node: Syntax58230 +Node: Preprocessing58822 +Node: Whitespace60386 +Node: Comments60782 +Node: Symbol Intro62793 +Node: Statements63518 +Node: Constants65506 +Node: Characters66137 +Node: Strings66639 +Node: Chars68803 +Node: Numbers69556 +Node: Integers70096 +Node: Bignums70752 +Node: Flonums71108 +Node: Sections72852 +Node: Secs Background73230 +Node: Ld Sections78263 +Node: As Sections80647 +Node: Sub-Sections81557 +Node: bss84705 +Node: Symbols85655 +Node: Labels86303 +Node: Setting Symbols87034 +Node: Symbol Names87588 +Node: Dot92883 +Node: Symbol Attributes93330 +Node: Symbol Value94063 +Node: Symbol Type95108 +Node: a.out Symbols95496 +Node: Symbol Desc95758 +Node: Symbol Other96054 +Node: COFF Symbols96223 +Node: SOM Symbols96896 +Node: Expressions97338 +Node: Empty Exprs98087 +Node: Integer Exprs98434 +Node: Arguments98829 +Node: Operators99935 +Node: Prefix Ops100270 +Node: Infix Ops100597 +Node: Pseudo Ops102991 +Node: Abort108593 +Node: ABORT (COFF)109006 +Node: Align109214 +Node: Altmacro111496 +Node: Ascii112827 +Node: Asciz113136 +Node: Balign113381 +Node: Bundle directives115257 +Node: Byte118185 +Node: CFI directives118446 +Node: Comm124079 +Ref: Comm-Footnote-1125679 +Node: Data126041 +Node: Def126358 +Node: Desc126590 +Node: Dim127090 +Node: Double127347 +Node: Eject127685 +Node: Else127860 +Node: Elseif128160 +Node: End128454 +Node: Endef128669 +Node: Endfunc128846 +Node: Endif129021 +Node: Equ129282 +Node: Equiv129796 +Node: Eqv130352 +Node: Err130716 +Node: Error131027 +Node: Exitm131472 +Node: Extern131641 +Node: Fail131902 +Node: File132347 +Node: Fill133676 +Node: Float134640 +Node: Func134982 +Node: Global135572 +Node: Gnu_attribute136329 +Node: Hidden136554 +Node: hword137140 +Node: Ident137468 +Node: If138042 +Node: Incbin141103 +Node: Include141797 +Node: Int142348 +Node: Internal142729 +Node: Irp143376 +Node: Irpc144255 +Node: Lcomm145171 +Node: Lflags145918 +Node: Line146112 +Node: Linkonce147028 +Node: List148257 +Node: Ln148864 +Node: Loc149014 +Node: Loc_mark_labels150399 +Node: Local150883 +Node: Long151495 +Node: Macro151673 +Node: MRI157604 +Node: Noaltmacro157942 +Node: Nolist158111 +Node: Octa158540 +Node: Offset158877 +Node: Org159204 +Node: P2align160489 +Node: PopSection162417 +Node: Previous162925 +Node: Print164337 +Node: Protected164566 +Node: Psize165213 +Node: Purgem165897 +Node: PushSection166118 +Node: Quad166862 +Node: Reloc167316 +Node: Rept168077 +Node: Sbttl168491 +Node: Scl168856 +Node: Section169197 +Node: Set175318 +Node: Short175891 +Node: Single176214 +Node: Size176561 +Node: Skip177229 +Node: Sleb128177553 +Node: Space177877 +Node: Stab178518 +Node: String180523 +Node: Struct181517 +Node: SubSection182242 +Node: Symver182805 +Node: Tag185201 +Node: Text185583 +Node: Title185905 +Node: Type186286 +Node: Uleb128188592 +Node: Val188916 +Node: Version189166 +Node: VTableEntry189440 +Node: VTableInherit189730 +Node: Warning190180 +Node: Weak190414 +Node: Weakref191083 +Node: Word192048 +Node: Deprecated193894 +Node: Object Attributes194128 +Node: GNU Object Attributes195848 +Node: Defining New Object Attributes198391 +Node: Machine Dependencies199183 +Node: AArch64-Dependent202961 +Node: AArch64 Options203407 +Node: AArch64 Syntax204038 +Node: AArch64-Chars204335 +Node: AArch64-Regs204821 +Node: AArch64-Relocations205115 +Node: AArch64 Floating Point206194 +Node: AArch64 Directives206419 +Node: AArch64 Opcodes207967 +Node: AArch64 Mapping Symbols208645 +Node: Alpha-Dependent209026 +Node: Alpha Notes209466 +Node: Alpha Options209747 +Node: Alpha Syntax212222 +Node: Alpha-Chars212691 +Node: Alpha-Regs213103 +Node: Alpha-Relocs213490 +Node: Alpha Floating Point219736 +Node: Alpha Directives219958 +Node: Alpha Opcodes225485 +Node: ARC-Dependent225780 +Node: ARC Options226163 +Node: ARC Syntax227234 +Node: ARC-Chars227466 +Node: ARC-Regs227947 +Node: ARC Floating Point228071 +Node: ARC Directives228382 +Node: ARC Opcodes234302 +Node: ARM-Dependent234528 +Node: ARM Options234993 +Node: ARM Syntax243839 +Node: ARM-Instruction-Set244207 +Node: ARM-Chars245422 +Node: ARM-Regs246133 +Node: ARM-Relocations246342 +Node: ARM-Neon-Alignment247477 +Node: ARM Floating Point247942 +Node: ARM Directives248141 +Ref: arm_pad249452 +Ref: arm_fnend252787 +Ref: arm_fnstart253106 +Ref: arm_save256115 +Ref: arm_setfp256816 +Node: ARM Opcodes260102 +Node: ARM Mapping Symbols262189 +Node: ARM Unwinding Tutorial262998 +Node: AVR-Dependent269198 +Node: AVR Options269488 +Node: AVR Syntax274375 +Node: AVR-Chars274662 +Node: AVR-Regs275221 +Node: AVR-Modifiers275802 +Node: AVR Opcodes277866 +Node: Blackfin-Dependent283112 +Node: Blackfin Options283424 +Node: Blackfin Syntax284398 +Node: Blackfin Directives290607 +Node: CR16-Dependent291348 +Node: CR16 Operand Qualifiers291648 +Node: CR16 Syntax294357 +Node: CR16-Chars294543 +Node: CRIS-Dependent295080 +Node: CRIS-Opts295426 +Ref: march-option297111 +Node: CRIS-Expand298930 +Node: CRIS-Symbols300113 +Node: CRIS-Syntax301284 +Node: CRIS-Chars301620 +Node: CRIS-Pic302171 +Ref: crispic302366 +Node: CRIS-Regs305915 +Node: CRIS-Pseudos306332 +Ref: crisnous307109 +Node: D10V-Dependent308397 +Node: D10V-Opts308748 +Node: D10V-Syntax309717 +Node: D10V-Size310246 +Node: D10V-Subs311217 +Node: D10V-Chars312252 +Node: D10V-Regs314063 +Node: D10V-Addressing315090 +Node: D10V-Word315768 +Node: D10V-Float316283 +Node: D10V-Opcodes316594 +Node: D30V-Dependent316987 +Node: D30V-Opts317344 +Node: D30V-Syntax318022 +Node: D30V-Size318556 +Node: D30V-Subs319529 +Node: D30V-Chars320566 +Node: D30V-Guarded323176 +Node: D30V-Regs323853 +Node: D30V-Addressing324972 +Node: D30V-Float325634 +Node: D30V-Opcodes325947 +Node: Epiphany-Dependent326342 +Node: Epiphany Options326630 +Node: Epiphany Syntax327029 +Node: Epiphany-Chars327230 +Node: H8/300-Dependent327784 +Node: H8/300 Options328200 +Node: H8/300 Syntax328466 +Node: H8/300-Chars328767 +Node: H8/300-Regs329066 +Node: H8/300-Addressing329985 +Node: H8/300 Floating Point331009 +Node: H8/300 Directives331336 +Node: H8/300 Opcodes332464 +Node: HPPA-Dependent340783 +Node: HPPA Notes341218 +Node: HPPA Options341976 +Node: HPPA Syntax342171 +Node: HPPA Floating Point343441 +Node: HPPA Directives343647 +Node: HPPA Opcodes352329 +Node: ESA/390-Dependent352588 +Node: ESA/390 Notes353048 +Node: ESA/390 Options353839 +Node: ESA/390 Syntax354049 +Node: ESA/390 Floating Point356222 +Node: ESA/390 Directives356501 +Node: ESA/390 Opcodes359791 +Node: i386-Dependent360053 +Node: i386-Options361380 +Node: i386-Directives366890 +Node: i386-Syntax367627 +Node: i386-Variations367932 +Node: i386-Chars370469 +Node: i386-Mnemonics371198 +Node: i386-Regs374508 +Node: i386-Prefixes376548 +Node: i386-Memory379308 +Node: i386-Jumps382247 +Node: i386-Float383370 +Node: i386-SIMD385202 +Node: i386-LWP386311 +Node: i386-BMI387145 +Node: i386-TBM387523 +Node: i386-16bit388053 +Node: i386-Bugs390124 +Node: i386-Arch390875 +Node: i386-Notes393995 +Node: i860-Dependent394854 +Node: Notes-i860395294 +Node: Options-i860396201 +Node: Directives-i860397561 +Node: Opcodes for i860398633 +Node: Syntax of i860400822 +Node: i860-Chars401006 +Node: i960-Dependent401565 +Node: Options-i960402012 +Node: Floating Point-i960405898 +Node: Directives-i960406166 +Node: Opcodes for i960408200 +Node: callj-i960408840 +Node: Compare-and-branch-i960409330 +Node: Syntax of i960411234 +Node: i960-Chars411434 +Node: IA-64-Dependent411977 +Node: IA-64 Options412278 +Node: IA-64 Syntax415429 +Node: IA-64-Chars415835 +Node: IA-64-Regs416065 +Node: IA-64-Bits416991 +Node: IA-64-Relocs417521 +Node: IA-64 Opcodes417992 +Node: IP2K-Dependent418264 +Node: IP2K-Opts418536 +Node: IP2K-Syntax419035 +Node: IP2K-Chars419209 +Node: LM32-Dependent419752 +Node: LM32 Options420047 +Node: LM32 Syntax420680 +Node: LM32-Regs420976 +Node: LM32-Modifiers421917 +Node: LM32-Chars423297 +Node: LM32 Opcodes423805 +Node: M32C-Dependent424109 +Node: M32C-Opts424615 +Node: M32C-Syntax425034 +Node: M32C-Modifiers425269 +Node: M32C-Chars427061 +Node: M32R-Dependent427627 +Node: M32R-Opts427948 +Node: M32R-Directives432110 +Node: M32R-Warnings436084 +Node: M68K-Dependent439089 +Node: M68K-Opts439556 +Node: M68K-Syntax446978 +Node: M68K-Moto-Syntax448818 +Node: M68K-Float451402 +Node: M68K-Directives451922 +Node: M68K-opcodes453249 +Node: M68K-Branch453475 +Node: M68K-Chars457668 +Node: M68HC11-Dependent458531 +Node: M68HC11-Opts459062 +Node: M68HC11-Syntax463374 +Node: M68HC11-Modifiers466168 +Node: M68HC11-Directives467995 +Node: M68HC11-Float469369 +Node: M68HC11-opcodes469897 +Node: M68HC11-Branch470079 +Node: Meta-Dependent472528 +Node: Meta Options472813 +Node: Meta Syntax473475 +Node: Meta-Chars473687 +Node: Meta-Regs473987 +Node: MicroBlaze-Dependent474263 +Node: MicroBlaze Directives474950 +Node: MicroBlaze Syntax476341 +Node: MicroBlaze-Chars476573 +Node: MIPS-Dependent477125 +Node: MIPS Options478511 +Node: MIPS Macros491670 +Ref: MIPS Macros-Footnote-1494384 +Node: MIPS Symbol Sizes494527 +Node: MIPS Small Data496199 +Node: MIPS ISA498363 +Node: MIPS assembly options500111 +Node: MIPS autoextend500680 +Node: MIPS insn501414 +Node: MIPS NaN Encodings502700 +Node: MIPS Option Stack504658 +Node: MIPS ASE Instruction Generation Overrides505443 +Node: MIPS Floating-Point507731 +Node: MIPS Syntax508637 +Node: MIPS-Chars508899 +Node: MMIX-Dependent509441 +Node: MMIX-Opts509821 +Node: MMIX-Expand513426 +Node: MMIX-Syntax514738 +Ref: mmixsite515094 +Node: MMIX-Chars515936 +Node: MMIX-Symbols516809 +Node: MMIX-Regs518880 +Node: MMIX-Pseudos519905 +Ref: MMIX-loc520047 +Ref: MMIX-local521128 +Ref: MMIX-is521661 +Ref: MMIX-greg521933 +Ref: GREG-base522851 +Ref: MMIX-byte524170 +Ref: MMIX-constants524642 +Ref: MMIX-prefix525284 +Ref: MMIX-spec525659 +Node: MMIX-mmixal525993 +Node: MSP430-Dependent529488 +Node: MSP430 Options529958 +Node: MSP430 Syntax531292 +Node: MSP430-Macros531608 +Node: MSP430-Chars532338 +Node: MSP430-Regs533053 +Node: MSP430-Ext533614 +Node: MSP430 Floating Point535433 +Node: MSP430 Directives535657 +Node: MSP430 Opcodes536529 +Node: MSP430 Profiling Capability536924 +Node: NiosII-Dependent539252 +Node: Nios II Options539672 +Node: Nios II Syntax540586 +Node: Nios II Chars540792 +Node: Nios II Relocations540983 +Node: Nios II Directives542458 +Node: Nios II Opcodes544020 +Node: NS32K-Dependent544295 +Node: NS32K Syntax544522 +Node: NS32K-Chars544671 +Node: PDP-11-Dependent545411 +Node: PDP-11-Options545801 +Node: PDP-11-Pseudos550860 +Node: PDP-11-Syntax551205 +Node: PDP-11-Mnemonics552037 +Node: PDP-11-Synthetic552339 +Node: PJ-Dependent552557 +Node: PJ Options552820 +Node: PJ Syntax553115 +Node: PJ-Chars553280 +Node: PPC-Dependent553829 +Node: PowerPC-Opts554162 +Node: PowerPC-Pseudo557657 +Node: PowerPC-Syntax558278 +Node: PowerPC-Chars558468 +Node: RL78-Dependent559219 +Node: RL78-Opts559617 +Node: RL78-Modifiers559891 +Node: RL78-Directives560670 +Node: RL78-Syntax561167 +Node: RL78-Chars561363 +Node: RX-Dependent561919 +Node: RX-Opts562350 +Node: RX-Modifiers565751 +Node: RX-Directives566854 +Node: RX-Float567593 +Node: RX-Syntax568228 +Node: RX-Chars568407 +Node: S/390-Dependent568959 +Node: s390 Options569674 +Node: s390 Characters571222 +Node: s390 Syntax571743 +Node: s390 Register572645 +Node: s390 Mnemonics573461 +Node: s390 Operands576483 +Node: s390 Formats579113 +Node: s390 Aliases586960 +Node: s390 Operand Modifier590925 +Node: s390 Instruction Marker594728 +Node: s390 Literal Pool Entries595742 +Node: s390 Directives597675 +Node: s390 Floating Point602733 +Node: SCORE-Dependent603181 +Node: SCORE-Opts603483 +Node: SCORE-Pseudo604770 +Node: SCORE-Syntax606852 +Node: SCORE-Chars607034 +Node: SH-Dependent607592 +Node: SH Options608003 +Node: SH Syntax609054 +Node: SH-Chars609327 +Node: SH-Regs609870 +Node: SH-Addressing610484 +Node: SH Floating Point611392 +Node: SH Directives612489 +Node: SH Opcodes612890 +Node: SH64-Dependent617211 +Node: SH64 Options617573 +Node: SH64 Syntax619364 +Node: SH64-Chars619647 +Node: SH64-Regs620196 +Node: SH64-Addressing621292 +Node: SH64 Directives622477 +Node: SH64 Opcodes623461 +Node: Sparc-Dependent624176 +Node: Sparc-Opts624587 +Node: Sparc-Aligned-Data629254 +Node: Sparc-Syntax630086 +Node: Sparc-Chars630660 +Node: Sparc-Regs631223 +Node: Sparc-Constants636334 +Node: Sparc-Relocs641094 +Node: Sparc-Size-Translations646212 +Node: Sparc-Float647862 +Node: Sparc-Directives648057 +Node: TIC54X-Dependent650019 +Node: TIC54X-Opts650782 +Node: TIC54X-Block651823 +Node: TIC54X-Env652183 +Node: TIC54X-Constants652531 +Node: TIC54X-Subsyms652927 +Node: TIC54X-Locals654831 +Node: TIC54X-Builtins655571 +Node: TIC54X-Ext657985 +Node: TIC54X-Directives658556 +Node: TIC54X-Macros669464 +Node: TIC54X-MMRegs671551 +Node: TIC54X-Syntax671788 +Node: TIC54X-Chars671978 +Node: TIC6X-Dependent672669 +Node: TIC6X Options672972 +Node: TIC6X Syntax674971 +Node: TIC6X Directives676074 +Node: TILE-Gx-Dependent678359 +Node: TILE-Gx Options678669 +Node: TILE-Gx Syntax679018 +Node: TILE-Gx Opcodes681254 +Node: TILE-Gx Registers681542 +Node: TILE-Gx Modifiers682313 +Node: TILE-Gx Directives687311 +Node: TILEPro-Dependent688214 +Node: TILEPro Options688522 +Node: TILEPro Syntax688706 +Node: TILEPro Opcodes690942 +Node: TILEPro Registers691233 +Node: TILEPro Modifiers692003 +Node: TILEPro Directives696791 +Node: Z80-Dependent697694 +Node: Z80 Options698083 +Node: Z80 Syntax699502 +Node: Z80-Chars700174 +Node: Z80-Regs701025 +Node: Z80-Case701377 +Node: Z80 Floating Point701822 +Node: Z80 Directives702016 +Node: Z80 Opcodes703641 +Node: Z8000-Dependent704987 +Node: Z8000 Options705945 +Node: Z8000 Syntax706162 +Node: Z8000-Chars706452 +Node: Z8000-Regs706934 +Node: Z8000-Addressing707724 +Node: Z8000 Directives708834 +Node: Z8000 Opcodes710438 +Node: Vax-Dependent720380 +Node: VAX-Opts720963 +Node: VAX-float724684 +Node: VAX-directives725317 +Node: VAX-opcodes726177 +Node: VAX-branch726566 +Node: VAX-operands729070 +Node: VAX-no729833 +Node: VAX-Syntax730089 +Node: VAX-Chars730255 +Node: V850-Dependent730809 +Node: V850 Options731203 +Node: V850 Syntax734847 +Node: V850-Chars735087 +Node: V850-Regs735631 +Node: V850 Floating Point737141 +Node: V850 Directives737347 +Node: V850 Opcodes739413 +Node: XGATE-Dependent745292 +Node: XGATE-Opts745712 +Node: XGATE-Syntax746701 +Node: XGATE-Directives748782 +Node: XGATE-Float749021 +Node: XGATE-opcodes749518 +Node: XSTORMY16-Dependent749630 +Node: XStormy16 Syntax749976 +Node: XStormy16-Chars750166 +Node: XStormy16 Directives750779 +Node: XStormy16 Opcodes751433 +Node: Xtensa-Dependent752488 +Node: Xtensa Options753219 +Node: Xtensa Syntax755950 +Node: Xtensa Opcodes758094 +Node: Xtensa Registers759887 +Node: Xtensa Optimizations760520 +Node: Density Instructions760972 +Node: Xtensa Automatic Alignment762074 +Node: Xtensa Relaxation764521 +Node: Xtensa Branch Relaxation765429 +Node: Xtensa Call Relaxation766801 +Node: Xtensa Immediate Relaxation768587 +Node: Xtensa Directives771162 +Node: Schedule Directive772870 +Node: Longcalls Directive773210 +Node: Transform Directive773754 +Node: Literal Directive774496 +Ref: Literal Directive-Footnote-1778035 +Node: Literal Position Directive778177 +Node: Literal Prefix Directive779876 +Node: Absolute Literals Directive780774 +Node: Reporting Bugs782081 +Node: Bug Criteria782807 +Node: Bug Reporting783574 +Node: Acknowledgements790218 +Ref: Acknowledgements-Footnote-1795184 +Node: GNU Free Documentation License795210 +Node: AS Index820359 End Tag Table |