diff options
Diffstat (limited to 'share/man/man1/aarch64-linux-android-as.1')
| -rw-r--r-- | share/man/man1/aarch64-linux-android-as.1 | 120 |
1 files changed, 90 insertions, 30 deletions
diff --git a/share/man/man1/aarch64-linux-android-as.1 b/share/man/man1/aarch64-linux-android-as.1 index ed9fb3d..f0ade69 100644 --- a/share/man/man1/aarch64-linux-android-as.1 +++ b/share/man/man1/aarch64-linux-android-as.1 @@ -1,4 +1,4 @@ -.\" Automatically generated by Pod::Man 2.25 (Pod::Simple 3.16) +.\" Automatically generated by Pod::Man 2.27 (Pod::Simple 3.28) .\" .\" Standard preamble: .\" ======================================================================== @@ -38,6 +38,8 @@ . ds PI \(*p . ds L" `` . ds R" '' +. ds C` +. ds C' 'br\} .\" .\" Escape single quotes in literal strings from groff's Unicode transform. @@ -48,17 +50,24 @@ .\" titles (.TH), headers (.SH), subsections (.SS), items (.Ip), and index .\" entries marked with X<> in POD. Of course, you'll have to process the .\" output yourself in some meaningful fashion. -.ie \nF \{\ -. de IX -. tm Index:\\$1\t\\n%\t"\\$2" +.\" +.\" Avoid warning from groff about undefined register 'F'. +.de IX .. -. nr % 0 -. rr F -.\} -.el \{\ -. de IX +.nr rF 0 +.if \n(.g .if rF .nr rF 1 +.if (\n(rF:(\n(.g==0)) \{ +. if \nF \{ +. de IX +. tm Index:\\$1\t\\n%\t"\\$2" .. +. if !\nF==2 \{ +. nr % 0 +. nr F 2 +. \} +. \} .\} +.rr rF .\" .\" Accent mark definitions (@(#)ms.acc 1.5 88/02/08 SMI; from UCB 4.2). .\" Fear. Run. Save yourself. No user-serviceable parts. @@ -124,7 +133,7 @@ .\" ======================================================================== .\" .IX Title "AS 1" -.TH AS 1 "2014-09-12" "binutils-2.23.52.0.2" "GNU Development Tools" +.TH AS 1 "2014-08-29" "binutils-2.24.0" "GNU Development Tools" .\" For nroff, turn off justification. Always turn off hyphenation; it makes .\" way too many mistakes in technical documents. .if n .ad l @@ -137,7 +146,8 @@ as [\fB\-a\fR[\fBcdghlns\fR][=\fIfile\fR]] [\fB\-\-alternate\fR] [\fB\-D\fR] [\fB\-\-compress\-debug\-sections\fR] [\fB\-\-nocompress\-debug\-sections\fR] [\fB\-\-debug\-prefix\-map\fR \fIold\fR=\fInew\fR] [\fB\-\-defsym\fR \fIsym\fR=\fIval\fR] [\fB\-f\fR] [\fB\-g\fR] [\fB\-\-gstabs\fR] - [\fB\-\-gstabs+\fR] [\fB\-\-gdwarf\-2\fR] [\fB\-\-help\fR] [\fB\-I\fR \fIdir\fR] [\fB\-J\fR] + [\fB\-\-gstabs+\fR] [\fB\-\-gdwarf\-2\fR] [\fB\-\-gdwarf\-sections\fR] + [\fB\-\-help\fR] [\fB\-I\fR \fIdir\fR] [\fB\-J\fR] [\fB\-K\fR] [\fB\-L\fR] [\fB\-\-listing\-lhs\-width\fR=\fI\s-1NUM\s0\fR] [\fB\-\-listing\-lhs\-width2\fR=\fI\s-1NUM\s0\fR] [\fB\-\-listing\-rhs\-width\fR=\fI\s-1NUM\s0\fR] [\fB\-\-listing\-cont\-lines\fR=\fI\s-1NUM\s0\fR] [\fB\-\-keep\-locals\fR] [\fB\-o\fR @@ -150,6 +160,7 @@ as [\fB\-a\fR[\fBcdghlns\fR][=\fIfile\fR]] [\fB\-\-alternate\fR] [\fB\-D\fR] .PP \&\fITarget AArch64 options:\fR [\fB\-EB\fR|\fB\-EL\fR] + [\fB\-mabi\fR=\fI\s-1ABI\s0\fR] .PP \&\fITarget Alpha options:\fR [\fB\-m\fR\fIcpu\fR] @@ -254,6 +265,7 @@ as [\fB\-a\fR[\fBcdghlns\fR][=\fIfile\fR]] [\fB\-\-alternate\fR] [\fB\-D\fR] [\fB\-mips3\fR] [\fB\-mips4\fR] [\fB\-mips5\fR] [\fB\-mips32\fR] [\fB\-mips32r2\fR] [\fB\-mips64\fR] [\fB\-mips64r2\fR] [\fB\-construct\-floats\fR] [\fB\-no\-construct\-floats\fR] + [\fB\-mnan=\fR\fIencoding\fR] [\fB\-trap\fR] [\fB\-no\-break\fR] [\fB\-break\fR] [\fB\-no\-trap\fR] [\fB\-mips16\fR] [\fB\-no\-mips16\fR] [\fB\-mmicromips\fR] [\fB\-mno\-micromips\fR] @@ -264,6 +276,7 @@ as [\fB\-a\fR[\fBcdghlns\fR][=\fIfile\fR]] [\fB\-\-alternate\fR] [\fB\-D\fR] [\fB\-mdspr2\fR] [\fB\-mno\-dspr2\fR] [\fB\-mmt\fR] [\fB\-mno\-mt\fR] [\fB\-mmcu\fR] [\fB\-mno\-mcu\fR] + [\fB\-minsn32\fR] [\fB\-mno\-insn32\fR] [\fB\-mfix7000\fR] [\fB\-mno\-fix7000\fR] [\fB\-mfix\-vr4120\fR] [\fB\-mno\-fix\-vr4120\fR] [\fB\-mfix\-vr4130\fR] [\fB\-mno\-fix\-vr4130\fR] @@ -357,7 +370,7 @@ as [\fB\-a\fR[\fBcdghlns\fR][=\fIfile\fR]] [\fB\-\-alternate\fR] [\fB\-D\fR] [ \fB\-forbid\-unportable\-instructions\fR] [\fB\-Fup\fR] .SH "DESCRIPTION" .IX Header "DESCRIPTION" -\&\s-1GNU\s0 \fBas\fR is really a family of assemblers. +\&\s-1GNU \s0\fBas\fR is really a family of assemblers. If you use (or have used) the \s-1GNU\s0 assembler on one architecture, you should find a fairly similar environment when you use it on another architecture. Each version has much in common with the others, @@ -365,7 +378,7 @@ including object file formats, most assembler directives (often called \&\fIpseudo-ops\fR) and assembler syntax. .PP \&\fBas\fR is primarily intended to assemble the output of the -\&\s-1GNU\s0 C compiler \f(CW\*(C`gcc\*(C'\fR for use by the linker +\&\s-1GNU C\s0 compiler \f(CW\*(C`gcc\*(C'\fR for use by the linker \&\f(CW\*(C`ld\*(C'\fR. Nevertheless, we've tried to make \fBas\fR assemble correctly everything that other assemblers for the same machine would assemble. @@ -400,7 +413,7 @@ runs \fBas\fR automatically. Warnings report an assumption made so that \fBas\fR could keep assembling a flawed program; errors report a grave problem that stops the assembly. .PP -If you are invoking \fBas\fR via the \s-1GNU\s0 C compiler, +If you are invoking \fBas\fR via the \s-1GNU C\s0 compiler, you can use the \fB\-Wa\fR option to pass arguments through to the assembler. The assembler arguments must be separated from each other (and the \fB\-Wa\fR) by commas. For example: @@ -508,8 +521,8 @@ compiler output). .IX Item "--gen-debug" .PD Generate debugging information for each assembler source line using whichever -debug format is preferred by the target. This currently means either \s-1STABS\s0, -\&\s-1ECOFF\s0 or \s-1DWARF2\s0. +debug format is preferred by the target. This currently means either \s-1STABS, +ECOFF\s0 or \s-1DWARF2.\s0 .IP "\fB\-\-gstabs\fR" 4 .IX Item "--gstabs" Generate stabs debugging information for each assembler line. This @@ -526,13 +539,22 @@ the location of the current working directory at assembling time. Generate \s-1DWARF2\s0 debugging information for each assembler line. This may help debugging assembler code, if the debugger can handle it. Note\-\-\-this option is only supported by some targets, not all of them. +.IP "\fB\-\-gdwarf\-sections\fR" 4 +.IX Item "--gdwarf-sections" +Instead of creating a .debug_line section, create a series of +\&.debug_line.\fIfoo\fR sections where \fIfoo\fR is the name of the +corresponding code section. For example a code section called \fI.text.func\fR +will have its dwarf line number information placed into a section called +\&\fI.debug_line.text.func\fR. If the code section is just called \fI.text\fR +then debug line section will still be called just \fI.debug_line\fR without any +suffix. .IP "\fB\-\-size\-check=error\fR" 4 .IX Item "--size-check=error" .PD 0 .IP "\fB\-\-size\-check=warning\fR" 4 .IX Item "--size-check=warning" .PD -Issue an error or warning for invalid \s-1ELF\s0 .size directive. +Issue an error or warning for invalid \s-1ELF \s0.size directive. .IP "\fB\-\-help\fR" 4 .IX Item "--help" Print a summary of the command line options and exit. @@ -643,6 +665,11 @@ be marked as being encoded for a big-endian processor. .IX Item "-EL" This option specifies that the output generated by the assembler should be marked as being encoded for a little-endian processor. +.IP "\fB\-mabi=\fR\fIabi\fR" 4 +.IX Item "-mabi=abi" +Specify which \s-1ABI\s0 the source code uses. The recognized arguments +are: \f(CW\*(C`ilp32\*(C'\fR and \f(CW\*(C`lp64\*(C'\fR, which decides the generated object +file in \s-1ELF32\s0 and \s-1ELF64\s0 format respectively. The default is \f(CW\*(C`lp64\*(C'\fR. .PP The following options are available when as is configured for an Alpha processor. @@ -710,7 +737,7 @@ Utility Manual. .IX Item "-g" This option is used when the compiler generates debug information. When \&\fBgcc\fR is using \fBmips-tfile\fR to generate debug -information for \s-1ECOFF\s0, local labels must be passed through to the object +information for \s-1ECOFF,\s0 local labels must be passed through to the object file. Otherwise this option has no effect. .IP "\fB\-G\fR\fIsize\fR" 4 .IX Item "-Gsize" @@ -810,7 +837,7 @@ and \&\f(CW\*(C`bf592\*(C'\fR. .IP "\fB\-mfdpic\fR" 4 .IX Item "-mfdpic" -Assemble for the \s-1FDPIC\s0 \s-1ABI\s0. +Assemble for the \s-1FDPIC ABI.\s0 .IP "\fB\-mno\-fdpic\fR" 4 .IX Item "-mno-fdpic" .PD 0 @@ -948,6 +975,12 @@ accept various extension mnemonics. For example, \&\f(CW\*(C`rdseed\*(C'\fR, \&\f(CW\*(C`prfchw\*(C'\fR, \&\f(CW\*(C`smap\*(C'\fR, +\&\f(CW\*(C`mpx\*(C'\fR, +\&\f(CW\*(C`sha\*(C'\fR, +\&\f(CW\*(C`avx512f\*(C'\fR, +\&\f(CW\*(C`avx512cd\*(C'\fR, +\&\f(CW\*(C`avx512er\*(C'\fR, +\&\f(CW\*(C`avx512pf\*(C'\fR, \&\f(CW\*(C`noavx\*(C'\fR, \&\f(CW\*(C`vmx\*(C'\fR, \&\f(CW\*(C`vmfunc\*(C'\fR, @@ -1007,12 +1040,12 @@ with \s-1VEX\s0 prefix. .IP "\fB\-msse\-check=\fR\fIerror\fR" 4 .IX Item "-msse-check=error" .PD -These options control if the assembler should check \s-1SSE\s0 intructions. +These options control if the assembler should check \s-1SSE\s0 instructions. \&\fB\-msse\-check=\fR\fInone\fR will make the assembler not to check \s-1SSE\s0 instructions, which is the default. \fB\-msse\-check=\fR\fIwarning\fR -will make the assembler issue a warning for any \s-1SSE\s0 intruction. +will make the assembler issue a warning for any \s-1SSE\s0 instruction. \&\fB\-msse\-check=\fR\fIerror\fR will make the assembler issue an error -for any \s-1SSE\s0 intruction. +for any \s-1SSE\s0 instruction. .IP "\fB\-mavxscalar=\fR\fI128\fR" 4 .IX Item "-mavxscalar=128" .PD 0 @@ -1024,6 +1057,31 @@ instructions. \fB\-mavxscalar=\fR\fI128\fR will encode scalar \&\s-1AVX\s0 instructions with 128bit vector length, which is the default. \&\fB\-mavxscalar=\fR\fI256\fR will encode scalar \s-1AVX\s0 instructions with 256bit vector length. +.IP "\fB\-mevexlig=\fR\fI128\fR" 4 +.IX Item "-mevexlig=128" +.PD 0 +.IP "\fB\-mevexlig=\fR\fI256\fR" 4 +.IX Item "-mevexlig=256" +.IP "\fB\-mevexlig=\fR\fI512\fR" 4 +.IX Item "-mevexlig=512" +.PD +These options control how the assembler should encode length-ignored +(\s-1LIG\s0) \s-1EVEX\s0 instructions. \fB\-mevexlig=\fR\fI128\fR will encode \s-1LIG +EVEX\s0 instructions with 128bit vector length, which is the default. +\&\fB\-mevexlig=\fR\fI256\fR and \fB\-mevexlig=\fR\fI512\fR will +encode \s-1LIG EVEX\s0 instructions with 256bit and 512bit vector length, +respectively. +.IP "\fB\-mevexwig=\fR\fI0\fR" 4 +.IX Item "-mevexwig=0" +.PD 0 +.IP "\fB\-mevexwig=\fR\fI1\fR" 4 +.IX Item "-mevexwig=1" +.PD +These options control how the assembler should encode w\-ignored (\s-1WIG\s0) +\&\s-1EVEX\s0 instructions. \fB\-mevexwig=\fR\fI0\fR will encode \s-1WIG +EVEX\s0 instructions with evex.w = 0, which is the default. +\&\fB\-mevexwig=\fR\fI1\fR will encode \s-1WIG EVEX\s0 instructions with +evex.w = 1. .IP "\fB\-mmnemonic=\fR\fIatt\fR" 4 .IX Item "-mmnemonic=att" .PD 0 @@ -1046,6 +1104,10 @@ take precedent. .IX Item "-mnaked-reg" This opetion specifies that registers don't require a \fB%\fR prefix. The \f(CW\*(C`.att_syntax\*(C'\fR and \f(CW\*(C`.intel_syntax\*(C'\fR directives will take precedent. +.IP "\fB\-madd\-bnd\-prefix\fR" 4 +.IX Item "-madd-bnd-prefix" +This option forces the assembler to add \s-1BND\s0 prefix to all branches, even +if such prefix was not explicitly specified in the source code. .PP The following options are available when as is configured for the Intel 80960 processor. @@ -1177,19 +1239,19 @@ The following options are available when as is configured for a PowerPC processor. .IP "\fB\-a32\fR" 4 .IX Item "-a32" -Generate \s-1ELF32\s0 or \s-1XCOFF32\s0. +Generate \s-1ELF32\s0 or \s-1XCOFF32.\s0 .IP "\fB\-a64\fR" 4 .IX Item "-a64" -Generate \s-1ELF64\s0 or \s-1XCOFF64\s0. +Generate \s-1ELF64\s0 or \s-1XCOFF64.\s0 .IP "\fB\-K \s-1PIC\s0\fR" 4 .IX Item "-K PIC" Set \s-1EF_PPC_RELOCATABLE_LIB\s0 in \s-1ELF\s0 flags. .IP "\fB\-mpwrx | \-mpwr2\fR" 4 .IX Item "-mpwrx | -mpwr2" -Generate code for \s-1POWER/2\s0 (\s-1RIOS2\s0). +Generate code for \s-1POWER/2 \s0(\s-1RIOS2\s0). .IP "\fB\-mpwr\fR" 4 .IX Item "-mpwr" -Generate code for \s-1POWER\s0 (\s-1RIOS1\s0) +Generate code for \s-1POWER \s0(\s-1RIOS1\s0) .IP "\fB\-m601\fR" 4 .IX Item "-m601" Generate code for PowerPC 601. @@ -1434,7 +1496,7 @@ Xtensa processor. Control the treatment of literal pools. The default is \&\fB\-\-no\-text\-section\-literals\fR, which places literals in separate sections in the output file. This allows the literal pool to be -placed in a data \s-1RAM/ROM\s0. With \fB\-\-text\-section\-literals\fR, the +placed in a data \s-1RAM/ROM. \s0 With \fB\-\-text\-section\-literals\fR, the literals are interspersed in the text section in order to keep them as close as possible to their references. This may be necessary for large assembly files, where the literals would otherwise be out of range of the @@ -1530,9 +1592,7 @@ Treat undocumented Z80 instructions that do not work on R800 as errors. \&\fIgcc\fR\|(1), \fIld\fR\|(1), and the Info entries for \fIbinutils\fR and \fIld\fR. .SH "COPYRIGHT" .IX Header "COPYRIGHT" -Copyright (c) 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, -2000, 2001, 2002, 2006, 2007, 2008, 2009, 2010, 2011 Free Software Foundation, -Inc. +Copyright (c) 1991\-2013 Free Software Foundation, Inc. .PP Permission is granted to copy, distribute and/or modify this document under the terms of the \s-1GNU\s0 Free Documentation License, Version 1.3 |