diff options
Diffstat (limited to 'share/man/man1/x86_64-w64-mingw32-g++.1')
| -rw-r--r-- | share/man/man1/x86_64-w64-mingw32-g++.1 | 266 |
1 files changed, 133 insertions, 133 deletions
diff --git a/share/man/man1/x86_64-w64-mingw32-g++.1 b/share/man/man1/x86_64-w64-mingw32-g++.1 index c683289e..b3630d2a 100644 --- a/share/man/man1/x86_64-w64-mingw32-g++.1 +++ b/share/man/man1/x86_64-w64-mingw32-g++.1 @@ -1,4 +1,4 @@ -.\" Automatically generated by Pod::Man 4.10 (Pod::Simple 3.35) +.\" Automatically generated by Pod::Man 2.27 (Pod::Simple 3.28) .\" .\" Standard preamble: .\" ======================================================================== @@ -46,7 +46,7 @@ .ie \n(.g .ds Aq \(aq .el .ds Aq ' .\" -.\" If the F register is >0, we'll generate index entries on stderr for +.\" If the F register is turned on, we'll generate index entries on stderr for .\" titles (.TH), headers (.SH), subsections (.SS), items (.Ip), and index .\" entries marked with X<> in POD. Of course, you'll have to process the .\" output yourself in some meaningful fashion. @@ -56,12 +56,12 @@ .. .nr rF 0 .if \n(.g .if rF .nr rF 1 -.if (\n(rF:(\n(.g==0)) \{\ -. if \nF \{\ +.if (\n(rF:(\n(.g==0)) \{ +. if \nF \{ . de IX . tm Index:\\$1\t\\n%\t"\\$2" .. -. if !\nF==2 \{\ +. if !\nF==2 \{ . nr % 0 . nr F 2 . \} @@ -1535,7 +1535,7 @@ In C mode, this is equivalent to \fB\-std=c90\fR. In \*(C+ mode, it is equivalent to \fB\-std=c++98\fR. .Sp This turns off certain features of \s-1GCC\s0 that are incompatible with \s-1ISO -C90\s0 (when compiling C code), or of standard \*(C+ (when compiling \*(C+ code), +C90 \s0(when compiling C code), or of standard \*(C+ (when compiling \*(C+ code), such as the \f(CW\*(C`asm\*(C'\fR and \f(CW\*(C`typeof\*(C'\fR keywords, and predefined macros such as \f(CW\*(C`unix\*(C'\fR and \f(CW\*(C`vax\*(C'\fR that identify the type of system you are using. It also enables the undesirable and @@ -1562,7 +1562,7 @@ from declaring certain functions or defining certain macros that the programs that might use these names for other things. .Sp Functions that are normally built in but do not have semantics -defined by \s-1ISO C\s0 (such as \f(CW\*(C`alloca\*(C'\fR and \f(CW\*(C`ffs\*(C'\fR) are not built-in +defined by \s-1ISO C \s0(such as \f(CW\*(C`alloca\*(C'\fR and \f(CW\*(C`ffs\*(C'\fR) are not built-in functions when \fB\-ansi\fR is used. .IP "\fB\-std=\fR" 4 .IX Item "-std=" @@ -1612,7 +1612,7 @@ with \s-1ISO C90\s0 are disabled). Same as \fB\-ansi\fR for C code. .IP "\fBiso9899:199x\fR" 4 .IX Item "iso9899:199x" .PD -\&\s-1ISO C99.\s0 Note that this standard is not yet fully supported; see +\&\s-1ISO C99. \s0 Note that this standard is not yet fully supported; see <\fBhttp://gcc.gnu.org/c99status.html\fR> for more information. The names \fBc9x\fR and \fBiso9899:199x\fR are deprecated. .IP "\fBc11\fR" 4 @@ -1632,7 +1632,7 @@ deprecated. .IP "\fBgnu89\fR" 4 .IX Item "gnu89" .PD -\&\s-1GNU\s0 dialect of \s-1ISO C90\s0 (including some C99 features). This +\&\s-1GNU\s0 dialect of \s-1ISO C90 \s0(including some C99 features). This is the default for C code. .IP "\fBgnu99\fR" 4 .IX Item "gnu99" @@ -1640,7 +1640,7 @@ is the default for C code. .IP "\fBgnu9x\fR" 4 .IX Item "gnu9x" .PD -\&\s-1GNU\s0 dialect of \s-1ISO C99.\s0 When \s-1ISO C99\s0 is fully implemented in \s-1GCC,\s0 +\&\s-1GNU\s0 dialect of \s-1ISO C99. \s0 When \s-1ISO C99\s0 is fully implemented in \s-1GCC,\s0 this will become the default. The name \fBgnu9x\fR is deprecated. .IP "\fBgnu11\fR" 4 .IX Item "gnu11" @@ -1648,7 +1648,7 @@ this will become the default. The name \fBgnu9x\fR is deprecated. .IP "\fBgnu1x\fR" 4 .IX Item "gnu1x" .PD -\&\s-1GNU\s0 dialect of \s-1ISO C11.\s0 Support is incomplete and experimental. The +\&\s-1GNU\s0 dialect of \s-1ISO C11. \s0 Support is incomplete and experimental. The name \fBgnu1x\fR is deprecated. .IP "\fBc++98\fR" 4 .IX Item "c++98" @@ -1710,7 +1710,7 @@ C99 mode. Using this option is roughly equivalent to adding the The option \fB\-fno\-gnu89\-inline\fR explicitly tells \s-1GCC\s0 to use the C99 semantics for \f(CW\*(C`inline\*(C'\fR when in C99 or gnu99 mode (i.e., it specifies the default behavior). This option was first supported in -\&\s-1GCC 4.3.\s0 This option is not supported in \fB\-std=c90\fR or +\&\s-1GCC 4.3. \s0 This option is not supported in \fB\-std=c90\fR or \&\fB\-std=gnu90\fR mode. .Sp The preprocessor macros \f(CW\*(C`_\|_GNUC_GNU_INLINE_\|_\*(C'\fR and @@ -1929,7 +1929,7 @@ language supported by \s-1GCC.\s0 Here is a list of options that are \fIonly\fR for compiling \*(C+ programs: .IP "\fB\-fabi\-version=\fR\fIn\fR" 4 .IX Item "-fabi-version=n" -Use version \fIn\fR of the \*(C+ \s-1ABI.\s0 The default is version 2. +Use version \fIn\fR of the \*(C+ \s-1ABI. \s0 The default is version 2. .Sp Version 0 refers to the version conforming most closely to the \*(C+ \s-1ABI\s0 specification. Therefore, the \s-1ABI\s0 obtained using version 0 @@ -1966,7 +1966,7 @@ Check that the pointer returned by \f(CW\*(C`operator new\*(C'\fR is non-null before attempting to modify the storage allocated. This check is normally unnecessary because the \*(C+ standard specifies that \&\f(CW\*(C`operator new\*(C'\fR only returns \f(CW0\fR if it is declared -\&\fB\fBthrow()\fB\fR, in which case the compiler always checks the +\&\fB\f(BIthrow()\fB\fR, in which case the compiler always checks the return value even without this option. In all other cases, when \&\f(CW\*(C`operator new\*(C'\fR has a non-empty exception specification, memory exhaustion is signalled by throwing \f(CW\*(C`std::bad_alloc\*(C'\fR. See also @@ -2093,7 +2093,7 @@ int and getting a pointer to member function via non-standard syntax. .IP "\fB\-fno\-nonansi\-builtins\fR" 4 .IX Item "-fno-nonansi-builtins" Disable built-in declarations of functions that are not mandated by -\&\s-1ANSI/ISO C.\s0 These include \f(CW\*(C`ffs\*(C'\fR, \f(CW\*(C`alloca\*(C'\fR, \f(CW\*(C`_exit\*(C'\fR, +\&\s-1ANSI/ISO C. \s0 These include \f(CW\*(C`ffs\*(C'\fR, \f(CW\*(C`alloca\*(C'\fR, \f(CW\*(C`_exit\*(C'\fR, \&\f(CW\*(C`index\*(C'\fR, \f(CW\*(C`bzero\*(C'\fR, \f(CW\*(C`conjf\*(C'\fR, and other related functions. .IP "\fB\-fnothrow\-opt\fR" 4 .IX Item "-fnothrow-opt" @@ -2198,7 +2198,7 @@ are taken in different shared objects. The effect of this is that \s-1GCC\s0 may, effectively, mark inline methods with \&\f(CW\*(C`_\|_attribute_\|_ ((visibility ("hidden")))\*(C'\fR so that they do not appear in the export table of a \s-1DSO\s0 and do not require a \s-1PLT\s0 indirection -when used within the \s-1DSO.\s0 Enabling this option can have a dramatic effect +when used within the \s-1DSO. \s0 Enabling this option can have a dramatic effect on load and link times of a \s-1DSO\s0 as it massively reduces the size of the dynamic export table when the library makes heavy use of templates. .Sp @@ -2271,7 +2271,7 @@ inlined by default. .IP "\fB\-Wabi\fR (C, Objective-C, \*(C+ and Objective\-\*(C+ only)" 4 .IX Item "-Wabi (C, Objective-C, and Objective- only)" Warn when G++ generates code that is probably not compatible with the -vendor-neutral \*(C+ \s-1ABI.\s0 Although an effort has been made to warn about +vendor-neutral \*(C+ \s-1ABI. \s0 Although an effort has been made to warn about all such cases, there are probably some cases that are not warned about, even though G++ is generating incompatible code. There may also be cases where warnings are emitted even though the code that is generated @@ -2449,7 +2449,7 @@ ill-formed in \s-1SFINAE\s0 context. .IX Item "-Wnoexcept ( and Objective- only)" Warn when a noexcept-expression evaluates to false because of a call to a function that does not have a non-throwing exception -specification (i.e. \fB\fBthrow()\fB\fR or \fBnoexcept\fR) but is known by +specification (i.e. \fB\f(BIthrow()\fB\fR or \fBnoexcept\fR) but is known by the compiler to never throw an exception. .IP "\fB\-Wnon\-virtual\-dtor\fR (\*(C+ and Objective\-\*(C+ only)" 4 .IX Item "-Wnon-virtual-dtor ( and Objective- only)" @@ -2622,7 +2622,7 @@ runtime. This is the default for most types of systems. .IP "\fB\-fnext\-runtime\fR" 4 .IX Item "-fnext-runtime" Generate output compatible with the NeXT runtime. This is the default -for NeXT-based systems, including Darwin and Mac \s-1OS X.\s0 The macro +for NeXT-based systems, including Darwin and Mac \s-1OS X. \s0 The macro \&\f(CW\*(C`_\|_NEXT_RUNTIME_\|_\*(C'\fR is predefined if (and only if) this option is used. .IP "\fB\-fno\-nil\-receivers\fR" 4 @@ -2639,7 +2639,7 @@ This option is currently supported only for the NeXT runtime. In that case, Version 0 is the traditional (32\-bit) \s-1ABI\s0 without support for properties and other Objective-C 2.0 additions. Version 1 is the traditional (32\-bit) \s-1ABI\s0 with support for properties and other -Objective-C 2.0 additions. Version 2 is the modern (64\-bit) \s-1ABI.\s0 If +Objective-C 2.0 additions. Version 2 is the modern (64\-bit) \s-1ABI. \s0 If nothing is specified, the default is Version 0 on 32\-bit target machines, and Version 2 on 64\-bit target machines. .IP "\fB\-fobjc\-call\-cxx\-cdtors\fR" 4 @@ -2697,7 +2697,7 @@ version of the NeXT runtime \s-1ABI,\s0 is used. .IP "\fB\-fobjc\-std=objc1\fR" 4 .IX Item "-fobjc-std=objc1" Conform to the language syntax of Objective-C 1.0, the language -recognized by \s-1GCC 4.0.\s0 This only affects the Objective-C additions to +recognized by \s-1GCC 4.0. \s0 This only affects the Objective-C additions to the C/\*(C+ language; it does not affect conformance to C/\*(C+ standards, which is controlled by the separate C/\*(C+ dialect option flags. When this option is used with the Objective-C or Objective\-\*(C+ compiler, @@ -2706,8 +2706,8 @@ This is useful if you need to make sure that your Objective-C code can be compiled with older versions of \s-1GCC.\s0 .IP "\fB\-freplace\-objc\-classes\fR" 4 .IX Item "-freplace-objc-classes" -Emit a special marker instructing \fB\fBld\fB\|(1)\fR not to statically link in -the resulting object file, and allow \fB\fBdyld\fB\|(1)\fR to load it in at +Emit a special marker instructing \fB\f(BIld\fB\|(1)\fR not to statically link in +the resulting object file, and allow \fB\f(BIdyld\fB\|(1)\fR to load it in at run time instead. This is used in conjunction with the Fix-and-Continue debugging mode, where the object file in question may be recompiled and dynamically reloaded in the course of program execution, without the need @@ -2791,7 +2791,7 @@ honor these options. .IX Item "-fmessage-length=n" Try to format error messages so that they fit on lines of about \fIn\fR characters. The default is 72 characters for \fBg++\fR and 0 for the rest of -the front ends supported by \s-1GCC.\s0 If \fIn\fR is zero, then no +the front ends supported by \s-1GCC. \s0 If \fIn\fR is zero, then no line-wrapping is done; each error message appears on a single line. .IP "\fB\-fdiagnostics\-show\-location=once\fR" 4 @@ -2894,7 +2894,7 @@ warns that an unrecognized option is present. .PD Issue all the warnings demanded by strict \s-1ISO C\s0 and \s-1ISO \*(C+\s0; reject all programs that use forbidden extensions, and some other -programs that do not follow \s-1ISO C\s0 and \s-1ISO \*(C+.\s0 For \s-1ISO C,\s0 follows the +programs that do not follow \s-1ISO C\s0 and \s-1ISO \*(C+. \s0 For \s-1ISO C,\s0 follows the version of the \s-1ISO C\s0 standard specified by any \fB\-std\fR option used. .Sp Valid \s-1ISO C\s0 and \s-1ISO \*(C+\s0 programs should compile properly with or without @@ -2912,7 +2912,7 @@ these escape routes; application programs should avoid them. Some users try to use \fB\-Wpedantic\fR to check programs for strict \s-1ISO C\s0 conformance. They soon find that it does not do quite what they want: it finds some non-ISO practices, but not all\-\-\-only those for which -\&\s-1ISO C\s0 \fIrequires\fR a diagnostic, and some others for which +\&\s-1ISO C \s0\fIrequires\fR a diagnostic, and some others for which diagnostics have been added. .Sp A feature to report any failure to conform to \s-1ISO C\s0 might be useful in @@ -3503,7 +3503,7 @@ this can happen: .Sp If the value of \f(CW\*(C`y\*(C'\fR is always 1, 2 or 3, then \f(CW\*(C`x\*(C'\fR is always initialized, but \s-1GCC\s0 doesn't know this. To suppress the -warning, you need to provide a default case with \fBassert\fR\|(0) or +warning, you need to provide a default case with \fIassert\fR\|(0) or similar code. .Sp This option also warns when a non-volatile automatic variable might be @@ -3523,7 +3523,7 @@ This warning is enabled by \fB\-Wall\fR or \fB\-Wextra\fR. .IP "\fB\-Wunknown\-pragmas\fR" 4 .IX Item "-Wunknown-pragmas" Warn when a \f(CW\*(C`#pragma\*(C'\fR directive is encountered that is not understood by -\&\s-1GCC.\s0 If this command-line option is used, warnings are even issued +\&\s-1GCC. \s0 If this command-line option is used, warnings are even issued for unknown pragmas in system header files. This is not the case if the warnings are only enabled by the \fB\-Wall\fR command-line option. .IP "\fB\-Wno\-pragmas\fR" 4 @@ -3724,7 +3724,7 @@ probably mistaken. .IP "\fB\-Wtraditional\fR (C and Objective-C only)" 4 .IX Item "-Wtraditional (C and Objective-C only)" Warn about certain constructs that behave differently in traditional and -\&\s-1ISO C.\s0 Also warn about \s-1ISO C\s0 constructs that have no traditional C +\&\s-1ISO C. \s0 Also warn about \s-1ISO C\s0 constructs that have no traditional C equivalent, and/or problematic constructs that should be avoided. .RS 4 .IP "\(bu" 4 @@ -3806,8 +3806,8 @@ except when the same as the default promotion. .IX Item "-Wdeclaration-after-statement (C and Objective-C only)" Warn when a declaration is found after a statement in a block. This construct, known from \*(C+, was introduced with \s-1ISO C99\s0 and is by default -allowed in \s-1GCC.\s0 It is not supported by \s-1ISO C90\s0 and was not supported by -\&\s-1GCC\s0 versions before \s-1GCC 3.0.\s0 +allowed in \s-1GCC. \s0 It is not supported by \s-1ISO C90\s0 and was not supported by +\&\s-1GCC\s0 versions before \s-1GCC 3.0. \s0 .IP "\fB\-Wundef\fR" 4 .IX Item "-Wundef" Warn if an undefined identifier is evaluated in an \fB#if\fR directive. @@ -3908,7 +3908,7 @@ Warn about \s-1ISO C\s0 constructs that are outside of the common subset of .IX Item "-Wc++11-compat ( and Objective- only)" Warn about \*(C+ constructs whose meaning differs between \s-1ISO \*(C+ 1998\s0 and \s-1ISO \*(C+ 2011,\s0 e.g., identifiers in \s-1ISO \*(C+ 1998\s0 that are keywords -in \s-1ISO \*(C+ 2011.\s0 This warning turns on \fB\-Wnarrowing\fR and is +in \s-1ISO \*(C+ 2011. \s0 This warning turns on \fB\-Wnarrowing\fR and is enabled by \fB\-Wall\fR. .IP "\fB\-Wcast\-qual\fR" 4 .IX Item "-Wcast-qual" @@ -4142,7 +4142,7 @@ when applied ensure that two sequences that look the same are turned into the same sequence. \s-1GCC\s0 can warn you if you are using identifiers that have not been normalized; this option controls that warning. .Sp -There are four levels of warning supported by \s-1GCC.\s0 The default is +There are four levels of warning supported by \s-1GCC. \s0 The default is \&\fB\-Wnormalized=nfc\fR, which warns about any identifier that is not in the \s-1ISO 10646 \*(L"C\*(R"\s0 normalized form, \fI\s-1NFC\s0\fR. \s-1NFC\s0 is the recommended form for most uses. @@ -4150,8 +4150,8 @@ recommended form for most uses. Unfortunately, there are some characters allowed in identifiers by \&\s-1ISO C\s0 and \s-1ISO \*(C+\s0 that, when turned into \s-1NFC,\s0 are not allowed in identifiers. That is, there's no way to use these symbols in portable -\&\s-1ISO C\s0 or \*(C+ and have all your identifiers in \s-1NFC.\s0 -\&\fB\-Wnormalized=id\fR suppresses the warning for these characters. +\&\s-1ISO C\s0 or \*(C+ and have all your identifiers in \s-1NFC. +\&\s0\fB\-Wnormalized=id\fR suppresses the warning for these characters. It is hoped that future versions of the standards involved will correct this, which is why this option is not the default. .Sp @@ -4361,7 +4361,7 @@ standard's minimum limit, but very portable programs should avoid using longer strings. .Sp The limit applies \fIafter\fR string constant concatenation, and does -not count the trailing \s-1NUL.\s0 In C90, the limit was 509 characters; in +not count the trailing \s-1NUL. \s0 In C90, the limit was 509 characters; in C99, it was raised to 4095. \*(C+98 does not specify a normative minimum maximum, so we do not diagnose overlength strings in \*(C+. .Sp @@ -4414,7 +4414,7 @@ be useful, this option requires a debugger capable of reading .dwo files. .IP "\fB\-ggdb\fR" 4 .IX Item "-ggdb" -Produce debugging information for use by \s-1GDB.\s0 This means to use the +Produce debugging information for use by \s-1GDB. \s0 This means to use the most expressive format available (\s-1DWARF 2,\s0 stabs, or the native format if neither of those are supported), including \s-1GDB\s0 extensions if at all possible. @@ -4698,7 +4698,7 @@ information describing them as in \fI\fInew\fI\fR instead. .IP "\fB\-fno\-dwarf2\-cfi\-asm\fR" 4 .IX Item "-fno-dwarf2-cfi-asm" Emit \s-1DWARF 2\s0 unwind info as compiler generated \f(CW\*(C`.eh_frame\*(C'\fR section -instead of using \s-1GAS\s0 \f(CW\*(C`.cfi_*\*(C'\fR directives. +instead of using \s-1GAS \s0\f(CW\*(C`.cfi_*\*(C'\fR directives. .IP "\fB\-p\fR" 4 .IX Item "-p" Generate extra code to write profile information suitable for the @@ -5364,7 +5364,7 @@ Enable showing virtual operands for every statement. Enable showing line numbers for statements. .IP "\fBuid\fR" 4 .IX Item "uid" -Enable showing the unique \s-1ID\s0 (\f(CW\*(C`DECL_UID\*(C'\fR) for each variable. +Enable showing the unique \s-1ID \s0(\f(CW\*(C`DECL_UID\*(C'\fR) for each variable. .IP "\fBverbose\fR" 4 .IX Item "verbose" Enable showing the tree dump for each statement. @@ -5442,7 +5442,7 @@ Dump aliasing information for each function. The file name is made by appending \fI.alias\fR to the source file name. .IP "\fBccp\fR" 4 .IX Item "ccp" -Dump each function after \s-1CCP.\s0 The file name is made by appending +Dump each function after \s-1CCP. \s0 The file name is made by appending \&\fI.ccp\fR to the source file name. .IP "\fBstoreccp\fR" 4 .IX Item "storeccp" @@ -6065,7 +6065,7 @@ function calls and pops them all at once. Disabled at levels \fB\-O\fR, \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR. .IP "\fB\-fforward\-propagate\fR" 4 .IX Item "-fforward-propagate" -Perform a forward propagation pass on \s-1RTL.\s0 The pass tries to combine two +Perform a forward propagation pass on \s-1RTL. \s0 The pass tries to combine two instructions and checks if the result can be simplified. If loop unrolling is active, two passes are performed and the second is scheduled after loop unrolling. @@ -6210,7 +6210,7 @@ attribute or declspec In C, emit \f(CW\*(C`static\*(C'\fR functions that are declared \f(CW\*(C`inline\*(C'\fR into the object file, even if the function has been inlined into all of its callers. This switch does not affect functions using the -\&\f(CW\*(C`extern inline\*(C'\fR extension in \s-1GNU C90.\s0 In \*(C+, emit any and all +\&\f(CW\*(C`extern inline\*(C'\fR extension in \s-1GNU C90. \s0 In \*(C+, emit any and all inline functions into the object file. .IP "\fB\-fkeep\-static\-consts\fR" 4 .IX Item "-fkeep-static-consts" @@ -6275,7 +6275,7 @@ The default is \fB\-ffunction\-cse\fR .IP "\fB\-fno\-zero\-initialized\-in\-bss\fR" 4 .IX Item "-fno-zero-initialized-in-bss" If the target supports a \s-1BSS\s0 section, \s-1GCC\s0 by default puts variables that -are initialized to zero into \s-1BSS.\s0 This can save space in the resulting +are initialized to zero into \s-1BSS. \s0 This can save space in the resulting code. .Sp This option turns off this behavior because some programs explicitly @@ -6983,7 +6983,7 @@ infrastructure. Enable the identity transformation for graphite. For every SCoP we generate the polyhedral representation and transform it back to gimple. Using \&\fB\-fgraphite\-identity\fR we can check the costs or benefits of the -\&\s-1GIMPLE\s0 \-> \s-1GRAPHITE\s0 \-> \s-1GIMPLE\s0 transformation. Some minimal optimizations +\&\s-1GIMPLE \-\s0> \s-1GRAPHITE \-\s0> \s-1GIMPLE\s0 transformation. Some minimal optimizations are also performed by the code generator CLooG, like index splitting and dead code elimination in loops. .IP "\fB\-floop\-nest\-optimize\fR" 4 @@ -7504,7 +7504,7 @@ information. .IP "\fB\-flto[=\fR\fIn\fR\fB]\fR" 4 .IX Item "-flto[=n]" This option runs the standard link-time optimizer. When invoked -with source code, it generates \s-1GIMPLE\s0 (one of \s-1GCC\s0's internal +with source code, it generates \s-1GIMPLE \s0(one of \s-1GCC\s0's internal representations) and writes it to special \s-1ELF\s0 sections in the object file. When the object files are linked together, all the function bodies are read from these \s-1ELF\s0 sections and instantiated as if they @@ -7830,8 +7830,8 @@ them to store all pertinent intermediate computations into variables. .IP "\fB\-fexcess\-precision=\fR\fIstyle\fR" 4 .IX Item "-fexcess-precision=style" This option allows further control over excess precision on machines -where floating-point registers have more precision than the \s-1IEEE\s0 -\&\f(CW\*(C`float\*(C'\fR and \f(CW\*(C`double\*(C'\fR types and the processor does not +where floating-point registers have more precision than the \s-1IEEE +\&\s0\f(CW\*(C`float\*(C'\fR and \f(CW\*(C`double\*(C'\fR types and the processor does not support operations rounding to those types. By default, \&\fB\-fexcess\-precision=fast\fR is in effect; this means that operations are carried out in the precision of the registers and that @@ -8005,8 +8005,8 @@ whether the result of a complex multiplication or division is \f(CW\*(C`NaN default is \fB\-fno\-cx\-limited\-range\fR, but is enabled by \&\fB\-ffast\-math\fR. .Sp -This option controls the default setting of the \s-1ISO C99\s0 -\&\f(CW\*(C`CX_LIMITED_RANGE\*(C'\fR pragma. Nevertheless, the option applies to +This option controls the default setting of the \s-1ISO C99 +\&\s0\f(CW\*(C`CX_LIMITED_RANGE\*(C'\fR pragma. Nevertheless, the option applies to all languages. .IP "\fB\-fcx\-fortran\-rules\fR" 4 .IX Item "-fcx-fortran-rules" @@ -8612,7 +8612,7 @@ Tuning this may improve compilation speed; it has no effect on code generation. .Sp The default is 30% + 70% * (\s-1RAM/1GB\s0) with an upper bound of 100% when -\&\s-1RAM\s0 >= 1GB. If \f(CW\*(C`getrlimit\*(C'\fR is available, the notion of \*(L"\s-1RAM\*(R"\s0 is +\&\s-1RAM \s0>= 1GB. If \f(CW\*(C`getrlimit\*(C'\fR is available, the notion of \*(L"\s-1RAM\*(R"\s0 is the smallest of actual \s-1RAM\s0 and \f(CW\*(C`RLIMIT_DATA\*(C'\fR or \f(CW\*(C`RLIMIT_AS\*(C'\fR. If \&\s-1GCC\s0 is not able to calculate \s-1RAM\s0 on a particular platform, the lower bound of 30% is used. Setting this parameter and @@ -8919,7 +8919,7 @@ The number of partitions should exceed the number of CPUs used for compilation. The default value is 32. .IP "\fBlto-minpartition\fR" 4 .IX Item "lto-minpartition" -Size of minimal partition for \s-1WHOPR\s0 (in estimated instructions). +Size of minimal partition for \s-1WHOPR \s0(in estimated instructions). This prevents expenses of splitting very small programs into too many partitions. .IP "\fBcxx-max-namespaces-for-diagnostic-help\fR" 4 @@ -9111,7 +9111,7 @@ get trigraph conversion without warnings, but get the other .IP "\fB\-Wtraditional\fR" 4 .IX Item "-Wtraditional" Warn about certain constructs that behave differently in traditional and -\&\s-1ISO C.\s0 Also warn about \s-1ISO C\s0 constructs that have no traditional C +\&\s-1ISO C. \s0 Also warn about \s-1ISO C\s0 constructs that have no traditional C equivalent, and problematic constructs which should be avoided. .IP "\fB\-Wundef\fR" 4 .IX Item "-Wundef" @@ -9307,7 +9307,7 @@ When \fB\-fpreprocessed\fR is in use, \s-1GCC\s0 recognizes this \f(CW\*(C`#prag and loads the \s-1PCH.\s0 .Sp This option is off by default, because the resulting preprocessed output -is only really suitable as input to \s-1GCC.\s0 It is switched on by +is only really suitable as input to \s-1GCC. \s0 It is switched on by \&\fB\-save\-temps\fR. .Sp You should not write this \f(CW\*(C`#pragma\*(C'\fR in your own code, but it is @@ -9580,7 +9580,7 @@ line. If the value is less than 1 or greater than 100, the option is ignored. The default is 8. .IP "\fB\-fdebug\-cpp\fR" 4 .IX Item "-fdebug-cpp" -This option is only useful for debugging \s-1GCC.\s0 When used with +This option is only useful for debugging \s-1GCC. \s0 When used with \&\fB\-E\fR, dumps debugging information about location maps. Every token in the output is preceded by the dump of the map its location belongs to. The dump of the map holding the location of a token would @@ -9613,7 +9613,7 @@ Note that \-ftrack\-macro\-expansion=2 is activated by default. .IP "\fB\-fexec\-charset=\fR\fIcharset\fR" 4 .IX Item "-fexec-charset=charset" Set the execution character set, used for string and character -constants. The default is \s-1UTF\-8.\s0 \fIcharset\fR can be any encoding +constants. The default is \s-1UTF\-8. \s0\fIcharset\fR can be any encoding supported by the system's \f(CW\*(C`iconv\*(C'\fR library routine. .IP "\fB\-fwide\-exec\-charset=\fR\fIcharset\fR" 4 .IX Item "-fwide-exec-charset=charset" @@ -9626,9 +9626,9 @@ problems with encodings that do not fit exactly in \f(CW\*(C`wchar_t\*(C'\fR. .IP "\fB\-finput\-charset=\fR\fIcharset\fR" 4 .IX Item "-finput-charset=charset" Set the input character set, used for translation from the character -set of the input file to the source character set used by \s-1GCC.\s0 If the +set of the input file to the source character set used by \s-1GCC. \s0 If the locale does not specify, or \s-1GCC\s0 cannot get this information from the -locale, the default is \s-1UTF\-8.\s0 This can be overridden by either the locale +locale, the default is \s-1UTF\-8. \s0 This can be overridden by either the locale or this command line option. Currently the command line option takes precedence if there's a conflict. \fIcharset\fR can be any encoding supported by the system's \f(CW\*(C`iconv\*(C'\fR library routine. @@ -10447,7 +10447,7 @@ These \fB\-m\fR options are defined for Advanced \s-1RISC\s0 Machines (\s-1ARM\s architectures: .IP "\fB\-mabi=\fR\fIname\fR" 4 .IX Item "-mabi=name" -Generate code for the specified \s-1ABI.\s0 Permissible values are: \fBapcs-gnu\fR, +Generate code for the specified \s-1ABI. \s0 Permissible values are: \fBapcs-gnu\fR, \&\fBatpcs\fR, \fBaapcs\fR, \fBaapcs-linux\fR and \fBiwmmxt\fR. .IP "\fB\-mapcs\-frame\fR" 4 .IX Item "-mapcs-frame" @@ -10854,8 +10854,8 @@ The default for this option is@tie{}\f(CW\*(C`avr2\*(C'\fR. .ie n .IP """avrxmega5""" 4 .el .IP "\f(CWavrxmega5\fR" 4 .IX Item "avrxmega5" -\&\*(L"\s-1XMEGA\*(R"\s0 devices with more than 64@tie{}KiB and up to 128@tie{}KiB of program memory and more than 64@tie{}KiB of \s-1RAM.\s0 -\&\fImcu\fR\f(CW@tie\fR{}= \f(CW\*(C`atxmega64a1\*(C'\fR, \f(CW\*(C`atxmega64a1u\*(C'\fR. +\&\*(L"\s-1XMEGA\*(R"\s0 devices with more than 64@tie{}KiB and up to 128@tie{}KiB of program memory and more than 64@tie{}KiB of \s-1RAM. +\&\s0\fImcu\fR\f(CW@tie\fR{}= \f(CW\*(C`atxmega64a1\*(C'\fR, \f(CW\*(C`atxmega64a1u\*(C'\fR. .ie n .IP """avrxmega6""" 4 .el .IP "\f(CWavrxmega6\fR" 4 .IX Item "avrxmega6" @@ -10864,8 +10864,8 @@ The default for this option is@tie{}\f(CW\*(C`avr2\*(C'\fR. .ie n .IP """avrxmega7""" 4 .el .IP "\f(CWavrxmega7\fR" 4 .IX Item "avrxmega7" -\&\*(L"\s-1XMEGA\*(R"\s0 devices with more than 128@tie{}KiB of program memory and more than 64@tie{}KiB of \s-1RAM.\s0 -\&\fImcu\fR\f(CW@tie\fR{}= \f(CW\*(C`atxmega128a1\*(C'\fR, \f(CW\*(C`atxmega128a1u\*(C'\fR, \f(CW\*(C`atxmega128a4u\*(C'\fR. +\&\*(L"\s-1XMEGA\*(R"\s0 devices with more than 128@tie{}KiB of program memory and more than 64@tie{}KiB of \s-1RAM. +\&\s0\fImcu\fR\f(CW@tie\fR{}= \f(CW\*(C`atxmega128a1\*(C'\fR, \f(CW\*(C`atxmega128a1u\*(C'\fR, \f(CW\*(C`atxmega128a4u\*(C'\fR. .ie n .IP """avr1""" 4 .el .IP "\f(CWavr1\fR" 4 .IX Item "avr1" @@ -11164,7 +11164,7 @@ for \fImcu\fR=\f(CW\*(C`avr2\*(C'\fR, \f(CW\*(C`avr25\*(C'\fR, \f(CW\*(C`avr3\*( If \fImcu\fR specifies a device, this built-in macro is set accordingly. For example, with \f(CW\*(C`\-mmcu=atmega8\*(C'\fR the macro will be defined to \f(CW4\fR. -.ie n .IP """_\|_AVR_\fIDevice\fP_\|_""" 4 +.ie n .IP """_\|_AVR_\f(CIDevice\f(CW_\|_""" 4 .el .IP "\f(CW_\|_AVR_\f(CIDevice\f(CW_\|_\fR" 4 .IX Item "__AVR_Device__" Setting \f(CW\*(C`\-mmcu=\f(CIdevice\f(CW\*(C'\fR defines this built-in macro which reflects @@ -11249,7 +11249,7 @@ The definition of these macros is affected by \f(CW\*(C`\-mtiny\-stack\*(C'\fR. .el .IP "\f(CW_\|_AVR_SP8_\|_\fR" 4 .IX Item "__AVR_SP8__" .PD -The device has the \s-1SPH\s0 (high part of stack pointer) special function +The device has the \s-1SPH \s0(high part of stack pointer) special function register or has an 8\-bit stack pointer, respectively. The definition of these macros is affected by \f(CW\*(C`\-mmcu=\*(C'\fR and in the cases of \f(CW\*(C`\-mmcu=avr2\*(C'\fR and \f(CW\*(C`\-mmcu=avr25\*(C'\fR also @@ -11287,7 +11287,7 @@ instructions because of a hardware erratum. Skip instructions are \&\f(CW\*(C`SBRS\*(C'\fR, \f(CW\*(C`SBRC\*(C'\fR, \f(CW\*(C`SBIS\*(C'\fR, \f(CW\*(C`SBIC\*(C'\fR and \f(CW\*(C`CPSE\*(C'\fR. The second macro is only defined if \f(CW\*(C`_\|_AVR_HAVE_JMP_CALL_\|_\*(C'\fR is also set. -.ie n .IP """_\|_AVR_SFR_OFFSET_\|_=\fIoffset\fP""" 4 +.ie n .IP """_\|_AVR_SFR_OFFSET_\|_=\f(CIoffset\f(CW""" 4 .el .IP "\f(CW_\|_AVR_SFR_OFFSET_\|_=\f(CIoffset\f(CW\fR" 4 .IX Item "__AVR_SFR_OFFSET__=offset" Instructions that can address I/O special function registers directly @@ -11623,7 +11623,7 @@ or storage for local variables needs to be allocated. With \fB\-fpic\fR and \fB\-fPIC\fR, don't generate (do generate) instruction sequences that load addresses for functions from the \s-1PLT\s0 part of the \s-1GOT\s0 rather than (traditional on other architectures) calls to the -\&\s-1PLT.\s0 The default is \fB\-mgotplt\fR. +\&\s-1PLT. \s0 The default is \fB\-mgotplt\fR. .IP "\fB\-melf\fR" 4 .IX Item "-melf" Legacy no-op option only recognized with the cris-axis-elf and @@ -11789,7 +11789,7 @@ are provided for backwards compatibility. .IP "\fB\-all_load\fR" 4 .IX Item "-all_load" Loads all members of static archive libraries. -See man \fBld\fR\|(1) for more information. +See man \fIld\fR\|(1) for more information. .IP "\fB\-arch_errors_fatal\fR" 4 .IX Item "-arch_errors_fatal" Cause the errors having to do with files that have the wrong architecture @@ -11801,11 +11801,11 @@ bind all undefined references when the file is loaded or launched. .IP "\fB\-bundle\fR" 4 .IX Item "-bundle" Produce a Mach-o bundle format file. -See man \fBld\fR\|(1) for more information. +See man \fIld\fR\|(1) for more information. .IP "\fB\-bundle_loader\fR \fIexecutable\fR" 4 .IX Item "-bundle_loader executable" This option specifies the \fIexecutable\fR that will load the build -output file being linked. See man \fBld\fR\|(1) for more information. +output file being linked. See man \fIld\fR\|(1) for more information. .IP "\fB\-dynamiclib\fR" 4 .IX Item "-dynamiclib" When passed this option, \s-1GCC\s0 produces a dynamic library instead of @@ -11989,7 +11989,7 @@ compilers call this option \fB\-ieee_with_no_inexact\fR. .IP "\fB\-mieee\-with\-inexact\fR" 4 .IX Item "-mieee-with-inexact" This is like \fB\-mieee\fR except the generated code also maintains -the \s-1IEEE\s0 \fIinexact-flag\fR. Turning on this option causes the +the \s-1IEEE \s0\fIinexact-flag\fR. Turning on this option causes the generated code to implement fully-compliant \s-1IEEE\s0 math. In addition to \&\f(CW\*(C`_IEEE_FP\*(C'\fR, \f(CW\*(C`_IEEE_FP_EXACT\*(C'\fR is defined as a preprocessor macro. On some Alpha implementations the resulting code may execute @@ -12594,7 +12594,7 @@ These \fB\-m\fR options are defined for the \s-1HPPA\s0 family of computers: .IP "\fB\-march=\fR\fIarchitecture-type\fR" 4 .IX Item "-march=architecture-type" Generate code for the specified architecture. The choices for -\&\fIarchitecture-type\fR are \fB1.0\fR for \s-1PA 1.0,\s0 \fB1.1\fR for \s-1PA +\&\fIarchitecture-type\fR are \fB1.0\fR for \s-1PA 1.0, \s0\fB1.1\fR for \s-1PA 1.1,\s0 and \fB2.0\fR for \s-1PA 2.0\s0 processors. Refer to \&\fI/usr/lib/sched.models\fR on an HP-UX system to determine the proper architecture option for your machine. Code compiled for lower numbered @@ -12689,13 +12689,13 @@ library that comes with \s-1GCC,\s0 with \fB\-msoft\-float\fR in order for this to work. .IP "\fB\-msio\fR" 4 .IX Item "-msio" -Generate the predefine, \f(CW\*(C`_SIO\*(C'\fR, for server \s-1IO.\s0 The default is +Generate the predefine, \f(CW\*(C`_SIO\*(C'\fR, for server \s-1IO. \s0 The default is \&\fB\-mwsio\fR. This generates the predefines, \f(CW\*(C`_\|_hp9000s700\*(C'\fR, -\&\f(CW\*(C`_\|_hp9000s700_\|_\*(C'\fR and \f(CW\*(C`_WSIO\*(C'\fR, for workstation \s-1IO.\s0 These +\&\f(CW\*(C`_\|_hp9000s700_\|_\*(C'\fR and \f(CW\*(C`_WSIO\*(C'\fR, for workstation \s-1IO. \s0 These options are available under HP-UX and HI-UX. .IP "\fB\-mgnu\-ld\fR" 4 .IX Item "-mgnu-ld" -Use options specific to \s-1GNU\s0 \fBld\fR. +Use options specific to \s-1GNU \s0\fBld\fR. This passes \fB\-shared\fR to \fBld\fR when building a shared library. It is the default when \s-1GCC\s0 is configured, explicitly or implicitly, with the \s-1GNU\s0 linker. This option does not @@ -12708,7 +12708,7 @@ using \fBwhich `gcc \-print\-prog\-name=ld`\fR. This option is only available on the 64\-bit HP-UX \s-1GCC,\s0 i.e. configured with \fBhppa*64*\-*\-hpux*\fR. .IP "\fB\-mhp\-ld\fR" 4 .IX Item "-mhp-ld" -Use options specific to \s-1HP\s0 \fBld\fR. +Use options specific to \s-1HP \s0\fBld\fR. This passes \fB\-b\fR to \fBld\fR when building a shared library and passes \fB+Accept TypeMismatch\fR to \fBld\fR on all links. It is the default when \s-1GCC\s0 is configured, explicitly or @@ -12823,7 +12823,7 @@ of the selected instruction set. Original Intel i386 \s-1CPU.\s0 .IP "\fBi486\fR" 4 .IX Item "i486" -Intel i486 \s-1CPU.\s0 (No scheduling is implemented for this chip.) +Intel i486 \s-1CPU. \s0(No scheduling is implemented for this chip.) .IP "\fBi586\fR" 4 .IX Item "i586" .PD 0 @@ -13000,7 +13000,7 @@ instruction set support. implemented for this chip.) .IP "\fBc3\-2\fR" 4 .IX Item "c3-2" -\&\s-1VIA C3\-2\s0 (Nehemiah/C5XL) \s-1CPU\s0 with \s-1MMX\s0 and \s-1SSE\s0 instruction set support. +\&\s-1VIA C3\-2 \s0(Nehemiah/C5XL) \s-1CPU\s0 with \s-1MMX\s0 and \s-1SSE\s0 instruction set support. (No scheduling is implemented for this chip.) .IP "\fBgeode\fR" 4 @@ -13132,7 +13132,7 @@ Do not use the \s-1FPU\s0 registers for return values of functions. .Sp The usual calling convention has functions return values of types \&\f(CW\*(C`float\*(C'\fR and \f(CW\*(C`double\*(C'\fR in an \s-1FPU\s0 register, even if there -is no \s-1FPU.\s0 The idea is that the operating system should emulate +is no \s-1FPU. \s0 The idea is that the operating system should emulate an \s-1FPU.\s0 .Sp The option \fB\-mno\-fp\-ret\-in\-387\fR causes such values to be returned @@ -13593,7 +13593,7 @@ external library. Supported values for \fItype\fR are \fBsvml\fR for the Intel short vector math library and \fBacml\fR for the \s-1AMD\s0 math core library. To use this option, both \fB\-ftree\-vectorize\fR and -\&\fB\-funsafe\-math\-optimizations\fR have to be enabled, and an \s-1SVML\s0 or \s-1ACML\s0 +\&\fB\-funsafe\-math\-optimizations\fR have to be enabled, and an \s-1SVML\s0 or \s-1ACML \s0 ABI-compatible library must be specified at link time. .Sp \&\s-1GCC\s0 currently emits calls to \f(CW\*(C`vmldExp2\*(C'\fR, @@ -13616,7 +13616,7 @@ when \fB\-mveclibabi=acml\fR is used. .IX Item "-mabi=name" Generate code for the specified calling convention. Permissible values are \fBsysv\fR for the \s-1ABI\s0 used on GNU/Linux and other systems, and -\&\fBms\fR for the Microsoft \s-1ABI.\s0 The default is to use the Microsoft +\&\fBms\fR for the Microsoft \s-1ABI. \s0 The default is to use the Microsoft \&\s-1ABI\s0 when targeting Microsoft Windows and the SysV \s-1ABI\s0 on all other systems. You can control this behavior for a specific function by using the function attribute \fBms_abi\fR/\fBsysv_abi\fR. @@ -14464,7 +14464,7 @@ have to be emulated by software on the 68060. Use this option if your 68060 does not have code to emulate those instructions. .IP "\fB\-mcpu32\fR" 4 .IX Item "-mcpu32" -Generate output for a \s-1CPU32.\s0 This is the default +Generate output for a \s-1CPU32. \s0 This is the default when the compiler is configured for CPU32\-based systems. It is equivalent to \fB\-march=cpu32\fR. .Sp @@ -14473,7 +14473,7 @@ Use this option for microcontrollers with a 68336, 68340, 68341, 68349 and 68360. .IP "\fB\-m5200\fR" 4 .IX Item "-m5200" -Generate output for a 520X ColdFire \s-1CPU.\s0 This is the default +Generate output for a 520X ColdFire \s-1CPU. \s0 This is the default when the compiler is configured for 520X\-based systems. It is equivalent to \fB\-mcpu=5206\fR, and is now deprecated in favor of that option. @@ -14482,7 +14482,7 @@ Use this option for microcontroller with a 5200 core, including the \s-1MCF5202, MCF5203, MCF5204\s0 and \s-1MCF5206.\s0 .IP "\fB\-m5206e\fR" 4 .IX Item "-m5206e" -Generate output for a 5206e ColdFire \s-1CPU.\s0 The option is now +Generate output for a 5206e ColdFire \s-1CPU. \s0 The option is now deprecated in favor of the equivalent \fB\-mcpu=5206e\fR. .IP "\fB\-m528x\fR" 4 .IX Item "-m528x" @@ -14491,15 +14491,15 @@ The option is now deprecated in favor of the equivalent \&\fB\-mcpu=528x\fR. .IP "\fB\-m5307\fR" 4 .IX Item "-m5307" -Generate output for a ColdFire 5307 \s-1CPU.\s0 The option is now deprecated +Generate output for a ColdFire 5307 \s-1CPU. \s0 The option is now deprecated in favor of the equivalent \fB\-mcpu=5307\fR. .IP "\fB\-m5407\fR" 4 .IX Item "-m5407" -Generate output for a ColdFire 5407 \s-1CPU.\s0 The option is now deprecated +Generate output for a ColdFire 5407 \s-1CPU. \s0 The option is now deprecated in favor of the equivalent \fB\-mcpu=5407\fR. .IP "\fB\-mcfv4e\fR" 4 .IX Item "-mcfv4e" -Generate output for a ColdFire V4e family \s-1CPU\s0 (e.g. 547x/548x). +Generate output for a ColdFire V4e family \s-1CPU \s0(e.g. 547x/548x). This includes use of hardware floating-point instructions. The option is equivalent to \fB\-mcpu=547x\fR, and is now deprecated in favor of that option. @@ -14526,7 +14526,7 @@ The option is equivalent to \fB\-march=68020\fR \fB\-mtune=68020\-60\fR. .IX Item "-m68881" .PD Generate floating-point instructions. This is the default for 68020 -and above, and for ColdFire devices that have an \s-1FPU.\s0 It defines the +and above, and for ColdFire devices that have an \s-1FPU. \s0 It defines the macro \fB_\|_HAVE_68881_\|_\fR on M680x0 targets and \fB_\|_mcffpu_\|_\fR on ColdFire targets. .IP "\fB\-msoft\-float\fR" 4 @@ -14543,8 +14543,8 @@ the default for ColdFire devices that have no \s-1FPU.\s0 Generate (do not generate) ColdFire hardware divide and remainder instructions. If \fB\-march\fR is used without \fB\-mcpu\fR, the default is \*(L"on\*(R" for ColdFire architectures and \*(L"off\*(R" for M680x0 -architectures. Otherwise, the default is taken from the target \s-1CPU\s0 -(either the default \s-1CPU,\s0 or the one specified by \fB\-mcpu\fR). For +architectures. Otherwise, the default is taken from the target \s-1CPU +\&\s0(either the default \s-1CPU,\s0 or the one specified by \fB\-mcpu\fR). For example, the default is \*(L"off\*(R" for \fB\-mcpu=5206\fR and \*(L"on\*(R" for \&\fB\-mcpu=5206e\fR. .Sp @@ -15022,7 +15022,7 @@ The processor names are: \&\fBvr5000\fR, \fBvr5400\fR, \fBvr5500\fR, \&\fBxlr\fR and \fBxlp\fR. The special value \fBfrom-abi\fR selects the -most compatible architecture for the selected \s-1ABI\s0 (that is, +most compatible architecture for the selected \s-1ABI \s0(that is, \&\fBmips1\fR for 32\-bit ABIs and \fBmips3\fR for 64\-bit ABIs). .Sp The native Linux/GNU toolchain also supports the value \fBnative\fR, @@ -15295,8 +15295,8 @@ configurations; see the installation documentation for details. .IP "\fB\-mno\-dsp\fR" 4 .IX Item "-mno-dsp" .PD -Use (do not use) revision 1 of the \s-1MIPS DSP ASE.\s0 - This option defines the +Use (do not use) revision 1 of the \s-1MIPS DSP ASE. + \s0 This option defines the preprocessor macro \fB_\|_mips_dsp\fR. It also defines \&\fB_\|_mips_dsp_rev\fR to 1. .IP "\fB\-mdspr2\fR" 4 @@ -15305,8 +15305,8 @@ preprocessor macro \fB_\|_mips_dsp\fR. It also defines .IP "\fB\-mno\-dspr2\fR" 4 .IX Item "-mno-dspr2" .PD -Use (do not use) revision 2 of the \s-1MIPS DSP ASE.\s0 - This option defines the +Use (do not use) revision 2 of the \s-1MIPS DSP ASE. + \s0 This option defines the preprocessor macros \fB_\|_mips_dsp\fR and \fB_\|_mips_dspr2\fR. It also defines \fB_\|_mips_dsp_rev\fR to 2. .IP "\fB\-msmartmips\fR" 4 @@ -15340,7 +15340,7 @@ hardware floating-point support to be enabled. .IP "\fB\-mno\-mips3d\fR" 4 .IX Item "-mno-mips3d" .PD -Use (do not use) the \s-1MIPS\-3D ASE.\s0 +Use (do not use) the \s-1MIPS\-3D ASE. \s0 The option \fB\-mips3d\fR implies \fB\-mpaired\-single\fR. .IP "\fB\-mmt\fR" 4 .IX Item "-mmt" @@ -15366,7 +15366,7 @@ determined. Force \f(CW\*(C`long\*(C'\fR, \f(CW\*(C`int\*(C'\fR, and pointer types to be 32 bits wide. .Sp The default size of \f(CW\*(C`int\*(C'\fRs, \f(CW\*(C`long\*(C'\fRs and pointers depends on -the \s-1ABI.\s0 All the supported ABIs use 32\-bit \f(CW\*(C`int\*(C'\fRs. The n64 \s-1ABI\s0 +the \s-1ABI. \s0 All the supported ABIs use 32\-bit \f(CW\*(C`int\*(C'\fRs. The n64 \s-1ABI\s0 uses 64\-bit \f(CW\*(C`long\*(C'\fRs, as does the 64\-bit \s-1EABI\s0; the others use 32\-bit \f(CW\*(C`long\*(C'\fRs. Pointers are the same size as \f(CW\*(C`long\*(C'\fRs, or the same size as integer registers, whichever is smaller. @@ -15377,7 +15377,7 @@ or the same size as integer registers, whichever is smaller. .IX Item "-mno-sym32" .PD Assume (do not assume) that all symbols have 32\-bit values, regardless -of the selected \s-1ABI.\s0 This option is useful in combination with +of the selected \s-1ABI. \s0 This option is useful in combination with \&\fB\-mabi=64\fR and \fB\-mno\-abicalls\fR because it allows \s-1GCC\s0 to generate shorter and faster references to symbolic addresses. .IP "\fB\-G\fR \fInum\fR" 4 @@ -15675,10 +15675,10 @@ instructions. These errata are handled by the assembler, not by \s-1GCC\s0 itse .RE .IP "\fB\-mfix\-vr4130\fR" 4 .IX Item "-mfix-vr4130" -Work around the \s-1VR4130\s0 \f(CW\*(C`mflo\*(C'\fR/\f(CW\*(C`mfhi\*(C'\fR errata. The +Work around the \s-1VR4130 \s0\f(CW\*(C`mflo\*(C'\fR/\f(CW\*(C`mfhi\*(C'\fR errata. The workarounds are implemented by the assembler rather than by \s-1GCC,\s0 although \s-1GCC\s0 avoids using \f(CW\*(C`mflo\*(C'\fR and \f(CW\*(C`mfhi\*(C'\fR if the -\&\s-1VR4130\s0 \f(CW\*(C`macc\*(C'\fR, \f(CW\*(C`macchi\*(C'\fR, \f(CW\*(C`dmacc\*(C'\fR and \f(CW\*(C`dmacchi\*(C'\fR +\&\s-1VR4130 \s0\f(CW\*(C`macc\*(C'\fR, \f(CW\*(C`macchi\*(C'\fR, \f(CW\*(C`dmacc\*(C'\fR and \f(CW\*(C`dmacchi\*(C'\fR instructions are available instead. .IP "\fB\-mfix\-sb1\fR" 4 .IX Item "-mfix-sb1" @@ -16067,7 +16067,7 @@ Return floating-point results in memory. This is the default. Generate code for a \s-1PDP\-11/40.\s0 .IP "\fB\-m45\fR" 4 .IX Item "-m45" -Generate code for a \s-1PDP\-11/45.\s0 This is the default. +Generate code for a \s-1PDP\-11/45. \s0 This is the default. .IP "\fB\-m10\fR" 4 .IX Item "-m10" Generate code for a \s-1PDP\-11/10.\s0 @@ -16147,7 +16147,7 @@ work properly on all types of \s-1AE.\s0 \&\fB\-mae=MUL\fR selects a \s-1MUL AE\s0 type. This is the most useful \s-1AE\s0 type for compiled code, and is the default. .Sp -\&\fB\-mae=MAC\fR selects a DSP-style \s-1MAC AE.\s0 Code compiled with this +\&\fB\-mae=MAC\fR selects a DSP-style \s-1MAC AE. \s0 Code compiled with this option may suffer from poor performance of byte (char) manipulation, since the \s-1DSP AE\s0 does not provide hardware support for byte load/stores. .IP "\fB\-msymbol\-as\-address\fR" 4 @@ -16243,7 +16243,7 @@ These \fB\-m\fR options are defined for the \s-1IBM RS/6000\s0 and PowerPC: .PD You use these options to specify which instructions are available on the processor you are using. The default value of these options is -determined when configuring \s-1GCC.\s0 Specifying the +determined when configuring \s-1GCC. \s0 Specifying the \&\fB\-mcpu=\fR\fIcpu_type\fR overrides the specification of these options. We recommend you use the \fB\-mcpu=\fR\fIcpu_type\fR option rather than the options listed above. @@ -16416,7 +16416,7 @@ This is a PowerPC 32\-bit \s-1SYSV ABI\s0 option. .IP "\fB\-mbss\-plt\fR" 4 .IX Item "-mbss-plt" -Generate code that uses a \s-1BSS\s0 \f(CW\*(C`.plt\*(C'\fR section that \fBld.so\fR +Generate code that uses a \s-1BSS \s0\f(CW\*(C`.plt\*(C'\fR section that \fBld.so\fR fills in, and requires \f(CW\*(C`.plt\*(C'\fR and \f(CW\*(C`.got\*(C'\fR sections that are both writable and executable. @@ -16495,7 +16495,7 @@ later processors. .IX Item "-mno-power8-vector" .PD Generate code that uses (does not use) the vector and scalar -instructions that were added in version 2.07 of the PowerPC \s-1ISA.\s0 Also +instructions that were added in version 2.07 of the PowerPC \s-1ISA. \s0 Also enable the use of built-in functions that allow more direct access to the vector instructions. .IP "\fB\-mquad\-memory\fR" 4 @@ -16558,11 +16558,11 @@ pointer to 64 bits, and generates code for PowerPC64, as for .IP "\fB\-mminimal\-toc\fR" 4 .IX Item "-mminimal-toc" .PD -Modify generation of the \s-1TOC\s0 (Table Of Contents), which is created for +Modify generation of the \s-1TOC \s0(Table Of Contents), which is created for every executable file. The \fB\-mfull\-toc\fR option is selected by default. In that case, \s-1GCC\s0 allocates at least one \s-1TOC\s0 entry for each unique non-automatic variable reference in your program. \s-1GCC\s0 -also places floating-point constants in the \s-1TOC.\s0 However, only +also places floating-point constants in the \s-1TOC. \s0 However, only 16,384 entries are available in the \s-1TOC.\s0 .Sp If you receive a linker error message that saying you have overflowed @@ -16571,7 +16571,7 @@ with the \fB\-mno\-fp\-in\-toc\fR and \fB\-mno\-sum\-in\-toc\fR options. \&\fB\-mno\-fp\-in\-toc\fR prevents \s-1GCC\s0 from putting floating-point constants in the \s-1TOC\s0 and \fB\-mno\-sum\-in\-toc\fR forces \s-1GCC\s0 to generate code to calculate the sum of an address and a constant at -run time instead of putting that sum into the \s-1TOC.\s0 You may specify one +run time instead of putting that sum into the \s-1TOC. \s0 You may specify one or both of these options. Each causes \s-1GCC\s0 to produce very slightly slower and larger code at the expense of conserving \s-1TOC\s0 space. .Sp @@ -16599,7 +16599,7 @@ implies \fB\-mno\-powerpc64\fR. \s-1GCC\s0 defaults to \fB\-maix32\fR. .IX Item "-mno-xl-compat" .PD Produce code that conforms more closely to \s-1IBM XL\s0 compiler semantics -when using AIX-compatible \s-1ABI.\s0 Pass floating-point arguments to +when using AIX-compatible \s-1ABI. \s0 Pass floating-point arguments to prototyped functions beyond the register save area (\s-1RSA\s0) on the stack in addition to argument FPRs. Do not assume that most significant double in 128\-bit long double value is properly rounded when comparing @@ -17125,7 +17125,7 @@ On Darwin/PPC systems, \f(CW\*(C`#pragma longcall\*(C'\fR generates \f(CW\*(C`jb callee, L42\*(C'\fR, plus a \fIbranch island\fR (glue code). The two target addresses represent the callee and the branch island. The Darwin/PPC linker prefers the first address and generates a \f(CW\*(C`bl -callee\*(C'\fR if the \s-1PPC\s0 \f(CW\*(C`bl\*(C'\fR instruction reaches the callee directly; +callee\*(C'\fR if the \s-1PPC \s0\f(CW\*(C`bl\*(C'\fR instruction reaches the callee directly; otherwise, the linker generates \f(CW\*(C`bl L42\*(C'\fR to call the branch island. The branch island is appended to the body of the calling function; it computes the full 32\-bit address of the callee @@ -17197,7 +17197,7 @@ which handle the double-precision reciprocal square root calculations. .PD Assume (do not assume) that the reciprocal estimate instructions provide higher-precision estimates than is mandated by the PowerPC -\&\s-1ABI.\s0 Selecting \fB\-mcpu=power6\fR, \fB\-mcpu=power7\fR or +\&\s-1ABI. \s0 Selecting \fB\-mcpu=power6\fR, \fB\-mcpu=power7\fR or \&\fB\-mcpu=power8\fR automatically selects \fB\-mrecip\-precision\fR. The double-precision square root estimate instructions are not generated by default on low-precision machines, since they do not provide an @@ -17272,10 +17272,10 @@ Generate (do not generate) code to pass structure parameters with a maximum alignment of 64 bits, for compatibility with older versions of \s-1GCC.\s0 .Sp -Older versions of \s-1GCC\s0 (prior to 4.9.0) incorrectly did not align a +Older versions of \s-1GCC \s0(prior to 4.9.0) incorrectly did not align a structure parameter on a 128\-bit boundary when that structure contained a member requiring 128\-bit alignment. This is corrected in more -recent versions of \s-1GCC.\s0 This option may be used to generate code +recent versions of \s-1GCC. \s0 This option may be used to generate code that is compatible with functions compiled with older versions of \&\s-1GCC.\s0 .Sp @@ -17318,7 +17318,7 @@ This is because the \s-1RX FPU\s0 instructions are themselves unsafe. .IX Item "-mcpu=name" Selects the type of \s-1RX CPU\s0 to be targeted. Currently three types are supported, the generic \fI\s-1RX600\s0\fR and \fI\s-1RX200\s0\fR series hardware and -the specific \fI\s-1RX610\s0\fR \s-1CPU.\s0 The default is \fI\s-1RX600\s0\fR. +the specific \fI\s-1RX610\s0\fR \s-1CPU. \s0 The default is \fI\s-1RX600\s0\fR. .Sp The only difference between \fI\s-1RX600\s0\fR and \fI\s-1RX610\s0\fR is that the \&\fI\s-1RX610\s0\fR does not support the \f(CW\*(C`MVTIPL\*(C'\fR instruction. @@ -17563,8 +17563,8 @@ which does not have this limitation. .IX Item "-m31" .PD When \fB\-m31\fR is specified, generate code compliant to the -GNU/Linux for S/390 \s-1ABI.\s0 When \fB\-m64\fR is specified, generate -code compliant to the GNU/Linux for zSeries \s-1ABI.\s0 This allows \s-1GCC\s0 in +GNU/Linux for S/390 \s-1ABI. \s0 When \fB\-m64\fR is specified, generate +code compliant to the GNU/Linux for zSeries \s-1ABI. \s0 This allows \s-1GCC\s0 in particular to generate 64\-bit instructions. For the \fBs390\fR targets, the default is \fB\-m31\fR, while the \fBs390x\fR targets default to \fB\-m64\fR. @@ -17577,7 +17577,7 @@ targets default to \fB\-m64\fR. When \fB\-mzarch\fR is specified, generate code using the instructions available on z/Architecture. When \fB\-mesa\fR is specified, generate code using the -instructions available on \s-1ESA/390.\s0 Note that \fB\-mesa\fR is +instructions available on \s-1ESA/390. \s0 Note that \fB\-mesa\fR is not possible with \fB\-m64\fR. When generating code compliant to the GNU/Linux for S/390 \s-1ABI,\s0 the default is \fB\-mesa\fR. When generating code compliant @@ -18017,14 +18017,14 @@ SH2A\s0 and SHcompact. .IX Item "call-fp" Calls a library function that performs the operation in double precision floating point. Division by zero causes a floating-point exception. This is -the default for SHcompact with \s-1FPU.\s0 Specifying this for targets that do not +the default for SHcompact with \s-1FPU. \s0 Specifying this for targets that do not have a double precision \s-1FPU\s0 will default to \f(CW\*(C`call\-div1\*(C'\fR. .IP "\fBcall-table\fR" 4 .IX Item "call-table" Calls a library function that uses a lookup table for small divisors and the \f(CW\*(C`div1\*(C'\fR instruction with case distinction for larger divisors. Division by zero calculates an unspecified result and does not trap. This is the default -for \s-1SH4.\s0 Specifying this for targets that do not have dynamic shift +for \s-1SH4. \s0 Specifying this for targets that do not have dynamic shift instructions will default to \f(CW\*(C`call\-div1\*(C'\fR. .RE .RS 4 @@ -18115,7 +18115,7 @@ is being compiled for. Assume (do not assume) that zero displacement conditional branch instructions \&\f(CW\*(C`bt\*(C'\fR and \f(CW\*(C`bf\*(C'\fR are fast. If \fB\-mzdcbranch\fR is specified, the compiler will try to prefer zero displacement branch code sequences. This is -enabled by default when generating code for \s-1SH4\s0 and \s-1SH4A.\s0 It can be explicitly +enabled by default when generating code for \s-1SH4\s0 and \s-1SH4A. \s0 It can be explicitly disabled by specifying \fB\-mno\-zdcbranch\fR. .IP "\fB\-mcbranchdi\fR" 4 .IX Item "-mcbranchdi" @@ -18145,7 +18145,7 @@ mapped to \fB\-ffp\-contract=off\fR. Allow or disallow the compiler to emit the \f(CW\*(C`fsca\*(C'\fR instruction for sine and cosine approximations. The option \f(CW\*(C`\-mfsca\*(C'\fR must be used in combination with \f(CW\*(C`\-funsafe\-math\-optimizations\*(C'\fR. It is enabled by default -when generating code for \s-1SH4A.\s0 Using \f(CW\*(C`\-mno\-fsca\*(C'\fR disables sine and cosine +when generating code for \s-1SH4A. \s0 Using \f(CW\*(C`\-mno\-fsca\*(C'\fR disables sine and cosine approximations even if \f(CW\*(C`\-funsafe\-math\-optimizations\*(C'\fR is in effect. .IP "\fB\-mfsrra\fR" 4 .IX Item "-mfsrra" @@ -18157,7 +18157,7 @@ Allow or disallow the compiler to emit the \f(CW\*(C`fsrra\*(C'\fR instruction f reciprocal square root approximations. The option \f(CW\*(C`\-mfsrra\*(C'\fR must be used in combination with \f(CW\*(C`\-funsafe\-math\-optimizations\*(C'\fR and \&\f(CW\*(C`\-ffinite\-math\-only\*(C'\fR. It is enabled by default when generating code for -\&\s-1SH4A.\s0 Using \f(CW\*(C`\-mno\-fsrra\*(C'\fR disables reciprocal square root approximations +\&\s-1SH4A. \s0 Using \f(CW\*(C`\-mno\-fsrra\*(C'\fR disables reciprocal square root approximations even if \f(CW\*(C`\-funsafe\-math\-optimizations\*(C'\fR and \f(CW\*(C`\-ffinite\-math\-only\*(C'\fR are in effect. .IP "\fB\-mpretend\-cmove\fR" 4 @@ -18261,7 +18261,7 @@ instructions. .IX Item "-msoft-quad-float" Generate output containing library calls for quad-word (long double) floating-point instructions. The functions called are those specified -in the \s-1SPARC ABI.\s0 This is the default. +in the \s-1SPARC ABI. \s0 This is the default. .Sp As of this writing, there are no \s-1SPARC\s0 implementations that have hardware support for the quad-word floating-point instructions. They all invoke @@ -18303,7 +18303,7 @@ should have 8\-byte alignment. This enables the use of pairs of \&\f(CW\*(C`ldd\*(C'\fR and \f(CW\*(C`std\*(C'\fR instructions for copies in structure assignment, in place of twice as many \f(CW\*(C`ld\*(C'\fR and \f(CW\*(C`st\*(C'\fR pairs. However, the use of this changed alignment directly violates the \s-1SPARC -ABI.\s0 Thus, it's intended only for use on targets where the developer +ABI. \s0 Thus, it's intended only for use on targets where the developer acknowledges that their resulting code is not directly in line with the rules of the \s-1ABI.\s0 .IP "\fB\-mcpu=\fR\fIcpu_type\fR" 4 @@ -18355,7 +18355,7 @@ SPARCStation 1, 2, \s-1IPX\s0 etc. With \fB\-mcpu=v8\fR, \s-1GCC\s0 generates code for the V8 variant of the \s-1SPARC\s0 architecture. The only difference from V7 code is that the compiler emits the integer multiply and integer divide instructions which exist in \s-1SPARC\-V8\s0 -but not in \s-1SPARC\-V7.\s0 With \fB\-mcpu=supersparc\fR, the compiler additionally +but not in \s-1SPARC\-V7. \s0 With \fB\-mcpu=supersparc\fR, the compiler additionally optimizes it for the SuperSPARC chip, as used in the SPARCStation 10, 1000 and 2000 series. .Sp @@ -18363,14 +18363,14 @@ With \fB\-mcpu=sparclite\fR, \s-1GCC\s0 generates code for the SPARClite variant the \s-1SPARC\s0 architecture. This adds the integer multiply, integer divide step and scan (\f(CW\*(C`ffs\*(C'\fR) instructions which exist in SPARClite but not in \s-1SPARC\-V7.\s0 With \fB\-mcpu=f930\fR, the compiler additionally optimizes it for the -Fujitsu \s-1MB86930\s0 chip, which is the original SPARClite, with no \s-1FPU.\s0 With +Fujitsu \s-1MB86930\s0 chip, which is the original SPARClite, with no \s-1FPU. \s0 With \&\fB\-mcpu=f934\fR, the compiler additionally optimizes it for the Fujitsu \&\s-1MB86934\s0 chip, which is the more recent SPARClite with \s-1FPU.\s0 .Sp With \fB\-mcpu=sparclet\fR, \s-1GCC\s0 generates code for the SPARClet variant of the \s-1SPARC\s0 architecture. This adds the integer multiply, multiply/accumulate, integer divide step and scan (\f(CW\*(C`ffs\*(C'\fR) instructions which exist in SPARClet -but not in \s-1SPARC\-V7.\s0 With \fB\-mcpu=tsc701\fR, the compiler additionally +but not in \s-1SPARC\-V7. \s0 With \fB\-mcpu=tsc701\fR, the compiler additionally optimizes it for the \s-1TEMIC\s0 SPARClet chip. .Sp With \fB\-mcpu=v9\fR, \s-1GCC\s0 generates code for the V9 variant of the \s-1SPARC\s0 @@ -18407,7 +18407,7 @@ can also be used. .IP "\fB\-mno\-v8plus\fR" 4 .IX Item "-mno-v8plus" .PD -With \fB\-mv8plus\fR, \s-1GCC\s0 generates code for the \s-1SPARC\-V8+ ABI.\s0 The +With \fB\-mv8plus\fR, \s-1GCC\s0 generates code for the \s-1SPARC\-V8+ ABI. \s0 The difference from the V8 \s-1ABI\s0 is that the global and out registers are considered 64 bits wide. This is enabled by default on Solaris in 32\-bit mode for all \s-1SPARC\-V9\s0 processors. @@ -18897,7 +18897,7 @@ selected because its use is still experimental. .IP "\fB\-mghs\fR" 4 .IX Item "-mghs" .PD -Enables support for the \s-1RH850\s0 version of the V850 \s-1ABI.\s0 This is the +Enables support for the \s-1RH850\s0 version of the V850 \s-1ABI. \s0 This is the default. With this version of the \s-1ABI\s0 the following rules apply: .RS 4 .IP "\(bu" 4 @@ -18922,7 +18922,7 @@ When this version of the \s-1ABI\s0 is enabled the C preprocessor symbol .RE .IP "\fB\-mgcc\-abi\fR" 4 .IX Item "-mgcc-abi" -Enables support for the old \s-1GCC\s0 version of the V850 \s-1ABI.\s0 With this +Enables support for the old \s-1GCC\s0 version of the V850 \s-1ABI. \s0 With this version of the \s-1ABI\s0 the following rules apply: .RS 4 .IP "\(bu" 4 @@ -19424,7 +19424,7 @@ the \s-1GOT\s0 size for the linked executable exceeds a machine-specific maximum size, you get an error message from the linker indicating that \&\fB\-fpic\fR does not work; in that case, recompile with \fB\-fPIC\fR instead. (These maximums are 8k on the \s-1SPARC\s0 and 32k -on the m68k and \s-1RS/6000.\s0 The 386 has no such limit.) +on the m68k and \s-1RS/6000. \s0 The 386 has no such limit.) .Sp Position-independent code requires special support, and therefore works only on certain machines. For the 386, \s-1GCC\s0 supports \s-1PIC\s0 for System V @@ -19984,8 +19984,8 @@ to subtle defects. Supplying them in cases where they are not necessary is innocuous. .SH "SEE ALSO" .IX Header "SEE ALSO" -\&\fBgpl\fR\|(7), \fBgfdl\fR\|(7), \fBfsf\-funding\fR\|(7), -\&\fBcpp\fR\|(1), \fBgcov\fR\|(1), \fBas\fR\|(1), \fBld\fR\|(1), \fBgdb\fR\|(1), \fBadb\fR\|(1), \fBdbx\fR\|(1), \fBsdb\fR\|(1) +\&\fIgpl\fR\|(7), \fIgfdl\fR\|(7), \fIfsf\-funding\fR\|(7), +\&\fIcpp\fR\|(1), \fIgcov\fR\|(1), \fIas\fR\|(1), \fIld\fR\|(1), \fIgdb\fR\|(1), \fIadb\fR\|(1), \fIdbx\fR\|(1), \fIsdb\fR\|(1) and the Info entries for \fIgcc\fR, \fIcpp\fR, \fIas\fR, \&\fIld\fR, \fIbinutils\fR and \fIgdb\fR. .SH "AUTHOR" @@ -20003,7 +20003,7 @@ any later version published by the Free Software Foundation; with the Invariant Sections being \*(L"\s-1GNU\s0 General Public License\*(R" and \*(L"Funding Free Software\*(R", the Front-Cover texts being (a) (see below), and with the Back-Cover Texts being (b) (see below). A copy of the license is -included in the \fBgfdl\fR\|(7) man page. +included in the \fIgfdl\fR\|(7) man page. .PP (a) The \s-1FSF\s0's Front-Cover Text is: .PP |