diff options
author | Qualcomm Android Team <qualcomm-android-team@localhost> | 2008-11-21 11:21:04 -0800 |
---|---|---|
committer | Qualcomm Android Team <qualcomm-android-team@localhost> | 2008-11-21 11:21:04 -0800 |
commit | 90c46cfadcc58a8d9d514bb7eed20db0b0be4310 (patch) | |
tree | 41b252e98ce1c3132f1a96f8c8ff2f4a9b051fd0 | |
download | surf-cupcake.tar.gz |
34 files changed, 1846 insertions, 0 deletions
diff --git a/Android.mk b/Android.mk new file mode 100644 index 0000000..03f37d3 --- /dev/null +++ b/Android.mk @@ -0,0 +1,18 @@ +LOCAL_PATH := $(call my-dir) + +file := $(TARGET_OUT_KEYLAYOUT)/halibut_keypad.kl +ALL_PREBUILT += $(file) +$(file) : $(LOCAL_PATH)/halibut_keypad.kl | $(ACP) + $(transform-prebuilt-to-target) + +include $(CLEAR_VARS) +LOCAL_SRC_FILES := halibut_keypad.kcm +include $(BUILD_KEY_CHAR_MAP) + +# to build the bootloader you need the common boot stuff, +# the architecture specific stuff, and the board specific stuff +include vendor/qcom/surf/boot/Android.mk +# include bootloader/legacy/Android.mk + +include vendor/qcom/surf/AndroidBoard.mk + diff --git a/AndroidBoard.mk b/AndroidBoard.mk new file mode 100644 index 0000000..feb29eb --- /dev/null +++ b/AndroidBoard.mk @@ -0,0 +1,2 @@ +LOCAL_PATH := $(my-dir) +include vendor/qcom-proprietary/Android.mk diff --git a/AndroidProducts.mk b/AndroidProducts.mk new file mode 100644 index 0000000..62a6fc8 --- /dev/null +++ b/AndroidProducts.mk @@ -0,0 +1,3 @@ + +PRODUCT_MAKEFILES := \ + $(LOCAL_DIR)/qcom_surf.mk diff --git a/BoardConfig.mk b/BoardConfig.mk new file mode 100644 index 0000000..cc21ef4 --- /dev/null +++ b/BoardConfig.mk @@ -0,0 +1,25 @@ +# config.mk +# +# Product-specific compile-time definitions. +# + +# BOARD_GPS_LIBRARIES := libgps + +BOARD_CAMERA_LIBRARIES := libcamera + +BOARD_OPENCORE_LIBRARIES := libOmxCore +BOARD_OPENCORE_FLAGS := -DHARDWARE_OMX=1 + +TARGET_NO_BOOTLOADER := true +TARGET_NO_KERNEL := true +TARGET_NO_RADIOIMAGE := true + +TARGET_BOOTLOADER_LIBS := \ + libboot_board_surf \ + libboot_arch_msm7k \ + libboot_arch_armv6 + +TARGET_BOOTLOADER_LINK_SCRIPT := \ + vendor/qcom/surf/boot/boot.ld + +BOARD_KERNEL_CMDLINE := mem=110M console=ttyMSM0,115200n8 diff --git a/boot/Android.mk b/boot/Android.mk new file mode 100644 index 0000000..c46f8c7 --- /dev/null +++ b/boot/Android.mk @@ -0,0 +1,18 @@ +LOCAL_PATH:= $(call my-dir) + +include $(CLEAR_VARS) + +LOCAL_ARM_MODE := arm + +LOCAL_SRC_FILES := board.c panel.c keypad.c + +LOCAL_C_INCLUDES := bootloader/legacy/include + +LOCAL_CFLAGS := -O2 -g -W -Wall +LOCAL_CFLAGS += -march=armv6 + +LOCAL_MODULE := libboot_board_surf + +include $(BUILD_RAW_STATIC_LIBRARY) + +include $(call all-subdir-makefiles) diff --git a/boot/board.c b/boot/board.c new file mode 100644 index 0000000..d9889f4 --- /dev/null +++ b/boot/board.c @@ -0,0 +1,71 @@ +/* Copyright 2007, Google Inc. */ + +#include <boot/boot.h> +#include <boot/flash.h> +#include <msm7k/shared.h> + +ptentry PTABLE[] = { + { + .start = 298, + .length = 40, + .name = "boot", + }, + { + .start = 354, + .length = 512, + .name = "system", + }, + { + .start = 866, + .length = 157 + 1024, + .name = "userdata", + }, + { + .name = "", + }, +}; + +const char *board_cmdline(void) +{ + return "mem=112M androidboot.console=ttyMSM0 console=ttyMSM0"; +} + +unsigned board_machtype(void) +{ + return 1439; +} + +void board_init() +{ + unsigned n; + + /* if we already have partitions from elsewhere, + ** don't use the hardcoded ones + */ + if(flash_get_ptn_count() == 0) { + for(n = 0; PTABLE[n].name[0]; n++) { + flash_add_ptn(PTABLE + n); + } + } + + clock_enable(UART1_CLK); + clock_set_rate(UART1_CLK, 19200000 / 4); + + uart_init(0); +} + +void board_usb_init(void) +{ +} + +void board_ulpi_init(void) +{ +} + +void board_reboot(void) +{ +} + +void board_getvar(const char *name, char *value) +{ +} diff --git a/boot/boot.ld b/boot/boot.ld new file mode 100644 index 0000000..9ecf86f --- /dev/null +++ b/boot/boot.ld @@ -0,0 +1,29 @@ +SECTIONS { + BOOTLOADER_START = 0x00000000 ; + .text BOOTLOADER_START : + { + *(.text) + . = ALIGN(8); + } + .init : { + . = ALIGN(8); + BOOTLOADER_INIT_FIRST = . ; + *(.init.func.0) + BOOTLOADER_INIT_LAST = . ; + } + .data : { + . = ALIGN(8); + *(.data) + . = ALIGN(8); + } + .bss : { + BOOTLOADER_BSS = . ; + . = ALIGN(8); + *(.bss) *(COMMON) + . = ALIGN(8); + BOOTLOADER_END = . ; + } + BOOTLOADER_STACK = 0x000FF000 ; + BOOTLOADER_HEAP = 0x00100000 ; +} + diff --git a/boot/keypad.c b/boot/keypad.c new file mode 100644 index 0000000..380fc01 --- /dev/null +++ b/boot/keypad.c @@ -0,0 +1,42 @@ +/* Copyright 2007, Google Inc. */ + +#include <boot/boot.h> +#include <boot/gpio_keypad.h> + +#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) + +static unsigned int halibut_row_gpios[] = { 31, 32, 33, 34, 35, 41 }; +static unsigned int halibut_col_gpios[] = { 36, 37, 38, 39, 40 }; + +static unsigned int halibut_key_map[] = { + [11] = BOOT_KEY_CONTINUE_BOOT, /* FA on SURF, B on FFA */ + [23] = BOOT_KEY_STOP_BOOT, /* FB on SURF */ + [27] = BOOT_KEY_STOP_BOOT, /* 2 on FFA */ +}; + +static gpio_keypad_info halibut_keypad = { + .output_gpios = halibut_row_gpios, + .input_gpios = halibut_col_gpios, + .noutputs = ARRAY_SIZE(halibut_row_gpios), + .ninputs = ARRAY_SIZE(halibut_col_gpios), + .key_map = halibut_key_map, + .settle_time = 5000, + .polarity = 0, + .drive_inactive_outputs = 1 +}; + +static void keypad_poll() +{ + static int skip = 0; + skip++; + if(skip > 10) { + gpio_keypad_scan_keys(&halibut_keypad); + skip = 0; + } +} + +void keypad_init(void) +{ + gpio_keypad_init(&halibut_keypad); + boot_register_poll_func(keypad_poll); +} diff --git a/boot/panel.c b/boot/panel.c new file mode 100644 index 0000000..2fa9958 --- /dev/null +++ b/boot/panel.c @@ -0,0 +1,470 @@ +/* Copyright 2007, Google Inc. */ + +#include <boot/boot.h> +#include <msm7k/mddi.h> + +#define MDDI_CLIENT_CORE_BASE 0x108000 +#define LCD_CONTROL_BLOCK_BASE 0x110000 +#define SPI_BLOCK_BASE 0x120000 +#define I2C_BLOCK_BASE 0x130000 +#define PWM_BLOCK_BASE 0x140000 +#define GPIO_BLOCK_BASE 0x150000 +#define SYSTEM_BLOCK1_BASE 0x160000 +#define SYSTEM_BLOCK2_BASE 0x170000 + + +#define MDDICAP0 (MDDI_CLIENT_CORE_BASE|0x00) +#define MDDICAP1 (MDDI_CLIENT_CORE_BASE|0x04) +#define MDDICAP2 (MDDI_CLIENT_CORE_BASE|0x08) +#define MDDICAP3 (MDDI_CLIENT_CORE_BASE|0x0C) +#define MDCAPCHG (MDDI_CLIENT_CORE_BASE|0x10) +#define MDCRCERC (MDDI_CLIENT_CORE_BASE|0x14) +#define TTBUSSEL (MDDI_CLIENT_CORE_BASE|0x18) +#define DPSET0 (MDDI_CLIENT_CORE_BASE|0x1C) +#define DPSET1 (MDDI_CLIENT_CORE_BASE|0x20) +#define DPSUS (MDDI_CLIENT_CORE_BASE|0x24) +#define DPRUN (MDDI_CLIENT_CORE_BASE|0x28) +#define SYSCKENA (MDDI_CLIENT_CORE_BASE|0x2C) +#define TESTMODE (MDDI_CLIENT_CORE_BASE|0x30) +#define FIFOMONI (MDDI_CLIENT_CORE_BASE|0x34) +#define INTMONI (MDDI_CLIENT_CORE_BASE|0x38) +#define MDIOBIST (MDDI_CLIENT_CORE_BASE|0x3C) +#define MDIOPSET (MDDI_CLIENT_CORE_BASE|0x40) +#define BITMAP0 (MDDI_CLIENT_CORE_BASE|0x44) +#define BITMAP1 (MDDI_CLIENT_CORE_BASE|0x48) +#define BITMAP2 (MDDI_CLIENT_CORE_BASE|0x4C) +#define BITMAP3 (MDDI_CLIENT_CORE_BASE|0x50) +#define BITMAP4 (MDDI_CLIENT_CORE_BASE|0x54) + + +#define SRST (LCD_CONTROL_BLOCK_BASE|0x00) +#define PORT_ENB (LCD_CONTROL_BLOCK_BASE|0x04) +#define START (LCD_CONTROL_BLOCK_BASE|0x08) +#define PORT (LCD_CONTROL_BLOCK_BASE|0x0C) +#define CMN (LCD_CONTROL_BLOCK_BASE|0x10) +#define GAMMA (LCD_CONTROL_BLOCK_BASE|0x14) +#define INTFLG (LCD_CONTROL_BLOCK_BASE|0x18) +#define INTMSK (LCD_CONTROL_BLOCK_BASE|0x1C) +#define MPLFBUF (LCD_CONTROL_BLOCK_BASE|0x20) +#define HDE_LEFT (LCD_CONTROL_BLOCK_BASE|0x24) +#define VDE_TOP (LCD_CONTROL_BLOCK_BASE|0x28) + +#define PXL (LCD_CONTROL_BLOCK_BASE|0x30) +#define HCYCLE (LCD_CONTROL_BLOCK_BASE|0x34) +#define HSW (LCD_CONTROL_BLOCK_BASE|0x38) +#define HDE_START (LCD_CONTROL_BLOCK_BASE|0x3C) +#define HDE_SIZE (LCD_CONTROL_BLOCK_BASE|0x40) +#define VCYCLE (LCD_CONTROL_BLOCK_BASE|0x44) +#define VSW (LCD_CONTROL_BLOCK_BASE|0x48) +#define VDE_START (LCD_CONTROL_BLOCK_BASE|0x4C) +#define VDE_SIZE (LCD_CONTROL_BLOCK_BASE|0x50) +#define WAKEUP (LCD_CONTROL_BLOCK_BASE|0x54) +#define WSYN_DLY (LCD_CONTROL_BLOCK_BASE|0x58) +#define REGENB (LCD_CONTROL_BLOCK_BASE|0x5C) +#define VSYNIF (LCD_CONTROL_BLOCK_BASE|0x60) +#define WRSTB (LCD_CONTROL_BLOCK_BASE|0x64) +#define RDSTB (LCD_CONTROL_BLOCK_BASE|0x68) +#define ASY_DATA (LCD_CONTROL_BLOCK_BASE|0x6C) +#define ASY_DATB (LCD_CONTROL_BLOCK_BASE|0x70) +#define ASY_DATC (LCD_CONTROL_BLOCK_BASE|0x74) +#define ASY_DATD (LCD_CONTROL_BLOCK_BASE|0x78) +#define ASY_DATE (LCD_CONTROL_BLOCK_BASE|0x7C) +#define ASY_DATF (LCD_CONTROL_BLOCK_BASE|0x80) +#define ASY_DATG (LCD_CONTROL_BLOCK_BASE|0x84) +#define ASY_DATH (LCD_CONTROL_BLOCK_BASE|0x88) +#define ASY_CMDSET (LCD_CONTROL_BLOCK_BASE|0x8C) + +#define MONI (LCD_CONTROL_BLOCK_BASE|0xB0) + +#define Current (LCD_CONTROL_BLOCK_BASE|0xC0) +#define LCD (LCD_CONTROL_BLOCK_BASE|0xC4) +#define COMMAND (LCD_CONTROL_BLOCK_BASE|0xC8) + + +#define SSICTL (SPI_BLOCK_BASE|0x00) +#define SSITIME (SPI_BLOCK_BASE|0x04) +#define SSITX (SPI_BLOCK_BASE|0x08) +#define SSIRX (SPI_BLOCK_BASE|0x0C) +#define SSIINTC (SPI_BLOCK_BASE|0x10) +#define SSIINTS (SPI_BLOCK_BASE|0x14) +#define SSIDBG1 (SPI_BLOCK_BASE|0x18) +#define SSIDBG2 (SPI_BLOCK_BASE|0x1C) +#define SSIID (SPI_BLOCK_BASE|0x20) + + +#define I2CSETUP (I2C_BLOCK_BASE|0x00) +#define I2CCTRL (I2C_BLOCK_BASE|0x04) + + +#define TIMER0LOAD (PWM_BLOCK_BASE|0x00) +#define TIMER0VALUE (PWM_BLOCK_BASE|0x04) +#define TIMER0CONTROL (PWM_BLOCK_BASE|0x08) +#define TIMER0INTCLR (PWM_BLOCK_BASE|0x0C) +#define TIMER0RIS (PWM_BLOCK_BASE|0x10) +#define TIMER0MIS (PWM_BLOCK_BASE|0x14) +#define TIMER0BGLOAD (PWM_BLOCK_BASE|0x18) +#define PWM0OFF (PWM_BLOCK_BASE|0x1C) +#define TIMER1LOAD (PWM_BLOCK_BASE|0x20) +#define TIMER1VALUE (PWM_BLOCK_BASE|0x24) +#define TIMER1CONTROL (PWM_BLOCK_BASE|0x28) +#define TIMER1INTCLR (PWM_BLOCK_BASE|0x2C) +#define TIMER1RIS (PWM_BLOCK_BASE|0x30) +#define TIMER1MIS (PWM_BLOCK_BASE|0x34) +#define TIMER1BGLOAD (PWM_BLOCK_BASE|0x38) +#define PWM1OFF (PWM_BLOCK_BASE|0x3C) +#define TIMERITCR (PWM_BLOCK_BASE|0x60) +#define TIMERITOP (PWM_BLOCK_BASE|0x64) +#define PWMCR (PWM_BLOCK_BASE|0x68) +#define PWMID (PWM_BLOCK_BASE|0x6C) +#define PWMMON (PWM_BLOCK_BASE|0x70) + + +#define GPIODATA (GPIO_BLOCK_BASE|0x00) +#define GPIODIR (GPIO_BLOCK_BASE|0x04) +#define GPIOIS (GPIO_BLOCK_BASE|0x08) +#define GPIOIBE (GPIO_BLOCK_BASE|0x0C) +#define GPIOIEV (GPIO_BLOCK_BASE|0x10) +#define GPIOIE (GPIO_BLOCK_BASE|0x14) +#define GPIORIS (GPIO_BLOCK_BASE|0x18) +#define GPIOMIS (GPIO_BLOCK_BASE|0x1C) +#define GPIOIC (GPIO_BLOCK_BASE|0x20) +#define GPIOOMS (GPIO_BLOCK_BASE|0x24) +#define GPIOPC (GPIO_BLOCK_BASE|0x28) + +#define GPIOID (GPIO_BLOCK_BASE|0x30) + + +#define WKREQ (SYSTEM_BLOCK1_BASE|0x00) +#define CLKENB (SYSTEM_BLOCK1_BASE|0x04) +#define DRAMPWR (SYSTEM_BLOCK1_BASE|0x08) +#define INTMASK (SYSTEM_BLOCK1_BASE|0x0C) +#define GPIOSEL (SYSTEM_BLOCK2_BASE|0x00) + +struct init_table { + unsigned int reg; + unsigned int val; +}; + +static struct init_table toshiba_480x640_init_table[] = { + { DPSET0, 0x4BEC0066 }, // # MDC.DPSET0 # Setup DPLL parameters + { DPSET1, 0x00000113 }, // # MDC.DPSET1 + { DPSUS, 0x00000000 }, // # MDC.DPSUS # Set DPLL oscillation enable + { DPRUN, 0x00000001 }, // # MDC.DPRUN # Release reset signal for DPLL + { 0, 14 }, // wait_ms(14); + { SYSCKENA, 0x00000001 }, // # MDC.SYSCKENA # Enable system clock output + { CLKENB, 0x000000EF }, // # SYS.CLKENB # Enable clocks for each module (without DCLK , i2cCLK) + { GPIO_BLOCK_BASE, 0x03FF0000 }, // # GPI .GPIODATA # GPIO2(RESET_LCD_N) set to 0 , GPIO3(eDRAM_Power) set to 0 + { GPIODIR, 0x0000024D }, // # GPI .GPIODIR # Select direction of GPIO port (0,2,3,6,9 output) + { SYSTEM_BLOCK2_BASE, 0x00000173 }, // # SYS.GPIOSEL # GPIO port multiplexing control + { GPIOPC, 0x03C300C0 }, // # GPI .GPIOPC # GPIO2,3 PD cut + { SYSTEM_BLOCK1_BASE, 0x00000000 }, // # SYS.WKREQ # Wake-up request event is VSYNC alignment + { GPIOIS, 0x00000000 }, // # GPI .GPIOIS # Set interrupt sense of GPIO + { GPIOIEV, 0x00000001 }, // # GPI .GPIOIEV # Set interrupt event of GPIO + { GPIOIC, 0x000003FF }, // # GPI .GPIOIC # GPIO interrupt clear + { GPIO_BLOCK_BASE, 0x00060006 }, // # GPI .GPIODATA # Release LCDD reset + { GPIO_BLOCK_BASE, 0x00080008 }, // # GPI .GPIODATA # eDRAM VD supply + { GPIO_BLOCK_BASE, 0x02000200 }, // # GPI .GPIODATA # TEST LED ON + { DRAMPWR, 0x00000001 }, // # SYS.DRAMPWR # eDRAM power up + { TIMER0CONTROL, 0x00000060 }, // # PWM.Timer0Control # PWM0 output stop + { PWM_BLOCK_BASE, 0x00001388 }, // # PWM.Timer0Load # PWM0 10kHz , Duty 99 (BackLight OFF) + //{PWM0OFF, 0x00000001 }, // # PWM.PWM0OFF +#if 0 + { PWM0OFF, 0x00001387 }, // SURF 100% backlight + { PWM0OFF, 0x00000000 }, // FFA 100% backlight +#endif + { PWM0OFF, 0x000009C3 }, // 50% BL + { TIMER1CONTROL, 0x00000060 }, // # PWM.Timer1Control # PWM1 output stop + { TIMER1LOAD, 0x00001388 }, // # PWM.Timer1Load # PWM1 10kHz , Duty 99 (BackLight OFF) + //{PWM1OFF, 0x00000001 }, // # PWM.PWM1OFF + { PWM1OFF, 0x00001387 }, + { TIMER0CONTROL, 0x000000E0 }, // # PWM.Timer0Control # PWM0 output start + { TIMER1CONTROL, 0x000000E0 }, // # PWM.Timer1Control # PWM1 output start + { PWMCR, 0x00000003 }, // # PWM.PWMCR # PWM output enable + { 0, 1 }, // wait_ms(1); + { SPI_BLOCK_BASE, 0x00000799 }, // # SPI .SSICTL # SPI operation mode setting + { SSITIME, 0x00000100 }, // # SPI .SSITIME # SPI serial interface timing setting + { SPI_BLOCK_BASE, 0x0000079b }, // # SPI .SSICTL # Set SPI active mode + + { SSITX, 0x00000000 }, // # SPI.SSITX # Release from Deep Stanby mode + { 0, 1 }, // wait_ms(1); + { SSITX, 0x00000000 }, // # SPI.SSITX + { 0, 1 }, // wait_ms(1); + { SSITX, 0x00000000 }, // # SPI.SSITX + { 0, 1 }, // wait_ms(1); + { SSITX, 0x000800BA }, // # SPI.SSITX *NOTE 1 # Command setting of SPI block + { SSITX, 0x00000111 }, // # Display mode setup(1) : Normaly Black + { SSITX, 0x00080036 }, // # Command setting of SPI block + { SSITX, 0x00000100 }, // # Memory access control + { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty + { SSITX, 0x000800BB }, // # Command setting of SPI block + { SSITX, 0x00000100 }, // # Display mode setup(2) + { SSITX, 0x0008003A }, // # Command setting of SPI block + { SSITX, 0x00000160 }, // # RGB Interface data format + { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty + { SSITX, 0x000800BF }, // # Command setting of SPI block + { SSITX, 0x00000100 }, // # Drivnig method + { SSITX, 0x000800B1 }, // # Command setting of SPI block + { SSITX, 0x0000015D }, // # Booster operation setup + { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty + { SSITX, 0x000800B2 }, // # Command setting of SPI block + { SSITX, 0x00000133 }, // # Booster mode setup + { SSITX, 0x000800B3 }, // # Command setting of SPI block + { SSITX, 0x00000122 }, // # Booster frequencies setup + { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty + { SSITX, 0x000800B4 }, // # Command setting of SPI block + { SSITX, 0x00000102 }, // # OP-amp capability/System clock freq. division setup + { SSITX, 0x000800B5 }, // # Command setting of SPI block + { SSITX, 0x0000011F }, // # VCS Voltage adjustment (1C->1F for Rev 2) + { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty + { SSITX, 0x000800B6 }, // # Command setting of SPI block + { SSITX, 0x00000128 }, // # VCOM Voltage adjustment + { SSITX, 0x000800B7 }, // # Command setting of SPI block + { SSITX, 0x00000103 }, // # Configure an external display signal + { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty + { SSITX, 0x000800B9 }, // # Command setting of SPI block + { SSITX, 0x00000120 }, // # DCCK/DCEV timing setup + { SSITX, 0x000800BD }, // # Command setting of SPI block + { SSITX, 0x00000102 }, // # ASW signal control + { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty + { SSITX, 0x000800BE }, // # Command setting of SPI block + { SSITX, 0x00000100 }, // # Dummy display (white/black) count setup for QUAD Data operation + { SSITX, 0x000800C0 }, // # Command setting of SPI block + { SSITX, 0x00000111 }, // # wait_ms(-out FR count setup (A) + { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty + { SSITX, 0x000800C1 }, // # Command setting of SPI block + { SSITX, 0x00000111 }, // # wait_ms(-out FR count setup (B) + { SSITX, 0x000800C2 }, // # Command setting of SPI block + { SSITX, 0x00000111 }, // # wait_ms(-out FR count setup (C) + { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty + { SSITX, 0x000800C3 }, // # Command setting of SPI block + { SSITX, 0x0008010A }, // # wait_ms(-in line clock count setup (D) + { SSITX, 0x0000010A }, // + { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty + { SSITX, 0x000800C4 }, // # Command setting of SPI block + { SSITX, 0x00080160 }, // # Seep-in line clock count setup (E) + { SSITX, 0x00000160 }, // + { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty + { SSITX, 0x000800C5 }, // # Command setting of SPI block + { SSITX, 0x00080160 }, // # wait_ms(-in line clock count setup (F) + { SSITX, 0x00000160 }, // + { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty + { SSITX, 0x000800C6 }, // # Command setting of SPI block + { SSITX, 0x00080160 }, // # wait_ms(-in line clock setup (G) + { SSITX, 0x00000160 }, // + { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty + { SSITX, 0x000800C7 }, // # Command setting of SPI block + { SSITX, 0x00080133 }, // # Gamma 1 fine tuning (1) + { SSITX, 0x00000143 }, // + { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty + { SSITX, 0x000800C8 }, // # Command setting of SPI block + { SSITX, 0x00000144 }, // # Gamma 1 fine tuning (2) + { SSITX, 0x000800C9 }, // # Command setting of SPI block + { SSITX, 0x00000133 }, // # Gamma 1 inclination adjustment + { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty + { SSITX, 0x000800CA }, // # Command setting of SPI block + { SSITX, 0x00000100 }, // # Gamma 1 blue offset adjustment + { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty + { SSITX, 0x000800EC }, // # Command setting of SPI block + { SSITX, 0x00080102 }, // # Total number of horizontal clock cycles (1) [PCLK Sync. VGA setting] + { SSITX, 0x00000118 }, // + { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty + { SSITX, 0x000800CF }, // # Command setting of SPI block + { SSITX, 0x00000101 }, // # Blanking period control (1) [PCLK Sync. Table1 for VGA] + { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty + { SSITX, 0x000800D0 }, // # Command setting of SPI block + { SSITX, 0x00080110 }, // # Blanking period control (2) [PCLK Sync. Table1 for VGA] + { SSITX, 0x00000104 }, // + { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty + { SSITX, 0x000800D1 }, // # Command setting of SPI block + { SSITX, 0x00000101 }, // # CKV timing control on/off [PCLK Sync. Table1 for VGA] + { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty + { SSITX, 0x000800D2 }, // # Command setting of SPI block + { SSITX, 0x00080100 }, // # CKV1,2 timing control [PCLK Sync. Table1 for VGA] + { SSITX, 0x0000013A }, // + { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty + { SSITX, 0x000800D3 }, // # Command setting of SPI block + { SSITX, 0x00080100 }, // # OEV timing control [PCLK Sync. Table1 for VGA] + { SSITX, 0x0000013A }, // + { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty + { SSITX, 0x000800D4 }, // # Command setting of SPI block + { SSITX, 0x00080124 }, // # ASW timing control (1) [PCLK Sync. Table1 for VGA] + { SSITX, 0x0000016E }, // + { 0, 1 }, // wait_ms(1); // # Wait SPI fifo empty + { SSITX, 0x000800D5 }, // # Command setting of SPI block + { SSITX, 0x00000124 }, // # ASW timing control (2) [PCLK Sync. Table1 for VGA] + { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty + { SSITX, 0x000800ED }, // # Command setting of SPI block + { SSITX, 0x00080101 }, // # Total number of horizontal clock cycles (2) [PCLK Sync. Table1 for QVGA ] + { SSITX, 0x0000010A }, // + { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty + { SSITX, 0x000800D6 }, // # Command setting of SPI block + { SSITX, 0x00000101 }, // # Blanking period control (1) [PCLK Sync. Table2 for QVGA] + { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty + { SSITX, 0x000800D7 }, // # Command setting of SPI block + { SSITX, 0x00080110 }, // # Blanking period control (2) [PCLK Sync. Table2 for QVGA] + { SSITX, 0x0000010A }, // + { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty + { SSITX, 0x000800D8 }, // # Command setting of SPI block + { SSITX, 0x00000101 }, // # CKV timing control on/off [PCLK Sync. Table2 for QVGA] + { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty + { SSITX, 0x000800D9 }, // # Command setting of SPI block + { SSITX, 0x00080100 }, // # CKV1,2 timing control [PCLK Sync. Table2 for QVGA] + { SSITX, 0x00000114 }, // + { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty + { SSITX, 0x000800DE }, // # Command setting of SPI block + { SSITX, 0x00080100 }, // # OEV timing control [PCLK Sync. Table2 for QVGA] + { SSITX, 0x00000114 }, // + { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty + { SSITX, 0x000800DF }, // # Command setting of SPI block + { SSITX, 0x00080112 }, // # ASW timing control (1) [PCLK Sync. Table2 for QVGA] + { SSITX, 0x0000013F }, // + { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty + { SSITX, 0x000800E0 }, // # Command setting of SPI block + { SSITX, 0x0000010B }, // # ASW timing control (2) [PCLK Sync. Table2 for QVGA] + { SSITX, 0x000800E2 }, // # Command setting of SPI block + { SSITX, 0x00000101 }, // # Built-in oscillator frequency division setup [Frequency division ratio : 2 (60Hq) + { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty + { SSITX, 0x000800E3 }, // # Command setting of SPI block + { SSITX, 0x00000136 }, // # Built-in oscillator clock count setup + { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty + { SSITX, 0x000800E4 }, // # Command setting of SPI block + { SSITX, 0x00080100 }, // # CKV timing control for using build-in osc + { SSITX, 0x00000103 }, // + { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty + { SSITX, 0x000800E5 }, // # Command setting of SPI block + { SSITX, 0x00080102 }, // # OEV timing control for using build-in osc + { SSITX, 0x00000104 }, // + { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty + { SSITX, 0x000800E6 }, // # Command setting of SPI block + { SSITX, 0x00000103 }, // # DCEV timing control for using build-in osc + { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty + { SSITX, 0x000800E7 }, // # Command setting of SPI block + { SSITX, 0x00080104 }, // # ASW timing setup for using build-in osc(1) + { SSITX, 0x0000010A }, // + { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty + { SSITX, 0x000800E8 }, // # Command setting of SPI block + { SSITX, 0x00000104 }, // # ASW timing setup for using build-in osc(2) + + + { CLKENB, 0x000001EF }, // # SYS.CLKENB # DCLK enable + { START, 0x00000000 }, // # LCD.START # LCDC wait_ms( mode + { WRSTB, 0x0000003F }, // # LCD.WRSTB # write_client_reg( strobe + { RDSTB, 0x00000432 }, // # LCD.RDSTB # Read strobe + { PORT_ENB, 0x00000002 }, // # LCD.PORT_ENB # Asynchronous port enable + { VSYNIF, 0x00000000 }, // # LCD.VSYNCIF # VSYNC I/F mode set + { ASY_DATA, 0x80000000 }, // # LCD.ASY_DATx # Index setting of SUB LCDD + { ASY_DATB, 0x00000001 }, // # Oscillator start + { ASY_CMDSET, 0x00000005 }, // # LCD.ASY_CMDSET # Direct command transfer enable + { ASY_CMDSET, 0x00000004 }, // # LCD.ASY_CMDSET # Direct command transfer disable + { 0, 10 }, // wait_ms(10); + { ASY_DATA, 0x80000000 }, // # LCD.ASY_DATx # DUMMY write_client_reg(@*NOTE2 + { ASY_DATB, 0x80000000 }, // + { ASY_DATC, 0x80000000 }, // + { ASY_DATD, 0x80000000 }, // + { ASY_CMDSET, 0x00000009 }, // # LCD.ASY_CMDSET + { ASY_CMDSET, 0x00000008 }, // # LCD.ASY_CMDSET + { ASY_DATA, 0x80000007 }, // # LCD.ASY_DATx # Index setting of SUB LCDD + { ASY_DATB, 0x00004005 }, // # LCD driver control + { ASY_CMDSET, 0x00000005 }, // # LCD.ASY_CMDSET # Direct command transfer enable + { ASY_CMDSET, 0x00000004 }, // # LCD.ASY_CMDSET # Direct command transfer disable + { 0, 20 }, // wait_ms(20); + { ASY_DATA, 0x80000059 }, // # LCD.ASY_DATx # Index setting of SUB LCDD + { ASY_DATB, 0x00000000 }, // # LTPS I/F control + { ASY_CMDSET, 0x00000005 }, // # LCD.ASY_CMDSET # Direct command transfer enable + { ASY_CMDSET, 0x00000004 }, // # LCD.ASY_CMDSET # Direct command transfer disable + + { VSYNIF, 0x00000001 }, // # LCD.VSYNCIF # VSYNC I/F mode OFF + { PORT_ENB, 0x00000001 }, // # LCD.PORT_ENB # SYNC I/F output select + + /******************************/ + + { VSYNIF, 0x00000001 }, // VSYNC I/F mode OFF + { PORT_ENB, 0x00000001 }, // SYNC I/F mode ON + + { BITMAP1, 0x01E000F0 }, // MDC.BITMAP2 ); // Setup of PITCH size to Frame buffer1 + { BITMAP2, 0x01E000F0 }, // MDC.BITMAP3 ); // Setup of PITCH size to Frame buffer2 + { BITMAP3, 0x01E000F0 }, // MDC.BITMAP4 ); // Setup of PITCH size to Frame buffer3 + { BITMAP4, 0x00DC00B0 }, // MDC.BITMAP5 ); // Setup of PITCH size to Frame buffer4 + { CLKENB, 0x000001EF }, // SYS.CLKENB ); // DCLK supply + { PORT_ENB, 0x00000001 }, // LCD.PORT_ENB ); // Synchronous port enable + { PORT, 0x00000004 }, // LCD.PORT ); // Polarity of DE is set to high active + { PXL, 0x00000002 }, // LCD.PXL ); // ACTMODE 2 set (1st frame black data output) + { MPLFBUF, 0x00000000 }, // LCD.MPLFBUF ); // Select the reading buffer + { HCYCLE, 0x0000010b }, // LCD.HCYCLE ); // Setup to VGA size + { HSW, 0x00000003 }, // LCD.HSW + { HDE_START, 0x00000007 }, // LCD.HDE_START + { HDE_SIZE, 0x000000EF }, // LCD.HDE_SIZE + { VCYCLE, 0x00000285 }, // LCD.VCYCLE + { VSW, 0x00000001 }, // LCD.VSW + { VDE_START, 0x00000003 }, // LCD.VDE_START + { VDE_SIZE, 0x0000027F }, // LCD.VDE_SIZE + + { START, 0x00000001 }, // LCD.START ); // LCDC - Pixel data transfer start + + { 0, 10 }, // wait_ms( 10 ); + { SSITX, 0x000800BC }, // SPI.SSITX ); // Command setting of SPI block + { SSITX, 0x00000180 }, // Display data setup + { SSITX, 0x0008003B }, // Command setting of SPI block + { SSITX, 0x00000100 }, // Quad Data configuration - VGA + { 0, 1 }, // wait_ms( 1 ); // Wait SPI fifo empty + { SSITX, 0x000800B0 }, // Command setting of SPI block + { SSITX, 0x00000116 }, // Power supply ON/OFF control + { 0, 1 }, // wait_ms( 1 ); // Wait SPI fifo empty + { SSITX, 0x000800B8 }, // Command setting of SPI block + { SSITX, 0x000801FF }, // Output control + { SSITX, 0x000001F5 }, + { 0, 1 }, // wait_ms( 1); // Wait SPI fifo empty + { SSITX, 0x00000011 }, // wait_ms(-out (Command only) + { SSITX, 0x00000029 }, // Display on (Command only) + + { SYSTEM_BLOCK1_BASE, 0x00000002 }, // # wakeREQ -> GPIO + + { 0, 0 } +}; + +static void _panel_init(struct init_table *init_table) +{ + unsigned n; + + dprintf("panel_init()\n"); + + n = 0; + for(;;) { + if(init_table[n].reg == 0) { + if(init_table[n].val == 0) break; + mdelay(init_table[n].val); + } else { + mddi_remote_write(init_table[n].val, init_table[n].reg); + } + n++; + } + + dprintf("panel_init() done\n"); +} + +void panel_init(struct mddi_client_caps *client_caps) +{ + switch(client_caps->manufacturer_name) { + case 0xd263: // Toshiba + dprintf("Found Toshiba panel\n"); + _panel_init(toshiba_480x640_init_table); + break; + case 0x4474: //?? + if(client_caps->product_code == 0xc065) + dprintf("Found WVGA panel\n"); + break; + } +} + +void panel_poweron(void) +{ + gpio_write(88, 0); + gpio_output_enable(88, 1); + udelay(10); + gpio_write(88, 1); + mdelay(10); + //mdelay(1000); // uncomment for second stage boot +} + +void panel_backlight(int on) +{} diff --git a/boot/tests/irqtest.c b/boot/tests/irqtest.c new file mode 100644 index 0000000..e1080a5 --- /dev/null +++ b/boot/tests/irqtest.c @@ -0,0 +1,122 @@ +/* Copyright 2007, Google Inc. */ + +#include "boot.h" + +#include "msm7200gpt.h" +#include "msm7200vic.h" +#include "msm7200uart.h" +#include "irqs.h" + +#define uwr(v,a) msm_writel(v, MSM_UART1_BASE + (a)) +#define urd(a) msm_readl(MSM_UART1_BASE + (a)) + +#define DIV 128 + +static unsigned scount = 0; +static unsigned ticks = 0; +static unsigned total = 0; + +void gpt_handler(unsigned n) +{ + msm_writel(1 << INT_GP_TIMER_EXP, VIC_INT_CLEAR0); + + scount++; + total++; + if(scount == DIV) { + scount = 0; + dprintf("TICK %d\n", ticks++); + } +#if 0 + msm_writel(0, GPT_CLEAR); + while(msm_readl(GPT_COUNT_VAL) != 0) ; +#endif +} + +void uart_handler(unsigned n) +{ + dprintf("uart_handler()\n"); + if(urd(UART_SR) & UART_SR_RX_READY) { + dprintf("<%c>", urd(UART_RF)); + } + + msm_writel(1 << INT_UART1, VIC_INT_CLEAR0); +} + +/* delays about one second at 19.2MHz */ +void pause() +{ + int delay = 19200000 / 25; + while(delay-- > 0) { + asm("nop\n"); + } +} + +void scantest(void) +{ + unsigned n, r, c, t; + char map[32]; + + map[16] = 0; + + dprintf("scantest\n"); + + /* setup rows */ + for(n = 33; n < 36; n++) { + gpio_output_enable(n, 0); + gpio_write(n, 0); + } + + /* setup columns */ + for(n = 36; n < 41; n++) { + gpio_output_enable(n, 0); + gpio_write(n, 0); + } + + for(;;) { + n = 0; + for(r = 0; r < 3; r++) { + gpio_output_enable(33+r, 1); + for(c = 0; c < 5; c++) { + if(gpio_read(36+c)) { + map[n++] = '-'; + } else { + map[n++] = 'X'; + } + } + gpio_output_enable(33+r, 0); + } + + dprintf("[ %s ]\n", map); + for(t = 0; t < 100000; t++) asm("nop;"); + } +} + +extern unsigned BOOTLOADER_HEAP; + +int _main(void) +{ + unsigned tmp = 0; + + scantest(); +// arm11_clock_init(); + + dprintf("\n\nHello, ARM1136 World!\n"); + + print_cpu_speed(); + + irq_init(); + irq_install(INT_GP_TIMER_EXP, gpt_handler, 1); + irq_install(INT_UART1, uart_handler, 0); + + msm_writel(0, GPT_CLEAR); + msm_writel(32768 / DIV, GPT_MATCH_VAL); + msm_writel(GPT_ENABLE_EN | GPT_ENABLE_CLR_ON_MATCH_EN, GPT_ENABLE); + + irq_unmask(INT_GP_TIMER_EXP); + irq_unmask(INT_UART1); + + uwr(UART_IMR_RXLEV, UART_IMR); + + for(;;) ; + +} diff --git a/boot/tests/timertest.c b/boot/tests/timertest.c new file mode 100644 index 0000000..7e2fc71 --- /dev/null +++ b/boot/tests/timertest.c @@ -0,0 +1,110 @@ +/* Copyright 2007, Google Inc. */ + +#include "msm7200gpt.h" +#include "msm7200uart.h" +#include "msm7200vic.h" +#include "irqs.h" + +#include "boot.h" + +void pause_1s() +{ + int delay = 19200000 / 25; + while(delay-- > 0) { + asm("nop\n"); + } +} + +void vic_init(void) +{ + /* select level interrupts */ + msm_writel(0, VIC_INT_TYPE0); + msm_writel(0, VIC_INT_TYPE1); + /* select IRQ for all INTs */ + msm_writel(0, VIC_INT_SELECT0); + msm_writel(0, VIC_INT_SELECT1); + /* disable all INTs */ + msm_writel(0, VIC_INT_EN0); + msm_writel(0, VIC_INT_EN1); + /* enable IRQs */ + + /* don't use 1136 vic */ + msm_writel(0, VIC_CONFIG); + + msm_writel(1, VIC_INT_MASTEREN); + enable_irq(); +} + +volatile int int_count = -10; + +int _main(void) +{ + unsigned r[6]; + unsigned n; + int last_int_count = int_count; + + dcc_puts("\n\nHello, ARM1136 World!\n"); + + read_isa_regs(r); + for(n = 0; n < 6; n++) { + dprintf("ISA%d = %x\n", n, r[0]); + } + + for(;;); + + +#if 0 + uart_init(); + uart_test(); +#endif + +// msm_writel(0, GPT_ENABLE); +// msm_writel(19200000 / 10, GPT_MATCH_VAL); +// msm_writel(19200, GPT_MATCH_VAL); + msm_writel(32768, GPT_MATCH_VAL); + msm_writel(0, GPT_CLEAR); + msm_writel(GPT_ENABLE_EN | GPT_ENABLE_CLR_ON_MATCH_EN, GPT_ENABLE); +// msm_writel(GPT_ENABLE_EN, GPT_ENABLE); + + msm_writel(1 << INT_GP_TIMER_EXP, VIC_INT_CLEAR0); + + /* select level interrupts */ + msm_writel(1 << INT_GP_TIMER_EXP, VIC_INT_TYPE0); + msm_writel(0, VIC_INT_TYPE1); + /* select IRQ for all INTs */ + msm_writel(0, VIC_INT_SELECT0); + msm_writel(0, VIC_INT_SELECT1); + /* disable all INTs */ + msm_writel(0, VIC_INT_EN0); + msm_writel(0, VIC_INT_EN1); + /* enable IRQs */ + + /* don't use 1136 vic */ + msm_writel(0, VIC_CONFIG); + + msm_writel(1, VIC_INT_MASTEREN); + + msm_writel(1 << INT_GP_TIMER_EXP, VIC_INT_EN0); + enable_irq(); + + dprintf("WHEE!\n"); + + for(;;) { + if(int_count != last_int_count) { + last_int_count++; + dprintf("COUNT %d\n", last_int_count); + } + n = msm_readl(GPT_COUNT_VAL); + } + return 0; +} + +void irq_handler(void) +{ + unsigned x, y, n; + + x = msm_readl(VIC_IRQ_VEC_PEND_RD); + msm_writel(1 << INT_GP_TIMER_EXP, VIC_INT_CLEAR0); + y = msm_readl(VIC_IRQ_VEC_PEND_RD); + int_count++; +} diff --git a/boot/tools/Android.mk b/boot/tools/Android.mk new file mode 100644 index 0000000..131a281 --- /dev/null +++ b/boot/tools/Android.mk @@ -0,0 +1,11 @@ +LOCAL_PATH:= $(call my-dir) + +include $(CLEAR_VARS) +LOCAL_SRC_FILES := mkheader.c +LOCAL_MODULE := mkheader +include $(BUILD_HOST_EXECUTABLE) + + +include $(CLEAR_VARS) +LOCAL_PREBUILT_EXECUTABLES:= mkbootloader +include $(BUILD_HOST_PREBUILT) diff --git a/boot/tools/mkbootloader b/boot/tools/mkbootloader new file mode 100755 index 0000000..8b3d040 --- /dev/null +++ b/boot/tools/mkbootloader @@ -0,0 +1,22 @@ +#!/bin/sh + +INSTALL="$1" + +if [ -z "$OUT" ] ; then + echo "Your build environment is not set up."; + exit 1; +fi; + +if [ "$INSTALL" = "" ] +then + INSTALL="$OUT" +fi + +echo header: $INSTALL/appsboothd.mbn +echo binary: $INSTALL/appsboot.mbn + +cp -f $OUT/usbloader $INSTALL/appsboot.mbn +$OUT/../../../host/linux-x86/bin/mkheader $OUT/usbloader $INSTALL/appsboothd.mbn + + + diff --git a/boot/tools/mkheader.c b/boot/tools/mkheader.c new file mode 100644 index 0000000..302bea2 --- /dev/null +++ b/boot/tools/mkheader.c @@ -0,0 +1,55 @@ +/* Copyright 2007, Google Inc. */ + +#include <stdio.h> +#include <stdlib.h> +#include <unistd.h> +#include <fcntl.h> + +#include <sys/stat.h> + +int main(int argc, char *argv[]) +{ + struct stat s; + unsigned size, base; + unsigned magic[10]; + int fd; + + if(argc != 3) { + fprintf(stderr,"usage: mkheader <bin> <hdr>\n"); + return -1; + } + + if(stat(argv[1], &s)) { + perror("cannot stat binary"); + return -1; + } + + size = s.st_size; + base = 0; + + magic[0] = 0x00000005; /* appsbl */ + magic[1] = 0x00000002; /* nand */ + magic[2] = 0x00000000; + magic[3] = base; + magic[4] = size; + magic[5] = size; + magic[6] = size + base; + magic[7] = 0x00000000; + magic[8] = size + base; + magic[9] = 0x00000000; + + fd = open(argv[2], O_WRONLY | O_CREAT | O_TRUNC, 0644); + if(fd < 0) { + perror("cannot open header for writing"); + return -1; + } + if(write(fd, magic, sizeof(magic)) != sizeof(magic)) { + perror("cannot write header"); + close(fd); + unlink(argv[2]); + return -1; + } + close(fd); + + return 0; +} diff --git a/halibut_keypad.kcm b/halibut_keypad.kcm new file mode 100644 index 0000000..9f96b69 --- /dev/null +++ b/halibut_keypad.kcm @@ -0,0 +1,66 @@ +[type=NUMERIC] + +# keycode display number base caps fn caps_fn + +A 'A' '#' 'a' 'A' '#' 0x00 +B 'B' '<' 'b' 'B' '<' 0x00 +C 'C' '9' 'c' 'C' '9' 0x00E7 +D 'D' '5' 'd' 'D' '5' 0x00 +E 'E' '2' 'e' 'E' '2' 0x0301 +F 'F' '6' 'f' 'F' '6' 0x00A5 +G 'G' '-' 'g' 'G' '-' '_' +H 'H' '[' 'h' 'H' '[' '{' +I 'I' '$' 'i' 'I' '$' 0x0302 +J 'J' ']' 'j' 'J' ']' '}' +K 'K' '"' 'k' 'K' '"' '~' +L 'L' ''' 'l' 'L' ''' '`' +M 'M' '%' 'm' 'M' '%' 0x00 +N 'N' '>' 'n' 'N' '>' 0x0303 +O 'O' '(' 'o' 'O' '(' 0x00 +P 'P' ')' 'p' 'P' ')' 0x00 +Q 'Q' '*' 'q' 'Q' '*' 0x0300 +R 'R' '3' 'r' 'R' '3' 0x20AC +S 'S' '4' 's' 'S' '4' 0x00DF +T 'T' '+' 't' 'T' '+' 0x00A3 +U 'U' '&' 'u' 'U' '&' 0x0308 +V 'V' '=' 'v' 'V' '=' '^' +W 'W' '1' 'w' 'W' '1' 0x00 +X 'X' '8' 'x' 'X' '8' 0xEF00 +Y 'Y' '!' 'y' 'Y' '!' 0x00A1 +Z 'Z' '7' 'z' 'Z' '7' 0x00 + +COMMA ',' ',' ',' ';' ';' '|' +PERIOD '.' '.' '.' ':' ':' 0x2026 +AT '@' '0' '@' '0' '0' 0x2022 +SLASH '/' '/' '/' '?' '?' '\' + +SPACE 0x20 0x20 0x20 0x20 0xEF01 0xEF01 +ENTER 0xa 0xa 0xa 0xa 0xa 0xa + +# on pc keyboards +TAB 0x9 0x9 0x9 0x9 0x9 0x9 +0 '0' '0' '0' ')' ')' ')' +1 '1' '1' '1' '!' '!' '!' +2 '2' '2' '2' '@' '@' '@' +3 '3' '3' '3' '#' '#' '#' +4 '4' '4' '4' '$' '$' '$' +5 '5' '5' '5' '%' '%' '%' +6 '6' '6' '6' '^' '^' '^' +7 '7' '7' '7' '&' '&' '&' +8 '8' '8' '8' '*' '*' '*' +9 '9' '9' '9' '(' '(' '(' + +GRAVE '`' '`' '`' '~' '`' '~' +MINUS '-' '-' '-' '_' '-' '_' +EQUALS '=' '=' '=' '+' '=' '+' +LEFT_BRACKET '[' '[' '[' '{' '[' '{' +RIGHT_BRACKET ']' ']' ']' '}' ']' '}' +BACKSLASH '\' '\' '\' '|' '\' '|' +SEMICOLON 'A' '%' ';' 'A' '%' 0x00 +APOSTROPHE 'A' '%' ''' 'A' '%' 0x00 +STAR '*' '*' '*' '*' '*' '*' +POUND '#' '#' '#' '#' '#' '#' +PLUS '+' '+' '+' '+' '+' '+' + + + diff --git a/halibut_keypad.kl b/halibut_keypad.kl new file mode 100644 index 0000000..10b88ba --- /dev/null +++ b/halibut_keypad.kl @@ -0,0 +1,75 @@ +key 2 1 +key 3 2 +key 4 3 +key 5 4 +key 6 5 +key 7 6 +key 8 7 +key 9 8 +key 10 9 +key 11 0 +key 158 BACK WAKE_DROPPED +key 230 SOFT_RIGHT WAKE +key 60 SOFT_RIGHT WAKE +key 107 ENDCALL WAKE_DROPPED +key 62 ENDCALL WAKE_DROPPED +key 229 MENU WAKE_DROPPED +key 59 MENU WAKE_DROPPED +key 228 POUND +key 227 STAR +key 231 CALL WAKE_DROPPED +key 61 CALL WAKE_DROPPED +key 232 DPAD_CENTER WAKE_DROPPED +key 108 DPAD_DOWN WAKE_DROPPED +key 103 DPAD_UP WAKE_DROPPED +key 102 HOME WAKE +key 105 DPAD_LEFT WAKE_DROPPED +key 106 DPAD_RIGHT WAKE_DROPPED +key 115 VOLUME_UP +key 114 VOLUME_DOWN +key 116 POWER WAKE +key 212 SLASH +key 213 MENU WAKE_DROPPED + +key 16 Q +key 17 W +key 18 E +key 19 R +key 20 T +key 21 Y +key 22 U +key 23 I +key 24 O +key 25 P + +key 30 A +key 31 S +key 32 D +key 33 F +key 34 G +key 35 H +key 36 J +key 37 K +key 38 L +key 14 DEL + +key 44 Z +key 45 X +key 46 C +key 47 V +key 48 B +key 49 N +key 50 M +key 51 COMMA +key 52 PERIOD +key 28 ENTER + +key 56 ALT_LEFT +key 42 SHIFT_LEFT +key 215 AT +key 57 SPACE +key 53 SLASH +key 127 SYM +key 100 ALT_RIGHT + +key 399 GRAVE diff --git a/qcom_surf.mk b/qcom_surf.mk new file mode 100644 index 0000000..8562798 --- /dev/null +++ b/qcom_surf.mk @@ -0,0 +1,10 @@ +PRODUCT_PACKAGES := \ + IM \ + VoiceDialer + + +$(call inherit-product, build/target/product/generic_with_google.mk) + +# Overrides +PRODUCT_NAME := qcom_surf +PRODUCT_DEVICE := surf diff --git a/scripts/a11.cmm b/scripts/a11.cmm new file mode 100644 index 0000000..c984184 --- /dev/null +++ b/scripts/a11.cmm @@ -0,0 +1,21 @@ +; MSM7200 ARM11 in JTAG Direct Mode + +system.option.TRST ON +system.option.CFLUSH ON +system.option.ResBreak ON +system.option.EnReset ON +system.option.WaitReset ON +system.jtagclock RTCK + +sys.cpu arm1136j +system.multicore irpre 0. +system.multicore drpre 0. +system.multicore irpost 0. +system.multicore drpost 0. +sys.mode attach + +if state.run() +( + break +) + diff --git a/scripts/a9.cmm b/scripts/a9.cmm new file mode 100644 index 0000000..2cd7046 --- /dev/null +++ b/scripts/a9.cmm @@ -0,0 +1,15 @@ +; MSM7200 ARM9 in JTAG Direct Mode + +system.option.TRST ON +system.option.CFLUSH ON +system.option.ResBreak ON +system.option.EnReset ON +system.option.WaitReset ON +system.jtagclock RTCK + +sys.cpu arm926ej +system.multicore irpre 0. +system.multicore drpre 0. +system.multicore irpost 0. +system.multicore drpost 0. +sys.mode attach diff --git a/scripts/boot.cmm b/scripts/boot.cmm new file mode 100644 index 0000000..36eb18e --- /dev/null +++ b/scripts/boot.cmm @@ -0,0 +1,22 @@ + +sys.cpu arm1136j +sys.jtagclock rtck +sys.mode attach +if state.run() +( + break +) + +do setup + +data.load.elf "&(OUT)obj/EXECUTABLES/bootloader_intermediates/bootloader.elf" /relpath /path ../boot/ + +tronchip.set dabort off +tronchip.set pabort off + +term.reset +term.size 50 100 +term.scroll.on +term + +go diff --git a/scripts/c11.cmm b/scripts/c11.cmm new file mode 100644 index 0000000..ee83843 --- /dev/null +++ b/scripts/c11.cmm @@ -0,0 +1,15 @@ +; MSM7200 ARM11 in JTAG Chained Mode + +system.option.TRST ON +system.option.CFLUSH ON +system.option.ResBreak ON +system.option.EnReset ON +system.option.WaitReset ON +system.jtagclock RTCK + +sys.cpu arm1136j +system.multicore irpre 0. +system.multicore drpre 0. +system.multicore irpost 4. +system.multicore drpost 1. +sys.mode attach diff --git a/scripts/c9.cmm b/scripts/c9.cmm new file mode 100644 index 0000000..65b8ecd --- /dev/null +++ b/scripts/c9.cmm @@ -0,0 +1,15 @@ +; MSM7200 ARM9 in JTAG Chained Mode + +system.option.TRST ON +system.option.CFLUSH ON +system.option.ResBreak ON +system.option.EnReset ON +system.option.WaitReset ON +system.jtagclock RTCK + +sys.cpu arm926ej +system.multicore irpre 5. +system.multicore drpre 1. +system.multicore irpost 0. +system.multicore drpost 0. +sys.mode attach diff --git a/scripts/chain.cmm b/scripts/chain.cmm new file mode 100644 index 0000000..0a1dd99 --- /dev/null +++ b/scripts/chain.cmm @@ -0,0 +1,73 @@ +;; +;; Script to attach to the ARM9 on the MSM7200 Primary JTAG interface +;; and reconfigure the Primary JTAG interface to ARM9+ARM11 w/ RTCK. +;; chained mode. The MSM7200 'MODE' pins must be 0001 for this to work. +;; +;; TDI -> ARM9 (4 bit IR) -> ARM11 (5 bit IR) -> TDO +;; + +; these are common to both the ARM9 and the ARM11 +system.option.TRST ON +system.option.CFLUSH ON +system.option.ResBreak ON +system.option.EnReset ON +system.option.WaitReset ON +system.jtagclock RTCK + +print "ARM9: attaching" +sys.cpu arm926ej +system.multicore irpre 0. +system.multicore drpre 0. +system.multicore irpost 0. +system.multicore drpost 0. + +sys.mode attach +if state.run() +( + break +) + +print "ARM9: selecting chained JTAG mode (expect bus error)" +; we're probably going to error out after +; we thwack the mode register +on error gosub +( + return +) + +; reconfigure primary jtag mode register for arm9+arm11 w/ RTCK +; TLMM_INT_JTAG_CTL = 9 +;d.s 0xa860020c %long 0x1f +;d.s 0xa860020c %long 0x0 +d.s 0xa900026c %long 9 + +system.down + +on error + +sys.cpu arm926ej +system.multicore irpre 5. +system.multicore drpre 1. +system.multicore irpost 0. +system.multicore drpost 0. + +print "ARM9: resuming execution" +sys.mode attach + +;confirm that this worked (it did) +;local ® +;®=data.long(d:0xa900026c) +;print "ARM9: TLMM_INT_JTAG_CTL = ®" + +go +system.down + +print "ARM11: attaching" +sys.cpu arm1136j +system.multicore irpre 0. +system.multicore drpre 0. +system.multicore irpost 4. +system.multicore drpost 1. + +sys.mode attach +print "ARM11: ready"
\ No newline at end of file diff --git a/scripts/dcc.cmm b/scripts/dcc.cmm new file mode 100644 index 0000000..1a6264d --- /dev/null +++ b/scripts/dcc.cmm @@ -0,0 +1,21 @@ + +sys.cpu arm1136j +sys.jtagclock rtck + +sys.mode attach + +if state.run() +( + break +) + +tronchip.set dabort off +tronchip.set pabort off + +term.reset +term.size 50 100 +term.scroll.on +term + +go + diff --git a/scripts/debug.cmm b/scripts/debug.cmm new file mode 100644 index 0000000..a843533 --- /dev/null +++ b/scripts/debug.cmm @@ -0,0 +1,74 @@ +;; Copyright 2007, Google Inc. +;; +;; script to communicate with debug/utility programs using the jtag.c interface +;; + +local &cmd +local &arg0 +local &arg1 +local &arg2 + +local &pc +local &str +local &n + +entry &cmd &arg0 &arg1 &arg2 + +area + +print +mainloop: + +b.reset +b.set jtag_hook /onchip +go +wait !run() +b.reset + +&pc=y.varname(A:register(pc)) +if ("&pc"!="jtag_hook") +( + print "ERROR: not stopped at jtag_hook()" + enddo 1 +) + +;; if there's a message, process it +;; and then keep waiting (if it's non-final) +;; +&n=data.long(_jtag_msg) +if (&n==3) +( + print "> " data.string(_jtag_msg_buffer) + d.s _jtag_msg %long 0 + goto mainloop +) +if (&n==1) +( + print + print "OKAY: " data.string(_jtag_msg_buffer) + d.s _jtag_msg %long 0 + enddo 0 +) +if (&n==2) +( + print + print "FAIL: " data.string(_jtag_msg_buffer) + d.s _jtag_msg %long 0 + enddo 1 +) + +if ("&cmd"!="") +( + &n=data.long(_jtag_cmd) + if (&n!=0) + goto mainloop + + d.s _jtag_cmd_buffer "&cmd" + d.s _jtag_arg0 %long &arg0 + d.s _jtag_arg1 %long &arg1 + d.s _jtag_arg2 %long &arg2 + d.s _jtag_cmd %long 1 + &cmd="" +) + +goto mainloop diff --git a/scripts/flash.cmm b/scripts/flash.cmm new file mode 100644 index 0000000..1f46d0a --- /dev/null +++ b/scripts/flash.cmm @@ -0,0 +1,67 @@ +;; Copyright 2007, Google Inc. +;; flash driver script +;; + +local &arg_ptn +local &arg_img +local &arg_extra +local &arg_size + +local &result +local &img_size +local &status + +ENTRY &arg_ptn &arg_img &arg_extra + +do setup.cmm + +if ("&arg_extra"!="again") +( + area + area.clear +) + +if ("&arg_ptn"=="") +( + print "USAGE: do flash <partition> <image>" + enddo +) + +if ("&arg_extra"!="again") +( + sys.down + sys.cpu arm1136j + sys.jtagclock rtck + sys.mode attach + if state.run() + ( + break + ) + data.load.elf "&(NANDWRITE)" +) + +if ("&arg_img"=="MEMORY") +( + &img_size=&arg_extra +) +else +( + if ("&arg_img"!="") + ( + if y.exist("\\flashimg") + symbol.delete \\flashimg + data.load.binary &arg_img 0x10001000 /name flashimg /noclear + &img_size=y.sizeof("\\flashimg") + ) + else + ( + &img_size=0 + ) +) + +&arg_ptn="flash:&arg_ptn" + +do debug &arg_ptn 0x10001000 &img_size + +entry &result +enddo &result diff --git a/scripts/flashall.cmm b/scripts/flashall.cmm new file mode 100644 index 0000000..ad4a841 --- /dev/null +++ b/scripts/flashall.cmm @@ -0,0 +1,36 @@ + +local &status + +do setup.cmm + +do flash userdata +entry &status +if (&status!=0) + enddo +print + +if ("&KERNEL"!="") +( + do flash kernel &KERNEL again + entry &status + if (&status!=0) + enddo + print +) + +if ("&RAMDISK"!="") +( + do flash ramdisk &RAMDISK again + entry &status + if (&status!=0) + enddo + print +) + +if ("&SYSTEM_IMG"!="") +( + do flash system &SYSTEM_IMG again + entry &status + if (&status!=0) + enddo +) diff --git a/scripts/flashbootimg.cmm b/scripts/flashbootimg.cmm new file mode 100644 index 0000000..7fc0648 --- /dev/null +++ b/scripts/flashbootimg.cmm @@ -0,0 +1,139 @@ + +do setup.cmm + +local &addr +local &size +local &pagesize +local &hdr + +sys.down +sys.cpu arm1136j +sys.jtagclock rtck +sys.mode attach +if state.run() + break + +&pagesize=0x800 +&hdr=0x10001000 + +; 000 magic +; 008 kernel_size +; 00c kernel_addr +; 010 ramdisk_size +; 014 ramdisk_addr +; 018 second_size +; 01c second_addr +; 020 tags_addr +; 024 page_size +; 028 unused0/1 +; 030 unused2/3/4/5 +; 040 cmdline + +; fill boot image header with 0s initially +; +d.s &hdr++&pagesize %byte 0 +;d.s &hdr++0x300000 %long 0 + +d.s &hdr+0x000 "ANDROID!" +d.s &hdr+0x00c %long &KERNEL_ADDR +d.s &hdr+0x014 %long &RAMDISK_ADDR +if ("&SECOND_STAGE"!="") +( + d.s &hdr+0x01c %long &SECOND_STAGE_ADDR +) +d.s &hdr+0x020 %long &TAGS_ADDR +d.s &hdr+0x024 %long &pagesize +d.s &hdr+0x040 "&CMDLINE" + +; advance to the kernel slot +; +&addr=&hdr+&pagesize + +; load the kernel image +; +if y.exist("\\flashimg") + symbol.delete \\flashimg +data.load.binary &KERNEL &addr /name flashimg /noclear +&size=y.sizeof("\\flashimg") + +d.s &hdr+0x008 %long &size + +; advance addr to next page-aligned region > &size +; +&addr=&addr+((&size+(&pagesize-1))&(~(&pagesize-1))) + +; load the ramdisk image +; +if y.exist("\\flashimg") + symbol.delete \\flashimg +data.load.binary &RAMDISK &addr /name flashimg /noclear +&size=y.sizeof("\\flashimg") + +d.s &hdr+0x010 %long &size + +&addr=&addr+((&size+(&pagesize-1))&(~(&pagesize-1))) + +if ("&SECOND_STAGE"!="") +( + if ("&SECOND_STAGE"=="wait") + ( + d.s &addr %long 0xeafffffe + &size= 4 + ) + else if ("&SECOND_STAGE"=="fixup") + ( + local &ip + &ip= &addr + ;gosub emit b &addr + gosub emit mov r1, #&MACHINE_ID + gosub emit mov r4, #0 + gosub emit str r4, [r2, #0xd0] ; terminate tags + + ; change kernel commandline + gosub emit mov r4, #0 + gosub emit strb r4, [r2, #0x28] ; no console + ;gosub emit strb r4, [r2, #0x35] ; tty1 only + ;gosub emit strb r4, [r2, #0x45] ; tty1 + ttyMSM0 only + + ;gosub emit b &ip + gosub emit mov r4, #0x98000000 ; CPLD base + gosub emit ldrb r5, [r4, #0x0a] ; INT2 + gosub emit tst r5, #0x10 ; NAVI_ACT# + gosub emit beq &ip-8 + gosub emit tst r5, #2 ; NAVI_DOWN# + gosub emit moveq r5, #0xab + gosub emit streqb r5, [r4, #0x00] ; MISC1 + gosub emit beq &ip + ;gosub emit b &ip + gosub emit mov r4, #(&KERNEL_ADDR&0xff000000) + gosub emit add r4, r4, #(&KERNEL_ADDR&0x00ff0000) + gosub emit add r4, r4, #(&KERNEL_ADDR&0x0000ff00) + gosub emit add pc, r4, #(&KERNEL_ADDR&0x000000ff) + &size= &ip-&addr + ) + else + ( + ; load the second stage image + ; + if y.exist("\\flashimg") + symbol.delete \\flashimg + data.load.binary &SECOND_STAGE &addr /name flashimg /noclear + &size=y.sizeof("\\flashimg") + ) + + d.s &hdr+0x018 %long &size + + &addr=&addr+((&size+(&pagesize-1))&(~(&pagesize-1))) +) + +do flash boot MEMORY (&addr-&hdr) +;do flash recovery MEMORY (&addr-&hdr) + +enddo + +emit: + ENTRY &op1 &op2 &op3 &op4 &op5 + d.a &ip &op1 &op2 &op3 &op4 &op5 + &ip=&ip+4 + RETURN + diff --git a/scripts/flashsystem.cmm b/scripts/flashsystem.cmm new file mode 100644 index 0000000..2080bda --- /dev/null +++ b/scripts/flashsystem.cmm @@ -0,0 +1,7 @@ + +do setup.cmm + +if ("&SYSTEM_IMG"!="") +( + do flash system &SYSTEM_IMG +) diff --git a/scripts/irqtest.cmm b/scripts/irqtest.cmm new file mode 100644 index 0000000..1f78749 --- /dev/null +++ b/scripts/irqtest.cmm @@ -0,0 +1,4 @@ +sys.cpu arm1136j +sys.jtagclock rtck +data.load.elf ../boot/irqtest.elf +go diff --git a/scripts/linux.cmm b/scripts/linux.cmm new file mode 100644 index 0000000..257dd53 --- /dev/null +++ b/scripts/linux.cmm @@ -0,0 +1,82 @@ + +sys.down + +do setup.cmm + +sys.cpu arm1136j +sys.jtagclock rtck + +sys.mode attach + +if state.run() +( + break +) + +data.load &KERNEL &KERNEL_ADDR /name kernel +data.load.ELF &KERNEL_ELF /NOCODE /RELPATH /PATH &KERNEL_SRC + +if ("&RAMDISK"!="") +( + data.load &RAMDISK &RAMDISK_ADDR /name ramdisk /noclear + &RAMDISK_SIZE=y.sizeof("\\ramdisk") +) +else +( + &RAMDISK_SIZE=0 +) + +local &tags +&tags=&TAGS_ADDR + +d.s &tags+0x00 %long 2 +d.s &tags+0x04 %long 0x54410001 +&tags=&tags+0x08 + +if (&RAMDISK_SIZE!=0) +( + d.s &tags+0x00 %long 4 + d.s &tags+0x04 %long 0x54420005 + d.s &tags+0x08 %long &RAMDISK_ADDR + d.s &tags+0x0C %long &RAMDISK_SIZE + &tags=&tags+0x10 +) + +if ("&CMDLINE"!="") +( + d.s &tags+0x00 %long 0x42 + d.s &tags+0x04 %long 0x54410009 + &tags=&tags+0x08 + d.s &tags++0x100 %byte 0 + d.s &tags "&CMDLINE" + &tags=&tags+0x100 +) + +d.s &tags+0x00 %long 0 +d.s &tags+0x04 %long 0 + + +register.set pc &KERNEL_ADDR +register.set r0 0 +register.set r1 &MACHINE_ID +register.set r2 &TAGS_ADDR + +tronchip.set dabort off +tronchip.set pabort off + +term.reset +term.size 50 100 +term.scroll.on +term + +break.select program onchip +break.delete +;break.set __irq_usr +;break.set __irq_svc +;break.set pte_hack +;break.set cpu_v6_set_pte +;break.set panic +;break.set do_DataAbort\10 + +go + diff --git a/scripts/setup.cmm b/scripts/setup.cmm new file mode 100644 index 0000000..60d214a --- /dev/null +++ b/scripts/setup.cmm @@ -0,0 +1,78 @@ +; Copyright 2007, Google Inc. + +; files +; +global &KERNEL +global &KERNEL_ELF +global &KERNEL_SRC +global &RAMDISK +global &SECOND_STAGE +global &SYSTEM_IMG +global &CMDLINE +global &NANDWRITE_ELF + +; memory locations +; +global &TAGS_ADDR +global &KERNEL_ADDR +global &RAMDISK_ADDR +global &RAMDISK_SIZE +global &SECOND_STAGE_ADDR +global &SYSTEM_IMG_ADDR +global &SYSTEM_IMG_SIZE + +; misc +global &MACHINE_ID + +global &TOP +global &OUT +global &NANDWRITE + +; relative path back up to the top of the device tree from here +; +&TOP="../../../" + +; directory where the results of the device build live +; +&OUT="&(TOP)out/target/product/surf/" + +; ---------------------------------------------------------------------- +; configure your memory layout, binary images, and commandline below: +; ---------------------------------------------------------------------- + +&KERNEL_ADDR= 0x10008000 +&RAMDISK_ADDR= 0x11000000 +&TAGS_ADDR= 0x10000100 +&SECOND_STAGE_ADDR= 0x00300000 +&SYSTEM_IMG_ADDR= 0x11000000 + +&MACHINE_ID= 0x59f ; halibut +;&MACHINE_ID= 0x5a0 ; trout + +;&KERNEL_SRC= "../../../git/kernel-msm/" +&KERNEL_SRC= "&(TOP)../kernel/" +;&KERNEL_SRC= "/scratch/linux-msm/" +;&KERNEL_SRC= "/work/kernel/mergebox/" +&KERNEL= "&(KERNEL_SRC)arch/arm/boot/zImage" +&KERNEL_ELF= "&(KERNEL_SRC)vmlinux" + +&SECOND_STAGE="" +;&SECOND_STAGE= "wait" +;&SECOND_STAGE= "&(OUT)usbloader" + +&RAMDISK= "&(OUT)ramdisk.img" +&SYSTEM_IMG= "&(OUT)system.img" +&NANDWRITE= "&(OUT)obj/EXECUTABLES/nandwrite_intermediates/nandwrite.elf" + +;&CMDLINE= "mem=50M" +;&CMDLINE= "mem=64M" +&CMDLINE= "mem=110M" +&CMDLINE= "&(CMDLINE) console=ttyMSM2 androidboot.console=ttyMSM2" +;&CMDLINE= "&(CMDLINE) board_halibut.ffa=1" +;&CMDLINE= "&(CMDLINE) console=tty1" +;&CMDLINE= "&(CMDLINE) androidboot.console=ttyMSM0" +;&CMDLINE= "&(CMDLINE) console=ttyDCC0" +;&CMDLINE= "&(CMDLINE) androidboot.console=ttyDCC0" +;&CMDLINE= "&(CMDLINE) console=null" + +; ---------------------------------------------------------------------- diff --git a/scripts/usb.cmm b/scripts/usb.cmm new file mode 100644 index 0000000..8a9963e --- /dev/null +++ b/scripts/usb.cmm @@ -0,0 +1,22 @@ + +sys.cpu arm1136j +sys.jtagclock rtck +sys.mode attach +if state.run() +( + break +) + +do setup + +data.load.elf "&(OUT)obj/EXECUTABLES/usbloader_intermediates/usbloader.elf" /relpath /path ../boot/ + +tronchip.set dabort off +tronchip.set pabort off + +term.reset +term.size 50 100 +term.scroll.on +;term + +go diff --git a/system.prop b/system.prop new file mode 100644 index 0000000..5134d29 --- /dev/null +++ b/system.prop @@ -0,0 +1,6 @@ +# +# system.prop for surf +# + +rild.libpath=/system/lib/libreference-ril.so +rild.libargs=-d /dev/smd0 |