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| author | Bernhard Rosenkränzer <Bernhard.Rosenkranzer@linaro.org> | 2014-10-20 23:02:40 +0200 |
|---|---|---|
| committer | Bernhard Rosenkränzer <Bernhard.Rosenkranzer@linaro.org> | 2014-10-20 23:02:40 +0200 |
| commit | 091dcb8140705c70e89ba9d42f5e4f53a4b8f2fd (patch) | |
| tree | fa7fc089278c436c92ec60310d1bc618e562fd03 | |
| parent | 14b76f84cd0c55d9da6a231e9ae2a2afe2134f3d (diff) | |
| download | gcc-patches-091dcb8140705c70e89ba9d42f5e4f53a4b8f2fd.tar.gz | |
Drop patch 28, merged upstream in 4.9-2014.10
Signed-off-by: Bernhard Rosenkränzer <Bernhard.Rosenkranzer@linaro.org>
| -rw-r--r-- | 4.9/0028-fix-bug-373.patch | 83 |
1 files changed, 0 insertions, 83 deletions
diff --git a/4.9/0028-fix-bug-373.patch b/4.9/0028-fix-bug-373.patch deleted file mode 100644 index 41a6ea2..0000000 --- a/4.9/0028-fix-bug-373.patch +++ /dev/null @@ -1,83 +0,0 @@ -Index: gcc-linaro/gcc/config/aarch64/iterators.md -=================================================================== ---- gcc-linaro/gcc/config/aarch64/iterators.md (revision 214194) -+++ gcc-linaro/gcc/config/aarch64/iterators.md (working copy) -@@ -66,6 +66,12 @@ - ;; Quad vector modes. - (define_mode_iterator VQ [V16QI V8HI V4SI V2DI V4SF V2DF]) - -+;; VQ without 2 element modes. -+(define_mode_iterator VQ_NO2E [V16QI V8HI V4SI V4SF]) -+ -+;; Quad vector with only 2 element modes. -+(define_mode_iterator VQ_2E [V2DI V2DF]) -+ - ;; All vector modes, except double. - (define_mode_iterator VQ_S [V8QI V16QI V4HI V8HI V2SI V4SI]) - -Index: gcc-linaro/gcc/config/aarch64/aarch64-simd.md -=================================================================== ---- gcc-linaro/gcc/config/aarch64/aarch64-simd.md (revision 214194) -+++ gcc-linaro/gcc/config/aarch64/aarch64-simd.md (working copy) -@@ -953,8 +953,8 @@ - ;; On big-endian this is { zeroes, operand } - - (define_insn "move_lo_quad_internal_<mode>" -- [(set (match_operand:VQ 0 "register_operand" "=w,w,w") -- (vec_concat:VQ -+ [(set (match_operand:VQ_NO2E 0 "register_operand" "=w,w,w") -+ (vec_concat:VQ_NO2E - (match_operand:<VHALF> 1 "register_operand" "w,r,r") - (vec_duplicate:<VHALF> (const_int 0))))] - "TARGET_SIMD && !BYTES_BIG_ENDIAN" -@@ -968,9 +968,25 @@ - (set_attr "length" "4")] - ) - -+(define_insn "move_lo_quad_internal_<mode>" -+ [(set (match_operand:VQ_2E 0 "register_operand" "=w,w,w") -+ (vec_concat:VQ_2E -+ (match_operand:<VHALF> 1 "register_operand" "w,r,r") -+ (const_int 0)))] -+ "TARGET_SIMD && !BYTES_BIG_ENDIAN" -+ "@ -+ dup\\t%d0, %1.d[0] -+ fmov\\t%d0, %1 -+ dup\\t%d0, %1" -+ [(set_attr "type" "neon_dup<q>,f_mcr,neon_dup<q>") -+ (set_attr "simd" "yes,*,yes") -+ (set_attr "fp" "*,yes,*") -+ (set_attr "length" "4")] -+) -+ - (define_insn "move_lo_quad_internal_be_<mode>" -- [(set (match_operand:VQ 0 "register_operand" "=w,w,w") -- (vec_concat:VQ -+ [(set (match_operand:VQ_NO2E 0 "register_operand" "=w,w,w") -+ (vec_concat:VQ_NO2E - (vec_duplicate:<VHALF> (const_int 0)) - (match_operand:<VHALF> 1 "register_operand" "w,r,r")))] - "TARGET_SIMD && BYTES_BIG_ENDIAN" -@@ -984,6 +1000,22 @@ - (set_attr "length" "4")] - ) - -+(define_insn "move_lo_quad_internal_be_<mode>" -+ [(set (match_operand:VQ_2E 0 "register_operand" "=w,w,w") -+ (vec_concat:VQ_2E -+ (const_int 0) -+ (match_operand:<VHALF> 1 "register_operand" "w,r,r")))] -+ "TARGET_SIMD && BYTES_BIG_ENDIAN" -+ "@ -+ dup\\t%d0, %1.d[0] -+ fmov\\t%d0, %1 -+ dup\\t%d0, %1" -+ [(set_attr "type" "neon_dup<q>,f_mcr,neon_dup<q>") -+ (set_attr "simd" "yes,*,yes") -+ (set_attr "fp" "*,yes,*") -+ (set_attr "length" "4")] -+) -+ - (define_expand "move_lo_quad_<mode>" - [(match_operand:VQ 0 "register_operand") - (match_operand:VQ 1 "register_operand")] |